1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Machine Code Emitter *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9uint64_t AArch64MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10 SmallVectorImpl<MCFixup> &Fixups,
11 const MCSubtargetInfo &STI) const {
12 static const uint64_t InstBits[] = {
13 UINT64_C(0),
14 UINT64_C(0),
15 UINT64_C(0),
16 UINT64_C(0),
17 UINT64_C(0),
18 UINT64_C(0),
19 UINT64_C(0),
20 UINT64_C(0),
21 UINT64_C(0),
22 UINT64_C(0),
23 UINT64_C(0),
24 UINT64_C(0),
25 UINT64_C(0),
26 UINT64_C(0),
27 UINT64_C(0),
28 UINT64_C(0),
29 UINT64_C(0),
30 UINT64_C(0),
31 UINT64_C(0),
32 UINT64_C(0),
33 UINT64_C(0),
34 UINT64_C(0),
35 UINT64_C(0),
36 UINT64_C(0),
37 UINT64_C(0),
38 UINT64_C(0),
39 UINT64_C(0),
40 UINT64_C(0),
41 UINT64_C(0),
42 UINT64_C(0),
43 UINT64_C(0),
44 UINT64_C(0),
45 UINT64_C(0),
46 UINT64_C(0),
47 UINT64_C(0),
48 UINT64_C(0),
49 UINT64_C(0),
50 UINT64_C(0),
51 UINT64_C(0),
52 UINT64_C(0),
53 UINT64_C(0),
54 UINT64_C(0),
55 UINT64_C(0),
56 UINT64_C(0),
57 UINT64_C(0),
58 UINT64_C(0),
59 UINT64_C(0),
60 UINT64_C(0),
61 UINT64_C(0),
62 UINT64_C(0),
63 UINT64_C(0),
64 UINT64_C(0),
65 UINT64_C(0),
66 UINT64_C(0),
67 UINT64_C(0),
68 UINT64_C(0),
69 UINT64_C(0),
70 UINT64_C(0),
71 UINT64_C(0),
72 UINT64_C(0),
73 UINT64_C(0),
74 UINT64_C(0),
75 UINT64_C(0),
76 UINT64_C(0),
77 UINT64_C(0),
78 UINT64_C(0),
79 UINT64_C(0),
80 UINT64_C(0),
81 UINT64_C(0),
82 UINT64_C(0),
83 UINT64_C(0),
84 UINT64_C(0),
85 UINT64_C(0),
86 UINT64_C(0),
87 UINT64_C(0),
88 UINT64_C(0),
89 UINT64_C(0),
90 UINT64_C(0),
91 UINT64_C(0),
92 UINT64_C(0),
93 UINT64_C(0),
94 UINT64_C(0),
95 UINT64_C(0),
96 UINT64_C(0),
97 UINT64_C(0),
98 UINT64_C(0),
99 UINT64_C(0),
100 UINT64_C(0),
101 UINT64_C(0),
102 UINT64_C(0),
103 UINT64_C(0),
104 UINT64_C(0),
105 UINT64_C(0),
106 UINT64_C(0),
107 UINT64_C(0),
108 UINT64_C(0),
109 UINT64_C(0),
110 UINT64_C(0),
111 UINT64_C(0),
112 UINT64_C(0),
113 UINT64_C(0),
114 UINT64_C(0),
115 UINT64_C(0),
116 UINT64_C(0),
117 UINT64_C(0),
118 UINT64_C(0),
119 UINT64_C(0),
120 UINT64_C(0),
121 UINT64_C(0),
122 UINT64_C(0),
123 UINT64_C(0),
124 UINT64_C(0),
125 UINT64_C(0),
126 UINT64_C(0),
127 UINT64_C(0),
128 UINT64_C(0),
129 UINT64_C(0),
130 UINT64_C(0),
131 UINT64_C(0),
132 UINT64_C(0),
133 UINT64_C(0),
134 UINT64_C(0),
135 UINT64_C(0),
136 UINT64_C(0),
137 UINT64_C(0),
138 UINT64_C(0),
139 UINT64_C(0),
140 UINT64_C(0),
141 UINT64_C(0),
142 UINT64_C(0),
143 UINT64_C(0),
144 UINT64_C(0),
145 UINT64_C(0),
146 UINT64_C(0),
147 UINT64_C(0),
148 UINT64_C(0),
149 UINT64_C(0),
150 UINT64_C(0),
151 UINT64_C(0),
152 UINT64_C(0),
153 UINT64_C(0),
154 UINT64_C(0),
155 UINT64_C(0),
156 UINT64_C(0),
157 UINT64_C(0),
158 UINT64_C(0),
159 UINT64_C(0),
160 UINT64_C(0),
161 UINT64_C(0),
162 UINT64_C(0),
163 UINT64_C(0),
164 UINT64_C(0),
165 UINT64_C(0),
166 UINT64_C(0),
167 UINT64_C(0),
168 UINT64_C(0),
169 UINT64_C(0),
170 UINT64_C(0),
171 UINT64_C(0),
172 UINT64_C(0),
173 UINT64_C(0),
174 UINT64_C(0),
175 UINT64_C(0),
176 UINT64_C(0),
177 UINT64_C(0),
178 UINT64_C(0),
179 UINT64_C(0),
180 UINT64_C(0),
181 UINT64_C(0),
182 UINT64_C(0),
183 UINT64_C(0),
184 UINT64_C(0),
185 UINT64_C(0),
186 UINT64_C(0),
187 UINT64_C(0),
188 UINT64_C(0),
189 UINT64_C(0),
190 UINT64_C(0),
191 UINT64_C(0),
192 UINT64_C(0),
193 UINT64_C(0),
194 UINT64_C(0),
195 UINT64_C(0),
196 UINT64_C(0),
197 UINT64_C(0),
198 UINT64_C(0),
199 UINT64_C(0),
200 UINT64_C(0),
201 UINT64_C(0),
202 UINT64_C(0),
203 UINT64_C(0),
204 UINT64_C(0),
205 UINT64_C(0),
206 UINT64_C(0),
207 UINT64_C(0),
208 UINT64_C(0),
209 UINT64_C(0),
210 UINT64_C(0),
211 UINT64_C(0),
212 UINT64_C(0),
213 UINT64_C(0),
214 UINT64_C(0),
215 UINT64_C(0),
216 UINT64_C(0),
217 UINT64_C(0),
218 UINT64_C(0),
219 UINT64_C(0),
220 UINT64_C(0),
221 UINT64_C(0),
222 UINT64_C(0),
223 UINT64_C(0),
224 UINT64_C(0),
225 UINT64_C(0),
226 UINT64_C(0),
227 UINT64_C(0),
228 UINT64_C(0),
229 UINT64_C(0),
230 UINT64_C(0),
231 UINT64_C(0),
232 UINT64_C(0),
233 UINT64_C(0),
234 UINT64_C(0),
235 UINT64_C(0),
236 UINT64_C(0),
237 UINT64_C(0),
238 UINT64_C(0),
239 UINT64_C(0),
240 UINT64_C(0),
241 UINT64_C(0),
242 UINT64_C(0),
243 UINT64_C(0),
244 UINT64_C(0),
245 UINT64_C(0),
246 UINT64_C(0),
247 UINT64_C(0),
248 UINT64_C(0),
249 UINT64_C(0),
250 UINT64_C(0),
251 UINT64_C(0),
252 UINT64_C(0),
253 UINT64_C(0),
254 UINT64_C(0),
255 UINT64_C(0),
256 UINT64_C(0),
257 UINT64_C(0),
258 UINT64_C(0),
259 UINT64_C(0),
260 UINT64_C(0),
261 UINT64_C(0),
262 UINT64_C(0),
263 UINT64_C(0),
264 UINT64_C(0),
265 UINT64_C(0),
266 UINT64_C(0),
267 UINT64_C(0),
268 UINT64_C(0),
269 UINT64_C(0),
270 UINT64_C(0),
271 UINT64_C(0),
272 UINT64_C(0),
273 UINT64_C(0),
274 UINT64_C(0),
275 UINT64_C(0),
276 UINT64_C(0),
277 UINT64_C(0),
278 UINT64_C(0),
279 UINT64_C(0),
280 UINT64_C(0),
281 UINT64_C(0),
282 UINT64_C(0),
283 UINT64_C(0),
284 UINT64_C(0),
285 UINT64_C(0),
286 UINT64_C(0),
287 UINT64_C(0),
288 UINT64_C(0),
289 UINT64_C(0),
290 UINT64_C(0),
291 UINT64_C(0),
292 UINT64_C(0),
293 UINT64_C(0),
294 UINT64_C(0),
295 UINT64_C(0),
296 UINT64_C(0),
297 UINT64_C(0),
298 UINT64_C(0),
299 UINT64_C(0),
300 UINT64_C(0),
301 UINT64_C(0),
302 UINT64_C(0),
303 UINT64_C(0),
304 UINT64_C(0),
305 UINT64_C(0),
306 UINT64_C(0),
307 UINT64_C(0),
308 UINT64_C(0),
309 UINT64_C(0),
310 UINT64_C(0),
311 UINT64_C(0),
312 UINT64_C(0),
313 UINT64_C(0),
314 UINT64_C(0),
315 UINT64_C(0),
316 UINT64_C(0),
317 UINT64_C(0),
318 UINT64_C(0),
319 UINT64_C(0),
320 UINT64_C(0),
321 UINT64_C(0),
322 UINT64_C(0),
323 UINT64_C(0),
324 UINT64_C(0),
325 UINT64_C(0),
326 UINT64_C(0),
327 UINT64_C(0),
328 UINT64_C(0),
329 UINT64_C(0),
330 UINT64_C(0),
331 UINT64_C(0),
332 UINT64_C(0),
333 UINT64_C(0),
334 UINT64_C(0),
335 UINT64_C(0),
336 UINT64_C(0),
337 UINT64_C(0),
338 UINT64_C(0),
339 UINT64_C(0),
340 UINT64_C(0),
341 UINT64_C(0),
342 UINT64_C(0),
343 UINT64_C(0),
344 UINT64_C(0),
345 UINT64_C(0),
346 UINT64_C(0),
347 UINT64_C(0),
348 UINT64_C(0),
349 UINT64_C(0),
350 UINT64_C(0),
351 UINT64_C(0),
352 UINT64_C(0),
353 UINT64_C(0),
354 UINT64_C(0),
355 UINT64_C(0),
356 UINT64_C(0),
357 UINT64_C(0),
358 UINT64_C(0),
359 UINT64_C(0),
360 UINT64_C(0),
361 UINT64_C(0),
362 UINT64_C(0),
363 UINT64_C(0),
364 UINT64_C(0),
365 UINT64_C(0),
366 UINT64_C(0),
367 UINT64_C(0),
368 UINT64_C(0),
369 UINT64_C(0),
370 UINT64_C(0),
371 UINT64_C(0),
372 UINT64_C(0),
373 UINT64_C(0),
374 UINT64_C(0),
375 UINT64_C(0),
376 UINT64_C(0),
377 UINT64_C(0),
378 UINT64_C(0),
379 UINT64_C(0),
380 UINT64_C(0),
381 UINT64_C(0),
382 UINT64_C(0),
383 UINT64_C(0),
384 UINT64_C(0),
385 UINT64_C(0),
386 UINT64_C(0),
387 UINT64_C(0),
388 UINT64_C(0),
389 UINT64_C(0),
390 UINT64_C(0),
391 UINT64_C(0),
392 UINT64_C(0),
393 UINT64_C(0),
394 UINT64_C(0),
395 UINT64_C(0),
396 UINT64_C(0),
397 UINT64_C(0),
398 UINT64_C(0),
399 UINT64_C(0),
400 UINT64_C(0),
401 UINT64_C(0),
402 UINT64_C(0),
403 UINT64_C(0),
404 UINT64_C(0),
405 UINT64_C(0),
406 UINT64_C(0),
407 UINT64_C(0),
408 UINT64_C(0),
409 UINT64_C(0),
410 UINT64_C(0),
411 UINT64_C(0),
412 UINT64_C(0),
413 UINT64_C(0),
414 UINT64_C(0),
415 UINT64_C(0),
416 UINT64_C(0),
417 UINT64_C(0),
418 UINT64_C(0),
419 UINT64_C(0),
420 UINT64_C(0),
421 UINT64_C(0),
422 UINT64_C(0),
423 UINT64_C(0),
424 UINT64_C(0),
425 UINT64_C(0),
426 UINT64_C(0),
427 UINT64_C(0),
428 UINT64_C(0),
429 UINT64_C(0),
430 UINT64_C(0),
431 UINT64_C(0),
432 UINT64_C(0),
433 UINT64_C(0),
434 UINT64_C(0),
435 UINT64_C(0),
436 UINT64_C(0),
437 UINT64_C(0),
438 UINT64_C(0),
439 UINT64_C(0),
440 UINT64_C(0),
441 UINT64_C(0),
442 UINT64_C(0),
443 UINT64_C(0),
444 UINT64_C(0),
445 UINT64_C(0),
446 UINT64_C(0),
447 UINT64_C(0),
448 UINT64_C(0),
449 UINT64_C(0),
450 UINT64_C(0),
451 UINT64_C(0),
452 UINT64_C(0),
453 UINT64_C(0),
454 UINT64_C(0),
455 UINT64_C(0),
456 UINT64_C(0),
457 UINT64_C(0),
458 UINT64_C(0),
459 UINT64_C(0),
460 UINT64_C(0),
461 UINT64_C(0),
462 UINT64_C(0),
463 UINT64_C(0),
464 UINT64_C(0),
465 UINT64_C(0),
466 UINT64_C(0),
467 UINT64_C(0),
468 UINT64_C(0),
469 UINT64_C(0),
470 UINT64_C(0),
471 UINT64_C(0),
472 UINT64_C(0),
473 UINT64_C(0),
474 UINT64_C(0),
475 UINT64_C(0),
476 UINT64_C(0),
477 UINT64_C(0),
478 UINT64_C(0),
479 UINT64_C(0),
480 UINT64_C(0),
481 UINT64_C(0),
482 UINT64_C(0),
483 UINT64_C(0),
484 UINT64_C(0),
485 UINT64_C(0),
486 UINT64_C(0),
487 UINT64_C(0),
488 UINT64_C(0),
489 UINT64_C(0),
490 UINT64_C(0),
491 UINT64_C(0),
492 UINT64_C(0),
493 UINT64_C(0),
494 UINT64_C(0),
495 UINT64_C(0),
496 UINT64_C(0),
497 UINT64_C(0),
498 UINT64_C(0),
499 UINT64_C(0),
500 UINT64_C(0),
501 UINT64_C(0),
502 UINT64_C(0),
503 UINT64_C(0),
504 UINT64_C(0),
505 UINT64_C(0),
506 UINT64_C(0),
507 UINT64_C(0),
508 UINT64_C(0),
509 UINT64_C(0),
510 UINT64_C(0),
511 UINT64_C(0),
512 UINT64_C(0),
513 UINT64_C(0),
514 UINT64_C(0),
515 UINT64_C(0),
516 UINT64_C(0),
517 UINT64_C(0),
518 UINT64_C(0),
519 UINT64_C(0),
520 UINT64_C(0),
521 UINT64_C(0),
522 UINT64_C(0),
523 UINT64_C(0),
524 UINT64_C(0),
525 UINT64_C(0),
526 UINT64_C(0),
527 UINT64_C(0),
528 UINT64_C(0),
529 UINT64_C(0),
530 UINT64_C(0),
531 UINT64_C(0),
532 UINT64_C(0),
533 UINT64_C(0),
534 UINT64_C(0),
535 UINT64_C(0),
536 UINT64_C(0),
537 UINT64_C(0),
538 UINT64_C(0),
539 UINT64_C(0),
540 UINT64_C(0),
541 UINT64_C(0),
542 UINT64_C(0),
543 UINT64_C(0),
544 UINT64_C(0),
545 UINT64_C(0),
546 UINT64_C(0),
547 UINT64_C(0),
548 UINT64_C(0),
549 UINT64_C(0),
550 UINT64_C(0),
551 UINT64_C(0),
552 UINT64_C(0),
553 UINT64_C(0),
554 UINT64_C(0),
555 UINT64_C(0),
556 UINT64_C(0),
557 UINT64_C(0),
558 UINT64_C(0),
559 UINT64_C(0),
560 UINT64_C(0),
561 UINT64_C(0),
562 UINT64_C(0),
563 UINT64_C(0),
564 UINT64_C(0),
565 UINT64_C(0),
566 UINT64_C(0),
567 UINT64_C(0),
568 UINT64_C(0),
569 UINT64_C(0),
570 UINT64_C(0),
571 UINT64_C(0),
572 UINT64_C(0),
573 UINT64_C(0),
574 UINT64_C(0),
575 UINT64_C(0),
576 UINT64_C(0),
577 UINT64_C(0),
578 UINT64_C(0),
579 UINT64_C(0),
580 UINT64_C(0),
581 UINT64_C(0),
582 UINT64_C(0),
583 UINT64_C(0),
584 UINT64_C(0),
585 UINT64_C(0),
586 UINT64_C(0),
587 UINT64_C(0),
588 UINT64_C(0),
589 UINT64_C(0),
590 UINT64_C(0),
591 UINT64_C(0),
592 UINT64_C(0),
593 UINT64_C(0),
594 UINT64_C(0),
595 UINT64_C(0),
596 UINT64_C(0),
597 UINT64_C(0),
598 UINT64_C(0),
599 UINT64_C(0),
600 UINT64_C(0),
601 UINT64_C(0),
602 UINT64_C(0),
603 UINT64_C(0),
604 UINT64_C(0),
605 UINT64_C(0),
606 UINT64_C(0),
607 UINT64_C(0),
608 UINT64_C(0),
609 UINT64_C(0),
610 UINT64_C(0),
611 UINT64_C(0),
612 UINT64_C(0),
613 UINT64_C(0),
614 UINT64_C(0),
615 UINT64_C(0),
616 UINT64_C(0),
617 UINT64_C(0),
618 UINT64_C(0),
619 UINT64_C(0),
620 UINT64_C(0),
621 UINT64_C(0),
622 UINT64_C(0),
623 UINT64_C(0),
624 UINT64_C(0),
625 UINT64_C(0),
626 UINT64_C(0),
627 UINT64_C(0),
628 UINT64_C(0),
629 UINT64_C(0),
630 UINT64_C(0),
631 UINT64_C(0),
632 UINT64_C(0),
633 UINT64_C(0),
634 UINT64_C(0),
635 UINT64_C(0),
636 UINT64_C(0),
637 UINT64_C(0),
638 UINT64_C(0),
639 UINT64_C(0),
640 UINT64_C(0),
641 UINT64_C(0),
642 UINT64_C(0),
643 UINT64_C(0),
644 UINT64_C(0),
645 UINT64_C(0),
646 UINT64_C(0),
647 UINT64_C(0),
648 UINT64_C(0),
649 UINT64_C(0),
650 UINT64_C(0),
651 UINT64_C(0),
652 UINT64_C(0),
653 UINT64_C(0),
654 UINT64_C(0),
655 UINT64_C(0),
656 UINT64_C(0),
657 UINT64_C(0),
658 UINT64_C(0),
659 UINT64_C(0),
660 UINT64_C(0),
661 UINT64_C(0),
662 UINT64_C(0),
663 UINT64_C(0),
664 UINT64_C(0),
665 UINT64_C(0),
666 UINT64_C(0),
667 UINT64_C(0),
668 UINT64_C(0),
669 UINT64_C(0),
670 UINT64_C(0),
671 UINT64_C(0),
672 UINT64_C(0),
673 UINT64_C(0),
674 UINT64_C(0),
675 UINT64_C(0),
676 UINT64_C(0),
677 UINT64_C(0),
678 UINT64_C(0),
679 UINT64_C(0),
680 UINT64_C(0),
681 UINT64_C(0),
682 UINT64_C(0),
683 UINT64_C(0),
684 UINT64_C(0),
685 UINT64_C(0),
686 UINT64_C(0),
687 UINT64_C(0),
688 UINT64_C(0),
689 UINT64_C(0),
690 UINT64_C(0),
691 UINT64_C(0),
692 UINT64_C(0),
693 UINT64_C(0),
694 UINT64_C(0),
695 UINT64_C(0),
696 UINT64_C(0),
697 UINT64_C(0),
698 UINT64_C(0),
699 UINT64_C(0),
700 UINT64_C(0),
701 UINT64_C(0),
702 UINT64_C(0),
703 UINT64_C(0),
704 UINT64_C(0),
705 UINT64_C(0),
706 UINT64_C(0),
707 UINT64_C(0),
708 UINT64_C(0),
709 UINT64_C(0),
710 UINT64_C(0),
711 UINT64_C(0),
712 UINT64_C(0),
713 UINT64_C(0),
714 UINT64_C(0),
715 UINT64_C(0),
716 UINT64_C(0),
717 UINT64_C(0),
718 UINT64_C(0),
719 UINT64_C(0),
720 UINT64_C(0),
721 UINT64_C(0),
722 UINT64_C(0),
723 UINT64_C(0),
724 UINT64_C(0),
725 UINT64_C(0),
726 UINT64_C(0),
727 UINT64_C(0),
728 UINT64_C(0),
729 UINT64_C(0),
730 UINT64_C(0),
731 UINT64_C(0),
732 UINT64_C(0),
733 UINT64_C(0),
734 UINT64_C(0),
735 UINT64_C(0),
736 UINT64_C(0),
737 UINT64_C(0),
738 UINT64_C(0),
739 UINT64_C(0),
740 UINT64_C(0),
741 UINT64_C(0),
742 UINT64_C(0),
743 UINT64_C(0),
744 UINT64_C(0),
745 UINT64_C(0),
746 UINT64_C(0),
747 UINT64_C(0),
748 UINT64_C(0),
749 UINT64_C(0),
750 UINT64_C(0),
751 UINT64_C(0),
752 UINT64_C(0),
753 UINT64_C(0),
754 UINT64_C(0),
755 UINT64_C(0),
756 UINT64_C(0),
757 UINT64_C(0),
758 UINT64_C(0),
759 UINT64_C(0),
760 UINT64_C(0),
761 UINT64_C(0),
762 UINT64_C(0),
763 UINT64_C(0),
764 UINT64_C(0),
765 UINT64_C(0),
766 UINT64_C(0),
767 UINT64_C(0),
768 UINT64_C(0),
769 UINT64_C(0),
770 UINT64_C(0),
771 UINT64_C(0),
772 UINT64_C(0),
773 UINT64_C(0),
774 UINT64_C(0),
775 UINT64_C(0),
776 UINT64_C(0),
777 UINT64_C(0),
778 UINT64_C(0),
779 UINT64_C(0),
780 UINT64_C(0),
781 UINT64_C(0),
782 UINT64_C(0),
783 UINT64_C(0),
784 UINT64_C(0),
785 UINT64_C(0),
786 UINT64_C(0),
787 UINT64_C(0),
788 UINT64_C(0),
789 UINT64_C(0),
790 UINT64_C(0),
791 UINT64_C(0),
792 UINT64_C(0),
793 UINT64_C(0),
794 UINT64_C(0),
795 UINT64_C(0),
796 UINT64_C(0),
797 UINT64_C(0),
798 UINT64_C(0),
799 UINT64_C(0),
800 UINT64_C(0),
801 UINT64_C(0),
802 UINT64_C(0),
803 UINT64_C(0),
804 UINT64_C(0),
805 UINT64_C(0),
806 UINT64_C(0),
807 UINT64_C(0),
808 UINT64_C(0),
809 UINT64_C(0),
810 UINT64_C(0),
811 UINT64_C(0),
812 UINT64_C(0),
813 UINT64_C(0),
814 UINT64_C(0),
815 UINT64_C(0),
816 UINT64_C(0),
817 UINT64_C(0),
818 UINT64_C(0),
819 UINT64_C(0),
820 UINT64_C(0),
821 UINT64_C(0),
822 UINT64_C(0),
823 UINT64_C(0),
824 UINT64_C(0),
825 UINT64_C(0),
826 UINT64_C(0),
827 UINT64_C(0),
828 UINT64_C(0),
829 UINT64_C(0),
830 UINT64_C(0),
831 UINT64_C(0),
832 UINT64_C(0),
833 UINT64_C(0),
834 UINT64_C(0),
835 UINT64_C(0),
836 UINT64_C(0),
837 UINT64_C(0),
838 UINT64_C(0),
839 UINT64_C(0),
840 UINT64_C(0),
841 UINT64_C(0),
842 UINT64_C(0),
843 UINT64_C(0),
844 UINT64_C(0),
845 UINT64_C(0),
846 UINT64_C(0),
847 UINT64_C(0),
848 UINT64_C(0),
849 UINT64_C(0),
850 UINT64_C(0),
851 UINT64_C(0),
852 UINT64_C(0),
853 UINT64_C(0),
854 UINT64_C(0),
855 UINT64_C(0),
856 UINT64_C(0),
857 UINT64_C(0),
858 UINT64_C(0),
859 UINT64_C(0),
860 UINT64_C(0),
861 UINT64_C(0),
862 UINT64_C(0),
863 UINT64_C(0),
864 UINT64_C(0),
865 UINT64_C(0),
866 UINT64_C(0),
867 UINT64_C(0),
868 UINT64_C(0),
869 UINT64_C(0),
870 UINT64_C(0),
871 UINT64_C(0),
872 UINT64_C(0),
873 UINT64_C(0),
874 UINT64_C(0),
875 UINT64_C(0),
876 UINT64_C(0),
877 UINT64_C(0),
878 UINT64_C(0),
879 UINT64_C(0),
880 UINT64_C(0),
881 UINT64_C(0),
882 UINT64_C(0),
883 UINT64_C(0),
884 UINT64_C(0),
885 UINT64_C(0),
886 UINT64_C(0),
887 UINT64_C(0),
888 UINT64_C(0),
889 UINT64_C(0),
890 UINT64_C(0),
891 UINT64_C(0),
892 UINT64_C(0),
893 UINT64_C(0),
894 UINT64_C(0),
895 UINT64_C(0),
896 UINT64_C(0),
897 UINT64_C(0),
898 UINT64_C(0),
899 UINT64_C(0),
900 UINT64_C(0),
901 UINT64_C(0),
902 UINT64_C(0),
903 UINT64_C(0),
904 UINT64_C(0),
905 UINT64_C(0),
906 UINT64_C(0),
907 UINT64_C(0),
908 UINT64_C(0),
909 UINT64_C(0),
910 UINT64_C(0),
911 UINT64_C(0),
912 UINT64_C(0),
913 UINT64_C(0),
914 UINT64_C(0),
915 UINT64_C(0),
916 UINT64_C(0),
917 UINT64_C(0),
918 UINT64_C(0),
919 UINT64_C(0),
920 UINT64_C(0),
921 UINT64_C(0),
922 UINT64_C(0),
923 UINT64_C(0),
924 UINT64_C(0),
925 UINT64_C(0),
926 UINT64_C(0),
927 UINT64_C(0),
928 UINT64_C(0),
929 UINT64_C(0),
930 UINT64_C(0),
931 UINT64_C(0),
932 UINT64_C(0),
933 UINT64_C(0),
934 UINT64_C(0),
935 UINT64_C(0),
936 UINT64_C(0),
937 UINT64_C(0),
938 UINT64_C(0),
939 UINT64_C(0),
940 UINT64_C(0),
941 UINT64_C(0),
942 UINT64_C(0),
943 UINT64_C(0),
944 UINT64_C(0),
945 UINT64_C(0),
946 UINT64_C(0),
947 UINT64_C(0),
948 UINT64_C(0),
949 UINT64_C(0),
950 UINT64_C(0),
951 UINT64_C(0),
952 UINT64_C(0),
953 UINT64_C(0),
954 UINT64_C(0),
955 UINT64_C(0),
956 UINT64_C(0),
957 UINT64_C(0),
958 UINT64_C(0),
959 UINT64_C(0),
960 UINT64_C(0),
961 UINT64_C(0),
962 UINT64_C(0),
963 UINT64_C(0),
964 UINT64_C(0),
965 UINT64_C(0),
966 UINT64_C(0),
967 UINT64_C(0),
968 UINT64_C(0),
969 UINT64_C(0),
970 UINT64_C(0),
971 UINT64_C(0),
972 UINT64_C(0),
973 UINT64_C(0),
974 UINT64_C(0),
975 UINT64_C(0),
976 UINT64_C(0),
977 UINT64_C(0),
978 UINT64_C(0),
979 UINT64_C(0),
980 UINT64_C(0),
981 UINT64_C(0),
982 UINT64_C(0),
983 UINT64_C(0),
984 UINT64_C(0),
985 UINT64_C(0),
986 UINT64_C(0),
987 UINT64_C(0),
988 UINT64_C(0),
989 UINT64_C(0),
990 UINT64_C(0),
991 UINT64_C(0),
992 UINT64_C(0),
993 UINT64_C(0),
994 UINT64_C(0),
995 UINT64_C(0),
996 UINT64_C(0),
997 UINT64_C(0),
998 UINT64_C(0),
999 UINT64_C(0),
1000 UINT64_C(0),
1001 UINT64_C(0),
1002 UINT64_C(0),
1003 UINT64_C(0),
1004 UINT64_C(0),
1005 UINT64_C(0),
1006 UINT64_C(0),
1007 UINT64_C(0),
1008 UINT64_C(0),
1009 UINT64_C(0),
1010 UINT64_C(0),
1011 UINT64_C(0),
1012 UINT64_C(0),
1013 UINT64_C(0),
1014 UINT64_C(0),
1015 UINT64_C(0),
1016 UINT64_C(0),
1017 UINT64_C(0),
1018 UINT64_C(0),
1019 UINT64_C(0),
1020 UINT64_C(0),
1021 UINT64_C(0),
1022 UINT64_C(0),
1023 UINT64_C(0),
1024 UINT64_C(0),
1025 UINT64_C(0),
1026 UINT64_C(0),
1027 UINT64_C(0),
1028 UINT64_C(0),
1029 UINT64_C(0),
1030 UINT64_C(0),
1031 UINT64_C(0),
1032 UINT64_C(0),
1033 UINT64_C(0),
1034 UINT64_C(0),
1035 UINT64_C(0),
1036 UINT64_C(0),
1037 UINT64_C(0),
1038 UINT64_C(0),
1039 UINT64_C(0),
1040 UINT64_C(0),
1041 UINT64_C(0),
1042 UINT64_C(0),
1043 UINT64_C(0),
1044 UINT64_C(0),
1045 UINT64_C(0),
1046 UINT64_C(0),
1047 UINT64_C(0),
1048 UINT64_C(0),
1049 UINT64_C(0),
1050 UINT64_C(0),
1051 UINT64_C(0),
1052 UINT64_C(0),
1053 UINT64_C(0),
1054 UINT64_C(0),
1055 UINT64_C(0),
1056 UINT64_C(0),
1057 UINT64_C(0),
1058 UINT64_C(0),
1059 UINT64_C(0),
1060 UINT64_C(0),
1061 UINT64_C(0),
1062 UINT64_C(0),
1063 UINT64_C(0),
1064 UINT64_C(0),
1065 UINT64_C(0),
1066 UINT64_C(0),
1067 UINT64_C(0),
1068 UINT64_C(0),
1069 UINT64_C(0),
1070 UINT64_C(0),
1071 UINT64_C(0),
1072 UINT64_C(0),
1073 UINT64_C(0),
1074 UINT64_C(0),
1075 UINT64_C(0),
1076 UINT64_C(0),
1077 UINT64_C(0),
1078 UINT64_C(0),
1079 UINT64_C(0),
1080 UINT64_C(0),
1081 UINT64_C(0),
1082 UINT64_C(0),
1083 UINT64_C(0),
1084 UINT64_C(0),
1085 UINT64_C(0),
1086 UINT64_C(0),
1087 UINT64_C(0),
1088 UINT64_C(0),
1089 UINT64_C(0),
1090 UINT64_C(0),
1091 UINT64_C(0),
1092 UINT64_C(0),
1093 UINT64_C(0),
1094 UINT64_C(0),
1095 UINT64_C(0),
1096 UINT64_C(0),
1097 UINT64_C(0),
1098 UINT64_C(0),
1099 UINT64_C(0),
1100 UINT64_C(0),
1101 UINT64_C(0),
1102 UINT64_C(0),
1103 UINT64_C(0),
1104 UINT64_C(0),
1105 UINT64_C(0),
1106 UINT64_C(0),
1107 UINT64_C(0),
1108 UINT64_C(0),
1109 UINT64_C(0),
1110 UINT64_C(0),
1111 UINT64_C(0),
1112 UINT64_C(0),
1113 UINT64_C(0),
1114 UINT64_C(0),
1115 UINT64_C(0),
1116 UINT64_C(0),
1117 UINT64_C(0),
1118 UINT64_C(0),
1119 UINT64_C(0),
1120 UINT64_C(0),
1121 UINT64_C(0),
1122 UINT64_C(0),
1123 UINT64_C(0),
1124 UINT64_C(0),
1125 UINT64_C(0),
1126 UINT64_C(0),
1127 UINT64_C(0),
1128 UINT64_C(0),
1129 UINT64_C(0),
1130 UINT64_C(0),
1131 UINT64_C(0),
1132 UINT64_C(0),
1133 UINT64_C(0),
1134 UINT64_C(0),
1135 UINT64_C(0),
1136 UINT64_C(0),
1137 UINT64_C(0),
1138 UINT64_C(0),
1139 UINT64_C(0),
1140 UINT64_C(0),
1141 UINT64_C(0),
1142 UINT64_C(0),
1143 UINT64_C(0),
1144 UINT64_C(0),
1145 UINT64_C(0),
1146 UINT64_C(0),
1147 UINT64_C(0),
1148 UINT64_C(0),
1149 UINT64_C(0),
1150 UINT64_C(0),
1151 UINT64_C(0),
1152 UINT64_C(0),
1153 UINT64_C(0),
1154 UINT64_C(0),
1155 UINT64_C(0),
1156 UINT64_C(0),
1157 UINT64_C(0),
1158 UINT64_C(0),
1159 UINT64_C(0),
1160 UINT64_C(0),
1161 UINT64_C(0),
1162 UINT64_C(0),
1163 UINT64_C(0),
1164 UINT64_C(0),
1165 UINT64_C(0),
1166 UINT64_C(0),
1167 UINT64_C(0),
1168 UINT64_C(0),
1169 UINT64_C(0),
1170 UINT64_C(0),
1171 UINT64_C(0),
1172 UINT64_C(0),
1173 UINT64_C(0),
1174 UINT64_C(0),
1175 UINT64_C(0),
1176 UINT64_C(0),
1177 UINT64_C(0),
1178 UINT64_C(0),
1179 UINT64_C(0),
1180 UINT64_C(0),
1181 UINT64_C(0),
1182 UINT64_C(0),
1183 UINT64_C(0),
1184 UINT64_C(0),
1185 UINT64_C(0),
1186 UINT64_C(0),
1187 UINT64_C(0),
1188 UINT64_C(0),
1189 UINT64_C(0),
1190 UINT64_C(0),
1191 UINT64_C(0),
1192 UINT64_C(0),
1193 UINT64_C(0),
1194 UINT64_C(0),
1195 UINT64_C(0),
1196 UINT64_C(0),
1197 UINT64_C(0),
1198 UINT64_C(0),
1199 UINT64_C(0),
1200 UINT64_C(0),
1201 UINT64_C(0),
1202 UINT64_C(0),
1203 UINT64_C(0),
1204 UINT64_C(0),
1205 UINT64_C(0),
1206 UINT64_C(0),
1207 UINT64_C(0),
1208 UINT64_C(0),
1209 UINT64_C(0),
1210 UINT64_C(0),
1211 UINT64_C(0),
1212 UINT64_C(0),
1213 UINT64_C(0),
1214 UINT64_C(0),
1215 UINT64_C(0),
1216 UINT64_C(0),
1217 UINT64_C(0),
1218 UINT64_C(0),
1219 UINT64_C(0),
1220 UINT64_C(0),
1221 UINT64_C(0),
1222 UINT64_C(0),
1223 UINT64_C(0),
1224 UINT64_C(0),
1225 UINT64_C(0),
1226 UINT64_C(0),
1227 UINT64_C(0),
1228 UINT64_C(0),
1229 UINT64_C(0),
1230 UINT64_C(0),
1231 UINT64_C(0),
1232 UINT64_C(0),
1233 UINT64_C(0),
1234 UINT64_C(0),
1235 UINT64_C(0),
1236 UINT64_C(0),
1237 UINT64_C(0),
1238 UINT64_C(0),
1239 UINT64_C(0),
1240 UINT64_C(0),
1241 UINT64_C(0),
1242 UINT64_C(0),
1243 UINT64_C(0),
1244 UINT64_C(0),
1245 UINT64_C(0),
1246 UINT64_C(0),
1247 UINT64_C(0),
1248 UINT64_C(0),
1249 UINT64_C(0),
1250 UINT64_C(0),
1251 UINT64_C(0),
1252 UINT64_C(0),
1253 UINT64_C(0),
1254 UINT64_C(0),
1255 UINT64_C(0),
1256 UINT64_C(0),
1257 UINT64_C(0),
1258 UINT64_C(0),
1259 UINT64_C(0),
1260 UINT64_C(0),
1261 UINT64_C(0),
1262 UINT64_C(0),
1263 UINT64_C(0),
1264 UINT64_C(0),
1265 UINT64_C(0),
1266 UINT64_C(0),
1267 UINT64_C(0),
1268 UINT64_C(0),
1269 UINT64_C(0),
1270 UINT64_C(0),
1271 UINT64_C(0),
1272 UINT64_C(0),
1273 UINT64_C(0),
1274 UINT64_C(0),
1275 UINT64_C(0),
1276 UINT64_C(0),
1277 UINT64_C(0),
1278 UINT64_C(0),
1279 UINT64_C(0),
1280 UINT64_C(0),
1281 UINT64_C(0),
1282 UINT64_C(0),
1283 UINT64_C(0),
1284 UINT64_C(0),
1285 UINT64_C(0),
1286 UINT64_C(0),
1287 UINT64_C(0),
1288 UINT64_C(0),
1289 UINT64_C(0),
1290 UINT64_C(0),
1291 UINT64_C(0),
1292 UINT64_C(0),
1293 UINT64_C(0),
1294 UINT64_C(0),
1295 UINT64_C(0),
1296 UINT64_C(0),
1297 UINT64_C(0),
1298 UINT64_C(0),
1299 UINT64_C(0),
1300 UINT64_C(0),
1301 UINT64_C(0),
1302 UINT64_C(0),
1303 UINT64_C(0),
1304 UINT64_C(0),
1305 UINT64_C(0),
1306 UINT64_C(0),
1307 UINT64_C(0),
1308 UINT64_C(0),
1309 UINT64_C(0),
1310 UINT64_C(0),
1311 UINT64_C(0),
1312 UINT64_C(0),
1313 UINT64_C(0),
1314 UINT64_C(0),
1315 UINT64_C(0),
1316 UINT64_C(0),
1317 UINT64_C(0),
1318 UINT64_C(0),
1319 UINT64_C(0),
1320 UINT64_C(0),
1321 UINT64_C(0),
1322 UINT64_C(0),
1323 UINT64_C(0),
1324 UINT64_C(0),
1325 UINT64_C(0),
1326 UINT64_C(0),
1327 UINT64_C(0),
1328 UINT64_C(0),
1329 UINT64_C(0),
1330 UINT64_C(0),
1331 UINT64_C(0),
1332 UINT64_C(0),
1333 UINT64_C(0),
1334 UINT64_C(0),
1335 UINT64_C(0),
1336 UINT64_C(0),
1337 UINT64_C(0),
1338 UINT64_C(0),
1339 UINT64_C(0),
1340 UINT64_C(0),
1341 UINT64_C(0),
1342 UINT64_C(0),
1343 UINT64_C(0),
1344 UINT64_C(0),
1345 UINT64_C(0),
1346 UINT64_C(0),
1347 UINT64_C(0),
1348 UINT64_C(0),
1349 UINT64_C(0),
1350 UINT64_C(0),
1351 UINT64_C(0),
1352 UINT64_C(0),
1353 UINT64_C(0),
1354 UINT64_C(0),
1355 UINT64_C(0),
1356 UINT64_C(0),
1357 UINT64_C(0),
1358 UINT64_C(0),
1359 UINT64_C(0),
1360 UINT64_C(0),
1361 UINT64_C(0),
1362 UINT64_C(0),
1363 UINT64_C(0),
1364 UINT64_C(0),
1365 UINT64_C(0),
1366 UINT64_C(0),
1367 UINT64_C(0),
1368 UINT64_C(0),
1369 UINT64_C(0),
1370 UINT64_C(0),
1371 UINT64_C(0),
1372 UINT64_C(0),
1373 UINT64_C(0),
1374 UINT64_C(0),
1375 UINT64_C(0),
1376 UINT64_C(0),
1377 UINT64_C(0),
1378 UINT64_C(0),
1379 UINT64_C(0),
1380 UINT64_C(0),
1381 UINT64_C(0),
1382 UINT64_C(0),
1383 UINT64_C(0),
1384 UINT64_C(0),
1385 UINT64_C(0),
1386 UINT64_C(0),
1387 UINT64_C(0),
1388 UINT64_C(0),
1389 UINT64_C(0),
1390 UINT64_C(0),
1391 UINT64_C(0),
1392 UINT64_C(0),
1393 UINT64_C(0),
1394 UINT64_C(0),
1395 UINT64_C(0),
1396 UINT64_C(0),
1397 UINT64_C(0),
1398 UINT64_C(0),
1399 UINT64_C(0),
1400 UINT64_C(0),
1401 UINT64_C(0),
1402 UINT64_C(1522540544), // ABSWr
1403 UINT64_C(3670024192), // ABSXr
1404 UINT64_C(68591616), // ABS_ZPmZ_B
1405 UINT64_C(81174528), // ABS_ZPmZ_D
1406 UINT64_C(72785920), // ABS_ZPmZ_H
1407 UINT64_C(76980224), // ABS_ZPmZ_S
1408 UINT64_C(1310767104), // ABSv16i8
1409 UINT64_C(1591785472), // ABSv1i64
1410 UINT64_C(245413888), // ABSv2i32
1411 UINT64_C(1323350016), // ABSv2i64
1412 UINT64_C(241219584), // ABSv4i16
1413 UINT64_C(1319155712), // ABSv4i32
1414 UINT64_C(1314961408), // ABSv8i16
1415 UINT64_C(237025280), // ABSv8i8
1416 UINT64_C(1161875456), // ADCLB_ZZZ_D
1417 UINT64_C(1157681152), // ADCLB_ZZZ_S
1418 UINT64_C(1161876480), // ADCLT_ZZZ_D
1419 UINT64_C(1157682176), // ADCLT_ZZZ_S
1420 UINT64_C(973078528), // ADCSWr
1421 UINT64_C(3120562176), // ADCSXr
1422 UINT64_C(436207616), // ADCWr
1423 UINT64_C(2583691264), // ADCXr
1424 UINT64_C(2441084928), // ADDG
1425 UINT64_C(3234856960), // ADDHA_MPPZ_D
1426 UINT64_C(3230662656), // ADDHA_MPPZ_S
1427 UINT64_C(1163943936), // ADDHNB_ZZZ_B
1428 UINT64_C(1168138240), // ADDHNB_ZZZ_H
1429 UINT64_C(1172332544), // ADDHNB_ZZZ_S
1430 UINT64_C(1163944960), // ADDHNT_ZZZ_B
1431 UINT64_C(1168139264), // ADDHNT_ZZZ_H
1432 UINT64_C(1172333568), // ADDHNT_ZZZ_S
1433 UINT64_C(245383168), // ADDHNv2i64_v2i32
1434 UINT64_C(1319124992), // ADDHNv2i64_v4i32
1435 UINT64_C(241188864), // ADDHNv4i32_v4i16
1436 UINT64_C(1314930688), // ADDHNv4i32_v8i16
1437 UINT64_C(1310736384), // ADDHNv8i16_v16i8
1438 UINT64_C(236994560), // ADDHNv8i16_v8i8
1439 UINT64_C(73420800), // ADDPL_XXI
1440 UINT64_C(2583699456), // ADDPT_shift
1441 UINT64_C(1142005760), // ADDP_ZPmZ_B
1442 UINT64_C(1154588672), // ADDP_ZPmZ_D
1443 UINT64_C(1146200064), // ADDP_ZPmZ_H
1444 UINT64_C(1150394368), // ADDP_ZPmZ_S
1445 UINT64_C(1310768128), // ADDPv16i8
1446 UINT64_C(245414912), // ADDPv2i32
1447 UINT64_C(1323351040), // ADDPv2i64
1448 UINT64_C(1592899584), // ADDPv2i64p
1449 UINT64_C(241220608), // ADDPv4i16
1450 UINT64_C(1319156736), // ADDPv4i32
1451 UINT64_C(1314962432), // ADDPv8i16
1452 UINT64_C(237026304), // ADDPv8i8
1453 UINT64_C(67444736), // ADDQV_VPZ_B
1454 UINT64_C(80027648), // ADDQV_VPZ_D
1455 UINT64_C(71639040), // ADDQV_VPZ_H
1456 UINT64_C(75833344), // ADDQV_VPZ_S
1457 UINT64_C(73422848), // ADDSPL_XXI
1458 UINT64_C(69228544), // ADDSVL_XXI
1459 UINT64_C(822083584), // ADDSWri
1460 UINT64_C(721420288), // ADDSWrs
1461 UINT64_C(723517440), // ADDSWrx
1462 UINT64_C(2969567232), // ADDSXri
1463 UINT64_C(2868903936), // ADDSXrs
1464 UINT64_C(2871001088), // ADDSXrx
1465 UINT64_C(2871025664), // ADDSXrx64
1466 UINT64_C(3234922496), // ADDVA_MPPZ_D
1467 UINT64_C(3230728192), // ADDVA_MPPZ_S
1468 UINT64_C(69226496), // ADDVL_XXI
1469 UINT64_C(1311881216), // ADDVv16i8v
1470 UINT64_C(242333696), // ADDVv4i16v
1471 UINT64_C(1320269824), // ADDVv4i32v
1472 UINT64_C(1316075520), // ADDVv8i16v
1473 UINT64_C(238139392), // ADDVv8i8v
1474 UINT64_C(285212672), // ADDWri
1475 UINT64_C(184549376), // ADDWrs
1476 UINT64_C(186646528), // ADDWrx
1477 UINT64_C(2432696320), // ADDXri
1478 UINT64_C(2332033024), // ADDXrs
1479 UINT64_C(2334130176), // ADDXrx
1480 UINT64_C(2334154752), // ADDXrx64
1481 UINT64_C(3240141568), // ADD_VG2_2ZZ_B
1482 UINT64_C(3252724480), // ADD_VG2_2ZZ_D
1483 UINT64_C(3244335872), // ADD_VG2_2ZZ_H
1484 UINT64_C(3248530176), // ADD_VG2_2ZZ_S
1485 UINT64_C(3252688912), // ADD_VG2_M2Z2Z_D
1486 UINT64_C(3248494608), // ADD_VG2_M2Z2Z_S
1487 UINT64_C(3244300304), // ADD_VG2_M2ZZ_D
1488 UINT64_C(3240106000), // ADD_VG2_M2ZZ_S
1489 UINT64_C(3252689936), // ADD_VG2_M2Z_D
1490 UINT64_C(3248495632), // ADD_VG2_M2Z_S
1491 UINT64_C(3240143616), // ADD_VG4_4ZZ_B
1492 UINT64_C(3252726528), // ADD_VG4_4ZZ_D
1493 UINT64_C(3244337920), // ADD_VG4_4ZZ_H
1494 UINT64_C(3248532224), // ADD_VG4_4ZZ_S
1495 UINT64_C(3252754448), // ADD_VG4_M4Z4Z_D
1496 UINT64_C(3248560144), // ADD_VG4_M4Z4Z_S
1497 UINT64_C(3245348880), // ADD_VG4_M4ZZ_D
1498 UINT64_C(3241154576), // ADD_VG4_M4ZZ_S
1499 UINT64_C(3252755472), // ADD_VG4_M4Z_D
1500 UINT64_C(3248561168), // ADD_VG4_M4Z_S
1501 UINT64_C(622903296), // ADD_ZI_B
1502 UINT64_C(635486208), // ADD_ZI_D
1503 UINT64_C(627097600), // ADD_ZI_H
1504 UINT64_C(631291904), // ADD_ZI_S
1505 UINT64_C(67108864), // ADD_ZPmZ_B
1506 UINT64_C(79953920), // ADD_ZPmZ_CPA
1507 UINT64_C(79691776), // ADD_ZPmZ_D
1508 UINT64_C(71303168), // ADD_ZPmZ_H
1509 UINT64_C(75497472), // ADD_ZPmZ_S
1510 UINT64_C(69206016), // ADD_ZZZ_B
1511 UINT64_C(81790976), // ADD_ZZZ_CPA
1512 UINT64_C(81788928), // ADD_ZZZ_D
1513 UINT64_C(73400320), // ADD_ZZZ_H
1514 UINT64_C(77594624), // ADD_ZZZ_S
1515 UINT64_C(1310753792), // ADDv16i8
1516 UINT64_C(1591772160), // ADDv1i64
1517 UINT64_C(245400576), // ADDv2i32
1518 UINT64_C(1323336704), // ADDv2i64
1519 UINT64_C(241206272), // ADDv4i16
1520 UINT64_C(1319142400), // ADDv4i32
1521 UINT64_C(1314948096), // ADDv8i16
1522 UINT64_C(237011968), // ADDv8i8
1523 UINT64_C(268435456), // ADR
1524 UINT64_C(2415919104), // ADRP
1525 UINT64_C(81829888), // ADR_LSL_ZZZ_D_0
1526 UINT64_C(81830912), // ADR_LSL_ZZZ_D_1
1527 UINT64_C(81831936), // ADR_LSL_ZZZ_D_2
1528 UINT64_C(81832960), // ADR_LSL_ZZZ_D_3
1529 UINT64_C(77635584), // ADR_LSL_ZZZ_S_0
1530 UINT64_C(77636608), // ADR_LSL_ZZZ_S_1
1531 UINT64_C(77637632), // ADR_LSL_ZZZ_S_2
1532 UINT64_C(77638656), // ADR_LSL_ZZZ_S_3
1533 UINT64_C(69246976), // ADR_SXTW_ZZZ_D_0
1534 UINT64_C(69248000), // ADR_SXTW_ZZZ_D_1
1535 UINT64_C(69249024), // ADR_SXTW_ZZZ_D_2
1536 UINT64_C(69250048), // ADR_SXTW_ZZZ_D_3
1537 UINT64_C(73441280), // ADR_UXTW_ZZZ_D_0
1538 UINT64_C(73442304), // ADR_UXTW_ZZZ_D_1
1539 UINT64_C(73443328), // ADR_UXTW_ZZZ_D_2
1540 UINT64_C(73444352), // ADR_UXTW_ZZZ_D_3
1541 UINT64_C(1159914496), // AESD_ZZZ_B
1542 UINT64_C(1311266816), // AESDrr
1543 UINT64_C(1159913472), // AESE_ZZZ_B
1544 UINT64_C(1311262720), // AESErr
1545 UINT64_C(1159783424), // AESIMC_ZZ_B
1546 UINT64_C(1311275008), // AESIMCrr
1547 UINT64_C(1159782400), // AESMC_ZZ_B
1548 UINT64_C(1311270912), // AESMCrr
1549 UINT64_C(69083136), // ANDQV_VPZ_B
1550 UINT64_C(81666048), // ANDQV_VPZ_D
1551 UINT64_C(73277440), // ANDQV_VPZ_H
1552 UINT64_C(77471744), // ANDQV_VPZ_S
1553 UINT64_C(1912602624), // ANDSWri
1554 UINT64_C(1778384896), // ANDSWrs
1555 UINT64_C(4060086272), // ANDSXri
1556 UINT64_C(3925868544), // ANDSXrs
1557 UINT64_C(624967680), // ANDS_PPzPP
1558 UINT64_C(68820992), // ANDV_VPZ_B
1559 UINT64_C(81403904), // ANDV_VPZ_D
1560 UINT64_C(73015296), // ANDV_VPZ_H
1561 UINT64_C(77209600), // ANDV_VPZ_S
1562 UINT64_C(301989888), // ANDWri
1563 UINT64_C(167772160), // ANDWrs
1564 UINT64_C(2449473536), // ANDXri
1565 UINT64_C(2315255808), // ANDXrs
1566 UINT64_C(620773376), // AND_PPzPP
1567 UINT64_C(92274688), // AND_ZI
1568 UINT64_C(68812800), // AND_ZPmZ_B
1569 UINT64_C(81395712), // AND_ZPmZ_D
1570 UINT64_C(73007104), // AND_ZPmZ_H
1571 UINT64_C(77201408), // AND_ZPmZ_S
1572 UINT64_C(69218304), // AND_ZZZ
1573 UINT64_C(1310727168), // ANDv16i8
1574 UINT64_C(236985344), // ANDv8i8
1575 UINT64_C(67404032), // ASRD_ZPmI_B
1576 UINT64_C(75792384), // ASRD_ZPmI_D
1577 UINT64_C(67404288), // ASRD_ZPmI_H
1578 UINT64_C(71598080), // ASRD_ZPmI_S
1579 UINT64_C(68452352), // ASRR_ZPmZ_B
1580 UINT64_C(81035264), // ASRR_ZPmZ_D
1581 UINT64_C(72646656), // ASRR_ZPmZ_H
1582 UINT64_C(76840960), // ASRR_ZPmZ_S
1583 UINT64_C(448800768), // ASRVWr
1584 UINT64_C(2596284416), // ASRVXr
1585 UINT64_C(68714496), // ASR_WIDE_ZPmZ_B
1586 UINT64_C(72908800), // ASR_WIDE_ZPmZ_H
1587 UINT64_C(77103104), // ASR_WIDE_ZPmZ_S
1588 UINT64_C(69238784), // ASR_WIDE_ZZZ_B
1589 UINT64_C(73433088), // ASR_WIDE_ZZZ_H
1590 UINT64_C(77627392), // ASR_WIDE_ZZZ_S
1591 UINT64_C(67141888), // ASR_ZPmI_B
1592 UINT64_C(75530240), // ASR_ZPmI_D
1593 UINT64_C(67142144), // ASR_ZPmI_H
1594 UINT64_C(71335936), // ASR_ZPmI_S
1595 UINT64_C(68190208), // ASR_ZPmZ_B
1596 UINT64_C(80773120), // ASR_ZPmZ_D
1597 UINT64_C(72384512), // ASR_ZPmZ_H
1598 UINT64_C(76578816), // ASR_ZPmZ_S
1599 UINT64_C(69767168), // ASR_ZZI_B
1600 UINT64_C(77631488), // ASR_ZZI_D
1601 UINT64_C(70291456), // ASR_ZZI_H
1602 UINT64_C(73437184), // ASR_ZZI_S
1603 UINT64_C(3670087680), // AUTDA
1604 UINT64_C(3670088704), // AUTDB
1605 UINT64_C(3670096864), // AUTDZA
1606 UINT64_C(3670097888), // AUTDZB
1607 UINT64_C(3670085632), // AUTIA
1608 UINT64_C(3573752223), // AUTIA1716
1609 UINT64_C(3670129662), // AUTIA171615
1610 UINT64_C(3573752767), // AUTIASP
1611 UINT64_C(4085252127), // AUTIASPPCi
1612 UINT64_C(3670118430), // AUTIASPPCr
1613 UINT64_C(3573752735), // AUTIAZ
1614 UINT64_C(3670086656), // AUTIB
1615 UINT64_C(3573752287), // AUTIB1716
1616 UINT64_C(3670130686), // AUTIB171615
1617 UINT64_C(3573752831), // AUTIBSP
1618 UINT64_C(4087349279), // AUTIBSPPCi
1619 UINT64_C(3670119454), // AUTIBSPPCr
1620 UINT64_C(3573752799), // AUTIBZ
1621 UINT64_C(3670094816), // AUTIZA
1622 UINT64_C(3670095840), // AUTIZB
1623 UINT64_C(3573563487), // AXFLAG
1624 UINT64_C(335544320), // B
1625 UINT64_C(3458203648), // BCAX
1626 UINT64_C(73414656), // BCAX_ZZZZ
1627 UINT64_C(1409286160), // BCcc
1628 UINT64_C(1157673984), // BDEP_ZZZ_B
1629 UINT64_C(1170256896), // BDEP_ZZZ_D
1630 UINT64_C(1161868288), // BDEP_ZZZ_H
1631 UINT64_C(1166062592), // BDEP_ZZZ_S
1632 UINT64_C(1157672960), // BEXT_ZZZ_B
1633 UINT64_C(1170255872), // BEXT_ZZZ_D
1634 UINT64_C(1161867264), // BEXT_ZZZ_H
1635 UINT64_C(1166061568), // BEXT_ZZZ_S
1636 UINT64_C(255913984), // BF16DOTlanev4bf16
1637 UINT64_C(1329655808), // BF16DOTlanev8bf16
1638 UINT64_C(1856075776), // BF1CVTL2v8f16
1639 UINT64_C(1695102976), // BF1CVTLT_ZZ_BtoH
1640 UINT64_C(3244744705), // BF1CVTL_2ZZ_BtoH_NAME
1641 UINT64_C(782333952), // BF1CVTLv8f16
1642 UINT64_C(3244744704), // BF1CVT_2ZZ_BtoH_NAME
1643 UINT64_C(1695037440), // BF1CVT_ZZ_BtoH
1644 UINT64_C(1860270080), // BF2CVTL2v8f16
1645 UINT64_C(1695104000), // BF2CVTLT_ZZ_BtoH
1646 UINT64_C(3253133313), // BF2CVTL_2ZZ_BtoH_NAME
1647 UINT64_C(786528256), // BF2CVTLv8f16
1648 UINT64_C(3253133312), // BF2CVT_2ZZ_BtoH_NAME
1649 UINT64_C(1695038464), // BF2CVT_ZZ_BtoH
1650 UINT64_C(3252952064), // BFADD_VG2_M2Z_H
1651 UINT64_C(3253017600), // BFADD_VG4_M4Z_H
1652 UINT64_C(1694531584), // BFADD_ZPmZZ
1653 UINT64_C(1694498816), // BFADD_ZZZ
1654 UINT64_C(3240148992), // BFCLAMP_VG2_2ZZZ_H
1655 UINT64_C(3240151040), // BFCLAMP_VG4_4ZZZ_H
1656 UINT64_C(1679827968), // BFCLAMP_ZZZ
1657 UINT64_C(509820928), // BFCVT
1658 UINT64_C(245458944), // BFCVTN
1659 UINT64_C(1319200768), // BFCVTN2
1660 UINT64_C(1686806528), // BFCVTNT_ZPmZ
1661 UINT64_C(1695168512), // BFCVTN_Z2Z_HtoB
1662 UINT64_C(3244351520), // BFCVTN_Z2Z_StoH
1663 UINT64_C(3244613632), // BFCVT_Z2Z_HtoB
1664 UINT64_C(3244351488), // BFCVT_Z2Z_StoH
1665 UINT64_C(1703583744), // BFCVT_ZPmZ
1666 UINT64_C(3248492560), // BFDOT_VG2_M2Z2Z_HtoS
1667 UINT64_C(3243249688), // BFDOT_VG2_M2ZZI_HtoS
1668 UINT64_C(3240103952), // BFDOT_VG2_M2ZZ_HtoS
1669 UINT64_C(3248558096), // BFDOT_VG4_M4Z4Z_HtoS
1670 UINT64_C(3243282456), // BFDOT_VG4_M4ZZI_HtoS
1671 UINT64_C(3241152528), // BFDOT_VG4_M4ZZ_HtoS
1672 UINT64_C(1684029440), // BFDOT_ZZI
1673 UINT64_C(1684045824), // BFDOT_ZZZ
1674 UINT64_C(776010752), // BFDOTv4bf16
1675 UINT64_C(1849752576), // BFDOTv8bf16
1676 UINT64_C(3240145184), // BFMAXNM_VG2_2Z2Z_H
1677 UINT64_C(3240141088), // BFMAXNM_VG2_2ZZ_H
1678 UINT64_C(3240147232), // BFMAXNM_VG4_4Z2Z_H
1679 UINT64_C(3240143136), // BFMAXNM_VG4_4ZZ_H
1680 UINT64_C(1694793728), // BFMAXNM_ZPmZZ
1681 UINT64_C(3240145152), // BFMAX_VG2_2Z2Z_H
1682 UINT64_C(3240141056), // BFMAX_VG2_2ZZ_H
1683 UINT64_C(3240147200), // BFMAX_VG4_4Z2Z_H
1684 UINT64_C(3240143104), // BFMAX_VG4_4ZZ_H
1685 UINT64_C(1694924800), // BFMAX_ZPmZZ
1686 UINT64_C(3240145185), // BFMINNM_VG2_2Z2Z_H
1687 UINT64_C(3240141089), // BFMINNM_VG2_2ZZ_H
1688 UINT64_C(3240147233), // BFMINNM_VG4_4Z2Z_H
1689 UINT64_C(3240143137), // BFMINNM_VG4_4ZZ_H
1690 UINT64_C(1694859264), // BFMINNM_ZPmZZ
1691 UINT64_C(3240145153), // BFMIN_VG2_2Z2Z_H
1692 UINT64_C(3240141057), // BFMIN_VG2_2ZZ_H
1693 UINT64_C(3240147201), // BFMIN_VG4_4Z2Z_H
1694 UINT64_C(3240143105), // BFMIN_VG4_4ZZ_H
1695 UINT64_C(1694990336), // BFMIN_ZPmZZ
1696 UINT64_C(784399360), // BFMLALB
1697 UINT64_C(264302592), // BFMLALBIdx
1698 UINT64_C(1692434432), // BFMLALB_ZZZ
1699 UINT64_C(1692418048), // BFMLALB_ZZZI
1700 UINT64_C(1858141184), // BFMLALT
1701 UINT64_C(1338044416), // BFMLALTIdx
1702 UINT64_C(1692435456), // BFMLALT_ZZZ
1703 UINT64_C(1692419072), // BFMLALT_ZZZI
1704 UINT64_C(3246395408), // BFMLAL_MZZI_HtoS
1705 UINT64_C(3240102928), // BFMLAL_MZZ_HtoS
1706 UINT64_C(3248490512), // BFMLAL_VG2_M2Z2Z_HtoS
1707 UINT64_C(3247443984), // BFMLAL_VG2_M2ZZI_HtoS
1708 UINT64_C(3240101904), // BFMLAL_VG2_M2ZZ_HtoS
1709 UINT64_C(3248556048), // BFMLAL_VG4_M4Z4Z_HtoS
1710 UINT64_C(3247476752), // BFMLAL_VG4_M4ZZI_HtoS
1711 UINT64_C(3241150480), // BFMLAL_VG4_M4ZZ_HtoS
1712 UINT64_C(3252686856), // BFMLA_VG2_M2Z2Z
1713 UINT64_C(3244301312), // BFMLA_VG2_M2ZZ
1714 UINT64_C(3239055392), // BFMLA_VG2_M2ZZI
1715 UINT64_C(3252752392), // BFMLA_VG4_M4Z4Z
1716 UINT64_C(3245349888), // BFMLA_VG4_M4ZZ
1717 UINT64_C(3239088160), // BFMLA_VG4_M4ZZI
1718 UINT64_C(1696595968), // BFMLA_ZPmZZ
1719 UINT64_C(1679820800), // BFMLA_ZZZI
1720 UINT64_C(1692426240), // BFMLSLB_ZZZI_S
1721 UINT64_C(1692442624), // BFMLSLB_ZZZ_S
1722 UINT64_C(1692427264), // BFMLSLT_ZZZI_S
1723 UINT64_C(1692443648), // BFMLSLT_ZZZ_S
1724 UINT64_C(3246395416), // BFMLSL_MZZI_HtoS
1725 UINT64_C(3240102936), // BFMLSL_MZZ_HtoS
1726 UINT64_C(3248490520), // BFMLSL_VG2_M2Z2Z_HtoS
1727 UINT64_C(3247443992), // BFMLSL_VG2_M2ZZI_HtoS
1728 UINT64_C(3240101912), // BFMLSL_VG2_M2ZZ_HtoS
1729 UINT64_C(3248556056), // BFMLSL_VG4_M4Z4Z_HtoS
1730 UINT64_C(3247476760), // BFMLSL_VG4_M4ZZI_HtoS
1731 UINT64_C(3241150488), // BFMLSL_VG4_M4ZZ_HtoS
1732 UINT64_C(3252686872), // BFMLS_VG2_M2Z2Z
1733 UINT64_C(3244301320), // BFMLS_VG2_M2ZZ
1734 UINT64_C(3239055408), // BFMLS_VG2_M2ZZI
1735 UINT64_C(3252752408), // BFMLS_VG4_M4Z4Z
1736 UINT64_C(3245349896), // BFMLS_VG4_M4ZZ
1737 UINT64_C(3239088176), // BFMLS_VG4_M4ZZI
1738 UINT64_C(1696604160), // BFMLS_ZPmZZ
1739 UINT64_C(1679821824), // BFMLS_ZZZI
1740 UINT64_C(1849748480), // BFMMLA
1741 UINT64_C(1684071424), // BFMMLA_ZZZ
1742 UINT64_C(2172649472), // BFMOPA_MPPZZ
1743 UINT64_C(2174746632), // BFMOPA_MPPZZ_H
1744 UINT64_C(2172649488), // BFMOPS_MPPZZ
1745 UINT64_C(2174746648), // BFMOPS_MPPZZ_H
1746 UINT64_C(1694662656), // BFMUL_ZPmZZ
1747 UINT64_C(1694500864), // BFMUL_ZZZ
1748 UINT64_C(1679828992), // BFMUL_ZZZI
1749 UINT64_C(855638016), // BFMWri
1750 UINT64_C(3007315968), // BFMXri
1751 UINT64_C(3252952072), // BFSUB_VG2_M2Z_H
1752 UINT64_C(3253017608), // BFSUB_VG4_M4Z_H
1753 UINT64_C(1694597120), // BFSUB_ZPmZZ
1754 UINT64_C(1694499840), // BFSUB_ZZZ
1755 UINT64_C(3243245592), // BFVDOT_VG2_M2ZZI_HtoS
1756 UINT64_C(1157675008), // BGRP_ZZZ_B
1757 UINT64_C(1170257920), // BGRP_ZZZ_D
1758 UINT64_C(1161869312), // BGRP_ZZZ_H
1759 UINT64_C(1166063616), // BGRP_ZZZ_S
1760 UINT64_C(1780482048), // BICSWrs
1761 UINT64_C(3927965696), // BICSXrs
1762 UINT64_C(624967696), // BICS_PPzPP
1763 UINT64_C(169869312), // BICWrs
1764 UINT64_C(2317352960), // BICXrs
1765 UINT64_C(620773392), // BIC_PPzPP
1766 UINT64_C(68878336), // BIC_ZPmZ_B
1767 UINT64_C(81461248), // BIC_ZPmZ_D
1768 UINT64_C(73072640), // BIC_ZPmZ_H
1769 UINT64_C(77266944), // BIC_ZPmZ_S
1770 UINT64_C(81801216), // BIC_ZZZ
1771 UINT64_C(1314921472), // BICv16i8
1772 UINT64_C(788534272), // BICv2i32
1773 UINT64_C(788567040), // BICv4i16
1774 UINT64_C(1862276096), // BICv4i32
1775 UINT64_C(1862308864), // BICv8i16
1776 UINT64_C(241179648), // BICv8i8
1777 UINT64_C(1860180992), // BIFv16i8
1778 UINT64_C(786439168), // BIFv8i8
1779 UINT64_C(1855986688), // BITv16i8
1780 UINT64_C(782244864), // BITv8i8
1781 UINT64_C(2483027968), // BL
1782 UINT64_C(3594452992), // BLR
1783 UINT64_C(3611232256), // BLRAA
1784 UINT64_C(3594455071), // BLRAAZ
1785 UINT64_C(3611233280), // BLRAB
1786 UINT64_C(3594456095), // BLRABZ
1787 UINT64_C(2155872264), // BMOPA_MPPZZ_S
1788 UINT64_C(2155872280), // BMOPS_MPPZZ_S
1789 UINT64_C(3592355840), // BR
1790 UINT64_C(3609135104), // BRAA
1791 UINT64_C(3592357919), // BRAAZ
1792 UINT64_C(3609136128), // BRAB
1793 UINT64_C(3592358943), // BRABZ
1794 UINT64_C(3574166175), // BRB_IALL
1795 UINT64_C(3574166207), // BRB_INJ
1796 UINT64_C(3558866944), // BRK
1797 UINT64_C(626016256), // BRKAS_PPzP
1798 UINT64_C(621821968), // BRKA_PPmP
1799 UINT64_C(621821952), // BRKA_PPzP
1800 UINT64_C(634404864), // BRKBS_PPzP
1801 UINT64_C(630210576), // BRKB_PPmP
1802 UINT64_C(630210560), // BRKB_PPzP
1803 UINT64_C(626540544), // BRKNS_PPzP
1804 UINT64_C(622346240), // BRKN_PPzP
1805 UINT64_C(625000448), // BRKPAS_PPzPP
1806 UINT64_C(620806144), // BRKPA_PPzPP
1807 UINT64_C(625000464), // BRKPBS_PPzPP
1808 UINT64_C(620806160), // BRKPB_PPzPP
1809 UINT64_C(73415680), // BSL1N_ZZZZ
1810 UINT64_C(77609984), // BSL2N_ZZZZ
1811 UINT64_C(69221376), // BSL_ZZZZ
1812 UINT64_C(1851792384), // BSLv16i8
1813 UINT64_C(778050560), // BSLv8i8
1814 UINT64_C(1409286144), // Bcc
1815 UINT64_C(1157683200), // CADD_ZZI_B
1816 UINT64_C(1170266112), // CADD_ZZI_D
1817 UINT64_C(1161877504), // CADD_ZZI_H
1818 UINT64_C(1166071808), // CADD_ZZI_S
1819 UINT64_C(148929536), // CASAB
1820 UINT64_C(1222671360), // CASAH
1821 UINT64_C(148962304), // CASALB
1822 UINT64_C(1222704128), // CASALH
1823 UINT64_C(2296445952), // CASALW
1824 UINT64_C(3370187776), // CASALX
1825 UINT64_C(2296413184), // CASAW
1826 UINT64_C(3370155008), // CASAX
1827 UINT64_C(144735232), // CASB
1828 UINT64_C(1218477056), // CASH
1829 UINT64_C(144768000), // CASLB
1830 UINT64_C(1218509824), // CASLH
1831 UINT64_C(2292251648), // CASLW
1832 UINT64_C(3365993472), // CASLX
1833 UINT64_C(140573696), // CASPALW
1834 UINT64_C(1214315520), // CASPALX
1835 UINT64_C(140540928), // CASPAW
1836 UINT64_C(1214282752), // CASPAX
1837 UINT64_C(136379392), // CASPLW
1838 UINT64_C(1210121216), // CASPLX
1839 UINT64_C(136346624), // CASPW
1840 UINT64_C(1210088448), // CASPX
1841 UINT64_C(2292218880), // CASW
1842 UINT64_C(3365960704), // CASX
1843 UINT64_C(889192448), // CBNZW
1844 UINT64_C(3036676096), // CBNZX
1845 UINT64_C(872415232), // CBZW
1846 UINT64_C(3019898880), // CBZX
1847 UINT64_C(977274880), // CCMNWi
1848 UINT64_C(977272832), // CCMNWr
1849 UINT64_C(3124758528), // CCMNXi
1850 UINT64_C(3124756480), // CCMNXr
1851 UINT64_C(2051016704), // CCMPWi
1852 UINT64_C(2051014656), // CCMPWr
1853 UINT64_C(4198500352), // CCMPXi
1854 UINT64_C(4198498304), // CCMPXr
1855 UINT64_C(1155547136), // CDOT_ZZZI_D
1856 UINT64_C(1151352832), // CDOT_ZZZI_S
1857 UINT64_C(1153437696), // CDOT_ZZZ_D
1858 UINT64_C(1149243392), // CDOT_ZZZ_S
1859 UINT64_C(3573563423), // CFINV
1860 UINT64_C(3573753119), // CHKFEAT
1861 UINT64_C(87072768), // CLASTA_RPZ_B
1862 UINT64_C(99655680), // CLASTA_RPZ_D
1863 UINT64_C(91267072), // CLASTA_RPZ_H
1864 UINT64_C(95461376), // CLASTA_RPZ_S
1865 UINT64_C(86671360), // CLASTA_VPZ_B
1866 UINT64_C(99254272), // CLASTA_VPZ_D
1867 UINT64_C(90865664), // CLASTA_VPZ_H
1868 UINT64_C(95059968), // CLASTA_VPZ_S
1869 UINT64_C(86540288), // CLASTA_ZPZ_B
1870 UINT64_C(99123200), // CLASTA_ZPZ_D
1871 UINT64_C(90734592), // CLASTA_ZPZ_H
1872 UINT64_C(94928896), // CLASTA_ZPZ_S
1873 UINT64_C(87138304), // CLASTB_RPZ_B
1874 UINT64_C(99721216), // CLASTB_RPZ_D
1875 UINT64_C(91332608), // CLASTB_RPZ_H
1876 UINT64_C(95526912), // CLASTB_RPZ_S
1877 UINT64_C(86736896), // CLASTB_VPZ_B
1878 UINT64_C(99319808), // CLASTB_VPZ_D
1879 UINT64_C(90931200), // CLASTB_VPZ_H
1880 UINT64_C(95125504), // CLASTB_VPZ_S
1881 UINT64_C(86605824), // CLASTB_ZPZ_B
1882 UINT64_C(99188736), // CLASTB_ZPZ_D
1883 UINT64_C(90800128), // CLASTB_ZPZ_H
1884 UINT64_C(94994432), // CLASTB_ZPZ_S
1885 UINT64_C(3573755999), // CLREX
1886 UINT64_C(1522537472), // CLSWr
1887 UINT64_C(3670021120), // CLSXr
1888 UINT64_C(68722688), // CLS_ZPmZ_B
1889 UINT64_C(81305600), // CLS_ZPmZ_D
1890 UINT64_C(72916992), // CLS_ZPmZ_H
1891 UINT64_C(77111296), // CLS_ZPmZ_S
1892 UINT64_C(1310738432), // CLSv16i8
1893 UINT64_C(245385216), // CLSv2i32
1894 UINT64_C(241190912), // CLSv4i16
1895 UINT64_C(1319127040), // CLSv4i32
1896 UINT64_C(1314932736), // CLSv8i16
1897 UINT64_C(236996608), // CLSv8i8
1898 UINT64_C(1522536448), // CLZWr
1899 UINT64_C(3670020096), // CLZXr
1900 UINT64_C(68788224), // CLZ_ZPmZ_B
1901 UINT64_C(81371136), // CLZ_ZPmZ_D
1902 UINT64_C(72982528), // CLZ_ZPmZ_H
1903 UINT64_C(77176832), // CLZ_ZPmZ_S
1904 UINT64_C(1847609344), // CLZv16i8
1905 UINT64_C(782256128), // CLZv2i32
1906 UINT64_C(778061824), // CLZv4i16
1907 UINT64_C(1855997952), // CLZv4i32
1908 UINT64_C(1851803648), // CLZv8i16
1909 UINT64_C(773867520), // CLZv8i8
1910 UINT64_C(1847626752), // CMEQv16i8
1911 UINT64_C(1310758912), // CMEQv16i8rz
1912 UINT64_C(2128645120), // CMEQv1i64
1913 UINT64_C(1591777280), // CMEQv1i64rz
1914 UINT64_C(782273536), // CMEQv2i32
1915 UINT64_C(245405696), // CMEQv2i32rz
1916 UINT64_C(1860209664), // CMEQv2i64
1917 UINT64_C(1323341824), // CMEQv2i64rz
1918 UINT64_C(778079232), // CMEQv4i16
1919 UINT64_C(241211392), // CMEQv4i16rz
1920 UINT64_C(1856015360), // CMEQv4i32
1921 UINT64_C(1319147520), // CMEQv4i32rz
1922 UINT64_C(1851821056), // CMEQv8i16
1923 UINT64_C(1314953216), // CMEQv8i16rz
1924 UINT64_C(773884928), // CMEQv8i8
1925 UINT64_C(237017088), // CMEQv8i8rz
1926 UINT64_C(1310735360), // CMGEv16i8
1927 UINT64_C(1847625728), // CMGEv16i8rz
1928 UINT64_C(1591753728), // CMGEv1i64
1929 UINT64_C(2128644096), // CMGEv1i64rz
1930 UINT64_C(245382144), // CMGEv2i32
1931 UINT64_C(782272512), // CMGEv2i32rz
1932 UINT64_C(1323318272), // CMGEv2i64
1933 UINT64_C(1860208640), // CMGEv2i64rz
1934 UINT64_C(241187840), // CMGEv4i16
1935 UINT64_C(778078208), // CMGEv4i16rz
1936 UINT64_C(1319123968), // CMGEv4i32
1937 UINT64_C(1856014336), // CMGEv4i32rz
1938 UINT64_C(1314929664), // CMGEv8i16
1939 UINT64_C(1851820032), // CMGEv8i16rz
1940 UINT64_C(236993536), // CMGEv8i8
1941 UINT64_C(773883904), // CMGEv8i8rz
1942 UINT64_C(1310733312), // CMGTv16i8
1943 UINT64_C(1310754816), // CMGTv16i8rz
1944 UINT64_C(1591751680), // CMGTv1i64
1945 UINT64_C(1591773184), // CMGTv1i64rz
1946 UINT64_C(245380096), // CMGTv2i32
1947 UINT64_C(245401600), // CMGTv2i32rz
1948 UINT64_C(1323316224), // CMGTv2i64
1949 UINT64_C(1323337728), // CMGTv2i64rz
1950 UINT64_C(241185792), // CMGTv4i16
1951 UINT64_C(241207296), // CMGTv4i16rz
1952 UINT64_C(1319121920), // CMGTv4i32
1953 UINT64_C(1319143424), // CMGTv4i32rz
1954 UINT64_C(1314927616), // CMGTv8i16
1955 UINT64_C(1314949120), // CMGTv8i16rz
1956 UINT64_C(236991488), // CMGTv8i8
1957 UINT64_C(237012992), // CMGTv8i8rz
1958 UINT64_C(1847604224), // CMHIv16i8
1959 UINT64_C(2128622592), // CMHIv1i64
1960 UINT64_C(782251008), // CMHIv2i32
1961 UINT64_C(1860187136), // CMHIv2i64
1962 UINT64_C(778056704), // CMHIv4i16
1963 UINT64_C(1855992832), // CMHIv4i32
1964 UINT64_C(1851798528), // CMHIv8i16
1965 UINT64_C(773862400), // CMHIv8i8
1966 UINT64_C(1847606272), // CMHSv16i8
1967 UINT64_C(2128624640), // CMHSv1i64
1968 UINT64_C(782253056), // CMHSv2i32
1969 UINT64_C(1860189184), // CMHSv2i64
1970 UINT64_C(778058752), // CMHSv4i16
1971 UINT64_C(1855994880), // CMHSv4i32
1972 UINT64_C(1851800576), // CMHSv8i16
1973 UINT64_C(773864448), // CMHSv8i8
1974 UINT64_C(1151361024), // CMLA_ZZZI_H
1975 UINT64_C(1155555328), // CMLA_ZZZI_S
1976 UINT64_C(1140858880), // CMLA_ZZZ_B
1977 UINT64_C(1153441792), // CMLA_ZZZ_D
1978 UINT64_C(1145053184), // CMLA_ZZZ_H
1979 UINT64_C(1149247488), // CMLA_ZZZ_S
1980 UINT64_C(1847629824), // CMLEv16i8rz
1981 UINT64_C(2128648192), // CMLEv1i64rz
1982 UINT64_C(782276608), // CMLEv2i32rz
1983 UINT64_C(1860212736), // CMLEv2i64rz
1984 UINT64_C(778082304), // CMLEv4i16rz
1985 UINT64_C(1856018432), // CMLEv4i32rz
1986 UINT64_C(1851824128), // CMLEv8i16rz
1987 UINT64_C(773888000), // CMLEv8i8rz
1988 UINT64_C(1310763008), // CMLTv16i8rz
1989 UINT64_C(1591781376), // CMLTv1i64rz
1990 UINT64_C(245409792), // CMLTv2i32rz
1991 UINT64_C(1323345920), // CMLTv2i64rz
1992 UINT64_C(241215488), // CMLTv4i16rz
1993 UINT64_C(1319151616), // CMLTv4i32rz
1994 UINT64_C(1314957312), // CMLTv8i16rz
1995 UINT64_C(237021184), // CMLTv8i8rz
1996 UINT64_C(620789760), // CMPEQ_PPzZI_B
1997 UINT64_C(633372672), // CMPEQ_PPzZI_D
1998 UINT64_C(624984064), // CMPEQ_PPzZI_H
1999 UINT64_C(629178368), // CMPEQ_PPzZI_S
2000 UINT64_C(604020736), // CMPEQ_PPzZZ_B
2001 UINT64_C(616603648), // CMPEQ_PPzZZ_D
2002 UINT64_C(608215040), // CMPEQ_PPzZZ_H
2003 UINT64_C(612409344), // CMPEQ_PPzZZ_S
2004 UINT64_C(603987968), // CMPEQ_WIDE_PPzZZ_B
2005 UINT64_C(608182272), // CMPEQ_WIDE_PPzZZ_H
2006 UINT64_C(612376576), // CMPEQ_WIDE_PPzZZ_S
2007 UINT64_C(620756992), // CMPGE_PPzZI_B
2008 UINT64_C(633339904), // CMPGE_PPzZI_D
2009 UINT64_C(624951296), // CMPGE_PPzZI_H
2010 UINT64_C(629145600), // CMPGE_PPzZI_S
2011 UINT64_C(604012544), // CMPGE_PPzZZ_B
2012 UINT64_C(616595456), // CMPGE_PPzZZ_D
2013 UINT64_C(608206848), // CMPGE_PPzZZ_H
2014 UINT64_C(612401152), // CMPGE_PPzZZ_S
2015 UINT64_C(603996160), // CMPGE_WIDE_PPzZZ_B
2016 UINT64_C(608190464), // CMPGE_WIDE_PPzZZ_H
2017 UINT64_C(612384768), // CMPGE_WIDE_PPzZZ_S
2018 UINT64_C(620757008), // CMPGT_PPzZI_B
2019 UINT64_C(633339920), // CMPGT_PPzZI_D
2020 UINT64_C(624951312), // CMPGT_PPzZI_H
2021 UINT64_C(629145616), // CMPGT_PPzZI_S
2022 UINT64_C(604012560), // CMPGT_PPzZZ_B
2023 UINT64_C(616595472), // CMPGT_PPzZZ_D
2024 UINT64_C(608206864), // CMPGT_PPzZZ_H
2025 UINT64_C(612401168), // CMPGT_PPzZZ_S
2026 UINT64_C(603996176), // CMPGT_WIDE_PPzZZ_B
2027 UINT64_C(608190480), // CMPGT_WIDE_PPzZZ_H
2028 UINT64_C(612384784), // CMPGT_WIDE_PPzZZ_S
2029 UINT64_C(606076944), // CMPHI_PPzZI_B
2030 UINT64_C(618659856), // CMPHI_PPzZI_D
2031 UINT64_C(610271248), // CMPHI_PPzZI_H
2032 UINT64_C(614465552), // CMPHI_PPzZI_S
2033 UINT64_C(603979792), // CMPHI_PPzZZ_B
2034 UINT64_C(616562704), // CMPHI_PPzZZ_D
2035 UINT64_C(608174096), // CMPHI_PPzZZ_H
2036 UINT64_C(612368400), // CMPHI_PPzZZ_S
2037 UINT64_C(604028944), // CMPHI_WIDE_PPzZZ_B
2038 UINT64_C(608223248), // CMPHI_WIDE_PPzZZ_H
2039 UINT64_C(612417552), // CMPHI_WIDE_PPzZZ_S
2040 UINT64_C(606076928), // CMPHS_PPzZI_B
2041 UINT64_C(618659840), // CMPHS_PPzZI_D
2042 UINT64_C(610271232), // CMPHS_PPzZI_H
2043 UINT64_C(614465536), // CMPHS_PPzZI_S
2044 UINT64_C(603979776), // CMPHS_PPzZZ_B
2045 UINT64_C(616562688), // CMPHS_PPzZZ_D
2046 UINT64_C(608174080), // CMPHS_PPzZZ_H
2047 UINT64_C(612368384), // CMPHS_PPzZZ_S
2048 UINT64_C(604028928), // CMPHS_WIDE_PPzZZ_B
2049 UINT64_C(608223232), // CMPHS_WIDE_PPzZZ_H
2050 UINT64_C(612417536), // CMPHS_WIDE_PPzZZ_S
2051 UINT64_C(620765200), // CMPLE_PPzZI_B
2052 UINT64_C(633348112), // CMPLE_PPzZI_D
2053 UINT64_C(624959504), // CMPLE_PPzZI_H
2054 UINT64_C(629153808), // CMPLE_PPzZI_S
2055 UINT64_C(604004368), // CMPLE_WIDE_PPzZZ_B
2056 UINT64_C(608198672), // CMPLE_WIDE_PPzZZ_H
2057 UINT64_C(612392976), // CMPLE_WIDE_PPzZZ_S
2058 UINT64_C(606085120), // CMPLO_PPzZI_B
2059 UINT64_C(618668032), // CMPLO_PPzZI_D
2060 UINT64_C(610279424), // CMPLO_PPzZI_H
2061 UINT64_C(614473728), // CMPLO_PPzZI_S
2062 UINT64_C(604037120), // CMPLO_WIDE_PPzZZ_B
2063 UINT64_C(608231424), // CMPLO_WIDE_PPzZZ_H
2064 UINT64_C(612425728), // CMPLO_WIDE_PPzZZ_S
2065 UINT64_C(606085136), // CMPLS_PPzZI_B
2066 UINT64_C(618668048), // CMPLS_PPzZI_D
2067 UINT64_C(610279440), // CMPLS_PPzZI_H
2068 UINT64_C(614473744), // CMPLS_PPzZI_S
2069 UINT64_C(604037136), // CMPLS_WIDE_PPzZZ_B
2070 UINT64_C(608231440), // CMPLS_WIDE_PPzZZ_H
2071 UINT64_C(612425744), // CMPLS_WIDE_PPzZZ_S
2072 UINT64_C(620765184), // CMPLT_PPzZI_B
2073 UINT64_C(633348096), // CMPLT_PPzZI_D
2074 UINT64_C(624959488), // CMPLT_PPzZI_H
2075 UINT64_C(629153792), // CMPLT_PPzZI_S
2076 UINT64_C(604004352), // CMPLT_WIDE_PPzZZ_B
2077 UINT64_C(608198656), // CMPLT_WIDE_PPzZZ_H
2078 UINT64_C(612392960), // CMPLT_WIDE_PPzZZ_S
2079 UINT64_C(620789776), // CMPNE_PPzZI_B
2080 UINT64_C(633372688), // CMPNE_PPzZI_D
2081 UINT64_C(624984080), // CMPNE_PPzZI_H
2082 UINT64_C(629178384), // CMPNE_PPzZI_S
2083 UINT64_C(604020752), // CMPNE_PPzZZ_B
2084 UINT64_C(616603664), // CMPNE_PPzZZ_D
2085 UINT64_C(608215056), // CMPNE_PPzZZ_H
2086 UINT64_C(612409360), // CMPNE_PPzZZ_S
2087 UINT64_C(603987984), // CMPNE_WIDE_PPzZZ_B
2088 UINT64_C(608182288), // CMPNE_WIDE_PPzZZ_H
2089 UINT64_C(612376592), // CMPNE_WIDE_PPzZZ_S
2090 UINT64_C(1310755840), // CMTSTv16i8
2091 UINT64_C(1591774208), // CMTSTv1i64
2092 UINT64_C(245402624), // CMTSTv2i32
2093 UINT64_C(1323338752), // CMTSTv2i64
2094 UINT64_C(241208320), // CMTSTv4i16
2095 UINT64_C(1319144448), // CMTSTv4i32
2096 UINT64_C(1314950144), // CMTSTv8i16
2097 UINT64_C(237014016), // CMTSTv8i8
2098 UINT64_C(68919296), // CNOT_ZPmZ_B
2099 UINT64_C(81502208), // CNOT_ZPmZ_D
2100 UINT64_C(73113600), // CNOT_ZPmZ_H
2101 UINT64_C(77307904), // CNOT_ZPmZ_S
2102 UINT64_C(69263360), // CNTB_XPiI
2103 UINT64_C(81846272), // CNTD_XPiI
2104 UINT64_C(73457664), // CNTH_XPiI
2105 UINT64_C(622887424), // CNTP_XCI_B
2106 UINT64_C(635470336), // CNTP_XCI_D
2107 UINT64_C(627081728), // CNTP_XCI_H
2108 UINT64_C(631276032), // CNTP_XCI_S
2109 UINT64_C(622886912), // CNTP_XPP_B
2110 UINT64_C(635469824), // CNTP_XPP_D
2111 UINT64_C(627081216), // CNTP_XPP_H
2112 UINT64_C(631275520), // CNTP_XPP_S
2113 UINT64_C(77651968), // CNTW_XPiI
2114 UINT64_C(1522539520), // CNTWr
2115 UINT64_C(3670023168), // CNTXr
2116 UINT64_C(68853760), // CNT_ZPmZ_B
2117 UINT64_C(81436672), // CNT_ZPmZ_D
2118 UINT64_C(73048064), // CNT_ZPmZ_H
2119 UINT64_C(77242368), // CNT_ZPmZ_S
2120 UINT64_C(1310742528), // CNTv16i8
2121 UINT64_C(237000704), // CNTv8i8
2122 UINT64_C(98664448), // COMPACT_ZPZ_D
2123 UINT64_C(94470144), // COMPACT_ZPZ_S
2124 UINT64_C(494928896), // CPYE
2125 UINT64_C(494978048), // CPYEN
2126 UINT64_C(494961664), // CPYERN
2127 UINT64_C(494937088), // CPYERT
2128 UINT64_C(494986240), // CPYERTN
2129 UINT64_C(494969856), // CPYERTRN
2130 UINT64_C(494953472), // CPYERTWN
2131 UINT64_C(494941184), // CPYET
2132 UINT64_C(494990336), // CPYETN
2133 UINT64_C(494973952), // CPYETRN
2134 UINT64_C(494957568), // CPYETWN
2135 UINT64_C(494945280), // CPYEWN
2136 UINT64_C(494932992), // CPYEWT
2137 UINT64_C(494982144), // CPYEWTN
2138 UINT64_C(494965760), // CPYEWTRN
2139 UINT64_C(494949376), // CPYEWTWN
2140 UINT64_C(427820032), // CPYFE
2141 UINT64_C(427869184), // CPYFEN
2142 UINT64_C(427852800), // CPYFERN
2143 UINT64_C(427828224), // CPYFERT
2144 UINT64_C(427877376), // CPYFERTN
2145 UINT64_C(427860992), // CPYFERTRN
2146 UINT64_C(427844608), // CPYFERTWN
2147 UINT64_C(427832320), // CPYFET
2148 UINT64_C(427881472), // CPYFETN
2149 UINT64_C(427865088), // CPYFETRN
2150 UINT64_C(427848704), // CPYFETWN
2151 UINT64_C(427836416), // CPYFEWN
2152 UINT64_C(427824128), // CPYFEWT
2153 UINT64_C(427873280), // CPYFEWTN
2154 UINT64_C(427856896), // CPYFEWTRN
2155 UINT64_C(427840512), // CPYFEWTWN
2156 UINT64_C(423625728), // CPYFM
2157 UINT64_C(423674880), // CPYFMN
2158 UINT64_C(423658496), // CPYFMRN
2159 UINT64_C(423633920), // CPYFMRT
2160 UINT64_C(423683072), // CPYFMRTN
2161 UINT64_C(423666688), // CPYFMRTRN
2162 UINT64_C(423650304), // CPYFMRTWN
2163 UINT64_C(423638016), // CPYFMT
2164 UINT64_C(423687168), // CPYFMTN
2165 UINT64_C(423670784), // CPYFMTRN
2166 UINT64_C(423654400), // CPYFMTWN
2167 UINT64_C(423642112), // CPYFMWN
2168 UINT64_C(423629824), // CPYFMWT
2169 UINT64_C(423678976), // CPYFMWTN
2170 UINT64_C(423662592), // CPYFMWTRN
2171 UINT64_C(423646208), // CPYFMWTWN
2172 UINT64_C(419431424), // CPYFP
2173 UINT64_C(419480576), // CPYFPN
2174 UINT64_C(419464192), // CPYFPRN
2175 UINT64_C(419439616), // CPYFPRT
2176 UINT64_C(419488768), // CPYFPRTN
2177 UINT64_C(419472384), // CPYFPRTRN
2178 UINT64_C(419456000), // CPYFPRTWN
2179 UINT64_C(419443712), // CPYFPT
2180 UINT64_C(419492864), // CPYFPTN
2181 UINT64_C(419476480), // CPYFPTRN
2182 UINT64_C(419460096), // CPYFPTWN
2183 UINT64_C(419447808), // CPYFPWN
2184 UINT64_C(419435520), // CPYFPWT
2185 UINT64_C(419484672), // CPYFPWTN
2186 UINT64_C(419468288), // CPYFPWTRN
2187 UINT64_C(419451904), // CPYFPWTWN
2188 UINT64_C(490734592), // CPYM
2189 UINT64_C(490783744), // CPYMN
2190 UINT64_C(490767360), // CPYMRN
2191 UINT64_C(490742784), // CPYMRT
2192 UINT64_C(490791936), // CPYMRTN
2193 UINT64_C(490775552), // CPYMRTRN
2194 UINT64_C(490759168), // CPYMRTWN
2195 UINT64_C(490746880), // CPYMT
2196 UINT64_C(490796032), // CPYMTN
2197 UINT64_C(490779648), // CPYMTRN
2198 UINT64_C(490763264), // CPYMTWN
2199 UINT64_C(490750976), // CPYMWN
2200 UINT64_C(490738688), // CPYMWT
2201 UINT64_C(490787840), // CPYMWTN
2202 UINT64_C(490771456), // CPYMWTRN
2203 UINT64_C(490755072), // CPYMWTWN
2204 UINT64_C(486540288), // CPYP
2205 UINT64_C(486589440), // CPYPN
2206 UINT64_C(486573056), // CPYPRN
2207 UINT64_C(486548480), // CPYPRT
2208 UINT64_C(486597632), // CPYPRTN
2209 UINT64_C(486581248), // CPYPRTRN
2210 UINT64_C(486564864), // CPYPRTWN
2211 UINT64_C(486552576), // CPYPT
2212 UINT64_C(486601728), // CPYPTN
2213 UINT64_C(486585344), // CPYPTRN
2214 UINT64_C(486568960), // CPYPTWN
2215 UINT64_C(486556672), // CPYPWN
2216 UINT64_C(486544384), // CPYPWT
2217 UINT64_C(486593536), // CPYPWTN
2218 UINT64_C(486577152), // CPYPWTRN
2219 UINT64_C(486560768), // CPYPWTWN
2220 UINT64_C(84951040), // CPY_ZPmI_B
2221 UINT64_C(97533952), // CPY_ZPmI_D
2222 UINT64_C(89145344), // CPY_ZPmI_H
2223 UINT64_C(93339648), // CPY_ZPmI_S
2224 UINT64_C(86548480), // CPY_ZPmR_B
2225 UINT64_C(99131392), // CPY_ZPmR_D
2226 UINT64_C(90742784), // CPY_ZPmR_H
2227 UINT64_C(94937088), // CPY_ZPmR_S
2228 UINT64_C(86016000), // CPY_ZPmV_B
2229 UINT64_C(98598912), // CPY_ZPmV_D
2230 UINT64_C(90210304), // CPY_ZPmV_H
2231 UINT64_C(94404608), // CPY_ZPmV_S
2232 UINT64_C(84934656), // CPY_ZPzI_B
2233 UINT64_C(97517568), // CPY_ZPzI_D
2234 UINT64_C(89128960), // CPY_ZPzI_H
2235 UINT64_C(93323264), // CPY_ZPzI_S
2236 UINT64_C(448806912), // CRC32Brr
2237 UINT64_C(448811008), // CRC32CBrr
2238 UINT64_C(448812032), // CRC32CHrr
2239 UINT64_C(448813056), // CRC32CWrr
2240 UINT64_C(2596297728), // CRC32CXrr
2241 UINT64_C(448807936), // CRC32Hrr
2242 UINT64_C(448808960), // CRC32Wrr
2243 UINT64_C(2596293632), // CRC32Xrr
2244 UINT64_C(444596224), // CSELWr
2245 UINT64_C(2592079872), // CSELXr
2246 UINT64_C(444597248), // CSINCWr
2247 UINT64_C(2592080896), // CSINCXr
2248 UINT64_C(1518338048), // CSINVWr
2249 UINT64_C(3665821696), // CSINVXr
2250 UINT64_C(1518339072), // CSNEGWr
2251 UINT64_C(3665822720), // CSNEGXr
2252 UINT64_C(631250944), // CTERMEQ_WW
2253 UINT64_C(635445248), // CTERMEQ_XX
2254 UINT64_C(631250960), // CTERMNE_WW
2255 UINT64_C(635445264), // CTERMNE_XX
2256 UINT64_C(1522538496), // CTZWr
2257 UINT64_C(3670022144), // CTZXr
2258 UINT64_C(3567255553), // DCPS1
2259 UINT64_C(3567255554), // DCPS2
2260 UINT64_C(3567255555), // DCPS3
2261 UINT64_C(70312960), // DECB_XPiI
2262 UINT64_C(82895872), // DECD_XPiI
2263 UINT64_C(82887680), // DECD_ZPiI
2264 UINT64_C(74507264), // DECH_XPiI
2265 UINT64_C(74499072), // DECH_ZPiI
2266 UINT64_C(623740928), // DECP_XP_B
2267 UINT64_C(636323840), // DECP_XP_D
2268 UINT64_C(627935232), // DECP_XP_H
2269 UINT64_C(632129536), // DECP_XP_S
2270 UINT64_C(636321792), // DECP_ZP_D
2271 UINT64_C(627933184), // DECP_ZP_H
2272 UINT64_C(632127488), // DECP_ZP_S
2273 UINT64_C(78701568), // DECW_XPiI
2274 UINT64_C(78693376), // DECW_ZPiI
2275 UINT64_C(3573756095), // DMB
2276 UINT64_C(3602842592), // DRPS
2277 UINT64_C(3573756063), // DSB
2278 UINT64_C(3573756479), // DSBnXS
2279 UINT64_C(96468992), // DUPM_ZI
2280 UINT64_C(86057984), // DUPQ_ZZI_B
2281 UINT64_C(86516736), // DUPQ_ZZI_D
2282 UINT64_C(86123520), // DUPQ_ZZI_H
2283 UINT64_C(86254592), // DUPQ_ZZI_S
2284 UINT64_C(624476160), // DUP_ZI_B
2285 UINT64_C(637059072), // DUP_ZI_D
2286 UINT64_C(628670464), // DUP_ZI_H
2287 UINT64_C(632864768), // DUP_ZI_S
2288 UINT64_C(85997568), // DUP_ZR_B
2289 UINT64_C(98580480), // DUP_ZR_D
2290 UINT64_C(90191872), // DUP_ZR_H
2291 UINT64_C(94386176), // DUP_ZR_S
2292 UINT64_C(86056960), // DUP_ZZI_B
2293 UINT64_C(86515712), // DUP_ZZI_D
2294 UINT64_C(86122496), // DUP_ZZI_H
2295 UINT64_C(87040000), // DUP_ZZI_Q
2296 UINT64_C(86253568), // DUP_ZZI_S
2297 UINT64_C(1577190400), // DUPi16
2298 UINT64_C(1577321472), // DUPi32
2299 UINT64_C(1577583616), // DUPi64
2300 UINT64_C(1577124864), // DUPi8
2301 UINT64_C(1308691456), // DUPv16i8gpr
2302 UINT64_C(1308689408), // DUPv16i8lane
2303 UINT64_C(235146240), // DUPv2i32gpr
2304 UINT64_C(235144192), // DUPv2i32lane
2305 UINT64_C(1309150208), // DUPv2i64gpr
2306 UINT64_C(1309148160), // DUPv2i64lane
2307 UINT64_C(235015168), // DUPv4i16gpr
2308 UINT64_C(235013120), // DUPv4i16lane
2309 UINT64_C(1308888064), // DUPv4i32gpr
2310 UINT64_C(1308886016), // DUPv4i32lane
2311 UINT64_C(1308756992), // DUPv8i16gpr
2312 UINT64_C(1308754944), // DUPv8i16lane
2313 UINT64_C(234949632), // DUPv8i8gpr
2314 UINT64_C(234947584), // DUPv8i8lane
2315 UINT64_C(1243611136), // EONWrs
2316 UINT64_C(3391094784), // EONXrs
2317 UINT64_C(3456106496), // EOR3
2318 UINT64_C(69220352), // EOR3_ZZZZ
2319 UINT64_C(1157664768), // EORBT_ZZZ_B
2320 UINT64_C(1170247680), // EORBT_ZZZ_D
2321 UINT64_C(1161859072), // EORBT_ZZZ_H
2322 UINT64_C(1166053376), // EORBT_ZZZ_S
2323 UINT64_C(69017600), // EORQV_VPZ_B
2324 UINT64_C(81600512), // EORQV_VPZ_D
2325 UINT64_C(73211904), // EORQV_VPZ_H
2326 UINT64_C(77406208), // EORQV_VPZ_S
2327 UINT64_C(624968192), // EORS_PPzPP
2328 UINT64_C(1157665792), // EORTB_ZZZ_B
2329 UINT64_C(1170248704), // EORTB_ZZZ_D
2330 UINT64_C(1161860096), // EORTB_ZZZ_H
2331 UINT64_C(1166054400), // EORTB_ZZZ_S
2332 UINT64_C(68755456), // EORV_VPZ_B
2333 UINT64_C(81338368), // EORV_VPZ_D
2334 UINT64_C(72949760), // EORV_VPZ_H
2335 UINT64_C(77144064), // EORV_VPZ_S
2336 UINT64_C(1375731712), // EORWri
2337 UINT64_C(1241513984), // EORWrs
2338 UINT64_C(3523215360), // EORXri
2339 UINT64_C(3388997632), // EORXrs
2340 UINT64_C(620773888), // EOR_PPzPP
2341 UINT64_C(88080384), // EOR_ZI
2342 UINT64_C(68747264), // EOR_ZPmZ_B
2343 UINT64_C(81330176), // EOR_ZPmZ_D
2344 UINT64_C(72941568), // EOR_ZPmZ_H
2345 UINT64_C(77135872), // EOR_ZPmZ_S
2346 UINT64_C(77606912), // EOR_ZZZ
2347 UINT64_C(1847598080), // EORv16i8
2348 UINT64_C(773856256), // EORv8i8
2349 UINT64_C(3600745440), // ERET
2350 UINT64_C(3600747519), // ERETAA
2351 UINT64_C(3600748543), // ERETAB
2352 UINT64_C(90186752), // EXTQ_ZZI
2353 UINT64_C(3221356544), // EXTRACT_ZPMXI_H_B
2354 UINT64_C(3233939456), // EXTRACT_ZPMXI_H_D
2355 UINT64_C(3225550848), // EXTRACT_ZPMXI_H_H
2356 UINT64_C(3234004992), // EXTRACT_ZPMXI_H_Q
2357 UINT64_C(3229745152), // EXTRACT_ZPMXI_H_S
2358 UINT64_C(3221389312), // EXTRACT_ZPMXI_V_B
2359 UINT64_C(3233972224), // EXTRACT_ZPMXI_V_D
2360 UINT64_C(3225583616), // EXTRACT_ZPMXI_V_H
2361 UINT64_C(3234037760), // EXTRACT_ZPMXI_V_Q
2362 UINT64_C(3229777920), // EXTRACT_ZPMXI_V_S
2363 UINT64_C(327155712), // EXTRWrri
2364 UINT64_C(2478833664), // EXTRXrri
2365 UINT64_C(85983232), // EXT_ZZI
2366 UINT64_C(90177536), // EXT_ZZI_B
2367 UINT64_C(1845493760), // EXTv16i8
2368 UINT64_C(771751936), // EXTv8i8
2369 UINT64_C(1847687168), // F1CVTL2v8f16
2370 UINT64_C(1695100928), // F1CVTLT_ZZ_BtoH
2371 UINT64_C(3240550401), // F1CVTL_2ZZ_BtoH_NAME
2372 UINT64_C(773945344), // F1CVTLv8f16
2373 UINT64_C(3240550400), // F1CVT_2ZZ_BtoH_NAME
2374 UINT64_C(1695035392), // F1CVT_ZZ_BtoH
2375 UINT64_C(1851881472), // F2CVTL2v8f16
2376 UINT64_C(1695101952), // F2CVTLT_ZZ_BtoH
2377 UINT64_C(3248939009), // F2CVTL_2ZZ_BtoH_NAME
2378 UINT64_C(778139648), // F2CVTLv8f16
2379 UINT64_C(3248939008), // F2CVT_2ZZ_BtoH_NAME
2380 UINT64_C(1695036416), // F2CVT_ZZ_BtoH
2381 UINT64_C(2126517248), // FABD16
2382 UINT64_C(2124469248), // FABD32
2383 UINT64_C(2128663552), // FABD64
2384 UINT64_C(1707638784), // FABD_ZPmZ_D
2385 UINT64_C(1699250176), // FABD_ZPmZ_H
2386 UINT64_C(1703444480), // FABD_ZPmZ_S
2387 UINT64_C(782291968), // FABDv2f32
2388 UINT64_C(1860228096), // FABDv2f64
2389 UINT64_C(784339968), // FABDv4f16
2390 UINT64_C(1856033792), // FABDv4f32
2391 UINT64_C(1858081792), // FABDv8f16
2392 UINT64_C(509657088), // FABSDr
2393 UINT64_C(518045696), // FABSHr
2394 UINT64_C(505462784), // FABSSr
2395 UINT64_C(81567744), // FABS_ZPmZ_D
2396 UINT64_C(73179136), // FABS_ZPmZ_H
2397 UINT64_C(77373440), // FABS_ZPmZ_S
2398 UINT64_C(245430272), // FABSv2f32
2399 UINT64_C(1323366400), // FABSv2f64
2400 UINT64_C(251197440), // FABSv4f16
2401 UINT64_C(1319172096), // FABSv4f32
2402 UINT64_C(1324939264), // FABSv8f16
2403 UINT64_C(2118134784), // FACGE16
2404 UINT64_C(2116086784), // FACGE32
2405 UINT64_C(2120281088), // FACGE64
2406 UINT64_C(1707130896), // FACGE_PPzZZ_D
2407 UINT64_C(1698742288), // FACGE_PPzZZ_H
2408 UINT64_C(1702936592), // FACGE_PPzZZ_S
2409 UINT64_C(773909504), // FACGEv2f32
2410 UINT64_C(1851845632), // FACGEv2f64
2411 UINT64_C(775957504), // FACGEv4f16
2412 UINT64_C(1847651328), // FACGEv4f32
2413 UINT64_C(1849699328), // FACGEv8f16
2414 UINT64_C(2126523392), // FACGT16
2415 UINT64_C(2124475392), // FACGT32
2416 UINT64_C(2128669696), // FACGT64
2417 UINT64_C(1707139088), // FACGT_PPzZZ_D
2418 UINT64_C(1698750480), // FACGT_PPzZZ_H
2419 UINT64_C(1702944784), // FACGT_PPzZZ_S
2420 UINT64_C(782298112), // FACGTv2f32
2421 UINT64_C(1860234240), // FACGTv2f64
2422 UINT64_C(784346112), // FACGTv4f16
2423 UINT64_C(1856039936), // FACGTv4f32
2424 UINT64_C(1858087936), // FACGTv8f16
2425 UINT64_C(1708662784), // FADDA_VPZ_D
2426 UINT64_C(1700274176), // FADDA_VPZ_H
2427 UINT64_C(1704468480), // FADDA_VPZ_S
2428 UINT64_C(509618176), // FADDDrr
2429 UINT64_C(518006784), // FADDHrr
2430 UINT64_C(1691385856), // FADDP_ZPmZZ_D
2431 UINT64_C(1682997248), // FADDP_ZPmZZ_H
2432 UINT64_C(1687191552), // FADDP_ZPmZZ_S
2433 UINT64_C(773903360), // FADDPv2f32
2434 UINT64_C(1851839488), // FADDPv2f64
2435 UINT64_C(1580259328), // FADDPv2i16p
2436 UINT64_C(2117130240), // FADDPv2i32p
2437 UINT64_C(2121324544), // FADDPv2i64p
2438 UINT64_C(775951360), // FADDPv4f16
2439 UINT64_C(1847645184), // FADDPv4f32
2440 UINT64_C(1849693184), // FADDPv8f16
2441 UINT64_C(1691394048), // FADDQV_D
2442 UINT64_C(1683005440), // FADDQV_H
2443 UINT64_C(1687199744), // FADDQV_S
2444 UINT64_C(505423872), // FADDSrr
2445 UINT64_C(1707089920), // FADDV_VPZ_D
2446 UINT64_C(1698701312), // FADDV_VPZ_H
2447 UINT64_C(1702895616), // FADDV_VPZ_S
2448 UINT64_C(3252689920), // FADD_VG2_M2Z_D
2449 UINT64_C(3248757760), // FADD_VG2_M2Z_H
2450 UINT64_C(3248495616), // FADD_VG2_M2Z_S
2451 UINT64_C(3252755456), // FADD_VG4_M4Z_D
2452 UINT64_C(3248823296), // FADD_VG4_M4Z_H
2453 UINT64_C(3248561152), // FADD_VG4_M4Z_S
2454 UINT64_C(1708687360), // FADD_ZPmI_D
2455 UINT64_C(1700298752), // FADD_ZPmI_H
2456 UINT64_C(1704493056), // FADD_ZPmI_S
2457 UINT64_C(1707114496), // FADD_ZPmZ_D
2458 UINT64_C(1698725888), // FADD_ZPmZ_H
2459 UINT64_C(1702920192), // FADD_ZPmZ_S
2460 UINT64_C(1707081728), // FADD_ZZZ_D
2461 UINT64_C(1698693120), // FADD_ZZZ_H
2462 UINT64_C(1702887424), // FADD_ZZZ_S
2463 UINT64_C(237032448), // FADDv2f32
2464 UINT64_C(1314968576), // FADDv2f64
2465 UINT64_C(239080448), // FADDv4f16
2466 UINT64_C(1310774272), // FADDv4f32
2467 UINT64_C(1312822272), // FADDv8f16
2468 UINT64_C(3252728128), // FAMAX_2Z2Z_D
2469 UINT64_C(3244339520), // FAMAX_2Z2Z_H
2470 UINT64_C(3248533824), // FAMAX_2Z2Z_S
2471 UINT64_C(3252730176), // FAMAX_4Z4Z_D
2472 UINT64_C(3244341568), // FAMAX_4Z4Z_H
2473 UINT64_C(3248535872), // FAMAX_4Z4Z_S
2474 UINT64_C(1708032000), // FAMAX_ZPmZ_D
2475 UINT64_C(1699643392), // FAMAX_ZPmZ_H
2476 UINT64_C(1703837696), // FAMAX_ZPmZ_S
2477 UINT64_C(245423104), // FAMAXv2f32
2478 UINT64_C(1323359232), // FAMAXv2f64
2479 UINT64_C(247471104), // FAMAXv4f16
2480 UINT64_C(1319164928), // FAMAXv4f32
2481 UINT64_C(1321212928), // FAMAXv8f16
2482 UINT64_C(3252728129), // FAMIN_2Z2Z_D
2483 UINT64_C(3244339521), // FAMIN_2Z2Z_H
2484 UINT64_C(3248533825), // FAMIN_2Z2Z_S
2485 UINT64_C(3252730177), // FAMIN_4Z4Z_D
2486 UINT64_C(3244341569), // FAMIN_4Z4Z_H
2487 UINT64_C(3248535873), // FAMIN_4Z4Z_S
2488 UINT64_C(1708097536), // FAMIN_ZPmZ_D
2489 UINT64_C(1699708928), // FAMIN_ZPmZ_H
2490 UINT64_C(1703903232), // FAMIN_ZPmZ_S
2491 UINT64_C(782294016), // FAMINv2f32
2492 UINT64_C(1860230144), // FAMINv2f64
2493 UINT64_C(784342016), // FAMINv4f16
2494 UINT64_C(1856035840), // FAMINv4f32
2495 UINT64_C(1858083840), // FAMINv8f16
2496 UINT64_C(1690337280), // FCADD_ZPmZ_D
2497 UINT64_C(1681948672), // FCADD_ZPmZ_H
2498 UINT64_C(1686142976), // FCADD_ZPmZ_S
2499 UINT64_C(780198912), // FCADDv2f32
2500 UINT64_C(1858135040), // FCADDv2f64
2501 UINT64_C(776004608), // FCADDv4f16
2502 UINT64_C(1853940736), // FCADDv4f32
2503 UINT64_C(1849746432), // FCADDv8f16
2504 UINT64_C(509608960), // FCCMPDrr
2505 UINT64_C(509608976), // FCCMPEDrr
2506 UINT64_C(517997584), // FCCMPEHrr
2507 UINT64_C(505414672), // FCCMPESrr
2508 UINT64_C(517997568), // FCCMPHrr
2509 UINT64_C(505414656), // FCCMPSrr
2510 UINT64_C(3252731904), // FCLAMP_VG2_2Z2Z_D
2511 UINT64_C(3244343296), // FCLAMP_VG2_2Z2Z_H
2512 UINT64_C(3248537600), // FCLAMP_VG2_2Z2Z_S
2513 UINT64_C(3252733952), // FCLAMP_VG4_4Z4Z_D
2514 UINT64_C(3244345344), // FCLAMP_VG4_4Z4Z_H
2515 UINT64_C(3248539648), // FCLAMP_VG4_4Z4Z_S
2516 UINT64_C(1692410880), // FCLAMP_ZZZ_D
2517 UINT64_C(1684022272), // FCLAMP_ZZZ_H
2518 UINT64_C(1688216576), // FCLAMP_ZZZ_S
2519 UINT64_C(1581261824), // FCMEQ16
2520 UINT64_C(1579213824), // FCMEQ32
2521 UINT64_C(1583408128), // FCMEQ64
2522 UINT64_C(1708269568), // FCMEQ_PPzZ0_D
2523 UINT64_C(1699880960), // FCMEQ_PPzZ0_H
2524 UINT64_C(1704075264), // FCMEQ_PPzZ0_S
2525 UINT64_C(1707106304), // FCMEQ_PPzZZ_D
2526 UINT64_C(1698717696), // FCMEQ_PPzZZ_H
2527 UINT64_C(1702912000), // FCMEQ_PPzZZ_S
2528 UINT64_C(1593366528), // FCMEQv1i16rz
2529 UINT64_C(1587599360), // FCMEQv1i32rz
2530 UINT64_C(1591793664), // FCMEQv1i64rz
2531 UINT64_C(237036544), // FCMEQv2f32
2532 UINT64_C(1314972672), // FCMEQv2f64
2533 UINT64_C(245422080), // FCMEQv2i32rz
2534 UINT64_C(1323358208), // FCMEQv2i64rz
2535 UINT64_C(239084544), // FCMEQv4f16
2536 UINT64_C(1310778368), // FCMEQv4f32
2537 UINT64_C(251189248), // FCMEQv4i16rz
2538 UINT64_C(1319163904), // FCMEQv4i32rz
2539 UINT64_C(1312826368), // FCMEQv8f16
2540 UINT64_C(1324931072), // FCMEQv8i16rz
2541 UINT64_C(2118132736), // FCMGE16
2542 UINT64_C(2116084736), // FCMGE32
2543 UINT64_C(2120279040), // FCMGE64
2544 UINT64_C(1708138496), // FCMGE_PPzZ0_D
2545 UINT64_C(1699749888), // FCMGE_PPzZ0_H
2546 UINT64_C(1703944192), // FCMGE_PPzZ0_S
2547 UINT64_C(1707098112), // FCMGE_PPzZZ_D
2548 UINT64_C(1698709504), // FCMGE_PPzZZ_H
2549 UINT64_C(1702903808), // FCMGE_PPzZZ_S
2550 UINT64_C(2130233344), // FCMGEv1i16rz
2551 UINT64_C(2124466176), // FCMGEv1i32rz
2552 UINT64_C(2128660480), // FCMGEv1i64rz
2553 UINT64_C(773907456), // FCMGEv2f32
2554 UINT64_C(1851843584), // FCMGEv2f64
2555 UINT64_C(782288896), // FCMGEv2i32rz
2556 UINT64_C(1860225024), // FCMGEv2i64rz
2557 UINT64_C(775955456), // FCMGEv4f16
2558 UINT64_C(1847649280), // FCMGEv4f32
2559 UINT64_C(788056064), // FCMGEv4i16rz
2560 UINT64_C(1856030720), // FCMGEv4i32rz
2561 UINT64_C(1849697280), // FCMGEv8f16
2562 UINT64_C(1861797888), // FCMGEv8i16rz
2563 UINT64_C(2126521344), // FCMGT16
2564 UINT64_C(2124473344), // FCMGT32
2565 UINT64_C(2128667648), // FCMGT64
2566 UINT64_C(1708138512), // FCMGT_PPzZ0_D
2567 UINT64_C(1699749904), // FCMGT_PPzZ0_H
2568 UINT64_C(1703944208), // FCMGT_PPzZ0_S
2569 UINT64_C(1707098128), // FCMGT_PPzZZ_D
2570 UINT64_C(1698709520), // FCMGT_PPzZZ_H
2571 UINT64_C(1702903824), // FCMGT_PPzZZ_S
2572 UINT64_C(1593362432), // FCMGTv1i16rz
2573 UINT64_C(1587595264), // FCMGTv1i32rz
2574 UINT64_C(1591789568), // FCMGTv1i64rz
2575 UINT64_C(782296064), // FCMGTv2f32
2576 UINT64_C(1860232192), // FCMGTv2f64
2577 UINT64_C(245417984), // FCMGTv2i32rz
2578 UINT64_C(1323354112), // FCMGTv2i64rz
2579 UINT64_C(784344064), // FCMGTv4f16
2580 UINT64_C(1856037888), // FCMGTv4f32
2581 UINT64_C(251185152), // FCMGTv4i16rz
2582 UINT64_C(1319159808), // FCMGTv4i32rz
2583 UINT64_C(1858085888), // FCMGTv8f16
2584 UINT64_C(1324926976), // FCMGTv8i16rz
2585 UINT64_C(1690304512), // FCMLA_ZPmZZ_D
2586 UINT64_C(1681915904), // FCMLA_ZPmZZ_H
2587 UINT64_C(1686110208), // FCMLA_ZPmZZ_S
2588 UINT64_C(1688211456), // FCMLA_ZZZI_H
2589 UINT64_C(1692405760), // FCMLA_ZZZI_S
2590 UINT64_C(780190720), // FCMLAv2f32
2591 UINT64_C(1858126848), // FCMLAv2f64
2592 UINT64_C(775996416), // FCMLAv4f16
2593 UINT64_C(792727552), // FCMLAv4f16_indexed
2594 UINT64_C(1853932544), // FCMLAv4f32
2595 UINT64_C(1870663680), // FCMLAv4f32_indexed
2596 UINT64_C(1849738240), // FCMLAv8f16
2597 UINT64_C(1866469376), // FCMLAv8f16_indexed
2598 UINT64_C(1708204048), // FCMLE_PPzZ0_D
2599 UINT64_C(1699815440), // FCMLE_PPzZ0_H
2600 UINT64_C(1704009744), // FCMLE_PPzZ0_S
2601 UINT64_C(2130237440), // FCMLEv1i16rz
2602 UINT64_C(2124470272), // FCMLEv1i32rz
2603 UINT64_C(2128664576), // FCMLEv1i64rz
2604 UINT64_C(782292992), // FCMLEv2i32rz
2605 UINT64_C(1860229120), // FCMLEv2i64rz
2606 UINT64_C(788060160), // FCMLEv4i16rz
2607 UINT64_C(1856034816), // FCMLEv4i32rz
2608 UINT64_C(1861801984), // FCMLEv8i16rz
2609 UINT64_C(1708204032), // FCMLT_PPzZ0_D
2610 UINT64_C(1699815424), // FCMLT_PPzZ0_H
2611 UINT64_C(1704009728), // FCMLT_PPzZ0_S
2612 UINT64_C(1593370624), // FCMLTv1i16rz
2613 UINT64_C(1587603456), // FCMLTv1i32rz
2614 UINT64_C(1591797760), // FCMLTv1i64rz
2615 UINT64_C(245426176), // FCMLTv2i32rz
2616 UINT64_C(1323362304), // FCMLTv2i64rz
2617 UINT64_C(251193344), // FCMLTv4i16rz
2618 UINT64_C(1319168000), // FCMLTv4i32rz
2619 UINT64_C(1324935168), // FCMLTv8i16rz
2620 UINT64_C(1708335104), // FCMNE_PPzZ0_D
2621 UINT64_C(1699946496), // FCMNE_PPzZ0_H
2622 UINT64_C(1704140800), // FCMNE_PPzZ0_S
2623 UINT64_C(1707106320), // FCMNE_PPzZZ_D
2624 UINT64_C(1698717712), // FCMNE_PPzZZ_H
2625 UINT64_C(1702912016), // FCMNE_PPzZZ_S
2626 UINT64_C(509616136), // FCMPDri
2627 UINT64_C(509616128), // FCMPDrr
2628 UINT64_C(509616152), // FCMPEDri
2629 UINT64_C(509616144), // FCMPEDrr
2630 UINT64_C(518004760), // FCMPEHri
2631 UINT64_C(518004752), // FCMPEHrr
2632 UINT64_C(505421848), // FCMPESri
2633 UINT64_C(505421840), // FCMPESrr
2634 UINT64_C(518004744), // FCMPHri
2635 UINT64_C(518004736), // FCMPHrr
2636 UINT64_C(505421832), // FCMPSri
2637 UINT64_C(505421824), // FCMPSrr
2638 UINT64_C(1707130880), // FCMUO_PPzZZ_D
2639 UINT64_C(1698742272), // FCMUO_PPzZZ_H
2640 UINT64_C(1702936576), // FCMUO_PPzZZ_S
2641 UINT64_C(97566720), // FCPY_ZPmI_D
2642 UINT64_C(89178112), // FCPY_ZPmI_H
2643 UINT64_C(93372416), // FCPY_ZPmI_S
2644 UINT64_C(509611008), // FCSELDrrr
2645 UINT64_C(517999616), // FCSELHrrr
2646 UINT64_C(505416704), // FCSELSrrr
2647 UINT64_C(509870080), // FCVTASUWDr
2648 UINT64_C(518258688), // FCVTASUWHr
2649 UINT64_C(505675776), // FCVTASUWSr
2650 UINT64_C(2657353728), // FCVTASUXDr
2651 UINT64_C(2665742336), // FCVTASUXHr
2652 UINT64_C(2653159424), // FCVTASUXSr
2653 UINT64_C(1585039360), // FCVTASv1f16
2654 UINT64_C(1579272192), // FCVTASv1i32
2655 UINT64_C(1583466496), // FCVTASv1i64
2656 UINT64_C(237094912), // FCVTASv2f32
2657 UINT64_C(1315031040), // FCVTASv2f64
2658 UINT64_C(242862080), // FCVTASv4f16
2659 UINT64_C(1310836736), // FCVTASv4f32
2660 UINT64_C(1316603904), // FCVTASv8f16
2661 UINT64_C(509935616), // FCVTAUUWDr
2662 UINT64_C(518324224), // FCVTAUUWHr
2663 UINT64_C(505741312), // FCVTAUUWSr
2664 UINT64_C(2657419264), // FCVTAUUXDr
2665 UINT64_C(2665807872), // FCVTAUUXHr
2666 UINT64_C(2653224960), // FCVTAUUXSr
2667 UINT64_C(2121910272), // FCVTAUv1f16
2668 UINT64_C(2116143104), // FCVTAUv1i32
2669 UINT64_C(2120337408), // FCVTAUv1i64
2670 UINT64_C(773965824), // FCVTAUv2f32
2671 UINT64_C(1851901952), // FCVTAUv2f64
2672 UINT64_C(779732992), // FCVTAUv4f16
2673 UINT64_C(1847707648), // FCVTAUv4f32
2674 UINT64_C(1853474816), // FCVTAUv8f16
2675 UINT64_C(518176768), // FCVTDHr
2676 UINT64_C(505593856), // FCVTDSr
2677 UINT64_C(509853696), // FCVTHDr
2678 UINT64_C(505659392), // FCVTHSr
2679 UINT64_C(1686740992), // FCVTLT_ZPmZ_HtoS
2680 UINT64_C(1691066368), // FCVTLT_ZPmZ_StoD
2681 UINT64_C(3248545793), // FCVTL_2ZZ_H_S
2682 UINT64_C(241268736), // FCVTLv2i32
2683 UINT64_C(237074432), // FCVTLv4i16
2684 UINT64_C(1315010560), // FCVTLv4i32
2685 UINT64_C(1310816256), // FCVTLv8i16
2686 UINT64_C(510656512), // FCVTMSUWDr
2687 UINT64_C(519045120), // FCVTMSUWHr
2688 UINT64_C(506462208), // FCVTMSUWSr
2689 UINT64_C(2658140160), // FCVTMSUXDr
2690 UINT64_C(2666528768), // FCVTMSUXHr
2691 UINT64_C(2653945856), // FCVTMSUXSr
2692 UINT64_C(1585035264), // FCVTMSv1f16
2693 UINT64_C(1579268096), // FCVTMSv1i32
2694 UINT64_C(1583462400), // FCVTMSv1i64
2695 UINT64_C(237090816), // FCVTMSv2f32
2696 UINT64_C(1315026944), // FCVTMSv2f64
2697 UINT64_C(242857984), // FCVTMSv4f16
2698 UINT64_C(1310832640), // FCVTMSv4f32
2699 UINT64_C(1316599808), // FCVTMSv8f16
2700 UINT64_C(510722048), // FCVTMUUWDr
2701 UINT64_C(519110656), // FCVTMUUWHr
2702 UINT64_C(506527744), // FCVTMUUWSr
2703 UINT64_C(2658205696), // FCVTMUUXDr
2704 UINT64_C(2666594304), // FCVTMUUXHr
2705 UINT64_C(2654011392), // FCVTMUUXSr
2706 UINT64_C(2121906176), // FCVTMUv1f16
2707 UINT64_C(2116139008), // FCVTMUv1i32
2708 UINT64_C(2120333312), // FCVTMUv1i64
2709 UINT64_C(773961728), // FCVTMUv2f32
2710 UINT64_C(1851897856), // FCVTMUv2f64
2711 UINT64_C(779728896), // FCVTMUv4f16
2712 UINT64_C(1847703552), // FCVTMUv4f32
2713 UINT64_C(1853470720), // FCVTMUv8f16
2714 UINT64_C(1695167488), // FCVTNB_Z2Z_StoB
2715 UINT64_C(509607936), // FCVTNSUWDr
2716 UINT64_C(517996544), // FCVTNSUWHr
2717 UINT64_C(505413632), // FCVTNSUWSr
2718 UINT64_C(2657091584), // FCVTNSUXDr
2719 UINT64_C(2665480192), // FCVTNSUXHr
2720 UINT64_C(2652897280), // FCVTNSUXSr
2721 UINT64_C(1585031168), // FCVTNSv1f16
2722 UINT64_C(1579264000), // FCVTNSv1i32
2723 UINT64_C(1583458304), // FCVTNSv1i64
2724 UINT64_C(237086720), // FCVTNSv2f32
2725 UINT64_C(1315022848), // FCVTNSv2f64
2726 UINT64_C(242853888), // FCVTNSv4f16
2727 UINT64_C(1310828544), // FCVTNSv4f32
2728 UINT64_C(1316595712), // FCVTNSv8f16
2729 UINT64_C(1695169536), // FCVTNT_Z2Z_StoB
2730 UINT64_C(1691000832), // FCVTNT_ZPmZ_DtoS
2731 UINT64_C(1686675456), // FCVTNT_ZPmZ_StoH
2732 UINT64_C(509673472), // FCVTNUUWDr
2733 UINT64_C(518062080), // FCVTNUUWHr
2734 UINT64_C(505479168), // FCVTNUUWSr
2735 UINT64_C(2657157120), // FCVTNUUXDr
2736 UINT64_C(2665545728), // FCVTNUUXHr
2737 UINT64_C(2652962816), // FCVTNUUXSr
2738 UINT64_C(2121902080), // FCVTNUv1f16
2739 UINT64_C(2116134912), // FCVTNUv1i32
2740 UINT64_C(2120329216), // FCVTNUv1i64
2741 UINT64_C(773957632), // FCVTNUv2f32
2742 UINT64_C(1851893760), // FCVTNUv2f64
2743 UINT64_C(779724800), // FCVTNUv4f16
2744 UINT64_C(1847699456), // FCVTNUv4f32
2745 UINT64_C(1853466624), // FCVTNUv8f16
2746 UINT64_C(1312879616), // FCVTN_F16_F8v16f8
2747 UINT64_C(239137792), // FCVTN_F16_F8v8f8
2748 UINT64_C(1308685312), // FCVTN_F32_F82v16f8
2749 UINT64_C(234943488), // FCVTN_F32_F8v8f8
2750 UINT64_C(1695166464), // FCVTN_Z2Z_HtoB
2751 UINT64_C(3240157216), // FCVTN_Z2Z_StoH
2752 UINT64_C(3241467936), // FCVTN_Z4Z_StoB_NAME
2753 UINT64_C(241264640), // FCVTNv2i32
2754 UINT64_C(237070336), // FCVTNv4i16
2755 UINT64_C(1315006464), // FCVTNv4i32
2756 UINT64_C(1310812160), // FCVTNv8i16
2757 UINT64_C(510132224), // FCVTPSUWDr
2758 UINT64_C(518520832), // FCVTPSUWHr
2759 UINT64_C(505937920), // FCVTPSUWSr
2760 UINT64_C(2657615872), // FCVTPSUXDr
2761 UINT64_C(2666004480), // FCVTPSUXHr
2762 UINT64_C(2653421568), // FCVTPSUXSr
2763 UINT64_C(1593419776), // FCVTPSv1f16
2764 UINT64_C(1587652608), // FCVTPSv1i32
2765 UINT64_C(1591846912), // FCVTPSv1i64
2766 UINT64_C(245475328), // FCVTPSv2f32
2767 UINT64_C(1323411456), // FCVTPSv2f64
2768 UINT64_C(251242496), // FCVTPSv4f16
2769 UINT64_C(1319217152), // FCVTPSv4f32
2770 UINT64_C(1324984320), // FCVTPSv8f16
2771 UINT64_C(510197760), // FCVTPUUWDr
2772 UINT64_C(518586368), // FCVTPUUWHr
2773 UINT64_C(506003456), // FCVTPUUWSr
2774 UINT64_C(2657681408), // FCVTPUUXDr
2775 UINT64_C(2666070016), // FCVTPUUXHr
2776 UINT64_C(2653487104), // FCVTPUUXSr
2777 UINT64_C(2130290688), // FCVTPUv1f16
2778 UINT64_C(2124523520), // FCVTPUv1i32
2779 UINT64_C(2128717824), // FCVTPUv1i64
2780 UINT64_C(782346240), // FCVTPUv2f32
2781 UINT64_C(1860282368), // FCVTPUv2f64
2782 UINT64_C(788113408), // FCVTPUv4f16
2783 UINT64_C(1856088064), // FCVTPUv4f32
2784 UINT64_C(1861855232), // FCVTPUv8f16
2785 UINT64_C(509755392), // FCVTSDr
2786 UINT64_C(518144000), // FCVTSHr
2787 UINT64_C(1678417920), // FCVTXNT_ZPmZ_DtoS
2788 UINT64_C(2120312832), // FCVTXNv1i64
2789 UINT64_C(778135552), // FCVTXNv2f32
2790 UINT64_C(1851877376), // FCVTXNv4f32
2791 UINT64_C(1695195136), // FCVTX_ZPmZ_DtoS
2792 UINT64_C(509116416), // FCVTZSSWDri
2793 UINT64_C(517505024), // FCVTZSSWHri
2794 UINT64_C(504922112), // FCVTZSSWSri
2795 UINT64_C(2656567296), // FCVTZSSXDri
2796 UINT64_C(2664955904), // FCVTZSSXHri
2797 UINT64_C(2652372992), // FCVTZSSXSri
2798 UINT64_C(511180800), // FCVTZSUWDr
2799 UINT64_C(519569408), // FCVTZSUWHr
2800 UINT64_C(506986496), // FCVTZSUWSr
2801 UINT64_C(2658664448), // FCVTZSUXDr
2802 UINT64_C(2667053056), // FCVTZSUXHr
2803 UINT64_C(2654470144), // FCVTZSUXSr
2804 UINT64_C(3240222720), // FCVTZS_2Z2Z_StoS
2805 UINT64_C(3241271296), // FCVTZS_4Z4Z_StoS
2806 UINT64_C(1709088768), // FCVTZS_ZPmZ_DtoD
2807 UINT64_C(1708695552), // FCVTZS_ZPmZ_DtoS
2808 UINT64_C(1700700160), // FCVTZS_ZPmZ_HtoD
2809 UINT64_C(1700438016), // FCVTZS_ZPmZ_HtoH
2810 UINT64_C(1700569088), // FCVTZS_ZPmZ_HtoS
2811 UINT64_C(1708957696), // FCVTZS_ZPmZ_StoD
2812 UINT64_C(1704763392), // FCVTZS_ZPmZ_StoS
2813 UINT64_C(1598094336), // FCVTZSd
2814 UINT64_C(1594948608), // FCVTZSh
2815 UINT64_C(1595997184), // FCVTZSs
2816 UINT64_C(1593423872), // FCVTZSv1f16
2817 UINT64_C(1587656704), // FCVTZSv1i32
2818 UINT64_C(1591851008), // FCVTZSv1i64
2819 UINT64_C(245479424), // FCVTZSv2f32
2820 UINT64_C(1323415552), // FCVTZSv2f64
2821 UINT64_C(253819904), // FCVTZSv2i32_shift
2822 UINT64_C(1329658880), // FCVTZSv2i64_shift
2823 UINT64_C(251246592), // FCVTZSv4f16
2824 UINT64_C(1319221248), // FCVTZSv4f32
2825 UINT64_C(252771328), // FCVTZSv4i16_shift
2826 UINT64_C(1327561728), // FCVTZSv4i32_shift
2827 UINT64_C(1324988416), // FCVTZSv8f16
2828 UINT64_C(1326513152), // FCVTZSv8i16_shift
2829 UINT64_C(509181952), // FCVTZUSWDri
2830 UINT64_C(517570560), // FCVTZUSWHri
2831 UINT64_C(504987648), // FCVTZUSWSri
2832 UINT64_C(2656632832), // FCVTZUSXDri
2833 UINT64_C(2665021440), // FCVTZUSXHri
2834 UINT64_C(2652438528), // FCVTZUSXSri
2835 UINT64_C(511246336), // FCVTZUUWDr
2836 UINT64_C(519634944), // FCVTZUUWHr
2837 UINT64_C(507052032), // FCVTZUUWSr
2838 UINT64_C(2658729984), // FCVTZUUXDr
2839 UINT64_C(2667118592), // FCVTZUUXHr
2840 UINT64_C(2654535680), // FCVTZUUXSr
2841 UINT64_C(3240222752), // FCVTZU_2Z2Z_StoS
2842 UINT64_C(3241271328), // FCVTZU_4Z4Z_StoS
2843 UINT64_C(1709154304), // FCVTZU_ZPmZ_DtoD
2844 UINT64_C(1708761088), // FCVTZU_ZPmZ_DtoS
2845 UINT64_C(1700765696), // FCVTZU_ZPmZ_HtoD
2846 UINT64_C(1700503552), // FCVTZU_ZPmZ_HtoH
2847 UINT64_C(1700634624), // FCVTZU_ZPmZ_HtoS
2848 UINT64_C(1709023232), // FCVTZU_ZPmZ_StoD
2849 UINT64_C(1704828928), // FCVTZU_ZPmZ_StoS
2850 UINT64_C(2134965248), // FCVTZUd
2851 UINT64_C(2131819520), // FCVTZUh
2852 UINT64_C(2132868096), // FCVTZUs
2853 UINT64_C(2130294784), // FCVTZUv1f16
2854 UINT64_C(2124527616), // FCVTZUv1i32
2855 UINT64_C(2128721920), // FCVTZUv1i64
2856 UINT64_C(782350336), // FCVTZUv2f32
2857 UINT64_C(1860286464), // FCVTZUv2f64
2858 UINT64_C(790690816), // FCVTZUv2i32_shift
2859 UINT64_C(1866529792), // FCVTZUv2i64_shift
2860 UINT64_C(788117504), // FCVTZUv4f16
2861 UINT64_C(1856092160), // FCVTZUv4f32
2862 UINT64_C(789642240), // FCVTZUv4i16_shift
2863 UINT64_C(1864432640), // FCVTZUv4i32_shift
2864 UINT64_C(1861859328), // FCVTZUv8f16
2865 UINT64_C(1863384064), // FCVTZUv8i16_shift
2866 UINT64_C(3248545792), // FCVT_2ZZ_H_S
2867 UINT64_C(3240419328), // FCVT_Z2Z_HtoB
2868 UINT64_C(3240157184), // FCVT_Z2Z_StoH
2869 UINT64_C(3241467904), // FCVT_Z4Z_StoB_NAME
2870 UINT64_C(1707646976), // FCVT_ZPmZ_DtoH
2871 UINT64_C(1707778048), // FCVT_ZPmZ_DtoS
2872 UINT64_C(1707712512), // FCVT_ZPmZ_HtoD
2873 UINT64_C(1703518208), // FCVT_ZPmZ_HtoS
2874 UINT64_C(1707843584), // FCVT_ZPmZ_StoD
2875 UINT64_C(1703452672), // FCVT_ZPmZ_StoH
2876 UINT64_C(509614080), // FDIVDrr
2877 UINT64_C(518002688), // FDIVHrr
2878 UINT64_C(1707900928), // FDIVR_ZPmZ_D
2879 UINT64_C(1699512320), // FDIVR_ZPmZ_H
2880 UINT64_C(1703706624), // FDIVR_ZPmZ_S
2881 UINT64_C(505419776), // FDIVSrr
2882 UINT64_C(1707966464), // FDIV_ZPmZ_D
2883 UINT64_C(1699577856), // FDIV_ZPmZ_H
2884 UINT64_C(1703772160), // FDIV_ZPmZ_S
2885 UINT64_C(773913600), // FDIVv2f32
2886 UINT64_C(1851849728), // FDIVv2f64
2887 UINT64_C(775961600), // FDIVv4f16
2888 UINT64_C(1847655424), // FDIVv4f32
2889 UINT64_C(1849703424), // FDIVv8f16
2890 UINT64_C(3248492576), // FDOT_VG2_M2Z2Z_BtoH
2891 UINT64_C(3248492592), // FDOT_VG2_M2Z2Z_BtoS
2892 UINT64_C(3248492544), // FDOT_VG2_M2Z2Z_HtoS
2893 UINT64_C(3251634208), // FDOT_VG2_M2ZZI_BtoH
2894 UINT64_C(3243245624), // FDOT_VG2_M2ZZI_BtoS
2895 UINT64_C(3243249672), // FDOT_VG2_M2ZZI_HtoS
2896 UINT64_C(3240103944), // FDOT_VG2_M2ZZ_BtoH
2897 UINT64_C(3240103960), // FDOT_VG2_M2ZZ_BtoS
2898 UINT64_C(3240103936), // FDOT_VG2_M2ZZ_HtoS
2899 UINT64_C(3248558112), // FDOT_VG4_M4Z4Z_BtoH
2900 UINT64_C(3248558128), // FDOT_VG4_M4Z4Z_BtoS
2901 UINT64_C(3248558080), // FDOT_VG4_M4Z4Z_HtoS
2902 UINT64_C(3239088192), // FDOT_VG4_M4ZZI_BtoH
2903 UINT64_C(3243278344), // FDOT_VG4_M4ZZI_BtoS
2904 UINT64_C(3243282440), // FDOT_VG4_M4ZZI_HtoS
2905 UINT64_C(3241152520), // FDOT_VG4_M4ZZ_BtoH
2906 UINT64_C(3241152536), // FDOT_VG4_M4ZZ_BtoS
2907 UINT64_C(3241152512), // FDOT_VG4_M4ZZ_HtoS
2908 UINT64_C(1679836160), // FDOT_ZZZI_BtoH
2909 UINT64_C(1684030464), // FDOT_ZZZI_BtoS
2910 UINT64_C(1679835136), // FDOT_ZZZI_S
2911 UINT64_C(1679852544), // FDOT_ZZZ_BtoH
2912 UINT64_C(1684046848), // FDOT_ZZZ_BtoS
2913 UINT64_C(1679851520), // FDOT_ZZZ_S
2914 UINT64_C(1325400064), // FDOTlanev16f8
2915 UINT64_C(255852544), // FDOTlanev4f16
2916 UINT64_C(1329594368), // FDOTlanev8f16
2917 UINT64_C(251658240), // FDOTlanev8f8
2918 UINT64_C(234945536), // FDOTv2f32
2919 UINT64_C(239139840), // FDOTv4f16
2920 UINT64_C(1308687360), // FDOTv4f32
2921 UINT64_C(1312881664), // FDOTv8f16
2922 UINT64_C(637124608), // FDUP_ZI_D
2923 UINT64_C(628736000), // FDUP_ZI_H
2924 UINT64_C(632930304), // FDUP_ZI_S
2925 UINT64_C(81836032), // FEXPA_ZZ_D
2926 UINT64_C(73447424), // FEXPA_ZZ_H
2927 UINT64_C(77641728), // FEXPA_ZZ_S
2928 UINT64_C(511574016), // FJCVTZS
2929 UINT64_C(1696505856), // FLOGB_ZPmZ_D
2930 UINT64_C(1696243712), // FLOGB_ZPmZ_H
2931 UINT64_C(1696374784), // FLOGB_ZPmZ_S
2932 UINT64_C(524288000), // FMADDDrrr
2933 UINT64_C(532676608), // FMADDHrrr
2934 UINT64_C(520093696), // FMADDSrrr
2935 UINT64_C(1709211648), // FMAD_ZPmZZ_D
2936 UINT64_C(1700823040), // FMAD_ZPmZZ_H
2937 UINT64_C(1705017344), // FMAD_ZPmZZ_S
2938 UINT64_C(509626368), // FMAXDrr
2939 UINT64_C(518014976), // FMAXHrr
2940 UINT64_C(509634560), // FMAXNMDrr
2941 UINT64_C(518023168), // FMAXNMHrr
2942 UINT64_C(1691648000), // FMAXNMP_ZPmZZ_D
2943 UINT64_C(1683259392), // FMAXNMP_ZPmZZ_H
2944 UINT64_C(1687453696), // FMAXNMP_ZPmZZ_S
2945 UINT64_C(773899264), // FMAXNMPv2f32
2946 UINT64_C(1851835392), // FMAXNMPv2f64
2947 UINT64_C(1580255232), // FMAXNMPv2i16p
2948 UINT64_C(2117126144), // FMAXNMPv2i32p
2949 UINT64_C(2121320448), // FMAXNMPv2i64p
2950 UINT64_C(775947264), // FMAXNMPv4f16
2951 UINT64_C(1847641088), // FMAXNMPv4f32
2952 UINT64_C(1849689088), // FMAXNMPv8f16
2953 UINT64_C(1691656192), // FMAXNMQV_D
2954 UINT64_C(1683267584), // FMAXNMQV_H
2955 UINT64_C(1687461888), // FMAXNMQV_S
2956 UINT64_C(505440256), // FMAXNMSrr
2957 UINT64_C(1707352064), // FMAXNMV_VPZ_D
2958 UINT64_C(1698963456), // FMAXNMV_VPZ_H
2959 UINT64_C(1703157760), // FMAXNMV_VPZ_S
2960 UINT64_C(238077952), // FMAXNMVv4i16v
2961 UINT64_C(1848690688), // FMAXNMVv4i32v
2962 UINT64_C(1311819776), // FMAXNMVv8i16v
2963 UINT64_C(3252728096), // FMAXNM_VG2_2Z2Z_D
2964 UINT64_C(3244339488), // FMAXNM_VG2_2Z2Z_H
2965 UINT64_C(3248533792), // FMAXNM_VG2_2Z2Z_S
2966 UINT64_C(3252724000), // FMAXNM_VG2_2ZZ_D
2967 UINT64_C(3244335392), // FMAXNM_VG2_2ZZ_H
2968 UINT64_C(3248529696), // FMAXNM_VG2_2ZZ_S
2969 UINT64_C(3252730144), // FMAXNM_VG4_4Z4Z_D
2970 UINT64_C(3244341536), // FMAXNM_VG4_4Z4Z_H
2971 UINT64_C(3248535840), // FMAXNM_VG4_4Z4Z_S
2972 UINT64_C(3252726048), // FMAXNM_VG4_4ZZ_D
2973 UINT64_C(3244337440), // FMAXNM_VG4_4ZZ_H
2974 UINT64_C(3248531744), // FMAXNM_VG4_4ZZ_S
2975 UINT64_C(1708949504), // FMAXNM_ZPmI_D
2976 UINT64_C(1700560896), // FMAXNM_ZPmI_H
2977 UINT64_C(1704755200), // FMAXNM_ZPmI_S
2978 UINT64_C(1707376640), // FMAXNM_ZPmZ_D
2979 UINT64_C(1698988032), // FMAXNM_ZPmZ_H
2980 UINT64_C(1703182336), // FMAXNM_ZPmZ_S
2981 UINT64_C(237028352), // FMAXNMv2f32
2982 UINT64_C(1314964480), // FMAXNMv2f64
2983 UINT64_C(239076352), // FMAXNMv4f16
2984 UINT64_C(1310770176), // FMAXNMv4f32
2985 UINT64_C(1312818176), // FMAXNMv8f16
2986 UINT64_C(1691779072), // FMAXP_ZPmZZ_D
2987 UINT64_C(1683390464), // FMAXP_ZPmZZ_H
2988 UINT64_C(1687584768), // FMAXP_ZPmZZ_S
2989 UINT64_C(773911552), // FMAXPv2f32
2990 UINT64_C(1851847680), // FMAXPv2f64
2991 UINT64_C(1580267520), // FMAXPv2i16p
2992 UINT64_C(2117138432), // FMAXPv2i32p
2993 UINT64_C(2121332736), // FMAXPv2i64p
2994 UINT64_C(775959552), // FMAXPv4f16
2995 UINT64_C(1847653376), // FMAXPv4f32
2996 UINT64_C(1849701376), // FMAXPv8f16
2997 UINT64_C(1691787264), // FMAXQV_D
2998 UINT64_C(1683398656), // FMAXQV_H
2999 UINT64_C(1687592960), // FMAXQV_S
3000 UINT64_C(505432064), // FMAXSrr
3001 UINT64_C(1707483136), // FMAXV_VPZ_D
3002 UINT64_C(1699094528), // FMAXV_VPZ_H
3003 UINT64_C(1703288832), // FMAXV_VPZ_S
3004 UINT64_C(238090240), // FMAXVv4i16v
3005 UINT64_C(1848702976), // FMAXVv4i32v
3006 UINT64_C(1311832064), // FMAXVv8i16v
3007 UINT64_C(3252728064), // FMAX_VG2_2Z2Z_D
3008 UINT64_C(3244339456), // FMAX_VG2_2Z2Z_H
3009 UINT64_C(3248533760), // FMAX_VG2_2Z2Z_S
3010 UINT64_C(3252723968), // FMAX_VG2_2ZZ_D
3011 UINT64_C(3244335360), // FMAX_VG2_2ZZ_H
3012 UINT64_C(3248529664), // FMAX_VG2_2ZZ_S
3013 UINT64_C(3252730112), // FMAX_VG4_4Z4Z_D
3014 UINT64_C(3244341504), // FMAX_VG4_4Z4Z_H
3015 UINT64_C(3248535808), // FMAX_VG4_4Z4Z_S
3016 UINT64_C(3252726016), // FMAX_VG4_4ZZ_D
3017 UINT64_C(3244337408), // FMAX_VG4_4ZZ_H
3018 UINT64_C(3248531712), // FMAX_VG4_4ZZ_S
3019 UINT64_C(1709080576), // FMAX_ZPmI_D
3020 UINT64_C(1700691968), // FMAX_ZPmI_H
3021 UINT64_C(1704886272), // FMAX_ZPmI_S
3022 UINT64_C(1707507712), // FMAX_ZPmZ_D
3023 UINT64_C(1699119104), // FMAX_ZPmZ_H
3024 UINT64_C(1703313408), // FMAX_ZPmZ_S
3025 UINT64_C(237040640), // FMAXv2f32
3026 UINT64_C(1314976768), // FMAXv2f64
3027 UINT64_C(239088640), // FMAXv4f16
3028 UINT64_C(1310782464), // FMAXv4f32
3029 UINT64_C(1312830464), // FMAXv8f16
3030 UINT64_C(509630464), // FMINDrr
3031 UINT64_C(518019072), // FMINHrr
3032 UINT64_C(509638656), // FMINNMDrr
3033 UINT64_C(518027264), // FMINNMHrr
3034 UINT64_C(1691713536), // FMINNMP_ZPmZZ_D
3035 UINT64_C(1683324928), // FMINNMP_ZPmZZ_H
3036 UINT64_C(1687519232), // FMINNMP_ZPmZZ_S
3037 UINT64_C(782287872), // FMINNMPv2f32
3038 UINT64_C(1860224000), // FMINNMPv2f64
3039 UINT64_C(1588643840), // FMINNMPv2i16p
3040 UINT64_C(2125514752), // FMINNMPv2i32p
3041 UINT64_C(2129709056), // FMINNMPv2i64p
3042 UINT64_C(784335872), // FMINNMPv4f16
3043 UINT64_C(1856029696), // FMINNMPv4f32
3044 UINT64_C(1858077696), // FMINNMPv8f16
3045 UINT64_C(1691721728), // FMINNMQV_D
3046 UINT64_C(1683333120), // FMINNMQV_H
3047 UINT64_C(1687527424), // FMINNMQV_S
3048 UINT64_C(505444352), // FMINNMSrr
3049 UINT64_C(1707417600), // FMINNMV_VPZ_D
3050 UINT64_C(1699028992), // FMINNMV_VPZ_H
3051 UINT64_C(1703223296), // FMINNMV_VPZ_S
3052 UINT64_C(246466560), // FMINNMVv4i16v
3053 UINT64_C(1857079296), // FMINNMVv4i32v
3054 UINT64_C(1320208384), // FMINNMVv8i16v
3055 UINT64_C(3252728097), // FMINNM_VG2_2Z2Z_D
3056 UINT64_C(3244339489), // FMINNM_VG2_2Z2Z_H
3057 UINT64_C(3248533793), // FMINNM_VG2_2Z2Z_S
3058 UINT64_C(3252724001), // FMINNM_VG2_2ZZ_D
3059 UINT64_C(3244335393), // FMINNM_VG2_2ZZ_H
3060 UINT64_C(3248529697), // FMINNM_VG2_2ZZ_S
3061 UINT64_C(3252730145), // FMINNM_VG4_4Z4Z_D
3062 UINT64_C(3244341537), // FMINNM_VG4_4Z4Z_H
3063 UINT64_C(3248535841), // FMINNM_VG4_4Z4Z_S
3064 UINT64_C(3252726049), // FMINNM_VG4_4ZZ_D
3065 UINT64_C(3244337441), // FMINNM_VG4_4ZZ_H
3066 UINT64_C(3248531745), // FMINNM_VG4_4ZZ_S
3067 UINT64_C(1709015040), // FMINNM_ZPmI_D
3068 UINT64_C(1700626432), // FMINNM_ZPmI_H
3069 UINT64_C(1704820736), // FMINNM_ZPmI_S
3070 UINT64_C(1707442176), // FMINNM_ZPmZ_D
3071 UINT64_C(1699053568), // FMINNM_ZPmZ_H
3072 UINT64_C(1703247872), // FMINNM_ZPmZ_S
3073 UINT64_C(245416960), // FMINNMv2f32
3074 UINT64_C(1323353088), // FMINNMv2f64
3075 UINT64_C(247464960), // FMINNMv4f16
3076 UINT64_C(1319158784), // FMINNMv4f32
3077 UINT64_C(1321206784), // FMINNMv8f16
3078 UINT64_C(1691844608), // FMINP_ZPmZZ_D
3079 UINT64_C(1683456000), // FMINP_ZPmZZ_H
3080 UINT64_C(1687650304), // FMINP_ZPmZZ_S
3081 UINT64_C(782300160), // FMINPv2f32
3082 UINT64_C(1860236288), // FMINPv2f64
3083 UINT64_C(1588656128), // FMINPv2i16p
3084 UINT64_C(2125527040), // FMINPv2i32p
3085 UINT64_C(2129721344), // FMINPv2i64p
3086 UINT64_C(784348160), // FMINPv4f16
3087 UINT64_C(1856041984), // FMINPv4f32
3088 UINT64_C(1858089984), // FMINPv8f16
3089 UINT64_C(1691852800), // FMINQV_D
3090 UINT64_C(1683464192), // FMINQV_H
3091 UINT64_C(1687658496), // FMINQV_S
3092 UINT64_C(505436160), // FMINSrr
3093 UINT64_C(1707548672), // FMINV_VPZ_D
3094 UINT64_C(1699160064), // FMINV_VPZ_H
3095 UINT64_C(1703354368), // FMINV_VPZ_S
3096 UINT64_C(246478848), // FMINVv4i16v
3097 UINT64_C(1857091584), // FMINVv4i32v
3098 UINT64_C(1320220672), // FMINVv8i16v
3099 UINT64_C(3252728065), // FMIN_VG2_2Z2Z_D
3100 UINT64_C(3244339457), // FMIN_VG2_2Z2Z_H
3101 UINT64_C(3248533761), // FMIN_VG2_2Z2Z_S
3102 UINT64_C(3252723969), // FMIN_VG2_2ZZ_D
3103 UINT64_C(3244335361), // FMIN_VG2_2ZZ_H
3104 UINT64_C(3248529665), // FMIN_VG2_2ZZ_S
3105 UINT64_C(3252730113), // FMIN_VG4_4Z4Z_D
3106 UINT64_C(3244341505), // FMIN_VG4_4Z4Z_H
3107 UINT64_C(3248535809), // FMIN_VG4_4Z4Z_S
3108 UINT64_C(3252726017), // FMIN_VG4_4ZZ_D
3109 UINT64_C(3244337409), // FMIN_VG4_4ZZ_H
3110 UINT64_C(3248531713), // FMIN_VG4_4ZZ_S
3111 UINT64_C(1709146112), // FMIN_ZPmI_D
3112 UINT64_C(1700757504), // FMIN_ZPmI_H
3113 UINT64_C(1704951808), // FMIN_ZPmI_S
3114 UINT64_C(1707573248), // FMIN_ZPmZ_D
3115 UINT64_C(1699184640), // FMIN_ZPmZ_H
3116 UINT64_C(1703378944), // FMIN_ZPmZ_S
3117 UINT64_C(245429248), // FMINv2f32
3118 UINT64_C(1323365376), // FMINv2f64
3119 UINT64_C(247477248), // FMINv4f16
3120 UINT64_C(1319171072), // FMINv4f32
3121 UINT64_C(1321219072), // FMINv8f16
3122 UINT64_C(796950528), // FMLAL2lanev4f16
3123 UINT64_C(1870692352), // FMLAL2lanev8f16
3124 UINT64_C(773901312), // FMLAL2v4f16
3125 UINT64_C(1847643136), // FMLAL2v8f16
3126 UINT64_C(1688242176), // FMLALB_ZZZ
3127 UINT64_C(1679839232), // FMLALB_ZZZI
3128 UINT64_C(1688223744), // FMLALB_ZZZI_SHH
3129 UINT64_C(1688240128), // FMLALB_ZZZ_SHH
3130 UINT64_C(264241152), // FMLALBlanev8f16
3131 UINT64_C(247528448), // FMLALBv8f16
3132 UINT64_C(1679853568), // FMLALLBB_ZZZ
3133 UINT64_C(1679867904), // FMLALLBB_ZZZI
3134 UINT64_C(788561920), // FMLALLBBlanev4f32
3135 UINT64_C(234931200), // FMLALLBBv4f32
3136 UINT64_C(1679857664), // FMLALLBT_ZZZ
3137 UINT64_C(1684062208), // FMLALLBT_ZZZI
3138 UINT64_C(792756224), // FMLALLBTlanev4f32
3139 UINT64_C(239125504), // FMLALLBTv4f32
3140 UINT64_C(1679861760), // FMLALLTB_ZZZ
3141 UINT64_C(1688256512), // FMLALLTB_ZZZI
3142 UINT64_C(1862303744), // FMLALLTBlanev4f32
3143 UINT64_C(1308673024), // FMLALLTBv4f32
3144 UINT64_C(1679865856), // FMLALLTT_ZZZ
3145 UINT64_C(1692450816), // FMLALLTT_ZZZI
3146 UINT64_C(1866498048), // FMLALLTTlanev4f32
3147 UINT64_C(1312867328), // FMLALLTTv4f32
3148 UINT64_C(3242196992), // FMLALL_MZZI_BtoS
3149 UINT64_C(3241149440), // FMLALL_MZZ_BtoS
3150 UINT64_C(3248488480), // FMLALL_VG2_M2Z2Z_BtoS
3151 UINT64_C(3247439904), // FMLALL_VG2_M2ZZI_BtoS
3152 UINT64_C(3240099842), // FMLALL_VG2_M2ZZ_BtoS
3153 UINT64_C(3248554016), // FMLALL_VG4_M4Z4Z_BtoS
3154 UINT64_C(3239084096), // FMLALL_VG4_M4ZZI_BtoS
3155 UINT64_C(3241148418), // FMLALL_VG4_M4ZZ_BtoS
3156 UINT64_C(1688246272), // FMLALT_ZZZ
3157 UINT64_C(1688227840), // FMLALT_ZZZI
3158 UINT64_C(1688224768), // FMLALT_ZZZI_SHH
3159 UINT64_C(1688241152), // FMLALT_ZZZ_SHH
3160 UINT64_C(1337982976), // FMLALTlanev8f16
3161 UINT64_C(1321270272), // FMLALTv8f16
3162 UINT64_C(3250585600), // FMLAL_MZZI_BtoH
3163 UINT64_C(3246395392), // FMLAL_MZZI_HtoS
3164 UINT64_C(3240102912), // FMLAL_MZZ_HtoS
3165 UINT64_C(3248490528), // FMLAL_VG2_M2Z2Z_BtoH
3166 UINT64_C(3248490496), // FMLAL_VG2_M2Z2Z_HtoS
3167 UINT64_C(3247444016), // FMLAL_VG2_M2ZZI_BtoH
3168 UINT64_C(3247443968), // FMLAL_VG2_M2ZZI_HtoS
3169 UINT64_C(3240101892), // FMLAL_VG2_M2ZZ_BtoH
3170 UINT64_C(3240101888), // FMLAL_VG2_M2ZZ_HtoS
3171 UINT64_C(3241151488), // FMLAL_VG2_MZZ_BtoH
3172 UINT64_C(3248556064), // FMLAL_VG4_M4Z4Z_BtoH
3173 UINT64_C(3248556032), // FMLAL_VG4_M4Z4Z_HtoS
3174 UINT64_C(3247476768), // FMLAL_VG4_M4ZZI_BtoH
3175 UINT64_C(3247476736), // FMLAL_VG4_M4ZZI_HtoS
3176 UINT64_C(3241150468), // FMLAL_VG4_M4ZZ_BtoH
3177 UINT64_C(3241150464), // FMLAL_VG4_M4ZZ_HtoS
3178 UINT64_C(260046848), // FMLALlanev4f16
3179 UINT64_C(1333788672), // FMLALlanev8f16
3180 UINT64_C(237038592), // FMLALv4f16
3181 UINT64_C(1310780416), // FMLALv8f16
3182 UINT64_C(3252688896), // FMLA_VG2_M2Z2Z_D
3183 UINT64_C(3248494592), // FMLA_VG2_M2Z2Z_S
3184 UINT64_C(3248492552), // FMLA_VG2_M2Z4Z_H
3185 UINT64_C(3251634176), // FMLA_VG2_M2ZZI_D
3186 UINT64_C(3239055360), // FMLA_VG2_M2ZZI_H
3187 UINT64_C(3243245568), // FMLA_VG2_M2ZZI_S
3188 UINT64_C(3244300288), // FMLA_VG2_M2ZZ_D
3189 UINT64_C(3240107008), // FMLA_VG2_M2ZZ_H
3190 UINT64_C(3240105984), // FMLA_VG2_M2ZZ_S
3191 UINT64_C(3252754432), // FMLA_VG4_M4Z4Z_D
3192 UINT64_C(3248558088), // FMLA_VG4_M4Z4Z_H
3193 UINT64_C(3248560128), // FMLA_VG4_M4Z4Z_S
3194 UINT64_C(3251666944), // FMLA_VG4_M4ZZI_D
3195 UINT64_C(3239088128), // FMLA_VG4_M4ZZI_H
3196 UINT64_C(3243278336), // FMLA_VG4_M4ZZI_S
3197 UINT64_C(3245348864), // FMLA_VG4_M4ZZ_D
3198 UINT64_C(3241155584), // FMLA_VG4_M4ZZ_H
3199 UINT64_C(3241154560), // FMLA_VG4_M4ZZ_S
3200 UINT64_C(1709178880), // FMLA_ZPmZZ_D
3201 UINT64_C(1700790272), // FMLA_ZPmZZ_H
3202 UINT64_C(1704984576), // FMLA_ZPmZZ_S
3203 UINT64_C(1692401664), // FMLA_ZZZI_D
3204 UINT64_C(1679818752), // FMLA_ZZZI_H
3205 UINT64_C(1688207360), // FMLA_ZZZI_S
3206 UINT64_C(1593839616), // FMLAv1i16_indexed
3207 UINT64_C(1602228224), // FMLAv1i32_indexed
3208 UINT64_C(1606422528), // FMLAv1i64_indexed
3209 UINT64_C(237030400), // FMLAv2f32
3210 UINT64_C(1314966528), // FMLAv2f64
3211 UINT64_C(260050944), // FMLAv2i32_indexed
3212 UINT64_C(1337987072), // FMLAv2i64_indexed
3213 UINT64_C(239078400), // FMLAv4f16
3214 UINT64_C(1310772224), // FMLAv4f32
3215 UINT64_C(251662336), // FMLAv4i16_indexed
3216 UINT64_C(1333792768), // FMLAv4i32_indexed
3217 UINT64_C(1312820224), // FMLAv8f16
3218 UINT64_C(1325404160), // FMLAv8i16_indexed
3219 UINT64_C(796966912), // FMLSL2lanev4f16
3220 UINT64_C(1870708736), // FMLSL2lanev8f16
3221 UINT64_C(782289920), // FMLSL2v4f16
3222 UINT64_C(1856031744), // FMLSL2v8f16
3223 UINT64_C(1688231936), // FMLSLB_ZZZI_SHH
3224 UINT64_C(1688248320), // FMLSLB_ZZZ_SHH
3225 UINT64_C(1688232960), // FMLSLT_ZZZI_SHH
3226 UINT64_C(1688249344), // FMLSLT_ZZZ_SHH
3227 UINT64_C(3246395400), // FMLSL_MZZI_HtoS
3228 UINT64_C(3240102920), // FMLSL_MZZ_HtoS
3229 UINT64_C(3248490504), // FMLSL_VG2_M2Z2Z_HtoS
3230 UINT64_C(3247443976), // FMLSL_VG2_M2ZZI_HtoS
3231 UINT64_C(3240101896), // FMLSL_VG2_M2ZZ_HtoS
3232 UINT64_C(3248556040), // FMLSL_VG4_M4Z4Z_HtoS
3233 UINT64_C(3247476744), // FMLSL_VG4_M4ZZI_HtoS
3234 UINT64_C(3241150472), // FMLSL_VG4_M4ZZ_HtoS
3235 UINT64_C(260063232), // FMLSLlanev4f16
3236 UINT64_C(1333805056), // FMLSLlanev8f16
3237 UINT64_C(245427200), // FMLSLv4f16
3238 UINT64_C(1319169024), // FMLSLv8f16
3239 UINT64_C(3252688904), // FMLS_VG2_M2Z2Z_D
3240 UINT64_C(3248492568), // FMLS_VG2_M2Z2Z_H
3241 UINT64_C(3248494600), // FMLS_VG2_M2Z2Z_S
3242 UINT64_C(3251634192), // FMLS_VG2_M2ZZI_D
3243 UINT64_C(3239055376), // FMLS_VG2_M2ZZI_H
3244 UINT64_C(3243245584), // FMLS_VG2_M2ZZI_S
3245 UINT64_C(3244300296), // FMLS_VG2_M2ZZ_D
3246 UINT64_C(3240107016), // FMLS_VG2_M2ZZ_H
3247 UINT64_C(3240105992), // FMLS_VG2_M2ZZ_S
3248 UINT64_C(3248558104), // FMLS_VG4_M4Z2Z_H
3249 UINT64_C(3252754440), // FMLS_VG4_M4Z4Z_D
3250 UINT64_C(3248560136), // FMLS_VG4_M4Z4Z_S
3251 UINT64_C(3251666960), // FMLS_VG4_M4ZZI_D
3252 UINT64_C(3239088144), // FMLS_VG4_M4ZZI_H
3253 UINT64_C(3243278352), // FMLS_VG4_M4ZZI_S
3254 UINT64_C(3245348872), // FMLS_VG4_M4ZZ_D
3255 UINT64_C(3241155592), // FMLS_VG4_M4ZZ_H
3256 UINT64_C(3241154568), // FMLS_VG4_M4ZZ_S
3257 UINT64_C(1709187072), // FMLS_ZPmZZ_D
3258 UINT64_C(1700798464), // FMLS_ZPmZZ_H
3259 UINT64_C(1704992768), // FMLS_ZPmZZ_S
3260 UINT64_C(1692402688), // FMLS_ZZZI_D
3261 UINT64_C(1679819776), // FMLS_ZZZI_H
3262 UINT64_C(1688208384), // FMLS_ZZZI_S
3263 UINT64_C(1593856000), // FMLSv1i16_indexed
3264 UINT64_C(1602244608), // FMLSv1i32_indexed
3265 UINT64_C(1606438912), // FMLSv1i64_indexed
3266 UINT64_C(245419008), // FMLSv2f32
3267 UINT64_C(1323355136), // FMLSv2f64
3268 UINT64_C(260067328), // FMLSv2i32_indexed
3269 UINT64_C(1338003456), // FMLSv2i64_indexed
3270 UINT64_C(247467008), // FMLSv4f16
3271 UINT64_C(1319160832), // FMLSv4f32
3272 UINT64_C(251678720), // FMLSv4i16_indexed
3273 UINT64_C(1333809152), // FMLSv4i32_indexed
3274 UINT64_C(1321208832), // FMLSv8f16
3275 UINT64_C(1325420544), // FMLSv8i16_indexed
3276 UINT64_C(1692460032), // FMMLA_ZZZ_D
3277 UINT64_C(1688265728), // FMMLA_ZZZ_S
3278 UINT64_C(2174746624), // FMOPAL_MPPZZ
3279 UINT64_C(2157969416), // FMOPA_MPPZZ_BtoH
3280 UINT64_C(2157969408), // FMOPA_MPPZZ_BtoS
3281 UINT64_C(2160066560), // FMOPA_MPPZZ_D
3282 UINT64_C(2172649480), // FMOPA_MPPZZ_H
3283 UINT64_C(2155872256), // FMOPA_MPPZZ_S
3284 UINT64_C(2174746640), // FMOPSL_MPPZZ
3285 UINT64_C(2160066576), // FMOPS_MPPZZ_D
3286 UINT64_C(2172649496), // FMOPS_MPPZZ_H
3287 UINT64_C(2155872272), // FMOPS_MPPZZ_S
3288 UINT64_C(2662203392), // FMOVDXHighr
3289 UINT64_C(2657484800), // FMOVDXr
3290 UINT64_C(509612032), // FMOVDi
3291 UINT64_C(509624320), // FMOVDr
3292 UINT64_C(518389760), // FMOVHWr
3293 UINT64_C(2665873408), // FMOVHXr
3294 UINT64_C(518000640), // FMOVHi
3295 UINT64_C(518012928), // FMOVHr
3296 UINT64_C(505806848), // FMOVSWr
3297 UINT64_C(505417728), // FMOVSi
3298 UINT64_C(505430016), // FMOVSr
3299 UINT64_C(518455296), // FMOVWHr
3300 UINT64_C(505872384), // FMOVWSr
3301 UINT64_C(2662268928), // FMOVXDHighr
3302 UINT64_C(2657550336), // FMOVXDr
3303 UINT64_C(2665938944), // FMOVXHr
3304 UINT64_C(251720704), // FMOVv2f32_ns
3305 UINT64_C(1862333440), // FMOVv2f64_ns
3306 UINT64_C(251722752), // FMOVv4f16_ns
3307 UINT64_C(1325462528), // FMOVv4f32_ns
3308 UINT64_C(1325464576), // FMOVv8f16_ns
3309 UINT64_C(1709219840), // FMSB_ZPmZZ_D
3310 UINT64_C(1700831232), // FMSB_ZPmZZ_H
3311 UINT64_C(1705025536), // FMSB_ZPmZZ_S
3312 UINT64_C(524320768), // FMSUBDrrr
3313 UINT64_C(532709376), // FMSUBHrrr
3314 UINT64_C(520126464), // FMSUBSrrr
3315 UINT64_C(509609984), // FMULDrr
3316 UINT64_C(517998592), // FMULHrr
3317 UINT64_C(505415680), // FMULSrr
3318 UINT64_C(1581259776), // FMULX16
3319 UINT64_C(1579211776), // FMULX32
3320 UINT64_C(1583406080), // FMULX64
3321 UINT64_C(1707769856), // FMULX_ZPmZ_D
3322 UINT64_C(1699381248), // FMULX_ZPmZ_H
3323 UINT64_C(1703575552), // FMULX_ZPmZ_S
3324 UINT64_C(2130743296), // FMULXv1i16_indexed
3325 UINT64_C(2139131904), // FMULXv1i32_indexed
3326 UINT64_C(2143326208), // FMULXv1i64_indexed
3327 UINT64_C(237034496), // FMULXv2f32
3328 UINT64_C(1314970624), // FMULXv2f64
3329 UINT64_C(796954624), // FMULXv2i32_indexed
3330 UINT64_C(1874890752), // FMULXv2i64_indexed
3331 UINT64_C(239082496), // FMULXv4f16
3332 UINT64_C(1310776320), // FMULXv4f32
3333 UINT64_C(788566016), // FMULXv4i16_indexed
3334 UINT64_C(1870696448), // FMULXv4i32_indexed
3335 UINT64_C(1312824320), // FMULXv8f16
3336 UINT64_C(1862307840), // FMULXv8i16_indexed
3337 UINT64_C(1708818432), // FMUL_ZPmI_D
3338 UINT64_C(1700429824), // FMUL_ZPmI_H
3339 UINT64_C(1704624128), // FMUL_ZPmI_S
3340 UINT64_C(1707245568), // FMUL_ZPmZ_D
3341 UINT64_C(1698856960), // FMUL_ZPmZ_H
3342 UINT64_C(1703051264), // FMUL_ZPmZ_S
3343 UINT64_C(1692409856), // FMUL_ZZZI_D
3344 UINT64_C(1679826944), // FMUL_ZZZI_H
3345 UINT64_C(1688215552), // FMUL_ZZZI_S
3346 UINT64_C(1707083776), // FMUL_ZZZ_D
3347 UINT64_C(1698695168), // FMUL_ZZZ_H
3348 UINT64_C(1702889472), // FMUL_ZZZ_S
3349 UINT64_C(1593872384), // FMULv1i16_indexed
3350 UINT64_C(1602260992), // FMULv1i32_indexed
3351 UINT64_C(1606455296), // FMULv1i64_indexed
3352 UINT64_C(773905408), // FMULv2f32
3353 UINT64_C(1851841536), // FMULv2f64
3354 UINT64_C(260083712), // FMULv2i32_indexed
3355 UINT64_C(1338019840), // FMULv2i64_indexed
3356 UINT64_C(775953408), // FMULv4f16
3357 UINT64_C(1847647232), // FMULv4f32
3358 UINT64_C(251695104), // FMULv4i16_indexed
3359 UINT64_C(1333825536), // FMULv4i32_indexed
3360 UINT64_C(1849695232), // FMULv8f16
3361 UINT64_C(1325436928), // FMULv8i16_indexed
3362 UINT64_C(509689856), // FNEGDr
3363 UINT64_C(518078464), // FNEGHr
3364 UINT64_C(505495552), // FNEGSr
3365 UINT64_C(81633280), // FNEG_ZPmZ_D
3366 UINT64_C(73244672), // FNEG_ZPmZ_H
3367 UINT64_C(77438976), // FNEG_ZPmZ_S
3368 UINT64_C(782301184), // FNEGv2f32
3369 UINT64_C(1860237312), // FNEGv2f64
3370 UINT64_C(788068352), // FNEGv4f16
3371 UINT64_C(1856043008), // FNEGv4f32
3372 UINT64_C(1861810176), // FNEGv8f16
3373 UINT64_C(526385152), // FNMADDDrrr
3374 UINT64_C(534773760), // FNMADDHrrr
3375 UINT64_C(522190848), // FNMADDSrrr
3376 UINT64_C(1709228032), // FNMAD_ZPmZZ_D
3377 UINT64_C(1700839424), // FNMAD_ZPmZZ_H
3378 UINT64_C(1705033728), // FNMAD_ZPmZZ_S
3379 UINT64_C(1709195264), // FNMLA_ZPmZZ_D
3380 UINT64_C(1700806656), // FNMLA_ZPmZZ_H
3381 UINT64_C(1705000960), // FNMLA_ZPmZZ_S
3382 UINT64_C(1709203456), // FNMLS_ZPmZZ_D
3383 UINT64_C(1700814848), // FNMLS_ZPmZZ_H
3384 UINT64_C(1705009152), // FNMLS_ZPmZZ_S
3385 UINT64_C(1709236224), // FNMSB_ZPmZZ_D
3386 UINT64_C(1700847616), // FNMSB_ZPmZZ_H
3387 UINT64_C(1705041920), // FNMSB_ZPmZZ_S
3388 UINT64_C(526417920), // FNMSUBDrrr
3389 UINT64_C(534806528), // FNMSUBHrrr
3390 UINT64_C(522223616), // FNMSUBSrrr
3391 UINT64_C(509642752), // FNMULDrr
3392 UINT64_C(518031360), // FNMULHrr
3393 UINT64_C(505448448), // FNMULSrr
3394 UINT64_C(1708011520), // FRECPE_ZZ_D
3395 UINT64_C(1699622912), // FRECPE_ZZ_H
3396 UINT64_C(1703817216), // FRECPE_ZZ_S
3397 UINT64_C(1593432064), // FRECPEv1f16
3398 UINT64_C(1587664896), // FRECPEv1i32
3399 UINT64_C(1591859200), // FRECPEv1i64
3400 UINT64_C(245487616), // FRECPEv2f32
3401 UINT64_C(1323423744), // FRECPEv2f64
3402 UINT64_C(251254784), // FRECPEv4f16
3403 UINT64_C(1319229440), // FRECPEv4f32
3404 UINT64_C(1324996608), // FRECPEv8f16
3405 UINT64_C(1581267968), // FRECPS16
3406 UINT64_C(1579219968), // FRECPS32
3407 UINT64_C(1583414272), // FRECPS64
3408 UINT64_C(1707087872), // FRECPS_ZZZ_D
3409 UINT64_C(1698699264), // FRECPS_ZZZ_H
3410 UINT64_C(1702893568), // FRECPS_ZZZ_S
3411 UINT64_C(237042688), // FRECPSv2f32
3412 UINT64_C(1314978816), // FRECPSv2f64
3413 UINT64_C(239090688), // FRECPSv4f16
3414 UINT64_C(1310784512), // FRECPSv4f32
3415 UINT64_C(1312832512), // FRECPSv8f16
3416 UINT64_C(1707909120), // FRECPX_ZPmZ_D
3417 UINT64_C(1699520512), // FRECPX_ZPmZ_H
3418 UINT64_C(1703714816), // FRECPX_ZPmZ_S
3419 UINT64_C(1593440256), // FRECPXv1f16
3420 UINT64_C(1587673088), // FRECPXv1i32
3421 UINT64_C(1591867392), // FRECPXv1i64
3422 UINT64_C(510181376), // FRINT32XDr
3423 UINT64_C(505987072), // FRINT32XSr
3424 UINT64_C(773974016), // FRINT32Xv2f32
3425 UINT64_C(1851910144), // FRINT32Xv2f64
3426 UINT64_C(1847715840), // FRINT32Xv4f32
3427 UINT64_C(510148608), // FRINT32ZDr
3428 UINT64_C(505954304), // FRINT32ZSr
3429 UINT64_C(237103104), // FRINT32Zv2f32
3430 UINT64_C(1315039232), // FRINT32Zv2f64
3431 UINT64_C(1310844928), // FRINT32Zv4f32
3432 UINT64_C(510246912), // FRINT64XDr
3433 UINT64_C(506052608), // FRINT64XSr
3434 UINT64_C(773978112), // FRINT64Xv2f32
3435 UINT64_C(1851914240), // FRINT64Xv2f64
3436 UINT64_C(1847719936), // FRINT64Xv4f32
3437 UINT64_C(510214144), // FRINT64ZDr
3438 UINT64_C(506019840), // FRINT64ZSr
3439 UINT64_C(237107200), // FRINT64Zv2f32
3440 UINT64_C(1315043328), // FRINT64Zv2f64
3441 UINT64_C(1310849024), // FRINT64Zv4f32
3442 UINT64_C(510017536), // FRINTADr
3443 UINT64_C(518406144), // FRINTAHr
3444 UINT64_C(505823232), // FRINTASr
3445 UINT64_C(3249332224), // FRINTA_2Z2Z_S
3446 UINT64_C(3250380800), // FRINTA_4Z4Z_S
3447 UINT64_C(1707384832), // FRINTA_ZPmZ_D
3448 UINT64_C(1698996224), // FRINTA_ZPmZ_H
3449 UINT64_C(1703190528), // FRINTA_ZPmZ_S
3450 UINT64_C(773949440), // FRINTAv2f32
3451 UINT64_C(1851885568), // FRINTAv2f64
3452 UINT64_C(779716608), // FRINTAv4f16
3453 UINT64_C(1847691264), // FRINTAv4f32
3454 UINT64_C(1853458432), // FRINTAv8f16
3455 UINT64_C(510115840), // FRINTIDr
3456 UINT64_C(518504448), // FRINTIHr
3457 UINT64_C(505921536), // FRINTISr
3458 UINT64_C(1707581440), // FRINTI_ZPmZ_D
3459 UINT64_C(1699192832), // FRINTI_ZPmZ_H
3460 UINT64_C(1703387136), // FRINTI_ZPmZ_S
3461 UINT64_C(782342144), // FRINTIv2f32
3462 UINT64_C(1860278272), // FRINTIv2f64
3463 UINT64_C(788109312), // FRINTIv4f16
3464 UINT64_C(1856083968), // FRINTIv4f32
3465 UINT64_C(1861851136), // FRINTIv8f16
3466 UINT64_C(509952000), // FRINTMDr
3467 UINT64_C(518340608), // FRINTMHr
3468 UINT64_C(505757696), // FRINTMSr
3469 UINT64_C(3249201152), // FRINTM_2Z2Z_S
3470 UINT64_C(3250249728), // FRINTM_4Z4Z_S
3471 UINT64_C(1707253760), // FRINTM_ZPmZ_D
3472 UINT64_C(1698865152), // FRINTM_ZPmZ_H
3473 UINT64_C(1703059456), // FRINTM_ZPmZ_S
3474 UINT64_C(237082624), // FRINTMv2f32
3475 UINT64_C(1315018752), // FRINTMv2f64
3476 UINT64_C(242849792), // FRINTMv4f16
3477 UINT64_C(1310824448), // FRINTMv4f32
3478 UINT64_C(1316591616), // FRINTMv8f16
3479 UINT64_C(509886464), // FRINTNDr
3480 UINT64_C(518275072), // FRINTNHr
3481 UINT64_C(505692160), // FRINTNSr
3482 UINT64_C(3249070080), // FRINTN_2Z2Z_S
3483 UINT64_C(3250118656), // FRINTN_4Z4Z_S
3484 UINT64_C(1707122688), // FRINTN_ZPmZ_D
3485 UINT64_C(1698734080), // FRINTN_ZPmZ_H
3486 UINT64_C(1702928384), // FRINTN_ZPmZ_S
3487 UINT64_C(237078528), // FRINTNv2f32
3488 UINT64_C(1315014656), // FRINTNv2f64
3489 UINT64_C(242845696), // FRINTNv4f16
3490 UINT64_C(1310820352), // FRINTNv4f32
3491 UINT64_C(1316587520), // FRINTNv8f16
3492 UINT64_C(509919232), // FRINTPDr
3493 UINT64_C(518307840), // FRINTPHr
3494 UINT64_C(505724928), // FRINTPSr
3495 UINT64_C(3249135616), // FRINTP_2Z2Z_S
3496 UINT64_C(3250184192), // FRINTP_4Z4Z_S
3497 UINT64_C(1707188224), // FRINTP_ZPmZ_D
3498 UINT64_C(1698799616), // FRINTP_ZPmZ_H
3499 UINT64_C(1702993920), // FRINTP_ZPmZ_S
3500 UINT64_C(245467136), // FRINTPv2f32
3501 UINT64_C(1323403264), // FRINTPv2f64
3502 UINT64_C(251234304), // FRINTPv4f16
3503 UINT64_C(1319208960), // FRINTPv4f32
3504 UINT64_C(1324976128), // FRINTPv8f16
3505 UINT64_C(510083072), // FRINTXDr
3506 UINT64_C(518471680), // FRINTXHr
3507 UINT64_C(505888768), // FRINTXSr
3508 UINT64_C(1707515904), // FRINTX_ZPmZ_D
3509 UINT64_C(1699127296), // FRINTX_ZPmZ_H
3510 UINT64_C(1703321600), // FRINTX_ZPmZ_S
3511 UINT64_C(773953536), // FRINTXv2f32
3512 UINT64_C(1851889664), // FRINTXv2f64
3513 UINT64_C(779720704), // FRINTXv4f16
3514 UINT64_C(1847695360), // FRINTXv4f32
3515 UINT64_C(1853462528), // FRINTXv8f16
3516 UINT64_C(509984768), // FRINTZDr
3517 UINT64_C(518373376), // FRINTZHr
3518 UINT64_C(505790464), // FRINTZSr
3519 UINT64_C(1707319296), // FRINTZ_ZPmZ_D
3520 UINT64_C(1698930688), // FRINTZ_ZPmZ_H
3521 UINT64_C(1703124992), // FRINTZ_ZPmZ_S
3522 UINT64_C(245471232), // FRINTZv2f32
3523 UINT64_C(1323407360), // FRINTZv2f64
3524 UINT64_C(251238400), // FRINTZv4f16
3525 UINT64_C(1319213056), // FRINTZv4f32
3526 UINT64_C(1324980224), // FRINTZv8f16
3527 UINT64_C(1708077056), // FRSQRTE_ZZ_D
3528 UINT64_C(1699688448), // FRSQRTE_ZZ_H
3529 UINT64_C(1703882752), // FRSQRTE_ZZ_S
3530 UINT64_C(2130302976), // FRSQRTEv1f16
3531 UINT64_C(2124535808), // FRSQRTEv1i32
3532 UINT64_C(2128730112), // FRSQRTEv1i64
3533 UINT64_C(782358528), // FRSQRTEv2f32
3534 UINT64_C(1860294656), // FRSQRTEv2f64
3535 UINT64_C(788125696), // FRSQRTEv4f16
3536 UINT64_C(1856100352), // FRSQRTEv4f32
3537 UINT64_C(1861867520), // FRSQRTEv8f16
3538 UINT64_C(1589656576), // FRSQRTS16
3539 UINT64_C(1587608576), // FRSQRTS32
3540 UINT64_C(1591802880), // FRSQRTS64
3541 UINT64_C(1707088896), // FRSQRTS_ZZZ_D
3542 UINT64_C(1698700288), // FRSQRTS_ZZZ_H
3543 UINT64_C(1702894592), // FRSQRTS_ZZZ_S
3544 UINT64_C(245431296), // FRSQRTSv2f32
3545 UINT64_C(1323367424), // FRSQRTSv2f64
3546 UINT64_C(247479296), // FRSQRTSv4f16
3547 UINT64_C(1319173120), // FRSQRTSv4f32
3548 UINT64_C(1321221120), // FRSQRTSv8f16
3549 UINT64_C(3252728192), // FSCALE_2Z2Z_D
3550 UINT64_C(3244339584), // FSCALE_2Z2Z_H
3551 UINT64_C(3248533888), // FSCALE_2Z2Z_S
3552 UINT64_C(3252724096), // FSCALE_2ZZ_D
3553 UINT64_C(3244335488), // FSCALE_2ZZ_H
3554 UINT64_C(3248529792), // FSCALE_2ZZ_S
3555 UINT64_C(3252730240), // FSCALE_4Z4Z_D
3556 UINT64_C(3244341632), // FSCALE_4Z4Z_H
3557 UINT64_C(3248535936), // FSCALE_4Z4Z_S
3558 UINT64_C(3252726144), // FSCALE_4ZZ_D
3559 UINT64_C(3244337536), // FSCALE_4ZZ_H
3560 UINT64_C(3248531840), // FSCALE_4ZZ_S
3561 UINT64_C(1707704320), // FSCALE_ZPmZ_D
3562 UINT64_C(1699315712), // FSCALE_ZPmZ_H
3563 UINT64_C(1703510016), // FSCALE_ZPmZ_S
3564 UINT64_C(782302208), // FSCALEv2f32
3565 UINT64_C(1860238336), // FSCALEv2f64
3566 UINT64_C(784350208), // FSCALEv4f16
3567 UINT64_C(1856044032), // FSCALEv4f32
3568 UINT64_C(1858092032), // FSCALEv8f16
3569 UINT64_C(509722624), // FSQRTDr
3570 UINT64_C(518111232), // FSQRTHr
3571 UINT64_C(505528320), // FSQRTSr
3572 UINT64_C(1707974656), // FSQRT_ZPmZ_D
3573 UINT64_C(1699586048), // FSQRT_ZPmZ_H
3574 UINT64_C(1703780352), // FSQRT_ZPmZ_S
3575 UINT64_C(782366720), // FSQRTv2f32
3576 UINT64_C(1860302848), // FSQRTv2f64
3577 UINT64_C(788133888), // FSQRTv4f16
3578 UINT64_C(1856108544), // FSQRTv4f32
3579 UINT64_C(1861875712), // FSQRTv8f16
3580 UINT64_C(509622272), // FSUBDrr
3581 UINT64_C(518010880), // FSUBHrr
3582 UINT64_C(1708883968), // FSUBR_ZPmI_D
3583 UINT64_C(1700495360), // FSUBR_ZPmI_H
3584 UINT64_C(1704689664), // FSUBR_ZPmI_S
3585 UINT64_C(1707311104), // FSUBR_ZPmZ_D
3586 UINT64_C(1698922496), // FSUBR_ZPmZ_H
3587 UINT64_C(1703116800), // FSUBR_ZPmZ_S
3588 UINT64_C(505427968), // FSUBSrr
3589 UINT64_C(3252689928), // FSUB_VG2_M2Z_D
3590 UINT64_C(3248757768), // FSUB_VG2_M2Z_H
3591 UINT64_C(3248495624), // FSUB_VG2_M2Z_S
3592 UINT64_C(3252755464), // FSUB_VG4_M4Z_D
3593 UINT64_C(3248823304), // FSUB_VG4_M4Z_H
3594 UINT64_C(3248561160), // FSUB_VG4_M4Z_S
3595 UINT64_C(1708752896), // FSUB_ZPmI_D
3596 UINT64_C(1700364288), // FSUB_ZPmI_H
3597 UINT64_C(1704558592), // FSUB_ZPmI_S
3598 UINT64_C(1707180032), // FSUB_ZPmZ_D
3599 UINT64_C(1698791424), // FSUB_ZPmZ_H
3600 UINT64_C(1702985728), // FSUB_ZPmZ_S
3601 UINT64_C(1707082752), // FSUB_ZZZ_D
3602 UINT64_C(1698694144), // FSUB_ZZZ_H
3603 UINT64_C(1702888448), // FSUB_ZZZ_S
3604 UINT64_C(245421056), // FSUBv2f32
3605 UINT64_C(1323357184), // FSUBv2f64
3606 UINT64_C(247469056), // FSUBv4f16
3607 UINT64_C(1319162880), // FSUBv4f32
3608 UINT64_C(1321210880), // FSUBv8f16
3609 UINT64_C(1708163072), // FTMAD_ZZI_D
3610 UINT64_C(1699774464), // FTMAD_ZZI_H
3611 UINT64_C(1703968768), // FTMAD_ZZI_S
3612 UINT64_C(1707084800), // FTSMUL_ZZZ_D
3613 UINT64_C(1698696192), // FTSMUL_ZZZ_H
3614 UINT64_C(1702890496), // FTSMUL_ZZZ_S
3615 UINT64_C(81833984), // FTSSEL_ZZZ_D
3616 UINT64_C(73445376), // FTSSEL_ZZZ_H
3617 UINT64_C(77639680), // FTSSEL_ZZZ_S
3618 UINT64_C(3251636224), // FVDOTB_VG4_M2ZZI_BtoS
3619 UINT64_C(3251636240), // FVDOTT_VG4_M2ZZI_BtoS
3620 UINT64_C(3251638304), // FVDOT_VG2_M2ZZI_BtoH
3621 UINT64_C(3243245576), // FVDOT_VG2_M2ZZI_HtoS
3622 UINT64_C(3574101951), // GCSPOPCX
3623 UINT64_C(3576395552), // GCSPOPM
3624 UINT64_C(3574101983), // GCSPOPX
3625 UINT64_C(3574298368), // GCSPUSHM
3626 UINT64_C(3574101919), // GCSPUSHX
3627 UINT64_C(3574298432), // GCSSS1
3628 UINT64_C(3576395616), // GCSSS2
3629 UINT64_C(3642690560), // GCSSTR
3630 UINT64_C(3642694656), // GCSSTTR
3631 UINT64_C(3292577792), // GLD1B_D
3632 UINT64_C(3290480640), // GLD1B_D_IMM
3633 UINT64_C(3292545024), // GLD1B_D_SXTW
3634 UINT64_C(3288350720), // GLD1B_D_UXTW
3635 UINT64_C(2216738816), // GLD1B_S_IMM
3636 UINT64_C(2218803200), // GLD1B_S_SXTW
3637 UINT64_C(2214608896), // GLD1B_S_UXTW
3638 UINT64_C(3317743616), // GLD1D
3639 UINT64_C(3315646464), // GLD1D_IMM
3640 UINT64_C(3319840768), // GLD1D_SCALED
3641 UINT64_C(3317710848), // GLD1D_SXTW
3642 UINT64_C(3319808000), // GLD1D_SXTW_SCALED
3643 UINT64_C(3313516544), // GLD1D_UXTW
3644 UINT64_C(3315613696), // GLD1D_UXTW_SCALED
3645 UINT64_C(3300966400), // GLD1H_D
3646 UINT64_C(3298869248), // GLD1H_D_IMM
3647 UINT64_C(3303063552), // GLD1H_D_SCALED
3648 UINT64_C(3300933632), // GLD1H_D_SXTW
3649 UINT64_C(3303030784), // GLD1H_D_SXTW_SCALED
3650 UINT64_C(3296739328), // GLD1H_D_UXTW
3651 UINT64_C(3298836480), // GLD1H_D_UXTW_SCALED
3652 UINT64_C(2225127424), // GLD1H_S_IMM
3653 UINT64_C(2227191808), // GLD1H_S_SXTW
3654 UINT64_C(2229288960), // GLD1H_S_SXTW_SCALED
3655 UINT64_C(2222997504), // GLD1H_S_UXTW
3656 UINT64_C(2225094656), // GLD1H_S_UXTW_SCALED
3657 UINT64_C(3288375296), // GLD1Q
3658 UINT64_C(3292561408), // GLD1SB_D
3659 UINT64_C(3290464256), // GLD1SB_D_IMM
3660 UINT64_C(3292528640), // GLD1SB_D_SXTW
3661 UINT64_C(3288334336), // GLD1SB_D_UXTW
3662 UINT64_C(2216722432), // GLD1SB_S_IMM
3663 UINT64_C(2218786816), // GLD1SB_S_SXTW
3664 UINT64_C(2214592512), // GLD1SB_S_UXTW
3665 UINT64_C(3300950016), // GLD1SH_D
3666 UINT64_C(3298852864), // GLD1SH_D_IMM
3667 UINT64_C(3303047168), // GLD1SH_D_SCALED
3668 UINT64_C(3300917248), // GLD1SH_D_SXTW
3669 UINT64_C(3303014400), // GLD1SH_D_SXTW_SCALED
3670 UINT64_C(3296722944), // GLD1SH_D_UXTW
3671 UINT64_C(3298820096), // GLD1SH_D_UXTW_SCALED
3672 UINT64_C(2225111040), // GLD1SH_S_IMM
3673 UINT64_C(2227175424), // GLD1SH_S_SXTW
3674 UINT64_C(2229272576), // GLD1SH_S_SXTW_SCALED
3675 UINT64_C(2222981120), // GLD1SH_S_UXTW
3676 UINT64_C(2225078272), // GLD1SH_S_UXTW_SCALED
3677 UINT64_C(3309338624), // GLD1SW_D
3678 UINT64_C(3307241472), // GLD1SW_D_IMM
3679 UINT64_C(3311435776), // GLD1SW_D_SCALED
3680 UINT64_C(3309305856), // GLD1SW_D_SXTW
3681 UINT64_C(3311403008), // GLD1SW_D_SXTW_SCALED
3682 UINT64_C(3305111552), // GLD1SW_D_UXTW
3683 UINT64_C(3307208704), // GLD1SW_D_UXTW_SCALED
3684 UINT64_C(3309355008), // GLD1W_D
3685 UINT64_C(3307257856), // GLD1W_D_IMM
3686 UINT64_C(3311452160), // GLD1W_D_SCALED
3687 UINT64_C(3309322240), // GLD1W_D_SXTW
3688 UINT64_C(3311419392), // GLD1W_D_SXTW_SCALED
3689 UINT64_C(3305127936), // GLD1W_D_UXTW
3690 UINT64_C(3307225088), // GLD1W_D_UXTW_SCALED
3691 UINT64_C(2233516032), // GLD1W_IMM
3692 UINT64_C(2235580416), // GLD1W_SXTW
3693 UINT64_C(2237677568), // GLD1W_SXTW_SCALED
3694 UINT64_C(2231386112), // GLD1W_UXTW
3695 UINT64_C(2233483264), // GLD1W_UXTW_SCALED
3696 UINT64_C(3292585984), // GLDFF1B_D
3697 UINT64_C(3290488832), // GLDFF1B_D_IMM
3698 UINT64_C(3292553216), // GLDFF1B_D_SXTW
3699 UINT64_C(3288358912), // GLDFF1B_D_UXTW
3700 UINT64_C(2216747008), // GLDFF1B_S_IMM
3701 UINT64_C(2218811392), // GLDFF1B_S_SXTW
3702 UINT64_C(2214617088), // GLDFF1B_S_UXTW
3703 UINT64_C(3317751808), // GLDFF1D
3704 UINT64_C(3315654656), // GLDFF1D_IMM
3705 UINT64_C(3319848960), // GLDFF1D_SCALED
3706 UINT64_C(3317719040), // GLDFF1D_SXTW
3707 UINT64_C(3319816192), // GLDFF1D_SXTW_SCALED
3708 UINT64_C(3313524736), // GLDFF1D_UXTW
3709 UINT64_C(3315621888), // GLDFF1D_UXTW_SCALED
3710 UINT64_C(3300974592), // GLDFF1H_D
3711 UINT64_C(3298877440), // GLDFF1H_D_IMM
3712 UINT64_C(3303071744), // GLDFF1H_D_SCALED
3713 UINT64_C(3300941824), // GLDFF1H_D_SXTW
3714 UINT64_C(3303038976), // GLDFF1H_D_SXTW_SCALED
3715 UINT64_C(3296747520), // GLDFF1H_D_UXTW
3716 UINT64_C(3298844672), // GLDFF1H_D_UXTW_SCALED
3717 UINT64_C(2225135616), // GLDFF1H_S_IMM
3718 UINT64_C(2227200000), // GLDFF1H_S_SXTW
3719 UINT64_C(2229297152), // GLDFF1H_S_SXTW_SCALED
3720 UINT64_C(2223005696), // GLDFF1H_S_UXTW
3721 UINT64_C(2225102848), // GLDFF1H_S_UXTW_SCALED
3722 UINT64_C(3292569600), // GLDFF1SB_D
3723 UINT64_C(3290472448), // GLDFF1SB_D_IMM
3724 UINT64_C(3292536832), // GLDFF1SB_D_SXTW
3725 UINT64_C(3288342528), // GLDFF1SB_D_UXTW
3726 UINT64_C(2216730624), // GLDFF1SB_S_IMM
3727 UINT64_C(2218795008), // GLDFF1SB_S_SXTW
3728 UINT64_C(2214600704), // GLDFF1SB_S_UXTW
3729 UINT64_C(3300958208), // GLDFF1SH_D
3730 UINT64_C(3298861056), // GLDFF1SH_D_IMM
3731 UINT64_C(3303055360), // GLDFF1SH_D_SCALED
3732 UINT64_C(3300925440), // GLDFF1SH_D_SXTW
3733 UINT64_C(3303022592), // GLDFF1SH_D_SXTW_SCALED
3734 UINT64_C(3296731136), // GLDFF1SH_D_UXTW
3735 UINT64_C(3298828288), // GLDFF1SH_D_UXTW_SCALED
3736 UINT64_C(2225119232), // GLDFF1SH_S_IMM
3737 UINT64_C(2227183616), // GLDFF1SH_S_SXTW
3738 UINT64_C(2229280768), // GLDFF1SH_S_SXTW_SCALED
3739 UINT64_C(2222989312), // GLDFF1SH_S_UXTW
3740 UINT64_C(2225086464), // GLDFF1SH_S_UXTW_SCALED
3741 UINT64_C(3309346816), // GLDFF1SW_D
3742 UINT64_C(3307249664), // GLDFF1SW_D_IMM
3743 UINT64_C(3311443968), // GLDFF1SW_D_SCALED
3744 UINT64_C(3309314048), // GLDFF1SW_D_SXTW
3745 UINT64_C(3311411200), // GLDFF1SW_D_SXTW_SCALED
3746 UINT64_C(3305119744), // GLDFF1SW_D_UXTW
3747 UINT64_C(3307216896), // GLDFF1SW_D_UXTW_SCALED
3748 UINT64_C(3309363200), // GLDFF1W_D
3749 UINT64_C(3307266048), // GLDFF1W_D_IMM
3750 UINT64_C(3311460352), // GLDFF1W_D_SCALED
3751 UINT64_C(3309330432), // GLDFF1W_D_SXTW
3752 UINT64_C(3311427584), // GLDFF1W_D_SXTW_SCALED
3753 UINT64_C(3305136128), // GLDFF1W_D_UXTW
3754 UINT64_C(3307233280), // GLDFF1W_D_UXTW_SCALED
3755 UINT64_C(2233524224), // GLDFF1W_IMM
3756 UINT64_C(2235588608), // GLDFF1W_SXTW
3757 UINT64_C(2237685760), // GLDFF1W_SXTW_SCALED
3758 UINT64_C(2231394304), // GLDFF1W_UXTW
3759 UINT64_C(2233491456), // GLDFF1W_UXTW_SCALED
3760 UINT64_C(2596279296), // GMI
3761 UINT64_C(3573751839), // HINT
3762 UINT64_C(1172357120), // HISTCNT_ZPzZZ_D
3763 UINT64_C(1168162816), // HISTCNT_ZPzZZ_S
3764 UINT64_C(1159766016), // HISTSEG_ZZZ
3765 UINT64_C(3560964096), // HLT
3766 UINT64_C(3556769794), // HVC
3767 UINT64_C(70311936), // INCB_XPiI
3768 UINT64_C(82894848), // INCD_XPiI
3769 UINT64_C(82886656), // INCD_ZPiI
3770 UINT64_C(74506240), // INCH_XPiI
3771 UINT64_C(74498048), // INCH_ZPiI
3772 UINT64_C(623675392), // INCP_XP_B
3773 UINT64_C(636258304), // INCP_XP_D
3774 UINT64_C(627869696), // INCP_XP_H
3775 UINT64_C(632064000), // INCP_XP_S
3776 UINT64_C(636256256), // INCP_ZP_D
3777 UINT64_C(627867648), // INCP_ZP_H
3778 UINT64_C(632061952), // INCP_ZP_S
3779 UINT64_C(78700544), // INCW_XPiI
3780 UINT64_C(78692352), // INCW_ZPiI
3781 UINT64_C(69222400), // INDEX_II_B
3782 UINT64_C(81805312), // INDEX_II_D
3783 UINT64_C(73416704), // INDEX_II_H
3784 UINT64_C(77611008), // INDEX_II_S
3785 UINT64_C(69224448), // INDEX_IR_B
3786 UINT64_C(81807360), // INDEX_IR_D
3787 UINT64_C(73418752), // INDEX_IR_H
3788 UINT64_C(77613056), // INDEX_IR_S
3789 UINT64_C(69223424), // INDEX_RI_B
3790 UINT64_C(81806336), // INDEX_RI_D
3791 UINT64_C(73417728), // INDEX_RI_H
3792 UINT64_C(77612032), // INDEX_RI_S
3793 UINT64_C(69225472), // INDEX_RR_B
3794 UINT64_C(81808384), // INDEX_RR_D
3795 UINT64_C(73419776), // INDEX_RR_H
3796 UINT64_C(77614080), // INDEX_RR_S
3797 UINT64_C(3221225472), // INSERT_MXIPZ_H_B
3798 UINT64_C(3233808384), // INSERT_MXIPZ_H_D
3799 UINT64_C(3225419776), // INSERT_MXIPZ_H_H
3800 UINT64_C(3233873920), // INSERT_MXIPZ_H_Q
3801 UINT64_C(3229614080), // INSERT_MXIPZ_H_S
3802 UINT64_C(3221258240), // INSERT_MXIPZ_V_B
3803 UINT64_C(3233841152), // INSERT_MXIPZ_V_D
3804 UINT64_C(3225452544), // INSERT_MXIPZ_V_H
3805 UINT64_C(3233906688), // INSERT_MXIPZ_V_Q
3806 UINT64_C(3229646848), // INSERT_MXIPZ_V_S
3807 UINT64_C(86259712), // INSR_ZR_B
3808 UINT64_C(98842624), // INSR_ZR_D
3809 UINT64_C(90454016), // INSR_ZR_H
3810 UINT64_C(94648320), // INSR_ZR_S
3811 UINT64_C(87308288), // INSR_ZV_B
3812 UINT64_C(99891200), // INSR_ZV_D
3813 UINT64_C(91502592), // INSR_ZV_H
3814 UINT64_C(95696896), // INSR_ZV_S
3815 UINT64_C(1308761088), // INSvi16gpr
3816 UINT64_C(1845625856), // INSvi16lane
3817 UINT64_C(1308892160), // INSvi32gpr
3818 UINT64_C(1845756928), // INSvi32lane
3819 UINT64_C(1309154304), // INSvi64gpr
3820 UINT64_C(1846019072), // INSvi64lane
3821 UINT64_C(1308695552), // INSvi8gpr
3822 UINT64_C(1845560320), // INSvi8lane
3823 UINT64_C(2596278272), // IRG
3824 UINT64_C(3573756127), // ISB
3825 UINT64_C(86024192), // LASTA_RPZ_B
3826 UINT64_C(98607104), // LASTA_RPZ_D
3827 UINT64_C(90218496), // LASTA_RPZ_H
3828 UINT64_C(94412800), // LASTA_RPZ_S
3829 UINT64_C(86147072), // LASTA_VPZ_B
3830 UINT64_C(98729984), // LASTA_VPZ_D
3831 UINT64_C(90341376), // LASTA_VPZ_H
3832 UINT64_C(94535680), // LASTA_VPZ_S
3833 UINT64_C(86089728), // LASTB_RPZ_B
3834 UINT64_C(98672640), // LASTB_RPZ_D
3835 UINT64_C(90284032), // LASTB_RPZ_H
3836 UINT64_C(94478336), // LASTB_RPZ_S
3837 UINT64_C(86212608), // LASTB_VPZ_B
3838 UINT64_C(98795520), // LASTB_VPZ_D
3839 UINT64_C(90406912), // LASTB_VPZ_H
3840 UINT64_C(94601216), // LASTB_VPZ_S
3841 UINT64_C(2751479808), // LD1B
3842 UINT64_C(2684354560), // LD1B_2Z
3843 UINT64_C(2688548864), // LD1B_2Z_IMM
3844 UINT64_C(2701131776), // LD1B_2Z_STRIDED
3845 UINT64_C(2705326080), // LD1B_2Z_STRIDED_IMM
3846 UINT64_C(2684387328), // LD1B_4Z
3847 UINT64_C(2688581632), // LD1B_4Z_IMM
3848 UINT64_C(2701164544), // LD1B_4Z_STRIDED
3849 UINT64_C(2705358848), // LD1B_4Z_STRIDED_IMM
3850 UINT64_C(2757771264), // LD1B_D
3851 UINT64_C(2757795840), // LD1B_D_IMM
3852 UINT64_C(2753576960), // LD1B_H
3853 UINT64_C(2753601536), // LD1B_H_IMM
3854 UINT64_C(2751504384), // LD1B_IMM
3855 UINT64_C(2755674112), // LD1B_S
3856 UINT64_C(2755698688), // LD1B_S_IMM
3857 UINT64_C(2782937088), // LD1D
3858 UINT64_C(2684379136), // LD1D_2Z
3859 UINT64_C(2688573440), // LD1D_2Z_IMM
3860 UINT64_C(2701156352), // LD1D_2Z_STRIDED
3861 UINT64_C(2705350656), // LD1D_2Z_STRIDED_IMM
3862 UINT64_C(2684411904), // LD1D_4Z
3863 UINT64_C(2688606208), // LD1D_4Z_IMM
3864 UINT64_C(2701189120), // LD1D_4Z_STRIDED
3865 UINT64_C(2705383424), // LD1D_4Z_STRIDED_IMM
3866 UINT64_C(2782961664), // LD1D_IMM
3867 UINT64_C(2776662016), // LD1D_Q
3868 UINT64_C(2777686016), // LD1D_Q_IMM
3869 UINT64_C(1279270912), // LD1Fourv16b
3870 UINT64_C(1287659520), // LD1Fourv16b_POST
3871 UINT64_C(205532160), // LD1Fourv1d
3872 UINT64_C(213920768), // LD1Fourv1d_POST
3873 UINT64_C(1279273984), // LD1Fourv2d
3874 UINT64_C(1287662592), // LD1Fourv2d_POST
3875 UINT64_C(205531136), // LD1Fourv2s
3876 UINT64_C(213919744), // LD1Fourv2s_POST
3877 UINT64_C(205530112), // LD1Fourv4h
3878 UINT64_C(213918720), // LD1Fourv4h_POST
3879 UINT64_C(1279272960), // LD1Fourv4s
3880 UINT64_C(1287661568), // LD1Fourv4s_POST
3881 UINT64_C(205529088), // LD1Fourv8b
3882 UINT64_C(213917696), // LD1Fourv8b_POST
3883 UINT64_C(1279271936), // LD1Fourv8h
3884 UINT64_C(1287660544), // LD1Fourv8h_POST
3885 UINT64_C(2761965568), // LD1H
3886 UINT64_C(2684362752), // LD1H_2Z
3887 UINT64_C(2688557056), // LD1H_2Z_IMM
3888 UINT64_C(2701139968), // LD1H_2Z_STRIDED
3889 UINT64_C(2705334272), // LD1H_2Z_STRIDED_IMM
3890 UINT64_C(2684395520), // LD1H_4Z
3891 UINT64_C(2688589824), // LD1H_4Z_IMM
3892 UINT64_C(2701172736), // LD1H_4Z_STRIDED
3893 UINT64_C(2705367040), // LD1H_4Z_STRIDED_IMM
3894 UINT64_C(2766159872), // LD1H_D
3895 UINT64_C(2766184448), // LD1H_D_IMM
3896 UINT64_C(2761990144), // LD1H_IMM
3897 UINT64_C(2764062720), // LD1H_S
3898 UINT64_C(2764087296), // LD1H_S_IMM
3899 UINT64_C(1279291392), // LD1Onev16b
3900 UINT64_C(1287680000), // LD1Onev16b_POST
3901 UINT64_C(205552640), // LD1Onev1d
3902 UINT64_C(213941248), // LD1Onev1d_POST
3903 UINT64_C(1279294464), // LD1Onev2d
3904 UINT64_C(1287683072), // LD1Onev2d_POST
3905 UINT64_C(205551616), // LD1Onev2s
3906 UINT64_C(213940224), // LD1Onev2s_POST
3907 UINT64_C(205550592), // LD1Onev4h
3908 UINT64_C(213939200), // LD1Onev4h_POST
3909 UINT64_C(1279293440), // LD1Onev4s
3910 UINT64_C(1287682048), // LD1Onev4s_POST
3911 UINT64_C(205549568), // LD1Onev8b
3912 UINT64_C(213938176), // LD1Onev8b_POST
3913 UINT64_C(1279292416), // LD1Onev8h
3914 UINT64_C(1287681024), // LD1Onev8h_POST
3915 UINT64_C(2218844160), // LD1RB_D_IMM
3916 UINT64_C(2218827776), // LD1RB_H_IMM
3917 UINT64_C(2218819584), // LD1RB_IMM
3918 UINT64_C(2218835968), // LD1RB_S_IMM
3919 UINT64_C(2244009984), // LD1RD_IMM
3920 UINT64_C(2227232768), // LD1RH_D_IMM
3921 UINT64_C(2227216384), // LD1RH_IMM
3922 UINT64_C(2227224576), // LD1RH_S_IMM
3923 UINT64_C(2753560576), // LD1RO_B
3924 UINT64_C(2753568768), // LD1RO_B_IMM
3925 UINT64_C(2778726400), // LD1RO_D
3926 UINT64_C(2778734592), // LD1RO_D_IMM
3927 UINT64_C(2761949184), // LD1RO_H
3928 UINT64_C(2761957376), // LD1RO_H_IMM
3929 UINT64_C(2770337792), // LD1RO_W
3930 UINT64_C(2770345984), // LD1RO_W_IMM
3931 UINT64_C(2751463424), // LD1RQ_B
3932 UINT64_C(2751471616), // LD1RQ_B_IMM
3933 UINT64_C(2776629248), // LD1RQ_D
3934 UINT64_C(2776637440), // LD1RQ_D_IMM
3935 UINT64_C(2759852032), // LD1RQ_H
3936 UINT64_C(2759860224), // LD1RQ_H_IMM
3937 UINT64_C(2768240640), // LD1RQ_W
3938 UINT64_C(2768248832), // LD1RQ_W_IMM
3939 UINT64_C(2243985408), // LD1RSB_D_IMM
3940 UINT64_C(2244001792), // LD1RSB_H_IMM
3941 UINT64_C(2243993600), // LD1RSB_S_IMM
3942 UINT64_C(2235596800), // LD1RSH_D_IMM
3943 UINT64_C(2235604992), // LD1RSH_S_IMM
3944 UINT64_C(2227208192), // LD1RSW_IMM
3945 UINT64_C(2235621376), // LD1RW_D_IMM
3946 UINT64_C(2235613184), // LD1RW_IMM
3947 UINT64_C(1296089088), // LD1Rv16b
3948 UINT64_C(1304477696), // LD1Rv16b_POST
3949 UINT64_C(222350336), // LD1Rv1d
3950 UINT64_C(230738944), // LD1Rv1d_POST
3951 UINT64_C(1296092160), // LD1Rv2d
3952 UINT64_C(1304480768), // LD1Rv2d_POST
3953 UINT64_C(222349312), // LD1Rv2s
3954 UINT64_C(230737920), // LD1Rv2s_POST
3955 UINT64_C(222348288), // LD1Rv4h
3956 UINT64_C(230736896), // LD1Rv4h_POST
3957 UINT64_C(1296091136), // LD1Rv4s
3958 UINT64_C(1304479744), // LD1Rv4s_POST
3959 UINT64_C(222347264), // LD1Rv8b
3960 UINT64_C(230735872), // LD1Rv8b_POST
3961 UINT64_C(1296090112), // LD1Rv8h
3962 UINT64_C(1304478720), // LD1Rv8h_POST
3963 UINT64_C(2776645632), // LD1SB_D
3964 UINT64_C(2776670208), // LD1SB_D_IMM
3965 UINT64_C(2780839936), // LD1SB_H
3966 UINT64_C(2780864512), // LD1SB_H_IMM
3967 UINT64_C(2778742784), // LD1SB_S
3968 UINT64_C(2778767360), // LD1SB_S_IMM
3969 UINT64_C(2768257024), // LD1SH_D
3970 UINT64_C(2768281600), // LD1SH_D_IMM
3971 UINT64_C(2770354176), // LD1SH_S
3972 UINT64_C(2770378752), // LD1SH_S_IMM
3973 UINT64_C(2759868416), // LD1SW_D
3974 UINT64_C(2759892992), // LD1SW_D_IMM
3975 UINT64_C(1279287296), // LD1Threev16b
3976 UINT64_C(1287675904), // LD1Threev16b_POST
3977 UINT64_C(205548544), // LD1Threev1d
3978 UINT64_C(213937152), // LD1Threev1d_POST
3979 UINT64_C(1279290368), // LD1Threev2d
3980 UINT64_C(1287678976), // LD1Threev2d_POST
3981 UINT64_C(205547520), // LD1Threev2s
3982 UINT64_C(213936128), // LD1Threev2s_POST
3983 UINT64_C(205546496), // LD1Threev4h
3984 UINT64_C(213935104), // LD1Threev4h_POST
3985 UINT64_C(1279289344), // LD1Threev4s
3986 UINT64_C(1287677952), // LD1Threev4s_POST
3987 UINT64_C(205545472), // LD1Threev8b
3988 UINT64_C(213934080), // LD1Threev8b_POST
3989 UINT64_C(1279288320), // LD1Threev8h
3990 UINT64_C(1287676928), // LD1Threev8h_POST
3991 UINT64_C(1279303680), // LD1Twov16b
3992 UINT64_C(1287692288), // LD1Twov16b_POST
3993 UINT64_C(205564928), // LD1Twov1d
3994 UINT64_C(213953536), // LD1Twov1d_POST
3995 UINT64_C(1279306752), // LD1Twov2d
3996 UINT64_C(1287695360), // LD1Twov2d_POST
3997 UINT64_C(205563904), // LD1Twov2s
3998 UINT64_C(213952512), // LD1Twov2s_POST
3999 UINT64_C(205562880), // LD1Twov4h
4000 UINT64_C(213951488), // LD1Twov4h_POST
4001 UINT64_C(1279305728), // LD1Twov4s
4002 UINT64_C(1287694336), // LD1Twov4s_POST
4003 UINT64_C(205561856), // LD1Twov8b
4004 UINT64_C(213950464), // LD1Twov8b_POST
4005 UINT64_C(1279304704), // LD1Twov8h
4006 UINT64_C(1287693312), // LD1Twov8h_POST
4007 UINT64_C(2772451328), // LD1W
4008 UINT64_C(2684370944), // LD1W_2Z
4009 UINT64_C(2688565248), // LD1W_2Z_IMM
4010 UINT64_C(2701148160), // LD1W_2Z_STRIDED
4011 UINT64_C(2705342464), // LD1W_2Z_STRIDED_IMM
4012 UINT64_C(2684403712), // LD1W_4Z
4013 UINT64_C(2688598016), // LD1W_4Z_IMM
4014 UINT64_C(2701180928), // LD1W_4Z_STRIDED
4015 UINT64_C(2705375232), // LD1W_4Z_STRIDED_IMM
4016 UINT64_C(2774548480), // LD1W_D
4017 UINT64_C(2774573056), // LD1W_D_IMM
4018 UINT64_C(2772475904), // LD1W_IMM
4019 UINT64_C(2768273408), // LD1W_Q
4020 UINT64_C(2769297408), // LD1W_Q_IMM
4021 UINT64_C(3758096384), // LD1_MXIPXX_H_B
4022 UINT64_C(3770679296), // LD1_MXIPXX_H_D
4023 UINT64_C(3762290688), // LD1_MXIPXX_H_H
4024 UINT64_C(3787456512), // LD1_MXIPXX_H_Q
4025 UINT64_C(3766484992), // LD1_MXIPXX_H_S
4026 UINT64_C(3758129152), // LD1_MXIPXX_V_B
4027 UINT64_C(3770712064), // LD1_MXIPXX_V_D
4028 UINT64_C(3762323456), // LD1_MXIPXX_V_H
4029 UINT64_C(3787489280), // LD1_MXIPXX_V_Q
4030 UINT64_C(3766517760), // LD1_MXIPXX_V_S
4031 UINT64_C(222314496), // LD1i16
4032 UINT64_C(230703104), // LD1i16_POST
4033 UINT64_C(222330880), // LD1i32
4034 UINT64_C(230719488), // LD1i32_POST
4035 UINT64_C(222331904), // LD1i64
4036 UINT64_C(230720512), // LD1i64_POST
4037 UINT64_C(222298112), // LD1i8
4038 UINT64_C(230686720), // LD1i8_POST
4039 UINT64_C(2753609728), // LD2B
4040 UINT64_C(2753617920), // LD2B_IMM
4041 UINT64_C(2778775552), // LD2D
4042 UINT64_C(2778783744), // LD2D_IMM
4043 UINT64_C(2761998336), // LD2H
4044 UINT64_C(2762006528), // LD2H_IMM
4045 UINT64_C(2761981952), // LD2Q
4046 UINT64_C(2760957952), // LD2Q_IMM
4047 UINT64_C(1298186240), // LD2Rv16b
4048 UINT64_C(1306574848), // LD2Rv16b_POST
4049 UINT64_C(224447488), // LD2Rv1d
4050 UINT64_C(232836096), // LD2Rv1d_POST
4051 UINT64_C(1298189312), // LD2Rv2d
4052 UINT64_C(1306577920), // LD2Rv2d_POST
4053 UINT64_C(224446464), // LD2Rv2s
4054 UINT64_C(232835072), // LD2Rv2s_POST
4055 UINT64_C(224445440), // LD2Rv4h
4056 UINT64_C(232834048), // LD2Rv4h_POST
4057 UINT64_C(1298188288), // LD2Rv4s
4058 UINT64_C(1306576896), // LD2Rv4s_POST
4059 UINT64_C(224444416), // LD2Rv8b
4060 UINT64_C(232833024), // LD2Rv8b_POST
4061 UINT64_C(1298187264), // LD2Rv8h
4062 UINT64_C(1306575872), // LD2Rv8h_POST
4063 UINT64_C(1279295488), // LD2Twov16b
4064 UINT64_C(1287684096), // LD2Twov16b_POST
4065 UINT64_C(1279298560), // LD2Twov2d
4066 UINT64_C(1287687168), // LD2Twov2d_POST
4067 UINT64_C(205555712), // LD2Twov2s
4068 UINT64_C(213944320), // LD2Twov2s_POST
4069 UINT64_C(205554688), // LD2Twov4h
4070 UINT64_C(213943296), // LD2Twov4h_POST
4071 UINT64_C(1279297536), // LD2Twov4s
4072 UINT64_C(1287686144), // LD2Twov4s_POST
4073 UINT64_C(205553664), // LD2Twov8b
4074 UINT64_C(213942272), // LD2Twov8b_POST
4075 UINT64_C(1279296512), // LD2Twov8h
4076 UINT64_C(1287685120), // LD2Twov8h_POST
4077 UINT64_C(2770386944), // LD2W
4078 UINT64_C(2770395136), // LD2W_IMM
4079 UINT64_C(224411648), // LD2i16
4080 UINT64_C(232800256), // LD2i16_POST
4081 UINT64_C(224428032), // LD2i32
4082 UINT64_C(232816640), // LD2i32_POST
4083 UINT64_C(224429056), // LD2i64
4084 UINT64_C(232817664), // LD2i64_POST
4085 UINT64_C(224395264), // LD2i8
4086 UINT64_C(232783872), // LD2i8_POST
4087 UINT64_C(2755706880), // LD3B
4088 UINT64_C(2755715072), // LD3B_IMM
4089 UINT64_C(2780872704), // LD3D
4090 UINT64_C(2780880896), // LD3D_IMM
4091 UINT64_C(2764095488), // LD3H
4092 UINT64_C(2764103680), // LD3H_IMM
4093 UINT64_C(2770370560), // LD3Q
4094 UINT64_C(2769346560), // LD3Q_IMM
4095 UINT64_C(1296097280), // LD3Rv16b
4096 UINT64_C(1304485888), // LD3Rv16b_POST
4097 UINT64_C(222358528), // LD3Rv1d
4098 UINT64_C(230747136), // LD3Rv1d_POST
4099 UINT64_C(1296100352), // LD3Rv2d
4100 UINT64_C(1304488960), // LD3Rv2d_POST
4101 UINT64_C(222357504), // LD3Rv2s
4102 UINT64_C(230746112), // LD3Rv2s_POST
4103 UINT64_C(222356480), // LD3Rv4h
4104 UINT64_C(230745088), // LD3Rv4h_POST
4105 UINT64_C(1296099328), // LD3Rv4s
4106 UINT64_C(1304487936), // LD3Rv4s_POST
4107 UINT64_C(222355456), // LD3Rv8b
4108 UINT64_C(230744064), // LD3Rv8b_POST
4109 UINT64_C(1296098304), // LD3Rv8h
4110 UINT64_C(1304486912), // LD3Rv8h_POST
4111 UINT64_C(1279279104), // LD3Threev16b
4112 UINT64_C(1287667712), // LD3Threev16b_POST
4113 UINT64_C(1279282176), // LD3Threev2d
4114 UINT64_C(1287670784), // LD3Threev2d_POST
4115 UINT64_C(205539328), // LD3Threev2s
4116 UINT64_C(213927936), // LD3Threev2s_POST
4117 UINT64_C(205538304), // LD3Threev4h
4118 UINT64_C(213926912), // LD3Threev4h_POST
4119 UINT64_C(1279281152), // LD3Threev4s
4120 UINT64_C(1287669760), // LD3Threev4s_POST
4121 UINT64_C(205537280), // LD3Threev8b
4122 UINT64_C(213925888), // LD3Threev8b_POST
4123 UINT64_C(1279280128), // LD3Threev8h
4124 UINT64_C(1287668736), // LD3Threev8h_POST
4125 UINT64_C(2772484096), // LD3W
4126 UINT64_C(2772492288), // LD3W_IMM
4127 UINT64_C(222322688), // LD3i16
4128 UINT64_C(230711296), // LD3i16_POST
4129 UINT64_C(222339072), // LD3i32
4130 UINT64_C(230727680), // LD3i32_POST
4131 UINT64_C(222340096), // LD3i64
4132 UINT64_C(230728704), // LD3i64_POST
4133 UINT64_C(222306304), // LD3i8
4134 UINT64_C(230694912), // LD3i8_POST
4135 UINT64_C(2757804032), // LD4B
4136 UINT64_C(2757812224), // LD4B_IMM
4137 UINT64_C(2782969856), // LD4D
4138 UINT64_C(2782978048), // LD4D_IMM
4139 UINT64_C(1279262720), // LD4Fourv16b
4140 UINT64_C(1287651328), // LD4Fourv16b_POST
4141 UINT64_C(1279265792), // LD4Fourv2d
4142 UINT64_C(1287654400), // LD4Fourv2d_POST
4143 UINT64_C(205522944), // LD4Fourv2s
4144 UINT64_C(213911552), // LD4Fourv2s_POST
4145 UINT64_C(205521920), // LD4Fourv4h
4146 UINT64_C(213910528), // LD4Fourv4h_POST
4147 UINT64_C(1279264768), // LD4Fourv4s
4148 UINT64_C(1287653376), // LD4Fourv4s_POST
4149 UINT64_C(205520896), // LD4Fourv8b
4150 UINT64_C(213909504), // LD4Fourv8b_POST
4151 UINT64_C(1279263744), // LD4Fourv8h
4152 UINT64_C(1287652352), // LD4Fourv8h_POST
4153 UINT64_C(2766192640), // LD4H
4154 UINT64_C(2766200832), // LD4H_IMM
4155 UINT64_C(2778759168), // LD4Q
4156 UINT64_C(2777735168), // LD4Q_IMM
4157 UINT64_C(1298194432), // LD4Rv16b
4158 UINT64_C(1306583040), // LD4Rv16b_POST
4159 UINT64_C(224455680), // LD4Rv1d
4160 UINT64_C(232844288), // LD4Rv1d_POST
4161 UINT64_C(1298197504), // LD4Rv2d
4162 UINT64_C(1306586112), // LD4Rv2d_POST
4163 UINT64_C(224454656), // LD4Rv2s
4164 UINT64_C(232843264), // LD4Rv2s_POST
4165 UINT64_C(224453632), // LD4Rv4h
4166 UINT64_C(232842240), // LD4Rv4h_POST
4167 UINT64_C(1298196480), // LD4Rv4s
4168 UINT64_C(1306585088), // LD4Rv4s_POST
4169 UINT64_C(224452608), // LD4Rv8b
4170 UINT64_C(232841216), // LD4Rv8b_POST
4171 UINT64_C(1298195456), // LD4Rv8h
4172 UINT64_C(1306584064), // LD4Rv8h_POST
4173 UINT64_C(2774581248), // LD4W
4174 UINT64_C(2774589440), // LD4W_IMM
4175 UINT64_C(224419840), // LD4i16
4176 UINT64_C(232808448), // LD4i16_POST
4177 UINT64_C(224436224), // LD4i32
4178 UINT64_C(232824832), // LD4i32_POST
4179 UINT64_C(224437248), // LD4i64
4180 UINT64_C(232825856), // LD4i64_POST
4181 UINT64_C(224403456), // LD4i8
4182 UINT64_C(232792064), // LD4i8_POST
4183 UINT64_C(4164931584), // LD64B
4184 UINT64_C(950009856), // LDADDAB
4185 UINT64_C(2023751680), // LDADDAH
4186 UINT64_C(954204160), // LDADDALB
4187 UINT64_C(2027945984), // LDADDALH
4188 UINT64_C(3101687808), // LDADDALW
4189 UINT64_C(4175429632), // LDADDALX
4190 UINT64_C(3097493504), // LDADDAW
4191 UINT64_C(4171235328), // LDADDAX
4192 UINT64_C(941621248), // LDADDB
4193 UINT64_C(2015363072), // LDADDH
4194 UINT64_C(945815552), // LDADDLB
4195 UINT64_C(2019557376), // LDADDLH
4196 UINT64_C(3093299200), // LDADDLW
4197 UINT64_C(4167041024), // LDADDLX
4198 UINT64_C(3089104896), // LDADDW
4199 UINT64_C(4162846720), // LDADDX
4200 UINT64_C(222397440), // LDAP1
4201 UINT64_C(952090624), // LDAPRB
4202 UINT64_C(2025832448), // LDAPRH
4203 UINT64_C(3099574272), // LDAPRW
4204 UINT64_C(2579499008), // LDAPRWpost
4205 UINT64_C(4173316096), // LDAPRX
4206 UINT64_C(3653240832), // LDAPRXpost
4207 UINT64_C(423624704), // LDAPURBi
4208 UINT64_C(1497366528), // LDAPURHi
4209 UINT64_C(432013312), // LDAPURSBWi
4210 UINT64_C(427819008), // LDAPURSBXi
4211 UINT64_C(1505755136), // LDAPURSHWi
4212 UINT64_C(1501560832), // LDAPURSHXi
4213 UINT64_C(2575302656), // LDAPURSWi
4214 UINT64_C(3644850176), // LDAPURXi
4215 UINT64_C(490735616), // LDAPURbi
4216 UINT64_C(3711961088), // LDAPURdi
4217 UINT64_C(1564477440), // LDAPURhi
4218 UINT64_C(2571108352), // LDAPURi
4219 UINT64_C(499124224), // LDAPURqi
4220 UINT64_C(2638219264), // LDAPURsi
4221 UINT64_C(148896768), // LDARB
4222 UINT64_C(1222638592), // LDARH
4223 UINT64_C(2296380416), // LDARW
4224 UINT64_C(3370122240), // LDARX
4225 UINT64_C(2288025600), // LDAXPW
4226 UINT64_C(3361767424), // LDAXPX
4227 UINT64_C(140508160), // LDAXRB
4228 UINT64_C(1214249984), // LDAXRH
4229 UINT64_C(2287991808), // LDAXRW
4230 UINT64_C(3361733632), // LDAXRX
4231 UINT64_C(950013952), // LDCLRAB
4232 UINT64_C(2023755776), // LDCLRAH
4233 UINT64_C(954208256), // LDCLRALB
4234 UINT64_C(2027950080), // LDCLRALH
4235 UINT64_C(3101691904), // LDCLRALW
4236 UINT64_C(4175433728), // LDCLRALX
4237 UINT64_C(3097497600), // LDCLRAW
4238 UINT64_C(4171239424), // LDCLRAX
4239 UINT64_C(941625344), // LDCLRB
4240 UINT64_C(2015367168), // LDCLRH
4241 UINT64_C(945819648), // LDCLRLB
4242 UINT64_C(2019561472), // LDCLRLH
4243 UINT64_C(3093303296), // LDCLRLW
4244 UINT64_C(4167045120), // LDCLRLX
4245 UINT64_C(421531648), // LDCLRP
4246 UINT64_C(429920256), // LDCLRPA
4247 UINT64_C(434114560), // LDCLRPAL
4248 UINT64_C(425725952), // LDCLRPL
4249 UINT64_C(3089108992), // LDCLRW
4250 UINT64_C(4162850816), // LDCLRX
4251 UINT64_C(950018048), // LDEORAB
4252 UINT64_C(2023759872), // LDEORAH
4253 UINT64_C(954212352), // LDEORALB
4254 UINT64_C(2027954176), // LDEORALH
4255 UINT64_C(3101696000), // LDEORALW
4256 UINT64_C(4175437824), // LDEORALX
4257 UINT64_C(3097501696), // LDEORAW
4258 UINT64_C(4171243520), // LDEORAX
4259 UINT64_C(941629440), // LDEORB
4260 UINT64_C(2015371264), // LDEORH
4261 UINT64_C(945823744), // LDEORLB
4262 UINT64_C(2019565568), // LDEORLH
4263 UINT64_C(3093307392), // LDEORLW
4264 UINT64_C(4167049216), // LDEORLX
4265 UINT64_C(3089113088), // LDEORW
4266 UINT64_C(4162854912), // LDEORX
4267 UINT64_C(2751488000), // LDFF1B
4268 UINT64_C(2757779456), // LDFF1B_D
4269 UINT64_C(2753585152), // LDFF1B_H
4270 UINT64_C(2755682304), // LDFF1B_S
4271 UINT64_C(2782945280), // LDFF1D
4272 UINT64_C(2761973760), // LDFF1H
4273 UINT64_C(2766168064), // LDFF1H_D
4274 UINT64_C(2764070912), // LDFF1H_S
4275 UINT64_C(2776653824), // LDFF1SB_D
4276 UINT64_C(2780848128), // LDFF1SB_H
4277 UINT64_C(2778750976), // LDFF1SB_S
4278 UINT64_C(2768265216), // LDFF1SH_D
4279 UINT64_C(2770362368), // LDFF1SH_S
4280 UINT64_C(2759876608), // LDFF1SW_D
4281 UINT64_C(2772459520), // LDFF1W
4282 UINT64_C(2774556672), // LDFF1W_D
4283 UINT64_C(3646947328), // LDG
4284 UINT64_C(3655335936), // LDGM
4285 UINT64_C(2571114496), // LDIAPPW
4286 UINT64_C(2571110400), // LDIAPPWpost
4287 UINT64_C(3644856320), // LDIAPPX
4288 UINT64_C(3644852224), // LDIAPPXpost
4289 UINT64_C(148864000), // LDLARB
4290 UINT64_C(1222605824), // LDLARH
4291 UINT64_C(2296347648), // LDLARW
4292 UINT64_C(3370089472), // LDLARX
4293 UINT64_C(2758844416), // LDNF1B_D_IMM
4294 UINT64_C(2754650112), // LDNF1B_H_IMM
4295 UINT64_C(2752552960), // LDNF1B_IMM
4296 UINT64_C(2756747264), // LDNF1B_S_IMM
4297 UINT64_C(2784010240), // LDNF1D_IMM
4298 UINT64_C(2767233024), // LDNF1H_D_IMM
4299 UINT64_C(2763038720), // LDNF1H_IMM
4300 UINT64_C(2765135872), // LDNF1H_S_IMM
4301 UINT64_C(2777718784), // LDNF1SB_D_IMM
4302 UINT64_C(2781913088), // LDNF1SB_H_IMM
4303 UINT64_C(2779815936), // LDNF1SB_S_IMM
4304 UINT64_C(2769330176), // LDNF1SH_D_IMM
4305 UINT64_C(2771427328), // LDNF1SH_S_IMM
4306 UINT64_C(2760941568), // LDNF1SW_D_IMM
4307 UINT64_C(2775621632), // LDNF1W_D_IMM
4308 UINT64_C(2773524480), // LDNF1W_IMM
4309 UINT64_C(1816133632), // LDNPDi
4310 UINT64_C(2889875456), // LDNPQi
4311 UINT64_C(742391808), // LDNPSi
4312 UINT64_C(675282944), // LDNPWi
4313 UINT64_C(2822766592), // LDNPXi
4314 UINT64_C(2684354561), // LDNT1B_2Z
4315 UINT64_C(2688548865), // LDNT1B_2Z_IMM
4316 UINT64_C(2701131784), // LDNT1B_2Z_STRIDED
4317 UINT64_C(2705326088), // LDNT1B_2Z_STRIDED_IMM
4318 UINT64_C(2684387329), // LDNT1B_4Z
4319 UINT64_C(2688581633), // LDNT1B_4Z_IMM
4320 UINT64_C(2701164552), // LDNT1B_4Z_STRIDED
4321 UINT64_C(2705358856), // LDNT1B_4Z_STRIDED_IMM
4322 UINT64_C(2751520768), // LDNT1B_ZRI
4323 UINT64_C(2751512576), // LDNT1B_ZRR
4324 UINT64_C(3288383488), // LDNT1B_ZZR_D
4325 UINT64_C(2214633472), // LDNT1B_ZZR_S
4326 UINT64_C(2684379137), // LDNT1D_2Z
4327 UINT64_C(2688573441), // LDNT1D_2Z_IMM
4328 UINT64_C(2701156360), // LDNT1D_2Z_STRIDED
4329 UINT64_C(2705350664), // LDNT1D_2Z_STRIDED_IMM
4330 UINT64_C(2684411905), // LDNT1D_4Z
4331 UINT64_C(2688606209), // LDNT1D_4Z_IMM
4332 UINT64_C(2701189128), // LDNT1D_4Z_STRIDED
4333 UINT64_C(2705383432), // LDNT1D_4Z_STRIDED_IMM
4334 UINT64_C(2776686592), // LDNT1D_ZRI
4335 UINT64_C(2776678400), // LDNT1D_ZRR
4336 UINT64_C(3313549312), // LDNT1D_ZZR_D
4337 UINT64_C(2684362753), // LDNT1H_2Z
4338 UINT64_C(2688557057), // LDNT1H_2Z_IMM
4339 UINT64_C(2701139976), // LDNT1H_2Z_STRIDED
4340 UINT64_C(2705334280), // LDNT1H_2Z_STRIDED_IMM
4341 UINT64_C(2684395521), // LDNT1H_4Z
4342 UINT64_C(2688589825), // LDNT1H_4Z_IMM
4343 UINT64_C(2701172744), // LDNT1H_4Z_STRIDED
4344 UINT64_C(2705367048), // LDNT1H_4Z_STRIDED_IMM
4345 UINT64_C(2759909376), // LDNT1H_ZRI
4346 UINT64_C(2759901184), // LDNT1H_ZRR
4347 UINT64_C(3296772096), // LDNT1H_ZZR_D
4348 UINT64_C(2223022080), // LDNT1H_ZZR_S
4349 UINT64_C(3288367104), // LDNT1SB_ZZR_D
4350 UINT64_C(2214625280), // LDNT1SB_ZZR_S
4351 UINT64_C(3296755712), // LDNT1SH_ZZR_D
4352 UINT64_C(2223013888), // LDNT1SH_ZZR_S
4353 UINT64_C(3305144320), // LDNT1SW_ZZR_D
4354 UINT64_C(2684370945), // LDNT1W_2Z
4355 UINT64_C(2688565249), // LDNT1W_2Z_IMM
4356 UINT64_C(2701148168), // LDNT1W_2Z_STRIDED
4357 UINT64_C(2705342472), // LDNT1W_2Z_STRIDED_IMM
4358 UINT64_C(2684403713), // LDNT1W_4Z
4359 UINT64_C(2688598017), // LDNT1W_4Z_IMM
4360 UINT64_C(2701180936), // LDNT1W_4Z_STRIDED
4361 UINT64_C(2705375240), // LDNT1W_4Z_STRIDED_IMM
4362 UINT64_C(2768297984), // LDNT1W_ZRI
4363 UINT64_C(2768289792), // LDNT1W_ZRR
4364 UINT64_C(3305160704), // LDNT1W_ZZR_D
4365 UINT64_C(2231410688), // LDNT1W_ZZR_S
4366 UINT64_C(1832910848), // LDPDi
4367 UINT64_C(1824522240), // LDPDpost
4368 UINT64_C(1841299456), // LDPDpre
4369 UINT64_C(2906652672), // LDPQi
4370 UINT64_C(2898264064), // LDPQpost
4371 UINT64_C(2915041280), // LDPQpre
4372 UINT64_C(1765801984), // LDPSWi
4373 UINT64_C(1757413376), // LDPSWpost
4374 UINT64_C(1774190592), // LDPSWpre
4375 UINT64_C(759169024), // LDPSi
4376 UINT64_C(750780416), // LDPSpost
4377 UINT64_C(767557632), // LDPSpre
4378 UINT64_C(692060160), // LDPWi
4379 UINT64_C(683671552), // LDPWpost
4380 UINT64_C(700448768), // LDPWpre
4381 UINT64_C(2839543808), // LDPXi
4382 UINT64_C(2831155200), // LDPXpost
4383 UINT64_C(2847932416), // LDPXpre
4384 UINT64_C(4162847744), // LDRAAindexed
4385 UINT64_C(4162849792), // LDRAAwriteback
4386 UINT64_C(4171236352), // LDRABindexed
4387 UINT64_C(4171238400), // LDRABwriteback
4388 UINT64_C(943719424), // LDRBBpost
4389 UINT64_C(943721472), // LDRBBpre
4390 UINT64_C(945833984), // LDRBBroW
4391 UINT64_C(945842176), // LDRBBroX
4392 UINT64_C(960495616), // LDRBBui
4393 UINT64_C(1010828288), // LDRBpost
4394 UINT64_C(1010830336), // LDRBpre
4395 UINT64_C(1012942848), // LDRBroW
4396 UINT64_C(1012951040), // LDRBroX
4397 UINT64_C(1027604480), // LDRBui
4398 UINT64_C(1543503872), // LDRDl
4399 UINT64_C(4232053760), // LDRDpost
4400 UINT64_C(4232055808), // LDRDpre
4401 UINT64_C(4234168320), // LDRDroW
4402 UINT64_C(4234176512), // LDRDroX
4403 UINT64_C(4248829952), // LDRDui
4404 UINT64_C(2017461248), // LDRHHpost
4405 UINT64_C(2017463296), // LDRHHpre
4406 UINT64_C(2019575808), // LDRHHroW
4407 UINT64_C(2019584000), // LDRHHroX
4408 UINT64_C(2034237440), // LDRHHui
4409 UINT64_C(2084570112), // LDRHpost
4410 UINT64_C(2084572160), // LDRHpre
4411 UINT64_C(2086684672), // LDRHroW
4412 UINT64_C(2086692864), // LDRHroX
4413 UINT64_C(2101346304), // LDRHui
4414 UINT64_C(2617245696), // LDRQl
4415 UINT64_C(1019216896), // LDRQpost
4416 UINT64_C(1019218944), // LDRQpre
4417 UINT64_C(1021331456), // LDRQroW
4418 UINT64_C(1021339648), // LDRQroX
4419 UINT64_C(1035993088), // LDRQui
4420 UINT64_C(952108032), // LDRSBWpost
4421 UINT64_C(952110080), // LDRSBWpre
4422 UINT64_C(954222592), // LDRSBWroW
4423 UINT64_C(954230784), // LDRSBWroX
4424 UINT64_C(968884224), // LDRSBWui
4425 UINT64_C(947913728), // LDRSBXpost
4426 UINT64_C(947915776), // LDRSBXpre
4427 UINT64_C(950028288), // LDRSBXroW
4428 UINT64_C(950036480), // LDRSBXroX
4429 UINT64_C(964689920), // LDRSBXui
4430 UINT64_C(2025849856), // LDRSHWpost
4431 UINT64_C(2025851904), // LDRSHWpre
4432 UINT64_C(2027964416), // LDRSHWroW
4433 UINT64_C(2027972608), // LDRSHWroX
4434 UINT64_C(2042626048), // LDRSHWui
4435 UINT64_C(2021655552), // LDRSHXpost
4436 UINT64_C(2021657600), // LDRSHXpre
4437 UINT64_C(2023770112), // LDRSHXroW
4438 UINT64_C(2023778304), // LDRSHXroX
4439 UINT64_C(2038431744), // LDRSHXui
4440 UINT64_C(2550136832), // LDRSWl
4441 UINT64_C(3095397376), // LDRSWpost
4442 UINT64_C(3095399424), // LDRSWpre
4443 UINT64_C(3097511936), // LDRSWroW
4444 UINT64_C(3097520128), // LDRSWroX
4445 UINT64_C(3112173568), // LDRSWui
4446 UINT64_C(469762048), // LDRSl
4447 UINT64_C(3158311936), // LDRSpost
4448 UINT64_C(3158313984), // LDRSpre
4449 UINT64_C(3160426496), // LDRSroW
4450 UINT64_C(3160434688), // LDRSroX
4451 UINT64_C(3175088128), // LDRSui
4452 UINT64_C(402653184), // LDRWl
4453 UINT64_C(3091203072), // LDRWpost
4454 UINT64_C(3091205120), // LDRWpre
4455 UINT64_C(3093317632), // LDRWroW
4456 UINT64_C(3093325824), // LDRWroX
4457 UINT64_C(3107979264), // LDRWui
4458 UINT64_C(1476395008), // LDRXl
4459 UINT64_C(4164944896), // LDRXpost
4460 UINT64_C(4164946944), // LDRXpre
4461 UINT64_C(4167059456), // LDRXroW
4462 UINT64_C(4167067648), // LDRXroX
4463 UINT64_C(4181721088), // LDRXui
4464 UINT64_C(2239758336), // LDR_PXI
4465 UINT64_C(3776937984), // LDR_TX
4466 UINT64_C(3774873600), // LDR_ZA
4467 UINT64_C(2239774720), // LDR_ZXI
4468 UINT64_C(950022144), // LDSETAB
4469 UINT64_C(2023763968), // LDSETAH
4470 UINT64_C(954216448), // LDSETALB
4471 UINT64_C(2027958272), // LDSETALH
4472 UINT64_C(3101700096), // LDSETALW
4473 UINT64_C(4175441920), // LDSETALX
4474 UINT64_C(3097505792), // LDSETAW
4475 UINT64_C(4171247616), // LDSETAX
4476 UINT64_C(941633536), // LDSETB
4477 UINT64_C(2015375360), // LDSETH
4478 UINT64_C(945827840), // LDSETLB
4479 UINT64_C(2019569664), // LDSETLH
4480 UINT64_C(3093311488), // LDSETLW
4481 UINT64_C(4167053312), // LDSETLX
4482 UINT64_C(421539840), // LDSETP
4483 UINT64_C(429928448), // LDSETPA
4484 UINT64_C(434122752), // LDSETPAL
4485 UINT64_C(425734144), // LDSETPL
4486 UINT64_C(3089117184), // LDSETW
4487 UINT64_C(4162859008), // LDSETX
4488 UINT64_C(950026240), // LDSMAXAB
4489 UINT64_C(2023768064), // LDSMAXAH
4490 UINT64_C(954220544), // LDSMAXALB
4491 UINT64_C(2027962368), // LDSMAXALH
4492 UINT64_C(3101704192), // LDSMAXALW
4493 UINT64_C(4175446016), // LDSMAXALX
4494 UINT64_C(3097509888), // LDSMAXAW
4495 UINT64_C(4171251712), // LDSMAXAX
4496 UINT64_C(941637632), // LDSMAXB
4497 UINT64_C(2015379456), // LDSMAXH
4498 UINT64_C(945831936), // LDSMAXLB
4499 UINT64_C(2019573760), // LDSMAXLH
4500 UINT64_C(3093315584), // LDSMAXLW
4501 UINT64_C(4167057408), // LDSMAXLX
4502 UINT64_C(3089121280), // LDSMAXW
4503 UINT64_C(4162863104), // LDSMAXX
4504 UINT64_C(950030336), // LDSMINAB
4505 UINT64_C(2023772160), // LDSMINAH
4506 UINT64_C(954224640), // LDSMINALB
4507 UINT64_C(2027966464), // LDSMINALH
4508 UINT64_C(3101708288), // LDSMINALW
4509 UINT64_C(4175450112), // LDSMINALX
4510 UINT64_C(3097513984), // LDSMINAW
4511 UINT64_C(4171255808), // LDSMINAX
4512 UINT64_C(941641728), // LDSMINB
4513 UINT64_C(2015383552), // LDSMINH
4514 UINT64_C(945836032), // LDSMINLB
4515 UINT64_C(2019577856), // LDSMINLH
4516 UINT64_C(3093319680), // LDSMINLW
4517 UINT64_C(4167061504), // LDSMINLX
4518 UINT64_C(3089125376), // LDSMINW
4519 UINT64_C(4162867200), // LDSMINX
4520 UINT64_C(943720448), // LDTRBi
4521 UINT64_C(2017462272), // LDTRHi
4522 UINT64_C(952109056), // LDTRSBWi
4523 UINT64_C(947914752), // LDTRSBXi
4524 UINT64_C(2025850880), // LDTRSHWi
4525 UINT64_C(2021656576), // LDTRSHXi
4526 UINT64_C(3095398400), // LDTRSWi
4527 UINT64_C(3091204096), // LDTRWi
4528 UINT64_C(4164945920), // LDTRXi
4529 UINT64_C(950034432), // LDUMAXAB
4530 UINT64_C(2023776256), // LDUMAXAH
4531 UINT64_C(954228736), // LDUMAXALB
4532 UINT64_C(2027970560), // LDUMAXALH
4533 UINT64_C(3101712384), // LDUMAXALW
4534 UINT64_C(4175454208), // LDUMAXALX
4535 UINT64_C(3097518080), // LDUMAXAW
4536 UINT64_C(4171259904), // LDUMAXAX
4537 UINT64_C(941645824), // LDUMAXB
4538 UINT64_C(2015387648), // LDUMAXH
4539 UINT64_C(945840128), // LDUMAXLB
4540 UINT64_C(2019581952), // LDUMAXLH
4541 UINT64_C(3093323776), // LDUMAXLW
4542 UINT64_C(4167065600), // LDUMAXLX
4543 UINT64_C(3089129472), // LDUMAXW
4544 UINT64_C(4162871296), // LDUMAXX
4545 UINT64_C(950038528), // LDUMINAB
4546 UINT64_C(2023780352), // LDUMINAH
4547 UINT64_C(954232832), // LDUMINALB
4548 UINT64_C(2027974656), // LDUMINALH
4549 UINT64_C(3101716480), // LDUMINALW
4550 UINT64_C(4175458304), // LDUMINALX
4551 UINT64_C(3097522176), // LDUMINAW
4552 UINT64_C(4171264000), // LDUMINAX
4553 UINT64_C(941649920), // LDUMINB
4554 UINT64_C(2015391744), // LDUMINH
4555 UINT64_C(945844224), // LDUMINLB
4556 UINT64_C(2019586048), // LDUMINLH
4557 UINT64_C(3093327872), // LDUMINLW
4558 UINT64_C(4167069696), // LDUMINLX
4559 UINT64_C(3089133568), // LDUMINW
4560 UINT64_C(4162875392), // LDUMINX
4561 UINT64_C(943718400), // LDURBBi
4562 UINT64_C(1010827264), // LDURBi
4563 UINT64_C(4232052736), // LDURDi
4564 UINT64_C(2017460224), // LDURHHi
4565 UINT64_C(2084569088), // LDURHi
4566 UINT64_C(1019215872), // LDURQi
4567 UINT64_C(952107008), // LDURSBWi
4568 UINT64_C(947912704), // LDURSBXi
4569 UINT64_C(2025848832), // LDURSHWi
4570 UINT64_C(2021654528), // LDURSHXi
4571 UINT64_C(3095396352), // LDURSWi
4572 UINT64_C(3158310912), // LDURSi
4573 UINT64_C(3091202048), // LDURWi
4574 UINT64_C(4164943872), // LDURXi
4575 UINT64_C(2287992832), // LDXPW
4576 UINT64_C(3361734656), // LDXPX
4577 UINT64_C(140475392), // LDXRB
4578 UINT64_C(1214217216), // LDXRH
4579 UINT64_C(2287959040), // LDXRW
4580 UINT64_C(3361700864), // LDXRX
4581 UINT64_C(68648960), // LSLR_ZPmZ_B
4582 UINT64_C(81231872), // LSLR_ZPmZ_D
4583 UINT64_C(72843264), // LSLR_ZPmZ_H
4584 UINT64_C(77037568), // LSLR_ZPmZ_S
4585 UINT64_C(448798720), // LSLVWr
4586 UINT64_C(2596282368), // LSLVXr
4587 UINT64_C(68911104), // LSL_WIDE_ZPmZ_B
4588 UINT64_C(73105408), // LSL_WIDE_ZPmZ_H
4589 UINT64_C(77299712), // LSL_WIDE_ZPmZ_S
4590 UINT64_C(69241856), // LSL_WIDE_ZZZ_B
4591 UINT64_C(73436160), // LSL_WIDE_ZZZ_H
4592 UINT64_C(77630464), // LSL_WIDE_ZZZ_S
4593 UINT64_C(67338496), // LSL_ZPmI_B
4594 UINT64_C(75726848), // LSL_ZPmI_D
4595 UINT64_C(67338752), // LSL_ZPmI_H
4596 UINT64_C(71532544), // LSL_ZPmI_S
4597 UINT64_C(68386816), // LSL_ZPmZ_B
4598 UINT64_C(80969728), // LSL_ZPmZ_D
4599 UINT64_C(72581120), // LSL_ZPmZ_H
4600 UINT64_C(76775424), // LSL_ZPmZ_S
4601 UINT64_C(69770240), // LSL_ZZI_B
4602 UINT64_C(77634560), // LSL_ZZI_D
4603 UINT64_C(70294528), // LSL_ZZI_H
4604 UINT64_C(73440256), // LSL_ZZI_S
4605 UINT64_C(68517888), // LSRR_ZPmZ_B
4606 UINT64_C(81100800), // LSRR_ZPmZ_D
4607 UINT64_C(72712192), // LSRR_ZPmZ_H
4608 UINT64_C(76906496), // LSRR_ZPmZ_S
4609 UINT64_C(448799744), // LSRVWr
4610 UINT64_C(2596283392), // LSRVXr
4611 UINT64_C(68780032), // LSR_WIDE_ZPmZ_B
4612 UINT64_C(72974336), // LSR_WIDE_ZPmZ_H
4613 UINT64_C(77168640), // LSR_WIDE_ZPmZ_S
4614 UINT64_C(69239808), // LSR_WIDE_ZZZ_B
4615 UINT64_C(73434112), // LSR_WIDE_ZZZ_H
4616 UINT64_C(77628416), // LSR_WIDE_ZZZ_S
4617 UINT64_C(67207424), // LSR_ZPmI_B
4618 UINT64_C(75595776), // LSR_ZPmI_D
4619 UINT64_C(67207680), // LSR_ZPmI_H
4620 UINT64_C(71401472), // LSR_ZPmI_S
4621 UINT64_C(68255744), // LSR_ZPmZ_B
4622 UINT64_C(80838656), // LSR_ZPmZ_D
4623 UINT64_C(72450048), // LSR_ZPmZ_H
4624 UINT64_C(76644352), // LSR_ZPmZ_S
4625 UINT64_C(69768192), // LSR_ZZI_B
4626 UINT64_C(77632512), // LSR_ZZI_D
4627 UINT64_C(70292480), // LSR_ZZI_H
4628 UINT64_C(73438208), // LSR_ZZI_S
4629 UINT64_C(1317015552), // LUT2v16f8
4630 UINT64_C(1321205760), // LUT2v8f16
4631 UINT64_C(1312825344), // LUT4v16f8
4632 UINT64_C(1312821248), // LUT4v8f16
4633 UINT64_C(3230416896), // LUTI2_2ZTZI_B
4634 UINT64_C(3230420992), // LUTI2_2ZTZI_H
4635 UINT64_C(3230425088), // LUTI2_2ZTZI_S
4636 UINT64_C(3230433280), // LUTI2_4ZTZI_B
4637 UINT64_C(3230437376), // LUTI2_4ZTZI_H
4638 UINT64_C(3230441472), // LUTI2_4ZTZI_S
4639 UINT64_C(3231465472), // LUTI2_S_2ZTZI_B
4640 UINT64_C(3231469568), // LUTI2_S_2ZTZI_H
4641 UINT64_C(3231481856), // LUTI2_S_4ZTZI_B
4642 UINT64_C(3231485952), // LUTI2_S_4ZTZI_H
4643 UINT64_C(3234594816), // LUTI2_ZTZI_B
4644 UINT64_C(3234598912), // LUTI2_ZTZI_H
4645 UINT64_C(3234603008), // LUTI2_ZTZI_S
4646 UINT64_C(1159770112), // LUTI2_ZZZI_B
4647 UINT64_C(1159768064), // LUTI2_ZZZI_H
4648 UINT64_C(3230285824), // LUTI4_2ZTZI_B
4649 UINT64_C(3230289920), // LUTI4_2ZTZI_H
4650 UINT64_C(3230294016), // LUTI4_2ZTZI_S
4651 UINT64_C(3230306304), // LUTI4_4ZTZI_H
4652 UINT64_C(3230310400), // LUTI4_4ZTZI_S
4653 UINT64_C(3230334976), // LUTI4_4ZZT2Z
4654 UINT64_C(3231334400), // LUTI4_S_2ZTZI_B
4655 UINT64_C(3231338496), // LUTI4_S_2ZTZI_H
4656 UINT64_C(3231354880), // LUTI4_S_4ZTZI_H
4657 UINT64_C(3231383552), // LUTI4_S_4ZZT2Z
4658 UINT64_C(1159771136), // LUTI4_Z2ZZI_H
4659 UINT64_C(3234463744), // LUTI4_ZTZI_B
4660 UINT64_C(3234467840), // LUTI4_ZTZI_H
4661 UINT64_C(3234471936), // LUTI4_ZTZI_S
4662 UINT64_C(1163961344), // LUTI4_ZZZI_B
4663 UINT64_C(1159773184), // LUTI4_ZZZI_H
4664 UINT64_C(2606759936), // MADDPT
4665 UINT64_C(452984832), // MADDWrrr
4666 UINT64_C(2600468480), // MADDXrrr
4667 UINT64_C(1153488896), // MAD_CPA
4668 UINT64_C(67158016), // MAD_ZPmZZ_B
4669 UINT64_C(79740928), // MAD_ZPmZZ_D
4670 UINT64_C(71352320), // MAD_ZPmZZ_H
4671 UINT64_C(75546624), // MAD_ZPmZZ_S
4672 UINT64_C(1159757824), // MATCH_PPzZZ_B
4673 UINT64_C(1163952128), // MATCH_PPzZZ_H
4674 UINT64_C(1153486848), // MLA_CPA
4675 UINT64_C(67125248), // MLA_ZPmZZ_B
4676 UINT64_C(79708160), // MLA_ZPmZZ_D
4677 UINT64_C(71319552), // MLA_ZPmZZ_H
4678 UINT64_C(75513856), // MLA_ZPmZZ_S
4679 UINT64_C(1155532800), // MLA_ZZZI_D
4680 UINT64_C(1142949888), // MLA_ZZZI_H
4681 UINT64_C(1151338496), // MLA_ZZZI_S
4682 UINT64_C(1310757888), // MLAv16i8
4683 UINT64_C(245404672), // MLAv2i32
4684 UINT64_C(796917760), // MLAv2i32_indexed
4685 UINT64_C(241210368), // MLAv4i16
4686 UINT64_C(792723456), // MLAv4i16_indexed
4687 UINT64_C(1319146496), // MLAv4i32
4688 UINT64_C(1870659584), // MLAv4i32_indexed
4689 UINT64_C(1314952192), // MLAv8i16
4690 UINT64_C(1866465280), // MLAv8i16_indexed
4691 UINT64_C(237016064), // MLAv8i8
4692 UINT64_C(67133440), // MLS_ZPmZZ_B
4693 UINT64_C(79716352), // MLS_ZPmZZ_D
4694 UINT64_C(71327744), // MLS_ZPmZZ_H
4695 UINT64_C(75522048), // MLS_ZPmZZ_S
4696 UINT64_C(1155533824), // MLS_ZZZI_D
4697 UINT64_C(1142950912), // MLS_ZZZI_H
4698 UINT64_C(1151339520), // MLS_ZZZI_S
4699 UINT64_C(1847628800), // MLSv16i8
4700 UINT64_C(782275584), // MLSv2i32
4701 UINT64_C(796934144), // MLSv2i32_indexed
4702 UINT64_C(778081280), // MLSv4i16
4703 UINT64_C(792739840), // MLSv4i16_indexed
4704 UINT64_C(1856017408), // MLSv4i32
4705 UINT64_C(1870675968), // MLSv4i32_indexed
4706 UINT64_C(1851823104), // MLSv8i16
4707 UINT64_C(1866481664), // MLSv8i16_indexed
4708 UINT64_C(773886976), // MLSv8i8
4709 UINT64_C(499155968), // MOPSSETGE
4710 UINT64_C(499164160), // MOPSSETGEN
4711 UINT64_C(499160064), // MOPSSETGET
4712 UINT64_C(499168256), // MOPSSETGETN
4713 UINT64_C(3221619200), // MOVAZ_2ZMI_H_B
4714 UINT64_C(3234202112), // MOVAZ_2ZMI_H_D
4715 UINT64_C(3225813504), // MOVAZ_2ZMI_H_H
4716 UINT64_C(3230007808), // MOVAZ_2ZMI_H_S
4717 UINT64_C(3221651968), // MOVAZ_2ZMI_V_B
4718 UINT64_C(3234234880), // MOVAZ_2ZMI_V_D
4719 UINT64_C(3225846272), // MOVAZ_2ZMI_V_H
4720 UINT64_C(3230040576), // MOVAZ_2ZMI_V_S
4721 UINT64_C(3221620224), // MOVAZ_4ZMI_H_B
4722 UINT64_C(3234203136), // MOVAZ_4ZMI_H_D
4723 UINT64_C(3225814528), // MOVAZ_4ZMI_H_H
4724 UINT64_C(3230008832), // MOVAZ_4ZMI_H_S
4725 UINT64_C(3221652992), // MOVAZ_4ZMI_V_B
4726 UINT64_C(3234235904), // MOVAZ_4ZMI_V_D
4727 UINT64_C(3225847296), // MOVAZ_4ZMI_V_H
4728 UINT64_C(3230041600), // MOVAZ_4ZMI_V_S
4729 UINT64_C(3221621248), // MOVAZ_VG2_2ZMXI
4730 UINT64_C(3221622272), // MOVAZ_VG4_4ZMXI
4731 UINT64_C(3221357056), // MOVAZ_ZMI_H_B
4732 UINT64_C(3233939968), // MOVAZ_ZMI_H_D
4733 UINT64_C(3225551360), // MOVAZ_ZMI_H_H
4734 UINT64_C(3234005504), // MOVAZ_ZMI_H_Q
4735 UINT64_C(3229745664), // MOVAZ_ZMI_H_S
4736 UINT64_C(3221389824), // MOVAZ_ZMI_V_B
4737 UINT64_C(3233972736), // MOVAZ_ZMI_V_D
4738 UINT64_C(3225584128), // MOVAZ_ZMI_V_H
4739 UINT64_C(3234038272), // MOVAZ_ZMI_V_Q
4740 UINT64_C(3229778432), // MOVAZ_ZMI_V_S
4741 UINT64_C(3221618688), // MOVA_2ZMXI_H_B
4742 UINT64_C(3234201600), // MOVA_2ZMXI_H_D
4743 UINT64_C(3225812992), // MOVA_2ZMXI_H_H
4744 UINT64_C(3230007296), // MOVA_2ZMXI_H_S
4745 UINT64_C(3221651456), // MOVA_2ZMXI_V_B
4746 UINT64_C(3234234368), // MOVA_2ZMXI_V_D
4747 UINT64_C(3225845760), // MOVA_2ZMXI_V_H
4748 UINT64_C(3230040064), // MOVA_2ZMXI_V_S
4749 UINT64_C(3221619712), // MOVA_4ZMXI_H_B
4750 UINT64_C(3234202624), // MOVA_4ZMXI_H_D
4751 UINT64_C(3225814016), // MOVA_4ZMXI_H_H
4752 UINT64_C(3230008320), // MOVA_4ZMXI_H_S
4753 UINT64_C(3221652480), // MOVA_4ZMXI_V_B
4754 UINT64_C(3234235392), // MOVA_4ZMXI_V_D
4755 UINT64_C(3225846784), // MOVA_4ZMXI_V_H
4756 UINT64_C(3230041088), // MOVA_4ZMXI_V_S
4757 UINT64_C(3221487616), // MOVA_MXI2Z_H_B
4758 UINT64_C(3234070528), // MOVA_MXI2Z_H_D
4759 UINT64_C(3225681920), // MOVA_MXI2Z_H_H
4760 UINT64_C(3229876224), // MOVA_MXI2Z_H_S
4761 UINT64_C(3221520384), // MOVA_MXI2Z_V_B
4762 UINT64_C(3234103296), // MOVA_MXI2Z_V_D
4763 UINT64_C(3225714688), // MOVA_MXI2Z_V_H
4764 UINT64_C(3229908992), // MOVA_MXI2Z_V_S
4765 UINT64_C(3221488640), // MOVA_MXI4Z_H_B
4766 UINT64_C(3234071552), // MOVA_MXI4Z_H_D
4767 UINT64_C(3225682944), // MOVA_MXI4Z_H_H
4768 UINT64_C(3229877248), // MOVA_MXI4Z_H_S
4769 UINT64_C(3221521408), // MOVA_MXI4Z_V_B
4770 UINT64_C(3234104320), // MOVA_MXI4Z_V_D
4771 UINT64_C(3225715712), // MOVA_MXI4Z_V_H
4772 UINT64_C(3229910016), // MOVA_MXI4Z_V_S
4773 UINT64_C(3221620736), // MOVA_VG2_2ZMXI
4774 UINT64_C(3221489664), // MOVA_VG2_MXI2Z
4775 UINT64_C(3221621760), // MOVA_VG4_4ZMXI
4776 UINT64_C(3221490688), // MOVA_VG4_MXI4Z
4777 UINT64_C(788587520), // MOVID
4778 UINT64_C(1325458432), // MOVIv16b_ns
4779 UINT64_C(1862329344), // MOVIv2d_ns
4780 UINT64_C(251659264), // MOVIv2i32
4781 UINT64_C(251708416), // MOVIv2s_msl
4782 UINT64_C(251692032), // MOVIv4i16
4783 UINT64_C(1325401088), // MOVIv4i32
4784 UINT64_C(1325450240), // MOVIv4s_msl
4785 UINT64_C(251716608), // MOVIv8b_ns
4786 UINT64_C(1325433856), // MOVIv8i16
4787 UINT64_C(1920991232), // MOVKWi
4788 UINT64_C(4068474880), // MOVKXi
4789 UINT64_C(310378496), // MOVNWi
4790 UINT64_C(2457862144), // MOVNXi
4791 UINT64_C(68231168), // MOVPRFX_ZPmZ_B
4792 UINT64_C(80814080), // MOVPRFX_ZPmZ_D
4793 UINT64_C(72425472), // MOVPRFX_ZPmZ_H
4794 UINT64_C(76619776), // MOVPRFX_ZPmZ_S
4795 UINT64_C(68165632), // MOVPRFX_ZPzZ_B
4796 UINT64_C(80748544), // MOVPRFX_ZPzZ_D
4797 UINT64_C(72359936), // MOVPRFX_ZPzZ_H
4798 UINT64_C(76554240), // MOVPRFX_ZPzZ_S
4799 UINT64_C(69254144), // MOVPRFX_ZZ
4800 UINT64_C(3226403808), // MOVT
4801 UINT64_C(3226338272), // MOVT_TIX
4802 UINT64_C(3226207200), // MOVT_XTI
4803 UINT64_C(1384120320), // MOVZWi
4804 UINT64_C(3531603968), // MOVZXi
4805 UINT64_C(3579838464), // MRRS
4806 UINT64_C(3575644160), // MRS
4807 UINT64_C(67166208), // MSB_ZPmZZ_B
4808 UINT64_C(79749120), // MSB_ZPmZZ_D
4809 UINT64_C(71360512), // MSB_ZPmZZ_H
4810 UINT64_C(75554816), // MSB_ZPmZZ_S
4811 UINT64_C(3573547008), // MSR
4812 UINT64_C(3577741312), // MSRR
4813 UINT64_C(3573563423), // MSRpstateImm1
4814 UINT64_C(3573563423), // MSRpstateImm4
4815 UINT64_C(3573760127), // MSRpstatesvcrImm1
4816 UINT64_C(2606792704), // MSUBPT
4817 UINT64_C(453017600), // MSUBWrrr
4818 UINT64_C(2600501248), // MSUBXrrr
4819 UINT64_C(623951872), // MUL_ZI_B
4820 UINT64_C(636534784), // MUL_ZI_D
4821 UINT64_C(628146176), // MUL_ZI_H
4822 UINT64_C(632340480), // MUL_ZI_S
4823 UINT64_C(68157440), // MUL_ZPmZ_B
4824 UINT64_C(80740352), // MUL_ZPmZ_D
4825 UINT64_C(72351744), // MUL_ZPmZ_H
4826 UINT64_C(76546048), // MUL_ZPmZ_S
4827 UINT64_C(1155594240), // MUL_ZZZI_D
4828 UINT64_C(1143011328), // MUL_ZZZI_H
4829 UINT64_C(1151399936), // MUL_ZZZI_S
4830 UINT64_C(69230592), // MUL_ZZZ_B
4831 UINT64_C(81813504), // MUL_ZZZ_D
4832 UINT64_C(73424896), // MUL_ZZZ_H
4833 UINT64_C(77619200), // MUL_ZZZ_S
4834 UINT64_C(1310759936), // MULv16i8
4835 UINT64_C(245406720), // MULv2i32
4836 UINT64_C(260079616), // MULv2i32_indexed
4837 UINT64_C(241212416), // MULv4i16
4838 UINT64_C(255885312), // MULv4i16_indexed
4839 UINT64_C(1319148544), // MULv4i32
4840 UINT64_C(1333821440), // MULv4i32_indexed
4841 UINT64_C(1314954240), // MULv8i16
4842 UINT64_C(1329627136), // MULv8i16_indexed
4843 UINT64_C(237018112), // MULv8i8
4844 UINT64_C(788530176), // MVNIv2i32
4845 UINT64_C(788579328), // MVNIv2s_msl
4846 UINT64_C(788562944), // MVNIv4i16
4847 UINT64_C(1862272000), // MVNIv4i32
4848 UINT64_C(1862321152), // MVNIv4s_msl
4849 UINT64_C(1862304768), // MVNIv8i16
4850 UINT64_C(633356816), // NANDS_PPzPP
4851 UINT64_C(629162512), // NAND_PPzPP
4852 UINT64_C(81804288), // NBSL_ZZZZ
4853 UINT64_C(68657152), // NEG_ZPmZ_B
4854 UINT64_C(81240064), // NEG_ZPmZ_D
4855 UINT64_C(72851456), // NEG_ZPmZ_H
4856 UINT64_C(77045760), // NEG_ZPmZ_S
4857 UINT64_C(1847638016), // NEGv16i8
4858 UINT64_C(2128656384), // NEGv1i64
4859 UINT64_C(782284800), // NEGv2i32
4860 UINT64_C(1860220928), // NEGv2i64
4861 UINT64_C(778090496), // NEGv4i16
4862 UINT64_C(1856026624), // NEGv4i32
4863 UINT64_C(1851832320), // NEGv8i16
4864 UINT64_C(773896192), // NEGv8i8
4865 UINT64_C(1159757840), // NMATCH_PPzZZ_B
4866 UINT64_C(1163952144), // NMATCH_PPzZZ_H
4867 UINT64_C(633356800), // NORS_PPzPP
4868 UINT64_C(629162496), // NOR_PPzPP
4869 UINT64_C(69115904), // NOT_ZPmZ_B
4870 UINT64_C(81698816), // NOT_ZPmZ_D
4871 UINT64_C(73310208), // NOT_ZPmZ_H
4872 UINT64_C(77504512), // NOT_ZPmZ_S
4873 UINT64_C(1847613440), // NOTv16i8
4874 UINT64_C(773871616), // NOTv8i8
4875 UINT64_C(633356304), // ORNS_PPzPP
4876 UINT64_C(706740224), // ORNWrs
4877 UINT64_C(2854223872), // ORNXrs
4878 UINT64_C(629162000), // ORN_PPzPP
4879 UINT64_C(1323310080), // ORNv16i8
4880 UINT64_C(249568256), // ORNv8i8
4881 UINT64_C(68952064), // ORQV_VPZ_B
4882 UINT64_C(81534976), // ORQV_VPZ_D
4883 UINT64_C(73146368), // ORQV_VPZ_H
4884 UINT64_C(77340672), // ORQV_VPZ_S
4885 UINT64_C(633356288), // ORRS_PPzPP
4886 UINT64_C(838860800), // ORRWri
4887 UINT64_C(704643072), // ORRWrs
4888 UINT64_C(2986344448), // ORRXri
4889 UINT64_C(2852126720), // ORRXrs
4890 UINT64_C(629161984), // ORR_PPzPP
4891 UINT64_C(83886080), // ORR_ZI
4892 UINT64_C(68681728), // ORR_ZPmZ_B
4893 UINT64_C(81264640), // ORR_ZPmZ_D
4894 UINT64_C(72876032), // ORR_ZPmZ_H
4895 UINT64_C(77070336), // ORR_ZPmZ_S
4896 UINT64_C(73412608), // ORR_ZZZ
4897 UINT64_C(1319115776), // ORRv16i8
4898 UINT64_C(251663360), // ORRv2i32
4899 UINT64_C(251696128), // ORRv4i16
4900 UINT64_C(1325405184), // ORRv4i32
4901 UINT64_C(1325437952), // ORRv8i16
4902 UINT64_C(245373952), // ORRv8i8
4903 UINT64_C(68689920), // ORV_VPZ_B
4904 UINT64_C(81272832), // ORV_VPZ_D
4905 UINT64_C(72884224), // ORV_VPZ_H
4906 UINT64_C(77078528), // ORV_VPZ_S
4907 UINT64_C(3670083584), // PACDA
4908 UINT64_C(3670084608), // PACDB
4909 UINT64_C(3670092768), // PACDZA
4910 UINT64_C(3670093792), // PACDZB
4911 UINT64_C(2596286464), // PACGA
4912 UINT64_C(3670081536), // PACIA
4913 UINT64_C(3573752095), // PACIA1716
4914 UINT64_C(3670117374), // PACIA171615
4915 UINT64_C(3573752639), // PACIASP
4916 UINT64_C(3670123518), // PACIASPPC
4917 UINT64_C(3573752607), // PACIAZ
4918 UINT64_C(3670082560), // PACIB
4919 UINT64_C(3573752159), // PACIB1716
4920 UINT64_C(3670118398), // PACIB171615
4921 UINT64_C(3573752703), // PACIBSP
4922 UINT64_C(3670124542), // PACIBSPPC
4923 UINT64_C(3573752671), // PACIBZ
4924 UINT64_C(3670090720), // PACIZA
4925 UINT64_C(3670091744), // PACIZB
4926 UINT64_C(3573753087), // PACM
4927 UINT64_C(3670115326), // PACNBIASPPC
4928 UINT64_C(3670116350), // PACNBIBSPPC
4929 UINT64_C(622883856), // PEXT_2PCI_B
4930 UINT64_C(635466768), // PEXT_2PCI_D
4931 UINT64_C(627078160), // PEXT_2PCI_H
4932 UINT64_C(631272464), // PEXT_2PCI_S
4933 UINT64_C(622882832), // PEXT_PCI_B
4934 UINT64_C(635465744), // PEXT_PCI_D
4935 UINT64_C(627077136), // PEXT_PCI_H
4936 UINT64_C(631271440), // PEXT_PCI_S
4937 UINT64_C(622388224), // PFALSE
4938 UINT64_C(626573312), // PFIRST_B
4939 UINT64_C(86652928), // PMOV_PZI_B
4940 UINT64_C(94910464), // PMOV_PZI_D
4941 UINT64_C(86784000), // PMOV_PZI_H
4942 UINT64_C(90716160), // PMOV_PZI_S
4943 UINT64_C(86718464), // PMOV_ZIP_B
4944 UINT64_C(94976000), // PMOV_ZIP_D
4945 UINT64_C(86849536), // PMOV_ZIP_H
4946 UINT64_C(90781696), // PMOV_ZIP_S
4947 UINT64_C(1170237440), // PMULLB_ZZZ_D
4948 UINT64_C(1161848832), // PMULLB_ZZZ_H
4949 UINT64_C(1157654528), // PMULLB_ZZZ_Q
4950 UINT64_C(1170238464), // PMULLT_ZZZ_D
4951 UINT64_C(1161849856), // PMULLT_ZZZ_H
4952 UINT64_C(1157655552), // PMULLT_ZZZ_Q
4953 UINT64_C(1310777344), // PMULLv16i8
4954 UINT64_C(249618432), // PMULLv1i64
4955 UINT64_C(1323360256), // PMULLv2i64
4956 UINT64_C(237035520), // PMULLv8i8
4957 UINT64_C(69231616), // PMUL_ZZZ_B
4958 UINT64_C(1847630848), // PMULv16i8
4959 UINT64_C(773889024), // PMULv8i8
4960 UINT64_C(622445568), // PNEXT_B
4961 UINT64_C(635028480), // PNEXT_D
4962 UINT64_C(626639872), // PNEXT_H
4963 UINT64_C(630834176), // PNEXT_S
4964 UINT64_C(3288391680), // PRFB_D_PZI
4965 UINT64_C(3294658560), // PRFB_D_SCALED
4966 UINT64_C(3294625792), // PRFB_D_SXTW_SCALED
4967 UINT64_C(3290431488), // PRFB_D_UXTW_SCALED
4968 UINT64_C(2243952640), // PRFB_PRI
4969 UINT64_C(2214641664), // PRFB_PRR
4970 UINT64_C(2214649856), // PRFB_S_PZI
4971 UINT64_C(2220883968), // PRFB_S_SXTW_SCALED
4972 UINT64_C(2216689664), // PRFB_S_UXTW_SCALED
4973 UINT64_C(3313557504), // PRFD_D_PZI
4974 UINT64_C(3294683136), // PRFD_D_SCALED
4975 UINT64_C(3294650368), // PRFD_D_SXTW_SCALED
4976 UINT64_C(3290456064), // PRFD_D_UXTW_SCALED
4977 UINT64_C(2243977216), // PRFD_PRI
4978 UINT64_C(2239807488), // PRFD_PRR
4979 UINT64_C(2239815680), // PRFD_S_PZI
4980 UINT64_C(2220908544), // PRFD_S_SXTW_SCALED
4981 UINT64_C(2216714240), // PRFD_S_UXTW_SCALED
4982 UINT64_C(3296780288), // PRFH_D_PZI
4983 UINT64_C(3294666752), // PRFH_D_SCALED
4984 UINT64_C(3294633984), // PRFH_D_SXTW_SCALED
4985 UINT64_C(3290439680), // PRFH_D_UXTW_SCALED
4986 UINT64_C(2243960832), // PRFH_PRI
4987 UINT64_C(2223030272), // PRFH_PRR
4988 UINT64_C(2223038464), // PRFH_S_PZI
4989 UINT64_C(2220892160), // PRFH_S_SXTW_SCALED
4990 UINT64_C(2216697856), // PRFH_S_UXTW_SCALED
4991 UINT64_C(3623878656), // PRFMl
4992 UINT64_C(4171253760), // PRFMroW
4993 UINT64_C(4171261952), // PRFMroX
4994 UINT64_C(4185915392), // PRFMui
4995 UINT64_C(4169138176), // PRFUMi
4996 UINT64_C(3305168896), // PRFW_D_PZI
4997 UINT64_C(3294674944), // PRFW_D_SCALED
4998 UINT64_C(3294642176), // PRFW_D_SXTW_SCALED
4999 UINT64_C(3290447872), // PRFW_D_UXTW_SCALED
5000 UINT64_C(2243969024), // PRFW_PRI
5001 UINT64_C(2231418880), // PRFW_PRR
5002 UINT64_C(2231427072), // PRFW_S_PZI
5003 UINT64_C(2220900352), // PRFW_S_SXTW_SCALED
5004 UINT64_C(2216706048), // PRFW_S_UXTW_SCALED
5005 UINT64_C(623132672), // PSEL_PPPRI_B
5006 UINT64_C(627064832), // PSEL_PPPRI_D
5007 UINT64_C(623394816), // PSEL_PPPRI_H
5008 UINT64_C(623919104), // PSEL_PPPRI_S
5009 UINT64_C(626049024), // PTEST_PP
5010 UINT64_C(622452736), // PTRUES_B
5011 UINT64_C(635035648), // PTRUES_D
5012 UINT64_C(626647040), // PTRUES_H
5013 UINT64_C(630841344), // PTRUES_S
5014 UINT64_C(622387200), // PTRUE_B
5015 UINT64_C(622884880), // PTRUE_C_B
5016 UINT64_C(635467792), // PTRUE_C_D
5017 UINT64_C(627079184), // PTRUE_C_H
5018 UINT64_C(631273488), // PTRUE_C_S
5019 UINT64_C(634970112), // PTRUE_D
5020 UINT64_C(626581504), // PTRUE_H
5021 UINT64_C(630775808), // PTRUE_S
5022 UINT64_C(87113728), // PUNPKHI_PP
5023 UINT64_C(87048192), // PUNPKLO_PP
5024 UINT64_C(1163945984), // RADDHNB_ZZZ_B
5025 UINT64_C(1168140288), // RADDHNB_ZZZ_H
5026 UINT64_C(1172334592), // RADDHNB_ZZZ_S
5027 UINT64_C(1163947008), // RADDHNT_ZZZ_B
5028 UINT64_C(1168141312), // RADDHNT_ZZZ_H
5029 UINT64_C(1172335616), // RADDHNT_ZZZ_S
5030 UINT64_C(782254080), // RADDHNv2i64_v2i32
5031 UINT64_C(1855995904), // RADDHNv2i64_v4i32
5032 UINT64_C(778059776), // RADDHNv4i32_v4i16
5033 UINT64_C(1851801600), // RADDHNv4i32_v8i16
5034 UINT64_C(1847607296), // RADDHNv8i16_v16i8
5035 UINT64_C(773865472), // RADDHNv8i16_v8i8
5036 UINT64_C(3462433792), // RAX1
5037 UINT64_C(1159787520), // RAX1_ZZZ_D
5038 UINT64_C(1522532352), // RBITWr
5039 UINT64_C(3670016000), // RBITXr
5040 UINT64_C(86474752), // RBIT_ZPmZ_B
5041 UINT64_C(99057664), // RBIT_ZPmZ_D
5042 UINT64_C(90669056), // RBIT_ZPmZ_H
5043 UINT64_C(94863360), // RBIT_ZPmZ_S
5044 UINT64_C(1851807744), // RBITv16i8
5045 UINT64_C(778065920), // RBITv8i8
5046 UINT64_C(421529600), // RCWCAS
5047 UINT64_C(429918208), // RCWCASA
5048 UINT64_C(434112512), // RCWCASAL
5049 UINT64_C(425723904), // RCWCASL
5050 UINT64_C(421530624), // RCWCASP
5051 UINT64_C(429919232), // RCWCASPA
5052 UINT64_C(434113536), // RCWCASPAL
5053 UINT64_C(425724928), // RCWCASPL
5054 UINT64_C(941658112), // RCWCLR
5055 UINT64_C(950046720), // RCWCLRA
5056 UINT64_C(954241024), // RCWCLRAL
5057 UINT64_C(945852416), // RCWCLRL
5058 UINT64_C(421564416), // RCWCLRP
5059 UINT64_C(429953024), // RCWCLRPA
5060 UINT64_C(434147328), // RCWCLRPAL
5061 UINT64_C(425758720), // RCWCLRPL
5062 UINT64_C(2015399936), // RCWCLRS
5063 UINT64_C(2023788544), // RCWCLRSA
5064 UINT64_C(2027982848), // RCWCLRSAL
5065 UINT64_C(2019594240), // RCWCLRSL
5066 UINT64_C(1495306240), // RCWCLRSP
5067 UINT64_C(1503694848), // RCWCLRSPA
5068 UINT64_C(1507889152), // RCWCLRSPAL
5069 UINT64_C(1499500544), // RCWCLRSPL
5070 UINT64_C(1495271424), // RCWSCAS
5071 UINT64_C(1503660032), // RCWSCASA
5072 UINT64_C(1507854336), // RCWSCASAL
5073 UINT64_C(1499465728), // RCWSCASL
5074 UINT64_C(1495272448), // RCWSCASP
5075 UINT64_C(1503661056), // RCWSCASPA
5076 UINT64_C(1507855360), // RCWSCASPAL
5077 UINT64_C(1499466752), // RCWSCASPL
5078 UINT64_C(941666304), // RCWSET
5079 UINT64_C(950054912), // RCWSETA
5080 UINT64_C(954249216), // RCWSETAL
5081 UINT64_C(945860608), // RCWSETL
5082 UINT64_C(421572608), // RCWSETP
5083 UINT64_C(429961216), // RCWSETPA
5084 UINT64_C(434155520), // RCWSETPAL
5085 UINT64_C(425766912), // RCWSETPL
5086 UINT64_C(2015408128), // RCWSETS
5087 UINT64_C(2023796736), // RCWSETSA
5088 UINT64_C(2027991040), // RCWSETSAL
5089 UINT64_C(2019602432), // RCWSETSL
5090 UINT64_C(1495314432), // RCWSETSP
5091 UINT64_C(1503703040), // RCWSETSPA
5092 UINT64_C(1507897344), // RCWSETSPAL
5093 UINT64_C(1499508736), // RCWSETSPL
5094 UINT64_C(941662208), // RCWSWP
5095 UINT64_C(950050816), // RCWSWPA
5096 UINT64_C(954245120), // RCWSWPAL
5097 UINT64_C(945856512), // RCWSWPL
5098 UINT64_C(421568512), // RCWSWPP
5099 UINT64_C(429957120), // RCWSWPPA
5100 UINT64_C(434151424), // RCWSWPPAL
5101 UINT64_C(425762816), // RCWSWPPL
5102 UINT64_C(2015404032), // RCWSWPS
5103 UINT64_C(2023792640), // RCWSWPSA
5104 UINT64_C(2027986944), // RCWSWPSAL
5105 UINT64_C(2019598336), // RCWSWPSL
5106 UINT64_C(1495310336), // RCWSWPSP
5107 UINT64_C(1503698944), // RCWSWPSPA
5108 UINT64_C(1507893248), // RCWSWPSPAL
5109 UINT64_C(1499504640), // RCWSWPSPL
5110 UINT64_C(626585600), // RDFFRS_PPz
5111 UINT64_C(622456832), // RDFFR_P
5112 UINT64_C(622391296), // RDFFR_PPz
5113 UINT64_C(79648768), // RDSVLI_XI
5114 UINT64_C(79646720), // RDVLI_XI
5115 UINT64_C(3596550144), // RET
5116 UINT64_C(3596553215), // RETAA
5117 UINT64_C(1426063391), // RETAASPPCi
5118 UINT64_C(3596553184), // RETAASPPCr
5119 UINT64_C(3596554239), // RETAB
5120 UINT64_C(1428160543), // RETABSPPCi
5121 UINT64_C(3596554208), // RETABSPPCr
5122 UINT64_C(1522533376), // REV16Wr
5123 UINT64_C(3670017024), // REV16Xr
5124 UINT64_C(1310726144), // REV16v16i8
5125 UINT64_C(236984320), // REV16v8i8
5126 UINT64_C(3670018048), // REV32Xr
5127 UINT64_C(1847592960), // REV32v16i8
5128 UINT64_C(778045440), // REV32v4i16
5129 UINT64_C(1851787264), // REV32v8i16
5130 UINT64_C(773851136), // REV32v8i8
5131 UINT64_C(1310722048), // REV64v16i8
5132 UINT64_C(245368832), // REV64v2i32
5133 UINT64_C(241174528), // REV64v4i16
5134 UINT64_C(1319110656), // REV64v4i32
5135 UINT64_C(1314916352), // REV64v8i16
5136 UINT64_C(236980224), // REV64v8i8
5137 UINT64_C(98861056), // REVB_ZPmZ_D
5138 UINT64_C(90472448), // REVB_ZPmZ_H
5139 UINT64_C(94666752), // REVB_ZPmZ_S
5140 UINT64_C(86933504), // REVD_ZPmZ
5141 UINT64_C(98926592), // REVH_ZPmZ_D
5142 UINT64_C(94732288), // REVH_ZPmZ_S
5143 UINT64_C(98992128), // REVW_ZPmZ_D
5144 UINT64_C(1522534400), // REVWr
5145 UINT64_C(3670019072), // REVXr
5146 UINT64_C(87310336), // REV_PP_B
5147 UINT64_C(99893248), // REV_PP_D
5148 UINT64_C(91504640), // REV_PP_H
5149 UINT64_C(95698944), // REV_PP_S
5150 UINT64_C(87570432), // REV_ZZ_B
5151 UINT64_C(100153344), // REV_ZZ_D
5152 UINT64_C(91764736), // REV_ZZ_H
5153 UINT64_C(95959040), // REV_ZZ_S
5154 UINT64_C(3120563200), // RMIF
5155 UINT64_C(448801792), // RORVWr
5156 UINT64_C(2596285440), // RORVXr
5157 UINT64_C(4171253784), // RPRFM
5158 UINT64_C(1160255488), // RSHRNB_ZZI_B
5159 UINT64_C(1160779776), // RSHRNB_ZZI_H
5160 UINT64_C(1163925504), // RSHRNB_ZZI_S
5161 UINT64_C(1160256512), // RSHRNT_ZZI_B
5162 UINT64_C(1160780800), // RSHRNT_ZZI_H
5163 UINT64_C(1163926528), // RSHRNT_ZZI_S
5164 UINT64_C(1325960192), // RSHRNv16i8_shift
5165 UINT64_C(253791232), // RSHRNv2i32_shift
5166 UINT64_C(252742656), // RSHRNv4i16_shift
5167 UINT64_C(1327533056), // RSHRNv4i32_shift
5168 UINT64_C(1326484480), // RSHRNv8i16_shift
5169 UINT64_C(252218368), // RSHRNv8i8_shift
5170 UINT64_C(1163950080), // RSUBHNB_ZZZ_B
5171 UINT64_C(1168144384), // RSUBHNB_ZZZ_H
5172 UINT64_C(1172338688), // RSUBHNB_ZZZ_S
5173 UINT64_C(1163951104), // RSUBHNT_ZZZ_B
5174 UINT64_C(1168145408), // RSUBHNT_ZZZ_H
5175 UINT64_C(1172339712), // RSUBHNT_ZZZ_S
5176 UINT64_C(782262272), // RSUBHNv2i64_v2i32
5177 UINT64_C(1856004096), // RSUBHNv2i64_v4i32
5178 UINT64_C(778067968), // RSUBHNv4i32_v4i16
5179 UINT64_C(1851809792), // RSUBHNv4i32_v8i16
5180 UINT64_C(1847615488), // RSUBHNv8i16_v16i8
5181 UINT64_C(773873664), // RSUBHNv8i16_v8i8
5182 UINT64_C(1170259968), // SABALB_ZZZ_D
5183 UINT64_C(1161871360), // SABALB_ZZZ_H
5184 UINT64_C(1166065664), // SABALB_ZZZ_S
5185 UINT64_C(1170260992), // SABALT_ZZZ_D
5186 UINT64_C(1161872384), // SABALT_ZZZ_H
5187 UINT64_C(1166066688), // SABALT_ZZZ_S
5188 UINT64_C(1310740480), // SABALv16i8_v8i16
5189 UINT64_C(245387264), // SABALv2i32_v2i64
5190 UINT64_C(241192960), // SABALv4i16_v4i32
5191 UINT64_C(1319129088), // SABALv4i32_v2i64
5192 UINT64_C(1314934784), // SABALv8i16_v4i32
5193 UINT64_C(236998656), // SABALv8i8_v8i16
5194 UINT64_C(1157691392), // SABA_ZZZ_B
5195 UINT64_C(1170274304), // SABA_ZZZ_D
5196 UINT64_C(1161885696), // SABA_ZZZ_H
5197 UINT64_C(1166080000), // SABA_ZZZ_S
5198 UINT64_C(1310751744), // SABAv16i8
5199 UINT64_C(245398528), // SABAv2i32
5200 UINT64_C(241204224), // SABAv4i16
5201 UINT64_C(1319140352), // SABAv4i32
5202 UINT64_C(1314946048), // SABAv8i16
5203 UINT64_C(237009920), // SABAv8i8
5204 UINT64_C(1170223104), // SABDLB_ZZZ_D
5205 UINT64_C(1161834496), // SABDLB_ZZZ_H
5206 UINT64_C(1166028800), // SABDLB_ZZZ_S
5207 UINT64_C(1170224128), // SABDLT_ZZZ_D
5208 UINT64_C(1161835520), // SABDLT_ZZZ_H
5209 UINT64_C(1166029824), // SABDLT_ZZZ_S
5210 UINT64_C(1310748672), // SABDLv16i8_v8i16
5211 UINT64_C(245395456), // SABDLv2i32_v2i64
5212 UINT64_C(241201152), // SABDLv4i16_v4i32
5213 UINT64_C(1319137280), // SABDLv4i32_v2i64
5214 UINT64_C(1314942976), // SABDLv8i16_v4i32
5215 UINT64_C(237006848), // SABDLv8i8_v8i16
5216 UINT64_C(67895296), // SABD_ZPmZ_B
5217 UINT64_C(80478208), // SABD_ZPmZ_D
5218 UINT64_C(72089600), // SABD_ZPmZ_H
5219 UINT64_C(76283904), // SABD_ZPmZ_S
5220 UINT64_C(1310749696), // SABDv16i8
5221 UINT64_C(245396480), // SABDv2i32
5222 UINT64_C(241202176), // SABDv4i16
5223 UINT64_C(1319138304), // SABDv4i32
5224 UINT64_C(1314944000), // SABDv8i16
5225 UINT64_C(237007872), // SABDv8i8
5226 UINT64_C(1153736704), // SADALP_ZPmZ_D
5227 UINT64_C(1145348096), // SADALP_ZPmZ_H
5228 UINT64_C(1149542400), // SADALP_ZPmZ_S
5229 UINT64_C(1310746624), // SADALPv16i8_v8i16
5230 UINT64_C(245393408), // SADALPv2i32_v1i64
5231 UINT64_C(241199104), // SADALPv4i16_v2i32
5232 UINT64_C(1319135232), // SADALPv4i32_v2i64
5233 UINT64_C(1314940928), // SADALPv8i16_v4i32
5234 UINT64_C(237004800), // SADALPv8i8_v4i16
5235 UINT64_C(1170243584), // SADDLBT_ZZZ_D
5236 UINT64_C(1161854976), // SADDLBT_ZZZ_H
5237 UINT64_C(1166049280), // SADDLBT_ZZZ_S
5238 UINT64_C(1170210816), // SADDLB_ZZZ_D
5239 UINT64_C(1161822208), // SADDLB_ZZZ_H
5240 UINT64_C(1166016512), // SADDLB_ZZZ_S
5241 UINT64_C(1310730240), // SADDLPv16i8_v8i16
5242 UINT64_C(245377024), // SADDLPv2i32_v1i64
5243 UINT64_C(241182720), // SADDLPv4i16_v2i32
5244 UINT64_C(1319118848), // SADDLPv4i32_v2i64
5245 UINT64_C(1314924544), // SADDLPv8i16_v4i32
5246 UINT64_C(236988416), // SADDLPv8i8_v4i16
5247 UINT64_C(1170211840), // SADDLT_ZZZ_D
5248 UINT64_C(1161823232), // SADDLT_ZZZ_H
5249 UINT64_C(1166017536), // SADDLT_ZZZ_S
5250 UINT64_C(1311782912), // SADDLVv16i8v
5251 UINT64_C(242235392), // SADDLVv4i16v
5252 UINT64_C(1320171520), // SADDLVv4i32v
5253 UINT64_C(1315977216), // SADDLVv8i16v
5254 UINT64_C(238041088), // SADDLVv8i8v
5255 UINT64_C(1310720000), // SADDLv16i8_v8i16
5256 UINT64_C(245366784), // SADDLv2i32_v2i64
5257 UINT64_C(241172480), // SADDLv4i16_v4i32
5258 UINT64_C(1319108608), // SADDLv4i32_v2i64
5259 UINT64_C(1314914304), // SADDLv8i16_v4i32
5260 UINT64_C(236978176), // SADDLv8i8_v8i16
5261 UINT64_C(67117056), // SADDV_VPZ_B
5262 UINT64_C(71311360), // SADDV_VPZ_H
5263 UINT64_C(75505664), // SADDV_VPZ_S
5264 UINT64_C(1170227200), // SADDWB_ZZZ_D
5265 UINT64_C(1161838592), // SADDWB_ZZZ_H
5266 UINT64_C(1166032896), // SADDWB_ZZZ_S
5267 UINT64_C(1170228224), // SADDWT_ZZZ_D
5268 UINT64_C(1161839616), // SADDWT_ZZZ_H
5269 UINT64_C(1166033920), // SADDWT_ZZZ_S
5270 UINT64_C(1310724096), // SADDWv16i8_v8i16
5271 UINT64_C(245370880), // SADDWv2i32_v2i64
5272 UINT64_C(241176576), // SADDWv4i16_v4i32
5273 UINT64_C(1319112704), // SADDWv4i32_v2i64
5274 UINT64_C(1314918400), // SADDWv8i16_v4i32
5275 UINT64_C(236982272), // SADDWv8i8_v8i16
5276 UINT64_C(3573756159), // SB
5277 UINT64_C(1170264064), // SBCLB_ZZZ_D
5278 UINT64_C(1166069760), // SBCLB_ZZZ_S
5279 UINT64_C(1170265088), // SBCLT_ZZZ_D
5280 UINT64_C(1166070784), // SBCLT_ZZZ_S
5281 UINT64_C(2046820352), // SBCSWr
5282 UINT64_C(4194304000), // SBCSXr
5283 UINT64_C(1509949440), // SBCWr
5284 UINT64_C(3657433088), // SBCXr
5285 UINT64_C(318767104), // SBFMWri
5286 UINT64_C(2470445056), // SBFMXri
5287 UINT64_C(3240150016), // SCLAMP_VG2_2Z2Z_B
5288 UINT64_C(3252732928), // SCLAMP_VG2_2Z2Z_D
5289 UINT64_C(3244344320), // SCLAMP_VG2_2Z2Z_H
5290 UINT64_C(3248538624), // SCLAMP_VG2_2Z2Z_S
5291 UINT64_C(3240152064), // SCLAMP_VG4_4Z4Z_B
5292 UINT64_C(3252734976), // SCLAMP_VG4_4Z4Z_D
5293 UINT64_C(3244346368), // SCLAMP_VG4_4Z4Z_H
5294 UINT64_C(3248540672), // SCLAMP_VG4_4Z4Z_S
5295 UINT64_C(1140899840), // SCLAMP_ZZZ_B
5296 UINT64_C(1153482752), // SCLAMP_ZZZ_D
5297 UINT64_C(1145094144), // SCLAMP_ZZZ_H
5298 UINT64_C(1149288448), // SCLAMP_ZZZ_S
5299 UINT64_C(507674624), // SCVTFSWDri
5300 UINT64_C(516063232), // SCVTFSWHri
5301 UINT64_C(503480320), // SCVTFSWSri
5302 UINT64_C(2655125504), // SCVTFSXDri
5303 UINT64_C(2663514112), // SCVTFSXHri
5304 UINT64_C(2650931200), // SCVTFSXSri
5305 UINT64_C(509739008), // SCVTFUWDri
5306 UINT64_C(518127616), // SCVTFUWHri
5307 UINT64_C(505544704), // SCVTFUWSri
5308 UINT64_C(2657222656), // SCVTFUXDri
5309 UINT64_C(2665611264), // SCVTFUXHri
5310 UINT64_C(2653028352), // SCVTFUXSri
5311 UINT64_C(3240288256), // SCVTF_2Z2Z_StoS
5312 UINT64_C(3241336832), // SCVTF_4Z4Z_StoS
5313 UINT64_C(1708564480), // SCVTF_ZPmZ_DtoD
5314 UINT64_C(1700175872), // SCVTF_ZPmZ_DtoH
5315 UINT64_C(1708433408), // SCVTF_ZPmZ_DtoS
5316 UINT64_C(1699913728), // SCVTF_ZPmZ_HtoH
5317 UINT64_C(1708171264), // SCVTF_ZPmZ_StoD
5318 UINT64_C(1700044800), // SCVTF_ZPmZ_StoH
5319 UINT64_C(1704239104), // SCVTF_ZPmZ_StoS
5320 UINT64_C(1598088192), // SCVTFd
5321 UINT64_C(1594942464), // SCVTFh
5322 UINT64_C(1595991040), // SCVTFs
5323 UINT64_C(1585043456), // SCVTFv1i16
5324 UINT64_C(1579276288), // SCVTFv1i32
5325 UINT64_C(1583470592), // SCVTFv1i64
5326 UINT64_C(237099008), // SCVTFv2f32
5327 UINT64_C(1315035136), // SCVTFv2f64
5328 UINT64_C(253813760), // SCVTFv2i32_shift
5329 UINT64_C(1329652736), // SCVTFv2i64_shift
5330 UINT64_C(242866176), // SCVTFv4f16
5331 UINT64_C(1310840832), // SCVTFv4f32
5332 UINT64_C(252765184), // SCVTFv4i16_shift
5333 UINT64_C(1327555584), // SCVTFv4i32_shift
5334 UINT64_C(1316608000), // SCVTFv8f16
5335 UINT64_C(1326507008), // SCVTFv8i16_shift
5336 UINT64_C(81133568), // SDIVR_ZPmZ_D
5337 UINT64_C(76939264), // SDIVR_ZPmZ_S
5338 UINT64_C(448793600), // SDIVWr
5339 UINT64_C(2596277248), // SDIVXr
5340 UINT64_C(81002496), // SDIV_ZPmZ_D
5341 UINT64_C(76808192), // SDIV_ZPmZ_S
5342 UINT64_C(3248493568), // SDOT_VG2_M2Z2Z_BtoS
5343 UINT64_C(3252687872), // SDOT_VG2_M2Z2Z_HtoD
5344 UINT64_C(3252687880), // SDOT_VG2_M2Z2Z_HtoS
5345 UINT64_C(3243249696), // SDOT_VG2_M2ZZI_BToS
5346 UINT64_C(3243249664), // SDOT_VG2_M2ZZI_HToS
5347 UINT64_C(3251634184), // SDOT_VG2_M2ZZI_HtoD
5348 UINT64_C(3240104960), // SDOT_VG2_M2ZZ_BtoS
5349 UINT64_C(3244299264), // SDOT_VG2_M2ZZ_HtoD
5350 UINT64_C(3244299272), // SDOT_VG2_M2ZZ_HtoS
5351 UINT64_C(3248559104), // SDOT_VG4_M4Z4Z_BtoS
5352 UINT64_C(3252753408), // SDOT_VG4_M4Z4Z_HtoD
5353 UINT64_C(3252753416), // SDOT_VG4_M4Z4Z_HtoS
5354 UINT64_C(3243282464), // SDOT_VG4_M4ZZI_BToS
5355 UINT64_C(3243282432), // SDOT_VG4_M4ZZI_HToS
5356 UINT64_C(3251666952), // SDOT_VG4_M4ZZI_HtoD
5357 UINT64_C(3241153536), // SDOT_VG4_M4ZZ_BtoS
5358 UINT64_C(3245347840), // SDOT_VG4_M4ZZ_HtoD
5359 UINT64_C(3245347848), // SDOT_VG4_M4ZZ_HtoS
5360 UINT64_C(1155530752), // SDOT_ZZZI_D
5361 UINT64_C(1149290496), // SDOT_ZZZI_HtoS
5362 UINT64_C(1151336448), // SDOT_ZZZI_S
5363 UINT64_C(1153433600), // SDOT_ZZZ_D
5364 UINT64_C(1140901888), // SDOT_ZZZ_HtoS
5365 UINT64_C(1149239296), // SDOT_ZZZ_S
5366 UINT64_C(1333846016), // SDOTlanev16i8
5367 UINT64_C(260104192), // SDOTlanev8i8
5368 UINT64_C(1317049344), // SDOTv16i8
5369 UINT64_C(243307520), // SDOTv8i8
5370 UINT64_C(620773904), // SEL_PPPP
5371 UINT64_C(3240132608), // SEL_VG2_2ZC2Z2Z_B
5372 UINT64_C(3252715520), // SEL_VG2_2ZC2Z2Z_D
5373 UINT64_C(3244326912), // SEL_VG2_2ZC2Z2Z_H
5374 UINT64_C(3248521216), // SEL_VG2_2ZC2Z2Z_S
5375 UINT64_C(3240198144), // SEL_VG4_4ZC4Z4Z_B
5376 UINT64_C(3252781056), // SEL_VG4_4ZC4Z4Z_D
5377 UINT64_C(3244392448), // SEL_VG4_4ZC4Z4Z_H
5378 UINT64_C(3248586752), // SEL_VG4_4ZC4Z4Z_S
5379 UINT64_C(86032384), // SEL_ZPZZ_B
5380 UINT64_C(98615296), // SEL_ZPZZ_D
5381 UINT64_C(90226688), // SEL_ZPZZ_H
5382 UINT64_C(94420992), // SEL_ZPZZ_S
5383 UINT64_C(432047104), // SETE
5384 UINT64_C(432055296), // SETEN
5385 UINT64_C(432051200), // SETET
5386 UINT64_C(432059392), // SETETN
5387 UINT64_C(973096973), // SETF16
5388 UINT64_C(973080589), // SETF8
5389 UINT64_C(623677440), // SETFFR
5390 UINT64_C(499139584), // SETGM
5391 UINT64_C(499147776), // SETGMN
5392 UINT64_C(499143680), // SETGMT
5393 UINT64_C(499151872), // SETGMTN
5394 UINT64_C(499123200), // SETGP
5395 UINT64_C(499131392), // SETGPN
5396 UINT64_C(499127296), // SETGPT
5397 UINT64_C(499135488), // SETGPTN
5398 UINT64_C(432030720), // SETM
5399 UINT64_C(432038912), // SETMN
5400 UINT64_C(432034816), // SETMT
5401 UINT64_C(432043008), // SETMTN
5402 UINT64_C(432014336), // SETP
5403 UINT64_C(432022528), // SETPN
5404 UINT64_C(432018432), // SETPT
5405 UINT64_C(432026624), // SETPTN
5406 UINT64_C(1577058304), // SHA1Crrr
5407 UINT64_C(1579681792), // SHA1Hrr
5408 UINT64_C(1577066496), // SHA1Mrrr
5409 UINT64_C(1577062400), // SHA1Prrr
5410 UINT64_C(1577070592), // SHA1SU0rrr
5411 UINT64_C(1579685888), // SHA1SU1rr
5412 UINT64_C(1577078784), // SHA256H2rrr
5413 UINT64_C(1577074688), // SHA256Hrrr
5414 UINT64_C(1579689984), // SHA256SU0rr
5415 UINT64_C(1577082880), // SHA256SU1rrr
5416 UINT64_C(3462430720), // SHA512H
5417 UINT64_C(3462431744), // SHA512H2
5418 UINT64_C(3468722176), // SHA512SU0
5419 UINT64_C(3462432768), // SHA512SU1
5420 UINT64_C(1141932032), // SHADD_ZPmZ_B
5421 UINT64_C(1154514944), // SHADD_ZPmZ_D
5422 UINT64_C(1146126336), // SHADD_ZPmZ_H
5423 UINT64_C(1150320640), // SHADD_ZPmZ_S
5424 UINT64_C(1310721024), // SHADDv16i8
5425 UINT64_C(245367808), // SHADDv2i32
5426 UINT64_C(241173504), // SHADDv4i16
5427 UINT64_C(1319109632), // SHADDv4i32
5428 UINT64_C(1314915328), // SHADDv8i16
5429 UINT64_C(236979200), // SHADDv8i8
5430 UINT64_C(1847670784), // SHLLv16i8
5431 UINT64_C(782317568), // SHLLv2i32
5432 UINT64_C(778123264), // SHLLv4i16
5433 UINT64_C(1856059392), // SHLLv4i32
5434 UINT64_C(1851865088), // SHLLv8i16
5435 UINT64_C(773928960), // SHLLv8i8
5436 UINT64_C(1598051328), // SHLd
5437 UINT64_C(1325945856), // SHLv16i8_shift
5438 UINT64_C(253776896), // SHLv2i32_shift
5439 UINT64_C(1329615872), // SHLv2i64_shift
5440 UINT64_C(252728320), // SHLv4i16_shift
5441 UINT64_C(1327518720), // SHLv4i32_shift
5442 UINT64_C(1326470144), // SHLv8i16_shift
5443 UINT64_C(252204032), // SHLv8i8_shift
5444 UINT64_C(1160253440), // SHRNB_ZZI_B
5445 UINT64_C(1160777728), // SHRNB_ZZI_H
5446 UINT64_C(1163923456), // SHRNB_ZZI_S
5447 UINT64_C(1160254464), // SHRNT_ZZI_B
5448 UINT64_C(1160778752), // SHRNT_ZZI_H
5449 UINT64_C(1163924480), // SHRNT_ZZI_S
5450 UINT64_C(1325958144), // SHRNv16i8_shift
5451 UINT64_C(253789184), // SHRNv2i32_shift
5452 UINT64_C(252740608), // SHRNv4i16_shift
5453 UINT64_C(1327531008), // SHRNv4i32_shift
5454 UINT64_C(1326482432), // SHRNv8i16_shift
5455 UINT64_C(252216320), // SHRNv8i8_shift
5456 UINT64_C(1142325248), // SHSUBR_ZPmZ_B
5457 UINT64_C(1154908160), // SHSUBR_ZPmZ_D
5458 UINT64_C(1146519552), // SHSUBR_ZPmZ_H
5459 UINT64_C(1150713856), // SHSUBR_ZPmZ_S
5460 UINT64_C(1142063104), // SHSUB_ZPmZ_B
5461 UINT64_C(1154646016), // SHSUB_ZPmZ_D
5462 UINT64_C(1146257408), // SHSUB_ZPmZ_H
5463 UINT64_C(1150451712), // SHSUB_ZPmZ_S
5464 UINT64_C(1310729216), // SHSUBv16i8
5465 UINT64_C(245376000), // SHSUBv2i32
5466 UINT64_C(241181696), // SHSUBv4i16
5467 UINT64_C(1319117824), // SHSUBv4i32
5468 UINT64_C(1314923520), // SHSUBv8i16
5469 UINT64_C(236987392), // SHSUBv8i8
5470 UINT64_C(1158214656), // SLI_ZZI_B
5471 UINT64_C(1166078976), // SLI_ZZI_D
5472 UINT64_C(1158738944), // SLI_ZZI_H
5473 UINT64_C(1161884672), // SLI_ZZI_S
5474 UINT64_C(2134922240), // SLId
5475 UINT64_C(1862816768), // SLIv16i8_shift
5476 UINT64_C(790647808), // SLIv2i32_shift
5477 UINT64_C(1866486784), // SLIv2i64_shift
5478 UINT64_C(789599232), // SLIv4i16_shift
5479 UINT64_C(1864389632), // SLIv4i32_shift
5480 UINT64_C(1863341056), // SLIv8i16_shift
5481 UINT64_C(789074944), // SLIv8i8_shift
5482 UINT64_C(3462447104), // SM3PARTW1
5483 UINT64_C(3462448128), // SM3PARTW2
5484 UINT64_C(3460300800), // SM3SS1
5485 UINT64_C(3460333568), // SM3TT1A
5486 UINT64_C(3460334592), // SM3TT1B
5487 UINT64_C(3460335616), // SM3TT2A
5488 UINT64_C(3460336640), // SM3TT2B
5489 UINT64_C(3468723200), // SM4E
5490 UINT64_C(1159786496), // SM4EKEY_ZZZ_S
5491 UINT64_C(3462449152), // SM4ENCKEY
5492 UINT64_C(1159979008), // SM4E_ZZZ_S
5493 UINT64_C(2602565632), // SMADDLrrr
5494 UINT64_C(1142202368), // SMAXP_ZPmZ_B
5495 UINT64_C(1154785280), // SMAXP_ZPmZ_D
5496 UINT64_C(1146396672), // SMAXP_ZPmZ_H
5497 UINT64_C(1150590976), // SMAXP_ZPmZ_S
5498 UINT64_C(1310761984), // SMAXPv16i8
5499 UINT64_C(245408768), // SMAXPv2i32
5500 UINT64_C(241214464), // SMAXPv4i16
5501 UINT64_C(1319150592), // SMAXPv4i32
5502 UINT64_C(1314956288), // SMAXPv8i16
5503 UINT64_C(237020160), // SMAXPv8i8
5504 UINT64_C(67903488), // SMAXQV_VPZ_B
5505 UINT64_C(80486400), // SMAXQV_VPZ_D
5506 UINT64_C(72097792), // SMAXQV_VPZ_H
5507 UINT64_C(76292096), // SMAXQV_VPZ_S
5508 UINT64_C(67641344), // SMAXV_VPZ_B
5509 UINT64_C(80224256), // SMAXV_VPZ_D
5510 UINT64_C(71835648), // SMAXV_VPZ_H
5511 UINT64_C(76029952), // SMAXV_VPZ_S
5512 UINT64_C(1311811584), // SMAXVv16i8v
5513 UINT64_C(242264064), // SMAXVv4i16v
5514 UINT64_C(1320200192), // SMAXVv4i32v
5515 UINT64_C(1316005888), // SMAXVv8i16v
5516 UINT64_C(238069760), // SMAXVv8i8v
5517 UINT64_C(297795584), // SMAXWri
5518 UINT64_C(448815104), // SMAXWrr
5519 UINT64_C(2445279232), // SMAXXri
5520 UINT64_C(2596298752), // SMAXXrr
5521 UINT64_C(3240144896), // SMAX_VG2_2Z2Z_B
5522 UINT64_C(3252727808), // SMAX_VG2_2Z2Z_D
5523 UINT64_C(3244339200), // SMAX_VG2_2Z2Z_H
5524 UINT64_C(3248533504), // SMAX_VG2_2Z2Z_S
5525 UINT64_C(3240140800), // SMAX_VG2_2ZZ_B
5526 UINT64_C(3252723712), // SMAX_VG2_2ZZ_D
5527 UINT64_C(3244335104), // SMAX_VG2_2ZZ_H
5528 UINT64_C(3248529408), // SMAX_VG2_2ZZ_S
5529 UINT64_C(3240146944), // SMAX_VG4_4Z4Z_B
5530 UINT64_C(3252729856), // SMAX_VG4_4Z4Z_D
5531 UINT64_C(3244341248), // SMAX_VG4_4Z4Z_H
5532 UINT64_C(3248535552), // SMAX_VG4_4Z4Z_S
5533 UINT64_C(3240142848), // SMAX_VG4_4ZZ_B
5534 UINT64_C(3252725760), // SMAX_VG4_4ZZ_D
5535 UINT64_C(3244337152), // SMAX_VG4_4ZZ_H
5536 UINT64_C(3248531456), // SMAX_VG4_4ZZ_S
5537 UINT64_C(623427584), // SMAX_ZI_B
5538 UINT64_C(636010496), // SMAX_ZI_D
5539 UINT64_C(627621888), // SMAX_ZI_H
5540 UINT64_C(631816192), // SMAX_ZI_S
5541 UINT64_C(67633152), // SMAX_ZPmZ_B
5542 UINT64_C(80216064), // SMAX_ZPmZ_D
5543 UINT64_C(71827456), // SMAX_ZPmZ_H
5544 UINT64_C(76021760), // SMAX_ZPmZ_S
5545 UINT64_C(1310745600), // SMAXv16i8
5546 UINT64_C(245392384), // SMAXv2i32
5547 UINT64_C(241198080), // SMAXv4i16
5548 UINT64_C(1319134208), // SMAXv4i32
5549 UINT64_C(1314939904), // SMAXv8i16
5550 UINT64_C(237003776), // SMAXv8i8
5551 UINT64_C(3556769795), // SMC
5552 UINT64_C(1142333440), // SMINP_ZPmZ_B
5553 UINT64_C(1154916352), // SMINP_ZPmZ_D
5554 UINT64_C(1146527744), // SMINP_ZPmZ_H
5555 UINT64_C(1150722048), // SMINP_ZPmZ_S
5556 UINT64_C(1310764032), // SMINPv16i8
5557 UINT64_C(245410816), // SMINPv2i32
5558 UINT64_C(241216512), // SMINPv4i16
5559 UINT64_C(1319152640), // SMINPv4i32
5560 UINT64_C(1314958336), // SMINPv8i16
5561 UINT64_C(237022208), // SMINPv8i8
5562 UINT64_C(68034560), // SMINQV_VPZ_B
5563 UINT64_C(80617472), // SMINQV_VPZ_D
5564 UINT64_C(72228864), // SMINQV_VPZ_H
5565 UINT64_C(76423168), // SMINQV_VPZ_S
5566 UINT64_C(67772416), // SMINV_VPZ_B
5567 UINT64_C(80355328), // SMINV_VPZ_D
5568 UINT64_C(71966720), // SMINV_VPZ_H
5569 UINT64_C(76161024), // SMINV_VPZ_S
5570 UINT64_C(1311877120), // SMINVv16i8v
5571 UINT64_C(242329600), // SMINVv4i16v
5572 UINT64_C(1320265728), // SMINVv4i32v
5573 UINT64_C(1316071424), // SMINVv8i16v
5574 UINT64_C(238135296), // SMINVv8i8v
5575 UINT64_C(298319872), // SMINWri
5576 UINT64_C(448817152), // SMINWrr
5577 UINT64_C(2445803520), // SMINXri
5578 UINT64_C(2596300800), // SMINXrr
5579 UINT64_C(3240144928), // SMIN_VG2_2Z2Z_B
5580 UINT64_C(3252727840), // SMIN_VG2_2Z2Z_D
5581 UINT64_C(3244339232), // SMIN_VG2_2Z2Z_H
5582 UINT64_C(3248533536), // SMIN_VG2_2Z2Z_S
5583 UINT64_C(3240140832), // SMIN_VG2_2ZZ_B
5584 UINT64_C(3252723744), // SMIN_VG2_2ZZ_D
5585 UINT64_C(3244335136), // SMIN_VG2_2ZZ_H
5586 UINT64_C(3248529440), // SMIN_VG2_2ZZ_S
5587 UINT64_C(3240146976), // SMIN_VG4_4Z4Z_B
5588 UINT64_C(3252729888), // SMIN_VG4_4Z4Z_D
5589 UINT64_C(3244341280), // SMIN_VG4_4Z4Z_H
5590 UINT64_C(3248535584), // SMIN_VG4_4Z4Z_S
5591 UINT64_C(3240142880), // SMIN_VG4_4ZZ_B
5592 UINT64_C(3252725792), // SMIN_VG4_4ZZ_D
5593 UINT64_C(3244337184), // SMIN_VG4_4ZZ_H
5594 UINT64_C(3248531488), // SMIN_VG4_4ZZ_S
5595 UINT64_C(623558656), // SMIN_ZI_B
5596 UINT64_C(636141568), // SMIN_ZI_D
5597 UINT64_C(627752960), // SMIN_ZI_H
5598 UINT64_C(631947264), // SMIN_ZI_S
5599 UINT64_C(67764224), // SMIN_ZPmZ_B
5600 UINT64_C(80347136), // SMIN_ZPmZ_D
5601 UINT64_C(71958528), // SMIN_ZPmZ_H
5602 UINT64_C(76152832), // SMIN_ZPmZ_S
5603 UINT64_C(1310747648), // SMINv16i8
5604 UINT64_C(245394432), // SMINv2i32
5605 UINT64_C(241200128), // SMINv4i16
5606 UINT64_C(1319136256), // SMINv4i32
5607 UINT64_C(1314941952), // SMINv8i16
5608 UINT64_C(237005824), // SMINv8i8
5609 UINT64_C(1155563520), // SMLALB_ZZZI_D
5610 UINT64_C(1151369216), // SMLALB_ZZZI_S
5611 UINT64_C(1153449984), // SMLALB_ZZZ_D
5612 UINT64_C(1145061376), // SMLALB_ZZZ_H
5613 UINT64_C(1149255680), // SMLALB_ZZZ_S
5614 UINT64_C(3238002688), // SMLALL_MZZI_BtoS
5615 UINT64_C(3246391296), // SMLALL_MZZI_HtoD
5616 UINT64_C(3240100864), // SMLALL_MZZ_BtoS
5617 UINT64_C(3244295168), // SMLALL_MZZ_HtoD
5618 UINT64_C(3248488448), // SMLALL_VG2_M2Z2Z_BtoS
5619 UINT64_C(3252682752), // SMLALL_VG2_M2Z2Z_HtoD
5620 UINT64_C(3239051264), // SMLALL_VG2_M2ZZI_BtoS
5621 UINT64_C(3247439872), // SMLALL_VG2_M2ZZI_HtoD
5622 UINT64_C(3240099840), // SMLALL_VG2_M2ZZ_BtoS
5623 UINT64_C(3244294144), // SMLALL_VG2_M2ZZ_HtoD
5624 UINT64_C(3248553984), // SMLALL_VG4_M4Z4Z_BtoS
5625 UINT64_C(3252748288), // SMLALL_VG4_M4Z4Z_HtoD
5626 UINT64_C(3239084032), // SMLALL_VG4_M4ZZI_BtoS
5627 UINT64_C(3247472640), // SMLALL_VG4_M4ZZI_HtoD
5628 UINT64_C(3241148416), // SMLALL_VG4_M4ZZ_BtoS
5629 UINT64_C(3245342720), // SMLALL_VG4_M4ZZ_HtoD
5630 UINT64_C(1155564544), // SMLALT_ZZZI_D
5631 UINT64_C(1151370240), // SMLALT_ZZZI_S
5632 UINT64_C(1153451008), // SMLALT_ZZZ_D
5633 UINT64_C(1145062400), // SMLALT_ZZZ_H
5634 UINT64_C(1149256704), // SMLALT_ZZZ_S
5635 UINT64_C(3250589696), // SMLAL_MZZI_HtoS
5636 UINT64_C(3244297216), // SMLAL_MZZ_HtoS
5637 UINT64_C(3252684800), // SMLAL_VG2_M2Z2Z_HtoS
5638 UINT64_C(3251638272), // SMLAL_VG2_M2ZZI_S
5639 UINT64_C(3244296192), // SMLAL_VG2_M2ZZ_HtoS
5640 UINT64_C(3252750336), // SMLAL_VG4_M4Z4Z_HtoS
5641 UINT64_C(3251671040), // SMLAL_VG4_M4ZZI_HtoS
5642 UINT64_C(3245344768), // SMLAL_VG4_M4ZZ_HtoS
5643 UINT64_C(1310752768), // SMLALv16i8_v8i16
5644 UINT64_C(260055040), // SMLALv2i32_indexed
5645 UINT64_C(245399552), // SMLALv2i32_v2i64
5646 UINT64_C(255860736), // SMLALv4i16_indexed
5647 UINT64_C(241205248), // SMLALv4i16_v4i32
5648 UINT64_C(1333796864), // SMLALv4i32_indexed
5649 UINT64_C(1319141376), // SMLALv4i32_v2i64
5650 UINT64_C(1329602560), // SMLALv8i16_indexed
5651 UINT64_C(1314947072), // SMLALv8i16_v4i32
5652 UINT64_C(237010944), // SMLALv8i8_v8i16
5653 UINT64_C(1155571712), // SMLSLB_ZZZI_D
5654 UINT64_C(1151377408), // SMLSLB_ZZZI_S
5655 UINT64_C(1153454080), // SMLSLB_ZZZ_D
5656 UINT64_C(1145065472), // SMLSLB_ZZZ_H
5657 UINT64_C(1149259776), // SMLSLB_ZZZ_S
5658 UINT64_C(3238002696), // SMLSLL_MZZI_BtoS
5659 UINT64_C(3246391304), // SMLSLL_MZZI_HtoD
5660 UINT64_C(3240100872), // SMLSLL_MZZ_BtoS
5661 UINT64_C(3244295176), // SMLSLL_MZZ_HtoD
5662 UINT64_C(3248488456), // SMLSLL_VG2_M2Z2Z_BtoS
5663 UINT64_C(3252682760), // SMLSLL_VG2_M2Z2Z_HtoD
5664 UINT64_C(3239051272), // SMLSLL_VG2_M2ZZI_BtoS
5665 UINT64_C(3247439880), // SMLSLL_VG2_M2ZZI_HtoD
5666 UINT64_C(3240099848), // SMLSLL_VG2_M2ZZ_BtoS
5667 UINT64_C(3244294152), // SMLSLL_VG2_M2ZZ_HtoD
5668 UINT64_C(3248553992), // SMLSLL_VG4_M4Z4Z_BtoS
5669 UINT64_C(3252748296), // SMLSLL_VG4_M4Z4Z_HtoD
5670 UINT64_C(3239084040), // SMLSLL_VG4_M4ZZI_BtoS
5671 UINT64_C(3247472648), // SMLSLL_VG4_M4ZZI_HtoD
5672 UINT64_C(3241148424), // SMLSLL_VG4_M4ZZ_BtoS
5673 UINT64_C(3245342728), // SMLSLL_VG4_M4ZZ_HtoD
5674 UINT64_C(1155572736), // SMLSLT_ZZZI_D
5675 UINT64_C(1151378432), // SMLSLT_ZZZI_S
5676 UINT64_C(1153455104), // SMLSLT_ZZZ_D
5677 UINT64_C(1145066496), // SMLSLT_ZZZ_H
5678 UINT64_C(1149260800), // SMLSLT_ZZZ_S
5679 UINT64_C(3250589704), // SMLSL_MZZI_HtoS
5680 UINT64_C(3244297224), // SMLSL_MZZ_HtoS
5681 UINT64_C(3252684808), // SMLSL_VG2_M2Z2Z_HtoS
5682 UINT64_C(3251638280), // SMLSL_VG2_M2ZZI_S
5683 UINT64_C(3244296200), // SMLSL_VG2_M2ZZ_HtoS
5684 UINT64_C(3252750344), // SMLSL_VG4_M4Z4Z_HtoS
5685 UINT64_C(3251671048), // SMLSL_VG4_M4ZZI_HtoS
5686 UINT64_C(3245344776), // SMLSL_VG4_M4ZZ_HtoS
5687 UINT64_C(1310760960), // SMLSLv16i8_v8i16
5688 UINT64_C(260071424), // SMLSLv2i32_indexed
5689 UINT64_C(245407744), // SMLSLv2i32_v2i64
5690 UINT64_C(255877120), // SMLSLv4i16_indexed
5691 UINT64_C(241213440), // SMLSLv4i16_v4i32
5692 UINT64_C(1333813248), // SMLSLv4i32_indexed
5693 UINT64_C(1319149568), // SMLSLv4i32_v2i64
5694 UINT64_C(1329618944), // SMLSLv8i16_indexed
5695 UINT64_C(1314955264), // SMLSLv8i16_v4i32
5696 UINT64_C(237019136), // SMLSLv8i8_v8i16
5697 UINT64_C(1317053440), // SMMLA
5698 UINT64_C(1157666816), // SMMLA_ZZZ
5699 UINT64_C(2696937472), // SMOPA_MPPZZ_D
5700 UINT64_C(2692743176), // SMOPA_MPPZZ_HtoS
5701 UINT64_C(2692743168), // SMOPA_MPPZZ_S
5702 UINT64_C(2696937488), // SMOPS_MPPZZ_D
5703 UINT64_C(2692743192), // SMOPS_MPPZZ_HtoS
5704 UINT64_C(2692743184), // SMOPS_MPPZZ_S
5705 UINT64_C(235023360), // SMOVvi16to32
5706 UINT64_C(235023360), // SMOVvi16to32_idx0
5707 UINT64_C(1308765184), // SMOVvi16to64
5708 UINT64_C(1308765184), // SMOVvi16to64_idx0
5709 UINT64_C(1308896256), // SMOVvi32to64
5710 UINT64_C(1308896256), // SMOVvi32to64_idx0
5711 UINT64_C(234957824), // SMOVvi8to32
5712 UINT64_C(234957824), // SMOVvi8to32_idx0
5713 UINT64_C(1308699648), // SMOVvi8to64
5714 UINT64_C(1308699648), // SMOVvi8to64_idx0
5715 UINT64_C(2602598400), // SMSUBLrrr
5716 UINT64_C(68288512), // SMULH_ZPmZ_B
5717 UINT64_C(80871424), // SMULH_ZPmZ_D
5718 UINT64_C(72482816), // SMULH_ZPmZ_H
5719 UINT64_C(76677120), // SMULH_ZPmZ_S
5720 UINT64_C(69232640), // SMULH_ZZZ_B
5721 UINT64_C(81815552), // SMULH_ZZZ_D
5722 UINT64_C(73426944), // SMULH_ZZZ_H
5723 UINT64_C(77621248), // SMULH_ZZZ_S
5724 UINT64_C(2604662784), // SMULHrr
5725 UINT64_C(1155579904), // SMULLB_ZZZI_D
5726 UINT64_C(1151385600), // SMULLB_ZZZI_S
5727 UINT64_C(1170239488), // SMULLB_ZZZ_D
5728 UINT64_C(1161850880), // SMULLB_ZZZ_H
5729 UINT64_C(1166045184), // SMULLB_ZZZ_S
5730 UINT64_C(1155580928), // SMULLT_ZZZI_D
5731 UINT64_C(1151386624), // SMULLT_ZZZI_S
5732 UINT64_C(1170240512), // SMULLT_ZZZ_D
5733 UINT64_C(1161851904), // SMULLT_ZZZ_H
5734 UINT64_C(1166046208), // SMULLT_ZZZ_S
5735 UINT64_C(1310769152), // SMULLv16i8_v8i16
5736 UINT64_C(260087808), // SMULLv2i32_indexed
5737 UINT64_C(245415936), // SMULLv2i32_v2i64
5738 UINT64_C(255893504), // SMULLv4i16_indexed
5739 UINT64_C(241221632), // SMULLv4i16_v4i32
5740 UINT64_C(1333829632), // SMULLv4i32_indexed
5741 UINT64_C(1319157760), // SMULLv4i32_v2i64
5742 UINT64_C(1329635328), // SMULLv8i16_indexed
5743 UINT64_C(1314963456), // SMULLv8i16_v4i32
5744 UINT64_C(237027328), // SMULLv8i8_v8i16
5745 UINT64_C(86867968), // SPLICE_ZPZZ_B
5746 UINT64_C(99450880), // SPLICE_ZPZZ_D
5747 UINT64_C(91062272), // SPLICE_ZPZZ_H
5748 UINT64_C(95256576), // SPLICE_ZPZZ_S
5749 UINT64_C(86802432), // SPLICE_ZPZ_B
5750 UINT64_C(99385344), // SPLICE_ZPZ_D
5751 UINT64_C(90996736), // SPLICE_ZPZ_H
5752 UINT64_C(95191040), // SPLICE_ZPZ_S
5753 UINT64_C(1141415936), // SQABS_ZPmZ_B
5754 UINT64_C(1153998848), // SQABS_ZPmZ_D
5755 UINT64_C(1145610240), // SQABS_ZPmZ_H
5756 UINT64_C(1149804544), // SQABS_ZPmZ_S
5757 UINT64_C(1310750720), // SQABSv16i8
5758 UINT64_C(1583380480), // SQABSv1i16
5759 UINT64_C(1587574784), // SQABSv1i32
5760 UINT64_C(1591769088), // SQABSv1i64
5761 UINT64_C(1579186176), // SQABSv1i8
5762 UINT64_C(245397504), // SQABSv2i32
5763 UINT64_C(1323333632), // SQABSv2i64
5764 UINT64_C(241203200), // SQABSv4i16
5765 UINT64_C(1319139328), // SQABSv4i32
5766 UINT64_C(1314945024), // SQABSv8i16
5767 UINT64_C(237008896), // SQABSv8i8
5768 UINT64_C(623165440), // SQADD_ZI_B
5769 UINT64_C(635748352), // SQADD_ZI_D
5770 UINT64_C(627359744), // SQADD_ZI_H
5771 UINT64_C(631554048), // SQADD_ZI_S
5772 UINT64_C(1142456320), // SQADD_ZPmZ_B
5773 UINT64_C(1155039232), // SQADD_ZPmZ_D
5774 UINT64_C(1146650624), // SQADD_ZPmZ_H
5775 UINT64_C(1150844928), // SQADD_ZPmZ_S
5776 UINT64_C(69210112), // SQADD_ZZZ_B
5777 UINT64_C(81793024), // SQADD_ZZZ_D
5778 UINT64_C(73404416), // SQADD_ZZZ_H
5779 UINT64_C(77598720), // SQADD_ZZZ_S
5780 UINT64_C(1310723072), // SQADDv16i8
5781 UINT64_C(1583352832), // SQADDv1i16
5782 UINT64_C(1587547136), // SQADDv1i32
5783 UINT64_C(1591741440), // SQADDv1i64
5784 UINT64_C(1579158528), // SQADDv1i8
5785 UINT64_C(245369856), // SQADDv2i32
5786 UINT64_C(1323305984), // SQADDv2i64
5787 UINT64_C(241175552), // SQADDv4i16
5788 UINT64_C(1319111680), // SQADDv4i32
5789 UINT64_C(1314917376), // SQADDv8i16
5790 UINT64_C(236981248), // SQADDv8i8
5791 UINT64_C(1157748736), // SQCADD_ZZI_B
5792 UINT64_C(1170331648), // SQCADD_ZZI_D
5793 UINT64_C(1161943040), // SQCADD_ZZI_H
5794 UINT64_C(1166137344), // SQCADD_ZZI_S
5795 UINT64_C(1160855552), // SQCVTN_Z2Z_StoH
5796 UINT64_C(3249791040), // SQCVTN_Z4Z_DtoH
5797 UINT64_C(3241402432), // SQCVTN_Z4Z_StoB
5798 UINT64_C(1160859648), // SQCVTUN_Z2Z_StoH
5799 UINT64_C(3253985344), // SQCVTUN_Z4Z_DtoH
5800 UINT64_C(3245596736), // SQCVTUN_Z4Z_StoB
5801 UINT64_C(3244548096), // SQCVTU_Z2Z_StoH
5802 UINT64_C(3253985280), // SQCVTU_Z4Z_DtoH
5803 UINT64_C(3245596672), // SQCVTU_Z4Z_StoB
5804 UINT64_C(3240353792), // SQCVT_Z2Z_StoH
5805 UINT64_C(3249790976), // SQCVT_Z4Z_DtoH
5806 UINT64_C(3241402368), // SQCVT_Z4Z_StoB
5807 UINT64_C(70318080), // SQDECB_XPiI
5808 UINT64_C(69269504), // SQDECB_XPiWdI
5809 UINT64_C(82900992), // SQDECD_XPiI
5810 UINT64_C(81852416), // SQDECD_XPiWdI
5811 UINT64_C(81840128), // SQDECD_ZPiI
5812 UINT64_C(74512384), // SQDECH_XPiI
5813 UINT64_C(73463808), // SQDECH_XPiWdI
5814 UINT64_C(73451520), // SQDECH_ZPiI
5815 UINT64_C(623544320), // SQDECP_XPWd_B
5816 UINT64_C(636127232), // SQDECP_XPWd_D
5817 UINT64_C(627738624), // SQDECP_XPWd_H
5818 UINT64_C(631932928), // SQDECP_XPWd_S
5819 UINT64_C(623545344), // SQDECP_XP_B
5820 UINT64_C(636128256), // SQDECP_XP_D
5821 UINT64_C(627739648), // SQDECP_XP_H
5822 UINT64_C(631933952), // SQDECP_XP_S
5823 UINT64_C(636125184), // SQDECP_ZP_D
5824 UINT64_C(627736576), // SQDECP_ZP_H
5825 UINT64_C(631930880), // SQDECP_ZP_S
5826 UINT64_C(78706688), // SQDECW_XPiI
5827 UINT64_C(77658112), // SQDECW_XPiWdI
5828 UINT64_C(77645824), // SQDECW_ZPiI
5829 UINT64_C(1153435648), // SQDMLALBT_ZZZ_D
5830 UINT64_C(1145047040), // SQDMLALBT_ZZZ_H
5831 UINT64_C(1149241344), // SQDMLALBT_ZZZ_S
5832 UINT64_C(1155538944), // SQDMLALB_ZZZI_D
5833 UINT64_C(1151344640), // SQDMLALB_ZZZI_S
5834 UINT64_C(1153458176), // SQDMLALB_ZZZ_D
5835 UINT64_C(1145069568), // SQDMLALB_ZZZ_H
5836 UINT64_C(1149263872), // SQDMLALB_ZZZ_S
5837 UINT64_C(1155539968), // SQDMLALT_ZZZI_D
5838 UINT64_C(1151345664), // SQDMLALT_ZZZI_S
5839 UINT64_C(1153459200), // SQDMLALT_ZZZ_D
5840 UINT64_C(1145070592), // SQDMLALT_ZZZ_H
5841 UINT64_C(1149264896), // SQDMLALT_ZZZ_S
5842 UINT64_C(1583386624), // SQDMLALi16
5843 UINT64_C(1587580928), // SQDMLALi32
5844 UINT64_C(1598042112), // SQDMLALv1i32_indexed
5845 UINT64_C(1602236416), // SQDMLALv1i64_indexed
5846 UINT64_C(260059136), // SQDMLALv2i32_indexed
5847 UINT64_C(245403648), // SQDMLALv2i32_v2i64
5848 UINT64_C(255864832), // SQDMLALv4i16_indexed
5849 UINT64_C(241209344), // SQDMLALv4i16_v4i32
5850 UINT64_C(1333800960), // SQDMLALv4i32_indexed
5851 UINT64_C(1319145472), // SQDMLALv4i32_v2i64
5852 UINT64_C(1329606656), // SQDMLALv8i16_indexed
5853 UINT64_C(1314951168), // SQDMLALv8i16_v4i32
5854 UINT64_C(1153436672), // SQDMLSLBT_ZZZ_D
5855 UINT64_C(1145048064), // SQDMLSLBT_ZZZ_H
5856 UINT64_C(1149242368), // SQDMLSLBT_ZZZ_S
5857 UINT64_C(1155543040), // SQDMLSLB_ZZZI_D
5858 UINT64_C(1151348736), // SQDMLSLB_ZZZI_S
5859 UINT64_C(1153460224), // SQDMLSLB_ZZZ_D
5860 UINT64_C(1145071616), // SQDMLSLB_ZZZ_H
5861 UINT64_C(1149265920), // SQDMLSLB_ZZZ_S
5862 UINT64_C(1155544064), // SQDMLSLT_ZZZI_D
5863 UINT64_C(1151349760), // SQDMLSLT_ZZZI_S
5864 UINT64_C(1153461248), // SQDMLSLT_ZZZ_D
5865 UINT64_C(1145072640), // SQDMLSLT_ZZZ_H
5866 UINT64_C(1149266944), // SQDMLSLT_ZZZ_S
5867 UINT64_C(1583394816), // SQDMLSLi16
5868 UINT64_C(1587589120), // SQDMLSLi32
5869 UINT64_C(1598058496), // SQDMLSLv1i32_indexed
5870 UINT64_C(1602252800), // SQDMLSLv1i64_indexed
5871 UINT64_C(260075520), // SQDMLSLv2i32_indexed
5872 UINT64_C(245411840), // SQDMLSLv2i32_v2i64
5873 UINT64_C(255881216), // SQDMLSLv4i16_indexed
5874 UINT64_C(241217536), // SQDMLSLv4i16_v4i32
5875 UINT64_C(1333817344), // SQDMLSLv4i32_indexed
5876 UINT64_C(1319153664), // SQDMLSLv4i32_v2i64
5877 UINT64_C(1329623040), // SQDMLSLv8i16_indexed
5878 UINT64_C(1314959360), // SQDMLSLv8i16_v4i32
5879 UINT64_C(3240145920), // SQDMULH_VG2_2Z2Z_B
5880 UINT64_C(3252728832), // SQDMULH_VG2_2Z2Z_D
5881 UINT64_C(3244340224), // SQDMULH_VG2_2Z2Z_H
5882 UINT64_C(3248534528), // SQDMULH_VG2_2Z2Z_S
5883 UINT64_C(3240141824), // SQDMULH_VG2_2ZZ_B
5884 UINT64_C(3252724736), // SQDMULH_VG2_2ZZ_D
5885 UINT64_C(3244336128), // SQDMULH_VG2_2ZZ_H
5886 UINT64_C(3248530432), // SQDMULH_VG2_2ZZ_S
5887 UINT64_C(3240147968), // SQDMULH_VG4_4Z4Z_B
5888 UINT64_C(3252730880), // SQDMULH_VG4_4Z4Z_D
5889 UINT64_C(3244342272), // SQDMULH_VG4_4Z4Z_H
5890 UINT64_C(3248536576), // SQDMULH_VG4_4Z4Z_S
5891 UINT64_C(3240143872), // SQDMULH_VG4_4ZZ_B
5892 UINT64_C(3252726784), // SQDMULH_VG4_4ZZ_D
5893 UINT64_C(3244338176), // SQDMULH_VG4_4ZZ_H
5894 UINT64_C(3248532480), // SQDMULH_VG4_4ZZ_S
5895 UINT64_C(1155592192), // SQDMULH_ZZZI_D
5896 UINT64_C(1143009280), // SQDMULH_ZZZI_H
5897 UINT64_C(1151397888), // SQDMULH_ZZZI_S
5898 UINT64_C(69234688), // SQDMULH_ZZZ_B
5899 UINT64_C(81817600), // SQDMULH_ZZZ_D
5900 UINT64_C(73428992), // SQDMULH_ZZZ_H
5901 UINT64_C(77623296), // SQDMULH_ZZZ_S
5902 UINT64_C(1583395840), // SQDMULHv1i16
5903 UINT64_C(1598078976), // SQDMULHv1i16_indexed
5904 UINT64_C(1587590144), // SQDMULHv1i32
5905 UINT64_C(1602273280), // SQDMULHv1i32_indexed
5906 UINT64_C(245412864), // SQDMULHv2i32
5907 UINT64_C(260096000), // SQDMULHv2i32_indexed
5908 UINT64_C(241218560), // SQDMULHv4i16
5909 UINT64_C(255901696), // SQDMULHv4i16_indexed
5910 UINT64_C(1319154688), // SQDMULHv4i32
5911 UINT64_C(1333837824), // SQDMULHv4i32_indexed
5912 UINT64_C(1314960384), // SQDMULHv8i16
5913 UINT64_C(1329643520), // SQDMULHv8i16_indexed
5914 UINT64_C(1155588096), // SQDMULLB_ZZZI_D
5915 UINT64_C(1151393792), // SQDMULLB_ZZZI_S
5916 UINT64_C(1170235392), // SQDMULLB_ZZZ_D
5917 UINT64_C(1161846784), // SQDMULLB_ZZZ_H
5918 UINT64_C(1166041088), // SQDMULLB_ZZZ_S
5919 UINT64_C(1155589120), // SQDMULLT_ZZZI_D
5920 UINT64_C(1151394816), // SQDMULLT_ZZZI_S
5921 UINT64_C(1170236416), // SQDMULLT_ZZZ_D
5922 UINT64_C(1161847808), // SQDMULLT_ZZZ_H
5923 UINT64_C(1166042112), // SQDMULLT_ZZZ_S
5924 UINT64_C(1583403008), // SQDMULLi16
5925 UINT64_C(1587597312), // SQDMULLi32
5926 UINT64_C(1598074880), // SQDMULLv1i32_indexed
5927 UINT64_C(1602269184), // SQDMULLv1i64_indexed
5928 UINT64_C(260091904), // SQDMULLv2i32_indexed
5929 UINT64_C(245420032), // SQDMULLv2i32_v2i64
5930 UINT64_C(255897600), // SQDMULLv4i16_indexed
5931 UINT64_C(241225728), // SQDMULLv4i16_v4i32
5932 UINT64_C(1333833728), // SQDMULLv4i32_indexed
5933 UINT64_C(1319161856), // SQDMULLv4i32_v2i64
5934 UINT64_C(1329639424), // SQDMULLv8i16_indexed
5935 UINT64_C(1314967552), // SQDMULLv8i16_v4i32
5936 UINT64_C(70316032), // SQINCB_XPiI
5937 UINT64_C(69267456), // SQINCB_XPiWdI
5938 UINT64_C(82898944), // SQINCD_XPiI
5939 UINT64_C(81850368), // SQINCD_XPiWdI
5940 UINT64_C(81838080), // SQINCD_ZPiI
5941 UINT64_C(74510336), // SQINCH_XPiI
5942 UINT64_C(73461760), // SQINCH_XPiWdI
5943 UINT64_C(73449472), // SQINCH_ZPiI
5944 UINT64_C(623413248), // SQINCP_XPWd_B
5945 UINT64_C(635996160), // SQINCP_XPWd_D
5946 UINT64_C(627607552), // SQINCP_XPWd_H
5947 UINT64_C(631801856), // SQINCP_XPWd_S
5948 UINT64_C(623414272), // SQINCP_XP_B
5949 UINT64_C(635997184), // SQINCP_XP_D
5950 UINT64_C(627608576), // SQINCP_XP_H
5951 UINT64_C(631802880), // SQINCP_XP_S
5952 UINT64_C(635994112), // SQINCP_ZP_D
5953 UINT64_C(627605504), // SQINCP_ZP_H
5954 UINT64_C(631799808), // SQINCP_ZP_S
5955 UINT64_C(78704640), // SQINCW_XPiI
5956 UINT64_C(77656064), // SQINCW_XPiWdI
5957 UINT64_C(77643776), // SQINCW_ZPiI
5958 UINT64_C(1141481472), // SQNEG_ZPmZ_B
5959 UINT64_C(1154064384), // SQNEG_ZPmZ_D
5960 UINT64_C(1145675776), // SQNEG_ZPmZ_H
5961 UINT64_C(1149870080), // SQNEG_ZPmZ_S
5962 UINT64_C(1847621632), // SQNEGv16i8
5963 UINT64_C(2120251392), // SQNEGv1i16
5964 UINT64_C(2124445696), // SQNEGv1i32
5965 UINT64_C(2128640000), // SQNEGv1i64
5966 UINT64_C(2116057088), // SQNEGv1i8
5967 UINT64_C(782268416), // SQNEGv2i32
5968 UINT64_C(1860204544), // SQNEGv2i64
5969 UINT64_C(778074112), // SQNEGv4i16
5970 UINT64_C(1856010240), // SQNEGv4i32
5971 UINT64_C(1851815936), // SQNEGv8i16
5972 UINT64_C(773879808), // SQNEGv8i8
5973 UINT64_C(1151365120), // SQRDCMLAH_ZZZI_H
5974 UINT64_C(1155559424), // SQRDCMLAH_ZZZI_S
5975 UINT64_C(1140862976), // SQRDCMLAH_ZZZ_B
5976 UINT64_C(1153445888), // SQRDCMLAH_ZZZ_D
5977 UINT64_C(1145057280), // SQRDCMLAH_ZZZ_H
5978 UINT64_C(1149251584), // SQRDCMLAH_ZZZ_S
5979 UINT64_C(1155534848), // SQRDMLAH_ZZZI_D
5980 UINT64_C(1142951936), // SQRDMLAH_ZZZI_H
5981 UINT64_C(1151340544), // SQRDMLAH_ZZZI_S
5982 UINT64_C(1140879360), // SQRDMLAH_ZZZ_B
5983 UINT64_C(1153462272), // SQRDMLAH_ZZZ_D
5984 UINT64_C(1145073664), // SQRDMLAH_ZZZ_H
5985 UINT64_C(1149267968), // SQRDMLAH_ZZZ_S
5986 UINT64_C(2118157312), // SQRDMLAHv1i16
5987 UINT64_C(2134953984), // SQRDMLAHv1i16_indexed
5988 UINT64_C(2122351616), // SQRDMLAHv1i32
5989 UINT64_C(2139148288), // SQRDMLAHv1i32_indexed
5990 UINT64_C(780174336), // SQRDMLAHv2i32
5991 UINT64_C(796971008), // SQRDMLAHv2i32_indexed
5992 UINT64_C(775980032), // SQRDMLAHv4i16
5993 UINT64_C(792776704), // SQRDMLAHv4i16_indexed
5994 UINT64_C(1853916160), // SQRDMLAHv4i32
5995 UINT64_C(1870712832), // SQRDMLAHv4i32_indexed
5996 UINT64_C(1849721856), // SQRDMLAHv8i16
5997 UINT64_C(1866518528), // SQRDMLAHv8i16_indexed
5998 UINT64_C(1155535872), // SQRDMLSH_ZZZI_D
5999 UINT64_C(1142952960), // SQRDMLSH_ZZZI_H
6000 UINT64_C(1151341568), // SQRDMLSH_ZZZI_S
6001 UINT64_C(1140880384), // SQRDMLSH_ZZZ_B
6002 UINT64_C(1153463296), // SQRDMLSH_ZZZ_D
6003 UINT64_C(1145074688), // SQRDMLSH_ZZZ_H
6004 UINT64_C(1149268992), // SQRDMLSH_ZZZ_S
6005 UINT64_C(2118159360), // SQRDMLSHv1i16
6006 UINT64_C(2134962176), // SQRDMLSHv1i16_indexed
6007 UINT64_C(2122353664), // SQRDMLSHv1i32
6008 UINT64_C(2139156480), // SQRDMLSHv1i32_indexed
6009 UINT64_C(780176384), // SQRDMLSHv2i32
6010 UINT64_C(796979200), // SQRDMLSHv2i32_indexed
6011 UINT64_C(775982080), // SQRDMLSHv4i16
6012 UINT64_C(792784896), // SQRDMLSHv4i16_indexed
6013 UINT64_C(1853918208), // SQRDMLSHv4i32
6014 UINT64_C(1870721024), // SQRDMLSHv4i32_indexed
6015 UINT64_C(1849723904), // SQRDMLSHv8i16
6016 UINT64_C(1866526720), // SQRDMLSHv8i16_indexed
6017 UINT64_C(1155593216), // SQRDMULH_ZZZI_D
6018 UINT64_C(1143010304), // SQRDMULH_ZZZI_H
6019 UINT64_C(1151398912), // SQRDMULH_ZZZI_S
6020 UINT64_C(69235712), // SQRDMULH_ZZZ_B
6021 UINT64_C(81818624), // SQRDMULH_ZZZ_D
6022 UINT64_C(73430016), // SQRDMULH_ZZZ_H
6023 UINT64_C(77624320), // SQRDMULH_ZZZ_S
6024 UINT64_C(2120266752), // SQRDMULHv1i16
6025 UINT64_C(1598083072), // SQRDMULHv1i16_indexed
6026 UINT64_C(2124461056), // SQRDMULHv1i32
6027 UINT64_C(1602277376), // SQRDMULHv1i32_indexed
6028 UINT64_C(782283776), // SQRDMULHv2i32
6029 UINT64_C(260100096), // SQRDMULHv2i32_indexed
6030 UINT64_C(778089472), // SQRDMULHv4i16
6031 UINT64_C(255905792), // SQRDMULHv4i16_indexed
6032 UINT64_C(1856025600), // SQRDMULHv4i32
6033 UINT64_C(1333841920), // SQRDMULHv4i32_indexed
6034 UINT64_C(1851831296), // SQRDMULHv8i16
6035 UINT64_C(1329647616), // SQRDMULHv8i16_indexed
6036 UINT64_C(1141800960), // SQRSHLR_ZPmZ_B
6037 UINT64_C(1154383872), // SQRSHLR_ZPmZ_D
6038 UINT64_C(1145995264), // SQRSHLR_ZPmZ_H
6039 UINT64_C(1150189568), // SQRSHLR_ZPmZ_S
6040 UINT64_C(1141538816), // SQRSHL_ZPmZ_B
6041 UINT64_C(1154121728), // SQRSHL_ZPmZ_D
6042 UINT64_C(1145733120), // SQRSHL_ZPmZ_H
6043 UINT64_C(1149927424), // SQRSHL_ZPmZ_S
6044 UINT64_C(1310743552), // SQRSHLv16i8
6045 UINT64_C(1583373312), // SQRSHLv1i16
6046 UINT64_C(1587567616), // SQRSHLv1i32
6047 UINT64_C(1591761920), // SQRSHLv1i64
6048 UINT64_C(1579179008), // SQRSHLv1i8
6049 UINT64_C(245390336), // SQRSHLv2i32
6050 UINT64_C(1323326464), // SQRSHLv2i64
6051 UINT64_C(241196032), // SQRSHLv4i16
6052 UINT64_C(1319132160), // SQRSHLv4i32
6053 UINT64_C(1314937856), // SQRSHLv8i16
6054 UINT64_C(237001728), // SQRSHLv8i8
6055 UINT64_C(1160259584), // SQRSHRNB_ZZI_B
6056 UINT64_C(1160783872), // SQRSHRNB_ZZI_H
6057 UINT64_C(1163929600), // SQRSHRNB_ZZI_S
6058 UINT64_C(1160260608), // SQRSHRNT_ZZI_B
6059 UINT64_C(1160784896), // SQRSHRNT_ZZI_H
6060 UINT64_C(1163930624), // SQRSHRNT_ZZI_S
6061 UINT64_C(3244350464), // SQRSHRN_VG4_Z4ZI_B
6062 UINT64_C(3248544768), // SQRSHRN_VG4_Z4ZI_H
6063 UINT64_C(1169172480), // SQRSHRN_Z2ZI_StoH
6064 UINT64_C(1594399744), // SQRSHRNb
6065 UINT64_C(1594924032), // SQRSHRNh
6066 UINT64_C(1595972608), // SQRSHRNs
6067 UINT64_C(1325964288), // SQRSHRNv16i8_shift
6068 UINT64_C(253795328), // SQRSHRNv2i32_shift
6069 UINT64_C(252746752), // SQRSHRNv4i16_shift
6070 UINT64_C(1327537152), // SQRSHRNv4i32_shift
6071 UINT64_C(1326488576), // SQRSHRNv8i16_shift
6072 UINT64_C(252222464), // SQRSHRNv8i8_shift
6073 UINT64_C(1160251392), // SQRSHRUNB_ZZI_B
6074 UINT64_C(1160775680), // SQRSHRUNB_ZZI_H
6075 UINT64_C(1163921408), // SQRSHRUNB_ZZI_S
6076 UINT64_C(1160252416), // SQRSHRUNT_ZZI_B
6077 UINT64_C(1160776704), // SQRSHRUNT_ZZI_H
6078 UINT64_C(1163922432), // SQRSHRUNT_ZZI_S
6079 UINT64_C(3244350528), // SQRSHRUN_VG4_Z4ZI_B
6080 UINT64_C(3248544832), // SQRSHRUN_VG4_Z4ZI_H
6081 UINT64_C(1169164288), // SQRSHRUN_Z2ZI_StoH
6082 UINT64_C(2131266560), // SQRSHRUNb
6083 UINT64_C(2131790848), // SQRSHRUNh
6084 UINT64_C(2132839424), // SQRSHRUNs
6085 UINT64_C(1862831104), // SQRSHRUNv16i8_shift
6086 UINT64_C(790662144), // SQRSHRUNv2i32_shift
6087 UINT64_C(789613568), // SQRSHRUNv4i16_shift
6088 UINT64_C(1864403968), // SQRSHRUNv4i32_shift
6089 UINT64_C(1863355392), // SQRSHRUNv8i16_shift
6090 UINT64_C(789089280), // SQRSHRUNv8i8_shift
6091 UINT64_C(3253785600), // SQRSHRU_VG2_Z2ZI_H
6092 UINT64_C(3244349504), // SQRSHRU_VG4_Z4ZI_B
6093 UINT64_C(3248543808), // SQRSHRU_VG4_Z4ZI_H
6094 UINT64_C(3252737024), // SQRSHR_VG2_Z2ZI_H
6095 UINT64_C(3244349440), // SQRSHR_VG4_Z4ZI_B
6096 UINT64_C(3248543744), // SQRSHR_VG4_Z4ZI_H
6097 UINT64_C(1141669888), // SQSHLR_ZPmZ_B
6098 UINT64_C(1154252800), // SQSHLR_ZPmZ_D
6099 UINT64_C(1145864192), // SQSHLR_ZPmZ_H
6100 UINT64_C(1150058496), // SQSHLR_ZPmZ_S
6101 UINT64_C(68124928), // SQSHLU_ZPmI_B
6102 UINT64_C(76513280), // SQSHLU_ZPmI_D
6103 UINT64_C(68125184), // SQSHLU_ZPmI_H
6104 UINT64_C(72318976), // SQSHLU_ZPmI_S
6105 UINT64_C(2131256320), // SQSHLUb
6106 UINT64_C(2134926336), // SQSHLUd
6107 UINT64_C(2131780608), // SQSHLUh
6108 UINT64_C(2132829184), // SQSHLUs
6109 UINT64_C(1862820864), // SQSHLUv16i8_shift
6110 UINT64_C(790651904), // SQSHLUv2i32_shift
6111 UINT64_C(1866490880), // SQSHLUv2i64_shift
6112 UINT64_C(789603328), // SQSHLUv4i16_shift
6113 UINT64_C(1864393728), // SQSHLUv4i32_shift
6114 UINT64_C(1863345152), // SQSHLUv8i16_shift
6115 UINT64_C(789079040), // SQSHLUv8i8_shift
6116 UINT64_C(67535104), // SQSHL_ZPmI_B
6117 UINT64_C(75923456), // SQSHL_ZPmI_D
6118 UINT64_C(67535360), // SQSHL_ZPmI_H
6119 UINT64_C(71729152), // SQSHL_ZPmI_S
6120 UINT64_C(1141407744), // SQSHL_ZPmZ_B
6121 UINT64_C(1153990656), // SQSHL_ZPmZ_D
6122 UINT64_C(1145602048), // SQSHL_ZPmZ_H
6123 UINT64_C(1149796352), // SQSHL_ZPmZ_S
6124 UINT64_C(1594389504), // SQSHLb
6125 UINT64_C(1598059520), // SQSHLd
6126 UINT64_C(1594913792), // SQSHLh
6127 UINT64_C(1595962368), // SQSHLs
6128 UINT64_C(1310739456), // SQSHLv16i8
6129 UINT64_C(1325954048), // SQSHLv16i8_shift
6130 UINT64_C(1583369216), // SQSHLv1i16
6131 UINT64_C(1587563520), // SQSHLv1i32
6132 UINT64_C(1591757824), // SQSHLv1i64
6133 UINT64_C(1579174912), // SQSHLv1i8
6134 UINT64_C(245386240), // SQSHLv2i32
6135 UINT64_C(253785088), // SQSHLv2i32_shift
6136 UINT64_C(1323322368), // SQSHLv2i64
6137 UINT64_C(1329624064), // SQSHLv2i64_shift
6138 UINT64_C(241191936), // SQSHLv4i16
6139 UINT64_C(252736512), // SQSHLv4i16_shift
6140 UINT64_C(1319128064), // SQSHLv4i32
6141 UINT64_C(1327526912), // SQSHLv4i32_shift
6142 UINT64_C(1314933760), // SQSHLv8i16
6143 UINT64_C(1326478336), // SQSHLv8i16_shift
6144 UINT64_C(236997632), // SQSHLv8i8
6145 UINT64_C(252212224), // SQSHLv8i8_shift
6146 UINT64_C(1160257536), // SQSHRNB_ZZI_B
6147 UINT64_C(1160781824), // SQSHRNB_ZZI_H
6148 UINT64_C(1163927552), // SQSHRNB_ZZI_S
6149 UINT64_C(1160258560), // SQSHRNT_ZZI_B
6150 UINT64_C(1160782848), // SQSHRNT_ZZI_H
6151 UINT64_C(1163928576), // SQSHRNT_ZZI_S
6152 UINT64_C(1594397696), // SQSHRNb
6153 UINT64_C(1594921984), // SQSHRNh
6154 UINT64_C(1595970560), // SQSHRNs
6155 UINT64_C(1325962240), // SQSHRNv16i8_shift
6156 UINT64_C(253793280), // SQSHRNv2i32_shift
6157 UINT64_C(252744704), // SQSHRNv4i16_shift
6158 UINT64_C(1327535104), // SQSHRNv4i32_shift
6159 UINT64_C(1326486528), // SQSHRNv8i16_shift
6160 UINT64_C(252220416), // SQSHRNv8i8_shift
6161 UINT64_C(1160249344), // SQSHRUNB_ZZI_B
6162 UINT64_C(1160773632), // SQSHRUNB_ZZI_H
6163 UINT64_C(1163919360), // SQSHRUNB_ZZI_S
6164 UINT64_C(1160250368), // SQSHRUNT_ZZI_B
6165 UINT64_C(1160774656), // SQSHRUNT_ZZI_H
6166 UINT64_C(1163920384), // SQSHRUNT_ZZI_S
6167 UINT64_C(2131264512), // SQSHRUNb
6168 UINT64_C(2131788800), // SQSHRUNh
6169 UINT64_C(2132837376), // SQSHRUNs
6170 UINT64_C(1862829056), // SQSHRUNv16i8_shift
6171 UINT64_C(790660096), // SQSHRUNv2i32_shift
6172 UINT64_C(789611520), // SQSHRUNv4i16_shift
6173 UINT64_C(1864401920), // SQSHRUNv4i32_shift
6174 UINT64_C(1863353344), // SQSHRUNv8i16_shift
6175 UINT64_C(789087232), // SQSHRUNv8i8_shift
6176 UINT64_C(1142849536), // SQSUBR_ZPmZ_B
6177 UINT64_C(1155432448), // SQSUBR_ZPmZ_D
6178 UINT64_C(1147043840), // SQSUBR_ZPmZ_H
6179 UINT64_C(1151238144), // SQSUBR_ZPmZ_S
6180 UINT64_C(623296512), // SQSUB_ZI_B
6181 UINT64_C(635879424), // SQSUB_ZI_D
6182 UINT64_C(627490816), // SQSUB_ZI_H
6183 UINT64_C(631685120), // SQSUB_ZI_S
6184 UINT64_C(1142587392), // SQSUB_ZPmZ_B
6185 UINT64_C(1155170304), // SQSUB_ZPmZ_D
6186 UINT64_C(1146781696), // SQSUB_ZPmZ_H
6187 UINT64_C(1150976000), // SQSUB_ZPmZ_S
6188 UINT64_C(69212160), // SQSUB_ZZZ_B
6189 UINT64_C(81795072), // SQSUB_ZZZ_D
6190 UINT64_C(73406464), // SQSUB_ZZZ_H
6191 UINT64_C(77600768), // SQSUB_ZZZ_S
6192 UINT64_C(1310731264), // SQSUBv16i8
6193 UINT64_C(1583361024), // SQSUBv1i16
6194 UINT64_C(1587555328), // SQSUBv1i32
6195 UINT64_C(1591749632), // SQSUBv1i64
6196 UINT64_C(1579166720), // SQSUBv1i8
6197 UINT64_C(245378048), // SQSUBv2i32
6198 UINT64_C(1323314176), // SQSUBv2i64
6199 UINT64_C(241183744), // SQSUBv4i16
6200 UINT64_C(1319119872), // SQSUBv4i32
6201 UINT64_C(1314925568), // SQSUBv8i16
6202 UINT64_C(236989440), // SQSUBv8i8
6203 UINT64_C(1160265728), // SQXTNB_ZZ_B
6204 UINT64_C(1160790016), // SQXTNB_ZZ_H
6205 UINT64_C(1163935744), // SQXTNB_ZZ_S
6206 UINT64_C(1160266752), // SQXTNT_ZZ_B
6207 UINT64_C(1160791040), // SQXTNT_ZZ_H
6208 UINT64_C(1163936768), // SQXTNT_ZZ_S
6209 UINT64_C(1310803968), // SQXTNv16i8
6210 UINT64_C(1583433728), // SQXTNv1i16
6211 UINT64_C(1587628032), // SQXTNv1i32
6212 UINT64_C(1579239424), // SQXTNv1i8
6213 UINT64_C(245450752), // SQXTNv2i32
6214 UINT64_C(241256448), // SQXTNv4i16
6215 UINT64_C(1319192576), // SQXTNv4i32
6216 UINT64_C(1314998272), // SQXTNv8i16
6217 UINT64_C(237062144), // SQXTNv8i8
6218 UINT64_C(1160269824), // SQXTUNB_ZZ_B
6219 UINT64_C(1160794112), // SQXTUNB_ZZ_H
6220 UINT64_C(1163939840), // SQXTUNB_ZZ_S
6221 UINT64_C(1160270848), // SQXTUNT_ZZ_B
6222 UINT64_C(1160795136), // SQXTUNT_ZZ_H
6223 UINT64_C(1163940864), // SQXTUNT_ZZ_S
6224 UINT64_C(1847666688), // SQXTUNv16i8
6225 UINT64_C(2120296448), // SQXTUNv1i16
6226 UINT64_C(2124490752), // SQXTUNv1i32
6227 UINT64_C(2116102144), // SQXTUNv1i8
6228 UINT64_C(782313472), // SQXTUNv2i32
6229 UINT64_C(778119168), // SQXTUNv4i16
6230 UINT64_C(1856055296), // SQXTUNv4i32
6231 UINT64_C(1851860992), // SQXTUNv8i16
6232 UINT64_C(773924864), // SQXTUNv8i8
6233 UINT64_C(1142194176), // SRHADD_ZPmZ_B
6234 UINT64_C(1154777088), // SRHADD_ZPmZ_D
6235 UINT64_C(1146388480), // SRHADD_ZPmZ_H
6236 UINT64_C(1150582784), // SRHADD_ZPmZ_S
6237 UINT64_C(1310725120), // SRHADDv16i8
6238 UINT64_C(245371904), // SRHADDv2i32
6239 UINT64_C(241177600), // SRHADDv4i16
6240 UINT64_C(1319113728), // SRHADDv4i32
6241 UINT64_C(1314919424), // SRHADDv8i16
6242 UINT64_C(236983296), // SRHADDv8i8
6243 UINT64_C(1158213632), // SRI_ZZI_B
6244 UINT64_C(1166077952), // SRI_ZZI_D
6245 UINT64_C(1158737920), // SRI_ZZI_H
6246 UINT64_C(1161883648), // SRI_ZZI_S
6247 UINT64_C(2134918144), // SRId
6248 UINT64_C(1862812672), // SRIv16i8_shift
6249 UINT64_C(790643712), // SRIv2i32_shift
6250 UINT64_C(1866482688), // SRIv2i64_shift
6251 UINT64_C(789595136), // SRIv4i16_shift
6252 UINT64_C(1864385536), // SRIv4i32_shift
6253 UINT64_C(1863336960), // SRIv8i16_shift
6254 UINT64_C(789070848), // SRIv8i8_shift
6255 UINT64_C(1141276672), // SRSHLR_ZPmZ_B
6256 UINT64_C(1153859584), // SRSHLR_ZPmZ_D
6257 UINT64_C(1145470976), // SRSHLR_ZPmZ_H
6258 UINT64_C(1149665280), // SRSHLR_ZPmZ_S
6259 UINT64_C(3240145440), // SRSHL_VG2_2Z2Z_B
6260 UINT64_C(3252728352), // SRSHL_VG2_2Z2Z_D
6261 UINT64_C(3244339744), // SRSHL_VG2_2Z2Z_H
6262 UINT64_C(3248534048), // SRSHL_VG2_2Z2Z_S
6263 UINT64_C(3240141344), // SRSHL_VG2_2ZZ_B
6264 UINT64_C(3252724256), // SRSHL_VG2_2ZZ_D
6265 UINT64_C(3244335648), // SRSHL_VG2_2ZZ_H
6266 UINT64_C(3248529952), // SRSHL_VG2_2ZZ_S
6267 UINT64_C(3240147488), // SRSHL_VG4_4Z4Z_B
6268 UINT64_C(3252730400), // SRSHL_VG4_4Z4Z_D
6269 UINT64_C(3244341792), // SRSHL_VG4_4Z4Z_H
6270 UINT64_C(3248536096), // SRSHL_VG4_4Z4Z_S
6271 UINT64_C(3240143392), // SRSHL_VG4_4ZZ_B
6272 UINT64_C(3252726304), // SRSHL_VG4_4ZZ_D
6273 UINT64_C(3244337696), // SRSHL_VG4_4ZZ_H
6274 UINT64_C(3248532000), // SRSHL_VG4_4ZZ_S
6275 UINT64_C(1141014528), // SRSHL_ZPmZ_B
6276 UINT64_C(1153597440), // SRSHL_ZPmZ_D
6277 UINT64_C(1145208832), // SRSHL_ZPmZ_H
6278 UINT64_C(1149403136), // SRSHL_ZPmZ_S
6279 UINT64_C(1310741504), // SRSHLv16i8
6280 UINT64_C(1591759872), // SRSHLv1i64
6281 UINT64_C(245388288), // SRSHLv2i32
6282 UINT64_C(1323324416), // SRSHLv2i64
6283 UINT64_C(241193984), // SRSHLv4i16
6284 UINT64_C(1319130112), // SRSHLv4i32
6285 UINT64_C(1314935808), // SRSHLv8i16
6286 UINT64_C(236999680), // SRSHLv8i8
6287 UINT64_C(67928320), // SRSHR_ZPmI_B
6288 UINT64_C(76316672), // SRSHR_ZPmI_D
6289 UINT64_C(67928576), // SRSHR_ZPmI_H
6290 UINT64_C(72122368), // SRSHR_ZPmI_S
6291 UINT64_C(1598039040), // SRSHRd
6292 UINT64_C(1325933568), // SRSHRv16i8_shift
6293 UINT64_C(253764608), // SRSHRv2i32_shift
6294 UINT64_C(1329603584), // SRSHRv2i64_shift
6295 UINT64_C(252716032), // SRSHRv4i16_shift
6296 UINT64_C(1327506432), // SRSHRv4i32_shift
6297 UINT64_C(1326457856), // SRSHRv8i16_shift
6298 UINT64_C(252191744), // SRSHRv8i8_shift
6299 UINT64_C(1158211584), // SRSRA_ZZI_B
6300 UINT64_C(1166075904), // SRSRA_ZZI_D
6301 UINT64_C(1158735872), // SRSRA_ZZI_H
6302 UINT64_C(1161881600), // SRSRA_ZZI_S
6303 UINT64_C(1598043136), // SRSRAd
6304 UINT64_C(1325937664), // SRSRAv16i8_shift
6305 UINT64_C(253768704), // SRSRAv2i32_shift
6306 UINT64_C(1329607680), // SRSRAv2i64_shift
6307 UINT64_C(252720128), // SRSRAv4i16_shift
6308 UINT64_C(1327510528), // SRSRAv4i32_shift
6309 UINT64_C(1326461952), // SRSRAv8i16_shift
6310 UINT64_C(252195840), // SRSRAv8i8_shift
6311 UINT64_C(1161863168), // SSHLLB_ZZI_D
6312 UINT64_C(1158193152), // SSHLLB_ZZI_H
6313 UINT64_C(1158717440), // SSHLLB_ZZI_S
6314 UINT64_C(1161864192), // SSHLLT_ZZI_D
6315 UINT64_C(1158194176), // SSHLLT_ZZI_H
6316 UINT64_C(1158718464), // SSHLLT_ZZI_S
6317 UINT64_C(1325966336), // SSHLLv16i8_shift
6318 UINT64_C(253797376), // SSHLLv2i32_shift
6319 UINT64_C(252748800), // SSHLLv4i16_shift
6320 UINT64_C(1327539200), // SSHLLv4i32_shift
6321 UINT64_C(1326490624), // SSHLLv8i16_shift
6322 UINT64_C(252224512), // SSHLLv8i8_shift
6323 UINT64_C(1310737408), // SSHLv16i8
6324 UINT64_C(1591755776), // SSHLv1i64
6325 UINT64_C(245384192), // SSHLv2i32
6326 UINT64_C(1323320320), // SSHLv2i64
6327 UINT64_C(241189888), // SSHLv4i16
6328 UINT64_C(1319126016), // SSHLv4i32
6329 UINT64_C(1314931712), // SSHLv8i16
6330 UINT64_C(236995584), // SSHLv8i8
6331 UINT64_C(1598030848), // SSHRd
6332 UINT64_C(1325925376), // SSHRv16i8_shift
6333 UINT64_C(253756416), // SSHRv2i32_shift
6334 UINT64_C(1329595392), // SSHRv2i64_shift
6335 UINT64_C(252707840), // SSHRv4i16_shift
6336 UINT64_C(1327498240), // SSHRv4i32_shift
6337 UINT64_C(1326449664), // SSHRv8i16_shift
6338 UINT64_C(252183552), // SSHRv8i8_shift
6339 UINT64_C(1158209536), // SSRA_ZZI_B
6340 UINT64_C(1166073856), // SSRA_ZZI_D
6341 UINT64_C(1158733824), // SSRA_ZZI_H
6342 UINT64_C(1161879552), // SSRA_ZZI_S
6343 UINT64_C(1598034944), // SSRAd
6344 UINT64_C(1325929472), // SSRAv16i8_shift
6345 UINT64_C(253760512), // SSRAv2i32_shift
6346 UINT64_C(1329599488), // SSRAv2i64_shift
6347 UINT64_C(252711936), // SSRAv4i16_shift
6348 UINT64_C(1327502336), // SSRAv4i32_shift
6349 UINT64_C(1326453760), // SSRAv8i16_shift
6350 UINT64_C(252187648), // SSRAv8i8_shift
6351 UINT64_C(3825246208), // SST1B_D
6352 UINT64_C(3829440512), // SST1B_D_IMM
6353 UINT64_C(3825254400), // SST1B_D_SXTW
6354 UINT64_C(3825238016), // SST1B_D_UXTW
6355 UINT64_C(3831537664), // SST1B_S_IMM
6356 UINT64_C(3829448704), // SST1B_S_SXTW
6357 UINT64_C(3829432320), // SST1B_S_UXTW
6358 UINT64_C(3850412032), // SST1D
6359 UINT64_C(3854606336), // SST1D_IMM
6360 UINT64_C(3852509184), // SST1D_SCALED
6361 UINT64_C(3850420224), // SST1D_SXTW
6362 UINT64_C(3852517376), // SST1D_SXTW_SCALED
6363 UINT64_C(3850403840), // SST1D_UXTW
6364 UINT64_C(3852500992), // SST1D_UXTW_SCALED
6365 UINT64_C(3833634816), // SST1H_D
6366 UINT64_C(3837829120), // SST1H_D_IMM
6367 UINT64_C(3835731968), // SST1H_D_SCALED
6368 UINT64_C(3833643008), // SST1H_D_SXTW
6369 UINT64_C(3835740160), // SST1H_D_SXTW_SCALED
6370 UINT64_C(3833626624), // SST1H_D_UXTW
6371 UINT64_C(3835723776), // SST1H_D_UXTW_SCALED
6372 UINT64_C(3839926272), // SST1H_S_IMM
6373 UINT64_C(3837837312), // SST1H_S_SXTW
6374 UINT64_C(3839934464), // SST1H_S_SXTW_SCALED
6375 UINT64_C(3837820928), // SST1H_S_UXTW
6376 UINT64_C(3839918080), // SST1H_S_UXTW_SCALED
6377 UINT64_C(3827310592), // SST1Q
6378 UINT64_C(3842023424), // SST1W_D
6379 UINT64_C(3846217728), // SST1W_D_IMM
6380 UINT64_C(3844120576), // SST1W_D_SCALED
6381 UINT64_C(3842031616), // SST1W_D_SXTW
6382 UINT64_C(3844128768), // SST1W_D_SXTW_SCALED
6383 UINT64_C(3842015232), // SST1W_D_UXTW
6384 UINT64_C(3844112384), // SST1W_D_UXTW_SCALED
6385 UINT64_C(3848314880), // SST1W_IMM
6386 UINT64_C(3846225920), // SST1W_SXTW
6387 UINT64_C(3848323072), // SST1W_SXTW_SCALED
6388 UINT64_C(3846209536), // SST1W_UXTW
6389 UINT64_C(3848306688), // SST1W_UXTW_SCALED
6390 UINT64_C(1170245632), // SSUBLBT_ZZZ_D
6391 UINT64_C(1161857024), // SSUBLBT_ZZZ_H
6392 UINT64_C(1166051328), // SSUBLBT_ZZZ_S
6393 UINT64_C(1170214912), // SSUBLB_ZZZ_D
6394 UINT64_C(1161826304), // SSUBLB_ZZZ_H
6395 UINT64_C(1166020608), // SSUBLB_ZZZ_S
6396 UINT64_C(1170246656), // SSUBLTB_ZZZ_D
6397 UINT64_C(1161858048), // SSUBLTB_ZZZ_H
6398 UINT64_C(1166052352), // SSUBLTB_ZZZ_S
6399 UINT64_C(1170215936), // SSUBLT_ZZZ_D
6400 UINT64_C(1161827328), // SSUBLT_ZZZ_H
6401 UINT64_C(1166021632), // SSUBLT_ZZZ_S
6402 UINT64_C(1310728192), // SSUBLv16i8_v8i16
6403 UINT64_C(245374976), // SSUBLv2i32_v2i64
6404 UINT64_C(241180672), // SSUBLv4i16_v4i32
6405 UINT64_C(1319116800), // SSUBLv4i32_v2i64
6406 UINT64_C(1314922496), // SSUBLv8i16_v4i32
6407 UINT64_C(236986368), // SSUBLv8i8_v8i16
6408 UINT64_C(1170231296), // SSUBWB_ZZZ_D
6409 UINT64_C(1161842688), // SSUBWB_ZZZ_H
6410 UINT64_C(1166036992), // SSUBWB_ZZZ_S
6411 UINT64_C(1170232320), // SSUBWT_ZZZ_D
6412 UINT64_C(1161843712), // SSUBWT_ZZZ_H
6413 UINT64_C(1166038016), // SSUBWT_ZZZ_S
6414 UINT64_C(1310732288), // SSUBWv16i8_v8i16
6415 UINT64_C(245379072), // SSUBWv2i32_v2i64
6416 UINT64_C(241184768), // SSUBWv4i16_v4i32
6417 UINT64_C(1319120896), // SSUBWv4i32_v2i64
6418 UINT64_C(1314926592), // SSUBWv8i16_v4i32
6419 UINT64_C(236990464), // SSUBWv8i8_v8i16
6420 UINT64_C(3825221632), // ST1B
6421 UINT64_C(2686451712), // ST1B_2Z
6422 UINT64_C(2690646016), // ST1B_2Z_IMM
6423 UINT64_C(2703228928), // ST1B_2Z_STRIDED
6424 UINT64_C(2707423232), // ST1B_2Z_STRIDED_IMM
6425 UINT64_C(2686484480), // ST1B_4Z
6426 UINT64_C(2690678784), // ST1B_4Z_IMM
6427 UINT64_C(2703261696), // ST1B_4Z_STRIDED
6428 UINT64_C(2707456000), // ST1B_4Z_STRIDED_IMM
6429 UINT64_C(3831513088), // ST1B_D
6430 UINT64_C(3831554048), // ST1B_D_IMM
6431 UINT64_C(3827318784), // ST1B_H
6432 UINT64_C(3827359744), // ST1B_H_IMM
6433 UINT64_C(3825262592), // ST1B_IMM
6434 UINT64_C(3829415936), // ST1B_S
6435 UINT64_C(3829456896), // ST1B_S_IMM
6436 UINT64_C(3856678912), // ST1D
6437 UINT64_C(2686476288), // ST1D_2Z
6438 UINT64_C(2690670592), // ST1D_2Z_IMM
6439 UINT64_C(2703253504), // ST1D_2Z_STRIDED
6440 UINT64_C(2707447808), // ST1D_2Z_STRIDED_IMM
6441 UINT64_C(2686509056), // ST1D_4Z
6442 UINT64_C(2690703360), // ST1D_4Z_IMM
6443 UINT64_C(2703286272), // ST1D_4Z_STRIDED
6444 UINT64_C(2707480576), // ST1D_4Z_STRIDED_IMM
6445 UINT64_C(3856719872), // ST1D_IMM
6446 UINT64_C(3854581760), // ST1D_Q
6447 UINT64_C(3854622720), // ST1D_Q_IMM
6448 UINT64_C(1275076608), // ST1Fourv16b
6449 UINT64_C(1283465216), // ST1Fourv16b_POST
6450 UINT64_C(201337856), // ST1Fourv1d
6451 UINT64_C(209726464), // ST1Fourv1d_POST
6452 UINT64_C(1275079680), // ST1Fourv2d
6453 UINT64_C(1283468288), // ST1Fourv2d_POST
6454 UINT64_C(201336832), // ST1Fourv2s
6455 UINT64_C(209725440), // ST1Fourv2s_POST
6456 UINT64_C(201335808), // ST1Fourv4h
6457 UINT64_C(209724416), // ST1Fourv4h_POST
6458 UINT64_C(1275078656), // ST1Fourv4s
6459 UINT64_C(1283467264), // ST1Fourv4s_POST
6460 UINT64_C(201334784), // ST1Fourv8b
6461 UINT64_C(209723392), // ST1Fourv8b_POST
6462 UINT64_C(1275077632), // ST1Fourv8h
6463 UINT64_C(1283466240), // ST1Fourv8h_POST
6464 UINT64_C(3835707392), // ST1H
6465 UINT64_C(2686459904), // ST1H_2Z
6466 UINT64_C(2690654208), // ST1H_2Z_IMM
6467 UINT64_C(2703237120), // ST1H_2Z_STRIDED
6468 UINT64_C(2707431424), // ST1H_2Z_STRIDED_IMM
6469 UINT64_C(2686492672), // ST1H_4Z
6470 UINT64_C(2690686976), // ST1H_4Z_IMM
6471 UINT64_C(2703269888), // ST1H_4Z_STRIDED
6472 UINT64_C(2707464192), // ST1H_4Z_STRIDED_IMM
6473 UINT64_C(3839901696), // ST1H_D
6474 UINT64_C(3839942656), // ST1H_D_IMM
6475 UINT64_C(3835748352), // ST1H_IMM
6476 UINT64_C(3837804544), // ST1H_S
6477 UINT64_C(3837845504), // ST1H_S_IMM
6478 UINT64_C(1275097088), // ST1Onev16b
6479 UINT64_C(1283485696), // ST1Onev16b_POST
6480 UINT64_C(201358336), // ST1Onev1d
6481 UINT64_C(209746944), // ST1Onev1d_POST
6482 UINT64_C(1275100160), // ST1Onev2d
6483 UINT64_C(1283488768), // ST1Onev2d_POST
6484 UINT64_C(201357312), // ST1Onev2s
6485 UINT64_C(209745920), // ST1Onev2s_POST
6486 UINT64_C(201356288), // ST1Onev4h
6487 UINT64_C(209744896), // ST1Onev4h_POST
6488 UINT64_C(1275099136), // ST1Onev4s
6489 UINT64_C(1283487744), // ST1Onev4s_POST
6490 UINT64_C(201355264), // ST1Onev8b
6491 UINT64_C(209743872), // ST1Onev8b_POST
6492 UINT64_C(1275098112), // ST1Onev8h
6493 UINT64_C(1283486720), // ST1Onev8h_POST
6494 UINT64_C(1275092992), // ST1Threev16b
6495 UINT64_C(1283481600), // ST1Threev16b_POST
6496 UINT64_C(201354240), // ST1Threev1d
6497 UINT64_C(209742848), // ST1Threev1d_POST
6498 UINT64_C(1275096064), // ST1Threev2d
6499 UINT64_C(1283484672), // ST1Threev2d_POST
6500 UINT64_C(201353216), // ST1Threev2s
6501 UINT64_C(209741824), // ST1Threev2s_POST
6502 UINT64_C(201352192), // ST1Threev4h
6503 UINT64_C(209740800), // ST1Threev4h_POST
6504 UINT64_C(1275095040), // ST1Threev4s
6505 UINT64_C(1283483648), // ST1Threev4s_POST
6506 UINT64_C(201351168), // ST1Threev8b
6507 UINT64_C(209739776), // ST1Threev8b_POST
6508 UINT64_C(1275094016), // ST1Threev8h
6509 UINT64_C(1283482624), // ST1Threev8h_POST
6510 UINT64_C(1275109376), // ST1Twov16b
6511 UINT64_C(1283497984), // ST1Twov16b_POST
6512 UINT64_C(201370624), // ST1Twov1d
6513 UINT64_C(209759232), // ST1Twov1d_POST
6514 UINT64_C(1275112448), // ST1Twov2d
6515 UINT64_C(1283501056), // ST1Twov2d_POST
6516 UINT64_C(201369600), // ST1Twov2s
6517 UINT64_C(209758208), // ST1Twov2s_POST
6518 UINT64_C(201368576), // ST1Twov4h
6519 UINT64_C(209757184), // ST1Twov4h_POST
6520 UINT64_C(1275111424), // ST1Twov4s
6521 UINT64_C(1283500032), // ST1Twov4s_POST
6522 UINT64_C(201367552), // ST1Twov8b
6523 UINT64_C(209756160), // ST1Twov8b_POST
6524 UINT64_C(1275110400), // ST1Twov8h
6525 UINT64_C(1283499008), // ST1Twov8h_POST
6526 UINT64_C(3846193152), // ST1W
6527 UINT64_C(2686468096), // ST1W_2Z
6528 UINT64_C(2690662400), // ST1W_2Z_IMM
6529 UINT64_C(2703245312), // ST1W_2Z_STRIDED
6530 UINT64_C(2707439616), // ST1W_2Z_STRIDED_IMM
6531 UINT64_C(2686500864), // ST1W_4Z
6532 UINT64_C(2690695168), // ST1W_4Z_IMM
6533 UINT64_C(2703278080), // ST1W_4Z_STRIDED
6534 UINT64_C(2707472384), // ST1W_4Z_STRIDED_IMM
6535 UINT64_C(3848290304), // ST1W_D
6536 UINT64_C(3848331264), // ST1W_D_IMM
6537 UINT64_C(3846234112), // ST1W_IMM
6538 UINT64_C(3841998848), // ST1W_Q
6539 UINT64_C(3842039808), // ST1W_Q_IMM
6540 UINT64_C(3760193536), // ST1_MXIPXX_H_B
6541 UINT64_C(3772776448), // ST1_MXIPXX_H_D
6542 UINT64_C(3764387840), // ST1_MXIPXX_H_H
6543 UINT64_C(3789553664), // ST1_MXIPXX_H_Q
6544 UINT64_C(3768582144), // ST1_MXIPXX_H_S
6545 UINT64_C(3760226304), // ST1_MXIPXX_V_B
6546 UINT64_C(3772809216), // ST1_MXIPXX_V_D
6547 UINT64_C(3764420608), // ST1_MXIPXX_V_H
6548 UINT64_C(3789586432), // ST1_MXIPXX_V_Q
6549 UINT64_C(3768614912), // ST1_MXIPXX_V_S
6550 UINT64_C(218120192), // ST1i16
6551 UINT64_C(226508800), // ST1i16_POST
6552 UINT64_C(218136576), // ST1i32
6553 UINT64_C(226525184), // ST1i32_POST
6554 UINT64_C(218137600), // ST1i64
6555 UINT64_C(226526208), // ST1i64_POST
6556 UINT64_C(218103808), // ST1i8
6557 UINT64_C(226492416), // ST1i8_POST
6558 UINT64_C(3827326976), // ST2B
6559 UINT64_C(3828408320), // ST2B_IMM
6560 UINT64_C(3852492800), // ST2D
6561 UINT64_C(3853574144), // ST2D_IMM
6562 UINT64_C(3651142656), // ST2GPostIndex
6563 UINT64_C(3651144704), // ST2GPreIndex
6564 UINT64_C(3651143680), // ST2Gi
6565 UINT64_C(3835715584), // ST2H
6566 UINT64_C(3836796928), // ST2H_IMM
6567 UINT64_C(3831496704), // ST2Q
6568 UINT64_C(3829399552), // ST2Q_IMM
6569 UINT64_C(1275101184), // ST2Twov16b
6570 UINT64_C(1283489792), // ST2Twov16b_POST
6571 UINT64_C(1275104256), // ST2Twov2d
6572 UINT64_C(1283492864), // ST2Twov2d_POST
6573 UINT64_C(201361408), // ST2Twov2s
6574 UINT64_C(209750016), // ST2Twov2s_POST
6575 UINT64_C(201360384), // ST2Twov4h
6576 UINT64_C(209748992), // ST2Twov4h_POST
6577 UINT64_C(1275103232), // ST2Twov4s
6578 UINT64_C(1283491840), // ST2Twov4s_POST
6579 UINT64_C(201359360), // ST2Twov8b
6580 UINT64_C(209747968), // ST2Twov8b_POST
6581 UINT64_C(1275102208), // ST2Twov8h
6582 UINT64_C(1283490816), // ST2Twov8h_POST
6583 UINT64_C(3844104192), // ST2W
6584 UINT64_C(3845185536), // ST2W_IMM
6585 UINT64_C(220217344), // ST2i16
6586 UINT64_C(228605952), // ST2i16_POST
6587 UINT64_C(220233728), // ST2i32
6588 UINT64_C(228622336), // ST2i32_POST
6589 UINT64_C(220234752), // ST2i64
6590 UINT64_C(228623360), // ST2i64_POST
6591 UINT64_C(220200960), // ST2i8
6592 UINT64_C(228589568), // ST2i8_POST
6593 UINT64_C(3829424128), // ST3B
6594 UINT64_C(3830505472), // ST3B_IMM
6595 UINT64_C(3854589952), // ST3D
6596 UINT64_C(3855671296), // ST3D_IMM
6597 UINT64_C(3837812736), // ST3H
6598 UINT64_C(3838894080), // ST3H_IMM
6599 UINT64_C(3835691008), // ST3Q
6600 UINT64_C(3833593856), // ST3Q_IMM
6601 UINT64_C(1275084800), // ST3Threev16b
6602 UINT64_C(1283473408), // ST3Threev16b_POST
6603 UINT64_C(1275087872), // ST3Threev2d
6604 UINT64_C(1283476480), // ST3Threev2d_POST
6605 UINT64_C(201345024), // ST3Threev2s
6606 UINT64_C(209733632), // ST3Threev2s_POST
6607 UINT64_C(201344000), // ST3Threev4h
6608 UINT64_C(209732608), // ST3Threev4h_POST
6609 UINT64_C(1275086848), // ST3Threev4s
6610 UINT64_C(1283475456), // ST3Threev4s_POST
6611 UINT64_C(201342976), // ST3Threev8b
6612 UINT64_C(209731584), // ST3Threev8b_POST
6613 UINT64_C(1275085824), // ST3Threev8h
6614 UINT64_C(1283474432), // ST3Threev8h_POST
6615 UINT64_C(3846201344), // ST3W
6616 UINT64_C(3847282688), // ST3W_IMM
6617 UINT64_C(218128384), // ST3i16
6618 UINT64_C(226516992), // ST3i16_POST
6619 UINT64_C(218144768), // ST3i32
6620 UINT64_C(226533376), // ST3i32_POST
6621 UINT64_C(218145792), // ST3i64
6622 UINT64_C(226534400), // ST3i64_POST
6623 UINT64_C(218112000), // ST3i8
6624 UINT64_C(226500608), // ST3i8_POST
6625 UINT64_C(3831521280), // ST4B
6626 UINT64_C(3832602624), // ST4B_IMM
6627 UINT64_C(3856687104), // ST4D
6628 UINT64_C(3857768448), // ST4D_IMM
6629 UINT64_C(1275068416), // ST4Fourv16b
6630 UINT64_C(1283457024), // ST4Fourv16b_POST
6631 UINT64_C(1275071488), // ST4Fourv2d
6632 UINT64_C(1283460096), // ST4Fourv2d_POST
6633 UINT64_C(201328640), // ST4Fourv2s
6634 UINT64_C(209717248), // ST4Fourv2s_POST
6635 UINT64_C(201327616), // ST4Fourv4h
6636 UINT64_C(209716224), // ST4Fourv4h_POST
6637 UINT64_C(1275070464), // ST4Fourv4s
6638 UINT64_C(1283459072), // ST4Fourv4s_POST
6639 UINT64_C(201326592), // ST4Fourv8b
6640 UINT64_C(209715200), // ST4Fourv8b_POST
6641 UINT64_C(1275069440), // ST4Fourv8h
6642 UINT64_C(1283458048), // ST4Fourv8h_POST
6643 UINT64_C(3839909888), // ST4H
6644 UINT64_C(3840991232), // ST4H_IMM
6645 UINT64_C(3839885312), // ST4Q
6646 UINT64_C(3837788160), // ST4Q_IMM
6647 UINT64_C(3848298496), // ST4W
6648 UINT64_C(3849379840), // ST4W_IMM
6649 UINT64_C(220225536), // ST4i16
6650 UINT64_C(228614144), // ST4i16_POST
6651 UINT64_C(220241920), // ST4i32
6652 UINT64_C(228630528), // ST4i32_POST
6653 UINT64_C(220242944), // ST4i64
6654 UINT64_C(228631552), // ST4i64_POST
6655 UINT64_C(220209152), // ST4i8
6656 UINT64_C(228597760), // ST4i8_POST
6657 UINT64_C(4164915200), // ST64B
6658 UINT64_C(4162891776), // ST64BV
6659 UINT64_C(4162887680), // ST64BV0
6660 UINT64_C(3651141632), // STGM
6661 UINT64_C(1761607680), // STGPi
6662 UINT64_C(3642754048), // STGPostIndex
6663 UINT64_C(1753219072), // STGPpost
6664 UINT64_C(1769996288), // STGPpre
6665 UINT64_C(3642756096), // STGPreIndex
6666 UINT64_C(3642755072), // STGi
6667 UINT64_C(2566920192), // STILPW
6668 UINT64_C(2566916096), // STILPWpre
6669 UINT64_C(3640662016), // STILPX
6670 UINT64_C(3640657920), // STILPXpre
6671 UINT64_C(218203136), // STL1
6672 UINT64_C(144669696), // STLLRB
6673 UINT64_C(1218411520), // STLLRH
6674 UINT64_C(2292153344), // STLLRW
6675 UINT64_C(3365895168), // STLLRX
6676 UINT64_C(144702464), // STLRB
6677 UINT64_C(1218444288), // STLRH
6678 UINT64_C(2292186112), // STLRW
6679 UINT64_C(2575304704), // STLRWpre
6680 UINT64_C(3365927936), // STLRX
6681 UINT64_C(3649046528), // STLRXpre
6682 UINT64_C(419430400), // STLURBi
6683 UINT64_C(1493172224), // STLURHi
6684 UINT64_C(2566914048), // STLURWi
6685 UINT64_C(3640655872), // STLURXi
6686 UINT64_C(486541312), // STLURbi
6687 UINT64_C(3707766784), // STLURdi
6688 UINT64_C(1560283136), // STLURhi
6689 UINT64_C(494929920), // STLURqi
6690 UINT64_C(2634024960), // STLURsi
6691 UINT64_C(2283831296), // STLXPW
6692 UINT64_C(3357573120), // STLXPX
6693 UINT64_C(134250496), // STLXRB
6694 UINT64_C(1207992320), // STLXRH
6695 UINT64_C(2281734144), // STLXRW
6696 UINT64_C(3355475968), // STLXRX
6697 UINT64_C(1811939328), // STNPDi
6698 UINT64_C(2885681152), // STNPQi
6699 UINT64_C(738197504), // STNPSi
6700 UINT64_C(671088640), // STNPWi
6701 UINT64_C(2818572288), // STNPXi
6702 UINT64_C(2686451713), // STNT1B_2Z
6703 UINT64_C(2690646017), // STNT1B_2Z_IMM
6704 UINT64_C(2703228936), // STNT1B_2Z_STRIDED
6705 UINT64_C(2707423240), // STNT1B_2Z_STRIDED_IMM
6706 UINT64_C(2686484481), // STNT1B_4Z
6707 UINT64_C(2690678785), // STNT1B_4Z_IMM
6708 UINT64_C(2703261704), // STNT1B_4Z_STRIDED
6709 UINT64_C(2707456008), // STNT1B_4Z_STRIDED_IMM
6710 UINT64_C(3826311168), // STNT1B_ZRI
6711 UINT64_C(3825229824), // STNT1B_ZRR
6712 UINT64_C(3825213440), // STNT1B_ZZR_D
6713 UINT64_C(3829407744), // STNT1B_ZZR_S
6714 UINT64_C(2686476289), // STNT1D_2Z
6715 UINT64_C(2690670593), // STNT1D_2Z_IMM
6716 UINT64_C(2703253512), // STNT1D_2Z_STRIDED
6717 UINT64_C(2707447816), // STNT1D_2Z_STRIDED_IMM
6718 UINT64_C(2686509057), // STNT1D_4Z
6719 UINT64_C(2690703361), // STNT1D_4Z_IMM
6720 UINT64_C(2703286280), // STNT1D_4Z_STRIDED
6721 UINT64_C(2707480584), // STNT1D_4Z_STRIDED_IMM
6722 UINT64_C(3851476992), // STNT1D_ZRI
6723 UINT64_C(3850395648), // STNT1D_ZRR
6724 UINT64_C(3850379264), // STNT1D_ZZR_D
6725 UINT64_C(2686459905), // STNT1H_2Z
6726 UINT64_C(2690654209), // STNT1H_2Z_IMM
6727 UINT64_C(2703237128), // STNT1H_2Z_STRIDED
6728 UINT64_C(2707431432), // STNT1H_2Z_STRIDED_IMM
6729 UINT64_C(2686492673), // STNT1H_4Z
6730 UINT64_C(2690686977), // STNT1H_4Z_IMM
6731 UINT64_C(2703269896), // STNT1H_4Z_STRIDED
6732 UINT64_C(2707464200), // STNT1H_4Z_STRIDED_IMM
6733 UINT64_C(3834699776), // STNT1H_ZRI
6734 UINT64_C(3833618432), // STNT1H_ZRR
6735 UINT64_C(3833602048), // STNT1H_ZZR_D
6736 UINT64_C(3837796352), // STNT1H_ZZR_S
6737 UINT64_C(2686468097), // STNT1W_2Z
6738 UINT64_C(2690662401), // STNT1W_2Z_IMM
6739 UINT64_C(2703245320), // STNT1W_2Z_STRIDED
6740 UINT64_C(2707439624), // STNT1W_2Z_STRIDED_IMM
6741 UINT64_C(2686500865), // STNT1W_4Z
6742 UINT64_C(2690695169), // STNT1W_4Z_IMM
6743 UINT64_C(2703278088), // STNT1W_4Z_STRIDED
6744 UINT64_C(2707472392), // STNT1W_4Z_STRIDED_IMM
6745 UINT64_C(3843088384), // STNT1W_ZRI
6746 UINT64_C(3842007040), // STNT1W_ZRR
6747 UINT64_C(3841990656), // STNT1W_ZZR_D
6748 UINT64_C(3846184960), // STNT1W_ZZR_S
6749 UINT64_C(1828716544), // STPDi
6750 UINT64_C(1820327936), // STPDpost
6751 UINT64_C(1837105152), // STPDpre
6752 UINT64_C(2902458368), // STPQi
6753 UINT64_C(2894069760), // STPQpost
6754 UINT64_C(2910846976), // STPQpre
6755 UINT64_C(754974720), // STPSi
6756 UINT64_C(746586112), // STPSpost
6757 UINT64_C(763363328), // STPSpre
6758 UINT64_C(687865856), // STPWi
6759 UINT64_C(679477248), // STPWpost
6760 UINT64_C(696254464), // STPWpre
6761 UINT64_C(2835349504), // STPXi
6762 UINT64_C(2826960896), // STPXpost
6763 UINT64_C(2843738112), // STPXpre
6764 UINT64_C(939525120), // STRBBpost
6765 UINT64_C(939527168), // STRBBpre
6766 UINT64_C(941639680), // STRBBroW
6767 UINT64_C(941647872), // STRBBroX
6768 UINT64_C(956301312), // STRBBui
6769 UINT64_C(1006633984), // STRBpost
6770 UINT64_C(1006636032), // STRBpre
6771 UINT64_C(1008748544), // STRBroW
6772 UINT64_C(1008756736), // STRBroX
6773 UINT64_C(1023410176), // STRBui
6774 UINT64_C(4227859456), // STRDpost
6775 UINT64_C(4227861504), // STRDpre
6776 UINT64_C(4229974016), // STRDroW
6777 UINT64_C(4229982208), // STRDroX
6778 UINT64_C(4244635648), // STRDui
6779 UINT64_C(2013266944), // STRHHpost
6780 UINT64_C(2013268992), // STRHHpre
6781 UINT64_C(2015381504), // STRHHroW
6782 UINT64_C(2015389696), // STRHHroX
6783 UINT64_C(2030043136), // STRHHui
6784 UINT64_C(2080375808), // STRHpost
6785 UINT64_C(2080377856), // STRHpre
6786 UINT64_C(2082490368), // STRHroW
6787 UINT64_C(2082498560), // STRHroX
6788 UINT64_C(2097152000), // STRHui
6789 UINT64_C(1015022592), // STRQpost
6790 UINT64_C(1015024640), // STRQpre
6791 UINT64_C(1017137152), // STRQroW
6792 UINT64_C(1017145344), // STRQroX
6793 UINT64_C(1031798784), // STRQui
6794 UINT64_C(3154117632), // STRSpost
6795 UINT64_C(3154119680), // STRSpre
6796 UINT64_C(3156232192), // STRSroW
6797 UINT64_C(3156240384), // STRSroX
6798 UINT64_C(3170893824), // STRSui
6799 UINT64_C(3087008768), // STRWpost
6800 UINT64_C(3087010816), // STRWpre
6801 UINT64_C(3089123328), // STRWroW
6802 UINT64_C(3089131520), // STRWroX
6803 UINT64_C(3103784960), // STRWui
6804 UINT64_C(4160750592), // STRXpost
6805 UINT64_C(4160752640), // STRXpre
6806 UINT64_C(4162865152), // STRXroW
6807 UINT64_C(4162873344), // STRXroX
6808 UINT64_C(4177526784), // STRXui
6809 UINT64_C(3850371072), // STR_PXI
6810 UINT64_C(3779035136), // STR_TX
6811 UINT64_C(3776970752), // STR_ZA
6812 UINT64_C(3850387456), // STR_ZXI
6813 UINT64_C(939526144), // STTRBi
6814 UINT64_C(2013267968), // STTRHi
6815 UINT64_C(3087009792), // STTRWi
6816 UINT64_C(4160751616), // STTRXi
6817 UINT64_C(939524096), // STURBBi
6818 UINT64_C(1006632960), // STURBi
6819 UINT64_C(4227858432), // STURDi
6820 UINT64_C(2013265920), // STURHHi
6821 UINT64_C(2080374784), // STURHi
6822 UINT64_C(1015021568), // STURQi
6823 UINT64_C(3154116608), // STURSi
6824 UINT64_C(3087007744), // STURWi
6825 UINT64_C(4160749568), // STURXi
6826 UINT64_C(2283798528), // STXPW
6827 UINT64_C(3357540352), // STXPX
6828 UINT64_C(134217728), // STXRB
6829 UINT64_C(1207959552), // STXRH
6830 UINT64_C(2281701376), // STXRW
6831 UINT64_C(3355443200), // STXRX
6832 UINT64_C(3655336960), // STZ2GPostIndex
6833 UINT64_C(3655339008), // STZ2GPreIndex
6834 UINT64_C(3655337984), // STZ2Gi
6835 UINT64_C(3642753024), // STZGM
6836 UINT64_C(3646948352), // STZGPostIndex
6837 UINT64_C(3646950400), // STZGPreIndex
6838 UINT64_C(3646949376), // STZGi
6839 UINT64_C(3514826752), // SUBG
6840 UINT64_C(1163948032), // SUBHNB_ZZZ_B
6841 UINT64_C(1168142336), // SUBHNB_ZZZ_H
6842 UINT64_C(1172336640), // SUBHNB_ZZZ_S
6843 UINT64_C(1163949056), // SUBHNT_ZZZ_B
6844 UINT64_C(1168143360), // SUBHNT_ZZZ_H
6845 UINT64_C(1172337664), // SUBHNT_ZZZ_S
6846 UINT64_C(245391360), // SUBHNv2i64_v2i32
6847 UINT64_C(1319133184), // SUBHNv2i64_v4i32
6848 UINT64_C(241197056), // SUBHNv4i32_v4i16
6849 UINT64_C(1314938880), // SUBHNv4i32_v8i16
6850 UINT64_C(1310744576), // SUBHNv8i16_v16i8
6851 UINT64_C(237002752), // SUBHNv8i16_v8i8
6852 UINT64_C(2596274176), // SUBP
6853 UINT64_C(3133145088), // SUBPS
6854 UINT64_C(3657441280), // SUBPT_shift
6855 UINT64_C(623099904), // SUBR_ZI_B
6856 UINT64_C(635682816), // SUBR_ZI_D
6857 UINT64_C(627294208), // SUBR_ZI_H
6858 UINT64_C(631488512), // SUBR_ZI_S
6859 UINT64_C(67305472), // SUBR_ZPmZ_B
6860 UINT64_C(79888384), // SUBR_ZPmZ_D
6861 UINT64_C(71499776), // SUBR_ZPmZ_H
6862 UINT64_C(75694080), // SUBR_ZPmZ_S
6863 UINT64_C(1895825408), // SUBSWri
6864 UINT64_C(1795162112), // SUBSWrs
6865 UINT64_C(1797259264), // SUBSWrx
6866 UINT64_C(4043309056), // SUBSXri
6867 UINT64_C(3942645760), // SUBSXrs
6868 UINT64_C(3944742912), // SUBSXrx
6869 UINT64_C(3944767488), // SUBSXrx64
6870 UINT64_C(1358954496), // SUBWri
6871 UINT64_C(1258291200), // SUBWrs
6872 UINT64_C(1260388352), // SUBWrx
6873 UINT64_C(3506438144), // SUBXri
6874 UINT64_C(3405774848), // SUBXrs
6875 UINT64_C(3407872000), // SUBXrx
6876 UINT64_C(3407896576), // SUBXrx64
6877 UINT64_C(3252688920), // SUB_VG2_M2Z2Z_D
6878 UINT64_C(3248494616), // SUB_VG2_M2Z2Z_S
6879 UINT64_C(3244300312), // SUB_VG2_M2ZZ_D
6880 UINT64_C(3240106008), // SUB_VG2_M2ZZ_S
6881 UINT64_C(3252689944), // SUB_VG2_M2Z_D
6882 UINT64_C(3248495640), // SUB_VG2_M2Z_S
6883 UINT64_C(3252754456), // SUB_VG4_M4Z4Z_D
6884 UINT64_C(3248560152), // SUB_VG4_M4Z4Z_S
6885 UINT64_C(3245348888), // SUB_VG4_M4ZZ_D
6886 UINT64_C(3241154584), // SUB_VG4_M4ZZ_S
6887 UINT64_C(3252755480), // SUB_VG4_M4Z_D
6888 UINT64_C(3248561176), // SUB_VG4_M4Z_S
6889 UINT64_C(622968832), // SUB_ZI_B
6890 UINT64_C(635551744), // SUB_ZI_D
6891 UINT64_C(627163136), // SUB_ZI_H
6892 UINT64_C(631357440), // SUB_ZI_S
6893 UINT64_C(67174400), // SUB_ZPmZ_B
6894 UINT64_C(80019456), // SUB_ZPmZ_CPA
6895 UINT64_C(79757312), // SUB_ZPmZ_D
6896 UINT64_C(71368704), // SUB_ZPmZ_H
6897 UINT64_C(75563008), // SUB_ZPmZ_S
6898 UINT64_C(69207040), // SUB_ZZZ_B
6899 UINT64_C(81792000), // SUB_ZZZ_CPA
6900 UINT64_C(81789952), // SUB_ZZZ_D
6901 UINT64_C(73401344), // SUB_ZZZ_H
6902 UINT64_C(77595648), // SUB_ZZZ_S
6903 UINT64_C(1847624704), // SUBv16i8
6904 UINT64_C(2128643072), // SUBv1i64
6905 UINT64_C(782271488), // SUBv2i32
6906 UINT64_C(1860207616), // SUBv2i64
6907 UINT64_C(778077184), // SUBv4i16
6908 UINT64_C(1856013312), // SUBv4i32
6909 UINT64_C(1851819008), // SUBv8i16
6910 UINT64_C(773882880), // SUBv8i8
6911 UINT64_C(3243249720), // SUDOT_VG2_M2ZZI_BToS
6912 UINT64_C(3240104984), // SUDOT_VG2_M2ZZ_BToS
6913 UINT64_C(3243282488), // SUDOT_VG4_M4ZZI_BToS
6914 UINT64_C(3241153560), // SUDOT_VG4_M4ZZ_BToS
6915 UINT64_C(1151343616), // SUDOT_ZZZI
6916 UINT64_C(1325461504), // SUDOTlanev16i8
6917 UINT64_C(251719680), // SUDOTlanev8i8
6918 UINT64_C(3238002708), // SUMLALL_MZZI_BtoS
6919 UINT64_C(3239051312), // SUMLALL_VG2_M2ZZI_BtoS
6920 UINT64_C(3240099860), // SUMLALL_VG2_M2ZZ_BtoS
6921 UINT64_C(3239084080), // SUMLALL_VG4_M4ZZI_BtoS
6922 UINT64_C(3241148436), // SUMLALL_VG4_M4ZZ_BtoS
6923 UINT64_C(2699034624), // SUMOPA_MPPZZ_D
6924 UINT64_C(2694840320), // SUMOPA_MPPZZ_S
6925 UINT64_C(2699034640), // SUMOPS_MPPZZ_D
6926 UINT64_C(2694840336), // SUMOPS_MPPZZ_S
6927 UINT64_C(99694592), // SUNPKHI_ZZ_D
6928 UINT64_C(91305984), // SUNPKHI_ZZ_H
6929 UINT64_C(95500288), // SUNPKHI_ZZ_S
6930 UINT64_C(99629056), // SUNPKLO_ZZ_D
6931 UINT64_C(91240448), // SUNPKLO_ZZ_H
6932 UINT64_C(95434752), // SUNPKLO_ZZ_S
6933 UINT64_C(3253067776), // SUNPK_VG2_2ZZ_D
6934 UINT64_C(3244679168), // SUNPK_VG2_2ZZ_H
6935 UINT64_C(3248873472), // SUNPK_VG2_2ZZ_S
6936 UINT64_C(3254116352), // SUNPK_VG4_4Z2Z_D
6937 UINT64_C(3245727744), // SUNPK_VG4_4Z2Z_H
6938 UINT64_C(3249922048), // SUNPK_VG4_4Z2Z_S
6939 UINT64_C(1142718464), // SUQADD_ZPmZ_B
6940 UINT64_C(1155301376), // SUQADD_ZPmZ_D
6941 UINT64_C(1146912768), // SUQADD_ZPmZ_H
6942 UINT64_C(1151107072), // SUQADD_ZPmZ_S
6943 UINT64_C(1310734336), // SUQADDv16i8
6944 UINT64_C(1583364096), // SUQADDv1i16
6945 UINT64_C(1587558400), // SUQADDv1i32
6946 UINT64_C(1591752704), // SUQADDv1i64
6947 UINT64_C(1579169792), // SUQADDv1i8
6948 UINT64_C(245381120), // SUQADDv2i32
6949 UINT64_C(1323317248), // SUQADDv2i64
6950 UINT64_C(241186816), // SUQADDv4i16
6951 UINT64_C(1319122944), // SUQADDv4i32
6952 UINT64_C(1314928640), // SUQADDv8i16
6953 UINT64_C(236992512), // SUQADDv8i8
6954 UINT64_C(3243278392), // SUVDOT_VG4_M4ZZI_BToS
6955 UINT64_C(3556769793), // SVC
6956 UINT64_C(3243245600), // SVDOT_VG2_M2ZZI_HtoS
6957 UINT64_C(3243278368), // SVDOT_VG4_M4ZZI_BtoS
6958 UINT64_C(3251669000), // SVDOT_VG4_M4ZZI_HtoD
6959 UINT64_C(950042624), // SWPAB
6960 UINT64_C(2023784448), // SWPAH
6961 UINT64_C(954236928), // SWPALB
6962 UINT64_C(2027978752), // SWPALH
6963 UINT64_C(3101720576), // SWPALW
6964 UINT64_C(4175462400), // SWPALX
6965 UINT64_C(3097526272), // SWPAW
6966 UINT64_C(4171268096), // SWPAX
6967 UINT64_C(941654016), // SWPB
6968 UINT64_C(2015395840), // SWPH
6969 UINT64_C(945848320), // SWPLB
6970 UINT64_C(2019590144), // SWPLH
6971 UINT64_C(3093331968), // SWPLW
6972 UINT64_C(4167073792), // SWPLX
6973 UINT64_C(421560320), // SWPP
6974 UINT64_C(429948928), // SWPPA
6975 UINT64_C(434143232), // SWPPAL
6976 UINT64_C(425754624), // SWPPL
6977 UINT64_C(3089137664), // SWPW
6978 UINT64_C(4162879488), // SWPX
6979 UINT64_C(80781312), // SXTB_ZPmZ_D
6980 UINT64_C(72392704), // SXTB_ZPmZ_H
6981 UINT64_C(76587008), // SXTB_ZPmZ_S
6982 UINT64_C(80912384), // SXTH_ZPmZ_D
6983 UINT64_C(76718080), // SXTH_ZPmZ_S
6984 UINT64_C(81043456), // SXTW_ZPmZ_D
6985 UINT64_C(3576168448), // SYSLxt
6986 UINT64_C(3578265600), // SYSPxt
6987 UINT64_C(3578265631), // SYSPxt_XZR
6988 UINT64_C(3574071296), // SYSxt
6989 UINT64_C(1140914176), // TBLQ_ZZZ_B
6990 UINT64_C(1153497088), // TBLQ_ZZZ_D
6991 UINT64_C(1145108480), // TBLQ_ZZZ_H
6992 UINT64_C(1149302784), // TBLQ_ZZZ_S
6993 UINT64_C(85993472), // TBL_ZZZZ_B
6994 UINT64_C(98576384), // TBL_ZZZZ_D
6995 UINT64_C(90187776), // TBL_ZZZZ_H
6996 UINT64_C(94382080), // TBL_ZZZZ_S
6997 UINT64_C(85995520), // TBL_ZZZ_B
6998 UINT64_C(98578432), // TBL_ZZZ_D
6999 UINT64_C(90189824), // TBL_ZZZ_H
7000 UINT64_C(94384128), // TBL_ZZZ_S
7001 UINT64_C(1308647424), // TBLv16i8Four
7002 UINT64_C(1308622848), // TBLv16i8One
7003 UINT64_C(1308639232), // TBLv16i8Three
7004 UINT64_C(1308631040), // TBLv16i8Two
7005 UINT64_C(234905600), // TBLv8i8Four
7006 UINT64_C(234881024), // TBLv8i8One
7007 UINT64_C(234897408), // TBLv8i8Three
7008 UINT64_C(234889216), // TBLv8i8Two
7009 UINT64_C(922746880), // TBNZW
7010 UINT64_C(3070230528), // TBNZX
7011 UINT64_C(85996544), // TBXQ_ZZZ_B
7012 UINT64_C(98579456), // TBXQ_ZZZ_D
7013 UINT64_C(90190848), // TBXQ_ZZZ_H
7014 UINT64_C(94385152), // TBXQ_ZZZ_S
7015 UINT64_C(85994496), // TBX_ZZZ_B
7016 UINT64_C(98577408), // TBX_ZZZ_D
7017 UINT64_C(90188800), // TBX_ZZZ_H
7018 UINT64_C(94383104), // TBX_ZZZ_S
7019 UINT64_C(1308651520), // TBXv16i8Four
7020 UINT64_C(1308626944), // TBXv16i8One
7021 UINT64_C(1308643328), // TBXv16i8Three
7022 UINT64_C(1308635136), // TBXv16i8Two
7023 UINT64_C(234909696), // TBXv8i8Four
7024 UINT64_C(234885120), // TBXv8i8One
7025 UINT64_C(234901504), // TBXv8i8Three
7026 UINT64_C(234893312), // TBXv8i8Two
7027 UINT64_C(905969664), // TBZW
7028 UINT64_C(3053453312), // TBZX
7029 UINT64_C(3563061248), // TCANCEL
7030 UINT64_C(3573756031), // TCOMMIT
7031 UINT64_C(3574297312), // TRCIT
7032 UINT64_C(86003712), // TRN1_PPP_B
7033 UINT64_C(98586624), // TRN1_PPP_D
7034 UINT64_C(90198016), // TRN1_PPP_H
7035 UINT64_C(94392320), // TRN1_PPP_S
7036 UINT64_C(86011904), // TRN1_ZZZ_B
7037 UINT64_C(98594816), // TRN1_ZZZ_D
7038 UINT64_C(90206208), // TRN1_ZZZ_H
7039 UINT64_C(94377984), // TRN1_ZZZ_Q
7040 UINT64_C(94400512), // TRN1_ZZZ_S
7041 UINT64_C(1308633088), // TRN1v16i8
7042 UINT64_C(243279872), // TRN1v2i32
7043 UINT64_C(1321216000), // TRN1v2i64
7044 UINT64_C(239085568), // TRN1v4i16
7045 UINT64_C(1317021696), // TRN1v4i32
7046 UINT64_C(1312827392), // TRN1v8i16
7047 UINT64_C(234891264), // TRN1v8i8
7048 UINT64_C(86004736), // TRN2_PPP_B
7049 UINT64_C(98587648), // TRN2_PPP_D
7050 UINT64_C(90199040), // TRN2_PPP_H
7051 UINT64_C(94393344), // TRN2_PPP_S
7052 UINT64_C(86012928), // TRN2_ZZZ_B
7053 UINT64_C(98595840), // TRN2_ZZZ_D
7054 UINT64_C(90207232), // TRN2_ZZZ_H
7055 UINT64_C(94379008), // TRN2_ZZZ_Q
7056 UINT64_C(94401536), // TRN2_ZZZ_S
7057 UINT64_C(1308649472), // TRN2v16i8
7058 UINT64_C(243296256), // TRN2v2i32
7059 UINT64_C(1321232384), // TRN2v2i64
7060 UINT64_C(239101952), // TRN2v4i16
7061 UINT64_C(1317038080), // TRN2v4i32
7062 UINT64_C(1312843776), // TRN2v8i16
7063 UINT64_C(234907648), // TRN2v8i8
7064 UINT64_C(3573752415), // TSB
7065 UINT64_C(3575853152), // TSTART
7066 UINT64_C(3575853408), // TTEST
7067 UINT64_C(1170262016), // UABALB_ZZZ_D
7068 UINT64_C(1161873408), // UABALB_ZZZ_H
7069 UINT64_C(1166067712), // UABALB_ZZZ_S
7070 UINT64_C(1170263040), // UABALT_ZZZ_D
7071 UINT64_C(1161874432), // UABALT_ZZZ_H
7072 UINT64_C(1166068736), // UABALT_ZZZ_S
7073 UINT64_C(1847611392), // UABALv16i8_v8i16
7074 UINT64_C(782258176), // UABALv2i32_v2i64
7075 UINT64_C(778063872), // UABALv4i16_v4i32
7076 UINT64_C(1856000000), // UABALv4i32_v2i64
7077 UINT64_C(1851805696), // UABALv8i16_v4i32
7078 UINT64_C(773869568), // UABALv8i8_v8i16
7079 UINT64_C(1157692416), // UABA_ZZZ_B
7080 UINT64_C(1170275328), // UABA_ZZZ_D
7081 UINT64_C(1161886720), // UABA_ZZZ_H
7082 UINT64_C(1166081024), // UABA_ZZZ_S
7083 UINT64_C(1847622656), // UABAv16i8
7084 UINT64_C(782269440), // UABAv2i32
7085 UINT64_C(778075136), // UABAv4i16
7086 UINT64_C(1856011264), // UABAv4i32
7087 UINT64_C(1851816960), // UABAv8i16
7088 UINT64_C(773880832), // UABAv8i8
7089 UINT64_C(1170225152), // UABDLB_ZZZ_D
7090 UINT64_C(1161836544), // UABDLB_ZZZ_H
7091 UINT64_C(1166030848), // UABDLB_ZZZ_S
7092 UINT64_C(1170226176), // UABDLT_ZZZ_D
7093 UINT64_C(1161837568), // UABDLT_ZZZ_H
7094 UINT64_C(1166031872), // UABDLT_ZZZ_S
7095 UINT64_C(1847619584), // UABDLv16i8_v8i16
7096 UINT64_C(782266368), // UABDLv2i32_v2i64
7097 UINT64_C(778072064), // UABDLv4i16_v4i32
7098 UINT64_C(1856008192), // UABDLv4i32_v2i64
7099 UINT64_C(1851813888), // UABDLv8i16_v4i32
7100 UINT64_C(773877760), // UABDLv8i8_v8i16
7101 UINT64_C(67960832), // UABD_ZPmZ_B
7102 UINT64_C(80543744), // UABD_ZPmZ_D
7103 UINT64_C(72155136), // UABD_ZPmZ_H
7104 UINT64_C(76349440), // UABD_ZPmZ_S
7105 UINT64_C(1847620608), // UABDv16i8
7106 UINT64_C(782267392), // UABDv2i32
7107 UINT64_C(778073088), // UABDv4i16
7108 UINT64_C(1856009216), // UABDv4i32
7109 UINT64_C(1851814912), // UABDv8i16
7110 UINT64_C(773878784), // UABDv8i8
7111 UINT64_C(1153802240), // UADALP_ZPmZ_D
7112 UINT64_C(1145413632), // UADALP_ZPmZ_H
7113 UINT64_C(1149607936), // UADALP_ZPmZ_S
7114 UINT64_C(1847617536), // UADALPv16i8_v8i16
7115 UINT64_C(782264320), // UADALPv2i32_v1i64
7116 UINT64_C(778070016), // UADALPv4i16_v2i32
7117 UINT64_C(1856006144), // UADALPv4i32_v2i64
7118 UINT64_C(1851811840), // UADALPv8i16_v4i32
7119 UINT64_C(773875712), // UADALPv8i8_v4i16
7120 UINT64_C(1170212864), // UADDLB_ZZZ_D
7121 UINT64_C(1161824256), // UADDLB_ZZZ_H
7122 UINT64_C(1166018560), // UADDLB_ZZZ_S
7123 UINT64_C(1847601152), // UADDLPv16i8_v8i16
7124 UINT64_C(782247936), // UADDLPv2i32_v1i64
7125 UINT64_C(778053632), // UADDLPv4i16_v2i32
7126 UINT64_C(1855989760), // UADDLPv4i32_v2i64
7127 UINT64_C(1851795456), // UADDLPv8i16_v4i32
7128 UINT64_C(773859328), // UADDLPv8i8_v4i16
7129 UINT64_C(1170213888), // UADDLT_ZZZ_D
7130 UINT64_C(1161825280), // UADDLT_ZZZ_H
7131 UINT64_C(1166019584), // UADDLT_ZZZ_S
7132 UINT64_C(1848653824), // UADDLVv16i8v
7133 UINT64_C(779106304), // UADDLVv4i16v
7134 UINT64_C(1857042432), // UADDLVv4i32v
7135 UINT64_C(1852848128), // UADDLVv8i16v
7136 UINT64_C(774912000), // UADDLVv8i8v
7137 UINT64_C(1847590912), // UADDLv16i8_v8i16
7138 UINT64_C(782237696), // UADDLv2i32_v2i64
7139 UINT64_C(778043392), // UADDLv4i16_v4i32
7140 UINT64_C(1855979520), // UADDLv4i32_v2i64
7141 UINT64_C(1851785216), // UADDLv8i16_v4i32
7142 UINT64_C(773849088), // UADDLv8i8_v8i16
7143 UINT64_C(67182592), // UADDV_VPZ_B
7144 UINT64_C(79765504), // UADDV_VPZ_D
7145 UINT64_C(71376896), // UADDV_VPZ_H
7146 UINT64_C(75571200), // UADDV_VPZ_S
7147 UINT64_C(1170229248), // UADDWB_ZZZ_D
7148 UINT64_C(1161840640), // UADDWB_ZZZ_H
7149 UINT64_C(1166034944), // UADDWB_ZZZ_S
7150 UINT64_C(1170230272), // UADDWT_ZZZ_D
7151 UINT64_C(1161841664), // UADDWT_ZZZ_H
7152 UINT64_C(1166035968), // UADDWT_ZZZ_S
7153 UINT64_C(1847595008), // UADDWv16i8_v8i16
7154 UINT64_C(782241792), // UADDWv2i32_v2i64
7155 UINT64_C(778047488), // UADDWv4i16_v4i32
7156 UINT64_C(1855983616), // UADDWv4i32_v2i64
7157 UINT64_C(1851789312), // UADDWv8i16_v4i32
7158 UINT64_C(773853184), // UADDWv8i8_v8i16
7159 UINT64_C(1392508928), // UBFMWri
7160 UINT64_C(3544186880), // UBFMXri
7161 UINT64_C(3240150017), // UCLAMP_VG2_2Z2Z_B
7162 UINT64_C(3252732929), // UCLAMP_VG2_2Z2Z_D
7163 UINT64_C(3244344321), // UCLAMP_VG2_2Z2Z_H
7164 UINT64_C(3248538625), // UCLAMP_VG2_2Z2Z_S
7165 UINT64_C(3240152065), // UCLAMP_VG4_4Z4Z_B
7166 UINT64_C(3252734977), // UCLAMP_VG4_4Z4Z_D
7167 UINT64_C(3244346369), // UCLAMP_VG4_4Z4Z_H
7168 UINT64_C(3248540673), // UCLAMP_VG4_4Z4Z_S
7169 UINT64_C(1140900864), // UCLAMP_ZZZ_B
7170 UINT64_C(1153483776), // UCLAMP_ZZZ_D
7171 UINT64_C(1145095168), // UCLAMP_ZZZ_H
7172 UINT64_C(1149289472), // UCLAMP_ZZZ_S
7173 UINT64_C(507740160), // UCVTFSWDri
7174 UINT64_C(516128768), // UCVTFSWHri
7175 UINT64_C(503545856), // UCVTFSWSri
7176 UINT64_C(2655191040), // UCVTFSXDri
7177 UINT64_C(2663579648), // UCVTFSXHri
7178 UINT64_C(2650996736), // UCVTFSXSri
7179 UINT64_C(509804544), // UCVTFUWDri
7180 UINT64_C(518193152), // UCVTFUWHri
7181 UINT64_C(505610240), // UCVTFUWSri
7182 UINT64_C(2657288192), // UCVTFUXDri
7183 UINT64_C(2665676800), // UCVTFUXHri
7184 UINT64_C(2653093888), // UCVTFUXSri
7185 UINT64_C(3240288288), // UCVTF_2Z2Z_StoS
7186 UINT64_C(3241336864), // UCVTF_4Z4Z_StoS
7187 UINT64_C(1708630016), // UCVTF_ZPmZ_DtoD
7188 UINT64_C(1700241408), // UCVTF_ZPmZ_DtoH
7189 UINT64_C(1708498944), // UCVTF_ZPmZ_DtoS
7190 UINT64_C(1699979264), // UCVTF_ZPmZ_HtoH
7191 UINT64_C(1708236800), // UCVTF_ZPmZ_StoD
7192 UINT64_C(1700110336), // UCVTF_ZPmZ_StoH
7193 UINT64_C(1704304640), // UCVTF_ZPmZ_StoS
7194 UINT64_C(2134959104), // UCVTFd
7195 UINT64_C(2131813376), // UCVTFh
7196 UINT64_C(2132861952), // UCVTFs
7197 UINT64_C(2121914368), // UCVTFv1i16
7198 UINT64_C(2116147200), // UCVTFv1i32
7199 UINT64_C(2120341504), // UCVTFv1i64
7200 UINT64_C(773969920), // UCVTFv2f32
7201 UINT64_C(1851906048), // UCVTFv2f64
7202 UINT64_C(790684672), // UCVTFv2i32_shift
7203 UINT64_C(1866523648), // UCVTFv2i64_shift
7204 UINT64_C(779737088), // UCVTFv4f16
7205 UINT64_C(1847711744), // UCVTFv4f32
7206 UINT64_C(789636096), // UCVTFv4i16_shift
7207 UINT64_C(1864426496), // UCVTFv4i32_shift
7208 UINT64_C(1853478912), // UCVTFv8f16
7209 UINT64_C(1863377920), // UCVTFv8i16_shift
7210 UINT64_C(0), // UDF
7211 UINT64_C(81199104), // UDIVR_ZPmZ_D
7212 UINT64_C(77004800), // UDIVR_ZPmZ_S
7213 UINT64_C(448792576), // UDIVWr
7214 UINT64_C(2596276224), // UDIVXr
7215 UINT64_C(81068032), // UDIV_ZPmZ_D
7216 UINT64_C(76873728), // UDIV_ZPmZ_S
7217 UINT64_C(3248493584), // UDOT_VG2_M2Z2Z_BtoS
7218 UINT64_C(3252687888), // UDOT_VG2_M2Z2Z_HtoD
7219 UINT64_C(3252687896), // UDOT_VG2_M2Z2Z_HtoS
7220 UINT64_C(3243249712), // UDOT_VG2_M2ZZI_BToS
7221 UINT64_C(3243249680), // UDOT_VG2_M2ZZI_HToS
7222 UINT64_C(3251634200), // UDOT_VG2_M2ZZI_HtoD
7223 UINT64_C(3240104976), // UDOT_VG2_M2ZZ_BtoS
7224 UINT64_C(3244299280), // UDOT_VG2_M2ZZ_HtoD
7225 UINT64_C(3244299288), // UDOT_VG2_M2ZZ_HtoS
7226 UINT64_C(3248559120), // UDOT_VG4_M4Z4Z_BtoS
7227 UINT64_C(3252753424), // UDOT_VG4_M4Z4Z_HtoD
7228 UINT64_C(3252753432), // UDOT_VG4_M4Z4Z_HtoS
7229 UINT64_C(3243282480), // UDOT_VG4_M4ZZI_BtoS
7230 UINT64_C(3243282448), // UDOT_VG4_M4ZZI_HToS
7231 UINT64_C(3251666968), // UDOT_VG4_M4ZZI_HtoD
7232 UINT64_C(3241153552), // UDOT_VG4_M4ZZ_BtoS
7233 UINT64_C(3245347856), // UDOT_VG4_M4ZZ_HtoD
7234 UINT64_C(3245347864), // UDOT_VG4_M4ZZ_HtoS
7235 UINT64_C(1155531776), // UDOT_ZZZI_D
7236 UINT64_C(1149291520), // UDOT_ZZZI_HtoS
7237 UINT64_C(1151337472), // UDOT_ZZZI_S
7238 UINT64_C(1153434624), // UDOT_ZZZ_D
7239 UINT64_C(1140902912), // UDOT_ZZZ_HtoS
7240 UINT64_C(1149240320), // UDOT_ZZZ_S
7241 UINT64_C(1870716928), // UDOTlanev16i8
7242 UINT64_C(796975104), // UDOTlanev8i8
7243 UINT64_C(1853920256), // UDOTv16i8
7244 UINT64_C(780178432), // UDOTv8i8
7245 UINT64_C(1141997568), // UHADD_ZPmZ_B
7246 UINT64_C(1154580480), // UHADD_ZPmZ_D
7247 UINT64_C(1146191872), // UHADD_ZPmZ_H
7248 UINT64_C(1150386176), // UHADD_ZPmZ_S
7249 UINT64_C(1847591936), // UHADDv16i8
7250 UINT64_C(782238720), // UHADDv2i32
7251 UINT64_C(778044416), // UHADDv4i16
7252 UINT64_C(1855980544), // UHADDv4i32
7253 UINT64_C(1851786240), // UHADDv8i16
7254 UINT64_C(773850112), // UHADDv8i8
7255 UINT64_C(1142390784), // UHSUBR_ZPmZ_B
7256 UINT64_C(1154973696), // UHSUBR_ZPmZ_D
7257 UINT64_C(1146585088), // UHSUBR_ZPmZ_H
7258 UINT64_C(1150779392), // UHSUBR_ZPmZ_S
7259 UINT64_C(1142128640), // UHSUB_ZPmZ_B
7260 UINT64_C(1154711552), // UHSUB_ZPmZ_D
7261 UINT64_C(1146322944), // UHSUB_ZPmZ_H
7262 UINT64_C(1150517248), // UHSUB_ZPmZ_S
7263 UINT64_C(1847600128), // UHSUBv16i8
7264 UINT64_C(782246912), // UHSUBv2i32
7265 UINT64_C(778052608), // UHSUBv4i16
7266 UINT64_C(1855988736), // UHSUBv4i32
7267 UINT64_C(1851794432), // UHSUBv8i16
7268 UINT64_C(773858304), // UHSUBv8i8
7269 UINT64_C(2610954240), // UMADDLrrr
7270 UINT64_C(1142267904), // UMAXP_ZPmZ_B
7271 UINT64_C(1154850816), // UMAXP_ZPmZ_D
7272 UINT64_C(1146462208), // UMAXP_ZPmZ_H
7273 UINT64_C(1150656512), // UMAXP_ZPmZ_S
7274 UINT64_C(1847632896), // UMAXPv16i8
7275 UINT64_C(782279680), // UMAXPv2i32
7276 UINT64_C(778085376), // UMAXPv4i16
7277 UINT64_C(1856021504), // UMAXPv4i32
7278 UINT64_C(1851827200), // UMAXPv8i16
7279 UINT64_C(773891072), // UMAXPv8i8
7280 UINT64_C(67969024), // UMAXQV_VPZ_B
7281 UINT64_C(80551936), // UMAXQV_VPZ_D
7282 UINT64_C(72163328), // UMAXQV_VPZ_H
7283 UINT64_C(76357632), // UMAXQV_VPZ_S
7284 UINT64_C(67706880), // UMAXV_VPZ_B
7285 UINT64_C(80289792), // UMAXV_VPZ_D
7286 UINT64_C(71901184), // UMAXV_VPZ_H
7287 UINT64_C(76095488), // UMAXV_VPZ_S
7288 UINT64_C(1848682496), // UMAXVv16i8v
7289 UINT64_C(779134976), // UMAXVv4i16v
7290 UINT64_C(1857071104), // UMAXVv4i32v
7291 UINT64_C(1852876800), // UMAXVv8i16v
7292 UINT64_C(774940672), // UMAXVv8i8v
7293 UINT64_C(298057728), // UMAXWri
7294 UINT64_C(448816128), // UMAXWrr
7295 UINT64_C(2445541376), // UMAXXri
7296 UINT64_C(2596299776), // UMAXXrr
7297 UINT64_C(3240144897), // UMAX_VG2_2Z2Z_B
7298 UINT64_C(3252727809), // UMAX_VG2_2Z2Z_D
7299 UINT64_C(3244339201), // UMAX_VG2_2Z2Z_H
7300 UINT64_C(3248533505), // UMAX_VG2_2Z2Z_S
7301 UINT64_C(3240140801), // UMAX_VG2_2ZZ_B
7302 UINT64_C(3252723713), // UMAX_VG2_2ZZ_D
7303 UINT64_C(3244335105), // UMAX_VG2_2ZZ_H
7304 UINT64_C(3248529409), // UMAX_VG2_2ZZ_S
7305 UINT64_C(3240146945), // UMAX_VG4_4Z4Z_B
7306 UINT64_C(3252729857), // UMAX_VG4_4Z4Z_D
7307 UINT64_C(3244341249), // UMAX_VG4_4Z4Z_H
7308 UINT64_C(3248535553), // UMAX_VG4_4Z4Z_S
7309 UINT64_C(3240142849), // UMAX_VG4_4ZZ_B
7310 UINT64_C(3252725761), // UMAX_VG4_4ZZ_D
7311 UINT64_C(3244337153), // UMAX_VG4_4ZZ_H
7312 UINT64_C(3248531457), // UMAX_VG4_4ZZ_S
7313 UINT64_C(623493120), // UMAX_ZI_B
7314 UINT64_C(636076032), // UMAX_ZI_D
7315 UINT64_C(627687424), // UMAX_ZI_H
7316 UINT64_C(631881728), // UMAX_ZI_S
7317 UINT64_C(67698688), // UMAX_ZPmZ_B
7318 UINT64_C(80281600), // UMAX_ZPmZ_D
7319 UINT64_C(71892992), // UMAX_ZPmZ_H
7320 UINT64_C(76087296), // UMAX_ZPmZ_S
7321 UINT64_C(1847616512), // UMAXv16i8
7322 UINT64_C(782263296), // UMAXv2i32
7323 UINT64_C(778068992), // UMAXv4i16
7324 UINT64_C(1856005120), // UMAXv4i32
7325 UINT64_C(1851810816), // UMAXv8i16
7326 UINT64_C(773874688), // UMAXv8i8
7327 UINT64_C(1142398976), // UMINP_ZPmZ_B
7328 UINT64_C(1154981888), // UMINP_ZPmZ_D
7329 UINT64_C(1146593280), // UMINP_ZPmZ_H
7330 UINT64_C(1150787584), // UMINP_ZPmZ_S
7331 UINT64_C(1847634944), // UMINPv16i8
7332 UINT64_C(782281728), // UMINPv2i32
7333 UINT64_C(778087424), // UMINPv4i16
7334 UINT64_C(1856023552), // UMINPv4i32
7335 UINT64_C(1851829248), // UMINPv8i16
7336 UINT64_C(773893120), // UMINPv8i8
7337 UINT64_C(68100096), // UMINQV_VPZ_B
7338 UINT64_C(80683008), // UMINQV_VPZ_D
7339 UINT64_C(72294400), // UMINQV_VPZ_H
7340 UINT64_C(76488704), // UMINQV_VPZ_S
7341 UINT64_C(67837952), // UMINV_VPZ_B
7342 UINT64_C(80420864), // UMINV_VPZ_D
7343 UINT64_C(72032256), // UMINV_VPZ_H
7344 UINT64_C(76226560), // UMINV_VPZ_S
7345 UINT64_C(1848748032), // UMINVv16i8v
7346 UINT64_C(779200512), // UMINVv4i16v
7347 UINT64_C(1857136640), // UMINVv4i32v
7348 UINT64_C(1852942336), // UMINVv8i16v
7349 UINT64_C(775006208), // UMINVv8i8v
7350 UINT64_C(298582016), // UMINWri
7351 UINT64_C(448818176), // UMINWrr
7352 UINT64_C(2446065664), // UMINXri
7353 UINT64_C(2596301824), // UMINXrr
7354 UINT64_C(3240144929), // UMIN_VG2_2Z2Z_B
7355 UINT64_C(3252727841), // UMIN_VG2_2Z2Z_D
7356 UINT64_C(3244339233), // UMIN_VG2_2Z2Z_H
7357 UINT64_C(3248533537), // UMIN_VG2_2Z2Z_S
7358 UINT64_C(3240140833), // UMIN_VG2_2ZZ_B
7359 UINT64_C(3252723745), // UMIN_VG2_2ZZ_D
7360 UINT64_C(3244335137), // UMIN_VG2_2ZZ_H
7361 UINT64_C(3248529441), // UMIN_VG2_2ZZ_S
7362 UINT64_C(3240146977), // UMIN_VG4_4Z4Z_B
7363 UINT64_C(3252729889), // UMIN_VG4_4Z4Z_D
7364 UINT64_C(3244341281), // UMIN_VG4_4Z4Z_H
7365 UINT64_C(3248535585), // UMIN_VG4_4Z4Z_S
7366 UINT64_C(3240142881), // UMIN_VG4_4ZZ_B
7367 UINT64_C(3252725793), // UMIN_VG4_4ZZ_D
7368 UINT64_C(3244337185), // UMIN_VG4_4ZZ_H
7369 UINT64_C(3248531489), // UMIN_VG4_4ZZ_S
7370 UINT64_C(623624192), // UMIN_ZI_B
7371 UINT64_C(636207104), // UMIN_ZI_D
7372 UINT64_C(627818496), // UMIN_ZI_H
7373 UINT64_C(632012800), // UMIN_ZI_S
7374 UINT64_C(67829760), // UMIN_ZPmZ_B
7375 UINT64_C(80412672), // UMIN_ZPmZ_D
7376 UINT64_C(72024064), // UMIN_ZPmZ_H
7377 UINT64_C(76218368), // UMIN_ZPmZ_S
7378 UINT64_C(1847618560), // UMINv16i8
7379 UINT64_C(782265344), // UMINv2i32
7380 UINT64_C(778071040), // UMINv4i16
7381 UINT64_C(1856007168), // UMINv4i32
7382 UINT64_C(1851812864), // UMINv8i16
7383 UINT64_C(773876736), // UMINv8i8
7384 UINT64_C(1155567616), // UMLALB_ZZZI_D
7385 UINT64_C(1151373312), // UMLALB_ZZZI_S
7386 UINT64_C(1153452032), // UMLALB_ZZZ_D
7387 UINT64_C(1145063424), // UMLALB_ZZZ_H
7388 UINT64_C(1149257728), // UMLALB_ZZZ_S
7389 UINT64_C(3238002704), // UMLALL_MZZI_BtoS
7390 UINT64_C(3246391312), // UMLALL_MZZI_HtoD
7391 UINT64_C(3240100880), // UMLALL_MZZ_BtoS
7392 UINT64_C(3244295184), // UMLALL_MZZ_HtoD
7393 UINT64_C(3248488464), // UMLALL_VG2_M2Z2Z_BtoS
7394 UINT64_C(3252682768), // UMLALL_VG2_M2Z2Z_HtoD
7395 UINT64_C(3239051280), // UMLALL_VG2_M2ZZI_BtoS
7396 UINT64_C(3247439888), // UMLALL_VG2_M2ZZI_HtoD
7397 UINT64_C(3240099856), // UMLALL_VG2_M2ZZ_BtoS
7398 UINT64_C(3244294160), // UMLALL_VG2_M2ZZ_HtoD
7399 UINT64_C(3248554000), // UMLALL_VG4_M4Z4Z_BtoS
7400 UINT64_C(3252748304), // UMLALL_VG4_M4Z4Z_HtoD
7401 UINT64_C(3239084048), // UMLALL_VG4_M4ZZI_BtoS
7402 UINT64_C(3247472656), // UMLALL_VG4_M4ZZI_HtoD
7403 UINT64_C(3241148432), // UMLALL_VG4_M4ZZ_BtoS
7404 UINT64_C(3245342736), // UMLALL_VG4_M4ZZ_HtoD
7405 UINT64_C(1155568640), // UMLALT_ZZZI_D
7406 UINT64_C(1151374336), // UMLALT_ZZZI_S
7407 UINT64_C(1153453056), // UMLALT_ZZZ_D
7408 UINT64_C(1145064448), // UMLALT_ZZZ_H
7409 UINT64_C(1149258752), // UMLALT_ZZZ_S
7410 UINT64_C(3250589712), // UMLAL_MZZI_HtoS
7411 UINT64_C(3244297232), // UMLAL_MZZ_HtoS
7412 UINT64_C(3252684816), // UMLAL_VG2_M2Z2Z_HtoS
7413 UINT64_C(3251638288), // UMLAL_VG2_M2ZZI_S
7414 UINT64_C(3244296208), // UMLAL_VG2_M2ZZ_HtoS
7415 UINT64_C(3252750352), // UMLAL_VG4_M4Z4Z_HtoS
7416 UINT64_C(3251671056), // UMLAL_VG4_M4ZZI_HtoS
7417 UINT64_C(3245344784), // UMLAL_VG4_M4ZZ_HtoS
7418 UINT64_C(1847623680), // UMLALv16i8_v8i16
7419 UINT64_C(796925952), // UMLALv2i32_indexed
7420 UINT64_C(782270464), // UMLALv2i32_v2i64
7421 UINT64_C(792731648), // UMLALv4i16_indexed
7422 UINT64_C(778076160), // UMLALv4i16_v4i32
7423 UINT64_C(1870667776), // UMLALv4i32_indexed
7424 UINT64_C(1856012288), // UMLALv4i32_v2i64
7425 UINT64_C(1866473472), // UMLALv8i16_indexed
7426 UINT64_C(1851817984), // UMLALv8i16_v4i32
7427 UINT64_C(773881856), // UMLALv8i8_v8i16
7428 UINT64_C(1155575808), // UMLSLB_ZZZI_D
7429 UINT64_C(1151381504), // UMLSLB_ZZZI_S
7430 UINT64_C(1153456128), // UMLSLB_ZZZ_D
7431 UINT64_C(1145067520), // UMLSLB_ZZZ_H
7432 UINT64_C(1149261824), // UMLSLB_ZZZ_S
7433 UINT64_C(3238002712), // UMLSLL_MZZI_BtoS
7434 UINT64_C(3246391320), // UMLSLL_MZZI_HtoD
7435 UINT64_C(3240100888), // UMLSLL_MZZ_BtoS
7436 UINT64_C(3244295192), // UMLSLL_MZZ_HtoD
7437 UINT64_C(3248488472), // UMLSLL_VG2_M2Z2Z_BtoS
7438 UINT64_C(3252682776), // UMLSLL_VG2_M2Z2Z_HtoD
7439 UINT64_C(3239051288), // UMLSLL_VG2_M2ZZI_BtoS
7440 UINT64_C(3247439896), // UMLSLL_VG2_M2ZZI_HtoD
7441 UINT64_C(3240099864), // UMLSLL_VG2_M2ZZ_BtoS
7442 UINT64_C(3244294168), // UMLSLL_VG2_M2ZZ_HtoD
7443 UINT64_C(3248554008), // UMLSLL_VG4_M4Z4Z_BtoS
7444 UINT64_C(3252748312), // UMLSLL_VG4_M4Z4Z_HtoD
7445 UINT64_C(3239084056), // UMLSLL_VG4_M4ZZI_BtoS
7446 UINT64_C(3247472664), // UMLSLL_VG4_M4ZZI_HtoD
7447 UINT64_C(3241148440), // UMLSLL_VG4_M4ZZ_BtoS
7448 UINT64_C(3245342744), // UMLSLL_VG4_M4ZZ_HtoD
7449 UINT64_C(1155576832), // UMLSLT_ZZZI_D
7450 UINT64_C(1151382528), // UMLSLT_ZZZI_S
7451 UINT64_C(1153457152), // UMLSLT_ZZZ_D
7452 UINT64_C(1145068544), // UMLSLT_ZZZ_H
7453 UINT64_C(1149262848), // UMLSLT_ZZZ_S
7454 UINT64_C(3250589720), // UMLSL_MZZI_HtoS
7455 UINT64_C(3244297240), // UMLSL_MZZ_HtoS
7456 UINT64_C(3252684824), // UMLSL_VG2_M2Z2Z_HtoS
7457 UINT64_C(3251638296), // UMLSL_VG2_M2ZZI_S
7458 UINT64_C(3244296216), // UMLSL_VG2_M2ZZ_HtoS
7459 UINT64_C(3252750360), // UMLSL_VG4_M4Z4Z_HtoS
7460 UINT64_C(3251671064), // UMLSL_VG4_M4ZZI_HtoS
7461 UINT64_C(3245344792), // UMLSL_VG4_M4ZZ_HtoS
7462 UINT64_C(1847631872), // UMLSLv16i8_v8i16
7463 UINT64_C(796942336), // UMLSLv2i32_indexed
7464 UINT64_C(782278656), // UMLSLv2i32_v2i64
7465 UINT64_C(792748032), // UMLSLv4i16_indexed
7466 UINT64_C(778084352), // UMLSLv4i16_v4i32
7467 UINT64_C(1870684160), // UMLSLv4i32_indexed
7468 UINT64_C(1856020480), // UMLSLv4i32_v2i64
7469 UINT64_C(1866489856), // UMLSLv8i16_indexed
7470 UINT64_C(1851826176), // UMLSLv8i16_v4i32
7471 UINT64_C(773890048), // UMLSLv8i8_v8i16
7472 UINT64_C(1853924352), // UMMLA
7473 UINT64_C(1170249728), // UMMLA_ZZZ
7474 UINT64_C(2715811840), // UMOPA_MPPZZ_D
7475 UINT64_C(2709520392), // UMOPA_MPPZZ_HtoS
7476 UINT64_C(2711617536), // UMOPA_MPPZZ_S
7477 UINT64_C(2715811856), // UMOPS_MPPZZ_D
7478 UINT64_C(2709520408), // UMOPS_MPPZZ_HtoS
7479 UINT64_C(2711617552), // UMOPS_MPPZZ_S
7480 UINT64_C(235027456), // UMOVvi16
7481 UINT64_C(235027456), // UMOVvi16_idx0
7482 UINT64_C(235158528), // UMOVvi32
7483 UINT64_C(235158528), // UMOVvi32_idx0
7484 UINT64_C(1309162496), // UMOVvi64
7485 UINT64_C(1309162496), // UMOVvi64_idx0
7486 UINT64_C(234961920), // UMOVvi8
7487 UINT64_C(234961920), // UMOVvi8_idx0
7488 UINT64_C(2610987008), // UMSUBLrrr
7489 UINT64_C(68354048), // UMULH_ZPmZ_B
7490 UINT64_C(80936960), // UMULH_ZPmZ_D
7491 UINT64_C(72548352), // UMULH_ZPmZ_H
7492 UINT64_C(76742656), // UMULH_ZPmZ_S
7493 UINT64_C(69233664), // UMULH_ZZZ_B
7494 UINT64_C(81816576), // UMULH_ZZZ_D
7495 UINT64_C(73427968), // UMULH_ZZZ_H
7496 UINT64_C(77622272), // UMULH_ZZZ_S
7497 UINT64_C(2613051392), // UMULHrr
7498 UINT64_C(1155584000), // UMULLB_ZZZI_D
7499 UINT64_C(1151389696), // UMULLB_ZZZI_S
7500 UINT64_C(1170241536), // UMULLB_ZZZ_D
7501 UINT64_C(1161852928), // UMULLB_ZZZ_H
7502 UINT64_C(1166047232), // UMULLB_ZZZ_S
7503 UINT64_C(1155585024), // UMULLT_ZZZI_D
7504 UINT64_C(1151390720), // UMULLT_ZZZI_S
7505 UINT64_C(1170242560), // UMULLT_ZZZ_D
7506 UINT64_C(1161853952), // UMULLT_ZZZ_H
7507 UINT64_C(1166048256), // UMULLT_ZZZ_S
7508 UINT64_C(1847640064), // UMULLv16i8_v8i16
7509 UINT64_C(796958720), // UMULLv2i32_indexed
7510 UINT64_C(782286848), // UMULLv2i32_v2i64
7511 UINT64_C(792764416), // UMULLv4i16_indexed
7512 UINT64_C(778092544), // UMULLv4i16_v4i32
7513 UINT64_C(1870700544), // UMULLv4i32_indexed
7514 UINT64_C(1856028672), // UMULLv4i32_v2i64
7515 UINT64_C(1866506240), // UMULLv8i16_indexed
7516 UINT64_C(1851834368), // UMULLv8i16_v4i32
7517 UINT64_C(773898240), // UMULLv8i8_v8i16
7518 UINT64_C(623230976), // UQADD_ZI_B
7519 UINT64_C(635813888), // UQADD_ZI_D
7520 UINT64_C(627425280), // UQADD_ZI_H
7521 UINT64_C(631619584), // UQADD_ZI_S
7522 UINT64_C(1142521856), // UQADD_ZPmZ_B
7523 UINT64_C(1155104768), // UQADD_ZPmZ_D
7524 UINT64_C(1146716160), // UQADD_ZPmZ_H
7525 UINT64_C(1150910464), // UQADD_ZPmZ_S
7526 UINT64_C(69211136), // UQADD_ZZZ_B
7527 UINT64_C(81794048), // UQADD_ZZZ_D
7528 UINT64_C(73405440), // UQADD_ZZZ_H
7529 UINT64_C(77599744), // UQADD_ZZZ_S
7530 UINT64_C(1847593984), // UQADDv16i8
7531 UINT64_C(2120223744), // UQADDv1i16
7532 UINT64_C(2124418048), // UQADDv1i32
7533 UINT64_C(2128612352), // UQADDv1i64
7534 UINT64_C(2116029440), // UQADDv1i8
7535 UINT64_C(782240768), // UQADDv2i32
7536 UINT64_C(1860176896), // UQADDv2i64
7537 UINT64_C(778046464), // UQADDv4i16
7538 UINT64_C(1855982592), // UQADDv4i32
7539 UINT64_C(1851788288), // UQADDv8i16
7540 UINT64_C(773852160), // UQADDv8i8
7541 UINT64_C(1160857600), // UQCVTN_Z2Z_StoH
7542 UINT64_C(3249791072), // UQCVTN_Z4Z_DtoH
7543 UINT64_C(3241402464), // UQCVTN_Z4Z_StoB
7544 UINT64_C(3240353824), // UQCVT_Z2Z_StoH
7545 UINT64_C(3249791008), // UQCVT_Z4Z_DtoH
7546 UINT64_C(3241402400), // UQCVT_Z4Z_StoB
7547 UINT64_C(69270528), // UQDECB_WPiI
7548 UINT64_C(70319104), // UQDECB_XPiI
7549 UINT64_C(81853440), // UQDECD_WPiI
7550 UINT64_C(82902016), // UQDECD_XPiI
7551 UINT64_C(81841152), // UQDECD_ZPiI
7552 UINT64_C(73464832), // UQDECH_WPiI
7553 UINT64_C(74513408), // UQDECH_XPiI
7554 UINT64_C(73452544), // UQDECH_ZPiI
7555 UINT64_C(623609856), // UQDECP_WP_B
7556 UINT64_C(636192768), // UQDECP_WP_D
7557 UINT64_C(627804160), // UQDECP_WP_H
7558 UINT64_C(631998464), // UQDECP_WP_S
7559 UINT64_C(623610880), // UQDECP_XP_B
7560 UINT64_C(636193792), // UQDECP_XP_D
7561 UINT64_C(627805184), // UQDECP_XP_H
7562 UINT64_C(631999488), // UQDECP_XP_S
7563 UINT64_C(636190720), // UQDECP_ZP_D
7564 UINT64_C(627802112), // UQDECP_ZP_H
7565 UINT64_C(631996416), // UQDECP_ZP_S
7566 UINT64_C(77659136), // UQDECW_WPiI
7567 UINT64_C(78707712), // UQDECW_XPiI
7568 UINT64_C(77646848), // UQDECW_ZPiI
7569 UINT64_C(69268480), // UQINCB_WPiI
7570 UINT64_C(70317056), // UQINCB_XPiI
7571 UINT64_C(81851392), // UQINCD_WPiI
7572 UINT64_C(82899968), // UQINCD_XPiI
7573 UINT64_C(81839104), // UQINCD_ZPiI
7574 UINT64_C(73462784), // UQINCH_WPiI
7575 UINT64_C(74511360), // UQINCH_XPiI
7576 UINT64_C(73450496), // UQINCH_ZPiI
7577 UINT64_C(623478784), // UQINCP_WP_B
7578 UINT64_C(636061696), // UQINCP_WP_D
7579 UINT64_C(627673088), // UQINCP_WP_H
7580 UINT64_C(631867392), // UQINCP_WP_S
7581 UINT64_C(623479808), // UQINCP_XP_B
7582 UINT64_C(636062720), // UQINCP_XP_D
7583 UINT64_C(627674112), // UQINCP_XP_H
7584 UINT64_C(631868416), // UQINCP_XP_S
7585 UINT64_C(636059648), // UQINCP_ZP_D
7586 UINT64_C(627671040), // UQINCP_ZP_H
7587 UINT64_C(631865344), // UQINCP_ZP_S
7588 UINT64_C(77657088), // UQINCW_WPiI
7589 UINT64_C(78705664), // UQINCW_XPiI
7590 UINT64_C(77644800), // UQINCW_ZPiI
7591 UINT64_C(1141866496), // UQRSHLR_ZPmZ_B
7592 UINT64_C(1154449408), // UQRSHLR_ZPmZ_D
7593 UINT64_C(1146060800), // UQRSHLR_ZPmZ_H
7594 UINT64_C(1150255104), // UQRSHLR_ZPmZ_S
7595 UINT64_C(1141604352), // UQRSHL_ZPmZ_B
7596 UINT64_C(1154187264), // UQRSHL_ZPmZ_D
7597 UINT64_C(1145798656), // UQRSHL_ZPmZ_H
7598 UINT64_C(1149992960), // UQRSHL_ZPmZ_S
7599 UINT64_C(1847614464), // UQRSHLv16i8
7600 UINT64_C(2120244224), // UQRSHLv1i16
7601 UINT64_C(2124438528), // UQRSHLv1i32
7602 UINT64_C(2128632832), // UQRSHLv1i64
7603 UINT64_C(2116049920), // UQRSHLv1i8
7604 UINT64_C(782261248), // UQRSHLv2i32
7605 UINT64_C(1860197376), // UQRSHLv2i64
7606 UINT64_C(778066944), // UQRSHLv4i16
7607 UINT64_C(1856003072), // UQRSHLv4i32
7608 UINT64_C(1851808768), // UQRSHLv8i16
7609 UINT64_C(773872640), // UQRSHLv8i8
7610 UINT64_C(1160263680), // UQRSHRNB_ZZI_B
7611 UINT64_C(1160787968), // UQRSHRNB_ZZI_H
7612 UINT64_C(1163933696), // UQRSHRNB_ZZI_S
7613 UINT64_C(1160264704), // UQRSHRNT_ZZI_B
7614 UINT64_C(1160788992), // UQRSHRNT_ZZI_H
7615 UINT64_C(1163934720), // UQRSHRNT_ZZI_S
7616 UINT64_C(3244350496), // UQRSHRN_VG4_Z4ZI_B
7617 UINT64_C(3248544800), // UQRSHRN_VG4_Z4ZI_H
7618 UINT64_C(1169176576), // UQRSHRN_Z2ZI_StoH
7619 UINT64_C(2131270656), // UQRSHRNb
7620 UINT64_C(2131794944), // UQRSHRNh
7621 UINT64_C(2132843520), // UQRSHRNs
7622 UINT64_C(1862835200), // UQRSHRNv16i8_shift
7623 UINT64_C(790666240), // UQRSHRNv2i32_shift
7624 UINT64_C(789617664), // UQRSHRNv4i16_shift
7625 UINT64_C(1864408064), // UQRSHRNv4i32_shift
7626 UINT64_C(1863359488), // UQRSHRNv8i16_shift
7627 UINT64_C(789093376), // UQRSHRNv8i8_shift
7628 UINT64_C(3252737056), // UQRSHR_VG2_Z2ZI_H
7629 UINT64_C(3244349472), // UQRSHR_VG4_Z4ZI_B
7630 UINT64_C(3248543776), // UQRSHR_VG4_Z4ZI_H
7631 UINT64_C(1141735424), // UQSHLR_ZPmZ_B
7632 UINT64_C(1154318336), // UQSHLR_ZPmZ_D
7633 UINT64_C(1145929728), // UQSHLR_ZPmZ_H
7634 UINT64_C(1150124032), // UQSHLR_ZPmZ_S
7635 UINT64_C(67600640), // UQSHL_ZPmI_B
7636 UINT64_C(75988992), // UQSHL_ZPmI_D
7637 UINT64_C(67600896), // UQSHL_ZPmI_H
7638 UINT64_C(71794688), // UQSHL_ZPmI_S
7639 UINT64_C(1141473280), // UQSHL_ZPmZ_B
7640 UINT64_C(1154056192), // UQSHL_ZPmZ_D
7641 UINT64_C(1145667584), // UQSHL_ZPmZ_H
7642 UINT64_C(1149861888), // UQSHL_ZPmZ_S
7643 UINT64_C(2131260416), // UQSHLb
7644 UINT64_C(2134930432), // UQSHLd
7645 UINT64_C(2131784704), // UQSHLh
7646 UINT64_C(2132833280), // UQSHLs
7647 UINT64_C(1847610368), // UQSHLv16i8
7648 UINT64_C(1862824960), // UQSHLv16i8_shift
7649 UINT64_C(2120240128), // UQSHLv1i16
7650 UINT64_C(2124434432), // UQSHLv1i32
7651 UINT64_C(2128628736), // UQSHLv1i64
7652 UINT64_C(2116045824), // UQSHLv1i8
7653 UINT64_C(782257152), // UQSHLv2i32
7654 UINT64_C(790656000), // UQSHLv2i32_shift
7655 UINT64_C(1860193280), // UQSHLv2i64
7656 UINT64_C(1866494976), // UQSHLv2i64_shift
7657 UINT64_C(778062848), // UQSHLv4i16
7658 UINT64_C(789607424), // UQSHLv4i16_shift
7659 UINT64_C(1855998976), // UQSHLv4i32
7660 UINT64_C(1864397824), // UQSHLv4i32_shift
7661 UINT64_C(1851804672), // UQSHLv8i16
7662 UINT64_C(1863349248), // UQSHLv8i16_shift
7663 UINT64_C(773868544), // UQSHLv8i8
7664 UINT64_C(789083136), // UQSHLv8i8_shift
7665 UINT64_C(1160261632), // UQSHRNB_ZZI_B
7666 UINT64_C(1160785920), // UQSHRNB_ZZI_H
7667 UINT64_C(1163931648), // UQSHRNB_ZZI_S
7668 UINT64_C(1160262656), // UQSHRNT_ZZI_B
7669 UINT64_C(1160786944), // UQSHRNT_ZZI_H
7670 UINT64_C(1163932672), // UQSHRNT_ZZI_S
7671 UINT64_C(2131268608), // UQSHRNb
7672 UINT64_C(2131792896), // UQSHRNh
7673 UINT64_C(2132841472), // UQSHRNs
7674 UINT64_C(1862833152), // UQSHRNv16i8_shift
7675 UINT64_C(790664192), // UQSHRNv2i32_shift
7676 UINT64_C(789615616), // UQSHRNv4i16_shift
7677 UINT64_C(1864406016), // UQSHRNv4i32_shift
7678 UINT64_C(1863357440), // UQSHRNv8i16_shift
7679 UINT64_C(789091328), // UQSHRNv8i8_shift
7680 UINT64_C(1142915072), // UQSUBR_ZPmZ_B
7681 UINT64_C(1155497984), // UQSUBR_ZPmZ_D
7682 UINT64_C(1147109376), // UQSUBR_ZPmZ_H
7683 UINT64_C(1151303680), // UQSUBR_ZPmZ_S
7684 UINT64_C(623362048), // UQSUB_ZI_B
7685 UINT64_C(635944960), // UQSUB_ZI_D
7686 UINT64_C(627556352), // UQSUB_ZI_H
7687 UINT64_C(631750656), // UQSUB_ZI_S
7688 UINT64_C(1142652928), // UQSUB_ZPmZ_B
7689 UINT64_C(1155235840), // UQSUB_ZPmZ_D
7690 UINT64_C(1146847232), // UQSUB_ZPmZ_H
7691 UINT64_C(1151041536), // UQSUB_ZPmZ_S
7692 UINT64_C(69213184), // UQSUB_ZZZ_B
7693 UINT64_C(81796096), // UQSUB_ZZZ_D
7694 UINT64_C(73407488), // UQSUB_ZZZ_H
7695 UINT64_C(77601792), // UQSUB_ZZZ_S
7696 UINT64_C(1847602176), // UQSUBv16i8
7697 UINT64_C(2120231936), // UQSUBv1i16
7698 UINT64_C(2124426240), // UQSUBv1i32
7699 UINT64_C(2128620544), // UQSUBv1i64
7700 UINT64_C(2116037632), // UQSUBv1i8
7701 UINT64_C(782248960), // UQSUBv2i32
7702 UINT64_C(1860185088), // UQSUBv2i64
7703 UINT64_C(778054656), // UQSUBv4i16
7704 UINT64_C(1855990784), // UQSUBv4i32
7705 UINT64_C(1851796480), // UQSUBv8i16
7706 UINT64_C(773860352), // UQSUBv8i8
7707 UINT64_C(1160267776), // UQXTNB_ZZ_B
7708 UINT64_C(1160792064), // UQXTNB_ZZ_H
7709 UINT64_C(1163937792), // UQXTNB_ZZ_S
7710 UINT64_C(1160268800), // UQXTNT_ZZ_B
7711 UINT64_C(1160793088), // UQXTNT_ZZ_H
7712 UINT64_C(1163938816), // UQXTNT_ZZ_S
7713 UINT64_C(1847674880), // UQXTNv16i8
7714 UINT64_C(2120304640), // UQXTNv1i16
7715 UINT64_C(2124498944), // UQXTNv1i32
7716 UINT64_C(2116110336), // UQXTNv1i8
7717 UINT64_C(782321664), // UQXTNv2i32
7718 UINT64_C(778127360), // UQXTNv4i16
7719 UINT64_C(1856063488), // UQXTNv4i32
7720 UINT64_C(1851869184), // UQXTNv8i16
7721 UINT64_C(773933056), // UQXTNv8i8
7722 UINT64_C(1149280256), // URECPE_ZPmZ_S
7723 UINT64_C(245483520), // URECPEv2i32
7724 UINT64_C(1319225344), // URECPEv4i32
7725 UINT64_C(1142259712), // URHADD_ZPmZ_B
7726 UINT64_C(1154842624), // URHADD_ZPmZ_D
7727 UINT64_C(1146454016), // URHADD_ZPmZ_H
7728 UINT64_C(1150648320), // URHADD_ZPmZ_S
7729 UINT64_C(1847596032), // URHADDv16i8
7730 UINT64_C(782242816), // URHADDv2i32
7731 UINT64_C(778048512), // URHADDv4i16
7732 UINT64_C(1855984640), // URHADDv4i32
7733 UINT64_C(1851790336), // URHADDv8i16
7734 UINT64_C(773854208), // URHADDv8i8
7735 UINT64_C(1141342208), // URSHLR_ZPmZ_B
7736 UINT64_C(1153925120), // URSHLR_ZPmZ_D
7737 UINT64_C(1145536512), // URSHLR_ZPmZ_H
7738 UINT64_C(1149730816), // URSHLR_ZPmZ_S
7739 UINT64_C(3240145441), // URSHL_VG2_2Z2Z_B
7740 UINT64_C(3252728353), // URSHL_VG2_2Z2Z_D
7741 UINT64_C(3244339745), // URSHL_VG2_2Z2Z_H
7742 UINT64_C(3248534049), // URSHL_VG2_2Z2Z_S
7743 UINT64_C(3240141345), // URSHL_VG2_2ZZ_B
7744 UINT64_C(3252724257), // URSHL_VG2_2ZZ_D
7745 UINT64_C(3244335649), // URSHL_VG2_2ZZ_H
7746 UINT64_C(3248529953), // URSHL_VG2_2ZZ_S
7747 UINT64_C(3240147489), // URSHL_VG4_4Z4Z_B
7748 UINT64_C(3252730401), // URSHL_VG4_4Z4Z_D
7749 UINT64_C(3244341793), // URSHL_VG4_4Z4Z_H
7750 UINT64_C(3248536097), // URSHL_VG4_4Z4Z_S
7751 UINT64_C(3240143393), // URSHL_VG4_4ZZ_B
7752 UINT64_C(3252726305), // URSHL_VG4_4ZZ_D
7753 UINT64_C(3244337697), // URSHL_VG4_4ZZ_H
7754 UINT64_C(3248532001), // URSHL_VG4_4ZZ_S
7755 UINT64_C(1141080064), // URSHL_ZPmZ_B
7756 UINT64_C(1153662976), // URSHL_ZPmZ_D
7757 UINT64_C(1145274368), // URSHL_ZPmZ_H
7758 UINT64_C(1149468672), // URSHL_ZPmZ_S
7759 UINT64_C(1847612416), // URSHLv16i8
7760 UINT64_C(2128630784), // URSHLv1i64
7761 UINT64_C(782259200), // URSHLv2i32
7762 UINT64_C(1860195328), // URSHLv2i64
7763 UINT64_C(778064896), // URSHLv4i16
7764 UINT64_C(1856001024), // URSHLv4i32
7765 UINT64_C(1851806720), // URSHLv8i16
7766 UINT64_C(773870592), // URSHLv8i8
7767 UINT64_C(67993856), // URSHR_ZPmI_B
7768 UINT64_C(76382208), // URSHR_ZPmI_D
7769 UINT64_C(67994112), // URSHR_ZPmI_H
7770 UINT64_C(72187904), // URSHR_ZPmI_S
7771 UINT64_C(2134909952), // URSHRd
7772 UINT64_C(1862804480), // URSHRv16i8_shift
7773 UINT64_C(790635520), // URSHRv2i32_shift
7774 UINT64_C(1866474496), // URSHRv2i64_shift
7775 UINT64_C(789586944), // URSHRv4i16_shift
7776 UINT64_C(1864377344), // URSHRv4i32_shift
7777 UINT64_C(1863328768), // URSHRv8i16_shift
7778 UINT64_C(789062656), // URSHRv8i8_shift
7779 UINT64_C(1149345792), // URSQRTE_ZPmZ_S
7780 UINT64_C(782354432), // URSQRTEv2i32
7781 UINT64_C(1856096256), // URSQRTEv4i32
7782 UINT64_C(1158212608), // URSRA_ZZI_B
7783 UINT64_C(1166076928), // URSRA_ZZI_D
7784 UINT64_C(1158736896), // URSRA_ZZI_H
7785 UINT64_C(1161882624), // URSRA_ZZI_S
7786 UINT64_C(2134914048), // URSRAd
7787 UINT64_C(1862808576), // URSRAv16i8_shift
7788 UINT64_C(790639616), // URSRAv2i32_shift
7789 UINT64_C(1866478592), // URSRAv2i64_shift
7790 UINT64_C(789591040), // URSRAv4i16_shift
7791 UINT64_C(1864381440), // URSRAv4i32_shift
7792 UINT64_C(1863332864), // URSRAv8i16_shift
7793 UINT64_C(789066752), // URSRAv8i8_shift
7794 UINT64_C(3248493576), // USDOT_VG2_M2Z2Z_BToS
7795 UINT64_C(3243249704), // USDOT_VG2_M2ZZI_BToS
7796 UINT64_C(3240104968), // USDOT_VG2_M2ZZ_BToS
7797 UINT64_C(3248559112), // USDOT_VG4_M4Z4Z_BToS
7798 UINT64_C(3243282472), // USDOT_VG4_M4ZZI_BToS
7799 UINT64_C(3241153544), // USDOT_VG4_M4ZZ_BToS
7800 UINT64_C(1149270016), // USDOT_ZZZ
7801 UINT64_C(1151342592), // USDOT_ZZZI
7802 UINT64_C(1333850112), // USDOTlanev16i8
7803 UINT64_C(260108288), // USDOTlanev8i8
7804 UINT64_C(1317051392), // USDOTv16i8
7805 UINT64_C(243309568), // USDOTv8i8
7806 UINT64_C(1161865216), // USHLLB_ZZI_D
7807 UINT64_C(1158195200), // USHLLB_ZZI_H
7808 UINT64_C(1158719488), // USHLLB_ZZI_S
7809 UINT64_C(1161866240), // USHLLT_ZZI_D
7810 UINT64_C(1158196224), // USHLLT_ZZI_H
7811 UINT64_C(1158720512), // USHLLT_ZZI_S
7812 UINT64_C(1862837248), // USHLLv16i8_shift
7813 UINT64_C(790668288), // USHLLv2i32_shift
7814 UINT64_C(789619712), // USHLLv4i16_shift
7815 UINT64_C(1864410112), // USHLLv4i32_shift
7816 UINT64_C(1863361536), // USHLLv8i16_shift
7817 UINT64_C(789095424), // USHLLv8i8_shift
7818 UINT64_C(1847608320), // USHLv16i8
7819 UINT64_C(2128626688), // USHLv1i64
7820 UINT64_C(782255104), // USHLv2i32
7821 UINT64_C(1860191232), // USHLv2i64
7822 UINT64_C(778060800), // USHLv4i16
7823 UINT64_C(1855996928), // USHLv4i32
7824 UINT64_C(1851802624), // USHLv8i16
7825 UINT64_C(773866496), // USHLv8i8
7826 UINT64_C(2134901760), // USHRd
7827 UINT64_C(1862796288), // USHRv16i8_shift
7828 UINT64_C(790627328), // USHRv2i32_shift
7829 UINT64_C(1866466304), // USHRv2i64_shift
7830 UINT64_C(789578752), // USHRv4i16_shift
7831 UINT64_C(1864369152), // USHRv4i32_shift
7832 UINT64_C(1863320576), // USHRv8i16_shift
7833 UINT64_C(789054464), // USHRv8i8_shift
7834 UINT64_C(3238002692), // USMLALL_MZZI_BtoS
7835 UINT64_C(3240100868), // USMLALL_MZZ_BtoS
7836 UINT64_C(3248488452), // USMLALL_VG2_M2Z2Z_BtoS
7837 UINT64_C(3239051296), // USMLALL_VG2_M2ZZI_BtoS
7838 UINT64_C(3240099844), // USMLALL_VG2_M2ZZ_BtoS
7839 UINT64_C(3248553988), // USMLALL_VG4_M4Z4Z_BtoS
7840 UINT64_C(3239084064), // USMLALL_VG4_M4ZZI_BtoS
7841 UINT64_C(3241148420), // USMLALL_VG4_M4ZZ_BtoS
7842 UINT64_C(1317055488), // USMMLA
7843 UINT64_C(1166055424), // USMMLA_ZZZ
7844 UINT64_C(2713714688), // USMOPA_MPPZZ_D
7845 UINT64_C(2709520384), // USMOPA_MPPZZ_S
7846 UINT64_C(2713714704), // USMOPS_MPPZZ_D
7847 UINT64_C(2709520400), // USMOPS_MPPZZ_S
7848 UINT64_C(1142784000), // USQADD_ZPmZ_B
7849 UINT64_C(1155366912), // USQADD_ZPmZ_D
7850 UINT64_C(1146978304), // USQADD_ZPmZ_H
7851 UINT64_C(1151172608), // USQADD_ZPmZ_S
7852 UINT64_C(1847605248), // USQADDv16i8
7853 UINT64_C(2120235008), // USQADDv1i16
7854 UINT64_C(2124429312), // USQADDv1i32
7855 UINT64_C(2128623616), // USQADDv1i64
7856 UINT64_C(2116040704), // USQADDv1i8
7857 UINT64_C(782252032), // USQADDv2i32
7858 UINT64_C(1860188160), // USQADDv2i64
7859 UINT64_C(778057728), // USQADDv4i16
7860 UINT64_C(1855993856), // USQADDv4i32
7861 UINT64_C(1851799552), // USQADDv8i16
7862 UINT64_C(773863424), // USQADDv8i8
7863 UINT64_C(1158210560), // USRA_ZZI_B
7864 UINT64_C(1166074880), // USRA_ZZI_D
7865 UINT64_C(1158734848), // USRA_ZZI_H
7866 UINT64_C(1161880576), // USRA_ZZI_S
7867 UINT64_C(2134905856), // USRAd
7868 UINT64_C(1862800384), // USRAv16i8_shift
7869 UINT64_C(790631424), // USRAv2i32_shift
7870 UINT64_C(1866470400), // USRAv2i64_shift
7871 UINT64_C(789582848), // USRAv4i16_shift
7872 UINT64_C(1864373248), // USRAv4i32_shift
7873 UINT64_C(1863324672), // USRAv8i16_shift
7874 UINT64_C(789058560), // USRAv8i8_shift
7875 UINT64_C(1170216960), // USUBLB_ZZZ_D
7876 UINT64_C(1161828352), // USUBLB_ZZZ_H
7877 UINT64_C(1166022656), // USUBLB_ZZZ_S
7878 UINT64_C(1170217984), // USUBLT_ZZZ_D
7879 UINT64_C(1161829376), // USUBLT_ZZZ_H
7880 UINT64_C(1166023680), // USUBLT_ZZZ_S
7881 UINT64_C(1847599104), // USUBLv16i8_v8i16
7882 UINT64_C(782245888), // USUBLv2i32_v2i64
7883 UINT64_C(778051584), // USUBLv4i16_v4i32
7884 UINT64_C(1855987712), // USUBLv4i32_v2i64
7885 UINT64_C(1851793408), // USUBLv8i16_v4i32
7886 UINT64_C(773857280), // USUBLv8i8_v8i16
7887 UINT64_C(1170233344), // USUBWB_ZZZ_D
7888 UINT64_C(1161844736), // USUBWB_ZZZ_H
7889 UINT64_C(1166039040), // USUBWB_ZZZ_S
7890 UINT64_C(1170234368), // USUBWT_ZZZ_D
7891 UINT64_C(1161845760), // USUBWT_ZZZ_H
7892 UINT64_C(1166040064), // USUBWT_ZZZ_S
7893 UINT64_C(1847603200), // USUBWv16i8_v8i16
7894 UINT64_C(782249984), // USUBWv2i32_v2i64
7895 UINT64_C(778055680), // USUBWv4i16_v4i32
7896 UINT64_C(1855991808), // USUBWv4i32_v2i64
7897 UINT64_C(1851797504), // USUBWv8i16_v4i32
7898 UINT64_C(773861376), // USUBWv8i8_v8i16
7899 UINT64_C(3243278376), // USVDOT_VG4_M4ZZI_BToS
7900 UINT64_C(99825664), // UUNPKHI_ZZ_D
7901 UINT64_C(91437056), // UUNPKHI_ZZ_H
7902 UINT64_C(95631360), // UUNPKHI_ZZ_S
7903 UINT64_C(99760128), // UUNPKLO_ZZ_D
7904 UINT64_C(91371520), // UUNPKLO_ZZ_H
7905 UINT64_C(95565824), // UUNPKLO_ZZ_S
7906 UINT64_C(3253067777), // UUNPK_VG2_2ZZ_D
7907 UINT64_C(3244679169), // UUNPK_VG2_2ZZ_H
7908 UINT64_C(3248873473), // UUNPK_VG2_2ZZ_S
7909 UINT64_C(3254116353), // UUNPK_VG4_4Z2Z_D
7910 UINT64_C(3245727745), // UUNPK_VG4_4Z2Z_H
7911 UINT64_C(3249922049), // UUNPK_VG4_4Z2Z_S
7912 UINT64_C(3243245616), // UVDOT_VG2_M2ZZI_HtoS
7913 UINT64_C(3243278384), // UVDOT_VG4_M4ZZI_BtoS
7914 UINT64_C(3251669016), // UVDOT_VG4_M4ZZI_HtoD
7915 UINT64_C(80846848), // UXTB_ZPmZ_D
7916 UINT64_C(72458240), // UXTB_ZPmZ_H
7917 UINT64_C(76652544), // UXTB_ZPmZ_S
7918 UINT64_C(80977920), // UXTH_ZPmZ_D
7919 UINT64_C(76783616), // UXTH_ZPmZ_S
7920 UINT64_C(81108992), // UXTW_ZPmZ_D
7921 UINT64_C(86001664), // UZP1_PPP_B
7922 UINT64_C(98584576), // UZP1_PPP_D
7923 UINT64_C(90195968), // UZP1_PPP_H
7924 UINT64_C(94390272), // UZP1_PPP_S
7925 UINT64_C(86009856), // UZP1_ZZZ_B
7926 UINT64_C(98592768), // UZP1_ZZZ_D
7927 UINT64_C(90204160), // UZP1_ZZZ_H
7928 UINT64_C(94373888), // UZP1_ZZZ_Q
7929 UINT64_C(94398464), // UZP1_ZZZ_S
7930 UINT64_C(1308628992), // UZP1v16i8
7931 UINT64_C(243275776), // UZP1v2i32
7932 UINT64_C(1321211904), // UZP1v2i64
7933 UINT64_C(239081472), // UZP1v4i16
7934 UINT64_C(1317017600), // UZP1v4i32
7935 UINT64_C(1312823296), // UZP1v8i16
7936 UINT64_C(234887168), // UZP1v8i8
7937 UINT64_C(86002688), // UZP2_PPP_B
7938 UINT64_C(98585600), // UZP2_PPP_D
7939 UINT64_C(90196992), // UZP2_PPP_H
7940 UINT64_C(94391296), // UZP2_PPP_S
7941 UINT64_C(86010880), // UZP2_ZZZ_B
7942 UINT64_C(98593792), // UZP2_ZZZ_D
7943 UINT64_C(90205184), // UZP2_ZZZ_H
7944 UINT64_C(94374912), // UZP2_ZZZ_Q
7945 UINT64_C(94399488), // UZP2_ZZZ_S
7946 UINT64_C(1308645376), // UZP2v16i8
7947 UINT64_C(243292160), // UZP2v2i32
7948 UINT64_C(1321228288), // UZP2v2i64
7949 UINT64_C(239097856), // UZP2v4i16
7950 UINT64_C(1317033984), // UZP2v4i32
7951 UINT64_C(1312839680), // UZP2v8i16
7952 UINT64_C(234903552), // UZP2v8i8
7953 UINT64_C(1140910080), // UZPQ1_ZZZ_B
7954 UINT64_C(1153492992), // UZPQ1_ZZZ_D
7955 UINT64_C(1145104384), // UZPQ1_ZZZ_H
7956 UINT64_C(1149298688), // UZPQ1_ZZZ_S
7957 UINT64_C(1140911104), // UZPQ2_ZZZ_B
7958 UINT64_C(1153494016), // UZPQ2_ZZZ_D
7959 UINT64_C(1145105408), // UZPQ2_ZZZ_H
7960 UINT64_C(1149299712), // UZPQ2_ZZZ_S
7961 UINT64_C(3240153089), // UZP_VG2_2ZZZ_B
7962 UINT64_C(3252736001), // UZP_VG2_2ZZZ_D
7963 UINT64_C(3244347393), // UZP_VG2_2ZZZ_H
7964 UINT64_C(3240154113), // UZP_VG2_2ZZZ_Q
7965 UINT64_C(3248541697), // UZP_VG2_2ZZZ_S
7966 UINT64_C(3241598978), // UZP_VG4_4Z4Z_B
7967 UINT64_C(3254181890), // UZP_VG4_4Z4Z_D
7968 UINT64_C(3245793282), // UZP_VG4_4Z4Z_H
7969 UINT64_C(3241664514), // UZP_VG4_4Z4Z_Q
7970 UINT64_C(3249987586), // UZP_VG4_4Z4Z_S
7971 UINT64_C(3573747712), // WFET
7972 UINT64_C(3573747744), // WFIT
7973 UINT64_C(622874640), // WHILEGE_2PXX_B
7974 UINT64_C(635457552), // WHILEGE_2PXX_D
7975 UINT64_C(627068944), // WHILEGE_2PXX_H
7976 UINT64_C(631263248), // WHILEGE_2PXX_S
7977 UINT64_C(622870544), // WHILEGE_CXX_B
7978 UINT64_C(635453456), // WHILEGE_CXX_D
7979 UINT64_C(627064848), // WHILEGE_CXX_H
7980 UINT64_C(631259152), // WHILEGE_CXX_S
7981 UINT64_C(622854144), // WHILEGE_PWW_B
7982 UINT64_C(635437056), // WHILEGE_PWW_D
7983 UINT64_C(627048448), // WHILEGE_PWW_H
7984 UINT64_C(631242752), // WHILEGE_PWW_S
7985 UINT64_C(622858240), // WHILEGE_PXX_B
7986 UINT64_C(635441152), // WHILEGE_PXX_D
7987 UINT64_C(627052544), // WHILEGE_PXX_H
7988 UINT64_C(631246848), // WHILEGE_PXX_S
7989 UINT64_C(622874641), // WHILEGT_2PXX_B
7990 UINT64_C(635457553), // WHILEGT_2PXX_D
7991 UINT64_C(627068945), // WHILEGT_2PXX_H
7992 UINT64_C(631263249), // WHILEGT_2PXX_S
7993 UINT64_C(622870552), // WHILEGT_CXX_B
7994 UINT64_C(635453464), // WHILEGT_CXX_D
7995 UINT64_C(627064856), // WHILEGT_CXX_H
7996 UINT64_C(631259160), // WHILEGT_CXX_S
7997 UINT64_C(622854160), // WHILEGT_PWW_B
7998 UINT64_C(635437072), // WHILEGT_PWW_D
7999 UINT64_C(627048464), // WHILEGT_PWW_H
8000 UINT64_C(631242768), // WHILEGT_PWW_S
8001 UINT64_C(622858256), // WHILEGT_PXX_B
8002 UINT64_C(635441168), // WHILEGT_PXX_D
8003 UINT64_C(627052560), // WHILEGT_PXX_H
8004 UINT64_C(631246864), // WHILEGT_PXX_S
8005 UINT64_C(622876689), // WHILEHI_2PXX_B
8006 UINT64_C(635459601), // WHILEHI_2PXX_D
8007 UINT64_C(627070993), // WHILEHI_2PXX_H
8008 UINT64_C(631265297), // WHILEHI_2PXX_S
8009 UINT64_C(622872600), // WHILEHI_CXX_B
8010 UINT64_C(635455512), // WHILEHI_CXX_D
8011 UINT64_C(627066904), // WHILEHI_CXX_H
8012 UINT64_C(631261208), // WHILEHI_CXX_S
8013 UINT64_C(622856208), // WHILEHI_PWW_B
8014 UINT64_C(635439120), // WHILEHI_PWW_D
8015 UINT64_C(627050512), // WHILEHI_PWW_H
8016 UINT64_C(631244816), // WHILEHI_PWW_S
8017 UINT64_C(622860304), // WHILEHI_PXX_B
8018 UINT64_C(635443216), // WHILEHI_PXX_D
8019 UINT64_C(627054608), // WHILEHI_PXX_H
8020 UINT64_C(631248912), // WHILEHI_PXX_S
8021 UINT64_C(622876688), // WHILEHS_2PXX_B
8022 UINT64_C(635459600), // WHILEHS_2PXX_D
8023 UINT64_C(627070992), // WHILEHS_2PXX_H
8024 UINT64_C(631265296), // WHILEHS_2PXX_S
8025 UINT64_C(622872592), // WHILEHS_CXX_B
8026 UINT64_C(635455504), // WHILEHS_CXX_D
8027 UINT64_C(627066896), // WHILEHS_CXX_H
8028 UINT64_C(631261200), // WHILEHS_CXX_S
8029 UINT64_C(622856192), // WHILEHS_PWW_B
8030 UINT64_C(635439104), // WHILEHS_PWW_D
8031 UINT64_C(627050496), // WHILEHS_PWW_H
8032 UINT64_C(631244800), // WHILEHS_PWW_S
8033 UINT64_C(622860288), // WHILEHS_PXX_B
8034 UINT64_C(635443200), // WHILEHS_PXX_D
8035 UINT64_C(627054592), // WHILEHS_PXX_H
8036 UINT64_C(631248896), // WHILEHS_PXX_S
8037 UINT64_C(622875665), // WHILELE_2PXX_B
8038 UINT64_C(635458577), // WHILELE_2PXX_D
8039 UINT64_C(627069969), // WHILELE_2PXX_H
8040 UINT64_C(631264273), // WHILELE_2PXX_S
8041 UINT64_C(622871576), // WHILELE_CXX_B
8042 UINT64_C(635454488), // WHILELE_CXX_D
8043 UINT64_C(627065880), // WHILELE_CXX_H
8044 UINT64_C(631260184), // WHILELE_CXX_S
8045 UINT64_C(622855184), // WHILELE_PWW_B
8046 UINT64_C(635438096), // WHILELE_PWW_D
8047 UINT64_C(627049488), // WHILELE_PWW_H
8048 UINT64_C(631243792), // WHILELE_PWW_S
8049 UINT64_C(622859280), // WHILELE_PXX_B
8050 UINT64_C(635442192), // WHILELE_PXX_D
8051 UINT64_C(627053584), // WHILELE_PXX_H
8052 UINT64_C(631247888), // WHILELE_PXX_S
8053 UINT64_C(622877712), // WHILELO_2PXX_B
8054 UINT64_C(635460624), // WHILELO_2PXX_D
8055 UINT64_C(627072016), // WHILELO_2PXX_H
8056 UINT64_C(631266320), // WHILELO_2PXX_S
8057 UINT64_C(622873616), // WHILELO_CXX_B
8058 UINT64_C(635456528), // WHILELO_CXX_D
8059 UINT64_C(627067920), // WHILELO_CXX_H
8060 UINT64_C(631262224), // WHILELO_CXX_S
8061 UINT64_C(622857216), // WHILELO_PWW_B
8062 UINT64_C(635440128), // WHILELO_PWW_D
8063 UINT64_C(627051520), // WHILELO_PWW_H
8064 UINT64_C(631245824), // WHILELO_PWW_S
8065 UINT64_C(622861312), // WHILELO_PXX_B
8066 UINT64_C(635444224), // WHILELO_PXX_D
8067 UINT64_C(627055616), // WHILELO_PXX_H
8068 UINT64_C(631249920), // WHILELO_PXX_S
8069 UINT64_C(622877713), // WHILELS_2PXX_B
8070 UINT64_C(635460625), // WHILELS_2PXX_D
8071 UINT64_C(627072017), // WHILELS_2PXX_H
8072 UINT64_C(631266321), // WHILELS_2PXX_S
8073 UINT64_C(622873624), // WHILELS_CXX_B
8074 UINT64_C(635456536), // WHILELS_CXX_D
8075 UINT64_C(627067928), // WHILELS_CXX_H
8076 UINT64_C(631262232), // WHILELS_CXX_S
8077 UINT64_C(622857232), // WHILELS_PWW_B
8078 UINT64_C(635440144), // WHILELS_PWW_D
8079 UINT64_C(627051536), // WHILELS_PWW_H
8080 UINT64_C(631245840), // WHILELS_PWW_S
8081 UINT64_C(622861328), // WHILELS_PXX_B
8082 UINT64_C(635444240), // WHILELS_PXX_D
8083 UINT64_C(627055632), // WHILELS_PXX_H
8084 UINT64_C(631249936), // WHILELS_PXX_S
8085 UINT64_C(622875664), // WHILELT_2PXX_B
8086 UINT64_C(635458576), // WHILELT_2PXX_D
8087 UINT64_C(627069968), // WHILELT_2PXX_H
8088 UINT64_C(631264272), // WHILELT_2PXX_S
8089 UINT64_C(622871568), // WHILELT_CXX_B
8090 UINT64_C(635454480), // WHILELT_CXX_D
8091 UINT64_C(627065872), // WHILELT_CXX_H
8092 UINT64_C(631260176), // WHILELT_CXX_S
8093 UINT64_C(622855168), // WHILELT_PWW_B
8094 UINT64_C(635438080), // WHILELT_PWW_D
8095 UINT64_C(627049472), // WHILELT_PWW_H
8096 UINT64_C(631243776), // WHILELT_PWW_S
8097 UINT64_C(622859264), // WHILELT_PXX_B
8098 UINT64_C(635442176), // WHILELT_PXX_D
8099 UINT64_C(627053568), // WHILELT_PXX_H
8100 UINT64_C(631247872), // WHILELT_PXX_S
8101 UINT64_C(622866448), // WHILERW_PXX_B
8102 UINT64_C(635449360), // WHILERW_PXX_D
8103 UINT64_C(627060752), // WHILERW_PXX_H
8104 UINT64_C(631255056), // WHILERW_PXX_S
8105 UINT64_C(622866432), // WHILEWR_PXX_B
8106 UINT64_C(635449344), // WHILEWR_PXX_D
8107 UINT64_C(627060736), // WHILEWR_PXX_H
8108 UINT64_C(631255040), // WHILEWR_PXX_S
8109 UINT64_C(623415296), // WRFFR
8110 UINT64_C(3573563455), // XAFLAG
8111 UINT64_C(3464495104), // XAR
8112 UINT64_C(69743616), // XAR_ZZZI_B
8113 UINT64_C(77607936), // XAR_ZZZI_D
8114 UINT64_C(70267904), // XAR_ZZZI_H
8115 UINT64_C(73413632), // XAR_ZZZI_S
8116 UINT64_C(3670099936), // XPACD
8117 UINT64_C(3670098912), // XPACI
8118 UINT64_C(3573752063), // XPACLRI
8119 UINT64_C(1310795776), // XTNv16i8
8120 UINT64_C(245442560), // XTNv2i32
8121 UINT64_C(241248256), // XTNv4i16
8122 UINT64_C(1319184384), // XTNv4i32
8123 UINT64_C(1314990080), // XTNv8i16
8124 UINT64_C(237053952), // XTNv8i8
8125 UINT64_C(3221749760), // ZERO_M
8126 UINT64_C(3222044672), // ZERO_MXI_2Z
8127 UINT64_C(3222175744), // ZERO_MXI_4Z
8128 UINT64_C(3222077440), // ZERO_MXI_VG2_2Z
8129 UINT64_C(3222208512), // ZERO_MXI_VG2_4Z
8130 UINT64_C(3222011904), // ZERO_MXI_VG2_Z
8131 UINT64_C(3222110208), // ZERO_MXI_VG4_2Z
8132 UINT64_C(3222241280), // ZERO_MXI_VG4_4Z
8133 UINT64_C(3222142976), // ZERO_MXI_VG4_Z
8134 UINT64_C(3225944065), // ZERO_T
8135 UINT64_C(85999616), // ZIP1_PPP_B
8136 UINT64_C(98582528), // ZIP1_PPP_D
8137 UINT64_C(90193920), // ZIP1_PPP_H
8138 UINT64_C(94388224), // ZIP1_PPP_S
8139 UINT64_C(86007808), // ZIP1_ZZZ_B
8140 UINT64_C(98590720), // ZIP1_ZZZ_D
8141 UINT64_C(90202112), // ZIP1_ZZZ_H
8142 UINT64_C(94371840), // ZIP1_ZZZ_Q
8143 UINT64_C(94396416), // ZIP1_ZZZ_S
8144 UINT64_C(1308637184), // ZIP1v16i8
8145 UINT64_C(243283968), // ZIP1v2i32
8146 UINT64_C(1321220096), // ZIP1v2i64
8147 UINT64_C(239089664), // ZIP1v4i16
8148 UINT64_C(1317025792), // ZIP1v4i32
8149 UINT64_C(1312831488), // ZIP1v8i16
8150 UINT64_C(234895360), // ZIP1v8i8
8151 UINT64_C(86000640), // ZIP2_PPP_B
8152 UINT64_C(98583552), // ZIP2_PPP_D
8153 UINT64_C(90194944), // ZIP2_PPP_H
8154 UINT64_C(94389248), // ZIP2_PPP_S
8155 UINT64_C(86008832), // ZIP2_ZZZ_B
8156 UINT64_C(98591744), // ZIP2_ZZZ_D
8157 UINT64_C(90203136), // ZIP2_ZZZ_H
8158 UINT64_C(94372864), // ZIP2_ZZZ_Q
8159 UINT64_C(94397440), // ZIP2_ZZZ_S
8160 UINT64_C(1308653568), // ZIP2v16i8
8161 UINT64_C(243300352), // ZIP2v2i32
8162 UINT64_C(1321236480), // ZIP2v2i64
8163 UINT64_C(239106048), // ZIP2v4i16
8164 UINT64_C(1317042176), // ZIP2v4i32
8165 UINT64_C(1312847872), // ZIP2v8i16
8166 UINT64_C(234911744), // ZIP2v8i8
8167 UINT64_C(1140908032), // ZIPQ1_ZZZ_B
8168 UINT64_C(1153490944), // ZIPQ1_ZZZ_D
8169 UINT64_C(1145102336), // ZIPQ1_ZZZ_H
8170 UINT64_C(1149296640), // ZIPQ1_ZZZ_S
8171 UINT64_C(1140909056), // ZIPQ2_ZZZ_B
8172 UINT64_C(1153491968), // ZIPQ2_ZZZ_D
8173 UINT64_C(1145103360), // ZIPQ2_ZZZ_H
8174 UINT64_C(1149297664), // ZIPQ2_ZZZ_S
8175 UINT64_C(3240153088), // ZIP_VG2_2ZZZ_B
8176 UINT64_C(3252736000), // ZIP_VG2_2ZZZ_D
8177 UINT64_C(3244347392), // ZIP_VG2_2ZZZ_H
8178 UINT64_C(3240154112), // ZIP_VG2_2ZZZ_Q
8179 UINT64_C(3248541696), // ZIP_VG2_2ZZZ_S
8180 UINT64_C(3241598976), // ZIP_VG4_4Z4Z_B
8181 UINT64_C(3254181888), // ZIP_VG4_4Z4Z_D
8182 UINT64_C(3245793280), // ZIP_VG4_4Z4Z_H
8183 UINT64_C(3241664512), // ZIP_VG4_4Z4Z_Q
8184 UINT64_C(3249987584), // ZIP_VG4_4Z4Z_S
8185 UINT64_C(0)
8186 };
8187 const unsigned opcode = MI.getOpcode();
8188 uint64_t Value = InstBits[opcode];
8189 uint64_t op = 0;
8190 (void)op; // suppress warning
8191 switch (opcode) {
8192 case AArch64::AUTIA1716:
8193 case AArch64::AUTIA171615:
8194 case AArch64::AUTIASP:
8195 case AArch64::AUTIAZ:
8196 case AArch64::AUTIB1716:
8197 case AArch64::AUTIB171615:
8198 case AArch64::AUTIBSP:
8199 case AArch64::AUTIBZ:
8200 case AArch64::AXFLAG:
8201 case AArch64::BRB_IALL:
8202 case AArch64::BRB_INJ:
8203 case AArch64::CFINV:
8204 case AArch64::CHKFEAT:
8205 case AArch64::DRPS:
8206 case AArch64::ERET:
8207 case AArch64::ERETAA:
8208 case AArch64::ERETAB:
8209 case AArch64::GCSPOPCX:
8210 case AArch64::GCSPOPX:
8211 case AArch64::GCSPUSHX:
8212 case AArch64::PACIA1716:
8213 case AArch64::PACIA171615:
8214 case AArch64::PACIASP:
8215 case AArch64::PACIASPPC:
8216 case AArch64::PACIAZ:
8217 case AArch64::PACIB1716:
8218 case AArch64::PACIB171615:
8219 case AArch64::PACIBSP:
8220 case AArch64::PACIBSPPC:
8221 case AArch64::PACIBZ:
8222 case AArch64::PACM:
8223 case AArch64::PACNBIASPPC:
8224 case AArch64::PACNBIBSPPC:
8225 case AArch64::RETAA:
8226 case AArch64::RETAB:
8227 case AArch64::SB:
8228 case AArch64::SETFFR:
8229 case AArch64::TCOMMIT:
8230 case AArch64::TSB:
8231 case AArch64::XAFLAG:
8232 case AArch64::XPACLRI:
8233 case AArch64::ZERO_T: {
8234 break;
8235 }
8236 case AArch64::DSBnXS: {
8237 // op: CRm
8238 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8239 op &= UINT64_C(12);
8240 op <<= 8;
8241 Value |= op;
8242 break;
8243 }
8244 case AArch64::CLREX:
8245 case AArch64::DMB:
8246 case AArch64::DSB:
8247 case AArch64::ISB: {
8248 // op: CRm
8249 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8250 op &= UINT64_C(15);
8251 op <<= 8;
8252 Value |= op;
8253 break;
8254 }
8255 case AArch64::PTRUE_C_B:
8256 case AArch64::PTRUE_C_D:
8257 case AArch64::PTRUE_C_H:
8258 case AArch64::PTRUE_C_S: {
8259 // op: PNd
8260 op = EncodePNR_p8to15(MI, OpIdx: 0, Fixups, STI);
8261 op &= UINT64_C(7);
8262 Value |= op;
8263 break;
8264 }
8265 case AArch64::WHILEGE_CXX_B:
8266 case AArch64::WHILEGE_CXX_D:
8267 case AArch64::WHILEGE_CXX_H:
8268 case AArch64::WHILEGE_CXX_S:
8269 case AArch64::WHILEGT_CXX_B:
8270 case AArch64::WHILEGT_CXX_D:
8271 case AArch64::WHILEGT_CXX_H:
8272 case AArch64::WHILEGT_CXX_S:
8273 case AArch64::WHILEHI_CXX_B:
8274 case AArch64::WHILEHI_CXX_D:
8275 case AArch64::WHILEHI_CXX_H:
8276 case AArch64::WHILEHI_CXX_S:
8277 case AArch64::WHILEHS_CXX_B:
8278 case AArch64::WHILEHS_CXX_D:
8279 case AArch64::WHILEHS_CXX_H:
8280 case AArch64::WHILEHS_CXX_S:
8281 case AArch64::WHILELE_CXX_B:
8282 case AArch64::WHILELE_CXX_D:
8283 case AArch64::WHILELE_CXX_H:
8284 case AArch64::WHILELE_CXX_S:
8285 case AArch64::WHILELO_CXX_B:
8286 case AArch64::WHILELO_CXX_D:
8287 case AArch64::WHILELO_CXX_H:
8288 case AArch64::WHILELO_CXX_S:
8289 case AArch64::WHILELS_CXX_B:
8290 case AArch64::WHILELS_CXX_D:
8291 case AArch64::WHILELS_CXX_H:
8292 case AArch64::WHILELS_CXX_S:
8293 case AArch64::WHILELT_CXX_B:
8294 case AArch64::WHILELT_CXX_D:
8295 case AArch64::WHILELT_CXX_H:
8296 case AArch64::WHILELT_CXX_S: {
8297 // op: PNd
8298 op = EncodePNR_p8to15(MI, OpIdx: 0, Fixups, STI);
8299 op &= UINT64_C(7);
8300 Value |= op;
8301 // op: Rn
8302 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8303 op &= UINT64_C(31);
8304 op <<= 5;
8305 Value |= op;
8306 // op: vl
8307 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8308 op &= UINT64_C(1);
8309 op <<= 13;
8310 Value |= op;
8311 // op: Rm
8312 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8313 op &= UINT64_C(31);
8314 op <<= 16;
8315 Value |= op;
8316 break;
8317 }
8318 case AArch64::SEL_VG2_2ZC2Z2Z_B:
8319 case AArch64::SEL_VG2_2ZC2Z2Z_D:
8320 case AArch64::SEL_VG2_2ZC2Z2Z_H:
8321 case AArch64::SEL_VG2_2ZC2Z2Z_S: {
8322 // op: PNg
8323 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
8324 op &= UINT64_C(7);
8325 op <<= 10;
8326 Value |= op;
8327 // op: Zm
8328 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 3, Fixups, STI);
8329 op &= UINT64_C(15);
8330 op <<= 17;
8331 Value |= op;
8332 // op: Zn
8333 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 2, Fixups, STI);
8334 op &= UINT64_C(15);
8335 op <<= 6;
8336 Value |= op;
8337 // op: Zd
8338 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
8339 op &= UINT64_C(15);
8340 op <<= 1;
8341 Value |= op;
8342 break;
8343 }
8344 case AArch64::SEL_VG4_4ZC4Z4Z_B:
8345 case AArch64::SEL_VG4_4ZC4Z4Z_D:
8346 case AArch64::SEL_VG4_4ZC4Z4Z_H:
8347 case AArch64::SEL_VG4_4ZC4Z4Z_S: {
8348 // op: PNg
8349 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
8350 op &= UINT64_C(7);
8351 op <<= 10;
8352 Value |= op;
8353 // op: Zm
8354 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 3, Fixups, STI);
8355 op &= UINT64_C(7);
8356 op <<= 18;
8357 Value |= op;
8358 // op: Zn
8359 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 2, Fixups, STI);
8360 op &= UINT64_C(7);
8361 op <<= 7;
8362 Value |= op;
8363 // op: Zd
8364 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
8365 op &= UINT64_C(7);
8366 op <<= 2;
8367 Value |= op;
8368 break;
8369 }
8370 case AArch64::WHILEGE_2PXX_B:
8371 case AArch64::WHILEGE_2PXX_D:
8372 case AArch64::WHILEGE_2PXX_H:
8373 case AArch64::WHILEGE_2PXX_S:
8374 case AArch64::WHILEGT_2PXX_B:
8375 case AArch64::WHILEGT_2PXX_D:
8376 case AArch64::WHILEGT_2PXX_H:
8377 case AArch64::WHILEGT_2PXX_S:
8378 case AArch64::WHILEHI_2PXX_B:
8379 case AArch64::WHILEHI_2PXX_D:
8380 case AArch64::WHILEHI_2PXX_H:
8381 case AArch64::WHILEHI_2PXX_S:
8382 case AArch64::WHILEHS_2PXX_B:
8383 case AArch64::WHILEHS_2PXX_D:
8384 case AArch64::WHILEHS_2PXX_H:
8385 case AArch64::WHILEHS_2PXX_S:
8386 case AArch64::WHILELE_2PXX_B:
8387 case AArch64::WHILELE_2PXX_D:
8388 case AArch64::WHILELE_2PXX_H:
8389 case AArch64::WHILELE_2PXX_S:
8390 case AArch64::WHILELO_2PXX_B:
8391 case AArch64::WHILELO_2PXX_D:
8392 case AArch64::WHILELO_2PXX_H:
8393 case AArch64::WHILELO_2PXX_S:
8394 case AArch64::WHILELS_2PXX_B:
8395 case AArch64::WHILELS_2PXX_D:
8396 case AArch64::WHILELS_2PXX_H:
8397 case AArch64::WHILELS_2PXX_S:
8398 case AArch64::WHILELT_2PXX_B:
8399 case AArch64::WHILELT_2PXX_D:
8400 case AArch64::WHILELT_2PXX_H:
8401 case AArch64::WHILELT_2PXX_S: {
8402 // op: Pd
8403 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
8404 op &= UINT64_C(7);
8405 op <<= 1;
8406 Value |= op;
8407 // op: Rn
8408 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8409 op &= UINT64_C(31);
8410 op <<= 5;
8411 Value |= op;
8412 // op: Rm
8413 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8414 op &= UINT64_C(31);
8415 op <<= 16;
8416 Value |= op;
8417 break;
8418 }
8419 case AArch64::PFALSE:
8420 case AArch64::RDFFR_P: {
8421 // op: Pd
8422 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8423 op &= UINT64_C(15);
8424 Value |= op;
8425 break;
8426 }
8427 case AArch64::PEXT_2PCI_B:
8428 case AArch64::PEXT_2PCI_D:
8429 case AArch64::PEXT_2PCI_H:
8430 case AArch64::PEXT_2PCI_S: {
8431 // op: Pd
8432 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8433 op &= UINT64_C(15);
8434 Value |= op;
8435 // op: PNn
8436 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
8437 op &= UINT64_C(7);
8438 op <<= 5;
8439 Value |= op;
8440 // op: index
8441 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8442 op &= UINT64_C(1);
8443 op <<= 8;
8444 Value |= op;
8445 break;
8446 }
8447 case AArch64::PEXT_PCI_B:
8448 case AArch64::PEXT_PCI_D:
8449 case AArch64::PEXT_PCI_H:
8450 case AArch64::PEXT_PCI_S: {
8451 // op: Pd
8452 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8453 op &= UINT64_C(15);
8454 Value |= op;
8455 // op: PNn
8456 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
8457 op &= UINT64_C(7);
8458 op <<= 5;
8459 Value |= op;
8460 // op: index
8461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8462 op &= UINT64_C(3);
8463 op <<= 8;
8464 Value |= op;
8465 break;
8466 }
8467 case AArch64::ANDS_PPzPP:
8468 case AArch64::AND_PPzPP:
8469 case AArch64::BICS_PPzPP:
8470 case AArch64::BIC_PPzPP:
8471 case AArch64::BRKPAS_PPzPP:
8472 case AArch64::BRKPA_PPzPP:
8473 case AArch64::BRKPBS_PPzPP:
8474 case AArch64::BRKPB_PPzPP:
8475 case AArch64::EORS_PPzPP:
8476 case AArch64::EOR_PPzPP:
8477 case AArch64::NANDS_PPzPP:
8478 case AArch64::NAND_PPzPP:
8479 case AArch64::NORS_PPzPP:
8480 case AArch64::NOR_PPzPP:
8481 case AArch64::ORNS_PPzPP:
8482 case AArch64::ORN_PPzPP:
8483 case AArch64::ORRS_PPzPP:
8484 case AArch64::ORR_PPzPP:
8485 case AArch64::SEL_PPPP: {
8486 // op: Pd
8487 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8488 op &= UINT64_C(15);
8489 Value |= op;
8490 // op: Pg
8491 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8492 op &= UINT64_C(15);
8493 op <<= 10;
8494 Value |= op;
8495 // op: Pm
8496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8497 op &= UINT64_C(15);
8498 op <<= 16;
8499 Value |= op;
8500 // op: Pn
8501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8502 op &= UINT64_C(15);
8503 op <<= 5;
8504 Value |= op;
8505 break;
8506 }
8507 case AArch64::BRKAS_PPzP:
8508 case AArch64::BRKA_PPzP:
8509 case AArch64::BRKBS_PPzP:
8510 case AArch64::BRKB_PPzP: {
8511 // op: Pd
8512 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8513 op &= UINT64_C(15);
8514 Value |= op;
8515 // op: Pg
8516 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8517 op &= UINT64_C(15);
8518 op <<= 10;
8519 Value |= op;
8520 // op: Pn
8521 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8522 op &= UINT64_C(15);
8523 op <<= 5;
8524 Value |= op;
8525 break;
8526 }
8527 case AArch64::RDFFRS_PPz:
8528 case AArch64::RDFFR_PPz: {
8529 // op: Pd
8530 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8531 op &= UINT64_C(15);
8532 Value |= op;
8533 // op: Pg
8534 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8535 op &= UINT64_C(15);
8536 op <<= 5;
8537 Value |= op;
8538 break;
8539 }
8540 case AArch64::CMPEQ_PPzZZ_B:
8541 case AArch64::CMPEQ_PPzZZ_D:
8542 case AArch64::CMPEQ_PPzZZ_H:
8543 case AArch64::CMPEQ_PPzZZ_S:
8544 case AArch64::CMPEQ_WIDE_PPzZZ_B:
8545 case AArch64::CMPEQ_WIDE_PPzZZ_H:
8546 case AArch64::CMPEQ_WIDE_PPzZZ_S:
8547 case AArch64::CMPGE_PPzZZ_B:
8548 case AArch64::CMPGE_PPzZZ_D:
8549 case AArch64::CMPGE_PPzZZ_H:
8550 case AArch64::CMPGE_PPzZZ_S:
8551 case AArch64::CMPGE_WIDE_PPzZZ_B:
8552 case AArch64::CMPGE_WIDE_PPzZZ_H:
8553 case AArch64::CMPGE_WIDE_PPzZZ_S:
8554 case AArch64::CMPGT_PPzZZ_B:
8555 case AArch64::CMPGT_PPzZZ_D:
8556 case AArch64::CMPGT_PPzZZ_H:
8557 case AArch64::CMPGT_PPzZZ_S:
8558 case AArch64::CMPGT_WIDE_PPzZZ_B:
8559 case AArch64::CMPGT_WIDE_PPzZZ_H:
8560 case AArch64::CMPGT_WIDE_PPzZZ_S:
8561 case AArch64::CMPHI_PPzZZ_B:
8562 case AArch64::CMPHI_PPzZZ_D:
8563 case AArch64::CMPHI_PPzZZ_H:
8564 case AArch64::CMPHI_PPzZZ_S:
8565 case AArch64::CMPHI_WIDE_PPzZZ_B:
8566 case AArch64::CMPHI_WIDE_PPzZZ_H:
8567 case AArch64::CMPHI_WIDE_PPzZZ_S:
8568 case AArch64::CMPHS_PPzZZ_B:
8569 case AArch64::CMPHS_PPzZZ_D:
8570 case AArch64::CMPHS_PPzZZ_H:
8571 case AArch64::CMPHS_PPzZZ_S:
8572 case AArch64::CMPHS_WIDE_PPzZZ_B:
8573 case AArch64::CMPHS_WIDE_PPzZZ_H:
8574 case AArch64::CMPHS_WIDE_PPzZZ_S:
8575 case AArch64::CMPLE_WIDE_PPzZZ_B:
8576 case AArch64::CMPLE_WIDE_PPzZZ_H:
8577 case AArch64::CMPLE_WIDE_PPzZZ_S:
8578 case AArch64::CMPLO_WIDE_PPzZZ_B:
8579 case AArch64::CMPLO_WIDE_PPzZZ_H:
8580 case AArch64::CMPLO_WIDE_PPzZZ_S:
8581 case AArch64::CMPLS_WIDE_PPzZZ_B:
8582 case AArch64::CMPLS_WIDE_PPzZZ_H:
8583 case AArch64::CMPLS_WIDE_PPzZZ_S:
8584 case AArch64::CMPLT_WIDE_PPzZZ_B:
8585 case AArch64::CMPLT_WIDE_PPzZZ_H:
8586 case AArch64::CMPLT_WIDE_PPzZZ_S:
8587 case AArch64::CMPNE_PPzZZ_B:
8588 case AArch64::CMPNE_PPzZZ_D:
8589 case AArch64::CMPNE_PPzZZ_H:
8590 case AArch64::CMPNE_PPzZZ_S:
8591 case AArch64::CMPNE_WIDE_PPzZZ_B:
8592 case AArch64::CMPNE_WIDE_PPzZZ_H:
8593 case AArch64::CMPNE_WIDE_PPzZZ_S:
8594 case AArch64::FACGE_PPzZZ_D:
8595 case AArch64::FACGE_PPzZZ_H:
8596 case AArch64::FACGE_PPzZZ_S:
8597 case AArch64::FACGT_PPzZZ_D:
8598 case AArch64::FACGT_PPzZZ_H:
8599 case AArch64::FACGT_PPzZZ_S:
8600 case AArch64::FCMEQ_PPzZZ_D:
8601 case AArch64::FCMEQ_PPzZZ_H:
8602 case AArch64::FCMEQ_PPzZZ_S:
8603 case AArch64::FCMGE_PPzZZ_D:
8604 case AArch64::FCMGE_PPzZZ_H:
8605 case AArch64::FCMGE_PPzZZ_S:
8606 case AArch64::FCMGT_PPzZZ_D:
8607 case AArch64::FCMGT_PPzZZ_H:
8608 case AArch64::FCMGT_PPzZZ_S:
8609 case AArch64::FCMNE_PPzZZ_D:
8610 case AArch64::FCMNE_PPzZZ_H:
8611 case AArch64::FCMNE_PPzZZ_S:
8612 case AArch64::FCMUO_PPzZZ_D:
8613 case AArch64::FCMUO_PPzZZ_H:
8614 case AArch64::FCMUO_PPzZZ_S:
8615 case AArch64::MATCH_PPzZZ_B:
8616 case AArch64::MATCH_PPzZZ_H:
8617 case AArch64::NMATCH_PPzZZ_B:
8618 case AArch64::NMATCH_PPzZZ_H: {
8619 // op: Pd
8620 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8621 op &= UINT64_C(15);
8622 Value |= op;
8623 // op: Pg
8624 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8625 op &= UINT64_C(7);
8626 op <<= 10;
8627 Value |= op;
8628 // op: Zm
8629 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8630 op &= UINT64_C(31);
8631 op <<= 16;
8632 Value |= op;
8633 // op: Zn
8634 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8635 op &= UINT64_C(31);
8636 op <<= 5;
8637 Value |= op;
8638 break;
8639 }
8640 case AArch64::FCMEQ_PPzZ0_D:
8641 case AArch64::FCMEQ_PPzZ0_H:
8642 case AArch64::FCMEQ_PPzZ0_S:
8643 case AArch64::FCMGE_PPzZ0_D:
8644 case AArch64::FCMGE_PPzZ0_H:
8645 case AArch64::FCMGE_PPzZ0_S:
8646 case AArch64::FCMGT_PPzZ0_D:
8647 case AArch64::FCMGT_PPzZ0_H:
8648 case AArch64::FCMGT_PPzZ0_S:
8649 case AArch64::FCMLE_PPzZ0_D:
8650 case AArch64::FCMLE_PPzZ0_H:
8651 case AArch64::FCMLE_PPzZ0_S:
8652 case AArch64::FCMLT_PPzZ0_D:
8653 case AArch64::FCMLT_PPzZ0_H:
8654 case AArch64::FCMLT_PPzZ0_S:
8655 case AArch64::FCMNE_PPzZ0_D:
8656 case AArch64::FCMNE_PPzZ0_H:
8657 case AArch64::FCMNE_PPzZ0_S: {
8658 // op: Pd
8659 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8660 op &= UINT64_C(15);
8661 Value |= op;
8662 // op: Pg
8663 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8664 op &= UINT64_C(7);
8665 op <<= 10;
8666 Value |= op;
8667 // op: Zn
8668 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8669 op &= UINT64_C(31);
8670 op <<= 5;
8671 Value |= op;
8672 break;
8673 }
8674 case AArch64::CMPEQ_PPzZI_B:
8675 case AArch64::CMPEQ_PPzZI_D:
8676 case AArch64::CMPEQ_PPzZI_H:
8677 case AArch64::CMPEQ_PPzZI_S:
8678 case AArch64::CMPGE_PPzZI_B:
8679 case AArch64::CMPGE_PPzZI_D:
8680 case AArch64::CMPGE_PPzZI_H:
8681 case AArch64::CMPGE_PPzZI_S:
8682 case AArch64::CMPGT_PPzZI_B:
8683 case AArch64::CMPGT_PPzZI_D:
8684 case AArch64::CMPGT_PPzZI_H:
8685 case AArch64::CMPGT_PPzZI_S:
8686 case AArch64::CMPLE_PPzZI_B:
8687 case AArch64::CMPLE_PPzZI_D:
8688 case AArch64::CMPLE_PPzZI_H:
8689 case AArch64::CMPLE_PPzZI_S:
8690 case AArch64::CMPLT_PPzZI_B:
8691 case AArch64::CMPLT_PPzZI_D:
8692 case AArch64::CMPLT_PPzZI_H:
8693 case AArch64::CMPLT_PPzZI_S:
8694 case AArch64::CMPNE_PPzZI_B:
8695 case AArch64::CMPNE_PPzZI_D:
8696 case AArch64::CMPNE_PPzZI_H:
8697 case AArch64::CMPNE_PPzZI_S: {
8698 // op: Pd
8699 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8700 op &= UINT64_C(15);
8701 Value |= op;
8702 // op: Pg
8703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8704 op &= UINT64_C(7);
8705 op <<= 10;
8706 Value |= op;
8707 // op: Zn
8708 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8709 op &= UINT64_C(31);
8710 op <<= 5;
8711 Value |= op;
8712 // op: imm5
8713 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8714 op &= UINT64_C(31);
8715 op <<= 16;
8716 Value |= op;
8717 break;
8718 }
8719 case AArch64::CMPHI_PPzZI_B:
8720 case AArch64::CMPHI_PPzZI_D:
8721 case AArch64::CMPHI_PPzZI_H:
8722 case AArch64::CMPHI_PPzZI_S:
8723 case AArch64::CMPHS_PPzZI_B:
8724 case AArch64::CMPHS_PPzZI_D:
8725 case AArch64::CMPHS_PPzZI_H:
8726 case AArch64::CMPHS_PPzZI_S:
8727 case AArch64::CMPLO_PPzZI_B:
8728 case AArch64::CMPLO_PPzZI_D:
8729 case AArch64::CMPLO_PPzZI_H:
8730 case AArch64::CMPLO_PPzZI_S:
8731 case AArch64::CMPLS_PPzZI_B:
8732 case AArch64::CMPLS_PPzZI_D:
8733 case AArch64::CMPLS_PPzZI_H:
8734 case AArch64::CMPLS_PPzZI_S: {
8735 // op: Pd
8736 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8737 op &= UINT64_C(15);
8738 Value |= op;
8739 // op: Pg
8740 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8741 op &= UINT64_C(7);
8742 op <<= 10;
8743 Value |= op;
8744 // op: Zn
8745 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8746 op &= UINT64_C(31);
8747 op <<= 5;
8748 Value |= op;
8749 // op: imm7
8750 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8751 op &= UINT64_C(127);
8752 op <<= 14;
8753 Value |= op;
8754 break;
8755 }
8756 case AArch64::BRKA_PPmP:
8757 case AArch64::BRKB_PPmP: {
8758 // op: Pd
8759 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8760 op &= UINT64_C(15);
8761 Value |= op;
8762 // op: Pg
8763 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8764 op &= UINT64_C(15);
8765 op <<= 10;
8766 Value |= op;
8767 // op: Pn
8768 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
8769 op &= UINT64_C(15);
8770 op <<= 5;
8771 Value |= op;
8772 break;
8773 }
8774 case AArch64::TRN1_PPP_B:
8775 case AArch64::TRN1_PPP_D:
8776 case AArch64::TRN1_PPP_H:
8777 case AArch64::TRN1_PPP_S:
8778 case AArch64::TRN2_PPP_B:
8779 case AArch64::TRN2_PPP_D:
8780 case AArch64::TRN2_PPP_H:
8781 case AArch64::TRN2_PPP_S:
8782 case AArch64::UZP1_PPP_B:
8783 case AArch64::UZP1_PPP_D:
8784 case AArch64::UZP1_PPP_H:
8785 case AArch64::UZP1_PPP_S:
8786 case AArch64::UZP2_PPP_B:
8787 case AArch64::UZP2_PPP_D:
8788 case AArch64::UZP2_PPP_H:
8789 case AArch64::UZP2_PPP_S:
8790 case AArch64::ZIP1_PPP_B:
8791 case AArch64::ZIP1_PPP_D:
8792 case AArch64::ZIP1_PPP_H:
8793 case AArch64::ZIP1_PPP_S:
8794 case AArch64::ZIP2_PPP_B:
8795 case AArch64::ZIP2_PPP_D:
8796 case AArch64::ZIP2_PPP_H:
8797 case AArch64::ZIP2_PPP_S: {
8798 // op: Pd
8799 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8800 op &= UINT64_C(15);
8801 Value |= op;
8802 // op: Pm
8803 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8804 op &= UINT64_C(15);
8805 op <<= 16;
8806 Value |= op;
8807 // op: Pn
8808 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8809 op &= UINT64_C(15);
8810 op <<= 5;
8811 Value |= op;
8812 break;
8813 }
8814 case AArch64::PUNPKHI_PP:
8815 case AArch64::PUNPKLO_PP:
8816 case AArch64::REV_PP_B:
8817 case AArch64::REV_PP_D:
8818 case AArch64::REV_PP_H:
8819 case AArch64::REV_PP_S: {
8820 // op: Pd
8821 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8822 op &= UINT64_C(15);
8823 Value |= op;
8824 // op: Pn
8825 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8826 op &= UINT64_C(15);
8827 op <<= 5;
8828 Value |= op;
8829 break;
8830 }
8831 case AArch64::WHILEGE_PWW_B:
8832 case AArch64::WHILEGE_PWW_D:
8833 case AArch64::WHILEGE_PWW_H:
8834 case AArch64::WHILEGE_PWW_S:
8835 case AArch64::WHILEGE_PXX_B:
8836 case AArch64::WHILEGE_PXX_D:
8837 case AArch64::WHILEGE_PXX_H:
8838 case AArch64::WHILEGE_PXX_S:
8839 case AArch64::WHILEGT_PWW_B:
8840 case AArch64::WHILEGT_PWW_D:
8841 case AArch64::WHILEGT_PWW_H:
8842 case AArch64::WHILEGT_PWW_S:
8843 case AArch64::WHILEGT_PXX_B:
8844 case AArch64::WHILEGT_PXX_D:
8845 case AArch64::WHILEGT_PXX_H:
8846 case AArch64::WHILEGT_PXX_S:
8847 case AArch64::WHILEHI_PWW_B:
8848 case AArch64::WHILEHI_PWW_D:
8849 case AArch64::WHILEHI_PWW_H:
8850 case AArch64::WHILEHI_PWW_S:
8851 case AArch64::WHILEHI_PXX_B:
8852 case AArch64::WHILEHI_PXX_D:
8853 case AArch64::WHILEHI_PXX_H:
8854 case AArch64::WHILEHI_PXX_S:
8855 case AArch64::WHILEHS_PWW_B:
8856 case AArch64::WHILEHS_PWW_D:
8857 case AArch64::WHILEHS_PWW_H:
8858 case AArch64::WHILEHS_PWW_S:
8859 case AArch64::WHILEHS_PXX_B:
8860 case AArch64::WHILEHS_PXX_D:
8861 case AArch64::WHILEHS_PXX_H:
8862 case AArch64::WHILEHS_PXX_S:
8863 case AArch64::WHILELE_PWW_B:
8864 case AArch64::WHILELE_PWW_D:
8865 case AArch64::WHILELE_PWW_H:
8866 case AArch64::WHILELE_PWW_S:
8867 case AArch64::WHILELE_PXX_B:
8868 case AArch64::WHILELE_PXX_D:
8869 case AArch64::WHILELE_PXX_H:
8870 case AArch64::WHILELE_PXX_S:
8871 case AArch64::WHILELO_PWW_B:
8872 case AArch64::WHILELO_PWW_D:
8873 case AArch64::WHILELO_PWW_H:
8874 case AArch64::WHILELO_PWW_S:
8875 case AArch64::WHILELO_PXX_B:
8876 case AArch64::WHILELO_PXX_D:
8877 case AArch64::WHILELO_PXX_H:
8878 case AArch64::WHILELO_PXX_S:
8879 case AArch64::WHILELS_PWW_B:
8880 case AArch64::WHILELS_PWW_D:
8881 case AArch64::WHILELS_PWW_H:
8882 case AArch64::WHILELS_PWW_S:
8883 case AArch64::WHILELS_PXX_B:
8884 case AArch64::WHILELS_PXX_D:
8885 case AArch64::WHILELS_PXX_H:
8886 case AArch64::WHILELS_PXX_S:
8887 case AArch64::WHILELT_PWW_B:
8888 case AArch64::WHILELT_PWW_D:
8889 case AArch64::WHILELT_PWW_H:
8890 case AArch64::WHILELT_PWW_S:
8891 case AArch64::WHILELT_PXX_B:
8892 case AArch64::WHILELT_PXX_D:
8893 case AArch64::WHILELT_PXX_H:
8894 case AArch64::WHILELT_PXX_S:
8895 case AArch64::WHILERW_PXX_B:
8896 case AArch64::WHILERW_PXX_D:
8897 case AArch64::WHILERW_PXX_H:
8898 case AArch64::WHILERW_PXX_S:
8899 case AArch64::WHILEWR_PXX_B:
8900 case AArch64::WHILEWR_PXX_D:
8901 case AArch64::WHILEWR_PXX_H:
8902 case AArch64::WHILEWR_PXX_S: {
8903 // op: Pd
8904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8905 op &= UINT64_C(15);
8906 Value |= op;
8907 // op: Rm
8908 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8909 op &= UINT64_C(31);
8910 op <<= 16;
8911 Value |= op;
8912 // op: Rn
8913 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8914 op &= UINT64_C(31);
8915 op <<= 5;
8916 Value |= op;
8917 break;
8918 }
8919 case AArch64::PMOV_PZI_B: {
8920 // op: Pd
8921 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8922 op &= UINT64_C(15);
8923 Value |= op;
8924 // op: Zn
8925 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8926 op &= UINT64_C(31);
8927 op <<= 5;
8928 Value |= op;
8929 break;
8930 }
8931 case AArch64::PMOV_PZI_D: {
8932 // op: Pd
8933 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8934 op &= UINT64_C(15);
8935 Value |= op;
8936 // op: Zn
8937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8938 op &= UINT64_C(31);
8939 op <<= 5;
8940 Value |= op;
8941 // op: index
8942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8943 Value |= (op & UINT64_C(4)) << 20;
8944 Value |= (op & UINT64_C(3)) << 17;
8945 break;
8946 }
8947 case AArch64::PMOV_PZI_H: {
8948 // op: Pd
8949 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8950 op &= UINT64_C(15);
8951 Value |= op;
8952 // op: Zn
8953 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8954 op &= UINT64_C(31);
8955 op <<= 5;
8956 Value |= op;
8957 // op: index
8958 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8959 op &= UINT64_C(1);
8960 op <<= 17;
8961 Value |= op;
8962 break;
8963 }
8964 case AArch64::PMOV_PZI_S: {
8965 // op: Pd
8966 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8967 op &= UINT64_C(15);
8968 Value |= op;
8969 // op: Zn
8970 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8971 op &= UINT64_C(31);
8972 op <<= 5;
8973 Value |= op;
8974 // op: index
8975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
8976 op &= UINT64_C(3);
8977 op <<= 17;
8978 Value |= op;
8979 break;
8980 }
8981 case AArch64::PTRUES_B:
8982 case AArch64::PTRUES_D:
8983 case AArch64::PTRUES_H:
8984 case AArch64::PTRUES_S:
8985 case AArch64::PTRUE_B:
8986 case AArch64::PTRUE_D:
8987 case AArch64::PTRUE_H:
8988 case AArch64::PTRUE_S: {
8989 // op: Pd
8990 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
8991 op &= UINT64_C(15);
8992 Value |= op;
8993 // op: pattern
8994 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
8995 op &= UINT64_C(31);
8996 op <<= 5;
8997 Value |= op;
8998 break;
8999 }
9000 case AArch64::BRKNS_PPzP:
9001 case AArch64::BRKN_PPzP: {
9002 // op: Pdm
9003 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9004 op &= UINT64_C(15);
9005 Value |= op;
9006 // op: Pg
9007 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9008 op &= UINT64_C(15);
9009 op <<= 10;
9010 Value |= op;
9011 // op: Pn
9012 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9013 op &= UINT64_C(15);
9014 op <<= 5;
9015 Value |= op;
9016 break;
9017 }
9018 case AArch64::PFIRST_B:
9019 case AArch64::PNEXT_B:
9020 case AArch64::PNEXT_D:
9021 case AArch64::PNEXT_H:
9022 case AArch64::PNEXT_S: {
9023 // op: Pdn
9024 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9025 op &= UINT64_C(15);
9026 Value |= op;
9027 // op: Pg
9028 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9029 op &= UINT64_C(15);
9030 op <<= 5;
9031 Value |= op;
9032 break;
9033 }
9034 case AArch64::PTEST_PP: {
9035 // op: Pg
9036 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9037 op &= UINT64_C(15);
9038 op <<= 10;
9039 Value |= op;
9040 // op: Pn
9041 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9042 op &= UINT64_C(15);
9043 op <<= 5;
9044 Value |= op;
9045 break;
9046 }
9047 case AArch64::CNTP_XPP_B:
9048 case AArch64::CNTP_XPP_D:
9049 case AArch64::CNTP_XPP_H:
9050 case AArch64::CNTP_XPP_S: {
9051 // op: Pg
9052 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9053 op &= UINT64_C(15);
9054 op <<= 10;
9055 Value |= op;
9056 // op: Pn
9057 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9058 op &= UINT64_C(15);
9059 op <<= 5;
9060 Value |= op;
9061 // op: Rd
9062 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9063 op &= UINT64_C(31);
9064 Value |= op;
9065 break;
9066 }
9067 case AArch64::SEL_ZPZZ_B:
9068 case AArch64::SEL_ZPZZ_D:
9069 case AArch64::SEL_ZPZZ_H:
9070 case AArch64::SEL_ZPZZ_S: {
9071 // op: Pg
9072 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9073 op &= UINT64_C(15);
9074 op <<= 10;
9075 Value |= op;
9076 // op: Zd
9077 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9078 op &= UINT64_C(31);
9079 Value |= op;
9080 // op: Zm
9081 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9082 op &= UINT64_C(31);
9083 op <<= 16;
9084 Value |= op;
9085 // op: Zn
9086 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9087 op &= UINT64_C(31);
9088 op <<= 5;
9089 Value |= op;
9090 break;
9091 }
9092 case AArch64::LASTA_RPZ_B:
9093 case AArch64::LASTA_RPZ_D:
9094 case AArch64::LASTA_RPZ_H:
9095 case AArch64::LASTA_RPZ_S:
9096 case AArch64::LASTB_RPZ_B:
9097 case AArch64::LASTB_RPZ_D:
9098 case AArch64::LASTB_RPZ_H:
9099 case AArch64::LASTB_RPZ_S: {
9100 // op: Pg
9101 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9102 op &= UINT64_C(7);
9103 op <<= 10;
9104 Value |= op;
9105 // op: Rd
9106 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9107 op &= UINT64_C(31);
9108 Value |= op;
9109 // op: Zn
9110 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9111 op &= UINT64_C(31);
9112 op <<= 5;
9113 Value |= op;
9114 break;
9115 }
9116 case AArch64::CLASTA_RPZ_B:
9117 case AArch64::CLASTA_RPZ_D:
9118 case AArch64::CLASTA_RPZ_H:
9119 case AArch64::CLASTA_RPZ_S:
9120 case AArch64::CLASTB_RPZ_B:
9121 case AArch64::CLASTB_RPZ_D:
9122 case AArch64::CLASTB_RPZ_H:
9123 case AArch64::CLASTB_RPZ_S: {
9124 // op: Pg
9125 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9126 op &= UINT64_C(7);
9127 op <<= 10;
9128 Value |= op;
9129 // op: Rdn
9130 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9131 op &= UINT64_C(31);
9132 Value |= op;
9133 // op: Zm
9134 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9135 op &= UINT64_C(31);
9136 op <<= 5;
9137 Value |= op;
9138 break;
9139 }
9140 case AArch64::LD2B:
9141 case AArch64::LD2D:
9142 case AArch64::LD2H:
9143 case AArch64::LD2Q:
9144 case AArch64::LD2W:
9145 case AArch64::LD3B:
9146 case AArch64::LD3D:
9147 case AArch64::LD3H:
9148 case AArch64::LD3Q:
9149 case AArch64::LD3W:
9150 case AArch64::LD4B:
9151 case AArch64::LD4D:
9152 case AArch64::LD4H:
9153 case AArch64::LD4Q:
9154 case AArch64::LD4W:
9155 case AArch64::LDNT1B_ZRR:
9156 case AArch64::LDNT1D_ZRR:
9157 case AArch64::LDNT1H_ZRR:
9158 case AArch64::LDNT1W_ZRR:
9159 case AArch64::ST1B:
9160 case AArch64::ST1B_D:
9161 case AArch64::ST1B_H:
9162 case AArch64::ST1B_S:
9163 case AArch64::ST1D:
9164 case AArch64::ST1D_Q:
9165 case AArch64::ST1H:
9166 case AArch64::ST1H_D:
9167 case AArch64::ST1H_S:
9168 case AArch64::ST1W:
9169 case AArch64::ST1W_D:
9170 case AArch64::ST1W_Q:
9171 case AArch64::ST2B:
9172 case AArch64::ST2D:
9173 case AArch64::ST2H:
9174 case AArch64::ST2W:
9175 case AArch64::ST3B:
9176 case AArch64::ST3D:
9177 case AArch64::ST3H:
9178 case AArch64::ST3W:
9179 case AArch64::ST4B:
9180 case AArch64::ST4D:
9181 case AArch64::ST4H:
9182 case AArch64::ST4W:
9183 case AArch64::STNT1B_ZRR:
9184 case AArch64::STNT1D_ZRR:
9185 case AArch64::STNT1H_ZRR:
9186 case AArch64::STNT1W_ZRR: {
9187 // op: Pg
9188 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9189 op &= UINT64_C(7);
9190 op <<= 10;
9191 Value |= op;
9192 // op: Rm
9193 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9194 op &= UINT64_C(31);
9195 op <<= 16;
9196 Value |= op;
9197 // op: Rn
9198 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9199 op &= UINT64_C(31);
9200 op <<= 5;
9201 Value |= op;
9202 // op: Zt
9203 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9204 op &= UINT64_C(31);
9205 Value |= op;
9206 break;
9207 }
9208 case AArch64::LDNT1B_ZZR_D:
9209 case AArch64::LDNT1B_ZZR_S:
9210 case AArch64::LDNT1D_ZZR_D:
9211 case AArch64::LDNT1H_ZZR_D:
9212 case AArch64::LDNT1H_ZZR_S:
9213 case AArch64::LDNT1SB_ZZR_D:
9214 case AArch64::LDNT1SB_ZZR_S:
9215 case AArch64::LDNT1SH_ZZR_D:
9216 case AArch64::LDNT1SH_ZZR_S:
9217 case AArch64::LDNT1SW_ZZR_D:
9218 case AArch64::LDNT1W_ZZR_D:
9219 case AArch64::LDNT1W_ZZR_S:
9220 case AArch64::STNT1B_ZZR_D:
9221 case AArch64::STNT1B_ZZR_S:
9222 case AArch64::STNT1D_ZZR_D:
9223 case AArch64::STNT1H_ZZR_D:
9224 case AArch64::STNT1H_ZZR_S:
9225 case AArch64::STNT1W_ZZR_D:
9226 case AArch64::STNT1W_ZZR_S: {
9227 // op: Pg
9228 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9229 op &= UINT64_C(7);
9230 op <<= 10;
9231 Value |= op;
9232 // op: Rm
9233 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9234 op &= UINT64_C(31);
9235 op <<= 16;
9236 Value |= op;
9237 // op: Zn
9238 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9239 op &= UINT64_C(31);
9240 op <<= 5;
9241 Value |= op;
9242 // op: Zt
9243 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9244 op &= UINT64_C(31);
9245 Value |= op;
9246 break;
9247 }
9248 case AArch64::GLD1B_D:
9249 case AArch64::GLD1B_D_SXTW:
9250 case AArch64::GLD1B_D_UXTW:
9251 case AArch64::GLD1B_S_SXTW:
9252 case AArch64::GLD1B_S_UXTW:
9253 case AArch64::GLD1D:
9254 case AArch64::GLD1D_SCALED:
9255 case AArch64::GLD1D_SXTW:
9256 case AArch64::GLD1D_SXTW_SCALED:
9257 case AArch64::GLD1D_UXTW:
9258 case AArch64::GLD1D_UXTW_SCALED:
9259 case AArch64::GLD1H_D:
9260 case AArch64::GLD1H_D_SCALED:
9261 case AArch64::GLD1H_D_SXTW:
9262 case AArch64::GLD1H_D_SXTW_SCALED:
9263 case AArch64::GLD1H_D_UXTW:
9264 case AArch64::GLD1H_D_UXTW_SCALED:
9265 case AArch64::GLD1H_S_SXTW:
9266 case AArch64::GLD1H_S_SXTW_SCALED:
9267 case AArch64::GLD1H_S_UXTW:
9268 case AArch64::GLD1H_S_UXTW_SCALED:
9269 case AArch64::GLD1SB_D:
9270 case AArch64::GLD1SB_D_SXTW:
9271 case AArch64::GLD1SB_D_UXTW:
9272 case AArch64::GLD1SB_S_SXTW:
9273 case AArch64::GLD1SB_S_UXTW:
9274 case AArch64::GLD1SH_D:
9275 case AArch64::GLD1SH_D_SCALED:
9276 case AArch64::GLD1SH_D_SXTW:
9277 case AArch64::GLD1SH_D_SXTW_SCALED:
9278 case AArch64::GLD1SH_D_UXTW:
9279 case AArch64::GLD1SH_D_UXTW_SCALED:
9280 case AArch64::GLD1SH_S_SXTW:
9281 case AArch64::GLD1SH_S_SXTW_SCALED:
9282 case AArch64::GLD1SH_S_UXTW:
9283 case AArch64::GLD1SH_S_UXTW_SCALED:
9284 case AArch64::GLD1SW_D:
9285 case AArch64::GLD1SW_D_SCALED:
9286 case AArch64::GLD1SW_D_SXTW:
9287 case AArch64::GLD1SW_D_SXTW_SCALED:
9288 case AArch64::GLD1SW_D_UXTW:
9289 case AArch64::GLD1SW_D_UXTW_SCALED:
9290 case AArch64::GLD1W_D:
9291 case AArch64::GLD1W_D_SCALED:
9292 case AArch64::GLD1W_D_SXTW:
9293 case AArch64::GLD1W_D_SXTW_SCALED:
9294 case AArch64::GLD1W_D_UXTW:
9295 case AArch64::GLD1W_D_UXTW_SCALED:
9296 case AArch64::GLD1W_SXTW:
9297 case AArch64::GLD1W_SXTW_SCALED:
9298 case AArch64::GLD1W_UXTW:
9299 case AArch64::GLD1W_UXTW_SCALED:
9300 case AArch64::GLDFF1B_D:
9301 case AArch64::GLDFF1B_D_SXTW:
9302 case AArch64::GLDFF1B_D_UXTW:
9303 case AArch64::GLDFF1B_S_SXTW:
9304 case AArch64::GLDFF1B_S_UXTW:
9305 case AArch64::GLDFF1D:
9306 case AArch64::GLDFF1D_SCALED:
9307 case AArch64::GLDFF1D_SXTW:
9308 case AArch64::GLDFF1D_SXTW_SCALED:
9309 case AArch64::GLDFF1D_UXTW:
9310 case AArch64::GLDFF1D_UXTW_SCALED:
9311 case AArch64::GLDFF1H_D:
9312 case AArch64::GLDFF1H_D_SCALED:
9313 case AArch64::GLDFF1H_D_SXTW:
9314 case AArch64::GLDFF1H_D_SXTW_SCALED:
9315 case AArch64::GLDFF1H_D_UXTW:
9316 case AArch64::GLDFF1H_D_UXTW_SCALED:
9317 case AArch64::GLDFF1H_S_SXTW:
9318 case AArch64::GLDFF1H_S_SXTW_SCALED:
9319 case AArch64::GLDFF1H_S_UXTW:
9320 case AArch64::GLDFF1H_S_UXTW_SCALED:
9321 case AArch64::GLDFF1SB_D:
9322 case AArch64::GLDFF1SB_D_SXTW:
9323 case AArch64::GLDFF1SB_D_UXTW:
9324 case AArch64::GLDFF1SB_S_SXTW:
9325 case AArch64::GLDFF1SB_S_UXTW:
9326 case AArch64::GLDFF1SH_D:
9327 case AArch64::GLDFF1SH_D_SCALED:
9328 case AArch64::GLDFF1SH_D_SXTW:
9329 case AArch64::GLDFF1SH_D_SXTW_SCALED:
9330 case AArch64::GLDFF1SH_D_UXTW:
9331 case AArch64::GLDFF1SH_D_UXTW_SCALED:
9332 case AArch64::GLDFF1SH_S_SXTW:
9333 case AArch64::GLDFF1SH_S_SXTW_SCALED:
9334 case AArch64::GLDFF1SH_S_UXTW:
9335 case AArch64::GLDFF1SH_S_UXTW_SCALED:
9336 case AArch64::GLDFF1SW_D:
9337 case AArch64::GLDFF1SW_D_SCALED:
9338 case AArch64::GLDFF1SW_D_SXTW:
9339 case AArch64::GLDFF1SW_D_SXTW_SCALED:
9340 case AArch64::GLDFF1SW_D_UXTW:
9341 case AArch64::GLDFF1SW_D_UXTW_SCALED:
9342 case AArch64::GLDFF1W_D:
9343 case AArch64::GLDFF1W_D_SCALED:
9344 case AArch64::GLDFF1W_D_SXTW:
9345 case AArch64::GLDFF1W_D_SXTW_SCALED:
9346 case AArch64::GLDFF1W_D_UXTW:
9347 case AArch64::GLDFF1W_D_UXTW_SCALED:
9348 case AArch64::GLDFF1W_SXTW:
9349 case AArch64::GLDFF1W_SXTW_SCALED:
9350 case AArch64::GLDFF1W_UXTW:
9351 case AArch64::GLDFF1W_UXTW_SCALED:
9352 case AArch64::SST1B_D:
9353 case AArch64::SST1B_D_SXTW:
9354 case AArch64::SST1B_D_UXTW:
9355 case AArch64::SST1B_S_SXTW:
9356 case AArch64::SST1B_S_UXTW:
9357 case AArch64::SST1D:
9358 case AArch64::SST1D_SCALED:
9359 case AArch64::SST1D_SXTW:
9360 case AArch64::SST1D_SXTW_SCALED:
9361 case AArch64::SST1D_UXTW:
9362 case AArch64::SST1D_UXTW_SCALED:
9363 case AArch64::SST1H_D:
9364 case AArch64::SST1H_D_SCALED:
9365 case AArch64::SST1H_D_SXTW:
9366 case AArch64::SST1H_D_SXTW_SCALED:
9367 case AArch64::SST1H_D_UXTW:
9368 case AArch64::SST1H_D_UXTW_SCALED:
9369 case AArch64::SST1H_S_SXTW:
9370 case AArch64::SST1H_S_SXTW_SCALED:
9371 case AArch64::SST1H_S_UXTW:
9372 case AArch64::SST1H_S_UXTW_SCALED:
9373 case AArch64::SST1W_D:
9374 case AArch64::SST1W_D_SCALED:
9375 case AArch64::SST1W_D_SXTW:
9376 case AArch64::SST1W_D_SXTW_SCALED:
9377 case AArch64::SST1W_D_UXTW:
9378 case AArch64::SST1W_D_UXTW_SCALED:
9379 case AArch64::SST1W_SXTW:
9380 case AArch64::SST1W_SXTW_SCALED:
9381 case AArch64::SST1W_UXTW:
9382 case AArch64::SST1W_UXTW_SCALED: {
9383 // op: Pg
9384 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9385 op &= UINT64_C(7);
9386 op <<= 10;
9387 Value |= op;
9388 // op: Rn
9389 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9390 op &= UINT64_C(31);
9391 op <<= 5;
9392 Value |= op;
9393 // op: Zm
9394 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9395 op &= UINT64_C(31);
9396 op <<= 16;
9397 Value |= op;
9398 // op: Zt
9399 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9400 op &= UINT64_C(31);
9401 Value |= op;
9402 break;
9403 }
9404 case AArch64::PRFB_D_SCALED:
9405 case AArch64::PRFB_D_SXTW_SCALED:
9406 case AArch64::PRFB_D_UXTW_SCALED:
9407 case AArch64::PRFB_S_SXTW_SCALED:
9408 case AArch64::PRFB_S_UXTW_SCALED:
9409 case AArch64::PRFD_D_SCALED:
9410 case AArch64::PRFD_D_SXTW_SCALED:
9411 case AArch64::PRFD_D_UXTW_SCALED:
9412 case AArch64::PRFD_S_SXTW_SCALED:
9413 case AArch64::PRFD_S_UXTW_SCALED:
9414 case AArch64::PRFH_D_SCALED:
9415 case AArch64::PRFH_D_SXTW_SCALED:
9416 case AArch64::PRFH_D_UXTW_SCALED:
9417 case AArch64::PRFH_S_SXTW_SCALED:
9418 case AArch64::PRFH_S_UXTW_SCALED:
9419 case AArch64::PRFW_D_SCALED:
9420 case AArch64::PRFW_D_SXTW_SCALED:
9421 case AArch64::PRFW_D_UXTW_SCALED:
9422 case AArch64::PRFW_S_SXTW_SCALED:
9423 case AArch64::PRFW_S_UXTW_SCALED: {
9424 // op: Pg
9425 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9426 op &= UINT64_C(7);
9427 op <<= 10;
9428 Value |= op;
9429 // op: Rn
9430 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9431 op &= UINT64_C(31);
9432 op <<= 5;
9433 Value |= op;
9434 // op: Zm
9435 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9436 op &= UINT64_C(31);
9437 op <<= 16;
9438 Value |= op;
9439 // op: prfop
9440 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9441 op &= UINT64_C(15);
9442 Value |= op;
9443 break;
9444 }
9445 case AArch64::LD1B_D_IMM:
9446 case AArch64::LD1B_H_IMM:
9447 case AArch64::LD1B_IMM:
9448 case AArch64::LD1B_S_IMM:
9449 case AArch64::LD1D_IMM:
9450 case AArch64::LD1H_D_IMM:
9451 case AArch64::LD1H_IMM:
9452 case AArch64::LD1H_S_IMM:
9453 case AArch64::LD1SB_D_IMM:
9454 case AArch64::LD1SB_H_IMM:
9455 case AArch64::LD1SB_S_IMM:
9456 case AArch64::LD1SH_D_IMM:
9457 case AArch64::LD1SH_S_IMM:
9458 case AArch64::LD1SW_D_IMM:
9459 case AArch64::LD1W_D_IMM:
9460 case AArch64::LD1W_IMM:
9461 case AArch64::LDNF1B_D_IMM:
9462 case AArch64::LDNF1B_H_IMM:
9463 case AArch64::LDNF1B_IMM:
9464 case AArch64::LDNF1B_S_IMM:
9465 case AArch64::LDNF1D_IMM:
9466 case AArch64::LDNF1H_D_IMM:
9467 case AArch64::LDNF1H_IMM:
9468 case AArch64::LDNF1H_S_IMM:
9469 case AArch64::LDNF1SB_D_IMM:
9470 case AArch64::LDNF1SB_H_IMM:
9471 case AArch64::LDNF1SB_S_IMM:
9472 case AArch64::LDNF1SH_D_IMM:
9473 case AArch64::LDNF1SH_S_IMM:
9474 case AArch64::LDNF1SW_D_IMM:
9475 case AArch64::LDNF1W_D_IMM:
9476 case AArch64::LDNF1W_IMM:
9477 case AArch64::ST1B_D_IMM:
9478 case AArch64::ST1B_H_IMM:
9479 case AArch64::ST1B_IMM:
9480 case AArch64::ST1B_S_IMM:
9481 case AArch64::ST1D_IMM:
9482 case AArch64::ST1D_Q_IMM:
9483 case AArch64::ST1H_D_IMM:
9484 case AArch64::ST1H_IMM:
9485 case AArch64::ST1H_S_IMM:
9486 case AArch64::ST1W_D_IMM:
9487 case AArch64::ST1W_IMM:
9488 case AArch64::ST1W_Q_IMM:
9489 case AArch64::ST2B_IMM:
9490 case AArch64::ST2D_IMM:
9491 case AArch64::ST2H_IMM:
9492 case AArch64::ST2W_IMM:
9493 case AArch64::ST3B_IMM:
9494 case AArch64::ST3D_IMM:
9495 case AArch64::ST3H_IMM:
9496 case AArch64::ST3W_IMM:
9497 case AArch64::ST4B_IMM:
9498 case AArch64::ST4D_IMM:
9499 case AArch64::ST4H_IMM:
9500 case AArch64::ST4W_IMM:
9501 case AArch64::STNT1B_ZRI:
9502 case AArch64::STNT1D_ZRI:
9503 case AArch64::STNT1H_ZRI:
9504 case AArch64::STNT1W_ZRI: {
9505 // op: Pg
9506 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9507 op &= UINT64_C(7);
9508 op <<= 10;
9509 Value |= op;
9510 // op: Rn
9511 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9512 op &= UINT64_C(31);
9513 op <<= 5;
9514 Value |= op;
9515 // op: Zt
9516 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9517 op &= UINT64_C(31);
9518 Value |= op;
9519 // op: imm4
9520 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9521 op &= UINT64_C(15);
9522 op <<= 16;
9523 Value |= op;
9524 break;
9525 }
9526 case AArch64::LD1RB_D_IMM:
9527 case AArch64::LD1RB_H_IMM:
9528 case AArch64::LD1RB_IMM:
9529 case AArch64::LD1RB_S_IMM:
9530 case AArch64::LD1RD_IMM:
9531 case AArch64::LD1RH_D_IMM:
9532 case AArch64::LD1RH_IMM:
9533 case AArch64::LD1RH_S_IMM:
9534 case AArch64::LD1RSB_D_IMM:
9535 case AArch64::LD1RSB_H_IMM:
9536 case AArch64::LD1RSB_S_IMM:
9537 case AArch64::LD1RSH_D_IMM:
9538 case AArch64::LD1RSH_S_IMM:
9539 case AArch64::LD1RSW_IMM:
9540 case AArch64::LD1RW_D_IMM:
9541 case AArch64::LD1RW_IMM: {
9542 // op: Pg
9543 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9544 op &= UINT64_C(7);
9545 op <<= 10;
9546 Value |= op;
9547 // op: Rn
9548 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9549 op &= UINT64_C(31);
9550 op <<= 5;
9551 Value |= op;
9552 // op: Zt
9553 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9554 op &= UINT64_C(31);
9555 Value |= op;
9556 // op: imm6
9557 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9558 op &= UINT64_C(63);
9559 op <<= 16;
9560 Value |= op;
9561 break;
9562 }
9563 case AArch64::ANDV_VPZ_B:
9564 case AArch64::ANDV_VPZ_D:
9565 case AArch64::ANDV_VPZ_H:
9566 case AArch64::ANDV_VPZ_S:
9567 case AArch64::EORV_VPZ_B:
9568 case AArch64::EORV_VPZ_D:
9569 case AArch64::EORV_VPZ_H:
9570 case AArch64::EORV_VPZ_S:
9571 case AArch64::LASTA_VPZ_B:
9572 case AArch64::LASTA_VPZ_D:
9573 case AArch64::LASTA_VPZ_H:
9574 case AArch64::LASTA_VPZ_S:
9575 case AArch64::LASTB_VPZ_B:
9576 case AArch64::LASTB_VPZ_D:
9577 case AArch64::LASTB_VPZ_H:
9578 case AArch64::LASTB_VPZ_S:
9579 case AArch64::ORV_VPZ_B:
9580 case AArch64::ORV_VPZ_D:
9581 case AArch64::ORV_VPZ_H:
9582 case AArch64::ORV_VPZ_S:
9583 case AArch64::SADDV_VPZ_B:
9584 case AArch64::SADDV_VPZ_H:
9585 case AArch64::SADDV_VPZ_S:
9586 case AArch64::SMAXV_VPZ_B:
9587 case AArch64::SMAXV_VPZ_D:
9588 case AArch64::SMAXV_VPZ_H:
9589 case AArch64::SMAXV_VPZ_S:
9590 case AArch64::SMINV_VPZ_B:
9591 case AArch64::SMINV_VPZ_D:
9592 case AArch64::SMINV_VPZ_H:
9593 case AArch64::SMINV_VPZ_S:
9594 case AArch64::UADDV_VPZ_B:
9595 case AArch64::UADDV_VPZ_D:
9596 case AArch64::UADDV_VPZ_H:
9597 case AArch64::UADDV_VPZ_S:
9598 case AArch64::UMAXV_VPZ_B:
9599 case AArch64::UMAXV_VPZ_D:
9600 case AArch64::UMAXV_VPZ_H:
9601 case AArch64::UMAXV_VPZ_S:
9602 case AArch64::UMINV_VPZ_B:
9603 case AArch64::UMINV_VPZ_D:
9604 case AArch64::UMINV_VPZ_H:
9605 case AArch64::UMINV_VPZ_S: {
9606 // op: Pg
9607 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9608 op &= UINT64_C(7);
9609 op <<= 10;
9610 Value |= op;
9611 // op: Vd
9612 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9613 op &= UINT64_C(31);
9614 Value |= op;
9615 // op: Zn
9616 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9617 op &= UINT64_C(31);
9618 op <<= 5;
9619 Value |= op;
9620 break;
9621 }
9622 case AArch64::CLASTA_VPZ_B:
9623 case AArch64::CLASTA_VPZ_D:
9624 case AArch64::CLASTA_VPZ_H:
9625 case AArch64::CLASTA_VPZ_S:
9626 case AArch64::CLASTB_VPZ_B:
9627 case AArch64::CLASTB_VPZ_D:
9628 case AArch64::CLASTB_VPZ_H:
9629 case AArch64::CLASTB_VPZ_S:
9630 case AArch64::FADDA_VPZ_D:
9631 case AArch64::FADDA_VPZ_H:
9632 case AArch64::FADDA_VPZ_S: {
9633 // op: Pg
9634 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9635 op &= UINT64_C(7);
9636 op <<= 10;
9637 Value |= op;
9638 // op: Vdn
9639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9640 op &= UINT64_C(31);
9641 Value |= op;
9642 // op: Zm
9643 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9644 op &= UINT64_C(31);
9645 op <<= 5;
9646 Value |= op;
9647 break;
9648 }
9649 case AArch64::FMAD_ZPmZZ_D:
9650 case AArch64::FMAD_ZPmZZ_H:
9651 case AArch64::FMAD_ZPmZZ_S:
9652 case AArch64::FMSB_ZPmZZ_D:
9653 case AArch64::FMSB_ZPmZZ_H:
9654 case AArch64::FMSB_ZPmZZ_S:
9655 case AArch64::FNMAD_ZPmZZ_D:
9656 case AArch64::FNMAD_ZPmZZ_H:
9657 case AArch64::FNMAD_ZPmZZ_S:
9658 case AArch64::FNMSB_ZPmZZ_D:
9659 case AArch64::FNMSB_ZPmZZ_H:
9660 case AArch64::FNMSB_ZPmZZ_S: {
9661 // op: Pg
9662 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9663 op &= UINT64_C(7);
9664 op <<= 10;
9665 Value |= op;
9666 // op: Za
9667 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
9668 op &= UINT64_C(31);
9669 op <<= 16;
9670 Value |= op;
9671 // op: Zdn
9672 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9673 op &= UINT64_C(31);
9674 Value |= op;
9675 // op: Zm
9676 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9677 op &= UINT64_C(31);
9678 op <<= 5;
9679 Value |= op;
9680 break;
9681 }
9682 case AArch64::COMPACT_ZPZ_D:
9683 case AArch64::COMPACT_ZPZ_S:
9684 case AArch64::MOVPRFX_ZPzZ_B:
9685 case AArch64::MOVPRFX_ZPzZ_D:
9686 case AArch64::MOVPRFX_ZPzZ_H:
9687 case AArch64::MOVPRFX_ZPzZ_S: {
9688 // op: Pg
9689 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9690 op &= UINT64_C(7);
9691 op <<= 10;
9692 Value |= op;
9693 // op: Zd
9694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9695 op &= UINT64_C(31);
9696 Value |= op;
9697 // op: Zn
9698 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
9699 op &= UINT64_C(31);
9700 op <<= 5;
9701 Value |= op;
9702 break;
9703 }
9704 case AArch64::BFMLA_ZPmZZ:
9705 case AArch64::BFMLS_ZPmZZ:
9706 case AArch64::FMLA_ZPmZZ_D:
9707 case AArch64::FMLA_ZPmZZ_H:
9708 case AArch64::FMLA_ZPmZZ_S:
9709 case AArch64::FMLS_ZPmZZ_D:
9710 case AArch64::FMLS_ZPmZZ_H:
9711 case AArch64::FMLS_ZPmZZ_S:
9712 case AArch64::FNMLA_ZPmZZ_D:
9713 case AArch64::FNMLA_ZPmZZ_H:
9714 case AArch64::FNMLA_ZPmZZ_S:
9715 case AArch64::FNMLS_ZPmZZ_D:
9716 case AArch64::FNMLS_ZPmZZ_H:
9717 case AArch64::FNMLS_ZPmZZ_S:
9718 case AArch64::MLA_ZPmZZ_B:
9719 case AArch64::MLA_ZPmZZ_D:
9720 case AArch64::MLA_ZPmZZ_H:
9721 case AArch64::MLA_ZPmZZ_S:
9722 case AArch64::MLS_ZPmZZ_B:
9723 case AArch64::MLS_ZPmZZ_D:
9724 case AArch64::MLS_ZPmZZ_H:
9725 case AArch64::MLS_ZPmZZ_S: {
9726 // op: Pg
9727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9728 op &= UINT64_C(7);
9729 op <<= 10;
9730 Value |= op;
9731 // op: Zda
9732 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9733 op &= UINT64_C(31);
9734 Value |= op;
9735 // op: Zm
9736 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
9737 op &= UINT64_C(31);
9738 op <<= 16;
9739 Value |= op;
9740 // op: Zn
9741 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9742 op &= UINT64_C(31);
9743 op <<= 5;
9744 Value |= op;
9745 break;
9746 }
9747 case AArch64::MAD_ZPmZZ_B:
9748 case AArch64::MAD_ZPmZZ_D:
9749 case AArch64::MAD_ZPmZZ_H:
9750 case AArch64::MAD_ZPmZZ_S:
9751 case AArch64::MSB_ZPmZZ_B:
9752 case AArch64::MSB_ZPmZZ_D:
9753 case AArch64::MSB_ZPmZZ_H:
9754 case AArch64::MSB_ZPmZZ_S: {
9755 // op: Pg
9756 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9757 op &= UINT64_C(7);
9758 op <<= 10;
9759 Value |= op;
9760 // op: Zdn
9761 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9762 op &= UINT64_C(31);
9763 Value |= op;
9764 // op: Za
9765 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
9766 op &= UINT64_C(31);
9767 op <<= 5;
9768 Value |= op;
9769 // op: Zm
9770 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9771 op &= UINT64_C(31);
9772 op <<= 16;
9773 Value |= op;
9774 break;
9775 }
9776 case AArch64::ADD_ZPmZ_B:
9777 case AArch64::ADD_ZPmZ_CPA:
9778 case AArch64::ADD_ZPmZ_D:
9779 case AArch64::ADD_ZPmZ_H:
9780 case AArch64::ADD_ZPmZ_S:
9781 case AArch64::AND_ZPmZ_B:
9782 case AArch64::AND_ZPmZ_D:
9783 case AArch64::AND_ZPmZ_H:
9784 case AArch64::AND_ZPmZ_S:
9785 case AArch64::ASRR_ZPmZ_B:
9786 case AArch64::ASRR_ZPmZ_D:
9787 case AArch64::ASRR_ZPmZ_H:
9788 case AArch64::ASRR_ZPmZ_S:
9789 case AArch64::ASR_WIDE_ZPmZ_B:
9790 case AArch64::ASR_WIDE_ZPmZ_H:
9791 case AArch64::ASR_WIDE_ZPmZ_S:
9792 case AArch64::ASR_ZPmZ_B:
9793 case AArch64::ASR_ZPmZ_D:
9794 case AArch64::ASR_ZPmZ_H:
9795 case AArch64::ASR_ZPmZ_S:
9796 case AArch64::BFADD_ZPmZZ:
9797 case AArch64::BFMAXNM_ZPmZZ:
9798 case AArch64::BFMAX_ZPmZZ:
9799 case AArch64::BFMINNM_ZPmZZ:
9800 case AArch64::BFMIN_ZPmZZ:
9801 case AArch64::BFMUL_ZPmZZ:
9802 case AArch64::BFSUB_ZPmZZ:
9803 case AArch64::BIC_ZPmZ_B:
9804 case AArch64::BIC_ZPmZ_D:
9805 case AArch64::BIC_ZPmZ_H:
9806 case AArch64::BIC_ZPmZ_S:
9807 case AArch64::CLASTA_ZPZ_B:
9808 case AArch64::CLASTA_ZPZ_D:
9809 case AArch64::CLASTA_ZPZ_H:
9810 case AArch64::CLASTA_ZPZ_S:
9811 case AArch64::CLASTB_ZPZ_B:
9812 case AArch64::CLASTB_ZPZ_D:
9813 case AArch64::CLASTB_ZPZ_H:
9814 case AArch64::CLASTB_ZPZ_S:
9815 case AArch64::EOR_ZPmZ_B:
9816 case AArch64::EOR_ZPmZ_D:
9817 case AArch64::EOR_ZPmZ_H:
9818 case AArch64::EOR_ZPmZ_S:
9819 case AArch64::FABD_ZPmZ_D:
9820 case AArch64::FABD_ZPmZ_H:
9821 case AArch64::FABD_ZPmZ_S:
9822 case AArch64::FADD_ZPmZ_D:
9823 case AArch64::FADD_ZPmZ_H:
9824 case AArch64::FADD_ZPmZ_S:
9825 case AArch64::FAMAX_ZPmZ_D:
9826 case AArch64::FAMAX_ZPmZ_H:
9827 case AArch64::FAMAX_ZPmZ_S:
9828 case AArch64::FAMIN_ZPmZ_D:
9829 case AArch64::FAMIN_ZPmZ_H:
9830 case AArch64::FAMIN_ZPmZ_S:
9831 case AArch64::FDIVR_ZPmZ_D:
9832 case AArch64::FDIVR_ZPmZ_H:
9833 case AArch64::FDIVR_ZPmZ_S:
9834 case AArch64::FDIV_ZPmZ_D:
9835 case AArch64::FDIV_ZPmZ_H:
9836 case AArch64::FDIV_ZPmZ_S:
9837 case AArch64::FMAXNM_ZPmZ_D:
9838 case AArch64::FMAXNM_ZPmZ_H:
9839 case AArch64::FMAXNM_ZPmZ_S:
9840 case AArch64::FMAX_ZPmZ_D:
9841 case AArch64::FMAX_ZPmZ_H:
9842 case AArch64::FMAX_ZPmZ_S:
9843 case AArch64::FMINNM_ZPmZ_D:
9844 case AArch64::FMINNM_ZPmZ_H:
9845 case AArch64::FMINNM_ZPmZ_S:
9846 case AArch64::FMIN_ZPmZ_D:
9847 case AArch64::FMIN_ZPmZ_H:
9848 case AArch64::FMIN_ZPmZ_S:
9849 case AArch64::FMULX_ZPmZ_D:
9850 case AArch64::FMULX_ZPmZ_H:
9851 case AArch64::FMULX_ZPmZ_S:
9852 case AArch64::FMUL_ZPmZ_D:
9853 case AArch64::FMUL_ZPmZ_H:
9854 case AArch64::FMUL_ZPmZ_S:
9855 case AArch64::FSCALE_ZPmZ_D:
9856 case AArch64::FSCALE_ZPmZ_H:
9857 case AArch64::FSCALE_ZPmZ_S:
9858 case AArch64::FSUBR_ZPmZ_D:
9859 case AArch64::FSUBR_ZPmZ_H:
9860 case AArch64::FSUBR_ZPmZ_S:
9861 case AArch64::FSUB_ZPmZ_D:
9862 case AArch64::FSUB_ZPmZ_H:
9863 case AArch64::FSUB_ZPmZ_S:
9864 case AArch64::LSLR_ZPmZ_B:
9865 case AArch64::LSLR_ZPmZ_D:
9866 case AArch64::LSLR_ZPmZ_H:
9867 case AArch64::LSLR_ZPmZ_S:
9868 case AArch64::LSL_WIDE_ZPmZ_B:
9869 case AArch64::LSL_WIDE_ZPmZ_H:
9870 case AArch64::LSL_WIDE_ZPmZ_S:
9871 case AArch64::LSL_ZPmZ_B:
9872 case AArch64::LSL_ZPmZ_D:
9873 case AArch64::LSL_ZPmZ_H:
9874 case AArch64::LSL_ZPmZ_S:
9875 case AArch64::LSRR_ZPmZ_B:
9876 case AArch64::LSRR_ZPmZ_D:
9877 case AArch64::LSRR_ZPmZ_H:
9878 case AArch64::LSRR_ZPmZ_S:
9879 case AArch64::LSR_WIDE_ZPmZ_B:
9880 case AArch64::LSR_WIDE_ZPmZ_H:
9881 case AArch64::LSR_WIDE_ZPmZ_S:
9882 case AArch64::LSR_ZPmZ_B:
9883 case AArch64::LSR_ZPmZ_D:
9884 case AArch64::LSR_ZPmZ_H:
9885 case AArch64::LSR_ZPmZ_S:
9886 case AArch64::MUL_ZPmZ_B:
9887 case AArch64::MUL_ZPmZ_D:
9888 case AArch64::MUL_ZPmZ_H:
9889 case AArch64::MUL_ZPmZ_S:
9890 case AArch64::ORR_ZPmZ_B:
9891 case AArch64::ORR_ZPmZ_D:
9892 case AArch64::ORR_ZPmZ_H:
9893 case AArch64::ORR_ZPmZ_S:
9894 case AArch64::SABD_ZPmZ_B:
9895 case AArch64::SABD_ZPmZ_D:
9896 case AArch64::SABD_ZPmZ_H:
9897 case AArch64::SABD_ZPmZ_S:
9898 case AArch64::SDIVR_ZPmZ_D:
9899 case AArch64::SDIVR_ZPmZ_S:
9900 case AArch64::SDIV_ZPmZ_D:
9901 case AArch64::SDIV_ZPmZ_S:
9902 case AArch64::SMAX_ZPmZ_B:
9903 case AArch64::SMAX_ZPmZ_D:
9904 case AArch64::SMAX_ZPmZ_H:
9905 case AArch64::SMAX_ZPmZ_S:
9906 case AArch64::SMIN_ZPmZ_B:
9907 case AArch64::SMIN_ZPmZ_D:
9908 case AArch64::SMIN_ZPmZ_H:
9909 case AArch64::SMIN_ZPmZ_S:
9910 case AArch64::SMULH_ZPmZ_B:
9911 case AArch64::SMULH_ZPmZ_D:
9912 case AArch64::SMULH_ZPmZ_H:
9913 case AArch64::SMULH_ZPmZ_S:
9914 case AArch64::SPLICE_ZPZ_B:
9915 case AArch64::SPLICE_ZPZ_D:
9916 case AArch64::SPLICE_ZPZ_H:
9917 case AArch64::SPLICE_ZPZ_S:
9918 case AArch64::SUBR_ZPmZ_B:
9919 case AArch64::SUBR_ZPmZ_D:
9920 case AArch64::SUBR_ZPmZ_H:
9921 case AArch64::SUBR_ZPmZ_S:
9922 case AArch64::SUB_ZPmZ_B:
9923 case AArch64::SUB_ZPmZ_CPA:
9924 case AArch64::SUB_ZPmZ_D:
9925 case AArch64::SUB_ZPmZ_H:
9926 case AArch64::SUB_ZPmZ_S:
9927 case AArch64::UABD_ZPmZ_B:
9928 case AArch64::UABD_ZPmZ_D:
9929 case AArch64::UABD_ZPmZ_H:
9930 case AArch64::UABD_ZPmZ_S:
9931 case AArch64::UDIVR_ZPmZ_D:
9932 case AArch64::UDIVR_ZPmZ_S:
9933 case AArch64::UDIV_ZPmZ_D:
9934 case AArch64::UDIV_ZPmZ_S:
9935 case AArch64::UMAX_ZPmZ_B:
9936 case AArch64::UMAX_ZPmZ_D:
9937 case AArch64::UMAX_ZPmZ_H:
9938 case AArch64::UMAX_ZPmZ_S:
9939 case AArch64::UMIN_ZPmZ_B:
9940 case AArch64::UMIN_ZPmZ_D:
9941 case AArch64::UMIN_ZPmZ_H:
9942 case AArch64::UMIN_ZPmZ_S:
9943 case AArch64::UMULH_ZPmZ_B:
9944 case AArch64::UMULH_ZPmZ_D:
9945 case AArch64::UMULH_ZPmZ_H:
9946 case AArch64::UMULH_ZPmZ_S: {
9947 // op: Pg
9948 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9949 op &= UINT64_C(7);
9950 op <<= 10;
9951 Value |= op;
9952 // op: Zdn
9953 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9954 op &= UINT64_C(31);
9955 Value |= op;
9956 // op: Zm
9957 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9958 op &= UINT64_C(31);
9959 op <<= 5;
9960 Value |= op;
9961 break;
9962 }
9963 case AArch64::FADD_ZPmI_D:
9964 case AArch64::FADD_ZPmI_H:
9965 case AArch64::FADD_ZPmI_S:
9966 case AArch64::FMAXNM_ZPmI_D:
9967 case AArch64::FMAXNM_ZPmI_H:
9968 case AArch64::FMAXNM_ZPmI_S:
9969 case AArch64::FMAX_ZPmI_D:
9970 case AArch64::FMAX_ZPmI_H:
9971 case AArch64::FMAX_ZPmI_S:
9972 case AArch64::FMINNM_ZPmI_D:
9973 case AArch64::FMINNM_ZPmI_H:
9974 case AArch64::FMINNM_ZPmI_S:
9975 case AArch64::FMIN_ZPmI_D:
9976 case AArch64::FMIN_ZPmI_H:
9977 case AArch64::FMIN_ZPmI_S:
9978 case AArch64::FMUL_ZPmI_D:
9979 case AArch64::FMUL_ZPmI_H:
9980 case AArch64::FMUL_ZPmI_S:
9981 case AArch64::FSUBR_ZPmI_D:
9982 case AArch64::FSUBR_ZPmI_H:
9983 case AArch64::FSUBR_ZPmI_S:
9984 case AArch64::FSUB_ZPmI_D:
9985 case AArch64::FSUB_ZPmI_H:
9986 case AArch64::FSUB_ZPmI_S: {
9987 // op: Pg
9988 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
9989 op &= UINT64_C(7);
9990 op <<= 10;
9991 Value |= op;
9992 // op: Zdn
9993 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
9994 op &= UINT64_C(31);
9995 Value |= op;
9996 // op: i1
9997 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
9998 op &= UINT64_C(1);
9999 op <<= 5;
10000 Value |= op;
10001 break;
10002 }
10003 case AArch64::LSL_ZPmI_H:
10004 case AArch64::SQSHLU_ZPmI_H:
10005 case AArch64::SQSHL_ZPmI_H:
10006 case AArch64::UQSHL_ZPmI_H: {
10007 // op: Pg
10008 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10009 op &= UINT64_C(7);
10010 op <<= 10;
10011 Value |= op;
10012 // op: Zdn
10013 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10014 op &= UINT64_C(31);
10015 Value |= op;
10016 // op: imm
10017 op = getVecShiftL16OpValue(MI, OpIdx: 3, Fixups, STI);
10018 op &= UINT64_C(15);
10019 op <<= 5;
10020 Value |= op;
10021 break;
10022 }
10023 case AArch64::LSL_ZPmI_S:
10024 case AArch64::SQSHLU_ZPmI_S:
10025 case AArch64::SQSHL_ZPmI_S:
10026 case AArch64::UQSHL_ZPmI_S: {
10027 // op: Pg
10028 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10029 op &= UINT64_C(7);
10030 op <<= 10;
10031 Value |= op;
10032 // op: Zdn
10033 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10034 op &= UINT64_C(31);
10035 Value |= op;
10036 // op: imm
10037 op = getVecShiftL32OpValue(MI, OpIdx: 3, Fixups, STI);
10038 op &= UINT64_C(31);
10039 op <<= 5;
10040 Value |= op;
10041 break;
10042 }
10043 case AArch64::LSL_ZPmI_D:
10044 case AArch64::SQSHLU_ZPmI_D:
10045 case AArch64::SQSHL_ZPmI_D:
10046 case AArch64::UQSHL_ZPmI_D: {
10047 // op: Pg
10048 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10049 op &= UINT64_C(7);
10050 op <<= 10;
10051 Value |= op;
10052 // op: Zdn
10053 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10054 op &= UINT64_C(31);
10055 Value |= op;
10056 // op: imm
10057 op = getVecShiftL64OpValue(MI, OpIdx: 3, Fixups, STI);
10058 Value |= (op & UINT64_C(32)) << 17;
10059 Value |= (op & UINT64_C(31)) << 5;
10060 break;
10061 }
10062 case AArch64::LSL_ZPmI_B:
10063 case AArch64::SQSHLU_ZPmI_B:
10064 case AArch64::SQSHL_ZPmI_B:
10065 case AArch64::UQSHL_ZPmI_B: {
10066 // op: Pg
10067 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10068 op &= UINT64_C(7);
10069 op <<= 10;
10070 Value |= op;
10071 // op: Zdn
10072 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10073 op &= UINT64_C(31);
10074 Value |= op;
10075 // op: imm
10076 op = getVecShiftL8OpValue(MI, OpIdx: 3, Fixups, STI);
10077 op &= UINT64_C(7);
10078 op <<= 5;
10079 Value |= op;
10080 break;
10081 }
10082 case AArch64::ASRD_ZPmI_H:
10083 case AArch64::ASR_ZPmI_H:
10084 case AArch64::LSR_ZPmI_H:
10085 case AArch64::SRSHR_ZPmI_H:
10086 case AArch64::URSHR_ZPmI_H: {
10087 // op: Pg
10088 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10089 op &= UINT64_C(7);
10090 op <<= 10;
10091 Value |= op;
10092 // op: Zdn
10093 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10094 op &= UINT64_C(31);
10095 Value |= op;
10096 // op: imm
10097 op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI);
10098 op &= UINT64_C(15);
10099 op <<= 5;
10100 Value |= op;
10101 break;
10102 }
10103 case AArch64::ASRD_ZPmI_S:
10104 case AArch64::ASR_ZPmI_S:
10105 case AArch64::LSR_ZPmI_S:
10106 case AArch64::SRSHR_ZPmI_S:
10107 case AArch64::URSHR_ZPmI_S: {
10108 // op: Pg
10109 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10110 op &= UINT64_C(7);
10111 op <<= 10;
10112 Value |= op;
10113 // op: Zdn
10114 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10115 op &= UINT64_C(31);
10116 Value |= op;
10117 // op: imm
10118 op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI);
10119 op &= UINT64_C(31);
10120 op <<= 5;
10121 Value |= op;
10122 break;
10123 }
10124 case AArch64::ASRD_ZPmI_D:
10125 case AArch64::ASR_ZPmI_D:
10126 case AArch64::LSR_ZPmI_D:
10127 case AArch64::SRSHR_ZPmI_D:
10128 case AArch64::URSHR_ZPmI_D: {
10129 // op: Pg
10130 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10131 op &= UINT64_C(7);
10132 op <<= 10;
10133 Value |= op;
10134 // op: Zdn
10135 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10136 op &= UINT64_C(31);
10137 Value |= op;
10138 // op: imm
10139 op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI);
10140 Value |= (op & UINT64_C(32)) << 17;
10141 Value |= (op & UINT64_C(31)) << 5;
10142 break;
10143 }
10144 case AArch64::ASRD_ZPmI_B:
10145 case AArch64::ASR_ZPmI_B:
10146 case AArch64::LSR_ZPmI_B:
10147 case AArch64::SRSHR_ZPmI_B:
10148 case AArch64::URSHR_ZPmI_B: {
10149 // op: Pg
10150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10151 op &= UINT64_C(7);
10152 op <<= 10;
10153 Value |= op;
10154 // op: Zdn
10155 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10156 op &= UINT64_C(31);
10157 Value |= op;
10158 // op: imm
10159 op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI);
10160 op &= UINT64_C(7);
10161 op <<= 5;
10162 Value |= op;
10163 break;
10164 }
10165 case AArch64::ADDP_ZPmZ_B:
10166 case AArch64::ADDP_ZPmZ_D:
10167 case AArch64::ADDP_ZPmZ_H:
10168 case AArch64::ADDP_ZPmZ_S:
10169 case AArch64::FADDP_ZPmZZ_D:
10170 case AArch64::FADDP_ZPmZZ_H:
10171 case AArch64::FADDP_ZPmZZ_S:
10172 case AArch64::FMAXNMP_ZPmZZ_D:
10173 case AArch64::FMAXNMP_ZPmZZ_H:
10174 case AArch64::FMAXNMP_ZPmZZ_S:
10175 case AArch64::FMAXP_ZPmZZ_D:
10176 case AArch64::FMAXP_ZPmZZ_H:
10177 case AArch64::FMAXP_ZPmZZ_S:
10178 case AArch64::FMINNMP_ZPmZZ_D:
10179 case AArch64::FMINNMP_ZPmZZ_H:
10180 case AArch64::FMINNMP_ZPmZZ_S:
10181 case AArch64::FMINP_ZPmZZ_D:
10182 case AArch64::FMINP_ZPmZZ_H:
10183 case AArch64::FMINP_ZPmZZ_S:
10184 case AArch64::SHADD_ZPmZ_B:
10185 case AArch64::SHADD_ZPmZ_D:
10186 case AArch64::SHADD_ZPmZ_H:
10187 case AArch64::SHADD_ZPmZ_S:
10188 case AArch64::SHSUBR_ZPmZ_B:
10189 case AArch64::SHSUBR_ZPmZ_D:
10190 case AArch64::SHSUBR_ZPmZ_H:
10191 case AArch64::SHSUBR_ZPmZ_S:
10192 case AArch64::SHSUB_ZPmZ_B:
10193 case AArch64::SHSUB_ZPmZ_D:
10194 case AArch64::SHSUB_ZPmZ_H:
10195 case AArch64::SHSUB_ZPmZ_S:
10196 case AArch64::SMAXP_ZPmZ_B:
10197 case AArch64::SMAXP_ZPmZ_D:
10198 case AArch64::SMAXP_ZPmZ_H:
10199 case AArch64::SMAXP_ZPmZ_S:
10200 case AArch64::SMINP_ZPmZ_B:
10201 case AArch64::SMINP_ZPmZ_D:
10202 case AArch64::SMINP_ZPmZ_H:
10203 case AArch64::SMINP_ZPmZ_S:
10204 case AArch64::SQADD_ZPmZ_B:
10205 case AArch64::SQADD_ZPmZ_D:
10206 case AArch64::SQADD_ZPmZ_H:
10207 case AArch64::SQADD_ZPmZ_S:
10208 case AArch64::SQRSHLR_ZPmZ_B:
10209 case AArch64::SQRSHLR_ZPmZ_D:
10210 case AArch64::SQRSHLR_ZPmZ_H:
10211 case AArch64::SQRSHLR_ZPmZ_S:
10212 case AArch64::SQRSHL_ZPmZ_B:
10213 case AArch64::SQRSHL_ZPmZ_D:
10214 case AArch64::SQRSHL_ZPmZ_H:
10215 case AArch64::SQRSHL_ZPmZ_S:
10216 case AArch64::SQSHLR_ZPmZ_B:
10217 case AArch64::SQSHLR_ZPmZ_D:
10218 case AArch64::SQSHLR_ZPmZ_H:
10219 case AArch64::SQSHLR_ZPmZ_S:
10220 case AArch64::SQSHL_ZPmZ_B:
10221 case AArch64::SQSHL_ZPmZ_D:
10222 case AArch64::SQSHL_ZPmZ_H:
10223 case AArch64::SQSHL_ZPmZ_S:
10224 case AArch64::SQSUBR_ZPmZ_B:
10225 case AArch64::SQSUBR_ZPmZ_D:
10226 case AArch64::SQSUBR_ZPmZ_H:
10227 case AArch64::SQSUBR_ZPmZ_S:
10228 case AArch64::SQSUB_ZPmZ_B:
10229 case AArch64::SQSUB_ZPmZ_D:
10230 case AArch64::SQSUB_ZPmZ_H:
10231 case AArch64::SQSUB_ZPmZ_S:
10232 case AArch64::SRHADD_ZPmZ_B:
10233 case AArch64::SRHADD_ZPmZ_D:
10234 case AArch64::SRHADD_ZPmZ_H:
10235 case AArch64::SRHADD_ZPmZ_S:
10236 case AArch64::SRSHLR_ZPmZ_B:
10237 case AArch64::SRSHLR_ZPmZ_D:
10238 case AArch64::SRSHLR_ZPmZ_H:
10239 case AArch64::SRSHLR_ZPmZ_S:
10240 case AArch64::SRSHL_ZPmZ_B:
10241 case AArch64::SRSHL_ZPmZ_D:
10242 case AArch64::SRSHL_ZPmZ_H:
10243 case AArch64::SRSHL_ZPmZ_S:
10244 case AArch64::SUQADD_ZPmZ_B:
10245 case AArch64::SUQADD_ZPmZ_D:
10246 case AArch64::SUQADD_ZPmZ_H:
10247 case AArch64::SUQADD_ZPmZ_S:
10248 case AArch64::UHADD_ZPmZ_B:
10249 case AArch64::UHADD_ZPmZ_D:
10250 case AArch64::UHADD_ZPmZ_H:
10251 case AArch64::UHADD_ZPmZ_S:
10252 case AArch64::UHSUBR_ZPmZ_B:
10253 case AArch64::UHSUBR_ZPmZ_D:
10254 case AArch64::UHSUBR_ZPmZ_H:
10255 case AArch64::UHSUBR_ZPmZ_S:
10256 case AArch64::UHSUB_ZPmZ_B:
10257 case AArch64::UHSUB_ZPmZ_D:
10258 case AArch64::UHSUB_ZPmZ_H:
10259 case AArch64::UHSUB_ZPmZ_S:
10260 case AArch64::UMAXP_ZPmZ_B:
10261 case AArch64::UMAXP_ZPmZ_D:
10262 case AArch64::UMAXP_ZPmZ_H:
10263 case AArch64::UMAXP_ZPmZ_S:
10264 case AArch64::UMINP_ZPmZ_B:
10265 case AArch64::UMINP_ZPmZ_D:
10266 case AArch64::UMINP_ZPmZ_H:
10267 case AArch64::UMINP_ZPmZ_S:
10268 case AArch64::UQADD_ZPmZ_B:
10269 case AArch64::UQADD_ZPmZ_D:
10270 case AArch64::UQADD_ZPmZ_H:
10271 case AArch64::UQADD_ZPmZ_S:
10272 case AArch64::UQRSHLR_ZPmZ_B:
10273 case AArch64::UQRSHLR_ZPmZ_D:
10274 case AArch64::UQRSHLR_ZPmZ_H:
10275 case AArch64::UQRSHLR_ZPmZ_S:
10276 case AArch64::UQRSHL_ZPmZ_B:
10277 case AArch64::UQRSHL_ZPmZ_D:
10278 case AArch64::UQRSHL_ZPmZ_H:
10279 case AArch64::UQRSHL_ZPmZ_S:
10280 case AArch64::UQSHLR_ZPmZ_B:
10281 case AArch64::UQSHLR_ZPmZ_D:
10282 case AArch64::UQSHLR_ZPmZ_H:
10283 case AArch64::UQSHLR_ZPmZ_S:
10284 case AArch64::UQSHL_ZPmZ_B:
10285 case AArch64::UQSHL_ZPmZ_D:
10286 case AArch64::UQSHL_ZPmZ_H:
10287 case AArch64::UQSHL_ZPmZ_S:
10288 case AArch64::UQSUBR_ZPmZ_B:
10289 case AArch64::UQSUBR_ZPmZ_D:
10290 case AArch64::UQSUBR_ZPmZ_H:
10291 case AArch64::UQSUBR_ZPmZ_S:
10292 case AArch64::UQSUB_ZPmZ_B:
10293 case AArch64::UQSUB_ZPmZ_D:
10294 case AArch64::UQSUB_ZPmZ_H:
10295 case AArch64::UQSUB_ZPmZ_S:
10296 case AArch64::URHADD_ZPmZ_B:
10297 case AArch64::URHADD_ZPmZ_D:
10298 case AArch64::URHADD_ZPmZ_H:
10299 case AArch64::URHADD_ZPmZ_S:
10300 case AArch64::URSHLR_ZPmZ_B:
10301 case AArch64::URSHLR_ZPmZ_D:
10302 case AArch64::URSHLR_ZPmZ_H:
10303 case AArch64::URSHLR_ZPmZ_S:
10304 case AArch64::URSHL_ZPmZ_B:
10305 case AArch64::URSHL_ZPmZ_D:
10306 case AArch64::URSHL_ZPmZ_H:
10307 case AArch64::URSHL_ZPmZ_S:
10308 case AArch64::USQADD_ZPmZ_B:
10309 case AArch64::USQADD_ZPmZ_D:
10310 case AArch64::USQADD_ZPmZ_H:
10311 case AArch64::USQADD_ZPmZ_S: {
10312 // op: Pg
10313 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10314 op &= UINT64_C(7);
10315 op <<= 10;
10316 Value |= op;
10317 // op: Zm
10318 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10319 op &= UINT64_C(31);
10320 op <<= 5;
10321 Value |= op;
10322 // op: Zdn
10323 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10324 op &= UINT64_C(31);
10325 Value |= op;
10326 break;
10327 }
10328 case AArch64::SPLICE_ZPZZ_B:
10329 case AArch64::SPLICE_ZPZZ_D:
10330 case AArch64::SPLICE_ZPZZ_H:
10331 case AArch64::SPLICE_ZPZZ_S: {
10332 // op: Pg
10333 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10334 op &= UINT64_C(7);
10335 op <<= 10;
10336 Value |= op;
10337 // op: Zn
10338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10339 op &= UINT64_C(31);
10340 op <<= 5;
10341 Value |= op;
10342 // op: Zd
10343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10344 op &= UINT64_C(31);
10345 Value |= op;
10346 break;
10347 }
10348 case AArch64::GLD1B_D_IMM:
10349 case AArch64::GLD1B_S_IMM:
10350 case AArch64::GLD1D_IMM:
10351 case AArch64::GLD1H_D_IMM:
10352 case AArch64::GLD1H_S_IMM:
10353 case AArch64::GLD1SB_D_IMM:
10354 case AArch64::GLD1SB_S_IMM:
10355 case AArch64::GLD1SH_D_IMM:
10356 case AArch64::GLD1SH_S_IMM:
10357 case AArch64::GLD1SW_D_IMM:
10358 case AArch64::GLD1W_D_IMM:
10359 case AArch64::GLD1W_IMM:
10360 case AArch64::GLDFF1B_D_IMM:
10361 case AArch64::GLDFF1B_S_IMM:
10362 case AArch64::GLDFF1D_IMM:
10363 case AArch64::GLDFF1H_D_IMM:
10364 case AArch64::GLDFF1H_S_IMM:
10365 case AArch64::GLDFF1SB_D_IMM:
10366 case AArch64::GLDFF1SB_S_IMM:
10367 case AArch64::GLDFF1SH_D_IMM:
10368 case AArch64::GLDFF1SH_S_IMM:
10369 case AArch64::GLDFF1SW_D_IMM:
10370 case AArch64::GLDFF1W_D_IMM:
10371 case AArch64::GLDFF1W_IMM: {
10372 // op: Pg
10373 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10374 op &= UINT64_C(7);
10375 op <<= 10;
10376 Value |= op;
10377 // op: Zn
10378 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10379 op &= UINT64_C(31);
10380 op <<= 5;
10381 Value |= op;
10382 // op: Zt
10383 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10384 op &= UINT64_C(31);
10385 Value |= op;
10386 // op: imm5
10387 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10388 op &= UINT64_C(31);
10389 op <<= 16;
10390 Value |= op;
10391 break;
10392 }
10393 case AArch64::PRFB_D_PZI:
10394 case AArch64::PRFB_S_PZI:
10395 case AArch64::PRFD_D_PZI:
10396 case AArch64::PRFD_S_PZI:
10397 case AArch64::PRFH_D_PZI:
10398 case AArch64::PRFH_S_PZI:
10399 case AArch64::PRFW_D_PZI:
10400 case AArch64::PRFW_S_PZI: {
10401 // op: Pg
10402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10403 op &= UINT64_C(7);
10404 op <<= 10;
10405 Value |= op;
10406 // op: Zn
10407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10408 op &= UINT64_C(31);
10409 op <<= 5;
10410 Value |= op;
10411 // op: imm5
10412 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10413 op &= UINT64_C(31);
10414 op <<= 16;
10415 Value |= op;
10416 // op: prfop
10417 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10418 op &= UINT64_C(15);
10419 Value |= op;
10420 break;
10421 }
10422 case AArch64::SADALP_ZPmZ_D:
10423 case AArch64::SADALP_ZPmZ_H:
10424 case AArch64::SADALP_ZPmZ_S:
10425 case AArch64::UADALP_ZPmZ_D:
10426 case AArch64::UADALP_ZPmZ_H:
10427 case AArch64::UADALP_ZPmZ_S: {
10428 // op: Pg
10429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10430 op &= UINT64_C(7);
10431 op <<= 10;
10432 Value |= op;
10433 // op: Zn
10434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10435 op &= UINT64_C(31);
10436 op <<= 5;
10437 Value |= op;
10438 // op: Zda
10439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10440 op &= UINT64_C(31);
10441 Value |= op;
10442 break;
10443 }
10444 case AArch64::SST1B_D_IMM:
10445 case AArch64::SST1B_S_IMM:
10446 case AArch64::SST1D_IMM:
10447 case AArch64::SST1H_D_IMM:
10448 case AArch64::SST1H_S_IMM:
10449 case AArch64::SST1W_D_IMM:
10450 case AArch64::SST1W_IMM: {
10451 // op: Pg
10452 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10453 op &= UINT64_C(7);
10454 op <<= 10;
10455 Value |= op;
10456 // op: imm5
10457 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10458 op &= UINT64_C(31);
10459 op <<= 16;
10460 Value |= op;
10461 // op: Zn
10462 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10463 op &= UINT64_C(31);
10464 op <<= 5;
10465 Value |= op;
10466 // op: Zt
10467 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10468 op &= UINT64_C(31);
10469 Value |= op;
10470 break;
10471 }
10472 case AArch64::FCPY_ZPmI_D:
10473 case AArch64::FCPY_ZPmI_H:
10474 case AArch64::FCPY_ZPmI_S: {
10475 // op: Pg
10476 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10477 op &= UINT64_C(15);
10478 op <<= 16;
10479 Value |= op;
10480 // op: Zd
10481 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10482 op &= UINT64_C(31);
10483 Value |= op;
10484 // op: imm8
10485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10486 op &= UINT64_C(255);
10487 op <<= 5;
10488 Value |= op;
10489 break;
10490 }
10491 case AArch64::CPY_ZPmR_B:
10492 case AArch64::CPY_ZPmR_D:
10493 case AArch64::CPY_ZPmR_H:
10494 case AArch64::CPY_ZPmR_S: {
10495 // op: Pg
10496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10497 op &= UINT64_C(7);
10498 op <<= 10;
10499 Value |= op;
10500 // op: Rn
10501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10502 op &= UINT64_C(31);
10503 op <<= 5;
10504 Value |= op;
10505 // op: Zd
10506 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10507 op &= UINT64_C(31);
10508 Value |= op;
10509 break;
10510 }
10511 case AArch64::CPY_ZPmV_B:
10512 case AArch64::CPY_ZPmV_D:
10513 case AArch64::CPY_ZPmV_H:
10514 case AArch64::CPY_ZPmV_S: {
10515 // op: Pg
10516 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10517 op &= UINT64_C(7);
10518 op <<= 10;
10519 Value |= op;
10520 // op: Vn
10521 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10522 op &= UINT64_C(31);
10523 op <<= 5;
10524 Value |= op;
10525 // op: Zd
10526 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10527 op &= UINT64_C(31);
10528 Value |= op;
10529 break;
10530 }
10531 case AArch64::ABS_ZPmZ_B:
10532 case AArch64::ABS_ZPmZ_D:
10533 case AArch64::ABS_ZPmZ_H:
10534 case AArch64::ABS_ZPmZ_S:
10535 case AArch64::CLS_ZPmZ_B:
10536 case AArch64::CLS_ZPmZ_D:
10537 case AArch64::CLS_ZPmZ_H:
10538 case AArch64::CLS_ZPmZ_S:
10539 case AArch64::CLZ_ZPmZ_B:
10540 case AArch64::CLZ_ZPmZ_D:
10541 case AArch64::CLZ_ZPmZ_H:
10542 case AArch64::CLZ_ZPmZ_S:
10543 case AArch64::CNOT_ZPmZ_B:
10544 case AArch64::CNOT_ZPmZ_D:
10545 case AArch64::CNOT_ZPmZ_H:
10546 case AArch64::CNOT_ZPmZ_S:
10547 case AArch64::CNT_ZPmZ_B:
10548 case AArch64::CNT_ZPmZ_D:
10549 case AArch64::CNT_ZPmZ_H:
10550 case AArch64::CNT_ZPmZ_S:
10551 case AArch64::FABS_ZPmZ_D:
10552 case AArch64::FABS_ZPmZ_H:
10553 case AArch64::FABS_ZPmZ_S:
10554 case AArch64::FCVTX_ZPmZ_DtoS:
10555 case AArch64::FCVTZS_ZPmZ_DtoD:
10556 case AArch64::FCVTZS_ZPmZ_DtoS:
10557 case AArch64::FCVTZS_ZPmZ_HtoD:
10558 case AArch64::FCVTZS_ZPmZ_HtoH:
10559 case AArch64::FCVTZS_ZPmZ_HtoS:
10560 case AArch64::FCVTZS_ZPmZ_StoD:
10561 case AArch64::FCVTZS_ZPmZ_StoS:
10562 case AArch64::FCVTZU_ZPmZ_DtoD:
10563 case AArch64::FCVTZU_ZPmZ_DtoS:
10564 case AArch64::FCVTZU_ZPmZ_HtoD:
10565 case AArch64::FCVTZU_ZPmZ_HtoH:
10566 case AArch64::FCVTZU_ZPmZ_HtoS:
10567 case AArch64::FCVTZU_ZPmZ_StoD:
10568 case AArch64::FCVTZU_ZPmZ_StoS:
10569 case AArch64::FCVT_ZPmZ_DtoH:
10570 case AArch64::FCVT_ZPmZ_DtoS:
10571 case AArch64::FCVT_ZPmZ_HtoD:
10572 case AArch64::FCVT_ZPmZ_HtoS:
10573 case AArch64::FCVT_ZPmZ_StoD:
10574 case AArch64::FCVT_ZPmZ_StoH:
10575 case AArch64::FLOGB_ZPmZ_D:
10576 case AArch64::FLOGB_ZPmZ_H:
10577 case AArch64::FLOGB_ZPmZ_S:
10578 case AArch64::FNEG_ZPmZ_D:
10579 case AArch64::FNEG_ZPmZ_H:
10580 case AArch64::FNEG_ZPmZ_S:
10581 case AArch64::FRECPX_ZPmZ_D:
10582 case AArch64::FRECPX_ZPmZ_H:
10583 case AArch64::FRECPX_ZPmZ_S:
10584 case AArch64::FRINTA_ZPmZ_D:
10585 case AArch64::FRINTA_ZPmZ_H:
10586 case AArch64::FRINTA_ZPmZ_S:
10587 case AArch64::FRINTI_ZPmZ_D:
10588 case AArch64::FRINTI_ZPmZ_H:
10589 case AArch64::FRINTI_ZPmZ_S:
10590 case AArch64::FRINTM_ZPmZ_D:
10591 case AArch64::FRINTM_ZPmZ_H:
10592 case AArch64::FRINTM_ZPmZ_S:
10593 case AArch64::FRINTN_ZPmZ_D:
10594 case AArch64::FRINTN_ZPmZ_H:
10595 case AArch64::FRINTN_ZPmZ_S:
10596 case AArch64::FRINTP_ZPmZ_D:
10597 case AArch64::FRINTP_ZPmZ_H:
10598 case AArch64::FRINTP_ZPmZ_S:
10599 case AArch64::FRINTX_ZPmZ_D:
10600 case AArch64::FRINTX_ZPmZ_H:
10601 case AArch64::FRINTX_ZPmZ_S:
10602 case AArch64::FRINTZ_ZPmZ_D:
10603 case AArch64::FRINTZ_ZPmZ_H:
10604 case AArch64::FRINTZ_ZPmZ_S:
10605 case AArch64::FSQRT_ZPmZ_D:
10606 case AArch64::FSQRT_ZPmZ_H:
10607 case AArch64::FSQRT_ZPmZ_S:
10608 case AArch64::MOVPRFX_ZPmZ_B:
10609 case AArch64::MOVPRFX_ZPmZ_D:
10610 case AArch64::MOVPRFX_ZPmZ_H:
10611 case AArch64::MOVPRFX_ZPmZ_S:
10612 case AArch64::NEG_ZPmZ_B:
10613 case AArch64::NEG_ZPmZ_D:
10614 case AArch64::NEG_ZPmZ_H:
10615 case AArch64::NEG_ZPmZ_S:
10616 case AArch64::NOT_ZPmZ_B:
10617 case AArch64::NOT_ZPmZ_D:
10618 case AArch64::NOT_ZPmZ_H:
10619 case AArch64::NOT_ZPmZ_S:
10620 case AArch64::SCVTF_ZPmZ_DtoD:
10621 case AArch64::SCVTF_ZPmZ_DtoH:
10622 case AArch64::SCVTF_ZPmZ_DtoS:
10623 case AArch64::SCVTF_ZPmZ_HtoH:
10624 case AArch64::SCVTF_ZPmZ_StoD:
10625 case AArch64::SCVTF_ZPmZ_StoH:
10626 case AArch64::SCVTF_ZPmZ_StoS:
10627 case AArch64::SQABS_ZPmZ_B:
10628 case AArch64::SQABS_ZPmZ_D:
10629 case AArch64::SQABS_ZPmZ_H:
10630 case AArch64::SQABS_ZPmZ_S:
10631 case AArch64::SQNEG_ZPmZ_B:
10632 case AArch64::SQNEG_ZPmZ_D:
10633 case AArch64::SQNEG_ZPmZ_H:
10634 case AArch64::SQNEG_ZPmZ_S:
10635 case AArch64::SXTB_ZPmZ_D:
10636 case AArch64::SXTB_ZPmZ_H:
10637 case AArch64::SXTB_ZPmZ_S:
10638 case AArch64::SXTH_ZPmZ_D:
10639 case AArch64::SXTH_ZPmZ_S:
10640 case AArch64::SXTW_ZPmZ_D:
10641 case AArch64::UCVTF_ZPmZ_DtoD:
10642 case AArch64::UCVTF_ZPmZ_DtoH:
10643 case AArch64::UCVTF_ZPmZ_DtoS:
10644 case AArch64::UCVTF_ZPmZ_HtoH:
10645 case AArch64::UCVTF_ZPmZ_StoD:
10646 case AArch64::UCVTF_ZPmZ_StoH:
10647 case AArch64::UCVTF_ZPmZ_StoS:
10648 case AArch64::URECPE_ZPmZ_S:
10649 case AArch64::URSQRTE_ZPmZ_S:
10650 case AArch64::UXTB_ZPmZ_D:
10651 case AArch64::UXTB_ZPmZ_H:
10652 case AArch64::UXTB_ZPmZ_S:
10653 case AArch64::UXTH_ZPmZ_D:
10654 case AArch64::UXTH_ZPmZ_S:
10655 case AArch64::UXTW_ZPmZ_D: {
10656 // op: Pg
10657 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10658 op &= UINT64_C(7);
10659 op <<= 10;
10660 Value |= op;
10661 // op: Zd
10662 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10663 op &= UINT64_C(31);
10664 Value |= op;
10665 // op: Zn
10666 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10667 op &= UINT64_C(31);
10668 op <<= 5;
10669 Value |= op;
10670 break;
10671 }
10672 case AArch64::DECP_ZP_D:
10673 case AArch64::DECP_ZP_H:
10674 case AArch64::DECP_ZP_S:
10675 case AArch64::INCP_ZP_D:
10676 case AArch64::INCP_ZP_H:
10677 case AArch64::INCP_ZP_S:
10678 case AArch64::SQDECP_ZP_D:
10679 case AArch64::SQDECP_ZP_H:
10680 case AArch64::SQDECP_ZP_S:
10681 case AArch64::SQINCP_ZP_D:
10682 case AArch64::SQINCP_ZP_H:
10683 case AArch64::SQINCP_ZP_S:
10684 case AArch64::UQDECP_ZP_D:
10685 case AArch64::UQDECP_ZP_H:
10686 case AArch64::UQDECP_ZP_S:
10687 case AArch64::UQINCP_ZP_D:
10688 case AArch64::UQINCP_ZP_H:
10689 case AArch64::UQINCP_ZP_S: {
10690 // op: Pm
10691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10692 op &= UINT64_C(15);
10693 op <<= 5;
10694 Value |= op;
10695 // op: Zdn
10696 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10697 op &= UINT64_C(31);
10698 Value |= op;
10699 break;
10700 }
10701 case AArch64::ADDHA_MPPZ_S:
10702 case AArch64::ADDVA_MPPZ_S: {
10703 // op: Pm
10704 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10705 op &= UINT64_C(7);
10706 op <<= 13;
10707 Value |= op;
10708 // op: Pn
10709 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10710 op &= UINT64_C(7);
10711 op <<= 10;
10712 Value |= op;
10713 // op: Zn
10714 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
10715 op &= UINT64_C(31);
10716 op <<= 5;
10717 Value |= op;
10718 // op: ZAda
10719 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10720 op &= UINT64_C(3);
10721 Value |= op;
10722 break;
10723 }
10724 case AArch64::ADDHA_MPPZ_D:
10725 case AArch64::ADDVA_MPPZ_D: {
10726 // op: Pm
10727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
10728 op &= UINT64_C(7);
10729 op <<= 13;
10730 Value |= op;
10731 // op: Pn
10732 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10733 op &= UINT64_C(7);
10734 op <<= 10;
10735 Value |= op;
10736 // op: Zn
10737 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
10738 op &= UINT64_C(31);
10739 op <<= 5;
10740 Value |= op;
10741 // op: ZAda
10742 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10743 op &= UINT64_C(7);
10744 Value |= op;
10745 break;
10746 }
10747 case AArch64::WRFFR: {
10748 // op: Pn
10749 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10750 op &= UINT64_C(15);
10751 op <<= 5;
10752 Value |= op;
10753 break;
10754 }
10755 case AArch64::LDR_PXI:
10756 case AArch64::STR_PXI: {
10757 // op: Pt
10758 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10759 op &= UINT64_C(15);
10760 Value |= op;
10761 // op: Rn
10762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10763 op &= UINT64_C(31);
10764 op <<= 5;
10765 Value |= op;
10766 // op: imm9
10767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10768 Value |= (op & UINT64_C(504)) << 13;
10769 Value |= (op & UINT64_C(7)) << 10;
10770 break;
10771 }
10772 case AArch64::XPACD:
10773 case AArch64::XPACI: {
10774 // op: Rd
10775 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10776 op &= UINT64_C(31);
10777 Value |= op;
10778 break;
10779 }
10780 case AArch64::CNTP_XCI_B:
10781 case AArch64::CNTP_XCI_D:
10782 case AArch64::CNTP_XCI_H:
10783 case AArch64::CNTP_XCI_S: {
10784 // op: Rd
10785 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10786 op &= UINT64_C(31);
10787 Value |= op;
10788 // op: PNn
10789 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10790 op &= UINT64_C(15);
10791 op <<= 5;
10792 Value |= op;
10793 // op: vl
10794 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10795 op &= UINT64_C(1);
10796 op <<= 10;
10797 Value |= op;
10798 break;
10799 }
10800 case AArch64::ADDPL_XXI:
10801 case AArch64::ADDSPL_XXI:
10802 case AArch64::ADDSVL_XXI:
10803 case AArch64::ADDVL_XXI: {
10804 // op: Rd
10805 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
10806 op &= UINT64_C(31);
10807 Value |= op;
10808 // op: Rn
10809 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
10810 op &= UINT64_C(31);
10811 op <<= 16;
10812 Value |= op;
10813 // op: imm6
10814 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
10815 op &= UINT64_C(63);
10816 op <<= 5;
10817 Value |= op;
10818 break;
10819 }
10820 case AArch64::ABSWr:
10821 case AArch64::ABSXr:
10822 case AArch64::ABSv1i64:
10823 case AArch64::ABSv2i32:
10824 case AArch64::ABSv2i64:
10825 case AArch64::ABSv4i16:
10826 case AArch64::ABSv4i32:
10827 case AArch64::ABSv8i8:
10828 case AArch64::ABSv8i16:
10829 case AArch64::ABSv16i8:
10830 case AArch64::ADDPv2i64p:
10831 case AArch64::ADDVv4i16v:
10832 case AArch64::ADDVv4i32v:
10833 case AArch64::ADDVv8i8v:
10834 case AArch64::ADDVv8i16v:
10835 case AArch64::ADDVv16i8v:
10836 case AArch64::AESIMCrr:
10837 case AArch64::AESMCrr:
10838 case AArch64::BF1CVTL2v8f16:
10839 case AArch64::BF1CVTLv8f16:
10840 case AArch64::BF2CVTL2v8f16:
10841 case AArch64::BF2CVTLv8f16:
10842 case AArch64::BFCVT:
10843 case AArch64::BFCVTN:
10844 case AArch64::CLSWr:
10845 case AArch64::CLSXr:
10846 case AArch64::CLSv2i32:
10847 case AArch64::CLSv4i16:
10848 case AArch64::CLSv4i32:
10849 case AArch64::CLSv8i8:
10850 case AArch64::CLSv8i16:
10851 case AArch64::CLSv16i8:
10852 case AArch64::CLZWr:
10853 case AArch64::CLZXr:
10854 case AArch64::CLZv2i32:
10855 case AArch64::CLZv4i16:
10856 case AArch64::CLZv4i32:
10857 case AArch64::CLZv8i8:
10858 case AArch64::CLZv8i16:
10859 case AArch64::CLZv16i8:
10860 case AArch64::CMEQv1i64rz:
10861 case AArch64::CMEQv2i32rz:
10862 case AArch64::CMEQv2i64rz:
10863 case AArch64::CMEQv4i16rz:
10864 case AArch64::CMEQv4i32rz:
10865 case AArch64::CMEQv8i8rz:
10866 case AArch64::CMEQv8i16rz:
10867 case AArch64::CMEQv16i8rz:
10868 case AArch64::CMGEv1i64rz:
10869 case AArch64::CMGEv2i32rz:
10870 case AArch64::CMGEv2i64rz:
10871 case AArch64::CMGEv4i16rz:
10872 case AArch64::CMGEv4i32rz:
10873 case AArch64::CMGEv8i8rz:
10874 case AArch64::CMGEv8i16rz:
10875 case AArch64::CMGEv16i8rz:
10876 case AArch64::CMGTv1i64rz:
10877 case AArch64::CMGTv2i32rz:
10878 case AArch64::CMGTv2i64rz:
10879 case AArch64::CMGTv4i16rz:
10880 case AArch64::CMGTv4i32rz:
10881 case AArch64::CMGTv8i8rz:
10882 case AArch64::CMGTv8i16rz:
10883 case AArch64::CMGTv16i8rz:
10884 case AArch64::CMLEv1i64rz:
10885 case AArch64::CMLEv2i32rz:
10886 case AArch64::CMLEv2i64rz:
10887 case AArch64::CMLEv4i16rz:
10888 case AArch64::CMLEv4i32rz:
10889 case AArch64::CMLEv8i8rz:
10890 case AArch64::CMLEv8i16rz:
10891 case AArch64::CMLEv16i8rz:
10892 case AArch64::CMLTv1i64rz:
10893 case AArch64::CMLTv2i32rz:
10894 case AArch64::CMLTv2i64rz:
10895 case AArch64::CMLTv4i16rz:
10896 case AArch64::CMLTv4i32rz:
10897 case AArch64::CMLTv8i8rz:
10898 case AArch64::CMLTv8i16rz:
10899 case AArch64::CMLTv16i8rz:
10900 case AArch64::CNTWr:
10901 case AArch64::CNTXr:
10902 case AArch64::CNTv8i8:
10903 case AArch64::CNTv16i8:
10904 case AArch64::CTZWr:
10905 case AArch64::CTZXr:
10906 case AArch64::DUPv2i32gpr:
10907 case AArch64::DUPv2i64gpr:
10908 case AArch64::DUPv4i16gpr:
10909 case AArch64::DUPv4i32gpr:
10910 case AArch64::DUPv8i8gpr:
10911 case AArch64::DUPv8i16gpr:
10912 case AArch64::DUPv16i8gpr:
10913 case AArch64::F1CVTL2v8f16:
10914 case AArch64::F1CVTLv8f16:
10915 case AArch64::F2CVTL2v8f16:
10916 case AArch64::F2CVTLv8f16:
10917 case AArch64::FABSDr:
10918 case AArch64::FABSHr:
10919 case AArch64::FABSSr:
10920 case AArch64::FABSv2f32:
10921 case AArch64::FABSv2f64:
10922 case AArch64::FABSv4f16:
10923 case AArch64::FABSv4f32:
10924 case AArch64::FABSv8f16:
10925 case AArch64::FADDPv2i16p:
10926 case AArch64::FADDPv2i32p:
10927 case AArch64::FADDPv2i64p:
10928 case AArch64::FCMEQv1i16rz:
10929 case AArch64::FCMEQv1i32rz:
10930 case AArch64::FCMEQv1i64rz:
10931 case AArch64::FCMEQv2i32rz:
10932 case AArch64::FCMEQv2i64rz:
10933 case AArch64::FCMEQv4i16rz:
10934 case AArch64::FCMEQv4i32rz:
10935 case AArch64::FCMEQv8i16rz:
10936 case AArch64::FCMGEv1i16rz:
10937 case AArch64::FCMGEv1i32rz:
10938 case AArch64::FCMGEv1i64rz:
10939 case AArch64::FCMGEv2i32rz:
10940 case AArch64::FCMGEv2i64rz:
10941 case AArch64::FCMGEv4i16rz:
10942 case AArch64::FCMGEv4i32rz:
10943 case AArch64::FCMGEv8i16rz:
10944 case AArch64::FCMGTv1i16rz:
10945 case AArch64::FCMGTv1i32rz:
10946 case AArch64::FCMGTv1i64rz:
10947 case AArch64::FCMGTv2i32rz:
10948 case AArch64::FCMGTv2i64rz:
10949 case AArch64::FCMGTv4i16rz:
10950 case AArch64::FCMGTv4i32rz:
10951 case AArch64::FCMGTv8i16rz:
10952 case AArch64::FCMLEv1i16rz:
10953 case AArch64::FCMLEv1i32rz:
10954 case AArch64::FCMLEv1i64rz:
10955 case AArch64::FCMLEv2i32rz:
10956 case AArch64::FCMLEv2i64rz:
10957 case AArch64::FCMLEv4i16rz:
10958 case AArch64::FCMLEv4i32rz:
10959 case AArch64::FCMLEv8i16rz:
10960 case AArch64::FCMLTv1i16rz:
10961 case AArch64::FCMLTv1i32rz:
10962 case AArch64::FCMLTv1i64rz:
10963 case AArch64::FCMLTv2i32rz:
10964 case AArch64::FCMLTv2i64rz:
10965 case AArch64::FCMLTv4i16rz:
10966 case AArch64::FCMLTv4i32rz:
10967 case AArch64::FCMLTv8i16rz:
10968 case AArch64::FCVTASUWDr:
10969 case AArch64::FCVTASUWHr:
10970 case AArch64::FCVTASUWSr:
10971 case AArch64::FCVTASUXDr:
10972 case AArch64::FCVTASUXHr:
10973 case AArch64::FCVTASUXSr:
10974 case AArch64::FCVTASv1f16:
10975 case AArch64::FCVTASv1i32:
10976 case AArch64::FCVTASv1i64:
10977 case AArch64::FCVTASv2f32:
10978 case AArch64::FCVTASv2f64:
10979 case AArch64::FCVTASv4f16:
10980 case AArch64::FCVTASv4f32:
10981 case AArch64::FCVTASv8f16:
10982 case AArch64::FCVTAUUWDr:
10983 case AArch64::FCVTAUUWHr:
10984 case AArch64::FCVTAUUWSr:
10985 case AArch64::FCVTAUUXDr:
10986 case AArch64::FCVTAUUXHr:
10987 case AArch64::FCVTAUUXSr:
10988 case AArch64::FCVTAUv1f16:
10989 case AArch64::FCVTAUv1i32:
10990 case AArch64::FCVTAUv1i64:
10991 case AArch64::FCVTAUv2f32:
10992 case AArch64::FCVTAUv2f64:
10993 case AArch64::FCVTAUv4f16:
10994 case AArch64::FCVTAUv4f32:
10995 case AArch64::FCVTAUv8f16:
10996 case AArch64::FCVTDHr:
10997 case AArch64::FCVTDSr:
10998 case AArch64::FCVTHDr:
10999 case AArch64::FCVTHSr:
11000 case AArch64::FCVTLv2i32:
11001 case AArch64::FCVTLv4i16:
11002 case AArch64::FCVTLv4i32:
11003 case AArch64::FCVTLv8i16:
11004 case AArch64::FCVTMSUWDr:
11005 case AArch64::FCVTMSUWHr:
11006 case AArch64::FCVTMSUWSr:
11007 case AArch64::FCVTMSUXDr:
11008 case AArch64::FCVTMSUXHr:
11009 case AArch64::FCVTMSUXSr:
11010 case AArch64::FCVTMSv1f16:
11011 case AArch64::FCVTMSv1i32:
11012 case AArch64::FCVTMSv1i64:
11013 case AArch64::FCVTMSv2f32:
11014 case AArch64::FCVTMSv2f64:
11015 case AArch64::FCVTMSv4f16:
11016 case AArch64::FCVTMSv4f32:
11017 case AArch64::FCVTMSv8f16:
11018 case AArch64::FCVTMUUWDr:
11019 case AArch64::FCVTMUUWHr:
11020 case AArch64::FCVTMUUWSr:
11021 case AArch64::FCVTMUUXDr:
11022 case AArch64::FCVTMUUXHr:
11023 case AArch64::FCVTMUUXSr:
11024 case AArch64::FCVTMUv1f16:
11025 case AArch64::FCVTMUv1i32:
11026 case AArch64::FCVTMUv1i64:
11027 case AArch64::FCVTMUv2f32:
11028 case AArch64::FCVTMUv2f64:
11029 case AArch64::FCVTMUv4f16:
11030 case AArch64::FCVTMUv4f32:
11031 case AArch64::FCVTMUv8f16:
11032 case AArch64::FCVTNSUWDr:
11033 case AArch64::FCVTNSUWHr:
11034 case AArch64::FCVTNSUWSr:
11035 case AArch64::FCVTNSUXDr:
11036 case AArch64::FCVTNSUXHr:
11037 case AArch64::FCVTNSUXSr:
11038 case AArch64::FCVTNSv1f16:
11039 case AArch64::FCVTNSv1i32:
11040 case AArch64::FCVTNSv1i64:
11041 case AArch64::FCVTNSv2f32:
11042 case AArch64::FCVTNSv2f64:
11043 case AArch64::FCVTNSv4f16:
11044 case AArch64::FCVTNSv4f32:
11045 case AArch64::FCVTNSv8f16:
11046 case AArch64::FCVTNUUWDr:
11047 case AArch64::FCVTNUUWHr:
11048 case AArch64::FCVTNUUWSr:
11049 case AArch64::FCVTNUUXDr:
11050 case AArch64::FCVTNUUXHr:
11051 case AArch64::FCVTNUUXSr:
11052 case AArch64::FCVTNUv1f16:
11053 case AArch64::FCVTNUv1i32:
11054 case AArch64::FCVTNUv1i64:
11055 case AArch64::FCVTNUv2f32:
11056 case AArch64::FCVTNUv2f64:
11057 case AArch64::FCVTNUv4f16:
11058 case AArch64::FCVTNUv4f32:
11059 case AArch64::FCVTNUv8f16:
11060 case AArch64::FCVTNv2i32:
11061 case AArch64::FCVTNv4i16:
11062 case AArch64::FCVTPSUWDr:
11063 case AArch64::FCVTPSUWHr:
11064 case AArch64::FCVTPSUWSr:
11065 case AArch64::FCVTPSUXDr:
11066 case AArch64::FCVTPSUXHr:
11067 case AArch64::FCVTPSUXSr:
11068 case AArch64::FCVTPSv1f16:
11069 case AArch64::FCVTPSv1i32:
11070 case AArch64::FCVTPSv1i64:
11071 case AArch64::FCVTPSv2f32:
11072 case AArch64::FCVTPSv2f64:
11073 case AArch64::FCVTPSv4f16:
11074 case AArch64::FCVTPSv4f32:
11075 case AArch64::FCVTPSv8f16:
11076 case AArch64::FCVTPUUWDr:
11077 case AArch64::FCVTPUUWHr:
11078 case AArch64::FCVTPUUWSr:
11079 case AArch64::FCVTPUUXDr:
11080 case AArch64::FCVTPUUXHr:
11081 case AArch64::FCVTPUUXSr:
11082 case AArch64::FCVTPUv1f16:
11083 case AArch64::FCVTPUv1i32:
11084 case AArch64::FCVTPUv1i64:
11085 case AArch64::FCVTPUv2f32:
11086 case AArch64::FCVTPUv2f64:
11087 case AArch64::FCVTPUv4f16:
11088 case AArch64::FCVTPUv4f32:
11089 case AArch64::FCVTPUv8f16:
11090 case AArch64::FCVTSDr:
11091 case AArch64::FCVTSHr:
11092 case AArch64::FCVTXNv1i64:
11093 case AArch64::FCVTXNv2f32:
11094 case AArch64::FCVTZSUWDr:
11095 case AArch64::FCVTZSUWHr:
11096 case AArch64::FCVTZSUWSr:
11097 case AArch64::FCVTZSUXDr:
11098 case AArch64::FCVTZSUXHr:
11099 case AArch64::FCVTZSUXSr:
11100 case AArch64::FCVTZSv1f16:
11101 case AArch64::FCVTZSv1i32:
11102 case AArch64::FCVTZSv1i64:
11103 case AArch64::FCVTZSv2f32:
11104 case AArch64::FCVTZSv2f64:
11105 case AArch64::FCVTZSv4f16:
11106 case AArch64::FCVTZSv4f32:
11107 case AArch64::FCVTZSv8f16:
11108 case AArch64::FCVTZUUWDr:
11109 case AArch64::FCVTZUUWHr:
11110 case AArch64::FCVTZUUWSr:
11111 case AArch64::FCVTZUUXDr:
11112 case AArch64::FCVTZUUXHr:
11113 case AArch64::FCVTZUUXSr:
11114 case AArch64::FCVTZUv1f16:
11115 case AArch64::FCVTZUv1i32:
11116 case AArch64::FCVTZUv1i64:
11117 case AArch64::FCVTZUv2f32:
11118 case AArch64::FCVTZUv2f64:
11119 case AArch64::FCVTZUv4f16:
11120 case AArch64::FCVTZUv4f32:
11121 case AArch64::FCVTZUv8f16:
11122 case AArch64::FJCVTZS:
11123 case AArch64::FMAXNMPv2i16p:
11124 case AArch64::FMAXNMPv2i32p:
11125 case AArch64::FMAXNMPv2i64p:
11126 case AArch64::FMAXNMVv4i16v:
11127 case AArch64::FMAXNMVv4i32v:
11128 case AArch64::FMAXNMVv8i16v:
11129 case AArch64::FMAXPv2i16p:
11130 case AArch64::FMAXPv2i32p:
11131 case AArch64::FMAXPv2i64p:
11132 case AArch64::FMAXVv4i16v:
11133 case AArch64::FMAXVv4i32v:
11134 case AArch64::FMAXVv8i16v:
11135 case AArch64::FMINNMPv2i16p:
11136 case AArch64::FMINNMPv2i32p:
11137 case AArch64::FMINNMPv2i64p:
11138 case AArch64::FMINNMVv4i16v:
11139 case AArch64::FMINNMVv4i32v:
11140 case AArch64::FMINNMVv8i16v:
11141 case AArch64::FMINPv2i16p:
11142 case AArch64::FMINPv2i32p:
11143 case AArch64::FMINPv2i64p:
11144 case AArch64::FMINVv4i16v:
11145 case AArch64::FMINVv4i32v:
11146 case AArch64::FMINVv8i16v:
11147 case AArch64::FMOVDXHighr:
11148 case AArch64::FMOVDXr:
11149 case AArch64::FMOVDr:
11150 case AArch64::FMOVHWr:
11151 case AArch64::FMOVHXr:
11152 case AArch64::FMOVHr:
11153 case AArch64::FMOVSWr:
11154 case AArch64::FMOVSr:
11155 case AArch64::FMOVWHr:
11156 case AArch64::FMOVWSr:
11157 case AArch64::FMOVXDHighr:
11158 case AArch64::FMOVXDr:
11159 case AArch64::FMOVXHr:
11160 case AArch64::FNEGDr:
11161 case AArch64::FNEGHr:
11162 case AArch64::FNEGSr:
11163 case AArch64::FNEGv2f32:
11164 case AArch64::FNEGv2f64:
11165 case AArch64::FNEGv4f16:
11166 case AArch64::FNEGv4f32:
11167 case AArch64::FNEGv8f16:
11168 case AArch64::FRECPEv1f16:
11169 case AArch64::FRECPEv1i32:
11170 case AArch64::FRECPEv1i64:
11171 case AArch64::FRECPEv2f32:
11172 case AArch64::FRECPEv2f64:
11173 case AArch64::FRECPEv4f16:
11174 case AArch64::FRECPEv4f32:
11175 case AArch64::FRECPEv8f16:
11176 case AArch64::FRECPXv1f16:
11177 case AArch64::FRECPXv1i32:
11178 case AArch64::FRECPXv1i64:
11179 case AArch64::FRINT32XDr:
11180 case AArch64::FRINT32XSr:
11181 case AArch64::FRINT32Xv2f32:
11182 case AArch64::FRINT32Xv2f64:
11183 case AArch64::FRINT32Xv4f32:
11184 case AArch64::FRINT32ZDr:
11185 case AArch64::FRINT32ZSr:
11186 case AArch64::FRINT32Zv2f32:
11187 case AArch64::FRINT32Zv2f64:
11188 case AArch64::FRINT32Zv4f32:
11189 case AArch64::FRINT64XDr:
11190 case AArch64::FRINT64XSr:
11191 case AArch64::FRINT64Xv2f32:
11192 case AArch64::FRINT64Xv2f64:
11193 case AArch64::FRINT64Xv4f32:
11194 case AArch64::FRINT64ZDr:
11195 case AArch64::FRINT64ZSr:
11196 case AArch64::FRINT64Zv2f32:
11197 case AArch64::FRINT64Zv2f64:
11198 case AArch64::FRINT64Zv4f32:
11199 case AArch64::FRINTADr:
11200 case AArch64::FRINTAHr:
11201 case AArch64::FRINTASr:
11202 case AArch64::FRINTAv2f32:
11203 case AArch64::FRINTAv2f64:
11204 case AArch64::FRINTAv4f16:
11205 case AArch64::FRINTAv4f32:
11206 case AArch64::FRINTAv8f16:
11207 case AArch64::FRINTIDr:
11208 case AArch64::FRINTIHr:
11209 case AArch64::FRINTISr:
11210 case AArch64::FRINTIv2f32:
11211 case AArch64::FRINTIv2f64:
11212 case AArch64::FRINTIv4f16:
11213 case AArch64::FRINTIv4f32:
11214 case AArch64::FRINTIv8f16:
11215 case AArch64::FRINTMDr:
11216 case AArch64::FRINTMHr:
11217 case AArch64::FRINTMSr:
11218 case AArch64::FRINTMv2f32:
11219 case AArch64::FRINTMv2f64:
11220 case AArch64::FRINTMv4f16:
11221 case AArch64::FRINTMv4f32:
11222 case AArch64::FRINTMv8f16:
11223 case AArch64::FRINTNDr:
11224 case AArch64::FRINTNHr:
11225 case AArch64::FRINTNSr:
11226 case AArch64::FRINTNv2f32:
11227 case AArch64::FRINTNv2f64:
11228 case AArch64::FRINTNv4f16:
11229 case AArch64::FRINTNv4f32:
11230 case AArch64::FRINTNv8f16:
11231 case AArch64::FRINTPDr:
11232 case AArch64::FRINTPHr:
11233 case AArch64::FRINTPSr:
11234 case AArch64::FRINTPv2f32:
11235 case AArch64::FRINTPv2f64:
11236 case AArch64::FRINTPv4f16:
11237 case AArch64::FRINTPv4f32:
11238 case AArch64::FRINTPv8f16:
11239 case AArch64::FRINTXDr:
11240 case AArch64::FRINTXHr:
11241 case AArch64::FRINTXSr:
11242 case AArch64::FRINTXv2f32:
11243 case AArch64::FRINTXv2f64:
11244 case AArch64::FRINTXv4f16:
11245 case AArch64::FRINTXv4f32:
11246 case AArch64::FRINTXv8f16:
11247 case AArch64::FRINTZDr:
11248 case AArch64::FRINTZHr:
11249 case AArch64::FRINTZSr:
11250 case AArch64::FRINTZv2f32:
11251 case AArch64::FRINTZv2f64:
11252 case AArch64::FRINTZv4f16:
11253 case AArch64::FRINTZv4f32:
11254 case AArch64::FRINTZv8f16:
11255 case AArch64::FRSQRTEv1f16:
11256 case AArch64::FRSQRTEv1i32:
11257 case AArch64::FRSQRTEv1i64:
11258 case AArch64::FRSQRTEv2f32:
11259 case AArch64::FRSQRTEv2f64:
11260 case AArch64::FRSQRTEv4f16:
11261 case AArch64::FRSQRTEv4f32:
11262 case AArch64::FRSQRTEv8f16:
11263 case AArch64::FSQRTDr:
11264 case AArch64::FSQRTHr:
11265 case AArch64::FSQRTSr:
11266 case AArch64::FSQRTv2f32:
11267 case AArch64::FSQRTv2f64:
11268 case AArch64::FSQRTv4f16:
11269 case AArch64::FSQRTv4f32:
11270 case AArch64::FSQRTv8f16:
11271 case AArch64::NEGv1i64:
11272 case AArch64::NEGv2i32:
11273 case AArch64::NEGv2i64:
11274 case AArch64::NEGv4i16:
11275 case AArch64::NEGv4i32:
11276 case AArch64::NEGv8i8:
11277 case AArch64::NEGv8i16:
11278 case AArch64::NEGv16i8:
11279 case AArch64::NOTv8i8:
11280 case AArch64::NOTv16i8:
11281 case AArch64::RBITWr:
11282 case AArch64::RBITXr:
11283 case AArch64::RBITv8i8:
11284 case AArch64::RBITv16i8:
11285 case AArch64::REV16Wr:
11286 case AArch64::REV16Xr:
11287 case AArch64::REV16v8i8:
11288 case AArch64::REV16v16i8:
11289 case AArch64::REV32Xr:
11290 case AArch64::REV32v4i16:
11291 case AArch64::REV32v8i8:
11292 case AArch64::REV32v8i16:
11293 case AArch64::REV32v16i8:
11294 case AArch64::REV64v2i32:
11295 case AArch64::REV64v4i16:
11296 case AArch64::REV64v4i32:
11297 case AArch64::REV64v8i8:
11298 case AArch64::REV64v8i16:
11299 case AArch64::REV64v16i8:
11300 case AArch64::REVWr:
11301 case AArch64::REVXr:
11302 case AArch64::SADDLPv2i32_v1i64:
11303 case AArch64::SADDLPv4i16_v2i32:
11304 case AArch64::SADDLPv4i32_v2i64:
11305 case AArch64::SADDLPv8i8_v4i16:
11306 case AArch64::SADDLPv8i16_v4i32:
11307 case AArch64::SADDLPv16i8_v8i16:
11308 case AArch64::SADDLVv4i16v:
11309 case AArch64::SADDLVv4i32v:
11310 case AArch64::SADDLVv8i8v:
11311 case AArch64::SADDLVv8i16v:
11312 case AArch64::SADDLVv16i8v:
11313 case AArch64::SCVTFUWDri:
11314 case AArch64::SCVTFUWHri:
11315 case AArch64::SCVTFUWSri:
11316 case AArch64::SCVTFUXDri:
11317 case AArch64::SCVTFUXHri:
11318 case AArch64::SCVTFUXSri:
11319 case AArch64::SCVTFv1i16:
11320 case AArch64::SCVTFv1i32:
11321 case AArch64::SCVTFv1i64:
11322 case AArch64::SCVTFv2f32:
11323 case AArch64::SCVTFv2f64:
11324 case AArch64::SCVTFv4f16:
11325 case AArch64::SCVTFv4f32:
11326 case AArch64::SCVTFv8f16:
11327 case AArch64::SHA1Hrr:
11328 case AArch64::SHLLv2i32:
11329 case AArch64::SHLLv4i16:
11330 case AArch64::SHLLv4i32:
11331 case AArch64::SHLLv8i8:
11332 case AArch64::SHLLv8i16:
11333 case AArch64::SHLLv16i8:
11334 case AArch64::SMAXVv4i16v:
11335 case AArch64::SMAXVv4i32v:
11336 case AArch64::SMAXVv8i8v:
11337 case AArch64::SMAXVv8i16v:
11338 case AArch64::SMAXVv16i8v:
11339 case AArch64::SMINVv4i16v:
11340 case AArch64::SMINVv4i32v:
11341 case AArch64::SMINVv8i8v:
11342 case AArch64::SMINVv8i16v:
11343 case AArch64::SMINVv16i8v:
11344 case AArch64::SMOVvi8to32_idx0:
11345 case AArch64::SMOVvi8to64_idx0:
11346 case AArch64::SMOVvi16to32_idx0:
11347 case AArch64::SMOVvi16to64_idx0:
11348 case AArch64::SMOVvi32to64_idx0:
11349 case AArch64::SQABSv1i8:
11350 case AArch64::SQABSv1i16:
11351 case AArch64::SQABSv1i32:
11352 case AArch64::SQABSv1i64:
11353 case AArch64::SQABSv2i32:
11354 case AArch64::SQABSv2i64:
11355 case AArch64::SQABSv4i16:
11356 case AArch64::SQABSv4i32:
11357 case AArch64::SQABSv8i8:
11358 case AArch64::SQABSv8i16:
11359 case AArch64::SQABSv16i8:
11360 case AArch64::SQNEGv1i8:
11361 case AArch64::SQNEGv1i16:
11362 case AArch64::SQNEGv1i32:
11363 case AArch64::SQNEGv1i64:
11364 case AArch64::SQNEGv2i32:
11365 case AArch64::SQNEGv2i64:
11366 case AArch64::SQNEGv4i16:
11367 case AArch64::SQNEGv4i32:
11368 case AArch64::SQNEGv8i8:
11369 case AArch64::SQNEGv8i16:
11370 case AArch64::SQNEGv16i8:
11371 case AArch64::SQXTNv1i8:
11372 case AArch64::SQXTNv1i16:
11373 case AArch64::SQXTNv1i32:
11374 case AArch64::SQXTNv2i32:
11375 case AArch64::SQXTNv4i16:
11376 case AArch64::SQXTNv8i8:
11377 case AArch64::SQXTUNv1i8:
11378 case AArch64::SQXTUNv1i16:
11379 case AArch64::SQXTUNv1i32:
11380 case AArch64::SQXTUNv2i32:
11381 case AArch64::SQXTUNv4i16:
11382 case AArch64::SQXTUNv8i8:
11383 case AArch64::UADDLPv2i32_v1i64:
11384 case AArch64::UADDLPv4i16_v2i32:
11385 case AArch64::UADDLPv4i32_v2i64:
11386 case AArch64::UADDLPv8i8_v4i16:
11387 case AArch64::UADDLPv8i16_v4i32:
11388 case AArch64::UADDLPv16i8_v8i16:
11389 case AArch64::UADDLVv4i16v:
11390 case AArch64::UADDLVv4i32v:
11391 case AArch64::UADDLVv8i8v:
11392 case AArch64::UADDLVv8i16v:
11393 case AArch64::UADDLVv16i8v:
11394 case AArch64::UCVTFUWDri:
11395 case AArch64::UCVTFUWHri:
11396 case AArch64::UCVTFUWSri:
11397 case AArch64::UCVTFUXDri:
11398 case AArch64::UCVTFUXHri:
11399 case AArch64::UCVTFUXSri:
11400 case AArch64::UCVTFv1i16:
11401 case AArch64::UCVTFv1i32:
11402 case AArch64::UCVTFv1i64:
11403 case AArch64::UCVTFv2f32:
11404 case AArch64::UCVTFv2f64:
11405 case AArch64::UCVTFv4f16:
11406 case AArch64::UCVTFv4f32:
11407 case AArch64::UCVTFv8f16:
11408 case AArch64::UMAXVv4i16v:
11409 case AArch64::UMAXVv4i32v:
11410 case AArch64::UMAXVv8i8v:
11411 case AArch64::UMAXVv8i16v:
11412 case AArch64::UMAXVv16i8v:
11413 case AArch64::UMINVv4i16v:
11414 case AArch64::UMINVv4i32v:
11415 case AArch64::UMINVv8i8v:
11416 case AArch64::UMINVv8i16v:
11417 case AArch64::UMINVv16i8v:
11418 case AArch64::UMOVvi8_idx0:
11419 case AArch64::UMOVvi16_idx0:
11420 case AArch64::UMOVvi32_idx0:
11421 case AArch64::UMOVvi64_idx0:
11422 case AArch64::UQXTNv1i8:
11423 case AArch64::UQXTNv1i16:
11424 case AArch64::UQXTNv1i32:
11425 case AArch64::UQXTNv2i32:
11426 case AArch64::UQXTNv4i16:
11427 case AArch64::UQXTNv8i8:
11428 case AArch64::URECPEv2i32:
11429 case AArch64::URECPEv4i32:
11430 case AArch64::URSQRTEv2i32:
11431 case AArch64::URSQRTEv4i32:
11432 case AArch64::XTNv2i32:
11433 case AArch64::XTNv4i16:
11434 case AArch64::XTNv8i8: {
11435 // op: Rd
11436 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11437 op &= UINT64_C(31);
11438 Value |= op;
11439 // op: Rn
11440 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11441 op &= UINT64_C(31);
11442 op <<= 5;
11443 Value |= op;
11444 break;
11445 }
11446 case AArch64::FMULXv1i16_indexed:
11447 case AArch64::FMULXv4i16_indexed:
11448 case AArch64::FMULXv8i16_indexed:
11449 case AArch64::FMULv1i16_indexed:
11450 case AArch64::FMULv4i16_indexed:
11451 case AArch64::FMULv8i16_indexed:
11452 case AArch64::MULv4i16_indexed:
11453 case AArch64::MULv8i16_indexed:
11454 case AArch64::SMULLv4i16_indexed:
11455 case AArch64::SMULLv8i16_indexed:
11456 case AArch64::SQDMULHv1i16_indexed:
11457 case AArch64::SQDMULHv4i16_indexed:
11458 case AArch64::SQDMULHv8i16_indexed:
11459 case AArch64::SQDMULLv1i32_indexed:
11460 case AArch64::SQDMULLv4i16_indexed:
11461 case AArch64::SQDMULLv8i16_indexed:
11462 case AArch64::SQRDMULHv1i16_indexed:
11463 case AArch64::SQRDMULHv4i16_indexed:
11464 case AArch64::SQRDMULHv8i16_indexed:
11465 case AArch64::UMULLv4i16_indexed:
11466 case AArch64::UMULLv8i16_indexed: {
11467 // op: Rd
11468 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
11469 op &= UINT64_C(31);
11470 Value |= op;
11471 // op: Rn
11472 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
11473 op &= UINT64_C(31);
11474 op <<= 5;
11475 Value |= op;
11476 // op: Rm
11477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
11478 op &= UINT64_C(15);
11479 op <<= 16;
11480 Value |= op;
11481 // op: idx
11482 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
11483 Value |= (op & UINT64_C(3)) << 20;
11484 Value |= (op & UINT64_C(4)) << 9;
11485 break;
11486 }
11487 case AArch64::ADCSWr:
11488 case AArch64::ADCSXr:
11489 case AArch64::ADCWr:
11490 case AArch64::ADCXr:
11491 case AArch64::ADDHNv2i64_v2i32:
11492 case AArch64::ADDHNv4i32_v4i16:
11493 case AArch64::ADDHNv8i16_v8i8:
11494 case AArch64::ADDPv2i32:
11495 case AArch64::ADDPv2i64:
11496 case AArch64::ADDPv4i16:
11497 case AArch64::ADDPv4i32:
11498 case AArch64::ADDPv8i8:
11499 case AArch64::ADDPv8i16:
11500 case AArch64::ADDPv16i8:
11501 case AArch64::ADDv1i64:
11502 case AArch64::ADDv2i32:
11503 case AArch64::ADDv2i64:
11504 case AArch64::ADDv4i16:
11505 case AArch64::ADDv4i32:
11506 case AArch64::ADDv8i8:
11507 case AArch64::ADDv8i16:
11508 case AArch64::ADDv16i8:
11509 case AArch64::ANDv8i8:
11510 case AArch64::ANDv16i8:
11511 case AArch64::ASRVWr:
11512 case AArch64::ASRVXr:
11513 case AArch64::BICv8i8:
11514 case AArch64::BICv16i8:
11515 case AArch64::CMEQv1i64:
11516 case AArch64::CMEQv2i32:
11517 case AArch64::CMEQv2i64:
11518 case AArch64::CMEQv4i16:
11519 case AArch64::CMEQv4i32:
11520 case AArch64::CMEQv8i8:
11521 case AArch64::CMEQv8i16:
11522 case AArch64::CMEQv16i8:
11523 case AArch64::CMGEv1i64:
11524 case AArch64::CMGEv2i32:
11525 case AArch64::CMGEv2i64:
11526 case AArch64::CMGEv4i16:
11527 case AArch64::CMGEv4i32:
11528 case AArch64::CMGEv8i8:
11529 case AArch64::CMGEv8i16:
11530 case AArch64::CMGEv16i8:
11531 case AArch64::CMGTv1i64:
11532 case AArch64::CMGTv2i32:
11533 case AArch64::CMGTv2i64:
11534 case AArch64::CMGTv4i16:
11535 case AArch64::CMGTv4i32:
11536 case AArch64::CMGTv8i8:
11537 case AArch64::CMGTv8i16:
11538 case AArch64::CMGTv16i8:
11539 case AArch64::CMHIv1i64:
11540 case AArch64::CMHIv2i32:
11541 case AArch64::CMHIv2i64:
11542 case AArch64::CMHIv4i16:
11543 case AArch64::CMHIv4i32:
11544 case AArch64::CMHIv8i8:
11545 case AArch64::CMHIv8i16:
11546 case AArch64::CMHIv16i8:
11547 case AArch64::CMHSv1i64:
11548 case AArch64::CMHSv2i32:
11549 case AArch64::CMHSv2i64:
11550 case AArch64::CMHSv4i16:
11551 case AArch64::CMHSv4i32:
11552 case AArch64::CMHSv8i8:
11553 case AArch64::CMHSv8i16:
11554 case AArch64::CMHSv16i8:
11555 case AArch64::CMTSTv1i64:
11556 case AArch64::CMTSTv2i32:
11557 case AArch64::CMTSTv2i64:
11558 case AArch64::CMTSTv4i16:
11559 case AArch64::CMTSTv4i32:
11560 case AArch64::CMTSTv8i8:
11561 case AArch64::CMTSTv8i16:
11562 case AArch64::CMTSTv16i8:
11563 case AArch64::CRC32Brr:
11564 case AArch64::CRC32CBrr:
11565 case AArch64::CRC32CHrr:
11566 case AArch64::CRC32CWrr:
11567 case AArch64::CRC32CXrr:
11568 case AArch64::CRC32Hrr:
11569 case AArch64::CRC32Wrr:
11570 case AArch64::CRC32Xrr:
11571 case AArch64::EORv8i8:
11572 case AArch64::EORv16i8:
11573 case AArch64::FABD16:
11574 case AArch64::FABD32:
11575 case AArch64::FABD64:
11576 case AArch64::FABDv2f32:
11577 case AArch64::FABDv2f64:
11578 case AArch64::FABDv4f16:
11579 case AArch64::FABDv4f32:
11580 case AArch64::FABDv8f16:
11581 case AArch64::FACGE16:
11582 case AArch64::FACGE32:
11583 case AArch64::FACGE64:
11584 case AArch64::FACGEv2f32:
11585 case AArch64::FACGEv2f64:
11586 case AArch64::FACGEv4f16:
11587 case AArch64::FACGEv4f32:
11588 case AArch64::FACGEv8f16:
11589 case AArch64::FACGT16:
11590 case AArch64::FACGT32:
11591 case AArch64::FACGT64:
11592 case AArch64::FACGTv2f32:
11593 case AArch64::FACGTv2f64:
11594 case AArch64::FACGTv4f16:
11595 case AArch64::FACGTv4f32:
11596 case AArch64::FACGTv8f16:
11597 case AArch64::FADDDrr:
11598 case AArch64::FADDHrr:
11599 case AArch64::FADDPv2f32:
11600 case AArch64::FADDPv2f64:
11601 case AArch64::FADDPv4f16:
11602 case AArch64::FADDPv4f32:
11603 case AArch64::FADDPv8f16:
11604 case AArch64::FADDSrr:
11605 case AArch64::FADDv2f32:
11606 case AArch64::FADDv2f64:
11607 case AArch64::FADDv4f16:
11608 case AArch64::FADDv4f32:
11609 case AArch64::FADDv8f16:
11610 case AArch64::FAMAXv2f32:
11611 case AArch64::FAMAXv2f64:
11612 case AArch64::FAMAXv4f16:
11613 case AArch64::FAMAXv4f32:
11614 case AArch64::FAMAXv8f16:
11615 case AArch64::FAMINv2f32:
11616 case AArch64::FAMINv2f64:
11617 case AArch64::FAMINv4f16:
11618 case AArch64::FAMINv4f32:
11619 case AArch64::FAMINv8f16:
11620 case AArch64::FCMEQ16:
11621 case AArch64::FCMEQ32:
11622 case AArch64::FCMEQ64:
11623 case AArch64::FCMEQv2f32:
11624 case AArch64::FCMEQv2f64:
11625 case AArch64::FCMEQv4f16:
11626 case AArch64::FCMEQv4f32:
11627 case AArch64::FCMEQv8f16:
11628 case AArch64::FCMGE16:
11629 case AArch64::FCMGE32:
11630 case AArch64::FCMGE64:
11631 case AArch64::FCMGEv2f32:
11632 case AArch64::FCMGEv2f64:
11633 case AArch64::FCMGEv4f16:
11634 case AArch64::FCMGEv4f32:
11635 case AArch64::FCMGEv8f16:
11636 case AArch64::FCMGT16:
11637 case AArch64::FCMGT32:
11638 case AArch64::FCMGT64:
11639 case AArch64::FCMGTv2f32:
11640 case AArch64::FCMGTv2f64:
11641 case AArch64::FCMGTv4f16:
11642 case AArch64::FCMGTv4f32:
11643 case AArch64::FCMGTv8f16:
11644 case AArch64::FCVTN_F16_F8v8f8:
11645 case AArch64::FCVTN_F16_F8v16f8:
11646 case AArch64::FCVTN_F32_F8v8f8:
11647 case AArch64::FDIVDrr:
11648 case AArch64::FDIVHrr:
11649 case AArch64::FDIVSrr:
11650 case AArch64::FDIVv2f32:
11651 case AArch64::FDIVv2f64:
11652 case AArch64::FDIVv4f16:
11653 case AArch64::FDIVv4f32:
11654 case AArch64::FDIVv8f16:
11655 case AArch64::FMAXDrr:
11656 case AArch64::FMAXHrr:
11657 case AArch64::FMAXNMDrr:
11658 case AArch64::FMAXNMHrr:
11659 case AArch64::FMAXNMPv2f32:
11660 case AArch64::FMAXNMPv2f64:
11661 case AArch64::FMAXNMPv4f16:
11662 case AArch64::FMAXNMPv4f32:
11663 case AArch64::FMAXNMPv8f16:
11664 case AArch64::FMAXNMSrr:
11665 case AArch64::FMAXNMv2f32:
11666 case AArch64::FMAXNMv2f64:
11667 case AArch64::FMAXNMv4f16:
11668 case AArch64::FMAXNMv4f32:
11669 case AArch64::FMAXNMv8f16:
11670 case AArch64::FMAXPv2f32:
11671 case AArch64::FMAXPv2f64:
11672 case AArch64::FMAXPv4f16:
11673 case AArch64::FMAXPv4f32:
11674 case AArch64::FMAXPv8f16:
11675 case AArch64::FMAXSrr:
11676 case AArch64::FMAXv2f32:
11677 case AArch64::FMAXv2f64:
11678 case AArch64::FMAXv4f16:
11679 case AArch64::FMAXv4f32:
11680 case AArch64::FMAXv8f16:
11681 case AArch64::FMINDrr:
11682 case AArch64::FMINHrr:
11683 case AArch64::FMINNMDrr:
11684 case AArch64::FMINNMHrr:
11685 case AArch64::FMINNMPv2f32:
11686 case AArch64::FMINNMPv2f64:
11687 case AArch64::FMINNMPv4f16:
11688 case AArch64::FMINNMPv4f32:
11689 case AArch64::FMINNMPv8f16:
11690 case AArch64::FMINNMSrr:
11691 case AArch64::FMINNMv2f32:
11692 case AArch64::FMINNMv2f64:
11693 case AArch64::FMINNMv4f16:
11694 case AArch64::FMINNMv4f32:
11695 case AArch64::FMINNMv8f16:
11696 case AArch64::FMINPv2f32:
11697 case AArch64::FMINPv2f64:
11698 case AArch64::FMINPv4f16:
11699 case AArch64::FMINPv4f32:
11700 case AArch64::FMINPv8f16:
11701 case AArch64::FMINSrr:
11702 case AArch64::FMINv2f32:
11703 case AArch64::FMINv2f64:
11704 case AArch64::FMINv4f16:
11705 case AArch64::FMINv4f32:
11706 case AArch64::FMINv8f16:
11707 case AArch64::FMULDrr:
11708 case AArch64::FMULHrr:
11709 case AArch64::FMULSrr:
11710 case AArch64::FMULX16:
11711 case AArch64::FMULX32:
11712 case AArch64::FMULX64:
11713 case AArch64::FMULXv2f32:
11714 case AArch64::FMULXv2f64:
11715 case AArch64::FMULXv4f16:
11716 case AArch64::FMULXv4f32:
11717 case AArch64::FMULXv8f16:
11718 case AArch64::FMULv2f32:
11719 case AArch64::FMULv2f64:
11720 case AArch64::FMULv4f16:
11721 case AArch64::FMULv4f32:
11722 case AArch64::FMULv8f16:
11723 case AArch64::FNMULDrr:
11724 case AArch64::FNMULHrr:
11725 case AArch64::FNMULSrr:
11726 case AArch64::FRECPS16:
11727 case AArch64::FRECPS32:
11728 case AArch64::FRECPS64:
11729 case AArch64::FRECPSv2f32:
11730 case AArch64::FRECPSv2f64:
11731 case AArch64::FRECPSv4f16:
11732 case AArch64::FRECPSv4f32:
11733 case AArch64::FRECPSv8f16:
11734 case AArch64::FRSQRTS16:
11735 case AArch64::FRSQRTS32:
11736 case AArch64::FRSQRTS64:
11737 case AArch64::FRSQRTSv2f32:
11738 case AArch64::FRSQRTSv2f64:
11739 case AArch64::FRSQRTSv4f16:
11740 case AArch64::FRSQRTSv4f32:
11741 case AArch64::FRSQRTSv8f16:
11742 case AArch64::FSCALEv2f32:
11743 case AArch64::FSCALEv2f64:
11744 case AArch64::FSCALEv4f16:
11745 case AArch64::FSCALEv4f32:
11746 case AArch64::FSCALEv8f16:
11747 case AArch64::FSUBDrr:
11748 case AArch64::FSUBHrr:
11749 case AArch64::FSUBSrr:
11750 case AArch64::FSUBv2f32:
11751 case AArch64::FSUBv2f64:
11752 case AArch64::FSUBv4f16:
11753 case AArch64::FSUBv4f32:
11754 case AArch64::FSUBv8f16:
11755 case AArch64::GMI:
11756 case AArch64::IRG:
11757 case AArch64::LSLVWr:
11758 case AArch64::LSLVXr:
11759 case AArch64::LSRVWr:
11760 case AArch64::LSRVXr:
11761 case AArch64::MULv2i32:
11762 case AArch64::MULv4i16:
11763 case AArch64::MULv4i32:
11764 case AArch64::MULv8i8:
11765 case AArch64::MULv8i16:
11766 case AArch64::MULv16i8:
11767 case AArch64::ORNv8i8:
11768 case AArch64::ORNv16i8:
11769 case AArch64::ORRv8i8:
11770 case AArch64::ORRv16i8:
11771 case AArch64::PACGA:
11772 case AArch64::PMULLv1i64:
11773 case AArch64::PMULLv2i64:
11774 case AArch64::PMULLv8i8:
11775 case AArch64::PMULLv16i8:
11776 case AArch64::PMULv8i8:
11777 case AArch64::PMULv16i8:
11778 case AArch64::RADDHNv2i64_v2i32:
11779 case AArch64::RADDHNv4i32_v4i16:
11780 case AArch64::RADDHNv8i16_v8i8:
11781 case AArch64::RORVWr:
11782 case AArch64::RORVXr:
11783 case AArch64::RSUBHNv2i64_v2i32:
11784 case AArch64::RSUBHNv4i32_v4i16:
11785 case AArch64::RSUBHNv8i16_v8i8:
11786 case AArch64::SABDLv2i32_v2i64:
11787 case AArch64::SABDLv4i16_v4i32:
11788 case AArch64::SABDLv4i32_v2i64:
11789 case AArch64::SABDLv8i8_v8i16:
11790 case AArch64::SABDLv8i16_v4i32:
11791 case AArch64::SABDLv16i8_v8i16:
11792 case AArch64::SABDv2i32:
11793 case AArch64::SABDv4i16:
11794 case AArch64::SABDv4i32:
11795 case AArch64::SABDv8i8:
11796 case AArch64::SABDv8i16:
11797 case AArch64::SABDv16i8:
11798 case AArch64::SADDLv2i32_v2i64:
11799 case AArch64::SADDLv4i16_v4i32:
11800 case AArch64::SADDLv4i32_v2i64:
11801 case AArch64::SADDLv8i8_v8i16:
11802 case AArch64::SADDLv8i16_v4i32:
11803 case AArch64::SADDLv16i8_v8i16:
11804 case AArch64::SADDWv2i32_v2i64:
11805 case AArch64::SADDWv4i16_v4i32:
11806 case AArch64::SADDWv4i32_v2i64:
11807 case AArch64::SADDWv8i8_v8i16:
11808 case AArch64::SADDWv8i16_v4i32:
11809 case AArch64::SADDWv16i8_v8i16:
11810 case AArch64::SBCSWr:
11811 case AArch64::SBCSXr:
11812 case AArch64::SBCWr:
11813 case AArch64::SBCXr:
11814 case AArch64::SDIVWr:
11815 case AArch64::SDIVXr:
11816 case AArch64::SHADDv2i32:
11817 case AArch64::SHADDv4i16:
11818 case AArch64::SHADDv4i32:
11819 case AArch64::SHADDv8i8:
11820 case AArch64::SHADDv8i16:
11821 case AArch64::SHADDv16i8:
11822 case AArch64::SHSUBv2i32:
11823 case AArch64::SHSUBv4i16:
11824 case AArch64::SHSUBv4i32:
11825 case AArch64::SHSUBv8i8:
11826 case AArch64::SHSUBv8i16:
11827 case AArch64::SHSUBv16i8:
11828 case AArch64::SMAXPv2i32:
11829 case AArch64::SMAXPv4i16:
11830 case AArch64::SMAXPv4i32:
11831 case AArch64::SMAXPv8i8:
11832 case AArch64::SMAXPv8i16:
11833 case AArch64::SMAXPv16i8:
11834 case AArch64::SMAXWrr:
11835 case AArch64::SMAXXrr:
11836 case AArch64::SMAXv2i32:
11837 case AArch64::SMAXv4i16:
11838 case AArch64::SMAXv4i32:
11839 case AArch64::SMAXv8i8:
11840 case AArch64::SMAXv8i16:
11841 case AArch64::SMAXv16i8:
11842 case AArch64::SMINPv2i32:
11843 case AArch64::SMINPv4i16:
11844 case AArch64::SMINPv4i32:
11845 case AArch64::SMINPv8i8:
11846 case AArch64::SMINPv8i16:
11847 case AArch64::SMINPv16i8:
11848 case AArch64::SMINWrr:
11849 case AArch64::SMINXrr:
11850 case AArch64::SMINv2i32:
11851 case AArch64::SMINv4i16:
11852 case AArch64::SMINv4i32:
11853 case AArch64::SMINv8i8:
11854 case AArch64::SMINv8i16:
11855 case AArch64::SMINv16i8:
11856 case AArch64::SMULLv2i32_v2i64:
11857 case AArch64::SMULLv4i16_v4i32:
11858 case AArch64::SMULLv4i32_v2i64:
11859 case AArch64::SMULLv8i8_v8i16:
11860 case AArch64::SMULLv8i16_v4i32:
11861 case AArch64::SMULLv16i8_v8i16:
11862 case AArch64::SQADDv1i8:
11863 case AArch64::SQADDv1i16:
11864 case AArch64::SQADDv1i32:
11865 case AArch64::SQADDv1i64:
11866 case AArch64::SQADDv2i32:
11867 case AArch64::SQADDv2i64:
11868 case AArch64::SQADDv4i16:
11869 case AArch64::SQADDv4i32:
11870 case AArch64::SQADDv8i8:
11871 case AArch64::SQADDv8i16:
11872 case AArch64::SQADDv16i8:
11873 case AArch64::SQDMULHv1i16:
11874 case AArch64::SQDMULHv1i32:
11875 case AArch64::SQDMULHv2i32:
11876 case AArch64::SQDMULHv4i16:
11877 case AArch64::SQDMULHv4i32:
11878 case AArch64::SQDMULHv8i16:
11879 case AArch64::SQDMULLi16:
11880 case AArch64::SQDMULLi32:
11881 case AArch64::SQDMULLv2i32_v2i64:
11882 case AArch64::SQDMULLv4i16_v4i32:
11883 case AArch64::SQDMULLv4i32_v2i64:
11884 case AArch64::SQDMULLv8i16_v4i32:
11885 case AArch64::SQRDMULHv1i16:
11886 case AArch64::SQRDMULHv1i32:
11887 case AArch64::SQRDMULHv2i32:
11888 case AArch64::SQRDMULHv4i16:
11889 case AArch64::SQRDMULHv4i32:
11890 case AArch64::SQRDMULHv8i16:
11891 case AArch64::SQRSHLv1i8:
11892 case AArch64::SQRSHLv1i16:
11893 case AArch64::SQRSHLv1i32:
11894 case AArch64::SQRSHLv1i64:
11895 case AArch64::SQRSHLv2i32:
11896 case AArch64::SQRSHLv2i64:
11897 case AArch64::SQRSHLv4i16:
11898 case AArch64::SQRSHLv4i32:
11899 case AArch64::SQRSHLv8i8:
11900 case AArch64::SQRSHLv8i16:
11901 case AArch64::SQRSHLv16i8:
11902 case AArch64::SQSHLv1i8:
11903 case AArch64::SQSHLv1i16:
11904 case AArch64::SQSHLv1i32:
11905 case AArch64::SQSHLv1i64:
11906 case AArch64::SQSHLv2i32:
11907 case AArch64::SQSHLv2i64:
11908 case AArch64::SQSHLv4i16:
11909 case AArch64::SQSHLv4i32:
11910 case AArch64::SQSHLv8i8:
11911 case AArch64::SQSHLv8i16:
11912 case AArch64::SQSHLv16i8:
11913 case AArch64::SQSUBv1i8:
11914 case AArch64::SQSUBv1i16:
11915 case AArch64::SQSUBv1i32:
11916 case AArch64::SQSUBv1i64:
11917 case AArch64::SQSUBv2i32:
11918 case AArch64::SQSUBv2i64:
11919 case AArch64::SQSUBv4i16:
11920 case AArch64::SQSUBv4i32:
11921 case AArch64::SQSUBv8i8:
11922 case AArch64::SQSUBv8i16:
11923 case AArch64::SQSUBv16i8:
11924 case AArch64::SRHADDv2i32:
11925 case AArch64::SRHADDv4i16:
11926 case AArch64::SRHADDv4i32:
11927 case AArch64::SRHADDv8i8:
11928 case AArch64::SRHADDv8i16:
11929 case AArch64::SRHADDv16i8:
11930 case AArch64::SRSHLv1i64:
11931 case AArch64::SRSHLv2i32:
11932 case AArch64::SRSHLv2i64:
11933 case AArch64::SRSHLv4i16:
11934 case AArch64::SRSHLv4i32:
11935 case AArch64::SRSHLv8i8:
11936 case AArch64::SRSHLv8i16:
11937 case AArch64::SRSHLv16i8:
11938 case AArch64::SSHLv1i64:
11939 case AArch64::SSHLv2i32:
11940 case AArch64::SSHLv2i64:
11941 case AArch64::SSHLv4i16:
11942 case AArch64::SSHLv4i32:
11943 case AArch64::SSHLv8i8:
11944 case AArch64::SSHLv8i16:
11945 case AArch64::SSHLv16i8:
11946 case AArch64::SSUBLv2i32_v2i64:
11947 case AArch64::SSUBLv4i16_v4i32:
11948 case AArch64::SSUBLv4i32_v2i64:
11949 case AArch64::SSUBLv8i8_v8i16:
11950 case AArch64::SSUBLv8i16_v4i32:
11951 case AArch64::SSUBLv16i8_v8i16:
11952 case AArch64::SSUBWv2i32_v2i64:
11953 case AArch64::SSUBWv4i16_v4i32:
11954 case AArch64::SSUBWv4i32_v2i64:
11955 case AArch64::SSUBWv8i8_v8i16:
11956 case AArch64::SSUBWv8i16_v4i32:
11957 case AArch64::SSUBWv16i8_v8i16:
11958 case AArch64::SUBHNv2i64_v2i32:
11959 case AArch64::SUBHNv4i32_v4i16:
11960 case AArch64::SUBHNv8i16_v8i8:
11961 case AArch64::SUBP:
11962 case AArch64::SUBPS:
11963 case AArch64::SUBv1i64:
11964 case AArch64::SUBv2i32:
11965 case AArch64::SUBv2i64:
11966 case AArch64::SUBv4i16:
11967 case AArch64::SUBv4i32:
11968 case AArch64::SUBv8i8:
11969 case AArch64::SUBv8i16:
11970 case AArch64::SUBv16i8:
11971 case AArch64::TRN1v2i32:
11972 case AArch64::TRN1v2i64:
11973 case AArch64::TRN1v4i16:
11974 case AArch64::TRN1v4i32:
11975 case AArch64::TRN1v8i8:
11976 case AArch64::TRN1v8i16:
11977 case AArch64::TRN1v16i8:
11978 case AArch64::TRN2v2i32:
11979 case AArch64::TRN2v2i64:
11980 case AArch64::TRN2v4i16:
11981 case AArch64::TRN2v4i32:
11982 case AArch64::TRN2v8i8:
11983 case AArch64::TRN2v8i16:
11984 case AArch64::TRN2v16i8:
11985 case AArch64::UABDLv2i32_v2i64:
11986 case AArch64::UABDLv4i16_v4i32:
11987 case AArch64::UABDLv4i32_v2i64:
11988 case AArch64::UABDLv8i8_v8i16:
11989 case AArch64::UABDLv8i16_v4i32:
11990 case AArch64::UABDLv16i8_v8i16:
11991 case AArch64::UABDv2i32:
11992 case AArch64::UABDv4i16:
11993 case AArch64::UABDv4i32:
11994 case AArch64::UABDv8i8:
11995 case AArch64::UABDv8i16:
11996 case AArch64::UABDv16i8:
11997 case AArch64::UADDLv2i32_v2i64:
11998 case AArch64::UADDLv4i16_v4i32:
11999 case AArch64::UADDLv4i32_v2i64:
12000 case AArch64::UADDLv8i8_v8i16:
12001 case AArch64::UADDLv8i16_v4i32:
12002 case AArch64::UADDLv16i8_v8i16:
12003 case AArch64::UADDWv2i32_v2i64:
12004 case AArch64::UADDWv4i16_v4i32:
12005 case AArch64::UADDWv4i32_v2i64:
12006 case AArch64::UADDWv8i8_v8i16:
12007 case AArch64::UADDWv8i16_v4i32:
12008 case AArch64::UADDWv16i8_v8i16:
12009 case AArch64::UDIVWr:
12010 case AArch64::UDIVXr:
12011 case AArch64::UHADDv2i32:
12012 case AArch64::UHADDv4i16:
12013 case AArch64::UHADDv4i32:
12014 case AArch64::UHADDv8i8:
12015 case AArch64::UHADDv8i16:
12016 case AArch64::UHADDv16i8:
12017 case AArch64::UHSUBv2i32:
12018 case AArch64::UHSUBv4i16:
12019 case AArch64::UHSUBv4i32:
12020 case AArch64::UHSUBv8i8:
12021 case AArch64::UHSUBv8i16:
12022 case AArch64::UHSUBv16i8:
12023 case AArch64::UMAXPv2i32:
12024 case AArch64::UMAXPv4i16:
12025 case AArch64::UMAXPv4i32:
12026 case AArch64::UMAXPv8i8:
12027 case AArch64::UMAXPv8i16:
12028 case AArch64::UMAXPv16i8:
12029 case AArch64::UMAXWrr:
12030 case AArch64::UMAXXrr:
12031 case AArch64::UMAXv2i32:
12032 case AArch64::UMAXv4i16:
12033 case AArch64::UMAXv4i32:
12034 case AArch64::UMAXv8i8:
12035 case AArch64::UMAXv8i16:
12036 case AArch64::UMAXv16i8:
12037 case AArch64::UMINPv2i32:
12038 case AArch64::UMINPv4i16:
12039 case AArch64::UMINPv4i32:
12040 case AArch64::UMINPv8i8:
12041 case AArch64::UMINPv8i16:
12042 case AArch64::UMINPv16i8:
12043 case AArch64::UMINWrr:
12044 case AArch64::UMINXrr:
12045 case AArch64::UMINv2i32:
12046 case AArch64::UMINv4i16:
12047 case AArch64::UMINv4i32:
12048 case AArch64::UMINv8i8:
12049 case AArch64::UMINv8i16:
12050 case AArch64::UMINv16i8:
12051 case AArch64::UMULLv2i32_v2i64:
12052 case AArch64::UMULLv4i16_v4i32:
12053 case AArch64::UMULLv4i32_v2i64:
12054 case AArch64::UMULLv8i8_v8i16:
12055 case AArch64::UMULLv8i16_v4i32:
12056 case AArch64::UMULLv16i8_v8i16:
12057 case AArch64::UQADDv1i8:
12058 case AArch64::UQADDv1i16:
12059 case AArch64::UQADDv1i32:
12060 case AArch64::UQADDv1i64:
12061 case AArch64::UQADDv2i32:
12062 case AArch64::UQADDv2i64:
12063 case AArch64::UQADDv4i16:
12064 case AArch64::UQADDv4i32:
12065 case AArch64::UQADDv8i8:
12066 case AArch64::UQADDv8i16:
12067 case AArch64::UQADDv16i8:
12068 case AArch64::UQRSHLv1i8:
12069 case AArch64::UQRSHLv1i16:
12070 case AArch64::UQRSHLv1i32:
12071 case AArch64::UQRSHLv1i64:
12072 case AArch64::UQRSHLv2i32:
12073 case AArch64::UQRSHLv2i64:
12074 case AArch64::UQRSHLv4i16:
12075 case AArch64::UQRSHLv4i32:
12076 case AArch64::UQRSHLv8i8:
12077 case AArch64::UQRSHLv8i16:
12078 case AArch64::UQRSHLv16i8:
12079 case AArch64::UQSHLv1i8:
12080 case AArch64::UQSHLv1i16:
12081 case AArch64::UQSHLv1i32:
12082 case AArch64::UQSHLv1i64:
12083 case AArch64::UQSHLv2i32:
12084 case AArch64::UQSHLv2i64:
12085 case AArch64::UQSHLv4i16:
12086 case AArch64::UQSHLv4i32:
12087 case AArch64::UQSHLv8i8:
12088 case AArch64::UQSHLv8i16:
12089 case AArch64::UQSHLv16i8:
12090 case AArch64::UQSUBv1i8:
12091 case AArch64::UQSUBv1i16:
12092 case AArch64::UQSUBv1i32:
12093 case AArch64::UQSUBv1i64:
12094 case AArch64::UQSUBv2i32:
12095 case AArch64::UQSUBv2i64:
12096 case AArch64::UQSUBv4i16:
12097 case AArch64::UQSUBv4i32:
12098 case AArch64::UQSUBv8i8:
12099 case AArch64::UQSUBv8i16:
12100 case AArch64::UQSUBv16i8:
12101 case AArch64::URHADDv2i32:
12102 case AArch64::URHADDv4i16:
12103 case AArch64::URHADDv4i32:
12104 case AArch64::URHADDv8i8:
12105 case AArch64::URHADDv8i16:
12106 case AArch64::URHADDv16i8:
12107 case AArch64::URSHLv1i64:
12108 case AArch64::URSHLv2i32:
12109 case AArch64::URSHLv2i64:
12110 case AArch64::URSHLv4i16:
12111 case AArch64::URSHLv4i32:
12112 case AArch64::URSHLv8i8:
12113 case AArch64::URSHLv8i16:
12114 case AArch64::URSHLv16i8:
12115 case AArch64::USHLv1i64:
12116 case AArch64::USHLv2i32:
12117 case AArch64::USHLv2i64:
12118 case AArch64::USHLv4i16:
12119 case AArch64::USHLv4i32:
12120 case AArch64::USHLv8i8:
12121 case AArch64::USHLv8i16:
12122 case AArch64::USHLv16i8:
12123 case AArch64::USUBLv2i32_v2i64:
12124 case AArch64::USUBLv4i16_v4i32:
12125 case AArch64::USUBLv4i32_v2i64:
12126 case AArch64::USUBLv8i8_v8i16:
12127 case AArch64::USUBLv8i16_v4i32:
12128 case AArch64::USUBLv16i8_v8i16:
12129 case AArch64::USUBWv2i32_v2i64:
12130 case AArch64::USUBWv4i16_v4i32:
12131 case AArch64::USUBWv4i32_v2i64:
12132 case AArch64::USUBWv8i8_v8i16:
12133 case AArch64::USUBWv8i16_v4i32:
12134 case AArch64::USUBWv16i8_v8i16:
12135 case AArch64::UZP1v2i32:
12136 case AArch64::UZP1v2i64:
12137 case AArch64::UZP1v4i16:
12138 case AArch64::UZP1v4i32:
12139 case AArch64::UZP1v8i8:
12140 case AArch64::UZP1v8i16:
12141 case AArch64::UZP1v16i8:
12142 case AArch64::UZP2v2i32:
12143 case AArch64::UZP2v2i64:
12144 case AArch64::UZP2v4i16:
12145 case AArch64::UZP2v4i32:
12146 case AArch64::UZP2v8i8:
12147 case AArch64::UZP2v8i16:
12148 case AArch64::UZP2v16i8:
12149 case AArch64::ZIP1v2i32:
12150 case AArch64::ZIP1v2i64:
12151 case AArch64::ZIP1v4i16:
12152 case AArch64::ZIP1v4i32:
12153 case AArch64::ZIP1v8i8:
12154 case AArch64::ZIP1v8i16:
12155 case AArch64::ZIP1v16i8:
12156 case AArch64::ZIP2v2i32:
12157 case AArch64::ZIP2v2i64:
12158 case AArch64::ZIP2v4i16:
12159 case AArch64::ZIP2v4i32:
12160 case AArch64::ZIP2v8i8:
12161 case AArch64::ZIP2v8i16:
12162 case AArch64::ZIP2v16i8: {
12163 // op: Rd
12164 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12165 op &= UINT64_C(31);
12166 Value |= op;
12167 // op: Rn
12168 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12169 op &= UINT64_C(31);
12170 op <<= 5;
12171 Value |= op;
12172 // op: Rm
12173 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12174 op &= UINT64_C(31);
12175 op <<= 16;
12176 Value |= op;
12177 break;
12178 }
12179 case AArch64::FMADDDrrr:
12180 case AArch64::FMADDHrrr:
12181 case AArch64::FMADDSrrr:
12182 case AArch64::FMSUBDrrr:
12183 case AArch64::FMSUBHrrr:
12184 case AArch64::FMSUBSrrr:
12185 case AArch64::FNMADDDrrr:
12186 case AArch64::FNMADDHrrr:
12187 case AArch64::FNMADDSrrr:
12188 case AArch64::FNMSUBDrrr:
12189 case AArch64::FNMSUBHrrr:
12190 case AArch64::FNMSUBSrrr:
12191 case AArch64::MADDPT:
12192 case AArch64::MADDWrrr:
12193 case AArch64::MADDXrrr:
12194 case AArch64::MSUBPT:
12195 case AArch64::MSUBWrrr:
12196 case AArch64::MSUBXrrr:
12197 case AArch64::SMADDLrrr:
12198 case AArch64::SMSUBLrrr:
12199 case AArch64::UMADDLrrr:
12200 case AArch64::UMSUBLrrr: {
12201 // op: Rd
12202 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12203 op &= UINT64_C(31);
12204 Value |= op;
12205 // op: Rn
12206 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12207 op &= UINT64_C(31);
12208 op <<= 5;
12209 Value |= op;
12210 // op: Rm
12211 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12212 op &= UINT64_C(31);
12213 op <<= 16;
12214 Value |= op;
12215 // op: Ra
12216 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12217 op &= UINT64_C(31);
12218 op <<= 10;
12219 Value |= op;
12220 break;
12221 }
12222 case AArch64::CSELWr:
12223 case AArch64::CSELXr:
12224 case AArch64::CSINCWr:
12225 case AArch64::CSINCXr:
12226 case AArch64::CSINVWr:
12227 case AArch64::CSINVXr:
12228 case AArch64::CSNEGWr:
12229 case AArch64::CSNEGXr:
12230 case AArch64::FCSELDrrr:
12231 case AArch64::FCSELHrrr:
12232 case AArch64::FCSELSrrr: {
12233 // op: Rd
12234 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12235 op &= UINT64_C(31);
12236 Value |= op;
12237 // op: Rn
12238 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12239 op &= UINT64_C(31);
12240 op <<= 5;
12241 Value |= op;
12242 // op: Rm
12243 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12244 op &= UINT64_C(31);
12245 op <<= 16;
12246 Value |= op;
12247 // op: cond
12248 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12249 op &= UINT64_C(15);
12250 op <<= 12;
12251 Value |= op;
12252 break;
12253 }
12254 case AArch64::ADDSXrx64:
12255 case AArch64::ADDXrx64:
12256 case AArch64::SUBSXrx64:
12257 case AArch64::SUBXrx64: {
12258 // op: Rd
12259 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12260 op &= UINT64_C(31);
12261 Value |= op;
12262 // op: Rn
12263 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12264 op &= UINT64_C(31);
12265 op <<= 5;
12266 Value |= op;
12267 // op: Rm
12268 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12269 op &= UINT64_C(31);
12270 op <<= 16;
12271 Value |= op;
12272 // op: ext
12273 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12274 Value |= (op & UINT64_C(32)) << 10;
12275 Value |= (op & UINT64_C(7)) << 10;
12276 break;
12277 }
12278 case AArch64::ADDSWrx:
12279 case AArch64::ADDSXrx:
12280 case AArch64::ADDWrx:
12281 case AArch64::ADDXrx:
12282 case AArch64::SUBSWrx:
12283 case AArch64::SUBSXrx:
12284 case AArch64::SUBWrx:
12285 case AArch64::SUBXrx: {
12286 // op: Rd
12287 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12288 op &= UINT64_C(31);
12289 Value |= op;
12290 // op: Rn
12291 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12292 op &= UINT64_C(31);
12293 op <<= 5;
12294 Value |= op;
12295 // op: Rm
12296 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12297 op &= UINT64_C(31);
12298 op <<= 16;
12299 Value |= op;
12300 // op: extend
12301 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12302 op &= UINT64_C(63);
12303 op <<= 10;
12304 Value |= op;
12305 break;
12306 }
12307 case AArch64::FMULXv1i32_indexed:
12308 case AArch64::FMULXv2i32_indexed:
12309 case AArch64::FMULXv4i32_indexed:
12310 case AArch64::FMULv1i32_indexed:
12311 case AArch64::FMULv2i32_indexed:
12312 case AArch64::FMULv4i32_indexed:
12313 case AArch64::MULv2i32_indexed:
12314 case AArch64::MULv4i32_indexed:
12315 case AArch64::SMULLv2i32_indexed:
12316 case AArch64::SMULLv4i32_indexed:
12317 case AArch64::SQDMULHv1i32_indexed:
12318 case AArch64::SQDMULHv2i32_indexed:
12319 case AArch64::SQDMULHv4i32_indexed:
12320 case AArch64::SQDMULLv1i64_indexed:
12321 case AArch64::SQDMULLv2i32_indexed:
12322 case AArch64::SQDMULLv4i32_indexed:
12323 case AArch64::SQRDMULHv1i32_indexed:
12324 case AArch64::SQRDMULHv2i32_indexed:
12325 case AArch64::SQRDMULHv4i32_indexed:
12326 case AArch64::UMULLv2i32_indexed:
12327 case AArch64::UMULLv4i32_indexed: {
12328 // op: Rd
12329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12330 op &= UINT64_C(31);
12331 Value |= op;
12332 // op: Rn
12333 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12334 op &= UINT64_C(31);
12335 op <<= 5;
12336 Value |= op;
12337 // op: Rm
12338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12339 op &= UINT64_C(31);
12340 op <<= 16;
12341 Value |= op;
12342 // op: idx
12343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12344 Value |= (op & UINT64_C(1)) << 21;
12345 Value |= (op & UINT64_C(2)) << 10;
12346 break;
12347 }
12348 case AArch64::FMULXv1i64_indexed:
12349 case AArch64::FMULXv2i64_indexed:
12350 case AArch64::FMULv1i64_indexed:
12351 case AArch64::FMULv2i64_indexed: {
12352 // op: Rd
12353 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12354 op &= UINT64_C(31);
12355 Value |= op;
12356 // op: Rn
12357 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12358 op &= UINT64_C(31);
12359 op <<= 5;
12360 Value |= op;
12361 // op: Rm
12362 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12363 op &= UINT64_C(31);
12364 op <<= 16;
12365 Value |= op;
12366 // op: idx
12367 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12368 op &= UINT64_C(1);
12369 op <<= 11;
12370 Value |= op;
12371 break;
12372 }
12373 case AArch64::LUT4v16f8: {
12374 // op: Rd
12375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12376 op &= UINT64_C(31);
12377 Value |= op;
12378 // op: Rn
12379 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12380 op &= UINT64_C(31);
12381 op <<= 5;
12382 Value |= op;
12383 // op: Rm
12384 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12385 op &= UINT64_C(31);
12386 op <<= 16;
12387 Value |= op;
12388 // op: idx
12389 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12390 op &= UINT64_C(1);
12391 op <<= 14;
12392 Value |= op;
12393 break;
12394 }
12395 case AArch64::LUT2v16f8:
12396 case AArch64::LUT4v8f16: {
12397 // op: Rd
12398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12399 op &= UINT64_C(31);
12400 Value |= op;
12401 // op: Rn
12402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12403 op &= UINT64_C(31);
12404 op <<= 5;
12405 Value |= op;
12406 // op: Rm
12407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12408 op &= UINT64_C(31);
12409 op <<= 16;
12410 Value |= op;
12411 // op: idx
12412 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12413 op &= UINT64_C(3);
12414 op <<= 13;
12415 Value |= op;
12416 break;
12417 }
12418 case AArch64::LUT2v8f16: {
12419 // op: Rd
12420 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12421 op &= UINT64_C(31);
12422 Value |= op;
12423 // op: Rn
12424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12425 op &= UINT64_C(31);
12426 op <<= 5;
12427 Value |= op;
12428 // op: Rm
12429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12430 op &= UINT64_C(31);
12431 op <<= 16;
12432 Value |= op;
12433 // op: idx
12434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12435 op &= UINT64_C(7);
12436 op <<= 12;
12437 Value |= op;
12438 break;
12439 }
12440 case AArch64::EXTv16i8: {
12441 // op: Rd
12442 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12443 op &= UINT64_C(31);
12444 Value |= op;
12445 // op: Rn
12446 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12447 op &= UINT64_C(31);
12448 op <<= 5;
12449 Value |= op;
12450 // op: Rm
12451 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12452 op &= UINT64_C(31);
12453 op <<= 16;
12454 Value |= op;
12455 // op: imm
12456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12457 op &= UINT64_C(15);
12458 op <<= 11;
12459 Value |= op;
12460 break;
12461 }
12462 case AArch64::EXTRWrri: {
12463 // op: Rd
12464 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12465 op &= UINT64_C(31);
12466 Value |= op;
12467 // op: Rn
12468 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12469 op &= UINT64_C(31);
12470 op <<= 5;
12471 Value |= op;
12472 // op: Rm
12473 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12474 op &= UINT64_C(31);
12475 op <<= 16;
12476 Value |= op;
12477 // op: imm
12478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12479 op &= UINT64_C(31);
12480 op <<= 10;
12481 Value |= op;
12482 break;
12483 }
12484 case AArch64::EXTRXrri: {
12485 // op: Rd
12486 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12487 op &= UINT64_C(31);
12488 Value |= op;
12489 // op: Rn
12490 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12491 op &= UINT64_C(31);
12492 op <<= 5;
12493 Value |= op;
12494 // op: Rm
12495 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12496 op &= UINT64_C(31);
12497 op <<= 16;
12498 Value |= op;
12499 // op: imm
12500 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12501 op &= UINT64_C(63);
12502 op <<= 10;
12503 Value |= op;
12504 break;
12505 }
12506 case AArch64::EXTv8i8: {
12507 // op: Rd
12508 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12509 op &= UINT64_C(31);
12510 Value |= op;
12511 // op: Rn
12512 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12513 op &= UINT64_C(31);
12514 op <<= 5;
12515 Value |= op;
12516 // op: Rm
12517 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12518 op &= UINT64_C(31);
12519 op <<= 16;
12520 Value |= op;
12521 // op: imm
12522 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12523 op &= UINT64_C(7);
12524 op <<= 11;
12525 Value |= op;
12526 break;
12527 }
12528 case AArch64::FCADDv2f32:
12529 case AArch64::FCADDv2f64:
12530 case AArch64::FCADDv4f16:
12531 case AArch64::FCADDv4f32:
12532 case AArch64::FCADDv8f16: {
12533 // op: Rd
12534 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12535 op &= UINT64_C(31);
12536 Value |= op;
12537 // op: Rn
12538 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12539 op &= UINT64_C(31);
12540 op <<= 5;
12541 Value |= op;
12542 // op: Rm
12543 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12544 op &= UINT64_C(31);
12545 op <<= 16;
12546 Value |= op;
12547 // op: rot
12548 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12549 op &= UINT64_C(1);
12550 op <<= 12;
12551 Value |= op;
12552 break;
12553 }
12554 case AArch64::ADDSWrs:
12555 case AArch64::ADDSXrs:
12556 case AArch64::ADDWrs:
12557 case AArch64::ADDXrs:
12558 case AArch64::ANDSWrs:
12559 case AArch64::ANDSXrs:
12560 case AArch64::ANDWrs:
12561 case AArch64::ANDXrs:
12562 case AArch64::BICSWrs:
12563 case AArch64::BICSXrs:
12564 case AArch64::BICWrs:
12565 case AArch64::BICXrs:
12566 case AArch64::EONWrs:
12567 case AArch64::EONXrs:
12568 case AArch64::EORWrs:
12569 case AArch64::EORXrs:
12570 case AArch64::ORNWrs:
12571 case AArch64::ORNXrs:
12572 case AArch64::ORRWrs:
12573 case AArch64::ORRXrs:
12574 case AArch64::SUBSWrs:
12575 case AArch64::SUBSXrs:
12576 case AArch64::SUBWrs:
12577 case AArch64::SUBXrs: {
12578 // op: Rd
12579 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12580 op &= UINT64_C(31);
12581 Value |= op;
12582 // op: Rn
12583 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12584 op &= UINT64_C(31);
12585 op <<= 5;
12586 Value |= op;
12587 // op: Rm
12588 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12589 op &= UINT64_C(31);
12590 op <<= 16;
12591 Value |= op;
12592 // op: shift
12593 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12594 Value |= (op & UINT64_C(192)) << 16;
12595 Value |= (op & UINT64_C(63)) << 10;
12596 break;
12597 }
12598 case AArch64::ADDPT_shift:
12599 case AArch64::SUBPT_shift: {
12600 // op: Rd
12601 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12602 op &= UINT64_C(31);
12603 Value |= op;
12604 // op: Rn
12605 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12606 op &= UINT64_C(31);
12607 op <<= 5;
12608 Value |= op;
12609 // op: Rm
12610 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12611 op &= UINT64_C(31);
12612 op <<= 16;
12613 Value |= op;
12614 // op: shift_imm
12615 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
12616 op &= UINT64_C(7);
12617 op <<= 10;
12618 Value |= op;
12619 break;
12620 }
12621 case AArch64::SMULHrr:
12622 case AArch64::UMULHrr: {
12623 // op: Rd
12624 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12625 op &= UINT64_C(31);
12626 Value |= op;
12627 // op: Rn
12628 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12629 op &= UINT64_C(31);
12630 op <<= 5;
12631 Value |= op;
12632 // op: Rm
12633 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12634 op &= UINT64_C(31);
12635 op <<= 16;
12636 Value |= op;
12637 Value = fixMulHigh(MI, EncodedValue: Value, STI);
12638 break;
12639 }
12640 case AArch64::DUPv2i64lane:
12641 case AArch64::UMOVvi64: {
12642 // op: Rd
12643 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12644 op &= UINT64_C(31);
12645 Value |= op;
12646 // op: Rn
12647 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12648 op &= UINT64_C(31);
12649 op <<= 5;
12650 Value |= op;
12651 // op: idx
12652 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12653 op &= UINT64_C(1);
12654 op <<= 20;
12655 Value |= op;
12656 break;
12657 }
12658 case AArch64::DUPv8i8lane:
12659 case AArch64::DUPv16i8lane:
12660 case AArch64::SMOVvi8to32:
12661 case AArch64::SMOVvi8to64:
12662 case AArch64::UMOVvi8: {
12663 // op: Rd
12664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12665 op &= UINT64_C(31);
12666 Value |= op;
12667 // op: Rn
12668 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12669 op &= UINT64_C(31);
12670 op <<= 5;
12671 Value |= op;
12672 // op: idx
12673 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12674 op &= UINT64_C(15);
12675 op <<= 17;
12676 Value |= op;
12677 break;
12678 }
12679 case AArch64::DUPv2i32lane:
12680 case AArch64::DUPv4i32lane:
12681 case AArch64::SMOVvi32to64:
12682 case AArch64::UMOVvi32: {
12683 // op: Rd
12684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12685 op &= UINT64_C(31);
12686 Value |= op;
12687 // op: Rn
12688 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12689 op &= UINT64_C(31);
12690 op <<= 5;
12691 Value |= op;
12692 // op: idx
12693 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12694 op &= UINT64_C(3);
12695 op <<= 19;
12696 Value |= op;
12697 break;
12698 }
12699 case AArch64::DUPv4i16lane:
12700 case AArch64::DUPv8i16lane:
12701 case AArch64::SMOVvi16to32:
12702 case AArch64::SMOVvi16to64:
12703 case AArch64::UMOVvi16: {
12704 // op: Rd
12705 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12706 op &= UINT64_C(31);
12707 Value |= op;
12708 // op: Rn
12709 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12710 op &= UINT64_C(31);
12711 op <<= 5;
12712 Value |= op;
12713 // op: idx
12714 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12715 op &= UINT64_C(7);
12716 op <<= 18;
12717 Value |= op;
12718 break;
12719 }
12720 case AArch64::ADDSWri:
12721 case AArch64::ADDSXri:
12722 case AArch64::ADDWri:
12723 case AArch64::ADDXri:
12724 case AArch64::SUBSWri:
12725 case AArch64::SUBSXri:
12726 case AArch64::SUBWri:
12727 case AArch64::SUBXri: {
12728 // op: Rd
12729 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12730 op &= UINT64_C(31);
12731 Value |= op;
12732 // op: Rn
12733 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12734 op &= UINT64_C(31);
12735 op <<= 5;
12736 Value |= op;
12737 // op: imm
12738 op = getAddSubImmOpValue(MI, OpIdx: 2, Fixups, STI);
12739 op &= UINT64_C(16383);
12740 op <<= 10;
12741 Value |= op;
12742 break;
12743 }
12744 case AArch64::SMAXWri:
12745 case AArch64::SMAXXri:
12746 case AArch64::SMINWri:
12747 case AArch64::SMINXri:
12748 case AArch64::UMAXWri:
12749 case AArch64::UMAXXri:
12750 case AArch64::UMINWri:
12751 case AArch64::UMINXri: {
12752 // op: Rd
12753 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12754 op &= UINT64_C(31);
12755 Value |= op;
12756 // op: Rn
12757 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12758 op &= UINT64_C(31);
12759 op <<= 5;
12760 Value |= op;
12761 // op: imm
12762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12763 op &= UINT64_C(255);
12764 op <<= 10;
12765 Value |= op;
12766 break;
12767 }
12768 case AArch64::ANDSWri:
12769 case AArch64::ANDWri:
12770 case AArch64::EORWri:
12771 case AArch64::ORRWri: {
12772 // op: Rd
12773 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12774 op &= UINT64_C(31);
12775 Value |= op;
12776 // op: Rn
12777 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12778 op &= UINT64_C(31);
12779 op <<= 5;
12780 Value |= op;
12781 // op: imm
12782 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12783 op &= UINT64_C(4095);
12784 op <<= 10;
12785 Value |= op;
12786 break;
12787 }
12788 case AArch64::ANDSXri:
12789 case AArch64::ANDXri:
12790 case AArch64::EORXri:
12791 case AArch64::ORRXri: {
12792 // op: Rd
12793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12794 op &= UINT64_C(31);
12795 Value |= op;
12796 // op: Rn
12797 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12798 op &= UINT64_C(31);
12799 op <<= 5;
12800 Value |= op;
12801 // op: imm
12802 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
12803 op &= UINT64_C(8191);
12804 op <<= 10;
12805 Value |= op;
12806 break;
12807 }
12808 case AArch64::SHLv4i16_shift:
12809 case AArch64::SHLv8i16_shift:
12810 case AArch64::SQSHLUh:
12811 case AArch64::SQSHLUv4i16_shift:
12812 case AArch64::SQSHLUv8i16_shift:
12813 case AArch64::SQSHLh:
12814 case AArch64::SQSHLv4i16_shift:
12815 case AArch64::SQSHLv8i16_shift:
12816 case AArch64::SSHLLv4i16_shift:
12817 case AArch64::SSHLLv8i16_shift:
12818 case AArch64::UQSHLh:
12819 case AArch64::UQSHLv4i16_shift:
12820 case AArch64::UQSHLv8i16_shift:
12821 case AArch64::USHLLv4i16_shift:
12822 case AArch64::USHLLv8i16_shift: {
12823 // op: Rd
12824 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12825 op &= UINT64_C(31);
12826 Value |= op;
12827 // op: Rn
12828 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12829 op &= UINT64_C(31);
12830 op <<= 5;
12831 Value |= op;
12832 // op: imm
12833 op = getVecShiftL16OpValue(MI, OpIdx: 2, Fixups, STI);
12834 op &= UINT64_C(15);
12835 op <<= 16;
12836 Value |= op;
12837 break;
12838 }
12839 case AArch64::SHLv2i32_shift:
12840 case AArch64::SHLv4i32_shift:
12841 case AArch64::SQSHLUs:
12842 case AArch64::SQSHLUv2i32_shift:
12843 case AArch64::SQSHLUv4i32_shift:
12844 case AArch64::SQSHLs:
12845 case AArch64::SQSHLv2i32_shift:
12846 case AArch64::SQSHLv4i32_shift:
12847 case AArch64::SSHLLv2i32_shift:
12848 case AArch64::SSHLLv4i32_shift:
12849 case AArch64::UQSHLs:
12850 case AArch64::UQSHLv2i32_shift:
12851 case AArch64::UQSHLv4i32_shift:
12852 case AArch64::USHLLv2i32_shift:
12853 case AArch64::USHLLv4i32_shift: {
12854 // op: Rd
12855 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12856 op &= UINT64_C(31);
12857 Value |= op;
12858 // op: Rn
12859 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12860 op &= UINT64_C(31);
12861 op <<= 5;
12862 Value |= op;
12863 // op: imm
12864 op = getVecShiftL32OpValue(MI, OpIdx: 2, Fixups, STI);
12865 op &= UINT64_C(31);
12866 op <<= 16;
12867 Value |= op;
12868 break;
12869 }
12870 case AArch64::SHLd:
12871 case AArch64::SHLv2i64_shift:
12872 case AArch64::SQSHLUd:
12873 case AArch64::SQSHLUv2i64_shift:
12874 case AArch64::SQSHLd:
12875 case AArch64::SQSHLv2i64_shift:
12876 case AArch64::UQSHLd:
12877 case AArch64::UQSHLv2i64_shift: {
12878 // op: Rd
12879 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12880 op &= UINT64_C(31);
12881 Value |= op;
12882 // op: Rn
12883 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12884 op &= UINT64_C(31);
12885 op <<= 5;
12886 Value |= op;
12887 // op: imm
12888 op = getVecShiftL64OpValue(MI, OpIdx: 2, Fixups, STI);
12889 op &= UINT64_C(63);
12890 op <<= 16;
12891 Value |= op;
12892 break;
12893 }
12894 case AArch64::SHLv8i8_shift:
12895 case AArch64::SHLv16i8_shift:
12896 case AArch64::SQSHLUb:
12897 case AArch64::SQSHLUv8i8_shift:
12898 case AArch64::SQSHLUv16i8_shift:
12899 case AArch64::SQSHLb:
12900 case AArch64::SQSHLv8i8_shift:
12901 case AArch64::SQSHLv16i8_shift:
12902 case AArch64::SSHLLv8i8_shift:
12903 case AArch64::SSHLLv16i8_shift:
12904 case AArch64::UQSHLb:
12905 case AArch64::UQSHLv8i8_shift:
12906 case AArch64::UQSHLv16i8_shift:
12907 case AArch64::USHLLv8i8_shift:
12908 case AArch64::USHLLv16i8_shift: {
12909 // op: Rd
12910 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12911 op &= UINT64_C(31);
12912 Value |= op;
12913 // op: Rn
12914 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12915 op &= UINT64_C(31);
12916 op <<= 5;
12917 Value |= op;
12918 // op: imm
12919 op = getVecShiftL8OpValue(MI, OpIdx: 2, Fixups, STI);
12920 op &= UINT64_C(7);
12921 op <<= 16;
12922 Value |= op;
12923 break;
12924 }
12925 case AArch64::FCVTZSh:
12926 case AArch64::FCVTZSv4i16_shift:
12927 case AArch64::FCVTZSv8i16_shift:
12928 case AArch64::FCVTZUh:
12929 case AArch64::FCVTZUv4i16_shift:
12930 case AArch64::FCVTZUv8i16_shift:
12931 case AArch64::SCVTFh:
12932 case AArch64::SCVTFv4i16_shift:
12933 case AArch64::SCVTFv8i16_shift:
12934 case AArch64::SQRSHRNh:
12935 case AArch64::SQRSHRUNh:
12936 case AArch64::SQSHRNh:
12937 case AArch64::SQSHRUNh:
12938 case AArch64::SRSHRv4i16_shift:
12939 case AArch64::SRSHRv8i16_shift:
12940 case AArch64::SSHRv4i16_shift:
12941 case AArch64::SSHRv8i16_shift:
12942 case AArch64::UCVTFh:
12943 case AArch64::UCVTFv4i16_shift:
12944 case AArch64::UCVTFv8i16_shift:
12945 case AArch64::UQRSHRNh:
12946 case AArch64::UQSHRNh:
12947 case AArch64::URSHRv4i16_shift:
12948 case AArch64::URSHRv8i16_shift:
12949 case AArch64::USHRv4i16_shift:
12950 case AArch64::USHRv8i16_shift: {
12951 // op: Rd
12952 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12953 op &= UINT64_C(31);
12954 Value |= op;
12955 // op: Rn
12956 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12957 op &= UINT64_C(31);
12958 op <<= 5;
12959 Value |= op;
12960 // op: imm
12961 op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI);
12962 op &= UINT64_C(15);
12963 op <<= 16;
12964 Value |= op;
12965 break;
12966 }
12967 case AArch64::RSHRNv8i8_shift:
12968 case AArch64::SHRNv8i8_shift:
12969 case AArch64::SQRSHRNv8i8_shift:
12970 case AArch64::SQRSHRUNv8i8_shift:
12971 case AArch64::SQSHRNv8i8_shift:
12972 case AArch64::SQSHRUNv8i8_shift:
12973 case AArch64::UQRSHRNv8i8_shift:
12974 case AArch64::UQSHRNv8i8_shift: {
12975 // op: Rd
12976 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
12977 op &= UINT64_C(31);
12978 Value |= op;
12979 // op: Rn
12980 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
12981 op &= UINT64_C(31);
12982 op <<= 5;
12983 Value |= op;
12984 // op: imm
12985 op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI);
12986 op &= UINT64_C(7);
12987 op <<= 16;
12988 Value |= op;
12989 break;
12990 }
12991 case AArch64::RSHRNv4i16_shift:
12992 case AArch64::SHRNv4i16_shift:
12993 case AArch64::SQRSHRNv4i16_shift:
12994 case AArch64::SQRSHRUNv4i16_shift:
12995 case AArch64::SQSHRNv4i16_shift:
12996 case AArch64::SQSHRUNv4i16_shift:
12997 case AArch64::UQRSHRNv4i16_shift:
12998 case AArch64::UQSHRNv4i16_shift: {
12999 // op: Rd
13000 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13001 op &= UINT64_C(31);
13002 Value |= op;
13003 // op: Rn
13004 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13005 op &= UINT64_C(31);
13006 op <<= 5;
13007 Value |= op;
13008 // op: imm
13009 op = getVecShiftR32OpValue(MI, OpIdx: 2, Fixups, STI);
13010 op &= UINT64_C(15);
13011 op <<= 16;
13012 Value |= op;
13013 break;
13014 }
13015 case AArch64::FCVTZSs:
13016 case AArch64::FCVTZSv2i32_shift:
13017 case AArch64::FCVTZSv4i32_shift:
13018 case AArch64::FCVTZUs:
13019 case AArch64::FCVTZUv2i32_shift:
13020 case AArch64::FCVTZUv4i32_shift:
13021 case AArch64::SCVTFs:
13022 case AArch64::SCVTFv2i32_shift:
13023 case AArch64::SCVTFv4i32_shift:
13024 case AArch64::SQRSHRNs:
13025 case AArch64::SQRSHRUNs:
13026 case AArch64::SQSHRNs:
13027 case AArch64::SQSHRUNs:
13028 case AArch64::SRSHRv2i32_shift:
13029 case AArch64::SRSHRv4i32_shift:
13030 case AArch64::SSHRv2i32_shift:
13031 case AArch64::SSHRv4i32_shift:
13032 case AArch64::UCVTFs:
13033 case AArch64::UCVTFv2i32_shift:
13034 case AArch64::UCVTFv4i32_shift:
13035 case AArch64::UQRSHRNs:
13036 case AArch64::UQSHRNs:
13037 case AArch64::URSHRv2i32_shift:
13038 case AArch64::URSHRv4i32_shift:
13039 case AArch64::USHRv2i32_shift:
13040 case AArch64::USHRv4i32_shift: {
13041 // op: Rd
13042 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13043 op &= UINT64_C(31);
13044 Value |= op;
13045 // op: Rn
13046 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13047 op &= UINT64_C(31);
13048 op <<= 5;
13049 Value |= op;
13050 // op: imm
13051 op = getVecShiftR32OpValue(MI, OpIdx: 2, Fixups, STI);
13052 op &= UINT64_C(31);
13053 op <<= 16;
13054 Value |= op;
13055 break;
13056 }
13057 case AArch64::RSHRNv2i32_shift:
13058 case AArch64::SHRNv2i32_shift:
13059 case AArch64::SQRSHRNv2i32_shift:
13060 case AArch64::SQRSHRUNv2i32_shift:
13061 case AArch64::SQSHRNv2i32_shift:
13062 case AArch64::SQSHRUNv2i32_shift:
13063 case AArch64::UQRSHRNv2i32_shift:
13064 case AArch64::UQSHRNv2i32_shift: {
13065 // op: Rd
13066 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13067 op &= UINT64_C(31);
13068 Value |= op;
13069 // op: Rn
13070 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13071 op &= UINT64_C(31);
13072 op <<= 5;
13073 Value |= op;
13074 // op: imm
13075 op = getVecShiftR64OpValue(MI, OpIdx: 2, Fixups, STI);
13076 op &= UINT64_C(31);
13077 op <<= 16;
13078 Value |= op;
13079 break;
13080 }
13081 case AArch64::FCVTZSd:
13082 case AArch64::FCVTZSv2i64_shift:
13083 case AArch64::FCVTZUd:
13084 case AArch64::FCVTZUv2i64_shift:
13085 case AArch64::SCVTFd:
13086 case AArch64::SCVTFv2i64_shift:
13087 case AArch64::SRSHRd:
13088 case AArch64::SRSHRv2i64_shift:
13089 case AArch64::SSHRd:
13090 case AArch64::SSHRv2i64_shift:
13091 case AArch64::UCVTFd:
13092 case AArch64::UCVTFv2i64_shift:
13093 case AArch64::URSHRd:
13094 case AArch64::URSHRv2i64_shift:
13095 case AArch64::USHRd:
13096 case AArch64::USHRv2i64_shift: {
13097 // op: Rd
13098 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13099 op &= UINT64_C(31);
13100 Value |= op;
13101 // op: Rn
13102 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13103 op &= UINT64_C(31);
13104 op <<= 5;
13105 Value |= op;
13106 // op: imm
13107 op = getVecShiftR64OpValue(MI, OpIdx: 2, Fixups, STI);
13108 op &= UINT64_C(63);
13109 op <<= 16;
13110 Value |= op;
13111 break;
13112 }
13113 case AArch64::SQRSHRNb:
13114 case AArch64::SQRSHRUNb:
13115 case AArch64::SQSHRNb:
13116 case AArch64::SQSHRUNb:
13117 case AArch64::SRSHRv8i8_shift:
13118 case AArch64::SRSHRv16i8_shift:
13119 case AArch64::SSHRv8i8_shift:
13120 case AArch64::SSHRv16i8_shift:
13121 case AArch64::UQRSHRNb:
13122 case AArch64::UQSHRNb:
13123 case AArch64::URSHRv8i8_shift:
13124 case AArch64::URSHRv16i8_shift:
13125 case AArch64::USHRv8i8_shift:
13126 case AArch64::USHRv16i8_shift: {
13127 // op: Rd
13128 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13129 op &= UINT64_C(31);
13130 Value |= op;
13131 // op: Rn
13132 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13133 op &= UINT64_C(31);
13134 op <<= 5;
13135 Value |= op;
13136 // op: imm
13137 op = getVecShiftR8OpValue(MI, OpIdx: 2, Fixups, STI);
13138 op &= UINT64_C(7);
13139 op <<= 16;
13140 Value |= op;
13141 break;
13142 }
13143 case AArch64::ADDG:
13144 case AArch64::SUBG: {
13145 // op: Rd
13146 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13147 op &= UINT64_C(31);
13148 Value |= op;
13149 // op: Rn
13150 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13151 op &= UINT64_C(31);
13152 op <<= 5;
13153 Value |= op;
13154 // op: imm6
13155 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13156 op &= UINT64_C(63);
13157 op <<= 16;
13158 Value |= op;
13159 // op: imm4
13160 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13161 op &= UINT64_C(15);
13162 op <<= 10;
13163 Value |= op;
13164 break;
13165 }
13166 case AArch64::SBFMWri:
13167 case AArch64::UBFMWri: {
13168 // op: Rd
13169 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13170 op &= UINT64_C(31);
13171 Value |= op;
13172 // op: Rn
13173 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13174 op &= UINT64_C(31);
13175 op <<= 5;
13176 Value |= op;
13177 // op: immr
13178 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13179 op &= UINT64_C(31);
13180 op <<= 16;
13181 Value |= op;
13182 // op: imms
13183 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13184 op &= UINT64_C(31);
13185 op <<= 10;
13186 Value |= op;
13187 break;
13188 }
13189 case AArch64::SBFMXri:
13190 case AArch64::UBFMXri: {
13191 // op: Rd
13192 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13193 op &= UINT64_C(31);
13194 Value |= op;
13195 // op: Rn
13196 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13197 op &= UINT64_C(31);
13198 op <<= 5;
13199 Value |= op;
13200 // op: immr
13201 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13202 op &= UINT64_C(63);
13203 op <<= 16;
13204 Value |= op;
13205 // op: imms
13206 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13207 op &= UINT64_C(63);
13208 op <<= 10;
13209 Value |= op;
13210 break;
13211 }
13212 case AArch64::FCVTZSSWDri:
13213 case AArch64::FCVTZSSWHri:
13214 case AArch64::FCVTZSSWSri:
13215 case AArch64::FCVTZUSWDri:
13216 case AArch64::FCVTZUSWHri:
13217 case AArch64::FCVTZUSWSri:
13218 case AArch64::SCVTFSWDri:
13219 case AArch64::SCVTFSWHri:
13220 case AArch64::SCVTFSWSri:
13221 case AArch64::UCVTFSWDri:
13222 case AArch64::UCVTFSWHri:
13223 case AArch64::UCVTFSWSri: {
13224 // op: Rd
13225 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13226 op &= UINT64_C(31);
13227 Value |= op;
13228 // op: Rn
13229 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13230 op &= UINT64_C(31);
13231 op <<= 5;
13232 Value |= op;
13233 // op: scale
13234 op = getFixedPointScaleOpValue(MI, OpIdx: 2, Fixups, STI);
13235 op &= UINT64_C(31);
13236 op <<= 10;
13237 Value |= op;
13238 break;
13239 }
13240 case AArch64::FCVTZSSXDri:
13241 case AArch64::FCVTZSSXHri:
13242 case AArch64::FCVTZSSXSri:
13243 case AArch64::FCVTZUSXDri:
13244 case AArch64::FCVTZUSXHri:
13245 case AArch64::FCVTZUSXSri:
13246 case AArch64::SCVTFSXDri:
13247 case AArch64::SCVTFSXHri:
13248 case AArch64::SCVTFSXSri:
13249 case AArch64::UCVTFSXDri:
13250 case AArch64::UCVTFSXHri:
13251 case AArch64::UCVTFSXSri: {
13252 // op: Rd
13253 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13254 op &= UINT64_C(31);
13255 Value |= op;
13256 // op: Rn
13257 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13258 op &= UINT64_C(31);
13259 op <<= 5;
13260 Value |= op;
13261 // op: scale
13262 op = getFixedPointScaleOpValue(MI, OpIdx: 2, Fixups, STI);
13263 op &= UINT64_C(63);
13264 op <<= 10;
13265 Value |= op;
13266 break;
13267 }
13268 case AArch64::BFMWri: {
13269 // op: Rd
13270 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13271 op &= UINT64_C(31);
13272 Value |= op;
13273 // op: Rn
13274 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13275 op &= UINT64_C(31);
13276 op <<= 5;
13277 Value |= op;
13278 // op: immr
13279 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13280 op &= UINT64_C(31);
13281 op <<= 16;
13282 Value |= op;
13283 // op: imms
13284 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
13285 op &= UINT64_C(31);
13286 op <<= 10;
13287 Value |= op;
13288 break;
13289 }
13290 case AArch64::BFMXri: {
13291 // op: Rd
13292 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13293 op &= UINT64_C(31);
13294 Value |= op;
13295 // op: Rn
13296 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13297 op &= UINT64_C(31);
13298 op <<= 5;
13299 Value |= op;
13300 // op: immr
13301 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13302 op &= UINT64_C(63);
13303 op <<= 16;
13304 Value |= op;
13305 // op: imms
13306 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
13307 op &= UINT64_C(63);
13308 op <<= 10;
13309 Value |= op;
13310 break;
13311 }
13312 case AArch64::FMOVDi:
13313 case AArch64::FMOVHi:
13314 case AArch64::FMOVSi: {
13315 // op: Rd
13316 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13317 op &= UINT64_C(31);
13318 Value |= op;
13319 // op: imm
13320 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13321 op &= UINT64_C(255);
13322 op <<= 13;
13323 Value |= op;
13324 break;
13325 }
13326 case AArch64::MOVNWi:
13327 case AArch64::MOVNXi: {
13328 // op: Rd
13329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13330 op &= UINT64_C(31);
13331 Value |= op;
13332 // op: imm
13333 op = getMoveWideImmOpValue(MI, OpIdx: 1, Fixups, STI);
13334 op &= UINT64_C(65535);
13335 op <<= 5;
13336 Value |= op;
13337 // op: shift
13338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13339 op &= UINT64_C(48);
13340 op <<= 17;
13341 Value |= op;
13342 break;
13343 }
13344 case AArch64::MOVZWi:
13345 case AArch64::MOVZXi: {
13346 // op: Rd
13347 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13348 op &= UINT64_C(31);
13349 Value |= op;
13350 // op: imm
13351 op = getMoveWideImmOpValue(MI, OpIdx: 1, Fixups, STI);
13352 op &= UINT64_C(65535);
13353 op <<= 5;
13354 Value |= op;
13355 // op: shift
13356 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13357 op &= UINT64_C(48);
13358 op <<= 17;
13359 Value |= op;
13360 Value = fixMOVZ(MI, EncodedValue: Value, STI);
13361 break;
13362 }
13363 case AArch64::MOVKWi:
13364 case AArch64::MOVKXi: {
13365 // op: Rd
13366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13367 op &= UINT64_C(31);
13368 Value |= op;
13369 // op: imm
13370 op = getMoveWideImmOpValue(MI, OpIdx: 2, Fixups, STI);
13371 op &= UINT64_C(65535);
13372 op <<= 5;
13373 Value |= op;
13374 // op: shift
13375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13376 op &= UINT64_C(48);
13377 op <<= 17;
13378 Value |= op;
13379 break;
13380 }
13381 case AArch64::CNTB_XPiI:
13382 case AArch64::CNTD_XPiI:
13383 case AArch64::CNTH_XPiI:
13384 case AArch64::CNTW_XPiI: {
13385 // op: Rd
13386 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13387 op &= UINT64_C(31);
13388 Value |= op;
13389 // op: imm4
13390 op = getSVEIncDecImm(MI, OpIdx: 2, Fixups, STI);
13391 op &= UINT64_C(15);
13392 op <<= 16;
13393 Value |= op;
13394 // op: pattern
13395 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13396 op &= UINT64_C(31);
13397 op <<= 5;
13398 Value |= op;
13399 break;
13400 }
13401 case AArch64::RDSVLI_XI:
13402 case AArch64::RDVLI_XI: {
13403 // op: Rd
13404 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13405 op &= UINT64_C(31);
13406 Value |= op;
13407 // op: imm6
13408 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13409 op &= UINT64_C(63);
13410 op <<= 5;
13411 Value |= op;
13412 break;
13413 }
13414 case AArch64::FMOVv2f32_ns:
13415 case AArch64::FMOVv2f64_ns:
13416 case AArch64::FMOVv4f16_ns:
13417 case AArch64::FMOVv4f32_ns:
13418 case AArch64::FMOVv8f16_ns:
13419 case AArch64::MOVID:
13420 case AArch64::MOVIv2d_ns:
13421 case AArch64::MOVIv8b_ns:
13422 case AArch64::MOVIv16b_ns: {
13423 // op: Rd
13424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13425 op &= UINT64_C(31);
13426 Value |= op;
13427 // op: imm8
13428 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13429 Value |= (op & UINT64_C(224)) << 11;
13430 Value |= (op & UINT64_C(31)) << 5;
13431 break;
13432 }
13433 case AArch64::MOVIv2s_msl:
13434 case AArch64::MOVIv4s_msl:
13435 case AArch64::MVNIv2s_msl:
13436 case AArch64::MVNIv4s_msl: {
13437 // op: Rd
13438 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13439 op &= UINT64_C(31);
13440 Value |= op;
13441 // op: imm8
13442 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13443 Value |= (op & UINT64_C(224)) << 11;
13444 Value |= (op & UINT64_C(31)) << 5;
13445 // op: shift
13446 op = getMoveVecShifterOpValue(MI, OpIdx: 2, Fixups, STI);
13447 op &= UINT64_C(1);
13448 op <<= 12;
13449 Value |= op;
13450 break;
13451 }
13452 case AArch64::MOVIv4i16:
13453 case AArch64::MOVIv8i16:
13454 case AArch64::MVNIv4i16:
13455 case AArch64::MVNIv8i16: {
13456 // op: Rd
13457 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13458 op &= UINT64_C(31);
13459 Value |= op;
13460 // op: imm8
13461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13462 Value |= (op & UINT64_C(224)) << 11;
13463 Value |= (op & UINT64_C(31)) << 5;
13464 // op: shift
13465 op = getVecShifterOpValue(MI, OpIdx: 2, Fixups, STI);
13466 op &= UINT64_C(1);
13467 op <<= 13;
13468 Value |= op;
13469 break;
13470 }
13471 case AArch64::MOVIv2i32:
13472 case AArch64::MOVIv4i32:
13473 case AArch64::MVNIv2i32:
13474 case AArch64::MVNIv4i32: {
13475 // op: Rd
13476 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
13477 op &= UINT64_C(31);
13478 Value |= op;
13479 // op: imm8
13480 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13481 Value |= (op & UINT64_C(224)) << 11;
13482 Value |= (op & UINT64_C(31)) << 5;
13483 // op: shift
13484 op = getVecShifterOpValue(MI, OpIdx: 2, Fixups, STI);
13485 op &= UINT64_C(3);
13486 op <<= 13;
13487 Value |= op;
13488 break;
13489 }
13490 case AArch64::AUTDZA:
13491 case AArch64::AUTDZB:
13492 case AArch64::AUTIZA:
13493 case AArch64::AUTIZB:
13494 case AArch64::PACDZA:
13495 case AArch64::PACDZB:
13496 case AArch64::PACIZA:
13497 case AArch64::PACIZB: {
13498 // op: Rd
13499 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13500 op &= UINT64_C(31);
13501 Value |= op;
13502 break;
13503 }
13504 case AArch64::AESDrr:
13505 case AArch64::AESErr:
13506 case AArch64::AUTDA:
13507 case AArch64::AUTDB:
13508 case AArch64::AUTIA:
13509 case AArch64::AUTIB:
13510 case AArch64::BFCVTN2:
13511 case AArch64::FCVTNv4i32:
13512 case AArch64::FCVTNv8i16:
13513 case AArch64::FCVTXNv4f32:
13514 case AArch64::PACDA:
13515 case AArch64::PACDB:
13516 case AArch64::PACIA:
13517 case AArch64::PACIB:
13518 case AArch64::SADALPv2i32_v1i64:
13519 case AArch64::SADALPv4i16_v2i32:
13520 case AArch64::SADALPv4i32_v2i64:
13521 case AArch64::SADALPv8i8_v4i16:
13522 case AArch64::SADALPv8i16_v4i32:
13523 case AArch64::SADALPv16i8_v8i16:
13524 case AArch64::SHA1SU1rr:
13525 case AArch64::SHA256SU0rr:
13526 case AArch64::SQXTNv4i32:
13527 case AArch64::SQXTNv8i16:
13528 case AArch64::SQXTNv16i8:
13529 case AArch64::SQXTUNv4i32:
13530 case AArch64::SQXTUNv8i16:
13531 case AArch64::SQXTUNv16i8:
13532 case AArch64::SUQADDv1i8:
13533 case AArch64::SUQADDv1i16:
13534 case AArch64::SUQADDv1i32:
13535 case AArch64::SUQADDv1i64:
13536 case AArch64::SUQADDv2i32:
13537 case AArch64::SUQADDv2i64:
13538 case AArch64::SUQADDv4i16:
13539 case AArch64::SUQADDv4i32:
13540 case AArch64::SUQADDv8i8:
13541 case AArch64::SUQADDv8i16:
13542 case AArch64::SUQADDv16i8:
13543 case AArch64::UADALPv2i32_v1i64:
13544 case AArch64::UADALPv4i16_v2i32:
13545 case AArch64::UADALPv4i32_v2i64:
13546 case AArch64::UADALPv8i8_v4i16:
13547 case AArch64::UADALPv8i16_v4i32:
13548 case AArch64::UADALPv16i8_v8i16:
13549 case AArch64::UQXTNv4i32:
13550 case AArch64::UQXTNv8i16:
13551 case AArch64::UQXTNv16i8:
13552 case AArch64::USQADDv1i8:
13553 case AArch64::USQADDv1i16:
13554 case AArch64::USQADDv1i32:
13555 case AArch64::USQADDv1i64:
13556 case AArch64::USQADDv2i32:
13557 case AArch64::USQADDv2i64:
13558 case AArch64::USQADDv4i16:
13559 case AArch64::USQADDv4i32:
13560 case AArch64::USQADDv8i8:
13561 case AArch64::USQADDv8i16:
13562 case AArch64::USQADDv16i8:
13563 case AArch64::XTNv4i32:
13564 case AArch64::XTNv8i16:
13565 case AArch64::XTNv16i8: {
13566 // op: Rd
13567 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13568 op &= UINT64_C(31);
13569 Value |= op;
13570 // op: Rn
13571 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13572 op &= UINT64_C(31);
13573 op <<= 5;
13574 Value |= op;
13575 break;
13576 }
13577 case AArch64::BFMLALBIdx:
13578 case AArch64::BFMLALTIdx:
13579 case AArch64::FDOTlanev4f16:
13580 case AArch64::FDOTlanev8f16:
13581 case AArch64::FMLAL2lanev4f16:
13582 case AArch64::FMLAL2lanev8f16:
13583 case AArch64::FMLALlanev4f16:
13584 case AArch64::FMLALlanev8f16:
13585 case AArch64::FMLAv1i16_indexed:
13586 case AArch64::FMLAv4i16_indexed:
13587 case AArch64::FMLAv8i16_indexed:
13588 case AArch64::FMLSL2lanev4f16:
13589 case AArch64::FMLSL2lanev8f16:
13590 case AArch64::FMLSLlanev4f16:
13591 case AArch64::FMLSLlanev8f16:
13592 case AArch64::FMLSv1i16_indexed:
13593 case AArch64::FMLSv4i16_indexed:
13594 case AArch64::FMLSv8i16_indexed:
13595 case AArch64::MLAv4i16_indexed:
13596 case AArch64::MLAv8i16_indexed:
13597 case AArch64::MLSv4i16_indexed:
13598 case AArch64::MLSv8i16_indexed:
13599 case AArch64::SMLALv4i16_indexed:
13600 case AArch64::SMLALv8i16_indexed:
13601 case AArch64::SMLSLv4i16_indexed:
13602 case AArch64::SMLSLv8i16_indexed:
13603 case AArch64::SQDMLALv1i32_indexed:
13604 case AArch64::SQDMLALv4i16_indexed:
13605 case AArch64::SQDMLALv8i16_indexed:
13606 case AArch64::SQDMLSLv1i32_indexed:
13607 case AArch64::SQDMLSLv4i16_indexed:
13608 case AArch64::SQDMLSLv8i16_indexed:
13609 case AArch64::SQRDMLAHv1i16_indexed:
13610 case AArch64::SQRDMLAHv4i16_indexed:
13611 case AArch64::SQRDMLAHv8i16_indexed:
13612 case AArch64::SQRDMLSHv1i16_indexed:
13613 case AArch64::SQRDMLSHv4i16_indexed:
13614 case AArch64::SQRDMLSHv8i16_indexed:
13615 case AArch64::UMLALv4i16_indexed:
13616 case AArch64::UMLALv8i16_indexed:
13617 case AArch64::UMLSLv4i16_indexed:
13618 case AArch64::UMLSLv8i16_indexed: {
13619 // op: Rd
13620 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13621 op &= UINT64_C(31);
13622 Value |= op;
13623 // op: Rn
13624 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13625 op &= UINT64_C(31);
13626 op <<= 5;
13627 Value |= op;
13628 // op: Rm
13629 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13630 op &= UINT64_C(15);
13631 op <<= 16;
13632 Value |= op;
13633 // op: idx
13634 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
13635 Value |= (op & UINT64_C(3)) << 20;
13636 Value |= (op & UINT64_C(4)) << 9;
13637 break;
13638 }
13639 case AArch64::ADDHNv2i64_v4i32:
13640 case AArch64::ADDHNv4i32_v8i16:
13641 case AArch64::ADDHNv8i16_v16i8:
13642 case AArch64::BFDOTv4bf16:
13643 case AArch64::BFDOTv8bf16:
13644 case AArch64::BFMLALB:
13645 case AArch64::BFMLALT:
13646 case AArch64::BFMMLA:
13647 case AArch64::BIFv8i8:
13648 case AArch64::BIFv16i8:
13649 case AArch64::BITv8i8:
13650 case AArch64::BITv16i8:
13651 case AArch64::BSLv8i8:
13652 case AArch64::BSLv16i8:
13653 case AArch64::FCVTN_F32_F82v16f8:
13654 case AArch64::FDOTv2f32:
13655 case AArch64::FDOTv4f16:
13656 case AArch64::FDOTv4f32:
13657 case AArch64::FDOTv8f16:
13658 case AArch64::FMLAL2v4f16:
13659 case AArch64::FMLAL2v8f16:
13660 case AArch64::FMLALBv8f16:
13661 case AArch64::FMLALLBBv4f32:
13662 case AArch64::FMLALLBTv4f32:
13663 case AArch64::FMLALLTBv4f32:
13664 case AArch64::FMLALLTTv4f32:
13665 case AArch64::FMLALTv8f16:
13666 case AArch64::FMLALv4f16:
13667 case AArch64::FMLALv8f16:
13668 case AArch64::FMLAv2f32:
13669 case AArch64::FMLAv2f64:
13670 case AArch64::FMLAv4f16:
13671 case AArch64::FMLAv4f32:
13672 case AArch64::FMLAv8f16:
13673 case AArch64::FMLSL2v4f16:
13674 case AArch64::FMLSL2v8f16:
13675 case AArch64::FMLSLv4f16:
13676 case AArch64::FMLSLv8f16:
13677 case AArch64::FMLSv2f32:
13678 case AArch64::FMLSv2f64:
13679 case AArch64::FMLSv4f16:
13680 case AArch64::FMLSv4f32:
13681 case AArch64::FMLSv8f16:
13682 case AArch64::MLAv2i32:
13683 case AArch64::MLAv4i16:
13684 case AArch64::MLAv4i32:
13685 case AArch64::MLAv8i8:
13686 case AArch64::MLAv8i16:
13687 case AArch64::MLAv16i8:
13688 case AArch64::MLSv2i32:
13689 case AArch64::MLSv4i16:
13690 case AArch64::MLSv4i32:
13691 case AArch64::MLSv8i8:
13692 case AArch64::MLSv8i16:
13693 case AArch64::MLSv16i8:
13694 case AArch64::RADDHNv2i64_v4i32:
13695 case AArch64::RADDHNv4i32_v8i16:
13696 case AArch64::RADDHNv8i16_v16i8:
13697 case AArch64::RSUBHNv2i64_v4i32:
13698 case AArch64::RSUBHNv4i32_v8i16:
13699 case AArch64::RSUBHNv8i16_v16i8:
13700 case AArch64::SABALv2i32_v2i64:
13701 case AArch64::SABALv4i16_v4i32:
13702 case AArch64::SABALv4i32_v2i64:
13703 case AArch64::SABALv8i8_v8i16:
13704 case AArch64::SABALv8i16_v4i32:
13705 case AArch64::SABALv16i8_v8i16:
13706 case AArch64::SABAv2i32:
13707 case AArch64::SABAv4i16:
13708 case AArch64::SABAv4i32:
13709 case AArch64::SABAv8i8:
13710 case AArch64::SABAv8i16:
13711 case AArch64::SABAv16i8:
13712 case AArch64::SDOTv8i8:
13713 case AArch64::SDOTv16i8:
13714 case AArch64::SHA1Crrr:
13715 case AArch64::SHA1Mrrr:
13716 case AArch64::SHA1Prrr:
13717 case AArch64::SHA1SU0rrr:
13718 case AArch64::SHA256H2rrr:
13719 case AArch64::SHA256Hrrr:
13720 case AArch64::SHA256SU1rrr:
13721 case AArch64::SMLALv2i32_v2i64:
13722 case AArch64::SMLALv4i16_v4i32:
13723 case AArch64::SMLALv4i32_v2i64:
13724 case AArch64::SMLALv8i8_v8i16:
13725 case AArch64::SMLALv8i16_v4i32:
13726 case AArch64::SMLALv16i8_v8i16:
13727 case AArch64::SMLSLv2i32_v2i64:
13728 case AArch64::SMLSLv4i16_v4i32:
13729 case AArch64::SMLSLv4i32_v2i64:
13730 case AArch64::SMLSLv8i8_v8i16:
13731 case AArch64::SMLSLv8i16_v4i32:
13732 case AArch64::SMLSLv16i8_v8i16:
13733 case AArch64::SMMLA:
13734 case AArch64::SQDMLALi16:
13735 case AArch64::SQDMLALi32:
13736 case AArch64::SQDMLALv2i32_v2i64:
13737 case AArch64::SQDMLALv4i16_v4i32:
13738 case AArch64::SQDMLALv4i32_v2i64:
13739 case AArch64::SQDMLALv8i16_v4i32:
13740 case AArch64::SQDMLSLi16:
13741 case AArch64::SQDMLSLi32:
13742 case AArch64::SQDMLSLv2i32_v2i64:
13743 case AArch64::SQDMLSLv4i16_v4i32:
13744 case AArch64::SQDMLSLv4i32_v2i64:
13745 case AArch64::SQDMLSLv8i16_v4i32:
13746 case AArch64::SQRDMLAHv1i16:
13747 case AArch64::SQRDMLAHv1i32:
13748 case AArch64::SQRDMLAHv2i32:
13749 case AArch64::SQRDMLAHv4i16:
13750 case AArch64::SQRDMLAHv4i32:
13751 case AArch64::SQRDMLAHv8i16:
13752 case AArch64::SQRDMLSHv1i16:
13753 case AArch64::SQRDMLSHv1i32:
13754 case AArch64::SQRDMLSHv2i32:
13755 case AArch64::SQRDMLSHv4i16:
13756 case AArch64::SQRDMLSHv4i32:
13757 case AArch64::SQRDMLSHv8i16:
13758 case AArch64::SUBHNv2i64_v4i32:
13759 case AArch64::SUBHNv4i32_v8i16:
13760 case AArch64::SUBHNv8i16_v16i8:
13761 case AArch64::UABALv2i32_v2i64:
13762 case AArch64::UABALv4i16_v4i32:
13763 case AArch64::UABALv4i32_v2i64:
13764 case AArch64::UABALv8i8_v8i16:
13765 case AArch64::UABALv8i16_v4i32:
13766 case AArch64::UABALv16i8_v8i16:
13767 case AArch64::UABAv2i32:
13768 case AArch64::UABAv4i16:
13769 case AArch64::UABAv4i32:
13770 case AArch64::UABAv8i8:
13771 case AArch64::UABAv8i16:
13772 case AArch64::UABAv16i8:
13773 case AArch64::UDOTv8i8:
13774 case AArch64::UDOTv16i8:
13775 case AArch64::UMLALv2i32_v2i64:
13776 case AArch64::UMLALv4i16_v4i32:
13777 case AArch64::UMLALv4i32_v2i64:
13778 case AArch64::UMLALv8i8_v8i16:
13779 case AArch64::UMLALv8i16_v4i32:
13780 case AArch64::UMLALv16i8_v8i16:
13781 case AArch64::UMLSLv2i32_v2i64:
13782 case AArch64::UMLSLv4i16_v4i32:
13783 case AArch64::UMLSLv4i32_v2i64:
13784 case AArch64::UMLSLv8i8_v8i16:
13785 case AArch64::UMLSLv8i16_v4i32:
13786 case AArch64::UMLSLv16i8_v8i16:
13787 case AArch64::UMMLA:
13788 case AArch64::USDOTv8i8:
13789 case AArch64::USDOTv16i8:
13790 case AArch64::USMMLA: {
13791 // op: Rd
13792 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13793 op &= UINT64_C(31);
13794 Value |= op;
13795 // op: Rn
13796 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13797 op &= UINT64_C(31);
13798 op <<= 5;
13799 Value |= op;
13800 // op: Rm
13801 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13802 op &= UINT64_C(31);
13803 op <<= 16;
13804 Value |= op;
13805 break;
13806 }
13807 case AArch64::BF16DOTlanev4bf16:
13808 case AArch64::BF16DOTlanev8bf16:
13809 case AArch64::FDOTlanev8f8:
13810 case AArch64::FDOTlanev16f8:
13811 case AArch64::FMLAv1i32_indexed:
13812 case AArch64::FMLAv2i32_indexed:
13813 case AArch64::FMLAv4i32_indexed:
13814 case AArch64::FMLSv1i32_indexed:
13815 case AArch64::FMLSv2i32_indexed:
13816 case AArch64::FMLSv4i32_indexed:
13817 case AArch64::MLAv2i32_indexed:
13818 case AArch64::MLAv4i32_indexed:
13819 case AArch64::MLSv2i32_indexed:
13820 case AArch64::MLSv4i32_indexed:
13821 case AArch64::SDOTlanev8i8:
13822 case AArch64::SDOTlanev16i8:
13823 case AArch64::SMLALv2i32_indexed:
13824 case AArch64::SMLALv4i32_indexed:
13825 case AArch64::SMLSLv2i32_indexed:
13826 case AArch64::SMLSLv4i32_indexed:
13827 case AArch64::SQDMLALv1i64_indexed:
13828 case AArch64::SQDMLALv2i32_indexed:
13829 case AArch64::SQDMLALv4i32_indexed:
13830 case AArch64::SQDMLSLv1i64_indexed:
13831 case AArch64::SQDMLSLv2i32_indexed:
13832 case AArch64::SQDMLSLv4i32_indexed:
13833 case AArch64::SQRDMLAHv1i32_indexed:
13834 case AArch64::SQRDMLAHv2i32_indexed:
13835 case AArch64::SQRDMLAHv4i32_indexed:
13836 case AArch64::SQRDMLSHv1i32_indexed:
13837 case AArch64::SQRDMLSHv2i32_indexed:
13838 case AArch64::SQRDMLSHv4i32_indexed:
13839 case AArch64::SUDOTlanev8i8:
13840 case AArch64::SUDOTlanev16i8:
13841 case AArch64::UDOTlanev8i8:
13842 case AArch64::UDOTlanev16i8:
13843 case AArch64::UMLALv2i32_indexed:
13844 case AArch64::UMLALv4i32_indexed:
13845 case AArch64::UMLSLv2i32_indexed:
13846 case AArch64::UMLSLv4i32_indexed:
13847 case AArch64::USDOTlanev8i8:
13848 case AArch64::USDOTlanev16i8: {
13849 // op: Rd
13850 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13851 op &= UINT64_C(31);
13852 Value |= op;
13853 // op: Rn
13854 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13855 op &= UINT64_C(31);
13856 op <<= 5;
13857 Value |= op;
13858 // op: Rm
13859 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13860 op &= UINT64_C(31);
13861 op <<= 16;
13862 Value |= op;
13863 // op: idx
13864 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
13865 Value |= (op & UINT64_C(1)) << 21;
13866 Value |= (op & UINT64_C(2)) << 10;
13867 break;
13868 }
13869 case AArch64::FMLAv1i64_indexed:
13870 case AArch64::FMLAv2i64_indexed:
13871 case AArch64::FMLSv1i64_indexed:
13872 case AArch64::FMLSv2i64_indexed: {
13873 // op: Rd
13874 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13875 op &= UINT64_C(31);
13876 Value |= op;
13877 // op: Rn
13878 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13879 op &= UINT64_C(31);
13880 op <<= 5;
13881 Value |= op;
13882 // op: Rm
13883 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13884 op &= UINT64_C(31);
13885 op <<= 16;
13886 Value |= op;
13887 // op: idx
13888 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
13889 op &= UINT64_C(1);
13890 op <<= 11;
13891 Value |= op;
13892 break;
13893 }
13894 case AArch64::FCMLAv2f32:
13895 case AArch64::FCMLAv2f64:
13896 case AArch64::FCMLAv4f16:
13897 case AArch64::FCMLAv4f32:
13898 case AArch64::FCMLAv8f16: {
13899 // op: Rd
13900 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13901 op &= UINT64_C(31);
13902 Value |= op;
13903 // op: Rn
13904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13905 op &= UINT64_C(31);
13906 op <<= 5;
13907 Value |= op;
13908 // op: Rm
13909 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13910 op &= UINT64_C(31);
13911 op <<= 16;
13912 Value |= op;
13913 // op: rot
13914 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
13915 op &= UINT64_C(3);
13916 op <<= 11;
13917 Value |= op;
13918 break;
13919 }
13920 case AArch64::FCMLAv8f16_indexed: {
13921 // op: Rd
13922 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13923 op &= UINT64_C(31);
13924 Value |= op;
13925 // op: Rn
13926 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13927 op &= UINT64_C(31);
13928 op <<= 5;
13929 Value |= op;
13930 // op: Rm
13931 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13932 op &= UINT64_C(31);
13933 op <<= 16;
13934 Value |= op;
13935 // op: rot
13936 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
13937 op &= UINT64_C(3);
13938 op <<= 13;
13939 Value |= op;
13940 // op: idx
13941 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
13942 Value |= (op & UINT64_C(1)) << 21;
13943 Value |= (op & UINT64_C(2)) << 10;
13944 break;
13945 }
13946 case AArch64::FCMLAv4f32_indexed: {
13947 // op: Rd
13948 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13949 op &= UINT64_C(31);
13950 Value |= op;
13951 // op: Rn
13952 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13953 op &= UINT64_C(31);
13954 op <<= 5;
13955 Value |= op;
13956 // op: Rm
13957 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13958 op &= UINT64_C(31);
13959 op <<= 16;
13960 Value |= op;
13961 // op: rot
13962 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
13963 op &= UINT64_C(3);
13964 op <<= 13;
13965 Value |= op;
13966 // op: idx
13967 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
13968 op &= UINT64_C(1);
13969 op <<= 11;
13970 Value |= op;
13971 break;
13972 }
13973 case AArch64::FCMLAv4f16_indexed: {
13974 // op: Rd
13975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
13976 op &= UINT64_C(31);
13977 Value |= op;
13978 // op: Rn
13979 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
13980 op &= UINT64_C(31);
13981 op <<= 5;
13982 Value |= op;
13983 // op: Rm
13984 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
13985 op &= UINT64_C(31);
13986 op <<= 16;
13987 Value |= op;
13988 // op: rot
13989 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
13990 op &= UINT64_C(3);
13991 op <<= 13;
13992 Value |= op;
13993 // op: idx
13994 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
13995 op &= UINT64_C(1);
13996 op <<= 21;
13997 Value |= op;
13998 break;
13999 }
14000 case AArch64::FMLALBlanev8f16:
14001 case AArch64::FMLALLBBlanev4f32:
14002 case AArch64::FMLALLBTlanev4f32:
14003 case AArch64::FMLALLTBlanev4f32:
14004 case AArch64::FMLALLTTlanev4f32:
14005 case AArch64::FMLALTlanev8f16: {
14006 // op: Rd
14007 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14008 op &= UINT64_C(31);
14009 Value |= op;
14010 // op: Rn
14011 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14012 op &= UINT64_C(31);
14013 op <<= 5;
14014 Value |= op;
14015 // op: Rm
14016 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14017 op &= UINT64_C(7);
14018 op <<= 16;
14019 Value |= op;
14020 // op: idx
14021 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14022 Value |= (op & UINT64_C(7)) << 19;
14023 Value |= (op & UINT64_C(8)) << 8;
14024 break;
14025 }
14026 case AArch64::SLIv4i16_shift:
14027 case AArch64::SLIv8i16_shift: {
14028 // op: Rd
14029 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14030 op &= UINT64_C(31);
14031 Value |= op;
14032 // op: Rn
14033 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14034 op &= UINT64_C(31);
14035 op <<= 5;
14036 Value |= op;
14037 // op: imm
14038 op = getVecShiftL16OpValue(MI, OpIdx: 3, Fixups, STI);
14039 op &= UINT64_C(15);
14040 op <<= 16;
14041 Value |= op;
14042 break;
14043 }
14044 case AArch64::SLIv2i32_shift:
14045 case AArch64::SLIv4i32_shift: {
14046 // op: Rd
14047 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14048 op &= UINT64_C(31);
14049 Value |= op;
14050 // op: Rn
14051 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14052 op &= UINT64_C(31);
14053 op <<= 5;
14054 Value |= op;
14055 // op: imm
14056 op = getVecShiftL32OpValue(MI, OpIdx: 3, Fixups, STI);
14057 op &= UINT64_C(31);
14058 op <<= 16;
14059 Value |= op;
14060 break;
14061 }
14062 case AArch64::SLId:
14063 case AArch64::SLIv2i64_shift: {
14064 // op: Rd
14065 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14066 op &= UINT64_C(31);
14067 Value |= op;
14068 // op: Rn
14069 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14070 op &= UINT64_C(31);
14071 op <<= 5;
14072 Value |= op;
14073 // op: imm
14074 op = getVecShiftL64OpValue(MI, OpIdx: 3, Fixups, STI);
14075 op &= UINT64_C(63);
14076 op <<= 16;
14077 Value |= op;
14078 break;
14079 }
14080 case AArch64::SLIv8i8_shift:
14081 case AArch64::SLIv16i8_shift: {
14082 // op: Rd
14083 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14084 op &= UINT64_C(31);
14085 Value |= op;
14086 // op: Rn
14087 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14088 op &= UINT64_C(31);
14089 op <<= 5;
14090 Value |= op;
14091 // op: imm
14092 op = getVecShiftL8OpValue(MI, OpIdx: 3, Fixups, STI);
14093 op &= UINT64_C(7);
14094 op <<= 16;
14095 Value |= op;
14096 break;
14097 }
14098 case AArch64::SRIv4i16_shift:
14099 case AArch64::SRIv8i16_shift:
14100 case AArch64::SRSRAv4i16_shift:
14101 case AArch64::SRSRAv8i16_shift:
14102 case AArch64::SSRAv4i16_shift:
14103 case AArch64::SSRAv8i16_shift:
14104 case AArch64::URSRAv4i16_shift:
14105 case AArch64::URSRAv8i16_shift:
14106 case AArch64::USRAv4i16_shift:
14107 case AArch64::USRAv8i16_shift: {
14108 // op: Rd
14109 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14110 op &= UINT64_C(31);
14111 Value |= op;
14112 // op: Rn
14113 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14114 op &= UINT64_C(31);
14115 op <<= 5;
14116 Value |= op;
14117 // op: imm
14118 op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI);
14119 op &= UINT64_C(15);
14120 op <<= 16;
14121 Value |= op;
14122 break;
14123 }
14124 case AArch64::RSHRNv16i8_shift:
14125 case AArch64::SHRNv16i8_shift:
14126 case AArch64::SQRSHRNv16i8_shift:
14127 case AArch64::SQRSHRUNv16i8_shift:
14128 case AArch64::SQSHRNv16i8_shift:
14129 case AArch64::SQSHRUNv16i8_shift:
14130 case AArch64::UQRSHRNv16i8_shift:
14131 case AArch64::UQSHRNv16i8_shift: {
14132 // op: Rd
14133 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14134 op &= UINT64_C(31);
14135 Value |= op;
14136 // op: Rn
14137 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14138 op &= UINT64_C(31);
14139 op <<= 5;
14140 Value |= op;
14141 // op: imm
14142 op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI);
14143 op &= UINT64_C(7);
14144 op <<= 16;
14145 Value |= op;
14146 break;
14147 }
14148 case AArch64::RSHRNv8i16_shift:
14149 case AArch64::SHRNv8i16_shift:
14150 case AArch64::SQRSHRNv8i16_shift:
14151 case AArch64::SQRSHRUNv8i16_shift:
14152 case AArch64::SQSHRNv8i16_shift:
14153 case AArch64::SQSHRUNv8i16_shift:
14154 case AArch64::UQRSHRNv8i16_shift:
14155 case AArch64::UQSHRNv8i16_shift: {
14156 // op: Rd
14157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14158 op &= UINT64_C(31);
14159 Value |= op;
14160 // op: Rn
14161 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14162 op &= UINT64_C(31);
14163 op <<= 5;
14164 Value |= op;
14165 // op: imm
14166 op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI);
14167 op &= UINT64_C(15);
14168 op <<= 16;
14169 Value |= op;
14170 break;
14171 }
14172 case AArch64::SRIv2i32_shift:
14173 case AArch64::SRIv4i32_shift:
14174 case AArch64::SRSRAv2i32_shift:
14175 case AArch64::SRSRAv4i32_shift:
14176 case AArch64::SSRAv2i32_shift:
14177 case AArch64::SSRAv4i32_shift:
14178 case AArch64::URSRAv2i32_shift:
14179 case AArch64::URSRAv4i32_shift:
14180 case AArch64::USRAv2i32_shift:
14181 case AArch64::USRAv4i32_shift: {
14182 // op: Rd
14183 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14184 op &= UINT64_C(31);
14185 Value |= op;
14186 // op: Rn
14187 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14188 op &= UINT64_C(31);
14189 op <<= 5;
14190 Value |= op;
14191 // op: imm
14192 op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI);
14193 op &= UINT64_C(31);
14194 op <<= 16;
14195 Value |= op;
14196 break;
14197 }
14198 case AArch64::RSHRNv4i32_shift:
14199 case AArch64::SHRNv4i32_shift:
14200 case AArch64::SQRSHRNv4i32_shift:
14201 case AArch64::SQRSHRUNv4i32_shift:
14202 case AArch64::SQSHRNv4i32_shift:
14203 case AArch64::SQSHRUNv4i32_shift:
14204 case AArch64::UQRSHRNv4i32_shift:
14205 case AArch64::UQSHRNv4i32_shift: {
14206 // op: Rd
14207 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14208 op &= UINT64_C(31);
14209 Value |= op;
14210 // op: Rn
14211 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14212 op &= UINT64_C(31);
14213 op <<= 5;
14214 Value |= op;
14215 // op: imm
14216 op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI);
14217 op &= UINT64_C(31);
14218 op <<= 16;
14219 Value |= op;
14220 break;
14221 }
14222 case AArch64::SRId:
14223 case AArch64::SRIv2i64_shift:
14224 case AArch64::SRSRAd:
14225 case AArch64::SRSRAv2i64_shift:
14226 case AArch64::SSRAd:
14227 case AArch64::SSRAv2i64_shift:
14228 case AArch64::URSRAd:
14229 case AArch64::URSRAv2i64_shift:
14230 case AArch64::USRAd:
14231 case AArch64::USRAv2i64_shift: {
14232 // op: Rd
14233 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14234 op &= UINT64_C(31);
14235 Value |= op;
14236 // op: Rn
14237 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14238 op &= UINT64_C(31);
14239 op <<= 5;
14240 Value |= op;
14241 // op: imm
14242 op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI);
14243 op &= UINT64_C(63);
14244 op <<= 16;
14245 Value |= op;
14246 break;
14247 }
14248 case AArch64::SRIv8i8_shift:
14249 case AArch64::SRIv16i8_shift:
14250 case AArch64::SRSRAv8i8_shift:
14251 case AArch64::SRSRAv16i8_shift:
14252 case AArch64::SSRAv8i8_shift:
14253 case AArch64::SSRAv16i8_shift:
14254 case AArch64::URSRAv8i8_shift:
14255 case AArch64::URSRAv16i8_shift:
14256 case AArch64::USRAv8i8_shift:
14257 case AArch64::USRAv16i8_shift: {
14258 // op: Rd
14259 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14260 op &= UINT64_C(31);
14261 Value |= op;
14262 // op: Rn
14263 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14264 op &= UINT64_C(31);
14265 op <<= 5;
14266 Value |= op;
14267 // op: imm
14268 op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI);
14269 op &= UINT64_C(7);
14270 op <<= 16;
14271 Value |= op;
14272 break;
14273 }
14274 case AArch64::INSvi64gpr: {
14275 // op: Rd
14276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14277 op &= UINT64_C(31);
14278 Value |= op;
14279 // op: Rn
14280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14281 op &= UINT64_C(31);
14282 op <<= 5;
14283 Value |= op;
14284 // op: idx
14285 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14286 op &= UINT64_C(1);
14287 op <<= 20;
14288 Value |= op;
14289 break;
14290 }
14291 case AArch64::INSvi64lane: {
14292 // op: Rd
14293 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14294 op &= UINT64_C(31);
14295 Value |= op;
14296 // op: Rn
14297 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14298 op &= UINT64_C(31);
14299 op <<= 5;
14300 Value |= op;
14301 // op: idx
14302 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14303 op &= UINT64_C(1);
14304 op <<= 20;
14305 Value |= op;
14306 // op: idx2
14307 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14308 op &= UINT64_C(1);
14309 op <<= 14;
14310 Value |= op;
14311 break;
14312 }
14313 case AArch64::INSvi8gpr: {
14314 // op: Rd
14315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14316 op &= UINT64_C(31);
14317 Value |= op;
14318 // op: Rn
14319 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14320 op &= UINT64_C(31);
14321 op <<= 5;
14322 Value |= op;
14323 // op: idx
14324 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14325 op &= UINT64_C(15);
14326 op <<= 17;
14327 Value |= op;
14328 break;
14329 }
14330 case AArch64::INSvi8lane: {
14331 // op: Rd
14332 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14333 op &= UINT64_C(31);
14334 Value |= op;
14335 // op: Rn
14336 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14337 op &= UINT64_C(31);
14338 op <<= 5;
14339 Value |= op;
14340 // op: idx
14341 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14342 op &= UINT64_C(15);
14343 op <<= 17;
14344 Value |= op;
14345 // op: idx2
14346 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14347 op &= UINT64_C(15);
14348 op <<= 11;
14349 Value |= op;
14350 break;
14351 }
14352 case AArch64::INSvi32gpr: {
14353 // op: Rd
14354 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14355 op &= UINT64_C(31);
14356 Value |= op;
14357 // op: Rn
14358 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14359 op &= UINT64_C(31);
14360 op <<= 5;
14361 Value |= op;
14362 // op: idx
14363 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14364 op &= UINT64_C(3);
14365 op <<= 19;
14366 Value |= op;
14367 break;
14368 }
14369 case AArch64::INSvi32lane: {
14370 // op: Rd
14371 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14372 op &= UINT64_C(31);
14373 Value |= op;
14374 // op: Rn
14375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14376 op &= UINT64_C(31);
14377 op <<= 5;
14378 Value |= op;
14379 // op: idx
14380 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14381 op &= UINT64_C(3);
14382 op <<= 19;
14383 Value |= op;
14384 // op: idx2
14385 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14386 op &= UINT64_C(3);
14387 op <<= 13;
14388 Value |= op;
14389 break;
14390 }
14391 case AArch64::INSvi16gpr: {
14392 // op: Rd
14393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14394 op &= UINT64_C(31);
14395 Value |= op;
14396 // op: Rn
14397 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14398 op &= UINT64_C(31);
14399 op <<= 5;
14400 Value |= op;
14401 // op: idx
14402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14403 op &= UINT64_C(7);
14404 op <<= 18;
14405 Value |= op;
14406 break;
14407 }
14408 case AArch64::INSvi16lane: {
14409 // op: Rd
14410 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14411 op &= UINT64_C(31);
14412 Value |= op;
14413 // op: Rn
14414 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14415 op &= UINT64_C(31);
14416 op <<= 5;
14417 Value |= op;
14418 // op: idx
14419 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14420 op &= UINT64_C(7);
14421 op <<= 18;
14422 Value |= op;
14423 // op: idx2
14424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14425 op &= UINT64_C(7);
14426 op <<= 12;
14427 Value |= op;
14428 break;
14429 }
14430 case AArch64::BICv4i16:
14431 case AArch64::BICv8i16:
14432 case AArch64::ORRv4i16:
14433 case AArch64::ORRv8i16: {
14434 // op: Rd
14435 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14436 op &= UINT64_C(31);
14437 Value |= op;
14438 // op: imm8
14439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14440 Value |= (op & UINT64_C(224)) << 11;
14441 Value |= (op & UINT64_C(31)) << 5;
14442 // op: shift
14443 op = getVecShifterOpValue(MI, OpIdx: 3, Fixups, STI);
14444 op &= UINT64_C(1);
14445 op <<= 13;
14446 Value |= op;
14447 break;
14448 }
14449 case AArch64::BICv2i32:
14450 case AArch64::BICv4i32:
14451 case AArch64::ORRv2i32:
14452 case AArch64::ORRv4i32: {
14453 // op: Rd
14454 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14455 op &= UINT64_C(31);
14456 Value |= op;
14457 // op: imm8
14458 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14459 Value |= (op & UINT64_C(224)) << 11;
14460 Value |= (op & UINT64_C(31)) << 5;
14461 // op: shift
14462 op = getVecShifterOpValue(MI, OpIdx: 3, Fixups, STI);
14463 op &= UINT64_C(3);
14464 op <<= 13;
14465 Value |= op;
14466 break;
14467 }
14468 case AArch64::MOPSSETGE:
14469 case AArch64::MOPSSETGEN:
14470 case AArch64::MOPSSETGET:
14471 case AArch64::MOPSSETGETN:
14472 case AArch64::SETE:
14473 case AArch64::SETEN:
14474 case AArch64::SETET:
14475 case AArch64::SETETN:
14476 case AArch64::SETGM:
14477 case AArch64::SETGMN:
14478 case AArch64::SETGMT:
14479 case AArch64::SETGMTN:
14480 case AArch64::SETGP:
14481 case AArch64::SETGPN:
14482 case AArch64::SETGPT:
14483 case AArch64::SETGPTN:
14484 case AArch64::SETM:
14485 case AArch64::SETMN:
14486 case AArch64::SETMT:
14487 case AArch64::SETMTN:
14488 case AArch64::SETP:
14489 case AArch64::SETPN:
14490 case AArch64::SETPT:
14491 case AArch64::SETPTN: {
14492 // op: Rd
14493 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14494 op &= UINT64_C(31);
14495 Value |= op;
14496 // op: Rn
14497 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14498 op &= UINT64_C(31);
14499 op <<= 5;
14500 Value |= op;
14501 // op: Rm
14502 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14503 op &= UINT64_C(31);
14504 op <<= 16;
14505 Value |= op;
14506 break;
14507 }
14508 case AArch64::CPYE:
14509 case AArch64::CPYEN:
14510 case AArch64::CPYERN:
14511 case AArch64::CPYERT:
14512 case AArch64::CPYERTN:
14513 case AArch64::CPYERTRN:
14514 case AArch64::CPYERTWN:
14515 case AArch64::CPYET:
14516 case AArch64::CPYETN:
14517 case AArch64::CPYETRN:
14518 case AArch64::CPYETWN:
14519 case AArch64::CPYEWN:
14520 case AArch64::CPYEWT:
14521 case AArch64::CPYEWTN:
14522 case AArch64::CPYEWTRN:
14523 case AArch64::CPYEWTWN:
14524 case AArch64::CPYFE:
14525 case AArch64::CPYFEN:
14526 case AArch64::CPYFERN:
14527 case AArch64::CPYFERT:
14528 case AArch64::CPYFERTN:
14529 case AArch64::CPYFERTRN:
14530 case AArch64::CPYFERTWN:
14531 case AArch64::CPYFET:
14532 case AArch64::CPYFETN:
14533 case AArch64::CPYFETRN:
14534 case AArch64::CPYFETWN:
14535 case AArch64::CPYFEWN:
14536 case AArch64::CPYFEWT:
14537 case AArch64::CPYFEWTN:
14538 case AArch64::CPYFEWTRN:
14539 case AArch64::CPYFEWTWN:
14540 case AArch64::CPYFM:
14541 case AArch64::CPYFMN:
14542 case AArch64::CPYFMRN:
14543 case AArch64::CPYFMRT:
14544 case AArch64::CPYFMRTN:
14545 case AArch64::CPYFMRTRN:
14546 case AArch64::CPYFMRTWN:
14547 case AArch64::CPYFMT:
14548 case AArch64::CPYFMTN:
14549 case AArch64::CPYFMTRN:
14550 case AArch64::CPYFMTWN:
14551 case AArch64::CPYFMWN:
14552 case AArch64::CPYFMWT:
14553 case AArch64::CPYFMWTN:
14554 case AArch64::CPYFMWTRN:
14555 case AArch64::CPYFMWTWN:
14556 case AArch64::CPYFP:
14557 case AArch64::CPYFPN:
14558 case AArch64::CPYFPRN:
14559 case AArch64::CPYFPRT:
14560 case AArch64::CPYFPRTN:
14561 case AArch64::CPYFPRTRN:
14562 case AArch64::CPYFPRTWN:
14563 case AArch64::CPYFPT:
14564 case AArch64::CPYFPTN:
14565 case AArch64::CPYFPTRN:
14566 case AArch64::CPYFPTWN:
14567 case AArch64::CPYFPWN:
14568 case AArch64::CPYFPWT:
14569 case AArch64::CPYFPWTN:
14570 case AArch64::CPYFPWTRN:
14571 case AArch64::CPYFPWTWN:
14572 case AArch64::CPYM:
14573 case AArch64::CPYMN:
14574 case AArch64::CPYMRN:
14575 case AArch64::CPYMRT:
14576 case AArch64::CPYMRTN:
14577 case AArch64::CPYMRTRN:
14578 case AArch64::CPYMRTWN:
14579 case AArch64::CPYMT:
14580 case AArch64::CPYMTN:
14581 case AArch64::CPYMTRN:
14582 case AArch64::CPYMTWN:
14583 case AArch64::CPYMWN:
14584 case AArch64::CPYMWT:
14585 case AArch64::CPYMWTN:
14586 case AArch64::CPYMWTRN:
14587 case AArch64::CPYMWTWN:
14588 case AArch64::CPYP:
14589 case AArch64::CPYPN:
14590 case AArch64::CPYPRN:
14591 case AArch64::CPYPRT:
14592 case AArch64::CPYPRTN:
14593 case AArch64::CPYPRTRN:
14594 case AArch64::CPYPRTWN:
14595 case AArch64::CPYPT:
14596 case AArch64::CPYPTN:
14597 case AArch64::CPYPTRN:
14598 case AArch64::CPYPTWN:
14599 case AArch64::CPYPWN:
14600 case AArch64::CPYPWT:
14601 case AArch64::CPYPWTN:
14602 case AArch64::CPYPWTRN:
14603 case AArch64::CPYPWTWN: {
14604 // op: Rd
14605 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14606 op &= UINT64_C(31);
14607 Value |= op;
14608 // op: Rs
14609 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14610 op &= UINT64_C(31);
14611 op <<= 16;
14612 Value |= op;
14613 // op: Rn
14614 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
14615 op &= UINT64_C(31);
14616 op <<= 5;
14617 Value |= op;
14618 break;
14619 }
14620 case AArch64::DECP_XP_B:
14621 case AArch64::DECP_XP_D:
14622 case AArch64::DECP_XP_H:
14623 case AArch64::DECP_XP_S:
14624 case AArch64::INCP_XP_B:
14625 case AArch64::INCP_XP_D:
14626 case AArch64::INCP_XP_H:
14627 case AArch64::INCP_XP_S:
14628 case AArch64::SQDECP_XPWd_B:
14629 case AArch64::SQDECP_XPWd_D:
14630 case AArch64::SQDECP_XPWd_H:
14631 case AArch64::SQDECP_XPWd_S:
14632 case AArch64::SQDECP_XP_B:
14633 case AArch64::SQDECP_XP_D:
14634 case AArch64::SQDECP_XP_H:
14635 case AArch64::SQDECP_XP_S:
14636 case AArch64::SQINCP_XPWd_B:
14637 case AArch64::SQINCP_XPWd_D:
14638 case AArch64::SQINCP_XPWd_H:
14639 case AArch64::SQINCP_XPWd_S:
14640 case AArch64::SQINCP_XP_B:
14641 case AArch64::SQINCP_XP_D:
14642 case AArch64::SQINCP_XP_H:
14643 case AArch64::SQINCP_XP_S:
14644 case AArch64::UQDECP_WP_B:
14645 case AArch64::UQDECP_WP_D:
14646 case AArch64::UQDECP_WP_H:
14647 case AArch64::UQDECP_WP_S:
14648 case AArch64::UQDECP_XP_B:
14649 case AArch64::UQDECP_XP_D:
14650 case AArch64::UQDECP_XP_H:
14651 case AArch64::UQDECP_XP_S:
14652 case AArch64::UQINCP_WP_B:
14653 case AArch64::UQINCP_WP_D:
14654 case AArch64::UQINCP_WP_H:
14655 case AArch64::UQINCP_WP_S:
14656 case AArch64::UQINCP_XP_B:
14657 case AArch64::UQINCP_XP_D:
14658 case AArch64::UQINCP_XP_H:
14659 case AArch64::UQINCP_XP_S: {
14660 // op: Rdn
14661 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14662 op &= UINT64_C(31);
14663 Value |= op;
14664 // op: Pg
14665 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14666 op &= UINT64_C(15);
14667 op <<= 5;
14668 Value |= op;
14669 break;
14670 }
14671 case AArch64::DECB_XPiI:
14672 case AArch64::DECD_XPiI:
14673 case AArch64::DECH_XPiI:
14674 case AArch64::DECW_XPiI:
14675 case AArch64::INCB_XPiI:
14676 case AArch64::INCD_XPiI:
14677 case AArch64::INCH_XPiI:
14678 case AArch64::INCW_XPiI:
14679 case AArch64::SQDECB_XPiI:
14680 case AArch64::SQDECB_XPiWdI:
14681 case AArch64::SQDECD_XPiI:
14682 case AArch64::SQDECD_XPiWdI:
14683 case AArch64::SQDECH_XPiI:
14684 case AArch64::SQDECH_XPiWdI:
14685 case AArch64::SQDECW_XPiI:
14686 case AArch64::SQDECW_XPiWdI:
14687 case AArch64::SQINCB_XPiI:
14688 case AArch64::SQINCB_XPiWdI:
14689 case AArch64::SQINCD_XPiI:
14690 case AArch64::SQINCD_XPiWdI:
14691 case AArch64::SQINCH_XPiI:
14692 case AArch64::SQINCH_XPiWdI:
14693 case AArch64::SQINCW_XPiI:
14694 case AArch64::SQINCW_XPiWdI:
14695 case AArch64::UQDECB_WPiI:
14696 case AArch64::UQDECB_XPiI:
14697 case AArch64::UQDECD_WPiI:
14698 case AArch64::UQDECD_XPiI:
14699 case AArch64::UQDECH_WPiI:
14700 case AArch64::UQDECH_XPiI:
14701 case AArch64::UQDECW_WPiI:
14702 case AArch64::UQDECW_XPiI:
14703 case AArch64::UQINCB_WPiI:
14704 case AArch64::UQINCB_XPiI:
14705 case AArch64::UQINCD_WPiI:
14706 case AArch64::UQINCD_XPiI:
14707 case AArch64::UQINCH_WPiI:
14708 case AArch64::UQINCH_XPiI:
14709 case AArch64::UQINCW_WPiI:
14710 case AArch64::UQINCW_XPiI: {
14711 // op: Rdn
14712 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14713 op &= UINT64_C(31);
14714 Value |= op;
14715 // op: pattern
14716 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14717 op &= UINT64_C(31);
14718 op <<= 5;
14719 Value |= op;
14720 // op: imm4
14721 op = getSVEIncDecImm(MI, OpIdx: 3, Fixups, STI);
14722 op &= UINT64_C(15);
14723 op <<= 16;
14724 Value |= op;
14725 break;
14726 }
14727 case AArch64::RETAASPPCr:
14728 case AArch64::RETABSPPCr: {
14729 // op: Rm
14730 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14731 op &= UINT64_C(31);
14732 Value |= op;
14733 break;
14734 }
14735 case AArch64::CTERMEQ_WW:
14736 case AArch64::CTERMEQ_XX:
14737 case AArch64::CTERMNE_WW:
14738 case AArch64::CTERMNE_XX:
14739 case AArch64::FCMPDrr:
14740 case AArch64::FCMPEDrr:
14741 case AArch64::FCMPEHrr:
14742 case AArch64::FCMPESrr:
14743 case AArch64::FCMPHrr:
14744 case AArch64::FCMPSrr: {
14745 // op: Rm
14746 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14747 op &= UINT64_C(31);
14748 op <<= 16;
14749 Value |= op;
14750 // op: Rn
14751 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14752 op &= UINT64_C(31);
14753 op <<= 5;
14754 Value |= op;
14755 break;
14756 }
14757 case AArch64::INDEX_IR_B:
14758 case AArch64::INDEX_IR_D:
14759 case AArch64::INDEX_IR_H:
14760 case AArch64::INDEX_IR_S: {
14761 // op: Rm
14762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14763 op &= UINT64_C(31);
14764 op <<= 16;
14765 Value |= op;
14766 // op: Zd
14767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14768 op &= UINT64_C(31);
14769 Value |= op;
14770 // op: imm5
14771 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14772 op &= UINT64_C(31);
14773 op <<= 5;
14774 Value |= op;
14775 break;
14776 }
14777 case AArch64::INSR_ZR_B:
14778 case AArch64::INSR_ZR_D:
14779 case AArch64::INSR_ZR_H:
14780 case AArch64::INSR_ZR_S: {
14781 // op: Rm
14782 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14783 op &= UINT64_C(31);
14784 op <<= 5;
14785 Value |= op;
14786 // op: Zdn
14787 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14788 op &= UINT64_C(31);
14789 Value |= op;
14790 break;
14791 }
14792 case AArch64::LD1B_2Z_STRIDED:
14793 case AArch64::LD1D_2Z_STRIDED:
14794 case AArch64::LD1H_2Z_STRIDED:
14795 case AArch64::LD1W_2Z_STRIDED:
14796 case AArch64::LDNT1B_2Z_STRIDED:
14797 case AArch64::LDNT1D_2Z_STRIDED:
14798 case AArch64::LDNT1H_2Z_STRIDED:
14799 case AArch64::LDNT1W_2Z_STRIDED:
14800 case AArch64::ST1B_2Z_STRIDED:
14801 case AArch64::ST1D_2Z_STRIDED:
14802 case AArch64::ST1H_2Z_STRIDED:
14803 case AArch64::ST1W_2Z_STRIDED:
14804 case AArch64::STNT1B_2Z_STRIDED:
14805 case AArch64::STNT1D_2Z_STRIDED:
14806 case AArch64::STNT1H_2Z_STRIDED:
14807 case AArch64::STNT1W_2Z_STRIDED: {
14808 // op: Rm
14809 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14810 op &= UINT64_C(31);
14811 op <<= 16;
14812 Value |= op;
14813 // op: PNg
14814 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
14815 op &= UINT64_C(7);
14816 op <<= 10;
14817 Value |= op;
14818 // op: Rn
14819 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14820 op &= UINT64_C(31);
14821 op <<= 5;
14822 Value |= op;
14823 // op: Zt
14824 op = EncodeZPR2StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
14825 Value |= (op & UINT64_C(8)) << 1;
14826 Value |= (op & UINT64_C(7));
14827 break;
14828 }
14829 case AArch64::LD1B_4Z_STRIDED:
14830 case AArch64::LD1D_4Z_STRIDED:
14831 case AArch64::LD1H_4Z_STRIDED:
14832 case AArch64::LD1W_4Z_STRIDED:
14833 case AArch64::LDNT1B_4Z_STRIDED:
14834 case AArch64::LDNT1D_4Z_STRIDED:
14835 case AArch64::LDNT1H_4Z_STRIDED:
14836 case AArch64::LDNT1W_4Z_STRIDED:
14837 case AArch64::ST1B_4Z_STRIDED:
14838 case AArch64::ST1D_4Z_STRIDED:
14839 case AArch64::ST1H_4Z_STRIDED:
14840 case AArch64::ST1W_4Z_STRIDED:
14841 case AArch64::STNT1B_4Z_STRIDED:
14842 case AArch64::STNT1D_4Z_STRIDED:
14843 case AArch64::STNT1H_4Z_STRIDED:
14844 case AArch64::STNT1W_4Z_STRIDED: {
14845 // op: Rm
14846 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14847 op &= UINT64_C(31);
14848 op <<= 16;
14849 Value |= op;
14850 // op: PNg
14851 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
14852 op &= UINT64_C(7);
14853 op <<= 10;
14854 Value |= op;
14855 // op: Rn
14856 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14857 op &= UINT64_C(31);
14858 op <<= 5;
14859 Value |= op;
14860 // op: Zt
14861 op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
14862 Value |= (op & UINT64_C(4)) << 2;
14863 Value |= (op & UINT64_C(3));
14864 break;
14865 }
14866 case AArch64::PRFB_PRR:
14867 case AArch64::PRFD_PRR:
14868 case AArch64::PRFH_PRR:
14869 case AArch64::PRFW_PRR: {
14870 // op: Rm
14871 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14872 op &= UINT64_C(31);
14873 op <<= 16;
14874 Value |= op;
14875 // op: Rn
14876 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14877 op &= UINT64_C(31);
14878 op <<= 5;
14879 Value |= op;
14880 // op: Pg
14881 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
14882 op &= UINT64_C(7);
14883 op <<= 10;
14884 Value |= op;
14885 // op: prfop
14886 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14887 op &= UINT64_C(15);
14888 Value |= op;
14889 break;
14890 }
14891 case AArch64::LD1_MXIPXX_H_H:
14892 case AArch64::LD1_MXIPXX_V_H:
14893 case AArch64::ST1_MXIPXX_H_H:
14894 case AArch64::ST1_MXIPXX_V_H: {
14895 // op: Rm
14896 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
14897 op &= UINT64_C(31);
14898 op <<= 16;
14899 Value |= op;
14900 // op: Rv
14901 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI);
14902 op &= UINT64_C(3);
14903 op <<= 13;
14904 Value |= op;
14905 // op: Pg
14906 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14907 op &= UINT64_C(7);
14908 op <<= 10;
14909 Value |= op;
14910 // op: Rn
14911 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14912 op &= UINT64_C(31);
14913 op <<= 5;
14914 Value |= op;
14915 // op: ZAt
14916 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14917 op &= UINT64_C(1);
14918 op <<= 3;
14919 Value |= op;
14920 // op: imm
14921 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14922 op &= UINT64_C(7);
14923 Value |= op;
14924 break;
14925 }
14926 case AArch64::LD1_MXIPXX_H_Q:
14927 case AArch64::LD1_MXIPXX_V_Q:
14928 case AArch64::ST1_MXIPXX_H_Q:
14929 case AArch64::ST1_MXIPXX_V_Q: {
14930 // op: Rm
14931 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
14932 op &= UINT64_C(31);
14933 op <<= 16;
14934 Value |= op;
14935 // op: Rv
14936 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI);
14937 op &= UINT64_C(3);
14938 op <<= 13;
14939 Value |= op;
14940 // op: Pg
14941 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14942 op &= UINT64_C(7);
14943 op <<= 10;
14944 Value |= op;
14945 // op: Rn
14946 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14947 op &= UINT64_C(31);
14948 op <<= 5;
14949 Value |= op;
14950 // op: ZAt
14951 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14952 op &= UINT64_C(15);
14953 Value |= op;
14954 break;
14955 }
14956 case AArch64::LD1_MXIPXX_H_S:
14957 case AArch64::LD1_MXIPXX_V_S:
14958 case AArch64::ST1_MXIPXX_H_S:
14959 case AArch64::ST1_MXIPXX_V_S: {
14960 // op: Rm
14961 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
14962 op &= UINT64_C(31);
14963 op <<= 16;
14964 Value |= op;
14965 // op: Rv
14966 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI);
14967 op &= UINT64_C(3);
14968 op <<= 13;
14969 Value |= op;
14970 // op: Pg
14971 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
14972 op &= UINT64_C(7);
14973 op <<= 10;
14974 Value |= op;
14975 // op: Rn
14976 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
14977 op &= UINT64_C(31);
14978 op <<= 5;
14979 Value |= op;
14980 // op: ZAt
14981 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
14982 op &= UINT64_C(3);
14983 op <<= 2;
14984 Value |= op;
14985 // op: imm
14986 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
14987 op &= UINT64_C(3);
14988 Value |= op;
14989 break;
14990 }
14991 case AArch64::LD1_MXIPXX_H_D:
14992 case AArch64::LD1_MXIPXX_V_D:
14993 case AArch64::ST1_MXIPXX_H_D:
14994 case AArch64::ST1_MXIPXX_V_D: {
14995 // op: Rm
14996 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
14997 op &= UINT64_C(31);
14998 op <<= 16;
14999 Value |= op;
15000 // op: Rv
15001 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI);
15002 op &= UINT64_C(3);
15003 op <<= 13;
15004 Value |= op;
15005 // op: Pg
15006 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15007 op &= UINT64_C(7);
15008 op <<= 10;
15009 Value |= op;
15010 // op: Rn
15011 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15012 op &= UINT64_C(31);
15013 op <<= 5;
15014 Value |= op;
15015 // op: ZAt
15016 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15017 op &= UINT64_C(7);
15018 op <<= 1;
15019 Value |= op;
15020 // op: imm
15021 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15022 op &= UINT64_C(1);
15023 Value |= op;
15024 break;
15025 }
15026 case AArch64::LD1_MXIPXX_H_B:
15027 case AArch64::LD1_MXIPXX_V_B:
15028 case AArch64::ST1_MXIPXX_H_B:
15029 case AArch64::ST1_MXIPXX_V_B: {
15030 // op: Rm
15031 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
15032 op &= UINT64_C(31);
15033 op <<= 16;
15034 Value |= op;
15035 // op: Rv
15036 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI);
15037 op &= UINT64_C(3);
15038 op <<= 13;
15039 Value |= op;
15040 // op: Pg
15041 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15042 op &= UINT64_C(7);
15043 op <<= 10;
15044 Value |= op;
15045 // op: Rn
15046 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15047 op &= UINT64_C(31);
15048 op <<= 5;
15049 Value |= op;
15050 // op: imm
15051 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15052 op &= UINT64_C(15);
15053 Value |= op;
15054 break;
15055 }
15056 case AArch64::AUTIASPPCr:
15057 case AArch64::AUTIBSPPCr:
15058 case AArch64::BLR:
15059 case AArch64::BLRAAZ:
15060 case AArch64::BLRABZ:
15061 case AArch64::BR:
15062 case AArch64::BRAAZ:
15063 case AArch64::BRABZ:
15064 case AArch64::RET:
15065 case AArch64::SETF8:
15066 case AArch64::SETF16: {
15067 // op: Rn
15068 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15069 op &= UINT64_C(31);
15070 op <<= 5;
15071 Value |= op;
15072 break;
15073 }
15074 case AArch64::BLRAA:
15075 case AArch64::BLRAB:
15076 case AArch64::BRAA:
15077 case AArch64::BRAB: {
15078 // op: Rn
15079 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15080 op &= UINT64_C(31);
15081 op <<= 5;
15082 Value |= op;
15083 // op: Rm
15084 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15085 op &= UINT64_C(31);
15086 Value |= op;
15087 break;
15088 }
15089 case AArch64::CCMNWr:
15090 case AArch64::CCMNXr:
15091 case AArch64::CCMPWr:
15092 case AArch64::CCMPXr:
15093 case AArch64::FCCMPDrr:
15094 case AArch64::FCCMPEDrr:
15095 case AArch64::FCCMPEHrr:
15096 case AArch64::FCCMPESrr:
15097 case AArch64::FCCMPHrr:
15098 case AArch64::FCCMPSrr: {
15099 // op: Rn
15100 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15101 op &= UINT64_C(31);
15102 op <<= 5;
15103 Value |= op;
15104 // op: Rm
15105 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15106 op &= UINT64_C(31);
15107 op <<= 16;
15108 Value |= op;
15109 // op: nzcv
15110 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15111 op &= UINT64_C(15);
15112 Value |= op;
15113 // op: cond
15114 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15115 op &= UINT64_C(15);
15116 op <<= 12;
15117 Value |= op;
15118 break;
15119 }
15120 case AArch64::CCMNWi:
15121 case AArch64::CCMNXi:
15122 case AArch64::CCMPWi:
15123 case AArch64::CCMPXi: {
15124 // op: Rn
15125 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15126 op &= UINT64_C(31);
15127 op <<= 5;
15128 Value |= op;
15129 // op: imm
15130 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15131 op &= UINT64_C(31);
15132 op <<= 16;
15133 Value |= op;
15134 // op: nzcv
15135 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15136 op &= UINT64_C(15);
15137 Value |= op;
15138 // op: cond
15139 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15140 op &= UINT64_C(15);
15141 op <<= 12;
15142 Value |= op;
15143 break;
15144 }
15145 case AArch64::RMIF: {
15146 // op: Rn
15147 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15148 op &= UINT64_C(31);
15149 op <<= 5;
15150 Value |= op;
15151 // op: imm
15152 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15153 op &= UINT64_C(63);
15154 op <<= 15;
15155 Value |= op;
15156 // op: mask
15157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15158 op &= UINT64_C(15);
15159 Value |= op;
15160 break;
15161 }
15162 case AArch64::FCMPDri:
15163 case AArch64::FCMPEDri:
15164 case AArch64::FCMPEHri:
15165 case AArch64::FCMPESri:
15166 case AArch64::FCMPHri:
15167 case AArch64::FCMPSri: {
15168 // op: Rn
15169 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15170 op &= UINT64_C(31);
15171 op <<= 5;
15172 Value |= op;
15173 Value = fixOneOperandFPComparison(MI, EncodedValue: Value, STI);
15174 break;
15175 }
15176 case AArch64::LDR_TX:
15177 case AArch64::STR_TX: {
15178 // op: Rn
15179 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15180 op &= UINT64_C(31);
15181 op <<= 5;
15182 Value |= op;
15183 break;
15184 }
15185 case AArch64::LDAPRB:
15186 case AArch64::LDAPRH:
15187 case AArch64::LDAPRW:
15188 case AArch64::LDAPRX:
15189 case AArch64::LDGM:
15190 case AArch64::STGM:
15191 case AArch64::STZGM: {
15192 // op: Rn
15193 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15194 op &= UINT64_C(31);
15195 op <<= 5;
15196 Value |= op;
15197 // op: Rt
15198 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15199 op &= UINT64_C(31);
15200 Value |= op;
15201 break;
15202 }
15203 case AArch64::ST2Gi:
15204 case AArch64::STGi:
15205 case AArch64::STZ2Gi:
15206 case AArch64::STZGi: {
15207 // op: Rn
15208 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15209 op &= UINT64_C(31);
15210 op <<= 5;
15211 Value |= op;
15212 // op: Rt
15213 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15214 op &= UINT64_C(31);
15215 Value |= op;
15216 // op: offset
15217 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15218 op &= UINT64_C(511);
15219 op <<= 12;
15220 Value |= op;
15221 break;
15222 }
15223 case AArch64::DUP_ZR_B:
15224 case AArch64::DUP_ZR_D:
15225 case AArch64::DUP_ZR_H:
15226 case AArch64::DUP_ZR_S: {
15227 // op: Rn
15228 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15229 op &= UINT64_C(31);
15230 op <<= 5;
15231 Value |= op;
15232 // op: Zd
15233 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15234 op &= UINT64_C(31);
15235 Value |= op;
15236 break;
15237 }
15238 case AArch64::INDEX_RI_B:
15239 case AArch64::INDEX_RI_D:
15240 case AArch64::INDEX_RI_H:
15241 case AArch64::INDEX_RI_S: {
15242 // op: Rn
15243 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15244 op &= UINT64_C(31);
15245 op <<= 5;
15246 Value |= op;
15247 // op: Zd
15248 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15249 op &= UINT64_C(31);
15250 Value |= op;
15251 // op: imm5
15252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15253 op &= UINT64_C(31);
15254 op <<= 16;
15255 Value |= op;
15256 break;
15257 }
15258 case AArch64::LDR_ZXI:
15259 case AArch64::STR_ZXI: {
15260 // op: Rn
15261 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15262 op &= UINT64_C(31);
15263 op <<= 5;
15264 Value |= op;
15265 // op: Zt
15266 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15267 op &= UINT64_C(31);
15268 Value |= op;
15269 // op: imm9
15270 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15271 Value |= (op & UINT64_C(504)) << 13;
15272 Value |= (op & UINT64_C(7)) << 10;
15273 break;
15274 }
15275 case AArch64::PRFB_PRI:
15276 case AArch64::PRFD_PRI:
15277 case AArch64::PRFH_PRI:
15278 case AArch64::PRFW_PRI: {
15279 // op: Rn
15280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15281 op &= UINT64_C(31);
15282 op <<= 5;
15283 Value |= op;
15284 // op: Pg
15285 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15286 op &= UINT64_C(7);
15287 op <<= 10;
15288 Value |= op;
15289 // op: imm6
15290 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15291 op &= UINT64_C(63);
15292 op <<= 16;
15293 Value |= op;
15294 // op: prfop
15295 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15296 op &= UINT64_C(15);
15297 Value |= op;
15298 break;
15299 }
15300 case AArch64::LDG:
15301 case AArch64::ST2GPostIndex:
15302 case AArch64::ST2GPreIndex:
15303 case AArch64::STGPostIndex:
15304 case AArch64::STGPreIndex:
15305 case AArch64::STZ2GPostIndex:
15306 case AArch64::STZ2GPreIndex:
15307 case AArch64::STZGPostIndex:
15308 case AArch64::STZGPreIndex: {
15309 // op: Rn
15310 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15311 op &= UINT64_C(31);
15312 op <<= 5;
15313 Value |= op;
15314 // op: Rt
15315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15316 op &= UINT64_C(31);
15317 Value |= op;
15318 // op: offset
15319 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15320 op &= UINT64_C(511);
15321 op <<= 12;
15322 Value |= op;
15323 break;
15324 }
15325 case AArch64::MOVA_MXI2Z_H_H:
15326 case AArch64::MOVA_MXI2Z_V_H: {
15327 // op: Rs
15328 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
15329 op &= UINT64_C(3);
15330 op <<= 13;
15331 Value |= op;
15332 // op: Zn
15333 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
15334 op &= UINT64_C(15);
15335 op <<= 6;
15336 Value |= op;
15337 // op: ZAd
15338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15339 op &= UINT64_C(1);
15340 op <<= 2;
15341 Value |= op;
15342 // op: imm
15343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15344 op &= UINT64_C(3);
15345 Value |= op;
15346 break;
15347 }
15348 case AArch64::MOVA_MXI2Z_H_S:
15349 case AArch64::MOVA_MXI2Z_V_S: {
15350 // op: Rs
15351 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
15352 op &= UINT64_C(3);
15353 op <<= 13;
15354 Value |= op;
15355 // op: Zn
15356 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
15357 op &= UINT64_C(15);
15358 op <<= 6;
15359 Value |= op;
15360 // op: ZAd
15361 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15362 op &= UINT64_C(3);
15363 op <<= 1;
15364 Value |= op;
15365 // op: imm
15366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15367 op &= UINT64_C(1);
15368 Value |= op;
15369 break;
15370 }
15371 case AArch64::MOVA_MXI2Z_H_D:
15372 case AArch64::MOVA_MXI2Z_V_D: {
15373 // op: Rs
15374 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
15375 op &= UINT64_C(3);
15376 op <<= 13;
15377 Value |= op;
15378 // op: Zn
15379 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
15380 op &= UINT64_C(15);
15381 op <<= 6;
15382 Value |= op;
15383 // op: ZAd
15384 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15385 op &= UINT64_C(7);
15386 Value |= op;
15387 break;
15388 }
15389 case AArch64::MOVA_MXI2Z_H_B:
15390 case AArch64::MOVA_MXI2Z_V_B: {
15391 // op: Rs
15392 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
15393 op &= UINT64_C(3);
15394 op <<= 13;
15395 Value |= op;
15396 // op: Zn
15397 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
15398 op &= UINT64_C(15);
15399 op <<= 6;
15400 Value |= op;
15401 // op: imm
15402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15403 op &= UINT64_C(7);
15404 Value |= op;
15405 break;
15406 }
15407 case AArch64::MOVA_MXI4Z_H_H:
15408 case AArch64::MOVA_MXI4Z_V_H: {
15409 // op: Rs
15410 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
15411 op &= UINT64_C(3);
15412 op <<= 13;
15413 Value |= op;
15414 // op: Zn
15415 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
15416 op &= UINT64_C(7);
15417 op <<= 7;
15418 Value |= op;
15419 // op: ZAd
15420 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15421 op &= UINT64_C(1);
15422 op <<= 1;
15423 Value |= op;
15424 // op: imm
15425 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15426 op &= UINT64_C(1);
15427 Value |= op;
15428 break;
15429 }
15430 case AArch64::MOVA_MXI4Z_H_S:
15431 case AArch64::MOVA_MXI4Z_V_S: {
15432 // op: Rs
15433 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
15434 op &= UINT64_C(3);
15435 op <<= 13;
15436 Value |= op;
15437 // op: Zn
15438 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
15439 op &= UINT64_C(7);
15440 op <<= 7;
15441 Value |= op;
15442 // op: ZAd
15443 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15444 op &= UINT64_C(3);
15445 Value |= op;
15446 break;
15447 }
15448 case AArch64::MOVA_MXI4Z_H_D:
15449 case AArch64::MOVA_MXI4Z_V_D: {
15450 // op: Rs
15451 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
15452 op &= UINT64_C(3);
15453 op <<= 13;
15454 Value |= op;
15455 // op: Zn
15456 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
15457 op &= UINT64_C(7);
15458 op <<= 7;
15459 Value |= op;
15460 // op: ZAd
15461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15462 op &= UINT64_C(7);
15463 Value |= op;
15464 break;
15465 }
15466 case AArch64::MOVA_MXI4Z_H_B:
15467 case AArch64::MOVA_MXI4Z_V_B: {
15468 // op: Rs
15469 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
15470 op &= UINT64_C(3);
15471 op <<= 13;
15472 Value |= op;
15473 // op: Zn
15474 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
15475 op &= UINT64_C(7);
15476 op <<= 7;
15477 Value |= op;
15478 // op: imm
15479 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15480 op &= UINT64_C(3);
15481 Value |= op;
15482 break;
15483 }
15484 case AArch64::MOVAZ_ZMI_H_H:
15485 case AArch64::MOVAZ_ZMI_V_H: {
15486 // op: Rs
15487 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
15488 op &= UINT64_C(3);
15489 op <<= 13;
15490 Value |= op;
15491 // op: Zd
15492 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15493 op &= UINT64_C(31);
15494 Value |= op;
15495 // op: ZAn
15496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15497 op &= UINT64_C(1);
15498 op <<= 8;
15499 Value |= op;
15500 // op: imm
15501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15502 op &= UINT64_C(7);
15503 op <<= 5;
15504 Value |= op;
15505 break;
15506 }
15507 case AArch64::MOVAZ_ZMI_H_Q:
15508 case AArch64::MOVAZ_ZMI_V_Q: {
15509 // op: Rs
15510 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
15511 op &= UINT64_C(3);
15512 op <<= 13;
15513 Value |= op;
15514 // op: Zd
15515 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15516 op &= UINT64_C(31);
15517 Value |= op;
15518 // op: ZAn
15519 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15520 op &= UINT64_C(15);
15521 op <<= 5;
15522 Value |= op;
15523 break;
15524 }
15525 case AArch64::MOVAZ_ZMI_H_S:
15526 case AArch64::MOVAZ_ZMI_V_S: {
15527 // op: Rs
15528 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
15529 op &= UINT64_C(3);
15530 op <<= 13;
15531 Value |= op;
15532 // op: Zd
15533 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15534 op &= UINT64_C(31);
15535 Value |= op;
15536 // op: ZAn
15537 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15538 op &= UINT64_C(3);
15539 op <<= 7;
15540 Value |= op;
15541 // op: imm
15542 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15543 op &= UINT64_C(3);
15544 op <<= 5;
15545 Value |= op;
15546 break;
15547 }
15548 case AArch64::MOVAZ_ZMI_H_D:
15549 case AArch64::MOVAZ_ZMI_V_D: {
15550 // op: Rs
15551 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
15552 op &= UINT64_C(3);
15553 op <<= 13;
15554 Value |= op;
15555 // op: Zd
15556 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15557 op &= UINT64_C(31);
15558 Value |= op;
15559 // op: ZAn
15560 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15561 op &= UINT64_C(7);
15562 op <<= 6;
15563 Value |= op;
15564 // op: imm
15565 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15566 op &= UINT64_C(1);
15567 op <<= 5;
15568 Value |= op;
15569 break;
15570 }
15571 case AArch64::MOVAZ_ZMI_H_B:
15572 case AArch64::MOVAZ_ZMI_V_B: {
15573 // op: Rs
15574 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
15575 op &= UINT64_C(3);
15576 op <<= 13;
15577 Value |= op;
15578 // op: Zd
15579 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15580 op &= UINT64_C(31);
15581 Value |= op;
15582 // op: imm
15583 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15584 op &= UINT64_C(15);
15585 op <<= 5;
15586 Value |= op;
15587 break;
15588 }
15589 case AArch64::MOVA_VG2_MXI2Z: {
15590 // op: Rs
15591 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
15592 op &= UINT64_C(3);
15593 op <<= 13;
15594 Value |= op;
15595 // op: imm
15596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15597 op &= UINT64_C(7);
15598 Value |= op;
15599 // op: Zn
15600 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
15601 op &= UINT64_C(15);
15602 op <<= 6;
15603 Value |= op;
15604 break;
15605 }
15606 case AArch64::MOVA_VG4_MXI4Z: {
15607 // op: Rs
15608 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
15609 op &= UINT64_C(3);
15610 op <<= 13;
15611 Value |= op;
15612 // op: imm
15613 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15614 op &= UINT64_C(7);
15615 Value |= op;
15616 // op: Zn
15617 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
15618 op &= UINT64_C(7);
15619 op <<= 7;
15620 Value |= op;
15621 break;
15622 }
15623 case AArch64::MOVA_VG2_2ZMXI: {
15624 // op: Rs
15625 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
15626 op &= UINT64_C(3);
15627 op <<= 13;
15628 Value |= op;
15629 // op: imm
15630 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15631 op &= UINT64_C(7);
15632 op <<= 5;
15633 Value |= op;
15634 // op: Zd
15635 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
15636 op &= UINT64_C(15);
15637 op <<= 1;
15638 Value |= op;
15639 break;
15640 }
15641 case AArch64::MOVA_VG4_4ZMXI: {
15642 // op: Rs
15643 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
15644 op &= UINT64_C(3);
15645 op <<= 13;
15646 Value |= op;
15647 // op: imm
15648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15649 op &= UINT64_C(7);
15650 op <<= 5;
15651 Value |= op;
15652 // op: Zd
15653 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
15654 op &= UINT64_C(7);
15655 op <<= 2;
15656 Value |= op;
15657 break;
15658 }
15659 case AArch64::MOVAZ_VG2_2ZMXI: {
15660 // op: Rs
15661 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 3, Fixups, STI);
15662 op &= UINT64_C(3);
15663 op <<= 13;
15664 Value |= op;
15665 // op: imm
15666 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15667 op &= UINT64_C(7);
15668 op <<= 5;
15669 Value |= op;
15670 // op: Zd
15671 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
15672 op &= UINT64_C(15);
15673 op <<= 1;
15674 Value |= op;
15675 break;
15676 }
15677 case AArch64::MOVAZ_VG4_4ZMXI: {
15678 // op: Rs
15679 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 3, Fixups, STI);
15680 op &= UINT64_C(3);
15681 op <<= 13;
15682 Value |= op;
15683 // op: imm
15684 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
15685 op &= UINT64_C(7);
15686 op <<= 5;
15687 Value |= op;
15688 // op: Zd
15689 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
15690 op &= UINT64_C(7);
15691 op <<= 2;
15692 Value |= op;
15693 break;
15694 }
15695 case AArch64::LDADDAB:
15696 case AArch64::LDADDAH:
15697 case AArch64::LDADDALB:
15698 case AArch64::LDADDALH:
15699 case AArch64::LDADDALW:
15700 case AArch64::LDADDALX:
15701 case AArch64::LDADDAW:
15702 case AArch64::LDADDAX:
15703 case AArch64::LDADDB:
15704 case AArch64::LDADDH:
15705 case AArch64::LDADDLB:
15706 case AArch64::LDADDLH:
15707 case AArch64::LDADDLW:
15708 case AArch64::LDADDLX:
15709 case AArch64::LDADDW:
15710 case AArch64::LDADDX:
15711 case AArch64::LDCLRAB:
15712 case AArch64::LDCLRAH:
15713 case AArch64::LDCLRALB:
15714 case AArch64::LDCLRALH:
15715 case AArch64::LDCLRALW:
15716 case AArch64::LDCLRALX:
15717 case AArch64::LDCLRAW:
15718 case AArch64::LDCLRAX:
15719 case AArch64::LDCLRB:
15720 case AArch64::LDCLRH:
15721 case AArch64::LDCLRLB:
15722 case AArch64::LDCLRLH:
15723 case AArch64::LDCLRLW:
15724 case AArch64::LDCLRLX:
15725 case AArch64::LDCLRW:
15726 case AArch64::LDCLRX:
15727 case AArch64::LDEORAB:
15728 case AArch64::LDEORAH:
15729 case AArch64::LDEORALB:
15730 case AArch64::LDEORALH:
15731 case AArch64::LDEORALW:
15732 case AArch64::LDEORALX:
15733 case AArch64::LDEORAW:
15734 case AArch64::LDEORAX:
15735 case AArch64::LDEORB:
15736 case AArch64::LDEORH:
15737 case AArch64::LDEORLB:
15738 case AArch64::LDEORLH:
15739 case AArch64::LDEORLW:
15740 case AArch64::LDEORLX:
15741 case AArch64::LDEORW:
15742 case AArch64::LDEORX:
15743 case AArch64::LDSETAB:
15744 case AArch64::LDSETAH:
15745 case AArch64::LDSETALB:
15746 case AArch64::LDSETALH:
15747 case AArch64::LDSETALW:
15748 case AArch64::LDSETALX:
15749 case AArch64::LDSETAW:
15750 case AArch64::LDSETAX:
15751 case AArch64::LDSETB:
15752 case AArch64::LDSETH:
15753 case AArch64::LDSETLB:
15754 case AArch64::LDSETLH:
15755 case AArch64::LDSETLW:
15756 case AArch64::LDSETLX:
15757 case AArch64::LDSETW:
15758 case AArch64::LDSETX:
15759 case AArch64::LDSMAXAB:
15760 case AArch64::LDSMAXAH:
15761 case AArch64::LDSMAXALB:
15762 case AArch64::LDSMAXALH:
15763 case AArch64::LDSMAXALW:
15764 case AArch64::LDSMAXALX:
15765 case AArch64::LDSMAXAW:
15766 case AArch64::LDSMAXAX:
15767 case AArch64::LDSMAXB:
15768 case AArch64::LDSMAXH:
15769 case AArch64::LDSMAXLB:
15770 case AArch64::LDSMAXLH:
15771 case AArch64::LDSMAXLW:
15772 case AArch64::LDSMAXLX:
15773 case AArch64::LDSMAXW:
15774 case AArch64::LDSMAXX:
15775 case AArch64::LDSMINAB:
15776 case AArch64::LDSMINAH:
15777 case AArch64::LDSMINALB:
15778 case AArch64::LDSMINALH:
15779 case AArch64::LDSMINALW:
15780 case AArch64::LDSMINALX:
15781 case AArch64::LDSMINAW:
15782 case AArch64::LDSMINAX:
15783 case AArch64::LDSMINB:
15784 case AArch64::LDSMINH:
15785 case AArch64::LDSMINLB:
15786 case AArch64::LDSMINLH:
15787 case AArch64::LDSMINLW:
15788 case AArch64::LDSMINLX:
15789 case AArch64::LDSMINW:
15790 case AArch64::LDSMINX:
15791 case AArch64::LDUMAXAB:
15792 case AArch64::LDUMAXAH:
15793 case AArch64::LDUMAXALB:
15794 case AArch64::LDUMAXALH:
15795 case AArch64::LDUMAXALW:
15796 case AArch64::LDUMAXALX:
15797 case AArch64::LDUMAXAW:
15798 case AArch64::LDUMAXAX:
15799 case AArch64::LDUMAXB:
15800 case AArch64::LDUMAXH:
15801 case AArch64::LDUMAXLB:
15802 case AArch64::LDUMAXLH:
15803 case AArch64::LDUMAXLW:
15804 case AArch64::LDUMAXLX:
15805 case AArch64::LDUMAXW:
15806 case AArch64::LDUMAXX:
15807 case AArch64::LDUMINAB:
15808 case AArch64::LDUMINAH:
15809 case AArch64::LDUMINALB:
15810 case AArch64::LDUMINALH:
15811 case AArch64::LDUMINALW:
15812 case AArch64::LDUMINALX:
15813 case AArch64::LDUMINAW:
15814 case AArch64::LDUMINAX:
15815 case AArch64::LDUMINB:
15816 case AArch64::LDUMINH:
15817 case AArch64::LDUMINLB:
15818 case AArch64::LDUMINLH:
15819 case AArch64::LDUMINLW:
15820 case AArch64::LDUMINLX:
15821 case AArch64::LDUMINW:
15822 case AArch64::LDUMINX:
15823 case AArch64::RCWCLR:
15824 case AArch64::RCWCLRA:
15825 case AArch64::RCWCLRAL:
15826 case AArch64::RCWCLRL:
15827 case AArch64::RCWCLRS:
15828 case AArch64::RCWCLRSA:
15829 case AArch64::RCWCLRSAL:
15830 case AArch64::RCWCLRSL:
15831 case AArch64::RCWSET:
15832 case AArch64::RCWSETA:
15833 case AArch64::RCWSETAL:
15834 case AArch64::RCWSETL:
15835 case AArch64::RCWSETS:
15836 case AArch64::RCWSETSA:
15837 case AArch64::RCWSETSAL:
15838 case AArch64::RCWSETSL:
15839 case AArch64::RCWSWP:
15840 case AArch64::RCWSWPA:
15841 case AArch64::RCWSWPAL:
15842 case AArch64::RCWSWPL:
15843 case AArch64::RCWSWPS:
15844 case AArch64::RCWSWPSA:
15845 case AArch64::RCWSWPSAL:
15846 case AArch64::RCWSWPSL:
15847 case AArch64::SWPAB:
15848 case AArch64::SWPAH:
15849 case AArch64::SWPALB:
15850 case AArch64::SWPALH:
15851 case AArch64::SWPALW:
15852 case AArch64::SWPALX:
15853 case AArch64::SWPAW:
15854 case AArch64::SWPAX:
15855 case AArch64::SWPB:
15856 case AArch64::SWPH:
15857 case AArch64::SWPLB:
15858 case AArch64::SWPLH:
15859 case AArch64::SWPLW:
15860 case AArch64::SWPLX:
15861 case AArch64::SWPW:
15862 case AArch64::SWPX: {
15863 // op: Rs
15864 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15865 op &= UINT64_C(31);
15866 op <<= 16;
15867 Value |= op;
15868 // op: Rn
15869 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15870 op &= UINT64_C(31);
15871 op <<= 5;
15872 Value |= op;
15873 // op: Rt
15874 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15875 op &= UINT64_C(31);
15876 Value |= op;
15877 break;
15878 }
15879 case AArch64::CASAB:
15880 case AArch64::CASAH:
15881 case AArch64::CASALB:
15882 case AArch64::CASALH:
15883 case AArch64::CASALW:
15884 case AArch64::CASALX:
15885 case AArch64::CASAW:
15886 case AArch64::CASAX:
15887 case AArch64::CASB:
15888 case AArch64::CASH:
15889 case AArch64::CASLB:
15890 case AArch64::CASLH:
15891 case AArch64::CASLW:
15892 case AArch64::CASLX:
15893 case AArch64::CASPALW:
15894 case AArch64::CASPALX:
15895 case AArch64::CASPAW:
15896 case AArch64::CASPAX:
15897 case AArch64::CASPLW:
15898 case AArch64::CASPLX:
15899 case AArch64::CASPW:
15900 case AArch64::CASPX:
15901 case AArch64::CASW:
15902 case AArch64::CASX:
15903 case AArch64::RCWCAS:
15904 case AArch64::RCWCASA:
15905 case AArch64::RCWCASAL:
15906 case AArch64::RCWCASL:
15907 case AArch64::RCWCASP:
15908 case AArch64::RCWCASPA:
15909 case AArch64::RCWCASPAL:
15910 case AArch64::RCWCASPL:
15911 case AArch64::RCWSCAS:
15912 case AArch64::RCWSCASA:
15913 case AArch64::RCWSCASAL:
15914 case AArch64::RCWSCASL:
15915 case AArch64::RCWSCASP:
15916 case AArch64::RCWSCASPA:
15917 case AArch64::RCWSCASPAL:
15918 case AArch64::RCWSCASPL: {
15919 // op: Rs
15920 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15921 op &= UINT64_C(31);
15922 op <<= 16;
15923 Value |= op;
15924 // op: Rn
15925 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
15926 op &= UINT64_C(31);
15927 op <<= 5;
15928 Value |= op;
15929 // op: Rt
15930 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15931 op &= UINT64_C(31);
15932 Value |= op;
15933 break;
15934 }
15935 case AArch64::RPRFM: {
15936 // op: Rt
15937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15938 Value |= (op & UINT64_C(32)) << 10;
15939 Value |= (op & UINT64_C(24)) << 9;
15940 Value |= (op & UINT64_C(7));
15941 // op: Rn
15942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
15943 op &= UINT64_C(31);
15944 op <<= 5;
15945 Value |= op;
15946 // op: Rm
15947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15948 op &= UINT64_C(31);
15949 op <<= 16;
15950 Value |= op;
15951 break;
15952 }
15953 case AArch64::GCSPOPM:
15954 case AArch64::GCSPUSHM:
15955 case AArch64::GCSSS1:
15956 case AArch64::GCSSS2:
15957 case AArch64::TRCIT:
15958 case AArch64::TSTART:
15959 case AArch64::TTEST:
15960 case AArch64::WFET:
15961 case AArch64::WFIT: {
15962 // op: Rt
15963 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15964 op &= UINT64_C(31);
15965 Value |= op;
15966 break;
15967 }
15968 case AArch64::GCSSTR:
15969 case AArch64::GCSSTTR:
15970 case AArch64::LD64B:
15971 case AArch64::ST64B: {
15972 // op: Rt
15973 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
15974 op &= UINT64_C(31);
15975 Value |= op;
15976 // op: Rn
15977 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
15978 op &= UINT64_C(31);
15979 op <<= 5;
15980 Value |= op;
15981 break;
15982 }
15983 case AArch64::LDRBBroW:
15984 case AArch64::LDRBBroX:
15985 case AArch64::LDRBroW:
15986 case AArch64::LDRBroX:
15987 case AArch64::LDRDroW:
15988 case AArch64::LDRDroX:
15989 case AArch64::LDRHHroW:
15990 case AArch64::LDRHHroX:
15991 case AArch64::LDRHroW:
15992 case AArch64::LDRHroX:
15993 case AArch64::LDRQroW:
15994 case AArch64::LDRQroX:
15995 case AArch64::LDRSBWroW:
15996 case AArch64::LDRSBWroX:
15997 case AArch64::LDRSBXroW:
15998 case AArch64::LDRSBXroX:
15999 case AArch64::LDRSHWroW:
16000 case AArch64::LDRSHWroX:
16001 case AArch64::LDRSHXroW:
16002 case AArch64::LDRSHXroX:
16003 case AArch64::LDRSWroW:
16004 case AArch64::LDRSWroX:
16005 case AArch64::LDRSroW:
16006 case AArch64::LDRSroX:
16007 case AArch64::LDRWroW:
16008 case AArch64::LDRWroX:
16009 case AArch64::LDRXroW:
16010 case AArch64::LDRXroX:
16011 case AArch64::PRFMroW:
16012 case AArch64::PRFMroX:
16013 case AArch64::STRBBroW:
16014 case AArch64::STRBBroX:
16015 case AArch64::STRBroW:
16016 case AArch64::STRBroX:
16017 case AArch64::STRDroW:
16018 case AArch64::STRDroX:
16019 case AArch64::STRHHroW:
16020 case AArch64::STRHHroX:
16021 case AArch64::STRHroW:
16022 case AArch64::STRHroX:
16023 case AArch64::STRQroW:
16024 case AArch64::STRQroX:
16025 case AArch64::STRSroW:
16026 case AArch64::STRSroX:
16027 case AArch64::STRWroW:
16028 case AArch64::STRWroX:
16029 case AArch64::STRXroW:
16030 case AArch64::STRXroX: {
16031 // op: Rt
16032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16033 op &= UINT64_C(31);
16034 Value |= op;
16035 // op: Rn
16036 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16037 op &= UINT64_C(31);
16038 op <<= 5;
16039 Value |= op;
16040 // op: Rm
16041 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16042 op &= UINT64_C(31);
16043 op <<= 16;
16044 Value |= op;
16045 // op: extend
16046 op = getMemExtendOpValue(MI, OpIdx: 3, Fixups, STI);
16047 Value |= (op & UINT64_C(2)) << 14;
16048 Value |= (op & UINT64_C(1)) << 12;
16049 break;
16050 }
16051 case AArch64::LDRQui:
16052 case AArch64::STRQui: {
16053 // op: Rt
16054 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16055 op &= UINT64_C(31);
16056 Value |= op;
16057 // op: Rn
16058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16059 op &= UINT64_C(31);
16060 op <<= 5;
16061 Value |= op;
16062 // op: offset
16063 op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale16>(MI, OpIdx: 2, Fixups, STI);
16064 op &= UINT64_C(4095);
16065 op <<= 10;
16066 Value |= op;
16067 break;
16068 }
16069 case AArch64::LDRBBui:
16070 case AArch64::LDRBui:
16071 case AArch64::LDRSBWui:
16072 case AArch64::LDRSBXui:
16073 case AArch64::STRBBui:
16074 case AArch64::STRBui: {
16075 // op: Rt
16076 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16077 op &= UINT64_C(31);
16078 Value |= op;
16079 // op: Rn
16080 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16081 op &= UINT64_C(31);
16082 op <<= 5;
16083 Value |= op;
16084 // op: offset
16085 op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale1>(MI, OpIdx: 2, Fixups, STI);
16086 op &= UINT64_C(4095);
16087 op <<= 10;
16088 Value |= op;
16089 break;
16090 }
16091 case AArch64::LDRHHui:
16092 case AArch64::LDRHui:
16093 case AArch64::LDRSHWui:
16094 case AArch64::LDRSHXui:
16095 case AArch64::STRHHui:
16096 case AArch64::STRHui: {
16097 // op: Rt
16098 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16099 op &= UINT64_C(31);
16100 Value |= op;
16101 // op: Rn
16102 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16103 op &= UINT64_C(31);
16104 op <<= 5;
16105 Value |= op;
16106 // op: offset
16107 op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale2>(MI, OpIdx: 2, Fixups, STI);
16108 op &= UINT64_C(4095);
16109 op <<= 10;
16110 Value |= op;
16111 break;
16112 }
16113 case AArch64::LDRSWui:
16114 case AArch64::LDRSui:
16115 case AArch64::LDRWui:
16116 case AArch64::STRSui:
16117 case AArch64::STRWui: {
16118 // op: Rt
16119 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16120 op &= UINT64_C(31);
16121 Value |= op;
16122 // op: Rn
16123 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16124 op &= UINT64_C(31);
16125 op <<= 5;
16126 Value |= op;
16127 // op: offset
16128 op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale4>(MI, OpIdx: 2, Fixups, STI);
16129 op &= UINT64_C(4095);
16130 op <<= 10;
16131 Value |= op;
16132 break;
16133 }
16134 case AArch64::LDRDui:
16135 case AArch64::LDRXui:
16136 case AArch64::PRFMui:
16137 case AArch64::STRDui:
16138 case AArch64::STRXui: {
16139 // op: Rt
16140 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16141 op &= UINT64_C(31);
16142 Value |= op;
16143 // op: Rn
16144 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16145 op &= UINT64_C(31);
16146 op <<= 5;
16147 Value |= op;
16148 // op: offset
16149 op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale8>(MI, OpIdx: 2, Fixups, STI);
16150 op &= UINT64_C(4095);
16151 op <<= 10;
16152 Value |= op;
16153 break;
16154 }
16155 case AArch64::LDAPURBi:
16156 case AArch64::LDAPURHi:
16157 case AArch64::LDAPURSBWi:
16158 case AArch64::LDAPURSBXi:
16159 case AArch64::LDAPURSHWi:
16160 case AArch64::LDAPURSHXi:
16161 case AArch64::LDAPURSWi:
16162 case AArch64::LDAPURXi:
16163 case AArch64::LDAPURi:
16164 case AArch64::LDTRBi:
16165 case AArch64::LDTRHi:
16166 case AArch64::LDTRSBWi:
16167 case AArch64::LDTRSBXi:
16168 case AArch64::LDTRSHWi:
16169 case AArch64::LDTRSHXi:
16170 case AArch64::LDTRSWi:
16171 case AArch64::LDTRWi:
16172 case AArch64::LDTRXi:
16173 case AArch64::LDURBBi:
16174 case AArch64::LDURBi:
16175 case AArch64::LDURDi:
16176 case AArch64::LDURHHi:
16177 case AArch64::LDURHi:
16178 case AArch64::LDURQi:
16179 case AArch64::LDURSBWi:
16180 case AArch64::LDURSBXi:
16181 case AArch64::LDURSHWi:
16182 case AArch64::LDURSHXi:
16183 case AArch64::LDURSWi:
16184 case AArch64::LDURSi:
16185 case AArch64::LDURWi:
16186 case AArch64::LDURXi:
16187 case AArch64::PRFUMi:
16188 case AArch64::STLURBi:
16189 case AArch64::STLURHi:
16190 case AArch64::STLURWi:
16191 case AArch64::STLURXi:
16192 case AArch64::STTRBi:
16193 case AArch64::STTRHi:
16194 case AArch64::STTRWi:
16195 case AArch64::STTRXi:
16196 case AArch64::STURBBi:
16197 case AArch64::STURBi:
16198 case AArch64::STURDi:
16199 case AArch64::STURHHi:
16200 case AArch64::STURHi:
16201 case AArch64::STURQi:
16202 case AArch64::STURSi:
16203 case AArch64::STURWi:
16204 case AArch64::STURXi: {
16205 // op: Rt
16206 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16207 op &= UINT64_C(31);
16208 Value |= op;
16209 // op: Rn
16210 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16211 op &= UINT64_C(31);
16212 op <<= 5;
16213 Value |= op;
16214 // op: offset
16215 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16216 op &= UINT64_C(511);
16217 op <<= 12;
16218 Value |= op;
16219 break;
16220 }
16221 case AArch64::LDAPURbi:
16222 case AArch64::LDAPURdi:
16223 case AArch64::LDAPURhi:
16224 case AArch64::LDAPURqi:
16225 case AArch64::LDAPURsi:
16226 case AArch64::STLURbi:
16227 case AArch64::STLURdi:
16228 case AArch64::STLURhi:
16229 case AArch64::STLURqi:
16230 case AArch64::STLURsi: {
16231 // op: Rt
16232 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16233 op &= UINT64_C(31);
16234 Value |= op;
16235 // op: Rn
16236 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16237 op &= UINT64_C(31);
16238 op <<= 5;
16239 Value |= op;
16240 // op: simm
16241 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16242 op &= UINT64_C(511);
16243 op <<= 12;
16244 Value |= op;
16245 break;
16246 }
16247 case AArch64::LDARB:
16248 case AArch64::LDARH:
16249 case AArch64::LDARW:
16250 case AArch64::LDARX:
16251 case AArch64::LDAXRB:
16252 case AArch64::LDAXRH:
16253 case AArch64::LDAXRW:
16254 case AArch64::LDAXRX:
16255 case AArch64::LDLARB:
16256 case AArch64::LDLARH:
16257 case AArch64::LDLARW:
16258 case AArch64::LDLARX:
16259 case AArch64::LDXRB:
16260 case AArch64::LDXRH:
16261 case AArch64::LDXRW:
16262 case AArch64::LDXRX:
16263 case AArch64::STLLRB:
16264 case AArch64::STLLRH:
16265 case AArch64::STLLRW:
16266 case AArch64::STLLRX:
16267 case AArch64::STLRB:
16268 case AArch64::STLRH:
16269 case AArch64::STLRW:
16270 case AArch64::STLRX: {
16271 // op: Rt
16272 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16273 op &= UINT64_C(31);
16274 Value |= op;
16275 // op: Rn
16276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16277 op &= UINT64_C(31);
16278 op <<= 5;
16279 Value |= op;
16280 Value = fixLoadStoreExclusive<0,0>(MI, EncodedValue: Value, STI);
16281 break;
16282 }
16283 case AArch64::LDIAPPW:
16284 case AArch64::LDIAPPX:
16285 case AArch64::STILPW:
16286 case AArch64::STILPX: {
16287 // op: Rt
16288 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16289 op &= UINT64_C(31);
16290 Value |= op;
16291 // op: Rn
16292 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16293 op &= UINT64_C(31);
16294 op <<= 5;
16295 Value |= op;
16296 // op: Rt2
16297 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16298 op &= UINT64_C(31);
16299 op <<= 16;
16300 Value |= op;
16301 break;
16302 }
16303 case AArch64::LDNPDi:
16304 case AArch64::LDNPQi:
16305 case AArch64::LDNPSi:
16306 case AArch64::LDNPWi:
16307 case AArch64::LDNPXi:
16308 case AArch64::LDPDi:
16309 case AArch64::LDPQi:
16310 case AArch64::LDPSWi:
16311 case AArch64::LDPSi:
16312 case AArch64::LDPWi:
16313 case AArch64::LDPXi:
16314 case AArch64::STGPi:
16315 case AArch64::STNPDi:
16316 case AArch64::STNPQi:
16317 case AArch64::STNPSi:
16318 case AArch64::STNPWi:
16319 case AArch64::STNPXi:
16320 case AArch64::STPDi:
16321 case AArch64::STPQi:
16322 case AArch64::STPSi:
16323 case AArch64::STPWi:
16324 case AArch64::STPXi: {
16325 // op: Rt
16326 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16327 op &= UINT64_C(31);
16328 Value |= op;
16329 // op: Rt2
16330 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16331 op &= UINT64_C(31);
16332 op <<= 10;
16333 Value |= op;
16334 // op: Rn
16335 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16336 op &= UINT64_C(31);
16337 op <<= 5;
16338 Value |= op;
16339 // op: offset
16340 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16341 op &= UINT64_C(127);
16342 op <<= 15;
16343 Value |= op;
16344 break;
16345 }
16346 case AArch64::LDAXPW:
16347 case AArch64::LDAXPX:
16348 case AArch64::LDXPW:
16349 case AArch64::LDXPX: {
16350 // op: Rt
16351 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16352 op &= UINT64_C(31);
16353 Value |= op;
16354 // op: Rt2
16355 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16356 op &= UINT64_C(31);
16357 op <<= 10;
16358 Value |= op;
16359 // op: Rn
16360 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16361 op &= UINT64_C(31);
16362 op <<= 5;
16363 Value |= op;
16364 Value = fixLoadStoreExclusive<0,1>(MI, EncodedValue: Value, STI);
16365 break;
16366 }
16367 case AArch64::TBNZW:
16368 case AArch64::TBNZX:
16369 case AArch64::TBZW:
16370 case AArch64::TBZX: {
16371 // op: Rt
16372 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16373 op &= UINT64_C(31);
16374 Value |= op;
16375 // op: bit_off
16376 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16377 op &= UINT64_C(31);
16378 op <<= 19;
16379 Value |= op;
16380 // op: target
16381 op = getTestBranchTargetOpValue(MI, OpIdx: 2, Fixups, STI);
16382 op &= UINT64_C(16383);
16383 op <<= 5;
16384 Value |= op;
16385 break;
16386 }
16387 case AArch64::LDRDl:
16388 case AArch64::LDRQl:
16389 case AArch64::LDRSWl:
16390 case AArch64::LDRSl:
16391 case AArch64::LDRWl:
16392 case AArch64::LDRXl:
16393 case AArch64::PRFMl: {
16394 // op: Rt
16395 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16396 op &= UINT64_C(31);
16397 Value |= op;
16398 // op: label
16399 op = getLoadLiteralOpValue(MI, OpIdx: 1, Fixups, STI);
16400 op &= UINT64_C(524287);
16401 op <<= 5;
16402 Value |= op;
16403 break;
16404 }
16405 case AArch64::SYSLxt: {
16406 // op: Rt
16407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16408 op &= UINT64_C(31);
16409 Value |= op;
16410 // op: op1
16411 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16412 op &= UINT64_C(7);
16413 op <<= 16;
16414 Value |= op;
16415 // op: Cn
16416 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16417 op &= UINT64_C(15);
16418 op <<= 12;
16419 Value |= op;
16420 // op: Cm
16421 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16422 op &= UINT64_C(15);
16423 op <<= 8;
16424 Value |= op;
16425 // op: op2
16426 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16427 op &= UINT64_C(7);
16428 op <<= 5;
16429 Value |= op;
16430 break;
16431 }
16432 case AArch64::MRRS:
16433 case AArch64::MRS: {
16434 // op: Rt
16435 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16436 op &= UINT64_C(31);
16437 Value |= op;
16438 // op: systemreg
16439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16440 op &= UINT64_C(65535);
16441 op <<= 5;
16442 Value |= op;
16443 break;
16444 }
16445 case AArch64::CBNZW:
16446 case AArch64::CBNZX:
16447 case AArch64::CBZW:
16448 case AArch64::CBZX: {
16449 // op: Rt
16450 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16451 op &= UINT64_C(31);
16452 Value |= op;
16453 // op: target
16454 op = getCondBranchTargetOpValue(MI, OpIdx: 1, Fixups, STI);
16455 op &= UINT64_C(524287);
16456 op <<= 5;
16457 Value |= op;
16458 break;
16459 }
16460 case AArch64::LDAPRWpost:
16461 case AArch64::LDAPRXpost:
16462 case AArch64::STLRWpre:
16463 case AArch64::STLRXpre: {
16464 // op: Rt
16465 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16466 op &= UINT64_C(31);
16467 Value |= op;
16468 // op: Rn
16469 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16470 op &= UINT64_C(31);
16471 op <<= 5;
16472 Value |= op;
16473 break;
16474 }
16475 case AArch64::ST64BV:
16476 case AArch64::ST64BV0: {
16477 // op: Rt
16478 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16479 op &= UINT64_C(31);
16480 Value |= op;
16481 // op: Rn
16482 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16483 op &= UINT64_C(31);
16484 op <<= 5;
16485 Value |= op;
16486 // op: Rs
16487 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16488 op &= UINT64_C(31);
16489 op <<= 16;
16490 Value |= op;
16491 break;
16492 }
16493 case AArch64::LDRBBpost:
16494 case AArch64::LDRBBpre:
16495 case AArch64::LDRBpost:
16496 case AArch64::LDRBpre:
16497 case AArch64::LDRDpost:
16498 case AArch64::LDRDpre:
16499 case AArch64::LDRHHpost:
16500 case AArch64::LDRHHpre:
16501 case AArch64::LDRHpost:
16502 case AArch64::LDRHpre:
16503 case AArch64::LDRQpost:
16504 case AArch64::LDRQpre:
16505 case AArch64::LDRSBWpost:
16506 case AArch64::LDRSBWpre:
16507 case AArch64::LDRSBXpost:
16508 case AArch64::LDRSBXpre:
16509 case AArch64::LDRSHWpost:
16510 case AArch64::LDRSHWpre:
16511 case AArch64::LDRSHXpost:
16512 case AArch64::LDRSHXpre:
16513 case AArch64::LDRSWpost:
16514 case AArch64::LDRSWpre:
16515 case AArch64::LDRSpost:
16516 case AArch64::LDRSpre:
16517 case AArch64::LDRWpost:
16518 case AArch64::LDRWpre:
16519 case AArch64::LDRXpost:
16520 case AArch64::LDRXpre:
16521 case AArch64::STRBBpost:
16522 case AArch64::STRBBpre:
16523 case AArch64::STRBpost:
16524 case AArch64::STRBpre:
16525 case AArch64::STRDpost:
16526 case AArch64::STRDpre:
16527 case AArch64::STRHHpost:
16528 case AArch64::STRHHpre:
16529 case AArch64::STRHpost:
16530 case AArch64::STRHpre:
16531 case AArch64::STRQpost:
16532 case AArch64::STRQpre:
16533 case AArch64::STRSpost:
16534 case AArch64::STRSpre:
16535 case AArch64::STRWpost:
16536 case AArch64::STRWpre:
16537 case AArch64::STRXpost:
16538 case AArch64::STRXpre: {
16539 // op: Rt
16540 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16541 op &= UINT64_C(31);
16542 Value |= op;
16543 // op: Rn
16544 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16545 op &= UINT64_C(31);
16546 op <<= 5;
16547 Value |= op;
16548 // op: offset
16549 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16550 op &= UINT64_C(511);
16551 op <<= 12;
16552 Value |= op;
16553 break;
16554 }
16555 case AArch64::LDIAPPWpost:
16556 case AArch64::LDIAPPXpost:
16557 case AArch64::STILPWpre:
16558 case AArch64::STILPXpre: {
16559 // op: Rt
16560 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16561 op &= UINT64_C(31);
16562 Value |= op;
16563 // op: Rn
16564 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16565 op &= UINT64_C(31);
16566 op <<= 5;
16567 Value |= op;
16568 // op: Rt2
16569 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16570 op &= UINT64_C(31);
16571 op <<= 16;
16572 Value |= op;
16573 break;
16574 }
16575 case AArch64::LDPDpost:
16576 case AArch64::LDPDpre:
16577 case AArch64::LDPQpost:
16578 case AArch64::LDPQpre:
16579 case AArch64::LDPSWpost:
16580 case AArch64::LDPSWpre:
16581 case AArch64::LDPSpost:
16582 case AArch64::LDPSpre:
16583 case AArch64::LDPWpost:
16584 case AArch64::LDPWpre:
16585 case AArch64::LDPXpost:
16586 case AArch64::LDPXpre:
16587 case AArch64::STGPpost:
16588 case AArch64::STGPpre:
16589 case AArch64::STPDpost:
16590 case AArch64::STPDpre:
16591 case AArch64::STPQpost:
16592 case AArch64::STPQpre:
16593 case AArch64::STPSpost:
16594 case AArch64::STPSpre:
16595 case AArch64::STPWpost:
16596 case AArch64::STPWpre:
16597 case AArch64::STPXpost:
16598 case AArch64::STPXpre: {
16599 // op: Rt
16600 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16601 op &= UINT64_C(31);
16602 Value |= op;
16603 // op: Rt2
16604 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16605 op &= UINT64_C(31);
16606 op <<= 10;
16607 Value |= op;
16608 // op: Rn
16609 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16610 op &= UINT64_C(31);
16611 op <<= 5;
16612 Value |= op;
16613 // op: offset
16614 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16615 op &= UINT64_C(127);
16616 op <<= 15;
16617 Value |= op;
16618 break;
16619 }
16620 case AArch64::MSR:
16621 case AArch64::MSRR: {
16622 // op: Rt
16623 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16624 op &= UINT64_C(31);
16625 Value |= op;
16626 // op: systemreg
16627 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16628 op &= UINT64_C(65535);
16629 op <<= 5;
16630 Value |= op;
16631 break;
16632 }
16633 case AArch64::LDCLRP:
16634 case AArch64::LDCLRPA:
16635 case AArch64::LDCLRPAL:
16636 case AArch64::LDCLRPL:
16637 case AArch64::LDSETP:
16638 case AArch64::LDSETPA:
16639 case AArch64::LDSETPAL:
16640 case AArch64::LDSETPL:
16641 case AArch64::SWPP:
16642 case AArch64::SWPPA:
16643 case AArch64::SWPPAL:
16644 case AArch64::SWPPL: {
16645 // op: Rt
16646 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16647 op &= UINT64_C(31);
16648 Value |= op;
16649 // op: Rt2
16650 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16651 op &= UINT64_C(31);
16652 op <<= 16;
16653 Value |= op;
16654 // op: Rn
16655 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16656 op &= UINT64_C(31);
16657 op <<= 5;
16658 Value |= op;
16659 break;
16660 }
16661 case AArch64::SYSPxt:
16662 case AArch64::SYSxt: {
16663 // op: Rt
16664 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16665 op &= UINT64_C(31);
16666 Value |= op;
16667 // op: op1
16668 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16669 op &= UINT64_C(7);
16670 op <<= 16;
16671 Value |= op;
16672 // op: Cn
16673 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16674 op &= UINT64_C(15);
16675 op <<= 12;
16676 Value |= op;
16677 // op: Cm
16678 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16679 op &= UINT64_C(15);
16680 op <<= 8;
16681 Value |= op;
16682 // op: op2
16683 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16684 op &= UINT64_C(7);
16685 op <<= 5;
16686 Value |= op;
16687 break;
16688 }
16689 case AArch64::RCWCLRP:
16690 case AArch64::RCWCLRPA:
16691 case AArch64::RCWCLRPAL:
16692 case AArch64::RCWCLRPL:
16693 case AArch64::RCWCLRSP:
16694 case AArch64::RCWCLRSPA:
16695 case AArch64::RCWCLRSPAL:
16696 case AArch64::RCWCLRSPL:
16697 case AArch64::RCWSETP:
16698 case AArch64::RCWSETPA:
16699 case AArch64::RCWSETPAL:
16700 case AArch64::RCWSETPL:
16701 case AArch64::RCWSETSP:
16702 case AArch64::RCWSETSPA:
16703 case AArch64::RCWSETSPAL:
16704 case AArch64::RCWSETSPL:
16705 case AArch64::RCWSWPP:
16706 case AArch64::RCWSWPPA:
16707 case AArch64::RCWSWPPAL:
16708 case AArch64::RCWSWPPL:
16709 case AArch64::RCWSWPSP:
16710 case AArch64::RCWSWPSPA:
16711 case AArch64::RCWSWPSPAL:
16712 case AArch64::RCWSWPSPL: {
16713 // op: Rt2
16714 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16715 op &= UINT64_C(31);
16716 op <<= 16;
16717 Value |= op;
16718 // op: Rn
16719 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16720 op &= UINT64_C(31);
16721 op <<= 5;
16722 Value |= op;
16723 // op: Rt
16724 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16725 op &= UINT64_C(31);
16726 Value |= op;
16727 break;
16728 }
16729 case AArch64::LDR_ZA:
16730 case AArch64::STR_ZA: {
16731 // op: Rv
16732 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI);
16733 op &= UINT64_C(3);
16734 op <<= 13;
16735 Value |= op;
16736 // op: Rn
16737 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16738 op &= UINT64_C(31);
16739 op <<= 5;
16740 Value |= op;
16741 // op: imm4
16742 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16743 op &= UINT64_C(15);
16744 Value |= op;
16745 break;
16746 }
16747 case AArch64::INSERT_MXIPZ_H_H:
16748 case AArch64::INSERT_MXIPZ_V_H: {
16749 // op: Rv
16750 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
16751 op &= UINT64_C(3);
16752 op <<= 13;
16753 Value |= op;
16754 // op: Pg
16755 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16756 op &= UINT64_C(7);
16757 op <<= 10;
16758 Value |= op;
16759 // op: Zn
16760 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16761 op &= UINT64_C(31);
16762 op <<= 5;
16763 Value |= op;
16764 // op: ZAd
16765 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16766 op &= UINT64_C(1);
16767 op <<= 3;
16768 Value |= op;
16769 // op: imm
16770 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16771 op &= UINT64_C(7);
16772 Value |= op;
16773 break;
16774 }
16775 case AArch64::INSERT_MXIPZ_H_Q:
16776 case AArch64::INSERT_MXIPZ_V_Q: {
16777 // op: Rv
16778 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
16779 op &= UINT64_C(3);
16780 op <<= 13;
16781 Value |= op;
16782 // op: Pg
16783 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16784 op &= UINT64_C(7);
16785 op <<= 10;
16786 Value |= op;
16787 // op: Zn
16788 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16789 op &= UINT64_C(31);
16790 op <<= 5;
16791 Value |= op;
16792 // op: ZAd
16793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16794 op &= UINT64_C(15);
16795 Value |= op;
16796 break;
16797 }
16798 case AArch64::INSERT_MXIPZ_H_S:
16799 case AArch64::INSERT_MXIPZ_V_S: {
16800 // op: Rv
16801 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
16802 op &= UINT64_C(3);
16803 op <<= 13;
16804 Value |= op;
16805 // op: Pg
16806 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16807 op &= UINT64_C(7);
16808 op <<= 10;
16809 Value |= op;
16810 // op: Zn
16811 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16812 op &= UINT64_C(31);
16813 op <<= 5;
16814 Value |= op;
16815 // op: ZAd
16816 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16817 op &= UINT64_C(3);
16818 op <<= 2;
16819 Value |= op;
16820 // op: imm
16821 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16822 op &= UINT64_C(3);
16823 Value |= op;
16824 break;
16825 }
16826 case AArch64::INSERT_MXIPZ_H_D:
16827 case AArch64::INSERT_MXIPZ_V_D: {
16828 // op: Rv
16829 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
16830 op &= UINT64_C(3);
16831 op <<= 13;
16832 Value |= op;
16833 // op: Pg
16834 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16835 op &= UINT64_C(7);
16836 op <<= 10;
16837 Value |= op;
16838 // op: Zn
16839 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16840 op &= UINT64_C(31);
16841 op <<= 5;
16842 Value |= op;
16843 // op: ZAd
16844 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16845 op &= UINT64_C(7);
16846 op <<= 1;
16847 Value |= op;
16848 // op: imm
16849 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16850 op &= UINT64_C(1);
16851 Value |= op;
16852 break;
16853 }
16854 case AArch64::INSERT_MXIPZ_H_B:
16855 case AArch64::INSERT_MXIPZ_V_B: {
16856 // op: Rv
16857 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
16858 op &= UINT64_C(3);
16859 op <<= 13;
16860 Value |= op;
16861 // op: Pg
16862 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16863 op &= UINT64_C(7);
16864 op <<= 10;
16865 Value |= op;
16866 // op: Zn
16867 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
16868 op &= UINT64_C(31);
16869 op <<= 5;
16870 Value |= op;
16871 // op: imm
16872 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
16873 op &= UINT64_C(15);
16874 Value |= op;
16875 break;
16876 }
16877 case AArch64::PSEL_PPPRI_B: {
16878 // op: Rv
16879 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
16880 op &= UINT64_C(3);
16881 op <<= 16;
16882 Value |= op;
16883 // op: Pn
16884 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16885 op &= UINT64_C(15);
16886 op <<= 10;
16887 Value |= op;
16888 // op: Pm
16889 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16890 op &= UINT64_C(15);
16891 op <<= 5;
16892 Value |= op;
16893 // op: Pd
16894 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16895 op &= UINT64_C(15);
16896 Value |= op;
16897 // op: imm
16898 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16899 Value |= (op & UINT64_C(12)) << 20;
16900 Value |= (op & UINT64_C(3)) << 19;
16901 break;
16902 }
16903 case AArch64::PSEL_PPPRI_H: {
16904 // op: Rv
16905 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
16906 op &= UINT64_C(3);
16907 op <<= 16;
16908 Value |= op;
16909 // op: Pn
16910 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16911 op &= UINT64_C(15);
16912 op <<= 10;
16913 Value |= op;
16914 // op: Pm
16915 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16916 op &= UINT64_C(15);
16917 op <<= 5;
16918 Value |= op;
16919 // op: Pd
16920 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16921 op &= UINT64_C(15);
16922 Value |= op;
16923 // op: imm
16924 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16925 Value |= (op & UINT64_C(6)) << 21;
16926 Value |= (op & UINT64_C(1)) << 20;
16927 break;
16928 }
16929 case AArch64::PSEL_PPPRI_D: {
16930 // op: Rv
16931 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
16932 op &= UINT64_C(3);
16933 op <<= 16;
16934 Value |= op;
16935 // op: Pn
16936 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16937 op &= UINT64_C(15);
16938 op <<= 10;
16939 Value |= op;
16940 // op: Pm
16941 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16942 op &= UINT64_C(15);
16943 op <<= 5;
16944 Value |= op;
16945 // op: Pd
16946 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16947 op &= UINT64_C(15);
16948 Value |= op;
16949 // op: imm
16950 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16951 op &= UINT64_C(1);
16952 op <<= 23;
16953 Value |= op;
16954 break;
16955 }
16956 case AArch64::PSEL_PPPRI_S: {
16957 // op: Rv
16958 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
16959 op &= UINT64_C(3);
16960 op <<= 16;
16961 Value |= op;
16962 // op: Pn
16963 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
16964 op &= UINT64_C(15);
16965 op <<= 10;
16966 Value |= op;
16967 // op: Pm
16968 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16969 op &= UINT64_C(15);
16970 op <<= 5;
16971 Value |= op;
16972 // op: Pd
16973 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16974 op &= UINT64_C(15);
16975 Value |= op;
16976 // op: imm
16977 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
16978 op &= UINT64_C(3);
16979 op <<= 22;
16980 Value |= op;
16981 break;
16982 }
16983 case AArch64::EXTRACT_ZPMXI_H_H:
16984 case AArch64::EXTRACT_ZPMXI_V_H: {
16985 // op: Rv
16986 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI);
16987 op &= UINT64_C(3);
16988 op <<= 13;
16989 Value |= op;
16990 // op: Pg
16991 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
16992 op &= UINT64_C(7);
16993 op <<= 10;
16994 Value |= op;
16995 // op: Zd
16996 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
16997 op &= UINT64_C(31);
16998 Value |= op;
16999 // op: ZAn
17000 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17001 op &= UINT64_C(1);
17002 op <<= 8;
17003 Value |= op;
17004 // op: imm
17005 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
17006 op &= UINT64_C(7);
17007 op <<= 5;
17008 Value |= op;
17009 break;
17010 }
17011 case AArch64::EXTRACT_ZPMXI_H_Q:
17012 case AArch64::EXTRACT_ZPMXI_V_Q: {
17013 // op: Rv
17014 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI);
17015 op &= UINT64_C(3);
17016 op <<= 13;
17017 Value |= op;
17018 // op: Pg
17019 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17020 op &= UINT64_C(7);
17021 op <<= 10;
17022 Value |= op;
17023 // op: Zd
17024 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17025 op &= UINT64_C(31);
17026 Value |= op;
17027 // op: ZAn
17028 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17029 op &= UINT64_C(15);
17030 op <<= 5;
17031 Value |= op;
17032 break;
17033 }
17034 case AArch64::EXTRACT_ZPMXI_H_S:
17035 case AArch64::EXTRACT_ZPMXI_V_S: {
17036 // op: Rv
17037 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI);
17038 op &= UINT64_C(3);
17039 op <<= 13;
17040 Value |= op;
17041 // op: Pg
17042 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17043 op &= UINT64_C(7);
17044 op <<= 10;
17045 Value |= op;
17046 // op: Zd
17047 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17048 op &= UINT64_C(31);
17049 Value |= op;
17050 // op: ZAn
17051 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17052 op &= UINT64_C(3);
17053 op <<= 7;
17054 Value |= op;
17055 // op: imm
17056 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
17057 op &= UINT64_C(3);
17058 op <<= 5;
17059 Value |= op;
17060 break;
17061 }
17062 case AArch64::EXTRACT_ZPMXI_H_D:
17063 case AArch64::EXTRACT_ZPMXI_V_D: {
17064 // op: Rv
17065 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI);
17066 op &= UINT64_C(3);
17067 op <<= 13;
17068 Value |= op;
17069 // op: Pg
17070 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17071 op &= UINT64_C(7);
17072 op <<= 10;
17073 Value |= op;
17074 // op: Zd
17075 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17076 op &= UINT64_C(31);
17077 Value |= op;
17078 // op: ZAn
17079 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17080 op &= UINT64_C(7);
17081 op <<= 6;
17082 Value |= op;
17083 // op: imm
17084 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
17085 op &= UINT64_C(1);
17086 op <<= 5;
17087 Value |= op;
17088 break;
17089 }
17090 case AArch64::EXTRACT_ZPMXI_H_B:
17091 case AArch64::EXTRACT_ZPMXI_V_B: {
17092 // op: Rv
17093 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI);
17094 op &= UINT64_C(3);
17095 op <<= 13;
17096 Value |= op;
17097 // op: Pg
17098 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17099 op &= UINT64_C(7);
17100 op <<= 10;
17101 Value |= op;
17102 // op: Zd
17103 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17104 op &= UINT64_C(31);
17105 Value |= op;
17106 // op: imm
17107 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
17108 op &= UINT64_C(15);
17109 op <<= 5;
17110 Value |= op;
17111 break;
17112 }
17113 case AArch64::BFMLAL_VG2_M2Z2Z_HtoS:
17114 case AArch64::BFMLSL_VG2_M2Z2Z_HtoS:
17115 case AArch64::FMLAL_VG2_M2Z2Z_BtoH:
17116 case AArch64::FMLAL_VG2_M2Z2Z_HtoS:
17117 case AArch64::FMLSL_VG2_M2Z2Z_HtoS:
17118 case AArch64::SMLAL_VG2_M2Z2Z_HtoS:
17119 case AArch64::SMLSL_VG2_M2Z2Z_HtoS:
17120 case AArch64::UMLAL_VG2_M2Z2Z_HtoS:
17121 case AArch64::UMLSL_VG2_M2Z2Z_HtoS: {
17122 // op: Rv
17123 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
17124 op &= UINT64_C(3);
17125 op <<= 13;
17126 Value |= op;
17127 // op: Zm
17128 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 5, Fixups, STI);
17129 op &= UINT64_C(15);
17130 op <<= 17;
17131 Value |= op;
17132 // op: Zn
17133 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
17134 op &= UINT64_C(15);
17135 op <<= 6;
17136 Value |= op;
17137 // op: imm
17138 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17139 op &= UINT64_C(3);
17140 Value |= op;
17141 break;
17142 }
17143 case AArch64::BFMLAL_VG4_M4Z4Z_HtoS:
17144 case AArch64::BFMLSL_VG4_M4Z4Z_HtoS:
17145 case AArch64::FMLAL_VG4_M4Z4Z_BtoH:
17146 case AArch64::FMLAL_VG4_M4Z4Z_HtoS:
17147 case AArch64::FMLSL_VG4_M4Z4Z_HtoS:
17148 case AArch64::SMLAL_VG4_M4Z4Z_HtoS:
17149 case AArch64::SMLSL_VG4_M4Z4Z_HtoS:
17150 case AArch64::UMLAL_VG4_M4Z4Z_HtoS:
17151 case AArch64::UMLSL_VG4_M4Z4Z_HtoS: {
17152 // op: Rv
17153 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
17154 op &= UINT64_C(3);
17155 op <<= 13;
17156 Value |= op;
17157 // op: Zm
17158 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 5, Fixups, STI);
17159 op &= UINT64_C(7);
17160 op <<= 18;
17161 Value |= op;
17162 // op: Zn
17163 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
17164 op &= UINT64_C(7);
17165 op <<= 7;
17166 Value |= op;
17167 // op: imm
17168 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17169 op &= UINT64_C(3);
17170 Value |= op;
17171 break;
17172 }
17173 case AArch64::BFMLAL_VG2_M2ZZ_HtoS:
17174 case AArch64::BFMLAL_VG4_M4ZZ_HtoS:
17175 case AArch64::BFMLSL_VG2_M2ZZ_HtoS:
17176 case AArch64::BFMLSL_VG4_M4ZZ_HtoS:
17177 case AArch64::FMLAL_VG2_M2ZZ_BtoH:
17178 case AArch64::FMLAL_VG2_M2ZZ_HtoS:
17179 case AArch64::FMLAL_VG4_M4ZZ_BtoH:
17180 case AArch64::FMLAL_VG4_M4ZZ_HtoS:
17181 case AArch64::FMLSL_VG2_M2ZZ_HtoS:
17182 case AArch64::FMLSL_VG4_M4ZZ_HtoS:
17183 case AArch64::SMLAL_VG2_M2ZZ_HtoS:
17184 case AArch64::SMLAL_VG4_M4ZZ_HtoS:
17185 case AArch64::SMLSL_VG2_M2ZZ_HtoS:
17186 case AArch64::SMLSL_VG4_M4ZZ_HtoS:
17187 case AArch64::UMLAL_VG2_M2ZZ_HtoS:
17188 case AArch64::UMLAL_VG4_M4ZZ_HtoS:
17189 case AArch64::UMLSL_VG2_M2ZZ_HtoS:
17190 case AArch64::UMLSL_VG4_M4ZZ_HtoS: {
17191 // op: Rv
17192 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
17193 op &= UINT64_C(3);
17194 op <<= 13;
17195 Value |= op;
17196 // op: Zm
17197 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
17198 op &= UINT64_C(15);
17199 op <<= 16;
17200 Value |= op;
17201 // op: Zn
17202 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
17203 op &= UINT64_C(31);
17204 op <<= 5;
17205 Value |= op;
17206 // op: imm
17207 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17208 op &= UINT64_C(3);
17209 Value |= op;
17210 break;
17211 }
17212 case AArch64::BFMLAL_MZZ_HtoS:
17213 case AArch64::BFMLSL_MZZ_HtoS:
17214 case AArch64::FMLAL_MZZ_HtoS:
17215 case AArch64::FMLAL_VG2_MZZ_BtoH:
17216 case AArch64::FMLSL_MZZ_HtoS:
17217 case AArch64::SMLAL_MZZ_HtoS:
17218 case AArch64::SMLSL_MZZ_HtoS:
17219 case AArch64::UMLAL_MZZ_HtoS:
17220 case AArch64::UMLSL_MZZ_HtoS: {
17221 // op: Rv
17222 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
17223 op &= UINT64_C(3);
17224 op <<= 13;
17225 Value |= op;
17226 // op: Zm
17227 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
17228 op &= UINT64_C(15);
17229 op <<= 16;
17230 Value |= op;
17231 // op: Zn
17232 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
17233 op &= UINT64_C(31);
17234 op <<= 5;
17235 Value |= op;
17236 // op: imm
17237 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17238 op &= UINT64_C(7);
17239 Value |= op;
17240 break;
17241 }
17242 case AArch64::ZERO_MXI_VG2_4Z:
17243 case AArch64::ZERO_MXI_VG4_4Z: {
17244 // op: Rv
17245 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
17246 op &= UINT64_C(3);
17247 op <<= 13;
17248 Value |= op;
17249 // op: imm
17250 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17251 op &= UINT64_C(1);
17252 Value |= op;
17253 break;
17254 }
17255 case AArch64::ZERO_MXI_4Z:
17256 case AArch64::ZERO_MXI_VG2_2Z:
17257 case AArch64::ZERO_MXI_VG4_2Z: {
17258 // op: Rv
17259 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
17260 op &= UINT64_C(3);
17261 op <<= 13;
17262 Value |= op;
17263 // op: imm
17264 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17265 op &= UINT64_C(3);
17266 Value |= op;
17267 break;
17268 }
17269 case AArch64::ZERO_MXI_2Z:
17270 case AArch64::ZERO_MXI_VG2_Z:
17271 case AArch64::ZERO_MXI_VG4_Z: {
17272 // op: Rv
17273 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
17274 op &= UINT64_C(3);
17275 op <<= 13;
17276 Value |= op;
17277 // op: imm
17278 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17279 op &= UINT64_C(7);
17280 Value |= op;
17281 break;
17282 }
17283 case AArch64::ADD_VG2_M2Z_D:
17284 case AArch64::ADD_VG2_M2Z_S:
17285 case AArch64::BFADD_VG2_M2Z_H:
17286 case AArch64::BFSUB_VG2_M2Z_H:
17287 case AArch64::FADD_VG2_M2Z_D:
17288 case AArch64::FADD_VG2_M2Z_H:
17289 case AArch64::FADD_VG2_M2Z_S:
17290 case AArch64::FSUB_VG2_M2Z_D:
17291 case AArch64::FSUB_VG2_M2Z_H:
17292 case AArch64::FSUB_VG2_M2Z_S:
17293 case AArch64::SUB_VG2_M2Z_D:
17294 case AArch64::SUB_VG2_M2Z_S: {
17295 // op: Rv
17296 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
17297 op &= UINT64_C(3);
17298 op <<= 13;
17299 Value |= op;
17300 // op: imm3
17301 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17302 op &= UINT64_C(7);
17303 Value |= op;
17304 // op: Zm
17305 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
17306 op &= UINT64_C(15);
17307 op <<= 6;
17308 Value |= op;
17309 break;
17310 }
17311 case AArch64::ADD_VG4_M4Z_D:
17312 case AArch64::ADD_VG4_M4Z_S:
17313 case AArch64::BFADD_VG4_M4Z_H:
17314 case AArch64::BFSUB_VG4_M4Z_H:
17315 case AArch64::FADD_VG4_M4Z_D:
17316 case AArch64::FADD_VG4_M4Z_H:
17317 case AArch64::FADD_VG4_M4Z_S:
17318 case AArch64::FSUB_VG4_M4Z_D:
17319 case AArch64::FSUB_VG4_M4Z_H:
17320 case AArch64::FSUB_VG4_M4Z_S:
17321 case AArch64::SUB_VG4_M4Z_D:
17322 case AArch64::SUB_VG4_M4Z_S: {
17323 // op: Rv
17324 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
17325 op &= UINT64_C(3);
17326 op <<= 13;
17327 Value |= op;
17328 // op: imm3
17329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17330 op &= UINT64_C(7);
17331 Value |= op;
17332 // op: Zm
17333 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
17334 op &= UINT64_C(7);
17335 op <<= 7;
17336 Value |= op;
17337 break;
17338 }
17339 case AArch64::RAX1:
17340 case AArch64::SM4ENCKEY:
17341 case AArch64::TBLv8i8Four:
17342 case AArch64::TBLv8i8One:
17343 case AArch64::TBLv8i8Three:
17344 case AArch64::TBLv8i8Two:
17345 case AArch64::TBLv16i8Four:
17346 case AArch64::TBLv16i8One:
17347 case AArch64::TBLv16i8Three:
17348 case AArch64::TBLv16i8Two: {
17349 // op: Vd
17350 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17351 op &= UINT64_C(31);
17352 Value |= op;
17353 // op: Vn
17354 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17355 op &= UINT64_C(31);
17356 op <<= 5;
17357 Value |= op;
17358 // op: Vm
17359 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17360 op &= UINT64_C(31);
17361 op <<= 16;
17362 Value |= op;
17363 break;
17364 }
17365 case AArch64::BCAX:
17366 case AArch64::EOR3:
17367 case AArch64::SM3SS1: {
17368 // op: Vd
17369 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17370 op &= UINT64_C(31);
17371 Value |= op;
17372 // op: Vn
17373 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17374 op &= UINT64_C(31);
17375 op <<= 5;
17376 Value |= op;
17377 // op: Vm
17378 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17379 op &= UINT64_C(31);
17380 op <<= 16;
17381 Value |= op;
17382 // op: Va
17383 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17384 op &= UINT64_C(31);
17385 op <<= 10;
17386 Value |= op;
17387 break;
17388 }
17389 case AArch64::XAR: {
17390 // op: Vd
17391 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17392 op &= UINT64_C(31);
17393 Value |= op;
17394 // op: Vn
17395 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17396 op &= UINT64_C(31);
17397 op <<= 5;
17398 Value |= op;
17399 // op: imm
17400 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17401 op &= UINT64_C(63);
17402 op <<= 10;
17403 Value |= op;
17404 // op: Vm
17405 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17406 op &= UINT64_C(31);
17407 op <<= 16;
17408 Value |= op;
17409 break;
17410 }
17411 case AArch64::ADDQV_VPZ_B:
17412 case AArch64::ADDQV_VPZ_D:
17413 case AArch64::ADDQV_VPZ_H:
17414 case AArch64::ADDQV_VPZ_S:
17415 case AArch64::ANDQV_VPZ_B:
17416 case AArch64::ANDQV_VPZ_D:
17417 case AArch64::ANDQV_VPZ_H:
17418 case AArch64::ANDQV_VPZ_S:
17419 case AArch64::EORQV_VPZ_B:
17420 case AArch64::EORQV_VPZ_D:
17421 case AArch64::EORQV_VPZ_H:
17422 case AArch64::EORQV_VPZ_S:
17423 case AArch64::FADDQV_D:
17424 case AArch64::FADDQV_H:
17425 case AArch64::FADDQV_S:
17426 case AArch64::FMAXNMQV_D:
17427 case AArch64::FMAXNMQV_H:
17428 case AArch64::FMAXNMQV_S:
17429 case AArch64::FMAXQV_D:
17430 case AArch64::FMAXQV_H:
17431 case AArch64::FMAXQV_S:
17432 case AArch64::FMINNMQV_D:
17433 case AArch64::FMINNMQV_H:
17434 case AArch64::FMINNMQV_S:
17435 case AArch64::FMINQV_D:
17436 case AArch64::FMINQV_H:
17437 case AArch64::FMINQV_S:
17438 case AArch64::ORQV_VPZ_B:
17439 case AArch64::ORQV_VPZ_D:
17440 case AArch64::ORQV_VPZ_H:
17441 case AArch64::ORQV_VPZ_S:
17442 case AArch64::SMAXQV_VPZ_B:
17443 case AArch64::SMAXQV_VPZ_D:
17444 case AArch64::SMAXQV_VPZ_H:
17445 case AArch64::SMAXQV_VPZ_S:
17446 case AArch64::SMINQV_VPZ_B:
17447 case AArch64::SMINQV_VPZ_D:
17448 case AArch64::SMINQV_VPZ_H:
17449 case AArch64::SMINQV_VPZ_S:
17450 case AArch64::UMAXQV_VPZ_B:
17451 case AArch64::UMAXQV_VPZ_D:
17452 case AArch64::UMAXQV_VPZ_H:
17453 case AArch64::UMAXQV_VPZ_S:
17454 case AArch64::UMINQV_VPZ_B:
17455 case AArch64::UMINQV_VPZ_D:
17456 case AArch64::UMINQV_VPZ_H:
17457 case AArch64::UMINQV_VPZ_S: {
17458 // op: Vd
17459 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17460 op &= UINT64_C(31);
17461 Value |= op;
17462 // op: Zn
17463 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17464 op &= UINT64_C(31);
17465 op <<= 5;
17466 Value |= op;
17467 // op: Pg
17468 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17469 op &= UINT64_C(7);
17470 op <<= 10;
17471 Value |= op;
17472 break;
17473 }
17474 case AArch64::SHA512SU0:
17475 case AArch64::SM4E: {
17476 // op: Vd
17477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17478 op &= UINT64_C(31);
17479 Value |= op;
17480 // op: Vn
17481 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17482 op &= UINT64_C(31);
17483 op <<= 5;
17484 Value |= op;
17485 break;
17486 }
17487 case AArch64::SHA512H:
17488 case AArch64::SHA512H2:
17489 case AArch64::SHA512SU1:
17490 case AArch64::SM3PARTW1:
17491 case AArch64::SM3PARTW2:
17492 case AArch64::TBXv8i8Four:
17493 case AArch64::TBXv8i8One:
17494 case AArch64::TBXv8i8Three:
17495 case AArch64::TBXv8i8Two:
17496 case AArch64::TBXv16i8Four:
17497 case AArch64::TBXv16i8One:
17498 case AArch64::TBXv16i8Three:
17499 case AArch64::TBXv16i8Two: {
17500 // op: Vd
17501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17502 op &= UINT64_C(31);
17503 Value |= op;
17504 // op: Vn
17505 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17506 op &= UINT64_C(31);
17507 op <<= 5;
17508 Value |= op;
17509 // op: Vm
17510 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17511 op &= UINT64_C(31);
17512 op <<= 16;
17513 Value |= op;
17514 break;
17515 }
17516 case AArch64::SM3TT1A:
17517 case AArch64::SM3TT1B:
17518 case AArch64::SM3TT2A:
17519 case AArch64::SM3TT2B: {
17520 // op: Vd
17521 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17522 op &= UINT64_C(31);
17523 Value |= op;
17524 // op: Vn
17525 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17526 op &= UINT64_C(31);
17527 op <<= 5;
17528 Value |= op;
17529 // op: imm
17530 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
17531 op &= UINT64_C(3);
17532 op <<= 12;
17533 Value |= op;
17534 // op: Vm
17535 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17536 op &= UINT64_C(31);
17537 op <<= 16;
17538 Value |= op;
17539 break;
17540 }
17541 case AArch64::INSR_ZV_B:
17542 case AArch64::INSR_ZV_D:
17543 case AArch64::INSR_ZV_H:
17544 case AArch64::INSR_ZV_S: {
17545 // op: Vm
17546 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17547 op &= UINT64_C(31);
17548 op <<= 5;
17549 Value |= op;
17550 // op: Zdn
17551 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17552 op &= UINT64_C(31);
17553 Value |= op;
17554 break;
17555 }
17556 case AArch64::LD1Fourv1d:
17557 case AArch64::LD1Fourv2d:
17558 case AArch64::LD1Fourv2s:
17559 case AArch64::LD1Fourv4h:
17560 case AArch64::LD1Fourv4s:
17561 case AArch64::LD1Fourv8b:
17562 case AArch64::LD1Fourv8h:
17563 case AArch64::LD1Fourv16b:
17564 case AArch64::LD1Onev1d:
17565 case AArch64::LD1Onev2d:
17566 case AArch64::LD1Onev2s:
17567 case AArch64::LD1Onev4h:
17568 case AArch64::LD1Onev4s:
17569 case AArch64::LD1Onev8b:
17570 case AArch64::LD1Onev8h:
17571 case AArch64::LD1Onev16b:
17572 case AArch64::LD1Rv1d:
17573 case AArch64::LD1Rv2d:
17574 case AArch64::LD1Rv2s:
17575 case AArch64::LD1Rv4h:
17576 case AArch64::LD1Rv4s:
17577 case AArch64::LD1Rv8b:
17578 case AArch64::LD1Rv8h:
17579 case AArch64::LD1Rv16b:
17580 case AArch64::LD1Threev1d:
17581 case AArch64::LD1Threev2d:
17582 case AArch64::LD1Threev2s:
17583 case AArch64::LD1Threev4h:
17584 case AArch64::LD1Threev4s:
17585 case AArch64::LD1Threev8b:
17586 case AArch64::LD1Threev8h:
17587 case AArch64::LD1Threev16b:
17588 case AArch64::LD1Twov1d:
17589 case AArch64::LD1Twov2d:
17590 case AArch64::LD1Twov2s:
17591 case AArch64::LD1Twov4h:
17592 case AArch64::LD1Twov4s:
17593 case AArch64::LD1Twov8b:
17594 case AArch64::LD1Twov8h:
17595 case AArch64::LD1Twov16b:
17596 case AArch64::LD2Rv1d:
17597 case AArch64::LD2Rv2d:
17598 case AArch64::LD2Rv2s:
17599 case AArch64::LD2Rv4h:
17600 case AArch64::LD2Rv4s:
17601 case AArch64::LD2Rv8b:
17602 case AArch64::LD2Rv8h:
17603 case AArch64::LD2Rv16b:
17604 case AArch64::LD2Twov2d:
17605 case AArch64::LD2Twov2s:
17606 case AArch64::LD2Twov4h:
17607 case AArch64::LD2Twov4s:
17608 case AArch64::LD2Twov8b:
17609 case AArch64::LD2Twov8h:
17610 case AArch64::LD2Twov16b:
17611 case AArch64::LD3Rv1d:
17612 case AArch64::LD3Rv2d:
17613 case AArch64::LD3Rv2s:
17614 case AArch64::LD3Rv4h:
17615 case AArch64::LD3Rv4s:
17616 case AArch64::LD3Rv8b:
17617 case AArch64::LD3Rv8h:
17618 case AArch64::LD3Rv16b:
17619 case AArch64::LD3Threev2d:
17620 case AArch64::LD3Threev2s:
17621 case AArch64::LD3Threev4h:
17622 case AArch64::LD3Threev4s:
17623 case AArch64::LD3Threev8b:
17624 case AArch64::LD3Threev8h:
17625 case AArch64::LD3Threev16b:
17626 case AArch64::LD4Fourv2d:
17627 case AArch64::LD4Fourv2s:
17628 case AArch64::LD4Fourv4h:
17629 case AArch64::LD4Fourv4s:
17630 case AArch64::LD4Fourv8b:
17631 case AArch64::LD4Fourv8h:
17632 case AArch64::LD4Fourv16b:
17633 case AArch64::LD4Rv1d:
17634 case AArch64::LD4Rv2d:
17635 case AArch64::LD4Rv2s:
17636 case AArch64::LD4Rv4h:
17637 case AArch64::LD4Rv4s:
17638 case AArch64::LD4Rv8b:
17639 case AArch64::LD4Rv8h:
17640 case AArch64::LD4Rv16b:
17641 case AArch64::ST1Fourv1d:
17642 case AArch64::ST1Fourv2d:
17643 case AArch64::ST1Fourv2s:
17644 case AArch64::ST1Fourv4h:
17645 case AArch64::ST1Fourv4s:
17646 case AArch64::ST1Fourv8b:
17647 case AArch64::ST1Fourv8h:
17648 case AArch64::ST1Fourv16b:
17649 case AArch64::ST1Onev1d:
17650 case AArch64::ST1Onev2d:
17651 case AArch64::ST1Onev2s:
17652 case AArch64::ST1Onev4h:
17653 case AArch64::ST1Onev4s:
17654 case AArch64::ST1Onev8b:
17655 case AArch64::ST1Onev8h:
17656 case AArch64::ST1Onev16b:
17657 case AArch64::ST1Threev1d:
17658 case AArch64::ST1Threev2d:
17659 case AArch64::ST1Threev2s:
17660 case AArch64::ST1Threev4h:
17661 case AArch64::ST1Threev4s:
17662 case AArch64::ST1Threev8b:
17663 case AArch64::ST1Threev8h:
17664 case AArch64::ST1Threev16b:
17665 case AArch64::ST1Twov1d:
17666 case AArch64::ST1Twov2d:
17667 case AArch64::ST1Twov2s:
17668 case AArch64::ST1Twov4h:
17669 case AArch64::ST1Twov4s:
17670 case AArch64::ST1Twov8b:
17671 case AArch64::ST1Twov8h:
17672 case AArch64::ST1Twov16b:
17673 case AArch64::ST2Twov2d:
17674 case AArch64::ST2Twov2s:
17675 case AArch64::ST2Twov4h:
17676 case AArch64::ST2Twov4s:
17677 case AArch64::ST2Twov8b:
17678 case AArch64::ST2Twov8h:
17679 case AArch64::ST2Twov16b:
17680 case AArch64::ST3Threev2d:
17681 case AArch64::ST3Threev2s:
17682 case AArch64::ST3Threev4h:
17683 case AArch64::ST3Threev4s:
17684 case AArch64::ST3Threev8b:
17685 case AArch64::ST3Threev8h:
17686 case AArch64::ST3Threev16b:
17687 case AArch64::ST4Fourv2d:
17688 case AArch64::ST4Fourv2s:
17689 case AArch64::ST4Fourv4h:
17690 case AArch64::ST4Fourv4s:
17691 case AArch64::ST4Fourv8b:
17692 case AArch64::ST4Fourv8h:
17693 case AArch64::ST4Fourv16b: {
17694 // op: Vt
17695 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17696 op &= UINT64_C(31);
17697 Value |= op;
17698 // op: Rn
17699 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17700 op &= UINT64_C(31);
17701 op <<= 5;
17702 Value |= op;
17703 break;
17704 }
17705 case AArch64::STL1: {
17706 // op: Vt
17707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17708 op &= UINT64_C(31);
17709 Value |= op;
17710 // op: Rn
17711 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17712 op &= UINT64_C(31);
17713 op <<= 5;
17714 Value |= op;
17715 // op: Q
17716 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17717 op &= UINT64_C(1);
17718 op <<= 30;
17719 Value |= op;
17720 break;
17721 }
17722 case AArch64::ST1i32:
17723 case AArch64::ST2i32:
17724 case AArch64::ST3i32:
17725 case AArch64::ST4i32: {
17726 // op: Vt
17727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17728 op &= UINT64_C(31);
17729 Value |= op;
17730 // op: Rn
17731 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17732 op &= UINT64_C(31);
17733 op <<= 5;
17734 Value |= op;
17735 // op: idx
17736 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17737 Value |= (op & UINT64_C(2)) << 29;
17738 Value |= (op & UINT64_C(1)) << 12;
17739 break;
17740 }
17741 case AArch64::ST1i16:
17742 case AArch64::ST2i16:
17743 case AArch64::ST3i16:
17744 case AArch64::ST4i16: {
17745 // op: Vt
17746 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17747 op &= UINT64_C(31);
17748 Value |= op;
17749 // op: Rn
17750 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17751 op &= UINT64_C(31);
17752 op <<= 5;
17753 Value |= op;
17754 // op: idx
17755 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17756 Value |= (op & UINT64_C(4)) << 28;
17757 Value |= (op & UINT64_C(3)) << 11;
17758 break;
17759 }
17760 case AArch64::ST1i8:
17761 case AArch64::ST2i8:
17762 case AArch64::ST3i8:
17763 case AArch64::ST4i8: {
17764 // op: Vt
17765 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17766 op &= UINT64_C(31);
17767 Value |= op;
17768 // op: Rn
17769 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17770 op &= UINT64_C(31);
17771 op <<= 5;
17772 Value |= op;
17773 // op: idx
17774 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17775 Value |= (op & UINT64_C(8)) << 27;
17776 Value |= (op & UINT64_C(7)) << 10;
17777 break;
17778 }
17779 case AArch64::ST1i64:
17780 case AArch64::ST2i64:
17781 case AArch64::ST3i64:
17782 case AArch64::ST4i64: {
17783 // op: Vt
17784 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
17785 op &= UINT64_C(31);
17786 Value |= op;
17787 // op: Rn
17788 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17789 op &= UINT64_C(31);
17790 op <<= 5;
17791 Value |= op;
17792 // op: idx
17793 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17794 op &= UINT64_C(1);
17795 op <<= 30;
17796 Value |= op;
17797 break;
17798 }
17799 case AArch64::LD1Fourv1d_POST:
17800 case AArch64::LD1Fourv2d_POST:
17801 case AArch64::LD1Fourv2s_POST:
17802 case AArch64::LD1Fourv4h_POST:
17803 case AArch64::LD1Fourv4s_POST:
17804 case AArch64::LD1Fourv8b_POST:
17805 case AArch64::LD1Fourv8h_POST:
17806 case AArch64::LD1Fourv16b_POST:
17807 case AArch64::LD1Onev1d_POST:
17808 case AArch64::LD1Onev2d_POST:
17809 case AArch64::LD1Onev2s_POST:
17810 case AArch64::LD1Onev4h_POST:
17811 case AArch64::LD1Onev4s_POST:
17812 case AArch64::LD1Onev8b_POST:
17813 case AArch64::LD1Onev8h_POST:
17814 case AArch64::LD1Onev16b_POST:
17815 case AArch64::LD1Rv1d_POST:
17816 case AArch64::LD1Rv2d_POST:
17817 case AArch64::LD1Rv2s_POST:
17818 case AArch64::LD1Rv4h_POST:
17819 case AArch64::LD1Rv4s_POST:
17820 case AArch64::LD1Rv8b_POST:
17821 case AArch64::LD1Rv8h_POST:
17822 case AArch64::LD1Rv16b_POST:
17823 case AArch64::LD1Threev1d_POST:
17824 case AArch64::LD1Threev2d_POST:
17825 case AArch64::LD1Threev2s_POST:
17826 case AArch64::LD1Threev4h_POST:
17827 case AArch64::LD1Threev4s_POST:
17828 case AArch64::LD1Threev8b_POST:
17829 case AArch64::LD1Threev8h_POST:
17830 case AArch64::LD1Threev16b_POST:
17831 case AArch64::LD1Twov1d_POST:
17832 case AArch64::LD1Twov2d_POST:
17833 case AArch64::LD1Twov2s_POST:
17834 case AArch64::LD1Twov4h_POST:
17835 case AArch64::LD1Twov4s_POST:
17836 case AArch64::LD1Twov8b_POST:
17837 case AArch64::LD1Twov8h_POST:
17838 case AArch64::LD1Twov16b_POST:
17839 case AArch64::LD2Rv1d_POST:
17840 case AArch64::LD2Rv2d_POST:
17841 case AArch64::LD2Rv2s_POST:
17842 case AArch64::LD2Rv4h_POST:
17843 case AArch64::LD2Rv4s_POST:
17844 case AArch64::LD2Rv8b_POST:
17845 case AArch64::LD2Rv8h_POST:
17846 case AArch64::LD2Rv16b_POST:
17847 case AArch64::LD2Twov2d_POST:
17848 case AArch64::LD2Twov2s_POST:
17849 case AArch64::LD2Twov4h_POST:
17850 case AArch64::LD2Twov4s_POST:
17851 case AArch64::LD2Twov8b_POST:
17852 case AArch64::LD2Twov8h_POST:
17853 case AArch64::LD2Twov16b_POST:
17854 case AArch64::LD3Rv1d_POST:
17855 case AArch64::LD3Rv2d_POST:
17856 case AArch64::LD3Rv2s_POST:
17857 case AArch64::LD3Rv4h_POST:
17858 case AArch64::LD3Rv4s_POST:
17859 case AArch64::LD3Rv8b_POST:
17860 case AArch64::LD3Rv8h_POST:
17861 case AArch64::LD3Rv16b_POST:
17862 case AArch64::LD3Threev2d_POST:
17863 case AArch64::LD3Threev2s_POST:
17864 case AArch64::LD3Threev4h_POST:
17865 case AArch64::LD3Threev4s_POST:
17866 case AArch64::LD3Threev8b_POST:
17867 case AArch64::LD3Threev8h_POST:
17868 case AArch64::LD3Threev16b_POST:
17869 case AArch64::LD4Fourv2d_POST:
17870 case AArch64::LD4Fourv2s_POST:
17871 case AArch64::LD4Fourv4h_POST:
17872 case AArch64::LD4Fourv4s_POST:
17873 case AArch64::LD4Fourv8b_POST:
17874 case AArch64::LD4Fourv8h_POST:
17875 case AArch64::LD4Fourv16b_POST:
17876 case AArch64::LD4Rv1d_POST:
17877 case AArch64::LD4Rv2d_POST:
17878 case AArch64::LD4Rv2s_POST:
17879 case AArch64::LD4Rv4h_POST:
17880 case AArch64::LD4Rv4s_POST:
17881 case AArch64::LD4Rv8b_POST:
17882 case AArch64::LD4Rv8h_POST:
17883 case AArch64::LD4Rv16b_POST:
17884 case AArch64::ST1Fourv1d_POST:
17885 case AArch64::ST1Fourv2d_POST:
17886 case AArch64::ST1Fourv2s_POST:
17887 case AArch64::ST1Fourv4h_POST:
17888 case AArch64::ST1Fourv4s_POST:
17889 case AArch64::ST1Fourv8b_POST:
17890 case AArch64::ST1Fourv8h_POST:
17891 case AArch64::ST1Fourv16b_POST:
17892 case AArch64::ST1Onev1d_POST:
17893 case AArch64::ST1Onev2d_POST:
17894 case AArch64::ST1Onev2s_POST:
17895 case AArch64::ST1Onev4h_POST:
17896 case AArch64::ST1Onev4s_POST:
17897 case AArch64::ST1Onev8b_POST:
17898 case AArch64::ST1Onev8h_POST:
17899 case AArch64::ST1Onev16b_POST:
17900 case AArch64::ST1Threev1d_POST:
17901 case AArch64::ST1Threev2d_POST:
17902 case AArch64::ST1Threev2s_POST:
17903 case AArch64::ST1Threev4h_POST:
17904 case AArch64::ST1Threev4s_POST:
17905 case AArch64::ST1Threev8b_POST:
17906 case AArch64::ST1Threev8h_POST:
17907 case AArch64::ST1Threev16b_POST:
17908 case AArch64::ST1Twov1d_POST:
17909 case AArch64::ST1Twov2d_POST:
17910 case AArch64::ST1Twov2s_POST:
17911 case AArch64::ST1Twov4h_POST:
17912 case AArch64::ST1Twov4s_POST:
17913 case AArch64::ST1Twov8b_POST:
17914 case AArch64::ST1Twov8h_POST:
17915 case AArch64::ST1Twov16b_POST:
17916 case AArch64::ST2Twov2d_POST:
17917 case AArch64::ST2Twov2s_POST:
17918 case AArch64::ST2Twov4h_POST:
17919 case AArch64::ST2Twov4s_POST:
17920 case AArch64::ST2Twov8b_POST:
17921 case AArch64::ST2Twov8h_POST:
17922 case AArch64::ST2Twov16b_POST:
17923 case AArch64::ST3Threev2d_POST:
17924 case AArch64::ST3Threev2s_POST:
17925 case AArch64::ST3Threev4h_POST:
17926 case AArch64::ST3Threev4s_POST:
17927 case AArch64::ST3Threev8b_POST:
17928 case AArch64::ST3Threev8h_POST:
17929 case AArch64::ST3Threev16b_POST:
17930 case AArch64::ST4Fourv2d_POST:
17931 case AArch64::ST4Fourv2s_POST:
17932 case AArch64::ST4Fourv4h_POST:
17933 case AArch64::ST4Fourv4s_POST:
17934 case AArch64::ST4Fourv8b_POST:
17935 case AArch64::ST4Fourv8h_POST:
17936 case AArch64::ST4Fourv16b_POST: {
17937 // op: Vt
17938 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17939 op &= UINT64_C(31);
17940 Value |= op;
17941 // op: Rn
17942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17943 op &= UINT64_C(31);
17944 op <<= 5;
17945 Value |= op;
17946 // op: Xm
17947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17948 op &= UINT64_C(31);
17949 op <<= 16;
17950 Value |= op;
17951 break;
17952 }
17953 case AArch64::LDAP1: {
17954 // op: Vt
17955 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17956 op &= UINT64_C(31);
17957 Value |= op;
17958 // op: Rn
17959 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17960 op &= UINT64_C(31);
17961 op <<= 5;
17962 Value |= op;
17963 // op: Q
17964 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17965 op &= UINT64_C(1);
17966 op <<= 30;
17967 Value |= op;
17968 break;
17969 }
17970 case AArch64::LD1i32:
17971 case AArch64::LD2i32:
17972 case AArch64::LD3i32:
17973 case AArch64::LD4i32: {
17974 // op: Vt
17975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17976 op &= UINT64_C(31);
17977 Value |= op;
17978 // op: Rn
17979 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17980 op &= UINT64_C(31);
17981 op <<= 5;
17982 Value |= op;
17983 // op: idx
17984 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
17985 Value |= (op & UINT64_C(2)) << 29;
17986 Value |= (op & UINT64_C(1)) << 12;
17987 break;
17988 }
17989 case AArch64::ST1i32_POST:
17990 case AArch64::ST2i32_POST:
17991 case AArch64::ST3i32_POST:
17992 case AArch64::ST4i32_POST: {
17993 // op: Vt
17994 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
17995 op &= UINT64_C(31);
17996 Value |= op;
17997 // op: Rn
17998 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
17999 op &= UINT64_C(31);
18000 op <<= 5;
18001 Value |= op;
18002 // op: idx
18003 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18004 Value |= (op & UINT64_C(2)) << 29;
18005 Value |= (op & UINT64_C(1)) << 12;
18006 // op: Xm
18007 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18008 op &= UINT64_C(31);
18009 op <<= 16;
18010 Value |= op;
18011 break;
18012 }
18013 case AArch64::LD1i16:
18014 case AArch64::LD2i16:
18015 case AArch64::LD3i16:
18016 case AArch64::LD4i16: {
18017 // op: Vt
18018 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18019 op &= UINT64_C(31);
18020 Value |= op;
18021 // op: Rn
18022 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18023 op &= UINT64_C(31);
18024 op <<= 5;
18025 Value |= op;
18026 // op: idx
18027 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18028 Value |= (op & UINT64_C(4)) << 28;
18029 Value |= (op & UINT64_C(3)) << 11;
18030 break;
18031 }
18032 case AArch64::ST1i16_POST:
18033 case AArch64::ST2i16_POST:
18034 case AArch64::ST3i16_POST:
18035 case AArch64::ST4i16_POST: {
18036 // op: Vt
18037 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18038 op &= UINT64_C(31);
18039 Value |= op;
18040 // op: Rn
18041 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18042 op &= UINT64_C(31);
18043 op <<= 5;
18044 Value |= op;
18045 // op: idx
18046 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18047 Value |= (op & UINT64_C(4)) << 28;
18048 Value |= (op & UINT64_C(3)) << 11;
18049 // op: Xm
18050 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18051 op &= UINT64_C(31);
18052 op <<= 16;
18053 Value |= op;
18054 break;
18055 }
18056 case AArch64::LD1i8:
18057 case AArch64::LD2i8:
18058 case AArch64::LD3i8:
18059 case AArch64::LD4i8: {
18060 // op: Vt
18061 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18062 op &= UINT64_C(31);
18063 Value |= op;
18064 // op: Rn
18065 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18066 op &= UINT64_C(31);
18067 op <<= 5;
18068 Value |= op;
18069 // op: idx
18070 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18071 Value |= (op & UINT64_C(8)) << 27;
18072 Value |= (op & UINT64_C(7)) << 10;
18073 break;
18074 }
18075 case AArch64::ST1i8_POST:
18076 case AArch64::ST2i8_POST:
18077 case AArch64::ST3i8_POST:
18078 case AArch64::ST4i8_POST: {
18079 // op: Vt
18080 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18081 op &= UINT64_C(31);
18082 Value |= op;
18083 // op: Rn
18084 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18085 op &= UINT64_C(31);
18086 op <<= 5;
18087 Value |= op;
18088 // op: idx
18089 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18090 Value |= (op & UINT64_C(8)) << 27;
18091 Value |= (op & UINT64_C(7)) << 10;
18092 // op: Xm
18093 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18094 op &= UINT64_C(31);
18095 op <<= 16;
18096 Value |= op;
18097 break;
18098 }
18099 case AArch64::LD1i64:
18100 case AArch64::LD2i64:
18101 case AArch64::LD3i64:
18102 case AArch64::LD4i64: {
18103 // op: Vt
18104 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18105 op &= UINT64_C(31);
18106 Value |= op;
18107 // op: Rn
18108 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18109 op &= UINT64_C(31);
18110 op <<= 5;
18111 Value |= op;
18112 // op: idx
18113 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18114 op &= UINT64_C(1);
18115 op <<= 30;
18116 Value |= op;
18117 break;
18118 }
18119 case AArch64::ST1i64_POST:
18120 case AArch64::ST2i64_POST:
18121 case AArch64::ST3i64_POST:
18122 case AArch64::ST4i64_POST: {
18123 // op: Vt
18124 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18125 op &= UINT64_C(31);
18126 Value |= op;
18127 // op: Rn
18128 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18129 op &= UINT64_C(31);
18130 op <<= 5;
18131 Value |= op;
18132 // op: idx
18133 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18134 op &= UINT64_C(1);
18135 op <<= 30;
18136 Value |= op;
18137 // op: Xm
18138 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18139 op &= UINT64_C(31);
18140 op <<= 16;
18141 Value |= op;
18142 break;
18143 }
18144 case AArch64::LD1i32_POST:
18145 case AArch64::LD2i32_POST:
18146 case AArch64::LD3i32_POST:
18147 case AArch64::LD4i32_POST: {
18148 // op: Vt
18149 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18150 op &= UINT64_C(31);
18151 Value |= op;
18152 // op: Rn
18153 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18154 op &= UINT64_C(31);
18155 op <<= 5;
18156 Value |= op;
18157 // op: idx
18158 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18159 Value |= (op & UINT64_C(2)) << 29;
18160 Value |= (op & UINT64_C(1)) << 12;
18161 // op: Xm
18162 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18163 op &= UINT64_C(31);
18164 op <<= 16;
18165 Value |= op;
18166 break;
18167 }
18168 case AArch64::LD1i16_POST:
18169 case AArch64::LD2i16_POST:
18170 case AArch64::LD3i16_POST:
18171 case AArch64::LD4i16_POST: {
18172 // op: Vt
18173 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18174 op &= UINT64_C(31);
18175 Value |= op;
18176 // op: Rn
18177 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18178 op &= UINT64_C(31);
18179 op <<= 5;
18180 Value |= op;
18181 // op: idx
18182 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18183 Value |= (op & UINT64_C(4)) << 28;
18184 Value |= (op & UINT64_C(3)) << 11;
18185 // op: Xm
18186 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18187 op &= UINT64_C(31);
18188 op <<= 16;
18189 Value |= op;
18190 break;
18191 }
18192 case AArch64::LD1i8_POST:
18193 case AArch64::LD2i8_POST:
18194 case AArch64::LD3i8_POST:
18195 case AArch64::LD4i8_POST: {
18196 // op: Vt
18197 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18198 op &= UINT64_C(31);
18199 Value |= op;
18200 // op: Rn
18201 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18202 op &= UINT64_C(31);
18203 op <<= 5;
18204 Value |= op;
18205 // op: idx
18206 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18207 Value |= (op & UINT64_C(8)) << 27;
18208 Value |= (op & UINT64_C(7)) << 10;
18209 // op: Xm
18210 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18211 op &= UINT64_C(31);
18212 op <<= 16;
18213 Value |= op;
18214 break;
18215 }
18216 case AArch64::LD1i64_POST:
18217 case AArch64::LD2i64_POST:
18218 case AArch64::LD3i64_POST:
18219 case AArch64::LD4i64_POST: {
18220 // op: Vt
18221 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18222 op &= UINT64_C(31);
18223 Value |= op;
18224 // op: Rn
18225 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18226 op &= UINT64_C(31);
18227 op <<= 5;
18228 Value |= op;
18229 // op: idx
18230 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18231 op &= UINT64_C(1);
18232 op <<= 30;
18233 Value |= op;
18234 // op: Xm
18235 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
18236 op &= UINT64_C(31);
18237 op <<= 16;
18238 Value |= op;
18239 break;
18240 }
18241 case AArch64::STLXRB:
18242 case AArch64::STLXRH:
18243 case AArch64::STLXRW:
18244 case AArch64::STLXRX:
18245 case AArch64::STXRB:
18246 case AArch64::STXRH:
18247 case AArch64::STXRW:
18248 case AArch64::STXRX: {
18249 // op: Ws
18250 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18251 op &= UINT64_C(31);
18252 op <<= 16;
18253 Value |= op;
18254 // op: Rt
18255 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18256 op &= UINT64_C(31);
18257 Value |= op;
18258 // op: Rn
18259 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18260 op &= UINT64_C(31);
18261 op <<= 5;
18262 Value |= op;
18263 Value = fixLoadStoreExclusive<1,0>(MI, EncodedValue: Value, STI);
18264 break;
18265 }
18266 case AArch64::STLXPW:
18267 case AArch64::STLXPX:
18268 case AArch64::STXPW:
18269 case AArch64::STXPX: {
18270 // op: Ws
18271 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18272 op &= UINT64_C(31);
18273 op <<= 16;
18274 Value |= op;
18275 // op: Rt
18276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18277 op &= UINT64_C(31);
18278 Value |= op;
18279 // op: Rt2
18280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18281 op &= UINT64_C(31);
18282 op <<= 10;
18283 Value |= op;
18284 // op: Rn
18285 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18286 op &= UINT64_C(31);
18287 op <<= 5;
18288 Value |= op;
18289 break;
18290 }
18291 case AArch64::ADR:
18292 case AArch64::ADRP: {
18293 // op: Xd
18294 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18295 op &= UINT64_C(31);
18296 Value |= op;
18297 // op: label
18298 op = getAdrLabelOpValue(MI, OpIdx: 1, Fixups, STI);
18299 Value |= (op & UINT64_C(3)) << 29;
18300 Value |= (op & UINT64_C(2097148)) << 3;
18301 break;
18302 }
18303 case AArch64::MOVA_2ZMXI_H_H:
18304 case AArch64::MOVA_2ZMXI_V_H: {
18305 // op: Zd
18306 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
18307 op &= UINT64_C(15);
18308 op <<= 1;
18309 Value |= op;
18310 // op: Rs
18311 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
18312 op &= UINT64_C(3);
18313 op <<= 13;
18314 Value |= op;
18315 // op: ZAn
18316 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18317 op &= UINT64_C(1);
18318 op <<= 7;
18319 Value |= op;
18320 // op: imm
18321 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18322 op &= UINT64_C(3);
18323 op <<= 5;
18324 Value |= op;
18325 break;
18326 }
18327 case AArch64::MOVA_2ZMXI_H_S:
18328 case AArch64::MOVA_2ZMXI_V_S: {
18329 // op: Zd
18330 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
18331 op &= UINT64_C(15);
18332 op <<= 1;
18333 Value |= op;
18334 // op: Rs
18335 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
18336 op &= UINT64_C(3);
18337 op <<= 13;
18338 Value |= op;
18339 // op: ZAn
18340 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18341 op &= UINT64_C(3);
18342 op <<= 6;
18343 Value |= op;
18344 // op: imm
18345 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18346 op &= UINT64_C(1);
18347 op <<= 5;
18348 Value |= op;
18349 break;
18350 }
18351 case AArch64::MOVA_2ZMXI_H_D:
18352 case AArch64::MOVA_2ZMXI_V_D: {
18353 // op: Zd
18354 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
18355 op &= UINT64_C(15);
18356 op <<= 1;
18357 Value |= op;
18358 // op: Rs
18359 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
18360 op &= UINT64_C(3);
18361 op <<= 13;
18362 Value |= op;
18363 // op: ZAn
18364 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18365 op &= UINT64_C(7);
18366 op <<= 5;
18367 Value |= op;
18368 break;
18369 }
18370 case AArch64::MOVA_2ZMXI_H_B:
18371 case AArch64::MOVA_2ZMXI_V_B: {
18372 // op: Zd
18373 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
18374 op &= UINT64_C(15);
18375 op <<= 1;
18376 Value |= op;
18377 // op: Rs
18378 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
18379 op &= UINT64_C(3);
18380 op <<= 13;
18381 Value |= op;
18382 // op: imm
18383 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18384 op &= UINT64_C(7);
18385 op <<= 5;
18386 Value |= op;
18387 break;
18388 }
18389 case AArch64::MOVAZ_2ZMI_H_H:
18390 case AArch64::MOVAZ_2ZMI_V_H: {
18391 // op: Zd
18392 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
18393 op &= UINT64_C(15);
18394 op <<= 1;
18395 Value |= op;
18396 // op: Rs
18397 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
18398 op &= UINT64_C(3);
18399 op <<= 13;
18400 Value |= op;
18401 // op: ZAn
18402 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18403 op &= UINT64_C(1);
18404 op <<= 7;
18405 Value |= op;
18406 // op: imm
18407 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18408 op &= UINT64_C(3);
18409 op <<= 5;
18410 Value |= op;
18411 break;
18412 }
18413 case AArch64::MOVAZ_2ZMI_H_S:
18414 case AArch64::MOVAZ_2ZMI_V_S: {
18415 // op: Zd
18416 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
18417 op &= UINT64_C(15);
18418 op <<= 1;
18419 Value |= op;
18420 // op: Rs
18421 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
18422 op &= UINT64_C(3);
18423 op <<= 13;
18424 Value |= op;
18425 // op: ZAn
18426 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18427 op &= UINT64_C(3);
18428 op <<= 6;
18429 Value |= op;
18430 // op: imm
18431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18432 op &= UINT64_C(1);
18433 op <<= 5;
18434 Value |= op;
18435 break;
18436 }
18437 case AArch64::MOVAZ_2ZMI_H_D:
18438 case AArch64::MOVAZ_2ZMI_V_D: {
18439 // op: Zd
18440 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
18441 op &= UINT64_C(15);
18442 op <<= 1;
18443 Value |= op;
18444 // op: Rs
18445 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
18446 op &= UINT64_C(3);
18447 op <<= 13;
18448 Value |= op;
18449 // op: ZAn
18450 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18451 op &= UINT64_C(7);
18452 op <<= 5;
18453 Value |= op;
18454 break;
18455 }
18456 case AArch64::MOVAZ_2ZMI_H_B:
18457 case AArch64::MOVAZ_2ZMI_V_B: {
18458 // op: Zd
18459 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
18460 op &= UINT64_C(15);
18461 op <<= 1;
18462 Value |= op;
18463 // op: Rs
18464 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
18465 op &= UINT64_C(3);
18466 op <<= 13;
18467 Value |= op;
18468 // op: imm
18469 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18470 op &= UINT64_C(7);
18471 op <<= 5;
18472 Value |= op;
18473 break;
18474 }
18475 case AArch64::UZP_VG2_2ZZZ_B:
18476 case AArch64::UZP_VG2_2ZZZ_D:
18477 case AArch64::UZP_VG2_2ZZZ_H:
18478 case AArch64::UZP_VG2_2ZZZ_Q:
18479 case AArch64::UZP_VG2_2ZZZ_S:
18480 case AArch64::ZIP_VG2_2ZZZ_B:
18481 case AArch64::ZIP_VG2_2ZZZ_D:
18482 case AArch64::ZIP_VG2_2ZZZ_H:
18483 case AArch64::ZIP_VG2_2ZZZ_Q:
18484 case AArch64::ZIP_VG2_2ZZZ_S: {
18485 // op: Zd
18486 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
18487 op &= UINT64_C(15);
18488 op <<= 1;
18489 Value |= op;
18490 // op: Zm
18491 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18492 op &= UINT64_C(31);
18493 op <<= 16;
18494 Value |= op;
18495 // op: Zn
18496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18497 op &= UINT64_C(31);
18498 op <<= 5;
18499 Value |= op;
18500 break;
18501 }
18502 case AArch64::MOVA_4ZMXI_H_H:
18503 case AArch64::MOVA_4ZMXI_V_H: {
18504 // op: Zd
18505 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
18506 op &= UINT64_C(7);
18507 op <<= 2;
18508 Value |= op;
18509 // op: Rs
18510 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
18511 op &= UINT64_C(3);
18512 op <<= 13;
18513 Value |= op;
18514 // op: ZAn
18515 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18516 op &= UINT64_C(1);
18517 op <<= 6;
18518 Value |= op;
18519 // op: imm
18520 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18521 op &= UINT64_C(1);
18522 op <<= 5;
18523 Value |= op;
18524 break;
18525 }
18526 case AArch64::MOVA_4ZMXI_H_S:
18527 case AArch64::MOVA_4ZMXI_V_S: {
18528 // op: Zd
18529 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
18530 op &= UINT64_C(7);
18531 op <<= 2;
18532 Value |= op;
18533 // op: Rs
18534 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
18535 op &= UINT64_C(3);
18536 op <<= 13;
18537 Value |= op;
18538 // op: ZAn
18539 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18540 op &= UINT64_C(3);
18541 op <<= 5;
18542 Value |= op;
18543 break;
18544 }
18545 case AArch64::MOVA_4ZMXI_H_D:
18546 case AArch64::MOVA_4ZMXI_V_D: {
18547 // op: Zd
18548 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
18549 op &= UINT64_C(7);
18550 op <<= 2;
18551 Value |= op;
18552 // op: Rs
18553 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
18554 op &= UINT64_C(3);
18555 op <<= 13;
18556 Value |= op;
18557 // op: ZAn
18558 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18559 op &= UINT64_C(7);
18560 op <<= 5;
18561 Value |= op;
18562 break;
18563 }
18564 case AArch64::MOVA_4ZMXI_H_B:
18565 case AArch64::MOVA_4ZMXI_V_B: {
18566 // op: Zd
18567 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
18568 op &= UINT64_C(7);
18569 op <<= 2;
18570 Value |= op;
18571 // op: Rs
18572 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI);
18573 op &= UINT64_C(3);
18574 op <<= 13;
18575 Value |= op;
18576 // op: imm
18577 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18578 op &= UINT64_C(3);
18579 op <<= 5;
18580 Value |= op;
18581 break;
18582 }
18583 case AArch64::MOVAZ_4ZMI_H_H:
18584 case AArch64::MOVAZ_4ZMI_V_H: {
18585 // op: Zd
18586 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
18587 op &= UINT64_C(7);
18588 op <<= 2;
18589 Value |= op;
18590 // op: Rs
18591 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
18592 op &= UINT64_C(3);
18593 op <<= 13;
18594 Value |= op;
18595 // op: ZAn
18596 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18597 op &= UINT64_C(1);
18598 op <<= 6;
18599 Value |= op;
18600 // op: imm
18601 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18602 op &= UINT64_C(1);
18603 op <<= 5;
18604 Value |= op;
18605 break;
18606 }
18607 case AArch64::MOVAZ_4ZMI_H_S:
18608 case AArch64::MOVAZ_4ZMI_V_S: {
18609 // op: Zd
18610 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
18611 op &= UINT64_C(7);
18612 op <<= 2;
18613 Value |= op;
18614 // op: Rs
18615 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
18616 op &= UINT64_C(3);
18617 op <<= 13;
18618 Value |= op;
18619 // op: ZAn
18620 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18621 op &= UINT64_C(3);
18622 op <<= 5;
18623 Value |= op;
18624 break;
18625 }
18626 case AArch64::MOVAZ_4ZMI_H_D:
18627 case AArch64::MOVAZ_4ZMI_V_D: {
18628 // op: Zd
18629 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
18630 op &= UINT64_C(7);
18631 op <<= 2;
18632 Value |= op;
18633 // op: Rs
18634 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
18635 op &= UINT64_C(3);
18636 op <<= 13;
18637 Value |= op;
18638 // op: ZAn
18639 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18640 op &= UINT64_C(7);
18641 op <<= 5;
18642 Value |= op;
18643 break;
18644 }
18645 case AArch64::MOVAZ_4ZMI_H_B:
18646 case AArch64::MOVAZ_4ZMI_V_B: {
18647 // op: Zd
18648 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
18649 op &= UINT64_C(7);
18650 op <<= 2;
18651 Value |= op;
18652 // op: Rs
18653 op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI);
18654 op &= UINT64_C(3);
18655 op <<= 13;
18656 Value |= op;
18657 // op: imm
18658 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
18659 op &= UINT64_C(3);
18660 op <<= 5;
18661 Value |= op;
18662 break;
18663 }
18664 case AArch64::CPY_ZPzI_B:
18665 case AArch64::CPY_ZPzI_D:
18666 case AArch64::CPY_ZPzI_H:
18667 case AArch64::CPY_ZPzI_S: {
18668 // op: Zd
18669 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18670 op &= UINT64_C(31);
18671 Value |= op;
18672 // op: Pg
18673 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18674 op &= UINT64_C(15);
18675 op <<= 16;
18676 Value |= op;
18677 // op: imm
18678 op = getImm8OptLsl(MI, OpIdx: 2, Fixups, STI);
18679 op &= UINT64_C(511);
18680 op <<= 5;
18681 Value |= op;
18682 break;
18683 }
18684 case AArch64::CPY_ZPmI_B:
18685 case AArch64::CPY_ZPmI_D:
18686 case AArch64::CPY_ZPmI_H:
18687 case AArch64::CPY_ZPmI_S: {
18688 // op: Zd
18689 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18690 op &= UINT64_C(31);
18691 Value |= op;
18692 // op: Pg
18693 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18694 op &= UINT64_C(15);
18695 op <<= 16;
18696 Value |= op;
18697 // op: imm
18698 op = getImm8OptLsl(MI, OpIdx: 3, Fixups, STI);
18699 op &= UINT64_C(511);
18700 op <<= 5;
18701 Value |= op;
18702 break;
18703 }
18704 case AArch64::BFCVTNT_ZPmZ:
18705 case AArch64::BFCVT_ZPmZ:
18706 case AArch64::RBIT_ZPmZ_B:
18707 case AArch64::RBIT_ZPmZ_D:
18708 case AArch64::RBIT_ZPmZ_H:
18709 case AArch64::RBIT_ZPmZ_S:
18710 case AArch64::REVB_ZPmZ_D:
18711 case AArch64::REVB_ZPmZ_H:
18712 case AArch64::REVB_ZPmZ_S:
18713 case AArch64::REVD_ZPmZ:
18714 case AArch64::REVH_ZPmZ_D:
18715 case AArch64::REVH_ZPmZ_S:
18716 case AArch64::REVW_ZPmZ_D: {
18717 // op: Zd
18718 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18719 op &= UINT64_C(31);
18720 Value |= op;
18721 // op: Pg
18722 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18723 op &= UINT64_C(7);
18724 op <<= 10;
18725 Value |= op;
18726 // op: Zn
18727 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18728 op &= UINT64_C(31);
18729 op <<= 5;
18730 Value |= op;
18731 break;
18732 }
18733 case AArch64::PMOV_ZIP_B: {
18734 // op: Zd
18735 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18736 op &= UINT64_C(31);
18737 Value |= op;
18738 // op: Pn
18739 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18740 op &= UINT64_C(15);
18741 op <<= 5;
18742 Value |= op;
18743 break;
18744 }
18745 case AArch64::PMOV_ZIP_D: {
18746 // op: Zd
18747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18748 op &= UINT64_C(31);
18749 Value |= op;
18750 // op: Pn
18751 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18752 op &= UINT64_C(15);
18753 op <<= 5;
18754 Value |= op;
18755 // op: index
18756 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18757 Value |= (op & UINT64_C(4)) << 20;
18758 Value |= (op & UINT64_C(3)) << 17;
18759 break;
18760 }
18761 case AArch64::PMOV_ZIP_H: {
18762 // op: Zd
18763 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18764 op &= UINT64_C(31);
18765 Value |= op;
18766 // op: Pn
18767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18768 op &= UINT64_C(15);
18769 op <<= 5;
18770 Value |= op;
18771 // op: index
18772 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18773 op &= UINT64_C(1);
18774 op <<= 17;
18775 Value |= op;
18776 break;
18777 }
18778 case AArch64::PMOV_ZIP_S: {
18779 // op: Zd
18780 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18781 op &= UINT64_C(31);
18782 Value |= op;
18783 // op: Pn
18784 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18785 op &= UINT64_C(15);
18786 op <<= 5;
18787 Value |= op;
18788 // op: index
18789 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18790 op &= UINT64_C(3);
18791 op <<= 17;
18792 Value |= op;
18793 break;
18794 }
18795 case AArch64::INDEX_RR_B:
18796 case AArch64::INDEX_RR_D:
18797 case AArch64::INDEX_RR_H:
18798 case AArch64::INDEX_RR_S: {
18799 // op: Zd
18800 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18801 op &= UINT64_C(31);
18802 Value |= op;
18803 // op: Rm
18804 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18805 op &= UINT64_C(31);
18806 op <<= 16;
18807 Value |= op;
18808 // op: Rn
18809 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18810 op &= UINT64_C(31);
18811 op <<= 5;
18812 Value |= op;
18813 break;
18814 }
18815 case AArch64::ADD_ZZZ_B:
18816 case AArch64::ADD_ZZZ_CPA:
18817 case AArch64::ADD_ZZZ_D:
18818 case AArch64::ADD_ZZZ_H:
18819 case AArch64::ADD_ZZZ_S:
18820 case AArch64::AND_ZZZ:
18821 case AArch64::ASR_WIDE_ZZZ_B:
18822 case AArch64::ASR_WIDE_ZZZ_H:
18823 case AArch64::ASR_WIDE_ZZZ_S:
18824 case AArch64::BFADD_ZZZ:
18825 case AArch64::BFMUL_ZZZ:
18826 case AArch64::BFSUB_ZZZ:
18827 case AArch64::BIC_ZZZ:
18828 case AArch64::EOR_ZZZ:
18829 case AArch64::FADD_ZZZ_D:
18830 case AArch64::FADD_ZZZ_H:
18831 case AArch64::FADD_ZZZ_S:
18832 case AArch64::FMUL_ZZZ_D:
18833 case AArch64::FMUL_ZZZ_H:
18834 case AArch64::FMUL_ZZZ_S:
18835 case AArch64::FRECPS_ZZZ_D:
18836 case AArch64::FRECPS_ZZZ_H:
18837 case AArch64::FRECPS_ZZZ_S:
18838 case AArch64::FRSQRTS_ZZZ_D:
18839 case AArch64::FRSQRTS_ZZZ_H:
18840 case AArch64::FRSQRTS_ZZZ_S:
18841 case AArch64::FSUB_ZZZ_D:
18842 case AArch64::FSUB_ZZZ_H:
18843 case AArch64::FSUB_ZZZ_S:
18844 case AArch64::FTSMUL_ZZZ_D:
18845 case AArch64::FTSMUL_ZZZ_H:
18846 case AArch64::FTSMUL_ZZZ_S:
18847 case AArch64::FTSSEL_ZZZ_D:
18848 case AArch64::FTSSEL_ZZZ_H:
18849 case AArch64::FTSSEL_ZZZ_S:
18850 case AArch64::LSL_WIDE_ZZZ_B:
18851 case AArch64::LSL_WIDE_ZZZ_H:
18852 case AArch64::LSL_WIDE_ZZZ_S:
18853 case AArch64::LSR_WIDE_ZZZ_B:
18854 case AArch64::LSR_WIDE_ZZZ_H:
18855 case AArch64::LSR_WIDE_ZZZ_S:
18856 case AArch64::MUL_ZZZ_B:
18857 case AArch64::MUL_ZZZ_D:
18858 case AArch64::MUL_ZZZ_H:
18859 case AArch64::MUL_ZZZ_S:
18860 case AArch64::ORR_ZZZ:
18861 case AArch64::PMUL_ZZZ_B:
18862 case AArch64::SMULH_ZZZ_B:
18863 case AArch64::SMULH_ZZZ_D:
18864 case AArch64::SMULH_ZZZ_H:
18865 case AArch64::SMULH_ZZZ_S:
18866 case AArch64::SQADD_ZZZ_B:
18867 case AArch64::SQADD_ZZZ_D:
18868 case AArch64::SQADD_ZZZ_H:
18869 case AArch64::SQADD_ZZZ_S:
18870 case AArch64::SQDMULH_ZZZ_B:
18871 case AArch64::SQDMULH_ZZZ_D:
18872 case AArch64::SQDMULH_ZZZ_H:
18873 case AArch64::SQDMULH_ZZZ_S:
18874 case AArch64::SQRDMULH_ZZZ_B:
18875 case AArch64::SQRDMULH_ZZZ_D:
18876 case AArch64::SQRDMULH_ZZZ_H:
18877 case AArch64::SQRDMULH_ZZZ_S:
18878 case AArch64::SQSUB_ZZZ_B:
18879 case AArch64::SQSUB_ZZZ_D:
18880 case AArch64::SQSUB_ZZZ_H:
18881 case AArch64::SQSUB_ZZZ_S:
18882 case AArch64::SUB_ZZZ_B:
18883 case AArch64::SUB_ZZZ_CPA:
18884 case AArch64::SUB_ZZZ_D:
18885 case AArch64::SUB_ZZZ_H:
18886 case AArch64::SUB_ZZZ_S:
18887 case AArch64::TBL_ZZZZ_B:
18888 case AArch64::TBL_ZZZZ_D:
18889 case AArch64::TBL_ZZZZ_H:
18890 case AArch64::TBL_ZZZZ_S:
18891 case AArch64::TBL_ZZZ_B:
18892 case AArch64::TBL_ZZZ_D:
18893 case AArch64::TBL_ZZZ_H:
18894 case AArch64::TBL_ZZZ_S:
18895 case AArch64::TRN1_ZZZ_B:
18896 case AArch64::TRN1_ZZZ_D:
18897 case AArch64::TRN1_ZZZ_H:
18898 case AArch64::TRN1_ZZZ_Q:
18899 case AArch64::TRN1_ZZZ_S:
18900 case AArch64::TRN2_ZZZ_B:
18901 case AArch64::TRN2_ZZZ_D:
18902 case AArch64::TRN2_ZZZ_H:
18903 case AArch64::TRN2_ZZZ_Q:
18904 case AArch64::TRN2_ZZZ_S:
18905 case AArch64::UMULH_ZZZ_B:
18906 case AArch64::UMULH_ZZZ_D:
18907 case AArch64::UMULH_ZZZ_H:
18908 case AArch64::UMULH_ZZZ_S:
18909 case AArch64::UQADD_ZZZ_B:
18910 case AArch64::UQADD_ZZZ_D:
18911 case AArch64::UQADD_ZZZ_H:
18912 case AArch64::UQADD_ZZZ_S:
18913 case AArch64::UQSUB_ZZZ_B:
18914 case AArch64::UQSUB_ZZZ_D:
18915 case AArch64::UQSUB_ZZZ_H:
18916 case AArch64::UQSUB_ZZZ_S:
18917 case AArch64::UZP1_ZZZ_B:
18918 case AArch64::UZP1_ZZZ_D:
18919 case AArch64::UZP1_ZZZ_H:
18920 case AArch64::UZP1_ZZZ_Q:
18921 case AArch64::UZP1_ZZZ_S:
18922 case AArch64::UZP2_ZZZ_B:
18923 case AArch64::UZP2_ZZZ_D:
18924 case AArch64::UZP2_ZZZ_H:
18925 case AArch64::UZP2_ZZZ_Q:
18926 case AArch64::UZP2_ZZZ_S:
18927 case AArch64::ZIP1_ZZZ_B:
18928 case AArch64::ZIP1_ZZZ_D:
18929 case AArch64::ZIP1_ZZZ_H:
18930 case AArch64::ZIP1_ZZZ_Q:
18931 case AArch64::ZIP1_ZZZ_S:
18932 case AArch64::ZIP2_ZZZ_B:
18933 case AArch64::ZIP2_ZZZ_D:
18934 case AArch64::ZIP2_ZZZ_H:
18935 case AArch64::ZIP2_ZZZ_Q:
18936 case AArch64::ZIP2_ZZZ_S: {
18937 // op: Zd
18938 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18939 op &= UINT64_C(31);
18940 Value |= op;
18941 // op: Zm
18942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18943 op &= UINT64_C(31);
18944 op <<= 16;
18945 Value |= op;
18946 // op: Zn
18947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
18948 op &= UINT64_C(31);
18949 op <<= 5;
18950 Value |= op;
18951 break;
18952 }
18953 case AArch64::TBXQ_ZZZ_B:
18954 case AArch64::TBXQ_ZZZ_D:
18955 case AArch64::TBXQ_ZZZ_H:
18956 case AArch64::TBXQ_ZZZ_S:
18957 case AArch64::TBX_ZZZ_B:
18958 case AArch64::TBX_ZZZ_D:
18959 case AArch64::TBX_ZZZ_H:
18960 case AArch64::TBX_ZZZ_S: {
18961 // op: Zd
18962 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18963 op &= UINT64_C(31);
18964 Value |= op;
18965 // op: Zm
18966 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
18967 op &= UINT64_C(31);
18968 op <<= 16;
18969 Value |= op;
18970 // op: Zn
18971 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
18972 op &= UINT64_C(31);
18973 op <<= 5;
18974 Value |= op;
18975 break;
18976 }
18977 case AArch64::BFCVTN_Z2Z_HtoB:
18978 case AArch64::FCVTNB_Z2Z_StoB:
18979 case AArch64::FCVTNT_Z2Z_StoB:
18980 case AArch64::FCVTN_Z2Z_HtoB:
18981 case AArch64::SQCVTN_Z2Z_StoH:
18982 case AArch64::SQCVTUN_Z2Z_StoH:
18983 case AArch64::UQCVTN_Z2Z_StoH: {
18984 // op: Zd
18985 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
18986 op &= UINT64_C(31);
18987 Value |= op;
18988 // op: Zn
18989 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 1, Fixups, STI);
18990 op &= UINT64_C(15);
18991 op <<= 6;
18992 Value |= op;
18993 break;
18994 }
18995 case AArch64::SQRSHRN_Z2ZI_StoH:
18996 case AArch64::SQRSHRUN_Z2ZI_StoH:
18997 case AArch64::UQRSHRN_Z2ZI_StoH: {
18998 // op: Zd
18999 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19000 op &= UINT64_C(31);
19001 Value |= op;
19002 // op: Zn
19003 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 1, Fixups, STI);
19004 op &= UINT64_C(15);
19005 op <<= 6;
19006 Value |= op;
19007 // op: imm4
19008 op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI);
19009 op &= UINT64_C(15);
19010 op <<= 16;
19011 Value |= op;
19012 break;
19013 }
19014 case AArch64::BF1CVTLT_ZZ_BtoH:
19015 case AArch64::BF1CVT_ZZ_BtoH:
19016 case AArch64::BF2CVTLT_ZZ_BtoH:
19017 case AArch64::BF2CVT_ZZ_BtoH:
19018 case AArch64::F1CVTLT_ZZ_BtoH:
19019 case AArch64::F1CVT_ZZ_BtoH:
19020 case AArch64::F2CVTLT_ZZ_BtoH:
19021 case AArch64::F2CVT_ZZ_BtoH:
19022 case AArch64::FEXPA_ZZ_D:
19023 case AArch64::FEXPA_ZZ_H:
19024 case AArch64::FEXPA_ZZ_S:
19025 case AArch64::FRECPE_ZZ_D:
19026 case AArch64::FRECPE_ZZ_H:
19027 case AArch64::FRECPE_ZZ_S:
19028 case AArch64::FRSQRTE_ZZ_D:
19029 case AArch64::FRSQRTE_ZZ_H:
19030 case AArch64::FRSQRTE_ZZ_S:
19031 case AArch64::MOVPRFX_ZZ:
19032 case AArch64::REV_ZZ_B:
19033 case AArch64::REV_ZZ_D:
19034 case AArch64::REV_ZZ_H:
19035 case AArch64::REV_ZZ_S:
19036 case AArch64::SQXTNB_ZZ_B:
19037 case AArch64::SQXTNB_ZZ_H:
19038 case AArch64::SQXTNB_ZZ_S:
19039 case AArch64::SQXTUNB_ZZ_B:
19040 case AArch64::SQXTUNB_ZZ_H:
19041 case AArch64::SQXTUNB_ZZ_S:
19042 case AArch64::SUNPKHI_ZZ_D:
19043 case AArch64::SUNPKHI_ZZ_H:
19044 case AArch64::SUNPKHI_ZZ_S:
19045 case AArch64::SUNPKLO_ZZ_D:
19046 case AArch64::SUNPKLO_ZZ_H:
19047 case AArch64::SUNPKLO_ZZ_S:
19048 case AArch64::UQXTNB_ZZ_B:
19049 case AArch64::UQXTNB_ZZ_H:
19050 case AArch64::UQXTNB_ZZ_S:
19051 case AArch64::UUNPKHI_ZZ_D:
19052 case AArch64::UUNPKHI_ZZ_H:
19053 case AArch64::UUNPKHI_ZZ_S:
19054 case AArch64::UUNPKLO_ZZ_D:
19055 case AArch64::UUNPKLO_ZZ_H:
19056 case AArch64::UUNPKLO_ZZ_S: {
19057 // op: Zd
19058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19059 op &= UINT64_C(31);
19060 Value |= op;
19061 // op: Zn
19062 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19063 op &= UINT64_C(31);
19064 op <<= 5;
19065 Value |= op;
19066 break;
19067 }
19068 case AArch64::SMULLB_ZZZI_D:
19069 case AArch64::SMULLT_ZZZI_D:
19070 case AArch64::SQDMULLB_ZZZI_D:
19071 case AArch64::SQDMULLT_ZZZI_D:
19072 case AArch64::UMULLB_ZZZI_D:
19073 case AArch64::UMULLT_ZZZI_D: {
19074 // op: Zd
19075 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19076 op &= UINT64_C(31);
19077 Value |= op;
19078 // op: Zn
19079 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19080 op &= UINT64_C(31);
19081 op <<= 5;
19082 Value |= op;
19083 // op: Zm
19084 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19085 op &= UINT64_C(15);
19086 op <<= 16;
19087 Value |= op;
19088 // op: iop
19089 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19090 Value |= (op & UINT64_C(2)) << 19;
19091 Value |= (op & UINT64_C(1)) << 11;
19092 break;
19093 }
19094 case AArch64::FMUL_ZZZI_D:
19095 case AArch64::MUL_ZZZI_D:
19096 case AArch64::SQDMULH_ZZZI_D:
19097 case AArch64::SQRDMULH_ZZZI_D: {
19098 // op: Zd
19099 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19100 op &= UINT64_C(31);
19101 Value |= op;
19102 // op: Zn
19103 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19104 op &= UINT64_C(31);
19105 op <<= 5;
19106 Value |= op;
19107 // op: Zm
19108 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19109 op &= UINT64_C(15);
19110 op <<= 16;
19111 Value |= op;
19112 // op: iop
19113 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19114 op &= UINT64_C(1);
19115 op <<= 20;
19116 Value |= op;
19117 break;
19118 }
19119 case AArch64::ADDHNB_ZZZ_B:
19120 case AArch64::ADDHNB_ZZZ_H:
19121 case AArch64::ADDHNB_ZZZ_S:
19122 case AArch64::ADR_LSL_ZZZ_D_0:
19123 case AArch64::ADR_LSL_ZZZ_D_1:
19124 case AArch64::ADR_LSL_ZZZ_D_2:
19125 case AArch64::ADR_LSL_ZZZ_D_3:
19126 case AArch64::ADR_LSL_ZZZ_S_0:
19127 case AArch64::ADR_LSL_ZZZ_S_1:
19128 case AArch64::ADR_LSL_ZZZ_S_2:
19129 case AArch64::ADR_LSL_ZZZ_S_3:
19130 case AArch64::ADR_SXTW_ZZZ_D_0:
19131 case AArch64::ADR_SXTW_ZZZ_D_1:
19132 case AArch64::ADR_SXTW_ZZZ_D_2:
19133 case AArch64::ADR_SXTW_ZZZ_D_3:
19134 case AArch64::ADR_UXTW_ZZZ_D_0:
19135 case AArch64::ADR_UXTW_ZZZ_D_1:
19136 case AArch64::ADR_UXTW_ZZZ_D_2:
19137 case AArch64::ADR_UXTW_ZZZ_D_3:
19138 case AArch64::BDEP_ZZZ_B:
19139 case AArch64::BDEP_ZZZ_D:
19140 case AArch64::BDEP_ZZZ_H:
19141 case AArch64::BDEP_ZZZ_S:
19142 case AArch64::BEXT_ZZZ_B:
19143 case AArch64::BEXT_ZZZ_D:
19144 case AArch64::BEXT_ZZZ_H:
19145 case AArch64::BEXT_ZZZ_S:
19146 case AArch64::BGRP_ZZZ_B:
19147 case AArch64::BGRP_ZZZ_D:
19148 case AArch64::BGRP_ZZZ_H:
19149 case AArch64::BGRP_ZZZ_S:
19150 case AArch64::HISTSEG_ZZZ:
19151 case AArch64::PMULLB_ZZZ_D:
19152 case AArch64::PMULLB_ZZZ_H:
19153 case AArch64::PMULLB_ZZZ_Q:
19154 case AArch64::PMULLT_ZZZ_D:
19155 case AArch64::PMULLT_ZZZ_H:
19156 case AArch64::PMULLT_ZZZ_Q:
19157 case AArch64::RADDHNB_ZZZ_B:
19158 case AArch64::RADDHNB_ZZZ_H:
19159 case AArch64::RADDHNB_ZZZ_S:
19160 case AArch64::RAX1_ZZZ_D:
19161 case AArch64::RSUBHNB_ZZZ_B:
19162 case AArch64::RSUBHNB_ZZZ_H:
19163 case AArch64::RSUBHNB_ZZZ_S:
19164 case AArch64::SABDLB_ZZZ_D:
19165 case AArch64::SABDLB_ZZZ_H:
19166 case AArch64::SABDLB_ZZZ_S:
19167 case AArch64::SABDLT_ZZZ_D:
19168 case AArch64::SABDLT_ZZZ_H:
19169 case AArch64::SABDLT_ZZZ_S:
19170 case AArch64::SADDLBT_ZZZ_D:
19171 case AArch64::SADDLBT_ZZZ_H:
19172 case AArch64::SADDLBT_ZZZ_S:
19173 case AArch64::SADDLB_ZZZ_D:
19174 case AArch64::SADDLB_ZZZ_H:
19175 case AArch64::SADDLB_ZZZ_S:
19176 case AArch64::SADDLT_ZZZ_D:
19177 case AArch64::SADDLT_ZZZ_H:
19178 case AArch64::SADDLT_ZZZ_S:
19179 case AArch64::SADDWB_ZZZ_D:
19180 case AArch64::SADDWB_ZZZ_H:
19181 case AArch64::SADDWB_ZZZ_S:
19182 case AArch64::SADDWT_ZZZ_D:
19183 case AArch64::SADDWT_ZZZ_H:
19184 case AArch64::SADDWT_ZZZ_S:
19185 case AArch64::SM4EKEY_ZZZ_S:
19186 case AArch64::SMULLB_ZZZ_D:
19187 case AArch64::SMULLB_ZZZ_H:
19188 case AArch64::SMULLB_ZZZ_S:
19189 case AArch64::SMULLT_ZZZ_D:
19190 case AArch64::SMULLT_ZZZ_H:
19191 case AArch64::SMULLT_ZZZ_S:
19192 case AArch64::SQDMULLB_ZZZ_D:
19193 case AArch64::SQDMULLB_ZZZ_H:
19194 case AArch64::SQDMULLB_ZZZ_S:
19195 case AArch64::SQDMULLT_ZZZ_D:
19196 case AArch64::SQDMULLT_ZZZ_H:
19197 case AArch64::SQDMULLT_ZZZ_S:
19198 case AArch64::SSUBLBT_ZZZ_D:
19199 case AArch64::SSUBLBT_ZZZ_H:
19200 case AArch64::SSUBLBT_ZZZ_S:
19201 case AArch64::SSUBLB_ZZZ_D:
19202 case AArch64::SSUBLB_ZZZ_H:
19203 case AArch64::SSUBLB_ZZZ_S:
19204 case AArch64::SSUBLTB_ZZZ_D:
19205 case AArch64::SSUBLTB_ZZZ_H:
19206 case AArch64::SSUBLTB_ZZZ_S:
19207 case AArch64::SSUBLT_ZZZ_D:
19208 case AArch64::SSUBLT_ZZZ_H:
19209 case AArch64::SSUBLT_ZZZ_S:
19210 case AArch64::SSUBWB_ZZZ_D:
19211 case AArch64::SSUBWB_ZZZ_H:
19212 case AArch64::SSUBWB_ZZZ_S:
19213 case AArch64::SSUBWT_ZZZ_D:
19214 case AArch64::SSUBWT_ZZZ_H:
19215 case AArch64::SSUBWT_ZZZ_S:
19216 case AArch64::SUBHNB_ZZZ_B:
19217 case AArch64::SUBHNB_ZZZ_H:
19218 case AArch64::SUBHNB_ZZZ_S:
19219 case AArch64::TBLQ_ZZZ_B:
19220 case AArch64::TBLQ_ZZZ_D:
19221 case AArch64::TBLQ_ZZZ_H:
19222 case AArch64::TBLQ_ZZZ_S:
19223 case AArch64::UABDLB_ZZZ_D:
19224 case AArch64::UABDLB_ZZZ_H:
19225 case AArch64::UABDLB_ZZZ_S:
19226 case AArch64::UABDLT_ZZZ_D:
19227 case AArch64::UABDLT_ZZZ_H:
19228 case AArch64::UABDLT_ZZZ_S:
19229 case AArch64::UADDLB_ZZZ_D:
19230 case AArch64::UADDLB_ZZZ_H:
19231 case AArch64::UADDLB_ZZZ_S:
19232 case AArch64::UADDLT_ZZZ_D:
19233 case AArch64::UADDLT_ZZZ_H:
19234 case AArch64::UADDLT_ZZZ_S:
19235 case AArch64::UADDWB_ZZZ_D:
19236 case AArch64::UADDWB_ZZZ_H:
19237 case AArch64::UADDWB_ZZZ_S:
19238 case AArch64::UADDWT_ZZZ_D:
19239 case AArch64::UADDWT_ZZZ_H:
19240 case AArch64::UADDWT_ZZZ_S:
19241 case AArch64::UMULLB_ZZZ_D:
19242 case AArch64::UMULLB_ZZZ_H:
19243 case AArch64::UMULLB_ZZZ_S:
19244 case AArch64::UMULLT_ZZZ_D:
19245 case AArch64::UMULLT_ZZZ_H:
19246 case AArch64::UMULLT_ZZZ_S:
19247 case AArch64::USUBLB_ZZZ_D:
19248 case AArch64::USUBLB_ZZZ_H:
19249 case AArch64::USUBLB_ZZZ_S:
19250 case AArch64::USUBLT_ZZZ_D:
19251 case AArch64::USUBLT_ZZZ_H:
19252 case AArch64::USUBLT_ZZZ_S:
19253 case AArch64::USUBWB_ZZZ_D:
19254 case AArch64::USUBWB_ZZZ_H:
19255 case AArch64::USUBWB_ZZZ_S:
19256 case AArch64::USUBWT_ZZZ_D:
19257 case AArch64::USUBWT_ZZZ_H:
19258 case AArch64::USUBWT_ZZZ_S:
19259 case AArch64::UZPQ1_ZZZ_B:
19260 case AArch64::UZPQ1_ZZZ_D:
19261 case AArch64::UZPQ1_ZZZ_H:
19262 case AArch64::UZPQ1_ZZZ_S:
19263 case AArch64::UZPQ2_ZZZ_B:
19264 case AArch64::UZPQ2_ZZZ_D:
19265 case AArch64::UZPQ2_ZZZ_H:
19266 case AArch64::UZPQ2_ZZZ_S:
19267 case AArch64::ZIPQ1_ZZZ_B:
19268 case AArch64::ZIPQ1_ZZZ_D:
19269 case AArch64::ZIPQ1_ZZZ_H:
19270 case AArch64::ZIPQ1_ZZZ_S:
19271 case AArch64::ZIPQ2_ZZZ_B:
19272 case AArch64::ZIPQ2_ZZZ_D:
19273 case AArch64::ZIPQ2_ZZZ_H:
19274 case AArch64::ZIPQ2_ZZZ_S: {
19275 // op: Zd
19276 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19277 op &= UINT64_C(31);
19278 Value |= op;
19279 // op: Zn
19280 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19281 op &= UINT64_C(31);
19282 op <<= 5;
19283 Value |= op;
19284 // op: Zm
19285 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19286 op &= UINT64_C(31);
19287 op <<= 16;
19288 Value |= op;
19289 break;
19290 }
19291 case AArch64::LUTI2_ZZZI_H: {
19292 // op: Zd
19293 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19294 op &= UINT64_C(31);
19295 Value |= op;
19296 // op: Zn
19297 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19298 op &= UINT64_C(31);
19299 op <<= 5;
19300 Value |= op;
19301 // op: Zm
19302 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19303 op &= UINT64_C(31);
19304 op <<= 16;
19305 Value |= op;
19306 // op: idx
19307 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19308 Value |= (op & UINT64_C(6)) << 21;
19309 Value |= (op & UINT64_C(1)) << 12;
19310 break;
19311 }
19312 case AArch64::LUTI4_ZZZI_B: {
19313 // op: Zd
19314 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19315 op &= UINT64_C(31);
19316 Value |= op;
19317 // op: Zn
19318 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19319 op &= UINT64_C(31);
19320 op <<= 5;
19321 Value |= op;
19322 // op: Zm
19323 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19324 op &= UINT64_C(31);
19325 op <<= 16;
19326 Value |= op;
19327 // op: idx
19328 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19329 op &= UINT64_C(1);
19330 op <<= 23;
19331 Value |= op;
19332 break;
19333 }
19334 case AArch64::LUTI2_ZZZI_B:
19335 case AArch64::LUTI4_Z2ZZI_H:
19336 case AArch64::LUTI4_ZZZI_H: {
19337 // op: Zd
19338 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19339 op &= UINT64_C(31);
19340 Value |= op;
19341 // op: Zn
19342 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19343 op &= UINT64_C(31);
19344 op <<= 5;
19345 Value |= op;
19346 // op: Zm
19347 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19348 op &= UINT64_C(31);
19349 op <<= 16;
19350 Value |= op;
19351 // op: idx
19352 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19353 op &= UINT64_C(3);
19354 op <<= 22;
19355 Value |= op;
19356 break;
19357 }
19358 case AArch64::BFMUL_ZZZI:
19359 case AArch64::FMUL_ZZZI_H:
19360 case AArch64::MUL_ZZZI_H:
19361 case AArch64::SQDMULH_ZZZI_H:
19362 case AArch64::SQRDMULH_ZZZI_H: {
19363 // op: Zd
19364 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19365 op &= UINT64_C(31);
19366 Value |= op;
19367 // op: Zn
19368 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19369 op &= UINT64_C(31);
19370 op <<= 5;
19371 Value |= op;
19372 // op: Zm
19373 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19374 op &= UINT64_C(7);
19375 op <<= 16;
19376 Value |= op;
19377 // op: iop
19378 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19379 Value |= (op & UINT64_C(4)) << 20;
19380 Value |= (op & UINT64_C(3)) << 19;
19381 break;
19382 }
19383 case AArch64::SMULLB_ZZZI_S:
19384 case AArch64::SMULLT_ZZZI_S:
19385 case AArch64::SQDMULLB_ZZZI_S:
19386 case AArch64::SQDMULLT_ZZZI_S:
19387 case AArch64::UMULLB_ZZZI_S:
19388 case AArch64::UMULLT_ZZZI_S: {
19389 // op: Zd
19390 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19391 op &= UINT64_C(31);
19392 Value |= op;
19393 // op: Zn
19394 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19395 op &= UINT64_C(31);
19396 op <<= 5;
19397 Value |= op;
19398 // op: Zm
19399 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19400 op &= UINT64_C(7);
19401 op <<= 16;
19402 Value |= op;
19403 // op: iop
19404 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19405 Value |= (op & UINT64_C(6)) << 18;
19406 Value |= (op & UINT64_C(1)) << 11;
19407 break;
19408 }
19409 case AArch64::FMUL_ZZZI_S:
19410 case AArch64::MUL_ZZZI_S:
19411 case AArch64::SQDMULH_ZZZI_S:
19412 case AArch64::SQRDMULH_ZZZI_S: {
19413 // op: Zd
19414 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19415 op &= UINT64_C(31);
19416 Value |= op;
19417 // op: Zn
19418 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19419 op &= UINT64_C(31);
19420 op <<= 5;
19421 Value |= op;
19422 // op: Zm
19423 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19424 op &= UINT64_C(7);
19425 op <<= 16;
19426 Value |= op;
19427 // op: iop
19428 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19429 op &= UINT64_C(3);
19430 op <<= 19;
19431 Value |= op;
19432 break;
19433 }
19434 case AArch64::DUP_ZZI_S: {
19435 // op: Zd
19436 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19437 op &= UINT64_C(31);
19438 Value |= op;
19439 // op: Zn
19440 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19441 op &= UINT64_C(31);
19442 op <<= 5;
19443 Value |= op;
19444 // op: idx
19445 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19446 Value |= (op & UINT64_C(12)) << 20;
19447 Value |= (op & UINT64_C(3)) << 19;
19448 break;
19449 }
19450 case AArch64::DUP_ZZI_H: {
19451 // op: Zd
19452 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19453 op &= UINT64_C(31);
19454 Value |= op;
19455 // op: Zn
19456 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19457 op &= UINT64_C(31);
19458 op <<= 5;
19459 Value |= op;
19460 // op: idx
19461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19462 Value |= (op & UINT64_C(24)) << 19;
19463 Value |= (op & UINT64_C(7)) << 18;
19464 break;
19465 }
19466 case AArch64::DUP_ZZI_B: {
19467 // op: Zd
19468 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19469 op &= UINT64_C(31);
19470 Value |= op;
19471 // op: Zn
19472 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19473 op &= UINT64_C(31);
19474 op <<= 5;
19475 Value |= op;
19476 // op: idx
19477 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19478 Value |= (op & UINT64_C(48)) << 18;
19479 Value |= (op & UINT64_C(15)) << 17;
19480 break;
19481 }
19482 case AArch64::DUP_ZZI_D: {
19483 // op: Zd
19484 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19485 op &= UINT64_C(31);
19486 Value |= op;
19487 // op: Zn
19488 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19489 op &= UINT64_C(31);
19490 op <<= 5;
19491 Value |= op;
19492 // op: idx
19493 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19494 Value |= (op & UINT64_C(6)) << 21;
19495 Value |= (op & UINT64_C(1)) << 20;
19496 break;
19497 }
19498 case AArch64::DUP_ZZI_Q: {
19499 // op: Zd
19500 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19501 op &= UINT64_C(31);
19502 Value |= op;
19503 // op: Zn
19504 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19505 op &= UINT64_C(31);
19506 op <<= 5;
19507 Value |= op;
19508 // op: idx
19509 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19510 op &= UINT64_C(3);
19511 op <<= 22;
19512 Value |= op;
19513 break;
19514 }
19515 case AArch64::LSL_ZZI_H:
19516 case AArch64::SSHLLB_ZZI_S:
19517 case AArch64::SSHLLT_ZZI_S:
19518 case AArch64::USHLLB_ZZI_S:
19519 case AArch64::USHLLT_ZZI_S: {
19520 // op: Zd
19521 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19522 op &= UINT64_C(31);
19523 Value |= op;
19524 // op: Zn
19525 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19526 op &= UINT64_C(31);
19527 op <<= 5;
19528 Value |= op;
19529 // op: imm
19530 op = getVecShiftL16OpValue(MI, OpIdx: 2, Fixups, STI);
19531 op &= UINT64_C(15);
19532 op <<= 16;
19533 Value |= op;
19534 break;
19535 }
19536 case AArch64::LSL_ZZI_S:
19537 case AArch64::SSHLLB_ZZI_D:
19538 case AArch64::SSHLLT_ZZI_D:
19539 case AArch64::USHLLB_ZZI_D:
19540 case AArch64::USHLLT_ZZI_D: {
19541 // op: Zd
19542 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19543 op &= UINT64_C(31);
19544 Value |= op;
19545 // op: Zn
19546 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19547 op &= UINT64_C(31);
19548 op <<= 5;
19549 Value |= op;
19550 // op: imm
19551 op = getVecShiftL32OpValue(MI, OpIdx: 2, Fixups, STI);
19552 op &= UINT64_C(31);
19553 op <<= 16;
19554 Value |= op;
19555 break;
19556 }
19557 case AArch64::LSL_ZZI_D: {
19558 // op: Zd
19559 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19560 op &= UINT64_C(31);
19561 Value |= op;
19562 // op: Zn
19563 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19564 op &= UINT64_C(31);
19565 op <<= 5;
19566 Value |= op;
19567 // op: imm
19568 op = getVecShiftL64OpValue(MI, OpIdx: 2, Fixups, STI);
19569 Value |= (op & UINT64_C(32)) << 17;
19570 Value |= (op & UINT64_C(31)) << 16;
19571 break;
19572 }
19573 case AArch64::LSL_ZZI_B:
19574 case AArch64::SSHLLB_ZZI_H:
19575 case AArch64::SSHLLT_ZZI_H:
19576 case AArch64::USHLLB_ZZI_H:
19577 case AArch64::USHLLT_ZZI_H: {
19578 // op: Zd
19579 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19580 op &= UINT64_C(31);
19581 Value |= op;
19582 // op: Zn
19583 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19584 op &= UINT64_C(31);
19585 op <<= 5;
19586 Value |= op;
19587 // op: imm
19588 op = getVecShiftL8OpValue(MI, OpIdx: 2, Fixups, STI);
19589 op &= UINT64_C(7);
19590 op <<= 16;
19591 Value |= op;
19592 break;
19593 }
19594 case AArch64::ASR_ZZI_H:
19595 case AArch64::LSR_ZZI_H:
19596 case AArch64::RSHRNB_ZZI_H:
19597 case AArch64::SHRNB_ZZI_H:
19598 case AArch64::SQRSHRNB_ZZI_H:
19599 case AArch64::SQRSHRUNB_ZZI_H:
19600 case AArch64::SQSHRNB_ZZI_H:
19601 case AArch64::SQSHRUNB_ZZI_H:
19602 case AArch64::UQRSHRNB_ZZI_H:
19603 case AArch64::UQSHRNB_ZZI_H: {
19604 // op: Zd
19605 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19606 op &= UINT64_C(31);
19607 Value |= op;
19608 // op: Zn
19609 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19610 op &= UINT64_C(31);
19611 op <<= 5;
19612 Value |= op;
19613 // op: imm
19614 op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI);
19615 op &= UINT64_C(15);
19616 op <<= 16;
19617 Value |= op;
19618 break;
19619 }
19620 case AArch64::ASR_ZZI_S:
19621 case AArch64::LSR_ZZI_S:
19622 case AArch64::RSHRNB_ZZI_S:
19623 case AArch64::SHRNB_ZZI_S:
19624 case AArch64::SQRSHRNB_ZZI_S:
19625 case AArch64::SQRSHRUNB_ZZI_S:
19626 case AArch64::SQSHRNB_ZZI_S:
19627 case AArch64::SQSHRUNB_ZZI_S:
19628 case AArch64::UQRSHRNB_ZZI_S:
19629 case AArch64::UQSHRNB_ZZI_S: {
19630 // op: Zd
19631 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19632 op &= UINT64_C(31);
19633 Value |= op;
19634 // op: Zn
19635 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19636 op &= UINT64_C(31);
19637 op <<= 5;
19638 Value |= op;
19639 // op: imm
19640 op = getVecShiftR32OpValue(MI, OpIdx: 2, Fixups, STI);
19641 op &= UINT64_C(31);
19642 op <<= 16;
19643 Value |= op;
19644 break;
19645 }
19646 case AArch64::ASR_ZZI_D:
19647 case AArch64::LSR_ZZI_D: {
19648 // op: Zd
19649 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19650 op &= UINT64_C(31);
19651 Value |= op;
19652 // op: Zn
19653 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19654 op &= UINT64_C(31);
19655 op <<= 5;
19656 Value |= op;
19657 // op: imm
19658 op = getVecShiftR64OpValue(MI, OpIdx: 2, Fixups, STI);
19659 Value |= (op & UINT64_C(32)) << 17;
19660 Value |= (op & UINT64_C(31)) << 16;
19661 break;
19662 }
19663 case AArch64::ASR_ZZI_B:
19664 case AArch64::LSR_ZZI_B:
19665 case AArch64::RSHRNB_ZZI_B:
19666 case AArch64::SHRNB_ZZI_B:
19667 case AArch64::SQRSHRNB_ZZI_B:
19668 case AArch64::SQRSHRUNB_ZZI_B:
19669 case AArch64::SQSHRNB_ZZI_B:
19670 case AArch64::SQSHRUNB_ZZI_B:
19671 case AArch64::UQRSHRNB_ZZI_B:
19672 case AArch64::UQSHRNB_ZZI_B: {
19673 // op: Zd
19674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19675 op &= UINT64_C(31);
19676 Value |= op;
19677 // op: Zn
19678 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19679 op &= UINT64_C(31);
19680 op <<= 5;
19681 Value |= op;
19682 // op: imm
19683 op = getVecShiftR8OpValue(MI, OpIdx: 2, Fixups, STI);
19684 op &= UINT64_C(7);
19685 op <<= 16;
19686 Value |= op;
19687 break;
19688 }
19689 case AArch64::EXT_ZZI_B: {
19690 // op: Zd
19691 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19692 op &= UINT64_C(31);
19693 Value |= op;
19694 // op: Zn
19695 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19696 op &= UINT64_C(31);
19697 op <<= 5;
19698 Value |= op;
19699 // op: imm8
19700 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19701 Value |= (op & UINT64_C(248)) << 13;
19702 Value |= (op & UINT64_C(7)) << 10;
19703 break;
19704 }
19705 case AArch64::DUPQ_ZZI_D: {
19706 // op: Zd
19707 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19708 op &= UINT64_C(31);
19709 Value |= op;
19710 // op: Zn
19711 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19712 op &= UINT64_C(31);
19713 op <<= 5;
19714 Value |= op;
19715 // op: index
19716 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19717 op &= UINT64_C(1);
19718 op <<= 20;
19719 Value |= op;
19720 break;
19721 }
19722 case AArch64::DUPQ_ZZI_B: {
19723 // op: Zd
19724 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19725 op &= UINT64_C(31);
19726 Value |= op;
19727 // op: Zn
19728 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19729 op &= UINT64_C(31);
19730 op <<= 5;
19731 Value |= op;
19732 // op: index
19733 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19734 op &= UINT64_C(15);
19735 op <<= 17;
19736 Value |= op;
19737 break;
19738 }
19739 case AArch64::DUPQ_ZZI_S: {
19740 // op: Zd
19741 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19742 op &= UINT64_C(31);
19743 Value |= op;
19744 // op: Zn
19745 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19746 op &= UINT64_C(31);
19747 op <<= 5;
19748 Value |= op;
19749 // op: index
19750 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19751 op &= UINT64_C(3);
19752 op <<= 19;
19753 Value |= op;
19754 break;
19755 }
19756 case AArch64::DUPQ_ZZI_H: {
19757 // op: Zd
19758 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19759 op &= UINT64_C(31);
19760 Value |= op;
19761 // op: Zn
19762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19763 op &= UINT64_C(31);
19764 op <<= 5;
19765 Value |= op;
19766 // op: index
19767 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19768 op &= UINT64_C(7);
19769 op <<= 18;
19770 Value |= op;
19771 break;
19772 }
19773 case AArch64::SQXTNT_ZZ_B:
19774 case AArch64::SQXTNT_ZZ_H:
19775 case AArch64::SQXTNT_ZZ_S:
19776 case AArch64::SQXTUNT_ZZ_B:
19777 case AArch64::SQXTUNT_ZZ_H:
19778 case AArch64::SQXTUNT_ZZ_S:
19779 case AArch64::UQXTNT_ZZ_B:
19780 case AArch64::UQXTNT_ZZ_H:
19781 case AArch64::UQXTNT_ZZ_S: {
19782 // op: Zd
19783 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19784 op &= UINT64_C(31);
19785 Value |= op;
19786 // op: Zn
19787 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19788 op &= UINT64_C(31);
19789 op <<= 5;
19790 Value |= op;
19791 break;
19792 }
19793 case AArch64::HISTCNT_ZPzZZ_D:
19794 case AArch64::HISTCNT_ZPzZZ_S: {
19795 // op: Zd
19796 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19797 op &= UINT64_C(31);
19798 Value |= op;
19799 // op: Zn
19800 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19801 op &= UINT64_C(31);
19802 op <<= 5;
19803 Value |= op;
19804 // op: Pg
19805 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
19806 op &= UINT64_C(7);
19807 op <<= 10;
19808 Value |= op;
19809 // op: Zm
19810 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19811 op &= UINT64_C(31);
19812 op <<= 16;
19813 Value |= op;
19814 break;
19815 }
19816 case AArch64::ADDHNT_ZZZ_B:
19817 case AArch64::ADDHNT_ZZZ_H:
19818 case AArch64::ADDHNT_ZZZ_S:
19819 case AArch64::EORBT_ZZZ_B:
19820 case AArch64::EORBT_ZZZ_D:
19821 case AArch64::EORBT_ZZZ_H:
19822 case AArch64::EORBT_ZZZ_S:
19823 case AArch64::EORTB_ZZZ_B:
19824 case AArch64::EORTB_ZZZ_D:
19825 case AArch64::EORTB_ZZZ_H:
19826 case AArch64::EORTB_ZZZ_S:
19827 case AArch64::RADDHNT_ZZZ_B:
19828 case AArch64::RADDHNT_ZZZ_H:
19829 case AArch64::RADDHNT_ZZZ_S:
19830 case AArch64::RSUBHNT_ZZZ_B:
19831 case AArch64::RSUBHNT_ZZZ_H:
19832 case AArch64::RSUBHNT_ZZZ_S:
19833 case AArch64::SUBHNT_ZZZ_B:
19834 case AArch64::SUBHNT_ZZZ_H:
19835 case AArch64::SUBHNT_ZZZ_S: {
19836 // op: Zd
19837 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19838 op &= UINT64_C(31);
19839 Value |= op;
19840 // op: Zn
19841 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19842 op &= UINT64_C(31);
19843 op <<= 5;
19844 Value |= op;
19845 // op: Zm
19846 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
19847 op &= UINT64_C(31);
19848 op <<= 16;
19849 Value |= op;
19850 break;
19851 }
19852 case AArch64::SLI_ZZI_H: {
19853 // op: Zd
19854 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19855 op &= UINT64_C(31);
19856 Value |= op;
19857 // op: Zn
19858 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19859 op &= UINT64_C(31);
19860 op <<= 5;
19861 Value |= op;
19862 // op: imm
19863 op = getVecShiftL16OpValue(MI, OpIdx: 3, Fixups, STI);
19864 op &= UINT64_C(15);
19865 op <<= 16;
19866 Value |= op;
19867 break;
19868 }
19869 case AArch64::SLI_ZZI_S: {
19870 // op: Zd
19871 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19872 op &= UINT64_C(31);
19873 Value |= op;
19874 // op: Zn
19875 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19876 op &= UINT64_C(31);
19877 op <<= 5;
19878 Value |= op;
19879 // op: imm
19880 op = getVecShiftL32OpValue(MI, OpIdx: 3, Fixups, STI);
19881 op &= UINT64_C(31);
19882 op <<= 16;
19883 Value |= op;
19884 break;
19885 }
19886 case AArch64::SLI_ZZI_D: {
19887 // op: Zd
19888 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19889 op &= UINT64_C(31);
19890 Value |= op;
19891 // op: Zn
19892 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19893 op &= UINT64_C(31);
19894 op <<= 5;
19895 Value |= op;
19896 // op: imm
19897 op = getVecShiftL64OpValue(MI, OpIdx: 3, Fixups, STI);
19898 Value |= (op & UINT64_C(32)) << 17;
19899 Value |= (op & UINT64_C(31)) << 16;
19900 break;
19901 }
19902 case AArch64::SLI_ZZI_B: {
19903 // op: Zd
19904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19905 op &= UINT64_C(31);
19906 Value |= op;
19907 // op: Zn
19908 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19909 op &= UINT64_C(31);
19910 op <<= 5;
19911 Value |= op;
19912 // op: imm
19913 op = getVecShiftL8OpValue(MI, OpIdx: 3, Fixups, STI);
19914 op &= UINT64_C(7);
19915 op <<= 16;
19916 Value |= op;
19917 break;
19918 }
19919 case AArch64::RSHRNT_ZZI_H:
19920 case AArch64::SHRNT_ZZI_H:
19921 case AArch64::SQRSHRNT_ZZI_H:
19922 case AArch64::SQRSHRUNT_ZZI_H:
19923 case AArch64::SQSHRNT_ZZI_H:
19924 case AArch64::SQSHRUNT_ZZI_H:
19925 case AArch64::SRI_ZZI_H:
19926 case AArch64::UQRSHRNT_ZZI_H:
19927 case AArch64::UQSHRNT_ZZI_H: {
19928 // op: Zd
19929 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19930 op &= UINT64_C(31);
19931 Value |= op;
19932 // op: Zn
19933 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19934 op &= UINT64_C(31);
19935 op <<= 5;
19936 Value |= op;
19937 // op: imm
19938 op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI);
19939 op &= UINT64_C(15);
19940 op <<= 16;
19941 Value |= op;
19942 break;
19943 }
19944 case AArch64::RSHRNT_ZZI_S:
19945 case AArch64::SHRNT_ZZI_S:
19946 case AArch64::SQRSHRNT_ZZI_S:
19947 case AArch64::SQRSHRUNT_ZZI_S:
19948 case AArch64::SQSHRNT_ZZI_S:
19949 case AArch64::SQSHRUNT_ZZI_S:
19950 case AArch64::SRI_ZZI_S:
19951 case AArch64::UQRSHRNT_ZZI_S:
19952 case AArch64::UQSHRNT_ZZI_S: {
19953 // op: Zd
19954 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19955 op &= UINT64_C(31);
19956 Value |= op;
19957 // op: Zn
19958 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19959 op &= UINT64_C(31);
19960 op <<= 5;
19961 Value |= op;
19962 // op: imm
19963 op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI);
19964 op &= UINT64_C(31);
19965 op <<= 16;
19966 Value |= op;
19967 break;
19968 }
19969 case AArch64::SRI_ZZI_D: {
19970 // op: Zd
19971 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19972 op &= UINT64_C(31);
19973 Value |= op;
19974 // op: Zn
19975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
19976 op &= UINT64_C(31);
19977 op <<= 5;
19978 Value |= op;
19979 // op: imm
19980 op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI);
19981 Value |= (op & UINT64_C(32)) << 17;
19982 Value |= (op & UINT64_C(31)) << 16;
19983 break;
19984 }
19985 case AArch64::RSHRNT_ZZI_B:
19986 case AArch64::SHRNT_ZZI_B:
19987 case AArch64::SQRSHRNT_ZZI_B:
19988 case AArch64::SQRSHRUNT_ZZI_B:
19989 case AArch64::SQSHRNT_ZZI_B:
19990 case AArch64::SQSHRUNT_ZZI_B:
19991 case AArch64::SRI_ZZI_B:
19992 case AArch64::UQRSHRNT_ZZI_B:
19993 case AArch64::UQSHRNT_ZZI_B: {
19994 // op: Zd
19995 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
19996 op &= UINT64_C(31);
19997 Value |= op;
19998 // op: Zn
19999 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20000 op &= UINT64_C(31);
20001 op <<= 5;
20002 Value |= op;
20003 // op: imm
20004 op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI);
20005 op &= UINT64_C(7);
20006 op <<= 16;
20007 Value |= op;
20008 break;
20009 }
20010 case AArch64::FCVTLT_ZPmZ_HtoS:
20011 case AArch64::FCVTLT_ZPmZ_StoD:
20012 case AArch64::FCVTNT_ZPmZ_DtoS:
20013 case AArch64::FCVTNT_ZPmZ_StoH:
20014 case AArch64::FCVTXNT_ZPmZ_DtoS: {
20015 // op: Zd
20016 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20017 op &= UINT64_C(31);
20018 Value |= op;
20019 // op: Zn
20020 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20021 op &= UINT64_C(31);
20022 op <<= 5;
20023 Value |= op;
20024 // op: Pg
20025 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20026 op &= UINT64_C(7);
20027 op <<= 10;
20028 Value |= op;
20029 break;
20030 }
20031 case AArch64::DUP_ZI_B:
20032 case AArch64::DUP_ZI_D:
20033 case AArch64::DUP_ZI_H:
20034 case AArch64::DUP_ZI_S: {
20035 // op: Zd
20036 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20037 op &= UINT64_C(31);
20038 Value |= op;
20039 // op: imm
20040 op = getImm8OptLsl(MI, OpIdx: 1, Fixups, STI);
20041 op &= UINT64_C(511);
20042 op <<= 5;
20043 Value |= op;
20044 break;
20045 }
20046 case AArch64::INDEX_II_B:
20047 case AArch64::INDEX_II_D:
20048 case AArch64::INDEX_II_H:
20049 case AArch64::INDEX_II_S: {
20050 // op: Zd
20051 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20052 op &= UINT64_C(31);
20053 Value |= op;
20054 // op: imm5
20055 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20056 op &= UINT64_C(31);
20057 op <<= 5;
20058 Value |= op;
20059 // op: imm5b
20060 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20061 op &= UINT64_C(31);
20062 op <<= 16;
20063 Value |= op;
20064 break;
20065 }
20066 case AArch64::FDUP_ZI_D:
20067 case AArch64::FDUP_ZI_H:
20068 case AArch64::FDUP_ZI_S: {
20069 // op: Zd
20070 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20071 op &= UINT64_C(31);
20072 Value |= op;
20073 // op: imm8
20074 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20075 op &= UINT64_C(255);
20076 op <<= 5;
20077 Value |= op;
20078 break;
20079 }
20080 case AArch64::DUPM_ZI: {
20081 // op: Zd
20082 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20083 op &= UINT64_C(31);
20084 Value |= op;
20085 // op: imms
20086 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20087 op &= UINT64_C(8191);
20088 op <<= 5;
20089 Value |= op;
20090 break;
20091 }
20092 case AArch64::FCMLA_ZPmZZ_D:
20093 case AArch64::FCMLA_ZPmZZ_H:
20094 case AArch64::FCMLA_ZPmZZ_S: {
20095 // op: Zda
20096 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20097 op &= UINT64_C(31);
20098 Value |= op;
20099 // op: Pg
20100 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20101 op &= UINT64_C(7);
20102 op <<= 10;
20103 Value |= op;
20104 // op: Zn
20105 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20106 op &= UINT64_C(31);
20107 op <<= 5;
20108 Value |= op;
20109 // op: Zm
20110 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20111 op &= UINT64_C(31);
20112 op <<= 16;
20113 Value |= op;
20114 // op: imm
20115 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
20116 op &= UINT64_C(3);
20117 op <<= 13;
20118 Value |= op;
20119 break;
20120 }
20121 case AArch64::SMLALB_ZZZI_D:
20122 case AArch64::SMLALT_ZZZI_D:
20123 case AArch64::SMLSLB_ZZZI_D:
20124 case AArch64::SMLSLT_ZZZI_D:
20125 case AArch64::SQDMLALB_ZZZI_D:
20126 case AArch64::SQDMLALT_ZZZI_D:
20127 case AArch64::SQDMLSLB_ZZZI_D:
20128 case AArch64::SQDMLSLT_ZZZI_D:
20129 case AArch64::UMLALB_ZZZI_D:
20130 case AArch64::UMLALT_ZZZI_D:
20131 case AArch64::UMLSLB_ZZZI_D:
20132 case AArch64::UMLSLT_ZZZI_D: {
20133 // op: Zda
20134 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20135 op &= UINT64_C(31);
20136 Value |= op;
20137 // op: Zn
20138 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20139 op &= UINT64_C(31);
20140 op <<= 5;
20141 Value |= op;
20142 // op: Zm
20143 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20144 op &= UINT64_C(15);
20145 op <<= 16;
20146 Value |= op;
20147 // op: iop
20148 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20149 Value |= (op & UINT64_C(2)) << 19;
20150 Value |= (op & UINT64_C(1)) << 11;
20151 break;
20152 }
20153 case AArch64::FMLA_ZZZI_D:
20154 case AArch64::FMLS_ZZZI_D:
20155 case AArch64::MLA_ZZZI_D:
20156 case AArch64::MLS_ZZZI_D:
20157 case AArch64::SQRDMLAH_ZZZI_D:
20158 case AArch64::SQRDMLSH_ZZZI_D: {
20159 // op: Zda
20160 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20161 op &= UINT64_C(31);
20162 Value |= op;
20163 // op: Zn
20164 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20165 op &= UINT64_C(31);
20166 op <<= 5;
20167 Value |= op;
20168 // op: Zm
20169 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20170 op &= UINT64_C(15);
20171 op <<= 16;
20172 Value |= op;
20173 // op: iop
20174 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20175 op &= UINT64_C(1);
20176 op <<= 20;
20177 Value |= op;
20178 break;
20179 }
20180 case AArch64::ADCLB_ZZZ_D:
20181 case AArch64::ADCLB_ZZZ_S:
20182 case AArch64::ADCLT_ZZZ_D:
20183 case AArch64::ADCLT_ZZZ_S:
20184 case AArch64::BFDOT_ZZZ:
20185 case AArch64::BFMLALB_ZZZ:
20186 case AArch64::BFMLALT_ZZZ:
20187 case AArch64::BFMLSLB_ZZZ_S:
20188 case AArch64::BFMLSLT_ZZZ_S:
20189 case AArch64::FDOT_ZZZ_BtoH:
20190 case AArch64::FDOT_ZZZ_BtoS:
20191 case AArch64::FDOT_ZZZ_S:
20192 case AArch64::FMLALB_ZZZ:
20193 case AArch64::FMLALB_ZZZ_SHH:
20194 case AArch64::FMLALLBB_ZZZ:
20195 case AArch64::FMLALLBT_ZZZ:
20196 case AArch64::FMLALLTB_ZZZ:
20197 case AArch64::FMLALLTT_ZZZ:
20198 case AArch64::FMLALT_ZZZ:
20199 case AArch64::FMLALT_ZZZ_SHH:
20200 case AArch64::FMLSLB_ZZZ_SHH:
20201 case AArch64::FMLSLT_ZZZ_SHH:
20202 case AArch64::FMMLA_ZZZ_D:
20203 case AArch64::FMMLA_ZZZ_S:
20204 case AArch64::MLA_CPA:
20205 case AArch64::SABALB_ZZZ_D:
20206 case AArch64::SABALB_ZZZ_H:
20207 case AArch64::SABALB_ZZZ_S:
20208 case AArch64::SABALT_ZZZ_D:
20209 case AArch64::SABALT_ZZZ_H:
20210 case AArch64::SABALT_ZZZ_S:
20211 case AArch64::SABA_ZZZ_B:
20212 case AArch64::SABA_ZZZ_D:
20213 case AArch64::SABA_ZZZ_H:
20214 case AArch64::SABA_ZZZ_S:
20215 case AArch64::SBCLB_ZZZ_D:
20216 case AArch64::SBCLB_ZZZ_S:
20217 case AArch64::SBCLT_ZZZ_D:
20218 case AArch64::SBCLT_ZZZ_S:
20219 case AArch64::SDOT_ZZZ_D:
20220 case AArch64::SDOT_ZZZ_HtoS:
20221 case AArch64::SDOT_ZZZ_S:
20222 case AArch64::SMLALB_ZZZ_D:
20223 case AArch64::SMLALB_ZZZ_H:
20224 case AArch64::SMLALB_ZZZ_S:
20225 case AArch64::SMLALT_ZZZ_D:
20226 case AArch64::SMLALT_ZZZ_H:
20227 case AArch64::SMLALT_ZZZ_S:
20228 case AArch64::SMLSLB_ZZZ_D:
20229 case AArch64::SMLSLB_ZZZ_H:
20230 case AArch64::SMLSLB_ZZZ_S:
20231 case AArch64::SMLSLT_ZZZ_D:
20232 case AArch64::SMLSLT_ZZZ_H:
20233 case AArch64::SMLSLT_ZZZ_S:
20234 case AArch64::SMMLA_ZZZ:
20235 case AArch64::SQDMLALBT_ZZZ_D:
20236 case AArch64::SQDMLALBT_ZZZ_H:
20237 case AArch64::SQDMLALBT_ZZZ_S:
20238 case AArch64::SQDMLALB_ZZZ_D:
20239 case AArch64::SQDMLALB_ZZZ_H:
20240 case AArch64::SQDMLALB_ZZZ_S:
20241 case AArch64::SQDMLALT_ZZZ_D:
20242 case AArch64::SQDMLALT_ZZZ_H:
20243 case AArch64::SQDMLALT_ZZZ_S:
20244 case AArch64::SQDMLSLBT_ZZZ_D:
20245 case AArch64::SQDMLSLBT_ZZZ_H:
20246 case AArch64::SQDMLSLBT_ZZZ_S:
20247 case AArch64::SQDMLSLB_ZZZ_D:
20248 case AArch64::SQDMLSLB_ZZZ_H:
20249 case AArch64::SQDMLSLB_ZZZ_S:
20250 case AArch64::SQDMLSLT_ZZZ_D:
20251 case AArch64::SQDMLSLT_ZZZ_H:
20252 case AArch64::SQDMLSLT_ZZZ_S:
20253 case AArch64::SQRDMLAH_ZZZ_B:
20254 case AArch64::SQRDMLAH_ZZZ_D:
20255 case AArch64::SQRDMLAH_ZZZ_H:
20256 case AArch64::SQRDMLAH_ZZZ_S:
20257 case AArch64::SQRDMLSH_ZZZ_B:
20258 case AArch64::SQRDMLSH_ZZZ_D:
20259 case AArch64::SQRDMLSH_ZZZ_H:
20260 case AArch64::SQRDMLSH_ZZZ_S:
20261 case AArch64::UABALB_ZZZ_D:
20262 case AArch64::UABALB_ZZZ_H:
20263 case AArch64::UABALB_ZZZ_S:
20264 case AArch64::UABALT_ZZZ_D:
20265 case AArch64::UABALT_ZZZ_H:
20266 case AArch64::UABALT_ZZZ_S:
20267 case AArch64::UABA_ZZZ_B:
20268 case AArch64::UABA_ZZZ_D:
20269 case AArch64::UABA_ZZZ_H:
20270 case AArch64::UABA_ZZZ_S:
20271 case AArch64::UDOT_ZZZ_D:
20272 case AArch64::UDOT_ZZZ_HtoS:
20273 case AArch64::UDOT_ZZZ_S:
20274 case AArch64::UMLALB_ZZZ_D:
20275 case AArch64::UMLALB_ZZZ_H:
20276 case AArch64::UMLALB_ZZZ_S:
20277 case AArch64::UMLALT_ZZZ_D:
20278 case AArch64::UMLALT_ZZZ_H:
20279 case AArch64::UMLALT_ZZZ_S:
20280 case AArch64::UMLSLB_ZZZ_D:
20281 case AArch64::UMLSLB_ZZZ_H:
20282 case AArch64::UMLSLB_ZZZ_S:
20283 case AArch64::UMLSLT_ZZZ_D:
20284 case AArch64::UMLSLT_ZZZ_H:
20285 case AArch64::UMLSLT_ZZZ_S:
20286 case AArch64::UMMLA_ZZZ:
20287 case AArch64::USDOT_ZZZ:
20288 case AArch64::USMMLA_ZZZ: {
20289 // op: Zda
20290 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20291 op &= UINT64_C(31);
20292 Value |= op;
20293 // op: Zn
20294 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20295 op &= UINT64_C(31);
20296 op <<= 5;
20297 Value |= op;
20298 // op: Zm
20299 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20300 op &= UINT64_C(31);
20301 op <<= 16;
20302 Value |= op;
20303 break;
20304 }
20305 case AArch64::CDOT_ZZZ_D:
20306 case AArch64::CDOT_ZZZ_S:
20307 case AArch64::CMLA_ZZZ_B:
20308 case AArch64::CMLA_ZZZ_D:
20309 case AArch64::CMLA_ZZZ_H:
20310 case AArch64::CMLA_ZZZ_S:
20311 case AArch64::SQRDCMLAH_ZZZ_B:
20312 case AArch64::SQRDCMLAH_ZZZ_D:
20313 case AArch64::SQRDCMLAH_ZZZ_H:
20314 case AArch64::SQRDCMLAH_ZZZ_S: {
20315 // op: Zda
20316 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20317 op &= UINT64_C(31);
20318 Value |= op;
20319 // op: Zn
20320 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20321 op &= UINT64_C(31);
20322 op <<= 5;
20323 Value |= op;
20324 // op: Zm
20325 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20326 op &= UINT64_C(31);
20327 op <<= 16;
20328 Value |= op;
20329 // op: rot
20330 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20331 op &= UINT64_C(3);
20332 op <<= 10;
20333 Value |= op;
20334 break;
20335 }
20336 case AArch64::SDOT_ZZZI_HtoS:
20337 case AArch64::UDOT_ZZZI_HtoS: {
20338 // op: Zda
20339 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20340 op &= UINT64_C(31);
20341 Value |= op;
20342 // op: Zn
20343 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20344 op &= UINT64_C(31);
20345 op <<= 5;
20346 Value |= op;
20347 // op: Zm
20348 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20349 op &= UINT64_C(7);
20350 op <<= 16;
20351 Value |= op;
20352 // op: i2
20353 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20354 op &= UINT64_C(3);
20355 op <<= 19;
20356 Value |= op;
20357 break;
20358 }
20359 case AArch64::SUDOT_ZZZI:
20360 case AArch64::USDOT_ZZZI: {
20361 // op: Zda
20362 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20363 op &= UINT64_C(31);
20364 Value |= op;
20365 // op: Zn
20366 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20367 op &= UINT64_C(31);
20368 op <<= 5;
20369 Value |= op;
20370 // op: Zm
20371 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20372 op &= UINT64_C(7);
20373 op <<= 16;
20374 Value |= op;
20375 // op: idx
20376 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20377 op &= UINT64_C(3);
20378 op <<= 19;
20379 Value |= op;
20380 break;
20381 }
20382 case AArch64::FMLALB_ZZZI:
20383 case AArch64::FMLALLBB_ZZZI:
20384 case AArch64::FMLALLBT_ZZZI:
20385 case AArch64::FMLALLTB_ZZZI:
20386 case AArch64::FMLALLTT_ZZZI:
20387 case AArch64::FMLALT_ZZZI: {
20388 // op: Zda
20389 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20390 op &= UINT64_C(31);
20391 Value |= op;
20392 // op: Zn
20393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20394 op &= UINT64_C(31);
20395 op <<= 5;
20396 Value |= op;
20397 // op: Zm
20398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20399 op &= UINT64_C(7);
20400 op <<= 16;
20401 Value |= op;
20402 // op: imm4
20403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20404 Value |= (op & UINT64_C(12)) << 17;
20405 Value |= (op & UINT64_C(3)) << 10;
20406 break;
20407 }
20408 case AArch64::BFMLA_ZZZI:
20409 case AArch64::BFMLS_ZZZI:
20410 case AArch64::FMLA_ZZZI_H:
20411 case AArch64::FMLS_ZZZI_H:
20412 case AArch64::MLA_ZZZI_H:
20413 case AArch64::MLS_ZZZI_H:
20414 case AArch64::SQRDMLAH_ZZZI_H:
20415 case AArch64::SQRDMLSH_ZZZI_H: {
20416 // op: Zda
20417 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20418 op &= UINT64_C(31);
20419 Value |= op;
20420 // op: Zn
20421 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20422 op &= UINT64_C(31);
20423 op <<= 5;
20424 Value |= op;
20425 // op: Zm
20426 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20427 op &= UINT64_C(7);
20428 op <<= 16;
20429 Value |= op;
20430 // op: iop
20431 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20432 Value |= (op & UINT64_C(4)) << 20;
20433 Value |= (op & UINT64_C(3)) << 19;
20434 break;
20435 }
20436 case AArch64::BFMLALB_ZZZI:
20437 case AArch64::BFMLALT_ZZZI:
20438 case AArch64::BFMLSLB_ZZZI_S:
20439 case AArch64::BFMLSLT_ZZZI_S:
20440 case AArch64::FDOT_ZZZI_BtoH:
20441 case AArch64::FMLALB_ZZZI_SHH:
20442 case AArch64::FMLALT_ZZZI_SHH:
20443 case AArch64::FMLSLB_ZZZI_SHH:
20444 case AArch64::FMLSLT_ZZZI_SHH:
20445 case AArch64::SMLALB_ZZZI_S:
20446 case AArch64::SMLALT_ZZZI_S:
20447 case AArch64::SMLSLB_ZZZI_S:
20448 case AArch64::SMLSLT_ZZZI_S:
20449 case AArch64::SQDMLALB_ZZZI_S:
20450 case AArch64::SQDMLALT_ZZZI_S:
20451 case AArch64::SQDMLSLB_ZZZI_S:
20452 case AArch64::SQDMLSLT_ZZZI_S:
20453 case AArch64::UMLALB_ZZZI_S:
20454 case AArch64::UMLALT_ZZZI_S:
20455 case AArch64::UMLSLB_ZZZI_S:
20456 case AArch64::UMLSLT_ZZZI_S: {
20457 // op: Zda
20458 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20459 op &= UINT64_C(31);
20460 Value |= op;
20461 // op: Zn
20462 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20463 op &= UINT64_C(31);
20464 op <<= 5;
20465 Value |= op;
20466 // op: Zm
20467 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20468 op &= UINT64_C(7);
20469 op <<= 16;
20470 Value |= op;
20471 // op: iop
20472 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20473 Value |= (op & UINT64_C(6)) << 18;
20474 Value |= (op & UINT64_C(1)) << 11;
20475 break;
20476 }
20477 case AArch64::BFDOT_ZZI:
20478 case AArch64::FDOT_ZZZI_BtoS:
20479 case AArch64::FDOT_ZZZI_S:
20480 case AArch64::FMLA_ZZZI_S:
20481 case AArch64::FMLS_ZZZI_S:
20482 case AArch64::MLA_ZZZI_S:
20483 case AArch64::MLS_ZZZI_S:
20484 case AArch64::SQRDMLAH_ZZZI_S:
20485 case AArch64::SQRDMLSH_ZZZI_S: {
20486 // op: Zda
20487 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20488 op &= UINT64_C(31);
20489 Value |= op;
20490 // op: Zn
20491 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20492 op &= UINT64_C(31);
20493 op <<= 5;
20494 Value |= op;
20495 // op: Zm
20496 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20497 op &= UINT64_C(7);
20498 op <<= 16;
20499 Value |= op;
20500 // op: iop
20501 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20502 op &= UINT64_C(3);
20503 op <<= 19;
20504 Value |= op;
20505 break;
20506 }
20507 case AArch64::FCMLA_ZZZI_S: {
20508 // op: Zda
20509 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20510 op &= UINT64_C(31);
20511 Value |= op;
20512 // op: Zn
20513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20514 op &= UINT64_C(31);
20515 op <<= 5;
20516 Value |= op;
20517 // op: imm
20518 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
20519 op &= UINT64_C(3);
20520 op <<= 10;
20521 Value |= op;
20522 // op: Zm
20523 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20524 op &= UINT64_C(15);
20525 op <<= 16;
20526 Value |= op;
20527 // op: iop
20528 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20529 op &= UINT64_C(1);
20530 op <<= 20;
20531 Value |= op;
20532 break;
20533 }
20534 case AArch64::FCMLA_ZZZI_H: {
20535 // op: Zda
20536 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20537 op &= UINT64_C(31);
20538 Value |= op;
20539 // op: Zn
20540 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20541 op &= UINT64_C(31);
20542 op <<= 5;
20543 Value |= op;
20544 // op: imm
20545 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
20546 op &= UINT64_C(3);
20547 op <<= 10;
20548 Value |= op;
20549 // op: Zm
20550 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20551 op &= UINT64_C(7);
20552 op <<= 16;
20553 Value |= op;
20554 // op: iop
20555 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20556 op &= UINT64_C(3);
20557 op <<= 19;
20558 Value |= op;
20559 break;
20560 }
20561 case AArch64::SRSRA_ZZI_H:
20562 case AArch64::SSRA_ZZI_H:
20563 case AArch64::URSRA_ZZI_H:
20564 case AArch64::USRA_ZZI_H: {
20565 // op: Zda
20566 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20567 op &= UINT64_C(31);
20568 Value |= op;
20569 // op: Zn
20570 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20571 op &= UINT64_C(31);
20572 op <<= 5;
20573 Value |= op;
20574 // op: imm
20575 op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI);
20576 op &= UINT64_C(15);
20577 op <<= 16;
20578 Value |= op;
20579 break;
20580 }
20581 case AArch64::SRSRA_ZZI_S:
20582 case AArch64::SSRA_ZZI_S:
20583 case AArch64::URSRA_ZZI_S:
20584 case AArch64::USRA_ZZI_S: {
20585 // op: Zda
20586 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20587 op &= UINT64_C(31);
20588 Value |= op;
20589 // op: Zn
20590 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20591 op &= UINT64_C(31);
20592 op <<= 5;
20593 Value |= op;
20594 // op: imm
20595 op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI);
20596 op &= UINT64_C(31);
20597 op <<= 16;
20598 Value |= op;
20599 break;
20600 }
20601 case AArch64::SRSRA_ZZI_D:
20602 case AArch64::SSRA_ZZI_D:
20603 case AArch64::URSRA_ZZI_D:
20604 case AArch64::USRA_ZZI_D: {
20605 // op: Zda
20606 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20607 op &= UINT64_C(31);
20608 Value |= op;
20609 // op: Zn
20610 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20611 op &= UINT64_C(31);
20612 op <<= 5;
20613 Value |= op;
20614 // op: imm
20615 op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI);
20616 Value |= (op & UINT64_C(32)) << 17;
20617 Value |= (op & UINT64_C(31)) << 16;
20618 break;
20619 }
20620 case AArch64::SRSRA_ZZI_B:
20621 case AArch64::SSRA_ZZI_B:
20622 case AArch64::URSRA_ZZI_B:
20623 case AArch64::USRA_ZZI_B: {
20624 // op: Zda
20625 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20626 op &= UINT64_C(31);
20627 Value |= op;
20628 // op: Zn
20629 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20630 op &= UINT64_C(31);
20631 op <<= 5;
20632 Value |= op;
20633 // op: imm
20634 op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI);
20635 op &= UINT64_C(7);
20636 op <<= 16;
20637 Value |= op;
20638 break;
20639 }
20640 case AArch64::SDOT_ZZZI_D:
20641 case AArch64::UDOT_ZZZI_D: {
20642 // op: Zda
20643 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20644 op &= UINT64_C(31);
20645 Value |= op;
20646 // op: Zn
20647 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20648 op &= UINT64_C(31);
20649 op <<= 5;
20650 Value |= op;
20651 // op: iop
20652 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20653 op &= UINT64_C(1);
20654 op <<= 20;
20655 Value |= op;
20656 // op: Zm
20657 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20658 op &= UINT64_C(15);
20659 op <<= 16;
20660 Value |= op;
20661 break;
20662 }
20663 case AArch64::SDOT_ZZZI_S:
20664 case AArch64::UDOT_ZZZI_S: {
20665 // op: Zda
20666 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20667 op &= UINT64_C(31);
20668 Value |= op;
20669 // op: Zn
20670 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20671 op &= UINT64_C(31);
20672 op <<= 5;
20673 Value |= op;
20674 // op: iop
20675 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20676 op &= UINT64_C(3);
20677 op <<= 19;
20678 Value |= op;
20679 // op: Zm
20680 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20681 op &= UINT64_C(7);
20682 op <<= 16;
20683 Value |= op;
20684 break;
20685 }
20686 case AArch64::CDOT_ZZZI_D:
20687 case AArch64::CMLA_ZZZI_S:
20688 case AArch64::SQRDCMLAH_ZZZI_S: {
20689 // op: Zda
20690 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20691 op &= UINT64_C(31);
20692 Value |= op;
20693 // op: Zn
20694 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20695 op &= UINT64_C(31);
20696 op <<= 5;
20697 Value |= op;
20698 // op: rot
20699 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
20700 op &= UINT64_C(3);
20701 op <<= 10;
20702 Value |= op;
20703 // op: iop
20704 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20705 op &= UINT64_C(1);
20706 op <<= 20;
20707 Value |= op;
20708 // op: Zm
20709 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20710 op &= UINT64_C(15);
20711 op <<= 16;
20712 Value |= op;
20713 break;
20714 }
20715 case AArch64::CDOT_ZZZI_S:
20716 case AArch64::CMLA_ZZZI_H:
20717 case AArch64::SQRDCMLAH_ZZZI_H: {
20718 // op: Zda
20719 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20720 op &= UINT64_C(31);
20721 Value |= op;
20722 // op: Zn
20723 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20724 op &= UINT64_C(31);
20725 op <<= 5;
20726 Value |= op;
20727 // op: rot
20728 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
20729 op &= UINT64_C(3);
20730 op <<= 10;
20731 Value |= op;
20732 // op: iop
20733 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20734 op &= UINT64_C(3);
20735 op <<= 19;
20736 Value |= op;
20737 // op: Zm
20738 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20739 op &= UINT64_C(7);
20740 op <<= 16;
20741 Value |= op;
20742 break;
20743 }
20744 case AArch64::AESIMC_ZZ_B:
20745 case AArch64::AESMC_ZZ_B: {
20746 // op: Zdn
20747 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20748 op &= UINT64_C(31);
20749 Value |= op;
20750 break;
20751 }
20752 case AArch64::BCAX_ZZZZ:
20753 case AArch64::BSL1N_ZZZZ:
20754 case AArch64::BSL2N_ZZZZ:
20755 case AArch64::BSL_ZZZZ:
20756 case AArch64::EOR3_ZZZZ:
20757 case AArch64::NBSL_ZZZZ: {
20758 // op: Zdn
20759 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20760 op &= UINT64_C(31);
20761 Value |= op;
20762 // op: Zk
20763 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20764 op &= UINT64_C(31);
20765 op <<= 5;
20766 Value |= op;
20767 // op: Zm
20768 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20769 op &= UINT64_C(31);
20770 op <<= 16;
20771 Value |= op;
20772 break;
20773 }
20774 case AArch64::MAD_CPA: {
20775 // op: Zdn
20776 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20777 op &= UINT64_C(31);
20778 Value |= op;
20779 // op: Zm
20780 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20781 op &= UINT64_C(31);
20782 op <<= 16;
20783 Value |= op;
20784 // op: Za
20785 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20786 op &= UINT64_C(31);
20787 op <<= 5;
20788 Value |= op;
20789 break;
20790 }
20791 case AArch64::AESD_ZZZ_B:
20792 case AArch64::AESE_ZZZ_B:
20793 case AArch64::SM4E_ZZZ_S: {
20794 // op: Zdn
20795 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20796 op &= UINT64_C(31);
20797 Value |= op;
20798 // op: Zm
20799 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20800 op &= UINT64_C(31);
20801 op <<= 5;
20802 Value |= op;
20803 break;
20804 }
20805 case AArch64::XAR_ZZZI_H: {
20806 // op: Zdn
20807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20808 op &= UINT64_C(31);
20809 Value |= op;
20810 // op: Zm
20811 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20812 op &= UINT64_C(31);
20813 op <<= 5;
20814 Value |= op;
20815 // op: imm
20816 op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI);
20817 op &= UINT64_C(15);
20818 op <<= 16;
20819 Value |= op;
20820 break;
20821 }
20822 case AArch64::XAR_ZZZI_S: {
20823 // op: Zdn
20824 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20825 op &= UINT64_C(31);
20826 Value |= op;
20827 // op: Zm
20828 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20829 op &= UINT64_C(31);
20830 op <<= 5;
20831 Value |= op;
20832 // op: imm
20833 op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI);
20834 op &= UINT64_C(31);
20835 op <<= 16;
20836 Value |= op;
20837 break;
20838 }
20839 case AArch64::XAR_ZZZI_D: {
20840 // op: Zdn
20841 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20842 op &= UINT64_C(31);
20843 Value |= op;
20844 // op: Zm
20845 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20846 op &= UINT64_C(31);
20847 op <<= 5;
20848 Value |= op;
20849 // op: imm
20850 op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI);
20851 Value |= (op & UINT64_C(32)) << 17;
20852 Value |= (op & UINT64_C(31)) << 16;
20853 break;
20854 }
20855 case AArch64::XAR_ZZZI_B: {
20856 // op: Zdn
20857 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20858 op &= UINT64_C(31);
20859 Value |= op;
20860 // op: Zm
20861 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20862 op &= UINT64_C(31);
20863 op <<= 5;
20864 Value |= op;
20865 // op: imm
20866 op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI);
20867 op &= UINT64_C(7);
20868 op <<= 16;
20869 Value |= op;
20870 break;
20871 }
20872 case AArch64::FTMAD_ZZI_D:
20873 case AArch64::FTMAD_ZZI_H:
20874 case AArch64::FTMAD_ZZI_S: {
20875 // op: Zdn
20876 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20877 op &= UINT64_C(31);
20878 Value |= op;
20879 // op: Zm
20880 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20881 op &= UINT64_C(31);
20882 op <<= 5;
20883 Value |= op;
20884 // op: imm3
20885 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20886 op &= UINT64_C(7);
20887 op <<= 16;
20888 Value |= op;
20889 break;
20890 }
20891 case AArch64::EXTQ_ZZI: {
20892 // op: Zdn
20893 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20894 op &= UINT64_C(31);
20895 Value |= op;
20896 // op: Zm
20897 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20898 op &= UINT64_C(31);
20899 op <<= 5;
20900 Value |= op;
20901 // op: imm4
20902 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20903 op &= UINT64_C(15);
20904 op <<= 16;
20905 Value |= op;
20906 break;
20907 }
20908 case AArch64::EXT_ZZI: {
20909 // op: Zdn
20910 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20911 op &= UINT64_C(31);
20912 Value |= op;
20913 // op: Zm
20914 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20915 op &= UINT64_C(31);
20916 op <<= 5;
20917 Value |= op;
20918 // op: imm8
20919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20920 Value |= (op & UINT64_C(248)) << 13;
20921 Value |= (op & UINT64_C(7)) << 10;
20922 break;
20923 }
20924 case AArch64::CADD_ZZI_B:
20925 case AArch64::CADD_ZZI_D:
20926 case AArch64::CADD_ZZI_H:
20927 case AArch64::CADD_ZZI_S:
20928 case AArch64::SQCADD_ZZI_B:
20929 case AArch64::SQCADD_ZZI_D:
20930 case AArch64::SQCADD_ZZI_H:
20931 case AArch64::SQCADD_ZZI_S: {
20932 // op: Zdn
20933 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20934 op &= UINT64_C(31);
20935 Value |= op;
20936 // op: Zm
20937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
20938 op &= UINT64_C(31);
20939 op <<= 5;
20940 Value |= op;
20941 // op: rot
20942 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20943 op &= UINT64_C(1);
20944 op <<= 10;
20945 Value |= op;
20946 break;
20947 }
20948 case AArch64::FCADD_ZPmZ_D:
20949 case AArch64::FCADD_ZPmZ_H:
20950 case AArch64::FCADD_ZPmZ_S: {
20951 // op: Zdn
20952 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
20953 op &= UINT64_C(31);
20954 Value |= op;
20955 // op: Zm
20956 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
20957 op &= UINT64_C(31);
20958 op <<= 5;
20959 Value |= op;
20960 // op: Pg
20961 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
20962 op &= UINT64_C(7);
20963 op <<= 10;
20964 Value |= op;
20965 // op: imm
20966 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
20967 op &= UINT64_C(1);
20968 op <<= 16;
20969 Value |= op;
20970 break;
20971 }
20972 case AArch64::ADD_ZI_B:
20973 case AArch64::ADD_ZI_D:
20974 case AArch64::ADD_ZI_H:
20975 case AArch64::ADD_ZI_S:
20976 case AArch64::SQADD_ZI_B:
20977 case AArch64::SQADD_ZI_D:
20978 case AArch64::SQADD_ZI_H:
20979 case AArch64::SQADD_ZI_S:
20980 case AArch64::SQSUB_ZI_B:
20981 case AArch64::SQSUB_ZI_D:
20982 case AArch64::SQSUB_ZI_H:
20983 case AArch64::SQSUB_ZI_S:
20984 case AArch64::SUBR_ZI_B:
20985 case AArch64::SUBR_ZI_D:
20986 case AArch64::SUBR_ZI_H:
20987 case AArch64::SUBR_ZI_S:
20988 case AArch64::SUB_ZI_B:
20989 case AArch64::SUB_ZI_D:
20990 case AArch64::SUB_ZI_H:
20991 case AArch64::SUB_ZI_S:
20992 case AArch64::UQADD_ZI_B:
20993 case AArch64::UQADD_ZI_D:
20994 case AArch64::UQADD_ZI_H:
20995 case AArch64::UQADD_ZI_S:
20996 case AArch64::UQSUB_ZI_B:
20997 case AArch64::UQSUB_ZI_D:
20998 case AArch64::UQSUB_ZI_H:
20999 case AArch64::UQSUB_ZI_S: {
21000 // op: Zdn
21001 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21002 op &= UINT64_C(31);
21003 Value |= op;
21004 // op: imm
21005 op = getImm8OptLsl(MI, OpIdx: 2, Fixups, STI);
21006 op &= UINT64_C(511);
21007 op <<= 5;
21008 Value |= op;
21009 break;
21010 }
21011 case AArch64::MUL_ZI_B:
21012 case AArch64::MUL_ZI_D:
21013 case AArch64::MUL_ZI_H:
21014 case AArch64::MUL_ZI_S:
21015 case AArch64::SMAX_ZI_B:
21016 case AArch64::SMAX_ZI_D:
21017 case AArch64::SMAX_ZI_H:
21018 case AArch64::SMAX_ZI_S:
21019 case AArch64::SMIN_ZI_B:
21020 case AArch64::SMIN_ZI_D:
21021 case AArch64::SMIN_ZI_H:
21022 case AArch64::SMIN_ZI_S:
21023 case AArch64::UMAX_ZI_B:
21024 case AArch64::UMAX_ZI_D:
21025 case AArch64::UMAX_ZI_H:
21026 case AArch64::UMAX_ZI_S:
21027 case AArch64::UMIN_ZI_B:
21028 case AArch64::UMIN_ZI_D:
21029 case AArch64::UMIN_ZI_H:
21030 case AArch64::UMIN_ZI_S: {
21031 // op: Zdn
21032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21033 op &= UINT64_C(31);
21034 Value |= op;
21035 // op: imm
21036 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21037 op &= UINT64_C(255);
21038 op <<= 5;
21039 Value |= op;
21040 break;
21041 }
21042 case AArch64::AND_ZI:
21043 case AArch64::EOR_ZI:
21044 case AArch64::ORR_ZI: {
21045 // op: Zdn
21046 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21047 op &= UINT64_C(31);
21048 Value |= op;
21049 // op: imms13
21050 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21051 op &= UINT64_C(8191);
21052 op <<= 5;
21053 Value |= op;
21054 break;
21055 }
21056 case AArch64::DECD_ZPiI:
21057 case AArch64::DECH_ZPiI:
21058 case AArch64::DECW_ZPiI:
21059 case AArch64::INCD_ZPiI:
21060 case AArch64::INCH_ZPiI:
21061 case AArch64::INCW_ZPiI:
21062 case AArch64::SQDECD_ZPiI:
21063 case AArch64::SQDECH_ZPiI:
21064 case AArch64::SQDECW_ZPiI:
21065 case AArch64::SQINCD_ZPiI:
21066 case AArch64::SQINCH_ZPiI:
21067 case AArch64::SQINCW_ZPiI:
21068 case AArch64::UQDECD_ZPiI:
21069 case AArch64::UQDECH_ZPiI:
21070 case AArch64::UQDECW_ZPiI:
21071 case AArch64::UQINCD_ZPiI:
21072 case AArch64::UQINCH_ZPiI:
21073 case AArch64::UQINCW_ZPiI: {
21074 // op: Zdn
21075 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21076 op &= UINT64_C(31);
21077 Value |= op;
21078 // op: pattern
21079 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21080 op &= UINT64_C(31);
21081 op <<= 5;
21082 Value |= op;
21083 // op: imm4
21084 op = getSVEIncDecImm(MI, OpIdx: 3, Fixups, STI);
21085 op &= UINT64_C(15);
21086 op <<= 16;
21087 Value |= op;
21088 break;
21089 }
21090 case AArch64::BFMAXNM_VG2_2Z2Z_H:
21091 case AArch64::BFMAX_VG2_2Z2Z_H:
21092 case AArch64::BFMINNM_VG2_2Z2Z_H:
21093 case AArch64::BFMIN_VG2_2Z2Z_H:
21094 case AArch64::FAMAX_2Z2Z_D:
21095 case AArch64::FAMAX_2Z2Z_H:
21096 case AArch64::FAMAX_2Z2Z_S:
21097 case AArch64::FAMIN_2Z2Z_D:
21098 case AArch64::FAMIN_2Z2Z_H:
21099 case AArch64::FAMIN_2Z2Z_S:
21100 case AArch64::FMAXNM_VG2_2Z2Z_D:
21101 case AArch64::FMAXNM_VG2_2Z2Z_H:
21102 case AArch64::FMAXNM_VG2_2Z2Z_S:
21103 case AArch64::FMAX_VG2_2Z2Z_D:
21104 case AArch64::FMAX_VG2_2Z2Z_H:
21105 case AArch64::FMAX_VG2_2Z2Z_S:
21106 case AArch64::FMINNM_VG2_2Z2Z_D:
21107 case AArch64::FMINNM_VG2_2Z2Z_H:
21108 case AArch64::FMINNM_VG2_2Z2Z_S:
21109 case AArch64::FMIN_VG2_2Z2Z_D:
21110 case AArch64::FMIN_VG2_2Z2Z_H:
21111 case AArch64::FMIN_VG2_2Z2Z_S:
21112 case AArch64::FSCALE_2Z2Z_D:
21113 case AArch64::FSCALE_2Z2Z_H:
21114 case AArch64::FSCALE_2Z2Z_S:
21115 case AArch64::SMAX_VG2_2Z2Z_B:
21116 case AArch64::SMAX_VG2_2Z2Z_D:
21117 case AArch64::SMAX_VG2_2Z2Z_H:
21118 case AArch64::SMAX_VG2_2Z2Z_S:
21119 case AArch64::SMIN_VG2_2Z2Z_B:
21120 case AArch64::SMIN_VG2_2Z2Z_D:
21121 case AArch64::SMIN_VG2_2Z2Z_H:
21122 case AArch64::SMIN_VG2_2Z2Z_S:
21123 case AArch64::SQDMULH_VG2_2Z2Z_B:
21124 case AArch64::SQDMULH_VG2_2Z2Z_D:
21125 case AArch64::SQDMULH_VG2_2Z2Z_H:
21126 case AArch64::SQDMULH_VG2_2Z2Z_S:
21127 case AArch64::SRSHL_VG2_2Z2Z_B:
21128 case AArch64::SRSHL_VG2_2Z2Z_D:
21129 case AArch64::SRSHL_VG2_2Z2Z_H:
21130 case AArch64::SRSHL_VG2_2Z2Z_S:
21131 case AArch64::UMAX_VG2_2Z2Z_B:
21132 case AArch64::UMAX_VG2_2Z2Z_D:
21133 case AArch64::UMAX_VG2_2Z2Z_H:
21134 case AArch64::UMAX_VG2_2Z2Z_S:
21135 case AArch64::UMIN_VG2_2Z2Z_B:
21136 case AArch64::UMIN_VG2_2Z2Z_D:
21137 case AArch64::UMIN_VG2_2Z2Z_H:
21138 case AArch64::UMIN_VG2_2Z2Z_S:
21139 case AArch64::URSHL_VG2_2Z2Z_B:
21140 case AArch64::URSHL_VG2_2Z2Z_D:
21141 case AArch64::URSHL_VG2_2Z2Z_H:
21142 case AArch64::URSHL_VG2_2Z2Z_S: {
21143 // op: Zm
21144 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 2, Fixups, STI);
21145 op &= UINT64_C(15);
21146 op <<= 17;
21147 Value |= op;
21148 // op: Zdn
21149 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
21150 op &= UINT64_C(15);
21151 op <<= 1;
21152 Value |= op;
21153 break;
21154 }
21155 case AArch64::FMLALL_VG2_M2Z2Z_BtoS:
21156 case AArch64::SMLALL_VG2_M2Z2Z_BtoS:
21157 case AArch64::SMLALL_VG2_M2Z2Z_HtoD:
21158 case AArch64::SMLSLL_VG2_M2Z2Z_BtoS:
21159 case AArch64::SMLSLL_VG2_M2Z2Z_HtoD:
21160 case AArch64::UMLALL_VG2_M2Z2Z_BtoS:
21161 case AArch64::UMLALL_VG2_M2Z2Z_HtoD:
21162 case AArch64::UMLSLL_VG2_M2Z2Z_BtoS:
21163 case AArch64::UMLSLL_VG2_M2Z2Z_HtoD:
21164 case AArch64::USMLALL_VG2_M2Z2Z_BtoS: {
21165 // op: Zm
21166 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 5, Fixups, STI);
21167 op &= UINT64_C(15);
21168 op <<= 17;
21169 Value |= op;
21170 // op: Rv
21171 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21172 op &= UINT64_C(3);
21173 op <<= 13;
21174 Value |= op;
21175 // op: Zn
21176 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
21177 op &= UINT64_C(15);
21178 op <<= 6;
21179 Value |= op;
21180 // op: imm
21181 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21182 op &= UINT64_C(1);
21183 Value |= op;
21184 break;
21185 }
21186 case AArch64::ADD_VG2_M2Z2Z_D:
21187 case AArch64::ADD_VG2_M2Z2Z_S:
21188 case AArch64::BFDOT_VG2_M2Z2Z_HtoS:
21189 case AArch64::BFMLA_VG2_M2Z2Z:
21190 case AArch64::BFMLS_VG2_M2Z2Z:
21191 case AArch64::FDOT_VG2_M2Z2Z_BtoH:
21192 case AArch64::FDOT_VG2_M2Z2Z_BtoS:
21193 case AArch64::FDOT_VG2_M2Z2Z_HtoS:
21194 case AArch64::FMLA_VG2_M2Z2Z_D:
21195 case AArch64::FMLA_VG2_M2Z2Z_S:
21196 case AArch64::FMLA_VG2_M2Z4Z_H:
21197 case AArch64::FMLS_VG2_M2Z2Z_D:
21198 case AArch64::FMLS_VG2_M2Z2Z_H:
21199 case AArch64::FMLS_VG2_M2Z2Z_S:
21200 case AArch64::SDOT_VG2_M2Z2Z_BtoS:
21201 case AArch64::SDOT_VG2_M2Z2Z_HtoD:
21202 case AArch64::SDOT_VG2_M2Z2Z_HtoS:
21203 case AArch64::SUB_VG2_M2Z2Z_D:
21204 case AArch64::SUB_VG2_M2Z2Z_S:
21205 case AArch64::UDOT_VG2_M2Z2Z_BtoS:
21206 case AArch64::UDOT_VG2_M2Z2Z_HtoD:
21207 case AArch64::UDOT_VG2_M2Z2Z_HtoS:
21208 case AArch64::USDOT_VG2_M2Z2Z_BToS: {
21209 // op: Zm
21210 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 5, Fixups, STI);
21211 op &= UINT64_C(15);
21212 op <<= 17;
21213 Value |= op;
21214 // op: Zn
21215 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
21216 op &= UINT64_C(15);
21217 op <<= 6;
21218 Value |= op;
21219 // op: Rv
21220 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21221 op &= UINT64_C(3);
21222 op <<= 13;
21223 Value |= op;
21224 // op: imm3
21225 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21226 op &= UINT64_C(7);
21227 Value |= op;
21228 break;
21229 }
21230 case AArch64::BFMAXNM_VG4_4Z2Z_H:
21231 case AArch64::BFMAX_VG4_4Z2Z_H:
21232 case AArch64::BFMINNM_VG4_4Z2Z_H:
21233 case AArch64::BFMIN_VG4_4Z2Z_H:
21234 case AArch64::FAMAX_4Z4Z_D:
21235 case AArch64::FAMAX_4Z4Z_H:
21236 case AArch64::FAMAX_4Z4Z_S:
21237 case AArch64::FAMIN_4Z4Z_D:
21238 case AArch64::FAMIN_4Z4Z_H:
21239 case AArch64::FAMIN_4Z4Z_S:
21240 case AArch64::FMAXNM_VG4_4Z4Z_D:
21241 case AArch64::FMAXNM_VG4_4Z4Z_H:
21242 case AArch64::FMAXNM_VG4_4Z4Z_S:
21243 case AArch64::FMAX_VG4_4Z4Z_D:
21244 case AArch64::FMAX_VG4_4Z4Z_H:
21245 case AArch64::FMAX_VG4_4Z4Z_S:
21246 case AArch64::FMINNM_VG4_4Z4Z_D:
21247 case AArch64::FMINNM_VG4_4Z4Z_H:
21248 case AArch64::FMINNM_VG4_4Z4Z_S:
21249 case AArch64::FMIN_VG4_4Z4Z_D:
21250 case AArch64::FMIN_VG4_4Z4Z_H:
21251 case AArch64::FMIN_VG4_4Z4Z_S:
21252 case AArch64::FSCALE_4Z4Z_D:
21253 case AArch64::FSCALE_4Z4Z_H:
21254 case AArch64::FSCALE_4Z4Z_S:
21255 case AArch64::SMAX_VG4_4Z4Z_B:
21256 case AArch64::SMAX_VG4_4Z4Z_D:
21257 case AArch64::SMAX_VG4_4Z4Z_H:
21258 case AArch64::SMAX_VG4_4Z4Z_S:
21259 case AArch64::SMIN_VG4_4Z4Z_B:
21260 case AArch64::SMIN_VG4_4Z4Z_D:
21261 case AArch64::SMIN_VG4_4Z4Z_H:
21262 case AArch64::SMIN_VG4_4Z4Z_S:
21263 case AArch64::SQDMULH_VG4_4Z4Z_B:
21264 case AArch64::SQDMULH_VG4_4Z4Z_D:
21265 case AArch64::SQDMULH_VG4_4Z4Z_H:
21266 case AArch64::SQDMULH_VG4_4Z4Z_S:
21267 case AArch64::SRSHL_VG4_4Z4Z_B:
21268 case AArch64::SRSHL_VG4_4Z4Z_D:
21269 case AArch64::SRSHL_VG4_4Z4Z_H:
21270 case AArch64::SRSHL_VG4_4Z4Z_S:
21271 case AArch64::UMAX_VG4_4Z4Z_B:
21272 case AArch64::UMAX_VG4_4Z4Z_D:
21273 case AArch64::UMAX_VG4_4Z4Z_H:
21274 case AArch64::UMAX_VG4_4Z4Z_S:
21275 case AArch64::UMIN_VG4_4Z4Z_B:
21276 case AArch64::UMIN_VG4_4Z4Z_D:
21277 case AArch64::UMIN_VG4_4Z4Z_H:
21278 case AArch64::UMIN_VG4_4Z4Z_S:
21279 case AArch64::URSHL_VG4_4Z4Z_B:
21280 case AArch64::URSHL_VG4_4Z4Z_D:
21281 case AArch64::URSHL_VG4_4Z4Z_H:
21282 case AArch64::URSHL_VG4_4Z4Z_S: {
21283 // op: Zm
21284 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 2, Fixups, STI);
21285 op &= UINT64_C(7);
21286 op <<= 18;
21287 Value |= op;
21288 // op: Zdn
21289 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
21290 op &= UINT64_C(7);
21291 op <<= 2;
21292 Value |= op;
21293 break;
21294 }
21295 case AArch64::FMLALL_VG4_M4Z4Z_BtoS:
21296 case AArch64::SMLALL_VG4_M4Z4Z_BtoS:
21297 case AArch64::SMLALL_VG4_M4Z4Z_HtoD:
21298 case AArch64::SMLSLL_VG4_M4Z4Z_BtoS:
21299 case AArch64::SMLSLL_VG4_M4Z4Z_HtoD:
21300 case AArch64::UMLALL_VG4_M4Z4Z_BtoS:
21301 case AArch64::UMLALL_VG4_M4Z4Z_HtoD:
21302 case AArch64::UMLSLL_VG4_M4Z4Z_BtoS:
21303 case AArch64::UMLSLL_VG4_M4Z4Z_HtoD:
21304 case AArch64::USMLALL_VG4_M4Z4Z_BtoS: {
21305 // op: Zm
21306 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 5, Fixups, STI);
21307 op &= UINT64_C(7);
21308 op <<= 18;
21309 Value |= op;
21310 // op: Rv
21311 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21312 op &= UINT64_C(3);
21313 op <<= 13;
21314 Value |= op;
21315 // op: Zn
21316 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
21317 op &= UINT64_C(7);
21318 op <<= 7;
21319 Value |= op;
21320 // op: imm
21321 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21322 op &= UINT64_C(1);
21323 Value |= op;
21324 break;
21325 }
21326 case AArch64::ADD_VG4_M4Z4Z_D:
21327 case AArch64::ADD_VG4_M4Z4Z_S:
21328 case AArch64::BFDOT_VG4_M4Z4Z_HtoS:
21329 case AArch64::BFMLA_VG4_M4Z4Z:
21330 case AArch64::BFMLS_VG4_M4Z4Z:
21331 case AArch64::FDOT_VG4_M4Z4Z_BtoH:
21332 case AArch64::FDOT_VG4_M4Z4Z_BtoS:
21333 case AArch64::FDOT_VG4_M4Z4Z_HtoS:
21334 case AArch64::FMLA_VG4_M4Z4Z_D:
21335 case AArch64::FMLA_VG4_M4Z4Z_H:
21336 case AArch64::FMLA_VG4_M4Z4Z_S:
21337 case AArch64::FMLS_VG4_M4Z2Z_H:
21338 case AArch64::FMLS_VG4_M4Z4Z_D:
21339 case AArch64::FMLS_VG4_M4Z4Z_S:
21340 case AArch64::SDOT_VG4_M4Z4Z_BtoS:
21341 case AArch64::SDOT_VG4_M4Z4Z_HtoD:
21342 case AArch64::SDOT_VG4_M4Z4Z_HtoS:
21343 case AArch64::SUB_VG4_M4Z4Z_D:
21344 case AArch64::SUB_VG4_M4Z4Z_S:
21345 case AArch64::UDOT_VG4_M4Z4Z_BtoS:
21346 case AArch64::UDOT_VG4_M4Z4Z_HtoD:
21347 case AArch64::UDOT_VG4_M4Z4Z_HtoS:
21348 case AArch64::USDOT_VG4_M4Z4Z_BToS: {
21349 // op: Zm
21350 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 5, Fixups, STI);
21351 op &= UINT64_C(7);
21352 op <<= 18;
21353 Value |= op;
21354 // op: Zn
21355 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
21356 op &= UINT64_C(7);
21357 op <<= 7;
21358 Value |= op;
21359 // op: Rv
21360 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21361 op &= UINT64_C(3);
21362 op <<= 13;
21363 Value |= op;
21364 // op: imm3
21365 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21366 op &= UINT64_C(7);
21367 Value |= op;
21368 break;
21369 }
21370 case AArch64::ADD_VG2_2ZZ_B:
21371 case AArch64::ADD_VG2_2ZZ_D:
21372 case AArch64::ADD_VG2_2ZZ_H:
21373 case AArch64::ADD_VG2_2ZZ_S:
21374 case AArch64::BFMAXNM_VG2_2ZZ_H:
21375 case AArch64::BFMAX_VG2_2ZZ_H:
21376 case AArch64::BFMINNM_VG2_2ZZ_H:
21377 case AArch64::BFMIN_VG2_2ZZ_H:
21378 case AArch64::FMAXNM_VG2_2ZZ_D:
21379 case AArch64::FMAXNM_VG2_2ZZ_H:
21380 case AArch64::FMAXNM_VG2_2ZZ_S:
21381 case AArch64::FMAX_VG2_2ZZ_D:
21382 case AArch64::FMAX_VG2_2ZZ_H:
21383 case AArch64::FMAX_VG2_2ZZ_S:
21384 case AArch64::FMINNM_VG2_2ZZ_D:
21385 case AArch64::FMINNM_VG2_2ZZ_H:
21386 case AArch64::FMINNM_VG2_2ZZ_S:
21387 case AArch64::FMIN_VG2_2ZZ_D:
21388 case AArch64::FMIN_VG2_2ZZ_H:
21389 case AArch64::FMIN_VG2_2ZZ_S:
21390 case AArch64::FSCALE_2ZZ_D:
21391 case AArch64::FSCALE_2ZZ_H:
21392 case AArch64::FSCALE_2ZZ_S:
21393 case AArch64::SMAX_VG2_2ZZ_B:
21394 case AArch64::SMAX_VG2_2ZZ_D:
21395 case AArch64::SMAX_VG2_2ZZ_H:
21396 case AArch64::SMAX_VG2_2ZZ_S:
21397 case AArch64::SMIN_VG2_2ZZ_B:
21398 case AArch64::SMIN_VG2_2ZZ_D:
21399 case AArch64::SMIN_VG2_2ZZ_H:
21400 case AArch64::SMIN_VG2_2ZZ_S:
21401 case AArch64::SQDMULH_VG2_2ZZ_B:
21402 case AArch64::SQDMULH_VG2_2ZZ_D:
21403 case AArch64::SQDMULH_VG2_2ZZ_H:
21404 case AArch64::SQDMULH_VG2_2ZZ_S:
21405 case AArch64::SRSHL_VG2_2ZZ_B:
21406 case AArch64::SRSHL_VG2_2ZZ_D:
21407 case AArch64::SRSHL_VG2_2ZZ_H:
21408 case AArch64::SRSHL_VG2_2ZZ_S:
21409 case AArch64::UMAX_VG2_2ZZ_B:
21410 case AArch64::UMAX_VG2_2ZZ_D:
21411 case AArch64::UMAX_VG2_2ZZ_H:
21412 case AArch64::UMAX_VG2_2ZZ_S:
21413 case AArch64::UMIN_VG2_2ZZ_B:
21414 case AArch64::UMIN_VG2_2ZZ_D:
21415 case AArch64::UMIN_VG2_2ZZ_H:
21416 case AArch64::UMIN_VG2_2ZZ_S:
21417 case AArch64::URSHL_VG2_2ZZ_B:
21418 case AArch64::URSHL_VG2_2ZZ_D:
21419 case AArch64::URSHL_VG2_2ZZ_H:
21420 case AArch64::URSHL_VG2_2ZZ_S: {
21421 // op: Zm
21422 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21423 op &= UINT64_C(15);
21424 op <<= 16;
21425 Value |= op;
21426 // op: Zdn
21427 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
21428 op &= UINT64_C(15);
21429 op <<= 1;
21430 Value |= op;
21431 break;
21432 }
21433 case AArch64::ADD_VG4_4ZZ_B:
21434 case AArch64::ADD_VG4_4ZZ_D:
21435 case AArch64::ADD_VG4_4ZZ_H:
21436 case AArch64::ADD_VG4_4ZZ_S:
21437 case AArch64::BFMAXNM_VG4_4ZZ_H:
21438 case AArch64::BFMAX_VG4_4ZZ_H:
21439 case AArch64::BFMINNM_VG4_4ZZ_H:
21440 case AArch64::BFMIN_VG4_4ZZ_H:
21441 case AArch64::FMAXNM_VG4_4ZZ_D:
21442 case AArch64::FMAXNM_VG4_4ZZ_H:
21443 case AArch64::FMAXNM_VG4_4ZZ_S:
21444 case AArch64::FMAX_VG4_4ZZ_D:
21445 case AArch64::FMAX_VG4_4ZZ_H:
21446 case AArch64::FMAX_VG4_4ZZ_S:
21447 case AArch64::FMINNM_VG4_4ZZ_D:
21448 case AArch64::FMINNM_VG4_4ZZ_H:
21449 case AArch64::FMINNM_VG4_4ZZ_S:
21450 case AArch64::FMIN_VG4_4ZZ_D:
21451 case AArch64::FMIN_VG4_4ZZ_H:
21452 case AArch64::FMIN_VG4_4ZZ_S:
21453 case AArch64::FSCALE_4ZZ_D:
21454 case AArch64::FSCALE_4ZZ_H:
21455 case AArch64::FSCALE_4ZZ_S:
21456 case AArch64::SMAX_VG4_4ZZ_B:
21457 case AArch64::SMAX_VG4_4ZZ_D:
21458 case AArch64::SMAX_VG4_4ZZ_H:
21459 case AArch64::SMAX_VG4_4ZZ_S:
21460 case AArch64::SMIN_VG4_4ZZ_B:
21461 case AArch64::SMIN_VG4_4ZZ_D:
21462 case AArch64::SMIN_VG4_4ZZ_H:
21463 case AArch64::SMIN_VG4_4ZZ_S:
21464 case AArch64::SQDMULH_VG4_4ZZ_B:
21465 case AArch64::SQDMULH_VG4_4ZZ_D:
21466 case AArch64::SQDMULH_VG4_4ZZ_H:
21467 case AArch64::SQDMULH_VG4_4ZZ_S:
21468 case AArch64::SRSHL_VG4_4ZZ_B:
21469 case AArch64::SRSHL_VG4_4ZZ_D:
21470 case AArch64::SRSHL_VG4_4ZZ_H:
21471 case AArch64::SRSHL_VG4_4ZZ_S:
21472 case AArch64::UMAX_VG4_4ZZ_B:
21473 case AArch64::UMAX_VG4_4ZZ_D:
21474 case AArch64::UMAX_VG4_4ZZ_H:
21475 case AArch64::UMAX_VG4_4ZZ_S:
21476 case AArch64::UMIN_VG4_4ZZ_B:
21477 case AArch64::UMIN_VG4_4ZZ_D:
21478 case AArch64::UMIN_VG4_4ZZ_H:
21479 case AArch64::UMIN_VG4_4ZZ_S:
21480 case AArch64::URSHL_VG4_4ZZ_B:
21481 case AArch64::URSHL_VG4_4ZZ_D:
21482 case AArch64::URSHL_VG4_4ZZ_H:
21483 case AArch64::URSHL_VG4_4ZZ_S: {
21484 // op: Zm
21485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21486 op &= UINT64_C(15);
21487 op <<= 16;
21488 Value |= op;
21489 // op: Zdn
21490 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
21491 op &= UINT64_C(7);
21492 op <<= 2;
21493 Value |= op;
21494 break;
21495 }
21496 case AArch64::BFMMLA_ZZZ: {
21497 // op: Zm
21498 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21499 op &= UINT64_C(31);
21500 op <<= 16;
21501 Value |= op;
21502 // op: Zda
21503 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21504 op &= UINT64_C(31);
21505 Value |= op;
21506 // op: Zn
21507 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21508 op &= UINT64_C(31);
21509 op <<= 5;
21510 Value |= op;
21511 break;
21512 }
21513 case AArch64::BFCLAMP_VG2_2ZZZ_H:
21514 case AArch64::FCLAMP_VG2_2Z2Z_D:
21515 case AArch64::FCLAMP_VG2_2Z2Z_H:
21516 case AArch64::FCLAMP_VG2_2Z2Z_S:
21517 case AArch64::SCLAMP_VG2_2Z2Z_B:
21518 case AArch64::SCLAMP_VG2_2Z2Z_D:
21519 case AArch64::SCLAMP_VG2_2Z2Z_H:
21520 case AArch64::SCLAMP_VG2_2Z2Z_S:
21521 case AArch64::UCLAMP_VG2_2Z2Z_B:
21522 case AArch64::UCLAMP_VG2_2Z2Z_D:
21523 case AArch64::UCLAMP_VG2_2Z2Z_H:
21524 case AArch64::UCLAMP_VG2_2Z2Z_S: {
21525 // op: Zm
21526 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21527 op &= UINT64_C(31);
21528 op <<= 16;
21529 Value |= op;
21530 // op: Zn
21531 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21532 op &= UINT64_C(31);
21533 op <<= 5;
21534 Value |= op;
21535 // op: Zd
21536 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
21537 op &= UINT64_C(15);
21538 op <<= 1;
21539 Value |= op;
21540 break;
21541 }
21542 case AArch64::BFCLAMP_VG4_4ZZZ_H:
21543 case AArch64::FCLAMP_VG4_4Z4Z_D:
21544 case AArch64::FCLAMP_VG4_4Z4Z_H:
21545 case AArch64::FCLAMP_VG4_4Z4Z_S:
21546 case AArch64::SCLAMP_VG4_4Z4Z_B:
21547 case AArch64::SCLAMP_VG4_4Z4Z_D:
21548 case AArch64::SCLAMP_VG4_4Z4Z_H:
21549 case AArch64::SCLAMP_VG4_4Z4Z_S:
21550 case AArch64::UCLAMP_VG4_4Z4Z_B:
21551 case AArch64::UCLAMP_VG4_4Z4Z_D:
21552 case AArch64::UCLAMP_VG4_4Z4Z_H:
21553 case AArch64::UCLAMP_VG4_4Z4Z_S: {
21554 // op: Zm
21555 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21556 op &= UINT64_C(31);
21557 op <<= 16;
21558 Value |= op;
21559 // op: Zn
21560 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21561 op &= UINT64_C(31);
21562 op <<= 5;
21563 Value |= op;
21564 // op: Zd
21565 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
21566 op &= UINT64_C(7);
21567 op <<= 2;
21568 Value |= op;
21569 break;
21570 }
21571 case AArch64::BFCLAMP_ZZZ:
21572 case AArch64::FCLAMP_ZZZ_D:
21573 case AArch64::FCLAMP_ZZZ_H:
21574 case AArch64::FCLAMP_ZZZ_S:
21575 case AArch64::SCLAMP_ZZZ_B:
21576 case AArch64::SCLAMP_ZZZ_D:
21577 case AArch64::SCLAMP_ZZZ_H:
21578 case AArch64::SCLAMP_ZZZ_S:
21579 case AArch64::UCLAMP_ZZZ_B:
21580 case AArch64::UCLAMP_ZZZ_D:
21581 case AArch64::UCLAMP_ZZZ_H:
21582 case AArch64::UCLAMP_ZZZ_S: {
21583 // op: Zm
21584 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21585 op &= UINT64_C(31);
21586 op <<= 16;
21587 Value |= op;
21588 // op: Zn
21589 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
21590 op &= UINT64_C(31);
21591 op <<= 5;
21592 Value |= op;
21593 // op: Zd
21594 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
21595 op &= UINT64_C(31);
21596 Value |= op;
21597 break;
21598 }
21599 case AArch64::FVDOTB_VG4_M2ZZI_BtoS:
21600 case AArch64::FVDOTT_VG4_M2ZZI_BtoS: {
21601 // op: Zm
21602 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21603 op &= UINT64_C(15);
21604 op <<= 16;
21605 Value |= op;
21606 // op: Rv
21607 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21608 op &= UINT64_C(3);
21609 op <<= 13;
21610 Value |= op;
21611 // op: Zn
21612 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
21613 op &= UINT64_C(15);
21614 op <<= 6;
21615 Value |= op;
21616 // op: imm3
21617 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21618 op &= UINT64_C(7);
21619 Value |= op;
21620 // op: i
21621 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
21622 Value |= (op & UINT64_C(2)) << 9;
21623 Value |= (op & UINT64_C(1)) << 3;
21624 break;
21625 }
21626 case AArch64::BFMLA_VG2_M2ZZI:
21627 case AArch64::BFMLS_VG2_M2ZZI:
21628 case AArch64::FDOT_VG2_M2ZZI_BtoH:
21629 case AArch64::FMLA_VG2_M2ZZI_H:
21630 case AArch64::FMLS_VG2_M2ZZI_H:
21631 case AArch64::FVDOT_VG2_M2ZZI_BtoH: {
21632 // op: Zm
21633 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21634 op &= UINT64_C(15);
21635 op <<= 16;
21636 Value |= op;
21637 // op: Rv
21638 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21639 op &= UINT64_C(3);
21640 op <<= 13;
21641 Value |= op;
21642 // op: Zn
21643 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
21644 op &= UINT64_C(15);
21645 op <<= 6;
21646 Value |= op;
21647 // op: imm3
21648 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21649 op &= UINT64_C(7);
21650 Value |= op;
21651 // op: i
21652 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
21653 Value |= (op & UINT64_C(6)) << 9;
21654 Value |= (op & UINT64_C(1)) << 3;
21655 break;
21656 }
21657 case AArch64::BFDOT_VG2_M2ZZI_HtoS:
21658 case AArch64::BFVDOT_VG2_M2ZZI_HtoS:
21659 case AArch64::FDOT_VG2_M2ZZI_BtoS:
21660 case AArch64::FDOT_VG2_M2ZZI_HtoS:
21661 case AArch64::FMLA_VG2_M2ZZI_S:
21662 case AArch64::FMLS_VG2_M2ZZI_S:
21663 case AArch64::FVDOT_VG2_M2ZZI_HtoS:
21664 case AArch64::SDOT_VG2_M2ZZI_BToS:
21665 case AArch64::SDOT_VG2_M2ZZI_HToS:
21666 case AArch64::SUDOT_VG2_M2ZZI_BToS:
21667 case AArch64::SVDOT_VG2_M2ZZI_HtoS:
21668 case AArch64::UDOT_VG2_M2ZZI_BToS:
21669 case AArch64::UDOT_VG2_M2ZZI_HToS:
21670 case AArch64::USDOT_VG2_M2ZZI_BToS:
21671 case AArch64::UVDOT_VG2_M2ZZI_HtoS: {
21672 // op: Zm
21673 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21674 op &= UINT64_C(15);
21675 op <<= 16;
21676 Value |= op;
21677 // op: Rv
21678 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21679 op &= UINT64_C(3);
21680 op <<= 13;
21681 Value |= op;
21682 // op: Zn
21683 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
21684 op &= UINT64_C(15);
21685 op <<= 6;
21686 Value |= op;
21687 // op: imm3
21688 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21689 op &= UINT64_C(7);
21690 Value |= op;
21691 // op: i
21692 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
21693 op &= UINT64_C(3);
21694 op <<= 10;
21695 Value |= op;
21696 break;
21697 }
21698 case AArch64::BFMLA_VG4_M4ZZI:
21699 case AArch64::BFMLS_VG4_M4ZZI:
21700 case AArch64::FDOT_VG4_M4ZZI_BtoH:
21701 case AArch64::FMLA_VG4_M4ZZI_H:
21702 case AArch64::FMLS_VG4_M4ZZI_H: {
21703 // op: Zm
21704 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21705 op &= UINT64_C(15);
21706 op <<= 16;
21707 Value |= op;
21708 // op: Rv
21709 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21710 op &= UINT64_C(3);
21711 op <<= 13;
21712 Value |= op;
21713 // op: Zn
21714 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
21715 op &= UINT64_C(7);
21716 op <<= 7;
21717 Value |= op;
21718 // op: imm3
21719 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21720 op &= UINT64_C(7);
21721 Value |= op;
21722 // op: i
21723 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
21724 Value |= (op & UINT64_C(6)) << 9;
21725 Value |= (op & UINT64_C(1)) << 3;
21726 break;
21727 }
21728 case AArch64::BFDOT_VG4_M4ZZI_HtoS:
21729 case AArch64::FDOT_VG4_M4ZZI_BtoS:
21730 case AArch64::FDOT_VG4_M4ZZI_HtoS:
21731 case AArch64::FMLA_VG4_M4ZZI_S:
21732 case AArch64::FMLS_VG4_M4ZZI_S:
21733 case AArch64::SDOT_VG4_M4ZZI_BToS:
21734 case AArch64::SDOT_VG4_M4ZZI_HToS:
21735 case AArch64::SUDOT_VG4_M4ZZI_BToS:
21736 case AArch64::SUVDOT_VG4_M4ZZI_BToS:
21737 case AArch64::SVDOT_VG4_M4ZZI_BtoS:
21738 case AArch64::UDOT_VG4_M4ZZI_BtoS:
21739 case AArch64::UDOT_VG4_M4ZZI_HToS:
21740 case AArch64::USDOT_VG4_M4ZZI_BToS:
21741 case AArch64::USVDOT_VG4_M4ZZI_BToS:
21742 case AArch64::UVDOT_VG4_M4ZZI_BtoS: {
21743 // op: Zm
21744 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21745 op &= UINT64_C(15);
21746 op <<= 16;
21747 Value |= op;
21748 // op: Rv
21749 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21750 op &= UINT64_C(3);
21751 op <<= 13;
21752 Value |= op;
21753 // op: Zn
21754 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
21755 op &= UINT64_C(7);
21756 op <<= 7;
21757 Value |= op;
21758 // op: imm3
21759 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21760 op &= UINT64_C(7);
21761 Value |= op;
21762 // op: i
21763 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
21764 op &= UINT64_C(3);
21765 op <<= 10;
21766 Value |= op;
21767 break;
21768 }
21769 case AArch64::FMLALL_VG2_M2ZZ_BtoS:
21770 case AArch64::FMLALL_VG4_M4ZZ_BtoS:
21771 case AArch64::SMLALL_VG2_M2ZZ_BtoS:
21772 case AArch64::SMLALL_VG2_M2ZZ_HtoD:
21773 case AArch64::SMLALL_VG4_M4ZZ_BtoS:
21774 case AArch64::SMLALL_VG4_M4ZZ_HtoD:
21775 case AArch64::SMLSLL_VG2_M2ZZ_BtoS:
21776 case AArch64::SMLSLL_VG2_M2ZZ_HtoD:
21777 case AArch64::SMLSLL_VG4_M4ZZ_BtoS:
21778 case AArch64::SMLSLL_VG4_M4ZZ_HtoD:
21779 case AArch64::SUMLALL_VG2_M2ZZ_BtoS:
21780 case AArch64::SUMLALL_VG4_M4ZZ_BtoS:
21781 case AArch64::UMLALL_VG2_M2ZZ_BtoS:
21782 case AArch64::UMLALL_VG2_M2ZZ_HtoD:
21783 case AArch64::UMLALL_VG4_M4ZZ_BtoS:
21784 case AArch64::UMLALL_VG4_M4ZZ_HtoD:
21785 case AArch64::UMLSLL_VG2_M2ZZ_BtoS:
21786 case AArch64::UMLSLL_VG2_M2ZZ_HtoD:
21787 case AArch64::UMLSLL_VG4_M4ZZ_BtoS:
21788 case AArch64::UMLSLL_VG4_M4ZZ_HtoD:
21789 case AArch64::USMLALL_VG2_M2ZZ_BtoS:
21790 case AArch64::USMLALL_VG4_M4ZZ_BtoS: {
21791 // op: Zm
21792 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21793 op &= UINT64_C(15);
21794 op <<= 16;
21795 Value |= op;
21796 // op: Rv
21797 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21798 op &= UINT64_C(3);
21799 op <<= 13;
21800 Value |= op;
21801 // op: Zn
21802 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
21803 op &= UINT64_C(31);
21804 op <<= 5;
21805 Value |= op;
21806 // op: imm
21807 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21808 op &= UINT64_C(1);
21809 Value |= op;
21810 break;
21811 }
21812 case AArch64::FMLALL_MZZ_BtoS:
21813 case AArch64::SMLALL_MZZ_BtoS:
21814 case AArch64::SMLALL_MZZ_HtoD:
21815 case AArch64::SMLSLL_MZZ_BtoS:
21816 case AArch64::SMLSLL_MZZ_HtoD:
21817 case AArch64::UMLALL_MZZ_BtoS:
21818 case AArch64::UMLALL_MZZ_HtoD:
21819 case AArch64::UMLSLL_MZZ_BtoS:
21820 case AArch64::UMLSLL_MZZ_HtoD:
21821 case AArch64::USMLALL_MZZ_BtoS: {
21822 // op: Zm
21823 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21824 op &= UINT64_C(15);
21825 op <<= 16;
21826 Value |= op;
21827 // op: Rv
21828 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21829 op &= UINT64_C(3);
21830 op <<= 13;
21831 Value |= op;
21832 // op: Zn
21833 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
21834 op &= UINT64_C(31);
21835 op <<= 5;
21836 Value |= op;
21837 // op: imm
21838 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21839 op &= UINT64_C(3);
21840 Value |= op;
21841 break;
21842 }
21843 case AArch64::FMLALL_VG2_M2ZZI_BtoS:
21844 case AArch64::SMLALL_VG2_M2ZZI_BtoS:
21845 case AArch64::SMLSLL_VG2_M2ZZI_BtoS:
21846 case AArch64::SUMLALL_VG2_M2ZZI_BtoS:
21847 case AArch64::UMLALL_VG2_M2ZZI_BtoS:
21848 case AArch64::UMLSLL_VG2_M2ZZI_BtoS:
21849 case AArch64::USMLALL_VG2_M2ZZI_BtoS: {
21850 // op: Zm
21851 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21852 op &= UINT64_C(15);
21853 op <<= 16;
21854 Value |= op;
21855 // op: Rv
21856 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21857 op &= UINT64_C(3);
21858 op <<= 13;
21859 Value |= op;
21860 // op: i
21861 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
21862 Value |= (op & UINT64_C(12)) << 8;
21863 Value |= (op & UINT64_C(3)) << 1;
21864 // op: imm
21865 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21866 op &= UINT64_C(1);
21867 Value |= op;
21868 // op: Zn
21869 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
21870 op &= UINT64_C(15);
21871 op <<= 6;
21872 Value |= op;
21873 break;
21874 }
21875 case AArch64::FMLALL_VG4_M4ZZI_BtoS:
21876 case AArch64::SMLALL_VG4_M4ZZI_BtoS:
21877 case AArch64::SMLSLL_VG4_M4ZZI_BtoS:
21878 case AArch64::SUMLALL_VG4_M4ZZI_BtoS:
21879 case AArch64::UMLALL_VG4_M4ZZI_BtoS:
21880 case AArch64::UMLSLL_VG4_M4ZZI_BtoS:
21881 case AArch64::USMLALL_VG4_M4ZZI_BtoS: {
21882 // op: Zm
21883 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21884 op &= UINT64_C(15);
21885 op <<= 16;
21886 Value |= op;
21887 // op: Rv
21888 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21889 op &= UINT64_C(3);
21890 op <<= 13;
21891 Value |= op;
21892 // op: i
21893 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
21894 Value |= (op & UINT64_C(12)) << 8;
21895 Value |= (op & UINT64_C(3)) << 1;
21896 // op: imm
21897 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21898 op &= UINT64_C(1);
21899 Value |= op;
21900 // op: Zn
21901 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
21902 op &= UINT64_C(7);
21903 op <<= 7;
21904 Value |= op;
21905 break;
21906 }
21907 case AArch64::FMLAL_VG2_M2ZZI_BtoH: {
21908 // op: Zm
21909 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21910 op &= UINT64_C(15);
21911 op <<= 16;
21912 Value |= op;
21913 // op: Rv
21914 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21915 op &= UINT64_C(3);
21916 op <<= 13;
21917 Value |= op;
21918 // op: i
21919 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
21920 Value |= (op & UINT64_C(12)) << 8;
21921 Value |= (op & UINT64_C(3)) << 2;
21922 // op: imm2
21923 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21924 op &= UINT64_C(3);
21925 Value |= op;
21926 // op: Zn
21927 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
21928 op &= UINT64_C(15);
21929 op <<= 6;
21930 Value |= op;
21931 break;
21932 }
21933 case AArch64::FMLAL_VG4_M4ZZI_BtoH: {
21934 // op: Zm
21935 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21936 op &= UINT64_C(15);
21937 op <<= 16;
21938 Value |= op;
21939 // op: Rv
21940 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21941 op &= UINT64_C(3);
21942 op <<= 13;
21943 Value |= op;
21944 // op: i
21945 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
21946 Value |= (op & UINT64_C(12)) << 8;
21947 Value |= (op & UINT64_C(3)) << 2;
21948 // op: imm2
21949 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21950 op &= UINT64_C(3);
21951 Value |= op;
21952 // op: Zn
21953 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
21954 op &= UINT64_C(7);
21955 op <<= 7;
21956 Value |= op;
21957 break;
21958 }
21959 case AArch64::SMLALL_MZZI_HtoD:
21960 case AArch64::SMLSLL_MZZI_HtoD:
21961 case AArch64::UMLALL_MZZI_HtoD:
21962 case AArch64::UMLSLL_MZZI_HtoD: {
21963 // op: Zm
21964 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21965 op &= UINT64_C(15);
21966 op <<= 16;
21967 Value |= op;
21968 // op: Rv
21969 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21970 op &= UINT64_C(3);
21971 op <<= 13;
21972 Value |= op;
21973 // op: i
21974 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
21975 Value |= (op & UINT64_C(4)) << 13;
21976 Value |= (op & UINT64_C(3)) << 10;
21977 // op: Zn
21978 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
21979 op &= UINT64_C(31);
21980 op <<= 5;
21981 Value |= op;
21982 // op: imm2
21983 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
21984 op &= UINT64_C(3);
21985 Value |= op;
21986 break;
21987 }
21988 case AArch64::SMLALL_VG2_M2ZZI_HtoD:
21989 case AArch64::SMLSLL_VG2_M2ZZI_HtoD:
21990 case AArch64::UMLALL_VG2_M2ZZI_HtoD:
21991 case AArch64::UMLSLL_VG2_M2ZZI_HtoD: {
21992 // op: Zm
21993 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
21994 op &= UINT64_C(15);
21995 op <<= 16;
21996 Value |= op;
21997 // op: Rv
21998 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
21999 op &= UINT64_C(3);
22000 op <<= 13;
22001 Value |= op;
22002 // op: i
22003 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
22004 Value |= (op & UINT64_C(4)) << 8;
22005 Value |= (op & UINT64_C(3)) << 1;
22006 // op: imm
22007 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22008 op &= UINT64_C(1);
22009 Value |= op;
22010 // op: Zn
22011 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
22012 op &= UINT64_C(15);
22013 op <<= 6;
22014 Value |= op;
22015 break;
22016 }
22017 case AArch64::SMLALL_VG4_M4ZZI_HtoD:
22018 case AArch64::SMLSLL_VG4_M4ZZI_HtoD:
22019 case AArch64::UMLALL_VG4_M4ZZI_HtoD:
22020 case AArch64::UMLSLL_VG4_M4ZZI_HtoD: {
22021 // op: Zm
22022 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22023 op &= UINT64_C(15);
22024 op <<= 16;
22025 Value |= op;
22026 // op: Rv
22027 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
22028 op &= UINT64_C(3);
22029 op <<= 13;
22030 Value |= op;
22031 // op: i
22032 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
22033 Value |= (op & UINT64_C(4)) << 8;
22034 Value |= (op & UINT64_C(3)) << 1;
22035 // op: imm
22036 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22037 op &= UINT64_C(1);
22038 Value |= op;
22039 // op: Zn
22040 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
22041 op &= UINT64_C(7);
22042 op <<= 7;
22043 Value |= op;
22044 break;
22045 }
22046 case AArch64::FMLAL_MZZI_BtoH: {
22047 // op: Zm
22048 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22049 op &= UINT64_C(15);
22050 op <<= 16;
22051 Value |= op;
22052 // op: Rv
22053 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
22054 op &= UINT64_C(3);
22055 op <<= 13;
22056 Value |= op;
22057 // op: i
22058 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
22059 Value |= (op & UINT64_C(8)) << 12;
22060 Value |= (op & UINT64_C(6)) << 9;
22061 Value |= (op & UINT64_C(1)) << 3;
22062 // op: Zn
22063 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22064 op &= UINT64_C(31);
22065 op <<= 5;
22066 Value |= op;
22067 // op: imm3
22068 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22069 op &= UINT64_C(7);
22070 Value |= op;
22071 break;
22072 }
22073 case AArch64::FMLALL_MZZI_BtoS:
22074 case AArch64::SMLALL_MZZI_BtoS:
22075 case AArch64::SMLSLL_MZZI_BtoS:
22076 case AArch64::SUMLALL_MZZI_BtoS:
22077 case AArch64::UMLALL_MZZI_BtoS:
22078 case AArch64::UMLSLL_MZZI_BtoS:
22079 case AArch64::USMLALL_MZZI_BtoS: {
22080 // op: Zm
22081 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22082 op &= UINT64_C(15);
22083 op <<= 16;
22084 Value |= op;
22085 // op: Rv
22086 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
22087 op &= UINT64_C(3);
22088 op <<= 13;
22089 Value |= op;
22090 // op: i
22091 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
22092 Value |= (op & UINT64_C(8)) << 12;
22093 Value |= (op & UINT64_C(7)) << 10;
22094 // op: Zn
22095 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22096 op &= UINT64_C(31);
22097 op <<= 5;
22098 Value |= op;
22099 // op: imm2
22100 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22101 op &= UINT64_C(3);
22102 Value |= op;
22103 break;
22104 }
22105 case AArch64::FMLA_VG2_M2ZZI_D:
22106 case AArch64::FMLS_VG2_M2ZZI_D:
22107 case AArch64::SDOT_VG2_M2ZZI_HtoD:
22108 case AArch64::UDOT_VG2_M2ZZI_HtoD: {
22109 // op: Zm
22110 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22111 op &= UINT64_C(15);
22112 op <<= 16;
22113 Value |= op;
22114 // op: Rv
22115 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
22116 op &= UINT64_C(3);
22117 op <<= 13;
22118 Value |= op;
22119 // op: i1
22120 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
22121 op &= UINT64_C(1);
22122 op <<= 10;
22123 Value |= op;
22124 // op: Zn
22125 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
22126 op &= UINT64_C(15);
22127 op <<= 6;
22128 Value |= op;
22129 // op: imm3
22130 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22131 op &= UINT64_C(7);
22132 Value |= op;
22133 break;
22134 }
22135 case AArch64::FMLA_VG4_M4ZZI_D:
22136 case AArch64::FMLS_VG4_M4ZZI_D:
22137 case AArch64::SDOT_VG4_M4ZZI_HtoD:
22138 case AArch64::SVDOT_VG4_M4ZZI_HtoD:
22139 case AArch64::UDOT_VG4_M4ZZI_HtoD:
22140 case AArch64::UVDOT_VG4_M4ZZI_HtoD: {
22141 // op: Zm
22142 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22143 op &= UINT64_C(15);
22144 op <<= 16;
22145 Value |= op;
22146 // op: Rv
22147 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
22148 op &= UINT64_C(3);
22149 op <<= 13;
22150 Value |= op;
22151 // op: i1
22152 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
22153 op &= UINT64_C(1);
22154 op <<= 10;
22155 Value |= op;
22156 // op: Zn
22157 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
22158 op &= UINT64_C(7);
22159 op <<= 7;
22160 Value |= op;
22161 // op: imm3
22162 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22163 op &= UINT64_C(7);
22164 Value |= op;
22165 break;
22166 }
22167 case AArch64::BFMLAL_MZZI_HtoS:
22168 case AArch64::BFMLSL_MZZI_HtoS:
22169 case AArch64::FMLAL_MZZI_HtoS:
22170 case AArch64::FMLSL_MZZI_HtoS:
22171 case AArch64::SMLAL_MZZI_HtoS:
22172 case AArch64::SMLSL_MZZI_HtoS:
22173 case AArch64::UMLAL_MZZI_HtoS:
22174 case AArch64::UMLSL_MZZI_HtoS: {
22175 // op: Zm
22176 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22177 op &= UINT64_C(15);
22178 op <<= 16;
22179 Value |= op;
22180 // op: Rv
22181 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
22182 op &= UINT64_C(3);
22183 op <<= 13;
22184 Value |= op;
22185 // op: i3
22186 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
22187 Value |= (op & UINT64_C(4)) << 13;
22188 Value |= (op & UINT64_C(3)) << 10;
22189 // op: Zn
22190 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22191 op &= UINT64_C(31);
22192 op <<= 5;
22193 Value |= op;
22194 // op: imm
22195 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22196 op &= UINT64_C(7);
22197 Value |= op;
22198 break;
22199 }
22200 case AArch64::BFMLAL_VG2_M2ZZI_HtoS:
22201 case AArch64::BFMLSL_VG2_M2ZZI_HtoS:
22202 case AArch64::FMLAL_VG2_M2ZZI_HtoS:
22203 case AArch64::FMLSL_VG2_M2ZZI_HtoS:
22204 case AArch64::SMLAL_VG2_M2ZZI_S:
22205 case AArch64::SMLSL_VG2_M2ZZI_S:
22206 case AArch64::UMLAL_VG2_M2ZZI_S:
22207 case AArch64::UMLSL_VG2_M2ZZI_S: {
22208 // op: Zm
22209 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22210 op &= UINT64_C(15);
22211 op <<= 16;
22212 Value |= op;
22213 // op: Rv
22214 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
22215 op &= UINT64_C(3);
22216 op <<= 13;
22217 Value |= op;
22218 // op: i3
22219 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
22220 Value |= (op & UINT64_C(6)) << 9;
22221 Value |= (op & UINT64_C(1)) << 2;
22222 // op: Zn
22223 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 4, Fixups, STI);
22224 op &= UINT64_C(15);
22225 op <<= 6;
22226 Value |= op;
22227 // op: imm
22228 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22229 op &= UINT64_C(3);
22230 Value |= op;
22231 break;
22232 }
22233 case AArch64::BFMLAL_VG4_M4ZZI_HtoS:
22234 case AArch64::BFMLSL_VG4_M4ZZI_HtoS:
22235 case AArch64::FMLAL_VG4_M4ZZI_HtoS:
22236 case AArch64::FMLSL_VG4_M4ZZI_HtoS:
22237 case AArch64::SMLAL_VG4_M4ZZI_HtoS:
22238 case AArch64::SMLSL_VG4_M4ZZI_HtoS:
22239 case AArch64::UMLAL_VG4_M4ZZI_HtoS:
22240 case AArch64::UMLSL_VG4_M4ZZI_HtoS: {
22241 // op: Zm
22242 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22243 op &= UINT64_C(15);
22244 op <<= 16;
22245 Value |= op;
22246 // op: Rv
22247 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
22248 op &= UINT64_C(3);
22249 op <<= 13;
22250 Value |= op;
22251 // op: i3
22252 op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI);
22253 Value |= (op & UINT64_C(6)) << 9;
22254 Value |= (op & UINT64_C(1)) << 2;
22255 // op: Zn
22256 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 4, Fixups, STI);
22257 op &= UINT64_C(7);
22258 op <<= 7;
22259 Value |= op;
22260 // op: imm
22261 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22262 op &= UINT64_C(3);
22263 Value |= op;
22264 break;
22265 }
22266 case AArch64::ADD_VG2_M2ZZ_D:
22267 case AArch64::ADD_VG2_M2ZZ_S:
22268 case AArch64::ADD_VG4_M4ZZ_D:
22269 case AArch64::ADD_VG4_M4ZZ_S:
22270 case AArch64::BFDOT_VG2_M2ZZ_HtoS:
22271 case AArch64::BFDOT_VG4_M4ZZ_HtoS:
22272 case AArch64::BFMLA_VG2_M2ZZ:
22273 case AArch64::BFMLA_VG4_M4ZZ:
22274 case AArch64::BFMLS_VG2_M2ZZ:
22275 case AArch64::BFMLS_VG4_M4ZZ:
22276 case AArch64::FDOT_VG2_M2ZZ_BtoH:
22277 case AArch64::FDOT_VG2_M2ZZ_BtoS:
22278 case AArch64::FDOT_VG2_M2ZZ_HtoS:
22279 case AArch64::FDOT_VG4_M4ZZ_BtoH:
22280 case AArch64::FDOT_VG4_M4ZZ_BtoS:
22281 case AArch64::FDOT_VG4_M4ZZ_HtoS:
22282 case AArch64::FMLA_VG2_M2ZZ_D:
22283 case AArch64::FMLA_VG2_M2ZZ_H:
22284 case AArch64::FMLA_VG2_M2ZZ_S:
22285 case AArch64::FMLA_VG4_M4ZZ_D:
22286 case AArch64::FMLA_VG4_M4ZZ_H:
22287 case AArch64::FMLA_VG4_M4ZZ_S:
22288 case AArch64::FMLS_VG2_M2ZZ_D:
22289 case AArch64::FMLS_VG2_M2ZZ_H:
22290 case AArch64::FMLS_VG2_M2ZZ_S:
22291 case AArch64::FMLS_VG4_M4ZZ_D:
22292 case AArch64::FMLS_VG4_M4ZZ_H:
22293 case AArch64::FMLS_VG4_M4ZZ_S:
22294 case AArch64::SDOT_VG2_M2ZZ_BtoS:
22295 case AArch64::SDOT_VG2_M2ZZ_HtoD:
22296 case AArch64::SDOT_VG2_M2ZZ_HtoS:
22297 case AArch64::SDOT_VG4_M4ZZ_BtoS:
22298 case AArch64::SDOT_VG4_M4ZZ_HtoD:
22299 case AArch64::SDOT_VG4_M4ZZ_HtoS:
22300 case AArch64::SUB_VG2_M2ZZ_D:
22301 case AArch64::SUB_VG2_M2ZZ_S:
22302 case AArch64::SUB_VG4_M4ZZ_D:
22303 case AArch64::SUB_VG4_M4ZZ_S:
22304 case AArch64::SUDOT_VG2_M2ZZ_BToS:
22305 case AArch64::SUDOT_VG4_M4ZZ_BToS:
22306 case AArch64::UDOT_VG2_M2ZZ_BtoS:
22307 case AArch64::UDOT_VG2_M2ZZ_HtoD:
22308 case AArch64::UDOT_VG2_M2ZZ_HtoS:
22309 case AArch64::UDOT_VG4_M4ZZ_BtoS:
22310 case AArch64::UDOT_VG4_M4ZZ_HtoD:
22311 case AArch64::UDOT_VG4_M4ZZ_HtoS:
22312 case AArch64::USDOT_VG2_M2ZZ_BToS:
22313 case AArch64::USDOT_VG4_M4ZZ_BToS: {
22314 // op: Zm
22315 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22316 op &= UINT64_C(15);
22317 op <<= 16;
22318 Value |= op;
22319 // op: Zn
22320 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22321 op &= UINT64_C(31);
22322 op <<= 5;
22323 Value |= op;
22324 // op: Rv
22325 op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI);
22326 op &= UINT64_C(3);
22327 op <<= 13;
22328 Value |= op;
22329 // op: imm3
22330 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22331 op &= UINT64_C(7);
22332 Value |= op;
22333 break;
22334 }
22335 case AArch64::BFMOPA_MPPZZ_H:
22336 case AArch64::BFMOPS_MPPZZ_H:
22337 case AArch64::FMOPA_MPPZZ_BtoH:
22338 case AArch64::FMOPA_MPPZZ_H:
22339 case AArch64::FMOPS_MPPZZ_H: {
22340 // op: Zm
22341 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22342 op &= UINT64_C(31);
22343 op <<= 16;
22344 Value |= op;
22345 // op: Pm
22346 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22347 op &= UINT64_C(7);
22348 op <<= 13;
22349 Value |= op;
22350 // op: Pn
22351 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22352 op &= UINT64_C(7);
22353 op <<= 10;
22354 Value |= op;
22355 // op: Zn
22356 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22357 op &= UINT64_C(31);
22358 op <<= 5;
22359 Value |= op;
22360 // op: ZAda
22361 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22362 op &= UINT64_C(1);
22363 Value |= op;
22364 break;
22365 }
22366 case AArch64::BFMOPA_MPPZZ:
22367 case AArch64::BFMOPS_MPPZZ:
22368 case AArch64::BMOPA_MPPZZ_S:
22369 case AArch64::BMOPS_MPPZZ_S:
22370 case AArch64::FMOPAL_MPPZZ:
22371 case AArch64::FMOPA_MPPZZ_BtoS:
22372 case AArch64::FMOPA_MPPZZ_S:
22373 case AArch64::FMOPSL_MPPZZ:
22374 case AArch64::FMOPS_MPPZZ_S:
22375 case AArch64::SMOPA_MPPZZ_HtoS:
22376 case AArch64::SMOPA_MPPZZ_S:
22377 case AArch64::SMOPS_MPPZZ_HtoS:
22378 case AArch64::SMOPS_MPPZZ_S:
22379 case AArch64::SUMOPA_MPPZZ_S:
22380 case AArch64::SUMOPS_MPPZZ_S:
22381 case AArch64::UMOPA_MPPZZ_HtoS:
22382 case AArch64::UMOPA_MPPZZ_S:
22383 case AArch64::UMOPS_MPPZZ_HtoS:
22384 case AArch64::UMOPS_MPPZZ_S:
22385 case AArch64::USMOPA_MPPZZ_S:
22386 case AArch64::USMOPS_MPPZZ_S: {
22387 // op: Zm
22388 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22389 op &= UINT64_C(31);
22390 op <<= 16;
22391 Value |= op;
22392 // op: Pm
22393 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22394 op &= UINT64_C(7);
22395 op <<= 13;
22396 Value |= op;
22397 // op: Pn
22398 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22399 op &= UINT64_C(7);
22400 op <<= 10;
22401 Value |= op;
22402 // op: Zn
22403 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22404 op &= UINT64_C(31);
22405 op <<= 5;
22406 Value |= op;
22407 // op: ZAda
22408 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22409 op &= UINT64_C(3);
22410 Value |= op;
22411 break;
22412 }
22413 case AArch64::FMOPA_MPPZZ_D:
22414 case AArch64::FMOPS_MPPZZ_D:
22415 case AArch64::SMOPA_MPPZZ_D:
22416 case AArch64::SMOPS_MPPZZ_D:
22417 case AArch64::SUMOPA_MPPZZ_D:
22418 case AArch64::SUMOPS_MPPZZ_D:
22419 case AArch64::UMOPA_MPPZZ_D:
22420 case AArch64::UMOPS_MPPZZ_D:
22421 case AArch64::USMOPA_MPPZZ_D:
22422 case AArch64::USMOPS_MPPZZ_D: {
22423 // op: Zm
22424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI);
22425 op &= UINT64_C(31);
22426 op <<= 16;
22427 Value |= op;
22428 // op: Pm
22429 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22430 op &= UINT64_C(7);
22431 op <<= 13;
22432 Value |= op;
22433 // op: Pn
22434 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22435 op &= UINT64_C(7);
22436 op <<= 10;
22437 Value |= op;
22438 // op: Zn
22439 op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI);
22440 op &= UINT64_C(31);
22441 op <<= 5;
22442 Value |= op;
22443 // op: ZAda
22444 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22445 op &= UINT64_C(7);
22446 Value |= op;
22447 break;
22448 }
22449 case AArch64::FCVTZS_2Z2Z_StoS:
22450 case AArch64::FCVTZU_2Z2Z_StoS:
22451 case AArch64::FRINTA_2Z2Z_S:
22452 case AArch64::FRINTM_2Z2Z_S:
22453 case AArch64::FRINTN_2Z2Z_S:
22454 case AArch64::FRINTP_2Z2Z_S:
22455 case AArch64::SCVTF_2Z2Z_StoS:
22456 case AArch64::UCVTF_2Z2Z_StoS: {
22457 // op: Zn
22458 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 1, Fixups, STI);
22459 op &= UINT64_C(15);
22460 op <<= 6;
22461 Value |= op;
22462 // op: Zd
22463 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
22464 op &= UINT64_C(15);
22465 op <<= 1;
22466 Value |= op;
22467 break;
22468 }
22469 case AArch64::SUNPK_VG4_4Z2Z_D:
22470 case AArch64::SUNPK_VG4_4Z2Z_H:
22471 case AArch64::SUNPK_VG4_4Z2Z_S:
22472 case AArch64::UUNPK_VG4_4Z2Z_D:
22473 case AArch64::UUNPK_VG4_4Z2Z_H:
22474 case AArch64::UUNPK_VG4_4Z2Z_S: {
22475 // op: Zn
22476 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 1, Fixups, STI);
22477 op &= UINT64_C(15);
22478 op <<= 6;
22479 Value |= op;
22480 // op: Zd
22481 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
22482 op &= UINT64_C(7);
22483 op <<= 2;
22484 Value |= op;
22485 break;
22486 }
22487 case AArch64::BFCVTN_Z2Z_StoH:
22488 case AArch64::BFCVT_Z2Z_HtoB:
22489 case AArch64::BFCVT_Z2Z_StoH:
22490 case AArch64::FCVTN_Z2Z_StoH:
22491 case AArch64::FCVT_Z2Z_HtoB:
22492 case AArch64::FCVT_Z2Z_StoH:
22493 case AArch64::SQCVTU_Z2Z_StoH:
22494 case AArch64::SQCVT_Z2Z_StoH:
22495 case AArch64::UQCVT_Z2Z_StoH: {
22496 // op: Zn
22497 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 1, Fixups, STI);
22498 op &= UINT64_C(15);
22499 op <<= 6;
22500 Value |= op;
22501 // op: Zd
22502 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22503 op &= UINT64_C(31);
22504 Value |= op;
22505 break;
22506 }
22507 case AArch64::LUTI4_4ZZT2Z: {
22508 // op: Zn
22509 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 2, Fixups, STI);
22510 op &= UINT64_C(15);
22511 op <<= 6;
22512 Value |= op;
22513 // op: Zd
22514 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
22515 op &= UINT64_C(7);
22516 op <<= 2;
22517 Value |= op;
22518 break;
22519 }
22520 case AArch64::LUTI4_S_4ZZT2Z: {
22521 // op: Zn
22522 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 2, Fixups, STI);
22523 op &= UINT64_C(15);
22524 op <<= 6;
22525 Value |= op;
22526 // op: Zd
22527 op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
22528 Value |= (op & UINT64_C(4)) << 2;
22529 Value |= (op & UINT64_C(3));
22530 break;
22531 }
22532 case AArch64::FCVTZS_4Z4Z_StoS:
22533 case AArch64::FCVTZU_4Z4Z_StoS:
22534 case AArch64::FRINTA_4Z4Z_S:
22535 case AArch64::FRINTM_4Z4Z_S:
22536 case AArch64::FRINTN_4Z4Z_S:
22537 case AArch64::FRINTP_4Z4Z_S:
22538 case AArch64::SCVTF_4Z4Z_StoS:
22539 case AArch64::UCVTF_4Z4Z_StoS:
22540 case AArch64::UZP_VG4_4Z4Z_B:
22541 case AArch64::UZP_VG4_4Z4Z_D:
22542 case AArch64::UZP_VG4_4Z4Z_H:
22543 case AArch64::UZP_VG4_4Z4Z_Q:
22544 case AArch64::UZP_VG4_4Z4Z_S:
22545 case AArch64::ZIP_VG4_4Z4Z_B:
22546 case AArch64::ZIP_VG4_4Z4Z_D:
22547 case AArch64::ZIP_VG4_4Z4Z_H:
22548 case AArch64::ZIP_VG4_4Z4Z_Q:
22549 case AArch64::ZIP_VG4_4Z4Z_S: {
22550 // op: Zn
22551 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 1, Fixups, STI);
22552 op &= UINT64_C(7);
22553 op <<= 7;
22554 Value |= op;
22555 // op: Zd
22556 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
22557 op &= UINT64_C(7);
22558 op <<= 2;
22559 Value |= op;
22560 break;
22561 }
22562 case AArch64::FCVTN_Z4Z_StoB_NAME:
22563 case AArch64::FCVT_Z4Z_StoB_NAME:
22564 case AArch64::SQCVTN_Z4Z_DtoH:
22565 case AArch64::SQCVTN_Z4Z_StoB:
22566 case AArch64::SQCVTUN_Z4Z_DtoH:
22567 case AArch64::SQCVTUN_Z4Z_StoB:
22568 case AArch64::SQCVTU_Z4Z_DtoH:
22569 case AArch64::SQCVTU_Z4Z_StoB:
22570 case AArch64::SQCVT_Z4Z_DtoH:
22571 case AArch64::SQCVT_Z4Z_StoB:
22572 case AArch64::UQCVTN_Z4Z_DtoH:
22573 case AArch64::UQCVTN_Z4Z_StoB:
22574 case AArch64::UQCVT_Z4Z_DtoH:
22575 case AArch64::UQCVT_Z4Z_StoB: {
22576 // op: Zn
22577 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 1, Fixups, STI);
22578 op &= UINT64_C(7);
22579 op <<= 7;
22580 Value |= op;
22581 // op: Zd
22582 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22583 op &= UINT64_C(31);
22584 Value |= op;
22585 break;
22586 }
22587 case AArch64::SQRSHRN_VG4_Z4ZI_B:
22588 case AArch64::SQRSHRUN_VG4_Z4ZI_B:
22589 case AArch64::SQRSHRU_VG4_Z4ZI_B:
22590 case AArch64::SQRSHR_VG4_Z4ZI_B:
22591 case AArch64::UQRSHRN_VG4_Z4ZI_B:
22592 case AArch64::UQRSHR_VG4_Z4ZI_B: {
22593 // op: Zn
22594 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 1, Fixups, STI);
22595 op &= UINT64_C(7);
22596 op <<= 7;
22597 Value |= op;
22598 // op: Zd
22599 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22600 op &= UINT64_C(31);
22601 Value |= op;
22602 // op: imm
22603 op = getVecShiftR32OpValue(MI, OpIdx: 2, Fixups, STI);
22604 op &= UINT64_C(31);
22605 op <<= 16;
22606 Value |= op;
22607 break;
22608 }
22609 case AArch64::SQRSHRN_VG4_Z4ZI_H:
22610 case AArch64::SQRSHRUN_VG4_Z4ZI_H:
22611 case AArch64::SQRSHRU_VG4_Z4ZI_H:
22612 case AArch64::SQRSHR_VG4_Z4ZI_H:
22613 case AArch64::UQRSHRN_VG4_Z4ZI_H:
22614 case AArch64::UQRSHR_VG4_Z4ZI_H: {
22615 // op: Zn
22616 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 1, Fixups, STI);
22617 op &= UINT64_C(7);
22618 op <<= 7;
22619 Value |= op;
22620 // op: Zd
22621 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22622 op &= UINT64_C(31);
22623 Value |= op;
22624 // op: imm
22625 op = getVecShiftR64OpValue(MI, OpIdx: 2, Fixups, STI);
22626 Value |= (op & UINT64_C(32)) << 17;
22627 Value |= (op & UINT64_C(31)) << 16;
22628 break;
22629 }
22630 case AArch64::BF1CVTL_2ZZ_BtoH_NAME:
22631 case AArch64::BF1CVT_2ZZ_BtoH_NAME:
22632 case AArch64::BF2CVTL_2ZZ_BtoH_NAME:
22633 case AArch64::BF2CVT_2ZZ_BtoH_NAME:
22634 case AArch64::F1CVTL_2ZZ_BtoH_NAME:
22635 case AArch64::F1CVT_2ZZ_BtoH_NAME:
22636 case AArch64::F2CVTL_2ZZ_BtoH_NAME:
22637 case AArch64::F2CVT_2ZZ_BtoH_NAME:
22638 case AArch64::FCVTL_2ZZ_H_S:
22639 case AArch64::FCVT_2ZZ_H_S:
22640 case AArch64::SUNPK_VG2_2ZZ_D:
22641 case AArch64::SUNPK_VG2_2ZZ_H:
22642 case AArch64::SUNPK_VG2_2ZZ_S:
22643 case AArch64::UUNPK_VG2_2ZZ_D:
22644 case AArch64::UUNPK_VG2_2ZZ_H:
22645 case AArch64::UUNPK_VG2_2ZZ_S: {
22646 // op: Zn
22647 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
22648 op &= UINT64_C(31);
22649 op <<= 5;
22650 Value |= op;
22651 // op: Zd
22652 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
22653 op &= UINT64_C(15);
22654 op <<= 1;
22655 Value |= op;
22656 break;
22657 }
22658 case AArch64::FADDV_VPZ_D:
22659 case AArch64::FADDV_VPZ_H:
22660 case AArch64::FADDV_VPZ_S:
22661 case AArch64::FMAXNMV_VPZ_D:
22662 case AArch64::FMAXNMV_VPZ_H:
22663 case AArch64::FMAXNMV_VPZ_S:
22664 case AArch64::FMAXV_VPZ_D:
22665 case AArch64::FMAXV_VPZ_H:
22666 case AArch64::FMAXV_VPZ_S:
22667 case AArch64::FMINNMV_VPZ_D:
22668 case AArch64::FMINNMV_VPZ_H:
22669 case AArch64::FMINNMV_VPZ_S:
22670 case AArch64::FMINV_VPZ_D:
22671 case AArch64::FMINV_VPZ_H:
22672 case AArch64::FMINV_VPZ_S: {
22673 // op: Zn
22674 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22675 op &= UINT64_C(31);
22676 op <<= 5;
22677 Value |= op;
22678 // op: Vd
22679 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22680 op &= UINT64_C(31);
22681 Value |= op;
22682 // op: Pg
22683 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
22684 op &= UINT64_C(7);
22685 op <<= 10;
22686 Value |= op;
22687 break;
22688 }
22689 case AArch64::LUTI4_2ZTZI_B:
22690 case AArch64::LUTI4_2ZTZI_H:
22691 case AArch64::LUTI4_2ZTZI_S: {
22692 // op: Zn
22693 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22694 op &= UINT64_C(31);
22695 op <<= 5;
22696 Value |= op;
22697 // op: Zd
22698 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
22699 op &= UINT64_C(15);
22700 op <<= 1;
22701 Value |= op;
22702 // op: i
22703 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22704 op &= UINT64_C(3);
22705 op <<= 15;
22706 Value |= op;
22707 break;
22708 }
22709 case AArch64::LUTI2_2ZTZI_B:
22710 case AArch64::LUTI2_2ZTZI_H:
22711 case AArch64::LUTI2_2ZTZI_S: {
22712 // op: Zn
22713 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22714 op &= UINT64_C(31);
22715 op <<= 5;
22716 Value |= op;
22717 // op: Zd
22718 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
22719 op &= UINT64_C(15);
22720 op <<= 1;
22721 Value |= op;
22722 // op: i
22723 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22724 op &= UINT64_C(7);
22725 op <<= 15;
22726 Value |= op;
22727 break;
22728 }
22729 case AArch64::LUTI4_4ZTZI_H:
22730 case AArch64::LUTI4_4ZTZI_S: {
22731 // op: Zn
22732 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22733 op &= UINT64_C(31);
22734 op <<= 5;
22735 Value |= op;
22736 // op: Zd
22737 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
22738 op &= UINT64_C(7);
22739 op <<= 2;
22740 Value |= op;
22741 // op: i
22742 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22743 op &= UINT64_C(1);
22744 op <<= 16;
22745 Value |= op;
22746 break;
22747 }
22748 case AArch64::LUTI2_4ZTZI_B:
22749 case AArch64::LUTI2_4ZTZI_H:
22750 case AArch64::LUTI2_4ZTZI_S: {
22751 // op: Zn
22752 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22753 op &= UINT64_C(31);
22754 op <<= 5;
22755 Value |= op;
22756 // op: Zd
22757 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
22758 op &= UINT64_C(7);
22759 op <<= 2;
22760 Value |= op;
22761 // op: i
22762 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22763 op &= UINT64_C(3);
22764 op <<= 16;
22765 Value |= op;
22766 break;
22767 }
22768 case AArch64::LUTI4_S_2ZTZI_B:
22769 case AArch64::LUTI4_S_2ZTZI_H: {
22770 // op: Zn
22771 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22772 op &= UINT64_C(31);
22773 op <<= 5;
22774 Value |= op;
22775 // op: Zd
22776 op = EncodeZPR2StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
22777 Value |= (op & UINT64_C(8)) << 1;
22778 Value |= (op & UINT64_C(7));
22779 // op: i
22780 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22781 op &= UINT64_C(3);
22782 op <<= 15;
22783 Value |= op;
22784 break;
22785 }
22786 case AArch64::LUTI2_S_2ZTZI_B:
22787 case AArch64::LUTI2_S_2ZTZI_H: {
22788 // op: Zn
22789 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22790 op &= UINT64_C(31);
22791 op <<= 5;
22792 Value |= op;
22793 // op: Zd
22794 op = EncodeZPR2StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
22795 Value |= (op & UINT64_C(8)) << 1;
22796 Value |= (op & UINT64_C(7));
22797 // op: i
22798 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22799 op &= UINT64_C(7);
22800 op <<= 15;
22801 Value |= op;
22802 break;
22803 }
22804 case AArch64::LUTI4_S_4ZTZI_H: {
22805 // op: Zn
22806 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22807 op &= UINT64_C(31);
22808 op <<= 5;
22809 Value |= op;
22810 // op: Zd
22811 op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
22812 Value |= (op & UINT64_C(4)) << 2;
22813 Value |= (op & UINT64_C(3));
22814 // op: i
22815 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22816 op &= UINT64_C(1);
22817 op <<= 16;
22818 Value |= op;
22819 break;
22820 }
22821 case AArch64::LUTI2_S_4ZTZI_B:
22822 case AArch64::LUTI2_S_4ZTZI_H: {
22823 // op: Zn
22824 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22825 op &= UINT64_C(31);
22826 op <<= 5;
22827 Value |= op;
22828 // op: Zd
22829 op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
22830 Value |= (op & UINT64_C(4)) << 2;
22831 Value |= (op & UINT64_C(3));
22832 // op: i
22833 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22834 op &= UINT64_C(3);
22835 op <<= 16;
22836 Value |= op;
22837 break;
22838 }
22839 case AArch64::LUTI2_ZTZI_B:
22840 case AArch64::LUTI2_ZTZI_H:
22841 case AArch64::LUTI2_ZTZI_S: {
22842 // op: Zn
22843 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22844 op &= UINT64_C(31);
22845 op <<= 5;
22846 Value |= op;
22847 // op: Zd
22848 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22849 op &= UINT64_C(31);
22850 Value |= op;
22851 // op: i
22852 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22853 op &= UINT64_C(15);
22854 op <<= 14;
22855 Value |= op;
22856 break;
22857 }
22858 case AArch64::LUTI4_ZTZI_B:
22859 case AArch64::LUTI4_ZTZI_H:
22860 case AArch64::LUTI4_ZTZI_S: {
22861 // op: Zn
22862 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22863 op &= UINT64_C(31);
22864 op <<= 5;
22865 Value |= op;
22866 // op: Zd
22867 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
22868 op &= UINT64_C(31);
22869 Value |= op;
22870 // op: i
22871 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22872 op &= UINT64_C(7);
22873 op <<= 14;
22874 Value |= op;
22875 break;
22876 }
22877 case AArch64::LD1B_2Z:
22878 case AArch64::LD1D_2Z:
22879 case AArch64::LD1H_2Z:
22880 case AArch64::LD1W_2Z:
22881 case AArch64::LDNT1B_2Z:
22882 case AArch64::LDNT1D_2Z:
22883 case AArch64::LDNT1H_2Z:
22884 case AArch64::LDNT1W_2Z:
22885 case AArch64::ST1B_2Z:
22886 case AArch64::ST1D_2Z:
22887 case AArch64::ST1H_2Z:
22888 case AArch64::ST1W_2Z:
22889 case AArch64::STNT1B_2Z:
22890 case AArch64::STNT1D_2Z:
22891 case AArch64::STNT1H_2Z:
22892 case AArch64::STNT1W_2Z: {
22893 // op: Zt
22894 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
22895 op &= UINT64_C(15);
22896 op <<= 1;
22897 Value |= op;
22898 // op: Rm
22899 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22900 op &= UINT64_C(31);
22901 op <<= 16;
22902 Value |= op;
22903 // op: Rn
22904 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22905 op &= UINT64_C(31);
22906 op <<= 5;
22907 Value |= op;
22908 // op: PNg
22909 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
22910 op &= UINT64_C(7);
22911 op <<= 10;
22912 Value |= op;
22913 break;
22914 }
22915 case AArch64::LD1B_2Z_IMM:
22916 case AArch64::LD1D_2Z_IMM:
22917 case AArch64::LD1H_2Z_IMM:
22918 case AArch64::LD1W_2Z_IMM:
22919 case AArch64::LDNT1B_2Z_IMM:
22920 case AArch64::LDNT1D_2Z_IMM:
22921 case AArch64::LDNT1H_2Z_IMM:
22922 case AArch64::LDNT1W_2Z_IMM:
22923 case AArch64::ST1B_2Z_IMM:
22924 case AArch64::ST1D_2Z_IMM:
22925 case AArch64::ST1H_2Z_IMM:
22926 case AArch64::ST1W_2Z_IMM:
22927 case AArch64::STNT1B_2Z_IMM:
22928 case AArch64::STNT1D_2Z_IMM:
22929 case AArch64::STNT1H_2Z_IMM:
22930 case AArch64::STNT1W_2Z_IMM: {
22931 // op: Zt
22932 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 0, Fixups, STI);
22933 op &= UINT64_C(15);
22934 op <<= 1;
22935 Value |= op;
22936 // op: Rn
22937 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22938 op &= UINT64_C(31);
22939 op <<= 5;
22940 Value |= op;
22941 // op: PNg
22942 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
22943 op &= UINT64_C(7);
22944 op <<= 10;
22945 Value |= op;
22946 // op: imm4
22947 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22948 op &= UINT64_C(15);
22949 op <<= 16;
22950 Value |= op;
22951 break;
22952 }
22953 case AArch64::LD1B_4Z:
22954 case AArch64::LD1D_4Z:
22955 case AArch64::LD1H_4Z:
22956 case AArch64::LD1W_4Z:
22957 case AArch64::LDNT1B_4Z:
22958 case AArch64::LDNT1D_4Z:
22959 case AArch64::LDNT1H_4Z:
22960 case AArch64::LDNT1W_4Z:
22961 case AArch64::ST1B_4Z:
22962 case AArch64::ST1D_4Z:
22963 case AArch64::ST1H_4Z:
22964 case AArch64::ST1W_4Z:
22965 case AArch64::STNT1B_4Z:
22966 case AArch64::STNT1D_4Z:
22967 case AArch64::STNT1H_4Z:
22968 case AArch64::STNT1W_4Z: {
22969 // op: Zt
22970 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
22971 op &= UINT64_C(7);
22972 op <<= 2;
22973 Value |= op;
22974 // op: Rm
22975 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
22976 op &= UINT64_C(31);
22977 op <<= 16;
22978 Value |= op;
22979 // op: Rn
22980 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
22981 op &= UINT64_C(31);
22982 op <<= 5;
22983 Value |= op;
22984 // op: PNg
22985 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
22986 op &= UINT64_C(7);
22987 op <<= 10;
22988 Value |= op;
22989 break;
22990 }
22991 case AArch64::LD1B_4Z_IMM:
22992 case AArch64::LD1D_4Z_IMM:
22993 case AArch64::LD1H_4Z_IMM:
22994 case AArch64::LD1W_4Z_IMM:
22995 case AArch64::LDNT1B_4Z_IMM:
22996 case AArch64::LDNT1D_4Z_IMM:
22997 case AArch64::LDNT1H_4Z_IMM:
22998 case AArch64::LDNT1W_4Z_IMM:
22999 case AArch64::ST1B_4Z_IMM:
23000 case AArch64::ST1D_4Z_IMM:
23001 case AArch64::ST1H_4Z_IMM:
23002 case AArch64::ST1W_4Z_IMM:
23003 case AArch64::STNT1B_4Z_IMM:
23004 case AArch64::STNT1D_4Z_IMM:
23005 case AArch64::STNT1H_4Z_IMM:
23006 case AArch64::STNT1W_4Z_IMM: {
23007 // op: Zt
23008 op = EncodeRegAsMultipleOf<4>(MI, OpIdx: 0, Fixups, STI);
23009 op &= UINT64_C(7);
23010 op <<= 2;
23011 Value |= op;
23012 // op: Rn
23013 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23014 op &= UINT64_C(31);
23015 op <<= 5;
23016 Value |= op;
23017 // op: PNg
23018 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
23019 op &= UINT64_C(7);
23020 op <<= 10;
23021 Value |= op;
23022 // op: imm4
23023 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23024 op &= UINT64_C(15);
23025 op <<= 16;
23026 Value |= op;
23027 break;
23028 }
23029 case AArch64::LD1B:
23030 case AArch64::LD1B_D:
23031 case AArch64::LD1B_H:
23032 case AArch64::LD1B_S:
23033 case AArch64::LD1D:
23034 case AArch64::LD1H:
23035 case AArch64::LD1H_D:
23036 case AArch64::LD1H_S:
23037 case AArch64::LD1SB_D:
23038 case AArch64::LD1SB_H:
23039 case AArch64::LD1SB_S:
23040 case AArch64::LD1SH_D:
23041 case AArch64::LD1SH_S:
23042 case AArch64::LD1SW_D:
23043 case AArch64::LD1W:
23044 case AArch64::LD1W_D:
23045 case AArch64::LDFF1B:
23046 case AArch64::LDFF1B_D:
23047 case AArch64::LDFF1B_H:
23048 case AArch64::LDFF1B_S:
23049 case AArch64::LDFF1D:
23050 case AArch64::LDFF1H:
23051 case AArch64::LDFF1H_D:
23052 case AArch64::LDFF1H_S:
23053 case AArch64::LDFF1SB_D:
23054 case AArch64::LDFF1SB_H:
23055 case AArch64::LDFF1SB_S:
23056 case AArch64::LDFF1SH_D:
23057 case AArch64::LDFF1SH_S:
23058 case AArch64::LDFF1SW_D:
23059 case AArch64::LDFF1W:
23060 case AArch64::LDFF1W_D: {
23061 // op: Zt
23062 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23063 op &= UINT64_C(31);
23064 Value |= op;
23065 // op: Pg
23066 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23067 op &= UINT64_C(7);
23068 op <<= 10;
23069 Value |= op;
23070 // op: Rm
23071 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23072 op &= UINT64_C(31);
23073 op <<= 16;
23074 Value |= op;
23075 // op: Rn
23076 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23077 op &= UINT64_C(31);
23078 op <<= 5;
23079 Value |= op;
23080 break;
23081 }
23082 case AArch64::LD1RO_B:
23083 case AArch64::LD1RO_D:
23084 case AArch64::LD1RO_H:
23085 case AArch64::LD1RO_W:
23086 case AArch64::LD1RQ_B:
23087 case AArch64::LD1RQ_D:
23088 case AArch64::LD1RQ_H:
23089 case AArch64::LD1RQ_W: {
23090 // op: Zt
23091 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23092 op &= UINT64_C(31);
23093 Value |= op;
23094 // op: Pg
23095 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23096 op &= UINT64_C(7);
23097 op <<= 10;
23098 Value |= op;
23099 // op: Rn
23100 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23101 op &= UINT64_C(31);
23102 op <<= 5;
23103 Value |= op;
23104 // op: Rm
23105 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23106 op &= UINT64_C(31);
23107 op <<= 16;
23108 Value |= op;
23109 break;
23110 }
23111 case AArch64::LD2B_IMM:
23112 case AArch64::LD2D_IMM:
23113 case AArch64::LD2H_IMM:
23114 case AArch64::LD2Q_IMM:
23115 case AArch64::LD2W_IMM:
23116 case AArch64::LD3B_IMM:
23117 case AArch64::LD3D_IMM:
23118 case AArch64::LD3H_IMM:
23119 case AArch64::LD3Q_IMM:
23120 case AArch64::LD3W_IMM:
23121 case AArch64::LD4B_IMM:
23122 case AArch64::LD4D_IMM:
23123 case AArch64::LD4H_IMM:
23124 case AArch64::LD4Q_IMM:
23125 case AArch64::LD4W_IMM:
23126 case AArch64::LDNT1B_ZRI:
23127 case AArch64::LDNT1D_ZRI:
23128 case AArch64::LDNT1H_ZRI:
23129 case AArch64::LDNT1W_ZRI: {
23130 // op: Zt
23131 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23132 op &= UINT64_C(31);
23133 Value |= op;
23134 // op: Pg
23135 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23136 op &= UINT64_C(7);
23137 op <<= 10;
23138 Value |= op;
23139 // op: Rn
23140 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23141 op &= UINT64_C(31);
23142 op <<= 5;
23143 Value |= op;
23144 // op: imm4
23145 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23146 op &= UINT64_C(15);
23147 op <<= 16;
23148 Value |= op;
23149 break;
23150 }
23151 case AArch64::LD1D_Q:
23152 case AArch64::LD1W_Q:
23153 case AArch64::ST2Q:
23154 case AArch64::ST3Q:
23155 case AArch64::ST4Q: {
23156 // op: Zt
23157 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23158 op &= UINT64_C(31);
23159 Value |= op;
23160 // op: Rn
23161 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23162 op &= UINT64_C(31);
23163 op <<= 5;
23164 Value |= op;
23165 // op: Pg
23166 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23167 op &= UINT64_C(7);
23168 op <<= 10;
23169 Value |= op;
23170 // op: Rm
23171 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23172 op &= UINT64_C(31);
23173 op <<= 16;
23174 Value |= op;
23175 break;
23176 }
23177 case AArch64::LD1D_Q_IMM:
23178 case AArch64::LD1RO_B_IMM:
23179 case AArch64::LD1RO_D_IMM:
23180 case AArch64::LD1RO_H_IMM:
23181 case AArch64::LD1RO_W_IMM:
23182 case AArch64::LD1RQ_B_IMM:
23183 case AArch64::LD1RQ_D_IMM:
23184 case AArch64::LD1RQ_H_IMM:
23185 case AArch64::LD1RQ_W_IMM:
23186 case AArch64::LD1W_Q_IMM:
23187 case AArch64::ST2Q_IMM:
23188 case AArch64::ST3Q_IMM:
23189 case AArch64::ST4Q_IMM: {
23190 // op: Zt
23191 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23192 op &= UINT64_C(31);
23193 Value |= op;
23194 // op: Rn
23195 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23196 op &= UINT64_C(31);
23197 op <<= 5;
23198 Value |= op;
23199 // op: Pg
23200 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23201 op &= UINT64_C(7);
23202 op <<= 10;
23203 Value |= op;
23204 // op: imm4
23205 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23206 op &= UINT64_C(15);
23207 op <<= 16;
23208 Value |= op;
23209 break;
23210 }
23211 case AArch64::GLD1Q:
23212 case AArch64::SST1Q: {
23213 // op: Zt
23214 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23215 op &= UINT64_C(31);
23216 Value |= op;
23217 // op: Zn
23218 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23219 op &= UINT64_C(31);
23220 op <<= 5;
23221 Value |= op;
23222 // op: Pg
23223 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23224 op &= UINT64_C(7);
23225 op <<= 10;
23226 Value |= op;
23227 // op: Rm
23228 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23229 op &= UINT64_C(31);
23230 op <<= 16;
23231 Value |= op;
23232 break;
23233 }
23234 case AArch64::MOVT: {
23235 // op: Zt
23236 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23237 op &= UINT64_C(31);
23238 Value |= op;
23239 // op: off2
23240 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23241 op &= UINT64_C(3);
23242 op <<= 12;
23243 Value |= op;
23244 break;
23245 }
23246 case AArch64::B:
23247 case AArch64::BL: {
23248 // op: addr
23249 op = getBranchTargetOpValue(MI, OpIdx: 0, Fixups, STI);
23250 op &= UINT64_C(67108863);
23251 Value |= op;
23252 break;
23253 }
23254 case AArch64::BCcc:
23255 case AArch64::Bcc: {
23256 // op: cond
23257 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23258 op &= UINT64_C(15);
23259 Value |= op;
23260 // op: target
23261 op = getCondBranchTargetOpValue(MI, OpIdx: 1, Fixups, STI);
23262 op &= UINT64_C(524287);
23263 op <<= 5;
23264 Value |= op;
23265 break;
23266 }
23267 case AArch64::DUPi64: {
23268 // op: dst
23269 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23270 op &= UINT64_C(31);
23271 Value |= op;
23272 // op: src
23273 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23274 op &= UINT64_C(31);
23275 op <<= 5;
23276 Value |= op;
23277 // op: idx
23278 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23279 op &= UINT64_C(1);
23280 op <<= 20;
23281 Value |= op;
23282 break;
23283 }
23284 case AArch64::DUPi8: {
23285 // op: dst
23286 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23287 op &= UINT64_C(31);
23288 Value |= op;
23289 // op: src
23290 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23291 op &= UINT64_C(31);
23292 op <<= 5;
23293 Value |= op;
23294 // op: idx
23295 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23296 op &= UINT64_C(15);
23297 op <<= 17;
23298 Value |= op;
23299 break;
23300 }
23301 case AArch64::DUPi32: {
23302 // op: dst
23303 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23304 op &= UINT64_C(31);
23305 Value |= op;
23306 // op: src
23307 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23308 op &= UINT64_C(31);
23309 op <<= 5;
23310 Value |= op;
23311 // op: idx
23312 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23313 op &= UINT64_C(3);
23314 op <<= 19;
23315 Value |= op;
23316 break;
23317 }
23318 case AArch64::DUPi16: {
23319 // op: dst
23320 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23321 op &= UINT64_C(31);
23322 Value |= op;
23323 // op: src
23324 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23325 op &= UINT64_C(31);
23326 op <<= 5;
23327 Value |= op;
23328 // op: idx
23329 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23330 op &= UINT64_C(7);
23331 op <<= 18;
23332 Value |= op;
23333 break;
23334 }
23335 case AArch64::ZERO_M: {
23336 // op: imm
23337 op = EncodeMatrixTileListRegisterClass(MI, OpIdx: 0, Fixups, STI);
23338 op &= UINT64_C(255);
23339 Value |= op;
23340 break;
23341 }
23342 case AArch64::HINT: {
23343 // op: imm
23344 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23345 op &= UINT64_C(127);
23346 op <<= 5;
23347 Value |= op;
23348 break;
23349 }
23350 case AArch64::UDF: {
23351 // op: imm
23352 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23353 op &= UINT64_C(65535);
23354 Value |= op;
23355 break;
23356 }
23357 case AArch64::BRK:
23358 case AArch64::DCPS1:
23359 case AArch64::DCPS2:
23360 case AArch64::DCPS3:
23361 case AArch64::HLT:
23362 case AArch64::HVC:
23363 case AArch64::SMC:
23364 case AArch64::SVC:
23365 case AArch64::TCANCEL: {
23366 // op: imm
23367 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23368 op &= UINT64_C(65535);
23369 op <<= 5;
23370 Value |= op;
23371 break;
23372 }
23373 case AArch64::MOVT_TIX: {
23374 // op: imm3
23375 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23376 op &= UINT64_C(7);
23377 op <<= 12;
23378 Value |= op;
23379 // op: Rt
23380 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23381 op &= UINT64_C(31);
23382 Value |= op;
23383 break;
23384 }
23385 case AArch64::MOVT_XTI: {
23386 // op: imm3
23387 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23388 op &= UINT64_C(7);
23389 op <<= 12;
23390 Value |= op;
23391 // op: Rt
23392 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23393 op &= UINT64_C(31);
23394 Value |= op;
23395 break;
23396 }
23397 case AArch64::LD1B_2Z_STRIDED_IMM:
23398 case AArch64::LD1D_2Z_STRIDED_IMM:
23399 case AArch64::LD1H_2Z_STRIDED_IMM:
23400 case AArch64::LD1W_2Z_STRIDED_IMM:
23401 case AArch64::LDNT1B_2Z_STRIDED_IMM:
23402 case AArch64::LDNT1D_2Z_STRIDED_IMM:
23403 case AArch64::LDNT1H_2Z_STRIDED_IMM:
23404 case AArch64::LDNT1W_2Z_STRIDED_IMM:
23405 case AArch64::ST1B_2Z_STRIDED_IMM:
23406 case AArch64::ST1D_2Z_STRIDED_IMM:
23407 case AArch64::ST1H_2Z_STRIDED_IMM:
23408 case AArch64::ST1W_2Z_STRIDED_IMM:
23409 case AArch64::STNT1B_2Z_STRIDED_IMM:
23410 case AArch64::STNT1D_2Z_STRIDED_IMM:
23411 case AArch64::STNT1H_2Z_STRIDED_IMM:
23412 case AArch64::STNT1W_2Z_STRIDED_IMM: {
23413 // op: imm4
23414 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23415 op &= UINT64_C(15);
23416 op <<= 16;
23417 Value |= op;
23418 // op: PNg
23419 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
23420 op &= UINT64_C(7);
23421 op <<= 10;
23422 Value |= op;
23423 // op: Rn
23424 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23425 op &= UINT64_C(31);
23426 op <<= 5;
23427 Value |= op;
23428 // op: Zt
23429 op = EncodeZPR2StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
23430 Value |= (op & UINT64_C(8)) << 1;
23431 Value |= (op & UINT64_C(7));
23432 break;
23433 }
23434 case AArch64::LD1B_4Z_STRIDED_IMM:
23435 case AArch64::LD1D_4Z_STRIDED_IMM:
23436 case AArch64::LD1H_4Z_STRIDED_IMM:
23437 case AArch64::LD1W_4Z_STRIDED_IMM:
23438 case AArch64::LDNT1B_4Z_STRIDED_IMM:
23439 case AArch64::LDNT1D_4Z_STRIDED_IMM:
23440 case AArch64::LDNT1H_4Z_STRIDED_IMM:
23441 case AArch64::LDNT1W_4Z_STRIDED_IMM:
23442 case AArch64::ST1B_4Z_STRIDED_IMM:
23443 case AArch64::ST1D_4Z_STRIDED_IMM:
23444 case AArch64::ST1H_4Z_STRIDED_IMM:
23445 case AArch64::ST1W_4Z_STRIDED_IMM:
23446 case AArch64::STNT1B_4Z_STRIDED_IMM:
23447 case AArch64::STNT1D_4Z_STRIDED_IMM:
23448 case AArch64::STNT1H_4Z_STRIDED_IMM:
23449 case AArch64::STNT1W_4Z_STRIDED_IMM: {
23450 // op: imm4
23451 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23452 op &= UINT64_C(15);
23453 op <<= 16;
23454 Value |= op;
23455 // op: PNg
23456 op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI);
23457 op &= UINT64_C(7);
23458 op <<= 10;
23459 Value |= op;
23460 // op: Rn
23461 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23462 op &= UINT64_C(31);
23463 op <<= 5;
23464 Value |= op;
23465 // op: Zt
23466 op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI);
23467 Value |= (op & UINT64_C(4)) << 2;
23468 Value |= (op & UINT64_C(3));
23469 break;
23470 }
23471 case AArch64::SQRSHRU_VG2_Z2ZI_H:
23472 case AArch64::SQRSHR_VG2_Z2ZI_H:
23473 case AArch64::UQRSHR_VG2_Z2ZI_H: {
23474 // op: imm4
23475 op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI);
23476 op &= UINT64_C(15);
23477 op <<= 16;
23478 Value |= op;
23479 // op: Zn
23480 op = EncodeRegAsMultipleOf<2>(MI, OpIdx: 1, Fixups, STI);
23481 op &= UINT64_C(15);
23482 op <<= 6;
23483 Value |= op;
23484 // op: Zd
23485 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23486 op &= UINT64_C(31);
23487 Value |= op;
23488 break;
23489 }
23490 case AArch64::AUTIASPPCi:
23491 case AArch64::AUTIBSPPCi:
23492 case AArch64::RETAASPPCi:
23493 case AArch64::RETABSPPCi: {
23494 // op: label
23495 op = getPAuthPCRelOpValue(MI, OpIdx: 0, Fixups, STI);
23496 op &= UINT64_C(65535);
23497 op <<= 5;
23498 Value |= op;
23499 break;
23500 }
23501 case AArch64::LDRAAindexed:
23502 case AArch64::LDRABindexed: {
23503 // op: offset
23504 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23505 Value |= (op & UINT64_C(512)) << 13;
23506 Value |= (op & UINT64_C(511)) << 12;
23507 // op: Rn
23508 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23509 op &= UINT64_C(31);
23510 op <<= 5;
23511 Value |= op;
23512 // op: Rt
23513 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23514 op &= UINT64_C(31);
23515 Value |= op;
23516 break;
23517 }
23518 case AArch64::LDRAAwriteback:
23519 case AArch64::LDRABwriteback: {
23520 // op: offset
23521 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23522 Value |= (op & UINT64_C(512)) << 13;
23523 Value |= (op & UINT64_C(511)) << 12;
23524 // op: Rn
23525 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23526 op &= UINT64_C(31);
23527 op <<= 5;
23528 Value |= op;
23529 // op: Rt
23530 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23531 op &= UINT64_C(31);
23532 Value |= op;
23533 break;
23534 }
23535 case AArch64::SYSPxt_XZR: {
23536 // op: op1
23537 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23538 op &= UINT64_C(7);
23539 op <<= 16;
23540 Value |= op;
23541 // op: Cn
23542 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23543 op &= UINT64_C(15);
23544 op <<= 12;
23545 Value |= op;
23546 // op: Cm
23547 op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI);
23548 op &= UINT64_C(15);
23549 op <<= 8;
23550 Value |= op;
23551 // op: op2
23552 op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI);
23553 op &= UINT64_C(7);
23554 op <<= 5;
23555 Value |= op;
23556 break;
23557 }
23558 case AArch64::MSRpstateImm1: {
23559 // op: pstatefield
23560 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23561 Value |= (op & UINT64_C(56)) << 13;
23562 Value |= (op & UINT64_C(448)) << 3;
23563 Value |= (op & UINT64_C(7)) << 5;
23564 // op: imm
23565 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23566 op &= UINT64_C(1);
23567 op <<= 8;
23568 Value |= op;
23569 break;
23570 }
23571 case AArch64::MSRpstateImm4: {
23572 // op: pstatefield
23573 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23574 Value |= (op & UINT64_C(56)) << 13;
23575 Value |= (op & UINT64_C(7)) << 5;
23576 // op: imm
23577 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23578 op &= UINT64_C(15);
23579 op <<= 8;
23580 Value |= op;
23581 break;
23582 }
23583 case AArch64::MSRpstatesvcrImm1: {
23584 // op: pstatefield
23585 op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI);
23586 op &= UINT64_C(7);
23587 op <<= 9;
23588 Value |= op;
23589 // op: imm
23590 op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI);
23591 op &= UINT64_C(1);
23592 op <<= 8;
23593 Value |= op;
23594 break;
23595 }
23596 default:
23597 std::string msg;
23598 raw_string_ostream Msg(msg);
23599 Msg << "Not supported instr: " << MI;
23600 report_fatal_error(reason: Msg.str().c_str());
23601 }
23602 return Value;
23603}
23604
23605#ifdef GET_OPERAND_BIT_OFFSET
23606#undef GET_OPERAND_BIT_OFFSET
23607
23608uint32_t AArch64MCCodeEmitter::getOperandBitOffset(const MCInst &MI,
23609 unsigned OpNum,
23610 const MCSubtargetInfo &STI) const {
23611 switch (MI.getOpcode()) {
23612 case AArch64::AUTIA1716:
23613 case AArch64::AUTIA171615:
23614 case AArch64::AUTIASP:
23615 case AArch64::AUTIAZ:
23616 case AArch64::AUTIB1716:
23617 case AArch64::AUTIB171615:
23618 case AArch64::AUTIBSP:
23619 case AArch64::AUTIBZ:
23620 case AArch64::AXFLAG:
23621 case AArch64::BRB_IALL:
23622 case AArch64::BRB_INJ:
23623 case AArch64::CFINV:
23624 case AArch64::CHKFEAT:
23625 case AArch64::DRPS:
23626 case AArch64::ERET:
23627 case AArch64::ERETAA:
23628 case AArch64::ERETAB:
23629 case AArch64::GCSPOPCX:
23630 case AArch64::GCSPOPX:
23631 case AArch64::GCSPUSHX:
23632 case AArch64::PACIA1716:
23633 case AArch64::PACIA171615:
23634 case AArch64::PACIASP:
23635 case AArch64::PACIASPPC:
23636 case AArch64::PACIAZ:
23637 case AArch64::PACIB1716:
23638 case AArch64::PACIB171615:
23639 case AArch64::PACIBSP:
23640 case AArch64::PACIBSPPC:
23641 case AArch64::PACIBZ:
23642 case AArch64::PACM:
23643 case AArch64::PACNBIASPPC:
23644 case AArch64::PACNBIBSPPC:
23645 case AArch64::RETAA:
23646 case AArch64::RETAB:
23647 case AArch64::SB:
23648 case AArch64::SETFFR:
23649 case AArch64::TCOMMIT:
23650 case AArch64::TSB:
23651 case AArch64::XAFLAG:
23652 case AArch64::XPACLRI:
23653 case AArch64::ZERO_T: {
23654 break;
23655 }
23656 case AArch64::DSBnXS: {
23657 switch (OpNum) {
23658 case 0:
23659 // op: CRm
23660 return 10;
23661 }
23662 break;
23663 }
23664 case AArch64::CLREX:
23665 case AArch64::DMB:
23666 case AArch64::DSB:
23667 case AArch64::ISB: {
23668 switch (OpNum) {
23669 case 0:
23670 // op: CRm
23671 return 8;
23672 }
23673 break;
23674 }
23675 case AArch64::WHILEGE_CXX_B:
23676 case AArch64::WHILEGE_CXX_D:
23677 case AArch64::WHILEGE_CXX_H:
23678 case AArch64::WHILEGE_CXX_S:
23679 case AArch64::WHILEGT_CXX_B:
23680 case AArch64::WHILEGT_CXX_D:
23681 case AArch64::WHILEGT_CXX_H:
23682 case AArch64::WHILEGT_CXX_S:
23683 case AArch64::WHILEHI_CXX_B:
23684 case AArch64::WHILEHI_CXX_D:
23685 case AArch64::WHILEHI_CXX_H:
23686 case AArch64::WHILEHI_CXX_S:
23687 case AArch64::WHILEHS_CXX_B:
23688 case AArch64::WHILEHS_CXX_D:
23689 case AArch64::WHILEHS_CXX_H:
23690 case AArch64::WHILEHS_CXX_S:
23691 case AArch64::WHILELE_CXX_B:
23692 case AArch64::WHILELE_CXX_D:
23693 case AArch64::WHILELE_CXX_H:
23694 case AArch64::WHILELE_CXX_S:
23695 case AArch64::WHILELO_CXX_B:
23696 case AArch64::WHILELO_CXX_D:
23697 case AArch64::WHILELO_CXX_H:
23698 case AArch64::WHILELO_CXX_S:
23699 case AArch64::WHILELS_CXX_B:
23700 case AArch64::WHILELS_CXX_D:
23701 case AArch64::WHILELS_CXX_H:
23702 case AArch64::WHILELS_CXX_S:
23703 case AArch64::WHILELT_CXX_B:
23704 case AArch64::WHILELT_CXX_D:
23705 case AArch64::WHILELT_CXX_H:
23706 case AArch64::WHILELT_CXX_S: {
23707 switch (OpNum) {
23708 case 0:
23709 // op: PNd
23710 return 0;
23711 case 1:
23712 // op: Rn
23713 return 5;
23714 case 3:
23715 // op: vl
23716 return 13;
23717 case 2:
23718 // op: Rm
23719 return 16;
23720 }
23721 break;
23722 }
23723 case AArch64::PTRUE_C_B:
23724 case AArch64::PTRUE_C_D:
23725 case AArch64::PTRUE_C_H:
23726 case AArch64::PTRUE_C_S: {
23727 switch (OpNum) {
23728 case 0:
23729 // op: PNd
23730 return 0;
23731 }
23732 break;
23733 }
23734 case AArch64::PEXT_2PCI_B:
23735 case AArch64::PEXT_2PCI_D:
23736 case AArch64::PEXT_2PCI_H:
23737 case AArch64::PEXT_2PCI_S:
23738 case AArch64::PEXT_PCI_B:
23739 case AArch64::PEXT_PCI_D:
23740 case AArch64::PEXT_PCI_H:
23741 case AArch64::PEXT_PCI_S: {
23742 switch (OpNum) {
23743 case 0:
23744 // op: Pd
23745 return 0;
23746 case 1:
23747 // op: PNn
23748 return 5;
23749 case 2:
23750 // op: index
23751 return 8;
23752 }
23753 break;
23754 }
23755 case AArch64::BRKAS_PPzP:
23756 case AArch64::BRKA_PPzP:
23757 case AArch64::BRKBS_PPzP:
23758 case AArch64::BRKB_PPzP: {
23759 switch (OpNum) {
23760 case 0:
23761 // op: Pd
23762 return 0;
23763 case 1:
23764 // op: Pg
23765 return 10;
23766 case 2:
23767 // op: Pn
23768 return 5;
23769 }
23770 break;
23771 }
23772 case AArch64::CMPEQ_PPzZI_B:
23773 case AArch64::CMPEQ_PPzZI_D:
23774 case AArch64::CMPEQ_PPzZI_H:
23775 case AArch64::CMPEQ_PPzZI_S:
23776 case AArch64::CMPGE_PPzZI_B:
23777 case AArch64::CMPGE_PPzZI_D:
23778 case AArch64::CMPGE_PPzZI_H:
23779 case AArch64::CMPGE_PPzZI_S:
23780 case AArch64::CMPGT_PPzZI_B:
23781 case AArch64::CMPGT_PPzZI_D:
23782 case AArch64::CMPGT_PPzZI_H:
23783 case AArch64::CMPGT_PPzZI_S:
23784 case AArch64::CMPLE_PPzZI_B:
23785 case AArch64::CMPLE_PPzZI_D:
23786 case AArch64::CMPLE_PPzZI_H:
23787 case AArch64::CMPLE_PPzZI_S:
23788 case AArch64::CMPLT_PPzZI_B:
23789 case AArch64::CMPLT_PPzZI_D:
23790 case AArch64::CMPLT_PPzZI_H:
23791 case AArch64::CMPLT_PPzZI_S:
23792 case AArch64::CMPNE_PPzZI_B:
23793 case AArch64::CMPNE_PPzZI_D:
23794 case AArch64::CMPNE_PPzZI_H:
23795 case AArch64::CMPNE_PPzZI_S: {
23796 switch (OpNum) {
23797 case 0:
23798 // op: Pd
23799 return 0;
23800 case 1:
23801 // op: Pg
23802 return 10;
23803 case 2:
23804 // op: Zn
23805 return 5;
23806 case 3:
23807 // op: imm5
23808 return 16;
23809 }
23810 break;
23811 }
23812 case AArch64::CMPHI_PPzZI_B:
23813 case AArch64::CMPHI_PPzZI_D:
23814 case AArch64::CMPHI_PPzZI_H:
23815 case AArch64::CMPHI_PPzZI_S:
23816 case AArch64::CMPHS_PPzZI_B:
23817 case AArch64::CMPHS_PPzZI_D:
23818 case AArch64::CMPHS_PPzZI_H:
23819 case AArch64::CMPHS_PPzZI_S:
23820 case AArch64::CMPLO_PPzZI_B:
23821 case AArch64::CMPLO_PPzZI_D:
23822 case AArch64::CMPLO_PPzZI_H:
23823 case AArch64::CMPLO_PPzZI_S:
23824 case AArch64::CMPLS_PPzZI_B:
23825 case AArch64::CMPLS_PPzZI_D:
23826 case AArch64::CMPLS_PPzZI_H:
23827 case AArch64::CMPLS_PPzZI_S: {
23828 switch (OpNum) {
23829 case 0:
23830 // op: Pd
23831 return 0;
23832 case 1:
23833 // op: Pg
23834 return 10;
23835 case 2:
23836 // op: Zn
23837 return 5;
23838 case 3:
23839 // op: imm7
23840 return 14;
23841 }
23842 break;
23843 }
23844 case AArch64::FCMEQ_PPzZ0_D:
23845 case AArch64::FCMEQ_PPzZ0_H:
23846 case AArch64::FCMEQ_PPzZ0_S:
23847 case AArch64::FCMGE_PPzZ0_D:
23848 case AArch64::FCMGE_PPzZ0_H:
23849 case AArch64::FCMGE_PPzZ0_S:
23850 case AArch64::FCMGT_PPzZ0_D:
23851 case AArch64::FCMGT_PPzZ0_H:
23852 case AArch64::FCMGT_PPzZ0_S:
23853 case AArch64::FCMLE_PPzZ0_D:
23854 case AArch64::FCMLE_PPzZ0_H:
23855 case AArch64::FCMLE_PPzZ0_S:
23856 case AArch64::FCMLT_PPzZ0_D:
23857 case AArch64::FCMLT_PPzZ0_H:
23858 case AArch64::FCMLT_PPzZ0_S:
23859 case AArch64::FCMNE_PPzZ0_D:
23860 case AArch64::FCMNE_PPzZ0_H:
23861 case AArch64::FCMNE_PPzZ0_S: {
23862 switch (OpNum) {
23863 case 0:
23864 // op: Pd
23865 return 0;
23866 case 1:
23867 // op: Pg
23868 return 10;
23869 case 2:
23870 // op: Zn
23871 return 5;
23872 }
23873 break;
23874 }
23875 case AArch64::ANDS_PPzPP:
23876 case AArch64::AND_PPzPP:
23877 case AArch64::BICS_PPzPP:
23878 case AArch64::BIC_PPzPP:
23879 case AArch64::BRKPAS_PPzPP:
23880 case AArch64::BRKPA_PPzPP:
23881 case AArch64::BRKPBS_PPzPP:
23882 case AArch64::BRKPB_PPzPP:
23883 case AArch64::EORS_PPzPP:
23884 case AArch64::EOR_PPzPP:
23885 case AArch64::NANDS_PPzPP:
23886 case AArch64::NAND_PPzPP:
23887 case AArch64::NORS_PPzPP:
23888 case AArch64::NOR_PPzPP:
23889 case AArch64::ORNS_PPzPP:
23890 case AArch64::ORN_PPzPP:
23891 case AArch64::ORRS_PPzPP:
23892 case AArch64::ORR_PPzPP:
23893 case AArch64::SEL_PPPP: {
23894 switch (OpNum) {
23895 case 0:
23896 // op: Pd
23897 return 0;
23898 case 1:
23899 // op: Pg
23900 return 10;
23901 case 3:
23902 // op: Pm
23903 return 16;
23904 case 2:
23905 // op: Pn
23906 return 5;
23907 }
23908 break;
23909 }
23910 case AArch64::CMPEQ_PPzZZ_B:
23911 case AArch64::CMPEQ_PPzZZ_D:
23912 case AArch64::CMPEQ_PPzZZ_H:
23913 case AArch64::CMPEQ_PPzZZ_S:
23914 case AArch64::CMPEQ_WIDE_PPzZZ_B:
23915 case AArch64::CMPEQ_WIDE_PPzZZ_H:
23916 case AArch64::CMPEQ_WIDE_PPzZZ_S:
23917 case AArch64::CMPGE_PPzZZ_B:
23918 case AArch64::CMPGE_PPzZZ_D:
23919 case AArch64::CMPGE_PPzZZ_H:
23920 case AArch64::CMPGE_PPzZZ_S:
23921 case AArch64::CMPGE_WIDE_PPzZZ_B:
23922 case AArch64::CMPGE_WIDE_PPzZZ_H:
23923 case AArch64::CMPGE_WIDE_PPzZZ_S:
23924 case AArch64::CMPGT_PPzZZ_B:
23925 case AArch64::CMPGT_PPzZZ_D:
23926 case AArch64::CMPGT_PPzZZ_H:
23927 case AArch64::CMPGT_PPzZZ_S:
23928 case AArch64::CMPGT_WIDE_PPzZZ_B:
23929 case AArch64::CMPGT_WIDE_PPzZZ_H:
23930 case AArch64::CMPGT_WIDE_PPzZZ_S:
23931 case AArch64::CMPHI_PPzZZ_B:
23932 case AArch64::CMPHI_PPzZZ_D:
23933 case AArch64::CMPHI_PPzZZ_H:
23934 case AArch64::CMPHI_PPzZZ_S:
23935 case AArch64::CMPHI_WIDE_PPzZZ_B:
23936 case AArch64::CMPHI_WIDE_PPzZZ_H:
23937 case AArch64::CMPHI_WIDE_PPzZZ_S:
23938 case AArch64::CMPHS_PPzZZ_B:
23939 case AArch64::CMPHS_PPzZZ_D:
23940 case AArch64::CMPHS_PPzZZ_H:
23941 case AArch64::CMPHS_PPzZZ_S:
23942 case AArch64::CMPHS_WIDE_PPzZZ_B:
23943 case AArch64::CMPHS_WIDE_PPzZZ_H:
23944 case AArch64::CMPHS_WIDE_PPzZZ_S:
23945 case AArch64::CMPLE_WIDE_PPzZZ_B:
23946 case AArch64::CMPLE_WIDE_PPzZZ_H:
23947 case AArch64::CMPLE_WIDE_PPzZZ_S:
23948 case AArch64::CMPLO_WIDE_PPzZZ_B:
23949 case AArch64::CMPLO_WIDE_PPzZZ_H:
23950 case AArch64::CMPLO_WIDE_PPzZZ_S:
23951 case AArch64::CMPLS_WIDE_PPzZZ_B:
23952 case AArch64::CMPLS_WIDE_PPzZZ_H:
23953 case AArch64::CMPLS_WIDE_PPzZZ_S:
23954 case AArch64::CMPLT_WIDE_PPzZZ_B:
23955 case AArch64::CMPLT_WIDE_PPzZZ_H:
23956 case AArch64::CMPLT_WIDE_PPzZZ_S:
23957 case AArch64::CMPNE_PPzZZ_B:
23958 case AArch64::CMPNE_PPzZZ_D:
23959 case AArch64::CMPNE_PPzZZ_H:
23960 case AArch64::CMPNE_PPzZZ_S:
23961 case AArch64::CMPNE_WIDE_PPzZZ_B:
23962 case AArch64::CMPNE_WIDE_PPzZZ_H:
23963 case AArch64::CMPNE_WIDE_PPzZZ_S:
23964 case AArch64::FACGE_PPzZZ_D:
23965 case AArch64::FACGE_PPzZZ_H:
23966 case AArch64::FACGE_PPzZZ_S:
23967 case AArch64::FACGT_PPzZZ_D:
23968 case AArch64::FACGT_PPzZZ_H:
23969 case AArch64::FACGT_PPzZZ_S:
23970 case AArch64::FCMEQ_PPzZZ_D:
23971 case AArch64::FCMEQ_PPzZZ_H:
23972 case AArch64::FCMEQ_PPzZZ_S:
23973 case AArch64::FCMGE_PPzZZ_D:
23974 case AArch64::FCMGE_PPzZZ_H:
23975 case AArch64::FCMGE_PPzZZ_S:
23976 case AArch64::FCMGT_PPzZZ_D:
23977 case AArch64::FCMGT_PPzZZ_H:
23978 case AArch64::FCMGT_PPzZZ_S:
23979 case AArch64::FCMNE_PPzZZ_D:
23980 case AArch64::FCMNE_PPzZZ_H:
23981 case AArch64::FCMNE_PPzZZ_S:
23982 case AArch64::FCMUO_PPzZZ_D:
23983 case AArch64::FCMUO_PPzZZ_H:
23984 case AArch64::FCMUO_PPzZZ_S:
23985 case AArch64::MATCH_PPzZZ_B:
23986 case AArch64::MATCH_PPzZZ_H:
23987 case AArch64::NMATCH_PPzZZ_B:
23988 case AArch64::NMATCH_PPzZZ_H: {
23989 switch (OpNum) {
23990 case 0:
23991 // op: Pd
23992 return 0;
23993 case 1:
23994 // op: Pg
23995 return 10;
23996 case 3:
23997 // op: Zm
23998 return 16;
23999 case 2:
24000 // op: Zn
24001 return 5;
24002 }
24003 break;
24004 }
24005 case AArch64::RDFFRS_PPz:
24006 case AArch64::RDFFR_PPz: {
24007 switch (OpNum) {
24008 case 0:
24009 // op: Pd
24010 return 0;
24011 case 1:
24012 // op: Pg
24013 return 5;
24014 }
24015 break;
24016 }
24017 case AArch64::PUNPKHI_PP:
24018 case AArch64::PUNPKLO_PP:
24019 case AArch64::REV_PP_B:
24020 case AArch64::REV_PP_D:
24021 case AArch64::REV_PP_H:
24022 case AArch64::REV_PP_S: {
24023 switch (OpNum) {
24024 case 0:
24025 // op: Pd
24026 return 0;
24027 case 1:
24028 // op: Pn
24029 return 5;
24030 }
24031 break;
24032 }
24033 case AArch64::PMOV_PZI_D:
24034 case AArch64::PMOV_PZI_H:
24035 case AArch64::PMOV_PZI_S: {
24036 switch (OpNum) {
24037 case 0:
24038 // op: Pd
24039 return 0;
24040 case 1:
24041 // op: Zn
24042 return 5;
24043 case 2:
24044 // op: index
24045 return 17;
24046 }
24047 break;
24048 }
24049 case AArch64::PMOV_PZI_B: {
24050 switch (OpNum) {
24051 case 0:
24052 // op: Pd
24053 return 0;
24054 case 1:
24055 // op: Zn
24056 return 5;
24057 }
24058 break;
24059 }
24060 case AArch64::PTRUES_B:
24061 case AArch64::PTRUES_D:
24062 case AArch64::PTRUES_H:
24063 case AArch64::PTRUES_S:
24064 case AArch64::PTRUE_B:
24065 case AArch64::PTRUE_D:
24066 case AArch64::PTRUE_H:
24067 case AArch64::PTRUE_S: {
24068 switch (OpNum) {
24069 case 0:
24070 // op: Pd
24071 return 0;
24072 case 1:
24073 // op: pattern
24074 return 5;
24075 }
24076 break;
24077 }
24078 case AArch64::BRKA_PPmP:
24079 case AArch64::BRKB_PPmP: {
24080 switch (OpNum) {
24081 case 0:
24082 // op: Pd
24083 return 0;
24084 case 2:
24085 // op: Pg
24086 return 10;
24087 case 3:
24088 // op: Pn
24089 return 5;
24090 }
24091 break;
24092 }
24093 case AArch64::TRN1_PPP_B:
24094 case AArch64::TRN1_PPP_D:
24095 case AArch64::TRN1_PPP_H:
24096 case AArch64::TRN1_PPP_S:
24097 case AArch64::TRN2_PPP_B:
24098 case AArch64::TRN2_PPP_D:
24099 case AArch64::TRN2_PPP_H:
24100 case AArch64::TRN2_PPP_S:
24101 case AArch64::UZP1_PPP_B:
24102 case AArch64::UZP1_PPP_D:
24103 case AArch64::UZP1_PPP_H:
24104 case AArch64::UZP1_PPP_S:
24105 case AArch64::UZP2_PPP_B:
24106 case AArch64::UZP2_PPP_D:
24107 case AArch64::UZP2_PPP_H:
24108 case AArch64::UZP2_PPP_S:
24109 case AArch64::ZIP1_PPP_B:
24110 case AArch64::ZIP1_PPP_D:
24111 case AArch64::ZIP1_PPP_H:
24112 case AArch64::ZIP1_PPP_S:
24113 case AArch64::ZIP2_PPP_B:
24114 case AArch64::ZIP2_PPP_D:
24115 case AArch64::ZIP2_PPP_H:
24116 case AArch64::ZIP2_PPP_S: {
24117 switch (OpNum) {
24118 case 0:
24119 // op: Pd
24120 return 0;
24121 case 2:
24122 // op: Pm
24123 return 16;
24124 case 1:
24125 // op: Pn
24126 return 5;
24127 }
24128 break;
24129 }
24130 case AArch64::WHILEGE_PWW_B:
24131 case AArch64::WHILEGE_PWW_D:
24132 case AArch64::WHILEGE_PWW_H:
24133 case AArch64::WHILEGE_PWW_S:
24134 case AArch64::WHILEGE_PXX_B:
24135 case AArch64::WHILEGE_PXX_D:
24136 case AArch64::WHILEGE_PXX_H:
24137 case AArch64::WHILEGE_PXX_S:
24138 case AArch64::WHILEGT_PWW_B:
24139 case AArch64::WHILEGT_PWW_D:
24140 case AArch64::WHILEGT_PWW_H:
24141 case AArch64::WHILEGT_PWW_S:
24142 case AArch64::WHILEGT_PXX_B:
24143 case AArch64::WHILEGT_PXX_D:
24144 case AArch64::WHILEGT_PXX_H:
24145 case AArch64::WHILEGT_PXX_S:
24146 case AArch64::WHILEHI_PWW_B:
24147 case AArch64::WHILEHI_PWW_D:
24148 case AArch64::WHILEHI_PWW_H:
24149 case AArch64::WHILEHI_PWW_S:
24150 case AArch64::WHILEHI_PXX_B:
24151 case AArch64::WHILEHI_PXX_D:
24152 case AArch64::WHILEHI_PXX_H:
24153 case AArch64::WHILEHI_PXX_S:
24154 case AArch64::WHILEHS_PWW_B:
24155 case AArch64::WHILEHS_PWW_D:
24156 case AArch64::WHILEHS_PWW_H:
24157 case AArch64::WHILEHS_PWW_S:
24158 case AArch64::WHILEHS_PXX_B:
24159 case AArch64::WHILEHS_PXX_D:
24160 case AArch64::WHILEHS_PXX_H:
24161 case AArch64::WHILEHS_PXX_S:
24162 case AArch64::WHILELE_PWW_B:
24163 case AArch64::WHILELE_PWW_D:
24164 case AArch64::WHILELE_PWW_H:
24165 case AArch64::WHILELE_PWW_S:
24166 case AArch64::WHILELE_PXX_B:
24167 case AArch64::WHILELE_PXX_D:
24168 case AArch64::WHILELE_PXX_H:
24169 case AArch64::WHILELE_PXX_S:
24170 case AArch64::WHILELO_PWW_B:
24171 case AArch64::WHILELO_PWW_D:
24172 case AArch64::WHILELO_PWW_H:
24173 case AArch64::WHILELO_PWW_S:
24174 case AArch64::WHILELO_PXX_B:
24175 case AArch64::WHILELO_PXX_D:
24176 case AArch64::WHILELO_PXX_H:
24177 case AArch64::WHILELO_PXX_S:
24178 case AArch64::WHILELS_PWW_B:
24179 case AArch64::WHILELS_PWW_D:
24180 case AArch64::WHILELS_PWW_H:
24181 case AArch64::WHILELS_PWW_S:
24182 case AArch64::WHILELS_PXX_B:
24183 case AArch64::WHILELS_PXX_D:
24184 case AArch64::WHILELS_PXX_H:
24185 case AArch64::WHILELS_PXX_S:
24186 case AArch64::WHILELT_PWW_B:
24187 case AArch64::WHILELT_PWW_D:
24188 case AArch64::WHILELT_PWW_H:
24189 case AArch64::WHILELT_PWW_S:
24190 case AArch64::WHILELT_PXX_B:
24191 case AArch64::WHILELT_PXX_D:
24192 case AArch64::WHILELT_PXX_H:
24193 case AArch64::WHILELT_PXX_S:
24194 case AArch64::WHILERW_PXX_B:
24195 case AArch64::WHILERW_PXX_D:
24196 case AArch64::WHILERW_PXX_H:
24197 case AArch64::WHILERW_PXX_S:
24198 case AArch64::WHILEWR_PXX_B:
24199 case AArch64::WHILEWR_PXX_D:
24200 case AArch64::WHILEWR_PXX_H:
24201 case AArch64::WHILEWR_PXX_S: {
24202 switch (OpNum) {
24203 case 0:
24204 // op: Pd
24205 return 0;
24206 case 2:
24207 // op: Rm
24208 return 16;
24209 case 1:
24210 // op: Rn
24211 return 5;
24212 }
24213 break;
24214 }
24215 case AArch64::PFALSE:
24216 case AArch64::RDFFR_P: {
24217 switch (OpNum) {
24218 case 0:
24219 // op: Pd
24220 return 0;
24221 }
24222 break;
24223 }
24224 case AArch64::WHILEGE_2PXX_B:
24225 case AArch64::WHILEGE_2PXX_D:
24226 case AArch64::WHILEGE_2PXX_H:
24227 case AArch64::WHILEGE_2PXX_S:
24228 case AArch64::WHILEGT_2PXX_B:
24229 case AArch64::WHILEGT_2PXX_D:
24230 case AArch64::WHILEGT_2PXX_H:
24231 case AArch64::WHILEGT_2PXX_S:
24232 case AArch64::WHILEHI_2PXX_B:
24233 case AArch64::WHILEHI_2PXX_D:
24234 case AArch64::WHILEHI_2PXX_H:
24235 case AArch64::WHILEHI_2PXX_S:
24236 case AArch64::WHILEHS_2PXX_B:
24237 case AArch64::WHILEHS_2PXX_D:
24238 case AArch64::WHILEHS_2PXX_H:
24239 case AArch64::WHILEHS_2PXX_S:
24240 case AArch64::WHILELE_2PXX_B:
24241 case AArch64::WHILELE_2PXX_D:
24242 case AArch64::WHILELE_2PXX_H:
24243 case AArch64::WHILELE_2PXX_S:
24244 case AArch64::WHILELO_2PXX_B:
24245 case AArch64::WHILELO_2PXX_D:
24246 case AArch64::WHILELO_2PXX_H:
24247 case AArch64::WHILELO_2PXX_S:
24248 case AArch64::WHILELS_2PXX_B:
24249 case AArch64::WHILELS_2PXX_D:
24250 case AArch64::WHILELS_2PXX_H:
24251 case AArch64::WHILELS_2PXX_S:
24252 case AArch64::WHILELT_2PXX_B:
24253 case AArch64::WHILELT_2PXX_D:
24254 case AArch64::WHILELT_2PXX_H:
24255 case AArch64::WHILELT_2PXX_S: {
24256 switch (OpNum) {
24257 case 0:
24258 // op: Pd
24259 return 1;
24260 case 1:
24261 // op: Rn
24262 return 5;
24263 case 2:
24264 // op: Rm
24265 return 16;
24266 }
24267 break;
24268 }
24269 case AArch64::BRKNS_PPzP:
24270 case AArch64::BRKN_PPzP: {
24271 switch (OpNum) {
24272 case 0:
24273 // op: Pdm
24274 return 0;
24275 case 1:
24276 // op: Pg
24277 return 10;
24278 case 2:
24279 // op: Pn
24280 return 5;
24281 }
24282 break;
24283 }
24284 case AArch64::PFIRST_B:
24285 case AArch64::PNEXT_B:
24286 case AArch64::PNEXT_D:
24287 case AArch64::PNEXT_H:
24288 case AArch64::PNEXT_S: {
24289 switch (OpNum) {
24290 case 0:
24291 // op: Pdn
24292 return 0;
24293 case 1:
24294 // op: Pg
24295 return 5;
24296 }
24297 break;
24298 }
24299 case AArch64::PTEST_PP: {
24300 switch (OpNum) {
24301 case 0:
24302 // op: Pg
24303 return 10;
24304 case 1:
24305 // op: Pn
24306 return 5;
24307 }
24308 break;
24309 }
24310 case AArch64::WRFFR: {
24311 switch (OpNum) {
24312 case 0:
24313 // op: Pn
24314 return 5;
24315 }
24316 break;
24317 }
24318 case AArch64::LDR_PXI:
24319 case AArch64::STR_PXI: {
24320 switch (OpNum) {
24321 case 0:
24322 // op: Pt
24323 return 0;
24324 case 1:
24325 // op: Rn
24326 return 5;
24327 case 2:
24328 // op: imm9
24329 return 10;
24330 }
24331 break;
24332 }
24333 case AArch64::CNTP_XCI_B:
24334 case AArch64::CNTP_XCI_D:
24335 case AArch64::CNTP_XCI_H:
24336 case AArch64::CNTP_XCI_S: {
24337 switch (OpNum) {
24338 case 0:
24339 // op: Rd
24340 return 0;
24341 case 1:
24342 // op: PNn
24343 return 5;
24344 case 2:
24345 // op: vl
24346 return 10;
24347 }
24348 break;
24349 }
24350 case AArch64::ADDPL_XXI:
24351 case AArch64::ADDSPL_XXI:
24352 case AArch64::ADDSVL_XXI:
24353 case AArch64::ADDVL_XXI: {
24354 switch (OpNum) {
24355 case 0:
24356 // op: Rd
24357 return 0;
24358 case 1:
24359 // op: Rn
24360 return 16;
24361 case 2:
24362 // op: imm6
24363 return 5;
24364 }
24365 break;
24366 }
24367 case AArch64::FMADDDrrr:
24368 case AArch64::FMADDHrrr:
24369 case AArch64::FMADDSrrr:
24370 case AArch64::FMSUBDrrr:
24371 case AArch64::FMSUBHrrr:
24372 case AArch64::FMSUBSrrr:
24373 case AArch64::FNMADDDrrr:
24374 case AArch64::FNMADDHrrr:
24375 case AArch64::FNMADDSrrr:
24376 case AArch64::FNMSUBDrrr:
24377 case AArch64::FNMSUBHrrr:
24378 case AArch64::FNMSUBSrrr:
24379 case AArch64::MADDPT:
24380 case AArch64::MADDWrrr:
24381 case AArch64::MADDXrrr:
24382 case AArch64::MSUBPT:
24383 case AArch64::MSUBWrrr:
24384 case AArch64::MSUBXrrr:
24385 case AArch64::SMADDLrrr:
24386 case AArch64::SMSUBLrrr:
24387 case AArch64::UMADDLrrr:
24388 case AArch64::UMSUBLrrr: {
24389 switch (OpNum) {
24390 case 0:
24391 // op: Rd
24392 return 0;
24393 case 1:
24394 // op: Rn
24395 return 5;
24396 case 2:
24397 // op: Rm
24398 return 16;
24399 case 3:
24400 // op: Ra
24401 return 10;
24402 }
24403 break;
24404 }
24405 case AArch64::CSELWr:
24406 case AArch64::CSELXr:
24407 case AArch64::CSINCWr:
24408 case AArch64::CSINCXr:
24409 case AArch64::CSINVWr:
24410 case AArch64::CSINVXr:
24411 case AArch64::CSNEGWr:
24412 case AArch64::CSNEGXr:
24413 case AArch64::FCSELDrrr:
24414 case AArch64::FCSELHrrr:
24415 case AArch64::FCSELSrrr: {
24416 switch (OpNum) {
24417 case 0:
24418 // op: Rd
24419 return 0;
24420 case 1:
24421 // op: Rn
24422 return 5;
24423 case 2:
24424 // op: Rm
24425 return 16;
24426 case 3:
24427 // op: cond
24428 return 12;
24429 }
24430 break;
24431 }
24432 case AArch64::ADDSXrx64:
24433 case AArch64::ADDXrx64:
24434 case AArch64::SUBSXrx64:
24435 case AArch64::SUBXrx64: {
24436 switch (OpNum) {
24437 case 0:
24438 // op: Rd
24439 return 0;
24440 case 1:
24441 // op: Rn
24442 return 5;
24443 case 2:
24444 // op: Rm
24445 return 16;
24446 case 3:
24447 // op: ext
24448 return 10;
24449 }
24450 break;
24451 }
24452 case AArch64::ADDSWrx:
24453 case AArch64::ADDSXrx:
24454 case AArch64::ADDWrx:
24455 case AArch64::ADDXrx:
24456 case AArch64::SUBSWrx:
24457 case AArch64::SUBSXrx:
24458 case AArch64::SUBWrx:
24459 case AArch64::SUBXrx: {
24460 switch (OpNum) {
24461 case 0:
24462 // op: Rd
24463 return 0;
24464 case 1:
24465 // op: Rn
24466 return 5;
24467 case 2:
24468 // op: Rm
24469 return 16;
24470 case 3:
24471 // op: extend
24472 return 10;
24473 }
24474 break;
24475 }
24476 case AArch64::FMULXv1i16_indexed:
24477 case AArch64::FMULXv1i32_indexed:
24478 case AArch64::FMULXv1i64_indexed:
24479 case AArch64::FMULXv2i32_indexed:
24480 case AArch64::FMULXv2i64_indexed:
24481 case AArch64::FMULXv4i16_indexed:
24482 case AArch64::FMULXv4i32_indexed:
24483 case AArch64::FMULXv8i16_indexed:
24484 case AArch64::FMULv1i16_indexed:
24485 case AArch64::FMULv1i32_indexed:
24486 case AArch64::FMULv1i64_indexed:
24487 case AArch64::FMULv2i32_indexed:
24488 case AArch64::FMULv2i64_indexed:
24489 case AArch64::FMULv4i16_indexed:
24490 case AArch64::FMULv4i32_indexed:
24491 case AArch64::FMULv8i16_indexed:
24492 case AArch64::MULv2i32_indexed:
24493 case AArch64::MULv4i16_indexed:
24494 case AArch64::MULv4i32_indexed:
24495 case AArch64::MULv8i16_indexed:
24496 case AArch64::SMULLv2i32_indexed:
24497 case AArch64::SMULLv4i16_indexed:
24498 case AArch64::SMULLv4i32_indexed:
24499 case AArch64::SMULLv8i16_indexed:
24500 case AArch64::SQDMULHv1i16_indexed:
24501 case AArch64::SQDMULHv1i32_indexed:
24502 case AArch64::SQDMULHv2i32_indexed:
24503 case AArch64::SQDMULHv4i16_indexed:
24504 case AArch64::SQDMULHv4i32_indexed:
24505 case AArch64::SQDMULHv8i16_indexed:
24506 case AArch64::SQDMULLv1i32_indexed:
24507 case AArch64::SQDMULLv1i64_indexed:
24508 case AArch64::SQDMULLv2i32_indexed:
24509 case AArch64::SQDMULLv4i16_indexed:
24510 case AArch64::SQDMULLv4i32_indexed:
24511 case AArch64::SQDMULLv8i16_indexed:
24512 case AArch64::SQRDMULHv1i16_indexed:
24513 case AArch64::SQRDMULHv1i32_indexed:
24514 case AArch64::SQRDMULHv2i32_indexed:
24515 case AArch64::SQRDMULHv4i16_indexed:
24516 case AArch64::SQRDMULHv4i32_indexed:
24517 case AArch64::SQRDMULHv8i16_indexed:
24518 case AArch64::UMULLv2i32_indexed:
24519 case AArch64::UMULLv4i16_indexed:
24520 case AArch64::UMULLv4i32_indexed:
24521 case AArch64::UMULLv8i16_indexed: {
24522 switch (OpNum) {
24523 case 0:
24524 // op: Rd
24525 return 0;
24526 case 1:
24527 // op: Rn
24528 return 5;
24529 case 2:
24530 // op: Rm
24531 return 16;
24532 case 3:
24533 // op: idx
24534 return 11;
24535 }
24536 break;
24537 }
24538 case AArch64::LUT2v8f16: {
24539 switch (OpNum) {
24540 case 0:
24541 // op: Rd
24542 return 0;
24543 case 1:
24544 // op: Rn
24545 return 5;
24546 case 2:
24547 // op: Rm
24548 return 16;
24549 case 3:
24550 // op: idx
24551 return 12;
24552 }
24553 break;
24554 }
24555 case AArch64::LUT2v16f8:
24556 case AArch64::LUT4v8f16: {
24557 switch (OpNum) {
24558 case 0:
24559 // op: Rd
24560 return 0;
24561 case 1:
24562 // op: Rn
24563 return 5;
24564 case 2:
24565 // op: Rm
24566 return 16;
24567 case 3:
24568 // op: idx
24569 return 13;
24570 }
24571 break;
24572 }
24573 case AArch64::LUT4v16f8: {
24574 switch (OpNum) {
24575 case 0:
24576 // op: Rd
24577 return 0;
24578 case 1:
24579 // op: Rn
24580 return 5;
24581 case 2:
24582 // op: Rm
24583 return 16;
24584 case 3:
24585 // op: idx
24586 return 14;
24587 }
24588 break;
24589 }
24590 case AArch64::EXTRWrri:
24591 case AArch64::EXTRXrri: {
24592 switch (OpNum) {
24593 case 0:
24594 // op: Rd
24595 return 0;
24596 case 1:
24597 // op: Rn
24598 return 5;
24599 case 2:
24600 // op: Rm
24601 return 16;
24602 case 3:
24603 // op: imm
24604 return 10;
24605 }
24606 break;
24607 }
24608 case AArch64::EXTv8i8:
24609 case AArch64::EXTv16i8: {
24610 switch (OpNum) {
24611 case 0:
24612 // op: Rd
24613 return 0;
24614 case 1:
24615 // op: Rn
24616 return 5;
24617 case 2:
24618 // op: Rm
24619 return 16;
24620 case 3:
24621 // op: imm
24622 return 11;
24623 }
24624 break;
24625 }
24626 case AArch64::FCADDv2f32:
24627 case AArch64::FCADDv2f64:
24628 case AArch64::FCADDv4f16:
24629 case AArch64::FCADDv4f32:
24630 case AArch64::FCADDv8f16: {
24631 switch (OpNum) {
24632 case 0:
24633 // op: Rd
24634 return 0;
24635 case 1:
24636 // op: Rn
24637 return 5;
24638 case 2:
24639 // op: Rm
24640 return 16;
24641 case 3:
24642 // op: rot
24643 return 12;
24644 }
24645 break;
24646 }
24647 case AArch64::ADDSWrs:
24648 case AArch64::ADDSXrs:
24649 case AArch64::ADDWrs:
24650 case AArch64::ADDXrs:
24651 case AArch64::ANDSWrs:
24652 case AArch64::ANDSXrs:
24653 case AArch64::ANDWrs:
24654 case AArch64::ANDXrs:
24655 case AArch64::BICSWrs:
24656 case AArch64::BICSXrs:
24657 case AArch64::BICWrs:
24658 case AArch64::BICXrs:
24659 case AArch64::EONWrs:
24660 case AArch64::EONXrs:
24661 case AArch64::EORWrs:
24662 case AArch64::EORXrs:
24663 case AArch64::ORNWrs:
24664 case AArch64::ORNXrs:
24665 case AArch64::ORRWrs:
24666 case AArch64::ORRXrs:
24667 case AArch64::SUBSWrs:
24668 case AArch64::SUBSXrs:
24669 case AArch64::SUBWrs:
24670 case AArch64::SUBXrs: {
24671 switch (OpNum) {
24672 case 0:
24673 // op: Rd
24674 return 0;
24675 case 1:
24676 // op: Rn
24677 return 5;
24678 case 2:
24679 // op: Rm
24680 return 16;
24681 case 3:
24682 // op: shift
24683 return 10;
24684 }
24685 break;
24686 }
24687 case AArch64::ADDPT_shift:
24688 case AArch64::SUBPT_shift: {
24689 switch (OpNum) {
24690 case 0:
24691 // op: Rd
24692 return 0;
24693 case 1:
24694 // op: Rn
24695 return 5;
24696 case 2:
24697 // op: Rm
24698 return 16;
24699 case 3:
24700 // op: shift_imm
24701 return 10;
24702 }
24703 break;
24704 }
24705 case AArch64::ADCSWr:
24706 case AArch64::ADCSXr:
24707 case AArch64::ADCWr:
24708 case AArch64::ADCXr:
24709 case AArch64::ADDHNv2i64_v2i32:
24710 case AArch64::ADDHNv4i32_v4i16:
24711 case AArch64::ADDHNv8i16_v8i8:
24712 case AArch64::ADDPv2i32:
24713 case AArch64::ADDPv2i64:
24714 case AArch64::ADDPv4i16:
24715 case AArch64::ADDPv4i32:
24716 case AArch64::ADDPv8i8:
24717 case AArch64::ADDPv8i16:
24718 case AArch64::ADDPv16i8:
24719 case AArch64::ADDv1i64:
24720 case AArch64::ADDv2i32:
24721 case AArch64::ADDv2i64:
24722 case AArch64::ADDv4i16:
24723 case AArch64::ADDv4i32:
24724 case AArch64::ADDv8i8:
24725 case AArch64::ADDv8i16:
24726 case AArch64::ADDv16i8:
24727 case AArch64::ANDv8i8:
24728 case AArch64::ANDv16i8:
24729 case AArch64::ASRVWr:
24730 case AArch64::ASRVXr:
24731 case AArch64::BICv8i8:
24732 case AArch64::BICv16i8:
24733 case AArch64::CMEQv1i64:
24734 case AArch64::CMEQv2i32:
24735 case AArch64::CMEQv2i64:
24736 case AArch64::CMEQv4i16:
24737 case AArch64::CMEQv4i32:
24738 case AArch64::CMEQv8i8:
24739 case AArch64::CMEQv8i16:
24740 case AArch64::CMEQv16i8:
24741 case AArch64::CMGEv1i64:
24742 case AArch64::CMGEv2i32:
24743 case AArch64::CMGEv2i64:
24744 case AArch64::CMGEv4i16:
24745 case AArch64::CMGEv4i32:
24746 case AArch64::CMGEv8i8:
24747 case AArch64::CMGEv8i16:
24748 case AArch64::CMGEv16i8:
24749 case AArch64::CMGTv1i64:
24750 case AArch64::CMGTv2i32:
24751 case AArch64::CMGTv2i64:
24752 case AArch64::CMGTv4i16:
24753 case AArch64::CMGTv4i32:
24754 case AArch64::CMGTv8i8:
24755 case AArch64::CMGTv8i16:
24756 case AArch64::CMGTv16i8:
24757 case AArch64::CMHIv1i64:
24758 case AArch64::CMHIv2i32:
24759 case AArch64::CMHIv2i64:
24760 case AArch64::CMHIv4i16:
24761 case AArch64::CMHIv4i32:
24762 case AArch64::CMHIv8i8:
24763 case AArch64::CMHIv8i16:
24764 case AArch64::CMHIv16i8:
24765 case AArch64::CMHSv1i64:
24766 case AArch64::CMHSv2i32:
24767 case AArch64::CMHSv2i64:
24768 case AArch64::CMHSv4i16:
24769 case AArch64::CMHSv4i32:
24770 case AArch64::CMHSv8i8:
24771 case AArch64::CMHSv8i16:
24772 case AArch64::CMHSv16i8:
24773 case AArch64::CMTSTv1i64:
24774 case AArch64::CMTSTv2i32:
24775 case AArch64::CMTSTv2i64:
24776 case AArch64::CMTSTv4i16:
24777 case AArch64::CMTSTv4i32:
24778 case AArch64::CMTSTv8i8:
24779 case AArch64::CMTSTv8i16:
24780 case AArch64::CMTSTv16i8:
24781 case AArch64::CRC32Brr:
24782 case AArch64::CRC32CBrr:
24783 case AArch64::CRC32CHrr:
24784 case AArch64::CRC32CWrr:
24785 case AArch64::CRC32CXrr:
24786 case AArch64::CRC32Hrr:
24787 case AArch64::CRC32Wrr:
24788 case AArch64::CRC32Xrr:
24789 case AArch64::EORv8i8:
24790 case AArch64::EORv16i8:
24791 case AArch64::FABD16:
24792 case AArch64::FABD32:
24793 case AArch64::FABD64:
24794 case AArch64::FABDv2f32:
24795 case AArch64::FABDv2f64:
24796 case AArch64::FABDv4f16:
24797 case AArch64::FABDv4f32:
24798 case AArch64::FABDv8f16:
24799 case AArch64::FACGE16:
24800 case AArch64::FACGE32:
24801 case AArch64::FACGE64:
24802 case AArch64::FACGEv2f32:
24803 case AArch64::FACGEv2f64:
24804 case AArch64::FACGEv4f16:
24805 case AArch64::FACGEv4f32:
24806 case AArch64::FACGEv8f16:
24807 case AArch64::FACGT16:
24808 case AArch64::FACGT32:
24809 case AArch64::FACGT64:
24810 case AArch64::FACGTv2f32:
24811 case AArch64::FACGTv2f64:
24812 case AArch64::FACGTv4f16:
24813 case AArch64::FACGTv4f32:
24814 case AArch64::FACGTv8f16:
24815 case AArch64::FADDDrr:
24816 case AArch64::FADDHrr:
24817 case AArch64::FADDPv2f32:
24818 case AArch64::FADDPv2f64:
24819 case AArch64::FADDPv4f16:
24820 case AArch64::FADDPv4f32:
24821 case AArch64::FADDPv8f16:
24822 case AArch64::FADDSrr:
24823 case AArch64::FADDv2f32:
24824 case AArch64::FADDv2f64:
24825 case AArch64::FADDv4f16:
24826 case AArch64::FADDv4f32:
24827 case AArch64::FADDv8f16:
24828 case AArch64::FAMAXv2f32:
24829 case AArch64::FAMAXv2f64:
24830 case AArch64::FAMAXv4f16:
24831 case AArch64::FAMAXv4f32:
24832 case AArch64::FAMAXv8f16:
24833 case AArch64::FAMINv2f32:
24834 case AArch64::FAMINv2f64:
24835 case AArch64::FAMINv4f16:
24836 case AArch64::FAMINv4f32:
24837 case AArch64::FAMINv8f16:
24838 case AArch64::FCMEQ16:
24839 case AArch64::FCMEQ32:
24840 case AArch64::FCMEQ64:
24841 case AArch64::FCMEQv2f32:
24842 case AArch64::FCMEQv2f64:
24843 case AArch64::FCMEQv4f16:
24844 case AArch64::FCMEQv4f32:
24845 case AArch64::FCMEQv8f16:
24846 case AArch64::FCMGE16:
24847 case AArch64::FCMGE32:
24848 case AArch64::FCMGE64:
24849 case AArch64::FCMGEv2f32:
24850 case AArch64::FCMGEv2f64:
24851 case AArch64::FCMGEv4f16:
24852 case AArch64::FCMGEv4f32:
24853 case AArch64::FCMGEv8f16:
24854 case AArch64::FCMGT16:
24855 case AArch64::FCMGT32:
24856 case AArch64::FCMGT64:
24857 case AArch64::FCMGTv2f32:
24858 case AArch64::FCMGTv2f64:
24859 case AArch64::FCMGTv4f16:
24860 case AArch64::FCMGTv4f32:
24861 case AArch64::FCMGTv8f16:
24862 case AArch64::FCVTN_F16_F8v8f8:
24863 case AArch64::FCVTN_F16_F8v16f8:
24864 case AArch64::FCVTN_F32_F8v8f8:
24865 case AArch64::FDIVDrr:
24866 case AArch64::FDIVHrr:
24867 case AArch64::FDIVSrr:
24868 case AArch64::FDIVv2f32:
24869 case AArch64::FDIVv2f64:
24870 case AArch64::FDIVv4f16:
24871 case AArch64::FDIVv4f32:
24872 case AArch64::FDIVv8f16:
24873 case AArch64::FMAXDrr:
24874 case AArch64::FMAXHrr:
24875 case AArch64::FMAXNMDrr:
24876 case AArch64::FMAXNMHrr:
24877 case AArch64::FMAXNMPv2f32:
24878 case AArch64::FMAXNMPv2f64:
24879 case AArch64::FMAXNMPv4f16:
24880 case AArch64::FMAXNMPv4f32:
24881 case AArch64::FMAXNMPv8f16:
24882 case AArch64::FMAXNMSrr:
24883 case AArch64::FMAXNMv2f32:
24884 case AArch64::FMAXNMv2f64:
24885 case AArch64::FMAXNMv4f16:
24886 case AArch64::FMAXNMv4f32:
24887 case AArch64::FMAXNMv8f16:
24888 case AArch64::FMAXPv2f32:
24889 case AArch64::FMAXPv2f64:
24890 case AArch64::FMAXPv4f16:
24891 case AArch64::FMAXPv4f32:
24892 case AArch64::FMAXPv8f16:
24893 case AArch64::FMAXSrr:
24894 case AArch64::FMAXv2f32:
24895 case AArch64::FMAXv2f64:
24896 case AArch64::FMAXv4f16:
24897 case AArch64::FMAXv4f32:
24898 case AArch64::FMAXv8f16:
24899 case AArch64::FMINDrr:
24900 case AArch64::FMINHrr:
24901 case AArch64::FMINNMDrr:
24902 case AArch64::FMINNMHrr:
24903 case AArch64::FMINNMPv2f32:
24904 case AArch64::FMINNMPv2f64:
24905 case AArch64::FMINNMPv4f16:
24906 case AArch64::FMINNMPv4f32:
24907 case AArch64::FMINNMPv8f16:
24908 case AArch64::FMINNMSrr:
24909 case AArch64::FMINNMv2f32:
24910 case AArch64::FMINNMv2f64:
24911 case AArch64::FMINNMv4f16:
24912 case AArch64::FMINNMv4f32:
24913 case AArch64::FMINNMv8f16:
24914 case AArch64::FMINPv2f32:
24915 case AArch64::FMINPv2f64:
24916 case AArch64::FMINPv4f16:
24917 case AArch64::FMINPv4f32:
24918 case AArch64::FMINPv8f16:
24919 case AArch64::FMINSrr:
24920 case AArch64::FMINv2f32:
24921 case AArch64::FMINv2f64:
24922 case AArch64::FMINv4f16:
24923 case AArch64::FMINv4f32:
24924 case AArch64::FMINv8f16:
24925 case AArch64::FMULDrr:
24926 case AArch64::FMULHrr:
24927 case AArch64::FMULSrr:
24928 case AArch64::FMULX16:
24929 case AArch64::FMULX32:
24930 case AArch64::FMULX64:
24931 case AArch64::FMULXv2f32:
24932 case AArch64::FMULXv2f64:
24933 case AArch64::FMULXv4f16:
24934 case AArch64::FMULXv4f32:
24935 case AArch64::FMULXv8f16:
24936 case AArch64::FMULv2f32:
24937 case AArch64::FMULv2f64:
24938 case AArch64::FMULv4f16:
24939 case AArch64::FMULv4f32:
24940 case AArch64::FMULv8f16:
24941 case AArch64::FNMULDrr:
24942 case AArch64::FNMULHrr:
24943 case AArch64::FNMULSrr:
24944 case AArch64::FRECPS16:
24945 case AArch64::FRECPS32:
24946 case AArch64::FRECPS64:
24947 case AArch64::FRECPSv2f32:
24948 case AArch64::FRECPSv2f64:
24949 case AArch64::FRECPSv4f16:
24950 case AArch64::FRECPSv4f32:
24951 case AArch64::FRECPSv8f16:
24952 case AArch64::FRSQRTS16:
24953 case AArch64::FRSQRTS32:
24954 case AArch64::FRSQRTS64:
24955 case AArch64::FRSQRTSv2f32:
24956 case AArch64::FRSQRTSv2f64:
24957 case AArch64::FRSQRTSv4f16:
24958 case AArch64::FRSQRTSv4f32:
24959 case AArch64::FRSQRTSv8f16:
24960 case AArch64::FSCALEv2f32:
24961 case AArch64::FSCALEv2f64:
24962 case AArch64::FSCALEv4f16:
24963 case AArch64::FSCALEv4f32:
24964 case AArch64::FSCALEv8f16:
24965 case AArch64::FSUBDrr:
24966 case AArch64::FSUBHrr:
24967 case AArch64::FSUBSrr:
24968 case AArch64::FSUBv2f32:
24969 case AArch64::FSUBv2f64:
24970 case AArch64::FSUBv4f16:
24971 case AArch64::FSUBv4f32:
24972 case AArch64::FSUBv8f16:
24973 case AArch64::GMI:
24974 case AArch64::IRG:
24975 case AArch64::LSLVWr:
24976 case AArch64::LSLVXr:
24977 case AArch64::LSRVWr:
24978 case AArch64::LSRVXr:
24979 case AArch64::MULv2i32:
24980 case AArch64::MULv4i16:
24981 case AArch64::MULv4i32:
24982 case AArch64::MULv8i8:
24983 case AArch64::MULv8i16:
24984 case AArch64::MULv16i8:
24985 case AArch64::ORNv8i8:
24986 case AArch64::ORNv16i8:
24987 case AArch64::ORRv8i8:
24988 case AArch64::ORRv16i8:
24989 case AArch64::PACGA:
24990 case AArch64::PMULLv1i64:
24991 case AArch64::PMULLv2i64:
24992 case AArch64::PMULLv8i8:
24993 case AArch64::PMULLv16i8:
24994 case AArch64::PMULv8i8:
24995 case AArch64::PMULv16i8:
24996 case AArch64::RADDHNv2i64_v2i32:
24997 case AArch64::RADDHNv4i32_v4i16:
24998 case AArch64::RADDHNv8i16_v8i8:
24999 case AArch64::RORVWr:
25000 case AArch64::RORVXr:
25001 case AArch64::RSUBHNv2i64_v2i32:
25002 case AArch64::RSUBHNv4i32_v4i16:
25003 case AArch64::RSUBHNv8i16_v8i8:
25004 case AArch64::SABDLv2i32_v2i64:
25005 case AArch64::SABDLv4i16_v4i32:
25006 case AArch64::SABDLv4i32_v2i64:
25007 case AArch64::SABDLv8i8_v8i16:
25008 case AArch64::SABDLv8i16_v4i32:
25009 case AArch64::SABDLv16i8_v8i16:
25010 case AArch64::SABDv2i32:
25011 case AArch64::SABDv4i16:
25012 case AArch64::SABDv4i32:
25013 case AArch64::SABDv8i8:
25014 case AArch64::SABDv8i16:
25015 case AArch64::SABDv16i8:
25016 case AArch64::SADDLv2i32_v2i64:
25017 case AArch64::SADDLv4i16_v4i32:
25018 case AArch64::SADDLv4i32_v2i64:
25019 case AArch64::SADDLv8i8_v8i16:
25020 case AArch64::SADDLv8i16_v4i32:
25021 case AArch64::SADDLv16i8_v8i16:
25022 case AArch64::SADDWv2i32_v2i64:
25023 case AArch64::SADDWv4i16_v4i32:
25024 case AArch64::SADDWv4i32_v2i64:
25025 case AArch64::SADDWv8i8_v8i16:
25026 case AArch64::SADDWv8i16_v4i32:
25027 case AArch64::SADDWv16i8_v8i16:
25028 case AArch64::SBCSWr:
25029 case AArch64::SBCSXr:
25030 case AArch64::SBCWr:
25031 case AArch64::SBCXr:
25032 case AArch64::SDIVWr:
25033 case AArch64::SDIVXr:
25034 case AArch64::SHADDv2i32:
25035 case AArch64::SHADDv4i16:
25036 case AArch64::SHADDv4i32:
25037 case AArch64::SHADDv8i8:
25038 case AArch64::SHADDv8i16:
25039 case AArch64::SHADDv16i8:
25040 case AArch64::SHSUBv2i32:
25041 case AArch64::SHSUBv4i16:
25042 case AArch64::SHSUBv4i32:
25043 case AArch64::SHSUBv8i8:
25044 case AArch64::SHSUBv8i16:
25045 case AArch64::SHSUBv16i8:
25046 case AArch64::SMAXPv2i32:
25047 case AArch64::SMAXPv4i16:
25048 case AArch64::SMAXPv4i32:
25049 case AArch64::SMAXPv8i8:
25050 case AArch64::SMAXPv8i16:
25051 case AArch64::SMAXPv16i8:
25052 case AArch64::SMAXWrr:
25053 case AArch64::SMAXXrr:
25054 case AArch64::SMAXv2i32:
25055 case AArch64::SMAXv4i16:
25056 case AArch64::SMAXv4i32:
25057 case AArch64::SMAXv8i8:
25058 case AArch64::SMAXv8i16:
25059 case AArch64::SMAXv16i8:
25060 case AArch64::SMINPv2i32:
25061 case AArch64::SMINPv4i16:
25062 case AArch64::SMINPv4i32:
25063 case AArch64::SMINPv8i8:
25064 case AArch64::SMINPv8i16:
25065 case AArch64::SMINPv16i8:
25066 case AArch64::SMINWrr:
25067 case AArch64::SMINXrr:
25068 case AArch64::SMINv2i32:
25069 case AArch64::SMINv4i16:
25070 case AArch64::SMINv4i32:
25071 case AArch64::SMINv8i8:
25072 case AArch64::SMINv8i16:
25073 case AArch64::SMINv16i8:
25074 case AArch64::SMULHrr:
25075 case AArch64::SMULLv2i32_v2i64:
25076 case AArch64::SMULLv4i16_v4i32:
25077 case AArch64::SMULLv4i32_v2i64:
25078 case AArch64::SMULLv8i8_v8i16:
25079 case AArch64::SMULLv8i16_v4i32:
25080 case AArch64::SMULLv16i8_v8i16:
25081 case AArch64::SQADDv1i8:
25082 case AArch64::SQADDv1i16:
25083 case AArch64::SQADDv1i32:
25084 case AArch64::SQADDv1i64:
25085 case AArch64::SQADDv2i32:
25086 case AArch64::SQADDv2i64:
25087 case AArch64::SQADDv4i16:
25088 case AArch64::SQADDv4i32:
25089 case AArch64::SQADDv8i8:
25090 case AArch64::SQADDv8i16:
25091 case AArch64::SQADDv16i8:
25092 case AArch64::SQDMULHv1i16:
25093 case AArch64::SQDMULHv1i32:
25094 case AArch64::SQDMULHv2i32:
25095 case AArch64::SQDMULHv4i16:
25096 case AArch64::SQDMULHv4i32:
25097 case AArch64::SQDMULHv8i16:
25098 case AArch64::SQDMULLi16:
25099 case AArch64::SQDMULLi32:
25100 case AArch64::SQDMULLv2i32_v2i64:
25101 case AArch64::SQDMULLv4i16_v4i32:
25102 case AArch64::SQDMULLv4i32_v2i64:
25103 case AArch64::SQDMULLv8i16_v4i32:
25104 case AArch64::SQRDMULHv1i16:
25105 case AArch64::SQRDMULHv1i32:
25106 case AArch64::SQRDMULHv2i32:
25107 case AArch64::SQRDMULHv4i16:
25108 case AArch64::SQRDMULHv4i32:
25109 case AArch64::SQRDMULHv8i16:
25110 case AArch64::SQRSHLv1i8:
25111 case AArch64::SQRSHLv1i16:
25112 case AArch64::SQRSHLv1i32:
25113 case AArch64::SQRSHLv1i64:
25114 case AArch64::SQRSHLv2i32:
25115 case AArch64::SQRSHLv2i64:
25116 case AArch64::SQRSHLv4i16:
25117 case AArch64::SQRSHLv4i32:
25118 case AArch64::SQRSHLv8i8:
25119 case AArch64::SQRSHLv8i16:
25120 case AArch64::SQRSHLv16i8:
25121 case AArch64::SQSHLv1i8:
25122 case AArch64::SQSHLv1i16:
25123 case AArch64::SQSHLv1i32:
25124 case AArch64::SQSHLv1i64:
25125 case AArch64::SQSHLv2i32:
25126 case AArch64::SQSHLv2i64:
25127 case AArch64::SQSHLv4i16:
25128 case AArch64::SQSHLv4i32:
25129 case AArch64::SQSHLv8i8:
25130 case AArch64::SQSHLv8i16:
25131 case AArch64::SQSHLv16i8:
25132 case AArch64::SQSUBv1i8:
25133 case AArch64::SQSUBv1i16:
25134 case AArch64::SQSUBv1i32:
25135 case AArch64::SQSUBv1i64:
25136 case AArch64::SQSUBv2i32:
25137 case AArch64::SQSUBv2i64:
25138 case AArch64::SQSUBv4i16:
25139 case AArch64::SQSUBv4i32:
25140 case AArch64::SQSUBv8i8:
25141 case AArch64::SQSUBv8i16:
25142 case AArch64::SQSUBv16i8:
25143 case AArch64::SRHADDv2i32:
25144 case AArch64::SRHADDv4i16:
25145 case AArch64::SRHADDv4i32:
25146 case AArch64::SRHADDv8i8:
25147 case AArch64::SRHADDv8i16:
25148 case AArch64::SRHADDv16i8:
25149 case AArch64::SRSHLv1i64:
25150 case AArch64::SRSHLv2i32:
25151 case AArch64::SRSHLv2i64:
25152 case AArch64::SRSHLv4i16:
25153 case AArch64::SRSHLv4i32:
25154 case AArch64::SRSHLv8i8:
25155 case AArch64::SRSHLv8i16:
25156 case AArch64::SRSHLv16i8:
25157 case AArch64::SSHLv1i64:
25158 case AArch64::SSHLv2i32:
25159 case AArch64::SSHLv2i64:
25160 case AArch64::SSHLv4i16:
25161 case AArch64::SSHLv4i32:
25162 case AArch64::SSHLv8i8:
25163 case AArch64::SSHLv8i16:
25164 case AArch64::SSHLv16i8:
25165 case AArch64::SSUBLv2i32_v2i64:
25166 case AArch64::SSUBLv4i16_v4i32:
25167 case AArch64::SSUBLv4i32_v2i64:
25168 case AArch64::SSUBLv8i8_v8i16:
25169 case AArch64::SSUBLv8i16_v4i32:
25170 case AArch64::SSUBLv16i8_v8i16:
25171 case AArch64::SSUBWv2i32_v2i64:
25172 case AArch64::SSUBWv4i16_v4i32:
25173 case AArch64::SSUBWv4i32_v2i64:
25174 case AArch64::SSUBWv8i8_v8i16:
25175 case AArch64::SSUBWv8i16_v4i32:
25176 case AArch64::SSUBWv16i8_v8i16:
25177 case AArch64::SUBHNv2i64_v2i32:
25178 case AArch64::SUBHNv4i32_v4i16:
25179 case AArch64::SUBHNv8i16_v8i8:
25180 case AArch64::SUBP:
25181 case AArch64::SUBPS:
25182 case AArch64::SUBv1i64:
25183 case AArch64::SUBv2i32:
25184 case AArch64::SUBv2i64:
25185 case AArch64::SUBv4i16:
25186 case AArch64::SUBv4i32:
25187 case AArch64::SUBv8i8:
25188 case AArch64::SUBv8i16:
25189 case AArch64::SUBv16i8:
25190 case AArch64::TRN1v2i32:
25191 case AArch64::TRN1v2i64:
25192 case AArch64::TRN1v4i16:
25193 case AArch64::TRN1v4i32:
25194 case AArch64::TRN1v8i8:
25195 case AArch64::TRN1v8i16:
25196 case AArch64::TRN1v16i8:
25197 case AArch64::TRN2v2i32:
25198 case AArch64::TRN2v2i64:
25199 case AArch64::TRN2v4i16:
25200 case AArch64::TRN2v4i32:
25201 case AArch64::TRN2v8i8:
25202 case AArch64::TRN2v8i16:
25203 case AArch64::TRN2v16i8:
25204 case AArch64::UABDLv2i32_v2i64:
25205 case AArch64::UABDLv4i16_v4i32:
25206 case AArch64::UABDLv4i32_v2i64:
25207 case AArch64::UABDLv8i8_v8i16:
25208 case AArch64::UABDLv8i16_v4i32:
25209 case AArch64::UABDLv16i8_v8i16:
25210 case AArch64::UABDv2i32:
25211 case AArch64::UABDv4i16:
25212 case AArch64::UABDv4i32:
25213 case AArch64::UABDv8i8:
25214 case AArch64::UABDv8i16:
25215 case AArch64::UABDv16i8:
25216 case AArch64::UADDLv2i32_v2i64:
25217 case AArch64::UADDLv4i16_v4i32:
25218 case AArch64::UADDLv4i32_v2i64:
25219 case AArch64::UADDLv8i8_v8i16:
25220 case AArch64::UADDLv8i16_v4i32:
25221 case AArch64::UADDLv16i8_v8i16:
25222 case AArch64::UADDWv2i32_v2i64:
25223 case AArch64::UADDWv4i16_v4i32:
25224 case AArch64::UADDWv4i32_v2i64:
25225 case AArch64::UADDWv8i8_v8i16:
25226 case AArch64::UADDWv8i16_v4i32:
25227 case AArch64::UADDWv16i8_v8i16:
25228 case AArch64::UDIVWr:
25229 case AArch64::UDIVXr:
25230 case AArch64::UHADDv2i32:
25231 case AArch64::UHADDv4i16:
25232 case AArch64::UHADDv4i32:
25233 case AArch64::UHADDv8i8:
25234 case AArch64::UHADDv8i16:
25235 case AArch64::UHADDv16i8:
25236 case AArch64::UHSUBv2i32:
25237 case AArch64::UHSUBv4i16:
25238 case AArch64::UHSUBv4i32:
25239 case AArch64::UHSUBv8i8:
25240 case AArch64::UHSUBv8i16:
25241 case AArch64::UHSUBv16i8:
25242 case AArch64::UMAXPv2i32:
25243 case AArch64::UMAXPv4i16:
25244 case AArch64::UMAXPv4i32:
25245 case AArch64::UMAXPv8i8:
25246 case AArch64::UMAXPv8i16:
25247 case AArch64::UMAXPv16i8:
25248 case AArch64::UMAXWrr:
25249 case AArch64::UMAXXrr:
25250 case AArch64::UMAXv2i32:
25251 case AArch64::UMAXv4i16:
25252 case AArch64::UMAXv4i32:
25253 case AArch64::UMAXv8i8:
25254 case AArch64::UMAXv8i16:
25255 case AArch64::UMAXv16i8:
25256 case AArch64::UMINPv2i32:
25257 case AArch64::UMINPv4i16:
25258 case AArch64::UMINPv4i32:
25259 case AArch64::UMINPv8i8:
25260 case AArch64::UMINPv8i16:
25261 case AArch64::UMINPv16i8:
25262 case AArch64::UMINWrr:
25263 case AArch64::UMINXrr:
25264 case AArch64::UMINv2i32:
25265 case AArch64::UMINv4i16:
25266 case AArch64::UMINv4i32:
25267 case AArch64::UMINv8i8:
25268 case AArch64::UMINv8i16:
25269 case AArch64::UMINv16i8:
25270 case AArch64::UMULHrr:
25271 case AArch64::UMULLv2i32_v2i64:
25272 case AArch64::UMULLv4i16_v4i32:
25273 case AArch64::UMULLv4i32_v2i64:
25274 case AArch64::UMULLv8i8_v8i16:
25275 case AArch64::UMULLv8i16_v4i32:
25276 case AArch64::UMULLv16i8_v8i16:
25277 case AArch64::UQADDv1i8:
25278 case AArch64::UQADDv1i16:
25279 case AArch64::UQADDv1i32:
25280 case AArch64::UQADDv1i64:
25281 case AArch64::UQADDv2i32:
25282 case AArch64::UQADDv2i64:
25283 case AArch64::UQADDv4i16:
25284 case AArch64::UQADDv4i32:
25285 case AArch64::UQADDv8i8:
25286 case AArch64::UQADDv8i16:
25287 case AArch64::UQADDv16i8:
25288 case AArch64::UQRSHLv1i8:
25289 case AArch64::UQRSHLv1i16:
25290 case AArch64::UQRSHLv1i32:
25291 case AArch64::UQRSHLv1i64:
25292 case AArch64::UQRSHLv2i32:
25293 case AArch64::UQRSHLv2i64:
25294 case AArch64::UQRSHLv4i16:
25295 case AArch64::UQRSHLv4i32:
25296 case AArch64::UQRSHLv8i8:
25297 case AArch64::UQRSHLv8i16:
25298 case AArch64::UQRSHLv16i8:
25299 case AArch64::UQSHLv1i8:
25300 case AArch64::UQSHLv1i16:
25301 case AArch64::UQSHLv1i32:
25302 case AArch64::UQSHLv1i64:
25303 case AArch64::UQSHLv2i32:
25304 case AArch64::UQSHLv2i64:
25305 case AArch64::UQSHLv4i16:
25306 case AArch64::UQSHLv4i32:
25307 case AArch64::UQSHLv8i8:
25308 case AArch64::UQSHLv8i16:
25309 case AArch64::UQSHLv16i8:
25310 case AArch64::UQSUBv1i8:
25311 case AArch64::UQSUBv1i16:
25312 case AArch64::UQSUBv1i32:
25313 case AArch64::UQSUBv1i64:
25314 case AArch64::UQSUBv2i32:
25315 case AArch64::UQSUBv2i64:
25316 case AArch64::UQSUBv4i16:
25317 case AArch64::UQSUBv4i32:
25318 case AArch64::UQSUBv8i8:
25319 case AArch64::UQSUBv8i16:
25320 case AArch64::UQSUBv16i8:
25321 case AArch64::URHADDv2i32:
25322 case AArch64::URHADDv4i16:
25323 case AArch64::URHADDv4i32:
25324 case AArch64::URHADDv8i8:
25325 case AArch64::URHADDv8i16:
25326 case AArch64::URHADDv16i8:
25327 case AArch64::URSHLv1i64:
25328 case AArch64::URSHLv2i32:
25329 case AArch64::URSHLv2i64:
25330 case AArch64::URSHLv4i16:
25331 case AArch64::URSHLv4i32:
25332 case AArch64::URSHLv8i8:
25333 case AArch64::URSHLv8i16:
25334 case AArch64::URSHLv16i8:
25335 case AArch64::USHLv1i64:
25336 case AArch64::USHLv2i32:
25337 case AArch64::USHLv2i64:
25338 case AArch64::USHLv4i16:
25339 case AArch64::USHLv4i32:
25340 case AArch64::USHLv8i8:
25341 case AArch64::USHLv8i16:
25342 case AArch64::USHLv16i8:
25343 case AArch64::USUBLv2i32_v2i64:
25344 case AArch64::USUBLv4i16_v4i32:
25345 case AArch64::USUBLv4i32_v2i64:
25346 case AArch64::USUBLv8i8_v8i16:
25347 case AArch64::USUBLv8i16_v4i32:
25348 case AArch64::USUBLv16i8_v8i16:
25349 case AArch64::USUBWv2i32_v2i64:
25350 case AArch64::USUBWv4i16_v4i32:
25351 case AArch64::USUBWv4i32_v2i64:
25352 case AArch64::USUBWv8i8_v8i16:
25353 case AArch64::USUBWv8i16_v4i32:
25354 case AArch64::USUBWv16i8_v8i16:
25355 case AArch64::UZP1v2i32:
25356 case AArch64::UZP1v2i64:
25357 case AArch64::UZP1v4i16:
25358 case AArch64::UZP1v4i32:
25359 case AArch64::UZP1v8i8:
25360 case AArch64::UZP1v8i16:
25361 case AArch64::UZP1v16i8:
25362 case AArch64::UZP2v2i32:
25363 case AArch64::UZP2v2i64:
25364 case AArch64::UZP2v4i16:
25365 case AArch64::UZP2v4i32:
25366 case AArch64::UZP2v8i8:
25367 case AArch64::UZP2v8i16:
25368 case AArch64::UZP2v16i8:
25369 case AArch64::ZIP1v2i32:
25370 case AArch64::ZIP1v2i64:
25371 case AArch64::ZIP1v4i16:
25372 case AArch64::ZIP1v4i32:
25373 case AArch64::ZIP1v8i8:
25374 case AArch64::ZIP1v8i16:
25375 case AArch64::ZIP1v16i8:
25376 case AArch64::ZIP2v2i32:
25377 case AArch64::ZIP2v2i64:
25378 case AArch64::ZIP2v4i16:
25379 case AArch64::ZIP2v4i32:
25380 case AArch64::ZIP2v8i8:
25381 case AArch64::ZIP2v8i16:
25382 case AArch64::ZIP2v16i8: {
25383 switch (OpNum) {
25384 case 0:
25385 // op: Rd
25386 return 0;
25387 case 1:
25388 // op: Rn
25389 return 5;
25390 case 2:
25391 // op: Rm
25392 return 16;
25393 }
25394 break;
25395 }
25396 case AArch64::DUPv8i8lane:
25397 case AArch64::DUPv16i8lane:
25398 case AArch64::SMOVvi8to32:
25399 case AArch64::SMOVvi8to64:
25400 case AArch64::UMOVvi8: {
25401 switch (OpNum) {
25402 case 0:
25403 // op: Rd
25404 return 0;
25405 case 1:
25406 // op: Rn
25407 return 5;
25408 case 2:
25409 // op: idx
25410 return 17;
25411 }
25412 break;
25413 }
25414 case AArch64::DUPv4i16lane:
25415 case AArch64::DUPv8i16lane:
25416 case AArch64::SMOVvi16to32:
25417 case AArch64::SMOVvi16to64:
25418 case AArch64::UMOVvi16: {
25419 switch (OpNum) {
25420 case 0:
25421 // op: Rd
25422 return 0;
25423 case 1:
25424 // op: Rn
25425 return 5;
25426 case 2:
25427 // op: idx
25428 return 18;
25429 }
25430 break;
25431 }
25432 case AArch64::DUPv2i32lane:
25433 case AArch64::DUPv4i32lane:
25434 case AArch64::SMOVvi32to64:
25435 case AArch64::UMOVvi32: {
25436 switch (OpNum) {
25437 case 0:
25438 // op: Rd
25439 return 0;
25440 case 1:
25441 // op: Rn
25442 return 5;
25443 case 2:
25444 // op: idx
25445 return 19;
25446 }
25447 break;
25448 }
25449 case AArch64::DUPv2i64lane:
25450 case AArch64::UMOVvi64: {
25451 switch (OpNum) {
25452 case 0:
25453 // op: Rd
25454 return 0;
25455 case 1:
25456 // op: Rn
25457 return 5;
25458 case 2:
25459 // op: idx
25460 return 20;
25461 }
25462 break;
25463 }
25464 case AArch64::ADDSWri:
25465 case AArch64::ADDSXri:
25466 case AArch64::ADDWri:
25467 case AArch64::ADDXri:
25468 case AArch64::ANDSWri:
25469 case AArch64::ANDSXri:
25470 case AArch64::ANDWri:
25471 case AArch64::ANDXri:
25472 case AArch64::EORWri:
25473 case AArch64::EORXri:
25474 case AArch64::ORRWri:
25475 case AArch64::ORRXri:
25476 case AArch64::SMAXWri:
25477 case AArch64::SMAXXri:
25478 case AArch64::SMINWri:
25479 case AArch64::SMINXri:
25480 case AArch64::SUBSWri:
25481 case AArch64::SUBSXri:
25482 case AArch64::SUBWri:
25483 case AArch64::SUBXri:
25484 case AArch64::UMAXWri:
25485 case AArch64::UMAXXri:
25486 case AArch64::UMINWri:
25487 case AArch64::UMINXri: {
25488 switch (OpNum) {
25489 case 0:
25490 // op: Rd
25491 return 0;
25492 case 1:
25493 // op: Rn
25494 return 5;
25495 case 2:
25496 // op: imm
25497 return 10;
25498 }
25499 break;
25500 }
25501 case AArch64::FCVTZSd:
25502 case AArch64::FCVTZSh:
25503 case AArch64::FCVTZSs:
25504 case AArch64::FCVTZSv2i32_shift:
25505 case AArch64::FCVTZSv2i64_shift:
25506 case AArch64::FCVTZSv4i16_shift:
25507 case AArch64::FCVTZSv4i32_shift:
25508 case AArch64::FCVTZSv8i16_shift:
25509 case AArch64::FCVTZUd:
25510 case AArch64::FCVTZUh:
25511 case AArch64::FCVTZUs:
25512 case AArch64::FCVTZUv2i32_shift:
25513 case AArch64::FCVTZUv2i64_shift:
25514 case AArch64::FCVTZUv4i16_shift:
25515 case AArch64::FCVTZUv4i32_shift:
25516 case AArch64::FCVTZUv8i16_shift:
25517 case AArch64::RSHRNv2i32_shift:
25518 case AArch64::RSHRNv4i16_shift:
25519 case AArch64::RSHRNv8i8_shift:
25520 case AArch64::SCVTFd:
25521 case AArch64::SCVTFh:
25522 case AArch64::SCVTFs:
25523 case AArch64::SCVTFv2i32_shift:
25524 case AArch64::SCVTFv2i64_shift:
25525 case AArch64::SCVTFv4i16_shift:
25526 case AArch64::SCVTFv4i32_shift:
25527 case AArch64::SCVTFv8i16_shift:
25528 case AArch64::SHLd:
25529 case AArch64::SHLv2i32_shift:
25530 case AArch64::SHLv2i64_shift:
25531 case AArch64::SHLv4i16_shift:
25532 case AArch64::SHLv4i32_shift:
25533 case AArch64::SHLv8i8_shift:
25534 case AArch64::SHLv8i16_shift:
25535 case AArch64::SHLv16i8_shift:
25536 case AArch64::SHRNv2i32_shift:
25537 case AArch64::SHRNv4i16_shift:
25538 case AArch64::SHRNv8i8_shift:
25539 case AArch64::SQRSHRNb:
25540 case AArch64::SQRSHRNh:
25541 case AArch64::SQRSHRNs:
25542 case AArch64::SQRSHRNv2i32_shift:
25543 case AArch64::SQRSHRNv4i16_shift:
25544 case AArch64::SQRSHRNv8i8_shift:
25545 case AArch64::SQRSHRUNb:
25546 case AArch64::SQRSHRUNh:
25547 case AArch64::SQRSHRUNs:
25548 case AArch64::SQRSHRUNv2i32_shift:
25549 case AArch64::SQRSHRUNv4i16_shift:
25550 case AArch64::SQRSHRUNv8i8_shift:
25551 case AArch64::SQSHLUb:
25552 case AArch64::SQSHLUd:
25553 case AArch64::SQSHLUh:
25554 case AArch64::SQSHLUs:
25555 case AArch64::SQSHLUv2i32_shift:
25556 case AArch64::SQSHLUv2i64_shift:
25557 case AArch64::SQSHLUv4i16_shift:
25558 case AArch64::SQSHLUv4i32_shift:
25559 case AArch64::SQSHLUv8i8_shift:
25560 case AArch64::SQSHLUv8i16_shift:
25561 case AArch64::SQSHLUv16i8_shift:
25562 case AArch64::SQSHLb:
25563 case AArch64::SQSHLd:
25564 case AArch64::SQSHLh:
25565 case AArch64::SQSHLs:
25566 case AArch64::SQSHLv2i32_shift:
25567 case AArch64::SQSHLv2i64_shift:
25568 case AArch64::SQSHLv4i16_shift:
25569 case AArch64::SQSHLv4i32_shift:
25570 case AArch64::SQSHLv8i8_shift:
25571 case AArch64::SQSHLv8i16_shift:
25572 case AArch64::SQSHLv16i8_shift:
25573 case AArch64::SQSHRNb:
25574 case AArch64::SQSHRNh:
25575 case AArch64::SQSHRNs:
25576 case AArch64::SQSHRNv2i32_shift:
25577 case AArch64::SQSHRNv4i16_shift:
25578 case AArch64::SQSHRNv8i8_shift:
25579 case AArch64::SQSHRUNb:
25580 case AArch64::SQSHRUNh:
25581 case AArch64::SQSHRUNs:
25582 case AArch64::SQSHRUNv2i32_shift:
25583 case AArch64::SQSHRUNv4i16_shift:
25584 case AArch64::SQSHRUNv8i8_shift:
25585 case AArch64::SRSHRd:
25586 case AArch64::SRSHRv2i32_shift:
25587 case AArch64::SRSHRv2i64_shift:
25588 case AArch64::SRSHRv4i16_shift:
25589 case AArch64::SRSHRv4i32_shift:
25590 case AArch64::SRSHRv8i8_shift:
25591 case AArch64::SRSHRv8i16_shift:
25592 case AArch64::SRSHRv16i8_shift:
25593 case AArch64::SSHLLv2i32_shift:
25594 case AArch64::SSHLLv4i16_shift:
25595 case AArch64::SSHLLv4i32_shift:
25596 case AArch64::SSHLLv8i8_shift:
25597 case AArch64::SSHLLv8i16_shift:
25598 case AArch64::SSHLLv16i8_shift:
25599 case AArch64::SSHRd:
25600 case AArch64::SSHRv2i32_shift:
25601 case AArch64::SSHRv2i64_shift:
25602 case AArch64::SSHRv4i16_shift:
25603 case AArch64::SSHRv4i32_shift:
25604 case AArch64::SSHRv8i8_shift:
25605 case AArch64::SSHRv8i16_shift:
25606 case AArch64::SSHRv16i8_shift:
25607 case AArch64::UCVTFd:
25608 case AArch64::UCVTFh:
25609 case AArch64::UCVTFs:
25610 case AArch64::UCVTFv2i32_shift:
25611 case AArch64::UCVTFv2i64_shift:
25612 case AArch64::UCVTFv4i16_shift:
25613 case AArch64::UCVTFv4i32_shift:
25614 case AArch64::UCVTFv8i16_shift:
25615 case AArch64::UQRSHRNb:
25616 case AArch64::UQRSHRNh:
25617 case AArch64::UQRSHRNs:
25618 case AArch64::UQRSHRNv2i32_shift:
25619 case AArch64::UQRSHRNv4i16_shift:
25620 case AArch64::UQRSHRNv8i8_shift:
25621 case AArch64::UQSHLb:
25622 case AArch64::UQSHLd:
25623 case AArch64::UQSHLh:
25624 case AArch64::UQSHLs:
25625 case AArch64::UQSHLv2i32_shift:
25626 case AArch64::UQSHLv2i64_shift:
25627 case AArch64::UQSHLv4i16_shift:
25628 case AArch64::UQSHLv4i32_shift:
25629 case AArch64::UQSHLv8i8_shift:
25630 case AArch64::UQSHLv8i16_shift:
25631 case AArch64::UQSHLv16i8_shift:
25632 case AArch64::UQSHRNb:
25633 case AArch64::UQSHRNh:
25634 case AArch64::UQSHRNs:
25635 case AArch64::UQSHRNv2i32_shift:
25636 case AArch64::UQSHRNv4i16_shift:
25637 case AArch64::UQSHRNv8i8_shift:
25638 case AArch64::URSHRd:
25639 case AArch64::URSHRv2i32_shift:
25640 case AArch64::URSHRv2i64_shift:
25641 case AArch64::URSHRv4i16_shift:
25642 case AArch64::URSHRv4i32_shift:
25643 case AArch64::URSHRv8i8_shift:
25644 case AArch64::URSHRv8i16_shift:
25645 case AArch64::URSHRv16i8_shift:
25646 case AArch64::USHLLv2i32_shift:
25647 case AArch64::USHLLv4i16_shift:
25648 case AArch64::USHLLv4i32_shift:
25649 case AArch64::USHLLv8i8_shift:
25650 case AArch64::USHLLv8i16_shift:
25651 case AArch64::USHLLv16i8_shift:
25652 case AArch64::USHRd:
25653 case AArch64::USHRv2i32_shift:
25654 case AArch64::USHRv2i64_shift:
25655 case AArch64::USHRv4i16_shift:
25656 case AArch64::USHRv4i32_shift:
25657 case AArch64::USHRv8i8_shift:
25658 case AArch64::USHRv8i16_shift:
25659 case AArch64::USHRv16i8_shift: {
25660 switch (OpNum) {
25661 case 0:
25662 // op: Rd
25663 return 0;
25664 case 1:
25665 // op: Rn
25666 return 5;
25667 case 2:
25668 // op: imm
25669 return 16;
25670 }
25671 break;
25672 }
25673 case AArch64::ADDG:
25674 case AArch64::SUBG: {
25675 switch (OpNum) {
25676 case 0:
25677 // op: Rd
25678 return 0;
25679 case 1:
25680 // op: Rn
25681 return 5;
25682 case 2:
25683 // op: imm6
25684 return 16;
25685 case 3:
25686 // op: imm4
25687 return 10;
25688 }
25689 break;
25690 }
25691 case AArch64::SBFMWri:
25692 case AArch64::SBFMXri:
25693 case AArch64::UBFMWri:
25694 case AArch64::UBFMXri: {
25695 switch (OpNum) {
25696 case 0:
25697 // op: Rd
25698 return 0;
25699 case 1:
25700 // op: Rn
25701 return 5;
25702 case 2:
25703 // op: immr
25704 return 16;
25705 case 3:
25706 // op: imms
25707 return 10;
25708 }
25709 break;
25710 }
25711 case AArch64::FCVTZSSWDri:
25712 case AArch64::FCVTZSSWHri:
25713 case AArch64::FCVTZSSWSri:
25714 case AArch64::FCVTZSSXDri:
25715 case AArch64::FCVTZSSXHri:
25716 case AArch64::FCVTZSSXSri:
25717 case AArch64::FCVTZUSWDri:
25718 case AArch64::FCVTZUSWHri:
25719 case AArch64::FCVTZUSWSri:
25720 case AArch64::FCVTZUSXDri:
25721 case AArch64::FCVTZUSXHri:
25722 case AArch64::FCVTZUSXSri:
25723 case AArch64::SCVTFSWDri:
25724 case AArch64::SCVTFSWHri:
25725 case AArch64::SCVTFSWSri:
25726 case AArch64::SCVTFSXDri:
25727 case AArch64::SCVTFSXHri:
25728 case AArch64::SCVTFSXSri:
25729 case AArch64::UCVTFSWDri:
25730 case AArch64::UCVTFSWHri:
25731 case AArch64::UCVTFSWSri:
25732 case AArch64::UCVTFSXDri:
25733 case AArch64::UCVTFSXHri:
25734 case AArch64::UCVTFSXSri: {
25735 switch (OpNum) {
25736 case 0:
25737 // op: Rd
25738 return 0;
25739 case 1:
25740 // op: Rn
25741 return 5;
25742 case 2:
25743 // op: scale
25744 return 10;
25745 }
25746 break;
25747 }
25748 case AArch64::ABSWr:
25749 case AArch64::ABSXr:
25750 case AArch64::ABSv1i64:
25751 case AArch64::ABSv2i32:
25752 case AArch64::ABSv2i64:
25753 case AArch64::ABSv4i16:
25754 case AArch64::ABSv4i32:
25755 case AArch64::ABSv8i8:
25756 case AArch64::ABSv8i16:
25757 case AArch64::ABSv16i8:
25758 case AArch64::ADDPv2i64p:
25759 case AArch64::ADDVv4i16v:
25760 case AArch64::ADDVv4i32v:
25761 case AArch64::ADDVv8i8v:
25762 case AArch64::ADDVv8i16v:
25763 case AArch64::ADDVv16i8v:
25764 case AArch64::AESIMCrr:
25765 case AArch64::AESMCrr:
25766 case AArch64::BF1CVTL2v8f16:
25767 case AArch64::BF1CVTLv8f16:
25768 case AArch64::BF2CVTL2v8f16:
25769 case AArch64::BF2CVTLv8f16:
25770 case AArch64::BFCVT:
25771 case AArch64::BFCVTN:
25772 case AArch64::CLSWr:
25773 case AArch64::CLSXr:
25774 case AArch64::CLSv2i32:
25775 case AArch64::CLSv4i16:
25776 case AArch64::CLSv4i32:
25777 case AArch64::CLSv8i8:
25778 case AArch64::CLSv8i16:
25779 case AArch64::CLSv16i8:
25780 case AArch64::CLZWr:
25781 case AArch64::CLZXr:
25782 case AArch64::CLZv2i32:
25783 case AArch64::CLZv4i16:
25784 case AArch64::CLZv4i32:
25785 case AArch64::CLZv8i8:
25786 case AArch64::CLZv8i16:
25787 case AArch64::CLZv16i8:
25788 case AArch64::CMEQv1i64rz:
25789 case AArch64::CMEQv2i32rz:
25790 case AArch64::CMEQv2i64rz:
25791 case AArch64::CMEQv4i16rz:
25792 case AArch64::CMEQv4i32rz:
25793 case AArch64::CMEQv8i8rz:
25794 case AArch64::CMEQv8i16rz:
25795 case AArch64::CMEQv16i8rz:
25796 case AArch64::CMGEv1i64rz:
25797 case AArch64::CMGEv2i32rz:
25798 case AArch64::CMGEv2i64rz:
25799 case AArch64::CMGEv4i16rz:
25800 case AArch64::CMGEv4i32rz:
25801 case AArch64::CMGEv8i8rz:
25802 case AArch64::CMGEv8i16rz:
25803 case AArch64::CMGEv16i8rz:
25804 case AArch64::CMGTv1i64rz:
25805 case AArch64::CMGTv2i32rz:
25806 case AArch64::CMGTv2i64rz:
25807 case AArch64::CMGTv4i16rz:
25808 case AArch64::CMGTv4i32rz:
25809 case AArch64::CMGTv8i8rz:
25810 case AArch64::CMGTv8i16rz:
25811 case AArch64::CMGTv16i8rz:
25812 case AArch64::CMLEv1i64rz:
25813 case AArch64::CMLEv2i32rz:
25814 case AArch64::CMLEv2i64rz:
25815 case AArch64::CMLEv4i16rz:
25816 case AArch64::CMLEv4i32rz:
25817 case AArch64::CMLEv8i8rz:
25818 case AArch64::CMLEv8i16rz:
25819 case AArch64::CMLEv16i8rz:
25820 case AArch64::CMLTv1i64rz:
25821 case AArch64::CMLTv2i32rz:
25822 case AArch64::CMLTv2i64rz:
25823 case AArch64::CMLTv4i16rz:
25824 case AArch64::CMLTv4i32rz:
25825 case AArch64::CMLTv8i8rz:
25826 case AArch64::CMLTv8i16rz:
25827 case AArch64::CMLTv16i8rz:
25828 case AArch64::CNTWr:
25829 case AArch64::CNTXr:
25830 case AArch64::CNTv8i8:
25831 case AArch64::CNTv16i8:
25832 case AArch64::CTZWr:
25833 case AArch64::CTZXr:
25834 case AArch64::DUPv2i32gpr:
25835 case AArch64::DUPv2i64gpr:
25836 case AArch64::DUPv4i16gpr:
25837 case AArch64::DUPv4i32gpr:
25838 case AArch64::DUPv8i8gpr:
25839 case AArch64::DUPv8i16gpr:
25840 case AArch64::DUPv16i8gpr:
25841 case AArch64::F1CVTL2v8f16:
25842 case AArch64::F1CVTLv8f16:
25843 case AArch64::F2CVTL2v8f16:
25844 case AArch64::F2CVTLv8f16:
25845 case AArch64::FABSDr:
25846 case AArch64::FABSHr:
25847 case AArch64::FABSSr:
25848 case AArch64::FABSv2f32:
25849 case AArch64::FABSv2f64:
25850 case AArch64::FABSv4f16:
25851 case AArch64::FABSv4f32:
25852 case AArch64::FABSv8f16:
25853 case AArch64::FADDPv2i16p:
25854 case AArch64::FADDPv2i32p:
25855 case AArch64::FADDPv2i64p:
25856 case AArch64::FCMEQv1i16rz:
25857 case AArch64::FCMEQv1i32rz:
25858 case AArch64::FCMEQv1i64rz:
25859 case AArch64::FCMEQv2i32rz:
25860 case AArch64::FCMEQv2i64rz:
25861 case AArch64::FCMEQv4i16rz:
25862 case AArch64::FCMEQv4i32rz:
25863 case AArch64::FCMEQv8i16rz:
25864 case AArch64::FCMGEv1i16rz:
25865 case AArch64::FCMGEv1i32rz:
25866 case AArch64::FCMGEv1i64rz:
25867 case AArch64::FCMGEv2i32rz:
25868 case AArch64::FCMGEv2i64rz:
25869 case AArch64::FCMGEv4i16rz:
25870 case AArch64::FCMGEv4i32rz:
25871 case AArch64::FCMGEv8i16rz:
25872 case AArch64::FCMGTv1i16rz:
25873 case AArch64::FCMGTv1i32rz:
25874 case AArch64::FCMGTv1i64rz:
25875 case AArch64::FCMGTv2i32rz:
25876 case AArch64::FCMGTv2i64rz:
25877 case AArch64::FCMGTv4i16rz:
25878 case AArch64::FCMGTv4i32rz:
25879 case AArch64::FCMGTv8i16rz:
25880 case AArch64::FCMLEv1i16rz:
25881 case AArch64::FCMLEv1i32rz:
25882 case AArch64::FCMLEv1i64rz:
25883 case AArch64::FCMLEv2i32rz:
25884 case AArch64::FCMLEv2i64rz:
25885 case AArch64::FCMLEv4i16rz:
25886 case AArch64::FCMLEv4i32rz:
25887 case AArch64::FCMLEv8i16rz:
25888 case AArch64::FCMLTv1i16rz:
25889 case AArch64::FCMLTv1i32rz:
25890 case AArch64::FCMLTv1i64rz:
25891 case AArch64::FCMLTv2i32rz:
25892 case AArch64::FCMLTv2i64rz:
25893 case AArch64::FCMLTv4i16rz:
25894 case AArch64::FCMLTv4i32rz:
25895 case AArch64::FCMLTv8i16rz:
25896 case AArch64::FCVTASUWDr:
25897 case AArch64::FCVTASUWHr:
25898 case AArch64::FCVTASUWSr:
25899 case AArch64::FCVTASUXDr:
25900 case AArch64::FCVTASUXHr:
25901 case AArch64::FCVTASUXSr:
25902 case AArch64::FCVTASv1f16:
25903 case AArch64::FCVTASv1i32:
25904 case AArch64::FCVTASv1i64:
25905 case AArch64::FCVTASv2f32:
25906 case AArch64::FCVTASv2f64:
25907 case AArch64::FCVTASv4f16:
25908 case AArch64::FCVTASv4f32:
25909 case AArch64::FCVTASv8f16:
25910 case AArch64::FCVTAUUWDr:
25911 case AArch64::FCVTAUUWHr:
25912 case AArch64::FCVTAUUWSr:
25913 case AArch64::FCVTAUUXDr:
25914 case AArch64::FCVTAUUXHr:
25915 case AArch64::FCVTAUUXSr:
25916 case AArch64::FCVTAUv1f16:
25917 case AArch64::FCVTAUv1i32:
25918 case AArch64::FCVTAUv1i64:
25919 case AArch64::FCVTAUv2f32:
25920 case AArch64::FCVTAUv2f64:
25921 case AArch64::FCVTAUv4f16:
25922 case AArch64::FCVTAUv4f32:
25923 case AArch64::FCVTAUv8f16:
25924 case AArch64::FCVTDHr:
25925 case AArch64::FCVTDSr:
25926 case AArch64::FCVTHDr:
25927 case AArch64::FCVTHSr:
25928 case AArch64::FCVTLv2i32:
25929 case AArch64::FCVTLv4i16:
25930 case AArch64::FCVTLv4i32:
25931 case AArch64::FCVTLv8i16:
25932 case AArch64::FCVTMSUWDr:
25933 case AArch64::FCVTMSUWHr:
25934 case AArch64::FCVTMSUWSr:
25935 case AArch64::FCVTMSUXDr:
25936 case AArch64::FCVTMSUXHr:
25937 case AArch64::FCVTMSUXSr:
25938 case AArch64::FCVTMSv1f16:
25939 case AArch64::FCVTMSv1i32:
25940 case AArch64::FCVTMSv1i64:
25941 case AArch64::FCVTMSv2f32:
25942 case AArch64::FCVTMSv2f64:
25943 case AArch64::FCVTMSv4f16:
25944 case AArch64::FCVTMSv4f32:
25945 case AArch64::FCVTMSv8f16:
25946 case AArch64::FCVTMUUWDr:
25947 case AArch64::FCVTMUUWHr:
25948 case AArch64::FCVTMUUWSr:
25949 case AArch64::FCVTMUUXDr:
25950 case AArch64::FCVTMUUXHr:
25951 case AArch64::FCVTMUUXSr:
25952 case AArch64::FCVTMUv1f16:
25953 case AArch64::FCVTMUv1i32:
25954 case AArch64::FCVTMUv1i64:
25955 case AArch64::FCVTMUv2f32:
25956 case AArch64::FCVTMUv2f64:
25957 case AArch64::FCVTMUv4f16:
25958 case AArch64::FCVTMUv4f32:
25959 case AArch64::FCVTMUv8f16:
25960 case AArch64::FCVTNSUWDr:
25961 case AArch64::FCVTNSUWHr:
25962 case AArch64::FCVTNSUWSr:
25963 case AArch64::FCVTNSUXDr:
25964 case AArch64::FCVTNSUXHr:
25965 case AArch64::FCVTNSUXSr:
25966 case AArch64::FCVTNSv1f16:
25967 case AArch64::FCVTNSv1i32:
25968 case AArch64::FCVTNSv1i64:
25969 case AArch64::FCVTNSv2f32:
25970 case AArch64::FCVTNSv2f64:
25971 case AArch64::FCVTNSv4f16:
25972 case AArch64::FCVTNSv4f32:
25973 case AArch64::FCVTNSv8f16:
25974 case AArch64::FCVTNUUWDr:
25975 case AArch64::FCVTNUUWHr:
25976 case AArch64::FCVTNUUWSr:
25977 case AArch64::FCVTNUUXDr:
25978 case AArch64::FCVTNUUXHr:
25979 case AArch64::FCVTNUUXSr:
25980 case AArch64::FCVTNUv1f16:
25981 case AArch64::FCVTNUv1i32:
25982 case AArch64::FCVTNUv1i64:
25983 case AArch64::FCVTNUv2f32:
25984 case AArch64::FCVTNUv2f64:
25985 case AArch64::FCVTNUv4f16:
25986 case AArch64::FCVTNUv4f32:
25987 case AArch64::FCVTNUv8f16:
25988 case AArch64::FCVTNv2i32:
25989 case AArch64::FCVTNv4i16:
25990 case AArch64::FCVTPSUWDr:
25991 case AArch64::FCVTPSUWHr:
25992 case AArch64::FCVTPSUWSr:
25993 case AArch64::FCVTPSUXDr:
25994 case AArch64::FCVTPSUXHr:
25995 case AArch64::FCVTPSUXSr:
25996 case AArch64::FCVTPSv1f16:
25997 case AArch64::FCVTPSv1i32:
25998 case AArch64::FCVTPSv1i64:
25999 case AArch64::FCVTPSv2f32:
26000 case AArch64::FCVTPSv2f64:
26001 case AArch64::FCVTPSv4f16:
26002 case AArch64::FCVTPSv4f32:
26003 case AArch64::FCVTPSv8f16:
26004 case AArch64::FCVTPUUWDr:
26005 case AArch64::FCVTPUUWHr:
26006 case AArch64::FCVTPUUWSr:
26007 case AArch64::FCVTPUUXDr:
26008 case AArch64::FCVTPUUXHr:
26009 case AArch64::FCVTPUUXSr:
26010 case AArch64::FCVTPUv1f16:
26011 case AArch64::FCVTPUv1i32:
26012 case AArch64::FCVTPUv1i64:
26013 case AArch64::FCVTPUv2f32:
26014 case AArch64::FCVTPUv2f64:
26015 case AArch64::FCVTPUv4f16:
26016 case AArch64::FCVTPUv4f32:
26017 case AArch64::FCVTPUv8f16:
26018 case AArch64::FCVTSDr:
26019 case AArch64::FCVTSHr:
26020 case AArch64::FCVTXNv1i64:
26021 case AArch64::FCVTXNv2f32:
26022 case AArch64::FCVTZSUWDr:
26023 case AArch64::FCVTZSUWHr:
26024 case AArch64::FCVTZSUWSr:
26025 case AArch64::FCVTZSUXDr:
26026 case AArch64::FCVTZSUXHr:
26027 case AArch64::FCVTZSUXSr:
26028 case AArch64::FCVTZSv1f16:
26029 case AArch64::FCVTZSv1i32:
26030 case AArch64::FCVTZSv1i64:
26031 case AArch64::FCVTZSv2f32:
26032 case AArch64::FCVTZSv2f64:
26033 case AArch64::FCVTZSv4f16:
26034 case AArch64::FCVTZSv4f32:
26035 case AArch64::FCVTZSv8f16:
26036 case AArch64::FCVTZUUWDr:
26037 case AArch64::FCVTZUUWHr:
26038 case AArch64::FCVTZUUWSr:
26039 case AArch64::FCVTZUUXDr:
26040 case AArch64::FCVTZUUXHr:
26041 case AArch64::FCVTZUUXSr:
26042 case AArch64::FCVTZUv1f16:
26043 case AArch64::FCVTZUv1i32:
26044 case AArch64::FCVTZUv1i64:
26045 case AArch64::FCVTZUv2f32:
26046 case AArch64::FCVTZUv2f64:
26047 case AArch64::FCVTZUv4f16:
26048 case AArch64::FCVTZUv4f32:
26049 case AArch64::FCVTZUv8f16:
26050 case AArch64::FJCVTZS:
26051 case AArch64::FMAXNMPv2i16p:
26052 case AArch64::FMAXNMPv2i32p:
26053 case AArch64::FMAXNMPv2i64p:
26054 case AArch64::FMAXNMVv4i16v:
26055 case AArch64::FMAXNMVv4i32v:
26056 case AArch64::FMAXNMVv8i16v:
26057 case AArch64::FMAXPv2i16p:
26058 case AArch64::FMAXPv2i32p:
26059 case AArch64::FMAXPv2i64p:
26060 case AArch64::FMAXVv4i16v:
26061 case AArch64::FMAXVv4i32v:
26062 case AArch64::FMAXVv8i16v:
26063 case AArch64::FMINNMPv2i16p:
26064 case AArch64::FMINNMPv2i32p:
26065 case AArch64::FMINNMPv2i64p:
26066 case AArch64::FMINNMVv4i16v:
26067 case AArch64::FMINNMVv4i32v:
26068 case AArch64::FMINNMVv8i16v:
26069 case AArch64::FMINPv2i16p:
26070 case AArch64::FMINPv2i32p:
26071 case AArch64::FMINPv2i64p:
26072 case AArch64::FMINVv4i16v:
26073 case AArch64::FMINVv4i32v:
26074 case AArch64::FMINVv8i16v:
26075 case AArch64::FMOVDXHighr:
26076 case AArch64::FMOVDXr:
26077 case AArch64::FMOVDr:
26078 case AArch64::FMOVHWr:
26079 case AArch64::FMOVHXr:
26080 case AArch64::FMOVHr:
26081 case AArch64::FMOVSWr:
26082 case AArch64::FMOVSr:
26083 case AArch64::FMOVWHr:
26084 case AArch64::FMOVWSr:
26085 case AArch64::FMOVXDHighr:
26086 case AArch64::FMOVXDr:
26087 case AArch64::FMOVXHr:
26088 case AArch64::FNEGDr:
26089 case AArch64::FNEGHr:
26090 case AArch64::FNEGSr:
26091 case AArch64::FNEGv2f32:
26092 case AArch64::FNEGv2f64:
26093 case AArch64::FNEGv4f16:
26094 case AArch64::FNEGv4f32:
26095 case AArch64::FNEGv8f16:
26096 case AArch64::FRECPEv1f16:
26097 case AArch64::FRECPEv1i32:
26098 case AArch64::FRECPEv1i64:
26099 case AArch64::FRECPEv2f32:
26100 case AArch64::FRECPEv2f64:
26101 case AArch64::FRECPEv4f16:
26102 case AArch64::FRECPEv4f32:
26103 case AArch64::FRECPEv8f16:
26104 case AArch64::FRECPXv1f16:
26105 case AArch64::FRECPXv1i32:
26106 case AArch64::FRECPXv1i64:
26107 case AArch64::FRINT32XDr:
26108 case AArch64::FRINT32XSr:
26109 case AArch64::FRINT32Xv2f32:
26110 case AArch64::FRINT32Xv2f64:
26111 case AArch64::FRINT32Xv4f32:
26112 case AArch64::FRINT32ZDr:
26113 case AArch64::FRINT32ZSr:
26114 case AArch64::FRINT32Zv2f32:
26115 case AArch64::FRINT32Zv2f64:
26116 case AArch64::FRINT32Zv4f32:
26117 case AArch64::FRINT64XDr:
26118 case AArch64::FRINT64XSr:
26119 case AArch64::FRINT64Xv2f32:
26120 case AArch64::FRINT64Xv2f64:
26121 case AArch64::FRINT64Xv4f32:
26122 case AArch64::FRINT64ZDr:
26123 case AArch64::FRINT64ZSr:
26124 case AArch64::FRINT64Zv2f32:
26125 case AArch64::FRINT64Zv2f64:
26126 case AArch64::FRINT64Zv4f32:
26127 case AArch64::FRINTADr:
26128 case AArch64::FRINTAHr:
26129 case AArch64::FRINTASr:
26130 case AArch64::FRINTAv2f32:
26131 case AArch64::FRINTAv2f64:
26132 case AArch64::FRINTAv4f16:
26133 case AArch64::FRINTAv4f32:
26134 case AArch64::FRINTAv8f16:
26135 case AArch64::FRINTIDr:
26136 case AArch64::FRINTIHr:
26137 case AArch64::FRINTISr:
26138 case AArch64::FRINTIv2f32:
26139 case AArch64::FRINTIv2f64:
26140 case AArch64::FRINTIv4f16:
26141 case AArch64::FRINTIv4f32:
26142 case AArch64::FRINTIv8f16:
26143 case AArch64::FRINTMDr:
26144 case AArch64::FRINTMHr:
26145 case AArch64::FRINTMSr:
26146 case AArch64::FRINTMv2f32:
26147 case AArch64::FRINTMv2f64:
26148 case AArch64::FRINTMv4f16:
26149 case AArch64::FRINTMv4f32:
26150 case AArch64::FRINTMv8f16:
26151 case AArch64::FRINTNDr:
26152 case AArch64::FRINTNHr:
26153 case AArch64::FRINTNSr:
26154 case AArch64::FRINTNv2f32:
26155 case AArch64::FRINTNv2f64:
26156 case AArch64::FRINTNv4f16:
26157 case AArch64::FRINTNv4f32:
26158 case AArch64::FRINTNv8f16:
26159 case AArch64::FRINTPDr:
26160 case AArch64::FRINTPHr:
26161 case AArch64::FRINTPSr:
26162 case AArch64::FRINTPv2f32:
26163 case AArch64::FRINTPv2f64:
26164 case AArch64::FRINTPv4f16:
26165 case AArch64::FRINTPv4f32:
26166 case AArch64::FRINTPv8f16:
26167 case AArch64::FRINTXDr:
26168 case AArch64::FRINTXHr:
26169 case AArch64::FRINTXSr:
26170 case AArch64::FRINTXv2f32:
26171 case AArch64::FRINTXv2f64:
26172 case AArch64::FRINTXv4f16:
26173 case AArch64::FRINTXv4f32:
26174 case AArch64::FRINTXv8f16:
26175 case AArch64::FRINTZDr:
26176 case AArch64::FRINTZHr:
26177 case AArch64::FRINTZSr:
26178 case AArch64::FRINTZv2f32:
26179 case AArch64::FRINTZv2f64:
26180 case AArch64::FRINTZv4f16:
26181 case AArch64::FRINTZv4f32:
26182 case AArch64::FRINTZv8f16:
26183 case AArch64::FRSQRTEv1f16:
26184 case AArch64::FRSQRTEv1i32:
26185 case AArch64::FRSQRTEv1i64:
26186 case AArch64::FRSQRTEv2f32:
26187 case AArch64::FRSQRTEv2f64:
26188 case AArch64::FRSQRTEv4f16:
26189 case AArch64::FRSQRTEv4f32:
26190 case AArch64::FRSQRTEv8f16:
26191 case AArch64::FSQRTDr:
26192 case AArch64::FSQRTHr:
26193 case AArch64::FSQRTSr:
26194 case AArch64::FSQRTv2f32:
26195 case AArch64::FSQRTv2f64:
26196 case AArch64::FSQRTv4f16:
26197 case AArch64::FSQRTv4f32:
26198 case AArch64::FSQRTv8f16:
26199 case AArch64::NEGv1i64:
26200 case AArch64::NEGv2i32:
26201 case AArch64::NEGv2i64:
26202 case AArch64::NEGv4i16:
26203 case AArch64::NEGv4i32:
26204 case AArch64::NEGv8i8:
26205 case AArch64::NEGv8i16:
26206 case AArch64::NEGv16i8:
26207 case AArch64::NOTv8i8:
26208 case AArch64::NOTv16i8:
26209 case AArch64::RBITWr:
26210 case AArch64::RBITXr:
26211 case AArch64::RBITv8i8:
26212 case AArch64::RBITv16i8:
26213 case AArch64::REV16Wr:
26214 case AArch64::REV16Xr:
26215 case AArch64::REV16v8i8:
26216 case AArch64::REV16v16i8:
26217 case AArch64::REV32Xr:
26218 case AArch64::REV32v4i16:
26219 case AArch64::REV32v8i8:
26220 case AArch64::REV32v8i16:
26221 case AArch64::REV32v16i8:
26222 case AArch64::REV64v2i32:
26223 case AArch64::REV64v4i16:
26224 case AArch64::REV64v4i32:
26225 case AArch64::REV64v8i8:
26226 case AArch64::REV64v8i16:
26227 case AArch64::REV64v16i8:
26228 case AArch64::REVWr:
26229 case AArch64::REVXr:
26230 case AArch64::SADDLPv2i32_v1i64:
26231 case AArch64::SADDLPv4i16_v2i32:
26232 case AArch64::SADDLPv4i32_v2i64:
26233 case AArch64::SADDLPv8i8_v4i16:
26234 case AArch64::SADDLPv8i16_v4i32:
26235 case AArch64::SADDLPv16i8_v8i16:
26236 case AArch64::SADDLVv4i16v:
26237 case AArch64::SADDLVv4i32v:
26238 case AArch64::SADDLVv8i8v:
26239 case AArch64::SADDLVv8i16v:
26240 case AArch64::SADDLVv16i8v:
26241 case AArch64::SCVTFUWDri:
26242 case AArch64::SCVTFUWHri:
26243 case AArch64::SCVTFUWSri:
26244 case AArch64::SCVTFUXDri:
26245 case AArch64::SCVTFUXHri:
26246 case AArch64::SCVTFUXSri:
26247 case AArch64::SCVTFv1i16:
26248 case AArch64::SCVTFv1i32:
26249 case AArch64::SCVTFv1i64:
26250 case AArch64::SCVTFv2f32:
26251 case AArch64::SCVTFv2f64:
26252 case AArch64::SCVTFv4f16:
26253 case AArch64::SCVTFv4f32:
26254 case AArch64::SCVTFv8f16:
26255 case AArch64::SHA1Hrr:
26256 case AArch64::SHLLv2i32:
26257 case AArch64::SHLLv4i16:
26258 case AArch64::SHLLv4i32:
26259 case AArch64::SHLLv8i8:
26260 case AArch64::SHLLv8i16:
26261 case AArch64::SHLLv16i8:
26262 case AArch64::SMAXVv4i16v:
26263 case AArch64::SMAXVv4i32v:
26264 case AArch64::SMAXVv8i8v:
26265 case AArch64::SMAXVv8i16v:
26266 case AArch64::SMAXVv16i8v:
26267 case AArch64::SMINVv4i16v:
26268 case AArch64::SMINVv4i32v:
26269 case AArch64::SMINVv8i8v:
26270 case AArch64::SMINVv8i16v:
26271 case AArch64::SMINVv16i8v:
26272 case AArch64::SMOVvi8to32_idx0:
26273 case AArch64::SMOVvi8to64_idx0:
26274 case AArch64::SMOVvi16to32_idx0:
26275 case AArch64::SMOVvi16to64_idx0:
26276 case AArch64::SMOVvi32to64_idx0:
26277 case AArch64::SQABSv1i8:
26278 case AArch64::SQABSv1i16:
26279 case AArch64::SQABSv1i32:
26280 case AArch64::SQABSv1i64:
26281 case AArch64::SQABSv2i32:
26282 case AArch64::SQABSv2i64:
26283 case AArch64::SQABSv4i16:
26284 case AArch64::SQABSv4i32:
26285 case AArch64::SQABSv8i8:
26286 case AArch64::SQABSv8i16:
26287 case AArch64::SQABSv16i8:
26288 case AArch64::SQNEGv1i8:
26289 case AArch64::SQNEGv1i16:
26290 case AArch64::SQNEGv1i32:
26291 case AArch64::SQNEGv1i64:
26292 case AArch64::SQNEGv2i32:
26293 case AArch64::SQNEGv2i64:
26294 case AArch64::SQNEGv4i16:
26295 case AArch64::SQNEGv4i32:
26296 case AArch64::SQNEGv8i8:
26297 case AArch64::SQNEGv8i16:
26298 case AArch64::SQNEGv16i8:
26299 case AArch64::SQXTNv1i8:
26300 case AArch64::SQXTNv1i16:
26301 case AArch64::SQXTNv1i32:
26302 case AArch64::SQXTNv2i32:
26303 case AArch64::SQXTNv4i16:
26304 case AArch64::SQXTNv8i8:
26305 case AArch64::SQXTUNv1i8:
26306 case AArch64::SQXTUNv1i16:
26307 case AArch64::SQXTUNv1i32:
26308 case AArch64::SQXTUNv2i32:
26309 case AArch64::SQXTUNv4i16:
26310 case AArch64::SQXTUNv8i8:
26311 case AArch64::UADDLPv2i32_v1i64:
26312 case AArch64::UADDLPv4i16_v2i32:
26313 case AArch64::UADDLPv4i32_v2i64:
26314 case AArch64::UADDLPv8i8_v4i16:
26315 case AArch64::UADDLPv8i16_v4i32:
26316 case AArch64::UADDLPv16i8_v8i16:
26317 case AArch64::UADDLVv4i16v:
26318 case AArch64::UADDLVv4i32v:
26319 case AArch64::UADDLVv8i8v:
26320 case AArch64::UADDLVv8i16v:
26321 case AArch64::UADDLVv16i8v:
26322 case AArch64::UCVTFUWDri:
26323 case AArch64::UCVTFUWHri:
26324 case AArch64::UCVTFUWSri:
26325 case AArch64::UCVTFUXDri:
26326 case AArch64::UCVTFUXHri:
26327 case AArch64::UCVTFUXSri:
26328 case AArch64::UCVTFv1i16:
26329 case AArch64::UCVTFv1i32:
26330 case AArch64::UCVTFv1i64:
26331 case AArch64::UCVTFv2f32:
26332 case AArch64::UCVTFv2f64:
26333 case AArch64::UCVTFv4f16:
26334 case AArch64::UCVTFv4f32:
26335 case AArch64::UCVTFv8f16:
26336 case AArch64::UMAXVv4i16v:
26337 case AArch64::UMAXVv4i32v:
26338 case AArch64::UMAXVv8i8v:
26339 case AArch64::UMAXVv8i16v:
26340 case AArch64::UMAXVv16i8v:
26341 case AArch64::UMINVv4i16v:
26342 case AArch64::UMINVv4i32v:
26343 case AArch64::UMINVv8i8v:
26344 case AArch64::UMINVv8i16v:
26345 case AArch64::UMINVv16i8v:
26346 case AArch64::UMOVvi8_idx0:
26347 case AArch64::UMOVvi16_idx0:
26348 case AArch64::UMOVvi32_idx0:
26349 case AArch64::UMOVvi64_idx0:
26350 case AArch64::UQXTNv1i8:
26351 case AArch64::UQXTNv1i16:
26352 case AArch64::UQXTNv1i32:
26353 case AArch64::UQXTNv2i32:
26354 case AArch64::UQXTNv4i16:
26355 case AArch64::UQXTNv8i8:
26356 case AArch64::URECPEv2i32:
26357 case AArch64::URECPEv4i32:
26358 case AArch64::URSQRTEv2i32:
26359 case AArch64::URSQRTEv4i32:
26360 case AArch64::XTNv2i32:
26361 case AArch64::XTNv4i16:
26362 case AArch64::XTNv8i8: {
26363 switch (OpNum) {
26364 case 0:
26365 // op: Rd
26366 return 0;
26367 case 1:
26368 // op: Rn
26369 return 5;
26370 }
26371 break;
26372 }
26373 case AArch64::FMOVDi:
26374 case AArch64::FMOVHi:
26375 case AArch64::FMOVSi: {
26376 switch (OpNum) {
26377 case 0:
26378 // op: Rd
26379 return 0;
26380 case 1:
26381 // op: imm
26382 return 13;
26383 }
26384 break;
26385 }
26386 case AArch64::MOVNWi:
26387 case AArch64::MOVNXi:
26388 case AArch64::MOVZWi:
26389 case AArch64::MOVZXi: {
26390 switch (OpNum) {
26391 case 0:
26392 // op: Rd
26393 return 0;
26394 case 1:
26395 // op: imm
26396 return 5;
26397 case 2:
26398 // op: shift
26399 return 21;
26400 }
26401 break;
26402 }
26403 case AArch64::RDSVLI_XI:
26404 case AArch64::RDVLI_XI: {
26405 switch (OpNum) {
26406 case 0:
26407 // op: Rd
26408 return 0;
26409 case 1:
26410 // op: imm6
26411 return 5;
26412 }
26413 break;
26414 }
26415 case AArch64::MOVIv2s_msl:
26416 case AArch64::MOVIv4s_msl:
26417 case AArch64::MVNIv2s_msl:
26418 case AArch64::MVNIv4s_msl: {
26419 switch (OpNum) {
26420 case 0:
26421 // op: Rd
26422 return 0;
26423 case 1:
26424 // op: imm8
26425 return 5;
26426 case 2:
26427 // op: shift
26428 return 12;
26429 }
26430 break;
26431 }
26432 case AArch64::MOVIv2i32:
26433 case AArch64::MOVIv4i16:
26434 case AArch64::MOVIv4i32:
26435 case AArch64::MOVIv8i16:
26436 case AArch64::MVNIv2i32:
26437 case AArch64::MVNIv4i16:
26438 case AArch64::MVNIv4i32:
26439 case AArch64::MVNIv8i16: {
26440 switch (OpNum) {
26441 case 0:
26442 // op: Rd
26443 return 0;
26444 case 1:
26445 // op: imm8
26446 return 5;
26447 case 2:
26448 // op: shift
26449 return 13;
26450 }
26451 break;
26452 }
26453 case AArch64::FMOVv2f32_ns:
26454 case AArch64::FMOVv2f64_ns:
26455 case AArch64::FMOVv4f16_ns:
26456 case AArch64::FMOVv4f32_ns:
26457 case AArch64::FMOVv8f16_ns:
26458 case AArch64::MOVID:
26459 case AArch64::MOVIv2d_ns:
26460 case AArch64::MOVIv8b_ns:
26461 case AArch64::MOVIv16b_ns: {
26462 switch (OpNum) {
26463 case 0:
26464 // op: Rd
26465 return 0;
26466 case 1:
26467 // op: imm8
26468 return 5;
26469 }
26470 break;
26471 }
26472 case AArch64::BFMWri:
26473 case AArch64::BFMXri: {
26474 switch (OpNum) {
26475 case 0:
26476 // op: Rd
26477 return 0;
26478 case 2:
26479 // op: Rn
26480 return 5;
26481 case 3:
26482 // op: immr
26483 return 16;
26484 case 4:
26485 // op: imms
26486 return 10;
26487 }
26488 break;
26489 }
26490 case AArch64::MOVKWi:
26491 case AArch64::MOVKXi: {
26492 switch (OpNum) {
26493 case 0:
26494 // op: Rd
26495 return 0;
26496 case 2:
26497 // op: imm
26498 return 5;
26499 case 3:
26500 // op: shift
26501 return 21;
26502 }
26503 break;
26504 }
26505 case AArch64::CNTB_XPiI:
26506 case AArch64::CNTD_XPiI:
26507 case AArch64::CNTH_XPiI:
26508 case AArch64::CNTW_XPiI: {
26509 switch (OpNum) {
26510 case 0:
26511 // op: Rd
26512 return 0;
26513 case 2:
26514 // op: imm4
26515 return 16;
26516 case 1:
26517 // op: pattern
26518 return 5;
26519 }
26520 break;
26521 }
26522 case AArch64::XPACD:
26523 case AArch64::XPACI: {
26524 switch (OpNum) {
26525 case 0:
26526 // op: Rd
26527 return 0;
26528 }
26529 break;
26530 }
26531 case AArch64::DECP_XP_B:
26532 case AArch64::DECP_XP_D:
26533 case AArch64::DECP_XP_H:
26534 case AArch64::DECP_XP_S:
26535 case AArch64::INCP_XP_B:
26536 case AArch64::INCP_XP_D:
26537 case AArch64::INCP_XP_H:
26538 case AArch64::INCP_XP_S:
26539 case AArch64::SQDECP_XPWd_B:
26540 case AArch64::SQDECP_XPWd_D:
26541 case AArch64::SQDECP_XPWd_H:
26542 case AArch64::SQDECP_XPWd_S:
26543 case AArch64::SQDECP_XP_B:
26544 case AArch64::SQDECP_XP_D:
26545 case AArch64::SQDECP_XP_H:
26546 case AArch64::SQDECP_XP_S:
26547 case AArch64::SQINCP_XPWd_B:
26548 case AArch64::SQINCP_XPWd_D:
26549 case AArch64::SQINCP_XPWd_H:
26550 case AArch64::SQINCP_XPWd_S:
26551 case AArch64::SQINCP_XP_B:
26552 case AArch64::SQINCP_XP_D:
26553 case AArch64::SQINCP_XP_H:
26554 case AArch64::SQINCP_XP_S:
26555 case AArch64::UQDECP_WP_B:
26556 case AArch64::UQDECP_WP_D:
26557 case AArch64::UQDECP_WP_H:
26558 case AArch64::UQDECP_WP_S:
26559 case AArch64::UQDECP_XP_B:
26560 case AArch64::UQDECP_XP_D:
26561 case AArch64::UQDECP_XP_H:
26562 case AArch64::UQDECP_XP_S:
26563 case AArch64::UQINCP_WP_B:
26564 case AArch64::UQINCP_WP_D:
26565 case AArch64::UQINCP_WP_H:
26566 case AArch64::UQINCP_WP_S:
26567 case AArch64::UQINCP_XP_B:
26568 case AArch64::UQINCP_XP_D:
26569 case AArch64::UQINCP_XP_H:
26570 case AArch64::UQINCP_XP_S: {
26571 switch (OpNum) {
26572 case 0:
26573 // op: Rdn
26574 return 0;
26575 case 1:
26576 // op: Pg
26577 return 5;
26578 }
26579 break;
26580 }
26581 case AArch64::DECB_XPiI:
26582 case AArch64::DECD_XPiI:
26583 case AArch64::DECH_XPiI:
26584 case AArch64::DECW_XPiI:
26585 case AArch64::INCB_XPiI:
26586 case AArch64::INCD_XPiI:
26587 case AArch64::INCH_XPiI:
26588 case AArch64::INCW_XPiI:
26589 case AArch64::SQDECB_XPiI:
26590 case AArch64::SQDECB_XPiWdI:
26591 case AArch64::SQDECD_XPiI:
26592 case AArch64::SQDECD_XPiWdI:
26593 case AArch64::SQDECH_XPiI:
26594 case AArch64::SQDECH_XPiWdI:
26595 case AArch64::SQDECW_XPiI:
26596 case AArch64::SQDECW_XPiWdI:
26597 case AArch64::SQINCB_XPiI:
26598 case AArch64::SQINCB_XPiWdI:
26599 case AArch64::SQINCD_XPiI:
26600 case AArch64::SQINCD_XPiWdI:
26601 case AArch64::SQINCH_XPiI:
26602 case AArch64::SQINCH_XPiWdI:
26603 case AArch64::SQINCW_XPiI:
26604 case AArch64::SQINCW_XPiWdI:
26605 case AArch64::UQDECB_WPiI:
26606 case AArch64::UQDECB_XPiI:
26607 case AArch64::UQDECD_WPiI:
26608 case AArch64::UQDECD_XPiI:
26609 case AArch64::UQDECH_WPiI:
26610 case AArch64::UQDECH_XPiI:
26611 case AArch64::UQDECW_WPiI:
26612 case AArch64::UQDECW_XPiI:
26613 case AArch64::UQINCB_WPiI:
26614 case AArch64::UQINCB_XPiI:
26615 case AArch64::UQINCD_WPiI:
26616 case AArch64::UQINCD_XPiI:
26617 case AArch64::UQINCH_WPiI:
26618 case AArch64::UQINCH_XPiI:
26619 case AArch64::UQINCW_WPiI:
26620 case AArch64::UQINCW_XPiI: {
26621 switch (OpNum) {
26622 case 0:
26623 // op: Rdn
26624 return 0;
26625 case 2:
26626 // op: pattern
26627 return 5;
26628 case 3:
26629 // op: imm4
26630 return 16;
26631 }
26632 break;
26633 }
26634 case AArch64::RETAASPPCr:
26635 case AArch64::RETABSPPCr: {
26636 switch (OpNum) {
26637 case 0:
26638 // op: Rm
26639 return 0;
26640 }
26641 break;
26642 }
26643 case AArch64::BLRAA:
26644 case AArch64::BLRAB:
26645 case AArch64::BRAA:
26646 case AArch64::BRAB: {
26647 switch (OpNum) {
26648 case 0:
26649 // op: Rn
26650 return 5;
26651 case 1:
26652 // op: Rm
26653 return 0;
26654 }
26655 break;
26656 }
26657 case AArch64::CCMNWr:
26658 case AArch64::CCMNXr:
26659 case AArch64::CCMPWr:
26660 case AArch64::CCMPXr:
26661 case AArch64::FCCMPDrr:
26662 case AArch64::FCCMPEDrr:
26663 case AArch64::FCCMPEHrr:
26664 case AArch64::FCCMPESrr:
26665 case AArch64::FCCMPHrr:
26666 case AArch64::FCCMPSrr: {
26667 switch (OpNum) {
26668 case 0:
26669 // op: Rn
26670 return 5;
26671 case 1:
26672 // op: Rm
26673 return 16;
26674 case 2:
26675 // op: nzcv
26676 return 0;
26677 case 3:
26678 // op: cond
26679 return 12;
26680 }
26681 break;
26682 }
26683 case AArch64::RMIF: {
26684 switch (OpNum) {
26685 case 0:
26686 // op: Rn
26687 return 5;
26688 case 1:
26689 // op: imm
26690 return 15;
26691 case 2:
26692 // op: mask
26693 return 0;
26694 }
26695 break;
26696 }
26697 case AArch64::CCMNWi:
26698 case AArch64::CCMNXi:
26699 case AArch64::CCMPWi:
26700 case AArch64::CCMPXi: {
26701 switch (OpNum) {
26702 case 0:
26703 // op: Rn
26704 return 5;
26705 case 1:
26706 // op: imm
26707 return 16;
26708 case 2:
26709 // op: nzcv
26710 return 0;
26711 case 3:
26712 // op: cond
26713 return 12;
26714 }
26715 break;
26716 }
26717 case AArch64::AUTIASPPCr:
26718 case AArch64::AUTIBSPPCr:
26719 case AArch64::BLR:
26720 case AArch64::BLRAAZ:
26721 case AArch64::BLRABZ:
26722 case AArch64::BR:
26723 case AArch64::BRAAZ:
26724 case AArch64::BRABZ:
26725 case AArch64::FCMPDri:
26726 case AArch64::FCMPEDri:
26727 case AArch64::FCMPEHri:
26728 case AArch64::FCMPESri:
26729 case AArch64::FCMPHri:
26730 case AArch64::FCMPSri:
26731 case AArch64::RET:
26732 case AArch64::SETF8:
26733 case AArch64::SETF16: {
26734 switch (OpNum) {
26735 case 0:
26736 // op: Rn
26737 return 5;
26738 }
26739 break;
26740 }
26741 case AArch64::LDRBBroW:
26742 case AArch64::LDRBBroX:
26743 case AArch64::LDRBroW:
26744 case AArch64::LDRBroX:
26745 case AArch64::LDRDroW:
26746 case AArch64::LDRDroX:
26747 case AArch64::LDRHHroW:
26748 case AArch64::LDRHHroX:
26749 case AArch64::LDRHroW:
26750 case AArch64::LDRHroX:
26751 case AArch64::LDRQroW:
26752 case AArch64::LDRQroX:
26753 case AArch64::LDRSBWroW:
26754 case AArch64::LDRSBWroX:
26755 case AArch64::LDRSBXroW:
26756 case AArch64::LDRSBXroX:
26757 case AArch64::LDRSHWroW:
26758 case AArch64::LDRSHWroX:
26759 case AArch64::LDRSHXroW:
26760 case AArch64::LDRSHXroX:
26761 case AArch64::LDRSWroW:
26762 case AArch64::LDRSWroX:
26763 case AArch64::LDRSroW:
26764 case AArch64::LDRSroX:
26765 case AArch64::LDRWroW:
26766 case AArch64::LDRWroX:
26767 case AArch64::LDRXroW:
26768 case AArch64::LDRXroX:
26769 case AArch64::PRFMroW:
26770 case AArch64::PRFMroX:
26771 case AArch64::STRBBroW:
26772 case AArch64::STRBBroX:
26773 case AArch64::STRBroW:
26774 case AArch64::STRBroX:
26775 case AArch64::STRDroW:
26776 case AArch64::STRDroX:
26777 case AArch64::STRHHroW:
26778 case AArch64::STRHHroX:
26779 case AArch64::STRHroW:
26780 case AArch64::STRHroX:
26781 case AArch64::STRQroW:
26782 case AArch64::STRQroX:
26783 case AArch64::STRSroW:
26784 case AArch64::STRSroX:
26785 case AArch64::STRWroW:
26786 case AArch64::STRWroX:
26787 case AArch64::STRXroW:
26788 case AArch64::STRXroX: {
26789 switch (OpNum) {
26790 case 0:
26791 // op: Rt
26792 return 0;
26793 case 1:
26794 // op: Rn
26795 return 5;
26796 case 2:
26797 // op: Rm
26798 return 16;
26799 case 3:
26800 // op: extend
26801 return 12;
26802 }
26803 break;
26804 }
26805 case AArch64::LDRBBui:
26806 case AArch64::LDRBui:
26807 case AArch64::LDRDui:
26808 case AArch64::LDRHHui:
26809 case AArch64::LDRHui:
26810 case AArch64::LDRQui:
26811 case AArch64::LDRSBWui:
26812 case AArch64::LDRSBXui:
26813 case AArch64::LDRSHWui:
26814 case AArch64::LDRSHXui:
26815 case AArch64::LDRSWui:
26816 case AArch64::LDRSui:
26817 case AArch64::LDRWui:
26818 case AArch64::LDRXui:
26819 case AArch64::PRFMui:
26820 case AArch64::STRBBui:
26821 case AArch64::STRBui:
26822 case AArch64::STRDui:
26823 case AArch64::STRHHui:
26824 case AArch64::STRHui:
26825 case AArch64::STRQui:
26826 case AArch64::STRSui:
26827 case AArch64::STRWui:
26828 case AArch64::STRXui: {
26829 switch (OpNum) {
26830 case 0:
26831 // op: Rt
26832 return 0;
26833 case 1:
26834 // op: Rn
26835 return 5;
26836 case 2:
26837 // op: offset
26838 return 10;
26839 }
26840 break;
26841 }
26842 case AArch64::LDAPURBi:
26843 case AArch64::LDAPURHi:
26844 case AArch64::LDAPURSBWi:
26845 case AArch64::LDAPURSBXi:
26846 case AArch64::LDAPURSHWi:
26847 case AArch64::LDAPURSHXi:
26848 case AArch64::LDAPURSWi:
26849 case AArch64::LDAPURXi:
26850 case AArch64::LDAPURi:
26851 case AArch64::LDTRBi:
26852 case AArch64::LDTRHi:
26853 case AArch64::LDTRSBWi:
26854 case AArch64::LDTRSBXi:
26855 case AArch64::LDTRSHWi:
26856 case AArch64::LDTRSHXi:
26857 case AArch64::LDTRSWi:
26858 case AArch64::LDTRWi:
26859 case AArch64::LDTRXi:
26860 case AArch64::LDURBBi:
26861 case AArch64::LDURBi:
26862 case AArch64::LDURDi:
26863 case AArch64::LDURHHi:
26864 case AArch64::LDURHi:
26865 case AArch64::LDURQi:
26866 case AArch64::LDURSBWi:
26867 case AArch64::LDURSBXi:
26868 case AArch64::LDURSHWi:
26869 case AArch64::LDURSHXi:
26870 case AArch64::LDURSWi:
26871 case AArch64::LDURSi:
26872 case AArch64::LDURWi:
26873 case AArch64::LDURXi:
26874 case AArch64::PRFUMi:
26875 case AArch64::STLURBi:
26876 case AArch64::STLURHi:
26877 case AArch64::STLURWi:
26878 case AArch64::STLURXi:
26879 case AArch64::STTRBi:
26880 case AArch64::STTRHi:
26881 case AArch64::STTRWi:
26882 case AArch64::STTRXi:
26883 case AArch64::STURBBi:
26884 case AArch64::STURBi:
26885 case AArch64::STURDi:
26886 case AArch64::STURHHi:
26887 case AArch64::STURHi:
26888 case AArch64::STURQi:
26889 case AArch64::STURSi:
26890 case AArch64::STURWi:
26891 case AArch64::STURXi: {
26892 switch (OpNum) {
26893 case 0:
26894 // op: Rt
26895 return 0;
26896 case 1:
26897 // op: Rn
26898 return 5;
26899 case 2:
26900 // op: offset
26901 return 12;
26902 }
26903 break;
26904 }
26905 case AArch64::LDAPURbi:
26906 case AArch64::LDAPURdi:
26907 case AArch64::LDAPURhi:
26908 case AArch64::LDAPURqi:
26909 case AArch64::LDAPURsi:
26910 case AArch64::STLURbi:
26911 case AArch64::STLURdi:
26912 case AArch64::STLURhi:
26913 case AArch64::STLURqi:
26914 case AArch64::STLURsi: {
26915 switch (OpNum) {
26916 case 0:
26917 // op: Rt
26918 return 0;
26919 case 1:
26920 // op: Rn
26921 return 5;
26922 case 2:
26923 // op: simm
26924 return 12;
26925 }
26926 break;
26927 }
26928 case AArch64::GCSSTR:
26929 case AArch64::GCSSTTR:
26930 case AArch64::LD64B:
26931 case AArch64::LDARB:
26932 case AArch64::LDARH:
26933 case AArch64::LDARW:
26934 case AArch64::LDARX:
26935 case AArch64::LDAXRB:
26936 case AArch64::LDAXRH:
26937 case AArch64::LDAXRW:
26938 case AArch64::LDAXRX:
26939 case AArch64::LDLARB:
26940 case AArch64::LDLARH:
26941 case AArch64::LDLARW:
26942 case AArch64::LDLARX:
26943 case AArch64::LDXRB:
26944 case AArch64::LDXRH:
26945 case AArch64::LDXRW:
26946 case AArch64::LDXRX:
26947 case AArch64::ST64B:
26948 case AArch64::STLLRB:
26949 case AArch64::STLLRH:
26950 case AArch64::STLLRW:
26951 case AArch64::STLLRX:
26952 case AArch64::STLRB:
26953 case AArch64::STLRH:
26954 case AArch64::STLRW:
26955 case AArch64::STLRX: {
26956 switch (OpNum) {
26957 case 0:
26958 // op: Rt
26959 return 0;
26960 case 1:
26961 // op: Rn
26962 return 5;
26963 }
26964 break;
26965 }
26966 case AArch64::LDNPDi:
26967 case AArch64::LDNPQi:
26968 case AArch64::LDNPSi:
26969 case AArch64::LDNPWi:
26970 case AArch64::LDNPXi:
26971 case AArch64::LDPDi:
26972 case AArch64::LDPQi:
26973 case AArch64::LDPSWi:
26974 case AArch64::LDPSi:
26975 case AArch64::LDPWi:
26976 case AArch64::LDPXi:
26977 case AArch64::STGPi:
26978 case AArch64::STNPDi:
26979 case AArch64::STNPQi:
26980 case AArch64::STNPSi:
26981 case AArch64::STNPWi:
26982 case AArch64::STNPXi:
26983 case AArch64::STPDi:
26984 case AArch64::STPQi:
26985 case AArch64::STPSi:
26986 case AArch64::STPWi:
26987 case AArch64::STPXi: {
26988 switch (OpNum) {
26989 case 0:
26990 // op: Rt
26991 return 0;
26992 case 1:
26993 // op: Rt2
26994 return 10;
26995 case 2:
26996 // op: Rn
26997 return 5;
26998 case 3:
26999 // op: offset
27000 return 15;
27001 }
27002 break;
27003 }
27004 case AArch64::LDAXPW:
27005 case AArch64::LDAXPX:
27006 case AArch64::LDXPW:
27007 case AArch64::LDXPX: {
27008 switch (OpNum) {
27009 case 0:
27010 // op: Rt
27011 return 0;
27012 case 1:
27013 // op: Rt2
27014 return 10;
27015 case 2:
27016 // op: Rn
27017 return 5;
27018 }
27019 break;
27020 }
27021 case AArch64::TBNZW:
27022 case AArch64::TBNZX:
27023 case AArch64::TBZW:
27024 case AArch64::TBZX: {
27025 switch (OpNum) {
27026 case 0:
27027 // op: Rt
27028 return 0;
27029 case 1:
27030 // op: bit_off
27031 return 19;
27032 case 2:
27033 // op: target
27034 return 5;
27035 }
27036 break;
27037 }
27038 case AArch64::LDRDl:
27039 case AArch64::LDRQl:
27040 case AArch64::LDRSWl:
27041 case AArch64::LDRSl:
27042 case AArch64::LDRWl:
27043 case AArch64::LDRXl:
27044 case AArch64::PRFMl: {
27045 switch (OpNum) {
27046 case 0:
27047 // op: Rt
27048 return 0;
27049 case 1:
27050 // op: label
27051 return 5;
27052 }
27053 break;
27054 }
27055 case AArch64::SYSLxt: {
27056 switch (OpNum) {
27057 case 0:
27058 // op: Rt
27059 return 0;
27060 case 1:
27061 // op: op1
27062 return 16;
27063 case 2:
27064 // op: Cn
27065 return 12;
27066 case 3:
27067 // op: Cm
27068 return 8;
27069 case 4:
27070 // op: op2
27071 return 5;
27072 }
27073 break;
27074 }
27075 case AArch64::MRRS:
27076 case AArch64::MRS: {
27077 switch (OpNum) {
27078 case 0:
27079 // op: Rt
27080 return 0;
27081 case 1:
27082 // op: systemreg
27083 return 5;
27084 }
27085 break;
27086 }
27087 case AArch64::CBNZW:
27088 case AArch64::CBNZX:
27089 case AArch64::CBZW:
27090 case AArch64::CBZX: {
27091 switch (OpNum) {
27092 case 0:
27093 // op: Rt
27094 return 0;
27095 case 1:
27096 // op: target
27097 return 5;
27098 }
27099 break;
27100 }
27101 case AArch64::RPRFM: {
27102 switch (OpNum) {
27103 case 0:
27104 // op: Rt
27105 return 0;
27106 case 2:
27107 // op: Rn
27108 return 5;
27109 case 1:
27110 // op: Rm
27111 return 16;
27112 }
27113 break;
27114 }
27115 case AArch64::LDIAPPW:
27116 case AArch64::LDIAPPX:
27117 case AArch64::STILPW:
27118 case AArch64::STILPX: {
27119 switch (OpNum) {
27120 case 0:
27121 // op: Rt
27122 return 0;
27123 case 2:
27124 // op: Rn
27125 return 5;
27126 case 1:
27127 // op: Rt2
27128 return 16;
27129 }
27130 break;
27131 }
27132 case AArch64::GCSPOPM:
27133 case AArch64::GCSPUSHM:
27134 case AArch64::GCSSS1:
27135 case AArch64::GCSSS2:
27136 case AArch64::TRCIT:
27137 case AArch64::TSTART:
27138 case AArch64::TTEST:
27139 case AArch64::WFET:
27140 case AArch64::WFIT: {
27141 switch (OpNum) {
27142 case 0:
27143 // op: Rt
27144 return 0;
27145 }
27146 break;
27147 }
27148 case AArch64::BCAX:
27149 case AArch64::EOR3:
27150 case AArch64::SM3SS1: {
27151 switch (OpNum) {
27152 case 0:
27153 // op: Vd
27154 return 0;
27155 case 1:
27156 // op: Vn
27157 return 5;
27158 case 2:
27159 // op: Vm
27160 return 16;
27161 case 3:
27162 // op: Va
27163 return 10;
27164 }
27165 break;
27166 }
27167 case AArch64::RAX1:
27168 case AArch64::SM4ENCKEY:
27169 case AArch64::TBLv8i8Four:
27170 case AArch64::TBLv8i8One:
27171 case AArch64::TBLv8i8Three:
27172 case AArch64::TBLv8i8Two:
27173 case AArch64::TBLv16i8Four:
27174 case AArch64::TBLv16i8One:
27175 case AArch64::TBLv16i8Three:
27176 case AArch64::TBLv16i8Two: {
27177 switch (OpNum) {
27178 case 0:
27179 // op: Vd
27180 return 0;
27181 case 1:
27182 // op: Vn
27183 return 5;
27184 case 2:
27185 // op: Vm
27186 return 16;
27187 }
27188 break;
27189 }
27190 case AArch64::XAR: {
27191 switch (OpNum) {
27192 case 0:
27193 // op: Vd
27194 return 0;
27195 case 1:
27196 // op: Vn
27197 return 5;
27198 case 3:
27199 // op: imm
27200 return 10;
27201 case 2:
27202 // op: Vm
27203 return 16;
27204 }
27205 break;
27206 }
27207 case AArch64::ADDQV_VPZ_B:
27208 case AArch64::ADDQV_VPZ_D:
27209 case AArch64::ADDQV_VPZ_H:
27210 case AArch64::ADDQV_VPZ_S:
27211 case AArch64::ANDQV_VPZ_B:
27212 case AArch64::ANDQV_VPZ_D:
27213 case AArch64::ANDQV_VPZ_H:
27214 case AArch64::ANDQV_VPZ_S:
27215 case AArch64::EORQV_VPZ_B:
27216 case AArch64::EORQV_VPZ_D:
27217 case AArch64::EORQV_VPZ_H:
27218 case AArch64::EORQV_VPZ_S:
27219 case AArch64::FADDQV_D:
27220 case AArch64::FADDQV_H:
27221 case AArch64::FADDQV_S:
27222 case AArch64::FMAXNMQV_D:
27223 case AArch64::FMAXNMQV_H:
27224 case AArch64::FMAXNMQV_S:
27225 case AArch64::FMAXQV_D:
27226 case AArch64::FMAXQV_H:
27227 case AArch64::FMAXQV_S:
27228 case AArch64::FMINNMQV_D:
27229 case AArch64::FMINNMQV_H:
27230 case AArch64::FMINNMQV_S:
27231 case AArch64::FMINQV_D:
27232 case AArch64::FMINQV_H:
27233 case AArch64::FMINQV_S:
27234 case AArch64::ORQV_VPZ_B:
27235 case AArch64::ORQV_VPZ_D:
27236 case AArch64::ORQV_VPZ_H:
27237 case AArch64::ORQV_VPZ_S:
27238 case AArch64::SMAXQV_VPZ_B:
27239 case AArch64::SMAXQV_VPZ_D:
27240 case AArch64::SMAXQV_VPZ_H:
27241 case AArch64::SMAXQV_VPZ_S:
27242 case AArch64::SMINQV_VPZ_B:
27243 case AArch64::SMINQV_VPZ_D:
27244 case AArch64::SMINQV_VPZ_H:
27245 case AArch64::SMINQV_VPZ_S:
27246 case AArch64::UMAXQV_VPZ_B:
27247 case AArch64::UMAXQV_VPZ_D:
27248 case AArch64::UMAXQV_VPZ_H:
27249 case AArch64::UMAXQV_VPZ_S:
27250 case AArch64::UMINQV_VPZ_B:
27251 case AArch64::UMINQV_VPZ_D:
27252 case AArch64::UMINQV_VPZ_H:
27253 case AArch64::UMINQV_VPZ_S: {
27254 switch (OpNum) {
27255 case 0:
27256 // op: Vd
27257 return 0;
27258 case 2:
27259 // op: Zn
27260 return 5;
27261 case 1:
27262 // op: Pg
27263 return 10;
27264 }
27265 break;
27266 }
27267 case AArch64::LD1Fourv1d:
27268 case AArch64::LD1Fourv2d:
27269 case AArch64::LD1Fourv2s:
27270 case AArch64::LD1Fourv4h:
27271 case AArch64::LD1Fourv4s:
27272 case AArch64::LD1Fourv8b:
27273 case AArch64::LD1Fourv8h:
27274 case AArch64::LD1Fourv16b:
27275 case AArch64::LD1Onev1d:
27276 case AArch64::LD1Onev2d:
27277 case AArch64::LD1Onev2s:
27278 case AArch64::LD1Onev4h:
27279 case AArch64::LD1Onev4s:
27280 case AArch64::LD1Onev8b:
27281 case AArch64::LD1Onev8h:
27282 case AArch64::LD1Onev16b:
27283 case AArch64::LD1Rv1d:
27284 case AArch64::LD1Rv2d:
27285 case AArch64::LD1Rv2s:
27286 case AArch64::LD1Rv4h:
27287 case AArch64::LD1Rv4s:
27288 case AArch64::LD1Rv8b:
27289 case AArch64::LD1Rv8h:
27290 case AArch64::LD1Rv16b:
27291 case AArch64::LD1Threev1d:
27292 case AArch64::LD1Threev2d:
27293 case AArch64::LD1Threev2s:
27294 case AArch64::LD1Threev4h:
27295 case AArch64::LD1Threev4s:
27296 case AArch64::LD1Threev8b:
27297 case AArch64::LD1Threev8h:
27298 case AArch64::LD1Threev16b:
27299 case AArch64::LD1Twov1d:
27300 case AArch64::LD1Twov2d:
27301 case AArch64::LD1Twov2s:
27302 case AArch64::LD1Twov4h:
27303 case AArch64::LD1Twov4s:
27304 case AArch64::LD1Twov8b:
27305 case AArch64::LD1Twov8h:
27306 case AArch64::LD1Twov16b:
27307 case AArch64::LD2Rv1d:
27308 case AArch64::LD2Rv2d:
27309 case AArch64::LD2Rv2s:
27310 case AArch64::LD2Rv4h:
27311 case AArch64::LD2Rv4s:
27312 case AArch64::LD2Rv8b:
27313 case AArch64::LD2Rv8h:
27314 case AArch64::LD2Rv16b:
27315 case AArch64::LD2Twov2d:
27316 case AArch64::LD2Twov2s:
27317 case AArch64::LD2Twov4h:
27318 case AArch64::LD2Twov4s:
27319 case AArch64::LD2Twov8b:
27320 case AArch64::LD2Twov8h:
27321 case AArch64::LD2Twov16b:
27322 case AArch64::LD3Rv1d:
27323 case AArch64::LD3Rv2d:
27324 case AArch64::LD3Rv2s:
27325 case AArch64::LD3Rv4h:
27326 case AArch64::LD3Rv4s:
27327 case AArch64::LD3Rv8b:
27328 case AArch64::LD3Rv8h:
27329 case AArch64::LD3Rv16b:
27330 case AArch64::LD3Threev2d:
27331 case AArch64::LD3Threev2s:
27332 case AArch64::LD3Threev4h:
27333 case AArch64::LD3Threev4s:
27334 case AArch64::LD3Threev8b:
27335 case AArch64::LD3Threev8h:
27336 case AArch64::LD3Threev16b:
27337 case AArch64::LD4Fourv2d:
27338 case AArch64::LD4Fourv2s:
27339 case AArch64::LD4Fourv4h:
27340 case AArch64::LD4Fourv4s:
27341 case AArch64::LD4Fourv8b:
27342 case AArch64::LD4Fourv8h:
27343 case AArch64::LD4Fourv16b:
27344 case AArch64::LD4Rv1d:
27345 case AArch64::LD4Rv2d:
27346 case AArch64::LD4Rv2s:
27347 case AArch64::LD4Rv4h:
27348 case AArch64::LD4Rv4s:
27349 case AArch64::LD4Rv8b:
27350 case AArch64::LD4Rv8h:
27351 case AArch64::LD4Rv16b:
27352 case AArch64::ST1Fourv1d:
27353 case AArch64::ST1Fourv2d:
27354 case AArch64::ST1Fourv2s:
27355 case AArch64::ST1Fourv4h:
27356 case AArch64::ST1Fourv4s:
27357 case AArch64::ST1Fourv8b:
27358 case AArch64::ST1Fourv8h:
27359 case AArch64::ST1Fourv16b:
27360 case AArch64::ST1Onev1d:
27361 case AArch64::ST1Onev2d:
27362 case AArch64::ST1Onev2s:
27363 case AArch64::ST1Onev4h:
27364 case AArch64::ST1Onev4s:
27365 case AArch64::ST1Onev8b:
27366 case AArch64::ST1Onev8h:
27367 case AArch64::ST1Onev16b:
27368 case AArch64::ST1Threev1d:
27369 case AArch64::ST1Threev2d:
27370 case AArch64::ST1Threev2s:
27371 case AArch64::ST1Threev4h:
27372 case AArch64::ST1Threev4s:
27373 case AArch64::ST1Threev8b:
27374 case AArch64::ST1Threev8h:
27375 case AArch64::ST1Threev16b:
27376 case AArch64::ST1Twov1d:
27377 case AArch64::ST1Twov2d:
27378 case AArch64::ST1Twov2s:
27379 case AArch64::ST1Twov4h:
27380 case AArch64::ST1Twov4s:
27381 case AArch64::ST1Twov8b:
27382 case AArch64::ST1Twov8h:
27383 case AArch64::ST1Twov16b:
27384 case AArch64::ST2Twov2d:
27385 case AArch64::ST2Twov2s:
27386 case AArch64::ST2Twov4h:
27387 case AArch64::ST2Twov4s:
27388 case AArch64::ST2Twov8b:
27389 case AArch64::ST2Twov8h:
27390 case AArch64::ST2Twov16b:
27391 case AArch64::ST3Threev2d:
27392 case AArch64::ST3Threev2s:
27393 case AArch64::ST3Threev4h:
27394 case AArch64::ST3Threev4s:
27395 case AArch64::ST3Threev8b:
27396 case AArch64::ST3Threev8h:
27397 case AArch64::ST3Threev16b:
27398 case AArch64::ST4Fourv2d:
27399 case AArch64::ST4Fourv2s:
27400 case AArch64::ST4Fourv4h:
27401 case AArch64::ST4Fourv4s:
27402 case AArch64::ST4Fourv8b:
27403 case AArch64::ST4Fourv8h:
27404 case AArch64::ST4Fourv16b: {
27405 switch (OpNum) {
27406 case 0:
27407 // op: Vt
27408 return 0;
27409 case 1:
27410 // op: Rn
27411 return 5;
27412 }
27413 break;
27414 }
27415 case AArch64::STL1: {
27416 switch (OpNum) {
27417 case 0:
27418 // op: Vt
27419 return 0;
27420 case 2:
27421 // op: Rn
27422 return 5;
27423 case 1:
27424 // op: Q
27425 return 30;
27426 }
27427 break;
27428 }
27429 case AArch64::ST1i8:
27430 case AArch64::ST2i8:
27431 case AArch64::ST3i8:
27432 case AArch64::ST4i8: {
27433 switch (OpNum) {
27434 case 0:
27435 // op: Vt
27436 return 0;
27437 case 2:
27438 // op: Rn
27439 return 5;
27440 case 1:
27441 // op: idx
27442 return 10;
27443 }
27444 break;
27445 }
27446 case AArch64::ST1i16:
27447 case AArch64::ST2i16:
27448 case AArch64::ST3i16:
27449 case AArch64::ST4i16: {
27450 switch (OpNum) {
27451 case 0:
27452 // op: Vt
27453 return 0;
27454 case 2:
27455 // op: Rn
27456 return 5;
27457 case 1:
27458 // op: idx
27459 return 11;
27460 }
27461 break;
27462 }
27463 case AArch64::ST1i32:
27464 case AArch64::ST2i32:
27465 case AArch64::ST3i32:
27466 case AArch64::ST4i32: {
27467 switch (OpNum) {
27468 case 0:
27469 // op: Vt
27470 return 0;
27471 case 2:
27472 // op: Rn
27473 return 5;
27474 case 1:
27475 // op: idx
27476 return 12;
27477 }
27478 break;
27479 }
27480 case AArch64::ST1i64:
27481 case AArch64::ST2i64:
27482 case AArch64::ST3i64:
27483 case AArch64::ST4i64: {
27484 switch (OpNum) {
27485 case 0:
27486 // op: Vt
27487 return 0;
27488 case 2:
27489 // op: Rn
27490 return 5;
27491 case 1:
27492 // op: idx
27493 return 30;
27494 }
27495 break;
27496 }
27497 case AArch64::STLXRB:
27498 case AArch64::STLXRH:
27499 case AArch64::STLXRW:
27500 case AArch64::STLXRX:
27501 case AArch64::STXRB:
27502 case AArch64::STXRH:
27503 case AArch64::STXRW:
27504 case AArch64::STXRX: {
27505 switch (OpNum) {
27506 case 0:
27507 // op: Ws
27508 return 16;
27509 case 1:
27510 // op: Rt
27511 return 0;
27512 case 2:
27513 // op: Rn
27514 return 5;
27515 }
27516 break;
27517 }
27518 case AArch64::STLXPW:
27519 case AArch64::STLXPX:
27520 case AArch64::STXPW:
27521 case AArch64::STXPX: {
27522 switch (OpNum) {
27523 case 0:
27524 // op: Ws
27525 return 16;
27526 case 1:
27527 // op: Rt
27528 return 0;
27529 case 2:
27530 // op: Rt2
27531 return 10;
27532 case 3:
27533 // op: Rn
27534 return 5;
27535 }
27536 break;
27537 }
27538 case AArch64::ADR:
27539 case AArch64::ADRP: {
27540 switch (OpNum) {
27541 case 0:
27542 // op: Xd
27543 return 0;
27544 case 1:
27545 // op: label
27546 return 5;
27547 }
27548 break;
27549 }
27550 case AArch64::CPY_ZPzI_B:
27551 case AArch64::CPY_ZPzI_D:
27552 case AArch64::CPY_ZPzI_H:
27553 case AArch64::CPY_ZPzI_S: {
27554 switch (OpNum) {
27555 case 0:
27556 // op: Zd
27557 return 0;
27558 case 1:
27559 // op: Pg
27560 return 16;
27561 case 2:
27562 // op: imm
27563 return 5;
27564 }
27565 break;
27566 }
27567 case AArch64::LUTI2_ZZZI_H: {
27568 switch (OpNum) {
27569 case 0:
27570 // op: Zd
27571 return 0;
27572 case 1:
27573 // op: Zn
27574 return 5;
27575 case 2:
27576 // op: Zm
27577 return 16;
27578 case 3:
27579 // op: idx
27580 return 12;
27581 }
27582 break;
27583 }
27584 case AArch64::LUTI2_ZZZI_B:
27585 case AArch64::LUTI4_Z2ZZI_H:
27586 case AArch64::LUTI4_ZZZI_H: {
27587 switch (OpNum) {
27588 case 0:
27589 // op: Zd
27590 return 0;
27591 case 1:
27592 // op: Zn
27593 return 5;
27594 case 2:
27595 // op: Zm
27596 return 16;
27597 case 3:
27598 // op: idx
27599 return 22;
27600 }
27601 break;
27602 }
27603 case AArch64::LUTI4_ZZZI_B: {
27604 switch (OpNum) {
27605 case 0:
27606 // op: Zd
27607 return 0;
27608 case 1:
27609 // op: Zn
27610 return 5;
27611 case 2:
27612 // op: Zm
27613 return 16;
27614 case 3:
27615 // op: idx
27616 return 23;
27617 }
27618 break;
27619 }
27620 case AArch64::SMULLB_ZZZI_D:
27621 case AArch64::SMULLB_ZZZI_S:
27622 case AArch64::SMULLT_ZZZI_D:
27623 case AArch64::SMULLT_ZZZI_S:
27624 case AArch64::SQDMULLB_ZZZI_D:
27625 case AArch64::SQDMULLB_ZZZI_S:
27626 case AArch64::SQDMULLT_ZZZI_D:
27627 case AArch64::SQDMULLT_ZZZI_S:
27628 case AArch64::UMULLB_ZZZI_D:
27629 case AArch64::UMULLB_ZZZI_S:
27630 case AArch64::UMULLT_ZZZI_D:
27631 case AArch64::UMULLT_ZZZI_S: {
27632 switch (OpNum) {
27633 case 0:
27634 // op: Zd
27635 return 0;
27636 case 1:
27637 // op: Zn
27638 return 5;
27639 case 2:
27640 // op: Zm
27641 return 16;
27642 case 3:
27643 // op: iop
27644 return 11;
27645 }
27646 break;
27647 }
27648 case AArch64::BFMUL_ZZZI:
27649 case AArch64::FMUL_ZZZI_H:
27650 case AArch64::FMUL_ZZZI_S:
27651 case AArch64::MUL_ZZZI_H:
27652 case AArch64::MUL_ZZZI_S:
27653 case AArch64::SQDMULH_ZZZI_H:
27654 case AArch64::SQDMULH_ZZZI_S:
27655 case AArch64::SQRDMULH_ZZZI_H:
27656 case AArch64::SQRDMULH_ZZZI_S: {
27657 switch (OpNum) {
27658 case 0:
27659 // op: Zd
27660 return 0;
27661 case 1:
27662 // op: Zn
27663 return 5;
27664 case 2:
27665 // op: Zm
27666 return 16;
27667 case 3:
27668 // op: iop
27669 return 19;
27670 }
27671 break;
27672 }
27673 case AArch64::FMUL_ZZZI_D:
27674 case AArch64::MUL_ZZZI_D:
27675 case AArch64::SQDMULH_ZZZI_D:
27676 case AArch64::SQRDMULH_ZZZI_D: {
27677 switch (OpNum) {
27678 case 0:
27679 // op: Zd
27680 return 0;
27681 case 1:
27682 // op: Zn
27683 return 5;
27684 case 2:
27685 // op: Zm
27686 return 16;
27687 case 3:
27688 // op: iop
27689 return 20;
27690 }
27691 break;
27692 }
27693 case AArch64::ADDHNB_ZZZ_B:
27694 case AArch64::ADDHNB_ZZZ_H:
27695 case AArch64::ADDHNB_ZZZ_S:
27696 case AArch64::ADR_LSL_ZZZ_D_0:
27697 case AArch64::ADR_LSL_ZZZ_D_1:
27698 case AArch64::ADR_LSL_ZZZ_D_2:
27699 case AArch64::ADR_LSL_ZZZ_D_3:
27700 case AArch64::ADR_LSL_ZZZ_S_0:
27701 case AArch64::ADR_LSL_ZZZ_S_1:
27702 case AArch64::ADR_LSL_ZZZ_S_2:
27703 case AArch64::ADR_LSL_ZZZ_S_3:
27704 case AArch64::ADR_SXTW_ZZZ_D_0:
27705 case AArch64::ADR_SXTW_ZZZ_D_1:
27706 case AArch64::ADR_SXTW_ZZZ_D_2:
27707 case AArch64::ADR_SXTW_ZZZ_D_3:
27708 case AArch64::ADR_UXTW_ZZZ_D_0:
27709 case AArch64::ADR_UXTW_ZZZ_D_1:
27710 case AArch64::ADR_UXTW_ZZZ_D_2:
27711 case AArch64::ADR_UXTW_ZZZ_D_3:
27712 case AArch64::BDEP_ZZZ_B:
27713 case AArch64::BDEP_ZZZ_D:
27714 case AArch64::BDEP_ZZZ_H:
27715 case AArch64::BDEP_ZZZ_S:
27716 case AArch64::BEXT_ZZZ_B:
27717 case AArch64::BEXT_ZZZ_D:
27718 case AArch64::BEXT_ZZZ_H:
27719 case AArch64::BEXT_ZZZ_S:
27720 case AArch64::BGRP_ZZZ_B:
27721 case AArch64::BGRP_ZZZ_D:
27722 case AArch64::BGRP_ZZZ_H:
27723 case AArch64::BGRP_ZZZ_S:
27724 case AArch64::HISTSEG_ZZZ:
27725 case AArch64::PMULLB_ZZZ_D:
27726 case AArch64::PMULLB_ZZZ_H:
27727 case AArch64::PMULLB_ZZZ_Q:
27728 case AArch64::PMULLT_ZZZ_D:
27729 case AArch64::PMULLT_ZZZ_H:
27730 case AArch64::PMULLT_ZZZ_Q:
27731 case AArch64::RADDHNB_ZZZ_B:
27732 case AArch64::RADDHNB_ZZZ_H:
27733 case AArch64::RADDHNB_ZZZ_S:
27734 case AArch64::RAX1_ZZZ_D:
27735 case AArch64::RSUBHNB_ZZZ_B:
27736 case AArch64::RSUBHNB_ZZZ_H:
27737 case AArch64::RSUBHNB_ZZZ_S:
27738 case AArch64::SABDLB_ZZZ_D:
27739 case AArch64::SABDLB_ZZZ_H:
27740 case AArch64::SABDLB_ZZZ_S:
27741 case AArch64::SABDLT_ZZZ_D:
27742 case AArch64::SABDLT_ZZZ_H:
27743 case AArch64::SABDLT_ZZZ_S:
27744 case AArch64::SADDLBT_ZZZ_D:
27745 case AArch64::SADDLBT_ZZZ_H:
27746 case AArch64::SADDLBT_ZZZ_S:
27747 case AArch64::SADDLB_ZZZ_D:
27748 case AArch64::SADDLB_ZZZ_H:
27749 case AArch64::SADDLB_ZZZ_S:
27750 case AArch64::SADDLT_ZZZ_D:
27751 case AArch64::SADDLT_ZZZ_H:
27752 case AArch64::SADDLT_ZZZ_S:
27753 case AArch64::SADDWB_ZZZ_D:
27754 case AArch64::SADDWB_ZZZ_H:
27755 case AArch64::SADDWB_ZZZ_S:
27756 case AArch64::SADDWT_ZZZ_D:
27757 case AArch64::SADDWT_ZZZ_H:
27758 case AArch64::SADDWT_ZZZ_S:
27759 case AArch64::SM4EKEY_ZZZ_S:
27760 case AArch64::SMULLB_ZZZ_D:
27761 case AArch64::SMULLB_ZZZ_H:
27762 case AArch64::SMULLB_ZZZ_S:
27763 case AArch64::SMULLT_ZZZ_D:
27764 case AArch64::SMULLT_ZZZ_H:
27765 case AArch64::SMULLT_ZZZ_S:
27766 case AArch64::SQDMULLB_ZZZ_D:
27767 case AArch64::SQDMULLB_ZZZ_H:
27768 case AArch64::SQDMULLB_ZZZ_S:
27769 case AArch64::SQDMULLT_ZZZ_D:
27770 case AArch64::SQDMULLT_ZZZ_H:
27771 case AArch64::SQDMULLT_ZZZ_S:
27772 case AArch64::SSUBLBT_ZZZ_D:
27773 case AArch64::SSUBLBT_ZZZ_H:
27774 case AArch64::SSUBLBT_ZZZ_S:
27775 case AArch64::SSUBLB_ZZZ_D:
27776 case AArch64::SSUBLB_ZZZ_H:
27777 case AArch64::SSUBLB_ZZZ_S:
27778 case AArch64::SSUBLTB_ZZZ_D:
27779 case AArch64::SSUBLTB_ZZZ_H:
27780 case AArch64::SSUBLTB_ZZZ_S:
27781 case AArch64::SSUBLT_ZZZ_D:
27782 case AArch64::SSUBLT_ZZZ_H:
27783 case AArch64::SSUBLT_ZZZ_S:
27784 case AArch64::SSUBWB_ZZZ_D:
27785 case AArch64::SSUBWB_ZZZ_H:
27786 case AArch64::SSUBWB_ZZZ_S:
27787 case AArch64::SSUBWT_ZZZ_D:
27788 case AArch64::SSUBWT_ZZZ_H:
27789 case AArch64::SSUBWT_ZZZ_S:
27790 case AArch64::SUBHNB_ZZZ_B:
27791 case AArch64::SUBHNB_ZZZ_H:
27792 case AArch64::SUBHNB_ZZZ_S:
27793 case AArch64::TBLQ_ZZZ_B:
27794 case AArch64::TBLQ_ZZZ_D:
27795 case AArch64::TBLQ_ZZZ_H:
27796 case AArch64::TBLQ_ZZZ_S:
27797 case AArch64::UABDLB_ZZZ_D:
27798 case AArch64::UABDLB_ZZZ_H:
27799 case AArch64::UABDLB_ZZZ_S:
27800 case AArch64::UABDLT_ZZZ_D:
27801 case AArch64::UABDLT_ZZZ_H:
27802 case AArch64::UABDLT_ZZZ_S:
27803 case AArch64::UADDLB_ZZZ_D:
27804 case AArch64::UADDLB_ZZZ_H:
27805 case AArch64::UADDLB_ZZZ_S:
27806 case AArch64::UADDLT_ZZZ_D:
27807 case AArch64::UADDLT_ZZZ_H:
27808 case AArch64::UADDLT_ZZZ_S:
27809 case AArch64::UADDWB_ZZZ_D:
27810 case AArch64::UADDWB_ZZZ_H:
27811 case AArch64::UADDWB_ZZZ_S:
27812 case AArch64::UADDWT_ZZZ_D:
27813 case AArch64::UADDWT_ZZZ_H:
27814 case AArch64::UADDWT_ZZZ_S:
27815 case AArch64::UMULLB_ZZZ_D:
27816 case AArch64::UMULLB_ZZZ_H:
27817 case AArch64::UMULLB_ZZZ_S:
27818 case AArch64::UMULLT_ZZZ_D:
27819 case AArch64::UMULLT_ZZZ_H:
27820 case AArch64::UMULLT_ZZZ_S:
27821 case AArch64::USUBLB_ZZZ_D:
27822 case AArch64::USUBLB_ZZZ_H:
27823 case AArch64::USUBLB_ZZZ_S:
27824 case AArch64::USUBLT_ZZZ_D:
27825 case AArch64::USUBLT_ZZZ_H:
27826 case AArch64::USUBLT_ZZZ_S:
27827 case AArch64::USUBWB_ZZZ_D:
27828 case AArch64::USUBWB_ZZZ_H:
27829 case AArch64::USUBWB_ZZZ_S:
27830 case AArch64::USUBWT_ZZZ_D:
27831 case AArch64::USUBWT_ZZZ_H:
27832 case AArch64::USUBWT_ZZZ_S:
27833 case AArch64::UZPQ1_ZZZ_B:
27834 case AArch64::UZPQ1_ZZZ_D:
27835 case AArch64::UZPQ1_ZZZ_H:
27836 case AArch64::UZPQ1_ZZZ_S:
27837 case AArch64::UZPQ2_ZZZ_B:
27838 case AArch64::UZPQ2_ZZZ_D:
27839 case AArch64::UZPQ2_ZZZ_H:
27840 case AArch64::UZPQ2_ZZZ_S:
27841 case AArch64::ZIPQ1_ZZZ_B:
27842 case AArch64::ZIPQ1_ZZZ_D:
27843 case AArch64::ZIPQ1_ZZZ_H:
27844 case AArch64::ZIPQ1_ZZZ_S:
27845 case AArch64::ZIPQ2_ZZZ_B:
27846 case AArch64::ZIPQ2_ZZZ_D:
27847 case AArch64::ZIPQ2_ZZZ_H:
27848 case AArch64::ZIPQ2_ZZZ_S: {
27849 switch (OpNum) {
27850 case 0:
27851 // op: Zd
27852 return 0;
27853 case 1:
27854 // op: Zn
27855 return 5;
27856 case 2:
27857 // op: Zm
27858 return 16;
27859 }
27860 break;
27861 }
27862 case AArch64::DUP_ZZI_B: {
27863 switch (OpNum) {
27864 case 0:
27865 // op: Zd
27866 return 0;
27867 case 1:
27868 // op: Zn
27869 return 5;
27870 case 2:
27871 // op: idx
27872 return 17;
27873 }
27874 break;
27875 }
27876 case AArch64::DUP_ZZI_H: {
27877 switch (OpNum) {
27878 case 0:
27879 // op: Zd
27880 return 0;
27881 case 1:
27882 // op: Zn
27883 return 5;
27884 case 2:
27885 // op: idx
27886 return 18;
27887 }
27888 break;
27889 }
27890 case AArch64::DUP_ZZI_S: {
27891 switch (OpNum) {
27892 case 0:
27893 // op: Zd
27894 return 0;
27895 case 1:
27896 // op: Zn
27897 return 5;
27898 case 2:
27899 // op: idx
27900 return 19;
27901 }
27902 break;
27903 }
27904 case AArch64::DUP_ZZI_D: {
27905 switch (OpNum) {
27906 case 0:
27907 // op: Zd
27908 return 0;
27909 case 1:
27910 // op: Zn
27911 return 5;
27912 case 2:
27913 // op: idx
27914 return 20;
27915 }
27916 break;
27917 }
27918 case AArch64::DUP_ZZI_Q: {
27919 switch (OpNum) {
27920 case 0:
27921 // op: Zd
27922 return 0;
27923 case 1:
27924 // op: Zn
27925 return 5;
27926 case 2:
27927 // op: idx
27928 return 22;
27929 }
27930 break;
27931 }
27932 case AArch64::ASR_ZZI_B:
27933 case AArch64::ASR_ZZI_D:
27934 case AArch64::ASR_ZZI_H:
27935 case AArch64::ASR_ZZI_S:
27936 case AArch64::LSL_ZZI_B:
27937 case AArch64::LSL_ZZI_D:
27938 case AArch64::LSL_ZZI_H:
27939 case AArch64::LSL_ZZI_S:
27940 case AArch64::LSR_ZZI_B:
27941 case AArch64::LSR_ZZI_D:
27942 case AArch64::LSR_ZZI_H:
27943 case AArch64::LSR_ZZI_S:
27944 case AArch64::RSHRNB_ZZI_B:
27945 case AArch64::RSHRNB_ZZI_H:
27946 case AArch64::RSHRNB_ZZI_S:
27947 case AArch64::SHRNB_ZZI_B:
27948 case AArch64::SHRNB_ZZI_H:
27949 case AArch64::SHRNB_ZZI_S:
27950 case AArch64::SQRSHRNB_ZZI_B:
27951 case AArch64::SQRSHRNB_ZZI_H:
27952 case AArch64::SQRSHRNB_ZZI_S:
27953 case AArch64::SQRSHRUNB_ZZI_B:
27954 case AArch64::SQRSHRUNB_ZZI_H:
27955 case AArch64::SQRSHRUNB_ZZI_S:
27956 case AArch64::SQSHRNB_ZZI_B:
27957 case AArch64::SQSHRNB_ZZI_H:
27958 case AArch64::SQSHRNB_ZZI_S:
27959 case AArch64::SQSHRUNB_ZZI_B:
27960 case AArch64::SQSHRUNB_ZZI_H:
27961 case AArch64::SQSHRUNB_ZZI_S:
27962 case AArch64::SSHLLB_ZZI_D:
27963 case AArch64::SSHLLB_ZZI_H:
27964 case AArch64::SSHLLB_ZZI_S:
27965 case AArch64::SSHLLT_ZZI_D:
27966 case AArch64::SSHLLT_ZZI_H:
27967 case AArch64::SSHLLT_ZZI_S:
27968 case AArch64::UQRSHRNB_ZZI_B:
27969 case AArch64::UQRSHRNB_ZZI_H:
27970 case AArch64::UQRSHRNB_ZZI_S:
27971 case AArch64::UQSHRNB_ZZI_B:
27972 case AArch64::UQSHRNB_ZZI_H:
27973 case AArch64::UQSHRNB_ZZI_S:
27974 case AArch64::USHLLB_ZZI_D:
27975 case AArch64::USHLLB_ZZI_H:
27976 case AArch64::USHLLB_ZZI_S:
27977 case AArch64::USHLLT_ZZI_D:
27978 case AArch64::USHLLT_ZZI_H:
27979 case AArch64::USHLLT_ZZI_S: {
27980 switch (OpNum) {
27981 case 0:
27982 // op: Zd
27983 return 0;
27984 case 1:
27985 // op: Zn
27986 return 5;
27987 case 2:
27988 // op: imm
27989 return 16;
27990 }
27991 break;
27992 }
27993 case AArch64::EXT_ZZI_B: {
27994 switch (OpNum) {
27995 case 0:
27996 // op: Zd
27997 return 0;
27998 case 1:
27999 // op: Zn
28000 return 5;
28001 case 2:
28002 // op: imm8
28003 return 10;
28004 }
28005 break;
28006 }
28007 case AArch64::DUPQ_ZZI_B: {
28008 switch (OpNum) {
28009 case 0:
28010 // op: Zd
28011 return 0;
28012 case 1:
28013 // op: Zn
28014 return 5;
28015 case 2:
28016 // op: index
28017 return 17;
28018 }
28019 break;
28020 }
28021 case AArch64::DUPQ_ZZI_H: {
28022 switch (OpNum) {
28023 case 0:
28024 // op: Zd
28025 return 0;
28026 case 1:
28027 // op: Zn
28028 return 5;
28029 case 2:
28030 // op: index
28031 return 18;
28032 }
28033 break;
28034 }
28035 case AArch64::DUPQ_ZZI_S: {
28036 switch (OpNum) {
28037 case 0:
28038 // op: Zd
28039 return 0;
28040 case 1:
28041 // op: Zn
28042 return 5;
28043 case 2:
28044 // op: index
28045 return 19;
28046 }
28047 break;
28048 }
28049 case AArch64::DUPQ_ZZI_D: {
28050 switch (OpNum) {
28051 case 0:
28052 // op: Zd
28053 return 0;
28054 case 1:
28055 // op: Zn
28056 return 5;
28057 case 2:
28058 // op: index
28059 return 20;
28060 }
28061 break;
28062 }
28063 case AArch64::BF1CVTLT_ZZ_BtoH:
28064 case AArch64::BF1CVT_ZZ_BtoH:
28065 case AArch64::BF2CVTLT_ZZ_BtoH:
28066 case AArch64::BF2CVT_ZZ_BtoH:
28067 case AArch64::F1CVTLT_ZZ_BtoH:
28068 case AArch64::F1CVT_ZZ_BtoH:
28069 case AArch64::F2CVTLT_ZZ_BtoH:
28070 case AArch64::F2CVT_ZZ_BtoH:
28071 case AArch64::FEXPA_ZZ_D:
28072 case AArch64::FEXPA_ZZ_H:
28073 case AArch64::FEXPA_ZZ_S:
28074 case AArch64::FRECPE_ZZ_D:
28075 case AArch64::FRECPE_ZZ_H:
28076 case AArch64::FRECPE_ZZ_S:
28077 case AArch64::FRSQRTE_ZZ_D:
28078 case AArch64::FRSQRTE_ZZ_H:
28079 case AArch64::FRSQRTE_ZZ_S:
28080 case AArch64::MOVPRFX_ZZ:
28081 case AArch64::REV_ZZ_B:
28082 case AArch64::REV_ZZ_D:
28083 case AArch64::REV_ZZ_H:
28084 case AArch64::REV_ZZ_S:
28085 case AArch64::SQXTNB_ZZ_B:
28086 case AArch64::SQXTNB_ZZ_H:
28087 case AArch64::SQXTNB_ZZ_S:
28088 case AArch64::SQXTUNB_ZZ_B:
28089 case AArch64::SQXTUNB_ZZ_H:
28090 case AArch64::SQXTUNB_ZZ_S:
28091 case AArch64::SUNPKHI_ZZ_D:
28092 case AArch64::SUNPKHI_ZZ_H:
28093 case AArch64::SUNPKHI_ZZ_S:
28094 case AArch64::SUNPKLO_ZZ_D:
28095 case AArch64::SUNPKLO_ZZ_H:
28096 case AArch64::SUNPKLO_ZZ_S:
28097 case AArch64::UQXTNB_ZZ_B:
28098 case AArch64::UQXTNB_ZZ_H:
28099 case AArch64::UQXTNB_ZZ_S:
28100 case AArch64::UUNPKHI_ZZ_D:
28101 case AArch64::UUNPKHI_ZZ_H:
28102 case AArch64::UUNPKHI_ZZ_S:
28103 case AArch64::UUNPKLO_ZZ_D:
28104 case AArch64::UUNPKLO_ZZ_H:
28105 case AArch64::UUNPKLO_ZZ_S: {
28106 switch (OpNum) {
28107 case 0:
28108 // op: Zd
28109 return 0;
28110 case 1:
28111 // op: Zn
28112 return 5;
28113 }
28114 break;
28115 }
28116 case AArch64::SQRSHRN_Z2ZI_StoH:
28117 case AArch64::SQRSHRUN_Z2ZI_StoH:
28118 case AArch64::UQRSHRN_Z2ZI_StoH: {
28119 switch (OpNum) {
28120 case 0:
28121 // op: Zd
28122 return 0;
28123 case 1:
28124 // op: Zn
28125 return 6;
28126 case 2:
28127 // op: imm4
28128 return 16;
28129 }
28130 break;
28131 }
28132 case AArch64::BFCVTN_Z2Z_HtoB:
28133 case AArch64::FCVTNB_Z2Z_StoB:
28134 case AArch64::FCVTNT_Z2Z_StoB:
28135 case AArch64::FCVTN_Z2Z_HtoB:
28136 case AArch64::SQCVTN_Z2Z_StoH:
28137 case AArch64::SQCVTUN_Z2Z_StoH:
28138 case AArch64::UQCVTN_Z2Z_StoH: {
28139 switch (OpNum) {
28140 case 0:
28141 // op: Zd
28142 return 0;
28143 case 1:
28144 // op: Zn
28145 return 6;
28146 }
28147 break;
28148 }
28149 case AArch64::DUP_ZI_B:
28150 case AArch64::DUP_ZI_D:
28151 case AArch64::DUP_ZI_H:
28152 case AArch64::DUP_ZI_S: {
28153 switch (OpNum) {
28154 case 0:
28155 // op: Zd
28156 return 0;
28157 case 1:
28158 // op: imm
28159 return 5;
28160 }
28161 break;
28162 }
28163 case AArch64::INDEX_II_B:
28164 case AArch64::INDEX_II_D:
28165 case AArch64::INDEX_II_H:
28166 case AArch64::INDEX_II_S: {
28167 switch (OpNum) {
28168 case 0:
28169 // op: Zd
28170 return 0;
28171 case 1:
28172 // op: imm5
28173 return 5;
28174 case 2:
28175 // op: imm5b
28176 return 16;
28177 }
28178 break;
28179 }
28180 case AArch64::FDUP_ZI_D:
28181 case AArch64::FDUP_ZI_H:
28182 case AArch64::FDUP_ZI_S: {
28183 switch (OpNum) {
28184 case 0:
28185 // op: Zd
28186 return 0;
28187 case 1:
28188 // op: imm8
28189 return 5;
28190 }
28191 break;
28192 }
28193 case AArch64::DUPM_ZI: {
28194 switch (OpNum) {
28195 case 0:
28196 // op: Zd
28197 return 0;
28198 case 1:
28199 // op: imms
28200 return 5;
28201 }
28202 break;
28203 }
28204 case AArch64::BFCVTNT_ZPmZ:
28205 case AArch64::BFCVT_ZPmZ:
28206 case AArch64::RBIT_ZPmZ_B:
28207 case AArch64::RBIT_ZPmZ_D:
28208 case AArch64::RBIT_ZPmZ_H:
28209 case AArch64::RBIT_ZPmZ_S:
28210 case AArch64::REVB_ZPmZ_D:
28211 case AArch64::REVB_ZPmZ_H:
28212 case AArch64::REVB_ZPmZ_S:
28213 case AArch64::REVD_ZPmZ:
28214 case AArch64::REVH_ZPmZ_D:
28215 case AArch64::REVH_ZPmZ_S:
28216 case AArch64::REVW_ZPmZ_D: {
28217 switch (OpNum) {
28218 case 0:
28219 // op: Zd
28220 return 0;
28221 case 2:
28222 // op: Pg
28223 return 10;
28224 case 3:
28225 // op: Zn
28226 return 5;
28227 }
28228 break;
28229 }
28230 case AArch64::CPY_ZPmI_B:
28231 case AArch64::CPY_ZPmI_D:
28232 case AArch64::CPY_ZPmI_H:
28233 case AArch64::CPY_ZPmI_S: {
28234 switch (OpNum) {
28235 case 0:
28236 // op: Zd
28237 return 0;
28238 case 2:
28239 // op: Pg
28240 return 16;
28241 case 3:
28242 // op: imm
28243 return 5;
28244 }
28245 break;
28246 }
28247 case AArch64::INDEX_RR_B:
28248 case AArch64::INDEX_RR_D:
28249 case AArch64::INDEX_RR_H:
28250 case AArch64::INDEX_RR_S: {
28251 switch (OpNum) {
28252 case 0:
28253 // op: Zd
28254 return 0;
28255 case 2:
28256 // op: Rm
28257 return 16;
28258 case 1:
28259 // op: Rn
28260 return 5;
28261 }
28262 break;
28263 }
28264 case AArch64::ADD_ZZZ_B:
28265 case AArch64::ADD_ZZZ_CPA:
28266 case AArch64::ADD_ZZZ_D:
28267 case AArch64::ADD_ZZZ_H:
28268 case AArch64::ADD_ZZZ_S:
28269 case AArch64::AND_ZZZ:
28270 case AArch64::ASR_WIDE_ZZZ_B:
28271 case AArch64::ASR_WIDE_ZZZ_H:
28272 case AArch64::ASR_WIDE_ZZZ_S:
28273 case AArch64::BFADD_ZZZ:
28274 case AArch64::BFMUL_ZZZ:
28275 case AArch64::BFSUB_ZZZ:
28276 case AArch64::BIC_ZZZ:
28277 case AArch64::EOR_ZZZ:
28278 case AArch64::FADD_ZZZ_D:
28279 case AArch64::FADD_ZZZ_H:
28280 case AArch64::FADD_ZZZ_S:
28281 case AArch64::FMUL_ZZZ_D:
28282 case AArch64::FMUL_ZZZ_H:
28283 case AArch64::FMUL_ZZZ_S:
28284 case AArch64::FRECPS_ZZZ_D:
28285 case AArch64::FRECPS_ZZZ_H:
28286 case AArch64::FRECPS_ZZZ_S:
28287 case AArch64::FRSQRTS_ZZZ_D:
28288 case AArch64::FRSQRTS_ZZZ_H:
28289 case AArch64::FRSQRTS_ZZZ_S:
28290 case AArch64::FSUB_ZZZ_D:
28291 case AArch64::FSUB_ZZZ_H:
28292 case AArch64::FSUB_ZZZ_S:
28293 case AArch64::FTSMUL_ZZZ_D:
28294 case AArch64::FTSMUL_ZZZ_H:
28295 case AArch64::FTSMUL_ZZZ_S:
28296 case AArch64::FTSSEL_ZZZ_D:
28297 case AArch64::FTSSEL_ZZZ_H:
28298 case AArch64::FTSSEL_ZZZ_S:
28299 case AArch64::LSL_WIDE_ZZZ_B:
28300 case AArch64::LSL_WIDE_ZZZ_H:
28301 case AArch64::LSL_WIDE_ZZZ_S:
28302 case AArch64::LSR_WIDE_ZZZ_B:
28303 case AArch64::LSR_WIDE_ZZZ_H:
28304 case AArch64::LSR_WIDE_ZZZ_S:
28305 case AArch64::MUL_ZZZ_B:
28306 case AArch64::MUL_ZZZ_D:
28307 case AArch64::MUL_ZZZ_H:
28308 case AArch64::MUL_ZZZ_S:
28309 case AArch64::ORR_ZZZ:
28310 case AArch64::PMUL_ZZZ_B:
28311 case AArch64::SMULH_ZZZ_B:
28312 case AArch64::SMULH_ZZZ_D:
28313 case AArch64::SMULH_ZZZ_H:
28314 case AArch64::SMULH_ZZZ_S:
28315 case AArch64::SQADD_ZZZ_B:
28316 case AArch64::SQADD_ZZZ_D:
28317 case AArch64::SQADD_ZZZ_H:
28318 case AArch64::SQADD_ZZZ_S:
28319 case AArch64::SQDMULH_ZZZ_B:
28320 case AArch64::SQDMULH_ZZZ_D:
28321 case AArch64::SQDMULH_ZZZ_H:
28322 case AArch64::SQDMULH_ZZZ_S:
28323 case AArch64::SQRDMULH_ZZZ_B:
28324 case AArch64::SQRDMULH_ZZZ_D:
28325 case AArch64::SQRDMULH_ZZZ_H:
28326 case AArch64::SQRDMULH_ZZZ_S:
28327 case AArch64::SQSUB_ZZZ_B:
28328 case AArch64::SQSUB_ZZZ_D:
28329 case AArch64::SQSUB_ZZZ_H:
28330 case AArch64::SQSUB_ZZZ_S:
28331 case AArch64::SUB_ZZZ_B:
28332 case AArch64::SUB_ZZZ_CPA:
28333 case AArch64::SUB_ZZZ_D:
28334 case AArch64::SUB_ZZZ_H:
28335 case AArch64::SUB_ZZZ_S:
28336 case AArch64::TBL_ZZZZ_B:
28337 case AArch64::TBL_ZZZZ_D:
28338 case AArch64::TBL_ZZZZ_H:
28339 case AArch64::TBL_ZZZZ_S:
28340 case AArch64::TBL_ZZZ_B:
28341 case AArch64::TBL_ZZZ_D:
28342 case AArch64::TBL_ZZZ_H:
28343 case AArch64::TBL_ZZZ_S:
28344 case AArch64::TRN1_ZZZ_B:
28345 case AArch64::TRN1_ZZZ_D:
28346 case AArch64::TRN1_ZZZ_H:
28347 case AArch64::TRN1_ZZZ_Q:
28348 case AArch64::TRN1_ZZZ_S:
28349 case AArch64::TRN2_ZZZ_B:
28350 case AArch64::TRN2_ZZZ_D:
28351 case AArch64::TRN2_ZZZ_H:
28352 case AArch64::TRN2_ZZZ_Q:
28353 case AArch64::TRN2_ZZZ_S:
28354 case AArch64::UMULH_ZZZ_B:
28355 case AArch64::UMULH_ZZZ_D:
28356 case AArch64::UMULH_ZZZ_H:
28357 case AArch64::UMULH_ZZZ_S:
28358 case AArch64::UQADD_ZZZ_B:
28359 case AArch64::UQADD_ZZZ_D:
28360 case AArch64::UQADD_ZZZ_H:
28361 case AArch64::UQADD_ZZZ_S:
28362 case AArch64::UQSUB_ZZZ_B:
28363 case AArch64::UQSUB_ZZZ_D:
28364 case AArch64::UQSUB_ZZZ_H:
28365 case AArch64::UQSUB_ZZZ_S:
28366 case AArch64::UZP1_ZZZ_B:
28367 case AArch64::UZP1_ZZZ_D:
28368 case AArch64::UZP1_ZZZ_H:
28369 case AArch64::UZP1_ZZZ_Q:
28370 case AArch64::UZP1_ZZZ_S:
28371 case AArch64::UZP2_ZZZ_B:
28372 case AArch64::UZP2_ZZZ_D:
28373 case AArch64::UZP2_ZZZ_H:
28374 case AArch64::UZP2_ZZZ_Q:
28375 case AArch64::UZP2_ZZZ_S:
28376 case AArch64::ZIP1_ZZZ_B:
28377 case AArch64::ZIP1_ZZZ_D:
28378 case AArch64::ZIP1_ZZZ_H:
28379 case AArch64::ZIP1_ZZZ_Q:
28380 case AArch64::ZIP1_ZZZ_S:
28381 case AArch64::ZIP2_ZZZ_B:
28382 case AArch64::ZIP2_ZZZ_D:
28383 case AArch64::ZIP2_ZZZ_H:
28384 case AArch64::ZIP2_ZZZ_Q:
28385 case AArch64::ZIP2_ZZZ_S: {
28386 switch (OpNum) {
28387 case 0:
28388 // op: Zd
28389 return 0;
28390 case 2:
28391 // op: Zm
28392 return 16;
28393 case 1:
28394 // op: Zn
28395 return 5;
28396 }
28397 break;
28398 }
28399 case AArch64::HISTCNT_ZPzZZ_D:
28400 case AArch64::HISTCNT_ZPzZZ_S: {
28401 switch (OpNum) {
28402 case 0:
28403 // op: Zd
28404 return 0;
28405 case 2:
28406 // op: Zn
28407 return 5;
28408 case 1:
28409 // op: Pg
28410 return 10;
28411 case 3:
28412 // op: Zm
28413 return 16;
28414 }
28415 break;
28416 }
28417 case AArch64::ADDHNT_ZZZ_B:
28418 case AArch64::ADDHNT_ZZZ_H:
28419 case AArch64::ADDHNT_ZZZ_S:
28420 case AArch64::EORBT_ZZZ_B:
28421 case AArch64::EORBT_ZZZ_D:
28422 case AArch64::EORBT_ZZZ_H:
28423 case AArch64::EORBT_ZZZ_S:
28424 case AArch64::EORTB_ZZZ_B:
28425 case AArch64::EORTB_ZZZ_D:
28426 case AArch64::EORTB_ZZZ_H:
28427 case AArch64::EORTB_ZZZ_S:
28428 case AArch64::RADDHNT_ZZZ_B:
28429 case AArch64::RADDHNT_ZZZ_H:
28430 case AArch64::RADDHNT_ZZZ_S:
28431 case AArch64::RSUBHNT_ZZZ_B:
28432 case AArch64::RSUBHNT_ZZZ_H:
28433 case AArch64::RSUBHNT_ZZZ_S:
28434 case AArch64::SUBHNT_ZZZ_B:
28435 case AArch64::SUBHNT_ZZZ_H:
28436 case AArch64::SUBHNT_ZZZ_S: {
28437 switch (OpNum) {
28438 case 0:
28439 // op: Zd
28440 return 0;
28441 case 2:
28442 // op: Zn
28443 return 5;
28444 case 3:
28445 // op: Zm
28446 return 16;
28447 }
28448 break;
28449 }
28450 case AArch64::RSHRNT_ZZI_B:
28451 case AArch64::RSHRNT_ZZI_H:
28452 case AArch64::RSHRNT_ZZI_S:
28453 case AArch64::SHRNT_ZZI_B:
28454 case AArch64::SHRNT_ZZI_H:
28455 case AArch64::SHRNT_ZZI_S:
28456 case AArch64::SLI_ZZI_B:
28457 case AArch64::SLI_ZZI_D:
28458 case AArch64::SLI_ZZI_H:
28459 case AArch64::SLI_ZZI_S:
28460 case AArch64::SQRSHRNT_ZZI_B:
28461 case AArch64::SQRSHRNT_ZZI_H:
28462 case AArch64::SQRSHRNT_ZZI_S:
28463 case AArch64::SQRSHRUNT_ZZI_B:
28464 case AArch64::SQRSHRUNT_ZZI_H:
28465 case AArch64::SQRSHRUNT_ZZI_S:
28466 case AArch64::SQSHRNT_ZZI_B:
28467 case AArch64::SQSHRNT_ZZI_H:
28468 case AArch64::SQSHRNT_ZZI_S:
28469 case AArch64::SQSHRUNT_ZZI_B:
28470 case AArch64::SQSHRUNT_ZZI_H:
28471 case AArch64::SQSHRUNT_ZZI_S:
28472 case AArch64::SRI_ZZI_B:
28473 case AArch64::SRI_ZZI_D:
28474 case AArch64::SRI_ZZI_H:
28475 case AArch64::SRI_ZZI_S:
28476 case AArch64::UQRSHRNT_ZZI_B:
28477 case AArch64::UQRSHRNT_ZZI_H:
28478 case AArch64::UQRSHRNT_ZZI_S:
28479 case AArch64::UQSHRNT_ZZI_B:
28480 case AArch64::UQSHRNT_ZZI_H:
28481 case AArch64::UQSHRNT_ZZI_S: {
28482 switch (OpNum) {
28483 case 0:
28484 // op: Zd
28485 return 0;
28486 case 2:
28487 // op: Zn
28488 return 5;
28489 case 3:
28490 // op: imm
28491 return 16;
28492 }
28493 break;
28494 }
28495 case AArch64::SQXTNT_ZZ_B:
28496 case AArch64::SQXTNT_ZZ_H:
28497 case AArch64::SQXTNT_ZZ_S:
28498 case AArch64::SQXTUNT_ZZ_B:
28499 case AArch64::SQXTUNT_ZZ_H:
28500 case AArch64::SQXTUNT_ZZ_S:
28501 case AArch64::UQXTNT_ZZ_B:
28502 case AArch64::UQXTNT_ZZ_H:
28503 case AArch64::UQXTNT_ZZ_S: {
28504 switch (OpNum) {
28505 case 0:
28506 // op: Zd
28507 return 0;
28508 case 2:
28509 // op: Zn
28510 return 5;
28511 }
28512 break;
28513 }
28514 case AArch64::PMOV_ZIP_D:
28515 case AArch64::PMOV_ZIP_H:
28516 case AArch64::PMOV_ZIP_S: {
28517 switch (OpNum) {
28518 case 0:
28519 // op: Zd
28520 return 0;
28521 case 3:
28522 // op: Pn
28523 return 5;
28524 case 2:
28525 // op: index
28526 return 17;
28527 }
28528 break;
28529 }
28530 case AArch64::PMOV_ZIP_B: {
28531 switch (OpNum) {
28532 case 0:
28533 // op: Zd
28534 return 0;
28535 case 3:
28536 // op: Pn
28537 return 5;
28538 }
28539 break;
28540 }
28541 case AArch64::TBXQ_ZZZ_B:
28542 case AArch64::TBXQ_ZZZ_D:
28543 case AArch64::TBXQ_ZZZ_H:
28544 case AArch64::TBXQ_ZZZ_S:
28545 case AArch64::TBX_ZZZ_B:
28546 case AArch64::TBX_ZZZ_D:
28547 case AArch64::TBX_ZZZ_H:
28548 case AArch64::TBX_ZZZ_S: {
28549 switch (OpNum) {
28550 case 0:
28551 // op: Zd
28552 return 0;
28553 case 3:
28554 // op: Zm
28555 return 16;
28556 case 2:
28557 // op: Zn
28558 return 5;
28559 }
28560 break;
28561 }
28562 case AArch64::FCVTLT_ZPmZ_HtoS:
28563 case AArch64::FCVTLT_ZPmZ_StoD:
28564 case AArch64::FCVTNT_ZPmZ_DtoS:
28565 case AArch64::FCVTNT_ZPmZ_StoH:
28566 case AArch64::FCVTXNT_ZPmZ_DtoS: {
28567 switch (OpNum) {
28568 case 0:
28569 // op: Zd
28570 return 0;
28571 case 3:
28572 // op: Zn
28573 return 5;
28574 case 2:
28575 // op: Pg
28576 return 10;
28577 }
28578 break;
28579 }
28580 case AArch64::MOVA_2ZMXI_H_D:
28581 case AArch64::MOVA_2ZMXI_V_D: {
28582 switch (OpNum) {
28583 case 0:
28584 // op: Zd
28585 return 1;
28586 case 2:
28587 // op: Rs
28588 return 13;
28589 case 1:
28590 // op: ZAn
28591 return 5;
28592 }
28593 break;
28594 }
28595 case AArch64::MOVA_2ZMXI_H_S:
28596 case AArch64::MOVA_2ZMXI_V_S: {
28597 switch (OpNum) {
28598 case 0:
28599 // op: Zd
28600 return 1;
28601 case 2:
28602 // op: Rs
28603 return 13;
28604 case 1:
28605 // op: ZAn
28606 return 6;
28607 case 3:
28608 // op: imm
28609 return 5;
28610 }
28611 break;
28612 }
28613 case AArch64::MOVA_2ZMXI_H_H:
28614 case AArch64::MOVA_2ZMXI_V_H: {
28615 switch (OpNum) {
28616 case 0:
28617 // op: Zd
28618 return 1;
28619 case 2:
28620 // op: Rs
28621 return 13;
28622 case 1:
28623 // op: ZAn
28624 return 7;
28625 case 3:
28626 // op: imm
28627 return 5;
28628 }
28629 break;
28630 }
28631 case AArch64::MOVA_2ZMXI_H_B:
28632 case AArch64::MOVA_2ZMXI_V_B: {
28633 switch (OpNum) {
28634 case 0:
28635 // op: Zd
28636 return 1;
28637 case 2:
28638 // op: Rs
28639 return 13;
28640 case 3:
28641 // op: imm
28642 return 5;
28643 }
28644 break;
28645 }
28646 case AArch64::UZP_VG2_2ZZZ_B:
28647 case AArch64::UZP_VG2_2ZZZ_D:
28648 case AArch64::UZP_VG2_2ZZZ_H:
28649 case AArch64::UZP_VG2_2ZZZ_Q:
28650 case AArch64::UZP_VG2_2ZZZ_S:
28651 case AArch64::ZIP_VG2_2ZZZ_B:
28652 case AArch64::ZIP_VG2_2ZZZ_D:
28653 case AArch64::ZIP_VG2_2ZZZ_H:
28654 case AArch64::ZIP_VG2_2ZZZ_Q:
28655 case AArch64::ZIP_VG2_2ZZZ_S: {
28656 switch (OpNum) {
28657 case 0:
28658 // op: Zd
28659 return 1;
28660 case 2:
28661 // op: Zm
28662 return 16;
28663 case 1:
28664 // op: Zn
28665 return 5;
28666 }
28667 break;
28668 }
28669 case AArch64::MOVAZ_2ZMI_H_D:
28670 case AArch64::MOVAZ_2ZMI_V_D: {
28671 switch (OpNum) {
28672 case 0:
28673 // op: Zd
28674 return 1;
28675 case 3:
28676 // op: Rs
28677 return 13;
28678 case 2:
28679 // op: ZAn
28680 return 5;
28681 }
28682 break;
28683 }
28684 case AArch64::MOVAZ_2ZMI_H_S:
28685 case AArch64::MOVAZ_2ZMI_V_S: {
28686 switch (OpNum) {
28687 case 0:
28688 // op: Zd
28689 return 1;
28690 case 3:
28691 // op: Rs
28692 return 13;
28693 case 2:
28694 // op: ZAn
28695 return 6;
28696 case 4:
28697 // op: imm
28698 return 5;
28699 }
28700 break;
28701 }
28702 case AArch64::MOVAZ_2ZMI_H_H:
28703 case AArch64::MOVAZ_2ZMI_V_H: {
28704 switch (OpNum) {
28705 case 0:
28706 // op: Zd
28707 return 1;
28708 case 3:
28709 // op: Rs
28710 return 13;
28711 case 2:
28712 // op: ZAn
28713 return 7;
28714 case 4:
28715 // op: imm
28716 return 5;
28717 }
28718 break;
28719 }
28720 case AArch64::MOVAZ_2ZMI_H_B:
28721 case AArch64::MOVAZ_2ZMI_V_B: {
28722 switch (OpNum) {
28723 case 0:
28724 // op: Zd
28725 return 1;
28726 case 3:
28727 // op: Rs
28728 return 13;
28729 case 4:
28730 // op: imm
28731 return 5;
28732 }
28733 break;
28734 }
28735 case AArch64::MOVA_4ZMXI_H_D:
28736 case AArch64::MOVA_4ZMXI_H_S:
28737 case AArch64::MOVA_4ZMXI_V_D:
28738 case AArch64::MOVA_4ZMXI_V_S: {
28739 switch (OpNum) {
28740 case 0:
28741 // op: Zd
28742 return 2;
28743 case 2:
28744 // op: Rs
28745 return 13;
28746 case 1:
28747 // op: ZAn
28748 return 5;
28749 }
28750 break;
28751 }
28752 case AArch64::MOVA_4ZMXI_H_H:
28753 case AArch64::MOVA_4ZMXI_V_H: {
28754 switch (OpNum) {
28755 case 0:
28756 // op: Zd
28757 return 2;
28758 case 2:
28759 // op: Rs
28760 return 13;
28761 case 1:
28762 // op: ZAn
28763 return 6;
28764 case 3:
28765 // op: imm
28766 return 5;
28767 }
28768 break;
28769 }
28770 case AArch64::MOVA_4ZMXI_H_B:
28771 case AArch64::MOVA_4ZMXI_V_B: {
28772 switch (OpNum) {
28773 case 0:
28774 // op: Zd
28775 return 2;
28776 case 2:
28777 // op: Rs
28778 return 13;
28779 case 3:
28780 // op: imm
28781 return 5;
28782 }
28783 break;
28784 }
28785 case AArch64::MOVAZ_4ZMI_H_D:
28786 case AArch64::MOVAZ_4ZMI_H_S:
28787 case AArch64::MOVAZ_4ZMI_V_D:
28788 case AArch64::MOVAZ_4ZMI_V_S: {
28789 switch (OpNum) {
28790 case 0:
28791 // op: Zd
28792 return 2;
28793 case 3:
28794 // op: Rs
28795 return 13;
28796 case 2:
28797 // op: ZAn
28798 return 5;
28799 }
28800 break;
28801 }
28802 case AArch64::MOVAZ_4ZMI_H_H:
28803 case AArch64::MOVAZ_4ZMI_V_H: {
28804 switch (OpNum) {
28805 case 0:
28806 // op: Zd
28807 return 2;
28808 case 3:
28809 // op: Rs
28810 return 13;
28811 case 2:
28812 // op: ZAn
28813 return 6;
28814 case 4:
28815 // op: imm
28816 return 5;
28817 }
28818 break;
28819 }
28820 case AArch64::MOVAZ_4ZMI_H_B:
28821 case AArch64::MOVAZ_4ZMI_V_B: {
28822 switch (OpNum) {
28823 case 0:
28824 // op: Zd
28825 return 2;
28826 case 3:
28827 // op: Rs
28828 return 13;
28829 case 4:
28830 // op: imm
28831 return 5;
28832 }
28833 break;
28834 }
28835 case AArch64::FCMLA_ZPmZZ_D:
28836 case AArch64::FCMLA_ZPmZZ_H:
28837 case AArch64::FCMLA_ZPmZZ_S: {
28838 switch (OpNum) {
28839 case 0:
28840 // op: Zda
28841 return 0;
28842 case 1:
28843 // op: Pg
28844 return 10;
28845 case 3:
28846 // op: Zn
28847 return 5;
28848 case 4:
28849 // op: Zm
28850 return 16;
28851 case 5:
28852 // op: imm
28853 return 13;
28854 }
28855 break;
28856 }
28857 case AArch64::SDOT_ZZZI_HtoS:
28858 case AArch64::UDOT_ZZZI_HtoS: {
28859 switch (OpNum) {
28860 case 0:
28861 // op: Zda
28862 return 0;
28863 case 2:
28864 // op: Zn
28865 return 5;
28866 case 3:
28867 // op: Zm
28868 return 16;
28869 case 4:
28870 // op: i2
28871 return 19;
28872 }
28873 break;
28874 }
28875 case AArch64::SUDOT_ZZZI:
28876 case AArch64::USDOT_ZZZI: {
28877 switch (OpNum) {
28878 case 0:
28879 // op: Zda
28880 return 0;
28881 case 2:
28882 // op: Zn
28883 return 5;
28884 case 3:
28885 // op: Zm
28886 return 16;
28887 case 4:
28888 // op: idx
28889 return 19;
28890 }
28891 break;
28892 }
28893 case AArch64::FMLALB_ZZZI:
28894 case AArch64::FMLALLBB_ZZZI:
28895 case AArch64::FMLALLBT_ZZZI:
28896 case AArch64::FMLALLTB_ZZZI:
28897 case AArch64::FMLALLTT_ZZZI:
28898 case AArch64::FMLALT_ZZZI: {
28899 switch (OpNum) {
28900 case 0:
28901 // op: Zda
28902 return 0;
28903 case 2:
28904 // op: Zn
28905 return 5;
28906 case 3:
28907 // op: Zm
28908 return 16;
28909 case 4:
28910 // op: imm4
28911 return 10;
28912 }
28913 break;
28914 }
28915 case AArch64::BFMLALB_ZZZI:
28916 case AArch64::BFMLALT_ZZZI:
28917 case AArch64::BFMLSLB_ZZZI_S:
28918 case AArch64::BFMLSLT_ZZZI_S:
28919 case AArch64::FDOT_ZZZI_BtoH:
28920 case AArch64::FMLALB_ZZZI_SHH:
28921 case AArch64::FMLALT_ZZZI_SHH:
28922 case AArch64::FMLSLB_ZZZI_SHH:
28923 case AArch64::FMLSLT_ZZZI_SHH:
28924 case AArch64::SMLALB_ZZZI_D:
28925 case AArch64::SMLALB_ZZZI_S:
28926 case AArch64::SMLALT_ZZZI_D:
28927 case AArch64::SMLALT_ZZZI_S:
28928 case AArch64::SMLSLB_ZZZI_D:
28929 case AArch64::SMLSLB_ZZZI_S:
28930 case AArch64::SMLSLT_ZZZI_D:
28931 case AArch64::SMLSLT_ZZZI_S:
28932 case AArch64::SQDMLALB_ZZZI_D:
28933 case AArch64::SQDMLALB_ZZZI_S:
28934 case AArch64::SQDMLALT_ZZZI_D:
28935 case AArch64::SQDMLALT_ZZZI_S:
28936 case AArch64::SQDMLSLB_ZZZI_D:
28937 case AArch64::SQDMLSLB_ZZZI_S:
28938 case AArch64::SQDMLSLT_ZZZI_D:
28939 case AArch64::SQDMLSLT_ZZZI_S:
28940 case AArch64::UMLALB_ZZZI_D:
28941 case AArch64::UMLALB_ZZZI_S:
28942 case AArch64::UMLALT_ZZZI_D:
28943 case AArch64::UMLALT_ZZZI_S:
28944 case AArch64::UMLSLB_ZZZI_D:
28945 case AArch64::UMLSLB_ZZZI_S:
28946 case AArch64::UMLSLT_ZZZI_D:
28947 case AArch64::UMLSLT_ZZZI_S: {
28948 switch (OpNum) {
28949 case 0:
28950 // op: Zda
28951 return 0;
28952 case 2:
28953 // op: Zn
28954 return 5;
28955 case 3:
28956 // op: Zm
28957 return 16;
28958 case 4:
28959 // op: iop
28960 return 11;
28961 }
28962 break;
28963 }
28964 case AArch64::BFDOT_ZZI:
28965 case AArch64::BFMLA_ZZZI:
28966 case AArch64::BFMLS_ZZZI:
28967 case AArch64::FDOT_ZZZI_BtoS:
28968 case AArch64::FDOT_ZZZI_S:
28969 case AArch64::FMLA_ZZZI_H:
28970 case AArch64::FMLA_ZZZI_S:
28971 case AArch64::FMLS_ZZZI_H:
28972 case AArch64::FMLS_ZZZI_S:
28973 case AArch64::MLA_ZZZI_H:
28974 case AArch64::MLA_ZZZI_S:
28975 case AArch64::MLS_ZZZI_H:
28976 case AArch64::MLS_ZZZI_S:
28977 case AArch64::SQRDMLAH_ZZZI_H:
28978 case AArch64::SQRDMLAH_ZZZI_S:
28979 case AArch64::SQRDMLSH_ZZZI_H:
28980 case AArch64::SQRDMLSH_ZZZI_S: {
28981 switch (OpNum) {
28982 case 0:
28983 // op: Zda
28984 return 0;
28985 case 2:
28986 // op: Zn
28987 return 5;
28988 case 3:
28989 // op: Zm
28990 return 16;
28991 case 4:
28992 // op: iop
28993 return 19;
28994 }
28995 break;
28996 }
28997 case AArch64::FMLA_ZZZI_D:
28998 case AArch64::FMLS_ZZZI_D:
28999 case AArch64::MLA_ZZZI_D:
29000 case AArch64::MLS_ZZZI_D:
29001 case AArch64::SQRDMLAH_ZZZI_D:
29002 case AArch64::SQRDMLSH_ZZZI_D: {
29003 switch (OpNum) {
29004 case 0:
29005 // op: Zda
29006 return 0;
29007 case 2:
29008 // op: Zn
29009 return 5;
29010 case 3:
29011 // op: Zm
29012 return 16;
29013 case 4:
29014 // op: iop
29015 return 20;
29016 }
29017 break;
29018 }
29019 case AArch64::CDOT_ZZZ_D:
29020 case AArch64::CDOT_ZZZ_S:
29021 case AArch64::CMLA_ZZZ_B:
29022 case AArch64::CMLA_ZZZ_D:
29023 case AArch64::CMLA_ZZZ_H:
29024 case AArch64::CMLA_ZZZ_S:
29025 case AArch64::SQRDCMLAH_ZZZ_B:
29026 case AArch64::SQRDCMLAH_ZZZ_D:
29027 case AArch64::SQRDCMLAH_ZZZ_H:
29028 case AArch64::SQRDCMLAH_ZZZ_S: {
29029 switch (OpNum) {
29030 case 0:
29031 // op: Zda
29032 return 0;
29033 case 2:
29034 // op: Zn
29035 return 5;
29036 case 3:
29037 // op: Zm
29038 return 16;
29039 case 4:
29040 // op: rot
29041 return 10;
29042 }
29043 break;
29044 }
29045 case AArch64::ADCLB_ZZZ_D:
29046 case AArch64::ADCLB_ZZZ_S:
29047 case AArch64::ADCLT_ZZZ_D:
29048 case AArch64::ADCLT_ZZZ_S:
29049 case AArch64::BFDOT_ZZZ:
29050 case AArch64::BFMLALB_ZZZ:
29051 case AArch64::BFMLALT_ZZZ:
29052 case AArch64::BFMLSLB_ZZZ_S:
29053 case AArch64::BFMLSLT_ZZZ_S:
29054 case AArch64::FDOT_ZZZ_BtoH:
29055 case AArch64::FDOT_ZZZ_BtoS:
29056 case AArch64::FDOT_ZZZ_S:
29057 case AArch64::FMLALB_ZZZ:
29058 case AArch64::FMLALB_ZZZ_SHH:
29059 case AArch64::FMLALLBB_ZZZ:
29060 case AArch64::FMLALLBT_ZZZ:
29061 case AArch64::FMLALLTB_ZZZ:
29062 case AArch64::FMLALLTT_ZZZ:
29063 case AArch64::FMLALT_ZZZ:
29064 case AArch64::FMLALT_ZZZ_SHH:
29065 case AArch64::FMLSLB_ZZZ_SHH:
29066 case AArch64::FMLSLT_ZZZ_SHH:
29067 case AArch64::FMMLA_ZZZ_D:
29068 case AArch64::FMMLA_ZZZ_S:
29069 case AArch64::MLA_CPA:
29070 case AArch64::SABALB_ZZZ_D:
29071 case AArch64::SABALB_ZZZ_H:
29072 case AArch64::SABALB_ZZZ_S:
29073 case AArch64::SABALT_ZZZ_D:
29074 case AArch64::SABALT_ZZZ_H:
29075 case AArch64::SABALT_ZZZ_S:
29076 case AArch64::SABA_ZZZ_B:
29077 case AArch64::SABA_ZZZ_D:
29078 case AArch64::SABA_ZZZ_H:
29079 case AArch64::SABA_ZZZ_S:
29080 case AArch64::SBCLB_ZZZ_D:
29081 case AArch64::SBCLB_ZZZ_S:
29082 case AArch64::SBCLT_ZZZ_D:
29083 case AArch64::SBCLT_ZZZ_S:
29084 case AArch64::SDOT_ZZZ_D:
29085 case AArch64::SDOT_ZZZ_HtoS:
29086 case AArch64::SDOT_ZZZ_S:
29087 case AArch64::SMLALB_ZZZ_D:
29088 case AArch64::SMLALB_ZZZ_H:
29089 case AArch64::SMLALB_ZZZ_S:
29090 case AArch64::SMLALT_ZZZ_D:
29091 case AArch64::SMLALT_ZZZ_H:
29092 case AArch64::SMLALT_ZZZ_S:
29093 case AArch64::SMLSLB_ZZZ_D:
29094 case AArch64::SMLSLB_ZZZ_H:
29095 case AArch64::SMLSLB_ZZZ_S:
29096 case AArch64::SMLSLT_ZZZ_D:
29097 case AArch64::SMLSLT_ZZZ_H:
29098 case AArch64::SMLSLT_ZZZ_S:
29099 case AArch64::SMMLA_ZZZ:
29100 case AArch64::SQDMLALBT_ZZZ_D:
29101 case AArch64::SQDMLALBT_ZZZ_H:
29102 case AArch64::SQDMLALBT_ZZZ_S:
29103 case AArch64::SQDMLALB_ZZZ_D:
29104 case AArch64::SQDMLALB_ZZZ_H:
29105 case AArch64::SQDMLALB_ZZZ_S:
29106 case AArch64::SQDMLALT_ZZZ_D:
29107 case AArch64::SQDMLALT_ZZZ_H:
29108 case AArch64::SQDMLALT_ZZZ_S:
29109 case AArch64::SQDMLSLBT_ZZZ_D:
29110 case AArch64::SQDMLSLBT_ZZZ_H:
29111 case AArch64::SQDMLSLBT_ZZZ_S:
29112 case AArch64::SQDMLSLB_ZZZ_D:
29113 case AArch64::SQDMLSLB_ZZZ_H:
29114 case AArch64::SQDMLSLB_ZZZ_S:
29115 case AArch64::SQDMLSLT_ZZZ_D:
29116 case AArch64::SQDMLSLT_ZZZ_H:
29117 case AArch64::SQDMLSLT_ZZZ_S:
29118 case AArch64::SQRDMLAH_ZZZ_B:
29119 case AArch64::SQRDMLAH_ZZZ_D:
29120 case AArch64::SQRDMLAH_ZZZ_H:
29121 case AArch64::SQRDMLAH_ZZZ_S:
29122 case AArch64::SQRDMLSH_ZZZ_B:
29123 case AArch64::SQRDMLSH_ZZZ_D:
29124 case AArch64::SQRDMLSH_ZZZ_H:
29125 case AArch64::SQRDMLSH_ZZZ_S:
29126 case AArch64::UABALB_ZZZ_D:
29127 case AArch64::UABALB_ZZZ_H:
29128 case AArch64::UABALB_ZZZ_S:
29129 case AArch64::UABALT_ZZZ_D:
29130 case AArch64::UABALT_ZZZ_H:
29131 case AArch64::UABALT_ZZZ_S:
29132 case AArch64::UABA_ZZZ_B:
29133 case AArch64::UABA_ZZZ_D:
29134 case AArch64::UABA_ZZZ_H:
29135 case AArch64::UABA_ZZZ_S:
29136 case AArch64::UDOT_ZZZ_D:
29137 case AArch64::UDOT_ZZZ_HtoS:
29138 case AArch64::UDOT_ZZZ_S:
29139 case AArch64::UMLALB_ZZZ_D:
29140 case AArch64::UMLALB_ZZZ_H:
29141 case AArch64::UMLALB_ZZZ_S:
29142 case AArch64::UMLALT_ZZZ_D:
29143 case AArch64::UMLALT_ZZZ_H:
29144 case AArch64::UMLALT_ZZZ_S:
29145 case AArch64::UMLSLB_ZZZ_D:
29146 case AArch64::UMLSLB_ZZZ_H:
29147 case AArch64::UMLSLB_ZZZ_S:
29148 case AArch64::UMLSLT_ZZZ_D:
29149 case AArch64::UMLSLT_ZZZ_H:
29150 case AArch64::UMLSLT_ZZZ_S:
29151 case AArch64::UMMLA_ZZZ:
29152 case AArch64::USDOT_ZZZ:
29153 case AArch64::USMMLA_ZZZ: {
29154 switch (OpNum) {
29155 case 0:
29156 // op: Zda
29157 return 0;
29158 case 2:
29159 // op: Zn
29160 return 5;
29161 case 3:
29162 // op: Zm
29163 return 16;
29164 }
29165 break;
29166 }
29167 case AArch64::SRSRA_ZZI_B:
29168 case AArch64::SRSRA_ZZI_D:
29169 case AArch64::SRSRA_ZZI_H:
29170 case AArch64::SRSRA_ZZI_S:
29171 case AArch64::SSRA_ZZI_B:
29172 case AArch64::SSRA_ZZI_D:
29173 case AArch64::SSRA_ZZI_H:
29174 case AArch64::SSRA_ZZI_S:
29175 case AArch64::URSRA_ZZI_B:
29176 case AArch64::URSRA_ZZI_D:
29177 case AArch64::URSRA_ZZI_H:
29178 case AArch64::URSRA_ZZI_S:
29179 case AArch64::USRA_ZZI_B:
29180 case AArch64::USRA_ZZI_D:
29181 case AArch64::USRA_ZZI_H:
29182 case AArch64::USRA_ZZI_S: {
29183 switch (OpNum) {
29184 case 0:
29185 // op: Zda
29186 return 0;
29187 case 2:
29188 // op: Zn
29189 return 5;
29190 case 3:
29191 // op: imm
29192 return 16;
29193 }
29194 break;
29195 }
29196 case AArch64::SDOT_ZZZI_S:
29197 case AArch64::UDOT_ZZZI_S: {
29198 switch (OpNum) {
29199 case 0:
29200 // op: Zda
29201 return 0;
29202 case 2:
29203 // op: Zn
29204 return 5;
29205 case 4:
29206 // op: iop
29207 return 19;
29208 case 3:
29209 // op: Zm
29210 return 16;
29211 }
29212 break;
29213 }
29214 case AArch64::SDOT_ZZZI_D:
29215 case AArch64::UDOT_ZZZI_D: {
29216 switch (OpNum) {
29217 case 0:
29218 // op: Zda
29219 return 0;
29220 case 2:
29221 // op: Zn
29222 return 5;
29223 case 4:
29224 // op: iop
29225 return 20;
29226 case 3:
29227 // op: Zm
29228 return 16;
29229 }
29230 break;
29231 }
29232 case AArch64::FCMLA_ZZZI_H: {
29233 switch (OpNum) {
29234 case 0:
29235 // op: Zda
29236 return 0;
29237 case 2:
29238 // op: Zn
29239 return 5;
29240 case 5:
29241 // op: imm
29242 return 10;
29243 case 3:
29244 // op: Zm
29245 return 16;
29246 case 4:
29247 // op: iop
29248 return 19;
29249 }
29250 break;
29251 }
29252 case AArch64::FCMLA_ZZZI_S: {
29253 switch (OpNum) {
29254 case 0:
29255 // op: Zda
29256 return 0;
29257 case 2:
29258 // op: Zn
29259 return 5;
29260 case 5:
29261 // op: imm
29262 return 10;
29263 case 3:
29264 // op: Zm
29265 return 16;
29266 case 4:
29267 // op: iop
29268 return 20;
29269 }
29270 break;
29271 }
29272 case AArch64::CDOT_ZZZI_S:
29273 case AArch64::CMLA_ZZZI_H:
29274 case AArch64::SQRDCMLAH_ZZZI_H: {
29275 switch (OpNum) {
29276 case 0:
29277 // op: Zda
29278 return 0;
29279 case 2:
29280 // op: Zn
29281 return 5;
29282 case 5:
29283 // op: rot
29284 return 10;
29285 case 4:
29286 // op: iop
29287 return 19;
29288 case 3:
29289 // op: Zm
29290 return 16;
29291 }
29292 break;
29293 }
29294 case AArch64::CDOT_ZZZI_D:
29295 case AArch64::CMLA_ZZZI_S:
29296 case AArch64::SQRDCMLAH_ZZZI_S: {
29297 switch (OpNum) {
29298 case 0:
29299 // op: Zda
29300 return 0;
29301 case 2:
29302 // op: Zn
29303 return 5;
29304 case 5:
29305 // op: rot
29306 return 10;
29307 case 4:
29308 // op: iop
29309 return 20;
29310 case 3:
29311 // op: Zm
29312 return 16;
29313 }
29314 break;
29315 }
29316 case AArch64::MAD_CPA: {
29317 switch (OpNum) {
29318 case 0:
29319 // op: Zdn
29320 return 0;
29321 case 2:
29322 // op: Zm
29323 return 16;
29324 case 3:
29325 // op: Za
29326 return 5;
29327 }
29328 break;
29329 }
29330 case AArch64::XAR_ZZZI_B:
29331 case AArch64::XAR_ZZZI_D:
29332 case AArch64::XAR_ZZZI_H:
29333 case AArch64::XAR_ZZZI_S: {
29334 switch (OpNum) {
29335 case 0:
29336 // op: Zdn
29337 return 0;
29338 case 2:
29339 // op: Zm
29340 return 5;
29341 case 3:
29342 // op: imm
29343 return 16;
29344 }
29345 break;
29346 }
29347 case AArch64::FTMAD_ZZI_D:
29348 case AArch64::FTMAD_ZZI_H:
29349 case AArch64::FTMAD_ZZI_S: {
29350 switch (OpNum) {
29351 case 0:
29352 // op: Zdn
29353 return 0;
29354 case 2:
29355 // op: Zm
29356 return 5;
29357 case 3:
29358 // op: imm3
29359 return 16;
29360 }
29361 break;
29362 }
29363 case AArch64::EXTQ_ZZI: {
29364 switch (OpNum) {
29365 case 0:
29366 // op: Zdn
29367 return 0;
29368 case 2:
29369 // op: Zm
29370 return 5;
29371 case 3:
29372 // op: imm4
29373 return 16;
29374 }
29375 break;
29376 }
29377 case AArch64::EXT_ZZI: {
29378 switch (OpNum) {
29379 case 0:
29380 // op: Zdn
29381 return 0;
29382 case 2:
29383 // op: Zm
29384 return 5;
29385 case 3:
29386 // op: imm8
29387 return 10;
29388 }
29389 break;
29390 }
29391 case AArch64::CADD_ZZI_B:
29392 case AArch64::CADD_ZZI_D:
29393 case AArch64::CADD_ZZI_H:
29394 case AArch64::CADD_ZZI_S:
29395 case AArch64::SQCADD_ZZI_B:
29396 case AArch64::SQCADD_ZZI_D:
29397 case AArch64::SQCADD_ZZI_H:
29398 case AArch64::SQCADD_ZZI_S: {
29399 switch (OpNum) {
29400 case 0:
29401 // op: Zdn
29402 return 0;
29403 case 2:
29404 // op: Zm
29405 return 5;
29406 case 3:
29407 // op: rot
29408 return 10;
29409 }
29410 break;
29411 }
29412 case AArch64::AESD_ZZZ_B:
29413 case AArch64::AESE_ZZZ_B:
29414 case AArch64::SM4E_ZZZ_S: {
29415 switch (OpNum) {
29416 case 0:
29417 // op: Zdn
29418 return 0;
29419 case 2:
29420 // op: Zm
29421 return 5;
29422 }
29423 break;
29424 }
29425 case AArch64::ADD_ZI_B:
29426 case AArch64::ADD_ZI_D:
29427 case AArch64::ADD_ZI_H:
29428 case AArch64::ADD_ZI_S:
29429 case AArch64::MUL_ZI_B:
29430 case AArch64::MUL_ZI_D:
29431 case AArch64::MUL_ZI_H:
29432 case AArch64::MUL_ZI_S:
29433 case AArch64::SMAX_ZI_B:
29434 case AArch64::SMAX_ZI_D:
29435 case AArch64::SMAX_ZI_H:
29436 case AArch64::SMAX_ZI_S:
29437 case AArch64::SMIN_ZI_B:
29438 case AArch64::SMIN_ZI_D:
29439 case AArch64::SMIN_ZI_H:
29440 case AArch64::SMIN_ZI_S:
29441 case AArch64::SQADD_ZI_B:
29442 case AArch64::SQADD_ZI_D:
29443 case AArch64::SQADD_ZI_H:
29444 case AArch64::SQADD_ZI_S:
29445 case AArch64::SQSUB_ZI_B:
29446 case AArch64::SQSUB_ZI_D:
29447 case AArch64::SQSUB_ZI_H:
29448 case AArch64::SQSUB_ZI_S:
29449 case AArch64::SUBR_ZI_B:
29450 case AArch64::SUBR_ZI_D:
29451 case AArch64::SUBR_ZI_H:
29452 case AArch64::SUBR_ZI_S:
29453 case AArch64::SUB_ZI_B:
29454 case AArch64::SUB_ZI_D:
29455 case AArch64::SUB_ZI_H:
29456 case AArch64::SUB_ZI_S:
29457 case AArch64::UMAX_ZI_B:
29458 case AArch64::UMAX_ZI_D:
29459 case AArch64::UMAX_ZI_H:
29460 case AArch64::UMAX_ZI_S:
29461 case AArch64::UMIN_ZI_B:
29462 case AArch64::UMIN_ZI_D:
29463 case AArch64::UMIN_ZI_H:
29464 case AArch64::UMIN_ZI_S:
29465 case AArch64::UQADD_ZI_B:
29466 case AArch64::UQADD_ZI_D:
29467 case AArch64::UQADD_ZI_H:
29468 case AArch64::UQADD_ZI_S:
29469 case AArch64::UQSUB_ZI_B:
29470 case AArch64::UQSUB_ZI_D:
29471 case AArch64::UQSUB_ZI_H:
29472 case AArch64::UQSUB_ZI_S: {
29473 switch (OpNum) {
29474 case 0:
29475 // op: Zdn
29476 return 0;
29477 case 2:
29478 // op: imm
29479 return 5;
29480 }
29481 break;
29482 }
29483 case AArch64::AND_ZI:
29484 case AArch64::EOR_ZI:
29485 case AArch64::ORR_ZI: {
29486 switch (OpNum) {
29487 case 0:
29488 // op: Zdn
29489 return 0;
29490 case 2:
29491 // op: imms13
29492 return 5;
29493 }
29494 break;
29495 }
29496 case AArch64::DECD_ZPiI:
29497 case AArch64::DECH_ZPiI:
29498 case AArch64::DECW_ZPiI:
29499 case AArch64::INCD_ZPiI:
29500 case AArch64::INCH_ZPiI:
29501 case AArch64::INCW_ZPiI:
29502 case AArch64::SQDECD_ZPiI:
29503 case AArch64::SQDECH_ZPiI:
29504 case AArch64::SQDECW_ZPiI:
29505 case AArch64::SQINCD_ZPiI:
29506 case AArch64::SQINCH_ZPiI:
29507 case AArch64::SQINCW_ZPiI:
29508 case AArch64::UQDECD_ZPiI:
29509 case AArch64::UQDECH_ZPiI:
29510 case AArch64::UQDECW_ZPiI:
29511 case AArch64::UQINCD_ZPiI:
29512 case AArch64::UQINCH_ZPiI:
29513 case AArch64::UQINCW_ZPiI: {
29514 switch (OpNum) {
29515 case 0:
29516 // op: Zdn
29517 return 0;
29518 case 2:
29519 // op: pattern
29520 return 5;
29521 case 3:
29522 // op: imm4
29523 return 16;
29524 }
29525 break;
29526 }
29527 case AArch64::BCAX_ZZZZ:
29528 case AArch64::BSL1N_ZZZZ:
29529 case AArch64::BSL2N_ZZZZ:
29530 case AArch64::BSL_ZZZZ:
29531 case AArch64::EOR3_ZZZZ:
29532 case AArch64::NBSL_ZZZZ: {
29533 switch (OpNum) {
29534 case 0:
29535 // op: Zdn
29536 return 0;
29537 case 3:
29538 // op: Zk
29539 return 5;
29540 case 2:
29541 // op: Zm
29542 return 16;
29543 }
29544 break;
29545 }
29546 case AArch64::FCADD_ZPmZ_D:
29547 case AArch64::FCADD_ZPmZ_H:
29548 case AArch64::FCADD_ZPmZ_S: {
29549 switch (OpNum) {
29550 case 0:
29551 // op: Zdn
29552 return 0;
29553 case 3:
29554 // op: Zm
29555 return 5;
29556 case 1:
29557 // op: Pg
29558 return 10;
29559 case 4:
29560 // op: imm
29561 return 16;
29562 }
29563 break;
29564 }
29565 case AArch64::AESIMC_ZZ_B:
29566 case AArch64::AESMC_ZZ_B: {
29567 switch (OpNum) {
29568 case 0:
29569 // op: Zdn
29570 return 0;
29571 }
29572 break;
29573 }
29574 case AArch64::LD1RO_B:
29575 case AArch64::LD1RO_D:
29576 case AArch64::LD1RO_H:
29577 case AArch64::LD1RO_W:
29578 case AArch64::LD1RQ_B:
29579 case AArch64::LD1RQ_D:
29580 case AArch64::LD1RQ_H:
29581 case AArch64::LD1RQ_W: {
29582 switch (OpNum) {
29583 case 0:
29584 // op: Zt
29585 return 0;
29586 case 1:
29587 // op: Pg
29588 return 10;
29589 case 2:
29590 // op: Rn
29591 return 5;
29592 case 3:
29593 // op: Rm
29594 return 16;
29595 }
29596 break;
29597 }
29598 case AArch64::LD2B_IMM:
29599 case AArch64::LD2D_IMM:
29600 case AArch64::LD2H_IMM:
29601 case AArch64::LD2Q_IMM:
29602 case AArch64::LD2W_IMM:
29603 case AArch64::LD3B_IMM:
29604 case AArch64::LD3D_IMM:
29605 case AArch64::LD3H_IMM:
29606 case AArch64::LD3Q_IMM:
29607 case AArch64::LD3W_IMM:
29608 case AArch64::LD4B_IMM:
29609 case AArch64::LD4D_IMM:
29610 case AArch64::LD4H_IMM:
29611 case AArch64::LD4Q_IMM:
29612 case AArch64::LD4W_IMM:
29613 case AArch64::LDNT1B_ZRI:
29614 case AArch64::LDNT1D_ZRI:
29615 case AArch64::LDNT1H_ZRI:
29616 case AArch64::LDNT1W_ZRI: {
29617 switch (OpNum) {
29618 case 0:
29619 // op: Zt
29620 return 0;
29621 case 1:
29622 // op: Pg
29623 return 10;
29624 case 2:
29625 // op: Rn
29626 return 5;
29627 case 3:
29628 // op: imm4
29629 return 16;
29630 }
29631 break;
29632 }
29633 case AArch64::LD1B:
29634 case AArch64::LD1B_D:
29635 case AArch64::LD1B_H:
29636 case AArch64::LD1B_S:
29637 case AArch64::LD1D:
29638 case AArch64::LD1H:
29639 case AArch64::LD1H_D:
29640 case AArch64::LD1H_S:
29641 case AArch64::LD1SB_D:
29642 case AArch64::LD1SB_H:
29643 case AArch64::LD1SB_S:
29644 case AArch64::LD1SH_D:
29645 case AArch64::LD1SH_S:
29646 case AArch64::LD1SW_D:
29647 case AArch64::LD1W:
29648 case AArch64::LD1W_D:
29649 case AArch64::LDFF1B:
29650 case AArch64::LDFF1B_D:
29651 case AArch64::LDFF1B_H:
29652 case AArch64::LDFF1B_S:
29653 case AArch64::LDFF1D:
29654 case AArch64::LDFF1H:
29655 case AArch64::LDFF1H_D:
29656 case AArch64::LDFF1H_S:
29657 case AArch64::LDFF1SB_D:
29658 case AArch64::LDFF1SB_H:
29659 case AArch64::LDFF1SB_S:
29660 case AArch64::LDFF1SH_D:
29661 case AArch64::LDFF1SH_S:
29662 case AArch64::LDFF1SW_D:
29663 case AArch64::LDFF1W:
29664 case AArch64::LDFF1W_D: {
29665 switch (OpNum) {
29666 case 0:
29667 // op: Zt
29668 return 0;
29669 case 1:
29670 // op: Pg
29671 return 10;
29672 case 3:
29673 // op: Rm
29674 return 16;
29675 case 2:
29676 // op: Rn
29677 return 5;
29678 }
29679 break;
29680 }
29681 case AArch64::LD1D_Q:
29682 case AArch64::LD1W_Q:
29683 case AArch64::ST2Q:
29684 case AArch64::ST3Q:
29685 case AArch64::ST4Q: {
29686 switch (OpNum) {
29687 case 0:
29688 // op: Zt
29689 return 0;
29690 case 2:
29691 // op: Rn
29692 return 5;
29693 case 1:
29694 // op: Pg
29695 return 10;
29696 case 3:
29697 // op: Rm
29698 return 16;
29699 }
29700 break;
29701 }
29702 case AArch64::LD1D_Q_IMM:
29703 case AArch64::LD1RO_B_IMM:
29704 case AArch64::LD1RO_D_IMM:
29705 case AArch64::LD1RO_H_IMM:
29706 case AArch64::LD1RO_W_IMM:
29707 case AArch64::LD1RQ_B_IMM:
29708 case AArch64::LD1RQ_D_IMM:
29709 case AArch64::LD1RQ_H_IMM:
29710 case AArch64::LD1RQ_W_IMM:
29711 case AArch64::LD1W_Q_IMM:
29712 case AArch64::ST2Q_IMM:
29713 case AArch64::ST3Q_IMM:
29714 case AArch64::ST4Q_IMM: {
29715 switch (OpNum) {
29716 case 0:
29717 // op: Zt
29718 return 0;
29719 case 2:
29720 // op: Rn
29721 return 5;
29722 case 1:
29723 // op: Pg
29724 return 10;
29725 case 3:
29726 // op: imm4
29727 return 16;
29728 }
29729 break;
29730 }
29731 case AArch64::GLD1Q:
29732 case AArch64::SST1Q: {
29733 switch (OpNum) {
29734 case 0:
29735 // op: Zt
29736 return 0;
29737 case 2:
29738 // op: Zn
29739 return 5;
29740 case 1:
29741 // op: Pg
29742 return 10;
29743 case 3:
29744 // op: Rm
29745 return 16;
29746 }
29747 break;
29748 }
29749 case AArch64::LD1B_2Z_IMM:
29750 case AArch64::LD1D_2Z_IMM:
29751 case AArch64::LD1H_2Z_IMM:
29752 case AArch64::LD1W_2Z_IMM:
29753 case AArch64::LDNT1B_2Z_IMM:
29754 case AArch64::LDNT1D_2Z_IMM:
29755 case AArch64::LDNT1H_2Z_IMM:
29756 case AArch64::LDNT1W_2Z_IMM:
29757 case AArch64::ST1B_2Z_IMM:
29758 case AArch64::ST1D_2Z_IMM:
29759 case AArch64::ST1H_2Z_IMM:
29760 case AArch64::ST1W_2Z_IMM:
29761 case AArch64::STNT1B_2Z_IMM:
29762 case AArch64::STNT1D_2Z_IMM:
29763 case AArch64::STNT1H_2Z_IMM:
29764 case AArch64::STNT1W_2Z_IMM: {
29765 switch (OpNum) {
29766 case 0:
29767 // op: Zt
29768 return 1;
29769 case 2:
29770 // op: Rn
29771 return 5;
29772 case 1:
29773 // op: PNg
29774 return 10;
29775 case 3:
29776 // op: imm4
29777 return 16;
29778 }
29779 break;
29780 }
29781 case AArch64::LD1B_2Z:
29782 case AArch64::LD1D_2Z:
29783 case AArch64::LD1H_2Z:
29784 case AArch64::LD1W_2Z:
29785 case AArch64::LDNT1B_2Z:
29786 case AArch64::LDNT1D_2Z:
29787 case AArch64::LDNT1H_2Z:
29788 case AArch64::LDNT1W_2Z:
29789 case AArch64::ST1B_2Z:
29790 case AArch64::ST1D_2Z:
29791 case AArch64::ST1H_2Z:
29792 case AArch64::ST1W_2Z:
29793 case AArch64::STNT1B_2Z:
29794 case AArch64::STNT1D_2Z:
29795 case AArch64::STNT1H_2Z:
29796 case AArch64::STNT1W_2Z: {
29797 switch (OpNum) {
29798 case 0:
29799 // op: Zt
29800 return 1;
29801 case 3:
29802 // op: Rm
29803 return 16;
29804 case 2:
29805 // op: Rn
29806 return 5;
29807 case 1:
29808 // op: PNg
29809 return 10;
29810 }
29811 break;
29812 }
29813 case AArch64::LD1B_4Z_IMM:
29814 case AArch64::LD1D_4Z_IMM:
29815 case AArch64::LD1H_4Z_IMM:
29816 case AArch64::LD1W_4Z_IMM:
29817 case AArch64::LDNT1B_4Z_IMM:
29818 case AArch64::LDNT1D_4Z_IMM:
29819 case AArch64::LDNT1H_4Z_IMM:
29820 case AArch64::LDNT1W_4Z_IMM:
29821 case AArch64::ST1B_4Z_IMM:
29822 case AArch64::ST1D_4Z_IMM:
29823 case AArch64::ST1H_4Z_IMM:
29824 case AArch64::ST1W_4Z_IMM:
29825 case AArch64::STNT1B_4Z_IMM:
29826 case AArch64::STNT1D_4Z_IMM:
29827 case AArch64::STNT1H_4Z_IMM:
29828 case AArch64::STNT1W_4Z_IMM: {
29829 switch (OpNum) {
29830 case 0:
29831 // op: Zt
29832 return 2;
29833 case 2:
29834 // op: Rn
29835 return 5;
29836 case 1:
29837 // op: PNg
29838 return 10;
29839 case 3:
29840 // op: imm4
29841 return 16;
29842 }
29843 break;
29844 }
29845 case AArch64::LD1B_4Z:
29846 case AArch64::LD1D_4Z:
29847 case AArch64::LD1H_4Z:
29848 case AArch64::LD1W_4Z:
29849 case AArch64::LDNT1B_4Z:
29850 case AArch64::LDNT1D_4Z:
29851 case AArch64::LDNT1H_4Z:
29852 case AArch64::LDNT1W_4Z:
29853 case AArch64::ST1B_4Z:
29854 case AArch64::ST1D_4Z:
29855 case AArch64::ST1H_4Z:
29856 case AArch64::ST1W_4Z:
29857 case AArch64::STNT1B_4Z:
29858 case AArch64::STNT1D_4Z:
29859 case AArch64::STNT1H_4Z:
29860 case AArch64::STNT1W_4Z: {
29861 switch (OpNum) {
29862 case 0:
29863 // op: Zt
29864 return 2;
29865 case 3:
29866 // op: Rm
29867 return 16;
29868 case 2:
29869 // op: Rn
29870 return 5;
29871 case 1:
29872 // op: PNg
29873 return 10;
29874 }
29875 break;
29876 }
29877 case AArch64::B:
29878 case AArch64::BL: {
29879 switch (OpNum) {
29880 case 0:
29881 // op: addr
29882 return 0;
29883 }
29884 break;
29885 }
29886 case AArch64::BCcc:
29887 case AArch64::Bcc: {
29888 switch (OpNum) {
29889 case 0:
29890 // op: cond
29891 return 0;
29892 case 1:
29893 // op: target
29894 return 5;
29895 }
29896 break;
29897 }
29898 case AArch64::DUPi8: {
29899 switch (OpNum) {
29900 case 0:
29901 // op: dst
29902 return 0;
29903 case 1:
29904 // op: src
29905 return 5;
29906 case 2:
29907 // op: idx
29908 return 17;
29909 }
29910 break;
29911 }
29912 case AArch64::DUPi16: {
29913 switch (OpNum) {
29914 case 0:
29915 // op: dst
29916 return 0;
29917 case 1:
29918 // op: src
29919 return 5;
29920 case 2:
29921 // op: idx
29922 return 18;
29923 }
29924 break;
29925 }
29926 case AArch64::DUPi32: {
29927 switch (OpNum) {
29928 case 0:
29929 // op: dst
29930 return 0;
29931 case 1:
29932 // op: src
29933 return 5;
29934 case 2:
29935 // op: idx
29936 return 19;
29937 }
29938 break;
29939 }
29940 case AArch64::DUPi64: {
29941 switch (OpNum) {
29942 case 0:
29943 // op: dst
29944 return 0;
29945 case 1:
29946 // op: src
29947 return 5;
29948 case 2:
29949 // op: idx
29950 return 20;
29951 }
29952 break;
29953 }
29954 case AArch64::UDF:
29955 case AArch64::ZERO_M: {
29956 switch (OpNum) {
29957 case 0:
29958 // op: imm
29959 return 0;
29960 }
29961 break;
29962 }
29963 case AArch64::BRK:
29964 case AArch64::DCPS1:
29965 case AArch64::DCPS2:
29966 case AArch64::DCPS3:
29967 case AArch64::HINT:
29968 case AArch64::HLT:
29969 case AArch64::HVC:
29970 case AArch64::SMC:
29971 case AArch64::SVC:
29972 case AArch64::TCANCEL: {
29973 switch (OpNum) {
29974 case 0:
29975 // op: imm
29976 return 5;
29977 }
29978 break;
29979 }
29980 case AArch64::AUTIASPPCi:
29981 case AArch64::AUTIBSPPCi:
29982 case AArch64::RETAASPPCi:
29983 case AArch64::RETABSPPCi: {
29984 switch (OpNum) {
29985 case 0:
29986 // op: label
29987 return 5;
29988 }
29989 break;
29990 }
29991 case AArch64::SYSPxt_XZR: {
29992 switch (OpNum) {
29993 case 0:
29994 // op: op1
29995 return 16;
29996 case 1:
29997 // op: Cn
29998 return 12;
29999 case 2:
30000 // op: Cm
30001 return 8;
30002 case 3:
30003 // op: op2
30004 return 5;
30005 }
30006 break;
30007 }
30008 case AArch64::MSRpstateImm1:
30009 case AArch64::MSRpstateImm4: {
30010 switch (OpNum) {
30011 case 0:
30012 // op: pstatefield
30013 return 5;
30014 case 1:
30015 // op: imm
30016 return 8;
30017 }
30018 break;
30019 }
30020 case AArch64::MSRpstatesvcrImm1: {
30021 switch (OpNum) {
30022 case 0:
30023 // op: pstatefield
30024 return 9;
30025 case 1:
30026 // op: imm
30027 return 8;
30028 }
30029 break;
30030 }
30031 case AArch64::SEL_VG2_2ZC2Z2Z_B:
30032 case AArch64::SEL_VG2_2ZC2Z2Z_D:
30033 case AArch64::SEL_VG2_2ZC2Z2Z_H:
30034 case AArch64::SEL_VG2_2ZC2Z2Z_S: {
30035 switch (OpNum) {
30036 case 1:
30037 // op: PNg
30038 return 10;
30039 case 3:
30040 // op: Zm
30041 return 17;
30042 case 2:
30043 // op: Zn
30044 return 6;
30045 case 0:
30046 // op: Zd
30047 return 1;
30048 }
30049 break;
30050 }
30051 case AArch64::SEL_VG4_4ZC4Z4Z_B:
30052 case AArch64::SEL_VG4_4ZC4Z4Z_D:
30053 case AArch64::SEL_VG4_4ZC4Z4Z_H:
30054 case AArch64::SEL_VG4_4ZC4Z4Z_S: {
30055 switch (OpNum) {
30056 case 1:
30057 // op: PNg
30058 return 10;
30059 case 3:
30060 // op: Zm
30061 return 18;
30062 case 2:
30063 // op: Zn
30064 return 7;
30065 case 0:
30066 // op: Zd
30067 return 2;
30068 }
30069 break;
30070 }
30071 case AArch64::LASTA_RPZ_B:
30072 case AArch64::LASTA_RPZ_D:
30073 case AArch64::LASTA_RPZ_H:
30074 case AArch64::LASTA_RPZ_S:
30075 case AArch64::LASTB_RPZ_B:
30076 case AArch64::LASTB_RPZ_D:
30077 case AArch64::LASTB_RPZ_H:
30078 case AArch64::LASTB_RPZ_S: {
30079 switch (OpNum) {
30080 case 1:
30081 // op: Pg
30082 return 10;
30083 case 0:
30084 // op: Rd
30085 return 0;
30086 case 2:
30087 // op: Zn
30088 return 5;
30089 }
30090 break;
30091 }
30092 case AArch64::CLASTA_RPZ_B:
30093 case AArch64::CLASTA_RPZ_D:
30094 case AArch64::CLASTA_RPZ_H:
30095 case AArch64::CLASTA_RPZ_S:
30096 case AArch64::CLASTB_RPZ_B:
30097 case AArch64::CLASTB_RPZ_D:
30098 case AArch64::CLASTB_RPZ_H:
30099 case AArch64::CLASTB_RPZ_S: {
30100 switch (OpNum) {
30101 case 1:
30102 // op: Pg
30103 return 10;
30104 case 0:
30105 // op: Rdn
30106 return 0;
30107 case 3:
30108 // op: Zm
30109 return 5;
30110 }
30111 break;
30112 }
30113 case AArch64::ANDV_VPZ_B:
30114 case AArch64::ANDV_VPZ_D:
30115 case AArch64::ANDV_VPZ_H:
30116 case AArch64::ANDV_VPZ_S:
30117 case AArch64::EORV_VPZ_B:
30118 case AArch64::EORV_VPZ_D:
30119 case AArch64::EORV_VPZ_H:
30120 case AArch64::EORV_VPZ_S:
30121 case AArch64::LASTA_VPZ_B:
30122 case AArch64::LASTA_VPZ_D:
30123 case AArch64::LASTA_VPZ_H:
30124 case AArch64::LASTA_VPZ_S:
30125 case AArch64::LASTB_VPZ_B:
30126 case AArch64::LASTB_VPZ_D:
30127 case AArch64::LASTB_VPZ_H:
30128 case AArch64::LASTB_VPZ_S:
30129 case AArch64::ORV_VPZ_B:
30130 case AArch64::ORV_VPZ_D:
30131 case AArch64::ORV_VPZ_H:
30132 case AArch64::ORV_VPZ_S:
30133 case AArch64::SADDV_VPZ_B:
30134 case AArch64::SADDV_VPZ_H:
30135 case AArch64::SADDV_VPZ_S:
30136 case AArch64::SMAXV_VPZ_B:
30137 case AArch64::SMAXV_VPZ_D:
30138 case AArch64::SMAXV_VPZ_H:
30139 case AArch64::SMAXV_VPZ_S:
30140 case AArch64::SMINV_VPZ_B:
30141 case AArch64::SMINV_VPZ_D:
30142 case AArch64::SMINV_VPZ_H:
30143 case AArch64::SMINV_VPZ_S:
30144 case AArch64::UADDV_VPZ_B:
30145 case AArch64::UADDV_VPZ_D:
30146 case AArch64::UADDV_VPZ_H:
30147 case AArch64::UADDV_VPZ_S:
30148 case AArch64::UMAXV_VPZ_B:
30149 case AArch64::UMAXV_VPZ_D:
30150 case AArch64::UMAXV_VPZ_H:
30151 case AArch64::UMAXV_VPZ_S:
30152 case AArch64::UMINV_VPZ_B:
30153 case AArch64::UMINV_VPZ_D:
30154 case AArch64::UMINV_VPZ_H:
30155 case AArch64::UMINV_VPZ_S: {
30156 switch (OpNum) {
30157 case 1:
30158 // op: Pg
30159 return 10;
30160 case 0:
30161 // op: Vd
30162 return 0;
30163 case 2:
30164 // op: Zn
30165 return 5;
30166 }
30167 break;
30168 }
30169 case AArch64::CLASTA_VPZ_B:
30170 case AArch64::CLASTA_VPZ_D:
30171 case AArch64::CLASTA_VPZ_H:
30172 case AArch64::CLASTA_VPZ_S:
30173 case AArch64::CLASTB_VPZ_B:
30174 case AArch64::CLASTB_VPZ_D:
30175 case AArch64::CLASTB_VPZ_H:
30176 case AArch64::CLASTB_VPZ_S:
30177 case AArch64::FADDA_VPZ_D:
30178 case AArch64::FADDA_VPZ_H:
30179 case AArch64::FADDA_VPZ_S: {
30180 switch (OpNum) {
30181 case 1:
30182 // op: Pg
30183 return 10;
30184 case 0:
30185 // op: Vdn
30186 return 0;
30187 case 3:
30188 // op: Zm
30189 return 5;
30190 }
30191 break;
30192 }
30193 case AArch64::COMPACT_ZPZ_D:
30194 case AArch64::COMPACT_ZPZ_S:
30195 case AArch64::MOVPRFX_ZPzZ_B:
30196 case AArch64::MOVPRFX_ZPzZ_D:
30197 case AArch64::MOVPRFX_ZPzZ_H:
30198 case AArch64::MOVPRFX_ZPzZ_S: {
30199 switch (OpNum) {
30200 case 1:
30201 // op: Pg
30202 return 10;
30203 case 0:
30204 // op: Zd
30205 return 0;
30206 case 2:
30207 // op: Zn
30208 return 5;
30209 }
30210 break;
30211 }
30212 case AArch64::SEL_ZPZZ_B:
30213 case AArch64::SEL_ZPZZ_D:
30214 case AArch64::SEL_ZPZZ_H:
30215 case AArch64::SEL_ZPZZ_S: {
30216 switch (OpNum) {
30217 case 1:
30218 // op: Pg
30219 return 10;
30220 case 0:
30221 // op: Zd
30222 return 0;
30223 case 3:
30224 // op: Zm
30225 return 16;
30226 case 2:
30227 // op: Zn
30228 return 5;
30229 }
30230 break;
30231 }
30232 case AArch64::BFMLA_ZPmZZ:
30233 case AArch64::BFMLS_ZPmZZ:
30234 case AArch64::FMLA_ZPmZZ_D:
30235 case AArch64::FMLA_ZPmZZ_H:
30236 case AArch64::FMLA_ZPmZZ_S:
30237 case AArch64::FMLS_ZPmZZ_D:
30238 case AArch64::FMLS_ZPmZZ_H:
30239 case AArch64::FMLS_ZPmZZ_S:
30240 case AArch64::FNMLA_ZPmZZ_D:
30241 case AArch64::FNMLA_ZPmZZ_H:
30242 case AArch64::FNMLA_ZPmZZ_S:
30243 case AArch64::FNMLS_ZPmZZ_D:
30244 case AArch64::FNMLS_ZPmZZ_H:
30245 case AArch64::FNMLS_ZPmZZ_S:
30246 case AArch64::MLA_ZPmZZ_B:
30247 case AArch64::MLA_ZPmZZ_D:
30248 case AArch64::MLA_ZPmZZ_H:
30249 case AArch64::MLA_ZPmZZ_S:
30250 case AArch64::MLS_ZPmZZ_B:
30251 case AArch64::MLS_ZPmZZ_D:
30252 case AArch64::MLS_ZPmZZ_H:
30253 case AArch64::MLS_ZPmZZ_S: {
30254 switch (OpNum) {
30255 case 1:
30256 // op: Pg
30257 return 10;
30258 case 0:
30259 // op: Zda
30260 return 0;
30261 case 4:
30262 // op: Zm
30263 return 16;
30264 case 3:
30265 // op: Zn
30266 return 5;
30267 }
30268 break;
30269 }
30270 case AArch64::ADD_ZPmZ_B:
30271 case AArch64::ADD_ZPmZ_CPA:
30272 case AArch64::ADD_ZPmZ_D:
30273 case AArch64::ADD_ZPmZ_H:
30274 case AArch64::ADD_ZPmZ_S:
30275 case AArch64::AND_ZPmZ_B:
30276 case AArch64::AND_ZPmZ_D:
30277 case AArch64::AND_ZPmZ_H:
30278 case AArch64::AND_ZPmZ_S:
30279 case AArch64::ASRR_ZPmZ_B:
30280 case AArch64::ASRR_ZPmZ_D:
30281 case AArch64::ASRR_ZPmZ_H:
30282 case AArch64::ASRR_ZPmZ_S:
30283 case AArch64::ASR_WIDE_ZPmZ_B:
30284 case AArch64::ASR_WIDE_ZPmZ_H:
30285 case AArch64::ASR_WIDE_ZPmZ_S:
30286 case AArch64::ASR_ZPmZ_B:
30287 case AArch64::ASR_ZPmZ_D:
30288 case AArch64::ASR_ZPmZ_H:
30289 case AArch64::ASR_ZPmZ_S:
30290 case AArch64::BFADD_ZPmZZ:
30291 case AArch64::BFMAXNM_ZPmZZ:
30292 case AArch64::BFMAX_ZPmZZ:
30293 case AArch64::BFMINNM_ZPmZZ:
30294 case AArch64::BFMIN_ZPmZZ:
30295 case AArch64::BFMUL_ZPmZZ:
30296 case AArch64::BFSUB_ZPmZZ:
30297 case AArch64::BIC_ZPmZ_B:
30298 case AArch64::BIC_ZPmZ_D:
30299 case AArch64::BIC_ZPmZ_H:
30300 case AArch64::BIC_ZPmZ_S:
30301 case AArch64::CLASTA_ZPZ_B:
30302 case AArch64::CLASTA_ZPZ_D:
30303 case AArch64::CLASTA_ZPZ_H:
30304 case AArch64::CLASTA_ZPZ_S:
30305 case AArch64::CLASTB_ZPZ_B:
30306 case AArch64::CLASTB_ZPZ_D:
30307 case AArch64::CLASTB_ZPZ_H:
30308 case AArch64::CLASTB_ZPZ_S:
30309 case AArch64::EOR_ZPmZ_B:
30310 case AArch64::EOR_ZPmZ_D:
30311 case AArch64::EOR_ZPmZ_H:
30312 case AArch64::EOR_ZPmZ_S:
30313 case AArch64::FABD_ZPmZ_D:
30314 case AArch64::FABD_ZPmZ_H:
30315 case AArch64::FABD_ZPmZ_S:
30316 case AArch64::FADD_ZPmZ_D:
30317 case AArch64::FADD_ZPmZ_H:
30318 case AArch64::FADD_ZPmZ_S:
30319 case AArch64::FAMAX_ZPmZ_D:
30320 case AArch64::FAMAX_ZPmZ_H:
30321 case AArch64::FAMAX_ZPmZ_S:
30322 case AArch64::FAMIN_ZPmZ_D:
30323 case AArch64::FAMIN_ZPmZ_H:
30324 case AArch64::FAMIN_ZPmZ_S:
30325 case AArch64::FDIVR_ZPmZ_D:
30326 case AArch64::FDIVR_ZPmZ_H:
30327 case AArch64::FDIVR_ZPmZ_S:
30328 case AArch64::FDIV_ZPmZ_D:
30329 case AArch64::FDIV_ZPmZ_H:
30330 case AArch64::FDIV_ZPmZ_S:
30331 case AArch64::FMAXNM_ZPmZ_D:
30332 case AArch64::FMAXNM_ZPmZ_H:
30333 case AArch64::FMAXNM_ZPmZ_S:
30334 case AArch64::FMAX_ZPmZ_D:
30335 case AArch64::FMAX_ZPmZ_H:
30336 case AArch64::FMAX_ZPmZ_S:
30337 case AArch64::FMINNM_ZPmZ_D:
30338 case AArch64::FMINNM_ZPmZ_H:
30339 case AArch64::FMINNM_ZPmZ_S:
30340 case AArch64::FMIN_ZPmZ_D:
30341 case AArch64::FMIN_ZPmZ_H:
30342 case AArch64::FMIN_ZPmZ_S:
30343 case AArch64::FMULX_ZPmZ_D:
30344 case AArch64::FMULX_ZPmZ_H:
30345 case AArch64::FMULX_ZPmZ_S:
30346 case AArch64::FMUL_ZPmZ_D:
30347 case AArch64::FMUL_ZPmZ_H:
30348 case AArch64::FMUL_ZPmZ_S:
30349 case AArch64::FSCALE_ZPmZ_D:
30350 case AArch64::FSCALE_ZPmZ_H:
30351 case AArch64::FSCALE_ZPmZ_S:
30352 case AArch64::FSUBR_ZPmZ_D:
30353 case AArch64::FSUBR_ZPmZ_H:
30354 case AArch64::FSUBR_ZPmZ_S:
30355 case AArch64::FSUB_ZPmZ_D:
30356 case AArch64::FSUB_ZPmZ_H:
30357 case AArch64::FSUB_ZPmZ_S:
30358 case AArch64::LSLR_ZPmZ_B:
30359 case AArch64::LSLR_ZPmZ_D:
30360 case AArch64::LSLR_ZPmZ_H:
30361 case AArch64::LSLR_ZPmZ_S:
30362 case AArch64::LSL_WIDE_ZPmZ_B:
30363 case AArch64::LSL_WIDE_ZPmZ_H:
30364 case AArch64::LSL_WIDE_ZPmZ_S:
30365 case AArch64::LSL_ZPmZ_B:
30366 case AArch64::LSL_ZPmZ_D:
30367 case AArch64::LSL_ZPmZ_H:
30368 case AArch64::LSL_ZPmZ_S:
30369 case AArch64::LSRR_ZPmZ_B:
30370 case AArch64::LSRR_ZPmZ_D:
30371 case AArch64::LSRR_ZPmZ_H:
30372 case AArch64::LSRR_ZPmZ_S:
30373 case AArch64::LSR_WIDE_ZPmZ_B:
30374 case AArch64::LSR_WIDE_ZPmZ_H:
30375 case AArch64::LSR_WIDE_ZPmZ_S:
30376 case AArch64::LSR_ZPmZ_B:
30377 case AArch64::LSR_ZPmZ_D:
30378 case AArch64::LSR_ZPmZ_H:
30379 case AArch64::LSR_ZPmZ_S:
30380 case AArch64::MUL_ZPmZ_B:
30381 case AArch64::MUL_ZPmZ_D:
30382 case AArch64::MUL_ZPmZ_H:
30383 case AArch64::MUL_ZPmZ_S:
30384 case AArch64::ORR_ZPmZ_B:
30385 case AArch64::ORR_ZPmZ_D:
30386 case AArch64::ORR_ZPmZ_H:
30387 case AArch64::ORR_ZPmZ_S:
30388 case AArch64::SABD_ZPmZ_B:
30389 case AArch64::SABD_ZPmZ_D:
30390 case AArch64::SABD_ZPmZ_H:
30391 case AArch64::SABD_ZPmZ_S:
30392 case AArch64::SDIVR_ZPmZ_D:
30393 case AArch64::SDIVR_ZPmZ_S:
30394 case AArch64::SDIV_ZPmZ_D:
30395 case AArch64::SDIV_ZPmZ_S:
30396 case AArch64::SMAX_ZPmZ_B:
30397 case AArch64::SMAX_ZPmZ_D:
30398 case AArch64::SMAX_ZPmZ_H:
30399 case AArch64::SMAX_ZPmZ_S:
30400 case AArch64::SMIN_ZPmZ_B:
30401 case AArch64::SMIN_ZPmZ_D:
30402 case AArch64::SMIN_ZPmZ_H:
30403 case AArch64::SMIN_ZPmZ_S:
30404 case AArch64::SMULH_ZPmZ_B:
30405 case AArch64::SMULH_ZPmZ_D:
30406 case AArch64::SMULH_ZPmZ_H:
30407 case AArch64::SMULH_ZPmZ_S:
30408 case AArch64::SPLICE_ZPZ_B:
30409 case AArch64::SPLICE_ZPZ_D:
30410 case AArch64::SPLICE_ZPZ_H:
30411 case AArch64::SPLICE_ZPZ_S:
30412 case AArch64::SUBR_ZPmZ_B:
30413 case AArch64::SUBR_ZPmZ_D:
30414 case AArch64::SUBR_ZPmZ_H:
30415 case AArch64::SUBR_ZPmZ_S:
30416 case AArch64::SUB_ZPmZ_B:
30417 case AArch64::SUB_ZPmZ_CPA:
30418 case AArch64::SUB_ZPmZ_D:
30419 case AArch64::SUB_ZPmZ_H:
30420 case AArch64::SUB_ZPmZ_S:
30421 case AArch64::UABD_ZPmZ_B:
30422 case AArch64::UABD_ZPmZ_D:
30423 case AArch64::UABD_ZPmZ_H:
30424 case AArch64::UABD_ZPmZ_S:
30425 case AArch64::UDIVR_ZPmZ_D:
30426 case AArch64::UDIVR_ZPmZ_S:
30427 case AArch64::UDIV_ZPmZ_D:
30428 case AArch64::UDIV_ZPmZ_S:
30429 case AArch64::UMAX_ZPmZ_B:
30430 case AArch64::UMAX_ZPmZ_D:
30431 case AArch64::UMAX_ZPmZ_H:
30432 case AArch64::UMAX_ZPmZ_S:
30433 case AArch64::UMIN_ZPmZ_B:
30434 case AArch64::UMIN_ZPmZ_D:
30435 case AArch64::UMIN_ZPmZ_H:
30436 case AArch64::UMIN_ZPmZ_S:
30437 case AArch64::UMULH_ZPmZ_B:
30438 case AArch64::UMULH_ZPmZ_D:
30439 case AArch64::UMULH_ZPmZ_H:
30440 case AArch64::UMULH_ZPmZ_S: {
30441 switch (OpNum) {
30442 case 1:
30443 // op: Pg
30444 return 10;
30445 case 0:
30446 // op: Zdn
30447 return 0;
30448 case 3:
30449 // op: Zm
30450 return 5;
30451 }
30452 break;
30453 }
30454 case AArch64::FADD_ZPmI_D:
30455 case AArch64::FADD_ZPmI_H:
30456 case AArch64::FADD_ZPmI_S:
30457 case AArch64::FMAXNM_ZPmI_D:
30458 case AArch64::FMAXNM_ZPmI_H:
30459 case AArch64::FMAXNM_ZPmI_S:
30460 case AArch64::FMAX_ZPmI_D:
30461 case AArch64::FMAX_ZPmI_H:
30462 case AArch64::FMAX_ZPmI_S:
30463 case AArch64::FMINNM_ZPmI_D:
30464 case AArch64::FMINNM_ZPmI_H:
30465 case AArch64::FMINNM_ZPmI_S:
30466 case AArch64::FMIN_ZPmI_D:
30467 case AArch64::FMIN_ZPmI_H:
30468 case AArch64::FMIN_ZPmI_S:
30469 case AArch64::FMUL_ZPmI_D:
30470 case AArch64::FMUL_ZPmI_H:
30471 case AArch64::FMUL_ZPmI_S:
30472 case AArch64::FSUBR_ZPmI_D:
30473 case AArch64::FSUBR_ZPmI_H:
30474 case AArch64::FSUBR_ZPmI_S:
30475 case AArch64::FSUB_ZPmI_D:
30476 case AArch64::FSUB_ZPmI_H:
30477 case AArch64::FSUB_ZPmI_S: {
30478 switch (OpNum) {
30479 case 1:
30480 // op: Pg
30481 return 10;
30482 case 0:
30483 // op: Zdn
30484 return 0;
30485 case 3:
30486 // op: i1
30487 return 5;
30488 }
30489 break;
30490 }
30491 case AArch64::ASRD_ZPmI_B:
30492 case AArch64::ASRD_ZPmI_D:
30493 case AArch64::ASRD_ZPmI_H:
30494 case AArch64::ASRD_ZPmI_S:
30495 case AArch64::ASR_ZPmI_B:
30496 case AArch64::ASR_ZPmI_D:
30497 case AArch64::ASR_ZPmI_H:
30498 case AArch64::ASR_ZPmI_S:
30499 case AArch64::LSL_ZPmI_B:
30500 case AArch64::LSL_ZPmI_D:
30501 case AArch64::LSL_ZPmI_H:
30502 case AArch64::LSL_ZPmI_S:
30503 case AArch64::LSR_ZPmI_B:
30504 case AArch64::LSR_ZPmI_D:
30505 case AArch64::LSR_ZPmI_H:
30506 case AArch64::LSR_ZPmI_S:
30507 case AArch64::SQSHLU_ZPmI_B:
30508 case AArch64::SQSHLU_ZPmI_D:
30509 case AArch64::SQSHLU_ZPmI_H:
30510 case AArch64::SQSHLU_ZPmI_S:
30511 case AArch64::SQSHL_ZPmI_B:
30512 case AArch64::SQSHL_ZPmI_D:
30513 case AArch64::SQSHL_ZPmI_H:
30514 case AArch64::SQSHL_ZPmI_S:
30515 case AArch64::SRSHR_ZPmI_B:
30516 case AArch64::SRSHR_ZPmI_D:
30517 case AArch64::SRSHR_ZPmI_H:
30518 case AArch64::SRSHR_ZPmI_S:
30519 case AArch64::UQSHL_ZPmI_B:
30520 case AArch64::UQSHL_ZPmI_D:
30521 case AArch64::UQSHL_ZPmI_H:
30522 case AArch64::UQSHL_ZPmI_S:
30523 case AArch64::URSHR_ZPmI_B:
30524 case AArch64::URSHR_ZPmI_D:
30525 case AArch64::URSHR_ZPmI_H:
30526 case AArch64::URSHR_ZPmI_S: {
30527 switch (OpNum) {
30528 case 1:
30529 // op: Pg
30530 return 10;
30531 case 0:
30532 // op: Zdn
30533 return 0;
30534 case 3:
30535 // op: imm
30536 return 5;
30537 }
30538 break;
30539 }
30540 case AArch64::MAD_ZPmZZ_B:
30541 case AArch64::MAD_ZPmZZ_D:
30542 case AArch64::MAD_ZPmZZ_H:
30543 case AArch64::MAD_ZPmZZ_S:
30544 case AArch64::MSB_ZPmZZ_B:
30545 case AArch64::MSB_ZPmZZ_D:
30546 case AArch64::MSB_ZPmZZ_H:
30547 case AArch64::MSB_ZPmZZ_S: {
30548 switch (OpNum) {
30549 case 1:
30550 // op: Pg
30551 return 10;
30552 case 0:
30553 // op: Zdn
30554 return 0;
30555 case 4:
30556 // op: Za
30557 return 5;
30558 case 3:
30559 // op: Zm
30560 return 16;
30561 }
30562 break;
30563 }
30564 case AArch64::CNTP_XPP_B:
30565 case AArch64::CNTP_XPP_D:
30566 case AArch64::CNTP_XPP_H:
30567 case AArch64::CNTP_XPP_S: {
30568 switch (OpNum) {
30569 case 1:
30570 // op: Pg
30571 return 10;
30572 case 2:
30573 // op: Pn
30574 return 5;
30575 case 0:
30576 // op: Rd
30577 return 0;
30578 }
30579 break;
30580 }
30581 case AArch64::LD1B_D_IMM:
30582 case AArch64::LD1B_H_IMM:
30583 case AArch64::LD1B_IMM:
30584 case AArch64::LD1B_S_IMM:
30585 case AArch64::LD1D_IMM:
30586 case AArch64::LD1H_D_IMM:
30587 case AArch64::LD1H_IMM:
30588 case AArch64::LD1H_S_IMM:
30589 case AArch64::LD1SB_D_IMM:
30590 case AArch64::LD1SB_H_IMM:
30591 case AArch64::LD1SB_S_IMM:
30592 case AArch64::LD1SH_D_IMM:
30593 case AArch64::LD1SH_S_IMM:
30594 case AArch64::LD1SW_D_IMM:
30595 case AArch64::LD1W_D_IMM:
30596 case AArch64::LD1W_IMM:
30597 case AArch64::LDNF1B_D_IMM:
30598 case AArch64::LDNF1B_H_IMM:
30599 case AArch64::LDNF1B_IMM:
30600 case AArch64::LDNF1B_S_IMM:
30601 case AArch64::LDNF1D_IMM:
30602 case AArch64::LDNF1H_D_IMM:
30603 case AArch64::LDNF1H_IMM:
30604 case AArch64::LDNF1H_S_IMM:
30605 case AArch64::LDNF1SB_D_IMM:
30606 case AArch64::LDNF1SB_H_IMM:
30607 case AArch64::LDNF1SB_S_IMM:
30608 case AArch64::LDNF1SH_D_IMM:
30609 case AArch64::LDNF1SH_S_IMM:
30610 case AArch64::LDNF1SW_D_IMM:
30611 case AArch64::LDNF1W_D_IMM:
30612 case AArch64::LDNF1W_IMM:
30613 case AArch64::ST1B_D_IMM:
30614 case AArch64::ST1B_H_IMM:
30615 case AArch64::ST1B_IMM:
30616 case AArch64::ST1B_S_IMM:
30617 case AArch64::ST1D_IMM:
30618 case AArch64::ST1D_Q_IMM:
30619 case AArch64::ST1H_D_IMM:
30620 case AArch64::ST1H_IMM:
30621 case AArch64::ST1H_S_IMM:
30622 case AArch64::ST1W_D_IMM:
30623 case AArch64::ST1W_IMM:
30624 case AArch64::ST1W_Q_IMM:
30625 case AArch64::ST2B_IMM:
30626 case AArch64::ST2D_IMM:
30627 case AArch64::ST2H_IMM:
30628 case AArch64::ST2W_IMM:
30629 case AArch64::ST3B_IMM:
30630 case AArch64::ST3D_IMM:
30631 case AArch64::ST3H_IMM:
30632 case AArch64::ST3W_IMM:
30633 case AArch64::ST4B_IMM:
30634 case AArch64::ST4D_IMM:
30635 case AArch64::ST4H_IMM:
30636 case AArch64::ST4W_IMM:
30637 case AArch64::STNT1B_ZRI:
30638 case AArch64::STNT1D_ZRI:
30639 case AArch64::STNT1H_ZRI:
30640 case AArch64::STNT1W_ZRI: {
30641 switch (OpNum) {
30642 case 1:
30643 // op: Pg
30644 return 10;
30645 case 2:
30646 // op: Rn
30647 return 5;
30648 case 0:
30649 // op: Zt
30650 return 0;
30651 case 3:
30652 // op: imm4
30653 return 16;
30654 }
30655 break;
30656 }
30657 case AArch64::LD1RB_D_IMM:
30658 case AArch64::LD1RB_H_IMM:
30659 case AArch64::LD1RB_IMM:
30660 case AArch64::LD1RB_S_IMM:
30661 case AArch64::LD1RD_IMM:
30662 case AArch64::LD1RH_D_IMM:
30663 case AArch64::LD1RH_IMM:
30664 case AArch64::LD1RH_S_IMM:
30665 case AArch64::LD1RSB_D_IMM:
30666 case AArch64::LD1RSB_H_IMM:
30667 case AArch64::LD1RSB_S_IMM:
30668 case AArch64::LD1RSH_D_IMM:
30669 case AArch64::LD1RSH_S_IMM:
30670 case AArch64::LD1RSW_IMM:
30671 case AArch64::LD1RW_D_IMM:
30672 case AArch64::LD1RW_IMM: {
30673 switch (OpNum) {
30674 case 1:
30675 // op: Pg
30676 return 10;
30677 case 2:
30678 // op: Rn
30679 return 5;
30680 case 0:
30681 // op: Zt
30682 return 0;
30683 case 3:
30684 // op: imm6
30685 return 16;
30686 }
30687 break;
30688 }
30689 case AArch64::GLD1B_D:
30690 case AArch64::GLD1B_D_SXTW:
30691 case AArch64::GLD1B_D_UXTW:
30692 case AArch64::GLD1B_S_SXTW:
30693 case AArch64::GLD1B_S_UXTW:
30694 case AArch64::GLD1D:
30695 case AArch64::GLD1D_SCALED:
30696 case AArch64::GLD1D_SXTW:
30697 case AArch64::GLD1D_SXTW_SCALED:
30698 case AArch64::GLD1D_UXTW:
30699 case AArch64::GLD1D_UXTW_SCALED:
30700 case AArch64::GLD1H_D:
30701 case AArch64::GLD1H_D_SCALED:
30702 case AArch64::GLD1H_D_SXTW:
30703 case AArch64::GLD1H_D_SXTW_SCALED:
30704 case AArch64::GLD1H_D_UXTW:
30705 case AArch64::GLD1H_D_UXTW_SCALED:
30706 case AArch64::GLD1H_S_SXTW:
30707 case AArch64::GLD1H_S_SXTW_SCALED:
30708 case AArch64::GLD1H_S_UXTW:
30709 case AArch64::GLD1H_S_UXTW_SCALED:
30710 case AArch64::GLD1SB_D:
30711 case AArch64::GLD1SB_D_SXTW:
30712 case AArch64::GLD1SB_D_UXTW:
30713 case AArch64::GLD1SB_S_SXTW:
30714 case AArch64::GLD1SB_S_UXTW:
30715 case AArch64::GLD1SH_D:
30716 case AArch64::GLD1SH_D_SCALED:
30717 case AArch64::GLD1SH_D_SXTW:
30718 case AArch64::GLD1SH_D_SXTW_SCALED:
30719 case AArch64::GLD1SH_D_UXTW:
30720 case AArch64::GLD1SH_D_UXTW_SCALED:
30721 case AArch64::GLD1SH_S_SXTW:
30722 case AArch64::GLD1SH_S_SXTW_SCALED:
30723 case AArch64::GLD1SH_S_UXTW:
30724 case AArch64::GLD1SH_S_UXTW_SCALED:
30725 case AArch64::GLD1SW_D:
30726 case AArch64::GLD1SW_D_SCALED:
30727 case AArch64::GLD1SW_D_SXTW:
30728 case AArch64::GLD1SW_D_SXTW_SCALED:
30729 case AArch64::GLD1SW_D_UXTW:
30730 case AArch64::GLD1SW_D_UXTW_SCALED:
30731 case AArch64::GLD1W_D:
30732 case AArch64::GLD1W_D_SCALED:
30733 case AArch64::GLD1W_D_SXTW:
30734 case AArch64::GLD1W_D_SXTW_SCALED:
30735 case AArch64::GLD1W_D_UXTW:
30736 case AArch64::GLD1W_D_UXTW_SCALED:
30737 case AArch64::GLD1W_SXTW:
30738 case AArch64::GLD1W_SXTW_SCALED:
30739 case AArch64::GLD1W_UXTW:
30740 case AArch64::GLD1W_UXTW_SCALED:
30741 case AArch64::GLDFF1B_D:
30742 case AArch64::GLDFF1B_D_SXTW:
30743 case AArch64::GLDFF1B_D_UXTW:
30744 case AArch64::GLDFF1B_S_SXTW:
30745 case AArch64::GLDFF1B_S_UXTW:
30746 case AArch64::GLDFF1D:
30747 case AArch64::GLDFF1D_SCALED:
30748 case AArch64::GLDFF1D_SXTW:
30749 case AArch64::GLDFF1D_SXTW_SCALED:
30750 case AArch64::GLDFF1D_UXTW:
30751 case AArch64::GLDFF1D_UXTW_SCALED:
30752 case AArch64::GLDFF1H_D:
30753 case AArch64::GLDFF1H_D_SCALED:
30754 case AArch64::GLDFF1H_D_SXTW:
30755 case AArch64::GLDFF1H_D_SXTW_SCALED:
30756 case AArch64::GLDFF1H_D_UXTW:
30757 case AArch64::GLDFF1H_D_UXTW_SCALED:
30758 case AArch64::GLDFF1H_S_SXTW:
30759 case AArch64::GLDFF1H_S_SXTW_SCALED:
30760 case AArch64::GLDFF1H_S_UXTW:
30761 case AArch64::GLDFF1H_S_UXTW_SCALED:
30762 case AArch64::GLDFF1SB_D:
30763 case AArch64::GLDFF1SB_D_SXTW:
30764 case AArch64::GLDFF1SB_D_UXTW:
30765 case AArch64::GLDFF1SB_S_SXTW:
30766 case AArch64::GLDFF1SB_S_UXTW:
30767 case AArch64::GLDFF1SH_D:
30768 case AArch64::GLDFF1SH_D_SCALED:
30769 case AArch64::GLDFF1SH_D_SXTW:
30770 case AArch64::GLDFF1SH_D_SXTW_SCALED:
30771 case AArch64::GLDFF1SH_D_UXTW:
30772 case AArch64::GLDFF1SH_D_UXTW_SCALED:
30773 case AArch64::GLDFF1SH_S_SXTW:
30774 case AArch64::GLDFF1SH_S_SXTW_SCALED:
30775 case AArch64::GLDFF1SH_S_UXTW:
30776 case AArch64::GLDFF1SH_S_UXTW_SCALED:
30777 case AArch64::GLDFF1SW_D:
30778 case AArch64::GLDFF1SW_D_SCALED:
30779 case AArch64::GLDFF1SW_D_SXTW:
30780 case AArch64::GLDFF1SW_D_SXTW_SCALED:
30781 case AArch64::GLDFF1SW_D_UXTW:
30782 case AArch64::GLDFF1SW_D_UXTW_SCALED:
30783 case AArch64::GLDFF1W_D:
30784 case AArch64::GLDFF1W_D_SCALED:
30785 case AArch64::GLDFF1W_D_SXTW:
30786 case AArch64::GLDFF1W_D_SXTW_SCALED:
30787 case AArch64::GLDFF1W_D_UXTW:
30788 case AArch64::GLDFF1W_D_UXTW_SCALED:
30789 case AArch64::GLDFF1W_SXTW:
30790 case AArch64::GLDFF1W_SXTW_SCALED:
30791 case AArch64::GLDFF1W_UXTW:
30792 case AArch64::GLDFF1W_UXTW_SCALED:
30793 case AArch64::SST1B_D:
30794 case AArch64::SST1B_D_SXTW:
30795 case AArch64::SST1B_D_UXTW:
30796 case AArch64::SST1B_S_SXTW:
30797 case AArch64::SST1B_S_UXTW:
30798 case AArch64::SST1D:
30799 case AArch64::SST1D_SCALED:
30800 case AArch64::SST1D_SXTW:
30801 case AArch64::SST1D_SXTW_SCALED:
30802 case AArch64::SST1D_UXTW:
30803 case AArch64::SST1D_UXTW_SCALED:
30804 case AArch64::SST1H_D:
30805 case AArch64::SST1H_D_SCALED:
30806 case AArch64::SST1H_D_SXTW:
30807 case AArch64::SST1H_D_SXTW_SCALED:
30808 case AArch64::SST1H_D_UXTW:
30809 case AArch64::SST1H_D_UXTW_SCALED:
30810 case AArch64::SST1H_S_SXTW:
30811 case AArch64::SST1H_S_SXTW_SCALED:
30812 case AArch64::SST1H_S_UXTW:
30813 case AArch64::SST1H_S_UXTW_SCALED:
30814 case AArch64::SST1W_D:
30815 case AArch64::SST1W_D_SCALED:
30816 case AArch64::SST1W_D_SXTW:
30817 case AArch64::SST1W_D_SXTW_SCALED:
30818 case AArch64::SST1W_D_UXTW:
30819 case AArch64::SST1W_D_UXTW_SCALED:
30820 case AArch64::SST1W_SXTW:
30821 case AArch64::SST1W_SXTW_SCALED:
30822 case AArch64::SST1W_UXTW:
30823 case AArch64::SST1W_UXTW_SCALED: {
30824 switch (OpNum) {
30825 case 1:
30826 // op: Pg
30827 return 10;
30828 case 2:
30829 // op: Rn
30830 return 5;
30831 case 3:
30832 // op: Zm
30833 return 16;
30834 case 0:
30835 // op: Zt
30836 return 0;
30837 }
30838 break;
30839 }
30840 case AArch64::PRFB_D_SCALED:
30841 case AArch64::PRFB_D_SXTW_SCALED:
30842 case AArch64::PRFB_D_UXTW_SCALED:
30843 case AArch64::PRFB_S_SXTW_SCALED:
30844 case AArch64::PRFB_S_UXTW_SCALED:
30845 case AArch64::PRFD_D_SCALED:
30846 case AArch64::PRFD_D_SXTW_SCALED:
30847 case AArch64::PRFD_D_UXTW_SCALED:
30848 case AArch64::PRFD_S_SXTW_SCALED:
30849 case AArch64::PRFD_S_UXTW_SCALED:
30850 case AArch64::PRFH_D_SCALED:
30851 case AArch64::PRFH_D_SXTW_SCALED:
30852 case AArch64::PRFH_D_UXTW_SCALED:
30853 case AArch64::PRFH_S_SXTW_SCALED:
30854 case AArch64::PRFH_S_UXTW_SCALED:
30855 case AArch64::PRFW_D_SCALED:
30856 case AArch64::PRFW_D_SXTW_SCALED:
30857 case AArch64::PRFW_D_UXTW_SCALED:
30858 case AArch64::PRFW_S_SXTW_SCALED:
30859 case AArch64::PRFW_S_UXTW_SCALED: {
30860 switch (OpNum) {
30861 case 1:
30862 // op: Pg
30863 return 10;
30864 case 2:
30865 // op: Rn
30866 return 5;
30867 case 3:
30868 // op: Zm
30869 return 16;
30870 case 0:
30871 // op: prfop
30872 return 0;
30873 }
30874 break;
30875 }
30876 case AArch64::SPLICE_ZPZZ_B:
30877 case AArch64::SPLICE_ZPZZ_D:
30878 case AArch64::SPLICE_ZPZZ_H:
30879 case AArch64::SPLICE_ZPZZ_S: {
30880 switch (OpNum) {
30881 case 1:
30882 // op: Pg
30883 return 10;
30884 case 2:
30885 // op: Zn
30886 return 5;
30887 case 0:
30888 // op: Zd
30889 return 0;
30890 }
30891 break;
30892 }
30893 case AArch64::GLD1B_D_IMM:
30894 case AArch64::GLD1B_S_IMM:
30895 case AArch64::GLD1D_IMM:
30896 case AArch64::GLD1H_D_IMM:
30897 case AArch64::GLD1H_S_IMM:
30898 case AArch64::GLD1SB_D_IMM:
30899 case AArch64::GLD1SB_S_IMM:
30900 case AArch64::GLD1SH_D_IMM:
30901 case AArch64::GLD1SH_S_IMM:
30902 case AArch64::GLD1SW_D_IMM:
30903 case AArch64::GLD1W_D_IMM:
30904 case AArch64::GLD1W_IMM:
30905 case AArch64::GLDFF1B_D_IMM:
30906 case AArch64::GLDFF1B_S_IMM:
30907 case AArch64::GLDFF1D_IMM:
30908 case AArch64::GLDFF1H_D_IMM:
30909 case AArch64::GLDFF1H_S_IMM:
30910 case AArch64::GLDFF1SB_D_IMM:
30911 case AArch64::GLDFF1SB_S_IMM:
30912 case AArch64::GLDFF1SH_D_IMM:
30913 case AArch64::GLDFF1SH_S_IMM:
30914 case AArch64::GLDFF1SW_D_IMM:
30915 case AArch64::GLDFF1W_D_IMM:
30916 case AArch64::GLDFF1W_IMM: {
30917 switch (OpNum) {
30918 case 1:
30919 // op: Pg
30920 return 10;
30921 case 2:
30922 // op: Zn
30923 return 5;
30924 case 0:
30925 // op: Zt
30926 return 0;
30927 case 3:
30928 // op: imm5
30929 return 16;
30930 }
30931 break;
30932 }
30933 case AArch64::PRFB_D_PZI:
30934 case AArch64::PRFB_S_PZI:
30935 case AArch64::PRFD_D_PZI:
30936 case AArch64::PRFD_S_PZI:
30937 case AArch64::PRFH_D_PZI:
30938 case AArch64::PRFH_S_PZI:
30939 case AArch64::PRFW_D_PZI:
30940 case AArch64::PRFW_S_PZI: {
30941 switch (OpNum) {
30942 case 1:
30943 // op: Pg
30944 return 10;
30945 case 2:
30946 // op: Zn
30947 return 5;
30948 case 3:
30949 // op: imm5
30950 return 16;
30951 case 0:
30952 // op: prfop
30953 return 0;
30954 }
30955 break;
30956 }
30957 case AArch64::LD2B:
30958 case AArch64::LD2D:
30959 case AArch64::LD2H:
30960 case AArch64::LD2Q:
30961 case AArch64::LD2W:
30962 case AArch64::LD3B:
30963 case AArch64::LD3D:
30964 case AArch64::LD3H:
30965 case AArch64::LD3Q:
30966 case AArch64::LD3W:
30967 case AArch64::LD4B:
30968 case AArch64::LD4D:
30969 case AArch64::LD4H:
30970 case AArch64::LD4Q:
30971 case AArch64::LD4W:
30972 case AArch64::LDNT1B_ZRR:
30973 case AArch64::LDNT1D_ZRR:
30974 case AArch64::LDNT1H_ZRR:
30975 case AArch64::LDNT1W_ZRR:
30976 case AArch64::ST1B:
30977 case AArch64::ST1B_D:
30978 case AArch64::ST1B_H:
30979 case AArch64::ST1B_S:
30980 case AArch64::ST1D:
30981 case AArch64::ST1D_Q:
30982 case AArch64::ST1H:
30983 case AArch64::ST1H_D:
30984 case AArch64::ST1H_S:
30985 case AArch64::ST1W:
30986 case AArch64::ST1W_D:
30987 case AArch64::ST1W_Q:
30988 case AArch64::ST2B:
30989 case AArch64::ST2D:
30990 case AArch64::ST2H:
30991 case AArch64::ST2W:
30992 case AArch64::ST3B:
30993 case AArch64::ST3D:
30994 case AArch64::ST3H:
30995 case AArch64::ST3W:
30996 case AArch64::ST4B:
30997 case AArch64::ST4D:
30998 case AArch64::ST4H:
30999 case AArch64::ST4W:
31000 case AArch64::STNT1B_ZRR:
31001 case AArch64::STNT1D_ZRR:
31002 case AArch64::STNT1H_ZRR:
31003 case AArch64::STNT1W_ZRR: {
31004 switch (OpNum) {
31005 case 1:
31006 // op: Pg
31007 return 10;
31008 case 3:
31009 // op: Rm
31010 return 16;
31011 case 2:
31012 // op: Rn
31013 return 5;
31014 case 0:
31015 // op: Zt
31016 return 0;
31017 }
31018 break;
31019 }
31020 case AArch64::LDNT1B_ZZR_D:
31021 case AArch64::LDNT1B_ZZR_S:
31022 case AArch64::LDNT1D_ZZR_D:
31023 case AArch64::LDNT1H_ZZR_D:
31024 case AArch64::LDNT1H_ZZR_S:
31025 case AArch64::LDNT1SB_ZZR_D:
31026 case AArch64::LDNT1SB_ZZR_S:
31027 case AArch64::LDNT1SH_ZZR_D:
31028 case AArch64::LDNT1SH_ZZR_S:
31029 case AArch64::LDNT1SW_ZZR_D:
31030 case AArch64::LDNT1W_ZZR_D:
31031 case AArch64::LDNT1W_ZZR_S:
31032 case AArch64::STNT1B_ZZR_D:
31033 case AArch64::STNT1B_ZZR_S:
31034 case AArch64::STNT1D_ZZR_D:
31035 case AArch64::STNT1H_ZZR_D:
31036 case AArch64::STNT1H_ZZR_S:
31037 case AArch64::STNT1W_ZZR_D:
31038 case AArch64::STNT1W_ZZR_S: {
31039 switch (OpNum) {
31040 case 1:
31041 // op: Pg
31042 return 10;
31043 case 3:
31044 // op: Rm
31045 return 16;
31046 case 2:
31047 // op: Zn
31048 return 5;
31049 case 0:
31050 // op: Zt
31051 return 0;
31052 }
31053 break;
31054 }
31055 case AArch64::ADDP_ZPmZ_B:
31056 case AArch64::ADDP_ZPmZ_D:
31057 case AArch64::ADDP_ZPmZ_H:
31058 case AArch64::ADDP_ZPmZ_S:
31059 case AArch64::FADDP_ZPmZZ_D:
31060 case AArch64::FADDP_ZPmZZ_H:
31061 case AArch64::FADDP_ZPmZZ_S:
31062 case AArch64::FMAXNMP_ZPmZZ_D:
31063 case AArch64::FMAXNMP_ZPmZZ_H:
31064 case AArch64::FMAXNMP_ZPmZZ_S:
31065 case AArch64::FMAXP_ZPmZZ_D:
31066 case AArch64::FMAXP_ZPmZZ_H:
31067 case AArch64::FMAXP_ZPmZZ_S:
31068 case AArch64::FMINNMP_ZPmZZ_D:
31069 case AArch64::FMINNMP_ZPmZZ_H:
31070 case AArch64::FMINNMP_ZPmZZ_S:
31071 case AArch64::FMINP_ZPmZZ_D:
31072 case AArch64::FMINP_ZPmZZ_H:
31073 case AArch64::FMINP_ZPmZZ_S:
31074 case AArch64::SHADD_ZPmZ_B:
31075 case AArch64::SHADD_ZPmZ_D:
31076 case AArch64::SHADD_ZPmZ_H:
31077 case AArch64::SHADD_ZPmZ_S:
31078 case AArch64::SHSUBR_ZPmZ_B:
31079 case AArch64::SHSUBR_ZPmZ_D:
31080 case AArch64::SHSUBR_ZPmZ_H:
31081 case AArch64::SHSUBR_ZPmZ_S:
31082 case AArch64::SHSUB_ZPmZ_B:
31083 case AArch64::SHSUB_ZPmZ_D:
31084 case AArch64::SHSUB_ZPmZ_H:
31085 case AArch64::SHSUB_ZPmZ_S:
31086 case AArch64::SMAXP_ZPmZ_B:
31087 case AArch64::SMAXP_ZPmZ_D:
31088 case AArch64::SMAXP_ZPmZ_H:
31089 case AArch64::SMAXP_ZPmZ_S:
31090 case AArch64::SMINP_ZPmZ_B:
31091 case AArch64::SMINP_ZPmZ_D:
31092 case AArch64::SMINP_ZPmZ_H:
31093 case AArch64::SMINP_ZPmZ_S:
31094 case AArch64::SQADD_ZPmZ_B:
31095 case AArch64::SQADD_ZPmZ_D:
31096 case AArch64::SQADD_ZPmZ_H:
31097 case AArch64::SQADD_ZPmZ_S:
31098 case AArch64::SQRSHLR_ZPmZ_B:
31099 case AArch64::SQRSHLR_ZPmZ_D:
31100 case AArch64::SQRSHLR_ZPmZ_H:
31101 case AArch64::SQRSHLR_ZPmZ_S:
31102 case AArch64::SQRSHL_ZPmZ_B:
31103 case AArch64::SQRSHL_ZPmZ_D:
31104 case AArch64::SQRSHL_ZPmZ_H:
31105 case AArch64::SQRSHL_ZPmZ_S:
31106 case AArch64::SQSHLR_ZPmZ_B:
31107 case AArch64::SQSHLR_ZPmZ_D:
31108 case AArch64::SQSHLR_ZPmZ_H:
31109 case AArch64::SQSHLR_ZPmZ_S:
31110 case AArch64::SQSHL_ZPmZ_B:
31111 case AArch64::SQSHL_ZPmZ_D:
31112 case AArch64::SQSHL_ZPmZ_H:
31113 case AArch64::SQSHL_ZPmZ_S:
31114 case AArch64::SQSUBR_ZPmZ_B:
31115 case AArch64::SQSUBR_ZPmZ_D:
31116 case AArch64::SQSUBR_ZPmZ_H:
31117 case AArch64::SQSUBR_ZPmZ_S:
31118 case AArch64::SQSUB_ZPmZ_B:
31119 case AArch64::SQSUB_ZPmZ_D:
31120 case AArch64::SQSUB_ZPmZ_H:
31121 case AArch64::SQSUB_ZPmZ_S:
31122 case AArch64::SRHADD_ZPmZ_B:
31123 case AArch64::SRHADD_ZPmZ_D:
31124 case AArch64::SRHADD_ZPmZ_H:
31125 case AArch64::SRHADD_ZPmZ_S:
31126 case AArch64::SRSHLR_ZPmZ_B:
31127 case AArch64::SRSHLR_ZPmZ_D:
31128 case AArch64::SRSHLR_ZPmZ_H:
31129 case AArch64::SRSHLR_ZPmZ_S:
31130 case AArch64::SRSHL_ZPmZ_B:
31131 case AArch64::SRSHL_ZPmZ_D:
31132 case AArch64::SRSHL_ZPmZ_H:
31133 case AArch64::SRSHL_ZPmZ_S:
31134 case AArch64::SUQADD_ZPmZ_B:
31135 case AArch64::SUQADD_ZPmZ_D:
31136 case AArch64::SUQADD_ZPmZ_H:
31137 case AArch64::SUQADD_ZPmZ_S:
31138 case AArch64::UHADD_ZPmZ_B:
31139 case AArch64::UHADD_ZPmZ_D:
31140 case AArch64::UHADD_ZPmZ_H:
31141 case AArch64::UHADD_ZPmZ_S:
31142 case AArch64::UHSUBR_ZPmZ_B:
31143 case AArch64::UHSUBR_ZPmZ_D:
31144 case AArch64::UHSUBR_ZPmZ_H:
31145 case AArch64::UHSUBR_ZPmZ_S:
31146 case AArch64::UHSUB_ZPmZ_B:
31147 case AArch64::UHSUB_ZPmZ_D:
31148 case AArch64::UHSUB_ZPmZ_H:
31149 case AArch64::UHSUB_ZPmZ_S:
31150 case AArch64::UMAXP_ZPmZ_B:
31151 case AArch64::UMAXP_ZPmZ_D:
31152 case AArch64::UMAXP_ZPmZ_H:
31153 case AArch64::UMAXP_ZPmZ_S:
31154 case AArch64::UMINP_ZPmZ_B:
31155 case AArch64::UMINP_ZPmZ_D:
31156 case AArch64::UMINP_ZPmZ_H:
31157 case AArch64::UMINP_ZPmZ_S:
31158 case AArch64::UQADD_ZPmZ_B:
31159 case AArch64::UQADD_ZPmZ_D:
31160 case AArch64::UQADD_ZPmZ_H:
31161 case AArch64::UQADD_ZPmZ_S:
31162 case AArch64::UQRSHLR_ZPmZ_B:
31163 case AArch64::UQRSHLR_ZPmZ_D:
31164 case AArch64::UQRSHLR_ZPmZ_H:
31165 case AArch64::UQRSHLR_ZPmZ_S:
31166 case AArch64::UQRSHL_ZPmZ_B:
31167 case AArch64::UQRSHL_ZPmZ_D:
31168 case AArch64::UQRSHL_ZPmZ_H:
31169 case AArch64::UQRSHL_ZPmZ_S:
31170 case AArch64::UQSHLR_ZPmZ_B:
31171 case AArch64::UQSHLR_ZPmZ_D:
31172 case AArch64::UQSHLR_ZPmZ_H:
31173 case AArch64::UQSHLR_ZPmZ_S:
31174 case AArch64::UQSHL_ZPmZ_B:
31175 case AArch64::UQSHL_ZPmZ_D:
31176 case AArch64::UQSHL_ZPmZ_H:
31177 case AArch64::UQSHL_ZPmZ_S:
31178 case AArch64::UQSUBR_ZPmZ_B:
31179 case AArch64::UQSUBR_ZPmZ_D:
31180 case AArch64::UQSUBR_ZPmZ_H:
31181 case AArch64::UQSUBR_ZPmZ_S:
31182 case AArch64::UQSUB_ZPmZ_B:
31183 case AArch64::UQSUB_ZPmZ_D:
31184 case AArch64::UQSUB_ZPmZ_H:
31185 case AArch64::UQSUB_ZPmZ_S:
31186 case AArch64::URHADD_ZPmZ_B:
31187 case AArch64::URHADD_ZPmZ_D:
31188 case AArch64::URHADD_ZPmZ_H:
31189 case AArch64::URHADD_ZPmZ_S:
31190 case AArch64::URSHLR_ZPmZ_B:
31191 case AArch64::URSHLR_ZPmZ_D:
31192 case AArch64::URSHLR_ZPmZ_H:
31193 case AArch64::URSHLR_ZPmZ_S:
31194 case AArch64::URSHL_ZPmZ_B:
31195 case AArch64::URSHL_ZPmZ_D:
31196 case AArch64::URSHL_ZPmZ_H:
31197 case AArch64::URSHL_ZPmZ_S:
31198 case AArch64::USQADD_ZPmZ_B:
31199 case AArch64::USQADD_ZPmZ_D:
31200 case AArch64::USQADD_ZPmZ_H:
31201 case AArch64::USQADD_ZPmZ_S: {
31202 switch (OpNum) {
31203 case 1:
31204 // op: Pg
31205 return 10;
31206 case 3:
31207 // op: Zm
31208 return 5;
31209 case 0:
31210 // op: Zdn
31211 return 0;
31212 }
31213 break;
31214 }
31215 case AArch64::SADALP_ZPmZ_D:
31216 case AArch64::SADALP_ZPmZ_H:
31217 case AArch64::SADALP_ZPmZ_S:
31218 case AArch64::UADALP_ZPmZ_D:
31219 case AArch64::UADALP_ZPmZ_H:
31220 case AArch64::UADALP_ZPmZ_S: {
31221 switch (OpNum) {
31222 case 1:
31223 // op: Pg
31224 return 10;
31225 case 3:
31226 // op: Zn
31227 return 5;
31228 case 0:
31229 // op: Zda
31230 return 0;
31231 }
31232 break;
31233 }
31234 case AArch64::SST1B_D_IMM:
31235 case AArch64::SST1B_S_IMM:
31236 case AArch64::SST1D_IMM:
31237 case AArch64::SST1H_D_IMM:
31238 case AArch64::SST1H_S_IMM:
31239 case AArch64::SST1W_D_IMM:
31240 case AArch64::SST1W_IMM: {
31241 switch (OpNum) {
31242 case 1:
31243 // op: Pg
31244 return 10;
31245 case 3:
31246 // op: imm5
31247 return 16;
31248 case 2:
31249 // op: Zn
31250 return 5;
31251 case 0:
31252 // op: Zt
31253 return 0;
31254 }
31255 break;
31256 }
31257 case AArch64::FMAD_ZPmZZ_D:
31258 case AArch64::FMAD_ZPmZZ_H:
31259 case AArch64::FMAD_ZPmZZ_S:
31260 case AArch64::FMSB_ZPmZZ_D:
31261 case AArch64::FMSB_ZPmZZ_H:
31262 case AArch64::FMSB_ZPmZZ_S:
31263 case AArch64::FNMAD_ZPmZZ_D:
31264 case AArch64::FNMAD_ZPmZZ_H:
31265 case AArch64::FNMAD_ZPmZZ_S:
31266 case AArch64::FNMSB_ZPmZZ_D:
31267 case AArch64::FNMSB_ZPmZZ_H:
31268 case AArch64::FNMSB_ZPmZZ_S: {
31269 switch (OpNum) {
31270 case 1:
31271 // op: Pg
31272 return 10;
31273 case 4:
31274 // op: Za
31275 return 16;
31276 case 0:
31277 // op: Zdn
31278 return 0;
31279 case 3:
31280 // op: Zm
31281 return 5;
31282 }
31283 break;
31284 }
31285 case AArch64::BF16DOTlanev4bf16:
31286 case AArch64::BF16DOTlanev8bf16:
31287 case AArch64::BFMLALBIdx:
31288 case AArch64::BFMLALTIdx:
31289 case AArch64::FDOTlanev4f16:
31290 case AArch64::FDOTlanev8f8:
31291 case AArch64::FDOTlanev8f16:
31292 case AArch64::FDOTlanev16f8:
31293 case AArch64::FMLAL2lanev4f16:
31294 case AArch64::FMLAL2lanev8f16:
31295 case AArch64::FMLALBlanev8f16:
31296 case AArch64::FMLALLBBlanev4f32:
31297 case AArch64::FMLALLBTlanev4f32:
31298 case AArch64::FMLALLTBlanev4f32:
31299 case AArch64::FMLALLTTlanev4f32:
31300 case AArch64::FMLALTlanev8f16:
31301 case AArch64::FMLALlanev4f16:
31302 case AArch64::FMLALlanev8f16:
31303 case AArch64::FMLAv1i16_indexed:
31304 case AArch64::FMLAv1i32_indexed:
31305 case AArch64::FMLAv1i64_indexed:
31306 case AArch64::FMLAv2i32_indexed:
31307 case AArch64::FMLAv2i64_indexed:
31308 case AArch64::FMLAv4i16_indexed:
31309 case AArch64::FMLAv4i32_indexed:
31310 case AArch64::FMLAv8i16_indexed:
31311 case AArch64::FMLSL2lanev4f16:
31312 case AArch64::FMLSL2lanev8f16:
31313 case AArch64::FMLSLlanev4f16:
31314 case AArch64::FMLSLlanev8f16:
31315 case AArch64::FMLSv1i16_indexed:
31316 case AArch64::FMLSv1i32_indexed:
31317 case AArch64::FMLSv1i64_indexed:
31318 case AArch64::FMLSv2i32_indexed:
31319 case AArch64::FMLSv2i64_indexed:
31320 case AArch64::FMLSv4i16_indexed:
31321 case AArch64::FMLSv4i32_indexed:
31322 case AArch64::FMLSv8i16_indexed:
31323 case AArch64::MLAv2i32_indexed:
31324 case AArch64::MLAv4i16_indexed:
31325 case AArch64::MLAv4i32_indexed:
31326 case AArch64::MLAv8i16_indexed:
31327 case AArch64::MLSv2i32_indexed:
31328 case AArch64::MLSv4i16_indexed:
31329 case AArch64::MLSv4i32_indexed:
31330 case AArch64::MLSv8i16_indexed:
31331 case AArch64::SDOTlanev8i8:
31332 case AArch64::SDOTlanev16i8:
31333 case AArch64::SMLALv2i32_indexed:
31334 case AArch64::SMLALv4i16_indexed:
31335 case AArch64::SMLALv4i32_indexed:
31336 case AArch64::SMLALv8i16_indexed:
31337 case AArch64::SMLSLv2i32_indexed:
31338 case AArch64::SMLSLv4i16_indexed:
31339 case AArch64::SMLSLv4i32_indexed:
31340 case AArch64::SMLSLv8i16_indexed:
31341 case AArch64::SQDMLALv1i32_indexed:
31342 case AArch64::SQDMLALv1i64_indexed:
31343 case AArch64::SQDMLALv2i32_indexed:
31344 case AArch64::SQDMLALv4i16_indexed:
31345 case AArch64::SQDMLALv4i32_indexed:
31346 case AArch64::SQDMLALv8i16_indexed:
31347 case AArch64::SQDMLSLv1i32_indexed:
31348 case AArch64::SQDMLSLv1i64_indexed:
31349 case AArch64::SQDMLSLv2i32_indexed:
31350 case AArch64::SQDMLSLv4i16_indexed:
31351 case AArch64::SQDMLSLv4i32_indexed:
31352 case AArch64::SQDMLSLv8i16_indexed:
31353 case AArch64::SQRDMLAHv1i16_indexed:
31354 case AArch64::SQRDMLAHv1i32_indexed:
31355 case AArch64::SQRDMLAHv2i32_indexed:
31356 case AArch64::SQRDMLAHv4i16_indexed:
31357 case AArch64::SQRDMLAHv4i32_indexed:
31358 case AArch64::SQRDMLAHv8i16_indexed:
31359 case AArch64::SQRDMLSHv1i16_indexed:
31360 case AArch64::SQRDMLSHv1i32_indexed:
31361 case AArch64::SQRDMLSHv2i32_indexed:
31362 case AArch64::SQRDMLSHv4i16_indexed:
31363 case AArch64::SQRDMLSHv4i32_indexed:
31364 case AArch64::SQRDMLSHv8i16_indexed:
31365 case AArch64::SUDOTlanev8i8:
31366 case AArch64::SUDOTlanev16i8:
31367 case AArch64::UDOTlanev8i8:
31368 case AArch64::UDOTlanev16i8:
31369 case AArch64::UMLALv2i32_indexed:
31370 case AArch64::UMLALv4i16_indexed:
31371 case AArch64::UMLALv4i32_indexed:
31372 case AArch64::UMLALv8i16_indexed:
31373 case AArch64::UMLSLv2i32_indexed:
31374 case AArch64::UMLSLv4i16_indexed:
31375 case AArch64::UMLSLv4i32_indexed:
31376 case AArch64::UMLSLv8i16_indexed:
31377 case AArch64::USDOTlanev8i8:
31378 case AArch64::USDOTlanev16i8: {
31379 switch (OpNum) {
31380 case 1:
31381 // op: Rd
31382 return 0;
31383 case 2:
31384 // op: Rn
31385 return 5;
31386 case 3:
31387 // op: Rm
31388 return 16;
31389 case 4:
31390 // op: idx
31391 return 11;
31392 }
31393 break;
31394 }
31395 case AArch64::FCMLAv2f32:
31396 case AArch64::FCMLAv2f64:
31397 case AArch64::FCMLAv4f16:
31398 case AArch64::FCMLAv4f32:
31399 case AArch64::FCMLAv8f16: {
31400 switch (OpNum) {
31401 case 1:
31402 // op: Rd
31403 return 0;
31404 case 2:
31405 // op: Rn
31406 return 5;
31407 case 3:
31408 // op: Rm
31409 return 16;
31410 case 4:
31411 // op: rot
31412 return 11;
31413 }
31414 break;
31415 }
31416 case AArch64::FCMLAv4f32_indexed:
31417 case AArch64::FCMLAv8f16_indexed: {
31418 switch (OpNum) {
31419 case 1:
31420 // op: Rd
31421 return 0;
31422 case 2:
31423 // op: Rn
31424 return 5;
31425 case 3:
31426 // op: Rm
31427 return 16;
31428 case 5:
31429 // op: rot
31430 return 13;
31431 case 4:
31432 // op: idx
31433 return 11;
31434 }
31435 break;
31436 }
31437 case AArch64::FCMLAv4f16_indexed: {
31438 switch (OpNum) {
31439 case 1:
31440 // op: Rd
31441 return 0;
31442 case 2:
31443 // op: Rn
31444 return 5;
31445 case 3:
31446 // op: Rm
31447 return 16;
31448 case 5:
31449 // op: rot
31450 return 13;
31451 case 4:
31452 // op: idx
31453 return 21;
31454 }
31455 break;
31456 }
31457 case AArch64::ADDHNv2i64_v4i32:
31458 case AArch64::ADDHNv4i32_v8i16:
31459 case AArch64::ADDHNv8i16_v16i8:
31460 case AArch64::BFDOTv4bf16:
31461 case AArch64::BFDOTv8bf16:
31462 case AArch64::BFMLALB:
31463 case AArch64::BFMLALT:
31464 case AArch64::BFMMLA:
31465 case AArch64::BIFv8i8:
31466 case AArch64::BIFv16i8:
31467 case AArch64::BITv8i8:
31468 case AArch64::BITv16i8:
31469 case AArch64::BSLv8i8:
31470 case AArch64::BSLv16i8:
31471 case AArch64::FCVTN_F32_F82v16f8:
31472 case AArch64::FDOTv2f32:
31473 case AArch64::FDOTv4f16:
31474 case AArch64::FDOTv4f32:
31475 case AArch64::FDOTv8f16:
31476 case AArch64::FMLAL2v4f16:
31477 case AArch64::FMLAL2v8f16:
31478 case AArch64::FMLALBv8f16:
31479 case AArch64::FMLALLBBv4f32:
31480 case AArch64::FMLALLBTv4f32:
31481 case AArch64::FMLALLTBv4f32:
31482 case AArch64::FMLALLTTv4f32:
31483 case AArch64::FMLALTv8f16:
31484 case AArch64::FMLALv4f16:
31485 case AArch64::FMLALv8f16:
31486 case AArch64::FMLAv2f32:
31487 case AArch64::FMLAv2f64:
31488 case AArch64::FMLAv4f16:
31489 case AArch64::FMLAv4f32:
31490 case AArch64::FMLAv8f16:
31491 case AArch64::FMLSL2v4f16:
31492 case AArch64::FMLSL2v8f16:
31493 case AArch64::FMLSLv4f16:
31494 case AArch64::FMLSLv8f16:
31495 case AArch64::FMLSv2f32:
31496 case AArch64::FMLSv2f64:
31497 case AArch64::FMLSv4f16:
31498 case AArch64::FMLSv4f32:
31499 case AArch64::FMLSv8f16:
31500 case AArch64::MLAv2i32:
31501 case AArch64::MLAv4i16:
31502 case AArch64::MLAv4i32:
31503 case AArch64::MLAv8i8:
31504 case AArch64::MLAv8i16:
31505 case AArch64::MLAv16i8:
31506 case AArch64::MLSv2i32:
31507 case AArch64::MLSv4i16:
31508 case AArch64::MLSv4i32:
31509 case AArch64::MLSv8i8:
31510 case AArch64::MLSv8i16:
31511 case AArch64::MLSv16i8:
31512 case AArch64::RADDHNv2i64_v4i32:
31513 case AArch64::RADDHNv4i32_v8i16:
31514 case AArch64::RADDHNv8i16_v16i8:
31515 case AArch64::RSUBHNv2i64_v4i32:
31516 case AArch64::RSUBHNv4i32_v8i16:
31517 case AArch64::RSUBHNv8i16_v16i8:
31518 case AArch64::SABALv2i32_v2i64:
31519 case AArch64::SABALv4i16_v4i32:
31520 case AArch64::SABALv4i32_v2i64:
31521 case AArch64::SABALv8i8_v8i16:
31522 case AArch64::SABALv8i16_v4i32:
31523 case AArch64::SABALv16i8_v8i16:
31524 case AArch64::SABAv2i32:
31525 case AArch64::SABAv4i16:
31526 case AArch64::SABAv4i32:
31527 case AArch64::SABAv8i8:
31528 case AArch64::SABAv8i16:
31529 case AArch64::SABAv16i8:
31530 case AArch64::SDOTv8i8:
31531 case AArch64::SDOTv16i8:
31532 case AArch64::SHA1Crrr:
31533 case AArch64::SHA1Mrrr:
31534 case AArch64::SHA1Prrr:
31535 case AArch64::SHA1SU0rrr:
31536 case AArch64::SHA256H2rrr:
31537 case AArch64::SHA256Hrrr:
31538 case AArch64::SHA256SU1rrr:
31539 case AArch64::SMLALv2i32_v2i64:
31540 case AArch64::SMLALv4i16_v4i32:
31541 case AArch64::SMLALv4i32_v2i64:
31542 case AArch64::SMLALv8i8_v8i16:
31543 case AArch64::SMLALv8i16_v4i32:
31544 case AArch64::SMLALv16i8_v8i16:
31545 case AArch64::SMLSLv2i32_v2i64:
31546 case AArch64::SMLSLv4i16_v4i32:
31547 case AArch64::SMLSLv4i32_v2i64:
31548 case AArch64::SMLSLv8i8_v8i16:
31549 case AArch64::SMLSLv8i16_v4i32:
31550 case AArch64::SMLSLv16i8_v8i16:
31551 case AArch64::SMMLA:
31552 case AArch64::SQDMLALi16:
31553 case AArch64::SQDMLALi32:
31554 case AArch64::SQDMLALv2i32_v2i64:
31555 case AArch64::SQDMLALv4i16_v4i32:
31556 case AArch64::SQDMLALv4i32_v2i64:
31557 case AArch64::SQDMLALv8i16_v4i32:
31558 case AArch64::SQDMLSLi16:
31559 case AArch64::SQDMLSLi32:
31560 case AArch64::SQDMLSLv2i32_v2i64:
31561 case AArch64::SQDMLSLv4i16_v4i32:
31562 case AArch64::SQDMLSLv4i32_v2i64:
31563 case AArch64::SQDMLSLv8i16_v4i32:
31564 case AArch64::SQRDMLAHv1i16:
31565 case AArch64::SQRDMLAHv1i32:
31566 case AArch64::SQRDMLAHv2i32:
31567 case AArch64::SQRDMLAHv4i16:
31568 case AArch64::SQRDMLAHv4i32:
31569 case AArch64::SQRDMLAHv8i16:
31570 case AArch64::SQRDMLSHv1i16:
31571 case AArch64::SQRDMLSHv1i32:
31572 case AArch64::SQRDMLSHv2i32:
31573 case AArch64::SQRDMLSHv4i16:
31574 case AArch64::SQRDMLSHv4i32:
31575 case AArch64::SQRDMLSHv8i16:
31576 case AArch64::SUBHNv2i64_v4i32:
31577 case AArch64::SUBHNv4i32_v8i16:
31578 case AArch64::SUBHNv8i16_v16i8:
31579 case AArch64::UABALv2i32_v2i64:
31580 case AArch64::UABALv4i16_v4i32:
31581 case AArch64::UABALv4i32_v2i64:
31582 case AArch64::UABALv8i8_v8i16:
31583 case AArch64::UABALv8i16_v4i32:
31584 case AArch64::UABALv16i8_v8i16:
31585 case AArch64::UABAv2i32:
31586 case AArch64::UABAv4i16:
31587 case AArch64::UABAv4i32:
31588 case AArch64::UABAv8i8:
31589 case AArch64::UABAv8i16:
31590 case AArch64::UABAv16i8:
31591 case AArch64::UDOTv8i8:
31592 case AArch64::UDOTv16i8:
31593 case AArch64::UMLALv2i32_v2i64:
31594 case AArch64::UMLALv4i16_v4i32:
31595 case AArch64::UMLALv4i32_v2i64:
31596 case AArch64::UMLALv8i8_v8i16:
31597 case AArch64::UMLALv8i16_v4i32:
31598 case AArch64::UMLALv16i8_v8i16:
31599 case AArch64::UMLSLv2i32_v2i64:
31600 case AArch64::UMLSLv4i16_v4i32:
31601 case AArch64::UMLSLv4i32_v2i64:
31602 case AArch64::UMLSLv8i8_v8i16:
31603 case AArch64::UMLSLv8i16_v4i32:
31604 case AArch64::UMLSLv16i8_v8i16:
31605 case AArch64::UMMLA:
31606 case AArch64::USDOTv8i8:
31607 case AArch64::USDOTv16i8:
31608 case AArch64::USMMLA: {
31609 switch (OpNum) {
31610 case 1:
31611 // op: Rd
31612 return 0;
31613 case 2:
31614 // op: Rn
31615 return 5;
31616 case 3:
31617 // op: Rm
31618 return 16;
31619 }
31620 break;
31621 }
31622 case AArch64::RSHRNv4i32_shift:
31623 case AArch64::RSHRNv8i16_shift:
31624 case AArch64::RSHRNv16i8_shift:
31625 case AArch64::SHRNv4i32_shift:
31626 case AArch64::SHRNv8i16_shift:
31627 case AArch64::SHRNv16i8_shift:
31628 case AArch64::SLId:
31629 case AArch64::SLIv2i32_shift:
31630 case AArch64::SLIv2i64_shift:
31631 case AArch64::SLIv4i16_shift:
31632 case AArch64::SLIv4i32_shift:
31633 case AArch64::SLIv8i8_shift:
31634 case AArch64::SLIv8i16_shift:
31635 case AArch64::SLIv16i8_shift:
31636 case AArch64::SQRSHRNv4i32_shift:
31637 case AArch64::SQRSHRNv8i16_shift:
31638 case AArch64::SQRSHRNv16i8_shift:
31639 case AArch64::SQRSHRUNv4i32_shift:
31640 case AArch64::SQRSHRUNv8i16_shift:
31641 case AArch64::SQRSHRUNv16i8_shift:
31642 case AArch64::SQSHRNv4i32_shift:
31643 case AArch64::SQSHRNv8i16_shift:
31644 case AArch64::SQSHRNv16i8_shift:
31645 case AArch64::SQSHRUNv4i32_shift:
31646 case AArch64::SQSHRUNv8i16_shift:
31647 case AArch64::SQSHRUNv16i8_shift:
31648 case AArch64::SRId:
31649 case AArch64::SRIv2i32_shift:
31650 case AArch64::SRIv2i64_shift:
31651 case AArch64::SRIv4i16_shift:
31652 case AArch64::SRIv4i32_shift:
31653 case AArch64::SRIv8i8_shift:
31654 case AArch64::SRIv8i16_shift:
31655 case AArch64::SRIv16i8_shift:
31656 case AArch64::SRSRAd:
31657 case AArch64::SRSRAv2i32_shift:
31658 case AArch64::SRSRAv2i64_shift:
31659 case AArch64::SRSRAv4i16_shift:
31660 case AArch64::SRSRAv4i32_shift:
31661 case AArch64::SRSRAv8i8_shift:
31662 case AArch64::SRSRAv8i16_shift:
31663 case AArch64::SRSRAv16i8_shift:
31664 case AArch64::SSRAd:
31665 case AArch64::SSRAv2i32_shift:
31666 case AArch64::SSRAv2i64_shift:
31667 case AArch64::SSRAv4i16_shift:
31668 case AArch64::SSRAv4i32_shift:
31669 case AArch64::SSRAv8i8_shift:
31670 case AArch64::SSRAv8i16_shift:
31671 case AArch64::SSRAv16i8_shift:
31672 case AArch64::UQRSHRNv4i32_shift:
31673 case AArch64::UQRSHRNv8i16_shift:
31674 case AArch64::UQRSHRNv16i8_shift:
31675 case AArch64::UQSHRNv4i32_shift:
31676 case AArch64::UQSHRNv8i16_shift:
31677 case AArch64::UQSHRNv16i8_shift:
31678 case AArch64::URSRAd:
31679 case AArch64::URSRAv2i32_shift:
31680 case AArch64::URSRAv2i64_shift:
31681 case AArch64::URSRAv4i16_shift:
31682 case AArch64::URSRAv4i32_shift:
31683 case AArch64::URSRAv8i8_shift:
31684 case AArch64::URSRAv8i16_shift:
31685 case AArch64::URSRAv16i8_shift:
31686 case AArch64::USRAd:
31687 case AArch64::USRAv2i32_shift:
31688 case AArch64::USRAv2i64_shift:
31689 case AArch64::USRAv4i16_shift:
31690 case AArch64::USRAv4i32_shift:
31691 case AArch64::USRAv8i8_shift:
31692 case AArch64::USRAv8i16_shift:
31693 case AArch64::USRAv16i8_shift: {
31694 switch (OpNum) {
31695 case 1:
31696 // op: Rd
31697 return 0;
31698 case 2:
31699 // op: Rn
31700 return 5;
31701 case 3:
31702 // op: imm
31703 return 16;
31704 }
31705 break;
31706 }
31707 case AArch64::AESDrr:
31708 case AArch64::AESErr:
31709 case AArch64::AUTDA:
31710 case AArch64::AUTDB:
31711 case AArch64::AUTIA:
31712 case AArch64::AUTIB:
31713 case AArch64::BFCVTN2:
31714 case AArch64::FCVTNv4i32:
31715 case AArch64::FCVTNv8i16:
31716 case AArch64::FCVTXNv4f32:
31717 case AArch64::PACDA:
31718 case AArch64::PACDB:
31719 case AArch64::PACIA:
31720 case AArch64::PACIB:
31721 case AArch64::SADALPv2i32_v1i64:
31722 case AArch64::SADALPv4i16_v2i32:
31723 case AArch64::SADALPv4i32_v2i64:
31724 case AArch64::SADALPv8i8_v4i16:
31725 case AArch64::SADALPv8i16_v4i32:
31726 case AArch64::SADALPv16i8_v8i16:
31727 case AArch64::SHA1SU1rr:
31728 case AArch64::SHA256SU0rr:
31729 case AArch64::SQXTNv4i32:
31730 case AArch64::SQXTNv8i16:
31731 case AArch64::SQXTNv16i8:
31732 case AArch64::SQXTUNv4i32:
31733 case AArch64::SQXTUNv8i16:
31734 case AArch64::SQXTUNv16i8:
31735 case AArch64::SUQADDv1i8:
31736 case AArch64::SUQADDv1i16:
31737 case AArch64::SUQADDv1i32:
31738 case AArch64::SUQADDv1i64:
31739 case AArch64::SUQADDv2i32:
31740 case AArch64::SUQADDv2i64:
31741 case AArch64::SUQADDv4i16:
31742 case AArch64::SUQADDv4i32:
31743 case AArch64::SUQADDv8i8:
31744 case AArch64::SUQADDv8i16:
31745 case AArch64::SUQADDv16i8:
31746 case AArch64::UADALPv2i32_v1i64:
31747 case AArch64::UADALPv4i16_v2i32:
31748 case AArch64::UADALPv4i32_v2i64:
31749 case AArch64::UADALPv8i8_v4i16:
31750 case AArch64::UADALPv8i16_v4i32:
31751 case AArch64::UADALPv16i8_v8i16:
31752 case AArch64::UQXTNv4i32:
31753 case AArch64::UQXTNv8i16:
31754 case AArch64::UQXTNv16i8:
31755 case AArch64::USQADDv1i8:
31756 case AArch64::USQADDv1i16:
31757 case AArch64::USQADDv1i32:
31758 case AArch64::USQADDv1i64:
31759 case AArch64::USQADDv2i32:
31760 case AArch64::USQADDv2i64:
31761 case AArch64::USQADDv4i16:
31762 case AArch64::USQADDv4i32:
31763 case AArch64::USQADDv8i8:
31764 case AArch64::USQADDv8i16:
31765 case AArch64::USQADDv16i8:
31766 case AArch64::XTNv4i32:
31767 case AArch64::XTNv8i16:
31768 case AArch64::XTNv16i8: {
31769 switch (OpNum) {
31770 case 1:
31771 // op: Rd
31772 return 0;
31773 case 2:
31774 // op: Rn
31775 return 5;
31776 }
31777 break;
31778 }
31779 case AArch64::BICv2i32:
31780 case AArch64::BICv4i16:
31781 case AArch64::BICv4i32:
31782 case AArch64::BICv8i16:
31783 case AArch64::ORRv2i32:
31784 case AArch64::ORRv4i16:
31785 case AArch64::ORRv4i32:
31786 case AArch64::ORRv8i16: {
31787 switch (OpNum) {
31788 case 1:
31789 // op: Rd
31790 return 0;
31791 case 2:
31792 // op: imm8
31793 return 5;
31794 case 3:
31795 // op: shift
31796 return 13;
31797 }
31798 break;
31799 }
31800 case AArch64::INSvi8lane: {
31801 switch (OpNum) {
31802 case 1:
31803 // op: Rd
31804 return 0;
31805 case 3:
31806 // op: Rn
31807 return 5;
31808 case 2:
31809 // op: idx
31810 return 17;
31811 case 4:
31812 // op: idx2
31813 return 11;
31814 }
31815 break;
31816 }
31817 case AArch64::INSvi8gpr: {
31818 switch (OpNum) {
31819 case 1:
31820 // op: Rd
31821 return 0;
31822 case 3:
31823 // op: Rn
31824 return 5;
31825 case 2:
31826 // op: idx
31827 return 17;
31828 }
31829 break;
31830 }
31831 case AArch64::INSvi16lane: {
31832 switch (OpNum) {
31833 case 1:
31834 // op: Rd
31835 return 0;
31836 case 3:
31837 // op: Rn
31838 return 5;
31839 case 2:
31840 // op: idx
31841 return 18;
31842 case 4:
31843 // op: idx2
31844 return 12;
31845 }
31846 break;
31847 }
31848 case AArch64::INSvi16gpr: {
31849 switch (OpNum) {
31850 case 1:
31851 // op: Rd
31852 return 0;
31853 case 3:
31854 // op: Rn
31855 return 5;
31856 case 2:
31857 // op: idx
31858 return 18;
31859 }
31860 break;
31861 }
31862 case AArch64::INSvi32lane: {
31863 switch (OpNum) {
31864 case 1:
31865 // op: Rd
31866 return 0;
31867 case 3:
31868 // op: Rn
31869 return 5;
31870 case 2:
31871 // op: idx
31872 return 19;
31873 case 4:
31874 // op: idx2
31875 return 13;
31876 }
31877 break;
31878 }
31879 case AArch64::INSvi32gpr: {
31880 switch (OpNum) {
31881 case 1:
31882 // op: Rd
31883 return 0;
31884 case 3:
31885 // op: Rn
31886 return 5;
31887 case 2:
31888 // op: idx
31889 return 19;
31890 }
31891 break;
31892 }
31893 case AArch64::INSvi64lane: {
31894 switch (OpNum) {
31895 case 1:
31896 // op: Rd
31897 return 0;
31898 case 3:
31899 // op: Rn
31900 return 5;
31901 case 2:
31902 // op: idx
31903 return 20;
31904 case 4:
31905 // op: idx2
31906 return 14;
31907 }
31908 break;
31909 }
31910 case AArch64::INSvi64gpr: {
31911 switch (OpNum) {
31912 case 1:
31913 // op: Rd
31914 return 0;
31915 case 3:
31916 // op: Rn
31917 return 5;
31918 case 2:
31919 // op: idx
31920 return 20;
31921 }
31922 break;
31923 }
31924 case AArch64::AUTDZA:
31925 case AArch64::AUTDZB:
31926 case AArch64::AUTIZA:
31927 case AArch64::AUTIZB:
31928 case AArch64::PACDZA:
31929 case AArch64::PACDZB:
31930 case AArch64::PACIZA:
31931 case AArch64::PACIZB: {
31932 switch (OpNum) {
31933 case 1:
31934 // op: Rd
31935 return 0;
31936 }
31937 break;
31938 }
31939 case AArch64::CTERMEQ_WW:
31940 case AArch64::CTERMEQ_XX:
31941 case AArch64::CTERMNE_WW:
31942 case AArch64::CTERMNE_XX:
31943 case AArch64::FCMPDrr:
31944 case AArch64::FCMPEDrr:
31945 case AArch64::FCMPEHrr:
31946 case AArch64::FCMPESrr:
31947 case AArch64::FCMPHrr:
31948 case AArch64::FCMPSrr: {
31949 switch (OpNum) {
31950 case 1:
31951 // op: Rm
31952 return 16;
31953 case 0:
31954 // op: Rn
31955 return 5;
31956 }
31957 break;
31958 }
31959 case AArch64::ST2Gi:
31960 case AArch64::STGi:
31961 case AArch64::STZ2Gi:
31962 case AArch64::STZGi: {
31963 switch (OpNum) {
31964 case 1:
31965 // op: Rn
31966 return 5;
31967 case 0:
31968 // op: Rt
31969 return 0;
31970 case 2:
31971 // op: offset
31972 return 12;
31973 }
31974 break;
31975 }
31976 case AArch64::LDAPRB:
31977 case AArch64::LDAPRH:
31978 case AArch64::LDAPRW:
31979 case AArch64::LDAPRX:
31980 case AArch64::LDGM:
31981 case AArch64::STGM:
31982 case AArch64::STZGM: {
31983 switch (OpNum) {
31984 case 1:
31985 // op: Rn
31986 return 5;
31987 case 0:
31988 // op: Rt
31989 return 0;
31990 }
31991 break;
31992 }
31993 case AArch64::INDEX_RI_B:
31994 case AArch64::INDEX_RI_D:
31995 case AArch64::INDEX_RI_H:
31996 case AArch64::INDEX_RI_S: {
31997 switch (OpNum) {
31998 case 1:
31999 // op: Rn
32000 return 5;
32001 case 0:
32002 // op: Zd
32003 return 0;
32004 case 2:
32005 // op: imm5
32006 return 16;
32007 }
32008 break;
32009 }
32010 case AArch64::DUP_ZR_B:
32011 case AArch64::DUP_ZR_D:
32012 case AArch64::DUP_ZR_H:
32013 case AArch64::DUP_ZR_S: {
32014 switch (OpNum) {
32015 case 1:
32016 // op: Rn
32017 return 5;
32018 case 0:
32019 // op: Zd
32020 return 0;
32021 }
32022 break;
32023 }
32024 case AArch64::LDR_ZXI:
32025 case AArch64::STR_ZXI: {
32026 switch (OpNum) {
32027 case 1:
32028 // op: Rn
32029 return 5;
32030 case 0:
32031 // op: Zt
32032 return 0;
32033 case 2:
32034 // op: imm9
32035 return 10;
32036 }
32037 break;
32038 }
32039 case AArch64::LDR_TX:
32040 case AArch64::STR_TX: {
32041 switch (OpNum) {
32042 case 1:
32043 // op: Rn
32044 return 5;
32045 }
32046 break;
32047 }
32048 case AArch64::LDADDAB:
32049 case AArch64::LDADDAH:
32050 case AArch64::LDADDALB:
32051 case AArch64::LDADDALH:
32052 case AArch64::LDADDALW:
32053 case AArch64::LDADDALX:
32054 case AArch64::LDADDAW:
32055 case AArch64::LDADDAX:
32056 case AArch64::LDADDB:
32057 case AArch64::LDADDH:
32058 case AArch64::LDADDLB:
32059 case AArch64::LDADDLH:
32060 case AArch64::LDADDLW:
32061 case AArch64::LDADDLX:
32062 case AArch64::LDADDW:
32063 case AArch64::LDADDX:
32064 case AArch64::LDCLRAB:
32065 case AArch64::LDCLRAH:
32066 case AArch64::LDCLRALB:
32067 case AArch64::LDCLRALH:
32068 case AArch64::LDCLRALW:
32069 case AArch64::LDCLRALX:
32070 case AArch64::LDCLRAW:
32071 case AArch64::LDCLRAX:
32072 case AArch64::LDCLRB:
32073 case AArch64::LDCLRH:
32074 case AArch64::LDCLRLB:
32075 case AArch64::LDCLRLH:
32076 case AArch64::LDCLRLW:
32077 case AArch64::LDCLRLX:
32078 case AArch64::LDCLRW:
32079 case AArch64::LDCLRX:
32080 case AArch64::LDEORAB:
32081 case AArch64::LDEORAH:
32082 case AArch64::LDEORALB:
32083 case AArch64::LDEORALH:
32084 case AArch64::LDEORALW:
32085 case AArch64::LDEORALX:
32086 case AArch64::LDEORAW:
32087 case AArch64::LDEORAX:
32088 case AArch64::LDEORB:
32089 case AArch64::LDEORH:
32090 case AArch64::LDEORLB:
32091 case AArch64::LDEORLH:
32092 case AArch64::LDEORLW:
32093 case AArch64::LDEORLX:
32094 case AArch64::LDEORW:
32095 case AArch64::LDEORX:
32096 case AArch64::LDSETAB:
32097 case AArch64::LDSETAH:
32098 case AArch64::LDSETALB:
32099 case AArch64::LDSETALH:
32100 case AArch64::LDSETALW:
32101 case AArch64::LDSETALX:
32102 case AArch64::LDSETAW:
32103 case AArch64::LDSETAX:
32104 case AArch64::LDSETB:
32105 case AArch64::LDSETH:
32106 case AArch64::LDSETLB:
32107 case AArch64::LDSETLH:
32108 case AArch64::LDSETLW:
32109 case AArch64::LDSETLX:
32110 case AArch64::LDSETW:
32111 case AArch64::LDSETX:
32112 case AArch64::LDSMAXAB:
32113 case AArch64::LDSMAXAH:
32114 case AArch64::LDSMAXALB:
32115 case AArch64::LDSMAXALH:
32116 case AArch64::LDSMAXALW:
32117 case AArch64::LDSMAXALX:
32118 case AArch64::LDSMAXAW:
32119 case AArch64::LDSMAXAX:
32120 case AArch64::LDSMAXB:
32121 case AArch64::LDSMAXH:
32122 case AArch64::LDSMAXLB:
32123 case AArch64::LDSMAXLH:
32124 case AArch64::LDSMAXLW:
32125 case AArch64::LDSMAXLX:
32126 case AArch64::LDSMAXW:
32127 case AArch64::LDSMAXX:
32128 case AArch64::LDSMINAB:
32129 case AArch64::LDSMINAH:
32130 case AArch64::LDSMINALB:
32131 case AArch64::LDSMINALH:
32132 case AArch64::LDSMINALW:
32133 case AArch64::LDSMINALX:
32134 case AArch64::LDSMINAW:
32135 case AArch64::LDSMINAX:
32136 case AArch64::LDSMINB:
32137 case AArch64::LDSMINH:
32138 case AArch64::LDSMINLB:
32139 case AArch64::LDSMINLH:
32140 case AArch64::LDSMINLW:
32141 case AArch64::LDSMINLX:
32142 case AArch64::LDSMINW:
32143 case AArch64::LDSMINX:
32144 case AArch64::LDUMAXAB:
32145 case AArch64::LDUMAXAH:
32146 case AArch64::LDUMAXALB:
32147 case AArch64::LDUMAXALH:
32148 case AArch64::LDUMAXALW:
32149 case AArch64::LDUMAXALX:
32150 case AArch64::LDUMAXAW:
32151 case AArch64::LDUMAXAX:
32152 case AArch64::LDUMAXB:
32153 case AArch64::LDUMAXH:
32154 case AArch64::LDUMAXLB:
32155 case AArch64::LDUMAXLH:
32156 case AArch64::LDUMAXLW:
32157 case AArch64::LDUMAXLX:
32158 case AArch64::LDUMAXW:
32159 case AArch64::LDUMAXX:
32160 case AArch64::LDUMINAB:
32161 case AArch64::LDUMINAH:
32162 case AArch64::LDUMINALB:
32163 case AArch64::LDUMINALH:
32164 case AArch64::LDUMINALW:
32165 case AArch64::LDUMINALX:
32166 case AArch64::LDUMINAW:
32167 case AArch64::LDUMINAX:
32168 case AArch64::LDUMINB:
32169 case AArch64::LDUMINH:
32170 case AArch64::LDUMINLB:
32171 case AArch64::LDUMINLH:
32172 case AArch64::LDUMINLW:
32173 case AArch64::LDUMINLX:
32174 case AArch64::LDUMINW:
32175 case AArch64::LDUMINX:
32176 case AArch64::RCWCLR:
32177 case AArch64::RCWCLRA:
32178 case AArch64::RCWCLRAL:
32179 case AArch64::RCWCLRL:
32180 case AArch64::RCWCLRS:
32181 case AArch64::RCWCLRSA:
32182 case AArch64::RCWCLRSAL:
32183 case AArch64::RCWCLRSL:
32184 case AArch64::RCWSET:
32185 case AArch64::RCWSETA:
32186 case AArch64::RCWSETAL:
32187 case AArch64::RCWSETL:
32188 case AArch64::RCWSETS:
32189 case AArch64::RCWSETSA:
32190 case AArch64::RCWSETSAL:
32191 case AArch64::RCWSETSL:
32192 case AArch64::RCWSWP:
32193 case AArch64::RCWSWPA:
32194 case AArch64::RCWSWPAL:
32195 case AArch64::RCWSWPL:
32196 case AArch64::RCWSWPS:
32197 case AArch64::RCWSWPSA:
32198 case AArch64::RCWSWPSAL:
32199 case AArch64::RCWSWPSL:
32200 case AArch64::SWPAB:
32201 case AArch64::SWPAH:
32202 case AArch64::SWPALB:
32203 case AArch64::SWPALH:
32204 case AArch64::SWPALW:
32205 case AArch64::SWPALX:
32206 case AArch64::SWPAW:
32207 case AArch64::SWPAX:
32208 case AArch64::SWPB:
32209 case AArch64::SWPH:
32210 case AArch64::SWPLB:
32211 case AArch64::SWPLH:
32212 case AArch64::SWPLW:
32213 case AArch64::SWPLX:
32214 case AArch64::SWPW:
32215 case AArch64::SWPX: {
32216 switch (OpNum) {
32217 case 1:
32218 // op: Rs
32219 return 16;
32220 case 2:
32221 // op: Rn
32222 return 5;
32223 case 0:
32224 // op: Rt
32225 return 0;
32226 }
32227 break;
32228 }
32229 case AArch64::CASAB:
32230 case AArch64::CASAH:
32231 case AArch64::CASALB:
32232 case AArch64::CASALH:
32233 case AArch64::CASALW:
32234 case AArch64::CASALX:
32235 case AArch64::CASAW:
32236 case AArch64::CASAX:
32237 case AArch64::CASB:
32238 case AArch64::CASH:
32239 case AArch64::CASLB:
32240 case AArch64::CASLH:
32241 case AArch64::CASLW:
32242 case AArch64::CASLX:
32243 case AArch64::CASPALW:
32244 case AArch64::CASPALX:
32245 case AArch64::CASPAW:
32246 case AArch64::CASPAX:
32247 case AArch64::CASPLW:
32248 case AArch64::CASPLX:
32249 case AArch64::CASPW:
32250 case AArch64::CASPX:
32251 case AArch64::CASW:
32252 case AArch64::CASX:
32253 case AArch64::RCWCAS:
32254 case AArch64::RCWCASA:
32255 case AArch64::RCWCASAL:
32256 case AArch64::RCWCASL:
32257 case AArch64::RCWCASP:
32258 case AArch64::RCWCASPA:
32259 case AArch64::RCWCASPAL:
32260 case AArch64::RCWCASPL:
32261 case AArch64::RCWSCAS:
32262 case AArch64::RCWSCASA:
32263 case AArch64::RCWSCASAL:
32264 case AArch64::RCWSCASL:
32265 case AArch64::RCWSCASP:
32266 case AArch64::RCWSCASPA:
32267 case AArch64::RCWSCASPAL:
32268 case AArch64::RCWSCASPL: {
32269 switch (OpNum) {
32270 case 1:
32271 // op: Rs
32272 return 16;
32273 case 3:
32274 // op: Rn
32275 return 5;
32276 case 2:
32277 // op: Rt
32278 return 0;
32279 }
32280 break;
32281 }
32282 case AArch64::MSR:
32283 case AArch64::MSRR: {
32284 switch (OpNum) {
32285 case 1:
32286 // op: Rt
32287 return 0;
32288 case 0:
32289 // op: systemreg
32290 return 5;
32291 }
32292 break;
32293 }
32294 case AArch64::ST64BV:
32295 case AArch64::ST64BV0: {
32296 switch (OpNum) {
32297 case 1:
32298 // op: Rt
32299 return 0;
32300 case 2:
32301 // op: Rn
32302 return 5;
32303 case 0:
32304 // op: Rs
32305 return 16;
32306 }
32307 break;
32308 }
32309 case AArch64::LDRBBpost:
32310 case AArch64::LDRBBpre:
32311 case AArch64::LDRBpost:
32312 case AArch64::LDRBpre:
32313 case AArch64::LDRDpost:
32314 case AArch64::LDRDpre:
32315 case AArch64::LDRHHpost:
32316 case AArch64::LDRHHpre:
32317 case AArch64::LDRHpost:
32318 case AArch64::LDRHpre:
32319 case AArch64::LDRQpost:
32320 case AArch64::LDRQpre:
32321 case AArch64::LDRSBWpost:
32322 case AArch64::LDRSBWpre:
32323 case AArch64::LDRSBXpost:
32324 case AArch64::LDRSBXpre:
32325 case AArch64::LDRSHWpost:
32326 case AArch64::LDRSHWpre:
32327 case AArch64::LDRSHXpost:
32328 case AArch64::LDRSHXpre:
32329 case AArch64::LDRSWpost:
32330 case AArch64::LDRSWpre:
32331 case AArch64::LDRSpost:
32332 case AArch64::LDRSpre:
32333 case AArch64::LDRWpost:
32334 case AArch64::LDRWpre:
32335 case AArch64::LDRXpost:
32336 case AArch64::LDRXpre:
32337 case AArch64::STRBBpost:
32338 case AArch64::STRBBpre:
32339 case AArch64::STRBpost:
32340 case AArch64::STRBpre:
32341 case AArch64::STRDpost:
32342 case AArch64::STRDpre:
32343 case AArch64::STRHHpost:
32344 case AArch64::STRHHpre:
32345 case AArch64::STRHpost:
32346 case AArch64::STRHpre:
32347 case AArch64::STRQpost:
32348 case AArch64::STRQpre:
32349 case AArch64::STRSpost:
32350 case AArch64::STRSpre:
32351 case AArch64::STRWpost:
32352 case AArch64::STRWpre:
32353 case AArch64::STRXpost:
32354 case AArch64::STRXpre: {
32355 switch (OpNum) {
32356 case 1:
32357 // op: Rt
32358 return 0;
32359 case 2:
32360 // op: Rn
32361 return 5;
32362 case 3:
32363 // op: offset
32364 return 12;
32365 }
32366 break;
32367 }
32368 case AArch64::LDAPRWpost:
32369 case AArch64::LDAPRXpost:
32370 case AArch64::STLRWpre:
32371 case AArch64::STLRXpre: {
32372 switch (OpNum) {
32373 case 1:
32374 // op: Rt
32375 return 0;
32376 case 2:
32377 // op: Rn
32378 return 5;
32379 }
32380 break;
32381 }
32382 case AArch64::LDPDpost:
32383 case AArch64::LDPDpre:
32384 case AArch64::LDPQpost:
32385 case AArch64::LDPQpre:
32386 case AArch64::LDPSWpost:
32387 case AArch64::LDPSWpre:
32388 case AArch64::LDPSpost:
32389 case AArch64::LDPSpre:
32390 case AArch64::LDPWpost:
32391 case AArch64::LDPWpre:
32392 case AArch64::LDPXpost:
32393 case AArch64::LDPXpre:
32394 case AArch64::STGPpost:
32395 case AArch64::STGPpre:
32396 case AArch64::STPDpost:
32397 case AArch64::STPDpre:
32398 case AArch64::STPQpost:
32399 case AArch64::STPQpre:
32400 case AArch64::STPSpost:
32401 case AArch64::STPSpre:
32402 case AArch64::STPWpost:
32403 case AArch64::STPWpre:
32404 case AArch64::STPXpost:
32405 case AArch64::STPXpre: {
32406 switch (OpNum) {
32407 case 1:
32408 // op: Rt
32409 return 0;
32410 case 2:
32411 // op: Rt2
32412 return 10;
32413 case 3:
32414 // op: Rn
32415 return 5;
32416 case 4:
32417 // op: offset
32418 return 15;
32419 }
32420 break;
32421 }
32422 case AArch64::LDIAPPWpost:
32423 case AArch64::LDIAPPXpost:
32424 case AArch64::STILPWpre:
32425 case AArch64::STILPXpre: {
32426 switch (OpNum) {
32427 case 1:
32428 // op: Rt
32429 return 0;
32430 case 3:
32431 // op: Rn
32432 return 5;
32433 case 2:
32434 // op: Rt2
32435 return 16;
32436 }
32437 break;
32438 }
32439 case AArch64::LDR_ZA:
32440 case AArch64::STR_ZA: {
32441 switch (OpNum) {
32442 case 1:
32443 // op: Rv
32444 return 13;
32445 case 3:
32446 // op: Rn
32447 return 5;
32448 case 2:
32449 // op: imm4
32450 return 0;
32451 }
32452 break;
32453 }
32454 case AArch64::SHA512H:
32455 case AArch64::SHA512H2:
32456 case AArch64::SHA512SU1:
32457 case AArch64::SM3PARTW1:
32458 case AArch64::SM3PARTW2:
32459 case AArch64::TBXv8i8Four:
32460 case AArch64::TBXv8i8One:
32461 case AArch64::TBXv8i8Three:
32462 case AArch64::TBXv8i8Two:
32463 case AArch64::TBXv16i8Four:
32464 case AArch64::TBXv16i8One:
32465 case AArch64::TBXv16i8Three:
32466 case AArch64::TBXv16i8Two: {
32467 switch (OpNum) {
32468 case 1:
32469 // op: Vd
32470 return 0;
32471 case 2:
32472 // op: Vn
32473 return 5;
32474 case 3:
32475 // op: Vm
32476 return 16;
32477 }
32478 break;
32479 }
32480 case AArch64::SM3TT1A:
32481 case AArch64::SM3TT1B:
32482 case AArch64::SM3TT2A:
32483 case AArch64::SM3TT2B: {
32484 switch (OpNum) {
32485 case 1:
32486 // op: Vd
32487 return 0;
32488 case 2:
32489 // op: Vn
32490 return 5;
32491 case 4:
32492 // op: imm
32493 return 12;
32494 case 3:
32495 // op: Vm
32496 return 16;
32497 }
32498 break;
32499 }
32500 case AArch64::SHA512SU0:
32501 case AArch64::SM4E: {
32502 switch (OpNum) {
32503 case 1:
32504 // op: Vd
32505 return 0;
32506 case 2:
32507 // op: Vn
32508 return 5;
32509 }
32510 break;
32511 }
32512 case AArch64::LD1Fourv1d_POST:
32513 case AArch64::LD1Fourv2d_POST:
32514 case AArch64::LD1Fourv2s_POST:
32515 case AArch64::LD1Fourv4h_POST:
32516 case AArch64::LD1Fourv4s_POST:
32517 case AArch64::LD1Fourv8b_POST:
32518 case AArch64::LD1Fourv8h_POST:
32519 case AArch64::LD1Fourv16b_POST:
32520 case AArch64::LD1Onev1d_POST:
32521 case AArch64::LD1Onev2d_POST:
32522 case AArch64::LD1Onev2s_POST:
32523 case AArch64::LD1Onev4h_POST:
32524 case AArch64::LD1Onev4s_POST:
32525 case AArch64::LD1Onev8b_POST:
32526 case AArch64::LD1Onev8h_POST:
32527 case AArch64::LD1Onev16b_POST:
32528 case AArch64::LD1Rv1d_POST:
32529 case AArch64::LD1Rv2d_POST:
32530 case AArch64::LD1Rv2s_POST:
32531 case AArch64::LD1Rv4h_POST:
32532 case AArch64::LD1Rv4s_POST:
32533 case AArch64::LD1Rv8b_POST:
32534 case AArch64::LD1Rv8h_POST:
32535 case AArch64::LD1Rv16b_POST:
32536 case AArch64::LD1Threev1d_POST:
32537 case AArch64::LD1Threev2d_POST:
32538 case AArch64::LD1Threev2s_POST:
32539 case AArch64::LD1Threev4h_POST:
32540 case AArch64::LD1Threev4s_POST:
32541 case AArch64::LD1Threev8b_POST:
32542 case AArch64::LD1Threev8h_POST:
32543 case AArch64::LD1Threev16b_POST:
32544 case AArch64::LD1Twov1d_POST:
32545 case AArch64::LD1Twov2d_POST:
32546 case AArch64::LD1Twov2s_POST:
32547 case AArch64::LD1Twov4h_POST:
32548 case AArch64::LD1Twov4s_POST:
32549 case AArch64::LD1Twov8b_POST:
32550 case AArch64::LD1Twov8h_POST:
32551 case AArch64::LD1Twov16b_POST:
32552 case AArch64::LD2Rv1d_POST:
32553 case AArch64::LD2Rv2d_POST:
32554 case AArch64::LD2Rv2s_POST:
32555 case AArch64::LD2Rv4h_POST:
32556 case AArch64::LD2Rv4s_POST:
32557 case AArch64::LD2Rv8b_POST:
32558 case AArch64::LD2Rv8h_POST:
32559 case AArch64::LD2Rv16b_POST:
32560 case AArch64::LD2Twov2d_POST:
32561 case AArch64::LD2Twov2s_POST:
32562 case AArch64::LD2Twov4h_POST:
32563 case AArch64::LD2Twov4s_POST:
32564 case AArch64::LD2Twov8b_POST:
32565 case AArch64::LD2Twov8h_POST:
32566 case AArch64::LD2Twov16b_POST:
32567 case AArch64::LD3Rv1d_POST:
32568 case AArch64::LD3Rv2d_POST:
32569 case AArch64::LD3Rv2s_POST:
32570 case AArch64::LD3Rv4h_POST:
32571 case AArch64::LD3Rv4s_POST:
32572 case AArch64::LD3Rv8b_POST:
32573 case AArch64::LD3Rv8h_POST:
32574 case AArch64::LD3Rv16b_POST:
32575 case AArch64::LD3Threev2d_POST:
32576 case AArch64::LD3Threev2s_POST:
32577 case AArch64::LD3Threev4h_POST:
32578 case AArch64::LD3Threev4s_POST:
32579 case AArch64::LD3Threev8b_POST:
32580 case AArch64::LD3Threev8h_POST:
32581 case AArch64::LD3Threev16b_POST:
32582 case AArch64::LD4Fourv2d_POST:
32583 case AArch64::LD4Fourv2s_POST:
32584 case AArch64::LD4Fourv4h_POST:
32585 case AArch64::LD4Fourv4s_POST:
32586 case AArch64::LD4Fourv8b_POST:
32587 case AArch64::LD4Fourv8h_POST:
32588 case AArch64::LD4Fourv16b_POST:
32589 case AArch64::LD4Rv1d_POST:
32590 case AArch64::LD4Rv2d_POST:
32591 case AArch64::LD4Rv2s_POST:
32592 case AArch64::LD4Rv4h_POST:
32593 case AArch64::LD4Rv4s_POST:
32594 case AArch64::LD4Rv8b_POST:
32595 case AArch64::LD4Rv8h_POST:
32596 case AArch64::LD4Rv16b_POST:
32597 case AArch64::ST1Fourv1d_POST:
32598 case AArch64::ST1Fourv2d_POST:
32599 case AArch64::ST1Fourv2s_POST:
32600 case AArch64::ST1Fourv4h_POST:
32601 case AArch64::ST1Fourv4s_POST:
32602 case AArch64::ST1Fourv8b_POST:
32603 case AArch64::ST1Fourv8h_POST:
32604 case AArch64::ST1Fourv16b_POST:
32605 case AArch64::ST1Onev1d_POST:
32606 case AArch64::ST1Onev2d_POST:
32607 case AArch64::ST1Onev2s_POST:
32608 case AArch64::ST1Onev4h_POST:
32609 case AArch64::ST1Onev4s_POST:
32610 case AArch64::ST1Onev8b_POST:
32611 case AArch64::ST1Onev8h_POST:
32612 case AArch64::ST1Onev16b_POST:
32613 case AArch64::ST1Threev1d_POST:
32614 case AArch64::ST1Threev2d_POST:
32615 case AArch64::ST1Threev2s_POST:
32616 case AArch64::ST1Threev4h_POST:
32617 case AArch64::ST1Threev4s_POST:
32618 case AArch64::ST1Threev8b_POST:
32619 case AArch64::ST1Threev8h_POST:
32620 case AArch64::ST1Threev16b_POST:
32621 case AArch64::ST1Twov1d_POST:
32622 case AArch64::ST1Twov2d_POST:
32623 case AArch64::ST1Twov2s_POST:
32624 case AArch64::ST1Twov4h_POST:
32625 case AArch64::ST1Twov4s_POST:
32626 case AArch64::ST1Twov8b_POST:
32627 case AArch64::ST1Twov8h_POST:
32628 case AArch64::ST1Twov16b_POST:
32629 case AArch64::ST2Twov2d_POST:
32630 case AArch64::ST2Twov2s_POST:
32631 case AArch64::ST2Twov4h_POST:
32632 case AArch64::ST2Twov4s_POST:
32633 case AArch64::ST2Twov8b_POST:
32634 case AArch64::ST2Twov8h_POST:
32635 case AArch64::ST2Twov16b_POST:
32636 case AArch64::ST3Threev2d_POST:
32637 case AArch64::ST3Threev2s_POST:
32638 case AArch64::ST3Threev4h_POST:
32639 case AArch64::ST3Threev4s_POST:
32640 case AArch64::ST3Threev8b_POST:
32641 case AArch64::ST3Threev8h_POST:
32642 case AArch64::ST3Threev16b_POST:
32643 case AArch64::ST4Fourv2d_POST:
32644 case AArch64::ST4Fourv2s_POST:
32645 case AArch64::ST4Fourv4h_POST:
32646 case AArch64::ST4Fourv4s_POST:
32647 case AArch64::ST4Fourv8b_POST:
32648 case AArch64::ST4Fourv8h_POST:
32649 case AArch64::ST4Fourv16b_POST: {
32650 switch (OpNum) {
32651 case 1:
32652 // op: Vt
32653 return 0;
32654 case 2:
32655 // op: Rn
32656 return 5;
32657 case 3:
32658 // op: Xm
32659 return 16;
32660 }
32661 break;
32662 }
32663 case AArch64::LDAP1: {
32664 switch (OpNum) {
32665 case 1:
32666 // op: Vt
32667 return 0;
32668 case 3:
32669 // op: Rn
32670 return 5;
32671 case 2:
32672 // op: Q
32673 return 30;
32674 }
32675 break;
32676 }
32677 case AArch64::ST1i8_POST:
32678 case AArch64::ST2i8_POST:
32679 case AArch64::ST3i8_POST:
32680 case AArch64::ST4i8_POST: {
32681 switch (OpNum) {
32682 case 1:
32683 // op: Vt
32684 return 0;
32685 case 3:
32686 // op: Rn
32687 return 5;
32688 case 2:
32689 // op: idx
32690 return 10;
32691 case 4:
32692 // op: Xm
32693 return 16;
32694 }
32695 break;
32696 }
32697 case AArch64::LD1i8:
32698 case AArch64::LD2i8:
32699 case AArch64::LD3i8:
32700 case AArch64::LD4i8: {
32701 switch (OpNum) {
32702 case 1:
32703 // op: Vt
32704 return 0;
32705 case 3:
32706 // op: Rn
32707 return 5;
32708 case 2:
32709 // op: idx
32710 return 10;
32711 }
32712 break;
32713 }
32714 case AArch64::ST1i16_POST:
32715 case AArch64::ST2i16_POST:
32716 case AArch64::ST3i16_POST:
32717 case AArch64::ST4i16_POST: {
32718 switch (OpNum) {
32719 case 1:
32720 // op: Vt
32721 return 0;
32722 case 3:
32723 // op: Rn
32724 return 5;
32725 case 2:
32726 // op: idx
32727 return 11;
32728 case 4:
32729 // op: Xm
32730 return 16;
32731 }
32732 break;
32733 }
32734 case AArch64::LD1i16:
32735 case AArch64::LD2i16:
32736 case AArch64::LD3i16:
32737 case AArch64::LD4i16: {
32738 switch (OpNum) {
32739 case 1:
32740 // op: Vt
32741 return 0;
32742 case 3:
32743 // op: Rn
32744 return 5;
32745 case 2:
32746 // op: idx
32747 return 11;
32748 }
32749 break;
32750 }
32751 case AArch64::ST1i32_POST:
32752 case AArch64::ST2i32_POST:
32753 case AArch64::ST3i32_POST:
32754 case AArch64::ST4i32_POST: {
32755 switch (OpNum) {
32756 case 1:
32757 // op: Vt
32758 return 0;
32759 case 3:
32760 // op: Rn
32761 return 5;
32762 case 2:
32763 // op: idx
32764 return 12;
32765 case 4:
32766 // op: Xm
32767 return 16;
32768 }
32769 break;
32770 }
32771 case AArch64::LD1i32:
32772 case AArch64::LD2i32:
32773 case AArch64::LD3i32:
32774 case AArch64::LD4i32: {
32775 switch (OpNum) {
32776 case 1:
32777 // op: Vt
32778 return 0;
32779 case 3:
32780 // op: Rn
32781 return 5;
32782 case 2:
32783 // op: idx
32784 return 12;
32785 }
32786 break;
32787 }
32788 case AArch64::ST1i64_POST:
32789 case AArch64::ST2i64_POST:
32790 case AArch64::ST3i64_POST:
32791 case AArch64::ST4i64_POST: {
32792 switch (OpNum) {
32793 case 1:
32794 // op: Vt
32795 return 0;
32796 case 3:
32797 // op: Rn
32798 return 5;
32799 case 2:
32800 // op: idx
32801 return 30;
32802 case 4:
32803 // op: Xm
32804 return 16;
32805 }
32806 break;
32807 }
32808 case AArch64::LD1i64:
32809 case AArch64::LD2i64:
32810 case AArch64::LD3i64:
32811 case AArch64::LD4i64: {
32812 switch (OpNum) {
32813 case 1:
32814 // op: Vt
32815 return 0;
32816 case 3:
32817 // op: Rn
32818 return 5;
32819 case 2:
32820 // op: idx
32821 return 30;
32822 }
32823 break;
32824 }
32825 case AArch64::BF1CVTL_2ZZ_BtoH_NAME:
32826 case AArch64::BF1CVT_2ZZ_BtoH_NAME:
32827 case AArch64::BF2CVTL_2ZZ_BtoH_NAME:
32828 case AArch64::BF2CVT_2ZZ_BtoH_NAME:
32829 case AArch64::F1CVTL_2ZZ_BtoH_NAME:
32830 case AArch64::F1CVT_2ZZ_BtoH_NAME:
32831 case AArch64::F2CVTL_2ZZ_BtoH_NAME:
32832 case AArch64::F2CVT_2ZZ_BtoH_NAME:
32833 case AArch64::FCVTL_2ZZ_H_S:
32834 case AArch64::FCVT_2ZZ_H_S:
32835 case AArch64::SUNPK_VG2_2ZZ_D:
32836 case AArch64::SUNPK_VG2_2ZZ_H:
32837 case AArch64::SUNPK_VG2_2ZZ_S:
32838 case AArch64::UUNPK_VG2_2ZZ_D:
32839 case AArch64::UUNPK_VG2_2ZZ_H:
32840 case AArch64::UUNPK_VG2_2ZZ_S: {
32841 switch (OpNum) {
32842 case 1:
32843 // op: Zn
32844 return 5;
32845 case 0:
32846 // op: Zd
32847 return 1;
32848 }
32849 break;
32850 }
32851 case AArch64::BFCVTN_Z2Z_StoH:
32852 case AArch64::BFCVT_Z2Z_HtoB:
32853 case AArch64::BFCVT_Z2Z_StoH:
32854 case AArch64::FCVTN_Z2Z_StoH:
32855 case AArch64::FCVT_Z2Z_HtoB:
32856 case AArch64::FCVT_Z2Z_StoH:
32857 case AArch64::SQCVTU_Z2Z_StoH:
32858 case AArch64::SQCVT_Z2Z_StoH:
32859 case AArch64::UQCVT_Z2Z_StoH: {
32860 switch (OpNum) {
32861 case 1:
32862 // op: Zn
32863 return 6;
32864 case 0:
32865 // op: Zd
32866 return 0;
32867 }
32868 break;
32869 }
32870 case AArch64::FCVTZS_2Z2Z_StoS:
32871 case AArch64::FCVTZU_2Z2Z_StoS:
32872 case AArch64::FRINTA_2Z2Z_S:
32873 case AArch64::FRINTM_2Z2Z_S:
32874 case AArch64::FRINTN_2Z2Z_S:
32875 case AArch64::FRINTP_2Z2Z_S:
32876 case AArch64::SCVTF_2Z2Z_StoS:
32877 case AArch64::UCVTF_2Z2Z_StoS: {
32878 switch (OpNum) {
32879 case 1:
32880 // op: Zn
32881 return 6;
32882 case 0:
32883 // op: Zd
32884 return 1;
32885 }
32886 break;
32887 }
32888 case AArch64::SUNPK_VG4_4Z2Z_D:
32889 case AArch64::SUNPK_VG4_4Z2Z_H:
32890 case AArch64::SUNPK_VG4_4Z2Z_S:
32891 case AArch64::UUNPK_VG4_4Z2Z_D:
32892 case AArch64::UUNPK_VG4_4Z2Z_H:
32893 case AArch64::UUNPK_VG4_4Z2Z_S: {
32894 switch (OpNum) {
32895 case 1:
32896 // op: Zn
32897 return 6;
32898 case 0:
32899 // op: Zd
32900 return 2;
32901 }
32902 break;
32903 }
32904 case AArch64::SQRSHRN_VG4_Z4ZI_B:
32905 case AArch64::SQRSHRN_VG4_Z4ZI_H:
32906 case AArch64::SQRSHRUN_VG4_Z4ZI_B:
32907 case AArch64::SQRSHRUN_VG4_Z4ZI_H:
32908 case AArch64::SQRSHRU_VG4_Z4ZI_B:
32909 case AArch64::SQRSHRU_VG4_Z4ZI_H:
32910 case AArch64::SQRSHR_VG4_Z4ZI_B:
32911 case AArch64::SQRSHR_VG4_Z4ZI_H:
32912 case AArch64::UQRSHRN_VG4_Z4ZI_B:
32913 case AArch64::UQRSHRN_VG4_Z4ZI_H:
32914 case AArch64::UQRSHR_VG4_Z4ZI_B:
32915 case AArch64::UQRSHR_VG4_Z4ZI_H: {
32916 switch (OpNum) {
32917 case 1:
32918 // op: Zn
32919 return 7;
32920 case 0:
32921 // op: Zd
32922 return 0;
32923 case 2:
32924 // op: imm
32925 return 16;
32926 }
32927 break;
32928 }
32929 case AArch64::FCVTN_Z4Z_StoB_NAME:
32930 case AArch64::FCVT_Z4Z_StoB_NAME:
32931 case AArch64::SQCVTN_Z4Z_DtoH:
32932 case AArch64::SQCVTN_Z4Z_StoB:
32933 case AArch64::SQCVTUN_Z4Z_DtoH:
32934 case AArch64::SQCVTUN_Z4Z_StoB:
32935 case AArch64::SQCVTU_Z4Z_DtoH:
32936 case AArch64::SQCVTU_Z4Z_StoB:
32937 case AArch64::SQCVT_Z4Z_DtoH:
32938 case AArch64::SQCVT_Z4Z_StoB:
32939 case AArch64::UQCVTN_Z4Z_DtoH:
32940 case AArch64::UQCVTN_Z4Z_StoB:
32941 case AArch64::UQCVT_Z4Z_DtoH:
32942 case AArch64::UQCVT_Z4Z_StoB: {
32943 switch (OpNum) {
32944 case 1:
32945 // op: Zn
32946 return 7;
32947 case 0:
32948 // op: Zd
32949 return 0;
32950 }
32951 break;
32952 }
32953 case AArch64::FCVTZS_4Z4Z_StoS:
32954 case AArch64::FCVTZU_4Z4Z_StoS:
32955 case AArch64::FRINTA_4Z4Z_S:
32956 case AArch64::FRINTM_4Z4Z_S:
32957 case AArch64::FRINTN_4Z4Z_S:
32958 case AArch64::FRINTP_4Z4Z_S:
32959 case AArch64::SCVTF_4Z4Z_StoS:
32960 case AArch64::UCVTF_4Z4Z_StoS:
32961 case AArch64::UZP_VG4_4Z4Z_B:
32962 case AArch64::UZP_VG4_4Z4Z_D:
32963 case AArch64::UZP_VG4_4Z4Z_H:
32964 case AArch64::UZP_VG4_4Z4Z_Q:
32965 case AArch64::UZP_VG4_4Z4Z_S:
32966 case AArch64::ZIP_VG4_4Z4Z_B:
32967 case AArch64::ZIP_VG4_4Z4Z_D:
32968 case AArch64::ZIP_VG4_4Z4Z_H:
32969 case AArch64::ZIP_VG4_4Z4Z_Q:
32970 case AArch64::ZIP_VG4_4Z4Z_S: {
32971 switch (OpNum) {
32972 case 1:
32973 // op: Zn
32974 return 7;
32975 case 0:
32976 // op: Zd
32977 return 2;
32978 }
32979 break;
32980 }
32981 case AArch64::MOVT_TIX: {
32982 switch (OpNum) {
32983 case 1:
32984 // op: imm3
32985 return 12;
32986 case 2:
32987 // op: Rt
32988 return 0;
32989 }
32990 break;
32991 }
32992 case AArch64::ABS_ZPmZ_B:
32993 case AArch64::ABS_ZPmZ_D:
32994 case AArch64::ABS_ZPmZ_H:
32995 case AArch64::ABS_ZPmZ_S:
32996 case AArch64::CLS_ZPmZ_B:
32997 case AArch64::CLS_ZPmZ_D:
32998 case AArch64::CLS_ZPmZ_H:
32999 case AArch64::CLS_ZPmZ_S:
33000 case AArch64::CLZ_ZPmZ_B:
33001 case AArch64::CLZ_ZPmZ_D:
33002 case AArch64::CLZ_ZPmZ_H:
33003 case AArch64::CLZ_ZPmZ_S:
33004 case AArch64::CNOT_ZPmZ_B:
33005 case AArch64::CNOT_ZPmZ_D:
33006 case AArch64::CNOT_ZPmZ_H:
33007 case AArch64::CNOT_ZPmZ_S:
33008 case AArch64::CNT_ZPmZ_B:
33009 case AArch64::CNT_ZPmZ_D:
33010 case AArch64::CNT_ZPmZ_H:
33011 case AArch64::CNT_ZPmZ_S:
33012 case AArch64::FABS_ZPmZ_D:
33013 case AArch64::FABS_ZPmZ_H:
33014 case AArch64::FABS_ZPmZ_S:
33015 case AArch64::FCVTX_ZPmZ_DtoS:
33016 case AArch64::FCVTZS_ZPmZ_DtoD:
33017 case AArch64::FCVTZS_ZPmZ_DtoS:
33018 case AArch64::FCVTZS_ZPmZ_HtoD:
33019 case AArch64::FCVTZS_ZPmZ_HtoH:
33020 case AArch64::FCVTZS_ZPmZ_HtoS:
33021 case AArch64::FCVTZS_ZPmZ_StoD:
33022 case AArch64::FCVTZS_ZPmZ_StoS:
33023 case AArch64::FCVTZU_ZPmZ_DtoD:
33024 case AArch64::FCVTZU_ZPmZ_DtoS:
33025 case AArch64::FCVTZU_ZPmZ_HtoD:
33026 case AArch64::FCVTZU_ZPmZ_HtoH:
33027 case AArch64::FCVTZU_ZPmZ_HtoS:
33028 case AArch64::FCVTZU_ZPmZ_StoD:
33029 case AArch64::FCVTZU_ZPmZ_StoS:
33030 case AArch64::FCVT_ZPmZ_DtoH:
33031 case AArch64::FCVT_ZPmZ_DtoS:
33032 case AArch64::FCVT_ZPmZ_HtoD:
33033 case AArch64::FCVT_ZPmZ_HtoS:
33034 case AArch64::FCVT_ZPmZ_StoD:
33035 case AArch64::FCVT_ZPmZ_StoH:
33036 case AArch64::FLOGB_ZPmZ_D:
33037 case AArch64::FLOGB_ZPmZ_H:
33038 case AArch64::FLOGB_ZPmZ_S:
33039 case AArch64::FNEG_ZPmZ_D:
33040 case AArch64::FNEG_ZPmZ_H:
33041 case AArch64::FNEG_ZPmZ_S:
33042 case AArch64::FRECPX_ZPmZ_D:
33043 case AArch64::FRECPX_ZPmZ_H:
33044 case AArch64::FRECPX_ZPmZ_S:
33045 case AArch64::FRINTA_ZPmZ_D:
33046 case AArch64::FRINTA_ZPmZ_H:
33047 case AArch64::FRINTA_ZPmZ_S:
33048 case AArch64::FRINTI_ZPmZ_D:
33049 case AArch64::FRINTI_ZPmZ_H:
33050 case AArch64::FRINTI_ZPmZ_S:
33051 case AArch64::FRINTM_ZPmZ_D:
33052 case AArch64::FRINTM_ZPmZ_H:
33053 case AArch64::FRINTM_ZPmZ_S:
33054 case AArch64::FRINTN_ZPmZ_D:
33055 case AArch64::FRINTN_ZPmZ_H:
33056 case AArch64::FRINTN_ZPmZ_S:
33057 case AArch64::FRINTP_ZPmZ_D:
33058 case AArch64::FRINTP_ZPmZ_H:
33059 case AArch64::FRINTP_ZPmZ_S:
33060 case AArch64::FRINTX_ZPmZ_D:
33061 case AArch64::FRINTX_ZPmZ_H:
33062 case AArch64::FRINTX_ZPmZ_S:
33063 case AArch64::FRINTZ_ZPmZ_D:
33064 case AArch64::FRINTZ_ZPmZ_H:
33065 case AArch64::FRINTZ_ZPmZ_S:
33066 case AArch64::FSQRT_ZPmZ_D:
33067 case AArch64::FSQRT_ZPmZ_H:
33068 case AArch64::FSQRT_ZPmZ_S:
33069 case AArch64::MOVPRFX_ZPmZ_B:
33070 case AArch64::MOVPRFX_ZPmZ_D:
33071 case AArch64::MOVPRFX_ZPmZ_H:
33072 case AArch64::MOVPRFX_ZPmZ_S:
33073 case AArch64::NEG_ZPmZ_B:
33074 case AArch64::NEG_ZPmZ_D:
33075 case AArch64::NEG_ZPmZ_H:
33076 case AArch64::NEG_ZPmZ_S:
33077 case AArch64::NOT_ZPmZ_B:
33078 case AArch64::NOT_ZPmZ_D:
33079 case AArch64::NOT_ZPmZ_H:
33080 case AArch64::NOT_ZPmZ_S:
33081 case AArch64::SCVTF_ZPmZ_DtoD:
33082 case AArch64::SCVTF_ZPmZ_DtoH:
33083 case AArch64::SCVTF_ZPmZ_DtoS:
33084 case AArch64::SCVTF_ZPmZ_HtoH:
33085 case AArch64::SCVTF_ZPmZ_StoD:
33086 case AArch64::SCVTF_ZPmZ_StoH:
33087 case AArch64::SCVTF_ZPmZ_StoS:
33088 case AArch64::SQABS_ZPmZ_B:
33089 case AArch64::SQABS_ZPmZ_D:
33090 case AArch64::SQABS_ZPmZ_H:
33091 case AArch64::SQABS_ZPmZ_S:
33092 case AArch64::SQNEG_ZPmZ_B:
33093 case AArch64::SQNEG_ZPmZ_D:
33094 case AArch64::SQNEG_ZPmZ_H:
33095 case AArch64::SQNEG_ZPmZ_S:
33096 case AArch64::SXTB_ZPmZ_D:
33097 case AArch64::SXTB_ZPmZ_H:
33098 case AArch64::SXTB_ZPmZ_S:
33099 case AArch64::SXTH_ZPmZ_D:
33100 case AArch64::SXTH_ZPmZ_S:
33101 case AArch64::SXTW_ZPmZ_D:
33102 case AArch64::UCVTF_ZPmZ_DtoD:
33103 case AArch64::UCVTF_ZPmZ_DtoH:
33104 case AArch64::UCVTF_ZPmZ_DtoS:
33105 case AArch64::UCVTF_ZPmZ_HtoH:
33106 case AArch64::UCVTF_ZPmZ_StoD:
33107 case AArch64::UCVTF_ZPmZ_StoH:
33108 case AArch64::UCVTF_ZPmZ_StoS:
33109 case AArch64::URECPE_ZPmZ_S:
33110 case AArch64::URSQRTE_ZPmZ_S:
33111 case AArch64::UXTB_ZPmZ_D:
33112 case AArch64::UXTB_ZPmZ_H:
33113 case AArch64::UXTB_ZPmZ_S:
33114 case AArch64::UXTH_ZPmZ_D:
33115 case AArch64::UXTH_ZPmZ_S:
33116 case AArch64::UXTW_ZPmZ_D: {
33117 switch (OpNum) {
33118 case 2:
33119 // op: Pg
33120 return 10;
33121 case 0:
33122 // op: Zd
33123 return 0;
33124 case 3:
33125 // op: Zn
33126 return 5;
33127 }
33128 break;
33129 }
33130 case AArch64::CPY_ZPmR_B:
33131 case AArch64::CPY_ZPmR_D:
33132 case AArch64::CPY_ZPmR_H:
33133 case AArch64::CPY_ZPmR_S: {
33134 switch (OpNum) {
33135 case 2:
33136 // op: Pg
33137 return 10;
33138 case 3:
33139 // op: Rn
33140 return 5;
33141 case 0:
33142 // op: Zd
33143 return 0;
33144 }
33145 break;
33146 }
33147 case AArch64::CPY_ZPmV_B:
33148 case AArch64::CPY_ZPmV_D:
33149 case AArch64::CPY_ZPmV_H:
33150 case AArch64::CPY_ZPmV_S: {
33151 switch (OpNum) {
33152 case 2:
33153 // op: Pg
33154 return 10;
33155 case 3:
33156 // op: Vn
33157 return 5;
33158 case 0:
33159 // op: Zd
33160 return 0;
33161 }
33162 break;
33163 }
33164 case AArch64::FCPY_ZPmI_D:
33165 case AArch64::FCPY_ZPmI_H:
33166 case AArch64::FCPY_ZPmI_S: {
33167 switch (OpNum) {
33168 case 2:
33169 // op: Pg
33170 return 16;
33171 case 0:
33172 // op: Zd
33173 return 0;
33174 case 3:
33175 // op: imm8
33176 return 5;
33177 }
33178 break;
33179 }
33180 case AArch64::DECP_ZP_D:
33181 case AArch64::DECP_ZP_H:
33182 case AArch64::DECP_ZP_S:
33183 case AArch64::INCP_ZP_D:
33184 case AArch64::INCP_ZP_H:
33185 case AArch64::INCP_ZP_S:
33186 case AArch64::SQDECP_ZP_D:
33187 case AArch64::SQDECP_ZP_H:
33188 case AArch64::SQDECP_ZP_S:
33189 case AArch64::SQINCP_ZP_D:
33190 case AArch64::SQINCP_ZP_H:
33191 case AArch64::SQINCP_ZP_S:
33192 case AArch64::UQDECP_ZP_D:
33193 case AArch64::UQDECP_ZP_H:
33194 case AArch64::UQDECP_ZP_S:
33195 case AArch64::UQINCP_ZP_D:
33196 case AArch64::UQINCP_ZP_H:
33197 case AArch64::UQINCP_ZP_S: {
33198 switch (OpNum) {
33199 case 2:
33200 // op: Pm
33201 return 5;
33202 case 0:
33203 // op: Zdn
33204 return 0;
33205 }
33206 break;
33207 }
33208 case AArch64::MOPSSETGE:
33209 case AArch64::MOPSSETGEN:
33210 case AArch64::MOPSSETGET:
33211 case AArch64::MOPSSETGETN:
33212 case AArch64::SETE:
33213 case AArch64::SETEN:
33214 case AArch64::SETET:
33215 case AArch64::SETETN:
33216 case AArch64::SETGM:
33217 case AArch64::SETGMN:
33218 case AArch64::SETGMT:
33219 case AArch64::SETGMTN:
33220 case AArch64::SETGP:
33221 case AArch64::SETGPN:
33222 case AArch64::SETGPT:
33223 case AArch64::SETGPTN:
33224 case AArch64::SETM:
33225 case AArch64::SETMN:
33226 case AArch64::SETMT:
33227 case AArch64::SETMTN:
33228 case AArch64::SETP:
33229 case AArch64::SETPN:
33230 case AArch64::SETPT:
33231 case AArch64::SETPTN: {
33232 switch (OpNum) {
33233 case 2:
33234 // op: Rd
33235 return 0;
33236 case 3:
33237 // op: Rn
33238 return 5;
33239 case 4:
33240 // op: Rm
33241 return 16;
33242 }
33243 break;
33244 }
33245 case AArch64::INDEX_IR_B:
33246 case AArch64::INDEX_IR_D:
33247 case AArch64::INDEX_IR_H:
33248 case AArch64::INDEX_IR_S: {
33249 switch (OpNum) {
33250 case 2:
33251 // op: Rm
33252 return 16;
33253 case 0:
33254 // op: Zd
33255 return 0;
33256 case 1:
33257 // op: imm5
33258 return 5;
33259 }
33260 break;
33261 }
33262 case AArch64::INSR_ZR_B:
33263 case AArch64::INSR_ZR_D:
33264 case AArch64::INSR_ZR_H:
33265 case AArch64::INSR_ZR_S: {
33266 switch (OpNum) {
33267 case 2:
33268 // op: Rm
33269 return 5;
33270 case 0:
33271 // op: Zdn
33272 return 0;
33273 }
33274 break;
33275 }
33276 case AArch64::PRFB_PRI:
33277 case AArch64::PRFD_PRI:
33278 case AArch64::PRFH_PRI:
33279 case AArch64::PRFW_PRI: {
33280 switch (OpNum) {
33281 case 2:
33282 // op: Rn
33283 return 5;
33284 case 1:
33285 // op: Pg
33286 return 10;
33287 case 3:
33288 // op: imm6
33289 return 16;
33290 case 0:
33291 // op: prfop
33292 return 0;
33293 }
33294 break;
33295 }
33296 case AArch64::LDG:
33297 case AArch64::ST2GPostIndex:
33298 case AArch64::ST2GPreIndex:
33299 case AArch64::STGPostIndex:
33300 case AArch64::STGPreIndex:
33301 case AArch64::STZ2GPostIndex:
33302 case AArch64::STZ2GPreIndex:
33303 case AArch64::STZGPostIndex:
33304 case AArch64::STZGPreIndex: {
33305 switch (OpNum) {
33306 case 2:
33307 // op: Rn
33308 return 5;
33309 case 1:
33310 // op: Rt
33311 return 0;
33312 case 3:
33313 // op: offset
33314 return 12;
33315 }
33316 break;
33317 }
33318 case AArch64::MOVA_VG2_MXI2Z: {
33319 switch (OpNum) {
33320 case 2:
33321 // op: Rs
33322 return 13;
33323 case 3:
33324 // op: imm
33325 return 0;
33326 case 4:
33327 // op: Zn
33328 return 6;
33329 }
33330 break;
33331 }
33332 case AArch64::MOVA_VG4_MXI4Z: {
33333 switch (OpNum) {
33334 case 2:
33335 // op: Rs
33336 return 13;
33337 case 3:
33338 // op: imm
33339 return 0;
33340 case 4:
33341 // op: Zn
33342 return 7;
33343 }
33344 break;
33345 }
33346 case AArch64::MOVA_VG2_2ZMXI: {
33347 switch (OpNum) {
33348 case 2:
33349 // op: Rs
33350 return 13;
33351 case 3:
33352 // op: imm
33353 return 5;
33354 case 0:
33355 // op: Zd
33356 return 1;
33357 }
33358 break;
33359 }
33360 case AArch64::MOVA_VG4_4ZMXI: {
33361 switch (OpNum) {
33362 case 2:
33363 // op: Rs
33364 return 13;
33365 case 3:
33366 // op: imm
33367 return 5;
33368 case 0:
33369 // op: Zd
33370 return 2;
33371 }
33372 break;
33373 }
33374 case AArch64::MOVA_MXI2Z_H_D:
33375 case AArch64::MOVA_MXI2Z_V_D: {
33376 switch (OpNum) {
33377 case 2:
33378 // op: Rs
33379 return 13;
33380 case 4:
33381 // op: Zn
33382 return 6;
33383 case 0:
33384 // op: ZAd
33385 return 0;
33386 }
33387 break;
33388 }
33389 case AArch64::MOVA_MXI2Z_H_S:
33390 case AArch64::MOVA_MXI2Z_V_S: {
33391 switch (OpNum) {
33392 case 2:
33393 // op: Rs
33394 return 13;
33395 case 4:
33396 // op: Zn
33397 return 6;
33398 case 0:
33399 // op: ZAd
33400 return 1;
33401 case 3:
33402 // op: imm
33403 return 0;
33404 }
33405 break;
33406 }
33407 case AArch64::MOVA_MXI2Z_H_H:
33408 case AArch64::MOVA_MXI2Z_V_H: {
33409 switch (OpNum) {
33410 case 2:
33411 // op: Rs
33412 return 13;
33413 case 4:
33414 // op: Zn
33415 return 6;
33416 case 0:
33417 // op: ZAd
33418 return 2;
33419 case 3:
33420 // op: imm
33421 return 0;
33422 }
33423 break;
33424 }
33425 case AArch64::MOVA_MXI2Z_H_B:
33426 case AArch64::MOVA_MXI2Z_V_B: {
33427 switch (OpNum) {
33428 case 2:
33429 // op: Rs
33430 return 13;
33431 case 4:
33432 // op: Zn
33433 return 6;
33434 case 3:
33435 // op: imm
33436 return 0;
33437 }
33438 break;
33439 }
33440 case AArch64::MOVA_MXI4Z_H_D:
33441 case AArch64::MOVA_MXI4Z_H_S:
33442 case AArch64::MOVA_MXI4Z_V_D:
33443 case AArch64::MOVA_MXI4Z_V_S: {
33444 switch (OpNum) {
33445 case 2:
33446 // op: Rs
33447 return 13;
33448 case 4:
33449 // op: Zn
33450 return 7;
33451 case 0:
33452 // op: ZAd
33453 return 0;
33454 }
33455 break;
33456 }
33457 case AArch64::MOVA_MXI4Z_H_H:
33458 case AArch64::MOVA_MXI4Z_V_H: {
33459 switch (OpNum) {
33460 case 2:
33461 // op: Rs
33462 return 13;
33463 case 4:
33464 // op: Zn
33465 return 7;
33466 case 0:
33467 // op: ZAd
33468 return 1;
33469 case 3:
33470 // op: imm
33471 return 0;
33472 }
33473 break;
33474 }
33475 case AArch64::MOVA_MXI4Z_H_B:
33476 case AArch64::MOVA_MXI4Z_V_B: {
33477 switch (OpNum) {
33478 case 2:
33479 // op: Rs
33480 return 13;
33481 case 4:
33482 // op: Zn
33483 return 7;
33484 case 3:
33485 // op: imm
33486 return 0;
33487 }
33488 break;
33489 }
33490 case AArch64::LDCLRP:
33491 case AArch64::LDCLRPA:
33492 case AArch64::LDCLRPAL:
33493 case AArch64::LDCLRPL:
33494 case AArch64::LDSETP:
33495 case AArch64::LDSETPA:
33496 case AArch64::LDSETPAL:
33497 case AArch64::LDSETPL:
33498 case AArch64::SWPP:
33499 case AArch64::SWPPA:
33500 case AArch64::SWPPAL:
33501 case AArch64::SWPPL: {
33502 switch (OpNum) {
33503 case 2:
33504 // op: Rt
33505 return 0;
33506 case 3:
33507 // op: Rt2
33508 return 16;
33509 case 4:
33510 // op: Rn
33511 return 5;
33512 }
33513 break;
33514 }
33515 case AArch64::ZERO_MXI_2Z:
33516 case AArch64::ZERO_MXI_4Z:
33517 case AArch64::ZERO_MXI_VG2_2Z:
33518 case AArch64::ZERO_MXI_VG2_4Z:
33519 case AArch64::ZERO_MXI_VG2_Z:
33520 case AArch64::ZERO_MXI_VG4_2Z:
33521 case AArch64::ZERO_MXI_VG4_4Z:
33522 case AArch64::ZERO_MXI_VG4_Z: {
33523 switch (OpNum) {
33524 case 2:
33525 // op: Rv
33526 return 13;
33527 case 3:
33528 // op: imm
33529 return 0;
33530 }
33531 break;
33532 }
33533 case AArch64::ADD_VG2_M2Z_D:
33534 case AArch64::ADD_VG2_M2Z_S:
33535 case AArch64::BFADD_VG2_M2Z_H:
33536 case AArch64::BFSUB_VG2_M2Z_H:
33537 case AArch64::FADD_VG2_M2Z_D:
33538 case AArch64::FADD_VG2_M2Z_H:
33539 case AArch64::FADD_VG2_M2Z_S:
33540 case AArch64::FSUB_VG2_M2Z_D:
33541 case AArch64::FSUB_VG2_M2Z_H:
33542 case AArch64::FSUB_VG2_M2Z_S:
33543 case AArch64::SUB_VG2_M2Z_D:
33544 case AArch64::SUB_VG2_M2Z_S: {
33545 switch (OpNum) {
33546 case 2:
33547 // op: Rv
33548 return 13;
33549 case 3:
33550 // op: imm3
33551 return 0;
33552 case 4:
33553 // op: Zm
33554 return 6;
33555 }
33556 break;
33557 }
33558 case AArch64::ADD_VG4_M4Z_D:
33559 case AArch64::ADD_VG4_M4Z_S:
33560 case AArch64::BFADD_VG4_M4Z_H:
33561 case AArch64::BFSUB_VG4_M4Z_H:
33562 case AArch64::FADD_VG4_M4Z_D:
33563 case AArch64::FADD_VG4_M4Z_H:
33564 case AArch64::FADD_VG4_M4Z_S:
33565 case AArch64::FSUB_VG4_M4Z_D:
33566 case AArch64::FSUB_VG4_M4Z_H:
33567 case AArch64::FSUB_VG4_M4Z_S:
33568 case AArch64::SUB_VG4_M4Z_D:
33569 case AArch64::SUB_VG4_M4Z_S: {
33570 switch (OpNum) {
33571 case 2:
33572 // op: Rv
33573 return 13;
33574 case 3:
33575 // op: imm3
33576 return 0;
33577 case 4:
33578 // op: Zm
33579 return 7;
33580 }
33581 break;
33582 }
33583 case AArch64::INSERT_MXIPZ_H_Q:
33584 case AArch64::INSERT_MXIPZ_V_Q: {
33585 switch (OpNum) {
33586 case 2:
33587 // op: Rv
33588 return 13;
33589 case 4:
33590 // op: Pg
33591 return 10;
33592 case 5:
33593 // op: Zn
33594 return 5;
33595 case 0:
33596 // op: ZAd
33597 return 0;
33598 }
33599 break;
33600 }
33601 case AArch64::INSERT_MXIPZ_H_D:
33602 case AArch64::INSERT_MXIPZ_V_D: {
33603 switch (OpNum) {
33604 case 2:
33605 // op: Rv
33606 return 13;
33607 case 4:
33608 // op: Pg
33609 return 10;
33610 case 5:
33611 // op: Zn
33612 return 5;
33613 case 0:
33614 // op: ZAd
33615 return 1;
33616 case 3:
33617 // op: imm
33618 return 0;
33619 }
33620 break;
33621 }
33622 case AArch64::INSERT_MXIPZ_H_S:
33623 case AArch64::INSERT_MXIPZ_V_S: {
33624 switch (OpNum) {
33625 case 2:
33626 // op: Rv
33627 return 13;
33628 case 4:
33629 // op: Pg
33630 return 10;
33631 case 5:
33632 // op: Zn
33633 return 5;
33634 case 0:
33635 // op: ZAd
33636 return 2;
33637 case 3:
33638 // op: imm
33639 return 0;
33640 }
33641 break;
33642 }
33643 case AArch64::INSERT_MXIPZ_H_H:
33644 case AArch64::INSERT_MXIPZ_V_H: {
33645 switch (OpNum) {
33646 case 2:
33647 // op: Rv
33648 return 13;
33649 case 4:
33650 // op: Pg
33651 return 10;
33652 case 5:
33653 // op: Zn
33654 return 5;
33655 case 0:
33656 // op: ZAd
33657 return 3;
33658 case 3:
33659 // op: imm
33660 return 0;
33661 }
33662 break;
33663 }
33664 case AArch64::INSERT_MXIPZ_H_B:
33665 case AArch64::INSERT_MXIPZ_V_B: {
33666 switch (OpNum) {
33667 case 2:
33668 // op: Rv
33669 return 13;
33670 case 4:
33671 // op: Pg
33672 return 10;
33673 case 5:
33674 // op: Zn
33675 return 5;
33676 case 3:
33677 // op: imm
33678 return 0;
33679 }
33680 break;
33681 }
33682 case AArch64::BFMLAL_MZZ_HtoS:
33683 case AArch64::BFMLAL_VG2_M2ZZ_HtoS:
33684 case AArch64::BFMLAL_VG4_M4ZZ_HtoS:
33685 case AArch64::BFMLSL_MZZ_HtoS:
33686 case AArch64::BFMLSL_VG2_M2ZZ_HtoS:
33687 case AArch64::BFMLSL_VG4_M4ZZ_HtoS:
33688 case AArch64::FMLAL_MZZ_HtoS:
33689 case AArch64::FMLAL_VG2_M2ZZ_BtoH:
33690 case AArch64::FMLAL_VG2_M2ZZ_HtoS:
33691 case AArch64::FMLAL_VG2_MZZ_BtoH:
33692 case AArch64::FMLAL_VG4_M4ZZ_BtoH:
33693 case AArch64::FMLAL_VG4_M4ZZ_HtoS:
33694 case AArch64::FMLSL_MZZ_HtoS:
33695 case AArch64::FMLSL_VG2_M2ZZ_HtoS:
33696 case AArch64::FMLSL_VG4_M4ZZ_HtoS:
33697 case AArch64::SMLAL_MZZ_HtoS:
33698 case AArch64::SMLAL_VG2_M2ZZ_HtoS:
33699 case AArch64::SMLAL_VG4_M4ZZ_HtoS:
33700 case AArch64::SMLSL_MZZ_HtoS:
33701 case AArch64::SMLSL_VG2_M2ZZ_HtoS:
33702 case AArch64::SMLSL_VG4_M4ZZ_HtoS:
33703 case AArch64::UMLAL_MZZ_HtoS:
33704 case AArch64::UMLAL_VG2_M2ZZ_HtoS:
33705 case AArch64::UMLAL_VG4_M4ZZ_HtoS:
33706 case AArch64::UMLSL_MZZ_HtoS:
33707 case AArch64::UMLSL_VG2_M2ZZ_HtoS:
33708 case AArch64::UMLSL_VG4_M4ZZ_HtoS: {
33709 switch (OpNum) {
33710 case 2:
33711 // op: Rv
33712 return 13;
33713 case 5:
33714 // op: Zm
33715 return 16;
33716 case 4:
33717 // op: Zn
33718 return 5;
33719 case 3:
33720 // op: imm
33721 return 0;
33722 }
33723 break;
33724 }
33725 case AArch64::BFMLAL_VG2_M2Z2Z_HtoS:
33726 case AArch64::BFMLSL_VG2_M2Z2Z_HtoS:
33727 case AArch64::FMLAL_VG2_M2Z2Z_BtoH:
33728 case AArch64::FMLAL_VG2_M2Z2Z_HtoS:
33729 case AArch64::FMLSL_VG2_M2Z2Z_HtoS:
33730 case AArch64::SMLAL_VG2_M2Z2Z_HtoS:
33731 case AArch64::SMLSL_VG2_M2Z2Z_HtoS:
33732 case AArch64::UMLAL_VG2_M2Z2Z_HtoS:
33733 case AArch64::UMLSL_VG2_M2Z2Z_HtoS: {
33734 switch (OpNum) {
33735 case 2:
33736 // op: Rv
33737 return 13;
33738 case 5:
33739 // op: Zm
33740 return 17;
33741 case 4:
33742 // op: Zn
33743 return 6;
33744 case 3:
33745 // op: imm
33746 return 0;
33747 }
33748 break;
33749 }
33750 case AArch64::BFMLAL_VG4_M4Z4Z_HtoS:
33751 case AArch64::BFMLSL_VG4_M4Z4Z_HtoS:
33752 case AArch64::FMLAL_VG4_M4Z4Z_BtoH:
33753 case AArch64::FMLAL_VG4_M4Z4Z_HtoS:
33754 case AArch64::FMLSL_VG4_M4Z4Z_HtoS:
33755 case AArch64::SMLAL_VG4_M4Z4Z_HtoS:
33756 case AArch64::SMLSL_VG4_M4Z4Z_HtoS:
33757 case AArch64::UMLAL_VG4_M4Z4Z_HtoS:
33758 case AArch64::UMLSL_VG4_M4Z4Z_HtoS: {
33759 switch (OpNum) {
33760 case 2:
33761 // op: Rv
33762 return 13;
33763 case 5:
33764 // op: Zm
33765 return 18;
33766 case 4:
33767 // op: Zn
33768 return 7;
33769 case 3:
33770 // op: imm
33771 return 0;
33772 }
33773 break;
33774 }
33775 case AArch64::INSR_ZV_B:
33776 case AArch64::INSR_ZV_D:
33777 case AArch64::INSR_ZV_H:
33778 case AArch64::INSR_ZV_S: {
33779 switch (OpNum) {
33780 case 2:
33781 // op: Vm
33782 return 5;
33783 case 0:
33784 // op: Zdn
33785 return 0;
33786 }
33787 break;
33788 }
33789 case AArch64::LD1i8_POST:
33790 case AArch64::LD2i8_POST:
33791 case AArch64::LD3i8_POST:
33792 case AArch64::LD4i8_POST: {
33793 switch (OpNum) {
33794 case 2:
33795 // op: Vt
33796 return 0;
33797 case 4:
33798 // op: Rn
33799 return 5;
33800 case 3:
33801 // op: idx
33802 return 10;
33803 case 5:
33804 // op: Xm
33805 return 16;
33806 }
33807 break;
33808 }
33809 case AArch64::LD1i16_POST:
33810 case AArch64::LD2i16_POST:
33811 case AArch64::LD3i16_POST:
33812 case AArch64::LD4i16_POST: {
33813 switch (OpNum) {
33814 case 2:
33815 // op: Vt
33816 return 0;
33817 case 4:
33818 // op: Rn
33819 return 5;
33820 case 3:
33821 // op: idx
33822 return 11;
33823 case 5:
33824 // op: Xm
33825 return 16;
33826 }
33827 break;
33828 }
33829 case AArch64::LD1i32_POST:
33830 case AArch64::LD2i32_POST:
33831 case AArch64::LD3i32_POST:
33832 case AArch64::LD4i32_POST: {
33833 switch (OpNum) {
33834 case 2:
33835 // op: Vt
33836 return 0;
33837 case 4:
33838 // op: Rn
33839 return 5;
33840 case 3:
33841 // op: idx
33842 return 12;
33843 case 5:
33844 // op: Xm
33845 return 16;
33846 }
33847 break;
33848 }
33849 case AArch64::LD1i64_POST:
33850 case AArch64::LD2i64_POST:
33851 case AArch64::LD3i64_POST:
33852 case AArch64::LD4i64_POST: {
33853 switch (OpNum) {
33854 case 2:
33855 // op: Vt
33856 return 0;
33857 case 4:
33858 // op: Rn
33859 return 5;
33860 case 3:
33861 // op: idx
33862 return 30;
33863 case 5:
33864 // op: Xm
33865 return 16;
33866 }
33867 break;
33868 }
33869 case AArch64::ADD_VG2_2ZZ_B:
33870 case AArch64::ADD_VG2_2ZZ_D:
33871 case AArch64::ADD_VG2_2ZZ_H:
33872 case AArch64::ADD_VG2_2ZZ_S:
33873 case AArch64::BFMAXNM_VG2_2ZZ_H:
33874 case AArch64::BFMAX_VG2_2ZZ_H:
33875 case AArch64::BFMINNM_VG2_2ZZ_H:
33876 case AArch64::BFMIN_VG2_2ZZ_H:
33877 case AArch64::FMAXNM_VG2_2ZZ_D:
33878 case AArch64::FMAXNM_VG2_2ZZ_H:
33879 case AArch64::FMAXNM_VG2_2ZZ_S:
33880 case AArch64::FMAX_VG2_2ZZ_D:
33881 case AArch64::FMAX_VG2_2ZZ_H:
33882 case AArch64::FMAX_VG2_2ZZ_S:
33883 case AArch64::FMINNM_VG2_2ZZ_D:
33884 case AArch64::FMINNM_VG2_2ZZ_H:
33885 case AArch64::FMINNM_VG2_2ZZ_S:
33886 case AArch64::FMIN_VG2_2ZZ_D:
33887 case AArch64::FMIN_VG2_2ZZ_H:
33888 case AArch64::FMIN_VG2_2ZZ_S:
33889 case AArch64::FSCALE_2ZZ_D:
33890 case AArch64::FSCALE_2ZZ_H:
33891 case AArch64::FSCALE_2ZZ_S:
33892 case AArch64::SMAX_VG2_2ZZ_B:
33893 case AArch64::SMAX_VG2_2ZZ_D:
33894 case AArch64::SMAX_VG2_2ZZ_H:
33895 case AArch64::SMAX_VG2_2ZZ_S:
33896 case AArch64::SMIN_VG2_2ZZ_B:
33897 case AArch64::SMIN_VG2_2ZZ_D:
33898 case AArch64::SMIN_VG2_2ZZ_H:
33899 case AArch64::SMIN_VG2_2ZZ_S:
33900 case AArch64::SQDMULH_VG2_2ZZ_B:
33901 case AArch64::SQDMULH_VG2_2ZZ_D:
33902 case AArch64::SQDMULH_VG2_2ZZ_H:
33903 case AArch64::SQDMULH_VG2_2ZZ_S:
33904 case AArch64::SRSHL_VG2_2ZZ_B:
33905 case AArch64::SRSHL_VG2_2ZZ_D:
33906 case AArch64::SRSHL_VG2_2ZZ_H:
33907 case AArch64::SRSHL_VG2_2ZZ_S:
33908 case AArch64::UMAX_VG2_2ZZ_B:
33909 case AArch64::UMAX_VG2_2ZZ_D:
33910 case AArch64::UMAX_VG2_2ZZ_H:
33911 case AArch64::UMAX_VG2_2ZZ_S:
33912 case AArch64::UMIN_VG2_2ZZ_B:
33913 case AArch64::UMIN_VG2_2ZZ_D:
33914 case AArch64::UMIN_VG2_2ZZ_H:
33915 case AArch64::UMIN_VG2_2ZZ_S:
33916 case AArch64::URSHL_VG2_2ZZ_B:
33917 case AArch64::URSHL_VG2_2ZZ_D:
33918 case AArch64::URSHL_VG2_2ZZ_H:
33919 case AArch64::URSHL_VG2_2ZZ_S: {
33920 switch (OpNum) {
33921 case 2:
33922 // op: Zm
33923 return 16;
33924 case 0:
33925 // op: Zdn
33926 return 1;
33927 }
33928 break;
33929 }
33930 case AArch64::ADD_VG4_4ZZ_B:
33931 case AArch64::ADD_VG4_4ZZ_D:
33932 case AArch64::ADD_VG4_4ZZ_H:
33933 case AArch64::ADD_VG4_4ZZ_S:
33934 case AArch64::BFMAXNM_VG4_4ZZ_H:
33935 case AArch64::BFMAX_VG4_4ZZ_H:
33936 case AArch64::BFMINNM_VG4_4ZZ_H:
33937 case AArch64::BFMIN_VG4_4ZZ_H:
33938 case AArch64::FMAXNM_VG4_4ZZ_D:
33939 case AArch64::FMAXNM_VG4_4ZZ_H:
33940 case AArch64::FMAXNM_VG4_4ZZ_S:
33941 case AArch64::FMAX_VG4_4ZZ_D:
33942 case AArch64::FMAX_VG4_4ZZ_H:
33943 case AArch64::FMAX_VG4_4ZZ_S:
33944 case AArch64::FMINNM_VG4_4ZZ_D:
33945 case AArch64::FMINNM_VG4_4ZZ_H:
33946 case AArch64::FMINNM_VG4_4ZZ_S:
33947 case AArch64::FMIN_VG4_4ZZ_D:
33948 case AArch64::FMIN_VG4_4ZZ_H:
33949 case AArch64::FMIN_VG4_4ZZ_S:
33950 case AArch64::FSCALE_4ZZ_D:
33951 case AArch64::FSCALE_4ZZ_H:
33952 case AArch64::FSCALE_4ZZ_S:
33953 case AArch64::SMAX_VG4_4ZZ_B:
33954 case AArch64::SMAX_VG4_4ZZ_D:
33955 case AArch64::SMAX_VG4_4ZZ_H:
33956 case AArch64::SMAX_VG4_4ZZ_S:
33957 case AArch64::SMIN_VG4_4ZZ_B:
33958 case AArch64::SMIN_VG4_4ZZ_D:
33959 case AArch64::SMIN_VG4_4ZZ_H:
33960 case AArch64::SMIN_VG4_4ZZ_S:
33961 case AArch64::SQDMULH_VG4_4ZZ_B:
33962 case AArch64::SQDMULH_VG4_4ZZ_D:
33963 case AArch64::SQDMULH_VG4_4ZZ_H:
33964 case AArch64::SQDMULH_VG4_4ZZ_S:
33965 case AArch64::SRSHL_VG4_4ZZ_B:
33966 case AArch64::SRSHL_VG4_4ZZ_D:
33967 case AArch64::SRSHL_VG4_4ZZ_H:
33968 case AArch64::SRSHL_VG4_4ZZ_S:
33969 case AArch64::UMAX_VG4_4ZZ_B:
33970 case AArch64::UMAX_VG4_4ZZ_D:
33971 case AArch64::UMAX_VG4_4ZZ_H:
33972 case AArch64::UMAX_VG4_4ZZ_S:
33973 case AArch64::UMIN_VG4_4ZZ_B:
33974 case AArch64::UMIN_VG4_4ZZ_D:
33975 case AArch64::UMIN_VG4_4ZZ_H:
33976 case AArch64::UMIN_VG4_4ZZ_S:
33977 case AArch64::URSHL_VG4_4ZZ_B:
33978 case AArch64::URSHL_VG4_4ZZ_D:
33979 case AArch64::URSHL_VG4_4ZZ_H:
33980 case AArch64::URSHL_VG4_4ZZ_S: {
33981 switch (OpNum) {
33982 case 2:
33983 // op: Zm
33984 return 16;
33985 case 0:
33986 // op: Zdn
33987 return 2;
33988 }
33989 break;
33990 }
33991 case AArch64::BFMAXNM_VG2_2Z2Z_H:
33992 case AArch64::BFMAX_VG2_2Z2Z_H:
33993 case AArch64::BFMINNM_VG2_2Z2Z_H:
33994 case AArch64::BFMIN_VG2_2Z2Z_H:
33995 case AArch64::FAMAX_2Z2Z_D:
33996 case AArch64::FAMAX_2Z2Z_H:
33997 case AArch64::FAMAX_2Z2Z_S:
33998 case AArch64::FAMIN_2Z2Z_D:
33999 case AArch64::FAMIN_2Z2Z_H:
34000 case AArch64::FAMIN_2Z2Z_S:
34001 case AArch64::FMAXNM_VG2_2Z2Z_D:
34002 case AArch64::FMAXNM_VG2_2Z2Z_H:
34003 case AArch64::FMAXNM_VG2_2Z2Z_S:
34004 case AArch64::FMAX_VG2_2Z2Z_D:
34005 case AArch64::FMAX_VG2_2Z2Z_H:
34006 case AArch64::FMAX_VG2_2Z2Z_S:
34007 case AArch64::FMINNM_VG2_2Z2Z_D:
34008 case AArch64::FMINNM_VG2_2Z2Z_H:
34009 case AArch64::FMINNM_VG2_2Z2Z_S:
34010 case AArch64::FMIN_VG2_2Z2Z_D:
34011 case AArch64::FMIN_VG2_2Z2Z_H:
34012 case AArch64::FMIN_VG2_2Z2Z_S:
34013 case AArch64::FSCALE_2Z2Z_D:
34014 case AArch64::FSCALE_2Z2Z_H:
34015 case AArch64::FSCALE_2Z2Z_S:
34016 case AArch64::SMAX_VG2_2Z2Z_B:
34017 case AArch64::SMAX_VG2_2Z2Z_D:
34018 case AArch64::SMAX_VG2_2Z2Z_H:
34019 case AArch64::SMAX_VG2_2Z2Z_S:
34020 case AArch64::SMIN_VG2_2Z2Z_B:
34021 case AArch64::SMIN_VG2_2Z2Z_D:
34022 case AArch64::SMIN_VG2_2Z2Z_H:
34023 case AArch64::SMIN_VG2_2Z2Z_S:
34024 case AArch64::SQDMULH_VG2_2Z2Z_B:
34025 case AArch64::SQDMULH_VG2_2Z2Z_D:
34026 case AArch64::SQDMULH_VG2_2Z2Z_H:
34027 case AArch64::SQDMULH_VG2_2Z2Z_S:
34028 case AArch64::SRSHL_VG2_2Z2Z_B:
34029 case AArch64::SRSHL_VG2_2Z2Z_D:
34030 case AArch64::SRSHL_VG2_2Z2Z_H:
34031 case AArch64::SRSHL_VG2_2Z2Z_S:
34032 case AArch64::UMAX_VG2_2Z2Z_B:
34033 case AArch64::UMAX_VG2_2Z2Z_D:
34034 case AArch64::UMAX_VG2_2Z2Z_H:
34035 case AArch64::UMAX_VG2_2Z2Z_S:
34036 case AArch64::UMIN_VG2_2Z2Z_B:
34037 case AArch64::UMIN_VG2_2Z2Z_D:
34038 case AArch64::UMIN_VG2_2Z2Z_H:
34039 case AArch64::UMIN_VG2_2Z2Z_S:
34040 case AArch64::URSHL_VG2_2Z2Z_B:
34041 case AArch64::URSHL_VG2_2Z2Z_D:
34042 case AArch64::URSHL_VG2_2Z2Z_H:
34043 case AArch64::URSHL_VG2_2Z2Z_S: {
34044 switch (OpNum) {
34045 case 2:
34046 // op: Zm
34047 return 17;
34048 case 0:
34049 // op: Zdn
34050 return 1;
34051 }
34052 break;
34053 }
34054 case AArch64::BFMAXNM_VG4_4Z2Z_H:
34055 case AArch64::BFMAX_VG4_4Z2Z_H:
34056 case AArch64::BFMINNM_VG4_4Z2Z_H:
34057 case AArch64::BFMIN_VG4_4Z2Z_H:
34058 case AArch64::FAMAX_4Z4Z_D:
34059 case AArch64::FAMAX_4Z4Z_H:
34060 case AArch64::FAMAX_4Z4Z_S:
34061 case AArch64::FAMIN_4Z4Z_D:
34062 case AArch64::FAMIN_4Z4Z_H:
34063 case AArch64::FAMIN_4Z4Z_S:
34064 case AArch64::FMAXNM_VG4_4Z4Z_D:
34065 case AArch64::FMAXNM_VG4_4Z4Z_H:
34066 case AArch64::FMAXNM_VG4_4Z4Z_S:
34067 case AArch64::FMAX_VG4_4Z4Z_D:
34068 case AArch64::FMAX_VG4_4Z4Z_H:
34069 case AArch64::FMAX_VG4_4Z4Z_S:
34070 case AArch64::FMINNM_VG4_4Z4Z_D:
34071 case AArch64::FMINNM_VG4_4Z4Z_H:
34072 case AArch64::FMINNM_VG4_4Z4Z_S:
34073 case AArch64::FMIN_VG4_4Z4Z_D:
34074 case AArch64::FMIN_VG4_4Z4Z_H:
34075 case AArch64::FMIN_VG4_4Z4Z_S:
34076 case AArch64::FSCALE_4Z4Z_D:
34077 case AArch64::FSCALE_4Z4Z_H:
34078 case AArch64::FSCALE_4Z4Z_S:
34079 case AArch64::SMAX_VG4_4Z4Z_B:
34080 case AArch64::SMAX_VG4_4Z4Z_D:
34081 case AArch64::SMAX_VG4_4Z4Z_H:
34082 case AArch64::SMAX_VG4_4Z4Z_S:
34083 case AArch64::SMIN_VG4_4Z4Z_B:
34084 case AArch64::SMIN_VG4_4Z4Z_D:
34085 case AArch64::SMIN_VG4_4Z4Z_H:
34086 case AArch64::SMIN_VG4_4Z4Z_S:
34087 case AArch64::SQDMULH_VG4_4Z4Z_B:
34088 case AArch64::SQDMULH_VG4_4Z4Z_D:
34089 case AArch64::SQDMULH_VG4_4Z4Z_H:
34090 case AArch64::SQDMULH_VG4_4Z4Z_S:
34091 case AArch64::SRSHL_VG4_4Z4Z_B:
34092 case AArch64::SRSHL_VG4_4Z4Z_D:
34093 case AArch64::SRSHL_VG4_4Z4Z_H:
34094 case AArch64::SRSHL_VG4_4Z4Z_S:
34095 case AArch64::UMAX_VG4_4Z4Z_B:
34096 case AArch64::UMAX_VG4_4Z4Z_D:
34097 case AArch64::UMAX_VG4_4Z4Z_H:
34098 case AArch64::UMAX_VG4_4Z4Z_S:
34099 case AArch64::UMIN_VG4_4Z4Z_B:
34100 case AArch64::UMIN_VG4_4Z4Z_D:
34101 case AArch64::UMIN_VG4_4Z4Z_H:
34102 case AArch64::UMIN_VG4_4Z4Z_S:
34103 case AArch64::URSHL_VG4_4Z4Z_B:
34104 case AArch64::URSHL_VG4_4Z4Z_D:
34105 case AArch64::URSHL_VG4_4Z4Z_H:
34106 case AArch64::URSHL_VG4_4Z4Z_S: {
34107 switch (OpNum) {
34108 case 2:
34109 // op: Zm
34110 return 18;
34111 case 0:
34112 // op: Zdn
34113 return 2;
34114 }
34115 break;
34116 }
34117 case AArch64::FADDV_VPZ_D:
34118 case AArch64::FADDV_VPZ_H:
34119 case AArch64::FADDV_VPZ_S:
34120 case AArch64::FMAXNMV_VPZ_D:
34121 case AArch64::FMAXNMV_VPZ_H:
34122 case AArch64::FMAXNMV_VPZ_S:
34123 case AArch64::FMAXV_VPZ_D:
34124 case AArch64::FMAXV_VPZ_H:
34125 case AArch64::FMAXV_VPZ_S:
34126 case AArch64::FMINNMV_VPZ_D:
34127 case AArch64::FMINNMV_VPZ_H:
34128 case AArch64::FMINNMV_VPZ_S:
34129 case AArch64::FMINV_VPZ_D:
34130 case AArch64::FMINV_VPZ_H:
34131 case AArch64::FMINV_VPZ_S: {
34132 switch (OpNum) {
34133 case 2:
34134 // op: Zn
34135 return 5;
34136 case 0:
34137 // op: Vd
34138 return 0;
34139 case 1:
34140 // op: Pg
34141 return 10;
34142 }
34143 break;
34144 }
34145 case AArch64::LUTI2_ZTZI_B:
34146 case AArch64::LUTI2_ZTZI_H:
34147 case AArch64::LUTI2_ZTZI_S:
34148 case AArch64::LUTI4_ZTZI_B:
34149 case AArch64::LUTI4_ZTZI_H:
34150 case AArch64::LUTI4_ZTZI_S: {
34151 switch (OpNum) {
34152 case 2:
34153 // op: Zn
34154 return 5;
34155 case 0:
34156 // op: Zd
34157 return 0;
34158 case 3:
34159 // op: i
34160 return 14;
34161 }
34162 break;
34163 }
34164 case AArch64::LUTI2_S_2ZTZI_B:
34165 case AArch64::LUTI2_S_2ZTZI_H:
34166 case AArch64::LUTI4_S_2ZTZI_B:
34167 case AArch64::LUTI4_S_2ZTZI_H: {
34168 switch (OpNum) {
34169 case 2:
34170 // op: Zn
34171 return 5;
34172 case 0:
34173 // op: Zd
34174 return 0;
34175 case 3:
34176 // op: i
34177 return 15;
34178 }
34179 break;
34180 }
34181 case AArch64::LUTI2_S_4ZTZI_B:
34182 case AArch64::LUTI2_S_4ZTZI_H:
34183 case AArch64::LUTI4_S_4ZTZI_H: {
34184 switch (OpNum) {
34185 case 2:
34186 // op: Zn
34187 return 5;
34188 case 0:
34189 // op: Zd
34190 return 0;
34191 case 3:
34192 // op: i
34193 return 16;
34194 }
34195 break;
34196 }
34197 case AArch64::LUTI2_2ZTZI_B:
34198 case AArch64::LUTI2_2ZTZI_H:
34199 case AArch64::LUTI2_2ZTZI_S:
34200 case AArch64::LUTI4_2ZTZI_B:
34201 case AArch64::LUTI4_2ZTZI_H:
34202 case AArch64::LUTI4_2ZTZI_S: {
34203 switch (OpNum) {
34204 case 2:
34205 // op: Zn
34206 return 5;
34207 case 0:
34208 // op: Zd
34209 return 1;
34210 case 3:
34211 // op: i
34212 return 15;
34213 }
34214 break;
34215 }
34216 case AArch64::LUTI2_4ZTZI_B:
34217 case AArch64::LUTI2_4ZTZI_H:
34218 case AArch64::LUTI2_4ZTZI_S:
34219 case AArch64::LUTI4_4ZTZI_H:
34220 case AArch64::LUTI4_4ZTZI_S: {
34221 switch (OpNum) {
34222 case 2:
34223 // op: Zn
34224 return 5;
34225 case 0:
34226 // op: Zd
34227 return 2;
34228 case 3:
34229 // op: i
34230 return 16;
34231 }
34232 break;
34233 }
34234 case AArch64::LUTI4_S_4ZZT2Z: {
34235 switch (OpNum) {
34236 case 2:
34237 // op: Zn
34238 return 6;
34239 case 0:
34240 // op: Zd
34241 return 0;
34242 }
34243 break;
34244 }
34245 case AArch64::LUTI4_4ZZT2Z: {
34246 switch (OpNum) {
34247 case 2:
34248 // op: Zn
34249 return 6;
34250 case 0:
34251 // op: Zd
34252 return 2;
34253 }
34254 break;
34255 }
34256 case AArch64::MOVT: {
34257 switch (OpNum) {
34258 case 2:
34259 // op: Zt
34260 return 0;
34261 case 1:
34262 // op: off2
34263 return 12;
34264 }
34265 break;
34266 }
34267 case AArch64::MOVT_XTI: {
34268 switch (OpNum) {
34269 case 2:
34270 // op: imm3
34271 return 12;
34272 case 0:
34273 // op: Rt
34274 return 0;
34275 }
34276 break;
34277 }
34278 case AArch64::SQRSHRU_VG2_Z2ZI_H:
34279 case AArch64::SQRSHR_VG2_Z2ZI_H:
34280 case AArch64::UQRSHR_VG2_Z2ZI_H: {
34281 switch (OpNum) {
34282 case 2:
34283 // op: imm4
34284 return 16;
34285 case 1:
34286 // op: Zn
34287 return 6;
34288 case 0:
34289 // op: Zd
34290 return 0;
34291 }
34292 break;
34293 }
34294 case AArch64::LDRAAindexed:
34295 case AArch64::LDRABindexed: {
34296 switch (OpNum) {
34297 case 2:
34298 // op: offset
34299 return 12;
34300 case 1:
34301 // op: Rn
34302 return 5;
34303 case 0:
34304 // op: Rt
34305 return 0;
34306 }
34307 break;
34308 }
34309 case AArch64::ADDHA_MPPZ_D:
34310 case AArch64::ADDHA_MPPZ_S:
34311 case AArch64::ADDVA_MPPZ_D:
34312 case AArch64::ADDVA_MPPZ_S: {
34313 switch (OpNum) {
34314 case 3:
34315 // op: Pm
34316 return 13;
34317 case 2:
34318 // op: Pn
34319 return 10;
34320 case 4:
34321 // op: Zn
34322 return 5;
34323 case 0:
34324 // op: ZAda
34325 return 0;
34326 }
34327 break;
34328 }
34329 case AArch64::CPYE:
34330 case AArch64::CPYEN:
34331 case AArch64::CPYERN:
34332 case AArch64::CPYERT:
34333 case AArch64::CPYERTN:
34334 case AArch64::CPYERTRN:
34335 case AArch64::CPYERTWN:
34336 case AArch64::CPYET:
34337 case AArch64::CPYETN:
34338 case AArch64::CPYETRN:
34339 case AArch64::CPYETWN:
34340 case AArch64::CPYEWN:
34341 case AArch64::CPYEWT:
34342 case AArch64::CPYEWTN:
34343 case AArch64::CPYEWTRN:
34344 case AArch64::CPYEWTWN:
34345 case AArch64::CPYFE:
34346 case AArch64::CPYFEN:
34347 case AArch64::CPYFERN:
34348 case AArch64::CPYFERT:
34349 case AArch64::CPYFERTN:
34350 case AArch64::CPYFERTRN:
34351 case AArch64::CPYFERTWN:
34352 case AArch64::CPYFET:
34353 case AArch64::CPYFETN:
34354 case AArch64::CPYFETRN:
34355 case AArch64::CPYFETWN:
34356 case AArch64::CPYFEWN:
34357 case AArch64::CPYFEWT:
34358 case AArch64::CPYFEWTN:
34359 case AArch64::CPYFEWTRN:
34360 case AArch64::CPYFEWTWN:
34361 case AArch64::CPYFM:
34362 case AArch64::CPYFMN:
34363 case AArch64::CPYFMRN:
34364 case AArch64::CPYFMRT:
34365 case AArch64::CPYFMRTN:
34366 case AArch64::CPYFMRTRN:
34367 case AArch64::CPYFMRTWN:
34368 case AArch64::CPYFMT:
34369 case AArch64::CPYFMTN:
34370 case AArch64::CPYFMTRN:
34371 case AArch64::CPYFMTWN:
34372 case AArch64::CPYFMWN:
34373 case AArch64::CPYFMWT:
34374 case AArch64::CPYFMWTN:
34375 case AArch64::CPYFMWTRN:
34376 case AArch64::CPYFMWTWN:
34377 case AArch64::CPYFP:
34378 case AArch64::CPYFPN:
34379 case AArch64::CPYFPRN:
34380 case AArch64::CPYFPRT:
34381 case AArch64::CPYFPRTN:
34382 case AArch64::CPYFPRTRN:
34383 case AArch64::CPYFPRTWN:
34384 case AArch64::CPYFPT:
34385 case AArch64::CPYFPTN:
34386 case AArch64::CPYFPTRN:
34387 case AArch64::CPYFPTWN:
34388 case AArch64::CPYFPWN:
34389 case AArch64::CPYFPWT:
34390 case AArch64::CPYFPWTN:
34391 case AArch64::CPYFPWTRN:
34392 case AArch64::CPYFPWTWN:
34393 case AArch64::CPYM:
34394 case AArch64::CPYMN:
34395 case AArch64::CPYMRN:
34396 case AArch64::CPYMRT:
34397 case AArch64::CPYMRTN:
34398 case AArch64::CPYMRTRN:
34399 case AArch64::CPYMRTWN:
34400 case AArch64::CPYMT:
34401 case AArch64::CPYMTN:
34402 case AArch64::CPYMTRN:
34403 case AArch64::CPYMTWN:
34404 case AArch64::CPYMWN:
34405 case AArch64::CPYMWT:
34406 case AArch64::CPYMWTN:
34407 case AArch64::CPYMWTRN:
34408 case AArch64::CPYMWTWN:
34409 case AArch64::CPYP:
34410 case AArch64::CPYPN:
34411 case AArch64::CPYPRN:
34412 case AArch64::CPYPRT:
34413 case AArch64::CPYPRTN:
34414 case AArch64::CPYPRTRN:
34415 case AArch64::CPYPRTWN:
34416 case AArch64::CPYPT:
34417 case AArch64::CPYPTN:
34418 case AArch64::CPYPTRN:
34419 case AArch64::CPYPTWN:
34420 case AArch64::CPYPWN:
34421 case AArch64::CPYPWT:
34422 case AArch64::CPYPWTN:
34423 case AArch64::CPYPWTRN:
34424 case AArch64::CPYPWTWN: {
34425 switch (OpNum) {
34426 case 3:
34427 // op: Rd
34428 return 0;
34429 case 4:
34430 // op: Rs
34431 return 16;
34432 case 5:
34433 // op: Rn
34434 return 5;
34435 }
34436 break;
34437 }
34438 case AArch64::LD1B_2Z_STRIDED:
34439 case AArch64::LD1B_4Z_STRIDED:
34440 case AArch64::LD1D_2Z_STRIDED:
34441 case AArch64::LD1D_4Z_STRIDED:
34442 case AArch64::LD1H_2Z_STRIDED:
34443 case AArch64::LD1H_4Z_STRIDED:
34444 case AArch64::LD1W_2Z_STRIDED:
34445 case AArch64::LD1W_4Z_STRIDED:
34446 case AArch64::LDNT1B_2Z_STRIDED:
34447 case AArch64::LDNT1B_4Z_STRIDED:
34448 case AArch64::LDNT1D_2Z_STRIDED:
34449 case AArch64::LDNT1D_4Z_STRIDED:
34450 case AArch64::LDNT1H_2Z_STRIDED:
34451 case AArch64::LDNT1H_4Z_STRIDED:
34452 case AArch64::LDNT1W_2Z_STRIDED:
34453 case AArch64::LDNT1W_4Z_STRIDED:
34454 case AArch64::ST1B_2Z_STRIDED:
34455 case AArch64::ST1B_4Z_STRIDED:
34456 case AArch64::ST1D_2Z_STRIDED:
34457 case AArch64::ST1D_4Z_STRIDED:
34458 case AArch64::ST1H_2Z_STRIDED:
34459 case AArch64::ST1H_4Z_STRIDED:
34460 case AArch64::ST1W_2Z_STRIDED:
34461 case AArch64::ST1W_4Z_STRIDED:
34462 case AArch64::STNT1B_2Z_STRIDED:
34463 case AArch64::STNT1B_4Z_STRIDED:
34464 case AArch64::STNT1D_2Z_STRIDED:
34465 case AArch64::STNT1D_4Z_STRIDED:
34466 case AArch64::STNT1H_2Z_STRIDED:
34467 case AArch64::STNT1H_4Z_STRIDED:
34468 case AArch64::STNT1W_2Z_STRIDED:
34469 case AArch64::STNT1W_4Z_STRIDED: {
34470 switch (OpNum) {
34471 case 3:
34472 // op: Rm
34473 return 16;
34474 case 1:
34475 // op: PNg
34476 return 10;
34477 case 2:
34478 // op: Rn
34479 return 5;
34480 case 0:
34481 // op: Zt
34482 return 0;
34483 }
34484 break;
34485 }
34486 case AArch64::PRFB_PRR:
34487 case AArch64::PRFD_PRR:
34488 case AArch64::PRFH_PRR:
34489 case AArch64::PRFW_PRR: {
34490 switch (OpNum) {
34491 case 3:
34492 // op: Rm
34493 return 16;
34494 case 2:
34495 // op: Rn
34496 return 5;
34497 case 1:
34498 // op: Pg
34499 return 10;
34500 case 0:
34501 // op: prfop
34502 return 0;
34503 }
34504 break;
34505 }
34506 case AArch64::MOVAZ_ZMI_H_Q:
34507 case AArch64::MOVAZ_ZMI_V_Q: {
34508 switch (OpNum) {
34509 case 3:
34510 // op: Rs
34511 return 13;
34512 case 0:
34513 // op: Zd
34514 return 0;
34515 case 1:
34516 // op: ZAn
34517 return 5;
34518 }
34519 break;
34520 }
34521 case AArch64::MOVAZ_ZMI_H_D:
34522 case AArch64::MOVAZ_ZMI_V_D: {
34523 switch (OpNum) {
34524 case 3:
34525 // op: Rs
34526 return 13;
34527 case 0:
34528 // op: Zd
34529 return 0;
34530 case 1:
34531 // op: ZAn
34532 return 6;
34533 case 4:
34534 // op: imm
34535 return 5;
34536 }
34537 break;
34538 }
34539 case AArch64::MOVAZ_ZMI_H_S:
34540 case AArch64::MOVAZ_ZMI_V_S: {
34541 switch (OpNum) {
34542 case 3:
34543 // op: Rs
34544 return 13;
34545 case 0:
34546 // op: Zd
34547 return 0;
34548 case 1:
34549 // op: ZAn
34550 return 7;
34551 case 4:
34552 // op: imm
34553 return 5;
34554 }
34555 break;
34556 }
34557 case AArch64::MOVAZ_ZMI_H_H:
34558 case AArch64::MOVAZ_ZMI_V_H: {
34559 switch (OpNum) {
34560 case 3:
34561 // op: Rs
34562 return 13;
34563 case 0:
34564 // op: Zd
34565 return 0;
34566 case 1:
34567 // op: ZAn
34568 return 8;
34569 case 4:
34570 // op: imm
34571 return 5;
34572 }
34573 break;
34574 }
34575 case AArch64::MOVAZ_ZMI_H_B:
34576 case AArch64::MOVAZ_ZMI_V_B: {
34577 switch (OpNum) {
34578 case 3:
34579 // op: Rs
34580 return 13;
34581 case 0:
34582 // op: Zd
34583 return 0;
34584 case 4:
34585 // op: imm
34586 return 5;
34587 }
34588 break;
34589 }
34590 case AArch64::MOVAZ_VG2_2ZMXI: {
34591 switch (OpNum) {
34592 case 3:
34593 // op: Rs
34594 return 13;
34595 case 4:
34596 // op: imm
34597 return 5;
34598 case 0:
34599 // op: Zd
34600 return 1;
34601 }
34602 break;
34603 }
34604 case AArch64::MOVAZ_VG4_4ZMXI: {
34605 switch (OpNum) {
34606 case 3:
34607 // op: Rs
34608 return 13;
34609 case 4:
34610 // op: imm
34611 return 5;
34612 case 0:
34613 // op: Zd
34614 return 2;
34615 }
34616 break;
34617 }
34618 case AArch64::RCWCLRP:
34619 case AArch64::RCWCLRPA:
34620 case AArch64::RCWCLRPAL:
34621 case AArch64::RCWCLRPL:
34622 case AArch64::RCWCLRSP:
34623 case AArch64::RCWCLRSPA:
34624 case AArch64::RCWCLRSPAL:
34625 case AArch64::RCWCLRSPL:
34626 case AArch64::RCWSETP:
34627 case AArch64::RCWSETPA:
34628 case AArch64::RCWSETPAL:
34629 case AArch64::RCWSETPL:
34630 case AArch64::RCWSETSP:
34631 case AArch64::RCWSETSPA:
34632 case AArch64::RCWSETSPAL:
34633 case AArch64::RCWSETSPL:
34634 case AArch64::RCWSWPP:
34635 case AArch64::RCWSWPPA:
34636 case AArch64::RCWSWPPAL:
34637 case AArch64::RCWSWPPL:
34638 case AArch64::RCWSWPSP:
34639 case AArch64::RCWSWPSPA:
34640 case AArch64::RCWSWPSPAL:
34641 case AArch64::RCWSWPSPL: {
34642 switch (OpNum) {
34643 case 3:
34644 // op: Rt2
34645 return 16;
34646 case 4:
34647 // op: Rn
34648 return 5;
34649 case 2:
34650 // op: Rt
34651 return 0;
34652 }
34653 break;
34654 }
34655 case AArch64::PSEL_PPPRI_B: {
34656 switch (OpNum) {
34657 case 3:
34658 // op: Rv
34659 return 16;
34660 case 1:
34661 // op: Pn
34662 return 10;
34663 case 2:
34664 // op: Pm
34665 return 5;
34666 case 0:
34667 // op: Pd
34668 return 0;
34669 case 4:
34670 // op: imm
34671 return 19;
34672 }
34673 break;
34674 }
34675 case AArch64::PSEL_PPPRI_H: {
34676 switch (OpNum) {
34677 case 3:
34678 // op: Rv
34679 return 16;
34680 case 1:
34681 // op: Pn
34682 return 10;
34683 case 2:
34684 // op: Pm
34685 return 5;
34686 case 0:
34687 // op: Pd
34688 return 0;
34689 case 4:
34690 // op: imm
34691 return 20;
34692 }
34693 break;
34694 }
34695 case AArch64::PSEL_PPPRI_S: {
34696 switch (OpNum) {
34697 case 3:
34698 // op: Rv
34699 return 16;
34700 case 1:
34701 // op: Pn
34702 return 10;
34703 case 2:
34704 // op: Pm
34705 return 5;
34706 case 0:
34707 // op: Pd
34708 return 0;
34709 case 4:
34710 // op: imm
34711 return 22;
34712 }
34713 break;
34714 }
34715 case AArch64::PSEL_PPPRI_D: {
34716 switch (OpNum) {
34717 case 3:
34718 // op: Rv
34719 return 16;
34720 case 1:
34721 // op: Pn
34722 return 10;
34723 case 2:
34724 // op: Pm
34725 return 5;
34726 case 0:
34727 // op: Pd
34728 return 0;
34729 case 4:
34730 // op: imm
34731 return 23;
34732 }
34733 break;
34734 }
34735 case AArch64::BFMMLA_ZZZ: {
34736 switch (OpNum) {
34737 case 3:
34738 // op: Zm
34739 return 16;
34740 case 0:
34741 // op: Zda
34742 return 0;
34743 case 2:
34744 // op: Zn
34745 return 5;
34746 }
34747 break;
34748 }
34749 case AArch64::BFCLAMP_ZZZ:
34750 case AArch64::FCLAMP_ZZZ_D:
34751 case AArch64::FCLAMP_ZZZ_H:
34752 case AArch64::FCLAMP_ZZZ_S:
34753 case AArch64::SCLAMP_ZZZ_B:
34754 case AArch64::SCLAMP_ZZZ_D:
34755 case AArch64::SCLAMP_ZZZ_H:
34756 case AArch64::SCLAMP_ZZZ_S:
34757 case AArch64::UCLAMP_ZZZ_B:
34758 case AArch64::UCLAMP_ZZZ_D:
34759 case AArch64::UCLAMP_ZZZ_H:
34760 case AArch64::UCLAMP_ZZZ_S: {
34761 switch (OpNum) {
34762 case 3:
34763 // op: Zm
34764 return 16;
34765 case 2:
34766 // op: Zn
34767 return 5;
34768 case 0:
34769 // op: Zd
34770 return 0;
34771 }
34772 break;
34773 }
34774 case AArch64::BFCLAMP_VG2_2ZZZ_H:
34775 case AArch64::FCLAMP_VG2_2Z2Z_D:
34776 case AArch64::FCLAMP_VG2_2Z2Z_H:
34777 case AArch64::FCLAMP_VG2_2Z2Z_S:
34778 case AArch64::SCLAMP_VG2_2Z2Z_B:
34779 case AArch64::SCLAMP_VG2_2Z2Z_D:
34780 case AArch64::SCLAMP_VG2_2Z2Z_H:
34781 case AArch64::SCLAMP_VG2_2Z2Z_S:
34782 case AArch64::UCLAMP_VG2_2Z2Z_B:
34783 case AArch64::UCLAMP_VG2_2Z2Z_D:
34784 case AArch64::UCLAMP_VG2_2Z2Z_H:
34785 case AArch64::UCLAMP_VG2_2Z2Z_S: {
34786 switch (OpNum) {
34787 case 3:
34788 // op: Zm
34789 return 16;
34790 case 2:
34791 // op: Zn
34792 return 5;
34793 case 0:
34794 // op: Zd
34795 return 1;
34796 }
34797 break;
34798 }
34799 case AArch64::BFCLAMP_VG4_4ZZZ_H:
34800 case AArch64::FCLAMP_VG4_4Z4Z_D:
34801 case AArch64::FCLAMP_VG4_4Z4Z_H:
34802 case AArch64::FCLAMP_VG4_4Z4Z_S:
34803 case AArch64::SCLAMP_VG4_4Z4Z_B:
34804 case AArch64::SCLAMP_VG4_4Z4Z_D:
34805 case AArch64::SCLAMP_VG4_4Z4Z_H:
34806 case AArch64::SCLAMP_VG4_4Z4Z_S:
34807 case AArch64::UCLAMP_VG4_4Z4Z_B:
34808 case AArch64::UCLAMP_VG4_4Z4Z_D:
34809 case AArch64::UCLAMP_VG4_4Z4Z_H:
34810 case AArch64::UCLAMP_VG4_4Z4Z_S: {
34811 switch (OpNum) {
34812 case 3:
34813 // op: Zm
34814 return 16;
34815 case 2:
34816 // op: Zn
34817 return 5;
34818 case 0:
34819 // op: Zd
34820 return 2;
34821 }
34822 break;
34823 }
34824 case AArch64::LD1B_2Z_STRIDED_IMM:
34825 case AArch64::LD1B_4Z_STRIDED_IMM:
34826 case AArch64::LD1D_2Z_STRIDED_IMM:
34827 case AArch64::LD1D_4Z_STRIDED_IMM:
34828 case AArch64::LD1H_2Z_STRIDED_IMM:
34829 case AArch64::LD1H_4Z_STRIDED_IMM:
34830 case AArch64::LD1W_2Z_STRIDED_IMM:
34831 case AArch64::LD1W_4Z_STRIDED_IMM:
34832 case AArch64::LDNT1B_2Z_STRIDED_IMM:
34833 case AArch64::LDNT1B_4Z_STRIDED_IMM:
34834 case AArch64::LDNT1D_2Z_STRIDED_IMM:
34835 case AArch64::LDNT1D_4Z_STRIDED_IMM:
34836 case AArch64::LDNT1H_2Z_STRIDED_IMM:
34837 case AArch64::LDNT1H_4Z_STRIDED_IMM:
34838 case AArch64::LDNT1W_2Z_STRIDED_IMM:
34839 case AArch64::LDNT1W_4Z_STRIDED_IMM:
34840 case AArch64::ST1B_2Z_STRIDED_IMM:
34841 case AArch64::ST1B_4Z_STRIDED_IMM:
34842 case AArch64::ST1D_2Z_STRIDED_IMM:
34843 case AArch64::ST1D_4Z_STRIDED_IMM:
34844 case AArch64::ST1H_2Z_STRIDED_IMM:
34845 case AArch64::ST1H_4Z_STRIDED_IMM:
34846 case AArch64::ST1W_2Z_STRIDED_IMM:
34847 case AArch64::ST1W_4Z_STRIDED_IMM:
34848 case AArch64::STNT1B_2Z_STRIDED_IMM:
34849 case AArch64::STNT1B_4Z_STRIDED_IMM:
34850 case AArch64::STNT1D_2Z_STRIDED_IMM:
34851 case AArch64::STNT1D_4Z_STRIDED_IMM:
34852 case AArch64::STNT1H_2Z_STRIDED_IMM:
34853 case AArch64::STNT1H_4Z_STRIDED_IMM:
34854 case AArch64::STNT1W_2Z_STRIDED_IMM:
34855 case AArch64::STNT1W_4Z_STRIDED_IMM: {
34856 switch (OpNum) {
34857 case 3:
34858 // op: imm4
34859 return 16;
34860 case 1:
34861 // op: PNg
34862 return 10;
34863 case 2:
34864 // op: Rn
34865 return 5;
34866 case 0:
34867 // op: Zt
34868 return 0;
34869 }
34870 break;
34871 }
34872 case AArch64::LDRAAwriteback:
34873 case AArch64::LDRABwriteback: {
34874 switch (OpNum) {
34875 case 3:
34876 // op: offset
34877 return 12;
34878 case 2:
34879 // op: Rn
34880 return 5;
34881 case 1:
34882 // op: Rt
34883 return 0;
34884 }
34885 break;
34886 }
34887 case AArch64::SYSPxt:
34888 case AArch64::SYSxt: {
34889 switch (OpNum) {
34890 case 4:
34891 // op: Rt
34892 return 0;
34893 case 0:
34894 // op: op1
34895 return 16;
34896 case 1:
34897 // op: Cn
34898 return 12;
34899 case 2:
34900 // op: Cm
34901 return 8;
34902 case 3:
34903 // op: op2
34904 return 5;
34905 }
34906 break;
34907 }
34908 case AArch64::EXTRACT_ZPMXI_H_Q:
34909 case AArch64::EXTRACT_ZPMXI_V_Q: {
34910 switch (OpNum) {
34911 case 4:
34912 // op: Rv
34913 return 13;
34914 case 2:
34915 // op: Pg
34916 return 10;
34917 case 0:
34918 // op: Zd
34919 return 0;
34920 case 3:
34921 // op: ZAn
34922 return 5;
34923 }
34924 break;
34925 }
34926 case AArch64::EXTRACT_ZPMXI_H_D:
34927 case AArch64::EXTRACT_ZPMXI_V_D: {
34928 switch (OpNum) {
34929 case 4:
34930 // op: Rv
34931 return 13;
34932 case 2:
34933 // op: Pg
34934 return 10;
34935 case 0:
34936 // op: Zd
34937 return 0;
34938 case 3:
34939 // op: ZAn
34940 return 6;
34941 case 5:
34942 // op: imm
34943 return 5;
34944 }
34945 break;
34946 }
34947 case AArch64::EXTRACT_ZPMXI_H_S:
34948 case AArch64::EXTRACT_ZPMXI_V_S: {
34949 switch (OpNum) {
34950 case 4:
34951 // op: Rv
34952 return 13;
34953 case 2:
34954 // op: Pg
34955 return 10;
34956 case 0:
34957 // op: Zd
34958 return 0;
34959 case 3:
34960 // op: ZAn
34961 return 7;
34962 case 5:
34963 // op: imm
34964 return 5;
34965 }
34966 break;
34967 }
34968 case AArch64::EXTRACT_ZPMXI_H_H:
34969 case AArch64::EXTRACT_ZPMXI_V_H: {
34970 switch (OpNum) {
34971 case 4:
34972 // op: Rv
34973 return 13;
34974 case 2:
34975 // op: Pg
34976 return 10;
34977 case 0:
34978 // op: Zd
34979 return 0;
34980 case 3:
34981 // op: ZAn
34982 return 8;
34983 case 5:
34984 // op: imm
34985 return 5;
34986 }
34987 break;
34988 }
34989 case AArch64::EXTRACT_ZPMXI_H_B:
34990 case AArch64::EXTRACT_ZPMXI_V_B: {
34991 switch (OpNum) {
34992 case 4:
34993 // op: Rv
34994 return 13;
34995 case 2:
34996 // op: Pg
34997 return 10;
34998 case 0:
34999 // op: Zd
35000 return 0;
35001 case 5:
35002 // op: imm
35003 return 5;
35004 }
35005 break;
35006 }
35007 case AArch64::LD1_MXIPXX_H_Q:
35008 case AArch64::LD1_MXIPXX_V_Q:
35009 case AArch64::ST1_MXIPXX_H_Q:
35010 case AArch64::ST1_MXIPXX_V_Q: {
35011 switch (OpNum) {
35012 case 5:
35013 // op: Rm
35014 return 16;
35015 case 1:
35016 // op: Rv
35017 return 13;
35018 case 3:
35019 // op: Pg
35020 return 10;
35021 case 4:
35022 // op: Rn
35023 return 5;
35024 case 0:
35025 // op: ZAt
35026 return 0;
35027 }
35028 break;
35029 }
35030 case AArch64::LD1_MXIPXX_H_D:
35031 case AArch64::LD1_MXIPXX_V_D:
35032 case AArch64::ST1_MXIPXX_H_D:
35033 case AArch64::ST1_MXIPXX_V_D: {
35034 switch (OpNum) {
35035 case 5:
35036 // op: Rm
35037 return 16;
35038 case 1:
35039 // op: Rv
35040 return 13;
35041 case 3:
35042 // op: Pg
35043 return 10;
35044 case 4:
35045 // op: Rn
35046 return 5;
35047 case 0:
35048 // op: ZAt
35049 return 1;
35050 case 2:
35051 // op: imm
35052 return 0;
35053 }
35054 break;
35055 }
35056 case AArch64::LD1_MXIPXX_H_S:
35057 case AArch64::LD1_MXIPXX_V_S:
35058 case AArch64::ST1_MXIPXX_H_S:
35059 case AArch64::ST1_MXIPXX_V_S: {
35060 switch (OpNum) {
35061 case 5:
35062 // op: Rm
35063 return 16;
35064 case 1:
35065 // op: Rv
35066 return 13;
35067 case 3:
35068 // op: Pg
35069 return 10;
35070 case 4:
35071 // op: Rn
35072 return 5;
35073 case 0:
35074 // op: ZAt
35075 return 2;
35076 case 2:
35077 // op: imm
35078 return 0;
35079 }
35080 break;
35081 }
35082 case AArch64::LD1_MXIPXX_H_H:
35083 case AArch64::LD1_MXIPXX_V_H:
35084 case AArch64::ST1_MXIPXX_H_H:
35085 case AArch64::ST1_MXIPXX_V_H: {
35086 switch (OpNum) {
35087 case 5:
35088 // op: Rm
35089 return 16;
35090 case 1:
35091 // op: Rv
35092 return 13;
35093 case 3:
35094 // op: Pg
35095 return 10;
35096 case 4:
35097 // op: Rn
35098 return 5;
35099 case 0:
35100 // op: ZAt
35101 return 3;
35102 case 2:
35103 // op: imm
35104 return 0;
35105 }
35106 break;
35107 }
35108 case AArch64::LD1_MXIPXX_H_B:
35109 case AArch64::LD1_MXIPXX_V_B:
35110 case AArch64::ST1_MXIPXX_H_B:
35111 case AArch64::ST1_MXIPXX_V_B: {
35112 switch (OpNum) {
35113 case 5:
35114 // op: Rm
35115 return 16;
35116 case 1:
35117 // op: Rv
35118 return 13;
35119 case 3:
35120 // op: Pg
35121 return 10;
35122 case 4:
35123 // op: Rn
35124 return 5;
35125 case 2:
35126 // op: imm
35127 return 0;
35128 }
35129 break;
35130 }
35131 case AArch64::FMLALL_MZZ_BtoS:
35132 case AArch64::FMLALL_VG2_M2ZZ_BtoS:
35133 case AArch64::FMLALL_VG4_M4ZZ_BtoS:
35134 case AArch64::SMLALL_MZZ_BtoS:
35135 case AArch64::SMLALL_MZZ_HtoD:
35136 case AArch64::SMLALL_VG2_M2ZZ_BtoS:
35137 case AArch64::SMLALL_VG2_M2ZZ_HtoD:
35138 case AArch64::SMLALL_VG4_M4ZZ_BtoS:
35139 case AArch64::SMLALL_VG4_M4ZZ_HtoD:
35140 case AArch64::SMLSLL_MZZ_BtoS:
35141 case AArch64::SMLSLL_MZZ_HtoD:
35142 case AArch64::SMLSLL_VG2_M2ZZ_BtoS:
35143 case AArch64::SMLSLL_VG2_M2ZZ_HtoD:
35144 case AArch64::SMLSLL_VG4_M4ZZ_BtoS:
35145 case AArch64::SMLSLL_VG4_M4ZZ_HtoD:
35146 case AArch64::SUMLALL_VG2_M2ZZ_BtoS:
35147 case AArch64::SUMLALL_VG4_M4ZZ_BtoS:
35148 case AArch64::UMLALL_MZZ_BtoS:
35149 case AArch64::UMLALL_MZZ_HtoD:
35150 case AArch64::UMLALL_VG2_M2ZZ_BtoS:
35151 case AArch64::UMLALL_VG2_M2ZZ_HtoD:
35152 case AArch64::UMLALL_VG4_M4ZZ_BtoS:
35153 case AArch64::UMLALL_VG4_M4ZZ_HtoD:
35154 case AArch64::UMLSLL_MZZ_BtoS:
35155 case AArch64::UMLSLL_MZZ_HtoD:
35156 case AArch64::UMLSLL_VG2_M2ZZ_BtoS:
35157 case AArch64::UMLSLL_VG2_M2ZZ_HtoD:
35158 case AArch64::UMLSLL_VG4_M4ZZ_BtoS:
35159 case AArch64::UMLSLL_VG4_M4ZZ_HtoD:
35160 case AArch64::USMLALL_MZZ_BtoS:
35161 case AArch64::USMLALL_VG2_M2ZZ_BtoS:
35162 case AArch64::USMLALL_VG4_M4ZZ_BtoS: {
35163 switch (OpNum) {
35164 case 5:
35165 // op: Zm
35166 return 16;
35167 case 2:
35168 // op: Rv
35169 return 13;
35170 case 4:
35171 // op: Zn
35172 return 5;
35173 case 3:
35174 // op: imm
35175 return 0;
35176 }
35177 break;
35178 }
35179 case AArch64::BFDOT_VG2_M2ZZI_HtoS:
35180 case AArch64::BFVDOT_VG2_M2ZZI_HtoS:
35181 case AArch64::FDOT_VG2_M2ZZI_BtoS:
35182 case AArch64::FDOT_VG2_M2ZZI_HtoS:
35183 case AArch64::FMLA_VG2_M2ZZI_S:
35184 case AArch64::FMLS_VG2_M2ZZI_S:
35185 case AArch64::FVDOT_VG2_M2ZZI_HtoS:
35186 case AArch64::SDOT_VG2_M2ZZI_BToS:
35187 case AArch64::SDOT_VG2_M2ZZI_HToS:
35188 case AArch64::SUDOT_VG2_M2ZZI_BToS:
35189 case AArch64::SVDOT_VG2_M2ZZI_HtoS:
35190 case AArch64::UDOT_VG2_M2ZZI_BToS:
35191 case AArch64::UDOT_VG2_M2ZZI_HToS:
35192 case AArch64::USDOT_VG2_M2ZZI_BToS:
35193 case AArch64::UVDOT_VG2_M2ZZI_HtoS: {
35194 switch (OpNum) {
35195 case 5:
35196 // op: Zm
35197 return 16;
35198 case 2:
35199 // op: Rv
35200 return 13;
35201 case 4:
35202 // op: Zn
35203 return 6;
35204 case 3:
35205 // op: imm3
35206 return 0;
35207 case 6:
35208 // op: i
35209 return 10;
35210 }
35211 break;
35212 }
35213 case AArch64::BFMLA_VG2_M2ZZI:
35214 case AArch64::BFMLS_VG2_M2ZZI:
35215 case AArch64::FDOT_VG2_M2ZZI_BtoH:
35216 case AArch64::FMLA_VG2_M2ZZI_H:
35217 case AArch64::FMLS_VG2_M2ZZI_H:
35218 case AArch64::FVDOTB_VG4_M2ZZI_BtoS:
35219 case AArch64::FVDOTT_VG4_M2ZZI_BtoS:
35220 case AArch64::FVDOT_VG2_M2ZZI_BtoH: {
35221 switch (OpNum) {
35222 case 5:
35223 // op: Zm
35224 return 16;
35225 case 2:
35226 // op: Rv
35227 return 13;
35228 case 4:
35229 // op: Zn
35230 return 6;
35231 case 3:
35232 // op: imm3
35233 return 0;
35234 case 6:
35235 // op: i
35236 return 3;
35237 }
35238 break;
35239 }
35240 case AArch64::BFDOT_VG4_M4ZZI_HtoS:
35241 case AArch64::FDOT_VG4_M4ZZI_BtoS:
35242 case AArch64::FDOT_VG4_M4ZZI_HtoS:
35243 case AArch64::FMLA_VG4_M4ZZI_S:
35244 case AArch64::FMLS_VG4_M4ZZI_S:
35245 case AArch64::SDOT_VG4_M4ZZI_BToS:
35246 case AArch64::SDOT_VG4_M4ZZI_HToS:
35247 case AArch64::SUDOT_VG4_M4ZZI_BToS:
35248 case AArch64::SUVDOT_VG4_M4ZZI_BToS:
35249 case AArch64::SVDOT_VG4_M4ZZI_BtoS:
35250 case AArch64::UDOT_VG4_M4ZZI_BtoS:
35251 case AArch64::UDOT_VG4_M4ZZI_HToS:
35252 case AArch64::USDOT_VG4_M4ZZI_BToS:
35253 case AArch64::USVDOT_VG4_M4ZZI_BToS:
35254 case AArch64::UVDOT_VG4_M4ZZI_BtoS: {
35255 switch (OpNum) {
35256 case 5:
35257 // op: Zm
35258 return 16;
35259 case 2:
35260 // op: Rv
35261 return 13;
35262 case 4:
35263 // op: Zn
35264 return 7;
35265 case 3:
35266 // op: imm3
35267 return 0;
35268 case 6:
35269 // op: i
35270 return 10;
35271 }
35272 break;
35273 }
35274 case AArch64::BFMLA_VG4_M4ZZI:
35275 case AArch64::BFMLS_VG4_M4ZZI:
35276 case AArch64::FDOT_VG4_M4ZZI_BtoH:
35277 case AArch64::FMLA_VG4_M4ZZI_H:
35278 case AArch64::FMLS_VG4_M4ZZI_H: {
35279 switch (OpNum) {
35280 case 5:
35281 // op: Zm
35282 return 16;
35283 case 2:
35284 // op: Rv
35285 return 13;
35286 case 4:
35287 // op: Zn
35288 return 7;
35289 case 3:
35290 // op: imm3
35291 return 0;
35292 case 6:
35293 // op: i
35294 return 3;
35295 }
35296 break;
35297 }
35298 case AArch64::FMLALL_MZZI_BtoS:
35299 case AArch64::SMLALL_MZZI_BtoS:
35300 case AArch64::SMLALL_MZZI_HtoD:
35301 case AArch64::SMLSLL_MZZI_BtoS:
35302 case AArch64::SMLSLL_MZZI_HtoD:
35303 case AArch64::SUMLALL_MZZI_BtoS:
35304 case AArch64::UMLALL_MZZI_BtoS:
35305 case AArch64::UMLALL_MZZI_HtoD:
35306 case AArch64::UMLSLL_MZZI_BtoS:
35307 case AArch64::UMLSLL_MZZI_HtoD:
35308 case AArch64::USMLALL_MZZI_BtoS: {
35309 switch (OpNum) {
35310 case 5:
35311 // op: Zm
35312 return 16;
35313 case 2:
35314 // op: Rv
35315 return 13;
35316 case 6:
35317 // op: i
35318 return 10;
35319 case 4:
35320 // op: Zn
35321 return 5;
35322 case 3:
35323 // op: imm2
35324 return 0;
35325 }
35326 break;
35327 }
35328 case AArch64::FMLALL_VG2_M2ZZI_BtoS:
35329 case AArch64::SMLALL_VG2_M2ZZI_BtoS:
35330 case AArch64::SMLALL_VG2_M2ZZI_HtoD:
35331 case AArch64::SMLSLL_VG2_M2ZZI_BtoS:
35332 case AArch64::SMLSLL_VG2_M2ZZI_HtoD:
35333 case AArch64::SUMLALL_VG2_M2ZZI_BtoS:
35334 case AArch64::UMLALL_VG2_M2ZZI_BtoS:
35335 case AArch64::UMLALL_VG2_M2ZZI_HtoD:
35336 case AArch64::UMLSLL_VG2_M2ZZI_BtoS:
35337 case AArch64::UMLSLL_VG2_M2ZZI_HtoD:
35338 case AArch64::USMLALL_VG2_M2ZZI_BtoS: {
35339 switch (OpNum) {
35340 case 5:
35341 // op: Zm
35342 return 16;
35343 case 2:
35344 // op: Rv
35345 return 13;
35346 case 6:
35347 // op: i
35348 return 1;
35349 case 3:
35350 // op: imm
35351 return 0;
35352 case 4:
35353 // op: Zn
35354 return 6;
35355 }
35356 break;
35357 }
35358 case AArch64::FMLALL_VG4_M4ZZI_BtoS:
35359 case AArch64::SMLALL_VG4_M4ZZI_BtoS:
35360 case AArch64::SMLALL_VG4_M4ZZI_HtoD:
35361 case AArch64::SMLSLL_VG4_M4ZZI_BtoS:
35362 case AArch64::SMLSLL_VG4_M4ZZI_HtoD:
35363 case AArch64::SUMLALL_VG4_M4ZZI_BtoS:
35364 case AArch64::UMLALL_VG4_M4ZZI_BtoS:
35365 case AArch64::UMLALL_VG4_M4ZZI_HtoD:
35366 case AArch64::UMLSLL_VG4_M4ZZI_BtoS:
35367 case AArch64::UMLSLL_VG4_M4ZZI_HtoD:
35368 case AArch64::USMLALL_VG4_M4ZZI_BtoS: {
35369 switch (OpNum) {
35370 case 5:
35371 // op: Zm
35372 return 16;
35373 case 2:
35374 // op: Rv
35375 return 13;
35376 case 6:
35377 // op: i
35378 return 1;
35379 case 3:
35380 // op: imm
35381 return 0;
35382 case 4:
35383 // op: Zn
35384 return 7;
35385 }
35386 break;
35387 }
35388 case AArch64::FMLAL_VG2_M2ZZI_BtoH: {
35389 switch (OpNum) {
35390 case 5:
35391 // op: Zm
35392 return 16;
35393 case 2:
35394 // op: Rv
35395 return 13;
35396 case 6:
35397 // op: i
35398 return 2;
35399 case 3:
35400 // op: imm2
35401 return 0;
35402 case 4:
35403 // op: Zn
35404 return 6;
35405 }
35406 break;
35407 }
35408 case AArch64::FMLAL_VG4_M4ZZI_BtoH: {
35409 switch (OpNum) {
35410 case 5:
35411 // op: Zm
35412 return 16;
35413 case 2:
35414 // op: Rv
35415 return 13;
35416 case 6:
35417 // op: i
35418 return 2;
35419 case 3:
35420 // op: imm2
35421 return 0;
35422 case 4:
35423 // op: Zn
35424 return 7;
35425 }
35426 break;
35427 }
35428 case AArch64::FMLAL_MZZI_BtoH: {
35429 switch (OpNum) {
35430 case 5:
35431 // op: Zm
35432 return 16;
35433 case 2:
35434 // op: Rv
35435 return 13;
35436 case 6:
35437 // op: i
35438 return 3;
35439 case 4:
35440 // op: Zn
35441 return 5;
35442 case 3:
35443 // op: imm3
35444 return 0;
35445 }
35446 break;
35447 }
35448 case AArch64::FMLA_VG2_M2ZZI_D:
35449 case AArch64::FMLS_VG2_M2ZZI_D:
35450 case AArch64::SDOT_VG2_M2ZZI_HtoD:
35451 case AArch64::UDOT_VG2_M2ZZI_HtoD: {
35452 switch (OpNum) {
35453 case 5:
35454 // op: Zm
35455 return 16;
35456 case 2:
35457 // op: Rv
35458 return 13;
35459 case 6:
35460 // op: i1
35461 return 10;
35462 case 4:
35463 // op: Zn
35464 return 6;
35465 case 3:
35466 // op: imm3
35467 return 0;
35468 }
35469 break;
35470 }
35471 case AArch64::FMLA_VG4_M4ZZI_D:
35472 case AArch64::FMLS_VG4_M4ZZI_D:
35473 case AArch64::SDOT_VG4_M4ZZI_HtoD:
35474 case AArch64::SVDOT_VG4_M4ZZI_HtoD:
35475 case AArch64::UDOT_VG4_M4ZZI_HtoD:
35476 case AArch64::UVDOT_VG4_M4ZZI_HtoD: {
35477 switch (OpNum) {
35478 case 5:
35479 // op: Zm
35480 return 16;
35481 case 2:
35482 // op: Rv
35483 return 13;
35484 case 6:
35485 // op: i1
35486 return 10;
35487 case 4:
35488 // op: Zn
35489 return 7;
35490 case 3:
35491 // op: imm3
35492 return 0;
35493 }
35494 break;
35495 }
35496 case AArch64::BFMLAL_MZZI_HtoS:
35497 case AArch64::BFMLSL_MZZI_HtoS:
35498 case AArch64::FMLAL_MZZI_HtoS:
35499 case AArch64::FMLSL_MZZI_HtoS:
35500 case AArch64::SMLAL_MZZI_HtoS:
35501 case AArch64::SMLSL_MZZI_HtoS:
35502 case AArch64::UMLAL_MZZI_HtoS:
35503 case AArch64::UMLSL_MZZI_HtoS: {
35504 switch (OpNum) {
35505 case 5:
35506 // op: Zm
35507 return 16;
35508 case 2:
35509 // op: Rv
35510 return 13;
35511 case 6:
35512 // op: i3
35513 return 10;
35514 case 4:
35515 // op: Zn
35516 return 5;
35517 case 3:
35518 // op: imm
35519 return 0;
35520 }
35521 break;
35522 }
35523 case AArch64::BFMLAL_VG2_M2ZZI_HtoS:
35524 case AArch64::BFMLSL_VG2_M2ZZI_HtoS:
35525 case AArch64::FMLAL_VG2_M2ZZI_HtoS:
35526 case AArch64::FMLSL_VG2_M2ZZI_HtoS:
35527 case AArch64::SMLAL_VG2_M2ZZI_S:
35528 case AArch64::SMLSL_VG2_M2ZZI_S:
35529 case AArch64::UMLAL_VG2_M2ZZI_S:
35530 case AArch64::UMLSL_VG2_M2ZZI_S: {
35531 switch (OpNum) {
35532 case 5:
35533 // op: Zm
35534 return 16;
35535 case 2:
35536 // op: Rv
35537 return 13;
35538 case 6:
35539 // op: i3
35540 return 2;
35541 case 4:
35542 // op: Zn
35543 return 6;
35544 case 3:
35545 // op: imm
35546 return 0;
35547 }
35548 break;
35549 }
35550 case AArch64::BFMLAL_VG4_M4ZZI_HtoS:
35551 case AArch64::BFMLSL_VG4_M4ZZI_HtoS:
35552 case AArch64::FMLAL_VG4_M4ZZI_HtoS:
35553 case AArch64::FMLSL_VG4_M4ZZI_HtoS:
35554 case AArch64::SMLAL_VG4_M4ZZI_HtoS:
35555 case AArch64::SMLSL_VG4_M4ZZI_HtoS:
35556 case AArch64::UMLAL_VG4_M4ZZI_HtoS:
35557 case AArch64::UMLSL_VG4_M4ZZI_HtoS: {
35558 switch (OpNum) {
35559 case 5:
35560 // op: Zm
35561 return 16;
35562 case 2:
35563 // op: Rv
35564 return 13;
35565 case 6:
35566 // op: i3
35567 return 2;
35568 case 4:
35569 // op: Zn
35570 return 7;
35571 case 3:
35572 // op: imm
35573 return 0;
35574 }
35575 break;
35576 }
35577 case AArch64::BFMOPA_MPPZZ:
35578 case AArch64::BFMOPA_MPPZZ_H:
35579 case AArch64::BFMOPS_MPPZZ:
35580 case AArch64::BFMOPS_MPPZZ_H:
35581 case AArch64::BMOPA_MPPZZ_S:
35582 case AArch64::BMOPS_MPPZZ_S:
35583 case AArch64::FMOPAL_MPPZZ:
35584 case AArch64::FMOPA_MPPZZ_BtoH:
35585 case AArch64::FMOPA_MPPZZ_BtoS:
35586 case AArch64::FMOPA_MPPZZ_D:
35587 case AArch64::FMOPA_MPPZZ_H:
35588 case AArch64::FMOPA_MPPZZ_S:
35589 case AArch64::FMOPSL_MPPZZ:
35590 case AArch64::FMOPS_MPPZZ_D:
35591 case AArch64::FMOPS_MPPZZ_H:
35592 case AArch64::FMOPS_MPPZZ_S:
35593 case AArch64::SMOPA_MPPZZ_D:
35594 case AArch64::SMOPA_MPPZZ_HtoS:
35595 case AArch64::SMOPA_MPPZZ_S:
35596 case AArch64::SMOPS_MPPZZ_D:
35597 case AArch64::SMOPS_MPPZZ_HtoS:
35598 case AArch64::SMOPS_MPPZZ_S:
35599 case AArch64::SUMOPA_MPPZZ_D:
35600 case AArch64::SUMOPA_MPPZZ_S:
35601 case AArch64::SUMOPS_MPPZZ_D:
35602 case AArch64::SUMOPS_MPPZZ_S:
35603 case AArch64::UMOPA_MPPZZ_D:
35604 case AArch64::UMOPA_MPPZZ_HtoS:
35605 case AArch64::UMOPA_MPPZZ_S:
35606 case AArch64::UMOPS_MPPZZ_D:
35607 case AArch64::UMOPS_MPPZZ_HtoS:
35608 case AArch64::UMOPS_MPPZZ_S:
35609 case AArch64::USMOPA_MPPZZ_D:
35610 case AArch64::USMOPA_MPPZZ_S:
35611 case AArch64::USMOPS_MPPZZ_D:
35612 case AArch64::USMOPS_MPPZZ_S: {
35613 switch (OpNum) {
35614 case 5:
35615 // op: Zm
35616 return 16;
35617 case 3:
35618 // op: Pm
35619 return 13;
35620 case 2:
35621 // op: Pn
35622 return 10;
35623 case 4:
35624 // op: Zn
35625 return 5;
35626 case 0:
35627 // op: ZAda
35628 return 0;
35629 }
35630 break;
35631 }
35632 case AArch64::ADD_VG2_M2ZZ_D:
35633 case AArch64::ADD_VG2_M2ZZ_S:
35634 case AArch64::ADD_VG4_M4ZZ_D:
35635 case AArch64::ADD_VG4_M4ZZ_S:
35636 case AArch64::BFDOT_VG2_M2ZZ_HtoS:
35637 case AArch64::BFDOT_VG4_M4ZZ_HtoS:
35638 case AArch64::BFMLA_VG2_M2ZZ:
35639 case AArch64::BFMLA_VG4_M4ZZ:
35640 case AArch64::BFMLS_VG2_M2ZZ:
35641 case AArch64::BFMLS_VG4_M4ZZ:
35642 case AArch64::FDOT_VG2_M2ZZ_BtoH:
35643 case AArch64::FDOT_VG2_M2ZZ_BtoS:
35644 case AArch64::FDOT_VG2_M2ZZ_HtoS:
35645 case AArch64::FDOT_VG4_M4ZZ_BtoH:
35646 case AArch64::FDOT_VG4_M4ZZ_BtoS:
35647 case AArch64::FDOT_VG4_M4ZZ_HtoS:
35648 case AArch64::FMLA_VG2_M2ZZ_D:
35649 case AArch64::FMLA_VG2_M2ZZ_H:
35650 case AArch64::FMLA_VG2_M2ZZ_S:
35651 case AArch64::FMLA_VG4_M4ZZ_D:
35652 case AArch64::FMLA_VG4_M4ZZ_H:
35653 case AArch64::FMLA_VG4_M4ZZ_S:
35654 case AArch64::FMLS_VG2_M2ZZ_D:
35655 case AArch64::FMLS_VG2_M2ZZ_H:
35656 case AArch64::FMLS_VG2_M2ZZ_S:
35657 case AArch64::FMLS_VG4_M4ZZ_D:
35658 case AArch64::FMLS_VG4_M4ZZ_H:
35659 case AArch64::FMLS_VG4_M4ZZ_S:
35660 case AArch64::SDOT_VG2_M2ZZ_BtoS:
35661 case AArch64::SDOT_VG2_M2ZZ_HtoD:
35662 case AArch64::SDOT_VG2_M2ZZ_HtoS:
35663 case AArch64::SDOT_VG4_M4ZZ_BtoS:
35664 case AArch64::SDOT_VG4_M4ZZ_HtoD:
35665 case AArch64::SDOT_VG4_M4ZZ_HtoS:
35666 case AArch64::SUB_VG2_M2ZZ_D:
35667 case AArch64::SUB_VG2_M2ZZ_S:
35668 case AArch64::SUB_VG4_M4ZZ_D:
35669 case AArch64::SUB_VG4_M4ZZ_S:
35670 case AArch64::SUDOT_VG2_M2ZZ_BToS:
35671 case AArch64::SUDOT_VG4_M4ZZ_BToS:
35672 case AArch64::UDOT_VG2_M2ZZ_BtoS:
35673 case AArch64::UDOT_VG2_M2ZZ_HtoD:
35674 case AArch64::UDOT_VG2_M2ZZ_HtoS:
35675 case AArch64::UDOT_VG4_M4ZZ_BtoS:
35676 case AArch64::UDOT_VG4_M4ZZ_HtoD:
35677 case AArch64::UDOT_VG4_M4ZZ_HtoS:
35678 case AArch64::USDOT_VG2_M2ZZ_BToS:
35679 case AArch64::USDOT_VG4_M4ZZ_BToS: {
35680 switch (OpNum) {
35681 case 5:
35682 // op: Zm
35683 return 16;
35684 case 4:
35685 // op: Zn
35686 return 5;
35687 case 2:
35688 // op: Rv
35689 return 13;
35690 case 3:
35691 // op: imm3
35692 return 0;
35693 }
35694 break;
35695 }
35696 case AArch64::FMLALL_VG2_M2Z2Z_BtoS:
35697 case AArch64::SMLALL_VG2_M2Z2Z_BtoS:
35698 case AArch64::SMLALL_VG2_M2Z2Z_HtoD:
35699 case AArch64::SMLSLL_VG2_M2Z2Z_BtoS:
35700 case AArch64::SMLSLL_VG2_M2Z2Z_HtoD:
35701 case AArch64::UMLALL_VG2_M2Z2Z_BtoS:
35702 case AArch64::UMLALL_VG2_M2Z2Z_HtoD:
35703 case AArch64::UMLSLL_VG2_M2Z2Z_BtoS:
35704 case AArch64::UMLSLL_VG2_M2Z2Z_HtoD:
35705 case AArch64::USMLALL_VG2_M2Z2Z_BtoS: {
35706 switch (OpNum) {
35707 case 5:
35708 // op: Zm
35709 return 17;
35710 case 2:
35711 // op: Rv
35712 return 13;
35713 case 4:
35714 // op: Zn
35715 return 6;
35716 case 3:
35717 // op: imm
35718 return 0;
35719 }
35720 break;
35721 }
35722 case AArch64::ADD_VG2_M2Z2Z_D:
35723 case AArch64::ADD_VG2_M2Z2Z_S:
35724 case AArch64::BFDOT_VG2_M2Z2Z_HtoS:
35725 case AArch64::BFMLA_VG2_M2Z2Z:
35726 case AArch64::BFMLS_VG2_M2Z2Z:
35727 case AArch64::FDOT_VG2_M2Z2Z_BtoH:
35728 case AArch64::FDOT_VG2_M2Z2Z_BtoS:
35729 case AArch64::FDOT_VG2_M2Z2Z_HtoS:
35730 case AArch64::FMLA_VG2_M2Z2Z_D:
35731 case AArch64::FMLA_VG2_M2Z2Z_S:
35732 case AArch64::FMLA_VG2_M2Z4Z_H:
35733 case AArch64::FMLS_VG2_M2Z2Z_D:
35734 case AArch64::FMLS_VG2_M2Z2Z_H:
35735 case AArch64::FMLS_VG2_M2Z2Z_S:
35736 case AArch64::SDOT_VG2_M2Z2Z_BtoS:
35737 case AArch64::SDOT_VG2_M2Z2Z_HtoD:
35738 case AArch64::SDOT_VG2_M2Z2Z_HtoS:
35739 case AArch64::SUB_VG2_M2Z2Z_D:
35740 case AArch64::SUB_VG2_M2Z2Z_S:
35741 case AArch64::UDOT_VG2_M2Z2Z_BtoS:
35742 case AArch64::UDOT_VG2_M2Z2Z_HtoD:
35743 case AArch64::UDOT_VG2_M2Z2Z_HtoS:
35744 case AArch64::USDOT_VG2_M2Z2Z_BToS: {
35745 switch (OpNum) {
35746 case 5:
35747 // op: Zm
35748 return 17;
35749 case 4:
35750 // op: Zn
35751 return 6;
35752 case 2:
35753 // op: Rv
35754 return 13;
35755 case 3:
35756 // op: imm3
35757 return 0;
35758 }
35759 break;
35760 }
35761 case AArch64::FMLALL_VG4_M4Z4Z_BtoS:
35762 case AArch64::SMLALL_VG4_M4Z4Z_BtoS:
35763 case AArch64::SMLALL_VG4_M4Z4Z_HtoD:
35764 case AArch64::SMLSLL_VG4_M4Z4Z_BtoS:
35765 case AArch64::SMLSLL_VG4_M4Z4Z_HtoD:
35766 case AArch64::UMLALL_VG4_M4Z4Z_BtoS:
35767 case AArch64::UMLALL_VG4_M4Z4Z_HtoD:
35768 case AArch64::UMLSLL_VG4_M4Z4Z_BtoS:
35769 case AArch64::UMLSLL_VG4_M4Z4Z_HtoD:
35770 case AArch64::USMLALL_VG4_M4Z4Z_BtoS: {
35771 switch (OpNum) {
35772 case 5:
35773 // op: Zm
35774 return 18;
35775 case 2:
35776 // op: Rv
35777 return 13;
35778 case 4:
35779 // op: Zn
35780 return 7;
35781 case 3:
35782 // op: imm
35783 return 0;
35784 }
35785 break;
35786 }
35787 case AArch64::ADD_VG4_M4Z4Z_D:
35788 case AArch64::ADD_VG4_M4Z4Z_S:
35789 case AArch64::BFDOT_VG4_M4Z4Z_HtoS:
35790 case AArch64::BFMLA_VG4_M4Z4Z:
35791 case AArch64::BFMLS_VG4_M4Z4Z:
35792 case AArch64::FDOT_VG4_M4Z4Z_BtoH:
35793 case AArch64::FDOT_VG4_M4Z4Z_BtoS:
35794 case AArch64::FDOT_VG4_M4Z4Z_HtoS:
35795 case AArch64::FMLA_VG4_M4Z4Z_D:
35796 case AArch64::FMLA_VG4_M4Z4Z_H:
35797 case AArch64::FMLA_VG4_M4Z4Z_S:
35798 case AArch64::FMLS_VG4_M4Z2Z_H:
35799 case AArch64::FMLS_VG4_M4Z4Z_D:
35800 case AArch64::FMLS_VG4_M4Z4Z_S:
35801 case AArch64::SDOT_VG4_M4Z4Z_BtoS:
35802 case AArch64::SDOT_VG4_M4Z4Z_HtoD:
35803 case AArch64::SDOT_VG4_M4Z4Z_HtoS:
35804 case AArch64::SUB_VG4_M4Z4Z_D:
35805 case AArch64::SUB_VG4_M4Z4Z_S:
35806 case AArch64::UDOT_VG4_M4Z4Z_BtoS:
35807 case AArch64::UDOT_VG4_M4Z4Z_HtoD:
35808 case AArch64::UDOT_VG4_M4Z4Z_HtoS:
35809 case AArch64::USDOT_VG4_M4Z4Z_BToS: {
35810 switch (OpNum) {
35811 case 5:
35812 // op: Zm
35813 return 18;
35814 case 4:
35815 // op: Zn
35816 return 7;
35817 case 2:
35818 // op: Rv
35819 return 13;
35820 case 3:
35821 // op: imm3
35822 return 0;
35823 }
35824 break;
35825 }
35826 }
35827 std::string msg;
35828 raw_string_ostream Msg(msg);
35829 Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
35830 report_fatal_error(Msg.str().c_str());
35831}
35832
35833#endif // GET_OPERAND_BIT_OFFSET
35834
35835