1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
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2 | |* *| |
3 | |* Pseudo-instruction MC lowering Source Fragment *| |
4 | |* *| |
5 | |* Automatically generated file, do not edit! *| |
6 | |* *| |
7 | \*===----------------------------------------------------------------------===*/ |
8 | |
9 | bool AMDGPUAsmPrinter:: |
10 | emitPseudoExpansionLowering(MCStreamer &OutStreamer, |
11 | const MachineInstr *MI) { |
12 | switch (MI->getOpcode()) { |
13 | default: return false; |
14 | case AMDGPU::V_MOV_B32_indirect_read: { |
15 | MCInst TmpInst; |
16 | MCOperand MCOp; |
17 | TmpInst.setOpcode(AMDGPU::V_MOV_B32_e32_vi); |
18 | // Operand: vdst |
19 | lowerOperand(MO: MI->getOperand(i: 0), MCOp); |
20 | TmpInst.addOperand(Op: MCOp); |
21 | // Operand: src0 |
22 | lowerOperand(MO: MI->getOperand(i: 1), MCOp); |
23 | TmpInst.addOperand(Op: MCOp); |
24 | EmitToStreamer(S&: OutStreamer, Inst: TmpInst); |
25 | break; |
26 | } |
27 | case AMDGPU::V_MOV_B32_indirect_write: { |
28 | MCInst TmpInst; |
29 | MCOperand MCOp; |
30 | TmpInst.setOpcode(AMDGPU::V_MOV_B32_e32_vi); |
31 | // Operand: vdst |
32 | lowerOperand(MO: MI->getOperand(i: 0), MCOp); |
33 | TmpInst.addOperand(Op: MCOp); |
34 | // Operand: src0 |
35 | lowerOperand(MO: MI->getOperand(i: 1), MCOp); |
36 | TmpInst.addOperand(Op: MCOp); |
37 | EmitToStreamer(S&: OutStreamer, Inst: TmpInst); |
38 | break; |
39 | } |
40 | } |
41 | return true; |
42 | } |
43 | |
44 |