1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace AMDGPU {
13enum : unsigned {
14 InvalidRegBankID = ~0u,
15 AGPRRegBankID = 0,
16 SGPRRegBankID = 1,
17 VCCRegBankID = 2,
18 VGPRRegBankID = 3,
19 NumRegisterBanks,
20};
21} // end namespace AMDGPU
22} // end namespace llvm
23#endif // GET_REGBANK_DECLARATIONS
24
25#ifdef GET_TARGET_REGBANK_CLASS
26#undef GET_TARGET_REGBANK_CLASS
27private:
28 static const RegisterBank *RegBanks[];
29 static const unsigned Sizes[];
30
31protected:
32 AMDGPUGenRegisterBankInfo(unsigned HwMode = 0);
33
34#endif // GET_TARGET_REGBANK_CLASS
35
36#ifdef GET_TARGET_REGBANK_IMPL
37#undef GET_TARGET_REGBANK_IMPL
38namespace llvm {
39namespace AMDGPU {
40const uint32_t AGPRRegBankCoverageData[] = {
41 // 0-31
42 (1u << (AMDGPU::AGPR_LO16RegClassID - 0)) |
43 (1u << (AMDGPU::AV_32RegClassID - 0)) |
44 0,
45 // 32-63
46 (1u << (AMDGPU::AGPR_32RegClassID - 32)) |
47 (1u << (AMDGPU::AReg_64RegClassID - 32)) |
48 (1u << (AMDGPU::AReg_64_Align2RegClassID - 32)) |
49 (1u << (AMDGPU::AV_64RegClassID - 32)) |
50 (1u << (AMDGPU::AV_64_Align2RegClassID - 32)) |
51 0,
52 // 64-95
53 (1u << (AMDGPU::AReg_96RegClassID - 64)) |
54 (1u << (AMDGPU::AReg_96_Align2RegClassID - 64)) |
55 (1u << (AMDGPU::AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 64)) |
56 (1u << (AMDGPU::AReg_128RegClassID - 64)) |
57 (1u << (AMDGPU::AV_96RegClassID - 64)) |
58 (1u << (AMDGPU::AV_96_Align2RegClassID - 64)) |
59 (1u << (AMDGPU::AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) |
60 (1u << (AMDGPU::AV_128RegClassID - 64)) |
61 (1u << (AMDGPU::AV_128_Align2RegClassID - 64)) |
62 (1u << (AMDGPU::AV_128_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) |
63 0,
64 // 96-127
65 (1u << (AMDGPU::AReg_128_Align2RegClassID - 96)) |
66 (1u << (AMDGPU::AReg_128_with_sub0_sub1_sub2_in_AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 96)) |
67 (1u << (AMDGPU::AReg_160RegClassID - 96)) |
68 (1u << (AMDGPU::AReg_160_Align2RegClassID - 96)) |
69 (1u << (AMDGPU::AReg_160_with_sub0_sub1_sub2_in_AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 96)) |
70 (1u << (AMDGPU::AV_160RegClassID - 96)) |
71 (1u << (AMDGPU::AV_160_Align2RegClassID - 96)) |
72 (1u << (AMDGPU::AV_160_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 96)) |
73 0,
74 // 128-159
75 (1u << (AMDGPU::AReg_192RegClassID - 128)) |
76 (1u << (AMDGPU::AReg_192_Align2RegClassID - 128)) |
77 (1u << (AMDGPU::AReg_192_with_sub0_sub1_sub2_in_AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 128)) |
78 (1u << (AMDGPU::AV_192RegClassID - 128)) |
79 (1u << (AMDGPU::AV_192_Align2RegClassID - 128)) |
80 (1u << (AMDGPU::AV_192_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 128)) |
81 0,
82 // 160-191
83 (1u << (AMDGPU::AReg_224RegClassID - 160)) |
84 (1u << (AMDGPU::AReg_224_Align2RegClassID - 160)) |
85 (1u << (AMDGPU::AV_224RegClassID - 160)) |
86 (1u << (AMDGPU::AV_224_Align2RegClassID - 160)) |
87 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 160)) |
88 0,
89 // 192-223
90 (1u << (AMDGPU::AReg_224_with_sub0_sub1_sub2_in_AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 192)) |
91 (1u << (AMDGPU::AReg_256RegClassID - 192)) |
92 (1u << (AMDGPU::AV_256RegClassID - 192)) |
93 (1u << (AMDGPU::AV_256_Align2RegClassID - 192)) |
94 0,
95 // 224-255
96 (1u << (AMDGPU::AReg_256_Align2RegClassID - 224)) |
97 (1u << (AMDGPU::AReg_256_with_sub0_sub1_sub2_in_AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 224)) |
98 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 224)) |
99 0,
100 // 256-287
101 (1u << (AMDGPU::AReg_288RegClassID - 256)) |
102 (1u << (AMDGPU::AReg_288_Align2RegClassID - 256)) |
103 (1u << (AMDGPU::AReg_288_with_sub0_sub1_sub2_in_AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 256)) |
104 (1u << (AMDGPU::AV_288RegClassID - 256)) |
105 (1u << (AMDGPU::AV_288_Align2RegClassID - 256)) |
106 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 256)) |
107 0,
108 // 288-319
109 (1u << (AMDGPU::AReg_320RegClassID - 288)) |
110 (1u << (AMDGPU::AReg_320_Align2RegClassID - 288)) |
111 (1u << (AMDGPU::AReg_320_with_sub0_sub1_sub2_in_AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 288)) |
112 (1u << (AMDGPU::AV_320RegClassID - 288)) |
113 (1u << (AMDGPU::AV_320_Align2RegClassID - 288)) |
114 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 288)) |
115 0,
116 // 320-351
117 (1u << (AMDGPU::AReg_352RegClassID - 320)) |
118 (1u << (AMDGPU::AV_352RegClassID - 320)) |
119 (1u << (AMDGPU::AV_352_Align2RegClassID - 320)) |
120 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 320)) |
121 0,
122 // 352-383
123 (1u << (AMDGPU::AReg_352_Align2RegClassID - 352)) |
124 (1u << (AMDGPU::AReg_352_with_sub0_sub1_sub2_in_AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 352)) |
125 0,
126 // 384-415
127 (1u << (AMDGPU::AReg_384RegClassID - 384)) |
128 (1u << (AMDGPU::AReg_384_Align2RegClassID - 384)) |
129 (1u << (AMDGPU::AReg_384_with_sub0_sub1_sub2_in_AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 384)) |
130 (1u << (AMDGPU::AV_384RegClassID - 384)) |
131 (1u << (AMDGPU::AV_384_Align2RegClassID - 384)) |
132 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 384)) |
133 0,
134 // 416-447
135 (1u << (AMDGPU::AV_512RegClassID - 416)) |
136 0,
137 // 448-479
138 (1u << (AMDGPU::AReg_512RegClassID - 448)) |
139 (1u << (AMDGPU::AReg_512_Align2RegClassID - 448)) |
140 (1u << (AMDGPU::AReg_512_with_sub0_sub1_sub2_in_AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 448)) |
141 (1u << (AMDGPU::AV_512_Align2RegClassID - 448)) |
142 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 448)) |
143 0,
144 // 480-511
145 0,
146 // 512-543
147 (1u << (AMDGPU::AReg_1024RegClassID - 512)) |
148 (1u << (AMDGPU::AReg_1024_Align2RegClassID - 512)) |
149 (1u << (AMDGPU::AReg_1024_with_sub0_sub1_sub2_in_AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 512)) |
150 0,
151 // 544-575
152 0,
153 // 576-607
154 0,
155 // 608-639
156 0,
157 // 640-671
158 0,
159};
160const uint32_t SGPRRegBankCoverageData[] = {
161 // 0-31
162 (1u << (AMDGPU::SReg_LO16RegClassID - 0)) |
163 (1u << (AMDGPU::SGPR_LO16RegClassID - 0)) |
164 (1u << (AMDGPU::TTMP_LO16RegClassID - 0)) |
165 (1u << (AMDGPU::M0_CLASS_LO16RegClassID - 0)) |
166 (1u << (AMDGPU::SReg_1RegClassID - 0)) |
167 (1u << (AMDGPU::VS_16RegClassID - 0)) |
168 (1u << (AMDGPU::VS_16_Lo128RegClassID - 0)) |
169 (1u << (AMDGPU::VS_16_and_SReg_1RegClassID - 0)) |
170 (1u << (AMDGPU::VS_32RegClassID - 0)) |
171 (1u << (AMDGPU::VS_32_with_hi16RegClassID - 0)) |
172 (1u << (AMDGPU::VS_32_Lo128RegClassID - 0)) |
173 (1u << (AMDGPU::VS_32_Lo128_with_hi16RegClassID - 0)) |
174 (1u << (AMDGPU::SReg_1_XEXECRegClassID - 0)) |
175 (1u << (AMDGPU::VS_16_and_SReg_1_XEXECRegClassID - 0)) |
176 (1u << (AMDGPU::SReg_1_with_lo16_in_SGPR_LO16RegClassID - 0)) |
177 (1u << (AMDGPU::VS_16_and_SReg_1_with_lo16_in_SGPR_LO16RegClassID - 0)) |
178 (1u << (AMDGPU::SReg_1_with_lo16_in_TTMP_LO16RegClassID - 0)) |
179 (1u << (AMDGPU::VS_16_and_SReg_1_with_lo16_in_TTMP_LO16RegClassID - 0)) |
180 (1u << (AMDGPU::SReg_1_with_sub0RegClassID - 0)) |
181 (1u << (AMDGPU::SReg_1_XEXEC_with_sub0RegClassID - 0)) |
182 (1u << (AMDGPU::SReg_1_with_sub0_and_SReg_1_with_lo16_in_SGPR_LO16RegClassID - 0)) |
183 (1u << (AMDGPU::SReg_1_with_sub0_and_SReg_1_with_lo16_in_TTMP_LO16RegClassID - 0)) |
184 0,
185 // 32-63
186 (1u << (AMDGPU::SReg_32RegClassID - 32)) |
187 (1u << (AMDGPU::SReg_32_XEXEC_HIRegClassID - 32)) |
188 (1u << (AMDGPU::SReg_32_XEXECRegClassID - 32)) |
189 (1u << (AMDGPU::SReg_32_XM0_XEXECRegClassID - 32)) |
190 (1u << (AMDGPU::SGPR_32RegClassID - 32)) |
191 (1u << (AMDGPU::TTMP_32RegClassID - 32)) |
192 (1u << (AMDGPU::M0_CLASSRegClassID - 32)) |
193 (1u << (AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID - 32)) |
194 (1u << (AMDGPU::SReg_32_XM0RegClassID - 32)) |
195 (1u << (AMDGPU::SReg_64RegClassID - 32)) |
196 (1u << (AMDGPU::SRegOrLds_32RegClassID - 32)) |
197 (1u << (AMDGPU::SReg_64_XEXECRegClassID - 32)) |
198 (1u << (AMDGPU::SGPR_64RegClassID - 32)) |
199 (1u << (AMDGPU::VS_64RegClassID - 32)) |
200 (1u << (AMDGPU::VS_64_with_sub0_in_VS_32_Lo128RegClassID - 32)) |
201 (1u << (AMDGPU::VS_64_with_sub1_in_VS_32_Lo128RegClassID - 32)) |
202 0,
203 // 64-95
204 (1u << (AMDGPU::CCR_SGPR_64RegClassID - 64)) |
205 (1u << (AMDGPU::Gfx_CCR_SGPR_64RegClassID - 64)) |
206 (1u << (AMDGPU::TTMP_64RegClassID - 64)) |
207 (1u << (AMDGPU::SReg_96RegClassID - 64)) |
208 (1u << (AMDGPU::SReg_96_with_sub0_sub1RegClassID - 64)) |
209 (1u << (AMDGPU::SGPR_96RegClassID - 64)) |
210 (1u << (AMDGPU::SGPR_96_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 64)) |
211 (1u << (AMDGPU::SGPR_96_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 64)) |
212 (1u << (AMDGPU::TTMP_96_with_sub0_sub1RegClassID - 64)) |
213 (1u << (AMDGPU::TTMP_96RegClassID - 64)) |
214 (1u << (AMDGPU::SReg_96_with_sub1_sub2RegClassID - 64)) |
215 0,
216 // 96-127
217 (1u << (AMDGPU::SReg_128RegClassID - 96)) |
218 (1u << (AMDGPU::SReg_128_with_sub0_sub1_sub2RegClassID - 96)) |
219 (1u << (AMDGPU::SGPR_128RegClassID - 96)) |
220 (1u << (AMDGPU::SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 96)) |
221 (1u << (AMDGPU::SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 96)) |
222 (1u << (AMDGPU::SGPR_128_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 96)) |
223 (1u << (AMDGPU::TTMP_128_with_sub0_sub1_sub2RegClassID - 96)) |
224 (1u << (AMDGPU::TTMP_128RegClassID - 96)) |
225 (1u << (AMDGPU::SReg_128_with_sub1_sub2_sub3RegClassID - 96)) |
226 0,
227 // 128-159
228 (1u << (AMDGPU::SReg_160RegClassID - 128)) |
229 (1u << (AMDGPU::SReg_160_with_sub0_sub1_sub2RegClassID - 128)) |
230 (1u << (AMDGPU::SGPR_160RegClassID - 128)) |
231 (1u << (AMDGPU::SGPR_160_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 128)) |
232 (1u << (AMDGPU::SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 128)) |
233 (1u << (AMDGPU::SGPR_160_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 128)) |
234 (1u << (AMDGPU::TTMP_160_with_sub0_sub1_sub2RegClassID - 128)) |
235 (1u << (AMDGPU::TTMP_160RegClassID - 128)) |
236 (1u << (AMDGPU::SReg_160_with_sub1_sub2_sub3RegClassID - 128)) |
237 (1u << (AMDGPU::SReg_160_with_sub2_sub3_sub4RegClassID - 128)) |
238 0,
239 // 160-191
240 (1u << (AMDGPU::SReg_192RegClassID - 160)) |
241 (1u << (AMDGPU::SReg_192_with_sub0_sub1_sub2RegClassID - 160)) |
242 (1u << (AMDGPU::SGPR_192RegClassID - 160)) |
243 (1u << (AMDGPU::SGPR_192_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 160)) |
244 (1u << (AMDGPU::SGPR_192_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 160)) |
245 (1u << (AMDGPU::SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 160)) |
246 (1u << (AMDGPU::SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 160)) |
247 (1u << (AMDGPU::SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 160)) |
248 (1u << (AMDGPU::SReg_192_with_sub3_sub4_sub5RegClassID - 160)) |
249 (1u << (AMDGPU::TTMP_192RegClassID - 160)) |
250 (1u << (AMDGPU::SReg_192_with_sub1_sub2_sub3RegClassID - 160)) |
251 (1u << (AMDGPU::SReg_192_with_sub2_sub3_sub4RegClassID - 160)) |
252 0,
253 // 192-223
254 (1u << (AMDGPU::SReg_224RegClassID - 192)) |
255 (1u << (AMDGPU::SReg_224_with_sub0_sub1_sub2RegClassID - 192)) |
256 (1u << (AMDGPU::SGPR_224RegClassID - 192)) |
257 (1u << (AMDGPU::SGPR_224_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 192)) |
258 (1u << (AMDGPU::SGPR_224_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 192)) |
259 (1u << (AMDGPU::SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 192)) |
260 (1u << (AMDGPU::SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_224_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 192)) |
261 (1u << (AMDGPU::SGPR_224_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 192)) |
262 (1u << (AMDGPU::SReg_224_with_sub3_sub4_sub5RegClassID - 192)) |
263 (1u << (AMDGPU::SReg_224_with_sub4_sub5_sub6RegClassID - 192)) |
264 (1u << (AMDGPU::SReg_224_with_sub1_sub2_sub3RegClassID - 192)) |
265 (1u << (AMDGPU::TTMP_224RegClassID - 192)) |
266 (1u << (AMDGPU::SReg_224_with_sub2_sub3_sub4RegClassID - 192)) |
267 0,
268 // 224-255
269 (1u << (AMDGPU::SReg_256RegClassID - 224)) |
270 (1u << (AMDGPU::SReg_256_with_sub0_sub1_sub2RegClassID - 224)) |
271 (1u << (AMDGPU::SGPR_256RegClassID - 224)) |
272 (1u << (AMDGPU::SGPR_256_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 224)) |
273 (1u << (AMDGPU::SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 224)) |
274 (1u << (AMDGPU::SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 224)) |
275 (1u << (AMDGPU::SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 224)) |
276 (1u << (AMDGPU::SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_256_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 224)) |
277 (1u << (AMDGPU::SGPR_256_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 224)) |
278 (1u << (AMDGPU::SReg_256_with_sub4_sub5_sub6RegClassID - 224)) |
279 0,
280 // 256-287
281 (1u << (AMDGPU::SReg_256_with_sub3_sub4_sub5RegClassID - 256)) |
282 (1u << (AMDGPU::SReg_256_with_sub1_sub2_sub3RegClassID - 256)) |
283 (1u << (AMDGPU::TTMP_256RegClassID - 256)) |
284 (1u << (AMDGPU::SReg_256_with_sub2_sub3_sub4RegClassID - 256)) |
285 0,
286 // 288-319
287 (1u << (AMDGPU::SReg_288RegClassID - 288)) |
288 (1u << (AMDGPU::SReg_288_with_sub0_sub1_sub2RegClassID - 288)) |
289 (1u << (AMDGPU::SGPR_288RegClassID - 288)) |
290 (1u << (AMDGPU::SGPR_288_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 288)) |
291 (1u << (AMDGPU::SGPR_288_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 288)) |
292 (1u << (AMDGPU::SGPR_288_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 288)) |
293 (1u << (AMDGPU::SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 288)) |
294 (1u << (AMDGPU::SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_288_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 288)) |
295 (1u << (AMDGPU::SGPR_288_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 288)) |
296 (1u << (AMDGPU::SReg_288_with_sub3_sub4_sub5RegClassID - 288)) |
297 (1u << (AMDGPU::TTMP_288RegClassID - 288)) |
298 (1u << (AMDGPU::SReg_288_with_sub2_sub3_sub4RegClassID - 288)) |
299 0,
300 // 320-351
301 (1u << (AMDGPU::SReg_320RegClassID - 320)) |
302 (1u << (AMDGPU::SReg_320_with_sub0_sub1_sub2RegClassID - 320)) |
303 (1u << (AMDGPU::SGPR_320RegClassID - 320)) |
304 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 320)) |
305 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 320)) |
306 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 320)) |
307 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 320)) |
308 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 320)) |
309 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 320)) |
310 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 320)) |
311 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 320)) |
312 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 320)) |
313 (1u << (AMDGPU::SGPR_320_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 320)) |
314 (1u << (AMDGPU::SReg_320_with_sub3_sub4_sub5RegClassID - 320)) |
315 (1u << (AMDGPU::TTMP_320RegClassID - 320)) |
316 (1u << (AMDGPU::SReg_320_with_sub2_sub3_sub4RegClassID - 320)) |
317 0,
318 // 352-383
319 (1u << (AMDGPU::SReg_352RegClassID - 352)) |
320 (1u << (AMDGPU::SReg_352_with_sub0_sub1_sub2RegClassID - 352)) |
321 (1u << (AMDGPU::SGPR_352RegClassID - 352)) |
322 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 352)) |
323 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 352)) |
324 (1u << (AMDGPU::SReg_352_with_sub8_sub9_sub10RegClassID - 352)) |
325 0,
326 // 384-415
327 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 384)) |
328 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 384)) |
329 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_352_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 384)) |
330 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 384)) |
331 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 384)) |
332 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 384)) |
333 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 384)) |
334 (1u << (AMDGPU::SGPR_352_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 384)) |
335 (1u << (AMDGPU::SReg_352_with_sub3_sub4_sub5RegClassID - 384)) |
336 (1u << (AMDGPU::SReg_352_with_sub2_sub3_sub4RegClassID - 384)) |
337 (1u << (AMDGPU::TTMP_352RegClassID - 384)) |
338 0,
339 // 416-447
340 (1u << (AMDGPU::SReg_384RegClassID - 416)) |
341 (1u << (AMDGPU::SReg_384_with_sub0_sub1_sub2RegClassID - 416)) |
342 (1u << (AMDGPU::SGPR_384RegClassID - 416)) |
343 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 416)) |
344 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 416)) |
345 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 416)) |
346 (1u << (AMDGPU::SGPR_384_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 416)) |
347 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 416)) |
348 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 416)) |
349 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 416)) |
350 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 416)) |
351 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 416)) |
352 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 416)) |
353 (1u << (AMDGPU::SGPR_384_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 416)) |
354 (1u << (AMDGPU::SReg_384_with_sub3_sub4_sub5RegClassID - 416)) |
355 (1u << (AMDGPU::SReg_384_with_sub8_sub9_sub10RegClassID - 416)) |
356 (1u << (AMDGPU::SReg_384_with_sub2_sub3_sub4RegClassID - 416)) |
357 (1u << (AMDGPU::TTMP_384RegClassID - 416)) |
358 0,
359 // 448-479
360 0,
361 // 480-511
362 (1u << (AMDGPU::SReg_512RegClassID - 480)) |
363 (1u << (AMDGPU::SGPR_512RegClassID - 480)) |
364 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 480)) |
365 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 480)) |
366 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 480)) |
367 (1u << (AMDGPU::SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 480)) |
368 (1u << (AMDGPU::SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 480)) |
369 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_SGPR_320_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 480)) |
370 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 480)) |
371 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 480)) |
372 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 480)) |
373 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 480)) |
374 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 480)) |
375 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 480)) |
376 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 480)) |
377 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 480)) |
378 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 480)) |
379 (1u << (AMDGPU::SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 480)) |
380 (1u << (AMDGPU::SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 480)) |
381 (1u << (AMDGPU::SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 480)) |
382 (1u << (AMDGPU::TTMP_512RegClassID - 480)) |
383 0,
384 // 512-543
385 0,
386 // 544-575
387 0,
388 // 576-607
389 (1u << (AMDGPU::SReg_1024RegClassID - 576)) |
390 (1u << (AMDGPU::SGPR_1024RegClassID - 576)) |
391 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 576)) |
392 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 576)) |
393 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 576)) |
394 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
395 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
396 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
397 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
398 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
399 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
400 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
401 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
402 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
403 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
404 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
405 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
406 (1u << (AMDGPU::SGPR_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
407 (1u << (AMDGPU::SGPR_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
408 (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
409 (1u << (AMDGPU::SGPR_1024_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
410 (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
411 (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
412 (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
413 0,
414 // 608-639
415 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 608)) |
416 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 608)) |
417 (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 608)) |
418 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
419 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
420 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
421 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
422 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
423 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
424 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
425 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
426 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
427 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
428 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
429 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
430 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
431 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
432 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
433 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
434 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
435 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
436 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
437 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
438 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
439 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
440 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
441 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
442 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
443 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
444 (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
445 (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
446 (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 608)) |
447 0,
448 // 640-671
449 (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 640)) |
450 (1u << (AMDGPU::SGPR_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 640)) |
451 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_SGPR_320_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 640)) |
452 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_SGPR_320_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 640)) |
453 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_SGPR_320_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 640)) |
454 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_SGPR_320_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 640)) |
455 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_SGPR_320_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 640)) |
456 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_SGPR_512_with_sub4_sub5_sub6_sub7_sub8_sub9_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 640)) |
457 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 640)) |
458 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub8_sub9_sub10_sub11_sub12_sub13_in_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 640)) |
459 0,
460};
461const uint32_t VCCRegBankCoverageData[] = {
462 // 0-31
463 (1u << (AMDGPU::SReg_1RegClassID - 0)) |
464 (1u << (AMDGPU::SReg_1_XEXECRegClassID - 0)) |
465 (1u << (AMDGPU::SReg_1_with_lo16_in_SGPR_LO16RegClassID - 0)) |
466 (1u << (AMDGPU::SReg_1_with_sub0_and_SReg_1_with_lo16_in_SGPR_LO16RegClassID - 0)) |
467 (1u << (AMDGPU::VReg_1RegClassID - 0)) |
468 (1u << (AMDGPU::VS_16RegClassID - 0)) |
469 (1u << (AMDGPU::VS_16_Lo128RegClassID - 0)) |
470 (1u << (AMDGPU::SReg_LO16RegClassID - 0)) |
471 (1u << (AMDGPU::VS_16_and_SReg_1RegClassID - 0)) |
472 (1u << (AMDGPU::VS_16_and_SReg_1_XEXECRegClassID - 0)) |
473 (1u << (AMDGPU::SGPR_LO16RegClassID - 0)) |
474 (1u << (AMDGPU::VS_16_and_SReg_1_with_lo16_in_SGPR_LO16RegClassID - 0)) |
475 (1u << (AMDGPU::VS_32RegClassID - 0)) |
476 (1u << (AMDGPU::VS_32_with_hi16RegClassID - 0)) |
477 (1u << (AMDGPU::VS_32_Lo128RegClassID - 0)) |
478 (1u << (AMDGPU::VS_32_Lo128_with_hi16RegClassID - 0)) |
479 (1u << (AMDGPU::SReg_1_XEXEC_with_sub0RegClassID - 0)) |
480 (1u << (AMDGPU::SReg_1_with_sub0_and_SReg_1_with_lo16_in_TTMP_LO16RegClassID - 0)) |
481 (1u << (AMDGPU::SReg_1_with_lo16_in_TTMP_LO16RegClassID - 0)) |
482 (1u << (AMDGPU::TTMP_LO16RegClassID - 0)) |
483 (1u << (AMDGPU::VS_16_and_SReg_1_with_lo16_in_TTMP_LO16RegClassID - 0)) |
484 (1u << (AMDGPU::SReg_1_with_lo16_in_M0_CLASS_LO16RegClassID - 0)) |
485 (1u << (AMDGPU::M0_CLASS_LO16RegClassID - 0)) |
486 (1u << (AMDGPU::SReg_1_with_sub0RegClassID - 0)) |
487 0,
488 // 32-63
489 (1u << (AMDGPU::SRegOrLds_32RegClassID - 32)) |
490 (1u << (AMDGPU::SReg_32RegClassID - 32)) |
491 (1u << (AMDGPU::SReg_32_XEXEC_HIRegClassID - 32)) |
492 (1u << (AMDGPU::SReg_32_XM0RegClassID - 32)) |
493 (1u << (AMDGPU::SReg_32_XEXECRegClassID - 32)) |
494 (1u << (AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID - 32)) |
495 (1u << (AMDGPU::SReg_32_XM0_XEXECRegClassID - 32)) |
496 (1u << (AMDGPU::SGPR_32RegClassID - 32)) |
497 (1u << (AMDGPU::SGPR_64RegClassID - 32)) |
498 (1u << (AMDGPU::TTMP_32RegClassID - 32)) |
499 (1u << (AMDGPU::SReg_64_XEXECRegClassID - 32)) |
500 (1u << (AMDGPU::M0_CLASSRegClassID - 32)) |
501 (1u << (AMDGPU::SReg_64RegClassID - 32)) |
502 0,
503 // 64-95
504 (1u << (AMDGPU::CCR_SGPR_64RegClassID - 64)) |
505 (1u << (AMDGPU::Gfx_CCR_SGPR_64RegClassID - 64)) |
506 (1u << (AMDGPU::TTMP_64RegClassID - 64)) |
507 0,
508 // 96-127
509 0,
510 // 128-159
511 0,
512 // 160-191
513 0,
514 // 192-223
515 0,
516 // 224-255
517 0,
518 // 256-287
519 0,
520 // 288-319
521 0,
522 // 320-351
523 0,
524 // 352-383
525 0,
526 // 384-415
527 0,
528 // 416-447
529 0,
530 // 448-479
531 0,
532 // 480-511
533 0,
534 // 512-543
535 0,
536 // 544-575
537 0,
538 // 576-607
539 0,
540 // 608-639
541 0,
542 // 640-671
543 0,
544};
545const uint32_t VGPRRegBankCoverageData[] = {
546 // 0-31
547 (1u << (AMDGPU::VS_16RegClassID - 0)) |
548 (1u << (AMDGPU::VGPR_16RegClassID - 0)) |
549 (1u << (AMDGPU::VS_16_Lo128RegClassID - 0)) |
550 (1u << (AMDGPU::VGPR_16_Lo128RegClassID - 0)) |
551 (1u << (AMDGPU::AV_32RegClassID - 0)) |
552 (1u << (AMDGPU::VS_32RegClassID - 0)) |
553 (1u << (AMDGPU::VS_32_with_hi16RegClassID - 0)) |
554 (1u << (AMDGPU::VRegOrLds_32RegClassID - 0)) |
555 (1u << (AMDGPU::VS_32_Lo128RegClassID - 0)) |
556 (1u << (AMDGPU::VS_32_Lo128_with_hi16RegClassID - 0)) |
557 0,
558 // 32-63
559 (1u << (AMDGPU::VGPR_32RegClassID - 32)) |
560 (1u << (AMDGPU::VGPR_32_Lo128RegClassID - 32)) |
561 (1u << (AMDGPU::VReg_64RegClassID - 32)) |
562 (1u << (AMDGPU::AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 32)) |
563 (1u << (AMDGPU::VRegOrLds_32_and_VS_32_Lo128RegClassID - 32)) |
564 (1u << (AMDGPU::AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 32)) |
565 (1u << (AMDGPU::AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 32)) |
566 (1u << (AMDGPU::VReg_64_Align2RegClassID - 32)) |
567 (1u << (AMDGPU::AV_64RegClassID - 32)) |
568 (1u << (AMDGPU::VS_64RegClassID - 32)) |
569 (1u << (AMDGPU::VS_64_with_sub0_in_VS_32_Lo128RegClassID - 32)) |
570 (1u << (AMDGPU::VS_64_with_sub1_in_VS_32_Lo128RegClassID - 32)) |
571 (1u << (AMDGPU::AV_64_Align2RegClassID - 32)) |
572 0,
573 // 64-95
574 (1u << (AMDGPU::VReg_96RegClassID - 64)) |
575 (1u << (AMDGPU::AV_96_with_hi16_in_VGPR_16_Lo128RegClassID - 64)) |
576 (1u << (AMDGPU::AV_96_with_sub0_sub1_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 64)) |
577 (1u << (AMDGPU::AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 64)) |
578 (1u << (AMDGPU::AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 64)) |
579 (1u << (AMDGPU::AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 64)) |
580 (1u << (AMDGPU::AV_96_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 64)) |
581 (1u << (AMDGPU::AV_96_with_hi16_in_VGPR_16_Lo128_and_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) |
582 (1u << (AMDGPU::AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 64)) |
583 (1u << (AMDGPU::VReg_96_Align2RegClassID - 64)) |
584 (1u << (AMDGPU::VReg_128RegClassID - 64)) |
585 (1u << (AMDGPU::AV_96RegClassID - 64)) |
586 (1u << (AMDGPU::AV_96_Align2RegClassID - 64)) |
587 (1u << (AMDGPU::AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) |
588 (1u << (AMDGPU::AV_128RegClassID - 64)) |
589 (1u << (AMDGPU::AV_128_Align2RegClassID - 64)) |
590 (1u << (AMDGPU::AV_128_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) |
591 0,
592 // 96-127
593 (1u << (AMDGPU::AV_128_with_hi16_in_VGPR_16_Lo128RegClassID - 96)) |
594 (1u << (AMDGPU::AV_128_with_sub0_sub1_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 96)) |
595 (1u << (AMDGPU::AV_128_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 96)) |
596 (1u << (AMDGPU::AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 96)) |
597 (1u << (AMDGPU::AV_128_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 96)) |
598 (1u << (AMDGPU::AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 96)) |
599 (1u << (AMDGPU::AV_128_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 96)) |
600 (1u << (AMDGPU::AV_128_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 96)) |
601 (1u << (AMDGPU::AV_128_with_hi16_in_VGPR_16_Lo128_and_AV_128_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 96)) |
602 (1u << (AMDGPU::VReg_128_Align2RegClassID - 96)) |
603 (1u << (AMDGPU::AV_128_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 96)) |
604 (1u << (AMDGPU::VReg_160RegClassID - 96)) |
605 (1u << (AMDGPU::AV_160_with_hi16_in_VGPR_16_Lo128RegClassID - 96)) |
606 (1u << (AMDGPU::AV_160_with_sub0_sub1_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 96)) |
607 (1u << (AMDGPU::AV_160RegClassID - 96)) |
608 (1u << (AMDGPU::AV_160_Align2RegClassID - 96)) |
609 (1u << (AMDGPU::AV_160_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 96)) |
610 0,
611 // 128-159
612 (1u << (AMDGPU::AV_160_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 128)) |
613 (1u << (AMDGPU::AV_160_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 128)) |
614 (1u << (AMDGPU::AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 128)) |
615 (1u << (AMDGPU::AV_160_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 128)) |
616 (1u << (AMDGPU::AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 128)) |
617 (1u << (AMDGPU::AV_160_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 128)) |
618 (1u << (AMDGPU::AV_160_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 128)) |
619 (1u << (AMDGPU::AV_160_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 128)) |
620 (1u << (AMDGPU::AV_160_with_hi16_in_VGPR_16_Lo128_and_AV_160_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 128)) |
621 (1u << (AMDGPU::AV_160_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 128)) |
622 (1u << (AMDGPU::VReg_160_Align2RegClassID - 128)) |
623 (1u << (AMDGPU::VReg_192RegClassID - 128)) |
624 (1u << (AMDGPU::AV_192_with_hi16_in_VGPR_16_Lo128RegClassID - 128)) |
625 (1u << (AMDGPU::AV_192_with_sub0_sub1_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 128)) |
626 (1u << (AMDGPU::AV_192_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 128)) |
627 (1u << (AMDGPU::VReg_192_Align2RegClassID - 128)) |
628 (1u << (AMDGPU::AV_192RegClassID - 128)) |
629 (1u << (AMDGPU::AV_192_Align2RegClassID - 128)) |
630 (1u << (AMDGPU::AV_192_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 128)) |
631 0,
632 // 160-191
633 (1u << (AMDGPU::AV_192_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 160)) |
634 (1u << (AMDGPU::AV_192_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 160)) |
635 (1u << (AMDGPU::AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 160)) |
636 (1u << (AMDGPU::AV_192_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 160)) |
637 (1u << (AMDGPU::AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 160)) |
638 (1u << (AMDGPU::AV_192_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 160)) |
639 (1u << (AMDGPU::AV_192_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 160)) |
640 (1u << (AMDGPU::AV_192_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 160)) |
641 (1u << (AMDGPU::AV_192_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 160)) |
642 (1u << (AMDGPU::AV_192_with_hi16_in_VGPR_16_Lo128_and_AV_192_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 160)) |
643 (1u << (AMDGPU::AV_192_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 160)) |
644 (1u << (AMDGPU::VReg_224RegClassID - 160)) |
645 (1u << (AMDGPU::AV_224_with_hi16_in_VGPR_16_Lo128RegClassID - 160)) |
646 (1u << (AMDGPU::AV_224_with_sub0_sub1_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 160)) |
647 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 160)) |
648 (1u << (AMDGPU::AV_224RegClassID - 160)) |
649 (1u << (AMDGPU::AV_224_Align2RegClassID - 160)) |
650 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 160)) |
651 0,
652 // 192-223
653 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 192)) |
654 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 192)) |
655 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 192)) |
656 (1u << (AMDGPU::AV_224_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 192)) |
657 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 192)) |
658 (1u << (AMDGPU::AV_224_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 192)) |
659 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 192)) |
660 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 192)) |
661 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 192)) |
662 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 192)) |
663 (1u << (AMDGPU::AV_224_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 192)) |
664 (1u << (AMDGPU::AV_224_with_hi16_in_VGPR_16_Lo128_and_AV_224_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 192)) |
665 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 192)) |
666 (1u << (AMDGPU::VReg_224_Align2RegClassID - 192)) |
667 (1u << (AMDGPU::VReg_256RegClassID - 192)) |
668 (1u << (AMDGPU::AV_256RegClassID - 192)) |
669 (1u << (AMDGPU::AV_256_Align2RegClassID - 192)) |
670 0,
671 // 224-255
672 (1u << (AMDGPU::AV_256_with_hi16_in_VGPR_16_Lo128RegClassID - 224)) |
673 (1u << (AMDGPU::AV_256_with_sub0_sub1_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
674 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
675 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
676 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
677 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
678 (1u << (AMDGPU::AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
679 (1u << (AMDGPU::AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
680 (1u << (AMDGPU::AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
681 (1u << (AMDGPU::AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
682 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
683 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
684 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
685 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
686 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 224)) |
687 (1u << (AMDGPU::AV_256_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 224)) |
688 (1u << (AMDGPU::AV_256_with_hi16_in_VGPR_16_Lo128_and_AV_256_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 224)) |
689 (1u << (AMDGPU::VReg_256_Align2RegClassID - 224)) |
690 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 224)) |
691 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 224)) |
692 0,
693 // 256-287
694 (1u << (AMDGPU::VReg_288RegClassID - 256)) |
695 (1u << (AMDGPU::AV_288_with_hi16_in_VGPR_16_Lo128RegClassID - 256)) |
696 (1u << (AMDGPU::AV_288_with_sub0_sub1_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
697 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
698 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
699 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
700 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
701 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
702 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
703 (1u << (AMDGPU::AV_288_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
704 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
705 (1u << (AMDGPU::AV_288_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
706 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
707 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
708 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
709 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
710 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) |
711 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 256)) |
712 (1u << (AMDGPU::AV_288_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 256)) |
713 (1u << (AMDGPU::AV_288_with_hi16_in_VGPR_16_Lo128_and_AV_288_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 256)) |
714 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 256)) |
715 (1u << (AMDGPU::VReg_288_Align2RegClassID - 256)) |
716 (1u << (AMDGPU::AV_288RegClassID - 256)) |
717 (1u << (AMDGPU::AV_288_Align2RegClassID - 256)) |
718 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 256)) |
719 0,
720 // 288-319
721 (1u << (AMDGPU::VReg_320RegClassID - 288)) |
722 (1u << (AMDGPU::AV_320_with_hi16_in_VGPR_16_Lo128RegClassID - 288)) |
723 (1u << (AMDGPU::AV_320_with_sub0_sub1_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 288)) |
724 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 288)) |
725 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 288)) |
726 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 288)) |
727 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 288)) |
728 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 288)) |
729 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 288)) |
730 (1u << (AMDGPU::AV_320_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 288)) |
731 (1u << (AMDGPU::AV_320_with_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 288)) |
732 (1u << (AMDGPU::AV_320_with_hi16_in_VGPR_16_Lo128_and_AV_320_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 288)) |
733 (1u << (AMDGPU::VReg_320_Align2RegClassID - 288)) |
734 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 288)) |
735 (1u << (AMDGPU::AV_320RegClassID - 288)) |
736 (1u << (AMDGPU::AV_320_Align2RegClassID - 288)) |
737 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 288)) |
738 0,
739 // 320-351
740 (1u << (AMDGPU::AV_320_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 320)) |
741 (1u << (AMDGPU::AV_320_with_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 320)) |
742 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 320)) |
743 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 320)) |
744 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 320)) |
745 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 320)) |
746 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 320)) |
747 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 320)) |
748 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 320)) |
749 (1u << (AMDGPU::AV_320_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 320)) |
750 (1u << (AMDGPU::VReg_352RegClassID - 320)) |
751 (1u << (AMDGPU::AV_352_with_hi16_in_VGPR_16_Lo128RegClassID - 320)) |
752 (1u << (AMDGPU::AV_352RegClassID - 320)) |
753 (1u << (AMDGPU::AV_352_Align2RegClassID - 320)) |
754 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 320)) |
755 0,
756 // 352-383
757 (1u << (AMDGPU::AV_352_with_sub0_sub1_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
758 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
759 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
760 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
761 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
762 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
763 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
764 (1u << (AMDGPU::AV_352_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
765 (1u << (AMDGPU::AV_352_with_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
766 (1u << (AMDGPU::AV_352_with_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
767 (1u << (AMDGPU::AV_352_with_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
768 (1u << (AMDGPU::AV_352_with_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
769 (1u << (AMDGPU::AV_352_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
770 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
771 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
772 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
773 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
774 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
775 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
776 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 352)) |
777 (1u << (AMDGPU::AV_352_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 352)) |
778 (1u << (AMDGPU::AV_352_with_hi16_in_VGPR_16_Lo128_and_AV_352_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 352)) |
779 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 352)) |
780 (1u << (AMDGPU::VReg_352_Align2RegClassID - 352)) |
781 0,
782 // 384-415
783 (1u << (AMDGPU::VReg_384RegClassID - 384)) |
784 (1u << (AMDGPU::AV_384_with_hi16_in_VGPR_16_Lo128RegClassID - 384)) |
785 (1u << (AMDGPU::AV_384_with_sub0_sub1_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 384)) |
786 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 384)) |
787 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 384)) |
788 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 384)) |
789 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 384)) |
790 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 384)) |
791 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 384)) |
792 (1u << (AMDGPU::AV_384_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 384)) |
793 (1u << (AMDGPU::AV_384_with_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 384)) |
794 (1u << (AMDGPU::AV_384_with_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 384)) |
795 (1u << (AMDGPU::AV_384_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 384)) |
796 (1u << (AMDGPU::VReg_384_Align2RegClassID - 384)) |
797 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 384)) |
798 (1u << (AMDGPU::AV_384RegClassID - 384)) |
799 (1u << (AMDGPU::AV_384_Align2RegClassID - 384)) |
800 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 384)) |
801 0,
802 // 416-447
803 (1u << (AMDGPU::AV_384_with_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 416)) |
804 (1u << (AMDGPU::AV_384_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 416)) |
805 (1u << (AMDGPU::AV_384_with_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 416)) |
806 (1u << (AMDGPU::AV_384_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 416)) |
807 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 416)) |
808 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 416)) |
809 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 416)) |
810 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 416)) |
811 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 416)) |
812 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 416)) |
813 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 416)) |
814 (1u << (AMDGPU::AV_384_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 416)) |
815 (1u << (AMDGPU::AV_384_with_hi16_in_VGPR_16_Lo128_and_AV_384_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 416)) |
816 (1u << (AMDGPU::AV_512RegClassID - 416)) |
817 0,
818 // 448-479
819 (1u << (AMDGPU::VReg_512RegClassID - 448)) |
820 (1u << (AMDGPU::AV_512_with_hi16_in_VGPR_16_Lo128RegClassID - 448)) |
821 (1u << (AMDGPU::AV_512_with_sub0_sub1_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
822 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
823 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
824 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
825 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
826 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
827 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
828 (1u << (AMDGPU::AV_512_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
829 (1u << (AMDGPU::AV_512_with_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
830 (1u << (AMDGPU::AV_512_with_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
831 (1u << (AMDGPU::AV_512_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
832 (1u << (AMDGPU::AV_512_with_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
833 (1u << (AMDGPU::AV_512_with_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
834 (1u << (AMDGPU::AV_512_with_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
835 (1u << (AMDGPU::AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
836 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
837 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
838 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
839 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
840 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
841 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 448)) |
842 (1u << (AMDGPU::AV_512_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 448)) |
843 (1u << (AMDGPU::AV_512_with_hi16_in_VGPR_16_Lo128_and_AV_512_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 448)) |
844 (1u << (AMDGPU::VReg_512_Align2RegClassID - 448)) |
845 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 448)) |
846 (1u << (AMDGPU::AV_512_Align2RegClassID - 448)) |
847 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 448)) |
848 0,
849 // 480-511
850 (1u << (AMDGPU::AV_512_with_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 480)) |
851 (1u << (AMDGPU::AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 480)) |
852 (1u << (AMDGPU::AV_512_with_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 480)) |
853 (1u << (AMDGPU::AV_512_with_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 480)) |
854 (1u << (AMDGPU::AV_512_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 480)) |
855 (1u << (AMDGPU::AV_512_with_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 480)) |
856 (1u << (AMDGPU::AV_512_with_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 480)) |
857 (1u << (AMDGPU::AV_512_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 480)) |
858 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 480)) |
859 0,
860 // 512-543
861 (1u << (AMDGPU::VReg_1024RegClassID - 512)) |
862 (1u << (AMDGPU::AV_1024_with_hi16_in_VGPR_16_Lo128RegClassID - 512)) |
863 (1u << (AMDGPU::AV_1024_with_sub0_sub1_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
864 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
865 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
866 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
867 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
868 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
869 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
870 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
871 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
872 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
873 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
874 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
875 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
876 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
877 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
878 (1u << (AMDGPU::AV_1024_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
879 (1u << (AMDGPU::AV_1024_with_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
880 (1u << (AMDGPU::AV_1024_with_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
881 (1u << (AMDGPU::AV_1024_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
882 (1u << (AMDGPU::AV_1024_with_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
883 (1u << (AMDGPU::AV_1024_with_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
884 (1u << (AMDGPU::AV_1024_with_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
885 (1u << (AMDGPU::AV_1024_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
886 (1u << (AMDGPU::AV_1024_with_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 512)) |
887 (1u << (AMDGPU::VReg_1024_Align2RegClassID - 512)) |
888 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 512)) |
889 0,
890 // 544-575
891 (1u << (AMDGPU::AV_1024_with_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
892 (1u << (AMDGPU::AV_1024_with_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
893 (1u << (AMDGPU::AV_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
894 (1u << (AMDGPU::AV_1024_with_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
895 (1u << (AMDGPU::AV_1024_with_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
896 (1u << (AMDGPU::AV_1024_with_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
897 (1u << (AMDGPU::AV_1024_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
898 (1u << (AMDGPU::AV_1024_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
899 (1u << (AMDGPU::AV_1024_with_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
900 (1u << (AMDGPU::AV_1024_with_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
901 (1u << (AMDGPU::AV_1024_with_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
902 (1u << (AMDGPU::AV_1024_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
903 (1u << (AMDGPU::AV_1024_with_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
904 (1u << (AMDGPU::AV_1024_with_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
905 (1u << (AMDGPU::AV_1024_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
906 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
907 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
908 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
909 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
910 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
911 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
912 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
913 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_512_with_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
914 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
915 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_256_with_sub1_sub2_sub3_sub4_sub5_sub6_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
916 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
917 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
918 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
919 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
920 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 544)) |
921 (1u << (AMDGPU::AV_1024_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 544)) |
922 (1u << (AMDGPU::AV_1024_with_hi16_in_VGPR_16_Lo128_and_AV_1024_with_sub0_sub1_sub2_in_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 544)) |
923 0,
924 // 576-607
925 (1u << (AMDGPU::AV_1024_with_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 576)) |
926 (1u << (AMDGPU::AV_1024_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 576)) |
927 (1u << (AMDGPU::AV_1024_with_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 576)) |
928 (1u << (AMDGPU::AV_1024_with_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 576)) |
929 (1u << (AMDGPU::AV_1024_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 576)) |
930 (1u << (AMDGPU::AV_1024_with_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 576)) |
931 (1u << (AMDGPU::AV_1024_with_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 576)) |
932 (1u << (AMDGPU::AV_1024_with_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_in_AV_512_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_AV_256_with_sub2_sub3_sub4_sub5_sub6_sub7_in_AV_192_with_sub1_sub2_sub3_sub4_sub5_in_AV_160_with_sub1_sub2_sub3_sub4_in_AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub1_sub2_in_AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 576)) |
933 0,
934 // 608-639
935 0,
936 // 640-671
937 0,
938};
939
940constexpr RegisterBank AGPRRegBank(/* ID */ AMDGPU::AGPRRegBankID, /* Name */ "AGPR", /* CoveredRegClasses */ AGPRRegBankCoverageData, /* NumRegClasses */ 650);
941constexpr RegisterBank SGPRRegBank(/* ID */ AMDGPU::SGPRRegBankID, /* Name */ "SGPR", /* CoveredRegClasses */ SGPRRegBankCoverageData, /* NumRegClasses */ 650);
942constexpr RegisterBank VCCRegBank(/* ID */ AMDGPU::VCCRegBankID, /* Name */ "VCC", /* CoveredRegClasses */ VCCRegBankCoverageData, /* NumRegClasses */ 650);
943constexpr RegisterBank VGPRRegBank(/* ID */ AMDGPU::VGPRRegBankID, /* Name */ "VGPR", /* CoveredRegClasses */ VGPRRegBankCoverageData, /* NumRegClasses */ 650);
944} // end namespace AMDGPU
945
946const RegisterBank *AMDGPUGenRegisterBankInfo::RegBanks[] = {
947 &AMDGPU::AGPRRegBank,
948 &AMDGPU::SGPRRegBank,
949 &AMDGPU::VCCRegBank,
950 &AMDGPU::VGPRRegBank,
951};
952
953const unsigned AMDGPUGenRegisterBankInfo::Sizes[] = {
954 // Mode = 0 (Default)
955 1024,
956 1024,
957 64,
958 1024,
959};
960
961AMDGPUGenRegisterBankInfo::AMDGPUGenRegisterBankInfo(unsigned HwMode)
962 : RegisterBankInfo(RegBanks, AMDGPU::NumRegisterBanks, Sizes, HwMode) {
963 // Assert that RegBank indices match their ID's
964#ifndef NDEBUG
965 for (auto RB : enumerate(RegBanks))
966 assert(RB.index() == RB.value()->getID() && "Index != ID");
967#endif // NDEBUG
968}
969} // end namespace llvm
970#endif // GET_TARGET_REGBANK_IMPL
971