1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace AMDGPU {
15enum {
16 Feature1_5xVGPRs = 0,
17 Feature16BitInsts = 1,
18 FeatureA16 = 2,
19 FeatureAddNoCarryInsts = 3,
20 FeatureAgentScopeFineGrainedRemoteMemoryAtomics = 4,
21 FeatureApertureRegs = 5,
22 FeatureArchitectedFlatScratch = 6,
23 FeatureArchitectedSGPRs = 7,
24 FeatureAtomicBufferGlobalPkAddF16Insts = 8,
25 FeatureAtomicBufferGlobalPkAddF16NoRtnInsts = 9,
26 FeatureAtomicBufferPkAddBF16Inst = 10,
27 FeatureAtomicCSubNoRtnInsts = 11,
28 FeatureAtomicDsPkAdd16Insts = 12,
29 FeatureAtomicFMinFMaxF32FlatInsts = 13,
30 FeatureAtomicFMinFMaxF32GlobalInsts = 14,
31 FeatureAtomicFMinFMaxF64FlatInsts = 15,
32 FeatureAtomicFMinFMaxF64GlobalInsts = 16,
33 FeatureAtomicFaddNoRtnInsts = 17,
34 FeatureAtomicFaddRtnInsts = 18,
35 FeatureAtomicFlatPkAdd16Insts = 19,
36 FeatureAtomicGlobalPkAddBF16Inst = 20,
37 FeatureAutoWaitcntBeforeBarrier = 21,
38 FeatureBackOffBarrier = 22,
39 FeatureCIInsts = 23,
40 FeatureCuMode = 24,
41 FeatureDLInsts = 25,
42 FeatureDPALU_DPP = 26,
43 FeatureDPP = 27,
44 FeatureDPP8 = 28,
45 FeatureDPPSrc1SGPR = 29,
46 FeatureDefaultComponentBroadcast = 30,
47 FeatureDefaultComponentZero = 31,
48 FeatureDisable = 32,
49 FeatureDot1Insts = 33,
50 FeatureDot2Insts = 34,
51 FeatureDot3Insts = 35,
52 FeatureDot4Insts = 36,
53 FeatureDot5Insts = 37,
54 FeatureDot6Insts = 38,
55 FeatureDot7Insts = 39,
56 FeatureDot8Insts = 40,
57 FeatureDot9Insts = 41,
58 FeatureDot10Insts = 42,
59 FeatureDot11Insts = 43,
60 FeatureDsSrc2Insts = 44,
61 FeatureDumpCode = 45,
62 FeatureDumpCodeLower = 46,
63 FeatureEnableDS128 = 47,
64 FeatureEnableFlatScratch = 48,
65 FeatureEnableLoadStoreOpt = 49,
66 FeatureEnablePRTStrictNull = 50,
67 FeatureEnableSIScheduler = 51,
68 FeatureEnableUnsafeDSOffsetFolding = 52,
69 FeatureExtendedImageInsts = 53,
70 FeatureFMA = 54,
71 FeatureFP8ConversionInsts = 55,
72 FeatureFP8Insts = 56,
73 FeatureFP64 = 57,
74 FeatureFastDenormalF32 = 58,
75 FeatureFastFMAF32 = 59,
76 FeatureFlatAddressSpace = 60,
77 FeatureFlatAtomicFaddF32Inst = 61,
78 FeatureFlatBufferGlobalAtomicFaddF64Inst = 62,
79 FeatureFlatForGlobal = 63,
80 FeatureFlatGlobalInsts = 64,
81 FeatureFlatInstOffsets = 65,
82 FeatureFlatScratchInsts = 66,
83 FeatureFlatSegmentOffsetBug = 67,
84 FeatureFmaMixInsts = 68,
85 FeatureFmacF64Inst = 69,
86 FeatureForceStoreSC0SC1 = 70,
87 FeatureG16 = 71,
88 FeatureGCN3Encoding = 72,
89 FeatureGDS = 73,
90 FeatureGFX7GFX8GFX9Insts = 74,
91 FeatureGFX8Insts = 75,
92 FeatureGFX9 = 76,
93 FeatureGFX9Insts = 77,
94 FeatureGFX10 = 78,
95 FeatureGFX10Insts = 79,
96 FeatureGFX10_3Insts = 80,
97 FeatureGFX10_AEncoding = 81,
98 FeatureGFX10_BEncoding = 82,
99 FeatureGFX11 = 83,
100 FeatureGFX11Insts = 84,
101 FeatureGFX12 = 85,
102 FeatureGFX12Insts = 86,
103 FeatureGFX90AInsts = 87,
104 FeatureGFX940Insts = 88,
105 FeatureGWS = 89,
106 FeatureGetWaveIdInst = 90,
107 FeatureHasRestrictedSOffset = 91,
108 FeatureImageGather4D16Bug = 92,
109 FeatureImageInsts = 93,
110 FeatureImageStoreD16Bug = 94,
111 FeatureInstFwdPrefetchBug = 95,
112 FeatureIntClamp = 96,
113 FeatureInv2PiInlineImm = 97,
114 FeatureKernargPreload = 98,
115 FeatureLDSBankCount16 = 99,
116 FeatureLDSBankCount32 = 100,
117 FeatureLdsBranchVmemWARHazard = 101,
118 FeatureLdsMisalignedBug = 102,
119 FeatureLocalMemorySize32768 = 103,
120 FeatureLocalMemorySize65536 = 104,
121 FeatureMADIntraFwdBug = 105,
122 FeatureMAIInsts = 106,
123 FeatureMFMAInlineLiteralBug = 107,
124 FeatureMIMG_R128 = 108,
125 FeatureMSAALoadDstSelBug = 109,
126 FeatureMadMacF32Insts = 110,
127 FeatureMadMixInsts = 111,
128 FeatureMaxHardClauseLength32 = 112,
129 FeatureMaxHardClauseLength63 = 113,
130 FeatureMaxPrivateElementSize4 = 114,
131 FeatureMaxPrivateElementSize8 = 115,
132 FeatureMaxPrivateElementSize16 = 116,
133 FeatureMemoryAtomicFAddF32DenormalSupport = 117,
134 FeatureMovrel = 118,
135 FeatureNSAClauseBug = 119,
136 FeatureNSAEncoding = 120,
137 FeatureNSAtoVMEMBug = 121,
138 FeatureNegativeScratchOffsetBug = 122,
139 FeatureNegativeUnalignedScratchOffsetBug = 123,
140 FeatureNoDataDepHazard = 124,
141 FeatureNoSdstCMPX = 125,
142 FeatureOffset3fBug = 126,
143 FeaturePackedFP32Ops = 127,
144 FeaturePackedTID = 128,
145 FeaturePartialNSAEncoding = 129,
146 FeaturePkFmacF16Inst = 130,
147 FeaturePreciseMemory = 131,
148 FeaturePrivEnabledTrap2NopBug = 132,
149 FeaturePromoteAlloca = 133,
150 FeaturePseudoScalarTrans = 134,
151 FeatureR128A16 = 135,
152 FeatureRealTrue16Insts = 136,
153 FeatureRequiredExportPriority = 137,
154 FeatureRequiresCOV6 = 138,
155 FeatureSALUFloatInsts = 139,
156 FeatureSDWA = 140,
157 FeatureSDWAMac = 141,
158 FeatureSDWAOmod = 142,
159 FeatureSDWAOutModsVOPC = 143,
160 FeatureSDWAScalar = 144,
161 FeatureSDWASdst = 145,
162 FeatureSGPRInitBug = 146,
163 FeatureSMEMtoVectorWriteHazard = 147,
164 FeatureSMemRealTime = 148,
165 FeatureSMemTimeInst = 149,
166 FeatureSRAMECC = 150,
167 FeatureScalarAtomics = 151,
168 FeatureScalarDwordx3Loads = 152,
169 FeatureScalarFlatScratchInsts = 153,
170 FeatureScalarStores = 154,
171 FeatureSeaIslands = 155,
172 FeatureShaderCyclesHiLoRegisters = 156,
173 FeatureShaderCyclesRegister = 157,
174 FeatureSouthernIslands = 158,
175 FeatureSupportsSRAMECC = 159,
176 FeatureSupportsXNACK = 160,
177 FeatureTgSplit = 161,
178 FeatureTrapHandler = 162,
179 FeatureTrigReducedRange = 163,
180 FeatureTrue16BitInsts = 164,
181 FeatureUnalignedAccessMode = 165,
182 FeatureUnalignedBufferAccess = 166,
183 FeatureUnalignedDSAccess = 167,
184 FeatureUnalignedScratchAccess = 168,
185 FeatureUnpackedD16VMem = 169,
186 FeatureUserSGPRInit16Bug = 170,
187 FeatureVALUTransUseHazard = 171,
188 FeatureVGPRIndexMode = 172,
189 FeatureVGPRSingleUseHintInsts = 173,
190 FeatureVMEMtoScalarWriteHazard = 174,
191 FeatureVOP3Literal = 175,
192 FeatureVOP3P = 176,
193 FeatureVOPD = 177,
194 FeatureVcmpxExecWARHazard = 178,
195 FeatureVcmpxPermlaneHazard = 179,
196 FeatureVmemWriteVgprInOrder = 180,
197 FeatureVolcanicIslands = 181,
198 FeatureVscnt = 182,
199 FeatureWavefrontSize16 = 183,
200 FeatureWavefrontSize32 = 184,
201 FeatureWavefrontSize64 = 185,
202 FeatureXNACK = 186,
203 FullRate64Ops = 187,
204 HalfRate64Ops = 188,
205 NumSubtargetFeatures = 189
206};
207} // end namespace AMDGPU
208} // end namespace llvm
209
210#endif // GET_SUBTARGETINFO_ENUM
211
212
213#ifdef GET_SUBTARGETINFO_MACRO
214GET_SUBTARGETINFO_MACRO(AddNoCarryInsts, false, addNoCarryInsts)
215GET_SUBTARGETINFO_MACRO(AutoWaitcntBeforeBarrier, false, autoWaitcntBeforeBarrier)
216GET_SUBTARGETINFO_MACRO(BackOffBarrier, false, backOffBarrier)
217GET_SUBTARGETINFO_MACRO(CIInsts, false, cIInsts)
218GET_SUBTARGETINFO_MACRO(DumpCode, false, dumpCode)
219GET_SUBTARGETINFO_MACRO(DumpCode, false, dumpCode)
220GET_SUBTARGETINFO_MACRO(EnableCuMode, false, enableCuMode)
221GET_SUBTARGETINFO_MACRO(EnableDS128, false, enableDS128)
222GET_SUBTARGETINFO_MACRO(EnableFlatScratch, false, enableFlatScratch)
223GET_SUBTARGETINFO_MACRO(EnableLoadStoreOpt, false, enableLoadStoreOpt)
224GET_SUBTARGETINFO_MACRO(EnablePRTStrictNull, false, enablePRTStrictNull)
225GET_SUBTARGETINFO_MACRO(EnablePreciseMemory, false, enablePreciseMemory)
226GET_SUBTARGETINFO_MACRO(EnablePromoteAlloca, false, enablePromoteAlloca)
227GET_SUBTARGETINFO_MACRO(EnableRealTrue16Insts, false, enableRealTrue16Insts)
228GET_SUBTARGETINFO_MACRO(EnableSIScheduler, false, enableSIScheduler)
229GET_SUBTARGETINFO_MACRO(EnableSRAMECC, false, enableSRAMECC)
230GET_SUBTARGETINFO_MACRO(EnableTgSplit, false, enableTgSplit)
231GET_SUBTARGETINFO_MACRO(EnableUnsafeDSOffsetFolding, false, enableUnsafeDSOffsetFolding)
232GET_SUBTARGETINFO_MACRO(EnableXNACK, false, enableXNACK)
233GET_SUBTARGETINFO_MACRO(FMA, false, fMA)
234GET_SUBTARGETINFO_MACRO(FP64, false, fP64)
235GET_SUBTARGETINFO_MACRO(FastDenormalF32, false, fastDenormalF32)
236GET_SUBTARGETINFO_MACRO(FastFMAF32, false, fastFMAF32)
237GET_SUBTARGETINFO_MACRO(FeatureDisable, false, featureDisable)
238GET_SUBTARGETINFO_MACRO(FlatAddressSpace, false, flatAddressSpace)
239GET_SUBTARGETINFO_MACRO(FlatForGlobal, false, flatForGlobal)
240GET_SUBTARGETINFO_MACRO(FlatGlobalInsts, false, flatGlobalInsts)
241GET_SUBTARGETINFO_MACRO(FlatInstOffsets, false, flatInstOffsets)
242GET_SUBTARGETINFO_MACRO(FlatScratchInsts, false, flatScratchInsts)
243GET_SUBTARGETINFO_MACRO(FullRate64Ops, false, fullRate64Ops)
244GET_SUBTARGETINFO_MACRO(GCN3Encoding, false, gCN3Encoding)
245GET_SUBTARGETINFO_MACRO(GFX10Insts, false, gFX10Insts)
246GET_SUBTARGETINFO_MACRO(GFX10_3Insts, false, gFX10_3Insts)
247GET_SUBTARGETINFO_MACRO(GFX10_AEncoding, false, gFX10_AEncoding)
248GET_SUBTARGETINFO_MACRO(GFX10_BEncoding, false, gFX10_BEncoding)
249GET_SUBTARGETINFO_MACRO(GFX11Insts, false, gFX11Insts)
250GET_SUBTARGETINFO_MACRO(GFX12Insts, false, gFX12Insts)
251GET_SUBTARGETINFO_MACRO(GFX7GFX8GFX9Insts, false, gFX7GFX8GFX9Insts)
252GET_SUBTARGETINFO_MACRO(GFX8Insts, false, gFX8Insts)
253GET_SUBTARGETINFO_MACRO(GFX90AInsts, false, gFX90AInsts)
254GET_SUBTARGETINFO_MACRO(GFX940Insts, false, gFX940Insts)
255GET_SUBTARGETINFO_MACRO(GFX9Insts, false, gFX9Insts)
256GET_SUBTARGETINFO_MACRO(HalfRate64Ops, false, halfRate64Ops)
257GET_SUBTARGETINFO_MACRO(Has16BitInsts, false, has16BitInsts)
258GET_SUBTARGETINFO_MACRO(Has1_5xVGPRs, false, has1_5xVGPRs)
259GET_SUBTARGETINFO_MACRO(HasA16, false, hasA16)
260GET_SUBTARGETINFO_MACRO(HasAgentScopeFineGrainedRemoteMemoryAtomics, false, hasAgentScopeFineGrainedRemoteMemoryAtomics)
261GET_SUBTARGETINFO_MACRO(HasApertureRegs, false, hasApertureRegs)
262GET_SUBTARGETINFO_MACRO(HasArchitectedFlatScratch, false, hasArchitectedFlatScratch)
263GET_SUBTARGETINFO_MACRO(HasArchitectedSGPRs, false, hasArchitectedSGPRs)
264GET_SUBTARGETINFO_MACRO(HasAtomicBufferGlobalPkAddF16Insts, false, hasAtomicBufferGlobalPkAddF16Insts)
265GET_SUBTARGETINFO_MACRO(HasAtomicBufferGlobalPkAddF16NoRtnInsts, false, hasAtomicBufferGlobalPkAddF16NoRtnInsts)
266GET_SUBTARGETINFO_MACRO(HasAtomicBufferPkAddBF16Inst, false, hasAtomicBufferPkAddBF16Inst)
267GET_SUBTARGETINFO_MACRO(HasAtomicCSubNoRtnInsts, false, hasAtomicCSubNoRtnInsts)
268GET_SUBTARGETINFO_MACRO(HasAtomicDsPkAdd16Insts, false, hasAtomicDsPkAdd16Insts)
269GET_SUBTARGETINFO_MACRO(HasAtomicFMinFMaxF32FlatInsts, false, hasAtomicFMinFMaxF32FlatInsts)
270GET_SUBTARGETINFO_MACRO(HasAtomicFMinFMaxF32GlobalInsts, false, hasAtomicFMinFMaxF32GlobalInsts)
271GET_SUBTARGETINFO_MACRO(HasAtomicFMinFMaxF64FlatInsts, false, hasAtomicFMinFMaxF64FlatInsts)
272GET_SUBTARGETINFO_MACRO(HasAtomicFMinFMaxF64GlobalInsts, false, hasAtomicFMinFMaxF64GlobalInsts)
273GET_SUBTARGETINFO_MACRO(HasAtomicFaddNoRtnInsts, false, hasAtomicFaddNoRtnInsts)
274GET_SUBTARGETINFO_MACRO(HasAtomicFaddRtnInsts, false, hasAtomicFaddRtnInsts)
275GET_SUBTARGETINFO_MACRO(HasAtomicFlatPkAdd16Insts, false, hasAtomicFlatPkAdd16Insts)
276GET_SUBTARGETINFO_MACRO(HasAtomicGlobalPkAddBF16Inst, false, hasAtomicGlobalPkAddBF16Inst)
277GET_SUBTARGETINFO_MACRO(HasDLInsts, false, hasDLInsts)
278GET_SUBTARGETINFO_MACRO(HasDPALU_DPP, false, hasDPALU_DPP)
279GET_SUBTARGETINFO_MACRO(HasDPP, false, hasDPP)
280GET_SUBTARGETINFO_MACRO(HasDPP8, false, hasDPP8)
281GET_SUBTARGETINFO_MACRO(HasDPPSrc1SGPR, false, hasDPPSrc1SGPR)
282GET_SUBTARGETINFO_MACRO(HasDefaultComponentBroadcast, false, hasDefaultComponentBroadcast)
283GET_SUBTARGETINFO_MACRO(HasDefaultComponentZero, false, hasDefaultComponentZero)
284GET_SUBTARGETINFO_MACRO(HasDot10Insts, false, hasDot10Insts)
285GET_SUBTARGETINFO_MACRO(HasDot11Insts, false, hasDot11Insts)
286GET_SUBTARGETINFO_MACRO(HasDot1Insts, false, hasDot1Insts)
287GET_SUBTARGETINFO_MACRO(HasDot2Insts, false, hasDot2Insts)
288GET_SUBTARGETINFO_MACRO(HasDot3Insts, false, hasDot3Insts)
289GET_SUBTARGETINFO_MACRO(HasDot4Insts, false, hasDot4Insts)
290GET_SUBTARGETINFO_MACRO(HasDot5Insts, false, hasDot5Insts)
291GET_SUBTARGETINFO_MACRO(HasDot6Insts, false, hasDot6Insts)
292GET_SUBTARGETINFO_MACRO(HasDot7Insts, false, hasDot7Insts)
293GET_SUBTARGETINFO_MACRO(HasDot8Insts, false, hasDot8Insts)
294GET_SUBTARGETINFO_MACRO(HasDot9Insts, false, hasDot9Insts)
295GET_SUBTARGETINFO_MACRO(HasDsSrc2Insts, false, hasDsSrc2Insts)
296GET_SUBTARGETINFO_MACRO(HasExtendedImageInsts, false, hasExtendedImageInsts)
297GET_SUBTARGETINFO_MACRO(HasFP8ConversionInsts, false, hasFP8ConversionInsts)
298GET_SUBTARGETINFO_MACRO(HasFP8Insts, false, hasFP8Insts)
299GET_SUBTARGETINFO_MACRO(HasFlatAtomicFaddF32Inst, false, hasFlatAtomicFaddF32Inst)
300GET_SUBTARGETINFO_MACRO(HasFlatBufferGlobalAtomicFaddF64Inst, false, hasFlatBufferGlobalAtomicFaddF64Inst)
301GET_SUBTARGETINFO_MACRO(HasFlatSegmentOffsetBug, false, hasFlatSegmentOffsetBug)
302GET_SUBTARGETINFO_MACRO(HasFmaMixInsts, false, hasFmaMixInsts)
303GET_SUBTARGETINFO_MACRO(HasFmacF64Inst, false, hasFmacF64Inst)
304GET_SUBTARGETINFO_MACRO(HasForceStoreSC0SC1, false, hasForceStoreSC0SC1)
305GET_SUBTARGETINFO_MACRO(HasG16, false, hasG16)
306GET_SUBTARGETINFO_MACRO(HasGDS, false, hasGDS)
307GET_SUBTARGETINFO_MACRO(HasGWS, false, hasGWS)
308GET_SUBTARGETINFO_MACRO(HasGetWaveIdInst, false, hasGetWaveIdInst)
309GET_SUBTARGETINFO_MACRO(HasImageGather4D16Bug, false, hasImageGather4D16Bug)
310GET_SUBTARGETINFO_MACRO(HasImageInsts, false, hasImageInsts)
311GET_SUBTARGETINFO_MACRO(HasImageStoreD16Bug, false, hasImageStoreD16Bug)
312GET_SUBTARGETINFO_MACRO(HasInstFwdPrefetchBug, false, hasInstFwdPrefetchBug)
313GET_SUBTARGETINFO_MACRO(HasIntClamp, false, hasIntClamp)
314GET_SUBTARGETINFO_MACRO(HasInv2PiInlineImm, false, hasInv2PiInlineImm)
315GET_SUBTARGETINFO_MACRO(HasLdsBranchVmemWARHazard, false, hasLdsBranchVmemWARHazard)
316GET_SUBTARGETINFO_MACRO(HasMADIntraFwdBug, false, hasMADIntraFwdBug)
317GET_SUBTARGETINFO_MACRO(HasMAIInsts, false, hasMAIInsts)
318GET_SUBTARGETINFO_MACRO(HasMFMAInlineLiteralBug, false, hasMFMAInlineLiteralBug)
319GET_SUBTARGETINFO_MACRO(HasMSAALoadDstSelBug, false, hasMSAALoadDstSelBug)
320GET_SUBTARGETINFO_MACRO(HasMadMacF32Insts, false, hasMadMacF32Insts)
321GET_SUBTARGETINFO_MACRO(HasMadMixInsts, false, hasMadMixInsts)
322GET_SUBTARGETINFO_MACRO(HasMemoryAtomicFaddF32DenormalSupport, false, hasMemoryAtomicFaddF32DenormalSupport)
323GET_SUBTARGETINFO_MACRO(HasMovrel, false, hasMovrel)
324GET_SUBTARGETINFO_MACRO(HasNSAClauseBug, false, hasNSAClauseBug)
325GET_SUBTARGETINFO_MACRO(HasNSAEncoding, false, hasNSAEncoding)
326GET_SUBTARGETINFO_MACRO(HasNSAtoVMEMBug, false, hasNSAtoVMEMBug)
327GET_SUBTARGETINFO_MACRO(HasNoDataDepHazard, false, hasNoDataDepHazard)
328GET_SUBTARGETINFO_MACRO(HasNoSdstCMPX, false, hasNoSdstCMPX)
329GET_SUBTARGETINFO_MACRO(HasOffset3fBug, false, hasOffset3fBug)
330GET_SUBTARGETINFO_MACRO(HasPackedFP32Ops, false, hasPackedFP32Ops)
331GET_SUBTARGETINFO_MACRO(HasPackedTID, false, hasPackedTID)
332GET_SUBTARGETINFO_MACRO(HasPartialNSAEncoding, false, hasPartialNSAEncoding)
333GET_SUBTARGETINFO_MACRO(HasPkFmacF16Inst, false, hasPkFmacF16Inst)
334GET_SUBTARGETINFO_MACRO(HasPrivEnabledTrap2NopBug, false, hasPrivEnabledTrap2NopBug)
335GET_SUBTARGETINFO_MACRO(HasPseudoScalarTrans, false, hasPseudoScalarTrans)
336GET_SUBTARGETINFO_MACRO(HasR128A16, false, hasR128A16)
337GET_SUBTARGETINFO_MACRO(HasRequiredExportPriority, false, hasRequiredExportPriority)
338GET_SUBTARGETINFO_MACRO(HasRestrictedSOffset, false, hasRestrictedSOffset)
339GET_SUBTARGETINFO_MACRO(HasSALUFloatInsts, false, hasSALUFloatInsts)
340GET_SUBTARGETINFO_MACRO(HasSDWA, false, hasSDWA)
341GET_SUBTARGETINFO_MACRO(HasSDWAMac, false, hasSDWAMac)
342GET_SUBTARGETINFO_MACRO(HasSDWAOmod, false, hasSDWAOmod)
343GET_SUBTARGETINFO_MACRO(HasSDWAOutModsVOPC, false, hasSDWAOutModsVOPC)
344GET_SUBTARGETINFO_MACRO(HasSDWAScalar, false, hasSDWAScalar)
345GET_SUBTARGETINFO_MACRO(HasSDWASdst, false, hasSDWASdst)
346GET_SUBTARGETINFO_MACRO(HasSMEMtoVectorWriteHazard, false, hasSMEMtoVectorWriteHazard)
347GET_SUBTARGETINFO_MACRO(HasSMemRealTime, false, hasSMemRealTime)
348GET_SUBTARGETINFO_MACRO(HasSMemTimeInst, false, hasSMemTimeInst)
349GET_SUBTARGETINFO_MACRO(HasScalarAtomics, false, hasScalarAtomics)
350GET_SUBTARGETINFO_MACRO(HasScalarDwordx3Loads, false, hasScalarDwordx3Loads)
351GET_SUBTARGETINFO_MACRO(HasScalarStores, false, hasScalarStores)
352GET_SUBTARGETINFO_MACRO(HasShaderCyclesHiLoRegisters, false, hasShaderCyclesHiLoRegisters)
353GET_SUBTARGETINFO_MACRO(HasShaderCyclesRegister, false, hasShaderCyclesRegister)
354GET_SUBTARGETINFO_MACRO(HasTrigReducedRange, false, hasTrigReducedRange)
355GET_SUBTARGETINFO_MACRO(HasTrue16BitInsts, false, hasTrue16BitInsts)
356GET_SUBTARGETINFO_MACRO(HasUnpackedD16VMem, false, hasUnpackedD16VMem)
357GET_SUBTARGETINFO_MACRO(HasVALUTransUseHazard, false, hasVALUTransUseHazard)
358GET_SUBTARGETINFO_MACRO(HasVGPRIndexMode, false, hasVGPRIndexMode)
359GET_SUBTARGETINFO_MACRO(HasVGPRSingleUseHintInsts, false, hasVGPRSingleUseHintInsts)
360GET_SUBTARGETINFO_MACRO(HasVMEMtoScalarWriteHazard, false, hasVMEMtoScalarWriteHazard)
361GET_SUBTARGETINFO_MACRO(HasVOP3Literal, false, hasVOP3Literal)
362GET_SUBTARGETINFO_MACRO(HasVOP3PInsts, false, hasVOP3PInsts)
363GET_SUBTARGETINFO_MACRO(HasVOPDInsts, false, hasVOPDInsts)
364GET_SUBTARGETINFO_MACRO(HasVcmpxExecWARHazard, false, hasVcmpxExecWARHazard)
365GET_SUBTARGETINFO_MACRO(HasVcmpxPermlaneHazard, false, hasVcmpxPermlaneHazard)
366GET_SUBTARGETINFO_MACRO(HasVmemWriteVgprInOrder, false, hasVmemWriteVgprInOrder)
367GET_SUBTARGETINFO_MACRO(HasVscnt, false, hasVscnt)
368GET_SUBTARGETINFO_MACRO(KernargPreload, false, kernargPreload)
369GET_SUBTARGETINFO_MACRO(LDSMisalignedBug, false, lDSMisalignedBug)
370GET_SUBTARGETINFO_MACRO(MIMG_R128, false, mIMG_R128)
371GET_SUBTARGETINFO_MACRO(NegativeScratchOffsetBug, false, negativeScratchOffsetBug)
372GET_SUBTARGETINFO_MACRO(NegativeUnalignedScratchOffsetBug, false, negativeUnalignedScratchOffsetBug)
373GET_SUBTARGETINFO_MACRO(RequiresCOV6, false, requiresCOV6)
374GET_SUBTARGETINFO_MACRO(SGPRInitBug, false, sGPRInitBug)
375GET_SUBTARGETINFO_MACRO(ScalarFlatScratchInsts, false, scalarFlatScratchInsts)
376GET_SUBTARGETINFO_MACRO(SupportsSRAMECC, false, supportsSRAMECC)
377GET_SUBTARGETINFO_MACRO(SupportsXNACK, false, supportsXNACK)
378GET_SUBTARGETINFO_MACRO(TrapHandler, false, trapHandler)
379GET_SUBTARGETINFO_MACRO(UnalignedAccessMode, false, unalignedAccessMode)
380GET_SUBTARGETINFO_MACRO(UnalignedBufferAccess, false, unalignedBufferAccess)
381GET_SUBTARGETINFO_MACRO(UnalignedDSAccess, false, unalignedDSAccess)
382GET_SUBTARGETINFO_MACRO(UnalignedScratchAccess, false, unalignedScratchAccess)
383GET_SUBTARGETINFO_MACRO(UserSGPRInit16Bug, false, userSGPRInit16Bug)
384#undef GET_SUBTARGETINFO_MACRO
385#endif // GET_SUBTARGETINFO_MACRO
386
387
388#ifdef GET_SUBTARGETINFO_MC_DESC
389#undef GET_SUBTARGETINFO_MC_DESC
390
391namespace llvm {
392// Sorted (by key) array of values for CPU features.
393extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[] = {
394 { "16-bit-insts", "Has i16/f16 instructions", AMDGPU::Feature16BitInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
395 { "DumpCode", "Dump MachineInstrs in the CodeEmitter", AMDGPU::FeatureDumpCode, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
396 { "a16", "Support A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands", AMDGPU::FeatureA16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
397 { "add-no-carry-insts", "Have VALU add/sub instructions without carry out", AMDGPU::FeatureAddNoCarryInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
398 { "agent-scope-fine-grained-remote-memory-atomics", "Agent (device) scoped atomic operations, excluding those directly supported by PCIe (i.e. integer atomic add, exchange, and compare-and-swap), are functional for allocations in host or peer device memory.", AMDGPU::FeatureAgentScopeFineGrainedRemoteMemoryAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
399 { "allocate1_5xvgprs", "Has 50% more physical VGPRs and 50% larger allocation granule", AMDGPU::Feature1_5xVGPRs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
400 { "aperture-regs", "Has Memory Aperture Base and Size Registers", AMDGPU::FeatureApertureRegs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
401 { "architected-flat-scratch", "Flat Scratch register is a readonly SPI initialized architected register", AMDGPU::FeatureArchitectedFlatScratch, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
402 { "architected-sgprs", "Enable the architected SGPRs", AMDGPU::FeatureArchitectedSGPRs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
403 { "atomic-buffer-global-pk-add-f16-insts", "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that can return original value", AMDGPU::FeatureAtomicBufferGlobalPkAddF16Insts, { { { 0x0ULL, 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
404 { "atomic-buffer-global-pk-add-f16-no-rtn-insts", "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that don't return original value", AMDGPU::FeatureAtomicBufferGlobalPkAddF16NoRtnInsts, { { { 0x0ULL, 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
405 { "atomic-buffer-pk-add-bf16-inst", "Has buffer_atomic_pk_add_bf16 instruction", AMDGPU::FeatureAtomicBufferPkAddBF16Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
406 { "atomic-csub-no-rtn-insts", "Has buffer_atomic_csub and global_atomic_csub instructions that don't return original value", AMDGPU::FeatureAtomicCSubNoRtnInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
407 { "atomic-ds-pk-add-16-insts", "Has ds_pk_add_bf16, ds_pk_add_f16, ds_pk_add_rtn_bf16, ds_pk_add_rtn_f16 instructions", AMDGPU::FeatureAtomicDsPkAdd16Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
408 { "atomic-fadd-no-rtn-insts", "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that don't return original value", AMDGPU::FeatureAtomicFaddNoRtnInsts, { { { 0x0ULL, 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
409 { "atomic-fadd-rtn-insts", "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that return original value", AMDGPU::FeatureAtomicFaddRtnInsts, { { { 0x0ULL, 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
410 { "atomic-flat-pk-add-16-insts", "Has flat_atomic_pk_add_f16 and flat_atomic_pk_add_bf16 instructions", AMDGPU::FeatureAtomicFlatPkAdd16Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
411 { "atomic-fmin-fmax-flat-f32", "Has flat memory instructions for atomicrmw fmin/fmax for float", AMDGPU::FeatureAtomicFMinFMaxF32FlatInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
412 { "atomic-fmin-fmax-flat-f64", "Has flat memory instructions for atomicrmw fmin/fmax for double", AMDGPU::FeatureAtomicFMinFMaxF64FlatInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
413 { "atomic-fmin-fmax-global-f32", "Has global/buffer instructions for atomicrmw fmin/fmax for float", AMDGPU::FeatureAtomicFMinFMaxF32GlobalInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
414 { "atomic-fmin-fmax-global-f64", "Has global/buffer instructions for atomicrmw fmin/fmax for float", AMDGPU::FeatureAtomicFMinFMaxF64GlobalInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
415 { "atomic-global-pk-add-bf16-inst", "Has global_atomic_pk_add_bf16 instruction", AMDGPU::FeatureAtomicGlobalPkAddBF16Inst, { { { 0x0ULL, 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
416 { "auto-waitcnt-before-barrier", "Hardware automatically inserts waitcnt before barrier", AMDGPU::FeatureAutoWaitcntBeforeBarrier, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
417 { "back-off-barrier", "Hardware supports backing off s_barrier if an exception occurs", AMDGPU::FeatureBackOffBarrier, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
418 { "ci-insts", "Additional instructions for CI+", AMDGPU::FeatureCIInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
419 { "cumode", "Enable CU wavefront execution mode", AMDGPU::FeatureCuMode, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
420 { "default-component-broadcast", "BUFFER/IMAGE store instructions set unspecified components to x component (GFX12)", AMDGPU::FeatureDefaultComponentBroadcast, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
421 { "default-component-zero", "BUFFER/IMAGE store instructions set unspecified components to zero (before GFX12)", AMDGPU::FeatureDefaultComponentZero, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
422 { "dl-insts", "Has v_fmac_f32 and v_xnor_b32 instructions", AMDGPU::FeatureDLInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
423 { "dot1-insts", "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions", AMDGPU::FeatureDot1Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
424 { "dot10-insts", "Has v_dot2_f32_f16 instruction", AMDGPU::FeatureDot10Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
425 { "dot11-insts", "Has v_dot4_f32_fp8_fp8, v_dot4_f32_fp8_bf8, v_dot4_f32_bf8_fp8, v_dot4_f32_bf8_bf8 instructions", AMDGPU::FeatureDot11Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
426 { "dot2-insts", "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions", AMDGPU::FeatureDot2Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
427 { "dot3-insts", "Has v_dot8c_i32_i4 instruction", AMDGPU::FeatureDot3Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
428 { "dot4-insts", "Has v_dot2c_i32_i16 instruction", AMDGPU::FeatureDot4Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
429 { "dot5-insts", "Has v_dot2c_f32_f16 instruction", AMDGPU::FeatureDot5Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
430 { "dot6-insts", "Has v_dot4c_i32_i8 instruction", AMDGPU::FeatureDot6Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
431 { "dot7-insts", "Has v_dot4_u32_u8, v_dot8_u32_u4 instructions", AMDGPU::FeatureDot7Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
432 { "dot8-insts", "Has v_dot4_i32_iu8, v_dot8_i32_iu4 instructions", AMDGPU::FeatureDot8Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
433 { "dot9-insts", "Has v_dot2_f16_f16, v_dot2_bf16_bf16, v_dot2_f32_bf16 instructions", AMDGPU::FeatureDot9Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
434 { "dpp", "Support DPP (Data Parallel Primitives) extension", AMDGPU::FeatureDPP, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
435 { "dpp-64bit", "Support DPP (Data Parallel Primitives) extension in DP ALU", AMDGPU::FeatureDPALU_DPP, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
436 { "dpp-src1-sgpr", "Support SGPR for Src1 of DPP instructions", AMDGPU::FeatureDPPSrc1SGPR, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
437 { "dpp8", "Support DPP8 (Data Parallel Primitives) extension", AMDGPU::FeatureDPP8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
438 { "ds-src2-insts", "Has ds_*_src2 instructions", AMDGPU::FeatureDsSrc2Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
439 { "dumpcode", "Dump MachineInstrs in the CodeEmitter", AMDGPU::FeatureDumpCodeLower, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
440 { "enable-ds128", "Use ds_{read|write}_b128", AMDGPU::FeatureEnableDS128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
441 { "enable-flat-scratch", "Use scratch_* flat memory instructions to access scratch", AMDGPU::FeatureEnableFlatScratch, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
442 { "enable-prt-strict-null", "Enable zeroing of result registers for sparse texture fetches", AMDGPU::FeatureEnablePRTStrictNull, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
443 { "extended-image-insts", "Support mips != 0, lod != 0, gather4, and get_lod", AMDGPU::FeatureExtendedImageInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
444 { "fast-denormal-f32", "Enabling denormals does not cause f32 instructions to run at f64 rates", AMDGPU::FeatureFastDenormalF32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
445 { "fast-fmaf", "Assuming f32 fma is at least as fast as mul + add", AMDGPU::FeatureFastFMAF32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
446 { "flat-address-space", "Support flat address space", AMDGPU::FeatureFlatAddressSpace, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
447 { "flat-atomic-fadd-f32-inst", "Has flat_atomic_add_f32 instruction", AMDGPU::FeatureFlatAtomicFaddF32Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
448 { "flat-buffer-global-fadd-f64-inst", "Has flat, buffer, and global instructions for f64 atomic fadd", AMDGPU::FeatureFlatBufferGlobalAtomicFaddF64Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
449 { "flat-for-global", "Force to generate flat instruction for global", AMDGPU::FeatureFlatForGlobal, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
450 { "flat-global-insts", "Have global_* flat memory instructions", AMDGPU::FeatureFlatGlobalInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
451 { "flat-inst-offsets", "Flat instructions have immediate offset addressing mode", AMDGPU::FeatureFlatInstOffsets, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
452 { "flat-scratch-insts", "Have scratch_* flat memory instructions", AMDGPU::FeatureFlatScratchInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
453 { "flat-segment-offset-bug", "GFX10 bug where inst_offset is ignored when flat instructions access global memory", AMDGPU::FeatureFlatSegmentOffsetBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
454 { "fma-mix-insts", "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions", AMDGPU::FeatureFmaMixInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
455 { "fmacf64-inst", "Has v_fmac_f64 instruction", AMDGPU::FeatureFmacF64Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
456 { "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", AMDGPU::FeatureFMA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
457 { "force-store-sc0-sc1", "Has SC0 and SC1 on stores", AMDGPU::FeatureForceStoreSC0SC1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
458 { "fp64", "Enable double precision operations", AMDGPU::FeatureFP64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
459 { "fp8-conversion-insts", "Has fp8 and bf8 conversion instructions", AMDGPU::FeatureFP8ConversionInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
460 { "fp8-insts", "Has fp8 and bf8 instructions", AMDGPU::FeatureFP8Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
461 { "full-rate-64-ops", "Most fp64 instructions are full rate", AMDGPU::FullRate64Ops, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
462 { "g16", "Support G16 for 16-bit gradient image operands", AMDGPU::FeatureG16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
463 { "gcn3-encoding", "Encoding format for VI", AMDGPU::FeatureGCN3Encoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
464 { "gds", "Has Global Data Share", AMDGPU::FeatureGDS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
465 { "get-wave-id-inst", "Has s_get_waveid_in_workgroup instruction", AMDGPU::FeatureGetWaveIdInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
466 { "gfx10", "GFX10 GPU generation", AMDGPU::FeatureGFX10, { { { 0x1e2000009881e02eULL, 0x304211032200aa97ULL, 0x5180c000335004ULL, 0x0ULL, 0x0ULL, } } } },
467 { "gfx10-3-insts", "Additional instructions for GFX10.3", AMDGPU::FeatureGFX10_3Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
468 { "gfx10-insts", "Additional instructions for GFX10+", AMDGPU::FeatureGFX10Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
469 { "gfx10_a-encoding", "Has BVH ray tracing instructions", AMDGPU::FeatureGFX10_AEncoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
470 { "gfx10_b-encoding", "Encoding format GFX10_B", AMDGPU::FeatureGFX10_BEncoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
471 { "gfx11", "GFX11 GPU generation", AMDGPU::FeatureGFX11, { { { 0x1e2000009880602eULL, 0x304111030217aa97ULL, 0x5380d000000004ULL, 0x0ULL, 0x0ULL, } } } },
472 { "gfx11-insts", "Additional instructions for GFX11+", AMDGPU::FeatureGFX11Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
473 { "gfx12", "GFX12 GPU generation", AMDGPU::FeatureGFX12, { { { 0x1e0000005880603eULL, 0x304111030057a897ULL, 0x4380d000000004ULL, 0x0ULL, 0x0ULL, } } } },
474 { "gfx12-insts", "Additional instructions for GFX12+", AMDGPU::FeatureGFX12Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
475 { "gfx7-gfx8-gfx9-insts", "Instructions shared in GFX7, GFX8, GFX9", AMDGPU::FeatureGFX7GFX8GFX9Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
476 { "gfx8-insts", "Additional instructions for GFX8+", AMDGPU::FeatureGFX8Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
477 { "gfx9", "GFX9 GPU generation", AMDGPU::FeatureGFX9, { { { 0x1e0000008880002eULL, 0x400010302002d07ULL, 0x21110c106b35080ULL, 0x0ULL, 0x0ULL, } } } },
478 { "gfx9-insts", "Additional instructions for GFX9+", AMDGPU::FeatureGFX9Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
479 { "gfx90a-insts", "Additional instructions for GFX90A+", AMDGPU::FeatureGFX90AInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
480 { "gfx940-insts", "Additional instructions for GFX940+", AMDGPU::FeatureGFX940Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
481 { "gws", "Has Global Wave Sync", AMDGPU::FeatureGWS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
482 { "half-rate-64-ops", "Most fp64 instructions are half rate instead of quarter", AMDGPU::HalfRate64Ops, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
483 { "image-gather4-d16-bug", "Image Gather4 D16 hardware bug", AMDGPU::FeatureImageGather4D16Bug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
484 { "image-insts", "Support image instructions", AMDGPU::FeatureImageInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
485 { "image-store-d16-bug", "Image Store D16 hardware bug", AMDGPU::FeatureImageStoreD16Bug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
486 { "inst-fwd-prefetch-bug", "S_INST_PREFETCH instruction causes shader to hang", AMDGPU::FeatureInstFwdPrefetchBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
487 { "int-clamp-insts", "Support clamp for integer destination", AMDGPU::FeatureIntClamp, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
488 { "inv-2pi-inline-imm", "Has 1 / (2 * pi) as inline immediate", AMDGPU::FeatureInv2PiInlineImm, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
489 { "kernarg-preload", "Hardware supports preloading of kernel arguments in user SGPRs.", AMDGPU::FeatureKernargPreload, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
490 { "lds-branch-vmem-war-hazard", "Switching between LDS and VMEM-tex not waiting VM_VSRC=0", AMDGPU::FeatureLdsBranchVmemWARHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
491 { "lds-misaligned-bug", "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode", AMDGPU::FeatureLdsMisalignedBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
492 { "ldsbankcount16", "The number of LDS banks per compute unit.", AMDGPU::FeatureLDSBankCount16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
493 { "ldsbankcount32", "The number of LDS banks per compute unit.", AMDGPU::FeatureLDSBankCount32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
494 { "load-store-opt", "Enable SI load/store optimizer pass", AMDGPU::FeatureEnableLoadStoreOpt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
495 { "localmemorysize32768", "The size of local memory in bytes", AMDGPU::FeatureLocalMemorySize32768, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
496 { "localmemorysize65536", "The size of local memory in bytes", AMDGPU::FeatureLocalMemorySize65536, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
497 { "mad-intra-fwd-bug", "MAD_U64/I64 intra instruction forwarding bug", AMDGPU::FeatureMADIntraFwdBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
498 { "mad-mac-f32-insts", "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions", AMDGPU::FeatureMadMacF32Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
499 { "mad-mix-insts", "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions", AMDGPU::FeatureMadMixInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
500 { "mai-insts", "Has mAI instructions", AMDGPU::FeatureMAIInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
501 { "max-hard-clause-length-32", "Maximum number of instructions in an explicit S_CLAUSE is 32", AMDGPU::FeatureMaxHardClauseLength32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
502 { "max-hard-clause-length-63", "Maximum number of instructions in an explicit S_CLAUSE is 63", AMDGPU::FeatureMaxHardClauseLength63, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
503 { "max-private-element-size-16", "Maximum private access size may be 16", AMDGPU::FeatureMaxPrivateElementSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
504 { "max-private-element-size-4", "Maximum private access size may be 4", AMDGPU::FeatureMaxPrivateElementSize4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
505 { "max-private-element-size-8", "Maximum private access size may be 8", AMDGPU::FeatureMaxPrivateElementSize8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
506 { "memory-atomic-fadd-f32-denormal-support", "global/flat/buffer atomic fadd for float supports denormal handling", AMDGPU::FeatureMemoryAtomicFAddF32DenormalSupport, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
507 { "mfma-inline-literal-bug", "MFMA cannot use inline literal as SrcC", AMDGPU::FeatureMFMAInlineLiteralBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
508 { "mimg-r128", "Support 128-bit texture resources", AMDGPU::FeatureMIMG_R128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
509 { "movrel", "Has v_movrel*_b32 instructions", AMDGPU::FeatureMovrel, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
510 { "msaa-load-dst-sel-bug", "MSAA loads not honoring dst_sel bug", AMDGPU::FeatureMSAALoadDstSelBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
511 { "negative-scratch-offset-bug", "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9", AMDGPU::FeatureNegativeScratchOffsetBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
512 { "negative-unaligned-scratch-offset-bug", "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10", AMDGPU::FeatureNegativeUnalignedScratchOffsetBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
513 { "no-data-dep-hazard", "Does not need SW waitstates", AMDGPU::FeatureNoDataDepHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
514 { "no-sdst-cmpx", "V_CMPX does not write VCC/SGPR in addition to EXEC", AMDGPU::FeatureNoSdstCMPX, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
515 { "nsa-clause-bug", "MIMG-NSA in a hard clause has unpredictable results on GFX10.1", AMDGPU::FeatureNSAClauseBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
516 { "nsa-encoding", "Support NSA encoding for image instructions", AMDGPU::FeatureNSAEncoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
517 { "nsa-to-vmem-bug", "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero", AMDGPU::FeatureNSAtoVMEMBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
518 { "offset-3f-bug", "Branch offset of 3f hardware bug", AMDGPU::FeatureOffset3fBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
519 { "packed-fp32-ops", "Support packed fp32 instructions", AMDGPU::FeaturePackedFP32Ops, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
520 { "packed-tid", "Workitem IDs are packed into v0 at kernel launch", AMDGPU::FeaturePackedTID, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
521 { "partial-nsa-encoding", "Support partial NSA encoding for image instructions", AMDGPU::FeaturePartialNSAEncoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
522 { "pk-fmac-f16-inst", "Has v_pk_fmac_f16 instruction", AMDGPU::FeaturePkFmacF16Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
523 { "precise-memory", "Enable precise memory mode", AMDGPU::FeaturePreciseMemory, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
524 { "priv-enabled-trap2-nop-bug", "Hardware that runs with PRIV=1 interpreting 's_trap 2' as a nop bug", AMDGPU::FeaturePrivEnabledTrap2NopBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
525 { "promote-alloca", "Enable promote alloca pass", AMDGPU::FeaturePromoteAlloca, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
526 { "pseudo-scalar-trans", "Has Pseudo Scalar Transcendental instructions", AMDGPU::FeaturePseudoScalarTrans, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
527 { "r128-a16", "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128", AMDGPU::FeatureR128A16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
528 { "real-true16", "Use true 16-bit registers", AMDGPU::FeatureRealTrue16Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
529 { "required-export-priority", "Export priority must be explicitly manipulated on GFX11.5", AMDGPU::FeatureRequiredExportPriority, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
530 { "requires-cov6", "Target Requires Code Object V6", AMDGPU::FeatureRequiresCOV6, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
531 { "restricted-soffset", "Has restricted SOffset (immediate not supported).", AMDGPU::FeatureHasRestrictedSOffset, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
532 { "s-memrealtime", "Has s_memrealtime instruction", AMDGPU::FeatureSMemRealTime, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
533 { "s-memtime-inst", "Has s_memtime instruction", AMDGPU::FeatureSMemTimeInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
534 { "salu-float", "Has SALU floating point instructions", AMDGPU::FeatureSALUFloatInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
535 { "scalar-atomics", "Has atomic scalar memory instructions", AMDGPU::FeatureScalarAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
536 { "scalar-dwordx3-loads", "Has 96-bit scalar load instructions", AMDGPU::FeatureScalarDwordx3Loads, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
537 { "scalar-flat-scratch-insts", "Have s_scratch_* flat memory instructions", AMDGPU::FeatureScalarFlatScratchInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
538 { "scalar-stores", "Has store scalar memory instructions", AMDGPU::FeatureScalarStores, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
539 { "sdwa", "Support SDWA (Sub-DWORD Addressing) extension", AMDGPU::FeatureSDWA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
540 { "sdwa-mav", "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension", AMDGPU::FeatureSDWAMac, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
541 { "sdwa-omod", "Support OMod with SDWA (Sub-DWORD Addressing) extension", AMDGPU::FeatureSDWAOmod, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
542 { "sdwa-out-mods-vopc", "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension", AMDGPU::FeatureSDWAOutModsVOPC, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
543 { "sdwa-scalar", "Support scalar register with SDWA (Sub-DWORD Addressing) extension", AMDGPU::FeatureSDWAScalar, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
544 { "sdwa-sdst", "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension", AMDGPU::FeatureSDWASdst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
545 { "sea-islands", "SEA_ISLANDS GPU generation", AMDGPU::FeatureSeaIslands, { { { 0x122010008081e000ULL, 0x40510022000600ULL, 0x210004800200000ULL, 0x0ULL, 0x0ULL, } } } },
546 { "sgpr-init-bug", "VI SGPR initialization bug requiring a fixed SGPR allocation size", AMDGPU::FeatureSGPRInitBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
547 { "shader-cycles-hi-lo-registers", "Has SHADER_CYCLES_HI/LO hardware registers", AMDGPU::FeatureShaderCyclesHiLoRegisters, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
548 { "shader-cycles-register", "Has SHADER_CYCLES hardware register", AMDGPU::FeatureShaderCyclesRegister, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
549 { "si-scheduler", "Enable SI Machine Scheduler", AMDGPU::FeatureEnableSIScheduler, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
550 { "smem-to-vector-write-hazard", "s_load_dword followed by v_cmp page faults", AMDGPU::FeatureSMEMtoVectorWriteHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
551 { "southern-islands", "SOUTHERN_ISLANDS GPU generation", AMDGPU::FeatureSouthernIslands, { { { 0x220100080014000ULL, 0x40509022000200ULL, 0x210000800200000ULL, 0x0ULL, 0x0ULL, } } } },
552 { "sramecc", "Enable SRAMECC", AMDGPU::FeatureSRAMECC, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
553 { "sramecc-support", "Hardware supports SRAMECC", AMDGPU::FeatureSupportsSRAMECC, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
554 { "tgsplit", "Enable threadgroup split execution", AMDGPU::FeatureTgSplit, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
555 { "trap-handler", "Trap handler support", AMDGPU::FeatureTrapHandler, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
556 { "trig-reduced-range", "Requires use of fract on arguments to trig instructions", AMDGPU::FeatureTrigReducedRange, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
557 { "true16", "True 16-bit operand instructions", AMDGPU::FeatureTrue16BitInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
558 { "unaligned-access-mode", "Enable unaligned global, local and region loads and stores if the hardware supports it", AMDGPU::FeatureUnalignedAccessMode, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
559 { "unaligned-buffer-access", "Hardware supports unaligned global loads and stores", AMDGPU::FeatureUnalignedBufferAccess, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
560 { "unaligned-ds-access", "Hardware supports unaligned local and region loads and stores", AMDGPU::FeatureUnalignedDSAccess, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
561 { "unaligned-scratch-access", "Support unaligned scratch loads and stores", AMDGPU::FeatureUnalignedScratchAccess, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
562 { "unpacked-d16-vmem", "Has unpacked d16 vmem instructions", AMDGPU::FeatureUnpackedD16VMem, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
563 { "unsafe-ds-offset-folding", "Force using DS instruction immediate offsets on SI", AMDGPU::FeatureEnableUnsafeDSOffsetFolding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
564 { "user-sgpr-init16-bug", "Bug requiring at least 16 user+system SGPRs to be enabled", AMDGPU::FeatureUserSGPRInit16Bug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
565 { "valu-trans-use-hazard", "Hazard when TRANS instructions are closely followed by a use of the result", AMDGPU::FeatureVALUTransUseHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
566 { "vcmpx-exec-war-hazard", "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)", AMDGPU::FeatureVcmpxExecWARHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
567 { "vcmpx-permlane-hazard", "TODO: describe me", AMDGPU::FeatureVcmpxPermlaneHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
568 { "vgpr-index-mode", "Has VGPR mode register indexing", AMDGPU::FeatureVGPRIndexMode, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
569 { "vgpr-singleuse-hint", "Has single-use VGPR hint instructions", AMDGPU::FeatureVGPRSingleUseHintInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
570 { "vmem-to-scalar-write-hazard", "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.", AMDGPU::FeatureVMEMtoScalarWriteHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
571 { "vmem-write-vgpr-in-order", "VMEM instructions of the same type write VGPR results in order", AMDGPU::FeatureVmemWriteVgprInOrder, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
572 { "volcanic-islands", "VOLCANIC_ISLANDS GPU generation", AMDGPU::FeatureVolcanicIslands, { { { 0x1620100088800002ULL, 0x40510322000f00ULL, 0x21010480430b000ULL, 0x0ULL, 0x0ULL, } } } },
573 { "vop3-literal", "Can use one literal in VOP3", AMDGPU::FeatureVOP3Literal, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
574 { "vop3p", "Has VOP3P packed instructions", AMDGPU::FeatureVOP3P, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
575 { "vopd", "Has VOPD dual issue wave32 instructions", AMDGPU::FeatureVOPD, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
576 { "vscnt", "Has separate store vscnt counter", AMDGPU::FeatureVscnt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
577 { "wavefrontsize16", "The number of threads per wavefront", AMDGPU::FeatureWavefrontSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
578 { "wavefrontsize32", "The number of threads per wavefront", AMDGPU::FeatureWavefrontSize32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
579 { "wavefrontsize64", "The number of threads per wavefront", AMDGPU::FeatureWavefrontSize64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
580 { "xnack", "Enable XNACK support", AMDGPU::FeatureXNACK, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
581 { "xnack-support", "Hardware supports XNACK", AMDGPU::FeatureSupportsXNACK, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
582};
583
584#ifdef DBGFIELD
585#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
586#endif
587#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
588#define DBGFIELD(x) x,
589#else
590#define DBGFIELD(x)
591#endif
592
593// ===============================================================
594// Data tables for the new per-operand machine model.
595
596// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
597extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[] = {
598 { 0, 0, 0 }, // Invalid
599 { 4, 1, 0}, // #1
600 { 5, 1, 0}, // #2
601 { 6, 1, 0}, // #3
602 { 3, 1, 0}, // #4
603 { 3, 2, 0}, // #5
604 { 2, 1, 0}, // #6
605 { 3, 1, 0}, // #7
606 { 6, 1, 0}, // #8
607 { 1, 1, 0}, // #9
608 { 5, 2, 0}, // #10
609 { 7, 2, 0}, // #11
610 { 7, 8, 0}, // #12
611 { 7, 16, 0}, // #13
612 { 4, 1, 0}, // #14
613 { 7, 1, 0}, // #15
614 { 4, 1, 0}, // #16
615 { 8, 1, 0}, // #17
616 { 3, 1, 0}, // #18
617 { 4, 1, 0}, // #19
618 { 3, 2, 0}, // #20
619 { 4, 2, 0}, // #21
620 { 2, 1, 0}, // #22
621 { 4, 1, 0}, // #23
622 { 3, 1, 0}, // #24
623 { 4, 2, 0}, // #25
624 { 8, 1, 0}, // #26
625 { 4, 2, 0}, // #27
626 { 5, 1, 0}, // #28
627 { 7, 1, 0}, // #29
628 { 4, 1, 0}, // #30
629 { 6, 1, 0}, // #31
630 { 4, 1, 0}, // #32
631 { 6, 1, 0}, // #33
632 { 7, 1, 0}, // #34
633 { 4, 2, 0}, // #35
634 { 7, 2, 0}, // #36
635 { 3, 1, 0}, // #37
636 { 4, 2, 0}, // #38
637 { 7, 1, 0}, // #39
638 { 4, 2, 0}, // #40
639 { 5, 1, 0}, // #41
640 { 6, 1, 0}, // #42
641 { 4, 2, 0}, // #43
642 { 6, 2, 0}, // #44
643 { 5, 4, 0}, // #45
644 { 5, 8, 0}, // #46
645 { 7, 4, 0} // #47
646}; // AMDGPUWriteProcResTable
647
648// {Cycles, WriteResourceID}
649extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[] = {
650 { 0, 0}, // Invalid
651 { 1, 0}, // #1 WriteSALU_Write32Bit_WriteFloatFMA_WriteDoubleAdd_Write64Bit_WriteDoubleCvt_WriteIntMul
652 {80, 0}, // #2 WriteVMEM
653 { 5, 0}, // #3 WriteLDS_WriteSMEM_Write32Bit_WriteFloatCvt_WriteFloatFMA
654 { 5, 0}, // #4 WriteLDS_Write32Bit
655 { 5, 0}, // #5 WriteLDS
656 { 4, 0}, // #6 WriteExport_WriteTrans32_WriteFloatCvt_WriteDoubleCvt_WriteQuarterRate32_WriteIntMul_WriteSFPU_WriteTrans64_Write4PassDGEMM_Write4PassMAI
657 { 8, 0}, // #7 WriteBranch_WriteDoubleAdd_Write8PassMAI_WriteQuarterRate32_WriteIntMul_Write8PassDGEMM
658 {500, 0}, // #8 WriteBarrier
659 { 1, 0}, // #9 WriteSALU
660 { 2, 0}, // #10 Write64Bit_Write2PassMAI_WriteSALU_WriteDoubleAdd
661 { 1, 0}, // #11 Write32Bit_WriteFloatFMA_WriteSALU_WriteDouble_WriteIntMul_Write64Bit
662 { 1, 0}, // #12 WriteSALU_Write32Bit_Write64Bit
663 {16, 0}, // #13 WriteFloatFMA_WriteDouble_WriteTrans64_Write16PassMAI_WriteExport
664 {16, 0}, // #14 WriteFloatFMA_WriteDouble
665 { 1, 0}, // #15 WriteSALU
666 { 4, 0}, // #16 WriteIntMul_WriteDouble
667 { 1, 0}, // #17 WriteSALU
668 { 2, 0}, // #18 Write64Bit
669 { 2, 0}, // #19 Write64Bit
670 {320, 0}, // #20 WriteVMEM
671 {20, 0}, // #21 WriteLDS_WriteSMEM
672 {20, 0}, // #22 WriteLDS
673 {20, 0}, // #23 WriteLDS
674 {32, 0}, // #24 WriteBranch
675 {2000, 0}, // #25 WriteBarrier
676 { 2, 0}, // #26 WriteSALU
677 { 6, 0}, // #27 Write64Bit
678 { 5, 0}, // #28 Write32Bit_WriteFloatFMA
679 { 2, 0}, // #29 WriteSALU
680 {22, 0}, // #30 WriteDoubleAdd_WriteDoubleCvt
681 {10, 0}, // #31 WriteTrans32
682 {22, 0}, // #32 WriteDouble
683 { 2, 0}, // #33 WriteSALU
684 { 8, 0}, // #34 WriteIntMul
685 { 2, 0}, // #35 WriteSALU
686 {24, 0}, // #36 WriteTrans64
687 { 6, 0}, // #37 Write64Bit
688 { 6, 0}, // #38 Write64Bit
689 {38, 0}, // #39 WriteDoubleAdd_WriteDoubleCvt
690 {38, 0}, // #40 WriteDouble
691 { 2, 0}, // #41 WriteSALU
692 {40, 0}, // #42 WriteTrans64
693 { 7, 0} // #43 WritePseudoScalarTrans
694}; // AMDGPUWriteLatencyTable
695
696// {UseIdx, WriteResourceID, Cycles}
697extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[] = {
698 {0, 0, 0}, // Invalid
699 {0, 0, -4}, // #1
700 {0, 0, -2} // #2
701}; // AMDGPUReadAdvanceTable
702
703// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
704static const llvm::MCSchedClassDesc SIQuarterSpeedModelSchedClasses[] = {
705 {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0},
706 {DBGFIELD("NullALU_WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #1
707 {DBGFIELD("NullALU_Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #2
708 {DBGFIELD("NullALU_WriteVMEM") 1, false, false, true, 3, 1, 2, 1, 0, 0}, // #3
709 {DBGFIELD("NullALU_WriteLDS") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #4
710 {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, true, 5, 1, 4, 2, 0, 0}, // #5
711 {DBGFIELD("NullALU_WriteExport") 1, false, false, true, 6, 1, 6, 1, 0, 0}, // #6
712 {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, true, 7, 2, 2, 2, 0, 0}, // #7
713 {DBGFIELD("WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #8
714 {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9
715 {DBGFIELD("NullALU_WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #10
716 {DBGFIELD("NullALU_WriteSFPU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #11
717 {DBGFIELD("NullALU_WriteSMEM") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #12
718 {DBGFIELD("NullALU_WriteBarrier") 1, false, false, true, 9, 1, 8, 1, 0, 0}, // #13
719 {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, true, 1, 2, 9, 2, 0, 0}, // #14
720 {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #15
721 {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, true, 2, 1, 7, 1, 0, 0}, // #16
722 {DBGFIELD("NullALU_Write64Bit") 1, false, false, true, 2, 1, 10, 1, 0, 0}, // #17
723 {DBGFIELD("NullALU_WriteTrans32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #18
724 {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #19
725 {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #20
726 {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, true, 2, 1, 13, 1, 0, 0}, // #21
727 {DBGFIELD("NullALU_WriteDouble") 1, false, false, true, 2, 1, 13, 1, 0, 0}, // #22
728 {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, true, 1, 2, 14, 2, 0, 0}, // #23
729 {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, true, 1, 2, 14, 2, 0, 0}, // #24
730 {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, true, 1, 2, 16, 2, 0, 0}, // #25
731 {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #26
732 {DBGFIELD("NullALU_WriteIntMul") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #27
733 {DBGFIELD("NullALU_WriteTrans64") 1, false, false, true, 2, 1, 13, 1, 0, 0}, // #28
734 {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, true, 10, 1, 18, 2, 0, 0}, // #29
735 {DBGFIELD("NullALU_WritePseudoScalarTrans") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #30
736 {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, true, 10, 1, 11, 2, 0, 0}, // #31
737 {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32
738 {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #33
739 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 11, 1, 10, 1, 1, 1}, // #34
740 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #35
741 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #36
742 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 11, 1, 10, 1, 1, 1}, // #37
743 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #38
744 {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #39
745 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #40
746 {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #41
747 {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #42
748 {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #43
749 {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #44
750 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #45
751 {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #46
752 {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #47
753 {DBGFIELD("Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #48
754 {DBGFIELD("Write64Bit") 1, false, false, true, 2, 1, 10, 1, 0, 0}, // #49
755 {DBGFIELD("WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #50
756 {DBGFIELD("Write64Bit_MIVGPRRead") 1, false, false, true, 2, 1, 10, 1, 2, 1}, // #51
757 {DBGFIELD("Write64Bit_ReadDefault") 1, false, false, true, 2, 1, 10, 1, 0, 0}, // #52
758}; // SIQuarterSpeedModelSchedClasses
759
760// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
761static const llvm::MCSchedClassDesc GFX10SpeedModelSchedClasses[] = {
762 {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0},
763 {DBGFIELD("NullALU_WriteSALU") 1, false, false, true, 1, 2, 10, 1, 0, 0}, // #1
764 {DBGFIELD("NullALU_Write32Bit") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #2
765 {DBGFIELD("NullALU_WriteVMEM") 1, false, false, true, 16, 2, 20, 1, 0, 0}, // #3
766 {DBGFIELD("NullALU_WriteLDS") 1, false, false, true, 18, 2, 21, 1, 0, 0}, // #4
767 {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, true, 20, 2, 22, 2, 0, 0}, // #5
768 {DBGFIELD("NullALU_WriteExport") 1, false, false, true, 22, 2, 13, 1, 0, 0}, // #6
769 {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, true, 24, 3, 20, 2, 0, 0}, // #7
770 {DBGFIELD("WriteBranch") 1, false, false, true, 9, 1, 24, 1, 0, 0}, // #8
771 {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9
772 {DBGFIELD("NullALU_WriteBranch") 1, false, false, true, 9, 1, 24, 1, 0, 0}, // #10
773 {DBGFIELD("NullALU_WriteSFPU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #11
774 {DBGFIELD("NullALU_WriteSMEM") 1, false, false, true, 18, 2, 21, 1, 0, 0}, // #12
775 {DBGFIELD("NullALU_WriteBarrier") 1, false, false, true, 9, 1, 25, 1, 0, 0}, // #13
776 {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, true, 27, 3, 26, 2, 0, 0}, // #14
777 {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, true, 27, 3, 28, 2, 0, 0}, // #15
778 {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, true, 14, 2, 30, 1, 0, 0}, // #16
779 {DBGFIELD("NullALU_Write64Bit") 1, false, false, true, 14, 2, 27, 1, 0, 0}, // #17
780 {DBGFIELD("NullALU_WriteTrans32") 1, false, false, true, 30, 2, 31, 1, 0, 0}, // #18
781 {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #19
782 {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, true, 14, 2, 30, 1, 0, 0}, // #20
783 {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #21
784 {DBGFIELD("NullALU_WriteDouble") 1, false, false, true, 14, 2, 30, 1, 0, 0}, // #22
785 {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, true, 27, 3, 28, 2, 0, 0}, // #23
786 {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, true, 27, 3, 32, 2, 0, 0}, // #24
787 {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, true, 27, 3, 34, 2, 0, 0}, // #25
788 {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, true, 14, 2, 7, 1, 0, 0}, // #26
789 {DBGFIELD("NullALU_WriteIntMul") 1, false, false, true, 14, 2, 7, 1, 0, 0}, // #27
790 {DBGFIELD("NullALU_WriteTrans64") 1, false, false, true, 32, 3, 36, 1, 0, 0}, // #28
791 {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, true, 35, 2, 37, 2, 0, 0}, // #29
792 {DBGFIELD("NullALU_WritePseudoScalarTrans") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #30
793 {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, true, 35, 2, 3, 2, 0, 0}, // #31
794 {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32
795 {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #33
796 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #34
797 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #35
798 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #36
799 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #37
800 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #38
801 {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #39
802 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #40
803 {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #41
804 {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #42
805 {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #43
806 {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #44
807 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #45
808 {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #46
809 {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #47
810 {DBGFIELD("Write32Bit") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #48
811 {DBGFIELD("Write64Bit") 1, false, false, true, 14, 2, 27, 1, 0, 0}, // #49
812 {DBGFIELD("WriteSALU") 1, false, false, true, 1, 2, 10, 1, 0, 0}, // #50
813 {DBGFIELD("Write64Bit_MIVGPRRead") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #51
814 {DBGFIELD("Write64Bit_ReadDefault") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #52
815}; // GFX10SpeedModelSchedClasses
816
817// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
818static const llvm::MCSchedClassDesc GFX11SpeedModelSchedClasses[] = {
819 {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0},
820 {DBGFIELD("NullALU_WriteSALU") 1, false, false, true, 1, 2, 10, 1, 0, 0}, // #1
821 {DBGFIELD("NullALU_Write32Bit") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #2
822 {DBGFIELD("NullALU_WriteVMEM") 1, false, false, true, 16, 2, 20, 1, 0, 0}, // #3
823 {DBGFIELD("NullALU_WriteLDS") 1, false, false, true, 18, 2, 21, 1, 0, 0}, // #4
824 {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, true, 20, 2, 21, 2, 0, 0}, // #5
825 {DBGFIELD("NullALU_WriteExport") 1, false, false, true, 22, 2, 13, 1, 0, 0}, // #6
826 {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, true, 24, 3, 20, 2, 0, 0}, // #7
827 {DBGFIELD("WriteBranch") 1, false, false, true, 9, 1, 24, 1, 0, 0}, // #8
828 {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9
829 {DBGFIELD("NullALU_WriteBranch") 1, false, false, true, 9, 1, 24, 1, 0, 0}, // #10
830 {DBGFIELD("NullALU_WriteSFPU") 1, false, false, true, 1, 2, 6, 1, 0, 0}, // #11
831 {DBGFIELD("NullALU_WriteSMEM") 1, false, false, true, 18, 2, 21, 1, 0, 0}, // #12
832 {DBGFIELD("NullALU_WriteBarrier") 1, false, false, true, 9, 1, 25, 1, 0, 0}, // #13
833 {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, true, 27, 3, 26, 2, 0, 0}, // #14
834 {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, true, 27, 3, 28, 2, 0, 0}, // #15
835 {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, true, 14, 2, 39, 1, 0, 0}, // #16
836 {DBGFIELD("NullALU_Write64Bit") 1, false, false, true, 14, 2, 27, 1, 0, 0}, // #17
837 {DBGFIELD("NullALU_WriteTrans32") 1, false, false, true, 30, 2, 31, 1, 0, 0}, // #18
838 {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #19
839 {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, true, 14, 2, 39, 1, 0, 0}, // #20
840 {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #21
841 {DBGFIELD("NullALU_WriteDouble") 1, false, false, true, 14, 2, 39, 1, 0, 0}, // #22
842 {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, true, 27, 3, 28, 2, 0, 0}, // #23
843 {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, true, 27, 3, 40, 2, 0, 0}, // #24
844 {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, true, 27, 3, 34, 2, 0, 0}, // #25
845 {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, true, 14, 2, 7, 1, 0, 0}, // #26
846 {DBGFIELD("NullALU_WriteIntMul") 1, false, false, true, 14, 2, 7, 1, 0, 0}, // #27
847 {DBGFIELD("NullALU_WriteTrans64") 1, false, false, true, 32, 3, 42, 1, 0, 0}, // #28
848 {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, true, 35, 2, 37, 2, 0, 0}, // #29
849 {DBGFIELD("NullALU_WritePseudoScalarTrans") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #30
850 {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, true, 35, 2, 3, 2, 0, 0}, // #31
851 {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32
852 {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #33
853 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #34
854 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #35
855 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #36
856 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #37
857 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #38
858 {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #39
859 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #40
860 {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #41
861 {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #42
862 {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #43
863 {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #44
864 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #45
865 {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #46
866 {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #47
867 {DBGFIELD("Write32Bit") 1, false, false, true, 14, 2, 3, 1, 0, 0}, // #48
868 {DBGFIELD("Write64Bit") 1, false, false, true, 14, 2, 27, 1, 0, 0}, // #49
869 {DBGFIELD("WriteSALU") 1, false, false, true, 1, 2, 10, 1, 0, 0}, // #50
870 {DBGFIELD("Write64Bit_MIVGPRRead") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #51
871 {DBGFIELD("Write64Bit_ReadDefault") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #52
872}; // GFX11SpeedModelSchedClasses
873
874// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
875static const llvm::MCSchedClassDesc GFX12SpeedModelSchedClasses[] = {
876 {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0},
877 {DBGFIELD("NullALU_WriteSALU") 1, false, false, false, 1, 2, 10, 1, 0, 0}, // #1
878 {DBGFIELD("NullALU_Write32Bit") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #2
879 {DBGFIELD("NullALU_WriteVMEM") 1, false, false, false, 14, 2, 20, 1, 0, 0}, // #3
880 {DBGFIELD("NullALU_WriteLDS") 1, false, false, false, 18, 2, 21, 1, 0, 0}, // #4
881 {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, false, 20, 2, 21, 2, 0, 0}, // #5
882 {DBGFIELD("NullALU_WriteExport") 1, false, false, false, 22, 2, 13, 1, 0, 0}, // #6
883 {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, false, 37, 3, 20, 2, 0, 0}, // #7
884 {DBGFIELD("WriteBranch") 1, false, false, false, 9, 1, 24, 1, 0, 0}, // #8
885 {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9
886 {DBGFIELD("NullALU_WriteBranch") 1, false, false, false, 9, 1, 24, 1, 0, 0}, // #10
887 {DBGFIELD("NullALU_WriteSFPU") 1, false, false, false, 1, 2, 6, 1, 0, 0}, // #11
888 {DBGFIELD("NullALU_WriteSMEM") 1, false, false, false, 18, 2, 21, 1, 0, 0}, // #12
889 {DBGFIELD("NullALU_WriteBarrier") 1, false, false, false, 9, 1, 25, 1, 0, 0}, // #13
890 {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, false, 40, 3, 26, 2, 0, 0}, // #14
891 {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, false, 40, 3, 28, 2, 0, 0}, // #15
892 {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, false, 30, 2, 39, 1, 0, 0}, // #16
893 {DBGFIELD("NullALU_Write64Bit") 1, false, false, false, 30, 2, 27, 1, 0, 0}, // #17
894 {DBGFIELD("NullALU_WriteTrans32") 1, false, false, false, 30, 2, 31, 1, 0, 0}, // #18
895 {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #19
896 {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, false, 30, 2, 39, 1, 0, 0}, // #20
897 {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #21
898 {DBGFIELD("NullALU_WriteDouble") 1, false, false, false, 30, 2, 39, 1, 0, 0}, // #22
899 {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, false, 40, 3, 28, 2, 0, 0}, // #23
900 {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, false, 40, 3, 40, 2, 0, 0}, // #24
901 {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, false, 40, 3, 34, 2, 0, 0}, // #25
902 {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, false, 30, 2, 7, 1, 0, 0}, // #26
903 {DBGFIELD("NullALU_WriteIntMul") 1, false, false, false, 30, 2, 7, 1, 0, 0}, // #27
904 {DBGFIELD("NullALU_WriteTrans64") 1, false, false, false, 30, 2, 42, 1, 0, 0}, // #28
905 {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, false, 43, 2, 37, 2, 0, 0}, // #29
906 {DBGFIELD("NullALU_WritePseudoScalarTrans") 1, false, false, false, 30, 2, 43, 1, 0, 0}, // #30
907 {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, false, 43, 2, 3, 2, 0, 0}, // #31
908 {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32
909 {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #33
910 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #34
911 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #35
912 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #36
913 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #37
914 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #38
915 {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #39
916 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #40
917 {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #41
918 {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #42
919 {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #43
920 {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #44
921 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #45
922 {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #46
923 {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #47
924 {DBGFIELD("Write32Bit") 1, false, false, false, 30, 2, 3, 1, 0, 0}, // #48
925 {DBGFIELD("Write64Bit") 1, false, false, false, 30, 2, 27, 1, 0, 0}, // #49
926 {DBGFIELD("WriteSALU") 1, false, false, false, 1, 2, 10, 1, 0, 0}, // #50
927 {DBGFIELD("Write64Bit_MIVGPRRead") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #51
928 {DBGFIELD("Write64Bit_ReadDefault") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #52
929}; // GFX12SpeedModelSchedClasses
930
931// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
932static const llvm::MCSchedClassDesc SIFullSpeedModelSchedClasses[] = {
933 {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0},
934 {DBGFIELD("NullALU_WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #1
935 {DBGFIELD("NullALU_Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #2
936 {DBGFIELD("NullALU_WriteVMEM") 1, false, false, true, 3, 1, 2, 1, 0, 0}, // #3
937 {DBGFIELD("NullALU_WriteLDS") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #4
938 {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, true, 5, 1, 3, 2, 0, 0}, // #5
939 {DBGFIELD("NullALU_WriteExport") 1, false, false, true, 6, 1, 6, 1, 0, 0}, // #6
940 {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, true, 7, 2, 2, 2, 0, 0}, // #7
941 {DBGFIELD("WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #8
942 {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9
943 {DBGFIELD("NullALU_WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #10
944 {DBGFIELD("NullALU_WriteSFPU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #11
945 {DBGFIELD("NullALU_WriteSMEM") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #12
946 {DBGFIELD("NullALU_WriteBarrier") 1, false, false, true, 9, 1, 8, 1, 0, 0}, // #13
947 {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, true, 1, 2, 9, 2, 0, 0}, // #14
948 {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #15
949 {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, true, 2, 1, 10, 1, 0, 0}, // #16
950 {DBGFIELD("NullALU_Write64Bit") 1, false, false, true, 2, 1, 10, 1, 0, 0}, // #17
951 {DBGFIELD("NullALU_WriteTrans32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #18
952 {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #19
953 {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #20
954 {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #21
955 {DBGFIELD("NullALU_WriteDouble") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #22
956 {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #23
957 {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, true, 1, 2, 16, 2, 0, 0}, // #24
958 {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, true, 1, 2, 16, 2, 0, 0}, // #25
959 {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #26
960 {DBGFIELD("NullALU_WriteIntMul") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #27
961 {DBGFIELD("NullALU_WriteTrans64") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #28
962 {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, true, 10, 1, 18, 2, 0, 0}, // #29
963 {DBGFIELD("NullALU_WritePseudoScalarTrans") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #30
964 {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, true, 10, 1, 11, 2, 0, 0}, // #31
965 {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32
966 {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #33
967 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #34
968 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #35
969 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #36
970 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #37
971 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #38
972 {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #39
973 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #40
974 {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #41
975 {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #42
976 {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #43
977 {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #44
978 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #45
979 {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #46
980 {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #47
981 {DBGFIELD("Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #48
982 {DBGFIELD("Write64Bit") 1, false, false, true, 2, 1, 10, 1, 0, 0}, // #49
983 {DBGFIELD("WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #50
984 {DBGFIELD("Write64Bit_MIVGPRRead") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #51
985 {DBGFIELD("Write64Bit_ReadDefault") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #52
986}; // SIFullSpeedModelSchedClasses
987
988// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
989static const llvm::MCSchedClassDesc SIDPFullSpeedModelSchedClasses[] = {
990 {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0},
991 {DBGFIELD("NullALU_WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #1
992 {DBGFIELD("NullALU_Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #2
993 {DBGFIELD("NullALU_WriteVMEM") 1, false, false, true, 3, 1, 2, 1, 0, 0}, // #3
994 {DBGFIELD("NullALU_WriteLDS") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #4
995 {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, true, 5, 1, 3, 2, 0, 0}, // #5
996 {DBGFIELD("NullALU_WriteExport") 1, false, false, true, 6, 1, 6, 1, 0, 0}, // #6
997 {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, true, 7, 2, 2, 2, 0, 0}, // #7
998 {DBGFIELD("WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #8
999 {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9
1000 {DBGFIELD("NullALU_WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #10
1001 {DBGFIELD("NullALU_WriteSFPU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #11
1002 {DBGFIELD("NullALU_WriteSMEM") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #12
1003 {DBGFIELD("NullALU_WriteBarrier") 1, false, false, true, 9, 1, 8, 1, 0, 0}, // #13
1004 {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #14
1005 {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #15
1006 {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #16
1007 {DBGFIELD("NullALU_Write64Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #17
1008 {DBGFIELD("NullALU_WriteTrans32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #18
1009 {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #19
1010 {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #20
1011 {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #21
1012 {DBGFIELD("NullALU_WriteDouble") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #22
1013 {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #23
1014 {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #24
1015 {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #25
1016 {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #26
1017 {DBGFIELD("NullALU_WriteIntMul") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #27
1018 {DBGFIELD("NullALU_WriteTrans64") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #28
1019 {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, true, 10, 1, 11, 2, 0, 0}, // #29
1020 {DBGFIELD("NullALU_WritePseudoScalarTrans") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #30
1021 {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, true, 10, 1, 11, 2, 0, 0}, // #31
1022 {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32
1023 {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #33
1024 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 45, 1, 6, 1, 1, 1}, // #34
1025 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 46, 1, 7, 1, 1, 1}, // #35
1026 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #36
1027 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 11, 1, 10, 1, 1, 1}, // #37
1028 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #38
1029 {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #39
1030 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #40
1031 {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #41
1032 {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #42
1033 {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #43
1034 {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #44
1035 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #45
1036 {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #46
1037 {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #47
1038 {DBGFIELD("Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #48
1039 {DBGFIELD("Write64Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #49
1040 {DBGFIELD("WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #50
1041 {DBGFIELD("Write64Bit_MIVGPRRead") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #51
1042 {DBGFIELD("Write64Bit_ReadDefault") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #52
1043}; // SIDPFullSpeedModelSchedClasses
1044
1045// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
1046static const llvm::MCSchedClassDesc SIDPGFX940FullSpeedModelSchedClasses[] = {
1047 {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0},
1048 {DBGFIELD("NullALU_WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #1
1049 {DBGFIELD("NullALU_Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #2
1050 {DBGFIELD("NullALU_WriteVMEM") 1, false, false, true, 3, 1, 2, 1, 0, 0}, // #3
1051 {DBGFIELD("NullALU_WriteLDS") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #4
1052 {DBGFIELD("NullALU_WriteLDS_WriteLDS") 2, false, false, true, 5, 1, 3, 2, 0, 0}, // #5
1053 {DBGFIELD("NullALU_WriteExport") 1, false, false, true, 6, 1, 6, 1, 0, 0}, // #6
1054 {DBGFIELD("NullALU_WriteVMEM_WriteLDS") 2, false, false, true, 7, 2, 2, 2, 0, 0}, // #7
1055 {DBGFIELD("WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #8
1056 {DBGFIELD("NullALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #9
1057 {DBGFIELD("NullALU_WriteBranch") 1, false, false, true, 9, 1, 7, 1, 0, 0}, // #10
1058 {DBGFIELD("NullALU_WriteSFPU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #11
1059 {DBGFIELD("NullALU_WriteSMEM") 1, false, false, true, 4, 1, 3, 1, 0, 0}, // #12
1060 {DBGFIELD("NullALU_WriteBarrier") 1, false, false, true, 9, 1, 8, 1, 0, 0}, // #13
1061 {DBGFIELD("NullALU_WriteSALU_Write64Bit") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #14
1062 {DBGFIELD("NullALU_Write32Bit_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #15
1063 {DBGFIELD("NullALU_WriteDoubleAdd") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #16
1064 {DBGFIELD("NullALU_Write64Bit") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #17
1065 {DBGFIELD("NullALU_WriteTrans32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #18
1066 {DBGFIELD("NullALU_WriteFloatCvt") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #19
1067 {DBGFIELD("NullALU_WriteDoubleCvt") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #20
1068 {DBGFIELD("NullALU_WriteFloatFMA") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #21
1069 {DBGFIELD("NullALU_WriteDouble") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #22
1070 {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #23
1071 {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #24
1072 {DBGFIELD("NullALU_WriteIntMul_WriteSALU") 2, false, false, true, 1, 2, 11, 2, 0, 0}, // #25
1073 {DBGFIELD("NullALU_WriteQuarterRate32") 1, false, false, true, 2, 1, 6, 1, 0, 0}, // #26
1074 {DBGFIELD("NullALU_WriteIntMul") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #27
1075 {DBGFIELD("NullALU_WriteTrans64") 1, false, false, false, 2, 1, 6, 1, 0, 0}, // #28
1076 {DBGFIELD("NullALU_Write64Bit_Write64Bit") 2, false, false, false, 10, 1, 11, 2, 0, 0}, // #29
1077 {DBGFIELD("NullALU_WritePseudoScalarTrans") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #30
1078 {DBGFIELD("NullALU_Write32Bit_Write32Bit") 2, false, false, true, 10, 1, 11, 2, 0, 0}, // #31
1079 {DBGFIELD("COPY") 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #32
1080 {DBGFIELD("V_ACCVGPR_WRITE_B32_e64") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #33
1081 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 45, 1, 6, 1, 1, 1}, // #34
1082 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 46, 1, 7, 1, 1, 1}, // #35
1083 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 13, 1, 13, 1, 1, 1}, // #36
1084 {DBGFIELD("V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi") 1, false, false, true, 11, 1, 10, 1, 1, 1}, // #37
1085 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #38
1086 {DBGFIELD("V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd") 1, false, false, true, 47, 1, 6, 1, 1, 1}, // #39
1087 {DBGFIELD("V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi") 1, false, false, true, 47, 1, 6, 1, 1, 1}, // #40
1088 {DBGFIELD("V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd") 1, false, false, true, 47, 1, 6, 1, 1, 1}, // #41
1089 {DBGFIELD("V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #42
1090 {DBGFIELD("V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #43
1091 {DBGFIELD("V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #44
1092 {DBGFIELD("V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #45
1093 {DBGFIELD("V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940") 1, false, false, true, 47, 1, 6, 1, 1, 1}, // #46
1094 {DBGFIELD("V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940") 1, false, false, true, 12, 1, 7, 1, 1, 1}, // #47
1095 {DBGFIELD("Write32Bit") 1, false, false, true, 2, 1, 1, 1, 0, 0}, // #48
1096 {DBGFIELD("Write64Bit") 1, false, false, false, 2, 1, 1, 1, 0, 0}, // #49
1097 {DBGFIELD("WriteSALU") 1, false, false, true, 1, 1, 1, 1, 0, 0}, // #50
1098 {DBGFIELD("Write64Bit_MIVGPRRead") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #51
1099 {DBGFIELD("Write64Bit_ReadDefault") 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #52
1100}; // SIDPGFX940FullSpeedModelSchedClasses
1101
1102#undef DBGFIELD
1103
1104static const llvm::MCSchedModel NoSchedModel = {
1105 MCSchedModel::DefaultIssueWidth,
1106 MCSchedModel::DefaultMicroOpBufferSize,
1107 MCSchedModel::DefaultLoopMicroOpBufferSize,
1108 MCSchedModel::DefaultLoadLatency,
1109 MCSchedModel::DefaultHighLatency,
1110 MCSchedModel::DefaultMispredictPenalty,
1111 false, // PostRAScheduler
1112 false, // CompleteModel
1113 false, // EnableIntervals
1114 0, // Processor ID
1115 nullptr, nullptr, 0, 0, // No instruction-level machine model.
1116 nullptr, // No Itinerary
1117 nullptr // No extra processor descriptor
1118};
1119
1120static const unsigned SIQuarterSpeedModelProcResourceSubUnits[] = {
1121 0, // Invalid
1122};
1123
1124// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
1125static const llvm::MCProcResourceDesc SIQuarterSpeedModelProcResources[] = {
1126 {"InvalidUnit", 0, 0, 0, 0},
1127 {"HWBranch", 1, 0, 1, nullptr}, // #1
1128 {"HWExport", 1, 0, 1, nullptr}, // #2
1129 {"HWLGKM", 1, 0, 1, nullptr}, // #3
1130 {"HWSALU", 1, 0, 1, nullptr}, // #4
1131 {"HWVALU", 1, 0, 1, nullptr}, // #5
1132 {"HWVMEM", 1, 0, 1, nullptr}, // #6
1133 {"HWXDL", 1, 0, 0, nullptr}, // #7
1134};
1135
1136static const llvm::MCSchedModel SIQuarterSpeedModel = {
1137 1, // IssueWidth
1138 1, // MicroOpBufferSize
1139 MCSchedModel::DefaultLoopMicroOpBufferSize,
1140 MCSchedModel::DefaultLoadLatency,
1141 MCSchedModel::DefaultHighLatency,
1142 20, // MispredictPenalty
1143 true, // PostRAScheduler
1144 true, // CompleteModel
1145 false, // EnableIntervals
1146 1, // Processor ID
1147 SIQuarterSpeedModelProcResources,
1148 SIQuarterSpeedModelSchedClasses,
1149 8,
1150 53,
1151 nullptr, // No Itinerary
1152 nullptr // No extra processor descriptor
1153};
1154
1155static const unsigned GFX10SpeedModelProcResourceSubUnits[] = {
1156 0, // Invalid
1157};
1158
1159// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
1160static const llvm::MCProcResourceDesc GFX10SpeedModelProcResources[] = {
1161 {"InvalidUnit", 0, 0, 0, 0},
1162 {"HWBranch", 1, 0, 1, nullptr}, // #1
1163 {"HWExport", 1, 0, 1, nullptr}, // #2
1164 {"HWLGKM", 1, 0, 1, nullptr}, // #3
1165 {"HWRC", 1, 0, 1, nullptr}, // #4
1166 {"HWSALU", 1, 0, 1, nullptr}, // #5
1167 {"HWTransVALU", 1, 0, 1, nullptr}, // #6
1168 {"HWVALU", 1, 0, 1, nullptr}, // #7
1169 {"HWVMEM", 1, 0, 1, nullptr}, // #8
1170};
1171
1172static const llvm::MCSchedModel GFX10SpeedModel = {
1173 1, // IssueWidth
1174 1, // MicroOpBufferSize
1175 MCSchedModel::DefaultLoopMicroOpBufferSize,
1176 MCSchedModel::DefaultLoadLatency,
1177 MCSchedModel::DefaultHighLatency,
1178 20, // MispredictPenalty
1179 true, // PostRAScheduler
1180 true, // CompleteModel
1181 false, // EnableIntervals
1182 2, // Processor ID
1183 GFX10SpeedModelProcResources,
1184 GFX10SpeedModelSchedClasses,
1185 9,
1186 53,
1187 nullptr, // No Itinerary
1188 nullptr // No extra processor descriptor
1189};
1190
1191static const unsigned GFX11SpeedModelProcResourceSubUnits[] = {
1192 0, // Invalid
1193};
1194
1195// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
1196static const llvm::MCProcResourceDesc GFX11SpeedModelProcResources[] = {
1197 {"InvalidUnit", 0, 0, 0, 0},
1198 {"HWBranch", 1, 0, 1, nullptr}, // #1
1199 {"HWExport", 1, 0, 1, nullptr}, // #2
1200 {"HWLGKM", 1, 0, 1, nullptr}, // #3
1201 {"HWRC", 1, 0, 1, nullptr}, // #4
1202 {"HWSALU", 1, 0, 1, nullptr}, // #5
1203 {"HWTransVALU", 1, 0, 1, nullptr}, // #6
1204 {"HWVALU", 1, 0, 1, nullptr}, // #7
1205 {"HWVMEM", 1, 0, 1, nullptr}, // #8
1206};
1207
1208static const llvm::MCSchedModel GFX11SpeedModel = {
1209 1, // IssueWidth
1210 1, // MicroOpBufferSize
1211 MCSchedModel::DefaultLoopMicroOpBufferSize,
1212 MCSchedModel::DefaultLoadLatency,
1213 MCSchedModel::DefaultHighLatency,
1214 20, // MispredictPenalty
1215 true, // PostRAScheduler
1216 true, // CompleteModel
1217 false, // EnableIntervals
1218 3, // Processor ID
1219 GFX11SpeedModelProcResources,
1220 GFX11SpeedModelSchedClasses,
1221 9,
1222 53,
1223 nullptr, // No Itinerary
1224 nullptr // No extra processor descriptor
1225};
1226
1227static const unsigned GFX12SpeedModelProcResourceSubUnits[] = {
1228 0, // Invalid
1229};
1230
1231// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
1232static const llvm::MCProcResourceDesc GFX12SpeedModelProcResources[] = {
1233 {"InvalidUnit", 0, 0, 0, 0},
1234 {"HWBranch", 1, 0, 1, nullptr}, // #1
1235 {"HWExport", 1, 0, 1, nullptr}, // #2
1236 {"HWLGKM", 1, 0, 1, nullptr}, // #3
1237 {"HWRC", 1, 0, 1, nullptr}, // #4
1238 {"HWSALU", 1, 0, 1, nullptr}, // #5
1239 {"HWVALU", 1, 0, 1, nullptr}, // #6
1240 {"HWVMEM", 1, 0, 1, nullptr}, // #7
1241};
1242
1243static const llvm::MCSchedModel GFX12SpeedModel = {
1244 1, // IssueWidth
1245 1, // MicroOpBufferSize
1246 MCSchedModel::DefaultLoopMicroOpBufferSize,
1247 MCSchedModel::DefaultLoadLatency,
1248 MCSchedModel::DefaultHighLatency,
1249 20, // MispredictPenalty
1250 true, // PostRAScheduler
1251 true, // CompleteModel
1252 false, // EnableIntervals
1253 4, // Processor ID
1254 GFX12SpeedModelProcResources,
1255 GFX12SpeedModelSchedClasses,
1256 8,
1257 53,
1258 nullptr, // No Itinerary
1259 nullptr // No extra processor descriptor
1260};
1261
1262static const unsigned SIFullSpeedModelProcResourceSubUnits[] = {
1263 0, // Invalid
1264};
1265
1266// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
1267static const llvm::MCProcResourceDesc SIFullSpeedModelProcResources[] = {
1268 {"InvalidUnit", 0, 0, 0, 0},
1269 {"HWBranch", 1, 0, 1, nullptr}, // #1
1270 {"HWExport", 1, 0, 1, nullptr}, // #2
1271 {"HWLGKM", 1, 0, 1, nullptr}, // #3
1272 {"HWSALU", 1, 0, 1, nullptr}, // #4
1273 {"HWVALU", 1, 0, 1, nullptr}, // #5
1274 {"HWVMEM", 1, 0, 1, nullptr}, // #6
1275 {"HWXDL", 1, 0, 0, nullptr}, // #7
1276};
1277
1278static const llvm::MCSchedModel SIFullSpeedModel = {
1279 1, // IssueWidth
1280 1, // MicroOpBufferSize
1281 MCSchedModel::DefaultLoopMicroOpBufferSize,
1282 MCSchedModel::DefaultLoadLatency,
1283 MCSchedModel::DefaultHighLatency,
1284 20, // MispredictPenalty
1285 true, // PostRAScheduler
1286 true, // CompleteModel
1287 false, // EnableIntervals
1288 5, // Processor ID
1289 SIFullSpeedModelProcResources,
1290 SIFullSpeedModelSchedClasses,
1291 8,
1292 53,
1293 nullptr, // No Itinerary
1294 nullptr // No extra processor descriptor
1295};
1296
1297static const unsigned SIDPFullSpeedModelProcResourceSubUnits[] = {
1298 0, // Invalid
1299};
1300
1301// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
1302static const llvm::MCProcResourceDesc SIDPFullSpeedModelProcResources[] = {
1303 {"InvalidUnit", 0, 0, 0, 0},
1304 {"HWBranch", 1, 0, 1, nullptr}, // #1
1305 {"HWExport", 1, 0, 1, nullptr}, // #2
1306 {"HWLGKM", 1, 0, 1, nullptr}, // #3
1307 {"HWSALU", 1, 0, 1, nullptr}, // #4
1308 {"HWVALU", 1, 0, 1, nullptr}, // #5
1309 {"HWVMEM", 1, 0, 1, nullptr}, // #6
1310 {"HWXDL", 1, 0, 0, nullptr}, // #7
1311};
1312
1313static const llvm::MCSchedModel SIDPFullSpeedModel = {
1314 1, // IssueWidth
1315 1, // MicroOpBufferSize
1316 MCSchedModel::DefaultLoopMicroOpBufferSize,
1317 MCSchedModel::DefaultLoadLatency,
1318 MCSchedModel::DefaultHighLatency,
1319 20, // MispredictPenalty
1320 true, // PostRAScheduler
1321 true, // CompleteModel
1322 false, // EnableIntervals
1323 6, // Processor ID
1324 SIDPFullSpeedModelProcResources,
1325 SIDPFullSpeedModelSchedClasses,
1326 8,
1327 53,
1328 nullptr, // No Itinerary
1329 nullptr // No extra processor descriptor
1330};
1331
1332static const unsigned SIDPGFX940FullSpeedModelProcResourceSubUnits[] = {
1333 0, // Invalid
1334};
1335
1336// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
1337static const llvm::MCProcResourceDesc SIDPGFX940FullSpeedModelProcResources[] = {
1338 {"InvalidUnit", 0, 0, 0, 0},
1339 {"HWBranch", 1, 0, 1, nullptr}, // #1
1340 {"HWExport", 1, 0, 1, nullptr}, // #2
1341 {"HWLGKM", 1, 0, 1, nullptr}, // #3
1342 {"HWSALU", 1, 0, 1, nullptr}, // #4
1343 {"HWVALU", 1, 0, 1, nullptr}, // #5
1344 {"HWVMEM", 1, 0, 1, nullptr}, // #6
1345 {"HWXDL", 1, 0, 0, nullptr}, // #7
1346};
1347
1348static const llvm::MCSchedModel SIDPGFX940FullSpeedModel = {
1349 1, // IssueWidth
1350 1, // MicroOpBufferSize
1351 MCSchedModel::DefaultLoopMicroOpBufferSize,
1352 MCSchedModel::DefaultLoadLatency,
1353 MCSchedModel::DefaultHighLatency,
1354 20, // MispredictPenalty
1355 true, // PostRAScheduler
1356 true, // CompleteModel
1357 false, // EnableIntervals
1358 7, // Processor ID
1359 SIDPGFX940FullSpeedModelProcResources,
1360 SIDPGFX940FullSpeedModelSchedClasses,
1361 8,
1362 53,
1363 nullptr, // No Itinerary
1364 nullptr // No extra processor descriptor
1365};
1366
1367// Sorted (by key) array of values for CPU subtype.
1368extern const llvm::SubtargetSubTypeKV AMDGPUSubTypeKV[] = {
1369 { "bonaire", { { { 0x0ULL, 0x1000000000ULL, 0x8000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1370 { "carrizo", { { { 0x800000000000000ULL, 0x1000000000ULL, 0x1020020100000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1371 { "fiji", { { { 0x0ULL, 0x1000000000ULL, 0x20020000000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1372 { "generic", { { { 0x0ULL, 0x2000200ULL, 0x200000000000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
1373 { "generic-hsa", { { { 0x1000000000000000ULL, 0x2000200ULL, 0x200000000000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
1374 { "gfx10-1-generic", { { { 0x100002400000ULL, 0x4b80407084004008ULL, 0xc400106880400ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel },
1375 { "gfx10-3-generic", { { { 0x4e602400000ULL, 0x100001000074000ULL, 0x20000400ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel },
1376 { "gfx1010", { { { 0x100002400000ULL, 0x4b80407084004008ULL, 0xc400106880000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel },
1377 { "gfx1011", { { { 0x14e602400000ULL, 0x4b80407084004008ULL, 0xc400106880000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel },
1378 { "gfx1012", { { { 0x14e602400000ULL, 0x4b80407084004008ULL, 0xc400106880000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel },
1379 { "gfx1013", { { { 0x100002400000ULL, 0x4b80407084024008ULL, 0xc400106880000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel },
1380 { "gfx1030", { { { 0x4e602400000ULL, 0x100001000074000ULL, 0x20000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel },
1381 { "gfx1031", { { { 0x4e602400000ULL, 0x100001000074000ULL, 0x20000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel },
1382 { "gfx1032", { { { 0x4e602400000ULL, 0x100001000074000ULL, 0x20000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel },
1383 { "gfx1033", { { { 0x4e602400000ULL, 0x100001000074000ULL, 0x20000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel },
1384 { "gfx1034", { { { 0x4e602400000ULL, 0x100001000074000ULL, 0x20000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel },
1385 { "gfx1035", { { { 0x4e602400000ULL, 0x100001000074000ULL, 0x20000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel },
1386 { "gfx1036", { { { 0x4e602400000ULL, 0x100001000074000ULL, 0x20000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX10SpeedModel },
1387 { "gfx11-generic", { { { 0x200007a002060040ULL, 0x120221020080000ULL, 0x80c0020000613ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel },
1388 { "gfx1100", { { { 0x200007a002060041ULL, 0x120221020080000ULL, 0x80c0020000013ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel },
1389 { "gfx1101", { { { 0x200007a002060041ULL, 0x120221020080000ULL, 0x8080020000013ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel },
1390 { "gfx1102", { { { 0x200007a002060040ULL, 0x120221020080000ULL, 0x80c0020000013ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel },
1391 { "gfx1103", { { { 0x200007a002060040ULL, 0x120221020080000ULL, 0x8080020000013ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel },
1392 { "gfx1150", { { { 0x200007a022060040ULL, 0x120001020080000ULL, 0x8200020000a03ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel },
1393 { "gfx1151", { { { 0x200007a022060041ULL, 0x120001020080000ULL, 0x8200020000a03ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel },
1394 { "gfx1152", { { { 0x200007a022060040ULL, 0x120001020080000ULL, 0x8200020000a03ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX11SpeedModel },
1395 { "gfx12-generic", { { { 0x20a00f80221e15c1ULL, 0x121001028200000ULL, 0x8200011000c43ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX12SpeedModel },
1396 { "gfx1200", { { { 0x20a00f80221e15c1ULL, 0x121001028200000ULL, 0x8200011000843ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX12SpeedModel },
1397 { "gfx1201", { { { 0x20a00f80221e15c1ULL, 0x121001028200000ULL, 0x8200011000843ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &GFX12SpeedModel },
1398 { "gfx600", { { { 0x800000000000000ULL, 0x1000000000ULL, 0x1000000040000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIFullSpeedModel },
1399 { "gfx601", { { { 0x0ULL, 0x1000000000ULL, 0x40000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1400 { "gfx602", { { { 0x0ULL, 0x1000000000ULL, 0x40000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1401 { "gfx700", { { { 0x0ULL, 0x1000000000ULL, 0x8000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1402 { "gfx701", { { { 0x800000000000000ULL, 0x1000000000ULL, 0x1000000008000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIFullSpeedModel },
1403 { "gfx702", { { { 0x800000000000000ULL, 0x800000000ULL, 0x8000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1404 { "gfx703", { { { 0x0ULL, 0x800000000ULL, 0x8000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1405 { "gfx704", { { { 0x0ULL, 0x1000000000ULL, 0x8000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1406 { "gfx705", { { { 0x0ULL, 0x800000000ULL, 0x8000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1407 { "gfx801", { { { 0x800000000000000ULL, 0x1000000000ULL, 0x1020020100000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1408 { "gfx802", { { { 0x0ULL, 0x1000000000ULL, 0x20020000040000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1409 { "gfx803", { { { 0x0ULL, 0x1000000000ULL, 0x20020000000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1410 { "gfx805", { { { 0x0ULL, 0x1000000000ULL, 0x20020000040000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1411 { "gfx810", { { { 0x0ULL, 0x850000000ULL, 0x20000100000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1412 { "gfx9-generic", { { { 0x20100000000000ULL, 0x401030001200ULL, 0x400ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1413 { "gfx900", { { { 0x20100000000000ULL, 0xc01030001200ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1414 { "gfx902", { { { 0x20100000000000ULL, 0xc01030001200ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1415 { "gfx904", { { { 0x20100000000000ULL, 0x401030001210ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1416 { "gfx906", { { { 0x20148602000000ULL, 0x401030001210ULL, 0x1000000080000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1417 { "gfx908", { { { 0x2014fe02020200ULL, 0x4c1030001210ULL, 0x1000000080000004ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1418 { "gfx909", { { { 0x20100000000000ULL, 0xc01030001200ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1419 { "gfx90a", { { { 0x400004fe06478100ULL, 0x8000441420801030ULL, 0x800000080000005ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIDPFullSpeedModel },
1420 { "gfx90c", { { { 0x20100000000000ULL, 0xc01030001200ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1421 { "gfx940", { { { 0x618004fe065f9150ULL, 0x8020041401801070ULL, 0x800000080000005ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIDPGFX940FullSpeedModel },
1422 { "gfx941", { { { 0x618004fe065f9150ULL, 0x8020041401801070ULL, 0x800000080000005ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIDPGFX940FullSpeedModel },
1423 { "gfx942", { { { 0x618004fe065f9150ULL, 0x8020041401801030ULL, 0x800000080000005ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIDPGFX940FullSpeedModel },
1424 { "hainan", { { { 0x0ULL, 0x1000000000ULL, 0x40000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1425 { "hawaii", { { { 0x800000000000000ULL, 0x1000000000ULL, 0x1000000008000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIFullSpeedModel },
1426 { "iceland", { { { 0x0ULL, 0x1000000000ULL, 0x20020000040000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1427 { "kabini", { { { 0x0ULL, 0x800000000ULL, 0x8000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1428 { "kaveri", { { { 0x0ULL, 0x1000000000ULL, 0x8000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1429 { "mullins", { { { 0x0ULL, 0x800000000ULL, 0x8000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1430 { "oland", { { { 0x0ULL, 0x1000000000ULL, 0x40000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1431 { "pitcairn", { { { 0x0ULL, 0x1000000000ULL, 0x40000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1432 { "polaris10", { { { 0x0ULL, 0x1000000000ULL, 0x20020000000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1433 { "polaris11", { { { 0x0ULL, 0x1000000000ULL, 0x20020000000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1434 { "stoney", { { { 0x0ULL, 0x850000000ULL, 0x20000100000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1435 { "tahiti", { { { 0x800000000000000ULL, 0x1000000000ULL, 0x1000000040000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIFullSpeedModel },
1436 { "tonga", { { { 0x0ULL, 0x1000000000ULL, 0x20020000040000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1437 { "tongapro", { { { 0x0ULL, 0x1000000000ULL, 0x20020000040000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1438 { "verde", { { { 0x0ULL, 0x1000000000ULL, 0x40000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &SIQuarterSpeedModel },
1439};
1440
1441namespace AMDGPU_MC {
1442unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
1443 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
1444 switch (SchedClass) {
1445 case 32: // COPY
1446 if (CPUID == 1) { // SIQuarterSpeedModel
1447 return 50; // WriteSALU
1448 }
1449 if (CPUID == 2) { // GFX10SpeedModel
1450 return 50; // WriteSALU
1451 }
1452 if (CPUID == 3) { // GFX11SpeedModel
1453 return 50; // WriteSALU
1454 }
1455 if (CPUID == 4) { // GFX12SpeedModel
1456 return 50; // WriteSALU
1457 }
1458 if (CPUID == 5) { // SIFullSpeedModel
1459 return 50; // WriteSALU
1460 }
1461 if (CPUID == 6) { // SIDPFullSpeedModel
1462 return 50; // WriteSALU
1463 }
1464 if (CPUID == 7) { // SIDPGFX940FullSpeedModel
1465 return 50; // WriteSALU
1466 }
1467 break;
1468 case 33: // V_ACCVGPR_WRITE_B32_e64
1469 if (CPUID == 1) { // SIQuarterSpeedModel
1470 return 52; // Write64Bit_ReadDefault
1471 }
1472 break;
1473 };
1474 // Don't know how to resolve this scheduling class.
1475 return 0;
1476}
1477} // end namespace AMDGPU_MC
1478
1479struct AMDGPUGenMCSubtargetInfo : public MCSubtargetInfo {
1480 AMDGPUGenMCSubtargetInfo(const Triple &TT,
1481 StringRef CPU, StringRef TuneCPU, StringRef FS,
1482 ArrayRef<SubtargetFeatureKV> PF,
1483 ArrayRef<SubtargetSubTypeKV> PD,
1484 const MCWriteProcResEntry *WPR,
1485 const MCWriteLatencyEntry *WL,
1486 const MCReadAdvanceEntry *RA, const InstrStage *IS,
1487 const unsigned *OC, const unsigned *FP) :
1488 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
1489 WPR, WL, RA, IS, OC, FP) { }
1490
1491 unsigned resolveVariantSchedClass(unsigned SchedClass,
1492 const MCInst *MI, const MCInstrInfo *MCII,
1493 unsigned CPUID) const override {
1494 return AMDGPU_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
1495 }
1496};
1497
1498static inline MCSubtargetInfo *createAMDGPUMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
1499 return new AMDGPUGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, AMDGPUFeatureKV, AMDGPUSubTypeKV,
1500 AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable,
1501 nullptr, nullptr, nullptr);
1502}
1503
1504} // end namespace llvm
1505
1506#endif // GET_SUBTARGETINFO_MC_DESC
1507
1508
1509#ifdef GET_SUBTARGETINFO_TARGET_DESC
1510#undef GET_SUBTARGETINFO_TARGET_DESC
1511
1512#include "llvm/Support/Debug.h"
1513#include "llvm/Support/raw_ostream.h"
1514
1515// ParseSubtargetFeatures - Parses features string setting specified
1516// subtarget options.
1517void llvm::AMDGPUSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
1518 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
1519 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
1520 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
1521 InitMCProcessorInfo(CPU, TuneCPU, FS);
1522 const FeatureBitset &Bits = getFeatureBits();
1523 if (Bits[AMDGPU::Feature1_5xVGPRs]) Has1_5xVGPRs = true;
1524 if (Bits[AMDGPU::Feature16BitInsts]) Has16BitInsts = true;
1525 if (Bits[AMDGPU::FeatureA16]) HasA16 = true;
1526 if (Bits[AMDGPU::FeatureAddNoCarryInsts]) AddNoCarryInsts = true;
1527 if (Bits[AMDGPU::FeatureAgentScopeFineGrainedRemoteMemoryAtomics]) HasAgentScopeFineGrainedRemoteMemoryAtomics = true;
1528 if (Bits[AMDGPU::FeatureApertureRegs]) HasApertureRegs = true;
1529 if (Bits[AMDGPU::FeatureArchitectedFlatScratch]) HasArchitectedFlatScratch = true;
1530 if (Bits[AMDGPU::FeatureArchitectedSGPRs]) HasArchitectedSGPRs = true;
1531 if (Bits[AMDGPU::FeatureAtomicBufferGlobalPkAddF16Insts]) HasAtomicBufferGlobalPkAddF16Insts = true;
1532 if (Bits[AMDGPU::FeatureAtomicBufferGlobalPkAddF16NoRtnInsts]) HasAtomicBufferGlobalPkAddF16NoRtnInsts = true;
1533 if (Bits[AMDGPU::FeatureAtomicBufferPkAddBF16Inst]) HasAtomicBufferPkAddBF16Inst = true;
1534 if (Bits[AMDGPU::FeatureAtomicCSubNoRtnInsts]) HasAtomicCSubNoRtnInsts = true;
1535 if (Bits[AMDGPU::FeatureAtomicDsPkAdd16Insts]) HasAtomicDsPkAdd16Insts = true;
1536 if (Bits[AMDGPU::FeatureAtomicFMinFMaxF32FlatInsts]) HasAtomicFMinFMaxF32FlatInsts = true;
1537 if (Bits[AMDGPU::FeatureAtomicFMinFMaxF32GlobalInsts]) HasAtomicFMinFMaxF32GlobalInsts = true;
1538 if (Bits[AMDGPU::FeatureAtomicFMinFMaxF64FlatInsts]) HasAtomicFMinFMaxF64FlatInsts = true;
1539 if (Bits[AMDGPU::FeatureAtomicFMinFMaxF64GlobalInsts]) HasAtomicFMinFMaxF64GlobalInsts = true;
1540 if (Bits[AMDGPU::FeatureAtomicFaddNoRtnInsts]) HasAtomicFaddNoRtnInsts = true;
1541 if (Bits[AMDGPU::FeatureAtomicFaddRtnInsts]) HasAtomicFaddRtnInsts = true;
1542 if (Bits[AMDGPU::FeatureAtomicFlatPkAdd16Insts]) HasAtomicFlatPkAdd16Insts = true;
1543 if (Bits[AMDGPU::FeatureAtomicGlobalPkAddBF16Inst]) HasAtomicGlobalPkAddBF16Inst = true;
1544 if (Bits[AMDGPU::FeatureAutoWaitcntBeforeBarrier]) AutoWaitcntBeforeBarrier = true;
1545 if (Bits[AMDGPU::FeatureBackOffBarrier]) BackOffBarrier = true;
1546 if (Bits[AMDGPU::FeatureCIInsts]) CIInsts = true;
1547 if (Bits[AMDGPU::FeatureCuMode]) EnableCuMode = true;
1548 if (Bits[AMDGPU::FeatureDLInsts]) HasDLInsts = true;
1549 if (Bits[AMDGPU::FeatureDPALU_DPP]) HasDPALU_DPP = true;
1550 if (Bits[AMDGPU::FeatureDPP]) HasDPP = true;
1551 if (Bits[AMDGPU::FeatureDPP8]) HasDPP8 = true;
1552 if (Bits[AMDGPU::FeatureDPPSrc1SGPR]) HasDPPSrc1SGPR = true;
1553 if (Bits[AMDGPU::FeatureDefaultComponentBroadcast]) HasDefaultComponentBroadcast = true;
1554 if (Bits[AMDGPU::FeatureDefaultComponentZero]) HasDefaultComponentZero = true;
1555 if (Bits[AMDGPU::FeatureDisable]) FeatureDisable = true;
1556 if (Bits[AMDGPU::FeatureDot1Insts]) HasDot1Insts = true;
1557 if (Bits[AMDGPU::FeatureDot2Insts]) HasDot2Insts = true;
1558 if (Bits[AMDGPU::FeatureDot3Insts]) HasDot3Insts = true;
1559 if (Bits[AMDGPU::FeatureDot4Insts]) HasDot4Insts = true;
1560 if (Bits[AMDGPU::FeatureDot5Insts]) HasDot5Insts = true;
1561 if (Bits[AMDGPU::FeatureDot6Insts]) HasDot6Insts = true;
1562 if (Bits[AMDGPU::FeatureDot7Insts]) HasDot7Insts = true;
1563 if (Bits[AMDGPU::FeatureDot8Insts]) HasDot8Insts = true;
1564 if (Bits[AMDGPU::FeatureDot9Insts]) HasDot9Insts = true;
1565 if (Bits[AMDGPU::FeatureDot10Insts]) HasDot10Insts = true;
1566 if (Bits[AMDGPU::FeatureDot11Insts]) HasDot11Insts = true;
1567 if (Bits[AMDGPU::FeatureDsSrc2Insts]) HasDsSrc2Insts = true;
1568 if (Bits[AMDGPU::FeatureDumpCode]) DumpCode = true;
1569 if (Bits[AMDGPU::FeatureDumpCodeLower]) DumpCode = true;
1570 if (Bits[AMDGPU::FeatureEnableDS128]) EnableDS128 = true;
1571 if (Bits[AMDGPU::FeatureEnableFlatScratch]) EnableFlatScratch = true;
1572 if (Bits[AMDGPU::FeatureEnableLoadStoreOpt]) EnableLoadStoreOpt = true;
1573 if (Bits[AMDGPU::FeatureEnablePRTStrictNull]) EnablePRTStrictNull = true;
1574 if (Bits[AMDGPU::FeatureEnableSIScheduler]) EnableSIScheduler = true;
1575 if (Bits[AMDGPU::FeatureEnableUnsafeDSOffsetFolding]) EnableUnsafeDSOffsetFolding = true;
1576 if (Bits[AMDGPU::FeatureExtendedImageInsts]) HasExtendedImageInsts = true;
1577 if (Bits[AMDGPU::FeatureFMA]) FMA = true;
1578 if (Bits[AMDGPU::FeatureFP8ConversionInsts]) HasFP8ConversionInsts = true;
1579 if (Bits[AMDGPU::FeatureFP8Insts]) HasFP8Insts = true;
1580 if (Bits[AMDGPU::FeatureFP64]) FP64 = true;
1581 if (Bits[AMDGPU::FeatureFastDenormalF32]) FastDenormalF32 = true;
1582 if (Bits[AMDGPU::FeatureFastFMAF32]) FastFMAF32 = true;
1583 if (Bits[AMDGPU::FeatureFlatAddressSpace]) FlatAddressSpace = true;
1584 if (Bits[AMDGPU::FeatureFlatAtomicFaddF32Inst]) HasFlatAtomicFaddF32Inst = true;
1585 if (Bits[AMDGPU::FeatureFlatBufferGlobalAtomicFaddF64Inst]) HasFlatBufferGlobalAtomicFaddF64Inst = true;
1586 if (Bits[AMDGPU::FeatureFlatForGlobal]) FlatForGlobal = true;
1587 if (Bits[AMDGPU::FeatureFlatGlobalInsts]) FlatGlobalInsts = true;
1588 if (Bits[AMDGPU::FeatureFlatInstOffsets]) FlatInstOffsets = true;
1589 if (Bits[AMDGPU::FeatureFlatScratchInsts]) FlatScratchInsts = true;
1590 if (Bits[AMDGPU::FeatureFlatSegmentOffsetBug]) HasFlatSegmentOffsetBug = true;
1591 if (Bits[AMDGPU::FeatureFmaMixInsts]) HasFmaMixInsts = true;
1592 if (Bits[AMDGPU::FeatureFmacF64Inst]) HasFmacF64Inst = true;
1593 if (Bits[AMDGPU::FeatureForceStoreSC0SC1]) HasForceStoreSC0SC1 = true;
1594 if (Bits[AMDGPU::FeatureG16]) HasG16 = true;
1595 if (Bits[AMDGPU::FeatureGCN3Encoding]) GCN3Encoding = true;
1596 if (Bits[AMDGPU::FeatureGDS]) HasGDS = true;
1597 if (Bits[AMDGPU::FeatureGFX7GFX8GFX9Insts]) GFX7GFX8GFX9Insts = true;
1598 if (Bits[AMDGPU::FeatureGFX8Insts]) GFX8Insts = true;
1599 if (Bits[AMDGPU::FeatureGFX9] && Gen < GCNSubtarget::GFX9) Gen = GCNSubtarget::GFX9;
1600 if (Bits[AMDGPU::FeatureGFX9Insts]) GFX9Insts = true;
1601 if (Bits[AMDGPU::FeatureGFX10] && Gen < GCNSubtarget::GFX10) Gen = GCNSubtarget::GFX10;
1602 if (Bits[AMDGPU::FeatureGFX10Insts]) GFX10Insts = true;
1603 if (Bits[AMDGPU::FeatureGFX10_3Insts]) GFX10_3Insts = true;
1604 if (Bits[AMDGPU::FeatureGFX10_AEncoding]) GFX10_AEncoding = true;
1605 if (Bits[AMDGPU::FeatureGFX10_BEncoding]) GFX10_BEncoding = true;
1606 if (Bits[AMDGPU::FeatureGFX11] && Gen < GCNSubtarget::GFX11) Gen = GCNSubtarget::GFX11;
1607 if (Bits[AMDGPU::FeatureGFX11Insts]) GFX11Insts = true;
1608 if (Bits[AMDGPU::FeatureGFX12] && Gen < GCNSubtarget::GFX12) Gen = GCNSubtarget::GFX12;
1609 if (Bits[AMDGPU::FeatureGFX12Insts]) GFX12Insts = true;
1610 if (Bits[AMDGPU::FeatureGFX90AInsts]) GFX90AInsts = true;
1611 if (Bits[AMDGPU::FeatureGFX940Insts]) GFX940Insts = true;
1612 if (Bits[AMDGPU::FeatureGWS]) HasGWS = true;
1613 if (Bits[AMDGPU::FeatureGetWaveIdInst]) HasGetWaveIdInst = true;
1614 if (Bits[AMDGPU::FeatureHasRestrictedSOffset]) HasRestrictedSOffset = true;
1615 if (Bits[AMDGPU::FeatureImageGather4D16Bug]) HasImageGather4D16Bug = true;
1616 if (Bits[AMDGPU::FeatureImageInsts]) HasImageInsts = true;
1617 if (Bits[AMDGPU::FeatureImageStoreD16Bug]) HasImageStoreD16Bug = true;
1618 if (Bits[AMDGPU::FeatureInstFwdPrefetchBug]) HasInstFwdPrefetchBug = true;
1619 if (Bits[AMDGPU::FeatureIntClamp]) HasIntClamp = true;
1620 if (Bits[AMDGPU::FeatureInv2PiInlineImm]) HasInv2PiInlineImm = true;
1621 if (Bits[AMDGPU::FeatureKernargPreload]) KernargPreload = true;
1622 if (Bits[AMDGPU::FeatureLDSBankCount16] && LDSBankCount < 16) LDSBankCount = 16;
1623 if (Bits[AMDGPU::FeatureLDSBankCount32] && LDSBankCount < 32) LDSBankCount = 32;
1624 if (Bits[AMDGPU::FeatureLdsBranchVmemWARHazard]) HasLdsBranchVmemWARHazard = true;
1625 if (Bits[AMDGPU::FeatureLdsMisalignedBug]) LDSMisalignedBug = true;
1626 if (Bits[AMDGPU::FeatureLocalMemorySize32768] && LocalMemorySize < 32768) LocalMemorySize = 32768;
1627 if (Bits[AMDGPU::FeatureLocalMemorySize65536] && LocalMemorySize < 65536) LocalMemorySize = 65536;
1628 if (Bits[AMDGPU::FeatureMADIntraFwdBug]) HasMADIntraFwdBug = true;
1629 if (Bits[AMDGPU::FeatureMAIInsts]) HasMAIInsts = true;
1630 if (Bits[AMDGPU::FeatureMFMAInlineLiteralBug]) HasMFMAInlineLiteralBug = true;
1631 if (Bits[AMDGPU::FeatureMIMG_R128]) MIMG_R128 = true;
1632 if (Bits[AMDGPU::FeatureMSAALoadDstSelBug]) HasMSAALoadDstSelBug = true;
1633 if (Bits[AMDGPU::FeatureMadMacF32Insts]) HasMadMacF32Insts = true;
1634 if (Bits[AMDGPU::FeatureMadMixInsts]) HasMadMixInsts = true;
1635 if (Bits[AMDGPU::FeatureMaxHardClauseLength32] && MaxHardClauseLength < 32) MaxHardClauseLength = 32;
1636 if (Bits[AMDGPU::FeatureMaxHardClauseLength63] && MaxHardClauseLength < 63) MaxHardClauseLength = 63;
1637 if (Bits[AMDGPU::FeatureMaxPrivateElementSize4] && MaxPrivateElementSize < 4) MaxPrivateElementSize = 4;
1638 if (Bits[AMDGPU::FeatureMaxPrivateElementSize8] && MaxPrivateElementSize < 8) MaxPrivateElementSize = 8;
1639 if (Bits[AMDGPU::FeatureMaxPrivateElementSize16] && MaxPrivateElementSize < 16) MaxPrivateElementSize = 16;
1640 if (Bits[AMDGPU::FeatureMemoryAtomicFAddF32DenormalSupport]) HasMemoryAtomicFaddF32DenormalSupport = true;
1641 if (Bits[AMDGPU::FeatureMovrel]) HasMovrel = true;
1642 if (Bits[AMDGPU::FeatureNSAClauseBug]) HasNSAClauseBug = true;
1643 if (Bits[AMDGPU::FeatureNSAEncoding]) HasNSAEncoding = true;
1644 if (Bits[AMDGPU::FeatureNSAtoVMEMBug]) HasNSAtoVMEMBug = true;
1645 if (Bits[AMDGPU::FeatureNegativeScratchOffsetBug]) NegativeScratchOffsetBug = true;
1646 if (Bits[AMDGPU::FeatureNegativeUnalignedScratchOffsetBug]) NegativeUnalignedScratchOffsetBug = true;
1647 if (Bits[AMDGPU::FeatureNoDataDepHazard]) HasNoDataDepHazard = true;
1648 if (Bits[AMDGPU::FeatureNoSdstCMPX]) HasNoSdstCMPX = true;
1649 if (Bits[AMDGPU::FeatureOffset3fBug]) HasOffset3fBug = true;
1650 if (Bits[AMDGPU::FeaturePackedFP32Ops]) HasPackedFP32Ops = true;
1651 if (Bits[AMDGPU::FeaturePackedTID]) HasPackedTID = true;
1652 if (Bits[AMDGPU::FeaturePartialNSAEncoding]) HasPartialNSAEncoding = true;
1653 if (Bits[AMDGPU::FeaturePkFmacF16Inst]) HasPkFmacF16Inst = true;
1654 if (Bits[AMDGPU::FeaturePreciseMemory]) EnablePreciseMemory = true;
1655 if (Bits[AMDGPU::FeaturePrivEnabledTrap2NopBug]) HasPrivEnabledTrap2NopBug = true;
1656 if (Bits[AMDGPU::FeaturePromoteAlloca]) EnablePromoteAlloca = true;
1657 if (Bits[AMDGPU::FeaturePseudoScalarTrans]) HasPseudoScalarTrans = true;
1658 if (Bits[AMDGPU::FeatureR128A16]) HasR128A16 = true;
1659 if (Bits[AMDGPU::FeatureRealTrue16Insts]) EnableRealTrue16Insts = true;
1660 if (Bits[AMDGPU::FeatureRequiredExportPriority]) HasRequiredExportPriority = true;
1661 if (Bits[AMDGPU::FeatureRequiresCOV6]) RequiresCOV6 = true;
1662 if (Bits[AMDGPU::FeatureSALUFloatInsts]) HasSALUFloatInsts = true;
1663 if (Bits[AMDGPU::FeatureSDWA]) HasSDWA = true;
1664 if (Bits[AMDGPU::FeatureSDWAMac]) HasSDWAMac = true;
1665 if (Bits[AMDGPU::FeatureSDWAOmod]) HasSDWAOmod = true;
1666 if (Bits[AMDGPU::FeatureSDWAOutModsVOPC]) HasSDWAOutModsVOPC = true;
1667 if (Bits[AMDGPU::FeatureSDWAScalar]) HasSDWAScalar = true;
1668 if (Bits[AMDGPU::FeatureSDWASdst]) HasSDWASdst = true;
1669 if (Bits[AMDGPU::FeatureSGPRInitBug]) SGPRInitBug = true;
1670 if (Bits[AMDGPU::FeatureSMEMtoVectorWriteHazard]) HasSMEMtoVectorWriteHazard = true;
1671 if (Bits[AMDGPU::FeatureSMemRealTime]) HasSMemRealTime = true;
1672 if (Bits[AMDGPU::FeatureSMemTimeInst]) HasSMemTimeInst = true;
1673 if (Bits[AMDGPU::FeatureSRAMECC]) EnableSRAMECC = true;
1674 if (Bits[AMDGPU::FeatureScalarAtomics]) HasScalarAtomics = true;
1675 if (Bits[AMDGPU::FeatureScalarDwordx3Loads]) HasScalarDwordx3Loads = true;
1676 if (Bits[AMDGPU::FeatureScalarFlatScratchInsts]) ScalarFlatScratchInsts = true;
1677 if (Bits[AMDGPU::FeatureScalarStores]) HasScalarStores = true;
1678 if (Bits[AMDGPU::FeatureSeaIslands] && Gen < GCNSubtarget::SEA_ISLANDS) Gen = GCNSubtarget::SEA_ISLANDS;
1679 if (Bits[AMDGPU::FeatureShaderCyclesHiLoRegisters]) HasShaderCyclesHiLoRegisters = true;
1680 if (Bits[AMDGPU::FeatureShaderCyclesRegister]) HasShaderCyclesRegister = true;
1681 if (Bits[AMDGPU::FeatureSouthernIslands] && Gen < GCNSubtarget::SOUTHERN_ISLANDS) Gen = GCNSubtarget::SOUTHERN_ISLANDS;
1682 if (Bits[AMDGPU::FeatureSupportsSRAMECC]) SupportsSRAMECC = true;
1683 if (Bits[AMDGPU::FeatureSupportsXNACK]) SupportsXNACK = true;
1684 if (Bits[AMDGPU::FeatureTgSplit]) EnableTgSplit = true;
1685 if (Bits[AMDGPU::FeatureTrapHandler]) TrapHandler = true;
1686 if (Bits[AMDGPU::FeatureTrigReducedRange]) HasTrigReducedRange = true;
1687 if (Bits[AMDGPU::FeatureTrue16BitInsts]) HasTrue16BitInsts = true;
1688 if (Bits[AMDGPU::FeatureUnalignedAccessMode]) UnalignedAccessMode = true;
1689 if (Bits[AMDGPU::FeatureUnalignedBufferAccess]) UnalignedBufferAccess = true;
1690 if (Bits[AMDGPU::FeatureUnalignedDSAccess]) UnalignedDSAccess = true;
1691 if (Bits[AMDGPU::FeatureUnalignedScratchAccess]) UnalignedScratchAccess = true;
1692 if (Bits[AMDGPU::FeatureUnpackedD16VMem]) HasUnpackedD16VMem = true;
1693 if (Bits[AMDGPU::FeatureUserSGPRInit16Bug]) UserSGPRInit16Bug = true;
1694 if (Bits[AMDGPU::FeatureVALUTransUseHazard]) HasVALUTransUseHazard = true;
1695 if (Bits[AMDGPU::FeatureVGPRIndexMode]) HasVGPRIndexMode = true;
1696 if (Bits[AMDGPU::FeatureVGPRSingleUseHintInsts]) HasVGPRSingleUseHintInsts = true;
1697 if (Bits[AMDGPU::FeatureVMEMtoScalarWriteHazard]) HasVMEMtoScalarWriteHazard = true;
1698 if (Bits[AMDGPU::FeatureVOP3Literal]) HasVOP3Literal = true;
1699 if (Bits[AMDGPU::FeatureVOP3P]) HasVOP3PInsts = true;
1700 if (Bits[AMDGPU::FeatureVOPD]) HasVOPDInsts = true;
1701 if (Bits[AMDGPU::FeatureVcmpxExecWARHazard]) HasVcmpxExecWARHazard = true;
1702 if (Bits[AMDGPU::FeatureVcmpxPermlaneHazard]) HasVcmpxPermlaneHazard = true;
1703 if (Bits[AMDGPU::FeatureVmemWriteVgprInOrder]) HasVmemWriteVgprInOrder = true;
1704 if (Bits[AMDGPU::FeatureVolcanicIslands] && Gen < GCNSubtarget::VOLCANIC_ISLANDS) Gen = GCNSubtarget::VOLCANIC_ISLANDS;
1705 if (Bits[AMDGPU::FeatureVscnt]) HasVscnt = true;
1706 if (Bits[AMDGPU::FeatureWavefrontSize16] && WavefrontSizeLog2 < 4) WavefrontSizeLog2 = 4;
1707 if (Bits[AMDGPU::FeatureWavefrontSize32] && WavefrontSizeLog2 < 5) WavefrontSizeLog2 = 5;
1708 if (Bits[AMDGPU::FeatureWavefrontSize64] && WavefrontSizeLog2 < 6) WavefrontSizeLog2 = 6;
1709 if (Bits[AMDGPU::FeatureXNACK]) EnableXNACK = true;
1710 if (Bits[AMDGPU::FullRate64Ops]) FullRate64Ops = true;
1711 if (Bits[AMDGPU::HalfRate64Ops]) HalfRate64Ops = true;
1712}
1713#endif // GET_SUBTARGETINFO_TARGET_DESC
1714
1715
1716#ifdef GET_SUBTARGETINFO_HEADER
1717#undef GET_SUBTARGETINFO_HEADER
1718
1719namespace llvm {
1720class DFAPacketizer;
1721namespace AMDGPU_MC {
1722unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
1723} // end namespace AMDGPU_MC
1724
1725struct AMDGPUGenSubtargetInfo : public TargetSubtargetInfo {
1726 explicit AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
1727public:
1728 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
1729 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
1730 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
1731};
1732} // end namespace llvm
1733
1734#endif // GET_SUBTARGETINFO_HEADER
1735
1736
1737#ifdef GET_SUBTARGETINFO_CTOR
1738#undef GET_SUBTARGETINFO_CTOR
1739
1740#include "llvm/CodeGen/TargetSchedule.h"
1741
1742namespace llvm {
1743extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[];
1744extern const llvm::SubtargetSubTypeKV AMDGPUSubTypeKV[];
1745extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[];
1746extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[];
1747extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[];
1748AMDGPUGenSubtargetInfo::AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
1749 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(AMDGPUFeatureKV, 188), ArrayRef(AMDGPUSubTypeKV, 70),
1750 AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable,
1751 nullptr, nullptr, nullptr) {}
1752
1753unsigned AMDGPUGenSubtargetInfo
1754::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
1755
1756 const SIInstrInfo *TII =
1757 static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());
1758 (void)TII;
1759
1760 switch (SchedClass) {
1761 case 32: // COPY
1762 if (SchedModel->getProcessorID() == 1) { // SIQuarterSpeedModel
1763 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32)
1764 return 48; // Write32Bit
1765 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32)
1766 return 49; // Write64Bit
1767 return 50; // WriteSALU
1768 }
1769 if (SchedModel->getProcessorID() == 2) { // GFX10SpeedModel
1770 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32)
1771 return 48; // Write32Bit
1772 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32)
1773 return 49; // Write64Bit
1774 return 50; // WriteSALU
1775 }
1776 if (SchedModel->getProcessorID() == 3) { // GFX11SpeedModel
1777 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32)
1778 return 48; // Write32Bit
1779 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32)
1780 return 49; // Write64Bit
1781 return 50; // WriteSALU
1782 }
1783 if (SchedModel->getProcessorID() == 4) { // GFX12SpeedModel
1784 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32)
1785 return 48; // Write32Bit
1786 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32)
1787 return 49; // Write64Bit
1788 return 50; // WriteSALU
1789 }
1790 if (SchedModel->getProcessorID() == 5) { // SIFullSpeedModel
1791 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32)
1792 return 48; // Write32Bit
1793 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32)
1794 return 49; // Write64Bit
1795 return 50; // WriteSALU
1796 }
1797 if (SchedModel->getProcessorID() == 6) { // SIDPFullSpeedModel
1798 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32)
1799 return 48; // Write32Bit
1800 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32)
1801 return 49; // Write64Bit
1802 return 50; // WriteSALU
1803 }
1804 if (SchedModel->getProcessorID() == 7) { // SIDPGFX940FullSpeedModel
1805 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32)
1806 return 48; // Write32Bit
1807 if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32)
1808 return 49; // Write64Bit
1809 return 50; // WriteSALU
1810 }
1811 break;
1812 case 33: // V_ACCVGPR_WRITE_B32_e64
1813 if (SchedModel->getProcessorID() == 1) { // SIQuarterSpeedModel
1814 if (TII->hasVGPRUses(*MI))
1815 return 51; // Write64Bit_MIVGPRRead
1816 return 52; // Write64Bit_ReadDefault
1817 }
1818 break;
1819 };
1820 report_fatal_error("Expected a variant SchedClass");
1821} // AMDGPUGenSubtargetInfo::resolveSchedClass
1822
1823unsigned AMDGPUGenSubtargetInfo
1824::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
1825 return AMDGPU_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
1826} // AMDGPUGenSubtargetInfo::resolveVariantSchedClass
1827
1828} // end namespace llvm
1829
1830#endif // GET_SUBTARGETINFO_CTOR
1831
1832
1833#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
1834#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
1835
1836#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
1837
1838
1839#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
1840#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
1841
1842#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
1843
1844