| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Global Instruction Selector for the ARM target *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 10 | const unsigned MAX_SUBTARGET_PREDICATES = 87; |
| 11 | using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>; |
| 12 | #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 13 | |
| 14 | #ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 15 | mutable MatcherState State; |
| 16 | typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; |
| 17 | typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; |
| 18 | const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo; |
| 19 | static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; |
| 20 | static ARMInstructionSelector::CustomRendererFn CustomRenderers[]; |
| 21 | bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; |
| 22 | bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; |
| 23 | bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; |
| 24 | const uint8_t *getMatchTable() const override; |
| 25 | bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; |
| 26 | bool testSimplePredicate(unsigned PredicateID) const override; |
| 27 | bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override; |
| 28 | #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 29 | |
| 30 | #ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 31 | , State(0), |
| 32 | ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) |
| 33 | #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 34 | |
| 35 | #ifdef GET_GLOBALISEL_IMPL |
| 36 | // LLT Objects. |
| 37 | enum { |
| 38 | GILLT_s16, |
| 39 | GILLT_s32, |
| 40 | GILLT_s64, |
| 41 | GILLT_v2s1, |
| 42 | GILLT_v2s32, |
| 43 | GILLT_v2s64, |
| 44 | GILLT_v4s1, |
| 45 | GILLT_v4s16, |
| 46 | GILLT_v4s32, |
| 47 | GILLT_v4s64, |
| 48 | GILLT_v8s1, |
| 49 | GILLT_v8s8, |
| 50 | GILLT_v8s16, |
| 51 | GILLT_v8s64, |
| 52 | GILLT_v16s1, |
| 53 | GILLT_v16s8, |
| 54 | }; |
| 55 | const static size_t NumTypeObjects = 16; |
| 56 | const static LLT TypeObjects[] = { |
| 57 | LLT::scalar(16), |
| 58 | LLT::scalar(32), |
| 59 | LLT::scalar(64), |
| 60 | LLT::vector(ElementCount::getFixed(2), 1), |
| 61 | LLT::vector(ElementCount::getFixed(2), 32), |
| 62 | LLT::vector(ElementCount::getFixed(2), 64), |
| 63 | LLT::vector(ElementCount::getFixed(4), 1), |
| 64 | LLT::vector(ElementCount::getFixed(4), 16), |
| 65 | LLT::vector(ElementCount::getFixed(4), 32), |
| 66 | LLT::vector(ElementCount::getFixed(4), 64), |
| 67 | LLT::vector(ElementCount::getFixed(8), 1), |
| 68 | LLT::vector(ElementCount::getFixed(8), 8), |
| 69 | LLT::vector(ElementCount::getFixed(8), 16), |
| 70 | LLT::vector(ElementCount::getFixed(8), 64), |
| 71 | LLT::vector(ElementCount::getFixed(16), 1), |
| 72 | LLT::vector(ElementCount::getFixed(16), 8), |
| 73 | }; |
| 74 | |
| 75 | // Bits for subtarget features that participate in instruction matching. |
| 76 | enum SubtargetFeatureBits : uint8_t { |
| 77 | Feature_NoHonorSignDependentRoundingBit = 78, |
| 78 | Feature_HasV4TBit = 6, |
| 79 | Feature_NoV4TBit = 7, |
| 80 | Feature_HasV5TBit = 13, |
| 81 | Feature_NoV5TBit = 67, |
| 82 | Feature_HasV5TEBit = 11, |
| 83 | Feature_HasV6Bit = 0, |
| 84 | Feature_NoV6Bit = 9, |
| 85 | Feature_HasV6MBit = 28, |
| 86 | Feature_HasV8MBaselineBit = 35, |
| 87 | Feature_HasV8_1MMainlineBit = 41, |
| 88 | Feature_HasMVEIntBit = 65, |
| 89 | Feature_HasMVEFloatBit = 66, |
| 90 | Feature_HasCDEBit = 86, |
| 91 | Feature_HasFPRegsBit = 42, |
| 92 | Feature_HasFPRegs16Bit = 43, |
| 93 | Feature_HasNoFPRegs16Bit = 77, |
| 94 | Feature_HasFPRegs64Bit = 52, |
| 95 | Feature_HasV6T2Bit = 8, |
| 96 | Feature_HasV6KBit = 18, |
| 97 | Feature_HasV7Bit = 3, |
| 98 | Feature_HasV8Bit = 56, |
| 99 | Feature_PreV8Bit = 19, |
| 100 | Feature_HasV8_1aBit = 80, |
| 101 | Feature_HasV8_3aBit = 81, |
| 102 | Feature_NoVFPBit = 22, |
| 103 | Feature_HasVFP2Bit = 21, |
| 104 | Feature_HasVFP3Bit = 53, |
| 105 | Feature_HasVFP4Bit = 50, |
| 106 | Feature_HasDPVFPBit = 44, |
| 107 | Feature_HasFPARMv8Bit = 47, |
| 108 | Feature_HasNEONBit = 54, |
| 109 | Feature_HasSHA2Bit = 63, |
| 110 | Feature_HasAESBit = 55, |
| 111 | Feature_HasDotProdBit = 57, |
| 112 | Feature_HasCRCBit = 14, |
| 113 | Feature_HasLOBBit = 40, |
| 114 | Feature_HasFP16Bit = 62, |
| 115 | Feature_HasFullFP16Bit = 46, |
| 116 | Feature_HasBF16Bit = 64, |
| 117 | Feature_HasMatMulInt8Bit = 58, |
| 118 | Feature_HasDivideInThumbBit = 37, |
| 119 | Feature_HasDivideInARMBit = 12, |
| 120 | Feature_HasDSPBit = 36, |
| 121 | Feature_HasDBBit = 15, |
| 122 | Feature_HasV7ClrexBit = 17, |
| 123 | Feature_HasAcquireReleaseBit = 16, |
| 124 | Feature_HasMPBit = 2, |
| 125 | Feature_Has8MSecExtBit = 29, |
| 126 | Feature_HasZCZBit = 59, |
| 127 | Feature_UseNEONForFPBit = 84, |
| 128 | Feature_DontUseNEONForFPBit = 45, |
| 129 | Feature_IsThumbBit = 26, |
| 130 | Feature_IsThumb1OnlyBit = 27, |
| 131 | Feature_IsThumb2Bit = 34, |
| 132 | Feature_IsNotMClassBit = 38, |
| 133 | Feature_IsARMBit = 1, |
| 134 | Feature_IsWindowsBit = 30, |
| 135 | Feature_IsNotWindowsBit = 31, |
| 136 | Feature_IsReadTPTPIDRURWBit = 70, |
| 137 | Feature_IsReadTPTPIDRUROBit = 71, |
| 138 | Feature_IsReadTPTPIDRPRWBit = 72, |
| 139 | Feature_IsReadTPSoftBit = 20, |
| 140 | Feature_UseNaClTrapBit = 4, |
| 141 | Feature_DontUseNaClTrapBit = 5, |
| 142 | Feature_UseMovtBit = 39, |
| 143 | Feature_DontUseMovtBit = 23, |
| 144 | Feature_UseMovtInPicBit = 24, |
| 145 | Feature_DontUseMovtInPicBit = 25, |
| 146 | Feature_UseFPVMLxBit = 49, |
| 147 | Feature_SLSBLRMitigationBit = 69, |
| 148 | Feature_NoSLSBLRMitigationBit = 68, |
| 149 | Feature_UseMulOpsBit = 10, |
| 150 | Feature_UseFusedMACBit = 51, |
| 151 | Feature_HasFastVGETLNi32Bit = 60, |
| 152 | Feature_HasSlowVGETLNi32Bit = 82, |
| 153 | Feature_HasFastVDUP32Bit = 61, |
| 154 | Feature_HasSlowVDUP32Bit = 83, |
| 155 | Feature_UseVMOVSRBit = 48, |
| 156 | Feature_DontUseVMOVSRBit = 85, |
| 157 | Feature_IsLEBit = 76, |
| 158 | Feature_IsBEBit = 79, |
| 159 | Feature_GenExecuteOnlyBit = 33, |
| 160 | Feature_DontGenExecuteOnlyBit = 32, |
| 161 | Feature_GenT1ExecuteOnlyBit = 75, |
| 162 | Feature_SignRetAddrBit = 74, |
| 163 | Feature_NoSignRetAddrBit = 73, |
| 164 | }; |
| 165 | |
| 166 | PredicateBitset ARMInstructionSelector:: |
| 167 | computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const { |
| 168 | PredicateBitset Features{}; |
| 169 | if (!TM.Options.HonorSignDependentRoundingFPMath()) |
| 170 | Features.set(Feature_NoHonorSignDependentRoundingBit); |
| 171 | if (Subtarget->hasV4TOps()) |
| 172 | Features.set(Feature_HasV4TBit); |
| 173 | if (!Subtarget->hasV4TOps()) |
| 174 | Features.set(Feature_NoV4TBit); |
| 175 | if (Subtarget->hasV5TOps()) |
| 176 | Features.set(Feature_HasV5TBit); |
| 177 | if (!Subtarget->hasV5TOps()) |
| 178 | Features.set(Feature_NoV5TBit); |
| 179 | if (Subtarget->hasV5TEOps()) |
| 180 | Features.set(Feature_HasV5TEBit); |
| 181 | if (Subtarget->hasV6Ops()) |
| 182 | Features.set(Feature_HasV6Bit); |
| 183 | if (!Subtarget->hasV6Ops()) |
| 184 | Features.set(Feature_NoV6Bit); |
| 185 | if (Subtarget->hasV6MOps()) |
| 186 | Features.set(Feature_HasV6MBit); |
| 187 | if (Subtarget->hasV8MBaselineOps()) |
| 188 | Features.set(Feature_HasV8MBaselineBit); |
| 189 | if (Subtarget->hasV8_1MMainlineOps()) |
| 190 | Features.set(Feature_HasV8_1MMainlineBit); |
| 191 | if (Subtarget->hasMVEIntegerOps()) |
| 192 | Features.set(Feature_HasMVEIntBit); |
| 193 | if (Subtarget->hasMVEFloatOps()) |
| 194 | Features.set(Feature_HasMVEFloatBit); |
| 195 | if (Subtarget->hasCDEOps()) |
| 196 | Features.set(Feature_HasCDEBit); |
| 197 | if (Subtarget->hasFPRegs()) |
| 198 | Features.set(Feature_HasFPRegsBit); |
| 199 | if (Subtarget->hasFPRegs16()) |
| 200 | Features.set(Feature_HasFPRegs16Bit); |
| 201 | if (!Subtarget->hasFPRegs16()) |
| 202 | Features.set(Feature_HasNoFPRegs16Bit); |
| 203 | if (Subtarget->hasFPRegs64()) |
| 204 | Features.set(Feature_HasFPRegs64Bit); |
| 205 | if (Subtarget->hasV6T2Ops()) |
| 206 | Features.set(Feature_HasV6T2Bit); |
| 207 | if (Subtarget->hasV6KOps()) |
| 208 | Features.set(Feature_HasV6KBit); |
| 209 | if (Subtarget->hasV7Ops()) |
| 210 | Features.set(Feature_HasV7Bit); |
| 211 | if (Subtarget->hasV8Ops()) |
| 212 | Features.set(Feature_HasV8Bit); |
| 213 | if (!Subtarget->hasV8Ops()) |
| 214 | Features.set(Feature_PreV8Bit); |
| 215 | if (Subtarget->hasV8_1aOps()) |
| 216 | Features.set(Feature_HasV8_1aBit); |
| 217 | if (Subtarget->hasV8_3aOps()) |
| 218 | Features.set(Feature_HasV8_3aBit); |
| 219 | if (!Subtarget->hasVFP2Base()) |
| 220 | Features.set(Feature_NoVFPBit); |
| 221 | if (Subtarget->hasVFP2Base()) |
| 222 | Features.set(Feature_HasVFP2Bit); |
| 223 | if (Subtarget->hasVFP3Base()) |
| 224 | Features.set(Feature_HasVFP3Bit); |
| 225 | if (Subtarget->hasVFP4Base()) |
| 226 | Features.set(Feature_HasVFP4Bit); |
| 227 | if (Subtarget->hasFP64()) |
| 228 | Features.set(Feature_HasDPVFPBit); |
| 229 | if (Subtarget->hasFPARMv8Base()) |
| 230 | Features.set(Feature_HasFPARMv8Bit); |
| 231 | if (Subtarget->hasNEON()) |
| 232 | Features.set(Feature_HasNEONBit); |
| 233 | if (Subtarget->hasSHA2()) |
| 234 | Features.set(Feature_HasSHA2Bit); |
| 235 | if (Subtarget->hasAES()) |
| 236 | Features.set(Feature_HasAESBit); |
| 237 | if (Subtarget->hasDotProd()) |
| 238 | Features.set(Feature_HasDotProdBit); |
| 239 | if (Subtarget->hasCRC()) |
| 240 | Features.set(Feature_HasCRCBit); |
| 241 | if (Subtarget->hasLOB()) |
| 242 | Features.set(Feature_HasLOBBit); |
| 243 | if (Subtarget->hasFP16()) |
| 244 | Features.set(Feature_HasFP16Bit); |
| 245 | if (Subtarget->hasFullFP16()) |
| 246 | Features.set(Feature_HasFullFP16Bit); |
| 247 | if (Subtarget->hasBF16()) |
| 248 | Features.set(Feature_HasBF16Bit); |
| 249 | if (Subtarget->hasMatMulInt8()) |
| 250 | Features.set(Feature_HasMatMulInt8Bit); |
| 251 | if (Subtarget->hasDivideInThumbMode()) |
| 252 | Features.set(Feature_HasDivideInThumbBit); |
| 253 | if (Subtarget->hasDivideInARMMode()) |
| 254 | Features.set(Feature_HasDivideInARMBit); |
| 255 | if (Subtarget->hasDSP()) |
| 256 | Features.set(Feature_HasDSPBit); |
| 257 | if (Subtarget->hasDataBarrier()) |
| 258 | Features.set(Feature_HasDBBit); |
| 259 | if (Subtarget->hasV7Clrex()) |
| 260 | Features.set(Feature_HasV7ClrexBit); |
| 261 | if (Subtarget->hasAcquireRelease()) |
| 262 | Features.set(Feature_HasAcquireReleaseBit); |
| 263 | if (Subtarget->hasMPExtension()) |
| 264 | Features.set(Feature_HasMPBit); |
| 265 | if (Subtarget->has8MSecExt()) |
| 266 | Features.set(Feature_Has8MSecExtBit); |
| 267 | if (Subtarget->hasZeroCycleZeroing()) |
| 268 | Features.set(Feature_HasZCZBit); |
| 269 | if (Subtarget->useNEONForSinglePrecisionFP()) |
| 270 | Features.set(Feature_UseNEONForFPBit); |
| 271 | if (!Subtarget->useNEONForSinglePrecisionFP()) |
| 272 | Features.set(Feature_DontUseNEONForFPBit); |
| 273 | if (Subtarget->isThumb()) |
| 274 | Features.set(Feature_IsThumbBit); |
| 275 | if (Subtarget->isThumb1Only()) |
| 276 | Features.set(Feature_IsThumb1OnlyBit); |
| 277 | if (Subtarget->isThumb2()) |
| 278 | Features.set(Feature_IsThumb2Bit); |
| 279 | if (!Subtarget->isMClass()) |
| 280 | Features.set(Feature_IsNotMClassBit); |
| 281 | if (!Subtarget->isThumb()) |
| 282 | Features.set(Feature_IsARMBit); |
| 283 | if (Subtarget->isTargetWindows()) |
| 284 | Features.set(Feature_IsWindowsBit); |
| 285 | if (!Subtarget->isTargetWindows()) |
| 286 | Features.set(Feature_IsNotWindowsBit); |
| 287 | if (Subtarget->isReadTPTPIDRURW()) |
| 288 | Features.set(Feature_IsReadTPTPIDRURWBit); |
| 289 | if (Subtarget->isReadTPTPIDRURO()) |
| 290 | Features.set(Feature_IsReadTPTPIDRUROBit); |
| 291 | if (Subtarget->isReadTPTPIDRPRW()) |
| 292 | Features.set(Feature_IsReadTPTPIDRPRWBit); |
| 293 | if (Subtarget->isReadTPSoft()) |
| 294 | Features.set(Feature_IsReadTPSoftBit); |
| 295 | if (Subtarget->useNaClTrap()) |
| 296 | Features.set(Feature_UseNaClTrapBit); |
| 297 | if (!Subtarget->useNaClTrap()) |
| 298 | Features.set(Feature_DontUseNaClTrapBit); |
| 299 | if (Subtarget->useMulOps()) |
| 300 | Features.set(Feature_UseMulOpsBit); |
| 301 | if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->useFPVFMx()) |
| 302 | Features.set(Feature_UseFusedMACBit); |
| 303 | if (!Subtarget->hasSlowVGETLNi32()) |
| 304 | Features.set(Feature_HasFastVGETLNi32Bit); |
| 305 | if (Subtarget->hasSlowVGETLNi32()) |
| 306 | Features.set(Feature_HasSlowVGETLNi32Bit); |
| 307 | if (!Subtarget->hasSlowVDUP32()) |
| 308 | Features.set(Feature_HasFastVDUP32Bit); |
| 309 | if (Subtarget->hasSlowVDUP32()) |
| 310 | Features.set(Feature_HasSlowVDUP32Bit); |
| 311 | if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP()) |
| 312 | Features.set(Feature_UseVMOVSRBit); |
| 313 | if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP()) |
| 314 | Features.set(Feature_DontUseVMOVSRBit); |
| 315 | if (Subtarget->genExecuteOnly()) |
| 316 | Features.set(Feature_GenExecuteOnlyBit); |
| 317 | if (!Subtarget->genExecuteOnly()) |
| 318 | Features.set(Feature_DontGenExecuteOnlyBit); |
| 319 | if (Subtarget->genExecuteOnly() && Subtarget->isThumb1Only() && !Subtarget->hasV8MBaselineOps()) |
| 320 | Features.set(Feature_GenT1ExecuteOnlyBit); |
| 321 | return Features; |
| 322 | } |
| 323 | |
| 324 | void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { |
| 325 | AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF); |
| 326 | } |
| 327 | PredicateBitset ARMInstructionSelector:: |
| 328 | computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const { |
| 329 | PredicateBitset Features{}; |
| 330 | if (Subtarget->useMovt()) |
| 331 | Features.set(Feature_UseMovtBit); |
| 332 | if (!Subtarget->useMovt()) |
| 333 | Features.set(Feature_DontUseMovtBit); |
| 334 | if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt()) |
| 335 | Features.set(Feature_UseMovtInPicBit); |
| 336 | if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt()) |
| 337 | Features.set(Feature_DontUseMovtInPicBit); |
| 338 | if (((Subtarget->useFPVMLx() && TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize())) |
| 339 | Features.set(Feature_UseFPVMLxBit); |
| 340 | if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() ) |
| 341 | Features.set(Feature_SLSBLRMitigationBit); |
| 342 | if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() ) |
| 343 | Features.set(Feature_NoSLSBLRMitigationBit); |
| 344 | if (MF->getDataLayout().isLittleEndian()) |
| 345 | Features.set(Feature_IsLEBit); |
| 346 | if (MF->getDataLayout().isBigEndian()) |
| 347 | Features.set(Feature_IsBEBit); |
| 348 | if ( MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) ) |
| 349 | Features.set(Feature_SignRetAddrBit); |
| 350 | if ( !MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) ) |
| 351 | Features.set(Feature_NoSignRetAddrBit); |
| 352 | return Features; |
| 353 | } |
| 354 | |
| 355 | // Feature bitsets. |
| 356 | enum { |
| 357 | GIFBS_Invalid, |
| 358 | GIFBS_HasDotProd, |
| 359 | GIFBS_HasFP16, |
| 360 | GIFBS_HasFPARMv8, |
| 361 | GIFBS_HasFPRegs, |
| 362 | GIFBS_HasFullFP16, |
| 363 | GIFBS_HasMVEFloat, |
| 364 | GIFBS_HasMVEInt, |
| 365 | GIFBS_HasMatMulInt8, |
| 366 | GIFBS_HasNEON, |
| 367 | GIFBS_HasVFP2, |
| 368 | GIFBS_HasVFP3, |
| 369 | GIFBS_HasVFP4, |
| 370 | GIFBS_IsARM, |
| 371 | GIFBS_IsThumb, |
| 372 | GIFBS_IsThumb2, |
| 373 | GIFBS_NoHonorSignDependentRounding, |
| 374 | GIFBS_DontUseNEONForFP_HasVFP2, |
| 375 | GIFBS_DontUseNaClTrap_IsARM, |
| 376 | GIFBS_DontUseVMOVSR_HasNEON, |
| 377 | GIFBS_Has8MSecExt_IsThumb, |
| 378 | GIFBS_HasAES_HasV8, |
| 379 | GIFBS_HasBF16_HasNEON, |
| 380 | GIFBS_HasCRC_IsARM, |
| 381 | GIFBS_HasCRC_IsThumb2, |
| 382 | GIFBS_HasDB_IsARM, |
| 383 | GIFBS_HasDB_IsThumb, |
| 384 | GIFBS_HasDPVFP_HasFPARMv8, |
| 385 | GIFBS_HasDPVFP_HasVFP2, |
| 386 | GIFBS_HasDPVFP_HasVFP3, |
| 387 | GIFBS_HasDPVFP_HasVFP4, |
| 388 | GIFBS_HasDPVFP_NoHonorSignDependentRounding, |
| 389 | GIFBS_HasDSP_IsThumb2, |
| 390 | GIFBS_HasDivideInARM_IsARM, |
| 391 | GIFBS_HasFP16_HasNEON, |
| 392 | GIFBS_HasFPARMv8_HasNEON, |
| 393 | GIFBS_HasFPRegs_HasFastVGETLNi32, |
| 394 | GIFBS_HasFPRegs_UseVMOVSR, |
| 395 | GIFBS_HasFullFP16_HasNEON, |
| 396 | GIFBS_HasMVEInt_HasV8_1MMainline, |
| 397 | GIFBS_HasMVEInt_IsBE, |
| 398 | GIFBS_HasMVEInt_IsLE, |
| 399 | GIFBS_HasNEON_HasV8, |
| 400 | GIFBS_HasNEON_HasV8_1a, |
| 401 | GIFBS_HasNEON_HasV8_3a, |
| 402 | GIFBS_HasNEON_HasVFP4, |
| 403 | GIFBS_HasNEON_IsBE, |
| 404 | GIFBS_HasNEON_IsLE, |
| 405 | GIFBS_HasNEON_UseNEONForFP, |
| 406 | GIFBS_HasSHA2_HasV8, |
| 407 | GIFBS_HasV5T_IsARM, |
| 408 | GIFBS_HasV5T_IsThumb, |
| 409 | GIFBS_HasV5TE_IsARM, |
| 410 | GIFBS_HasV6_IsARM, |
| 411 | GIFBS_HasV6K_IsARM, |
| 412 | GIFBS_HasV6M_IsThumb, |
| 413 | GIFBS_HasV6T2_IsARM, |
| 414 | GIFBS_HasV7_IsARM, |
| 415 | GIFBS_HasV7Clrex_IsThumb, |
| 416 | GIFBS_HasV8MBaseline_IsThumb, |
| 417 | GIFBS_IsARM_NoV5T, |
| 418 | GIFBS_IsARM_NoV6, |
| 419 | GIFBS_IsARM_PreV8, |
| 420 | GIFBS_IsARM_UseNaClTrap, |
| 421 | GIFBS_IsThumb_IsThumb1Only, |
| 422 | GIFBS_IsThumb_IsWindows, |
| 423 | GIFBS_IsThumb_NoV5T, |
| 424 | GIFBS_IsThumb_UseMovt, |
| 425 | GIFBS_IsThumb2_PreV8, |
| 426 | GIFBS_IsThumb2_UseMulOps, |
| 427 | GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only, |
| 428 | GIFBS_HasDSP_IsThumb2_UseMulOps, |
| 429 | GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb, |
| 430 | GIFBS_HasFPARMv8_HasFullFP16_HasNEON, |
| 431 | GIFBS_HasFullFP16_HasNEON_HasV8, |
| 432 | GIFBS_HasFullFP16_HasNEON_HasV8_3a, |
| 433 | GIFBS_HasFullFP16_HasNEON_UseFPVMLx, |
| 434 | GIFBS_HasFullFP16_HasNEON_UseFusedMAC, |
| 435 | GIFBS_HasLOB_HasV8_1MMainline_IsThumb2, |
| 436 | GIFBS_HasNEON_UseFPVMLx_UseNEONForFP, |
| 437 | GIFBS_HasV5TE_IsARM_UseMulOps, |
| 438 | GIFBS_HasV6_IsARM_UseMulOps, |
| 439 | GIFBS_HasV6_IsThumb_IsThumb1Only, |
| 440 | GIFBS_HasV6T2_IsARM_UseMulOps, |
| 441 | GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP, |
| 442 | GIFBS_IsARM_NoV6_UseMulOps, |
| 443 | }; |
| 444 | constexpr static PredicateBitset FeatureBitsets[] { |
| 445 | {}, // GIFBS_Invalid |
| 446 | {Feature_HasDotProdBit, }, |
| 447 | {Feature_HasFP16Bit, }, |
| 448 | {Feature_HasFPARMv8Bit, }, |
| 449 | {Feature_HasFPRegsBit, }, |
| 450 | {Feature_HasFullFP16Bit, }, |
| 451 | {Feature_HasMVEFloatBit, }, |
| 452 | {Feature_HasMVEIntBit, }, |
| 453 | {Feature_HasMatMulInt8Bit, }, |
| 454 | {Feature_HasNEONBit, }, |
| 455 | {Feature_HasVFP2Bit, }, |
| 456 | {Feature_HasVFP3Bit, }, |
| 457 | {Feature_HasVFP4Bit, }, |
| 458 | {Feature_IsARMBit, }, |
| 459 | {Feature_IsThumbBit, }, |
| 460 | {Feature_IsThumb2Bit, }, |
| 461 | {Feature_NoHonorSignDependentRoundingBit, }, |
| 462 | {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, }, |
| 463 | {Feature_DontUseNaClTrapBit, Feature_IsARMBit, }, |
| 464 | {Feature_DontUseVMOVSRBit, Feature_HasNEONBit, }, |
| 465 | {Feature_Has8MSecExtBit, Feature_IsThumbBit, }, |
| 466 | {Feature_HasAESBit, Feature_HasV8Bit, }, |
| 467 | {Feature_HasBF16Bit, Feature_HasNEONBit, }, |
| 468 | {Feature_HasCRCBit, Feature_IsARMBit, }, |
| 469 | {Feature_HasCRCBit, Feature_IsThumb2Bit, }, |
| 470 | {Feature_HasDBBit, Feature_IsARMBit, }, |
| 471 | {Feature_HasDBBit, Feature_IsThumbBit, }, |
| 472 | {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, }, |
| 473 | {Feature_HasDPVFPBit, Feature_HasVFP2Bit, }, |
| 474 | {Feature_HasDPVFPBit, Feature_HasVFP3Bit, }, |
| 475 | {Feature_HasDPVFPBit, Feature_HasVFP4Bit, }, |
| 476 | {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, }, |
| 477 | {Feature_HasDSPBit, Feature_IsThumb2Bit, }, |
| 478 | {Feature_HasDivideInARMBit, Feature_IsARMBit, }, |
| 479 | {Feature_HasFP16Bit, Feature_HasNEONBit, }, |
| 480 | {Feature_HasFPARMv8Bit, Feature_HasNEONBit, }, |
| 481 | {Feature_HasFPRegsBit, Feature_HasFastVGETLNi32Bit, }, |
| 482 | {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, }, |
| 483 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, }, |
| 484 | {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, }, |
| 485 | {Feature_HasMVEIntBit, Feature_IsBEBit, }, |
| 486 | {Feature_HasMVEIntBit, Feature_IsLEBit, }, |
| 487 | {Feature_HasNEONBit, Feature_HasV8Bit, }, |
| 488 | {Feature_HasNEONBit, Feature_HasV8_1aBit, }, |
| 489 | {Feature_HasNEONBit, Feature_HasV8_3aBit, }, |
| 490 | {Feature_HasNEONBit, Feature_HasVFP4Bit, }, |
| 491 | {Feature_HasNEONBit, Feature_IsBEBit, }, |
| 492 | {Feature_HasNEONBit, Feature_IsLEBit, }, |
| 493 | {Feature_HasNEONBit, Feature_UseNEONForFPBit, }, |
| 494 | {Feature_HasSHA2Bit, Feature_HasV8Bit, }, |
| 495 | {Feature_HasV5TBit, Feature_IsARMBit, }, |
| 496 | {Feature_HasV5TBit, Feature_IsThumbBit, }, |
| 497 | {Feature_HasV5TEBit, Feature_IsARMBit, }, |
| 498 | {Feature_HasV6Bit, Feature_IsARMBit, }, |
| 499 | {Feature_HasV6KBit, Feature_IsARMBit, }, |
| 500 | {Feature_HasV6MBit, Feature_IsThumbBit, }, |
| 501 | {Feature_HasV6T2Bit, Feature_IsARMBit, }, |
| 502 | {Feature_HasV7Bit, Feature_IsARMBit, }, |
| 503 | {Feature_HasV7ClrexBit, Feature_IsThumbBit, }, |
| 504 | {Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, |
| 505 | {Feature_IsARMBit, Feature_NoV5TBit, }, |
| 506 | {Feature_IsARMBit, Feature_NoV6Bit, }, |
| 507 | {Feature_IsARMBit, Feature_PreV8Bit, }, |
| 508 | {Feature_IsARMBit, Feature_UseNaClTrapBit, }, |
| 509 | {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, |
| 510 | {Feature_IsThumbBit, Feature_IsWindowsBit, }, |
| 511 | {Feature_IsThumbBit, Feature_NoV5TBit, }, |
| 512 | {Feature_IsThumbBit, Feature_UseMovtBit, }, |
| 513 | {Feature_IsThumb2Bit, Feature_PreV8Bit, }, |
| 514 | {Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, |
| 515 | {Feature_DontUseMovtBit, Feature_GenExecuteOnlyBit, Feature_IsThumb1OnlyBit, }, |
| 516 | {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, |
| 517 | {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, |
| 518 | {Feature_HasFPARMv8Bit, Feature_HasFullFP16Bit, Feature_HasNEONBit, }, |
| 519 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, }, |
| 520 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, }, |
| 521 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, }, |
| 522 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, }, |
| 523 | {Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, }, |
| 524 | {Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, }, |
| 525 | {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 526 | {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 527 | {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, |
| 528 | {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 529 | {Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, }, |
| 530 | {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, }, |
| 531 | }; |
| 532 | |
| 533 | // ComplexPattern predicates. |
| 534 | enum { |
| 535 | GICP_Invalid, |
| 536 | }; |
| 537 | // See constructor for table contents |
| 538 | |
| 539 | ARMInstructionSelector::ComplexMatcherMemFn |
| 540 | ARMInstructionSelector::ComplexPredicateFns[] = { |
| 541 | nullptr, // GICP_Invalid |
| 542 | }; |
| 543 | |
| 544 | // PatFrag predicates. |
| 545 | enum { |
| 546 | GICXXPred_MI_Predicate_bf_inv_mask_imm = GICXXPred_Invalid + 1, |
| 547 | GICXXPred_MI_Predicate_vfp_f32imm, |
| 548 | GICXXPred_MI_Predicate_vfp_f64imm, |
| 549 | }; |
| 550 | bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const { |
| 551 | const MachineFunction &MF = *MI.getParent()->getParent(); |
| 552 | const MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 553 | const auto &Operands = State.RecordedOperands; |
| 554 | (void)Operands; |
| 555 | (void)MRI; |
| 556 | switch (PredicateID) { |
| 557 | case GICXXPred_MI_Predicate_bf_inv_mask_imm: { |
| 558 | |
| 559 | // There's better methods of implementing this check. IntImmLeaf<> would be |
| 560 | // equivalent and have less boilerplate but we need a test for C++ |
| 561 | // predicates and this one causes new rules to be imported into GlobalISel |
| 562 | // without requiring additional features first. |
| 563 | const auto &MO = MI.getOperand(1); |
| 564 | if (!MO.isCImm()) |
| 565 | return false; |
| 566 | return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); |
| 567 | |
| 568 | llvm_unreachable("bf_inv_mask_imm should have returned"); |
| 569 | } |
| 570 | case GICXXPred_MI_Predicate_vfp_f32imm: { |
| 571 | |
| 572 | const auto &MO = MI.getOperand(1); |
| 573 | if (!MO.isFPImm()) |
| 574 | return false; |
| 575 | return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1; |
| 576 | |
| 577 | llvm_unreachable("vfp_f32imm should have returned"); |
| 578 | } |
| 579 | case GICXXPred_MI_Predicate_vfp_f64imm: { |
| 580 | |
| 581 | const auto &MO = MI.getOperand(1); |
| 582 | if (!MO.isFPImm()) |
| 583 | return false; |
| 584 | return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1; |
| 585 | |
| 586 | llvm_unreachable("vfp_f64imm should have returned"); |
| 587 | } |
| 588 | } |
| 589 | llvm_unreachable("Unknown predicate"); |
| 590 | return false; |
| 591 | } |
| 592 | // PatFrag predicates. |
| 593 | enum { |
| 594 | GICXXPred_I64_Predicate_VectorIndex8 = GICXXPred_Invalid + 1, |
| 595 | GICXXPred_I64_Predicate_VectorIndex16, |
| 596 | GICXXPred_I64_Predicate_VectorIndex32, |
| 597 | GICXXPred_I64_Predicate_VectorIndex64, |
| 598 | GICXXPred_I64_Predicate_asr_imm, |
| 599 | GICXXPred_I64_Predicate_imm0_7, |
| 600 | GICXXPred_I64_Predicate_imm0_15, |
| 601 | GICXXPred_I64_Predicate_imm0_31, |
| 602 | GICXXPred_I64_Predicate_imm0_32, |
| 603 | GICXXPred_I64_Predicate_imm0_63, |
| 604 | GICXXPred_I64_Predicate_imm0_239, |
| 605 | GICXXPred_I64_Predicate_imm0_255, |
| 606 | GICXXPred_I64_Predicate_imm0_255_expr, |
| 607 | GICXXPred_I64_Predicate_imm0_4095, |
| 608 | GICXXPred_I64_Predicate_imm0_65535, |
| 609 | GICXXPred_I64_Predicate_imm0_65535_expr, |
| 610 | GICXXPred_I64_Predicate_imm0_65535_neg, |
| 611 | GICXXPred_I64_Predicate_imm1_7, |
| 612 | GICXXPred_I64_Predicate_imm1_15, |
| 613 | GICXXPred_I64_Predicate_imm1_16, |
| 614 | GICXXPred_I64_Predicate_imm1_31, |
| 615 | GICXXPred_I64_Predicate_imm8, |
| 616 | GICXXPred_I64_Predicate_imm8_255, |
| 617 | GICXXPred_I64_Predicate_imm8_or_16, |
| 618 | GICXXPred_I64_Predicate_imm16, |
| 619 | GICXXPred_I64_Predicate_imm16_31, |
| 620 | GICXXPred_I64_Predicate_imm24b, |
| 621 | GICXXPred_I64_Predicate_imm32, |
| 622 | GICXXPred_I64_Predicate_imm256_510, |
| 623 | GICXXPred_I64_Predicate_imm_3b, |
| 624 | GICXXPred_I64_Predicate_imm_4b, |
| 625 | GICXXPred_I64_Predicate_imm_6b, |
| 626 | GICXXPred_I64_Predicate_imm_7b, |
| 627 | GICXXPred_I64_Predicate_imm_9b, |
| 628 | GICXXPred_I64_Predicate_imm_11b, |
| 629 | GICXXPred_I64_Predicate_imm_12b, |
| 630 | GICXXPred_I64_Predicate_imm_13b, |
| 631 | GICXXPred_I64_Predicate_imm_even, |
| 632 | GICXXPred_I64_Predicate_imm_odd, |
| 633 | GICXXPred_I64_Predicate_long_shift, |
| 634 | GICXXPred_I64_Predicate_mod_imm, |
| 635 | GICXXPred_I64_Predicate_mod_imm_not, |
| 636 | GICXXPred_I64_Predicate_pkh_asr_amt, |
| 637 | GICXXPred_I64_Predicate_pkh_lsl_amt, |
| 638 | GICXXPred_I64_Predicate_shr_imm8, |
| 639 | GICXXPred_I64_Predicate_shr_imm16, |
| 640 | GICXXPred_I64_Predicate_shr_imm32, |
| 641 | GICXXPred_I64_Predicate_shr_imm64, |
| 642 | GICXXPred_I64_Predicate_t2_so_imm, |
| 643 | GICXXPred_I64_Predicate_t2_so_imm_neg, |
| 644 | }; |
| 645 | bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { |
| 646 | switch (PredicateID) { |
| 647 | case GICXXPred_I64_Predicate_VectorIndex8: { |
| 648 | |
| 649 | return ((uint64_t)Imm) < 8; |
| 650 | |
| 651 | } |
| 652 | case GICXXPred_I64_Predicate_VectorIndex16: { |
| 653 | |
| 654 | return ((uint64_t)Imm) < 4; |
| 655 | |
| 656 | } |
| 657 | case GICXXPred_I64_Predicate_VectorIndex32: { |
| 658 | |
| 659 | return ((uint64_t)Imm) < 2; |
| 660 | |
| 661 | } |
| 662 | case GICXXPred_I64_Predicate_VectorIndex64: { |
| 663 | |
| 664 | return ((uint64_t)Imm) < 1; |
| 665 | |
| 666 | } |
| 667 | case GICXXPred_I64_Predicate_asr_imm: { |
| 668 | return Imm > 0 && Imm <= 32; |
| 669 | } |
| 670 | case GICXXPred_I64_Predicate_imm0_7: { |
| 671 | |
| 672 | return Imm >= 0 && Imm < 8; |
| 673 | |
| 674 | } |
| 675 | case GICXXPred_I64_Predicate_imm0_15: { |
| 676 | |
| 677 | return Imm >= 0 && Imm < 16; |
| 678 | |
| 679 | } |
| 680 | case GICXXPred_I64_Predicate_imm0_31: { |
| 681 | |
| 682 | return Imm >= 0 && Imm < 32; |
| 683 | |
| 684 | } |
| 685 | case GICXXPred_I64_Predicate_imm0_32: { |
| 686 | |
| 687 | return Imm >= 0 && Imm < 33; |
| 688 | |
| 689 | } |
| 690 | case GICXXPred_I64_Predicate_imm0_63: { |
| 691 | |
| 692 | return Imm >= 0 && Imm < 64; |
| 693 | |
| 694 | } |
| 695 | case GICXXPred_I64_Predicate_imm0_239: { |
| 696 | return Imm >= 0 && Imm < 240; |
| 697 | } |
| 698 | case GICXXPred_I64_Predicate_imm0_255: { |
| 699 | return Imm >= 0 && Imm < 256; |
| 700 | } |
| 701 | case GICXXPred_I64_Predicate_imm0_255_expr: { |
| 702 | return Imm >= 0 && Imm < 256; |
| 703 | } |
| 704 | case GICXXPred_I64_Predicate_imm0_4095: { |
| 705 | |
| 706 | return Imm >= 0 && Imm < 4096; |
| 707 | |
| 708 | } |
| 709 | case GICXXPred_I64_Predicate_imm0_65535: { |
| 710 | |
| 711 | return Imm >= 0 && Imm < 65536; |
| 712 | |
| 713 | } |
| 714 | case GICXXPred_I64_Predicate_imm0_65535_expr: { |
| 715 | |
| 716 | return Imm >= 0 && Imm < 65536; |
| 717 | |
| 718 | } |
| 719 | case GICXXPred_I64_Predicate_imm0_65535_neg: { |
| 720 | |
| 721 | return -Imm >= 0 && -Imm < 65536; |
| 722 | |
| 723 | } |
| 724 | case GICXXPred_I64_Predicate_imm1_7: { |
| 725 | return Imm > 0 && Imm < 8; |
| 726 | } |
| 727 | case GICXXPred_I64_Predicate_imm1_15: { |
| 728 | return Imm > 0 && Imm < 16; |
| 729 | } |
| 730 | case GICXXPred_I64_Predicate_imm1_16: { |
| 731 | |
| 732 | return Imm > 0 && Imm <= 16; |
| 733 | |
| 734 | } |
| 735 | case GICXXPred_I64_Predicate_imm1_31: { |
| 736 | return Imm > 0 && Imm < 32; |
| 737 | } |
| 738 | case GICXXPred_I64_Predicate_imm8: { |
| 739 | return Imm == 8; |
| 740 | } |
| 741 | case GICXXPred_I64_Predicate_imm8_255: { |
| 742 | |
| 743 | return Imm >= 8 && Imm < 256; |
| 744 | |
| 745 | } |
| 746 | case GICXXPred_I64_Predicate_imm8_or_16: { |
| 747 | return Imm == 8 || Imm == 16; |
| 748 | } |
| 749 | case GICXXPred_I64_Predicate_imm16: { |
| 750 | return Imm == 16; |
| 751 | } |
| 752 | case GICXXPred_I64_Predicate_imm16_31: { |
| 753 | |
| 754 | return (int32_t)Imm >= 16 && (int32_t)Imm < 32; |
| 755 | |
| 756 | } |
| 757 | case GICXXPred_I64_Predicate_imm24b: { |
| 758 | |
| 759 | return Imm >= 0 && Imm <= 0xffffff; |
| 760 | |
| 761 | } |
| 762 | case GICXXPred_I64_Predicate_imm32: { |
| 763 | return Imm == 32; |
| 764 | } |
| 765 | case GICXXPred_I64_Predicate_imm256_510: { |
| 766 | |
| 767 | return Imm >= 256 && Imm < 511; |
| 768 | |
| 769 | } |
| 770 | case GICXXPred_I64_Predicate_imm_3b: { |
| 771 | { return Imm >= 0 && Imm < (1 << 3); } |
| 772 | llvm_unreachable("imm_3b should have returned"); |
| 773 | } |
| 774 | case GICXXPred_I64_Predicate_imm_4b: { |
| 775 | { return Imm >= 0 && Imm < (1 << 4); } |
| 776 | llvm_unreachable("imm_4b should have returned"); |
| 777 | } |
| 778 | case GICXXPred_I64_Predicate_imm_6b: { |
| 779 | { return Imm >= 0 && Imm < (1 << 6); } |
| 780 | llvm_unreachable("imm_6b should have returned"); |
| 781 | } |
| 782 | case GICXXPred_I64_Predicate_imm_7b: { |
| 783 | { return Imm >= 0 && Imm < (1 << 7); } |
| 784 | llvm_unreachable("imm_7b should have returned"); |
| 785 | } |
| 786 | case GICXXPred_I64_Predicate_imm_9b: { |
| 787 | { return Imm >= 0 && Imm < (1 << 9); } |
| 788 | llvm_unreachable("imm_9b should have returned"); |
| 789 | } |
| 790 | case GICXXPred_I64_Predicate_imm_11b: { |
| 791 | { return Imm >= 0 && Imm < (1 << 11); } |
| 792 | llvm_unreachable("imm_11b should have returned"); |
| 793 | } |
| 794 | case GICXXPred_I64_Predicate_imm_12b: { |
| 795 | { return Imm >= 0 && Imm < (1 << 12); } |
| 796 | llvm_unreachable("imm_12b should have returned"); |
| 797 | } |
| 798 | case GICXXPred_I64_Predicate_imm_13b: { |
| 799 | { return Imm >= 0 && Imm < (1 << 13); } |
| 800 | llvm_unreachable("imm_13b should have returned"); |
| 801 | } |
| 802 | case GICXXPred_I64_Predicate_imm_even: { |
| 803 | return (Imm & 1) == 0; |
| 804 | } |
| 805 | case GICXXPred_I64_Predicate_imm_odd: { |
| 806 | return (Imm & 1) == 1; |
| 807 | } |
| 808 | case GICXXPred_I64_Predicate_long_shift: { |
| 809 | return Imm > 0 && Imm <= 32; |
| 810 | } |
| 811 | case GICXXPred_I64_Predicate_mod_imm: { |
| 812 | |
| 813 | return ARM_AM::getSOImmVal(Imm) != -1; |
| 814 | |
| 815 | } |
| 816 | case GICXXPred_I64_Predicate_mod_imm_not: { |
| 817 | |
| 818 | return ARM_AM::getSOImmVal(~(uint32_t)Imm) != -1; |
| 819 | |
| 820 | } |
| 821 | case GICXXPred_I64_Predicate_pkh_asr_amt: { |
| 822 | return Imm > 0 && Imm <= 32; |
| 823 | } |
| 824 | case GICXXPred_I64_Predicate_pkh_lsl_amt: { |
| 825 | return Imm >= 0 && Imm < 32; |
| 826 | } |
| 827 | case GICXXPred_I64_Predicate_shr_imm8: { |
| 828 | return Imm > 0 && Imm <= 8; |
| 829 | } |
| 830 | case GICXXPred_I64_Predicate_shr_imm16: { |
| 831 | return Imm > 0 && Imm <= 16; |
| 832 | } |
| 833 | case GICXXPred_I64_Predicate_shr_imm32: { |
| 834 | return Imm > 0 && Imm <= 32; |
| 835 | } |
| 836 | case GICXXPred_I64_Predicate_shr_imm64: { |
| 837 | return Imm > 0 && Imm <= 64; |
| 838 | } |
| 839 | case GICXXPred_I64_Predicate_t2_so_imm: { |
| 840 | |
| 841 | return ARM_AM::getT2SOImmVal(Imm) != -1; |
| 842 | |
| 843 | } |
| 844 | case GICXXPred_I64_Predicate_t2_so_imm_neg: { |
| 845 | |
| 846 | return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1; |
| 847 | |
| 848 | } |
| 849 | } |
| 850 | llvm_unreachable("Unknown predicate"); |
| 851 | return false; |
| 852 | } |
| 853 | // PatFrag predicates. |
| 854 | bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { |
| 855 | llvm_unreachable("Unknown predicate"); |
| 856 | return false; |
| 857 | } |
| 858 | // PatFrag predicates. |
| 859 | enum { |
| 860 | GICXXPred_APInt_Predicate_arm_i32imm = GICXXPred_Invalid + 1, |
| 861 | }; |
| 862 | bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { |
| 863 | switch (PredicateID) { |
| 864 | case GICXXPred_APInt_Predicate_arm_i32imm: { |
| 865 | |
| 866 | if (Subtarget->useMovt()) |
| 867 | return true; |
| 868 | if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue())) |
| 869 | return true; |
| 870 | return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue()); |
| 871 | |
| 872 | llvm_unreachable("arm_i32imm should have returned"); |
| 873 | } |
| 874 | } |
| 875 | llvm_unreachable("Unknown predicate"); |
| 876 | return false; |
| 877 | } |
| 878 | bool ARMInstructionSelector::testSimplePredicate(unsigned) const { |
| 879 | llvm_unreachable("ARMInstructionSelector does not support simple predicates!"); |
| 880 | return false; |
| 881 | } |
| 882 | // Custom renderers. |
| 883 | enum { |
| 884 | GICR_Invalid, |
| 885 | GICR_renderInvertedImm, |
| 886 | GICR_renderVFPF32Imm, |
| 887 | GICR_renderVFPF64Imm, |
| 888 | }; |
| 889 | ARMInstructionSelector::CustomRendererFn |
| 890 | ARMInstructionSelector::CustomRenderers[] = { |
| 891 | nullptr, // GICR_Invalid |
| 892 | &ARMInstructionSelector::renderInvertedImm, |
| 893 | &ARMInstructionSelector::renderVFPF32Imm, |
| 894 | &ARMInstructionSelector::renderVFPF64Imm, |
| 895 | }; |
| 896 | |
| 897 | bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { |
| 898 | const PredicateBitset AvailableFeatures = getAvailableFeatures(); |
| 899 | MachineIRBuilder B(I); |
| 900 | State.MIs.clear(); |
| 901 | State.MIs.push_back(&I); |
| 902 | |
| 903 | if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) { |
| 904 | return true; |
| 905 | } |
| 906 | |
| 907 | return false; |
| 908 | } |
| 909 | |
| 910 | bool ARMInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const { |
| 911 | llvm_unreachable("ARMInstructionSelector does not support custom C++ actions!"); |
| 912 | } |
| 913 | #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ |
| 914 | #define GIMT_Encode2(Val) uint8_t(Val), uint8_t((uint16_t)Val >> 8) |
| 915 | #define GIMT_Encode4(Val) uint8_t(Val), uint8_t((uint32_t)Val >> 8), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 24) |
| 916 | #define GIMT_Encode8(Val) uint8_t(Val), uint8_t((uint64_t)Val >> 8), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 56) |
| 917 | #else |
| 918 | #define GIMT_Encode2(Val) uint8_t((uint16_t)Val >> 8), uint8_t(Val) |
| 919 | #define GIMT_Encode4(Val) uint8_t((uint32_t)Val >> 24), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 8), uint8_t(Val) |
| 920 | #define GIMT_Encode8(Val) uint8_t((uint64_t)Val >> 56), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 8), uint8_t(Val) |
| 921 | #endif |
| 922 | const uint8_t *ARMInstructionSelector::getMatchTable() const { |
| 923 | constexpr static uint8_t MatchTable0[] = { |
| 924 | GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(51), GIMT_Encode2(293), /*)*//*default:*//*Label 76*/ GIMT_Encode4(126069), |
| 925 | /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(978), |
| 926 | /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(6603), |
| 927 | /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(9751), |
| 928 | /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(10621), |
| 929 | /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(10717), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 930 | /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(10813), |
| 931 | /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(13773), |
| 932 | /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(19504), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 933 | /*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ GIMT_Encode4(21077), GIMT_Encode4(0), GIMT_Encode4(0), |
| 934 | /*TargetOpcode::G_BITCAST*//*Label 9*/ GIMT_Encode4(21503), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 935 | /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ GIMT_Encode4(31951), |
| 936 | /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ GIMT_Encode4(32243), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 937 | /*TargetOpcode::G_FENCE*//*Label 12*/ GIMT_Encode4(32502), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 938 | /*TargetOpcode::G_INTRINSIC*//*Label 13*/ GIMT_Encode4(32523), |
| 939 | /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 14*/ GIMT_Encode4(88245), GIMT_Encode4(0), GIMT_Encode4(0), |
| 940 | /*TargetOpcode::G_ANYEXT*//*Label 15*/ GIMT_Encode4(95907), |
| 941 | /*TargetOpcode::G_TRUNC*//*Label 16*/ GIMT_Encode4(96065), |
| 942 | /*TargetOpcode::G_CONSTANT*//*Label 17*/ GIMT_Encode4(96223), |
| 943 | /*TargetOpcode::G_FCONSTANT*//*Label 18*/ GIMT_Encode4(96503), GIMT_Encode4(0), GIMT_Encode4(0), |
| 944 | /*TargetOpcode::G_SEXT*//*Label 19*/ GIMT_Encode4(96599), GIMT_Encode4(0), |
| 945 | /*TargetOpcode::G_ZEXT*//*Label 20*/ GIMT_Encode4(96757), |
| 946 | /*TargetOpcode::G_SHL*//*Label 21*/ GIMT_Encode4(96915), |
| 947 | /*TargetOpcode::G_LSHR*//*Label 22*/ GIMT_Encode4(97026), |
| 948 | /*TargetOpcode::G_ASHR*//*Label 23*/ GIMT_Encode4(97082), GIMT_Encode4(0), GIMT_Encode4(0), |
| 949 | /*TargetOpcode::G_ROTR*//*Label 24*/ GIMT_Encode4(97311), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 950 | /*TargetOpcode::G_UMULH*//*Label 25*/ GIMT_Encode4(97593), |
| 951 | /*TargetOpcode::G_SMULH*//*Label 26*/ GIMT_Encode4(97835), |
| 952 | /*TargetOpcode::G_UADDSAT*//*Label 27*/ GIMT_Encode4(98198), |
| 953 | /*TargetOpcode::G_SADDSAT*//*Label 28*/ GIMT_Encode4(98837), |
| 954 | /*TargetOpcode::G_USUBSAT*//*Label 29*/ GIMT_Encode4(100131), |
| 955 | /*TargetOpcode::G_SSUBSAT*//*Label 30*/ GIMT_Encode4(100770), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 956 | /*TargetOpcode::G_FADD*//*Label 31*/ GIMT_Encode4(101784), |
| 957 | /*TargetOpcode::G_FSUB*//*Label 32*/ GIMT_Encode4(104096), |
| 958 | /*TargetOpcode::G_FMUL*//*Label 33*/ GIMT_Encode4(105760), |
| 959 | /*TargetOpcode::G_FMA*//*Label 34*/ GIMT_Encode4(106740), GIMT_Encode4(0), |
| 960 | /*TargetOpcode::G_FDIV*//*Label 35*/ GIMT_Encode4(108555), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 961 | /*TargetOpcode::G_FNEG*//*Label 36*/ GIMT_Encode4(108720), |
| 962 | /*TargetOpcode::G_FPEXT*//*Label 37*/ GIMT_Encode4(110261), |
| 963 | /*TargetOpcode::G_FPTRUNC*//*Label 38*/ GIMT_Encode4(110491), |
| 964 | /*TargetOpcode::G_FPTOSI*//*Label 39*/ GIMT_Encode4(110763), |
| 965 | /*TargetOpcode::G_FPTOUI*//*Label 40*/ GIMT_Encode4(112093), |
| 966 | /*TargetOpcode::G_SITOFP*//*Label 41*/ GIMT_Encode4(113423), |
| 967 | /*TargetOpcode::G_UITOFP*//*Label 42*/ GIMT_Encode4(114067), |
| 968 | /*TargetOpcode::G_FABS*//*Label 43*/ GIMT_Encode4(114711), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 969 | /*TargetOpcode::G_FMINNUM*//*Label 44*/ GIMT_Encode4(115481), |
| 970 | /*TargetOpcode::G_FMAXNUM*//*Label 45*/ GIMT_Encode4(116069), GIMT_Encode4(0), GIMT_Encode4(0), |
| 971 | /*TargetOpcode::G_FMINIMUM*//*Label 46*/ GIMT_Encode4(116657), |
| 972 | /*TargetOpcode::G_FMAXIMUM*//*Label 47*/ GIMT_Encode4(117373), |
| 973 | /*TargetOpcode::G_GET_FPENV*//*Label 48*/ GIMT_Encode4(118089), |
| 974 | /*TargetOpcode::G_SET_FPENV*//*Label 49*/ GIMT_Encode4(118122), |
| 975 | /*TargetOpcode::G_RESET_FPENV*//*Label 50*/ GIMT_Encode4(118158), |
| 976 | /*TargetOpcode::G_GET_FPMODE*//*Label 51*/ GIMT_Encode4(118223), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 977 | /*TargetOpcode::G_SMIN*//*Label 52*/ GIMT_Encode4(118256), |
| 978 | /*TargetOpcode::G_SMAX*//*Label 53*/ GIMT_Encode4(118793), |
| 979 | /*TargetOpcode::G_UMIN*//*Label 54*/ GIMT_Encode4(119330), |
| 980 | /*TargetOpcode::G_UMAX*//*Label 55*/ GIMT_Encode4(120245), |
| 981 | /*TargetOpcode::G_ABS*//*Label 56*/ GIMT_Encode4(121160), GIMT_Encode4(0), GIMT_Encode4(0), |
| 982 | /*TargetOpcode::G_BR*//*Label 57*/ GIMT_Encode4(121625), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 983 | /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 58*/ GIMT_Encode4(121698), |
| 984 | /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 59*/ GIMT_Encode4(121998), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 985 | /*TargetOpcode::G_CTLZ*//*Label 60*/ GIMT_Encode4(122153), GIMT_Encode4(0), |
| 986 | /*TargetOpcode::G_CTPOP*//*Label 61*/ GIMT_Encode4(122708), |
| 987 | /*TargetOpcode::G_BSWAP*//*Label 62*/ GIMT_Encode4(122816), |
| 988 | /*TargetOpcode::G_BITREVERSE*//*Label 63*/ GIMT_Encode4(123102), |
| 989 | /*TargetOpcode::G_FCEIL*//*Label 64*/ GIMT_Encode4(123528), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 990 | /*TargetOpcode::G_FSQRT*//*Label 65*/ GIMT_Encode4(123787), |
| 991 | /*TargetOpcode::G_FFLOOR*//*Label 66*/ GIMT_Encode4(123925), |
| 992 | /*TargetOpcode::G_FRINT*//*Label 67*/ GIMT_Encode4(124184), |
| 993 | /*TargetOpcode::G_FNEARBYINT*//*Label 68*/ GIMT_Encode4(124476), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 994 | /*TargetOpcode::G_TRAP*//*Label 69*/ GIMT_Encode4(124614), |
| 995 | /*TargetOpcode::G_DEBUGTRAP*//*Label 70*/ GIMT_Encode4(124660), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 996 | /*TargetOpcode::G_VECREDUCE_ADD*//*Label 71*/ GIMT_Encode4(124747), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 997 | /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 72*/ GIMT_Encode4(124923), |
| 998 | /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 73*/ GIMT_Encode4(125203), |
| 999 | /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 74*/ GIMT_Encode4(125492), |
| 1000 | /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 75*/ GIMT_Encode4(125773), |
| 1001 | // Label 0: @978 |
| 1002 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 86*/ GIMT_Encode4(6602), |
| 1003 | /*GILLT_s32*//*Label 77*/ GIMT_Encode4(1049), |
| 1004 | /*GILLT_s64*//*Label 78*/ GIMT_Encode4(3129), GIMT_Encode4(0), |
| 1005 | /*GILLT_v2s32*//*Label 79*/ GIMT_Encode4(3176), |
| 1006 | /*GILLT_v2s64*//*Label 80*/ GIMT_Encode4(3361), GIMT_Encode4(0), |
| 1007 | /*GILLT_v4s16*//*Label 81*/ GIMT_Encode4(4072), |
| 1008 | /*GILLT_v4s32*//*Label 82*/ GIMT_Encode4(4257), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1009 | /*GILLT_v8s8*//*Label 83*/ GIMT_Encode4(5211), |
| 1010 | /*GILLT_v8s16*//*Label 84*/ GIMT_Encode4(5396), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1011 | /*GILLT_v16s8*//*Label 85*/ GIMT_Encode4(6350), |
| 1012 | // Label 77: @1049 |
| 1013 | GIM_Try, /*On fail goto*//*Label 87*/ GIMT_Encode4(3128), |
| 1014 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 1015 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 1016 | GIM_Try, /*On fail goto*//*Label 88*/ GIMT_Encode4(1135), // Rule ID 5787 // |
| 1017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 1018 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1019 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1020 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1021 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1022 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1023 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1024 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1025 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1026 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1027 | // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB), |
| 1029 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1030 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1031 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1034 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1035 | GIR_RootConstrainSelectedInstOperands, |
| 1036 | // GIR_Coverage, 5787, |
| 1037 | GIR_EraseRootFromParent_Done, |
| 1038 | // Label 88: @1135 |
| 1039 | GIM_Try, /*On fail goto*//*Label 89*/ GIMT_Encode4(1210), // Rule ID 5788 // |
| 1040 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 1041 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1042 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1043 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1044 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1045 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1046 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1047 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1048 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1049 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1050 | // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1051 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH), |
| 1052 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1053 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1054 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1057 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1058 | GIR_RootConstrainSelectedInstOperands, |
| 1059 | // GIR_Coverage, 5788, |
| 1060 | GIR_EraseRootFromParent_Done, |
| 1061 | // Label 89: @1210 |
| 1062 | GIM_Try, /*On fail goto*//*Label 90*/ GIMT_Encode4(1285), // Rule ID 5822 // |
| 1063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1065 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1066 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1067 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1068 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1069 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1070 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1071 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1072 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1073 | // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB), |
| 1075 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1076 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1077 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1080 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1081 | GIR_RootConstrainSelectedInstOperands, |
| 1082 | // GIR_Coverage, 5822, |
| 1083 | GIR_EraseRootFromParent_Done, |
| 1084 | // Label 90: @1285 |
| 1085 | GIM_Try, /*On fail goto*//*Label 91*/ GIMT_Encode4(1360), // Rule ID 5823 // |
| 1086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1087 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1088 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1089 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1090 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1091 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1092 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1093 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1094 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1095 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1096 | // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1097 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH), |
| 1098 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1099 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1100 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1103 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1104 | GIR_RootConstrainSelectedInstOperands, |
| 1105 | // GIR_Coverage, 5823, |
| 1106 | GIR_EraseRootFromParent_Done, |
| 1107 | // Label 91: @1360 |
| 1108 | GIM_Try, /*On fail goto*//*Label 92*/ GIMT_Encode4(1435), // Rule ID 2015 // |
| 1109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 1110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1111 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1112 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1113 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1114 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1115 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1116 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1117 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1118 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1119 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1120 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB), |
| 1121 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1122 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1123 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1126 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1127 | GIR_RootConstrainSelectedInstOperands, |
| 1128 | // GIR_Coverage, 2015, |
| 1129 | GIR_EraseRootFromParent_Done, |
| 1130 | // Label 92: @1435 |
| 1131 | GIM_Try, /*On fail goto*//*Label 93*/ GIMT_Encode4(1510), // Rule ID 2016 // |
| 1132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 1133 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1134 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1135 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1136 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1137 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1138 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1139 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1140 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1141 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1142 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH), |
| 1144 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1145 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1146 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1149 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1150 | GIR_RootConstrainSelectedInstOperands, |
| 1151 | // GIR_Coverage, 2016, |
| 1152 | GIR_EraseRootFromParent_Done, |
| 1153 | // Label 93: @1510 |
| 1154 | GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1585), // Rule ID 2237 // |
| 1155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1157 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1158 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1159 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1160 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1161 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1162 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1163 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1164 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1165 | // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB), |
| 1167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1168 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1169 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1172 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1173 | GIR_RootConstrainSelectedInstOperands, |
| 1174 | // GIR_Coverage, 2237, |
| 1175 | GIR_EraseRootFromParent_Done, |
| 1176 | // Label 94: @1585 |
| 1177 | GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1660), // Rule ID 2238 // |
| 1178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1179 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1180 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1181 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1182 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1183 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1184 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1185 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1186 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1187 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1188 | // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH), |
| 1190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1191 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1192 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1195 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1196 | GIR_RootConstrainSelectedInstOperands, |
| 1197 | // GIR_Coverage, 2238, |
| 1198 | GIR_EraseRootFromParent_Done, |
| 1199 | // Label 95: @1660 |
| 1200 | GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(1770), // Rule ID 5566 // |
| 1201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1202 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1203 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1204 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1205 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1206 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1207 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1208 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1209 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1210 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1211 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1212 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1213 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1214 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1215 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1216 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1217 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1218 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1219 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1220 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1221 | // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 1223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1224 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1225 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1226 | GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1228 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1229 | GIR_RootConstrainSelectedInstOperands, |
| 1230 | // GIR_Coverage, 5566, |
| 1231 | GIR_EraseRootFromParent_Done, |
| 1232 | // Label 96: @1770 |
| 1233 | GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(1880), // Rule ID 5603 // |
| 1234 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1235 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1236 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1237 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1238 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1239 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1240 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1241 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1242 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1243 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1244 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1245 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1246 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1247 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1248 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1249 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1250 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1251 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1252 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1253 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1254 | // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1255 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 1256 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1257 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1259 | GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1261 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1262 | GIR_RootConstrainSelectedInstOperands, |
| 1263 | // GIR_Coverage, 5603, |
| 1264 | GIR_EraseRootFromParent_Done, |
| 1265 | // Label 97: @1880 |
| 1266 | GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(1990), // Rule ID 192 // |
| 1267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1268 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1269 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1270 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1271 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1272 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1273 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1274 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1275 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1276 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1277 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1278 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1279 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1280 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1281 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1282 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1283 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1284 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1285 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1286 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1287 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 1289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1290 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1291 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1292 | GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1294 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1295 | GIR_RootConstrainSelectedInstOperands, |
| 1296 | // GIR_Coverage, 192, |
| 1297 | GIR_EraseRootFromParent_Done, |
| 1298 | // Label 98: @1990 |
| 1299 | GIM_Try, /*On fail goto*//*Label 99*/ GIMT_Encode4(2100), // Rule ID 529 // |
| 1300 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1301 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1302 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1303 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1304 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1305 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1306 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1307 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1308 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1309 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1310 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1311 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1312 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1313 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1314 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1315 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1316 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1317 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1318 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1319 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1320 | // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 1322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1323 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1324 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1325 | GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1327 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1328 | GIR_RootConstrainSelectedInstOperands, |
| 1329 | // GIR_Coverage, 529, |
| 1330 | GIR_EraseRootFromParent_Done, |
| 1331 | // Label 99: @2100 |
| 1332 | GIM_Try, /*On fail goto*//*Label 100*/ GIMT_Encode4(2157), // Rule ID 72 // |
| 1333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 1334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1335 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1336 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1337 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 1338 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 1339 | // MIs[1] Operand 1 |
| 1340 | // No operand predicates |
| 1341 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1342 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 1343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDri), |
| 1344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1345 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1346 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 1347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1348 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1349 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1350 | GIR_RootConstrainSelectedInstOperands, |
| 1351 | // GIR_Coverage, 72, |
| 1352 | GIR_EraseRootFromParent_Done, |
| 1353 | // Label 100: @2157 |
| 1354 | GIM_Try, /*On fail goto*//*Label 101*/ GIMT_Encode4(2214), // Rule ID 415 // |
| 1355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 1356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1357 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1358 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1359 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 1360 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 1361 | // MIs[1] Operand 1 |
| 1362 | // No operand predicates |
| 1363 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1364 | // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 1365 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri), |
| 1366 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1367 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1368 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 1369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1370 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1371 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1372 | GIR_RootConstrainSelectedInstOperands, |
| 1373 | // GIR_Coverage, 415, |
| 1374 | GIR_EraseRootFromParent_Done, |
| 1375 | // Label 101: @2214 |
| 1376 | GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(2265), // Rule ID 416 // |
| 1377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 1378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1379 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1380 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1381 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 1382 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095), |
| 1383 | // MIs[1] Operand 1 |
| 1384 | // No operand predicates |
| 1385 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1386 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 1387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri12), |
| 1388 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1389 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1390 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 1391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1392 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1393 | GIR_RootConstrainSelectedInstOperands, |
| 1394 | // GIR_Coverage, 416, |
| 1395 | GIR_EraseRootFromParent_Done, |
| 1396 | // Label 102: @2265 |
| 1397 | GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(2341), // Rule ID 171 // |
| 1398 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), |
| 1399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1400 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1401 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1402 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1403 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1404 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1405 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1406 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1407 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1408 | // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 1409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA), |
| 1410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1411 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 1412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 1413 | GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1415 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1416 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1417 | GIR_RootConstrainSelectedInstOperands, |
| 1418 | // GIR_Coverage, 171, |
| 1419 | GIR_EraseRootFromParent_Done, |
| 1420 | // Label 103: @2341 |
| 1421 | GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(2417), // Rule ID 172 // |
| 1422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6), |
| 1423 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1424 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1425 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1426 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1427 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1428 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1429 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1430 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1431 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1432 | // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 1433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5), |
| 1434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1435 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 1436 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 1437 | GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1439 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1440 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1441 | GIR_RootConstrainSelectedInstOperands, |
| 1442 | // GIR_Coverage, 172, |
| 1443 | GIR_EraseRootFromParent_Done, |
| 1444 | // Label 104: @2417 |
| 1445 | GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(2487), // Rule ID 511 // |
| 1446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), |
| 1447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1448 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1449 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1450 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1451 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1452 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1453 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1454 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1455 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1456 | // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA), |
| 1458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1459 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 1460 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 1461 | GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1463 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1464 | GIR_RootConstrainSelectedInstOperands, |
| 1465 | // GIR_Coverage, 511, |
| 1466 | GIR_EraseRootFromParent_Done, |
| 1467 | // Label 105: @2487 |
| 1468 | GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(2557), // Rule ID 180 // |
| 1469 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), |
| 1470 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1471 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1472 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 1473 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1474 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1475 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1476 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1477 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1478 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1479 | // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA), |
| 1481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1482 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 1483 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 1484 | GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1486 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1487 | GIR_RootConstrainSelectedInstOperands, |
| 1488 | // GIR_Coverage, 180, |
| 1489 | GIR_EraseRootFromParent_Done, |
| 1490 | // Label 106: @2557 |
| 1491 | GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(2627), // Rule ID 517 // |
| 1492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1493 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1494 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1495 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 1496 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1497 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1498 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1499 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1500 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1501 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1502 | // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1503 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA), |
| 1504 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1505 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 1506 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1507 | GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1509 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1510 | GIR_RootConstrainSelectedInstOperands, |
| 1511 | // GIR_Coverage, 517, |
| 1512 | GIR_EraseRootFromParent_Done, |
| 1513 | // Label 107: @2627 |
| 1514 | GIM_Try, /*On fail goto*//*Label 108*/ GIMT_Encode4(2703), // Rule ID 5560 // |
| 1515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), |
| 1516 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1517 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1518 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1519 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1520 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1521 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1522 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1523 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1524 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1525 | // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 1526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA), |
| 1527 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 1529 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 1530 | GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1532 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1533 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1534 | GIR_RootConstrainSelectedInstOperands, |
| 1535 | // GIR_Coverage, 5560, |
| 1536 | GIR_EraseRootFromParent_Done, |
| 1537 | // Label 108: @2703 |
| 1538 | GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(2779), // Rule ID 5561 // |
| 1539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6), |
| 1540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1541 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1542 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1543 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1544 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1545 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1546 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1547 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1548 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1549 | // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 1550 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5), |
| 1551 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1552 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 1553 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 1554 | GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1556 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1557 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1558 | GIR_RootConstrainSelectedInstOperands, |
| 1559 | // GIR_Coverage, 5561, |
| 1560 | GIR_EraseRootFromParent_Done, |
| 1561 | // Label 109: @2779 |
| 1562 | GIM_Try, /*On fail goto*//*Label 110*/ GIMT_Encode4(2849), // Rule ID 5598 // |
| 1563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), |
| 1564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1565 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1566 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1567 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1568 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1569 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1570 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1571 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1572 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1573 | // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1574 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA), |
| 1575 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1576 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 1577 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 1578 | GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1580 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1581 | GIR_RootConstrainSelectedInstOperands, |
| 1582 | // GIR_Coverage, 5598, |
| 1583 | GIR_EraseRootFromParent_Done, |
| 1584 | // Label 110: @2849 |
| 1585 | GIM_Try, /*On fail goto*//*Label 111*/ GIMT_Encode4(2919), // Rule ID 5562 // |
| 1586 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), |
| 1587 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1588 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1589 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1590 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 1591 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1592 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1593 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1594 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1595 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1596 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA), |
| 1598 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1599 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 1600 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 1601 | GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1603 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1604 | GIR_RootConstrainSelectedInstOperands, |
| 1605 | // GIR_Coverage, 5562, |
| 1606 | GIR_EraseRootFromParent_Done, |
| 1607 | // Label 111: @2919 |
| 1608 | GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(2989), // Rule ID 5599 // |
| 1609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1610 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1611 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1612 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1613 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 1614 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1615 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1616 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1617 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1618 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1619 | // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA), |
| 1621 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1622 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 1623 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1624 | GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1626 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1627 | GIR_RootConstrainSelectedInstOperands, |
| 1628 | // GIR_Coverage, 5599, |
| 1629 | GIR_EraseRootFromParent_Done, |
| 1630 | // Label 112: @2989 |
| 1631 | GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(3035), // Rule ID 73 // |
| 1632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 1633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1634 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1635 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1636 | // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 1637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDrr), |
| 1638 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1639 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1640 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 1641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1642 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1643 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1644 | GIR_RootConstrainSelectedInstOperands, |
| 1645 | // GIR_Coverage, 73, |
| 1646 | GIR_EraseRootFromParent_Done, |
| 1647 | // Label 113: @3035 |
| 1648 | GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(3081), // Rule ID 417 // |
| 1649 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 1650 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1651 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1652 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1653 | // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 1654 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr), |
| 1655 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1656 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1657 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 1658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1659 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1660 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1661 | GIR_RootConstrainSelectedInstOperands, |
| 1662 | // GIR_Coverage, 417, |
| 1663 | GIR_EraseRootFromParent_Done, |
| 1664 | // Label 114: @3081 |
| 1665 | GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(3127), // Rule ID 5580 // |
| 1666 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 1667 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1668 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1669 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1670 | // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 1671 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr), |
| 1672 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1673 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1674 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 1675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1676 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1677 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1678 | GIR_RootConstrainSelectedInstOperands, |
| 1679 | // GIR_Coverage, 5580, |
| 1680 | GIR_EraseRootFromParent_Done, |
| 1681 | // Label 115: @3127 |
| 1682 | GIM_Reject, |
| 1683 | // Label 87: @3128 |
| 1684 | GIM_Reject, |
| 1685 | // Label 78: @3129 |
| 1686 | GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(3175), // Rule ID 779 // |
| 1687 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1688 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 1689 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 1690 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1691 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1692 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1693 | // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 1694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv1i64), |
| 1695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1696 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 1697 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 1698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1699 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1700 | GIR_RootConstrainSelectedInstOperands, |
| 1701 | // GIR_Coverage, 779, |
| 1702 | GIR_EraseRootFromParent_Done, |
| 1703 | // Label 116: @3175 |
| 1704 | GIM_Reject, |
| 1705 | // Label 79: @3176 |
| 1706 | GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(3360), |
| 1707 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1708 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 1709 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1710 | GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(3257), // Rule ID 5649 // |
| 1711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1712 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1713 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1714 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1715 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 1716 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1717 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1718 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1719 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1720 | // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32), |
| 1722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1723 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 1724 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 1725 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 1726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1727 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1728 | GIR_RootConstrainSelectedInstOperands, |
| 1729 | // GIR_Coverage, 5649, |
| 1730 | GIR_EraseRootFromParent_Done, |
| 1731 | // Label 118: @3257 |
| 1732 | GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(3323), // Rule ID 906 // |
| 1733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1734 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1735 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1736 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1737 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1738 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 1739 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1740 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1741 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1742 | // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32), |
| 1744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1745 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 1746 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 1747 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 1748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1749 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1750 | GIR_RootConstrainSelectedInstOperands, |
| 1751 | // GIR_Coverage, 906, |
| 1752 | GIR_EraseRootFromParent_Done, |
| 1753 | // Label 119: @3323 |
| 1754 | GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(3359), // Rule ID 775 // |
| 1755 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1756 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1757 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1758 | // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i32), |
| 1760 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1761 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 1762 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 1763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1764 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1765 | GIR_RootConstrainSelectedInstOperands, |
| 1766 | // GIR_Coverage, 775, |
| 1767 | GIR_EraseRootFromParent_Done, |
| 1768 | // Label 120: @3359 |
| 1769 | GIM_Reject, |
| 1770 | // Label 117: @3360 |
| 1771 | GIM_Reject, |
| 1772 | // Label 80: @3361 |
| 1773 | GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(4071), |
| 1774 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 1775 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 1776 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 1777 | GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(3444), // Rule ID 799 // |
| 1778 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1779 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1780 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 1781 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1782 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1783 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 1784 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 1785 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1786 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1787 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1788 | // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 1790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1791 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 1792 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 1793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1794 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1795 | GIR_RootConstrainSelectedInstOperands, |
| 1796 | // GIR_Coverage, 799, |
| 1797 | GIR_EraseRootFromParent_Done, |
| 1798 | // Label 122: @3444 |
| 1799 | GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(3512), // Rule ID 798 // |
| 1800 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1801 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1802 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 1803 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1804 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1805 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 1806 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 1807 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1808 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1809 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1810 | // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 1812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1813 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 1814 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 1815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1816 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1817 | GIR_RootConstrainSelectedInstOperands, |
| 1818 | // GIR_Coverage, 798, |
| 1819 | GIR_EraseRootFromParent_Done, |
| 1820 | // Label 123: @3512 |
| 1821 | GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(3580), // Rule ID 787 // |
| 1822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1823 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1824 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 1825 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1826 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1827 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 1828 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 1829 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1830 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1831 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1832 | // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv2i64), |
| 1834 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1835 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 1836 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 1837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1838 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1839 | GIR_RootConstrainSelectedInstOperands, |
| 1840 | // GIR_Coverage, 787, |
| 1841 | GIR_EraseRootFromParent_Done, |
| 1842 | // Label 124: @3580 |
| 1843 | GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(3648), // Rule ID 797 // |
| 1844 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1845 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1846 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 1847 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1848 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1849 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 1850 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 1851 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1852 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1853 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1854 | // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1855 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 1856 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1857 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 1858 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 1859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1860 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1861 | GIR_RootConstrainSelectedInstOperands, |
| 1862 | // GIR_Coverage, 797, |
| 1863 | GIR_EraseRootFromParent_Done, |
| 1864 | // Label 125: @3648 |
| 1865 | GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(3716), // Rule ID 796 // |
| 1866 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1867 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1868 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 1869 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1870 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1871 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 1872 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 1873 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1874 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1875 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1876 | // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 1878 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1879 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 1880 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 1881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1882 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1883 | GIR_RootConstrainSelectedInstOperands, |
| 1884 | // GIR_Coverage, 796, |
| 1885 | GIR_EraseRootFromParent_Done, |
| 1886 | // Label 126: @3716 |
| 1887 | GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(3769), // Rule ID 5628 // |
| 1888 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1889 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1890 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 1891 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1892 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1893 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 1894 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1895 | // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 1897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1898 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 1899 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 1900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1901 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1902 | GIR_RootConstrainSelectedInstOperands, |
| 1903 | // GIR_Coverage, 5628, |
| 1904 | GIR_EraseRootFromParent_Done, |
| 1905 | // Label 127: @3769 |
| 1906 | GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(3822), // Rule ID 5622 // |
| 1907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1908 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1909 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 1910 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1911 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1912 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 1913 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1914 | // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64), |
| 1916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1917 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 1918 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 1919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1920 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1921 | GIR_RootConstrainSelectedInstOperands, |
| 1922 | // GIR_Coverage, 5622, |
| 1923 | GIR_EraseRootFromParent_Done, |
| 1924 | // Label 128: @3822 |
| 1925 | GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(3875), // Rule ID 5627 // |
| 1926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1927 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1928 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 1929 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1930 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1931 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 1932 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1933 | // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 1935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1936 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 1937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 1938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1939 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1940 | GIR_RootConstrainSelectedInstOperands, |
| 1941 | // GIR_Coverage, 5627, |
| 1942 | GIR_EraseRootFromParent_Done, |
| 1943 | // Label 129: @3875 |
| 1944 | GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(3928), // Rule ID 808 // |
| 1945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 1947 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1948 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 1949 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1950 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1951 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1952 | // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 1954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1955 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 1956 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 1957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1958 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1959 | GIR_RootConstrainSelectedInstOperands, |
| 1960 | // GIR_Coverage, 808, |
| 1961 | GIR_EraseRootFromParent_Done, |
| 1962 | // Label 130: @3928 |
| 1963 | GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(3981), // Rule ID 802 // |
| 1964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1965 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 1966 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1967 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 1968 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1969 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1970 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1971 | // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64), |
| 1973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1974 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 1975 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 1976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1977 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1978 | GIR_RootConstrainSelectedInstOperands, |
| 1979 | // GIR_Coverage, 802, |
| 1980 | GIR_EraseRootFromParent_Done, |
| 1981 | // Label 131: @3981 |
| 1982 | GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(4034), // Rule ID 807 // |
| 1983 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 1984 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 1985 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1986 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 1987 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 1988 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 1989 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1990 | // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 1991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 1992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 1993 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 1994 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 1995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1996 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1997 | GIR_RootConstrainSelectedInstOperands, |
| 1998 | // GIR_Coverage, 807, |
| 1999 | GIR_EraseRootFromParent_Done, |
| 2000 | // Label 132: @4034 |
| 2001 | GIM_Try, /*On fail goto*//*Label 133*/ GIMT_Encode4(4070), // Rule ID 780 // |
| 2002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2003 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2004 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2005 | // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 2006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i64), |
| 2007 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2008 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2009 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 2010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2011 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2012 | GIR_RootConstrainSelectedInstOperands, |
| 2013 | // GIR_Coverage, 780, |
| 2014 | GIR_EraseRootFromParent_Done, |
| 2015 | // Label 133: @4070 |
| 2016 | GIM_Reject, |
| 2017 | // Label 121: @4071 |
| 2018 | GIM_Reject, |
| 2019 | // Label 81: @4072 |
| 2020 | GIM_Try, /*On fail goto*//*Label 134*/ GIMT_Encode4(4256), |
| 2021 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2022 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 2023 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2024 | GIM_Try, /*On fail goto*//*Label 135*/ GIMT_Encode4(4153), // Rule ID 5648 // |
| 2025 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2026 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2027 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2028 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2029 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 2030 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2031 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2032 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2033 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2034 | // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16), |
| 2036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2037 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2038 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2039 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2041 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2042 | GIR_RootConstrainSelectedInstOperands, |
| 2043 | // GIR_Coverage, 5648, |
| 2044 | GIR_EraseRootFromParent_Done, |
| 2045 | // Label 135: @4153 |
| 2046 | GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(4219), // Rule ID 905 // |
| 2047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2048 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2049 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2050 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2051 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2052 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 2053 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2054 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2055 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2056 | // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16), |
| 2058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2059 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2060 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2061 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2063 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2064 | GIR_RootConstrainSelectedInstOperands, |
| 2065 | // GIR_Coverage, 905, |
| 2066 | GIR_EraseRootFromParent_Done, |
| 2067 | // Label 136: @4219 |
| 2068 | GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(4255), // Rule ID 774 // |
| 2069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2070 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2071 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2072 | // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i16), |
| 2074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2075 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2076 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 2077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2078 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2079 | GIR_RootConstrainSelectedInstOperands, |
| 2080 | // GIR_Coverage, 774, |
| 2081 | GIR_EraseRootFromParent_Done, |
| 2082 | // Label 137: @4255 |
| 2083 | GIM_Reject, |
| 2084 | // Label 134: @4256 |
| 2085 | GIM_Reject, |
| 2086 | // Label 82: @4257 |
| 2087 | GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(5210), |
| 2088 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2089 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2090 | GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(4340), // Rule ID 795 // |
| 2091 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2092 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2093 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2094 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2095 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2096 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2097 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2098 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2099 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2100 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2101 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2102 | // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 2104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2105 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2106 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 2107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2108 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2109 | GIR_RootConstrainSelectedInstOperands, |
| 2110 | // GIR_Coverage, 795, |
| 2111 | GIR_EraseRootFromParent_Done, |
| 2112 | // Label 139: @4340 |
| 2113 | GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(4412), // Rule ID 794 // |
| 2114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2116 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2117 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2118 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2119 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2120 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2121 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2122 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2123 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2124 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2125 | // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 2127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2128 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2129 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 2130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2131 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2132 | GIR_RootConstrainSelectedInstOperands, |
| 2133 | // GIR_Coverage, 794, |
| 2134 | GIR_EraseRootFromParent_Done, |
| 2135 | // Label 140: @4412 |
| 2136 | GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(4484), // Rule ID 786 // |
| 2137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2139 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2140 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 2141 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2142 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2143 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2144 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 2145 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2146 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2147 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2148 | // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv4i32), |
| 2150 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2151 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2152 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 2153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2154 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2155 | GIR_RootConstrainSelectedInstOperands, |
| 2156 | // GIR_Coverage, 786, |
| 2157 | GIR_EraseRootFromParent_Done, |
| 2158 | // Label 141: @4484 |
| 2159 | GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(4556), // Rule ID 793 // |
| 2160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2161 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2162 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2163 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2164 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2165 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2166 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2167 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2168 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2169 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2170 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2171 | // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 2173 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2174 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2175 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 2176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2177 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2178 | GIR_RootConstrainSelectedInstOperands, |
| 2179 | // GIR_Coverage, 793, |
| 2180 | GIR_EraseRootFromParent_Done, |
| 2181 | // Label 142: @4556 |
| 2182 | GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(4628), // Rule ID 792 // |
| 2183 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2185 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2186 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2187 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2188 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2189 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2190 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2191 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2192 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2193 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2194 | // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2195 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 2196 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2197 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2198 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 2199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2200 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2201 | GIR_RootConstrainSelectedInstOperands, |
| 2202 | // GIR_Coverage, 792, |
| 2203 | GIR_EraseRootFromParent_Done, |
| 2204 | // Label 143: @4628 |
| 2205 | GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(4698), // Rule ID 5652 // |
| 2206 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2207 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2208 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2209 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2210 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2211 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2212 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2213 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2214 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2215 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2216 | // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 2217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32), |
| 2218 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2219 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2220 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2221 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2223 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2224 | GIR_RootConstrainSelectedInstOperands, |
| 2225 | // GIR_Coverage, 5652, |
| 2226 | GIR_EraseRootFromParent_Done, |
| 2227 | // Label 144: @4698 |
| 2228 | GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(4755), // Rule ID 5626 // |
| 2229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2230 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2231 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2232 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2233 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2234 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2235 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2236 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2237 | // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 2239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2240 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 2241 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 2242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2243 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2244 | GIR_RootConstrainSelectedInstOperands, |
| 2245 | // GIR_Coverage, 5626, |
| 2246 | GIR_EraseRootFromParent_Done, |
| 2247 | // Label 145: @4755 |
| 2248 | GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(4812), // Rule ID 5621 // |
| 2249 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2250 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2251 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2252 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 2253 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2254 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2255 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2256 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2257 | // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32), |
| 2259 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2260 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 2261 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 2262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2263 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2264 | GIR_RootConstrainSelectedInstOperands, |
| 2265 | // GIR_Coverage, 5621, |
| 2266 | GIR_EraseRootFromParent_Done, |
| 2267 | // Label 146: @4812 |
| 2268 | GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(4869), // Rule ID 5625 // |
| 2269 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2270 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2271 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2272 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2273 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2274 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2275 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2276 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2277 | // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 2279 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2280 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 2281 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 2282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2283 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2284 | GIR_RootConstrainSelectedInstOperands, |
| 2285 | // GIR_Coverage, 5625, |
| 2286 | GIR_EraseRootFromParent_Done, |
| 2287 | // Label 147: @4869 |
| 2288 | GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(4939), // Rule ID 909 // |
| 2289 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2290 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2291 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2292 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2293 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2294 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2295 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2296 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2297 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2298 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2299 | // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 2300 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32), |
| 2301 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2302 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2303 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2304 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2306 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2307 | GIR_RootConstrainSelectedInstOperands, |
| 2308 | // GIR_Coverage, 909, |
| 2309 | GIR_EraseRootFromParent_Done, |
| 2310 | // Label 148: @4939 |
| 2311 | GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(4996), // Rule ID 806 // |
| 2312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2313 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2314 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2315 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2316 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2317 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2318 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2319 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2320 | // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 2322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2323 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2324 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 2325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2326 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2327 | GIR_RootConstrainSelectedInstOperands, |
| 2328 | // GIR_Coverage, 806, |
| 2329 | GIR_EraseRootFromParent_Done, |
| 2330 | // Label 149: @4996 |
| 2331 | GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(5053), // Rule ID 801 // |
| 2332 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2333 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2334 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2335 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2336 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 2337 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2338 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2339 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2340 | // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2341 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32), |
| 2342 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2343 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2344 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 2345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2346 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2347 | GIR_RootConstrainSelectedInstOperands, |
| 2348 | // GIR_Coverage, 801, |
| 2349 | GIR_EraseRootFromParent_Done, |
| 2350 | // Label 150: @5053 |
| 2351 | GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(5110), // Rule ID 805 // |
| 2352 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2353 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2354 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2355 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2356 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2357 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 2358 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2359 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2360 | // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 2361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 2362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2363 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2364 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 2365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2366 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2367 | GIR_RootConstrainSelectedInstOperands, |
| 2368 | // GIR_Coverage, 805, |
| 2369 | GIR_EraseRootFromParent_Done, |
| 2370 | // Label 151: @5110 |
| 2371 | GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(5150), // Rule ID 778 // |
| 2372 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2373 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2374 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2375 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2376 | // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 2377 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i32), |
| 2378 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2379 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2380 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 2381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2382 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2383 | GIR_RootConstrainSelectedInstOperands, |
| 2384 | // GIR_Coverage, 778, |
| 2385 | GIR_EraseRootFromParent_Done, |
| 2386 | // Label 152: @5150 |
| 2387 | GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(5209), // Rule ID 3593 // |
| 2388 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2389 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2390 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2391 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2392 | // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 2393 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 2394 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 2395 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 2396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi32), |
| 2397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 2398 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 2399 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 2400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2401 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2402 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2403 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2404 | GIR_RootConstrainSelectedInstOperands, |
| 2405 | // GIR_Coverage, 3593, |
| 2406 | GIR_EraseRootFromParent_Done, |
| 2407 | // Label 153: @5209 |
| 2408 | GIM_Reject, |
| 2409 | // Label 138: @5210 |
| 2410 | GIM_Reject, |
| 2411 | // Label 83: @5211 |
| 2412 | GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(5395), |
| 2413 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2414 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2415 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2416 | GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(5292), // Rule ID 5647 // |
| 2417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2418 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2419 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2420 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2421 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2422 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2423 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2424 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2425 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2426 | // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8), |
| 2428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2429 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2430 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2431 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2433 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2434 | GIR_RootConstrainSelectedInstOperands, |
| 2435 | // GIR_Coverage, 5647, |
| 2436 | GIR_EraseRootFromParent_Done, |
| 2437 | // Label 155: @5292 |
| 2438 | GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(5358), // Rule ID 904 // |
| 2439 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2440 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2441 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2442 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2443 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2444 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2445 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2446 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2447 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2448 | // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8), |
| 2450 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2451 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2452 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2453 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2455 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2456 | GIR_RootConstrainSelectedInstOperands, |
| 2457 | // GIR_Coverage, 904, |
| 2458 | GIR_EraseRootFromParent_Done, |
| 2459 | // Label 156: @5358 |
| 2460 | GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(5394), // Rule ID 773 // |
| 2461 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2462 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2463 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2464 | // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i8), |
| 2466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2467 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2468 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 2469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2470 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2471 | GIR_RootConstrainSelectedInstOperands, |
| 2472 | // GIR_Coverage, 773, |
| 2473 | GIR_EraseRootFromParent_Done, |
| 2474 | // Label 157: @5394 |
| 2475 | GIM_Reject, |
| 2476 | // Label 154: @5395 |
| 2477 | GIM_Reject, |
| 2478 | // Label 84: @5396 |
| 2479 | GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(6349), |
| 2480 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2481 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 2482 | GIM_Try, /*On fail goto*//*Label 159*/ GIMT_Encode4(5479), // Rule ID 791 // |
| 2483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2485 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2486 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2487 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2488 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2489 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2490 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2491 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2492 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2493 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2494 | // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 2496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2497 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2498 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 2499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2500 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2501 | GIR_RootConstrainSelectedInstOperands, |
| 2502 | // GIR_Coverage, 791, |
| 2503 | GIR_EraseRootFromParent_Done, |
| 2504 | // Label 159: @5479 |
| 2505 | GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(5551), // Rule ID 790 // |
| 2506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2508 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2509 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2510 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2511 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2512 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2513 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2514 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2515 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2516 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2517 | // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 2519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2520 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2521 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 2522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2523 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2524 | GIR_RootConstrainSelectedInstOperands, |
| 2525 | // GIR_Coverage, 790, |
| 2526 | GIR_EraseRootFromParent_Done, |
| 2527 | // Label 160: @5551 |
| 2528 | GIM_Try, /*On fail goto*//*Label 161*/ GIMT_Encode4(5623), // Rule ID 785 // |
| 2529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2531 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2532 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 2533 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2534 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2535 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2536 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 2537 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2538 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2539 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2540 | // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv8i16), |
| 2542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2543 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2544 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 2545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2546 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2547 | GIR_RootConstrainSelectedInstOperands, |
| 2548 | // GIR_Coverage, 785, |
| 2549 | GIR_EraseRootFromParent_Done, |
| 2550 | // Label 161: @5623 |
| 2551 | GIM_Try, /*On fail goto*//*Label 162*/ GIMT_Encode4(5695), // Rule ID 789 // |
| 2552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2553 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2554 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2555 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2556 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2557 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2558 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2559 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2560 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2561 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2562 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2563 | // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 2565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2566 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2567 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 2568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2569 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2570 | GIR_RootConstrainSelectedInstOperands, |
| 2571 | // GIR_Coverage, 789, |
| 2572 | GIR_EraseRootFromParent_Done, |
| 2573 | // Label 162: @5695 |
| 2574 | GIM_Try, /*On fail goto*//*Label 163*/ GIMT_Encode4(5767), // Rule ID 788 // |
| 2575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2577 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2578 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2579 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2580 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2581 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2582 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2583 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2584 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2585 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2586 | // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 2588 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2589 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2590 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 2591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2592 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2593 | GIR_RootConstrainSelectedInstOperands, |
| 2594 | // GIR_Coverage, 788, |
| 2595 | GIR_EraseRootFromParent_Done, |
| 2596 | // Label 163: @5767 |
| 2597 | GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(5837), // Rule ID 5651 // |
| 2598 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2599 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2600 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2601 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2602 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2603 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 2604 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2605 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2606 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2607 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2608 | // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 2609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16), |
| 2610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2611 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2612 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2613 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2615 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2616 | GIR_RootConstrainSelectedInstOperands, |
| 2617 | // GIR_Coverage, 5651, |
| 2618 | GIR_EraseRootFromParent_Done, |
| 2619 | // Label 164: @5837 |
| 2620 | GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(5894), // Rule ID 5624 // |
| 2621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2623 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2624 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2625 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2626 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2627 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2628 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2629 | // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2630 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 2631 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2632 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 2633 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 2634 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2635 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2636 | GIR_RootConstrainSelectedInstOperands, |
| 2637 | // GIR_Coverage, 5624, |
| 2638 | GIR_EraseRootFromParent_Done, |
| 2639 | // Label 165: @5894 |
| 2640 | GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(5951), // Rule ID 5620 // |
| 2641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2643 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2644 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 2645 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2646 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2647 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2648 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2649 | // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16), |
| 2651 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2652 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 2653 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 2654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2655 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2656 | GIR_RootConstrainSelectedInstOperands, |
| 2657 | // GIR_Coverage, 5620, |
| 2658 | GIR_EraseRootFromParent_Done, |
| 2659 | // Label 166: @5951 |
| 2660 | GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(6008), // Rule ID 5623 // |
| 2661 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2663 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2664 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2665 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2666 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2667 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2668 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2669 | // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 2671 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2672 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 2673 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 2674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2675 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2676 | GIR_RootConstrainSelectedInstOperands, |
| 2677 | // GIR_Coverage, 5623, |
| 2678 | GIR_EraseRootFromParent_Done, |
| 2679 | // Label 167: @6008 |
| 2680 | GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(6078), // Rule ID 908 // |
| 2681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2683 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2684 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2685 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2686 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2687 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 2688 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2689 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2690 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2691 | // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 2692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16), |
| 2693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2694 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2695 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2696 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2698 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2699 | GIR_RootConstrainSelectedInstOperands, |
| 2700 | // GIR_Coverage, 908, |
| 2701 | GIR_EraseRootFromParent_Done, |
| 2702 | // Label 168: @6078 |
| 2703 | GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(6135), // Rule ID 804 // |
| 2704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2705 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2706 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2707 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2708 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2709 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2710 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2711 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2712 | // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2713 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 2714 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2715 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2716 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 2717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2718 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2719 | GIR_RootConstrainSelectedInstOperands, |
| 2720 | // GIR_Coverage, 804, |
| 2721 | GIR_EraseRootFromParent_Done, |
| 2722 | // Label 169: @6135 |
| 2723 | GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(6192), // Rule ID 800 // |
| 2724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2725 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2726 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2727 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2728 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 2729 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2730 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2731 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2732 | // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16), |
| 2734 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2735 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2736 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 2737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2738 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2739 | GIR_RootConstrainSelectedInstOperands, |
| 2740 | // GIR_Coverage, 800, |
| 2741 | GIR_EraseRootFromParent_Done, |
| 2742 | // Label 170: @6192 |
| 2743 | GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(6249), // Rule ID 803 // |
| 2744 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2745 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2746 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2747 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2748 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2749 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2750 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2751 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2752 | // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2753 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 2754 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2755 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2756 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 2757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2758 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2759 | GIR_RootConstrainSelectedInstOperands, |
| 2760 | // GIR_Coverage, 803, |
| 2761 | GIR_EraseRootFromParent_Done, |
| 2762 | // Label 171: @6249 |
| 2763 | GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(6289), // Rule ID 777 // |
| 2764 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2765 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2766 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2767 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2768 | // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 2769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i16), |
| 2770 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2771 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2772 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 2773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2774 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2775 | GIR_RootConstrainSelectedInstOperands, |
| 2776 | // GIR_Coverage, 777, |
| 2777 | GIR_EraseRootFromParent_Done, |
| 2778 | // Label 172: @6289 |
| 2779 | GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(6348), // Rule ID 3589 // |
| 2780 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2781 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2782 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2783 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2784 | // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 2785 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 2786 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 2787 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 2788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi16), |
| 2789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 2790 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 2791 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 2792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2793 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2794 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2795 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2796 | GIR_RootConstrainSelectedInstOperands, |
| 2797 | // GIR_Coverage, 3589, |
| 2798 | GIR_EraseRootFromParent_Done, |
| 2799 | // Label 173: @6348 |
| 2800 | GIM_Reject, |
| 2801 | // Label 158: @6349 |
| 2802 | GIM_Reject, |
| 2803 | // Label 85: @6350 |
| 2804 | GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(6601), |
| 2805 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2806 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2807 | GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(6431), // Rule ID 5650 // |
| 2808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2810 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2811 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2812 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2813 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2814 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2815 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2816 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2817 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2818 | // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 2819 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8), |
| 2820 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2821 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2822 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2823 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2825 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2826 | GIR_RootConstrainSelectedInstOperands, |
| 2827 | // GIR_Coverage, 5650, |
| 2828 | GIR_EraseRootFromParent_Done, |
| 2829 | // Label 175: @6431 |
| 2830 | GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(6501), // Rule ID 907 // |
| 2831 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2832 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2833 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2834 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2835 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2836 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2837 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2838 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2839 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2840 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2841 | // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 2842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8), |
| 2843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2844 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2845 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2846 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2848 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2849 | GIR_RootConstrainSelectedInstOperands, |
| 2850 | // GIR_Coverage, 907, |
| 2851 | GIR_EraseRootFromParent_Done, |
| 2852 | // Label 176: @6501 |
| 2853 | GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(6541), // Rule ID 776 // |
| 2854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2855 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2856 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2857 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2858 | // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 2859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv16i8), |
| 2860 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2861 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2862 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 2863 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2864 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2865 | GIR_RootConstrainSelectedInstOperands, |
| 2866 | // GIR_Coverage, 776, |
| 2867 | GIR_EraseRootFromParent_Done, |
| 2868 | // Label 177: @6541 |
| 2869 | GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(6600), // Rule ID 3585 // |
| 2870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2872 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2873 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2874 | // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 2875 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 2876 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 2877 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 2878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi8), |
| 2879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 2880 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 2881 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 2882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2883 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2884 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2885 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2886 | GIR_RootConstrainSelectedInstOperands, |
| 2887 | // GIR_Coverage, 3585, |
| 2888 | GIR_EraseRootFromParent_Done, |
| 2889 | // Label 178: @6600 |
| 2890 | GIM_Reject, |
| 2891 | // Label 174: @6601 |
| 2892 | GIM_Reject, |
| 2893 | // Label 86: @6602 |
| 2894 | GIM_Reject, |
| 2895 | // Label 1: @6603 |
| 2896 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 188*/ GIMT_Encode4(9750), |
| 2897 | /*GILLT_s32*//*Label 179*/ GIMT_Encode4(6674), |
| 2898 | /*GILLT_s64*//*Label 180*/ GIMT_Encode4(7198), GIMT_Encode4(0), |
| 2899 | /*GILLT_v2s32*//*Label 181*/ GIMT_Encode4(7245), |
| 2900 | /*GILLT_v2s64*//*Label 182*/ GIMT_Encode4(7360), GIMT_Encode4(0), |
| 2901 | /*GILLT_v4s16*//*Label 183*/ GIMT_Encode4(7912), |
| 2902 | /*GILLT_v4s32*//*Label 184*/ GIMT_Encode4(8027), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2903 | /*GILLT_v8s8*//*Label 185*/ GIMT_Encode4(8740), |
| 2904 | /*GILLT_v8s16*//*Label 186*/ GIMT_Encode4(8855), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2905 | /*GILLT_v16s8*//*Label 187*/ GIMT_Encode4(9568), |
| 2906 | // Label 179: @6674 |
| 2907 | GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(7197), |
| 2908 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 2909 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 2910 | GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(6742), // Rule ID 96 // |
| 2911 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 2912 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2913 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2914 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2915 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 2916 | // MIs[1] Operand 1 |
| 2917 | // No operand predicates |
| 2918 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2919 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2920 | // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn) => (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RSBri), |
| 2922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2923 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2924 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2926 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2927 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2928 | GIR_RootConstrainSelectedInstOperands, |
| 2929 | // GIR_Coverage, 96, |
| 2930 | GIR_EraseRootFromParent_Done, |
| 2931 | // Label 190: @6742 |
| 2932 | GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(6799), // Rule ID 435 // |
| 2933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 2934 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2935 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2936 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2937 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 2938 | // MIs[1] Operand 1 |
| 2939 | // No operand predicates |
| 2940 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2941 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2942 | // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn) => (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RSBri), |
| 2944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2945 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2946 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2948 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2949 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2950 | GIR_RootConstrainSelectedInstOperands, |
| 2951 | // GIR_Coverage, 435, |
| 2952 | GIR_EraseRootFromParent_Done, |
| 2953 | // Label 191: @6799 |
| 2954 | GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(6856), // Rule ID 76 // |
| 2955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 2956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2957 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2958 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2959 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2960 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 2961 | // MIs[1] Operand 1 |
| 2962 | // No operand predicates |
| 2963 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2964 | // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBri), |
| 2966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2967 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2968 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2970 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2971 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2972 | GIR_RootConstrainSelectedInstOperands, |
| 2973 | // GIR_Coverage, 76, |
| 2974 | GIR_EraseRootFromParent_Done, |
| 2975 | // Label 192: @6856 |
| 2976 | GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(6913), // Rule ID 419 // |
| 2977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 2978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2979 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2980 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2981 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2982 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 2983 | // MIs[1] Operand 1 |
| 2984 | // No operand predicates |
| 2985 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2986 | // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri), |
| 2988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2989 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2990 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2992 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2993 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2994 | GIR_RootConstrainSelectedInstOperands, |
| 2995 | // GIR_Coverage, 419, |
| 2996 | GIR_EraseRootFromParent_Done, |
| 2997 | // Label 193: @6913 |
| 2998 | GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(6964), // Rule ID 420 // |
| 2999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 3000 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 3001 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 3002 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3003 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 3004 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095), |
| 3005 | // MIs[1] Operand 1 |
| 3006 | // No operand predicates |
| 3007 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3008 | // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 3009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri12), |
| 3010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 3011 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 3012 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 3013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3014 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3015 | GIR_RootConstrainSelectedInstOperands, |
| 3016 | // GIR_Coverage, 420, |
| 3017 | GIR_EraseRootFromParent_Done, |
| 3018 | // Label 194: @6964 |
| 3019 | GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(7034), // Rule ID 173 // |
| 3020 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM_UseMulOps), |
| 3021 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 3022 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 3023 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3024 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3025 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3026 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3027 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 3028 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 3029 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3030 | // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 3031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLS), |
| 3032 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 3033 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3034 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 3035 | GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 3036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3037 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3038 | GIR_RootConstrainSelectedInstOperands, |
| 3039 | // GIR_Coverage, 173, |
| 3040 | GIR_EraseRootFromParent_Done, |
| 3041 | // Label 195: @7034 |
| 3042 | GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(7104), // Rule ID 512 // |
| 3043 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), |
| 3044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 3045 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 3046 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3047 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3048 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3049 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3050 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 3051 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 3052 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3053 | // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 3054 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLS), |
| 3055 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 3056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3057 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 3058 | GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 3059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3060 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3061 | GIR_RootConstrainSelectedInstOperands, |
| 3062 | // GIR_Coverage, 512, |
| 3063 | GIR_EraseRootFromParent_Done, |
| 3064 | // Label 196: @7104 |
| 3065 | GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(7150), // Rule ID 77 // |
| 3066 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 3067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 3068 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 3069 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 3070 | // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 3071 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBrr), |
| 3072 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 3073 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 3074 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 3075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3076 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3077 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3078 | GIR_RootConstrainSelectedInstOperands, |
| 3079 | // GIR_Coverage, 77, |
| 3080 | GIR_EraseRootFromParent_Done, |
| 3081 | // Label 197: @7150 |
| 3082 | GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(7196), // Rule ID 421 // |
| 3083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 3084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 3085 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 3086 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 3087 | // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 3088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBrr), |
| 3089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 3090 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 3091 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 3092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3093 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3094 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3095 | GIR_RootConstrainSelectedInstOperands, |
| 3096 | // GIR_Coverage, 421, |
| 3097 | GIR_EraseRootFromParent_Done, |
| 3098 | // Label 198: @7196 |
| 3099 | GIM_Reject, |
| 3100 | // Label 189: @7197 |
| 3101 | GIM_Reject, |
| 3102 | // Label 180: @7198 |
| 3103 | GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(7244), // Rule ID 983 // |
| 3104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3105 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 3106 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 3107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3108 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3109 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3110 | // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 3111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv1i64), |
| 3112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3113 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3114 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3116 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3117 | GIR_RootConstrainSelectedInstOperands, |
| 3118 | // GIR_Coverage, 983, |
| 3119 | GIR_EraseRootFromParent_Done, |
| 3120 | // Label 199: @7244 |
| 3121 | GIM_Reject, |
| 3122 | // Label 181: @7245 |
| 3123 | GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(7359), |
| 3124 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3125 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3126 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3127 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3128 | GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(7326), // Rule ID 934 // |
| 3129 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3130 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3131 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3132 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3133 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3134 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3135 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3136 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3137 | // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv2i32), |
| 3139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3140 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3141 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3142 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3144 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3145 | GIR_RootConstrainSelectedInstOperands, |
| 3146 | // GIR_Coverage, 934, |
| 3147 | GIR_EraseRootFromParent_Done, |
| 3148 | // Label 201: @7326 |
| 3149 | GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(7358), // Rule ID 979 // |
| 3150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3151 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3152 | // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3153 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i32), |
| 3154 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3155 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3156 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3158 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3159 | GIR_RootConstrainSelectedInstOperands, |
| 3160 | // GIR_Coverage, 979, |
| 3161 | GIR_EraseRootFromParent_Done, |
| 3162 | // Label 202: @7358 |
| 3163 | GIM_Reject, |
| 3164 | // Label 200: @7359 |
| 3165 | GIM_Reject, |
| 3166 | // Label 182: @7360 |
| 3167 | GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(7911), |
| 3168 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3169 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 3170 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3171 | GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(7443), // Rule ID 1003 // |
| 3172 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3173 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3174 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3175 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3176 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3177 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3178 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3179 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3180 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3181 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3182 | // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3183 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 3184 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3185 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3186 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3188 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3189 | GIR_RootConstrainSelectedInstOperands, |
| 3190 | // GIR_Coverage, 1003, |
| 3191 | GIR_EraseRootFromParent_Done, |
| 3192 | // Label 204: @7443 |
| 3193 | GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(7511), // Rule ID 1002 // |
| 3194 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3195 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3196 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3197 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3198 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3199 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3200 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3201 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3202 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3203 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3204 | // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3205 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 3206 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3207 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3208 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3210 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3211 | GIR_RootConstrainSelectedInstOperands, |
| 3212 | // GIR_Coverage, 1002, |
| 3213 | GIR_EraseRootFromParent_Done, |
| 3214 | // Label 205: @7511 |
| 3215 | GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(7579), // Rule ID 991 // |
| 3216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3217 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3218 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3219 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3220 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3221 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3222 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3223 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3224 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3225 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3226 | // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3227 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv2i64), |
| 3228 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3229 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3230 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3232 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3233 | GIR_RootConstrainSelectedInstOperands, |
| 3234 | // GIR_Coverage, 991, |
| 3235 | GIR_EraseRootFromParent_Done, |
| 3236 | // Label 206: @7579 |
| 3237 | GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(7647), // Rule ID 1001 // |
| 3238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3239 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3240 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3241 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3242 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3243 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3244 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3245 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3246 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3247 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3248 | // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 3250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3251 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3252 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3254 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3255 | GIR_RootConstrainSelectedInstOperands, |
| 3256 | // GIR_Coverage, 1001, |
| 3257 | GIR_EraseRootFromParent_Done, |
| 3258 | // Label 207: @7647 |
| 3259 | GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(7715), // Rule ID 1000 // |
| 3260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3261 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3262 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3263 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3264 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3265 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3266 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3267 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3268 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3269 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3270 | // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3271 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 3272 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3273 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3274 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3276 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3277 | GIR_RootConstrainSelectedInstOperands, |
| 3278 | // GIR_Coverage, 1000, |
| 3279 | GIR_EraseRootFromParent_Done, |
| 3280 | // Label 208: @7715 |
| 3281 | GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(7768), // Rule ID 1012 // |
| 3282 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3283 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3284 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3285 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3286 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3287 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3288 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3289 | // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64), |
| 3291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3292 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3293 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3295 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3296 | GIR_RootConstrainSelectedInstOperands, |
| 3297 | // GIR_Coverage, 1012, |
| 3298 | GIR_EraseRootFromParent_Done, |
| 3299 | // Label 209: @7768 |
| 3300 | GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(7821), // Rule ID 1006 // |
| 3301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3302 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3303 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3304 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3305 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3306 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3307 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3308 | // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv2i64), |
| 3310 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3311 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3312 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3314 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3315 | GIR_RootConstrainSelectedInstOperands, |
| 3316 | // GIR_Coverage, 1006, |
| 3317 | GIR_EraseRootFromParent_Done, |
| 3318 | // Label 210: @7821 |
| 3319 | GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(7874), // Rule ID 1011 // |
| 3320 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3321 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3322 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3323 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3324 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3325 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3326 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3327 | // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64), |
| 3329 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3330 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3331 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3333 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3334 | GIR_RootConstrainSelectedInstOperands, |
| 3335 | // GIR_Coverage, 1011, |
| 3336 | GIR_EraseRootFromParent_Done, |
| 3337 | // Label 211: @7874 |
| 3338 | GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(7910), // Rule ID 984 // |
| 3339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3340 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3341 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3342 | // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 3343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i64), |
| 3344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3345 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3346 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3348 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3349 | GIR_RootConstrainSelectedInstOperands, |
| 3350 | // GIR_Coverage, 984, |
| 3351 | GIR_EraseRootFromParent_Done, |
| 3352 | // Label 212: @7910 |
| 3353 | GIM_Reject, |
| 3354 | // Label 203: @7911 |
| 3355 | GIM_Reject, |
| 3356 | // Label 183: @7912 |
| 3357 | GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(8026), |
| 3358 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3359 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3360 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3361 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3362 | GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(7993), // Rule ID 933 // |
| 3363 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3364 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3365 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3366 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3367 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3368 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3369 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3370 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3371 | // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3372 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i16), |
| 3373 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3374 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3375 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3376 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3377 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3378 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3379 | GIR_RootConstrainSelectedInstOperands, |
| 3380 | // GIR_Coverage, 933, |
| 3381 | GIR_EraseRootFromParent_Done, |
| 3382 | // Label 214: @7993 |
| 3383 | GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(8025), // Rule ID 978 // |
| 3384 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3385 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3386 | // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i16), |
| 3388 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3389 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3390 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3392 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3393 | GIR_RootConstrainSelectedInstOperands, |
| 3394 | // GIR_Coverage, 978, |
| 3395 | GIR_EraseRootFromParent_Done, |
| 3396 | // Label 215: @8025 |
| 3397 | GIM_Reject, |
| 3398 | // Label 213: @8026 |
| 3399 | GIM_Reject, |
| 3400 | // Label 184: @8027 |
| 3401 | GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(8739), |
| 3402 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3403 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3404 | GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(8110), // Rule ID 999 // |
| 3405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3407 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3408 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3409 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3410 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3411 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3412 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3413 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3414 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3415 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3416 | // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 3418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3419 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3420 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3422 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3423 | GIR_RootConstrainSelectedInstOperands, |
| 3424 | // GIR_Coverage, 999, |
| 3425 | GIR_EraseRootFromParent_Done, |
| 3426 | // Label 217: @8110 |
| 3427 | GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(8182), // Rule ID 998 // |
| 3428 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3429 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3430 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3431 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3432 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3433 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3434 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3435 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3436 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3437 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3438 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3439 | // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 3441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3442 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3445 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3446 | GIR_RootConstrainSelectedInstOperands, |
| 3447 | // GIR_Coverage, 998, |
| 3448 | GIR_EraseRootFromParent_Done, |
| 3449 | // Label 218: @8182 |
| 3450 | GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(8254), // Rule ID 990 // |
| 3451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3452 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3453 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3454 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3455 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3456 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3457 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3458 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3459 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3460 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3461 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3462 | // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv4i32), |
| 3464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3468 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3469 | GIR_RootConstrainSelectedInstOperands, |
| 3470 | // GIR_Coverage, 990, |
| 3471 | GIR_EraseRootFromParent_Done, |
| 3472 | // Label 219: @8254 |
| 3473 | GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(8326), // Rule ID 997 // |
| 3474 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3475 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3476 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3477 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3478 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3479 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3480 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3481 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3482 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3483 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3484 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3485 | // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 3487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3488 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3489 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3491 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3492 | GIR_RootConstrainSelectedInstOperands, |
| 3493 | // GIR_Coverage, 997, |
| 3494 | GIR_EraseRootFromParent_Done, |
| 3495 | // Label 220: @8326 |
| 3496 | GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(8398), // Rule ID 996 // |
| 3497 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3499 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3500 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3501 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3502 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3503 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3504 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3505 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3506 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3507 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3508 | // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3509 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 3510 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3511 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3512 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3514 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3515 | GIR_RootConstrainSelectedInstOperands, |
| 3516 | // GIR_Coverage, 996, |
| 3517 | GIR_EraseRootFromParent_Done, |
| 3518 | // Label 221: @8398 |
| 3519 | GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(8468), // Rule ID 937 // |
| 3520 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3522 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3523 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3524 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3525 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3526 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3527 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3528 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3529 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3530 | // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 3531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i32), |
| 3532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3533 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3534 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3535 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3537 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3538 | GIR_RootConstrainSelectedInstOperands, |
| 3539 | // GIR_Coverage, 937, |
| 3540 | GIR_EraseRootFromParent_Done, |
| 3541 | // Label 222: @8468 |
| 3542 | GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(8525), // Rule ID 1010 // |
| 3543 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3544 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3545 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3546 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3547 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3548 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3549 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3550 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3551 | // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32), |
| 3553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3554 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3555 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3557 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3558 | GIR_RootConstrainSelectedInstOperands, |
| 3559 | // GIR_Coverage, 1010, |
| 3560 | GIR_EraseRootFromParent_Done, |
| 3561 | // Label 223: @8525 |
| 3562 | GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(8582), // Rule ID 1005 // |
| 3563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3565 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3566 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3567 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3568 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3569 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3570 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3571 | // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv4i32), |
| 3573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3574 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3575 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3577 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3578 | GIR_RootConstrainSelectedInstOperands, |
| 3579 | // GIR_Coverage, 1005, |
| 3580 | GIR_EraseRootFromParent_Done, |
| 3581 | // Label 224: @8582 |
| 3582 | GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(8639), // Rule ID 1009 // |
| 3583 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3585 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3586 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3587 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3588 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3589 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3590 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3591 | // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32), |
| 3593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3594 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3595 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3597 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3598 | GIR_RootConstrainSelectedInstOperands, |
| 3599 | // GIR_Coverage, 1009, |
| 3600 | GIR_EraseRootFromParent_Done, |
| 3601 | // Label 225: @8639 |
| 3602 | GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(8679), // Rule ID 982 // |
| 3603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3604 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3605 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3606 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3607 | // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 3608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i32), |
| 3609 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3610 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3611 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3613 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3614 | GIR_RootConstrainSelectedInstOperands, |
| 3615 | // GIR_Coverage, 982, |
| 3616 | GIR_EraseRootFromParent_Done, |
| 3617 | // Label 226: @8679 |
| 3618 | GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(8738), // Rule ID 3605 // |
| 3619 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 3620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3621 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3622 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3623 | // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 3624 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3625 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3626 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 3627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi32), |
| 3628 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 3629 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 3630 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 3631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3632 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3633 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3634 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3635 | GIR_RootConstrainSelectedInstOperands, |
| 3636 | // GIR_Coverage, 3605, |
| 3637 | GIR_EraseRootFromParent_Done, |
| 3638 | // Label 227: @8738 |
| 3639 | GIM_Reject, |
| 3640 | // Label 216: @8739 |
| 3641 | GIM_Reject, |
| 3642 | // Label 185: @8740 |
| 3643 | GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(8854), |
| 3644 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3645 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3646 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3647 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3648 | GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(8821), // Rule ID 932 // |
| 3649 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3650 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3651 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3652 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3653 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3654 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3655 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3656 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3657 | // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i8), |
| 3659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3660 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3661 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3662 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3664 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3665 | GIR_RootConstrainSelectedInstOperands, |
| 3666 | // GIR_Coverage, 932, |
| 3667 | GIR_EraseRootFromParent_Done, |
| 3668 | // Label 229: @8821 |
| 3669 | GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(8853), // Rule ID 977 // |
| 3670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3671 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3672 | // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i8), |
| 3674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3675 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3676 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3678 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3679 | GIR_RootConstrainSelectedInstOperands, |
| 3680 | // GIR_Coverage, 977, |
| 3681 | GIR_EraseRootFromParent_Done, |
| 3682 | // Label 230: @8853 |
| 3683 | GIM_Reject, |
| 3684 | // Label 228: @8854 |
| 3685 | GIM_Reject, |
| 3686 | // Label 186: @8855 |
| 3687 | GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(9567), |
| 3688 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3689 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3690 | GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(8938), // Rule ID 995 // |
| 3691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3693 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3694 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3695 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3696 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3697 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3698 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3699 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3700 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3701 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3702 | // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3703 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 3704 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3705 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3706 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3708 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3709 | GIR_RootConstrainSelectedInstOperands, |
| 3710 | // GIR_Coverage, 995, |
| 3711 | GIR_EraseRootFromParent_Done, |
| 3712 | // Label 232: @8938 |
| 3713 | GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(9010), // Rule ID 994 // |
| 3714 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3715 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3716 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3717 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3718 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3719 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3720 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3721 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3722 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3723 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3724 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3725 | // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 3727 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3728 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3729 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3731 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3732 | GIR_RootConstrainSelectedInstOperands, |
| 3733 | // GIR_Coverage, 994, |
| 3734 | GIR_EraseRootFromParent_Done, |
| 3735 | // Label 233: @9010 |
| 3736 | GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(9082), // Rule ID 989 // |
| 3737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3738 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3739 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3740 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3741 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3742 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3743 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3744 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3745 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3746 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3747 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3748 | // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv8i16), |
| 3750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3751 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3752 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3754 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3755 | GIR_RootConstrainSelectedInstOperands, |
| 3756 | // GIR_Coverage, 989, |
| 3757 | GIR_EraseRootFromParent_Done, |
| 3758 | // Label 234: @9082 |
| 3759 | GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(9154), // Rule ID 993 // |
| 3760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3762 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3763 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3764 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3765 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3766 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3767 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3768 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3769 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3770 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3771 | // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3772 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 3773 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3774 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3775 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3777 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3778 | GIR_RootConstrainSelectedInstOperands, |
| 3779 | // GIR_Coverage, 993, |
| 3780 | GIR_EraseRootFromParent_Done, |
| 3781 | // Label 235: @9154 |
| 3782 | GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(9226), // Rule ID 992 // |
| 3783 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3785 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3786 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3787 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3788 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3789 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3790 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3791 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3792 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3793 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3794 | // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3795 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 3796 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3797 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3798 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3800 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3801 | GIR_RootConstrainSelectedInstOperands, |
| 3802 | // GIR_Coverage, 992, |
| 3803 | GIR_EraseRootFromParent_Done, |
| 3804 | // Label 236: @9226 |
| 3805 | GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(9296), // Rule ID 936 // |
| 3806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3807 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3808 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3809 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3810 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3811 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3812 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3813 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3814 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3815 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3816 | // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3817 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i16), |
| 3818 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3819 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3820 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3821 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3823 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3824 | GIR_RootConstrainSelectedInstOperands, |
| 3825 | // GIR_Coverage, 936, |
| 3826 | GIR_EraseRootFromParent_Done, |
| 3827 | // Label 237: @9296 |
| 3828 | GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(9353), // Rule ID 1008 // |
| 3829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3831 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3832 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3833 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3834 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3835 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3836 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3837 | // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16), |
| 3839 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3840 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3841 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3843 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3844 | GIR_RootConstrainSelectedInstOperands, |
| 3845 | // GIR_Coverage, 1008, |
| 3846 | GIR_EraseRootFromParent_Done, |
| 3847 | // Label 238: @9353 |
| 3848 | GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(9410), // Rule ID 1004 // |
| 3849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3851 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3852 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3853 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3854 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3855 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3856 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3857 | // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv8i16), |
| 3859 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3860 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3861 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3862 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3863 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3864 | GIR_RootConstrainSelectedInstOperands, |
| 3865 | // GIR_Coverage, 1004, |
| 3866 | GIR_EraseRootFromParent_Done, |
| 3867 | // Label 239: @9410 |
| 3868 | GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(9467), // Rule ID 1007 // |
| 3869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3870 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3871 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3872 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3873 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3874 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3875 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3876 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3877 | // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16), |
| 3879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3880 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3881 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3883 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3884 | GIR_RootConstrainSelectedInstOperands, |
| 3885 | // GIR_Coverage, 1007, |
| 3886 | GIR_EraseRootFromParent_Done, |
| 3887 | // Label 240: @9467 |
| 3888 | GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(9507), // Rule ID 981 // |
| 3889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3891 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3892 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3893 | // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i16), |
| 3895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3896 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3897 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3899 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3900 | GIR_RootConstrainSelectedInstOperands, |
| 3901 | // GIR_Coverage, 981, |
| 3902 | GIR_EraseRootFromParent_Done, |
| 3903 | // Label 241: @9507 |
| 3904 | GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(9566), // Rule ID 3601 // |
| 3905 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 3906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3907 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3908 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3909 | // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 3910 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3911 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3912 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 3913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi16), |
| 3914 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 3915 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 3916 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 3917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3918 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3919 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3920 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3921 | GIR_RootConstrainSelectedInstOperands, |
| 3922 | // GIR_Coverage, 3601, |
| 3923 | GIR_EraseRootFromParent_Done, |
| 3924 | // Label 242: @9566 |
| 3925 | GIM_Reject, |
| 3926 | // Label 231: @9567 |
| 3927 | GIM_Reject, |
| 3928 | // Label 187: @9568 |
| 3929 | GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(9749), |
| 3930 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3931 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3932 | GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(9649), // Rule ID 935 // |
| 3933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3934 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3935 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3936 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3937 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3938 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3939 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3940 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3941 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3942 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3943 | // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3944 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv16i8), |
| 3945 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3946 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3947 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3948 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3950 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3951 | GIR_RootConstrainSelectedInstOperands, |
| 3952 | // GIR_Coverage, 935, |
| 3953 | GIR_EraseRootFromParent_Done, |
| 3954 | // Label 244: @9649 |
| 3955 | GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(9689), // Rule ID 980 // |
| 3956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3957 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3958 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3959 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3960 | // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3961 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv16i8), |
| 3962 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3963 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3964 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3966 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3967 | GIR_RootConstrainSelectedInstOperands, |
| 3968 | // GIR_Coverage, 980, |
| 3969 | GIR_EraseRootFromParent_Done, |
| 3970 | // Label 245: @9689 |
| 3971 | GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(9748), // Rule ID 3597 // |
| 3972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 3973 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3974 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3975 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3976 | // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 3977 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3978 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3979 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 3980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi8), |
| 3981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 3982 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 3983 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 3984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3985 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3986 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3987 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3988 | GIR_RootConstrainSelectedInstOperands, |
| 3989 | // GIR_Coverage, 3597, |
| 3990 | GIR_EraseRootFromParent_Done, |
| 3991 | // Label 246: @9748 |
| 3992 | GIM_Reject, |
| 3993 | // Label 243: @9749 |
| 3994 | GIM_Reject, |
| 3995 | // Label 188: @9750 |
| 3996 | GIM_Reject, |
| 3997 | // Label 2: @9751 |
| 3998 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 254*/ GIMT_Encode4(10620), |
| 3999 | /*GILLT_s32*//*Label 247*/ GIMT_Encode4(9822), GIMT_Encode4(0), GIMT_Encode4(0), |
| 4000 | /*GILLT_v2s32*//*Label 248*/ GIMT_Encode4(10143), GIMT_Encode4(0), GIMT_Encode4(0), |
| 4001 | /*GILLT_v4s16*//*Label 249*/ GIMT_Encode4(10190), |
| 4002 | /*GILLT_v4s32*//*Label 250*/ GIMT_Encode4(10237), GIMT_Encode4(0), GIMT_Encode4(0), |
| 4003 | /*GILLT_v8s8*//*Label 251*/ GIMT_Encode4(10349), |
| 4004 | /*GILLT_v8s16*//*Label 252*/ GIMT_Encode4(10396), GIMT_Encode4(0), GIMT_Encode4(0), |
| 4005 | /*GILLT_v16s8*//*Label 253*/ GIMT_Encode4(10508), |
| 4006 | // Label 247: @9822 |
| 4007 | GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(10142), |
| 4008 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 4009 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4010 | GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(9921), // Rule ID 186 // |
| 4011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 4012 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4013 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4014 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 4015 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4016 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4017 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4018 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 4019 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4020 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 4021 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 4022 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 4023 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4024 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 4025 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4026 | // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 4027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT), |
| 4028 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4029 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4030 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 4031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4032 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4033 | GIR_RootConstrainSelectedInstOperands, |
| 4034 | // GIR_Coverage, 186, |
| 4035 | GIR_EraseRootFromParent_Done, |
| 4036 | // Label 256: @9921 |
| 4037 | GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(10009), // Rule ID 523 // |
| 4038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 4039 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4040 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4041 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 4042 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4043 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4044 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4045 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 4046 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4047 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 4048 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 4049 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 4050 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4051 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 4052 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4053 | // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 4054 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT), |
| 4055 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4057 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 4058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4059 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4060 | GIR_RootConstrainSelectedInstOperands, |
| 4061 | // GIR_Coverage, 523, |
| 4062 | GIR_EraseRootFromParent_Done, |
| 4063 | // Label 257: @10009 |
| 4064 | GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(10055), // Rule ID 169 // |
| 4065 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 4066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4067 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4068 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4069 | // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 4070 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MUL), |
| 4071 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4072 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4073 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4075 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4076 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4077 | GIR_RootConstrainSelectedInstOperands, |
| 4078 | // GIR_Coverage, 169, |
| 4079 | GIR_EraseRootFromParent_Done, |
| 4080 | // Label 258: @10055 |
| 4081 | GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(10101), // Rule ID 170 // |
| 4082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6_UseMulOps), |
| 4083 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4084 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4085 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4086 | // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 4087 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MULv5), |
| 4088 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4089 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4090 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4092 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4093 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4094 | GIR_RootConstrainSelectedInstOperands, |
| 4095 | // GIR_Coverage, 170, |
| 4096 | GIR_EraseRootFromParent_Done, |
| 4097 | // Label 259: @10101 |
| 4098 | GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(10141), // Rule ID 510 // |
| 4099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4101 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4102 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4103 | // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 4104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MUL), |
| 4105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4106 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4107 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4109 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4110 | GIR_RootConstrainSelectedInstOperands, |
| 4111 | // GIR_Coverage, 510, |
| 4112 | GIR_EraseRootFromParent_Done, |
| 4113 | // Label 260: @10141 |
| 4114 | GIM_Reject, |
| 4115 | // Label 255: @10142 |
| 4116 | GIM_Reject, |
| 4117 | // Label 248: @10143 |
| 4118 | GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(10189), // Rule ID 854 // |
| 4119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4120 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4121 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4123 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4124 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4125 | // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv2i32), |
| 4127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4128 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4129 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4131 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4132 | GIR_RootConstrainSelectedInstOperands, |
| 4133 | // GIR_Coverage, 854, |
| 4134 | GIR_EraseRootFromParent_Done, |
| 4135 | // Label 261: @10189 |
| 4136 | GIM_Reject, |
| 4137 | // Label 249: @10190 |
| 4138 | GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(10236), // Rule ID 853 // |
| 4139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4140 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4141 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4143 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4144 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4145 | // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4146 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i16), |
| 4147 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4148 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4149 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4151 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4152 | GIR_RootConstrainSelectedInstOperands, |
| 4153 | // GIR_Coverage, 853, |
| 4154 | GIR_EraseRootFromParent_Done, |
| 4155 | // Label 262: @10236 |
| 4156 | GIM_Reject, |
| 4157 | // Label 250: @10237 |
| 4158 | GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(10348), |
| 4159 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4160 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4161 | GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(10288), // Rule ID 857 // |
| 4162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4163 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4164 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4165 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4166 | // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4167 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i32), |
| 4168 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4169 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4170 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4172 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4173 | GIR_RootConstrainSelectedInstOperands, |
| 4174 | // GIR_Coverage, 857, |
| 4175 | GIR_EraseRootFromParent_Done, |
| 4176 | // Label 264: @10288 |
| 4177 | GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(10347), // Rule ID 3563 // |
| 4178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 4179 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4180 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4181 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4182 | // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 4183 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 4184 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4185 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 4186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi32), |
| 4187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 4188 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 4189 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 4190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4191 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4192 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4193 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4194 | GIR_RootConstrainSelectedInstOperands, |
| 4195 | // GIR_Coverage, 3563, |
| 4196 | GIR_EraseRootFromParent_Done, |
| 4197 | // Label 265: @10347 |
| 4198 | GIM_Reject, |
| 4199 | // Label 263: @10348 |
| 4200 | GIM_Reject, |
| 4201 | // Label 251: @10349 |
| 4202 | GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(10395), // Rule ID 852 // |
| 4203 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4204 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4205 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4206 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4207 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4208 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4209 | // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i8), |
| 4211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4212 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4213 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4215 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4216 | GIR_RootConstrainSelectedInstOperands, |
| 4217 | // GIR_Coverage, 852, |
| 4218 | GIR_EraseRootFromParent_Done, |
| 4219 | // Label 266: @10395 |
| 4220 | GIM_Reject, |
| 4221 | // Label 252: @10396 |
| 4222 | GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(10507), |
| 4223 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4224 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4225 | GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(10447), // Rule ID 856 // |
| 4226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4227 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4228 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4229 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4230 | // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 4231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i16), |
| 4232 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4233 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4234 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4236 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4237 | GIR_RootConstrainSelectedInstOperands, |
| 4238 | // GIR_Coverage, 856, |
| 4239 | GIR_EraseRootFromParent_Done, |
| 4240 | // Label 268: @10447 |
| 4241 | GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(10506), // Rule ID 3559 // |
| 4242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 4243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4244 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4245 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4246 | // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 4247 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 4248 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4249 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 4250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi16), |
| 4251 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 4252 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 4253 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 4254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4255 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4256 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4257 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4258 | GIR_RootConstrainSelectedInstOperands, |
| 4259 | // GIR_Coverage, 3559, |
| 4260 | GIR_EraseRootFromParent_Done, |
| 4261 | // Label 269: @10506 |
| 4262 | GIM_Reject, |
| 4263 | // Label 267: @10507 |
| 4264 | GIM_Reject, |
| 4265 | // Label 253: @10508 |
| 4266 | GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(10619), |
| 4267 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 4268 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4269 | GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(10559), // Rule ID 855 // |
| 4270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4271 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4272 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4273 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4274 | // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 4275 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv16i8), |
| 4276 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4277 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4278 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4280 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4281 | GIR_RootConstrainSelectedInstOperands, |
| 4282 | // GIR_Coverage, 855, |
| 4283 | GIR_EraseRootFromParent_Done, |
| 4284 | // Label 271: @10559 |
| 4285 | GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(10618), // Rule ID 3555 // |
| 4286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 4287 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4288 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4289 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4290 | // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 4291 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 4292 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4293 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 4294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi8), |
| 4295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 4296 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 4297 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 4298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4299 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4300 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4301 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4302 | GIR_RootConstrainSelectedInstOperands, |
| 4303 | // GIR_Coverage, 3555, |
| 4304 | GIR_EraseRootFromParent_Done, |
| 4305 | // Label 272: @10618 |
| 4306 | GIM_Reject, |
| 4307 | // Label 270: @10619 |
| 4308 | GIM_Reject, |
| 4309 | // Label 254: @10620 |
| 4310 | GIM_Reject, |
| 4311 | // Label 3: @10621 |
| 4312 | GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(10716), |
| 4313 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4314 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 4315 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4316 | GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(10675), // Rule ID 195 // |
| 4317 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), |
| 4318 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4319 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4320 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4321 | // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 4322 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SDIV), |
| 4323 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4324 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4325 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4327 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4328 | GIR_RootConstrainSelectedInstOperands, |
| 4329 | // GIR_Coverage, 195, |
| 4330 | GIR_EraseRootFromParent_Done, |
| 4331 | // Label 274: @10675 |
| 4332 | GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(10715), // Rule ID 540 // |
| 4333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), |
| 4334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4335 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4336 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4337 | // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 4338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SDIV), |
| 4339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4340 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4341 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4343 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4344 | GIR_RootConstrainSelectedInstOperands, |
| 4345 | // GIR_Coverage, 540, |
| 4346 | GIR_EraseRootFromParent_Done, |
| 4347 | // Label 275: @10715 |
| 4348 | GIM_Reject, |
| 4349 | // Label 273: @10716 |
| 4350 | GIM_Reject, |
| 4351 | // Label 4: @10717 |
| 4352 | GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(10812), |
| 4353 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4354 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 4355 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4356 | GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(10771), // Rule ID 196 // |
| 4357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), |
| 4358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4359 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4360 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4361 | // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 4362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDIV), |
| 4363 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4364 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4365 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4367 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4368 | GIR_RootConstrainSelectedInstOperands, |
| 4369 | // GIR_Coverage, 196, |
| 4370 | GIR_EraseRootFromParent_Done, |
| 4371 | // Label 277: @10771 |
| 4372 | GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(10811), // Rule ID 541 // |
| 4373 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), |
| 4374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4375 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4376 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4377 | // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 4378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDIV), |
| 4379 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4380 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4381 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4383 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4384 | GIR_RootConstrainSelectedInstOperands, |
| 4385 | // GIR_Coverage, 541, |
| 4386 | GIR_EraseRootFromParent_Done, |
| 4387 | // Label 278: @10811 |
| 4388 | GIM_Reject, |
| 4389 | // Label 276: @10812 |
| 4390 | GIM_Reject, |
| 4391 | // Label 5: @10813 |
| 4392 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 292*/ GIMT_Encode4(13772), |
| 4393 | /*GILLT_s32*//*Label 279*/ GIMT_Encode4(10884), |
| 4394 | /*GILLT_s64*//*Label 280*/ GIMT_Encode4(12688), |
| 4395 | /*GILLT_v2s1*//*Label 281*/ GIMT_Encode4(12735), |
| 4396 | /*GILLT_v2s32*//*Label 282*/ GIMT_Encode4(12847), |
| 4397 | /*GILLT_v2s64*//*Label 283*/ GIMT_Encode4(12894), |
| 4398 | /*GILLT_v4s1*//*Label 284*/ GIMT_Encode4(13006), |
| 4399 | /*GILLT_v4s16*//*Label 285*/ GIMT_Encode4(13118), |
| 4400 | /*GILLT_v4s32*//*Label 286*/ GIMT_Encode4(13165), GIMT_Encode4(0), |
| 4401 | /*GILLT_v8s1*//*Label 287*/ GIMT_Encode4(13277), |
| 4402 | /*GILLT_v8s8*//*Label 288*/ GIMT_Encode4(13389), |
| 4403 | /*GILLT_v8s16*//*Label 289*/ GIMT_Encode4(13436), GIMT_Encode4(0), |
| 4404 | /*GILLT_v16s1*//*Label 290*/ GIMT_Encode4(13548), |
| 4405 | /*GILLT_v16s8*//*Label 291*/ GIMT_Encode4(13660), |
| 4406 | // Label 279: @10884 |
| 4407 | GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(12687), |
| 4408 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 4409 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4410 | GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(10968), // Rule ID 1879 // |
| 4411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 4412 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4413 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4414 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 4415 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4416 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4417 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4418 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8, |
| 4419 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 4420 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4421 | // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) |
| 4422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 4423 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4424 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src |
| 4425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 4426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4427 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4428 | GIR_RootConstrainSelectedInstOperands, |
| 4429 | // GIR_Coverage, 1879, |
| 4430 | GIR_EraseRootFromParent_Done, |
| 4431 | // Label 294: @10968 |
| 4432 | GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(11041), // Rule ID 2119 // |
| 4433 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 4434 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4435 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4436 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 4437 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4438 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4439 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4440 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8, |
| 4441 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 4442 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4443 | // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) |
| 4444 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 4445 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4446 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src |
| 4447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 4448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4449 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4450 | GIR_RootConstrainSelectedInstOperands, |
| 4451 | // GIR_Coverage, 2119, |
| 4452 | GIR_EraseRootFromParent_Done, |
| 4453 | // Label 295: @11041 |
| 4454 | GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(11089), // Rule ID 2012 // |
| 4455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 4456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4457 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4458 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 4459 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] }) => (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 4460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB), |
| 4461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4462 | GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 4463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4465 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4466 | GIR_RootConstrainSelectedInstOperands, |
| 4467 | // GIR_Coverage, 2012, |
| 4468 | GIR_EraseRootFromParent_Done, |
| 4469 | // Label 296: @11089 |
| 4470 | GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(11137), // Rule ID 2013 // |
| 4471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 4472 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4473 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4474 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 4475 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] }) => (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 4476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTH), |
| 4477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4478 | GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 4479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4481 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4482 | GIR_RootConstrainSelectedInstOperands, |
| 4483 | // GIR_Coverage, 2013, |
| 4484 | GIR_EraseRootFromParent_Done, |
| 4485 | // Label 297: @11137 |
| 4486 | GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(11185), // Rule ID 2014 // |
| 4487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 4488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4489 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4490 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 4491 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 4492 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 4493 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4494 | GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 4495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4497 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4498 | GIR_RootConstrainSelectedInstOperands, |
| 4499 | // GIR_Coverage, 2014, |
| 4500 | GIR_EraseRootFromParent_Done, |
| 4501 | // Label 298: @11185 |
| 4502 | GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(11233), // Rule ID 2234 // |
| 4503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4504 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4505 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4506 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 4507 | // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 4508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB), |
| 4509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4510 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 4511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4513 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4514 | GIR_RootConstrainSelectedInstOperands, |
| 4515 | // GIR_Coverage, 2234, |
| 4516 | GIR_EraseRootFromParent_Done, |
| 4517 | // Label 299: @11233 |
| 4518 | GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(11281), // Rule ID 2235 // |
| 4519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4520 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4521 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4522 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 4523 | // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 4524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTH), |
| 4525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4526 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 4527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4529 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4530 | GIR_RootConstrainSelectedInstOperands, |
| 4531 | // GIR_Coverage, 2235, |
| 4532 | GIR_EraseRootFromParent_Done, |
| 4533 | // Label 300: @11281 |
| 4534 | GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(11329), // Rule ID 2236 // |
| 4535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 4536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4537 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4538 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 4539 | // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 4540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 4541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4542 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 4543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4545 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4546 | GIR_RootConstrainSelectedInstOperands, |
| 4547 | // GIR_Coverage, 2236, |
| 4548 | GIR_EraseRootFromParent_Done, |
| 4549 | // Label 301: @11329 |
| 4550 | GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(11406), // Rule ID 5556 // |
| 4551 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4552 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4553 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4554 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4555 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4556 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4557 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 4558 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4559 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4560 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 4561 | // MIs[2] Operand 1 |
| 4562 | // No operand predicates |
| 4563 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4564 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4565 | // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 4567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4568 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4569 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4571 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4572 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4573 | GIR_RootConstrainSelectedInstOperands, |
| 4574 | // GIR_Coverage, 5556, |
| 4575 | GIR_EraseRootFromParent_Done, |
| 4576 | // Label 302: @11406 |
| 4577 | GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(11483), // Rule ID 5589 // |
| 4578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4580 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4581 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4582 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4583 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4584 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 4585 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4586 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4587 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 4588 | // MIs[2] Operand 1 |
| 4589 | // No operand predicates |
| 4590 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4591 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4592 | // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4593 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 4594 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4595 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4596 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4598 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4599 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4600 | GIR_RootConstrainSelectedInstOperands, |
| 4601 | // GIR_Coverage, 5589, |
| 4602 | GIR_EraseRootFromParent_Done, |
| 4603 | // Label 303: @11483 |
| 4604 | GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(11560), // Rule ID 5555 // |
| 4605 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4606 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4607 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4608 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4609 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4610 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4611 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4612 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4613 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 4614 | // MIs[2] Operand 1 |
| 4615 | // No operand predicates |
| 4616 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4617 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4618 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4619 | // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 4621 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4622 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4623 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4625 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4626 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4627 | GIR_RootConstrainSelectedInstOperands, |
| 4628 | // GIR_Coverage, 5555, |
| 4629 | GIR_EraseRootFromParent_Done, |
| 4630 | // Label 304: @11560 |
| 4631 | GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(11637), // Rule ID 5588 // |
| 4632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4634 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4635 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4636 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4637 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4638 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4639 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4640 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 4641 | // MIs[2] Operand 1 |
| 4642 | // No operand predicates |
| 4643 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4644 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4645 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4646 | // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4647 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 4648 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4649 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4650 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4652 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4653 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4654 | GIR_RootConstrainSelectedInstOperands, |
| 4655 | // GIR_Coverage, 5588, |
| 4656 | GIR_EraseRootFromParent_Done, |
| 4657 | // Label 305: @11637 |
| 4658 | GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(11714), // Rule ID 5554 // |
| 4659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4660 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4661 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4662 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4663 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4664 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4665 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4666 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 4667 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4668 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4669 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 4670 | // MIs[2] Operand 1 |
| 4671 | // No operand predicates |
| 4672 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4673 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4674 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 4675 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4676 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4677 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4679 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4680 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4681 | GIR_RootConstrainSelectedInstOperands, |
| 4682 | // GIR_Coverage, 5554, |
| 4683 | GIR_EraseRootFromParent_Done, |
| 4684 | // Label 306: @11714 |
| 4685 | GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(11791), // Rule ID 5587 // |
| 4686 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4687 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4688 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4689 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4690 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4691 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4692 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4693 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 4694 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4695 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4696 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 4697 | // MIs[2] Operand 1 |
| 4698 | // No operand predicates |
| 4699 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4700 | // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 4702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4703 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4704 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4706 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4707 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4708 | GIR_RootConstrainSelectedInstOperands, |
| 4709 | // GIR_Coverage, 5587, |
| 4710 | GIR_EraseRootFromParent_Done, |
| 4711 | // Label 307: @11791 |
| 4712 | GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(11868), // Rule ID 159 // |
| 4713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4714 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4715 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4716 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4717 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4718 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4719 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4720 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4721 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4722 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 4723 | // MIs[2] Operand 1 |
| 4724 | // No operand predicates |
| 4725 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4726 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4727 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] })) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 4729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4730 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4731 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4733 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4734 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4735 | GIR_RootConstrainSelectedInstOperands, |
| 4736 | // GIR_Coverage, 159, |
| 4737 | GIR_EraseRootFromParent_Done, |
| 4738 | // Label 308: @11868 |
| 4739 | GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(11945), // Rule ID 498 // |
| 4740 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4741 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4742 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4743 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4744 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4745 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4746 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4747 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4748 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4749 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 4750 | // MIs[2] Operand 1 |
| 4751 | // No operand predicates |
| 4752 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4753 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4754 | // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4755 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 4756 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4757 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4758 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4760 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4761 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4762 | GIR_RootConstrainSelectedInstOperands, |
| 4763 | // GIR_Coverage, 498, |
| 4764 | GIR_EraseRootFromParent_Done, |
| 4765 | // Label 309: @11945 |
| 4766 | GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(12016), // Rule ID 5557 // |
| 4767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4769 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4770 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4771 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4772 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4773 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4774 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4775 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4776 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4777 | // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 4778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr), |
| 4779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4780 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 4782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4783 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4784 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4785 | GIR_RootConstrainSelectedInstOperands, |
| 4786 | // GIR_Coverage, 5557, |
| 4787 | GIR_EraseRootFromParent_Done, |
| 4788 | // Label 310: @12016 |
| 4789 | GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(12087), // Rule ID 5590 // |
| 4790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4792 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4793 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4794 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4795 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4796 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4797 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4798 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4799 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4800 | // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 4801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr), |
| 4802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4803 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4804 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 4805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4806 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4807 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4808 | GIR_RootConstrainSelectedInstOperands, |
| 4809 | // GIR_Coverage, 5590, |
| 4810 | GIR_EraseRootFromParent_Done, |
| 4811 | // Label 311: @12087 |
| 4812 | GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(12158), // Rule ID 160 // |
| 4813 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4814 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4815 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4816 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4817 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4818 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4819 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4820 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4821 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4822 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4823 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 4824 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr), |
| 4825 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4826 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4827 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 4828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4829 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4830 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4831 | GIR_RootConstrainSelectedInstOperands, |
| 4832 | // GIR_Coverage, 160, |
| 4833 | GIR_EraseRootFromParent_Done, |
| 4834 | // Label 312: @12158 |
| 4835 | GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(12229), // Rule ID 499 // |
| 4836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4837 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4838 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4839 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4840 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4841 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4842 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4843 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4844 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4845 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4846 | // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 4847 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr), |
| 4848 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4849 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4850 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 4851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4852 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4853 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4854 | GIR_RootConstrainSelectedInstOperands, |
| 4855 | // GIR_Coverage, 499, |
| 4856 | GIR_EraseRootFromParent_Done, |
| 4857 | // Label 313: @12229 |
| 4858 | GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(12274), // Rule ID 352 // |
| 4859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 4860 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4861 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4862 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 4863 | // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 4864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTB), |
| 4865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4866 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 4867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4868 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4869 | GIR_RootConstrainSelectedInstOperands, |
| 4870 | // GIR_Coverage, 352, |
| 4871 | GIR_EraseRootFromParent_Done, |
| 4872 | // Label 314: @12274 |
| 4873 | GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(12319), // Rule ID 353 // |
| 4874 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 4875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4876 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4877 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 4878 | // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 4879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTH), |
| 4880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4881 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 4882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4883 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4884 | GIR_RootConstrainSelectedInstOperands, |
| 4885 | // GIR_Coverage, 353, |
| 4886 | GIR_EraseRootFromParent_Done, |
| 4887 | // Label 315: @12319 |
| 4888 | GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(12378), // Rule ID 1918 // |
| 4889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4891 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4892 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4893 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4894 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not), |
| 4895 | // MIs[1] Operand 1 |
| 4896 | // No operand predicates |
| 4897 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4898 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>>:$imm)) |
| 4899 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 4900 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4901 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 4902 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm |
| 4903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4904 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4905 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4906 | GIR_RootConstrainSelectedInstOperands, |
| 4907 | // GIR_Coverage, 1918, |
| 4908 | GIR_EraseRootFromParent_Done, |
| 4909 | // Label 316: @12378 |
| 4910 | GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(12435), // Rule ID 147 // |
| 4911 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4912 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4913 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4914 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4915 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4916 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 4917 | // MIs[1] Operand 1 |
| 4918 | // No operand predicates |
| 4919 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4920 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDri), |
| 4922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4923 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4924 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4926 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4927 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4928 | GIR_RootConstrainSelectedInstOperands, |
| 4929 | // GIR_Coverage, 147, |
| 4930 | GIR_EraseRootFromParent_Done, |
| 4931 | // Label 317: @12435 |
| 4932 | GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(12492), // Rule ID 489 // |
| 4933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4934 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4935 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4936 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4937 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4938 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 4939 | // MIs[1] Operand 1 |
| 4940 | // No operand predicates |
| 4941 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4942 | // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDri), |
| 4944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4945 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4946 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4948 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4949 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4950 | GIR_RootConstrainSelectedInstOperands, |
| 4951 | // GIR_Coverage, 489, |
| 4952 | GIR_EraseRootFromParent_Done, |
| 4953 | // Label 318: @12492 |
| 4954 | GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(12543), // Rule ID 163 // |
| 4955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), |
| 4956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4957 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4958 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4959 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4960 | // MIs[1] Operand 1 |
| 4961 | // No operand predicates |
| 4962 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm), |
| 4963 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4964 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) |
| 4965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BFC), |
| 4966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4967 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 4968 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4970 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4971 | GIR_RootConstrainSelectedInstOperands, |
| 4972 | // GIR_Coverage, 163, |
| 4973 | GIR_EraseRootFromParent_Done, |
| 4974 | // Label 319: @12543 |
| 4975 | GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(12594), // Rule ID 501 // |
| 4976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4978 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4979 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4980 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4981 | // MIs[1] Operand 1 |
| 4982 | // No operand predicates |
| 4983 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm), |
| 4984 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4985 | // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) |
| 4986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BFC), |
| 4987 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4988 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 4989 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4991 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4992 | GIR_RootConstrainSelectedInstOperands, |
| 4993 | // GIR_Coverage, 501, |
| 4994 | GIR_EraseRootFromParent_Done, |
| 4995 | // Label 320: @12594 |
| 4996 | GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(12640), // Rule ID 148 // |
| 4997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4998 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4999 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5000 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5001 | // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDrr), |
| 5003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5004 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5005 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 5006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5007 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5008 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5009 | GIR_RootConstrainSelectedInstOperands, |
| 5010 | // GIR_Coverage, 148, |
| 5011 | GIR_EraseRootFromParent_Done, |
| 5012 | // Label 321: @12640 |
| 5013 | GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(12686), // Rule ID 490 // |
| 5014 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 5015 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5016 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5017 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5018 | // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5019 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 5020 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5021 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5022 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 5023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5024 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5025 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5026 | GIR_RootConstrainSelectedInstOperands, |
| 5027 | // GIR_Coverage, 490, |
| 5028 | GIR_EraseRootFromParent_Done, |
| 5029 | // Label 322: @12686 |
| 5030 | GIM_Reject, |
| 5031 | // Label 293: @12687 |
| 5032 | GIM_Reject, |
| 5033 | // Label 280: @12688 |
| 5034 | GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(12734), // Rule ID 2523 // |
| 5035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5036 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 5037 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5039 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5040 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5041 | // (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VANDd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 5042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 5043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5044 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 5045 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 5046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5047 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5048 | GIR_RootConstrainSelectedInstOperands, |
| 5049 | // GIR_Coverage, 2523, |
| 5050 | GIR_EraseRootFromParent_Done, |
| 5051 | // Label 323: @12734 |
| 5052 | GIM_Reject, |
| 5053 | // Label 281: @12735 |
| 5054 | GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(12846), // Rule ID 1850 // |
| 5055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5056 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 5057 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 5058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 5059 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 5060 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 5061 | // (and:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 5062 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 5063 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 5064 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 5065 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5066 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5067 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 5068 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5069 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5070 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5071 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 5072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5073 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 5074 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5075 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5076 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5077 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 5078 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5079 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5080 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5081 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5082 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 5083 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5084 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 5085 | // GIR_Coverage, 1850, |
| 5086 | GIR_EraseRootFromParent_Done, |
| 5087 | // Label 324: @12846 |
| 5088 | GIM_Reject, |
| 5089 | // Label 282: @12847 |
| 5090 | GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(12893), // Rule ID 1150 // |
| 5091 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5092 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5093 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 5094 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5095 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5096 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5097 | // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 5099 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5100 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5101 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5103 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5104 | GIR_RootConstrainSelectedInstOperands, |
| 5105 | // GIR_Coverage, 1150, |
| 5106 | GIR_EraseRootFromParent_Done, |
| 5107 | // Label 325: @12893 |
| 5108 | GIM_Reject, |
| 5109 | // Label 283: @12894 |
| 5110 | GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(13005), |
| 5111 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 5112 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5113 | GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(12945), // Rule ID 2526 // |
| 5114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5116 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5117 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5118 | // (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VANDq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 5119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 5120 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5121 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 5122 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 5123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5124 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5125 | GIR_RootConstrainSelectedInstOperands, |
| 5126 | // GIR_Coverage, 2526, |
| 5127 | GIR_EraseRootFromParent_Done, |
| 5128 | // Label 327: @12945 |
| 5129 | GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(13004), // Rule ID 3467 // |
| 5130 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5131 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5132 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5133 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5134 | // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 5135 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5136 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5137 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 5138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 5139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5140 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5141 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5143 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5144 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5145 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5146 | GIR_RootConstrainSelectedInstOperands, |
| 5147 | // GIR_Coverage, 3467, |
| 5148 | GIR_EraseRootFromParent_Done, |
| 5149 | // Label 328: @13004 |
| 5150 | GIM_Reject, |
| 5151 | // Label 326: @13005 |
| 5152 | GIM_Reject, |
| 5153 | // Label 284: @13006 |
| 5154 | GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(13117), // Rule ID 1851 // |
| 5155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5156 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 5157 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 5158 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 5159 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 5160 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 5161 | // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 5162 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 5163 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 5164 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 5165 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5166 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5167 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 5168 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5169 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5170 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5171 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 5172 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5173 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 5174 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5175 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5176 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5177 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 5178 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5179 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5180 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5181 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5182 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 5183 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5184 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 5185 | // GIR_Coverage, 1851, |
| 5186 | GIR_EraseRootFromParent_Done, |
| 5187 | // Label 329: @13117 |
| 5188 | GIM_Reject, |
| 5189 | // Label 285: @13118 |
| 5190 | GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(13164), // Rule ID 2522 // |
| 5191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5192 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5193 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 5194 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5195 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5196 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5197 | // (and:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VANDd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 5198 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 5199 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5200 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 5201 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 5202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5203 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5204 | GIR_RootConstrainSelectedInstOperands, |
| 5205 | // GIR_Coverage, 2522, |
| 5206 | GIR_EraseRootFromParent_Done, |
| 5207 | // Label 330: @13164 |
| 5208 | GIM_Reject, |
| 5209 | // Label 286: @13165 |
| 5210 | GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(13276), |
| 5211 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 5212 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5213 | GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(13216), // Rule ID 1151 // |
| 5214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5215 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5216 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5217 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5218 | // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 5219 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 5220 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5221 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5222 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5224 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5225 | GIR_RootConstrainSelectedInstOperands, |
| 5226 | // GIR_Coverage, 1151, |
| 5227 | GIR_EraseRootFromParent_Done, |
| 5228 | // Label 332: @13216 |
| 5229 | GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(13275), // Rule ID 3463 // |
| 5230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5232 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5233 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5234 | // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 5235 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5236 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5237 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 5238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 5239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5240 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5241 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5243 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5244 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5245 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5246 | GIR_RootConstrainSelectedInstOperands, |
| 5247 | // GIR_Coverage, 3463, |
| 5248 | GIR_EraseRootFromParent_Done, |
| 5249 | // Label 333: @13275 |
| 5250 | GIM_Reject, |
| 5251 | // Label 331: @13276 |
| 5252 | GIM_Reject, |
| 5253 | // Label 287: @13277 |
| 5254 | GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(13388), // Rule ID 1852 // |
| 5255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5256 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 5257 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 5258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 5259 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 5260 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 5261 | // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 5262 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 5263 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 5264 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 5265 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5266 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5267 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 5268 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5269 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5270 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5271 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 5272 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5273 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 5274 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5275 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5276 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5277 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 5278 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5279 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5280 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5281 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5282 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 5283 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5284 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 5285 | // GIR_Coverage, 1852, |
| 5286 | GIR_EraseRootFromParent_Done, |
| 5287 | // Label 334: @13388 |
| 5288 | GIM_Reject, |
| 5289 | // Label 288: @13389 |
| 5290 | GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(13435), // Rule ID 2521 // |
| 5291 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5292 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5293 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 5294 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5295 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5296 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5297 | // (and:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VANDd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 5298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 5299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5300 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 5301 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 5302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5303 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5304 | GIR_RootConstrainSelectedInstOperands, |
| 5305 | // GIR_Coverage, 2521, |
| 5306 | GIR_EraseRootFromParent_Done, |
| 5307 | // Label 335: @13435 |
| 5308 | GIM_Reject, |
| 5309 | // Label 289: @13436 |
| 5310 | GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(13547), |
| 5311 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5312 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5313 | GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(13487), // Rule ID 2525 // |
| 5314 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5315 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5316 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5317 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5318 | // (and:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VANDq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 5319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 5320 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5321 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 5322 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 5323 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5324 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5325 | GIR_RootConstrainSelectedInstOperands, |
| 5326 | // GIR_Coverage, 2525, |
| 5327 | GIR_EraseRootFromParent_Done, |
| 5328 | // Label 337: @13487 |
| 5329 | GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(13546), // Rule ID 3459 // |
| 5330 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5332 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5333 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5334 | // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 5335 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5336 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5337 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 5338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 5339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5340 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5341 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5343 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5344 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5345 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5346 | GIR_RootConstrainSelectedInstOperands, |
| 5347 | // GIR_Coverage, 3459, |
| 5348 | GIR_EraseRootFromParent_Done, |
| 5349 | // Label 338: @13546 |
| 5350 | GIM_Reject, |
| 5351 | // Label 336: @13547 |
| 5352 | GIM_Reject, |
| 5353 | // Label 290: @13548 |
| 5354 | GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(13659), // Rule ID 1853 // |
| 5355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5356 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 5357 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 5358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 5359 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 5360 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 5361 | // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 5362 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 5363 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 5364 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 5365 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5366 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5367 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 5368 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5369 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5370 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5371 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 5372 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5373 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 5374 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5375 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5376 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5377 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 5378 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5379 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5380 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 5383 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5384 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 5385 | // GIR_Coverage, 1853, |
| 5386 | GIR_EraseRootFromParent_Done, |
| 5387 | // Label 339: @13659 |
| 5388 | GIM_Reject, |
| 5389 | // Label 291: @13660 |
| 5390 | GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(13771), |
| 5391 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5392 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5393 | GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(13711), // Rule ID 2524 // |
| 5394 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5395 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5396 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5397 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5398 | // (and:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VANDq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 5399 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 5400 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5401 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 5402 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 5403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5404 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5405 | GIR_RootConstrainSelectedInstOperands, |
| 5406 | // GIR_Coverage, 2524, |
| 5407 | GIR_EraseRootFromParent_Done, |
| 5408 | // Label 341: @13711 |
| 5409 | GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(13770), // Rule ID 3455 // |
| 5410 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5411 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5412 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5413 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5414 | // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 5415 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5416 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5417 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 5418 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 5419 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5420 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5421 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5423 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5424 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5425 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5426 | GIR_RootConstrainSelectedInstOperands, |
| 5427 | // GIR_Coverage, 3455, |
| 5428 | GIR_EraseRootFromParent_Done, |
| 5429 | // Label 342: @13770 |
| 5430 | GIM_Reject, |
| 5431 | // Label 340: @13771 |
| 5432 | GIM_Reject, |
| 5433 | // Label 292: @13772 |
| 5434 | GIM_Reject, |
| 5435 | // Label 6: @13773 |
| 5436 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 356*/ GIMT_Encode4(19503), |
| 5437 | /*GILLT_s32*//*Label 343*/ GIMT_Encode4(13844), |
| 5438 | /*GILLT_s64*//*Label 344*/ GIMT_Encode4(18419), |
| 5439 | /*GILLT_v2s1*//*Label 345*/ GIMT_Encode4(18466), |
| 5440 | /*GILLT_v2s32*//*Label 346*/ GIMT_Encode4(18578), |
| 5441 | /*GILLT_v2s64*//*Label 347*/ GIMT_Encode4(18625), |
| 5442 | /*GILLT_v4s1*//*Label 348*/ GIMT_Encode4(18737), |
| 5443 | /*GILLT_v4s16*//*Label 349*/ GIMT_Encode4(18849), |
| 5444 | /*GILLT_v4s32*//*Label 350*/ GIMT_Encode4(18896), GIMT_Encode4(0), |
| 5445 | /*GILLT_v8s1*//*Label 351*/ GIMT_Encode4(19008), |
| 5446 | /*GILLT_v8s8*//*Label 352*/ GIMT_Encode4(19120), |
| 5447 | /*GILLT_v8s16*//*Label 353*/ GIMT_Encode4(19167), GIMT_Encode4(0), |
| 5448 | /*GILLT_v16s1*//*Label 354*/ GIMT_Encode4(19279), |
| 5449 | /*GILLT_v16s8*//*Label 355*/ GIMT_Encode4(19391), |
| 5450 | // Label 343: @13844 |
| 5451 | GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(18418), |
| 5452 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 5453 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 5454 | GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(13982), // Rule ID 5772 // |
| 5455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 5456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5457 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5458 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5459 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5460 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5461 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5462 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 5463 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5464 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5465 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5466 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8, |
| 5467 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 5468 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 5469 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5470 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 5471 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 5472 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 5473 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 5474 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 5475 | // MIs[4] Rm |
| 5476 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 5477 | GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 5478 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 5479 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5480 | // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 5481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 5482 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5483 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5485 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5486 | GIR_RootConstrainSelectedInstOperands, |
| 5487 | // GIR_Coverage, 5772, |
| 5488 | GIR_EraseRootFromParent_Done, |
| 5489 | // Label 358: @13982 |
| 5490 | GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(14109), // Rule ID 5814 // |
| 5491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 5492 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5493 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5494 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5495 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5496 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5497 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5498 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 5499 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5500 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5501 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5502 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8, |
| 5503 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 5504 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 5505 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5506 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 5507 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 5508 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 5509 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 5510 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 5511 | // MIs[4] Rm |
| 5512 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 5513 | GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 5514 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 5515 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5516 | // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 5517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 5518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5519 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5521 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5522 | GIR_RootConstrainSelectedInstOperands, |
| 5523 | // GIR_Coverage, 5814, |
| 5524 | GIR_EraseRootFromParent_Done, |
| 5525 | // Label 359: @14109 |
| 5526 | GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(14236), // Rule ID 1938 // |
| 5527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 5528 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5529 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5530 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5531 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5532 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5533 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5534 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 5535 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5536 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5537 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5538 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 5539 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5540 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 5541 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 5542 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 5543 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 5544 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 5545 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 5546 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 5547 | // MIs[4] Rm |
| 5548 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 5549 | GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 5550 | GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255), |
| 5551 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5552 | // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 5553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 5554 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5555 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5557 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5558 | GIR_RootConstrainSelectedInstOperands, |
| 5559 | // GIR_Coverage, 1938, |
| 5560 | GIR_EraseRootFromParent_Done, |
| 5561 | // Label 360: @14236 |
| 5562 | GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(14363), // Rule ID 2203 // |
| 5563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 5564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5565 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5566 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5567 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5568 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5569 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5570 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 5571 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5572 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5573 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5574 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 5575 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5576 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 5577 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 5578 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 5579 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 5580 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 5581 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 5582 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 5583 | // MIs[4] Rm |
| 5584 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 5585 | GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 5586 | GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255), |
| 5587 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5588 | // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 5589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 5590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5591 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5593 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5594 | GIR_RootConstrainSelectedInstOperands, |
| 5595 | // GIR_Coverage, 2203, |
| 5596 | GIR_EraseRootFromParent_Done, |
| 5597 | // Label 361: @14363 |
| 5598 | GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(14496), // Rule ID 5570 // |
| 5599 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 5600 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5601 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5602 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5603 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5604 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5605 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5606 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5607 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5608 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5609 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5610 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 5611 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5612 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 5613 | // MIs[3] Operand 1 |
| 5614 | // No operand predicates |
| 5615 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 5616 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 5617 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 5618 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 5619 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 5620 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5621 | GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 5622 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5623 | // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 5624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 5625 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5626 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 5627 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5628 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 5629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5630 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5631 | GIR_RootConstrainSelectedInstOperands, |
| 5632 | // GIR_Coverage, 5570, |
| 5633 | GIR_EraseRootFromParent_Done, |
| 5634 | // Label 362: @14496 |
| 5635 | GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(14629), // Rule ID 5607 // |
| 5636 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 5637 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5638 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5639 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5640 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5641 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5642 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5643 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5644 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5645 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5646 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5647 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 5648 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5649 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 5650 | // MIs[3] Operand 1 |
| 5651 | // No operand predicates |
| 5652 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 5653 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 5654 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 5655 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 5656 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 5657 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5658 | GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 5659 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5660 | // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 5661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 5662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5663 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 5664 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5665 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 5666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5667 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5668 | GIR_RootConstrainSelectedInstOperands, |
| 5669 | // GIR_Coverage, 5607, |
| 5670 | GIR_EraseRootFromParent_Done, |
| 5671 | // Label 363: @14629 |
| 5672 | GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(14762), // Rule ID 5777 // |
| 5673 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 5674 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5675 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5676 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5677 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5678 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5679 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5680 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 5681 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5682 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5683 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5684 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 5685 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5686 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 5687 | // MIs[3] Operand 1 |
| 5688 | // No operand predicates |
| 5689 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 5690 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 5691 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 5692 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 5693 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 5694 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5695 | GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 5696 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5697 | // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 5698 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 5699 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5700 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 |
| 5701 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 5702 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 5703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5704 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5705 | GIR_RootConstrainSelectedInstOperands, |
| 5706 | // GIR_Coverage, 5777, |
| 5707 | GIR_EraseRootFromParent_Done, |
| 5708 | // Label 364: @14762 |
| 5709 | GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(14895), // Rule ID 5819 // |
| 5710 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 5711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5712 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5713 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5714 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5715 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5716 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5717 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 5718 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5719 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5720 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5721 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 5722 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5723 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 5724 | // MIs[3] Operand 1 |
| 5725 | // No operand predicates |
| 5726 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 5727 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 5728 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 5729 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 5730 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 5731 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5732 | GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 5733 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5734 | // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 5735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 5736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5737 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 |
| 5738 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 5739 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 5740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5741 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5742 | GIR_RootConstrainSelectedInstOperands, |
| 5743 | // GIR_Coverage, 5819, |
| 5744 | GIR_EraseRootFromParent_Done, |
| 5745 | // Label 365: @14895 |
| 5746 | GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(15028), // Rule ID 5569 // |
| 5747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 5748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5749 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5750 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5751 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5752 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5753 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5754 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 5755 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5756 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5757 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5758 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 5759 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5760 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 5761 | // MIs[3] Operand 1 |
| 5762 | // No operand predicates |
| 5763 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 5764 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 5765 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 5766 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 5767 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 5768 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5769 | GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535), |
| 5770 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5771 | // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 5772 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 5773 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5774 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 5775 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5776 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 5777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5778 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5779 | GIR_RootConstrainSelectedInstOperands, |
| 5780 | // GIR_Coverage, 5569, |
| 5781 | GIR_EraseRootFromParent_Done, |
| 5782 | // Label 366: @15028 |
| 5783 | GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(15161), // Rule ID 5606 // |
| 5784 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 5785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5786 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5787 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5788 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5789 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5790 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5791 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 5792 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5793 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5794 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5795 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 5796 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5797 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 5798 | // MIs[3] Operand 1 |
| 5799 | // No operand predicates |
| 5800 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 5801 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 5802 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 5803 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 5804 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 5805 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5806 | GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535), |
| 5807 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5808 | // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 5809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 5810 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5811 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 5812 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5813 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 5814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5815 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5816 | GIR_RootConstrainSelectedInstOperands, |
| 5817 | // GIR_Coverage, 5606, |
| 5818 | GIR_EraseRootFromParent_Done, |
| 5819 | // Label 367: @15161 |
| 5820 | GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(15294), // Rule ID 203 // |
| 5821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 5822 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5823 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5824 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5825 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5826 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5827 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5828 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 5829 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5830 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5831 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5832 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5833 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 5834 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5835 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 5836 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 5837 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5838 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 5839 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5840 | GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 5841 | // MIs[4] Operand 1 |
| 5842 | // No operand predicates |
| 5843 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 5844 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5845 | // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 5846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 5847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5848 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5849 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 5850 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 5851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5852 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5853 | GIR_RootConstrainSelectedInstOperands, |
| 5854 | // GIR_Coverage, 203, |
| 5855 | GIR_EraseRootFromParent_Done, |
| 5856 | // Label 368: @15294 |
| 5857 | GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(15427), // Rule ID 548 // |
| 5858 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 5859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5860 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5861 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5862 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5863 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5864 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5865 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 5866 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5867 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5868 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5869 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5870 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 5871 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5872 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 5873 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 5874 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5875 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 5876 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5877 | GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 5878 | // MIs[4] Operand 1 |
| 5879 | // No operand predicates |
| 5880 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 5881 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5882 | // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 5883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 5884 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5885 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5886 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 5887 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 5888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5889 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5890 | GIR_RootConstrainSelectedInstOperands, |
| 5891 | // GIR_Coverage, 548, |
| 5892 | GIR_EraseRootFromParent_Done, |
| 5893 | // Label 369: @15427 |
| 5894 | GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(15560), // Rule ID 1943 // |
| 5895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 5896 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5897 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5898 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5899 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5900 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5901 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5902 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 5903 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5904 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5905 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5906 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5907 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 5908 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 5909 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 5910 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 5911 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5912 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 5913 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5914 | GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 5915 | // MIs[4] Operand 1 |
| 5916 | // No operand predicates |
| 5917 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 5918 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5919 | // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 5920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 5921 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5922 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 5923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 |
| 5924 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 5925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5926 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5927 | GIR_RootConstrainSelectedInstOperands, |
| 5928 | // GIR_Coverage, 1943, |
| 5929 | GIR_EraseRootFromParent_Done, |
| 5930 | // Label 370: @15560 |
| 5931 | GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(15693), // Rule ID 2208 // |
| 5932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 5933 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5934 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5935 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5936 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5937 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5938 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5939 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 5940 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5941 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5942 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5943 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5944 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 5945 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 5946 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 5947 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 5948 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5949 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 5950 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5951 | GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 5952 | // MIs[4] Operand 1 |
| 5953 | // No operand predicates |
| 5954 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 5955 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5956 | // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 5957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 5958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 5960 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 |
| 5961 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 5962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5963 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5964 | GIR_RootConstrainSelectedInstOperands, |
| 5965 | // GIR_Coverage, 2208, |
| 5966 | GIR_EraseRootFromParent_Done, |
| 5967 | // Label 371: @15693 |
| 5968 | GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(15826), // Rule ID 202 // |
| 5969 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 5970 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5971 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5972 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5973 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5974 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5975 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5976 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 5977 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5978 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5979 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5980 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5981 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 5982 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 5983 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 5984 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 5985 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5986 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 5987 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5988 | GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 5989 | // MIs[4] Operand 1 |
| 5990 | // No operand predicates |
| 5991 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 5992 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 5993 | // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 5994 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 5995 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5996 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5997 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 5998 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 5999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6000 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6001 | GIR_RootConstrainSelectedInstOperands, |
| 6002 | // GIR_Coverage, 202, |
| 6003 | GIR_EraseRootFromParent_Done, |
| 6004 | // Label 372: @15826 |
| 6005 | GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(15959), // Rule ID 547 // |
| 6006 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6007 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6008 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6009 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6010 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6011 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6012 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6013 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 6014 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6015 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 6016 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6017 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6018 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 6019 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 6020 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 6021 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 6022 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6023 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 6024 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6025 | GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 6026 | // MIs[4] Operand 1 |
| 6027 | // No operand predicates |
| 6028 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 6029 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 6030 | // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 6031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 6032 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6033 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6034 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 6035 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 6036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6037 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6038 | GIR_RootConstrainSelectedInstOperands, |
| 6039 | // GIR_Coverage, 547, |
| 6040 | GIR_EraseRootFromParent_Done, |
| 6041 | // Label 373: @15959 |
| 6042 | GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(16064), // Rule ID 1939 // |
| 6043 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6045 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6046 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6047 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6048 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6049 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6050 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 6051 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6052 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 6053 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6054 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6055 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6056 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 6057 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6058 | // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 6059 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 6060 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6061 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6062 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6065 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6066 | GIR_RootConstrainSelectedInstOperands, |
| 6067 | // GIR_Coverage, 1939, |
| 6068 | GIR_EraseRootFromParent_Done, |
| 6069 | // Label 374: @16064 |
| 6070 | GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(16169), // Rule ID 2204 // |
| 6071 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6073 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6074 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6075 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6076 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6077 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6078 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 6079 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6080 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 6081 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6082 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6083 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6084 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 6085 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6086 | // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) |
| 6087 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 6088 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6089 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 6090 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 6091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6093 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6094 | GIR_RootConstrainSelectedInstOperands, |
| 6095 | // GIR_Coverage, 2204, |
| 6096 | GIR_EraseRootFromParent_Done, |
| 6097 | // Label 375: @16169 |
| 6098 | GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(16274), // Rule ID 5773 // |
| 6099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6101 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6102 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6103 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6104 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6105 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6106 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 6107 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6108 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 6109 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6110 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6111 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6112 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 6113 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6114 | // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 6115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 6116 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6117 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 6118 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6121 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6122 | GIR_RootConstrainSelectedInstOperands, |
| 6123 | // GIR_Coverage, 5773, |
| 6124 | GIR_EraseRootFromParent_Done, |
| 6125 | // Label 376: @16274 |
| 6126 | GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(16379), // Rule ID 5815 // |
| 6127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6128 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6129 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6130 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6131 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6132 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6133 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6134 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 6135 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6136 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 6137 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6138 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6139 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6140 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 6141 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6142 | // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) |
| 6143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 6144 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6145 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 6146 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 6147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6149 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6150 | GIR_RootConstrainSelectedInstOperands, |
| 6151 | // GIR_Coverage, 5815, |
| 6152 | GIR_EraseRootFromParent_Done, |
| 6153 | // Label 377: @16379 |
| 6154 | GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(16485), // Rule ID 1942 // |
| 6155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6157 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6158 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6159 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6160 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6161 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6162 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 6163 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6164 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6165 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6166 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6167 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6168 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 6169 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6170 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 6171 | // MIs[3] Operand 1 |
| 6172 | // No operand predicates |
| 6173 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6174 | // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 6175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 6176 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6177 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 6178 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 6179 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 6180 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6181 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6182 | GIR_RootConstrainSelectedInstOperands, |
| 6183 | // GIR_Coverage, 1942, |
| 6184 | GIR_EraseRootFromParent_Done, |
| 6185 | // Label 378: @16485 |
| 6186 | GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(16591), // Rule ID 2207 // |
| 6187 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6188 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6189 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6190 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6191 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6192 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6193 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6194 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 6195 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6196 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6197 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6198 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6199 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6200 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 6201 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6202 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 6203 | // MIs[3] Operand 1 |
| 6204 | // No operand predicates |
| 6205 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6206 | // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 6207 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 6208 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6209 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 6210 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 6211 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 6212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6213 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6214 | GIR_RootConstrainSelectedInstOperands, |
| 6215 | // GIR_Coverage, 2207, |
| 6216 | GIR_EraseRootFromParent_Done, |
| 6217 | // Label 379: @16591 |
| 6218 | GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(16697), // Rule ID 1941 // |
| 6219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6220 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6221 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6222 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6223 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6224 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6225 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6226 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 6227 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6228 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 6229 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6230 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6231 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6232 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 6233 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6234 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 6235 | // MIs[3] Operand 1 |
| 6236 | // No operand predicates |
| 6237 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6238 | // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 6239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 6240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6241 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 6242 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 6243 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 6244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6245 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6246 | GIR_RootConstrainSelectedInstOperands, |
| 6247 | // GIR_Coverage, 1941, |
| 6248 | GIR_EraseRootFromParent_Done, |
| 6249 | // Label 380: @16697 |
| 6250 | GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(16803), // Rule ID 2206 // |
| 6251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6252 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6253 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6254 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6255 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6256 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6257 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6258 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 6259 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6260 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 6261 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6262 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6263 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6264 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 6265 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6266 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 6267 | // MIs[3] Operand 1 |
| 6268 | // No operand predicates |
| 6269 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6270 | // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 6271 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 6272 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6273 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 6274 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 6275 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 6276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6277 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6278 | GIR_RootConstrainSelectedInstOperands, |
| 6279 | // GIR_Coverage, 2206, |
| 6280 | GIR_EraseRootFromParent_Done, |
| 6281 | // Label 381: @16803 |
| 6282 | GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(16909), // Rule ID 1940 // |
| 6283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6284 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6285 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6286 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6287 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6288 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6289 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6290 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 6291 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6292 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 6293 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6294 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6295 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6296 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 6297 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6298 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 6299 | // MIs[3] Operand 1 |
| 6300 | // No operand predicates |
| 6301 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6302 | // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 6303 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 6304 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6305 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6306 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6307 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 6308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6309 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6310 | GIR_RootConstrainSelectedInstOperands, |
| 6311 | // GIR_Coverage, 1940, |
| 6312 | GIR_EraseRootFromParent_Done, |
| 6313 | // Label 382: @16909 |
| 6314 | GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(17015), // Rule ID 2205 // |
| 6315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6317 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6318 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6319 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6320 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6321 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6322 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 6323 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6324 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 6325 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6326 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6327 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6328 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 6329 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6330 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 6331 | // MIs[3] Operand 1 |
| 6332 | // No operand predicates |
| 6333 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6334 | // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 6335 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 6336 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6337 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 6338 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 6339 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 6340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6341 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6342 | GIR_RootConstrainSelectedInstOperands, |
| 6343 | // GIR_Coverage, 2205, |
| 6344 | GIR_EraseRootFromParent_Done, |
| 6345 | // Label 383: @17015 |
| 6346 | GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(17121), // Rule ID 5776 // |
| 6347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6348 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6349 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6350 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6351 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6352 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6353 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6354 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6355 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6356 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 6357 | // MIs[2] Operand 1 |
| 6358 | // No operand predicates |
| 6359 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6360 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 6361 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 6362 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 6363 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6364 | GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 6365 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6366 | // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 6367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 6368 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6369 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 6370 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 6371 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 6372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6373 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6374 | GIR_RootConstrainSelectedInstOperands, |
| 6375 | // GIR_Coverage, 5776, |
| 6376 | GIR_EraseRootFromParent_Done, |
| 6377 | // Label 384: @17121 |
| 6378 | GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(17227), // Rule ID 5818 // |
| 6379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6381 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6382 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6383 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6384 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6385 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6386 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6387 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6388 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 6389 | // MIs[2] Operand 1 |
| 6390 | // No operand predicates |
| 6391 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6392 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 6393 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 6394 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 6395 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6396 | GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 6397 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6398 | // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 6399 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 6400 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6401 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 6402 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 6403 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 6404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6405 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6406 | GIR_RootConstrainSelectedInstOperands, |
| 6407 | // GIR_Coverage, 5818, |
| 6408 | GIR_EraseRootFromParent_Done, |
| 6409 | // Label 385: @17227 |
| 6410 | GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(17333), // Rule ID 5775 // |
| 6411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6412 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6413 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6414 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 6415 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6416 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6417 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6418 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6419 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6420 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 6421 | // MIs[2] Operand 1 |
| 6422 | // No operand predicates |
| 6423 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6424 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 6425 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 6426 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 6427 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6428 | GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 6429 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6430 | // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 6431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 6432 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6433 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 6434 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 6435 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 6436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6437 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6438 | GIR_RootConstrainSelectedInstOperands, |
| 6439 | // GIR_Coverage, 5775, |
| 6440 | GIR_EraseRootFromParent_Done, |
| 6441 | // Label 386: @17333 |
| 6442 | GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(17439), // Rule ID 5817 // |
| 6443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6444 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6445 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6446 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 6447 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6448 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6449 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6450 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6451 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6452 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 6453 | // MIs[2] Operand 1 |
| 6454 | // No operand predicates |
| 6455 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6456 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 6457 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 6458 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 6459 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6460 | GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 6461 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6462 | // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 6463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 6464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 6466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 6467 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 6468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6469 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6470 | GIR_RootConstrainSelectedInstOperands, |
| 6471 | // GIR_Coverage, 5817, |
| 6472 | GIR_EraseRootFromParent_Done, |
| 6473 | // Label 387: @17439 |
| 6474 | GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(17545), // Rule ID 5774 // |
| 6475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6477 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6478 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 6479 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6480 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6481 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6482 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6483 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6484 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 6485 | // MIs[2] Operand 1 |
| 6486 | // No operand predicates |
| 6487 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6488 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 6489 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 6490 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 6491 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6492 | GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535), |
| 6493 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6494 | // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 6495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 6496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6497 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 6498 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6499 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 6500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6501 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6502 | GIR_RootConstrainSelectedInstOperands, |
| 6503 | // GIR_Coverage, 5774, |
| 6504 | GIR_EraseRootFromParent_Done, |
| 6505 | // Label 388: @17545 |
| 6506 | GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(17651), // Rule ID 5816 // |
| 6507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 6508 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6509 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6510 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 6511 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6512 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6513 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6514 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6515 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6516 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 6517 | // MIs[2] Operand 1 |
| 6518 | // No operand predicates |
| 6519 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6520 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 6521 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 6522 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 6523 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6524 | GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535), |
| 6525 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6526 | // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 6527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 6528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6529 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 6530 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 6531 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 6532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6533 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6534 | GIR_RootConstrainSelectedInstOperands, |
| 6535 | // GIR_Coverage, 5816, |
| 6536 | GIR_EraseRootFromParent_Done, |
| 6537 | // Label 389: @17651 |
| 6538 | GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(17728), // Rule ID 5594 // |
| 6539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6541 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6542 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6543 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6544 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6545 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 6546 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6547 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6548 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6549 | // MIs[2] Operand 1 |
| 6550 | // No operand predicates |
| 6551 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6552 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6553 | // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 6555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6556 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6557 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6559 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6560 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6561 | GIR_RootConstrainSelectedInstOperands, |
| 6562 | // GIR_Coverage, 5594, |
| 6563 | GIR_EraseRootFromParent_Done, |
| 6564 | // Label 390: @17728 |
| 6565 | GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(17805), // Rule ID 5593 // |
| 6566 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6567 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6568 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6569 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6570 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6571 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6572 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6573 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6574 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6575 | // MIs[2] Operand 1 |
| 6576 | // No operand predicates |
| 6577 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6578 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6579 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6580 | // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6581 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 6582 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6583 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6584 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6586 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6587 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6588 | GIR_RootConstrainSelectedInstOperands, |
| 6589 | // GIR_Coverage, 5593, |
| 6590 | GIR_EraseRootFromParent_Done, |
| 6591 | // Label 391: @17805 |
| 6592 | GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(17882), // Rule ID 5592 // |
| 6593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6595 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6596 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6597 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6598 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6599 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6600 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 6601 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6602 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6603 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6604 | // MIs[2] Operand 1 |
| 6605 | // No operand predicates |
| 6606 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6607 | // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 6609 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6610 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6611 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6613 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6614 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6615 | GIR_RootConstrainSelectedInstOperands, |
| 6616 | // GIR_Coverage, 5592, |
| 6617 | GIR_EraseRootFromParent_Done, |
| 6618 | // Label 392: @17882 |
| 6619 | GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(17959), // Rule ID 504 // |
| 6620 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6621 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6622 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6623 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6624 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6625 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6626 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6627 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6628 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6629 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6630 | // MIs[2] Operand 1 |
| 6631 | // No operand predicates |
| 6632 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6633 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6634 | // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 6636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6637 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6638 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6640 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6641 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6642 | GIR_RootConstrainSelectedInstOperands, |
| 6643 | // GIR_Coverage, 504, |
| 6644 | GIR_EraseRootFromParent_Done, |
| 6645 | // Label 393: @17959 |
| 6646 | GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(18030), // Rule ID 5595 // |
| 6647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6649 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6650 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6651 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6652 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6653 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6654 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6655 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6656 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6657 | // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr), |
| 6659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6660 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6661 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6663 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6664 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6665 | GIR_RootConstrainSelectedInstOperands, |
| 6666 | // GIR_Coverage, 5595, |
| 6667 | GIR_EraseRootFromParent_Done, |
| 6668 | // Label 394: @18030 |
| 6669 | GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(18101), // Rule ID 505 // |
| 6670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6672 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6673 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6674 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6675 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6676 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6677 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6678 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6679 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6680 | // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr), |
| 6682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6683 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6686 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6687 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6688 | GIR_RootConstrainSelectedInstOperands, |
| 6689 | // GIR_Coverage, 505, |
| 6690 | GIR_EraseRootFromParent_Done, |
| 6691 | // Label 395: @18101 |
| 6692 | GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(18156), // Rule ID 1872 // |
| 6693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), |
| 6694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6695 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6696 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760), |
| 6697 | // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) |
| 6698 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVTi16), |
| 6699 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6700 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 6701 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535), |
| 6702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6703 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6704 | GIR_RootConstrainSelectedInstOperands, |
| 6705 | // GIR_Coverage, 1872, |
| 6706 | GIR_EraseRootFromParent_Done, |
| 6707 | // Label 396: @18156 |
| 6708 | GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(18211), // Rule ID 2101 // |
| 6709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6710 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6711 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6712 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760), |
| 6713 | // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) |
| 6714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVTi16), |
| 6715 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6716 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 6717 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535), |
| 6718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6719 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6720 | GIR_RootConstrainSelectedInstOperands, |
| 6721 | // GIR_Coverage, 2101, |
| 6722 | GIR_EraseRootFromParent_Done, |
| 6723 | // Label 397: @18211 |
| 6724 | GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(18268), // Rule ID 151 // |
| 6725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 6726 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6727 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6728 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6729 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6730 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6731 | // MIs[1] Operand 1 |
| 6732 | // No operand predicates |
| 6733 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6734 | // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRri), |
| 6736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6737 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6738 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 6739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6740 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6741 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6742 | GIR_RootConstrainSelectedInstOperands, |
| 6743 | // GIR_Coverage, 151, |
| 6744 | GIR_EraseRootFromParent_Done, |
| 6745 | // Label 398: @18268 |
| 6746 | GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(18325), // Rule ID 492 // |
| 6747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6749 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6750 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6751 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6752 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6753 | // MIs[1] Operand 1 |
| 6754 | // No operand predicates |
| 6755 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6756 | // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRri), |
| 6758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6759 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6760 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 6761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6762 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6763 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6764 | GIR_RootConstrainSelectedInstOperands, |
| 6765 | // GIR_Coverage, 492, |
| 6766 | GIR_EraseRootFromParent_Done, |
| 6767 | // Label 399: @18325 |
| 6768 | GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(18371), // Rule ID 152 // |
| 6769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 6770 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6771 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6772 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6773 | // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRrr), |
| 6775 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6776 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6777 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6779 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6780 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6781 | GIR_RootConstrainSelectedInstOperands, |
| 6782 | // GIR_Coverage, 152, |
| 6783 | GIR_EraseRootFromParent_Done, |
| 6784 | // Label 400: @18371 |
| 6785 | GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(18417), // Rule ID 493 // |
| 6786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6787 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6788 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6789 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6790 | // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6791 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 6792 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6793 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6794 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6796 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6797 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6798 | GIR_RootConstrainSelectedInstOperands, |
| 6799 | // GIR_Coverage, 493, |
| 6800 | GIR_EraseRootFromParent_Done, |
| 6801 | // Label 401: @18417 |
| 6802 | GIM_Reject, |
| 6803 | // Label 357: @18418 |
| 6804 | GIM_Reject, |
| 6805 | // Label 344: @18419 |
| 6806 | GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(18465), // Rule ID 2529 // |
| 6807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6808 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 6809 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 6810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6811 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6812 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6813 | // (or:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VORRd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 6814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 6815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6816 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 6817 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 6818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6819 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6820 | GIR_RootConstrainSelectedInstOperands, |
| 6821 | // GIR_Coverage, 2529, |
| 6822 | GIR_EraseRootFromParent_Done, |
| 6823 | // Label 402: @18465 |
| 6824 | GIM_Reject, |
| 6825 | // Label 345: @18466 |
| 6826 | GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(18577), // Rule ID 1858 // |
| 6827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6828 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 6829 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 6830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6831 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6832 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6833 | // (or:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 6834 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 6835 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6836 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6837 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6838 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6839 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 6840 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 6841 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6842 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6843 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 6844 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 6845 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 6846 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6847 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6848 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6849 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 6850 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6851 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6852 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6855 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6856 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 6857 | // GIR_Coverage, 1858, |
| 6858 | GIR_EraseRootFromParent_Done, |
| 6859 | // Label 403: @18577 |
| 6860 | GIM_Reject, |
| 6861 | // Label 346: @18578 |
| 6862 | GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(18624), // Rule ID 1154 // |
| 6863 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6864 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6865 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 6866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6867 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6868 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6869 | // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 6870 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 6871 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6872 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6873 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6875 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6876 | GIR_RootConstrainSelectedInstOperands, |
| 6877 | // GIR_Coverage, 1154, |
| 6878 | GIR_EraseRootFromParent_Done, |
| 6879 | // Label 404: @18624 |
| 6880 | GIM_Reject, |
| 6881 | // Label 347: @18625 |
| 6882 | GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(18736), |
| 6883 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 6884 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 6885 | GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(18676), // Rule ID 2532 // |
| 6886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6888 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6889 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6890 | // (or:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VORRq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 6891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 6892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6893 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 6894 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 6895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6896 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6897 | GIR_RootConstrainSelectedInstOperands, |
| 6898 | // GIR_Coverage, 2532, |
| 6899 | GIR_EraseRootFromParent_Done, |
| 6900 | // Label 406: @18676 |
| 6901 | GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(18735), // Rule ID 3481 // |
| 6902 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6903 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6904 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6905 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6906 | // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 6907 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6908 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6909 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 6910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 6911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6912 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6913 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6915 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6916 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6917 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6918 | GIR_RootConstrainSelectedInstOperands, |
| 6919 | // GIR_Coverage, 3481, |
| 6920 | GIR_EraseRootFromParent_Done, |
| 6921 | // Label 407: @18735 |
| 6922 | GIM_Reject, |
| 6923 | // Label 405: @18736 |
| 6924 | GIM_Reject, |
| 6925 | // Label 348: @18737 |
| 6926 | GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(18848), // Rule ID 1859 // |
| 6927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6928 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 6929 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 6930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6931 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6932 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6933 | // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 6934 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 6935 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6936 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6937 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6938 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6939 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 6940 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 6941 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6942 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6943 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 6944 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 6945 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 6946 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6947 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6948 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6949 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 6950 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6951 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6952 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6955 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6956 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 6957 | // GIR_Coverage, 1859, |
| 6958 | GIR_EraseRootFromParent_Done, |
| 6959 | // Label 408: @18848 |
| 6960 | GIM_Reject, |
| 6961 | // Label 349: @18849 |
| 6962 | GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(18895), // Rule ID 2528 // |
| 6963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6964 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6965 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 6966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6967 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6968 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6969 | // (or:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VORRd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 6970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 6971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6972 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 6973 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 6974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6975 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6976 | GIR_RootConstrainSelectedInstOperands, |
| 6977 | // GIR_Coverage, 2528, |
| 6978 | GIR_EraseRootFromParent_Done, |
| 6979 | // Label 409: @18895 |
| 6980 | GIM_Reject, |
| 6981 | // Label 350: @18896 |
| 6982 | GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(19007), |
| 6983 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6984 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6985 | GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(18947), // Rule ID 1155 // |
| 6986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6987 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6988 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6989 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6990 | // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 6991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 6992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6993 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6994 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6996 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6997 | GIR_RootConstrainSelectedInstOperands, |
| 6998 | // GIR_Coverage, 1155, |
| 6999 | GIR_EraseRootFromParent_Done, |
| 7000 | // Label 411: @18947 |
| 7001 | GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(19006), // Rule ID 3477 // |
| 7002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7004 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7005 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7006 | // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 7007 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7008 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7009 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 7010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 7011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7012 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7013 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7015 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7016 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7017 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7018 | GIR_RootConstrainSelectedInstOperands, |
| 7019 | // GIR_Coverage, 3477, |
| 7020 | GIR_EraseRootFromParent_Done, |
| 7021 | // Label 412: @19006 |
| 7022 | GIM_Reject, |
| 7023 | // Label 410: @19007 |
| 7024 | GIM_Reject, |
| 7025 | // Label 351: @19008 |
| 7026 | GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(19119), // Rule ID 1860 // |
| 7027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7028 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 7029 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 7030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7031 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7032 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7033 | // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7034 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7035 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7036 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7037 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7038 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7039 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7040 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 7041 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7042 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7043 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7044 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7045 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 7046 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7047 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7048 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7049 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7050 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7051 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7052 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7055 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7056 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7057 | // GIR_Coverage, 1860, |
| 7058 | GIR_EraseRootFromParent_Done, |
| 7059 | // Label 413: @19119 |
| 7060 | GIM_Reject, |
| 7061 | // Label 352: @19120 |
| 7062 | GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(19166), // Rule ID 2527 // |
| 7063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7064 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 7065 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 7066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7067 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7068 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7069 | // (or:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VORRd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 7070 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 7071 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7072 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7073 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7075 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7076 | GIR_RootConstrainSelectedInstOperands, |
| 7077 | // GIR_Coverage, 2527, |
| 7078 | GIR_EraseRootFromParent_Done, |
| 7079 | // Label 414: @19166 |
| 7080 | GIM_Reject, |
| 7081 | // Label 353: @19167 |
| 7082 | GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(19278), |
| 7083 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 7084 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7085 | GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(19218), // Rule ID 2531 // |
| 7086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7087 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7088 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7089 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7090 | // (or:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VORRq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 7091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 7092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7093 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7094 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7096 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7097 | GIR_RootConstrainSelectedInstOperands, |
| 7098 | // GIR_Coverage, 2531, |
| 7099 | GIR_EraseRootFromParent_Done, |
| 7100 | // Label 416: @19218 |
| 7101 | GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(19277), // Rule ID 3473 // |
| 7102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7104 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7105 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7106 | // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 7107 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7108 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7109 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 7110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 7111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7112 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7113 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7115 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7116 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7117 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7118 | GIR_RootConstrainSelectedInstOperands, |
| 7119 | // GIR_Coverage, 3473, |
| 7120 | GIR_EraseRootFromParent_Done, |
| 7121 | // Label 417: @19277 |
| 7122 | GIM_Reject, |
| 7123 | // Label 415: @19278 |
| 7124 | GIM_Reject, |
| 7125 | // Label 354: @19279 |
| 7126 | GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(19390), // Rule ID 1861 // |
| 7127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7128 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 7129 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 7130 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7131 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7132 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7133 | // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7134 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7135 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7136 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7137 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7138 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7139 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7140 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 7141 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7142 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7143 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7144 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7145 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 7146 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7147 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7148 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7149 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7150 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7151 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7152 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7153 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7154 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7155 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7156 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7157 | // GIR_Coverage, 1861, |
| 7158 | GIR_EraseRootFromParent_Done, |
| 7159 | // Label 418: @19390 |
| 7160 | GIM_Reject, |
| 7161 | // Label 355: @19391 |
| 7162 | GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(19502), |
| 7163 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 7164 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7165 | GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(19442), // Rule ID 2530 // |
| 7166 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7167 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7168 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7169 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7170 | // (or:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VORRq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 7171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 7172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7173 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7174 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7176 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7177 | GIR_RootConstrainSelectedInstOperands, |
| 7178 | // GIR_Coverage, 2530, |
| 7179 | GIR_EraseRootFromParent_Done, |
| 7180 | // Label 420: @19442 |
| 7181 | GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(19501), // Rule ID 3469 // |
| 7182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7183 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7184 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7185 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7186 | // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 7187 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7188 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7189 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 7190 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 7191 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7192 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7193 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7195 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7196 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7197 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7198 | GIR_RootConstrainSelectedInstOperands, |
| 7199 | // GIR_Coverage, 3469, |
| 7200 | GIR_EraseRootFromParent_Done, |
| 7201 | // Label 421: @19501 |
| 7202 | GIM_Reject, |
| 7203 | // Label 419: @19502 |
| 7204 | GIM_Reject, |
| 7205 | // Label 356: @19503 |
| 7206 | GIM_Reject, |
| 7207 | // Label 7: @19504 |
| 7208 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 435*/ GIMT_Encode4(21076), |
| 7209 | /*GILLT_s32*//*Label 422*/ GIMT_Encode4(19575), |
| 7210 | /*GILLT_s64*//*Label 423*/ GIMT_Encode4(19992), |
| 7211 | /*GILLT_v2s1*//*Label 424*/ GIMT_Encode4(20039), |
| 7212 | /*GILLT_v2s32*//*Label 425*/ GIMT_Encode4(20151), |
| 7213 | /*GILLT_v2s64*//*Label 426*/ GIMT_Encode4(20198), |
| 7214 | /*GILLT_v4s1*//*Label 427*/ GIMT_Encode4(20310), |
| 7215 | /*GILLT_v4s16*//*Label 428*/ GIMT_Encode4(20422), |
| 7216 | /*GILLT_v4s32*//*Label 429*/ GIMT_Encode4(20469), GIMT_Encode4(0), |
| 7217 | /*GILLT_v8s1*//*Label 430*/ GIMT_Encode4(20581), |
| 7218 | /*GILLT_v8s8*//*Label 431*/ GIMT_Encode4(20693), |
| 7219 | /*GILLT_v8s16*//*Label 432*/ GIMT_Encode4(20740), GIMT_Encode4(0), |
| 7220 | /*GILLT_v16s1*//*Label 433*/ GIMT_Encode4(20852), |
| 7221 | /*GILLT_v16s8*//*Label 434*/ GIMT_Encode4(20964), |
| 7222 | // Label 422: @19575 |
| 7223 | GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(19991), |
| 7224 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 7225 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 7226 | GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(19641), // Rule ID 5597 // |
| 7227 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7228 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7229 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, uint8_t(-1), |
| 7230 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7231 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7232 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 7233 | // MIs[1] Operand 1 |
| 7234 | // No operand predicates |
| 7235 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7236 | // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 7237 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 7238 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7239 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7241 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7242 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7243 | GIR_RootConstrainSelectedInstOperands, |
| 7244 | // GIR_Coverage, 5597, |
| 7245 | GIR_EraseRootFromParent_Done, |
| 7246 | // Label 437: @19641 |
| 7247 | GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(19696), // Rule ID 507 // |
| 7248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7249 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7250 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7251 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7252 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 7253 | // MIs[1] Operand 1 |
| 7254 | // No operand predicates |
| 7255 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 7256 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7257 | // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 7258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 7259 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7260 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7262 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7263 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7264 | GIR_RootConstrainSelectedInstOperands, |
| 7265 | // GIR_Coverage, 507, |
| 7266 | GIR_EraseRootFromParent_Done, |
| 7267 | // Label 438: @19696 |
| 7268 | GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(19740), // Rule ID 508 // |
| 7269 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7270 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7271 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7272 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 7273 | // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 7274 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNr), |
| 7275 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7276 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 7277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7278 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7279 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7280 | GIR_RootConstrainSelectedInstOperands, |
| 7281 | // GIR_Coverage, 508, |
| 7282 | GIR_EraseRootFromParent_Done, |
| 7283 | // Label 439: @19740 |
| 7284 | GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(19784), // Rule ID 165 // |
| 7285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 7286 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7287 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7288 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 7289 | // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 7290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNr), |
| 7291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7292 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 7293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7294 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7295 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7296 | GIR_RootConstrainSelectedInstOperands, |
| 7297 | // GIR_Coverage, 165, |
| 7298 | GIR_EraseRootFromParent_Done, |
| 7299 | // Label 440: @19784 |
| 7300 | GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(19841), // Rule ID 155 // |
| 7301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 7302 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7303 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7304 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7305 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7306 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 7307 | // MIs[1] Operand 1 |
| 7308 | // No operand predicates |
| 7309 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7310 | // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 7311 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORri), |
| 7312 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7313 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7314 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7316 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7317 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7318 | GIR_RootConstrainSelectedInstOperands, |
| 7319 | // GIR_Coverage, 155, |
| 7320 | GIR_EraseRootFromParent_Done, |
| 7321 | // Label 441: @19841 |
| 7322 | GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(19898), // Rule ID 495 // |
| 7323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7325 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7326 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7327 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7328 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 7329 | // MIs[1] Operand 1 |
| 7330 | // No operand predicates |
| 7331 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7332 | // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 7333 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORri), |
| 7334 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7335 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7336 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7338 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7339 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7340 | GIR_RootConstrainSelectedInstOperands, |
| 7341 | // GIR_Coverage, 495, |
| 7342 | GIR_EraseRootFromParent_Done, |
| 7343 | // Label 442: @19898 |
| 7344 | GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(19944), // Rule ID 156 // |
| 7345 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 7346 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7347 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7348 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7349 | // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 7350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORrr), |
| 7351 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7352 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7353 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 7354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7355 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7356 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7357 | GIR_RootConstrainSelectedInstOperands, |
| 7358 | // GIR_Coverage, 156, |
| 7359 | GIR_EraseRootFromParent_Done, |
| 7360 | // Label 443: @19944 |
| 7361 | GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(19990), // Rule ID 496 // |
| 7362 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7363 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7364 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7365 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7366 | // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 7367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 7368 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7369 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7370 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 7371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7372 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7373 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7374 | GIR_RootConstrainSelectedInstOperands, |
| 7375 | // GIR_Coverage, 496, |
| 7376 | GIR_EraseRootFromParent_Done, |
| 7377 | // Label 444: @19990 |
| 7378 | GIM_Reject, |
| 7379 | // Label 436: @19991 |
| 7380 | GIM_Reject, |
| 7381 | // Label 423: @19992 |
| 7382 | GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(20038), // Rule ID 2535 // |
| 7383 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7384 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 7385 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 7386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7387 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7388 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7389 | // (xor:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VEORd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 7390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 7391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7392 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7393 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7395 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7396 | GIR_RootConstrainSelectedInstOperands, |
| 7397 | // GIR_Coverage, 2535, |
| 7398 | GIR_EraseRootFromParent_Done, |
| 7399 | // Label 445: @20038 |
| 7400 | GIM_Reject, |
| 7401 | // Label 424: @20039 |
| 7402 | GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(20150), // Rule ID 1854 // |
| 7403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7404 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 7405 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 7406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7407 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7408 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7409 | // (xor:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7410 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7411 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7412 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7413 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7414 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7415 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7416 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 7417 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7418 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7419 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7420 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7421 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 7422 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7423 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7424 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7425 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7426 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7427 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7428 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7429 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7430 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7431 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7432 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7433 | // GIR_Coverage, 1854, |
| 7434 | GIR_EraseRootFromParent_Done, |
| 7435 | // Label 446: @20150 |
| 7436 | GIM_Reject, |
| 7437 | // Label 425: @20151 |
| 7438 | GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(20197), // Rule ID 1152 // |
| 7439 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7440 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 7441 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 7442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7443 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7444 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7445 | // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 7446 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 7447 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7448 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 7449 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 7450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7451 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7452 | GIR_RootConstrainSelectedInstOperands, |
| 7453 | // GIR_Coverage, 1152, |
| 7454 | GIR_EraseRootFromParent_Done, |
| 7455 | // Label 447: @20197 |
| 7456 | GIM_Reject, |
| 7457 | // Label 426: @20198 |
| 7458 | GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(20309), |
| 7459 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 7460 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7461 | GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(20249), // Rule ID 2538 // |
| 7462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7463 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7464 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7465 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7466 | // (xor:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VEORq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 7467 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 7468 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7469 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7470 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7472 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7473 | GIR_RootConstrainSelectedInstOperands, |
| 7474 | // GIR_Coverage, 2538, |
| 7475 | GIR_EraseRootFromParent_Done, |
| 7476 | // Label 449: @20249 |
| 7477 | GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(20308), // Rule ID 3495 // |
| 7478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7479 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7480 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7481 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7482 | // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 7483 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7484 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7485 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 7486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 7487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7488 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7489 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7491 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7492 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7493 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7494 | GIR_RootConstrainSelectedInstOperands, |
| 7495 | // GIR_Coverage, 3495, |
| 7496 | GIR_EraseRootFromParent_Done, |
| 7497 | // Label 450: @20308 |
| 7498 | GIM_Reject, |
| 7499 | // Label 448: @20309 |
| 7500 | GIM_Reject, |
| 7501 | // Label 427: @20310 |
| 7502 | GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(20421), // Rule ID 1855 // |
| 7503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7504 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 7505 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 7506 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7507 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7508 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7509 | // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7510 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7511 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7512 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7513 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7514 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7515 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7516 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 7517 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7518 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7519 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7520 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7521 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 7522 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7523 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7524 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7525 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7526 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7527 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7528 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7531 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7532 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7533 | // GIR_Coverage, 1855, |
| 7534 | GIR_EraseRootFromParent_Done, |
| 7535 | // Label 451: @20421 |
| 7536 | GIM_Reject, |
| 7537 | // Label 428: @20422 |
| 7538 | GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(20468), // Rule ID 2534 // |
| 7539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7540 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 7541 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 7542 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7543 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7544 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7545 | // (xor:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VEORd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 7546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 7547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7548 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7549 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7551 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7552 | GIR_RootConstrainSelectedInstOperands, |
| 7553 | // GIR_Coverage, 2534, |
| 7554 | GIR_EraseRootFromParent_Done, |
| 7555 | // Label 452: @20468 |
| 7556 | GIM_Reject, |
| 7557 | // Label 429: @20469 |
| 7558 | GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(20580), |
| 7559 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 7560 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7561 | GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(20520), // Rule ID 1153 // |
| 7562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7563 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7564 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7565 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7566 | // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 7567 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 7568 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7569 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 7570 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 7571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7572 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7573 | GIR_RootConstrainSelectedInstOperands, |
| 7574 | // GIR_Coverage, 1153, |
| 7575 | GIR_EraseRootFromParent_Done, |
| 7576 | // Label 454: @20520 |
| 7577 | GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(20579), // Rule ID 3491 // |
| 7578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7580 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7581 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7582 | // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 7583 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7584 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7585 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 7586 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 7587 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7588 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7589 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7591 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7592 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7593 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7594 | GIR_RootConstrainSelectedInstOperands, |
| 7595 | // GIR_Coverage, 3491, |
| 7596 | GIR_EraseRootFromParent_Done, |
| 7597 | // Label 455: @20579 |
| 7598 | GIM_Reject, |
| 7599 | // Label 453: @20580 |
| 7600 | GIM_Reject, |
| 7601 | // Label 430: @20581 |
| 7602 | GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(20692), // Rule ID 1856 // |
| 7603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7604 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 7605 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 7606 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7607 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7608 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7609 | // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7610 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7611 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7612 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7613 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7614 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7615 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7616 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 7617 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7618 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7619 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7620 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7621 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 7622 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7623 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7624 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7625 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7626 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7627 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7628 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7629 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7630 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7631 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7632 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7633 | // GIR_Coverage, 1856, |
| 7634 | GIR_EraseRootFromParent_Done, |
| 7635 | // Label 456: @20692 |
| 7636 | GIM_Reject, |
| 7637 | // Label 431: @20693 |
| 7638 | GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(20739), // Rule ID 2533 // |
| 7639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7640 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 7641 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 7642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7643 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7644 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7645 | // (xor:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VEORd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 7646 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 7647 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7648 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7649 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7651 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7652 | GIR_RootConstrainSelectedInstOperands, |
| 7653 | // GIR_Coverage, 2533, |
| 7654 | GIR_EraseRootFromParent_Done, |
| 7655 | // Label 457: @20739 |
| 7656 | GIM_Reject, |
| 7657 | // Label 432: @20740 |
| 7658 | GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(20851), |
| 7659 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 7660 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7661 | GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(20791), // Rule ID 2537 // |
| 7662 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7663 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7664 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7665 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7666 | // (xor:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VEORq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 7667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 7668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7669 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7670 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7672 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7673 | GIR_RootConstrainSelectedInstOperands, |
| 7674 | // GIR_Coverage, 2537, |
| 7675 | GIR_EraseRootFromParent_Done, |
| 7676 | // Label 459: @20791 |
| 7677 | GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(20850), // Rule ID 3487 // |
| 7678 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7679 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7680 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7681 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7682 | // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 7683 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7684 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7685 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 7686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 7687 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7688 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7689 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7691 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7692 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7693 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7694 | GIR_RootConstrainSelectedInstOperands, |
| 7695 | // GIR_Coverage, 3487, |
| 7696 | GIR_EraseRootFromParent_Done, |
| 7697 | // Label 460: @20850 |
| 7698 | GIM_Reject, |
| 7699 | // Label 458: @20851 |
| 7700 | GIM_Reject, |
| 7701 | // Label 433: @20852 |
| 7702 | GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(20963), // Rule ID 1857 // |
| 7703 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7704 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 7705 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 7706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7707 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7708 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7709 | // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7710 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7711 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7712 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7713 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7714 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7715 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7716 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 7717 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7718 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7719 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7720 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7721 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 7722 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7723 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7724 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7725 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7726 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7727 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7728 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7730 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7731 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7732 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7733 | // GIR_Coverage, 1857, |
| 7734 | GIR_EraseRootFromParent_Done, |
| 7735 | // Label 461: @20963 |
| 7736 | GIM_Reject, |
| 7737 | // Label 434: @20964 |
| 7738 | GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(21075), |
| 7739 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 7740 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7741 | GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(21015), // Rule ID 2536 // |
| 7742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7743 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7744 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7745 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7746 | // (xor:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VEORq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 7747 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 7748 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7749 | GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7750 | GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7752 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7753 | GIR_RootConstrainSelectedInstOperands, |
| 7754 | // GIR_Coverage, 2536, |
| 7755 | GIR_EraseRootFromParent_Done, |
| 7756 | // Label 463: @21015 |
| 7757 | GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(21074), // Rule ID 3483 // |
| 7758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 7759 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7760 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7761 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7762 | // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 7763 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7764 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7765 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 7766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 7767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7768 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7769 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7771 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7772 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7773 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7774 | GIR_RootConstrainSelectedInstOperands, |
| 7775 | // GIR_Coverage, 3483, |
| 7776 | GIR_EraseRootFromParent_Done, |
| 7777 | // Label 464: @21074 |
| 7778 | GIM_Reject, |
| 7779 | // Label 462: @21075 |
| 7780 | GIM_Reject, |
| 7781 | // Label 435: @21076 |
| 7782 | GIM_Reject, |
| 7783 | // Label 8: @21077 |
| 7784 | GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(21502), |
| 7785 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 7786 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(16), /*)*//*default:*//*Label 470*/ GIMT_Encode4(21501), |
| 7787 | /*GILLT_v2s64*//*Label 466*/ GIMT_Encode4(21140), GIMT_Encode4(0), GIMT_Encode4(0), |
| 7788 | /*GILLT_v4s32*//*Label 467*/ GIMT_Encode4(21198), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 7789 | /*GILLT_v8s16*//*Label 468*/ GIMT_Encode4(21301), GIMT_Encode4(0), GIMT_Encode4(0), |
| 7790 | /*GILLT_v16s8*//*Label 469*/ GIMT_Encode4(21443), |
| 7791 | // Label 466: @21140 |
| 7792 | GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(21197), // Rule ID 3116 // |
| 7793 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7794 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 7795 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 7796 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7797 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7798 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7799 | // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm) => (REG_SEQUENCE:{ *:[v2i64] } QPR:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] }) |
| 7800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7802 | GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 7803 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 7804 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 7805 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 7806 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 7807 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 7808 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 7809 | // GIR_Coverage, 3116, |
| 7810 | GIR_EraseRootFromParent_Done, |
| 7811 | // Label 471: @21197 |
| 7812 | GIM_Reject, |
| 7813 | // Label 467: @21198 |
| 7814 | GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(21300), |
| 7815 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 7816 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 7817 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7818 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7819 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7820 | GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(21260), // Rule ID 3117 // |
| 7821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7822 | // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm) => (REG_SEQUENCE:{ *:[v4i32] } QPR:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] }) |
| 7823 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7824 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7825 | GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 7826 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 7827 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 7828 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 7829 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 7830 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 7831 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 7832 | // GIR_Coverage, 3117, |
| 7833 | GIR_EraseRootFromParent_Done, |
| 7834 | // Label 473: @21260 |
| 7835 | GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(21299), // Rule ID 3120 // |
| 7836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7837 | // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm) => (REG_SEQUENCE:{ *:[v4f32] } QPR:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] }) |
| 7838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7839 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7840 | GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 7841 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 7842 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 7843 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 7844 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 7845 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 7846 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 7847 | // GIR_Coverage, 3120, |
| 7848 | GIR_EraseRootFromParent_Done, |
| 7849 | // Label 474: @21299 |
| 7850 | GIM_Reject, |
| 7851 | // Label 472: @21300 |
| 7852 | GIM_Reject, |
| 7853 | // Label 468: @21301 |
| 7854 | GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(21442), |
| 7855 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 7856 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 7857 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7858 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7859 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7860 | GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(21363), // Rule ID 3118 // |
| 7861 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7862 | // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm) => (REG_SEQUENCE:{ *:[v8i16] } QPR:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] }) |
| 7863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7865 | GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 7866 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 7867 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 7868 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 7869 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 7870 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 7871 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 7872 | // GIR_Coverage, 3118, |
| 7873 | GIR_EraseRootFromParent_Done, |
| 7874 | // Label 476: @21363 |
| 7875 | GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(21402), // Rule ID 3121 // |
| 7876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7877 | // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm) => (REG_SEQUENCE:{ *:[v8f16] } QPR:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] }) |
| 7878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7880 | GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 7881 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 7882 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 7883 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 7884 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 7885 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 7886 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 7887 | // GIR_Coverage, 3121, |
| 7888 | GIR_EraseRootFromParent_Done, |
| 7889 | // Label 477: @21402 |
| 7890 | GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(21441), // Rule ID 3122 // |
| 7891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7892 | // (concat_vectors:{ *:[v8bf16] } DPR:{ *:[v4bf16] }:$Dn, DPR:{ *:[v4bf16] }:$Dm) => (REG_SEQUENCE:{ *:[v8bf16] } QPR:{ *:[i32] }, DPR:{ *:[v4bf16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4bf16] }:$Dm, dsub_1:{ *:[i32] }) |
| 7893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7894 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7895 | GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 7896 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 7897 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 7898 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 7899 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 7900 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 7901 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 7902 | // GIR_Coverage, 3122, |
| 7903 | GIR_EraseRootFromParent_Done, |
| 7904 | // Label 478: @21441 |
| 7905 | GIM_Reject, |
| 7906 | // Label 475: @21442 |
| 7907 | GIM_Reject, |
| 7908 | // Label 469: @21443 |
| 7909 | GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(21500), // Rule ID 3119 // |
| 7910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 7911 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 7912 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 7913 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7914 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7915 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7916 | // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm) => (REG_SEQUENCE:{ *:[v16i8] } QPR:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] }) |
| 7917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7918 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7919 | GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 7920 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 7921 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 7922 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 7923 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 7924 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 7925 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 7926 | // GIR_Coverage, 3119, |
| 7927 | GIR_EraseRootFromParent_Done, |
| 7928 | // Label 479: @21500 |
| 7929 | GIM_Reject, |
| 7930 | // Label 470: @21501 |
| 7931 | GIM_Reject, |
| 7932 | // Label 465: @21502 |
| 7933 | GIM_Reject, |
| 7934 | // Label 9: @21503 |
| 7935 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 489*/ GIMT_Encode4(31950), |
| 7936 | /*GILLT_s32*//*Label 480*/ GIMT_Encode4(21574), |
| 7937 | /*GILLT_s64*//*Label 481*/ GIMT_Encode4(21722), GIMT_Encode4(0), |
| 7938 | /*GILLT_v2s32*//*Label 482*/ GIMT_Encode4(22615), |
| 7939 | /*GILLT_v2s64*//*Label 483*/ GIMT_Encode4(23508), GIMT_Encode4(0), |
| 7940 | /*GILLT_v4s16*//*Label 484*/ GIMT_Encode4(25345), |
| 7941 | /*GILLT_v4s32*//*Label 485*/ GIMT_Encode4(26509), GIMT_Encode4(0), GIMT_Encode4(0), |
| 7942 | /*GILLT_v8s8*//*Label 486*/ GIMT_Encode4(28346), |
| 7943 | /*GILLT_v8s16*//*Label 487*/ GIMT_Encode4(28830), GIMT_Encode4(0), GIMT_Encode4(0), |
| 7944 | /*GILLT_v16s8*//*Label 488*/ GIMT_Encode4(30938), |
| 7945 | // Label 480: @21574 |
| 7946 | GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(21721), |
| 7947 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 7948 | GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(21616), // Rule ID 706 // |
| 7949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs), |
| 7950 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7951 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 7952 | // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn) => (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn) |
| 7953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVRS), |
| 7954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 7955 | GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 7956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7957 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7958 | GIR_RootConstrainSelectedInstOperands, |
| 7959 | // GIR_Coverage, 706, |
| 7960 | GIR_EraseRootFromParent_Done, |
| 7961 | // Label 491: @21616 |
| 7962 | GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(21650), // Rule ID 707 // |
| 7963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs_UseVMOVSR), |
| 7964 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 7965 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7966 | // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt) => (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt) |
| 7967 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVSR), |
| 7968 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sn] |
| 7969 | GIR_RootToRootCopy, /*OpIdx*/1, // Rt |
| 7970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7971 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7972 | GIR_RootConstrainSelectedInstOperands, |
| 7973 | // GIR_Coverage, 707, |
| 7974 | GIR_EraseRootFromParent_Done, |
| 7975 | // Label 492: @21650 |
| 7976 | GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(21720), // Rule ID 2736 // |
| 7977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseVMOVSR_HasNEON), |
| 7978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7979 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7980 | // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VMOVDRR:{ *:[f64] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$a), ssub_0:{ *:[i32] }) |
| 7981 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 7982 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VMOVDRR), |
| 7983 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7984 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 7985 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 7986 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7987 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7988 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7990 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7991 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 7992 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 7993 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 7994 | // GIR_Coverage, 2736, |
| 7995 | GIR_EraseRootFromParent_Done, |
| 7996 | // Label 493: @21720 |
| 7997 | GIM_Reject, |
| 7998 | // Label 490: @21721 |
| 7999 | GIM_Reject, |
| 8000 | // Label 481: @21722 |
| 8001 | GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(21754), // Rule ID 2738 // |
| 8002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8003 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8005 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8006 | // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[f64] }:$src |
| 8007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8008 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8009 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8010 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8011 | // GIR_Coverage, 2738, |
| 8012 | GIR_EraseRootFromParent_Done, |
| 8013 | // Label 494: @21754 |
| 8014 | GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(21786), // Rule ID 2739 // |
| 8015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8016 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8018 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8019 | // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v1i64] }:$src |
| 8020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8021 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8022 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8023 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8024 | // GIR_Coverage, 2739, |
| 8025 | GIR_EraseRootFromParent_Done, |
| 8026 | // Label 495: @21786 |
| 8027 | GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(21818), // Rule ID 2754 // |
| 8028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8029 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8031 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8032 | // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[f64] }:$src |
| 8033 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8034 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8035 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8036 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8037 | // GIR_Coverage, 2754, |
| 8038 | GIR_EraseRootFromParent_Done, |
| 8039 | // Label 496: @21818 |
| 8040 | GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(21850), // Rule ID 2755 // |
| 8041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8042 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8044 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8045 | // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[f64] }:$src |
| 8046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8047 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8048 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8049 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8050 | // GIR_Coverage, 2755, |
| 8051 | GIR_EraseRootFromParent_Done, |
| 8052 | // Label 497: @21850 |
| 8053 | GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(21882), // Rule ID 2756 // |
| 8054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8055 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8057 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8058 | // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[f64] }:$src |
| 8059 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8060 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8061 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8062 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8063 | // GIR_Coverage, 2756, |
| 8064 | GIR_EraseRootFromParent_Done, |
| 8065 | // Label 498: @21882 |
| 8066 | GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(21914), // Rule ID 2757 // |
| 8067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8068 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8069 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8070 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8071 | // (bitconvert:{ *:[f64] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[f64] }:$src |
| 8072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8073 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8074 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8075 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8076 | // GIR_Coverage, 2757, |
| 8077 | GIR_EraseRootFromParent_Done, |
| 8078 | // Label 499: @21914 |
| 8079 | GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(21946), // Rule ID 2758 // |
| 8080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8081 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8083 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8084 | // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[f64] }:$src |
| 8085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8086 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8087 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8088 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8089 | // GIR_Coverage, 2758, |
| 8090 | GIR_EraseRootFromParent_Done, |
| 8091 | // Label 500: @21946 |
| 8092 | GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(21978), // Rule ID 2759 // |
| 8093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8094 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8095 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8096 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8097 | // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[f64] }:$src |
| 8098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8099 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8100 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8101 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8102 | // GIR_Coverage, 2759, |
| 8103 | GIR_EraseRootFromParent_Done, |
| 8104 | // Label 501: @21978 |
| 8105 | GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(22010), // Rule ID 2760 // |
| 8106 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8107 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8109 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8110 | // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v1i64] }:$src |
| 8111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8112 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8113 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8114 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8115 | // GIR_Coverage, 2760, |
| 8116 | GIR_EraseRootFromParent_Done, |
| 8117 | // Label 502: @22010 |
| 8118 | GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(22042), // Rule ID 2761 // |
| 8119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8120 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8121 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8122 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8123 | // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v1i64] }:$src |
| 8124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8125 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8126 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8127 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8128 | // GIR_Coverage, 2761, |
| 8129 | GIR_EraseRootFromParent_Done, |
| 8130 | // Label 503: @22042 |
| 8131 | GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(22074), // Rule ID 2762 // |
| 8132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8133 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8135 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8136 | // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v1i64] }:$src |
| 8137 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8138 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8139 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8140 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8141 | // GIR_Coverage, 2762, |
| 8142 | GIR_EraseRootFromParent_Done, |
| 8143 | // Label 504: @22074 |
| 8144 | GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(22106), // Rule ID 2763 // |
| 8145 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8146 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8147 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8148 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8149 | // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v1i64] }:$src |
| 8150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8151 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8152 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8153 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8154 | // GIR_Coverage, 2763, |
| 8155 | GIR_EraseRootFromParent_Done, |
| 8156 | // Label 505: @22106 |
| 8157 | GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(22138), // Rule ID 2764 // |
| 8158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8159 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8161 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8162 | // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v1i64] }:$src |
| 8163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8164 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8165 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8166 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8167 | // GIR_Coverage, 2764, |
| 8168 | GIR_EraseRootFromParent_Done, |
| 8169 | // Label 506: @22138 |
| 8170 | GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(22170), // Rule ID 2765 // |
| 8171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8172 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8173 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8174 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8175 | // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v1i64] }:$src |
| 8176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8177 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8178 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8179 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8180 | // GIR_Coverage, 2765, |
| 8181 | GIR_EraseRootFromParent_Done, |
| 8182 | // Label 507: @22170 |
| 8183 | GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(22207), // Rule ID 2846 // |
| 8184 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8185 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8186 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8187 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8188 | // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src) |
| 8189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 8190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8191 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8193 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8194 | GIR_RootConstrainSelectedInstOperands, |
| 8195 | // GIR_Coverage, 2846, |
| 8196 | GIR_EraseRootFromParent_Done, |
| 8197 | // Label 508: @22207 |
| 8198 | GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(22244), // Rule ID 2847 // |
| 8199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8200 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8201 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8202 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8203 | // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src) |
| 8204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 8205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8206 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8208 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8209 | GIR_RootConstrainSelectedInstOperands, |
| 8210 | // GIR_Coverage, 2847, |
| 8211 | GIR_EraseRootFromParent_Done, |
| 8212 | // Label 509: @22244 |
| 8213 | GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(22281), // Rule ID 2848 // |
| 8214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8215 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8217 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8218 | // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src) |
| 8219 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 8220 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8221 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8223 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8224 | GIR_RootConstrainSelectedInstOperands, |
| 8225 | // GIR_Coverage, 2848, |
| 8226 | GIR_EraseRootFromParent_Done, |
| 8227 | // Label 510: @22281 |
| 8228 | GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(22318), // Rule ID 2849 // |
| 8229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8230 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8232 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8233 | // (bitconvert:{ *:[f64] } DPR:{ *:[v4bf16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4bf16] }:$src) |
| 8234 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 8235 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8236 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8238 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8239 | GIR_RootConstrainSelectedInstOperands, |
| 8240 | // GIR_Coverage, 2849, |
| 8241 | GIR_EraseRootFromParent_Done, |
| 8242 | // Label 511: @22318 |
| 8243 | GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(22355), // Rule ID 2850 // |
| 8244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8245 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8246 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8247 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8248 | // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src) |
| 8249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 8250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8251 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8253 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8254 | GIR_RootConstrainSelectedInstOperands, |
| 8255 | // GIR_Coverage, 2850, |
| 8256 | GIR_EraseRootFromParent_Done, |
| 8257 | // Label 512: @22355 |
| 8258 | GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(22392), // Rule ID 2851 // |
| 8259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8260 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8261 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8262 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8263 | // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src) |
| 8264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 8265 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8266 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8268 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8269 | GIR_RootConstrainSelectedInstOperands, |
| 8270 | // GIR_Coverage, 2851, |
| 8271 | GIR_EraseRootFromParent_Done, |
| 8272 | // Label 513: @22392 |
| 8273 | GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(22429), // Rule ID 2852 // |
| 8274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8275 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8277 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8278 | // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) |
| 8279 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 8280 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8281 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8283 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8284 | GIR_RootConstrainSelectedInstOperands, |
| 8285 | // GIR_Coverage, 2852, |
| 8286 | GIR_EraseRootFromParent_Done, |
| 8287 | // Label 514: @22429 |
| 8288 | GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(22466), // Rule ID 2853 // |
| 8289 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8290 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8291 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8292 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8293 | // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) |
| 8294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 8295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8296 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8298 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8299 | GIR_RootConstrainSelectedInstOperands, |
| 8300 | // GIR_Coverage, 2853, |
| 8301 | GIR_EraseRootFromParent_Done, |
| 8302 | // Label 515: @22466 |
| 8303 | GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(22503), // Rule ID 2854 // |
| 8304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8305 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8307 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8308 | // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) |
| 8309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 8310 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8311 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8313 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8314 | GIR_RootConstrainSelectedInstOperands, |
| 8315 | // GIR_Coverage, 2854, |
| 8316 | GIR_EraseRootFromParent_Done, |
| 8317 | // Label 516: @22503 |
| 8318 | GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(22540), // Rule ID 2855 // |
| 8319 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8320 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8322 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8323 | // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src) |
| 8324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 8325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8326 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8328 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8329 | GIR_RootConstrainSelectedInstOperands, |
| 8330 | // GIR_Coverage, 2855, |
| 8331 | GIR_EraseRootFromParent_Done, |
| 8332 | // Label 517: @22540 |
| 8333 | GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(22577), // Rule ID 2856 // |
| 8334 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8335 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8337 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8338 | // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) |
| 8339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 8340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8341 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8343 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8344 | GIR_RootConstrainSelectedInstOperands, |
| 8345 | // GIR_Coverage, 2856, |
| 8346 | GIR_EraseRootFromParent_Done, |
| 8347 | // Label 518: @22577 |
| 8348 | GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(22614), // Rule ID 2857 // |
| 8349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8350 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8351 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8352 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8353 | // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) |
| 8354 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 8355 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8356 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8358 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8359 | GIR_RootConstrainSelectedInstOperands, |
| 8360 | // GIR_Coverage, 2857, |
| 8361 | GIR_EraseRootFromParent_Done, |
| 8362 | // Label 519: @22614 |
| 8363 | GIM_Reject, |
| 8364 | // Label 482: @22615 |
| 8365 | GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(22647), // Rule ID 2740 // |
| 8366 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8367 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8368 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8369 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8370 | // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v2f32] }:$src |
| 8371 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8372 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8373 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8374 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8375 | // GIR_Coverage, 2740, |
| 8376 | GIR_EraseRootFromParent_Done, |
| 8377 | // Label 520: @22647 |
| 8378 | GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(22679), // Rule ID 2741 // |
| 8379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8380 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8381 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8382 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8383 | // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v2i32] }:$src |
| 8384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8385 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8386 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8387 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8388 | // GIR_Coverage, 2741, |
| 8389 | GIR_EraseRootFromParent_Done, |
| 8390 | // Label 521: @22679 |
| 8391 | GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(22711), // Rule ID 2766 // |
| 8392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8393 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8395 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8396 | // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2f32] }:$src |
| 8397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8398 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8399 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8400 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8401 | // GIR_Coverage, 2766, |
| 8402 | GIR_EraseRootFromParent_Done, |
| 8403 | // Label 522: @22711 |
| 8404 | GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(22743), // Rule ID 2767 // |
| 8405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8406 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8408 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8409 | // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2f32] }:$src |
| 8410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8411 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8412 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8413 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8414 | // GIR_Coverage, 2767, |
| 8415 | GIR_EraseRootFromParent_Done, |
| 8416 | // Label 523: @22743 |
| 8417 | GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(22775), // Rule ID 2768 // |
| 8418 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8419 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8420 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8421 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8422 | // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2f32] }:$src |
| 8423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8424 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8425 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8426 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8427 | // GIR_Coverage, 2768, |
| 8428 | GIR_EraseRootFromParent_Done, |
| 8429 | // Label 524: @22775 |
| 8430 | GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(22807), // Rule ID 2769 // |
| 8431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8432 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8434 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8435 | // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v2f32] }:$src |
| 8436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8437 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8438 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8439 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8440 | // GIR_Coverage, 2769, |
| 8441 | GIR_EraseRootFromParent_Done, |
| 8442 | // Label 525: @22807 |
| 8443 | GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(22839), // Rule ID 2770 // |
| 8444 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8445 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8446 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8447 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8448 | // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2f32] }:$src |
| 8449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8450 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8451 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8452 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8453 | // GIR_Coverage, 2770, |
| 8454 | GIR_EraseRootFromParent_Done, |
| 8455 | // Label 526: @22839 |
| 8456 | GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(22871), // Rule ID 2771 // |
| 8457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8458 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8459 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8460 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8461 | // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2f32] }:$src |
| 8462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8463 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8464 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8465 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8466 | // GIR_Coverage, 2771, |
| 8467 | GIR_EraseRootFromParent_Done, |
| 8468 | // Label 527: @22871 |
| 8469 | GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(22903), // Rule ID 2772 // |
| 8470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8471 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8472 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8473 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8474 | // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2i32] }:$src |
| 8475 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8476 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8477 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8478 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8479 | // GIR_Coverage, 2772, |
| 8480 | GIR_EraseRootFromParent_Done, |
| 8481 | // Label 528: @22903 |
| 8482 | GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(22935), // Rule ID 2773 // |
| 8483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8484 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8485 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8486 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8487 | // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2i32] }:$src |
| 8488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8489 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8490 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8491 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8492 | // GIR_Coverage, 2773, |
| 8493 | GIR_EraseRootFromParent_Done, |
| 8494 | // Label 529: @22935 |
| 8495 | GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(22967), // Rule ID 2774 // |
| 8496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8497 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8499 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8500 | // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2i32] }:$src |
| 8501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8502 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8503 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8504 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8505 | // GIR_Coverage, 2774, |
| 8506 | GIR_EraseRootFromParent_Done, |
| 8507 | // Label 530: @22967 |
| 8508 | GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(22999), // Rule ID 2775 // |
| 8509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8510 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8511 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8512 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8513 | // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v2i32] }:$src |
| 8514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8515 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8516 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8517 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8518 | // GIR_Coverage, 2775, |
| 8519 | GIR_EraseRootFromParent_Done, |
| 8520 | // Label 531: @22999 |
| 8521 | GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(23031), // Rule ID 2776 // |
| 8522 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8523 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8525 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8526 | // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2i32] }:$src |
| 8527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8528 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8529 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8530 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8531 | // GIR_Coverage, 2776, |
| 8532 | GIR_EraseRootFromParent_Done, |
| 8533 | // Label 532: @23031 |
| 8534 | GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(23063), // Rule ID 2777 // |
| 8535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8536 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8537 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8538 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8539 | // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2i32] }:$src |
| 8540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8541 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8542 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8543 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 8544 | // GIR_Coverage, 2777, |
| 8545 | GIR_EraseRootFromParent_Done, |
| 8546 | // Label 533: @23063 |
| 8547 | GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(23100), // Rule ID 2858 // |
| 8548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8549 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8550 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8551 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8552 | // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src) |
| 8553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 8554 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8555 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8557 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8558 | GIR_RootConstrainSelectedInstOperands, |
| 8559 | // GIR_Coverage, 2858, |
| 8560 | GIR_EraseRootFromParent_Done, |
| 8561 | // Label 534: @23100 |
| 8562 | GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(23137), // Rule ID 2859 // |
| 8563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8564 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8565 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8566 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8567 | // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) |
| 8568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 8569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8570 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8572 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8573 | GIR_RootConstrainSelectedInstOperands, |
| 8574 | // GIR_Coverage, 2859, |
| 8575 | GIR_EraseRootFromParent_Done, |
| 8576 | // Label 535: @23137 |
| 8577 | GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(23174), // Rule ID 2860 // |
| 8578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8579 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8580 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8581 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8582 | // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) |
| 8583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 8584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8585 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8587 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8588 | GIR_RootConstrainSelectedInstOperands, |
| 8589 | // GIR_Coverage, 2860, |
| 8590 | GIR_EraseRootFromParent_Done, |
| 8591 | // Label 536: @23174 |
| 8592 | GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(23211), // Rule ID 2861 // |
| 8593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8594 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8596 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8597 | // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src) |
| 8598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 8599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8600 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8602 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8603 | GIR_RootConstrainSelectedInstOperands, |
| 8604 | // GIR_Coverage, 2861, |
| 8605 | GIR_EraseRootFromParent_Done, |
| 8606 | // Label 537: @23211 |
| 8607 | GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(23248), // Rule ID 2862 // |
| 8608 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8609 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8610 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8611 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8612 | // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) |
| 8613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 8614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8615 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8617 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8618 | GIR_RootConstrainSelectedInstOperands, |
| 8619 | // GIR_Coverage, 2862, |
| 8620 | GIR_EraseRootFromParent_Done, |
| 8621 | // Label 538: @23248 |
| 8622 | GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(23285), // Rule ID 2863 // |
| 8623 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8624 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8625 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8626 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8627 | // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) |
| 8628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 8629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8630 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8632 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8633 | GIR_RootConstrainSelectedInstOperands, |
| 8634 | // GIR_Coverage, 2863, |
| 8635 | GIR_EraseRootFromParent_Done, |
| 8636 | // Label 539: @23285 |
| 8637 | GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(23322), // Rule ID 2864 // |
| 8638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8639 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8640 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8641 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8642 | // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src) |
| 8643 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 8644 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8645 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8647 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8648 | GIR_RootConstrainSelectedInstOperands, |
| 8649 | // GIR_Coverage, 2864, |
| 8650 | GIR_EraseRootFromParent_Done, |
| 8651 | // Label 540: @23322 |
| 8652 | GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(23359), // Rule ID 2865 // |
| 8653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8654 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8655 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8656 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8657 | // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) |
| 8658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 8659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8660 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8662 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8663 | GIR_RootConstrainSelectedInstOperands, |
| 8664 | // GIR_Coverage, 2865, |
| 8665 | GIR_EraseRootFromParent_Done, |
| 8666 | // Label 541: @23359 |
| 8667 | GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(23396), // Rule ID 2866 // |
| 8668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8669 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8670 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8671 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8672 | // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) |
| 8673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 8674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8675 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8677 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8678 | GIR_RootConstrainSelectedInstOperands, |
| 8679 | // GIR_Coverage, 2866, |
| 8680 | GIR_EraseRootFromParent_Done, |
| 8681 | // Label 542: @23396 |
| 8682 | GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(23433), // Rule ID 2867 // |
| 8683 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8684 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8686 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8687 | // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src) |
| 8688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 8689 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8690 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8692 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8693 | GIR_RootConstrainSelectedInstOperands, |
| 8694 | // GIR_Coverage, 2867, |
| 8695 | GIR_EraseRootFromParent_Done, |
| 8696 | // Label 543: @23433 |
| 8697 | GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(23470), // Rule ID 2868 // |
| 8698 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8699 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8700 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8701 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8702 | // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) |
| 8703 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 8704 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8705 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8707 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8708 | GIR_RootConstrainSelectedInstOperands, |
| 8709 | // GIR_Coverage, 2868, |
| 8710 | GIR_EraseRootFromParent_Done, |
| 8711 | // Label 544: @23470 |
| 8712 | GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(23507), // Rule ID 2869 // |
| 8713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8714 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8715 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8716 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8717 | // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) |
| 8718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 8719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8720 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8722 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8723 | GIR_RootConstrainSelectedInstOperands, |
| 8724 | // GIR_Coverage, 2869, |
| 8725 | GIR_EraseRootFromParent_Done, |
| 8726 | // Label 545: @23507 |
| 8727 | GIM_Reject, |
| 8728 | // Label 483: @23508 |
| 8729 | GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(23540), // Rule ID 2746 // |
| 8730 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8731 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 8732 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8733 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8734 | // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v2f64] }:$src |
| 8735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8736 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8737 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8738 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8739 | // GIR_Coverage, 2746, |
| 8740 | GIR_EraseRootFromParent_Done, |
| 8741 | // Label 546: @23540 |
| 8742 | GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(23572), // Rule ID 2747 // |
| 8743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8744 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 8745 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8746 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8747 | // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v2i64] }:$src |
| 8748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8749 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8750 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8751 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8752 | // GIR_Coverage, 2747, |
| 8753 | GIR_EraseRootFromParent_Done, |
| 8754 | // Label 547: @23572 |
| 8755 | GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(23604), // Rule ID 2800 // |
| 8756 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8757 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 8758 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8759 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8760 | // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2f64] }:$src |
| 8761 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8762 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8763 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8764 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8765 | // GIR_Coverage, 2800, |
| 8766 | GIR_EraseRootFromParent_Done, |
| 8767 | // Label 548: @23604 |
| 8768 | GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(23636), // Rule ID 2801 // |
| 8769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8770 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 8771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8772 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8773 | // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2f64] }:$src |
| 8774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8775 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8776 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8777 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8778 | // GIR_Coverage, 2801, |
| 8779 | GIR_EraseRootFromParent_Done, |
| 8780 | // Label 549: @23636 |
| 8781 | GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(23668), // Rule ID 2802 // |
| 8782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8783 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8785 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8786 | // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2f64] }:$src |
| 8787 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8788 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8789 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8790 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8791 | // GIR_Coverage, 2802, |
| 8792 | GIR_EraseRootFromParent_Done, |
| 8793 | // Label 550: @23668 |
| 8794 | GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(23700), // Rule ID 2803 // |
| 8795 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8796 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8798 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8799 | // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v2f64] }:$src |
| 8800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8801 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8802 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8803 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8804 | // GIR_Coverage, 2803, |
| 8805 | GIR_EraseRootFromParent_Done, |
| 8806 | // Label 551: @23700 |
| 8807 | GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(23732), // Rule ID 2804 // |
| 8808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8809 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8811 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8812 | // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2f64] }:$src |
| 8813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8814 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8815 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8816 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8817 | // GIR_Coverage, 2804, |
| 8818 | GIR_EraseRootFromParent_Done, |
| 8819 | // Label 552: @23732 |
| 8820 | GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(23764), // Rule ID 2805 // |
| 8821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8822 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 8823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8824 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8825 | // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2f64] }:$src |
| 8826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8827 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8828 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8829 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8830 | // GIR_Coverage, 2805, |
| 8831 | GIR_EraseRootFromParent_Done, |
| 8832 | // Label 553: @23764 |
| 8833 | GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(23796), // Rule ID 2806 // |
| 8834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8835 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 8836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8837 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8838 | // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2i64] }:$src |
| 8839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8840 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8841 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8842 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8843 | // GIR_Coverage, 2806, |
| 8844 | GIR_EraseRootFromParent_Done, |
| 8845 | // Label 554: @23796 |
| 8846 | GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(23828), // Rule ID 2807 // |
| 8847 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8848 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 8849 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8850 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8851 | // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2i64] }:$src |
| 8852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8853 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8854 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8855 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8856 | // GIR_Coverage, 2807, |
| 8857 | GIR_EraseRootFromParent_Done, |
| 8858 | // Label 555: @23828 |
| 8859 | GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(23860), // Rule ID 2808 // |
| 8860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8861 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8862 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8863 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8864 | // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2i64] }:$src |
| 8865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8866 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8867 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8868 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8869 | // GIR_Coverage, 2808, |
| 8870 | GIR_EraseRootFromParent_Done, |
| 8871 | // Label 556: @23860 |
| 8872 | GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(23892), // Rule ID 2809 // |
| 8873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8874 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8876 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8877 | // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v2i64] }:$src |
| 8878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8879 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8880 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8881 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8882 | // GIR_Coverage, 2809, |
| 8883 | GIR_EraseRootFromParent_Done, |
| 8884 | // Label 557: @23892 |
| 8885 | GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(23924), // Rule ID 2810 // |
| 8886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8887 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8888 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8889 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8890 | // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2i64] }:$src |
| 8891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8892 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8893 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8894 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8895 | // GIR_Coverage, 2810, |
| 8896 | GIR_EraseRootFromParent_Done, |
| 8897 | // Label 558: @23924 |
| 8898 | GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(23956), // Rule ID 2811 // |
| 8899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 8900 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 8901 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8902 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8903 | // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2i64] }:$src |
| 8904 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8905 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 8906 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8907 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 8908 | // GIR_Coverage, 2811, |
| 8909 | GIR_EraseRootFromParent_Done, |
| 8910 | // Label 559: @23956 |
| 8911 | GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(23993), // Rule ID 2892 // |
| 8912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8913 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 8914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8915 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8916 | // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) |
| 8917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 8918 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8919 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8921 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8922 | GIR_RootConstrainSelectedInstOperands, |
| 8923 | // GIR_Coverage, 2892, |
| 8924 | GIR_EraseRootFromParent_Done, |
| 8925 | // Label 560: @23993 |
| 8926 | GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(24030), // Rule ID 2893 // |
| 8927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8928 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 8929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8930 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8931 | // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) |
| 8932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 8933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8934 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8936 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8937 | GIR_RootConstrainSelectedInstOperands, |
| 8938 | // GIR_Coverage, 2893, |
| 8939 | GIR_EraseRootFromParent_Done, |
| 8940 | // Label 561: @24030 |
| 8941 | GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(24067), // Rule ID 2894 // |
| 8942 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8943 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8944 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8945 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8946 | // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) |
| 8947 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 8948 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8949 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8951 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8952 | GIR_RootConstrainSelectedInstOperands, |
| 8953 | // GIR_Coverage, 2894, |
| 8954 | GIR_EraseRootFromParent_Done, |
| 8955 | // Label 562: @24067 |
| 8956 | GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(24104), // Rule ID 2895 // |
| 8957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8958 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8959 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8960 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8961 | // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src) |
| 8962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 8963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8964 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8966 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8967 | GIR_RootConstrainSelectedInstOperands, |
| 8968 | // GIR_Coverage, 2895, |
| 8969 | GIR_EraseRootFromParent_Done, |
| 8970 | // Label 563: @24104 |
| 8971 | GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(24141), // Rule ID 2896 // |
| 8972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8973 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8974 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8975 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8976 | // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) |
| 8977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 8978 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8979 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8981 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8982 | GIR_RootConstrainSelectedInstOperands, |
| 8983 | // GIR_Coverage, 2896, |
| 8984 | GIR_EraseRootFromParent_Done, |
| 8985 | // Label 564: @24141 |
| 8986 | GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(24178), // Rule ID 2897 // |
| 8987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 8988 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 8989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8990 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8991 | // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) |
| 8992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 8993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8994 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8996 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8997 | GIR_RootConstrainSelectedInstOperands, |
| 8998 | // GIR_Coverage, 2897, |
| 8999 | GIR_EraseRootFromParent_Done, |
| 9000 | // Label 565: @24178 |
| 9001 | GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(24215), // Rule ID 2898 // |
| 9002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9003 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9005 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9006 | // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) |
| 9007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 9008 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9009 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9011 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9012 | GIR_RootConstrainSelectedInstOperands, |
| 9013 | // GIR_Coverage, 2898, |
| 9014 | GIR_EraseRootFromParent_Done, |
| 9015 | // Label 566: @24215 |
| 9016 | GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(24252), // Rule ID 2899 // |
| 9017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9018 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9019 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9020 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9021 | // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) |
| 9022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 9023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9024 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9026 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9027 | GIR_RootConstrainSelectedInstOperands, |
| 9028 | // GIR_Coverage, 2899, |
| 9029 | GIR_EraseRootFromParent_Done, |
| 9030 | // Label 567: @24252 |
| 9031 | GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(24289), // Rule ID 2900 // |
| 9032 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9033 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9035 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9036 | // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) |
| 9037 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 9038 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9039 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9041 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9042 | GIR_RootConstrainSelectedInstOperands, |
| 9043 | // GIR_Coverage, 2900, |
| 9044 | GIR_EraseRootFromParent_Done, |
| 9045 | // Label 568: @24289 |
| 9046 | GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(24326), // Rule ID 2901 // |
| 9047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9048 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9049 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9050 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9051 | // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src) |
| 9052 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 9053 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9054 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9056 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9057 | GIR_RootConstrainSelectedInstOperands, |
| 9058 | // GIR_Coverage, 2901, |
| 9059 | GIR_EraseRootFromParent_Done, |
| 9060 | // Label 569: @24326 |
| 9061 | GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(24363), // Rule ID 2902 // |
| 9062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9063 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9065 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9066 | // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) |
| 9067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 9068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9069 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9071 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9072 | GIR_RootConstrainSelectedInstOperands, |
| 9073 | // GIR_Coverage, 2902, |
| 9074 | GIR_EraseRootFromParent_Done, |
| 9075 | // Label 570: @24363 |
| 9076 | GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(24400), // Rule ID 2903 // |
| 9077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9078 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9079 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9080 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9081 | // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) |
| 9082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 9083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9084 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9086 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9087 | GIR_RootConstrainSelectedInstOperands, |
| 9088 | // GIR_Coverage, 2903, |
| 9089 | GIR_EraseRootFromParent_Done, |
| 9090 | // Label 571: @24400 |
| 9091 | GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(24432), // Rule ID 5400 // |
| 9092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9093 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 9094 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9095 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9096 | // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 9097 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9098 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9099 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9100 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 9101 | // GIR_Coverage, 5400, |
| 9102 | GIR_EraseRootFromParent_Done, |
| 9103 | // Label 572: @24432 |
| 9104 | GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(24464), // Rule ID 5401 // |
| 9105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9106 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 9107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9108 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9109 | // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 9110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9111 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9112 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9113 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 9114 | // GIR_Coverage, 5401, |
| 9115 | GIR_EraseRootFromParent_Done, |
| 9116 | // Label 573: @24464 |
| 9117 | GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(24496), // Rule ID 5406 // |
| 9118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 9119 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9121 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9122 | // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 9123 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9124 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9125 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9126 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 9127 | // GIR_Coverage, 5406, |
| 9128 | GIR_EraseRootFromParent_Done, |
| 9129 | // Label 574: @24496 |
| 9130 | GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(24528), // Rule ID 5407 // |
| 9131 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 9132 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9133 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9134 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9135 | // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 9136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9137 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9138 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9139 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 9140 | // GIR_Coverage, 5407, |
| 9141 | GIR_EraseRootFromParent_Done, |
| 9142 | // Label 575: @24528 |
| 9143 | GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(24560), // Rule ID 5408 // |
| 9144 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 9145 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9147 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9148 | // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 9149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9150 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9151 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9152 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 9153 | // GIR_Coverage, 5408, |
| 9154 | GIR_EraseRootFromParent_Done, |
| 9155 | // Label 576: @24560 |
| 9156 | GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(24592), // Rule ID 5409 // |
| 9157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 9158 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9160 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9161 | // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 9162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9163 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9164 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9165 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 9166 | // GIR_Coverage, 5409, |
| 9167 | GIR_EraseRootFromParent_Done, |
| 9168 | // Label 577: @24592 |
| 9169 | GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(24624), // Rule ID 5410 // |
| 9170 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 9171 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9173 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9174 | // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 9175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9176 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9177 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9178 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 9179 | // GIR_Coverage, 5410, |
| 9180 | GIR_EraseRootFromParent_Done, |
| 9181 | // Label 578: @24624 |
| 9182 | GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(24656), // Rule ID 5411 // |
| 9183 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 9184 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9185 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9186 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9187 | // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 9188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9189 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9190 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9191 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 9192 | // GIR_Coverage, 5411, |
| 9193 | GIR_EraseRootFromParent_Done, |
| 9194 | // Label 579: @24656 |
| 9195 | GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(24688), // Rule ID 5412 // |
| 9196 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 9197 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9198 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9199 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9200 | // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 9201 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9202 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9203 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9204 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 9205 | // GIR_Coverage, 5412, |
| 9206 | GIR_EraseRootFromParent_Done, |
| 9207 | // Label 580: @24688 |
| 9208 | GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(24720), // Rule ID 5413 // |
| 9209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 9210 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9211 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9212 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9213 | // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 9214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9215 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9216 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9217 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 9218 | // GIR_Coverage, 5413, |
| 9219 | GIR_EraseRootFromParent_Done, |
| 9220 | // Label 581: @24720 |
| 9221 | GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(24752), // Rule ID 5414 // |
| 9222 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 9223 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9225 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9226 | // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 9227 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9228 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9229 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9230 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 9231 | // GIR_Coverage, 5414, |
| 9232 | GIR_EraseRootFromParent_Done, |
| 9233 | // Label 582: @24752 |
| 9234 | GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(24784), // Rule ID 5415 // |
| 9235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 9236 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9237 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9238 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9239 | // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 9240 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9241 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9242 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9243 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 9244 | // GIR_Coverage, 5415, |
| 9245 | GIR_EraseRootFromParent_Done, |
| 9246 | // Label 583: @24784 |
| 9247 | GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(24840), // Rule ID 5442 // |
| 9248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 9249 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9250 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9251 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9252 | // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) |
| 9253 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9254 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9255 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 9256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 9257 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9258 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9260 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9261 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9262 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9263 | GIR_RootConstrainSelectedInstOperands, |
| 9264 | // GIR_Coverage, 5442, |
| 9265 | GIR_EraseRootFromParent_Done, |
| 9266 | // Label 584: @24840 |
| 9267 | GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(24896), // Rule ID 5443 // |
| 9268 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 9269 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9270 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9271 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9272 | // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) |
| 9273 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9274 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9275 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 9276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 9277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9278 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9280 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9281 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9282 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9283 | GIR_RootConstrainSelectedInstOperands, |
| 9284 | // GIR_Coverage, 5443, |
| 9285 | GIR_EraseRootFromParent_Done, |
| 9286 | // Label 585: @24896 |
| 9287 | GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(24952), // Rule ID 5444 // |
| 9288 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 9289 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9290 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9291 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9292 | // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) |
| 9293 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9294 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9295 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 9296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 9297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9298 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9300 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9301 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9302 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9303 | GIR_RootConstrainSelectedInstOperands, |
| 9304 | // GIR_Coverage, 5444, |
| 9305 | GIR_EraseRootFromParent_Done, |
| 9306 | // Label 586: @24952 |
| 9307 | GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(25008), // Rule ID 5445 // |
| 9308 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 9309 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9310 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9311 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9312 | // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) |
| 9313 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9314 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9315 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 9316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 9317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9318 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9320 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9321 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9322 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9323 | GIR_RootConstrainSelectedInstOperands, |
| 9324 | // GIR_Coverage, 5445, |
| 9325 | GIR_EraseRootFromParent_Done, |
| 9326 | // Label 587: @25008 |
| 9327 | GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(25064), // Rule ID 5446 // |
| 9328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 9329 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9330 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9331 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9332 | // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) |
| 9333 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9334 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9335 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 9336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 9337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9338 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9340 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9341 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9342 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9343 | GIR_RootConstrainSelectedInstOperands, |
| 9344 | // GIR_Coverage, 5446, |
| 9345 | GIR_EraseRootFromParent_Done, |
| 9346 | // Label 588: @25064 |
| 9347 | GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(25120), // Rule ID 5447 // |
| 9348 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 9349 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9350 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9351 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9352 | // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) |
| 9353 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9354 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9355 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 9356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 9357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9358 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9360 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9361 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9362 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9363 | GIR_RootConstrainSelectedInstOperands, |
| 9364 | // GIR_Coverage, 5447, |
| 9365 | GIR_EraseRootFromParent_Done, |
| 9366 | // Label 589: @25120 |
| 9367 | GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(25176), // Rule ID 5448 // |
| 9368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 9369 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9370 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9371 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9372 | // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) |
| 9373 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9374 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9375 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 9376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 9377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9378 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9380 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9381 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9382 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9383 | GIR_RootConstrainSelectedInstOperands, |
| 9384 | // GIR_Coverage, 5448, |
| 9385 | GIR_EraseRootFromParent_Done, |
| 9386 | // Label 590: @25176 |
| 9387 | GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(25232), // Rule ID 5449 // |
| 9388 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 9389 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9390 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9391 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9392 | // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) |
| 9393 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9394 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9395 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 9396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 9397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9398 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9400 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9401 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9402 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9403 | GIR_RootConstrainSelectedInstOperands, |
| 9404 | // GIR_Coverage, 5449, |
| 9405 | GIR_EraseRootFromParent_Done, |
| 9406 | // Label 591: @25232 |
| 9407 | GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(25288), // Rule ID 5450 // |
| 9408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 9409 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9410 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9411 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9412 | // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) |
| 9413 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9414 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9415 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 9416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 9417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9418 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9420 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9421 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9422 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9423 | GIR_RootConstrainSelectedInstOperands, |
| 9424 | // GIR_Coverage, 5450, |
| 9425 | GIR_EraseRootFromParent_Done, |
| 9426 | // Label 592: @25288 |
| 9427 | GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(25344), // Rule ID 5451 // |
| 9428 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 9429 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9430 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9431 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9432 | // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) |
| 9433 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9434 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9435 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 9436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 9437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9438 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9440 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9441 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9442 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9443 | GIR_RootConstrainSelectedInstOperands, |
| 9444 | // GIR_Coverage, 5451, |
| 9445 | GIR_EraseRootFromParent_Done, |
| 9446 | // Label 593: @25344 |
| 9447 | GIM_Reject, |
| 9448 | // Label 484: @25345 |
| 9449 | GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(25377), // Rule ID 2742 // |
| 9450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9451 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9452 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9453 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9454 | // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v4i16] }:$src |
| 9455 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9456 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9457 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9458 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9459 | // GIR_Coverage, 2742, |
| 9460 | GIR_EraseRootFromParent_Done, |
| 9461 | // Label 594: @25377 |
| 9462 | GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(25409), // Rule ID 2743 // |
| 9463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9464 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9465 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9466 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9467 | // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4f16] }:$src |
| 9468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9469 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9470 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9471 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9472 | // GIR_Coverage, 2743, |
| 9473 | GIR_EraseRootFromParent_Done, |
| 9474 | // Label 595: @25409 |
| 9475 | GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(25441), // Rule ID 2744 // |
| 9476 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9477 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9478 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9479 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9480 | // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v4i16] }:$src |
| 9481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9482 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9483 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9484 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9485 | // GIR_Coverage, 2744, |
| 9486 | GIR_EraseRootFromParent_Done, |
| 9487 | // Label 596: @25441 |
| 9488 | GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(25473), // Rule ID 2745 // |
| 9489 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9490 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9491 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9492 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9493 | // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4bf16] }:$src |
| 9494 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9495 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9496 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9497 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9498 | // GIR_Coverage, 2745, |
| 9499 | GIR_EraseRootFromParent_Done, |
| 9500 | // Label 597: @25473 |
| 9501 | GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(25505), // Rule ID 2778 // |
| 9502 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9503 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9504 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9505 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9506 | // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4f16] }:$src |
| 9507 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9508 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9509 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9510 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9511 | // GIR_Coverage, 2778, |
| 9512 | GIR_EraseRootFromParent_Done, |
| 9513 | // Label 598: @25505 |
| 9514 | GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(25537), // Rule ID 2779 // |
| 9515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9516 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9517 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9518 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9519 | // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4f16] }:$src |
| 9520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9521 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9522 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9523 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9524 | // GIR_Coverage, 2779, |
| 9525 | GIR_EraseRootFromParent_Done, |
| 9526 | // Label 599: @25537 |
| 9527 | GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(25569), // Rule ID 2780 // |
| 9528 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9529 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9531 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9532 | // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4f16] }:$src |
| 9533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9534 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9535 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9536 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9537 | // GIR_Coverage, 2780, |
| 9538 | GIR_EraseRootFromParent_Done, |
| 9539 | // Label 600: @25569 |
| 9540 | GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(25601), // Rule ID 2781 // |
| 9541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9542 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9544 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9545 | // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4f16] }:$src |
| 9546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9547 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9548 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9549 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9550 | // GIR_Coverage, 2781, |
| 9551 | GIR_EraseRootFromParent_Done, |
| 9552 | // Label 601: @25601 |
| 9553 | GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(25633), // Rule ID 2782 // |
| 9554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9555 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9556 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9557 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9558 | // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4f16] }:$src |
| 9559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9560 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9561 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9562 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9563 | // GIR_Coverage, 2782, |
| 9564 | GIR_EraseRootFromParent_Done, |
| 9565 | // Label 602: @25633 |
| 9566 | GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(25665), // Rule ID 2783 // |
| 9567 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9568 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9569 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9570 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9571 | // (bitconvert:{ *:[v4bf16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4bf16] }:$src |
| 9572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9573 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9574 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9575 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9576 | // GIR_Coverage, 2783, |
| 9577 | GIR_EraseRootFromParent_Done, |
| 9578 | // Label 603: @25665 |
| 9579 | GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(25697), // Rule ID 2784 // |
| 9580 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9581 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9582 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9583 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9584 | // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4bf16] }:$src |
| 9585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9586 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9587 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9588 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9589 | // GIR_Coverage, 2784, |
| 9590 | GIR_EraseRootFromParent_Done, |
| 9591 | // Label 604: @25697 |
| 9592 | GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(25729), // Rule ID 2785 // |
| 9593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9594 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9596 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9597 | // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4bf16] }:$src |
| 9598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9599 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9600 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9601 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9602 | // GIR_Coverage, 2785, |
| 9603 | GIR_EraseRootFromParent_Done, |
| 9604 | // Label 605: @25729 |
| 9605 | GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(25761), // Rule ID 2786 // |
| 9606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9607 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9608 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9609 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9610 | // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4bf16] }:$src |
| 9611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9612 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9613 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9614 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9615 | // GIR_Coverage, 2786, |
| 9616 | GIR_EraseRootFromParent_Done, |
| 9617 | // Label 606: @25761 |
| 9618 | GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(25793), // Rule ID 2787 // |
| 9619 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9620 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9621 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9622 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9623 | // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4bf16] }:$src |
| 9624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9625 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9626 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9627 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9628 | // GIR_Coverage, 2787, |
| 9629 | GIR_EraseRootFromParent_Done, |
| 9630 | // Label 607: @25793 |
| 9631 | GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(25825), // Rule ID 2788 // |
| 9632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9633 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9635 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9636 | // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4i16] }:$src |
| 9637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9638 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9639 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9640 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9641 | // GIR_Coverage, 2788, |
| 9642 | GIR_EraseRootFromParent_Done, |
| 9643 | // Label 608: @25825 |
| 9644 | GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(25857), // Rule ID 2789 // |
| 9645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9646 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9647 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9648 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9649 | // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4i16] }:$src |
| 9650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9651 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9652 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9653 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9654 | // GIR_Coverage, 2789, |
| 9655 | GIR_EraseRootFromParent_Done, |
| 9656 | // Label 609: @25857 |
| 9657 | GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(25889), // Rule ID 2790 // |
| 9658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9659 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9660 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9661 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9662 | // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4i16] }:$src |
| 9663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9664 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9665 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9666 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9667 | // GIR_Coverage, 2790, |
| 9668 | GIR_EraseRootFromParent_Done, |
| 9669 | // Label 610: @25889 |
| 9670 | GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(25921), // Rule ID 2791 // |
| 9671 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9672 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9673 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9674 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9675 | // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4i16] }:$src |
| 9676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9677 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9678 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9679 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9680 | // GIR_Coverage, 2791, |
| 9681 | GIR_EraseRootFromParent_Done, |
| 9682 | // Label 611: @25921 |
| 9683 | GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(25953), // Rule ID 2792 // |
| 9684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9685 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9686 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9687 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9688 | // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4i16] }:$src |
| 9689 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9690 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9691 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9692 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9693 | // GIR_Coverage, 2792, |
| 9694 | GIR_EraseRootFromParent_Done, |
| 9695 | // Label 612: @25953 |
| 9696 | GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(25990), // Rule ID 2870 // |
| 9697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9698 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9699 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9700 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9701 | // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src) |
| 9702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 9703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9704 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9706 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9707 | GIR_RootConstrainSelectedInstOperands, |
| 9708 | // GIR_Coverage, 2870, |
| 9709 | GIR_EraseRootFromParent_Done, |
| 9710 | // Label 613: @25990 |
| 9711 | GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(26027), // Rule ID 2871 // |
| 9712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9713 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9714 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9715 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9716 | // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) |
| 9717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 9718 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9719 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9721 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9722 | GIR_RootConstrainSelectedInstOperands, |
| 9723 | // GIR_Coverage, 2871, |
| 9724 | GIR_EraseRootFromParent_Done, |
| 9725 | // Label 614: @26027 |
| 9726 | GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(26064), // Rule ID 2872 // |
| 9727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9728 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9729 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9730 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9731 | // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) |
| 9732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 9733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9734 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9736 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9737 | GIR_RootConstrainSelectedInstOperands, |
| 9738 | // GIR_Coverage, 2872, |
| 9739 | GIR_EraseRootFromParent_Done, |
| 9740 | // Label 615: @26064 |
| 9741 | GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(26101), // Rule ID 2873 // |
| 9742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9743 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9744 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9745 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9746 | // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) |
| 9747 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 9748 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9749 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9751 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9752 | GIR_RootConstrainSelectedInstOperands, |
| 9753 | // GIR_Coverage, 2873, |
| 9754 | GIR_EraseRootFromParent_Done, |
| 9755 | // Label 616: @26101 |
| 9756 | GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(26138), // Rule ID 2874 // |
| 9757 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9758 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9759 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9760 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9761 | // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) |
| 9762 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 9763 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9764 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9766 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9767 | GIR_RootConstrainSelectedInstOperands, |
| 9768 | // GIR_Coverage, 2874, |
| 9769 | GIR_EraseRootFromParent_Done, |
| 9770 | // Label 617: @26138 |
| 9771 | GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(26175), // Rule ID 2875 // |
| 9772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9773 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9774 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9775 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9776 | // (bitconvert:{ *:[v4bf16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4bf16] } DPR:{ *:[f64] }:$src) |
| 9777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 9778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9779 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9781 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9782 | GIR_RootConstrainSelectedInstOperands, |
| 9783 | // GIR_Coverage, 2875, |
| 9784 | GIR_EraseRootFromParent_Done, |
| 9785 | // Label 618: @26175 |
| 9786 | GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(26212), // Rule ID 2876 // |
| 9787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9788 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9789 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9790 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9791 | // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src) |
| 9792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 9793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9794 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9796 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9797 | GIR_RootConstrainSelectedInstOperands, |
| 9798 | // GIR_Coverage, 2876, |
| 9799 | GIR_EraseRootFromParent_Done, |
| 9800 | // Label 619: @26212 |
| 9801 | GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(26249), // Rule ID 2877 // |
| 9802 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9803 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9805 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9806 | // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src) |
| 9807 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 9808 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9809 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9811 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9812 | GIR_RootConstrainSelectedInstOperands, |
| 9813 | // GIR_Coverage, 2877, |
| 9814 | GIR_EraseRootFromParent_Done, |
| 9815 | // Label 620: @26249 |
| 9816 | GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(26286), // Rule ID 2878 // |
| 9817 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9818 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9819 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9820 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9821 | // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src) |
| 9822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 9823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9824 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9826 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9827 | GIR_RootConstrainSelectedInstOperands, |
| 9828 | // GIR_Coverage, 2878, |
| 9829 | GIR_EraseRootFromParent_Done, |
| 9830 | // Label 621: @26286 |
| 9831 | GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(26323), // Rule ID 2879 // |
| 9832 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9833 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9834 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9835 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9836 | // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src) |
| 9837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 9838 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9839 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9841 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9842 | GIR_RootConstrainSelectedInstOperands, |
| 9843 | // GIR_Coverage, 2879, |
| 9844 | GIR_EraseRootFromParent_Done, |
| 9845 | // Label 622: @26323 |
| 9846 | GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(26360), // Rule ID 2880 // |
| 9847 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9848 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9849 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9850 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9851 | // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src) |
| 9852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 9853 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9854 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9856 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9857 | GIR_RootConstrainSelectedInstOperands, |
| 9858 | // GIR_Coverage, 2880, |
| 9859 | GIR_EraseRootFromParent_Done, |
| 9860 | // Label 623: @26360 |
| 9861 | GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(26397), // Rule ID 2881 // |
| 9862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9863 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9864 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9865 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9866 | // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) |
| 9867 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 9868 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9869 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9871 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9872 | GIR_RootConstrainSelectedInstOperands, |
| 9873 | // GIR_Coverage, 2881, |
| 9874 | GIR_EraseRootFromParent_Done, |
| 9875 | // Label 624: @26397 |
| 9876 | GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(26434), // Rule ID 2882 // |
| 9877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9878 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9879 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9880 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9881 | // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) |
| 9882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 9883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9884 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9886 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9887 | GIR_RootConstrainSelectedInstOperands, |
| 9888 | // GIR_Coverage, 2882, |
| 9889 | GIR_EraseRootFromParent_Done, |
| 9890 | // Label 625: @26434 |
| 9891 | GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(26471), // Rule ID 2883 // |
| 9892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9893 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9895 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9896 | // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) |
| 9897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 9898 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9899 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9901 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9902 | GIR_RootConstrainSelectedInstOperands, |
| 9903 | // GIR_Coverage, 2883, |
| 9904 | GIR_EraseRootFromParent_Done, |
| 9905 | // Label 626: @26471 |
| 9906 | GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(26508), // Rule ID 2884 // |
| 9907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9908 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9910 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9911 | // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) |
| 9912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 9913 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9914 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9916 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9917 | GIR_RootConstrainSelectedInstOperands, |
| 9918 | // GIR_Coverage, 2884, |
| 9919 | GIR_EraseRootFromParent_Done, |
| 9920 | // Label 627: @26508 |
| 9921 | GIM_Reject, |
| 9922 | // Label 485: @26509 |
| 9923 | GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(26541), // Rule ID 2748 // |
| 9924 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9925 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9927 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9928 | // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v4i32] }:$src |
| 9929 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9930 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9931 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9932 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 9933 | // GIR_Coverage, 2748, |
| 9934 | GIR_EraseRootFromParent_Done, |
| 9935 | // Label 628: @26541 |
| 9936 | GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(26573), // Rule ID 2749 // |
| 9937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9938 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9939 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9940 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9941 | // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v4f32] }:$src |
| 9942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9943 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9944 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9945 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 9946 | // GIR_Coverage, 2749, |
| 9947 | GIR_EraseRootFromParent_Done, |
| 9948 | // Label 629: @26573 |
| 9949 | GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(26605), // Rule ID 2812 // |
| 9950 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9951 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 9952 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9953 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9954 | // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4f32] }:$src |
| 9955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9956 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9957 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9958 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 9959 | // GIR_Coverage, 2812, |
| 9960 | GIR_EraseRootFromParent_Done, |
| 9961 | // Label 630: @26605 |
| 9962 | GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(26637), // Rule ID 2813 // |
| 9963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9964 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 9965 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9966 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9967 | // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4f32] }:$src |
| 9968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9969 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9970 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9971 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 9972 | // GIR_Coverage, 2813, |
| 9973 | GIR_EraseRootFromParent_Done, |
| 9974 | // Label 631: @26637 |
| 9975 | GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(26669), // Rule ID 2814 // |
| 9976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9977 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9979 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9980 | // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4f32] }:$src |
| 9981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9982 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9983 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9984 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 9985 | // GIR_Coverage, 2814, |
| 9986 | GIR_EraseRootFromParent_Done, |
| 9987 | // Label 632: @26669 |
| 9988 | GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(26701), // Rule ID 2815 // |
| 9989 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9990 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9991 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9992 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9993 | // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v4f32] }:$src |
| 9994 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9995 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9996 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9997 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 9998 | // GIR_Coverage, 2815, |
| 9999 | GIR_EraseRootFromParent_Done, |
| 10000 | // Label 633: @26701 |
| 10001 | GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(26733), // Rule ID 2816 // |
| 10002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10003 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10005 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10006 | // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4f32] }:$src |
| 10007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10008 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10009 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10010 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10011 | // GIR_Coverage, 2816, |
| 10012 | GIR_EraseRootFromParent_Done, |
| 10013 | // Label 634: @26733 |
| 10014 | GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(26765), // Rule ID 2817 // |
| 10015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10016 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10018 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10019 | // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4f32] }:$src |
| 10020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10021 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10022 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10023 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10024 | // GIR_Coverage, 2817, |
| 10025 | GIR_EraseRootFromParent_Done, |
| 10026 | // Label 635: @26765 |
| 10027 | GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(26797), // Rule ID 2818 // |
| 10028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10029 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10031 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10032 | // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4i32] }:$src |
| 10033 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10034 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10035 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10036 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10037 | // GIR_Coverage, 2818, |
| 10038 | GIR_EraseRootFromParent_Done, |
| 10039 | // Label 636: @26797 |
| 10040 | GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(26829), // Rule ID 2819 // |
| 10041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10042 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10044 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10045 | // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4i32] }:$src |
| 10046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10047 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10048 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10049 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10050 | // GIR_Coverage, 2819, |
| 10051 | GIR_EraseRootFromParent_Done, |
| 10052 | // Label 637: @26829 |
| 10053 | GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(26861), // Rule ID 2820 // |
| 10054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10055 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10057 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10058 | // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4i32] }:$src |
| 10059 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10060 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10061 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10062 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10063 | // GIR_Coverage, 2820, |
| 10064 | GIR_EraseRootFromParent_Done, |
| 10065 | // Label 638: @26861 |
| 10066 | GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(26893), // Rule ID 2821 // |
| 10067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10068 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10069 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10070 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10071 | // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v4i32] }:$src |
| 10072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10073 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10074 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10075 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10076 | // GIR_Coverage, 2821, |
| 10077 | GIR_EraseRootFromParent_Done, |
| 10078 | // Label 639: @26893 |
| 10079 | GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(26925), // Rule ID 2822 // |
| 10080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10081 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10083 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10084 | // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4i32] }:$src |
| 10085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10086 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10087 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10088 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10089 | // GIR_Coverage, 2822, |
| 10090 | GIR_EraseRootFromParent_Done, |
| 10091 | // Label 640: @26925 |
| 10092 | GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(26957), // Rule ID 2823 // |
| 10093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10094 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10095 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10096 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10097 | // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4i32] }:$src |
| 10098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10099 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10100 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10101 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10102 | // GIR_Coverage, 2823, |
| 10103 | GIR_EraseRootFromParent_Done, |
| 10104 | // Label 641: @26957 |
| 10105 | GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(26994), // Rule ID 2904 // |
| 10106 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10107 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10109 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10110 | // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) |
| 10111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 10112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10113 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10115 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10116 | GIR_RootConstrainSelectedInstOperands, |
| 10117 | // GIR_Coverage, 2904, |
| 10118 | GIR_EraseRootFromParent_Done, |
| 10119 | // Label 642: @26994 |
| 10120 | GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(27031), // Rule ID 2905 // |
| 10121 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10122 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10123 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10124 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10125 | // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) |
| 10126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 10127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10128 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10130 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10131 | GIR_RootConstrainSelectedInstOperands, |
| 10132 | // GIR_Coverage, 2905, |
| 10133 | GIR_EraseRootFromParent_Done, |
| 10134 | // Label 643: @27031 |
| 10135 | GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(27068), // Rule ID 2906 // |
| 10136 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10137 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10139 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10140 | // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) |
| 10141 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 10142 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10143 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10145 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10146 | GIR_RootConstrainSelectedInstOperands, |
| 10147 | // GIR_Coverage, 2906, |
| 10148 | GIR_EraseRootFromParent_Done, |
| 10149 | // Label 644: @27068 |
| 10150 | GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(27105), // Rule ID 2907 // |
| 10151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10152 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10154 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10155 | // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src) |
| 10156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 10157 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10158 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10160 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10161 | GIR_RootConstrainSelectedInstOperands, |
| 10162 | // GIR_Coverage, 2907, |
| 10163 | GIR_EraseRootFromParent_Done, |
| 10164 | // Label 645: @27105 |
| 10165 | GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(27142), // Rule ID 2908 // |
| 10166 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10167 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10168 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10169 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10170 | // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) |
| 10171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 10172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10173 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10175 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10176 | GIR_RootConstrainSelectedInstOperands, |
| 10177 | // GIR_Coverage, 2908, |
| 10178 | GIR_EraseRootFromParent_Done, |
| 10179 | // Label 646: @27142 |
| 10180 | GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(27179), // Rule ID 2909 // |
| 10181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10182 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10183 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10184 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10185 | // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) |
| 10186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 10187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10188 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10190 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10191 | GIR_RootConstrainSelectedInstOperands, |
| 10192 | // GIR_Coverage, 2909, |
| 10193 | GIR_EraseRootFromParent_Done, |
| 10194 | // Label 647: @27179 |
| 10195 | GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(27216), // Rule ID 2910 // |
| 10196 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10197 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10198 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10199 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10200 | // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) |
| 10201 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 10202 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10203 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10205 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10206 | GIR_RootConstrainSelectedInstOperands, |
| 10207 | // GIR_Coverage, 2910, |
| 10208 | GIR_EraseRootFromParent_Done, |
| 10209 | // Label 648: @27216 |
| 10210 | GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(27253), // Rule ID 2911 // |
| 10211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10212 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10213 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10214 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10215 | // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) |
| 10216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 10217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10218 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10220 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10221 | GIR_RootConstrainSelectedInstOperands, |
| 10222 | // GIR_Coverage, 2911, |
| 10223 | GIR_EraseRootFromParent_Done, |
| 10224 | // Label 649: @27253 |
| 10225 | GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(27290), // Rule ID 2912 // |
| 10226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10227 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10228 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10229 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10230 | // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) |
| 10231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 10232 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10233 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10235 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10236 | GIR_RootConstrainSelectedInstOperands, |
| 10237 | // GIR_Coverage, 2912, |
| 10238 | GIR_EraseRootFromParent_Done, |
| 10239 | // Label 650: @27290 |
| 10240 | GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(27327), // Rule ID 2913 // |
| 10241 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10242 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10244 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10245 | // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src) |
| 10246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 10247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10248 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10250 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10251 | GIR_RootConstrainSelectedInstOperands, |
| 10252 | // GIR_Coverage, 2913, |
| 10253 | GIR_EraseRootFromParent_Done, |
| 10254 | // Label 651: @27327 |
| 10255 | GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(27364), // Rule ID 2914 // |
| 10256 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10257 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10259 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10260 | // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) |
| 10261 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 10262 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10263 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10265 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10266 | GIR_RootConstrainSelectedInstOperands, |
| 10267 | // GIR_Coverage, 2914, |
| 10268 | GIR_EraseRootFromParent_Done, |
| 10269 | // Label 652: @27364 |
| 10270 | GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(27401), // Rule ID 2915 // |
| 10271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10272 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10273 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10274 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10275 | // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) |
| 10276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 10277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10278 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10280 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10281 | GIR_RootConstrainSelectedInstOperands, |
| 10282 | // GIR_Coverage, 2915, |
| 10283 | GIR_EraseRootFromParent_Done, |
| 10284 | // Label 653: @27401 |
| 10285 | GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(27433), // Rule ID 5402 // |
| 10286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10287 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10288 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10289 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10290 | // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 10291 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10292 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10293 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10294 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10295 | // GIR_Coverage, 5402, |
| 10296 | GIR_EraseRootFromParent_Done, |
| 10297 | // Label 654: @27433 |
| 10298 | GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(27465), // Rule ID 5403 // |
| 10299 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10300 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10301 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10302 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10303 | // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 10304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10305 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10306 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10307 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10308 | // GIR_Coverage, 5403, |
| 10309 | GIR_EraseRootFromParent_Done, |
| 10310 | // Label 655: @27465 |
| 10311 | GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(27497), // Rule ID 5416 // |
| 10312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10313 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10314 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10315 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10316 | // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 10317 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10318 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10319 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10320 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10321 | // GIR_Coverage, 5416, |
| 10322 | GIR_EraseRootFromParent_Done, |
| 10323 | // Label 656: @27497 |
| 10324 | GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(27529), // Rule ID 5417 // |
| 10325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10326 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10327 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10328 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10329 | // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 10330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10331 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10332 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10333 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10334 | // GIR_Coverage, 5417, |
| 10335 | GIR_EraseRootFromParent_Done, |
| 10336 | // Label 657: @27529 |
| 10337 | GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(27561), // Rule ID 5418 // |
| 10338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10339 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10341 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10342 | // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 10343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10344 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10345 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10346 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10347 | // GIR_Coverage, 5418, |
| 10348 | GIR_EraseRootFromParent_Done, |
| 10349 | // Label 658: @27561 |
| 10350 | GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(27593), // Rule ID 5419 // |
| 10351 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10352 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10353 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10354 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10355 | // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 10356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10357 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10358 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10359 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10360 | // GIR_Coverage, 5419, |
| 10361 | GIR_EraseRootFromParent_Done, |
| 10362 | // Label 659: @27593 |
| 10363 | GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(27625), // Rule ID 5420 // |
| 10364 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10365 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10366 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10367 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10368 | // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 10369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10370 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10371 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10372 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10373 | // GIR_Coverage, 5420, |
| 10374 | GIR_EraseRootFromParent_Done, |
| 10375 | // Label 660: @27625 |
| 10376 | GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(27657), // Rule ID 5421 // |
| 10377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10378 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10379 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10380 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10381 | // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 10382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10383 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10384 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10385 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10386 | // GIR_Coverage, 5421, |
| 10387 | GIR_EraseRootFromParent_Done, |
| 10388 | // Label 661: @27657 |
| 10389 | GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(27689), // Rule ID 5422 // |
| 10390 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10391 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10392 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10393 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10394 | // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 10395 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10396 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10397 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10398 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10399 | // GIR_Coverage, 5422, |
| 10400 | GIR_EraseRootFromParent_Done, |
| 10401 | // Label 662: @27689 |
| 10402 | GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(27721), // Rule ID 5423 // |
| 10403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10404 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10406 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10407 | // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 10408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10409 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10410 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10411 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10412 | // GIR_Coverage, 5423, |
| 10413 | GIR_EraseRootFromParent_Done, |
| 10414 | // Label 663: @27721 |
| 10415 | GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(27753), // Rule ID 5424 // |
| 10416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10417 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10419 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10420 | // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 10421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10422 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10423 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10424 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10425 | // GIR_Coverage, 5424, |
| 10426 | GIR_EraseRootFromParent_Done, |
| 10427 | // Label 664: @27753 |
| 10428 | GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(27785), // Rule ID 5425 // |
| 10429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10430 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10431 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10432 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10433 | // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 10434 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10435 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10436 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10437 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10438 | // GIR_Coverage, 5425, |
| 10439 | GIR_EraseRootFromParent_Done, |
| 10440 | // Label 665: @27785 |
| 10441 | GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(27841), // Rule ID 5452 // |
| 10442 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10443 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10444 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10445 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10446 | // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) |
| 10447 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10448 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10449 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 10450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 10451 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10452 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10454 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10455 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10456 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10457 | GIR_RootConstrainSelectedInstOperands, |
| 10458 | // GIR_Coverage, 5452, |
| 10459 | GIR_EraseRootFromParent_Done, |
| 10460 | // Label 666: @27841 |
| 10461 | GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(27897), // Rule ID 5453 // |
| 10462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10463 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10464 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10465 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10466 | // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) |
| 10467 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10468 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10469 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 10470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 10471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10472 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10474 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10475 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10476 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10477 | GIR_RootConstrainSelectedInstOperands, |
| 10478 | // GIR_Coverage, 5453, |
| 10479 | GIR_EraseRootFromParent_Done, |
| 10480 | // Label 667: @27897 |
| 10481 | GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(27953), // Rule ID 5454 // |
| 10482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10483 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10485 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10486 | // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) |
| 10487 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10488 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10489 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 10490 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 10491 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10492 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10494 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10495 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10496 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10497 | GIR_RootConstrainSelectedInstOperands, |
| 10498 | // GIR_Coverage, 5454, |
| 10499 | GIR_EraseRootFromParent_Done, |
| 10500 | // Label 668: @27953 |
| 10501 | GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(28009), // Rule ID 5455 // |
| 10502 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10503 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10504 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10505 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10506 | // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) |
| 10507 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10508 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10509 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 10510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 10511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10512 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10514 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10515 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10516 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10517 | GIR_RootConstrainSelectedInstOperands, |
| 10518 | // GIR_Coverage, 5455, |
| 10519 | GIR_EraseRootFromParent_Done, |
| 10520 | // Label 669: @28009 |
| 10521 | GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(28065), // Rule ID 5456 // |
| 10522 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10523 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10525 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10526 | // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) |
| 10527 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10528 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10529 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 10530 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 10531 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10532 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10534 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10535 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10536 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10537 | GIR_RootConstrainSelectedInstOperands, |
| 10538 | // GIR_Coverage, 5456, |
| 10539 | GIR_EraseRootFromParent_Done, |
| 10540 | // Label 670: @28065 |
| 10541 | GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(28121), // Rule ID 5457 // |
| 10542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10543 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10544 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10545 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10546 | // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) |
| 10547 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10548 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10549 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 10550 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 10551 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10552 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10554 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10555 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10556 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10557 | GIR_RootConstrainSelectedInstOperands, |
| 10558 | // GIR_Coverage, 5457, |
| 10559 | GIR_EraseRootFromParent_Done, |
| 10560 | // Label 671: @28121 |
| 10561 | GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(28177), // Rule ID 5458 // |
| 10562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10563 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10565 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10566 | // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) |
| 10567 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10568 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10569 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 10570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 10571 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10572 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10574 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10575 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10576 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10577 | GIR_RootConstrainSelectedInstOperands, |
| 10578 | // GIR_Coverage, 5458, |
| 10579 | GIR_EraseRootFromParent_Done, |
| 10580 | // Label 672: @28177 |
| 10581 | GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(28233), // Rule ID 5459 // |
| 10582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10583 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10585 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10586 | // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) |
| 10587 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10588 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10589 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 10590 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 10591 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10592 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10594 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10595 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10596 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10597 | GIR_RootConstrainSelectedInstOperands, |
| 10598 | // GIR_Coverage, 5459, |
| 10599 | GIR_EraseRootFromParent_Done, |
| 10600 | // Label 673: @28233 |
| 10601 | GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(28289), // Rule ID 5460 // |
| 10602 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10603 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10604 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10605 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10606 | // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 10607 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10608 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10609 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 10610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 10611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10612 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10614 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10615 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10616 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10617 | GIR_RootConstrainSelectedInstOperands, |
| 10618 | // GIR_Coverage, 5460, |
| 10619 | GIR_EraseRootFromParent_Done, |
| 10620 | // Label 674: @28289 |
| 10621 | GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(28345), // Rule ID 5461 // |
| 10622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10623 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10624 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10625 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10626 | // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) |
| 10627 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10628 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10629 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 10630 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 10631 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10632 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10634 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10635 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10636 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10637 | GIR_RootConstrainSelectedInstOperands, |
| 10638 | // GIR_Coverage, 5461, |
| 10639 | GIR_EraseRootFromParent_Done, |
| 10640 | // Label 675: @28345 |
| 10641 | GIM_Reject, |
| 10642 | // Label 486: @28346 |
| 10643 | GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(28378), // Rule ID 2793 // |
| 10644 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10645 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10646 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10647 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10648 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v8i8] }:$src |
| 10649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10650 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10651 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10652 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10653 | // GIR_Coverage, 2793, |
| 10654 | GIR_EraseRootFromParent_Done, |
| 10655 | // Label 676: @28378 |
| 10656 | GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(28410), // Rule ID 2794 // |
| 10657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10658 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10659 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10660 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10661 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v8i8] }:$src |
| 10662 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10663 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10664 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10665 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10666 | // GIR_Coverage, 2794, |
| 10667 | GIR_EraseRootFromParent_Done, |
| 10668 | // Label 677: @28410 |
| 10669 | GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(28442), // Rule ID 2795 // |
| 10670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10671 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10672 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10673 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10674 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v8i8] }:$src |
| 10675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10676 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10677 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10678 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10679 | // GIR_Coverage, 2795, |
| 10680 | GIR_EraseRootFromParent_Done, |
| 10681 | // Label 678: @28442 |
| 10682 | GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(28474), // Rule ID 2796 // |
| 10683 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10684 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10686 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10687 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v8i8] }:$src |
| 10688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10689 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10690 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10691 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10692 | // GIR_Coverage, 2796, |
| 10693 | GIR_EraseRootFromParent_Done, |
| 10694 | // Label 679: @28474 |
| 10695 | GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(28506), // Rule ID 2797 // |
| 10696 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10697 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10698 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10699 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10700 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v8i8] }:$src |
| 10701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10702 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10703 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10704 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10705 | // GIR_Coverage, 2797, |
| 10706 | GIR_EraseRootFromParent_Done, |
| 10707 | // Label 680: @28506 |
| 10708 | GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(28538), // Rule ID 2798 // |
| 10709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10710 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10712 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10713 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v8i8] }:$src |
| 10714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10715 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10716 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10717 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10718 | // GIR_Coverage, 2798, |
| 10719 | GIR_EraseRootFromParent_Done, |
| 10720 | // Label 681: @28538 |
| 10721 | GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(28570), // Rule ID 2799 // |
| 10722 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10723 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10724 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10725 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10726 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v8i8] }:$src |
| 10727 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10728 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10729 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10730 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10731 | // GIR_Coverage, 2799, |
| 10732 | GIR_EraseRootFromParent_Done, |
| 10733 | // Label 682: @28570 |
| 10734 | GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(28607), // Rule ID 2885 // |
| 10735 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10736 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10737 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10738 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10739 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src) |
| 10740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 10741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10742 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10744 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10745 | GIR_RootConstrainSelectedInstOperands, |
| 10746 | // GIR_Coverage, 2885, |
| 10747 | GIR_EraseRootFromParent_Done, |
| 10748 | // Label 683: @28607 |
| 10749 | GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(28644), // Rule ID 2886 // |
| 10750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10751 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10753 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10754 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) |
| 10755 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 10756 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10757 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10759 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10760 | GIR_RootConstrainSelectedInstOperands, |
| 10761 | // GIR_Coverage, 2886, |
| 10762 | GIR_EraseRootFromParent_Done, |
| 10763 | // Label 684: @28644 |
| 10764 | GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(28681), // Rule ID 2887 // |
| 10765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10766 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10767 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10768 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10769 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) |
| 10770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 10771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10772 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10774 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10775 | GIR_RootConstrainSelectedInstOperands, |
| 10776 | // GIR_Coverage, 2887, |
| 10777 | GIR_EraseRootFromParent_Done, |
| 10778 | // Label 685: @28681 |
| 10779 | GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(28718), // Rule ID 2888 // |
| 10780 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10781 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10783 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10784 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) |
| 10785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 10786 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10787 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10789 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10790 | GIR_RootConstrainSelectedInstOperands, |
| 10791 | // GIR_Coverage, 2888, |
| 10792 | GIR_EraseRootFromParent_Done, |
| 10793 | // Label 686: @28718 |
| 10794 | GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(28755), // Rule ID 2889 // |
| 10795 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10796 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10798 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10799 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) |
| 10800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 10801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10802 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10804 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10805 | GIR_RootConstrainSelectedInstOperands, |
| 10806 | // GIR_Coverage, 2889, |
| 10807 | GIR_EraseRootFromParent_Done, |
| 10808 | // Label 687: @28755 |
| 10809 | GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(28792), // Rule ID 2890 // |
| 10810 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10811 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10812 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10813 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10814 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src) |
| 10815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 10816 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10817 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10819 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10820 | GIR_RootConstrainSelectedInstOperands, |
| 10821 | // GIR_Coverage, 2890, |
| 10822 | GIR_EraseRootFromParent_Done, |
| 10823 | // Label 688: @28792 |
| 10824 | GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(28829), // Rule ID 2891 // |
| 10825 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10826 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10827 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10828 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10829 | // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) |
| 10830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 10831 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10832 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10834 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10835 | GIR_RootConstrainSelectedInstOperands, |
| 10836 | // GIR_Coverage, 2891, |
| 10837 | GIR_EraseRootFromParent_Done, |
| 10838 | // Label 689: @28829 |
| 10839 | GIM_Reject, |
| 10840 | // Label 487: @28830 |
| 10841 | GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(28862), // Rule ID 2750 // |
| 10842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10843 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10844 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10845 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10846 | // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v8i16] }:$src |
| 10847 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10848 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10849 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10850 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10851 | // GIR_Coverage, 2750, |
| 10852 | GIR_EraseRootFromParent_Done, |
| 10853 | // Label 690: @28862 |
| 10854 | GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(28894), // Rule ID 2751 // |
| 10855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10856 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10857 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10858 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10859 | // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8f16] }:$src |
| 10860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10861 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10862 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10863 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10864 | // GIR_Coverage, 2751, |
| 10865 | GIR_EraseRootFromParent_Done, |
| 10866 | // Label 691: @28894 |
| 10867 | GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(28926), // Rule ID 2752 // |
| 10868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10869 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10870 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10871 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10872 | // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v8i16] }:$src |
| 10873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10874 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10875 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10876 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10877 | // GIR_Coverage, 2752, |
| 10878 | GIR_EraseRootFromParent_Done, |
| 10879 | // Label 692: @28926 |
| 10880 | GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(28958), // Rule ID 2753 // |
| 10881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10882 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10883 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10884 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10885 | // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8bf16] }:$src |
| 10886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10887 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10888 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10889 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10890 | // GIR_Coverage, 2753, |
| 10891 | GIR_EraseRootFromParent_Done, |
| 10892 | // Label 693: @28958 |
| 10893 | GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(28990), // Rule ID 2824 // |
| 10894 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10895 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10896 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10897 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10898 | // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8f16] }:$src |
| 10899 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10900 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10901 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10902 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10903 | // GIR_Coverage, 2824, |
| 10904 | GIR_EraseRootFromParent_Done, |
| 10905 | // Label 694: @28990 |
| 10906 | GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(29022), // Rule ID 2825 // |
| 10907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10908 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10910 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10911 | // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8f16] }:$src |
| 10912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10913 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10914 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10915 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10916 | // GIR_Coverage, 2825, |
| 10917 | GIR_EraseRootFromParent_Done, |
| 10918 | // Label 695: @29022 |
| 10919 | GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(29054), // Rule ID 2826 // |
| 10920 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10921 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10923 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10924 | // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8f16] }:$src |
| 10925 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10926 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10927 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10928 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10929 | // GIR_Coverage, 2826, |
| 10930 | GIR_EraseRootFromParent_Done, |
| 10931 | // Label 696: @29054 |
| 10932 | GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(29086), // Rule ID 2827 // |
| 10933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10934 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10936 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10937 | // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8f16] }:$src |
| 10938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10939 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10940 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10941 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10942 | // GIR_Coverage, 2827, |
| 10943 | GIR_EraseRootFromParent_Done, |
| 10944 | // Label 697: @29086 |
| 10945 | GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(29118), // Rule ID 2828 // |
| 10946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10947 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10948 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10949 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10950 | // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8f16] }:$src |
| 10951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10952 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10953 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10954 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10955 | // GIR_Coverage, 2828, |
| 10956 | GIR_EraseRootFromParent_Done, |
| 10957 | // Label 698: @29118 |
| 10958 | GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(29150), // Rule ID 2829 // |
| 10959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10960 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10961 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10962 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10963 | // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8bf16] }:$src |
| 10964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10965 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10966 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10967 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10968 | // GIR_Coverage, 2829, |
| 10969 | GIR_EraseRootFromParent_Done, |
| 10970 | // Label 699: @29150 |
| 10971 | GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(29182), // Rule ID 2830 // |
| 10972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10973 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10974 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10975 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10976 | // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8bf16] }:$src |
| 10977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10978 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10979 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10980 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10981 | // GIR_Coverage, 2830, |
| 10982 | GIR_EraseRootFromParent_Done, |
| 10983 | // Label 700: @29182 |
| 10984 | GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(29214), // Rule ID 2831 // |
| 10985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10986 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10987 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10988 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10989 | // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8bf16] }:$src |
| 10990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10991 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10992 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10993 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10994 | // GIR_Coverage, 2831, |
| 10995 | GIR_EraseRootFromParent_Done, |
| 10996 | // Label 701: @29214 |
| 10997 | GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(29246), // Rule ID 2832 // |
| 10998 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10999 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11000 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11001 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11002 | // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8bf16] }:$src |
| 11003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11004 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11005 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11006 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11007 | // GIR_Coverage, 2832, |
| 11008 | GIR_EraseRootFromParent_Done, |
| 11009 | // Label 702: @29246 |
| 11010 | GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(29278), // Rule ID 2833 // |
| 11011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11012 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11013 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11014 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11015 | // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8bf16] }:$src |
| 11016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11017 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11018 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11019 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11020 | // GIR_Coverage, 2833, |
| 11021 | GIR_EraseRootFromParent_Done, |
| 11022 | // Label 703: @29278 |
| 11023 | GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(29310), // Rule ID 2834 // |
| 11024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11025 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11027 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11028 | // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11030 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11031 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11032 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11033 | // GIR_Coverage, 2834, |
| 11034 | GIR_EraseRootFromParent_Done, |
| 11035 | // Label 704: @29310 |
| 11036 | GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(29342), // Rule ID 2835 // |
| 11037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11038 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11039 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11040 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11041 | // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11043 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11044 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11045 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11046 | // GIR_Coverage, 2835, |
| 11047 | GIR_EraseRootFromParent_Done, |
| 11048 | // Label 705: @29342 |
| 11049 | GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(29374), // Rule ID 2836 // |
| 11050 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11051 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11052 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11053 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11054 | // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11056 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11057 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11058 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11059 | // GIR_Coverage, 2836, |
| 11060 | GIR_EraseRootFromParent_Done, |
| 11061 | // Label 706: @29374 |
| 11062 | GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(29406), // Rule ID 2837 // |
| 11063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11064 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11065 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11066 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11067 | // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11069 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11070 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11071 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11072 | // GIR_Coverage, 2837, |
| 11073 | GIR_EraseRootFromParent_Done, |
| 11074 | // Label 707: @29406 |
| 11075 | GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(29438), // Rule ID 2838 // |
| 11076 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11077 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11078 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11079 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11080 | // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11081 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11082 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11083 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11084 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11085 | // GIR_Coverage, 2838, |
| 11086 | GIR_EraseRootFromParent_Done, |
| 11087 | // Label 708: @29438 |
| 11088 | GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(29475), // Rule ID 2916 // |
| 11089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11090 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11092 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11093 | // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) |
| 11094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 11095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11096 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11098 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11099 | GIR_RootConstrainSelectedInstOperands, |
| 11100 | // GIR_Coverage, 2916, |
| 11101 | GIR_EraseRootFromParent_Done, |
| 11102 | // Label 709: @29475 |
| 11103 | GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(29512), // Rule ID 2917 // |
| 11104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11105 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11107 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11108 | // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) |
| 11109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 11110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11111 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11113 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11114 | GIR_RootConstrainSelectedInstOperands, |
| 11115 | // GIR_Coverage, 2917, |
| 11116 | GIR_EraseRootFromParent_Done, |
| 11117 | // Label 710: @29512 |
| 11118 | GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(29549), // Rule ID 2918 // |
| 11119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11120 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11121 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11122 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11123 | // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) |
| 11124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11126 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11128 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11129 | GIR_RootConstrainSelectedInstOperands, |
| 11130 | // GIR_Coverage, 2918, |
| 11131 | GIR_EraseRootFromParent_Done, |
| 11132 | // Label 711: @29549 |
| 11133 | GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(29586), // Rule ID 2919 // |
| 11134 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11135 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11137 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11138 | // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) |
| 11139 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11140 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11141 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11143 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11144 | GIR_RootConstrainSelectedInstOperands, |
| 11145 | // GIR_Coverage, 2919, |
| 11146 | GIR_EraseRootFromParent_Done, |
| 11147 | // Label 712: @29586 |
| 11148 | GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(29623), // Rule ID 2920 // |
| 11149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11150 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11151 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11152 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11153 | // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) |
| 11154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11156 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11158 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11159 | GIR_RootConstrainSelectedInstOperands, |
| 11160 | // GIR_Coverage, 2920, |
| 11161 | GIR_EraseRootFromParent_Done, |
| 11162 | // Label 713: @29623 |
| 11163 | GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(29660), // Rule ID 2921 // |
| 11164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11165 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11167 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11168 | // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src) |
| 11169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 11170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11171 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11173 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11174 | GIR_RootConstrainSelectedInstOperands, |
| 11175 | // GIR_Coverage, 2921, |
| 11176 | GIR_EraseRootFromParent_Done, |
| 11177 | // Label 714: @29660 |
| 11178 | GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(29697), // Rule ID 2922 // |
| 11179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11180 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11181 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11182 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11183 | // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src) |
| 11184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 11185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11186 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11188 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11189 | GIR_RootConstrainSelectedInstOperands, |
| 11190 | // GIR_Coverage, 2922, |
| 11191 | GIR_EraseRootFromParent_Done, |
| 11192 | // Label 715: @29697 |
| 11193 | GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(29734), // Rule ID 2923 // |
| 11194 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11195 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11197 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11198 | // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src) |
| 11199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11200 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11201 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11203 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11204 | GIR_RootConstrainSelectedInstOperands, |
| 11205 | // GIR_Coverage, 2923, |
| 11206 | GIR_EraseRootFromParent_Done, |
| 11207 | // Label 716: @29734 |
| 11208 | GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(29771), // Rule ID 2924 // |
| 11209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11210 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11211 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11212 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11213 | // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src) |
| 11214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11215 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11216 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11218 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11219 | GIR_RootConstrainSelectedInstOperands, |
| 11220 | // GIR_Coverage, 2924, |
| 11221 | GIR_EraseRootFromParent_Done, |
| 11222 | // Label 717: @29771 |
| 11223 | GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(29808), // Rule ID 2925 // |
| 11224 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11225 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11226 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11227 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11228 | // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src) |
| 11229 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11230 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11231 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11233 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11234 | GIR_RootConstrainSelectedInstOperands, |
| 11235 | // GIR_Coverage, 2925, |
| 11236 | GIR_EraseRootFromParent_Done, |
| 11237 | // Label 718: @29808 |
| 11238 | GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(29845), // Rule ID 2926 // |
| 11239 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11240 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11242 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11243 | // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) |
| 11244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 11245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11246 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11248 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11249 | GIR_RootConstrainSelectedInstOperands, |
| 11250 | // GIR_Coverage, 2926, |
| 11251 | GIR_EraseRootFromParent_Done, |
| 11252 | // Label 719: @29845 |
| 11253 | GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(29882), // Rule ID 2927 // |
| 11254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11255 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11256 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11257 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11258 | // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) |
| 11259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 11260 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11261 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11263 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11264 | GIR_RootConstrainSelectedInstOperands, |
| 11265 | // GIR_Coverage, 2927, |
| 11266 | GIR_EraseRootFromParent_Done, |
| 11267 | // Label 720: @29882 |
| 11268 | GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(29919), // Rule ID 2928 // |
| 11269 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11270 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11271 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11272 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11273 | // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) |
| 11274 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11275 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11276 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11278 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11279 | GIR_RootConstrainSelectedInstOperands, |
| 11280 | // GIR_Coverage, 2928, |
| 11281 | GIR_EraseRootFromParent_Done, |
| 11282 | // Label 721: @29919 |
| 11283 | GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(29956), // Rule ID 2929 // |
| 11284 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11285 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11286 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11287 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11288 | // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) |
| 11289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11291 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11293 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11294 | GIR_RootConstrainSelectedInstOperands, |
| 11295 | // GIR_Coverage, 2929, |
| 11296 | GIR_EraseRootFromParent_Done, |
| 11297 | // Label 722: @29956 |
| 11298 | GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(29993), // Rule ID 2930 // |
| 11299 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11300 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11301 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11302 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11303 | // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) |
| 11304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11306 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11308 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11309 | GIR_RootConstrainSelectedInstOperands, |
| 11310 | // GIR_Coverage, 2930, |
| 11311 | GIR_EraseRootFromParent_Done, |
| 11312 | // Label 723: @29993 |
| 11313 | GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(30025), // Rule ID 5404 // |
| 11314 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 11315 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11317 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11318 | // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 11319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11320 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11321 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11322 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11323 | // GIR_Coverage, 5404, |
| 11324 | GIR_EraseRootFromParent_Done, |
| 11325 | // Label 724: @30025 |
| 11326 | GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(30057), // Rule ID 5405 // |
| 11327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 11328 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11329 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11330 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11331 | // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 11332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11333 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11334 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11335 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11336 | // GIR_Coverage, 5405, |
| 11337 | GIR_EraseRootFromParent_Done, |
| 11338 | // Label 725: @30057 |
| 11339 | GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(30089), // Rule ID 5426 // |
| 11340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11341 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11342 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11343 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11344 | // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 11345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11346 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11347 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11348 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11349 | // GIR_Coverage, 5426, |
| 11350 | GIR_EraseRootFromParent_Done, |
| 11351 | // Label 726: @30089 |
| 11352 | GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(30121), // Rule ID 5427 // |
| 11353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11354 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11356 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11357 | // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 11358 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11359 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11360 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11361 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11362 | // GIR_Coverage, 5427, |
| 11363 | GIR_EraseRootFromParent_Done, |
| 11364 | // Label 727: @30121 |
| 11365 | GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(30153), // Rule ID 5428 // |
| 11366 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11367 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11368 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11369 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11370 | // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 11371 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11372 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11373 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11374 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11375 | // GIR_Coverage, 5428, |
| 11376 | GIR_EraseRootFromParent_Done, |
| 11377 | // Label 728: @30153 |
| 11378 | GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(30185), // Rule ID 5429 // |
| 11379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11380 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11381 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11382 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11383 | // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 11384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11385 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11386 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11387 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11388 | // GIR_Coverage, 5429, |
| 11389 | GIR_EraseRootFromParent_Done, |
| 11390 | // Label 729: @30185 |
| 11391 | GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(30217), // Rule ID 5430 // |
| 11392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11393 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11395 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11396 | // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 11397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11398 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11399 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11400 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11401 | // GIR_Coverage, 5430, |
| 11402 | GIR_EraseRootFromParent_Done, |
| 11403 | // Label 730: @30217 |
| 11404 | GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(30249), // Rule ID 5431 // |
| 11405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11406 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11408 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11409 | // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 11410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11411 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11412 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11413 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11414 | // GIR_Coverage, 5431, |
| 11415 | GIR_EraseRootFromParent_Done, |
| 11416 | // Label 731: @30249 |
| 11417 | GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(30281), // Rule ID 5432 // |
| 11418 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11419 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11420 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11421 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11422 | // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 11423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11424 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11425 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11426 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11427 | // GIR_Coverage, 5432, |
| 11428 | GIR_EraseRootFromParent_Done, |
| 11429 | // Label 732: @30281 |
| 11430 | GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(30313), // Rule ID 5433 // |
| 11431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11432 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11434 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11435 | // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 11436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11437 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11438 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11439 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11440 | // GIR_Coverage, 5433, |
| 11441 | GIR_EraseRootFromParent_Done, |
| 11442 | // Label 733: @30313 |
| 11443 | GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(30345), // Rule ID 5434 // |
| 11444 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11445 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11446 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11447 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11448 | // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 11449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11450 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11451 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11452 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11453 | // GIR_Coverage, 5434, |
| 11454 | GIR_EraseRootFromParent_Done, |
| 11455 | // Label 734: @30345 |
| 11456 | GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(30377), // Rule ID 5435 // |
| 11457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11458 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11459 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11460 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11461 | // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 11462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11463 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11464 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11465 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11466 | // GIR_Coverage, 5435, |
| 11467 | GIR_EraseRootFromParent_Done, |
| 11468 | // Label 735: @30377 |
| 11469 | GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(30433), // Rule ID 5462 // |
| 11470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11471 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11472 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11473 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11474 | // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) |
| 11475 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11476 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11477 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 11478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 11479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11480 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11482 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11483 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11484 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11485 | GIR_RootConstrainSelectedInstOperands, |
| 11486 | // GIR_Coverage, 5462, |
| 11487 | GIR_EraseRootFromParent_Done, |
| 11488 | // Label 736: @30433 |
| 11489 | GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(30489), // Rule ID 5463 // |
| 11490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11491 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11492 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11493 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11494 | // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) |
| 11495 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11496 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11497 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 11498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 11499 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11500 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11502 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11503 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11504 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11505 | GIR_RootConstrainSelectedInstOperands, |
| 11506 | // GIR_Coverage, 5463, |
| 11507 | GIR_EraseRootFromParent_Done, |
| 11508 | // Label 737: @30489 |
| 11509 | GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(30545), // Rule ID 5464 // |
| 11510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11511 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11513 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11514 | // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) |
| 11515 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11516 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11517 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 11518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 11519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11520 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11522 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11523 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11524 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11525 | GIR_RootConstrainSelectedInstOperands, |
| 11526 | // GIR_Coverage, 5464, |
| 11527 | GIR_EraseRootFromParent_Done, |
| 11528 | // Label 738: @30545 |
| 11529 | GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(30601), // Rule ID 5465 // |
| 11530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11531 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11532 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11533 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11534 | // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) |
| 11535 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11536 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11537 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 11538 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 11539 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11540 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11542 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11543 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11544 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11545 | GIR_RootConstrainSelectedInstOperands, |
| 11546 | // GIR_Coverage, 5465, |
| 11547 | GIR_EraseRootFromParent_Done, |
| 11548 | // Label 739: @30601 |
| 11549 | GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(30657), // Rule ID 5466 // |
| 11550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11551 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11552 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11553 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11554 | // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) |
| 11555 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11556 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11557 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 11558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 11559 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11560 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11562 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11563 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11564 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11565 | GIR_RootConstrainSelectedInstOperands, |
| 11566 | // GIR_Coverage, 5466, |
| 11567 | GIR_EraseRootFromParent_Done, |
| 11568 | // Label 740: @30657 |
| 11569 | GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(30713), // Rule ID 5467 // |
| 11570 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11571 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11573 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11574 | // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) |
| 11575 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11576 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11577 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 11578 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 11579 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11580 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11582 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11583 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11584 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11585 | GIR_RootConstrainSelectedInstOperands, |
| 11586 | // GIR_Coverage, 5467, |
| 11587 | GIR_EraseRootFromParent_Done, |
| 11588 | // Label 741: @30713 |
| 11589 | GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(30769), // Rule ID 5468 // |
| 11590 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11591 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11592 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11593 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11594 | // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) |
| 11595 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11596 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11597 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 11598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 11599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11600 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11602 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11603 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11604 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11605 | GIR_RootConstrainSelectedInstOperands, |
| 11606 | // GIR_Coverage, 5468, |
| 11607 | GIR_EraseRootFromParent_Done, |
| 11608 | // Label 742: @30769 |
| 11609 | GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(30825), // Rule ID 5469 // |
| 11610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11611 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11613 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11614 | // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) |
| 11615 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11616 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11617 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 11618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 11619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11620 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11622 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11623 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11624 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11625 | GIR_RootConstrainSelectedInstOperands, |
| 11626 | // GIR_Coverage, 5469, |
| 11627 | GIR_EraseRootFromParent_Done, |
| 11628 | // Label 743: @30825 |
| 11629 | GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(30881), // Rule ID 5470 // |
| 11630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11631 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11633 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11634 | // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) |
| 11635 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11636 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11637 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 11638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 11639 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11640 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11642 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11643 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11644 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11645 | GIR_RootConstrainSelectedInstOperands, |
| 11646 | // GIR_Coverage, 5470, |
| 11647 | GIR_EraseRootFromParent_Done, |
| 11648 | // Label 744: @30881 |
| 11649 | GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(30937), // Rule ID 5471 // |
| 11650 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11651 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11652 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11653 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11654 | // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 11655 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11656 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11657 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 11658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 11659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11660 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11662 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11663 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11664 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11665 | GIR_RootConstrainSelectedInstOperands, |
| 11666 | // GIR_Coverage, 5471, |
| 11667 | GIR_EraseRootFromParent_Done, |
| 11668 | // Label 745: @30937 |
| 11669 | GIM_Reject, |
| 11670 | // Label 488: @30938 |
| 11671 | GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(30970), // Rule ID 2839 // |
| 11672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11673 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11674 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11675 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11676 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11678 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11679 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11680 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11681 | // GIR_Coverage, 2839, |
| 11682 | GIR_EraseRootFromParent_Done, |
| 11683 | // Label 746: @30970 |
| 11684 | GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(31002), // Rule ID 2840 // |
| 11685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11686 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11687 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11688 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11689 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11691 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11692 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11693 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11694 | // GIR_Coverage, 2840, |
| 11695 | GIR_EraseRootFromParent_Done, |
| 11696 | // Label 747: @31002 |
| 11697 | GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(31034), // Rule ID 2841 // |
| 11698 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11699 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11700 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11701 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11702 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11703 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11704 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11705 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11706 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11707 | // GIR_Coverage, 2841, |
| 11708 | GIR_EraseRootFromParent_Done, |
| 11709 | // Label 748: @31034 |
| 11710 | GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(31066), // Rule ID 2842 // |
| 11711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11712 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11713 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11714 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11715 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11717 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11718 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11719 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11720 | // GIR_Coverage, 2842, |
| 11721 | GIR_EraseRootFromParent_Done, |
| 11722 | // Label 749: @31066 |
| 11723 | GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(31098), // Rule ID 2843 // |
| 11724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11725 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11726 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11727 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11728 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11730 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11731 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11732 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11733 | // GIR_Coverage, 2843, |
| 11734 | GIR_EraseRootFromParent_Done, |
| 11735 | // Label 750: @31098 |
| 11736 | GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(31130), // Rule ID 2844 // |
| 11737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11738 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11740 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11741 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11743 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11744 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11745 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11746 | // GIR_Coverage, 2844, |
| 11747 | GIR_EraseRootFromParent_Done, |
| 11748 | // Label 751: @31130 |
| 11749 | GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(31162), // Rule ID 2845 // |
| 11750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11751 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11753 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11754 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11755 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11756 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11757 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11758 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11759 | // GIR_Coverage, 2845, |
| 11760 | GIR_EraseRootFromParent_Done, |
| 11761 | // Label 752: @31162 |
| 11762 | GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(31199), // Rule ID 2931 // |
| 11763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11764 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11765 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11766 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11767 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) |
| 11768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 11769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11770 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11772 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11773 | GIR_RootConstrainSelectedInstOperands, |
| 11774 | // GIR_Coverage, 2931, |
| 11775 | GIR_EraseRootFromParent_Done, |
| 11776 | // Label 753: @31199 |
| 11777 | GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(31236), // Rule ID 2932 // |
| 11778 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11779 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11780 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11781 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11782 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) |
| 11783 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 11784 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11785 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11786 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11787 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11788 | GIR_RootConstrainSelectedInstOperands, |
| 11789 | // GIR_Coverage, 2932, |
| 11790 | GIR_EraseRootFromParent_Done, |
| 11791 | // Label 754: @31236 |
| 11792 | GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(31273), // Rule ID 2933 // |
| 11793 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11794 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11795 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11796 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11797 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) |
| 11798 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 11799 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11800 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11802 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11803 | GIR_RootConstrainSelectedInstOperands, |
| 11804 | // GIR_Coverage, 2933, |
| 11805 | GIR_EraseRootFromParent_Done, |
| 11806 | // Label 755: @31273 |
| 11807 | GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(31310), // Rule ID 2934 // |
| 11808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11809 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11811 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11812 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) |
| 11813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 11814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11815 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11817 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11818 | GIR_RootConstrainSelectedInstOperands, |
| 11819 | // GIR_Coverage, 2934, |
| 11820 | GIR_EraseRootFromParent_Done, |
| 11821 | // Label 756: @31310 |
| 11822 | GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(31347), // Rule ID 2935 // |
| 11823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11824 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11826 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11827 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) |
| 11828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11830 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11832 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11833 | GIR_RootConstrainSelectedInstOperands, |
| 11834 | // GIR_Coverage, 2935, |
| 11835 | GIR_EraseRootFromParent_Done, |
| 11836 | // Label 757: @31347 |
| 11837 | GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(31384), // Rule ID 2936 // |
| 11838 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11839 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11840 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11841 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11842 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src) |
| 11843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11844 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11845 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11847 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11848 | GIR_RootConstrainSelectedInstOperands, |
| 11849 | // GIR_Coverage, 2936, |
| 11850 | GIR_EraseRootFromParent_Done, |
| 11851 | // Label 758: @31384 |
| 11852 | GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(31421), // Rule ID 2937 // |
| 11853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11854 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11855 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11856 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11857 | // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) |
| 11858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11859 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11860 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11862 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11863 | GIR_RootConstrainSelectedInstOperands, |
| 11864 | // GIR_Coverage, 2937, |
| 11865 | GIR_EraseRootFromParent_Done, |
| 11866 | // Label 759: @31421 |
| 11867 | GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(31453), // Rule ID 5436 // |
| 11868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11869 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11870 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11871 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11872 | // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11874 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11875 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11876 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11877 | // GIR_Coverage, 5436, |
| 11878 | GIR_EraseRootFromParent_Done, |
| 11879 | // Label 760: @31453 |
| 11880 | GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(31485), // Rule ID 5437 // |
| 11881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11882 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11883 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11884 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11885 | // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11887 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11888 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11889 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11890 | // GIR_Coverage, 5437, |
| 11891 | GIR_EraseRootFromParent_Done, |
| 11892 | // Label 761: @31485 |
| 11893 | GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(31517), // Rule ID 5438 // |
| 11894 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11895 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11896 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11897 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11898 | // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11899 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11900 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11901 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11902 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11903 | // GIR_Coverage, 5438, |
| 11904 | GIR_EraseRootFromParent_Done, |
| 11905 | // Label 762: @31517 |
| 11906 | GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(31549), // Rule ID 5439 // |
| 11907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11908 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11910 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11911 | // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11913 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11914 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11915 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11916 | // GIR_Coverage, 5439, |
| 11917 | GIR_EraseRootFromParent_Done, |
| 11918 | // Label 763: @31549 |
| 11919 | GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(31581), // Rule ID 5440 // |
| 11920 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11921 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11923 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11924 | // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11925 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11926 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11927 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11928 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11929 | // GIR_Coverage, 5440, |
| 11930 | GIR_EraseRootFromParent_Done, |
| 11931 | // Label 764: @31581 |
| 11932 | GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(31613), // Rule ID 5441 // |
| 11933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11934 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11936 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11937 | // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11939 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11940 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11941 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11942 | // GIR_Coverage, 5441, |
| 11943 | GIR_EraseRootFromParent_Done, |
| 11944 | // Label 765: @31613 |
| 11945 | GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(31669), // Rule ID 5472 // |
| 11946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11947 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11948 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11949 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11950 | // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) |
| 11951 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11952 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11953 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 11954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 11955 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11956 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11958 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11959 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11960 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11961 | GIR_RootConstrainSelectedInstOperands, |
| 11962 | // GIR_Coverage, 5472, |
| 11963 | GIR_EraseRootFromParent_Done, |
| 11964 | // Label 766: @31669 |
| 11965 | GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(31725), // Rule ID 5473 // |
| 11966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11967 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11969 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11970 | // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) |
| 11971 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11972 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11973 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 11974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 11975 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11976 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11978 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11979 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11980 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11981 | GIR_RootConstrainSelectedInstOperands, |
| 11982 | // GIR_Coverage, 5473, |
| 11983 | GIR_EraseRootFromParent_Done, |
| 11984 | // Label 767: @31725 |
| 11985 | GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(31781), // Rule ID 5474 // |
| 11986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11987 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11989 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11990 | // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) |
| 11991 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11992 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11993 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 11994 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 11995 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11996 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11998 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11999 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12000 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12001 | GIR_RootConstrainSelectedInstOperands, |
| 12002 | // GIR_Coverage, 5474, |
| 12003 | GIR_EraseRootFromParent_Done, |
| 12004 | // Label 768: @31781 |
| 12005 | GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(31837), // Rule ID 5475 // |
| 12006 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12007 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12008 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12009 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12010 | // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) |
| 12011 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12012 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12013 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 12014 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 12015 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12016 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12018 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12019 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12020 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12021 | GIR_RootConstrainSelectedInstOperands, |
| 12022 | // GIR_Coverage, 5475, |
| 12023 | GIR_EraseRootFromParent_Done, |
| 12024 | // Label 769: @31837 |
| 12025 | GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(31893), // Rule ID 5476 // |
| 12026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12027 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12028 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12029 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12030 | // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) |
| 12031 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12032 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12033 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 12034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 12035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12036 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12038 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12039 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12040 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12041 | GIR_RootConstrainSelectedInstOperands, |
| 12042 | // GIR_Coverage, 5476, |
| 12043 | GIR_EraseRootFromParent_Done, |
| 12044 | // Label 770: @31893 |
| 12045 | GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(31949), // Rule ID 5477 // |
| 12046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12047 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12048 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12049 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12050 | // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) |
| 12051 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12052 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12053 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 12054 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 12055 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12056 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12058 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12059 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12060 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12061 | GIR_RootConstrainSelectedInstOperands, |
| 12062 | // GIR_Coverage, 5477, |
| 12063 | GIR_EraseRootFromParent_Done, |
| 12064 | // Label 771: @31949 |
| 12065 | GIM_Reject, |
| 12066 | // Label 489: @31950 |
| 12067 | GIM_Reject, |
| 12068 | // Label 10: @31951 |
| 12069 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 777*/ GIMT_Encode4(32242), |
| 12070 | /*GILLT_s16*//*Label 772*/ GIMT_Encode4(32014), |
| 12071 | /*GILLT_s32*//*Label 773*/ GIMT_Encode4(32052), |
| 12072 | /*GILLT_s64*//*Label 774*/ GIMT_Encode4(32090), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 12073 | /*GILLT_v4s32*//*Label 775*/ GIMT_Encode4(32128), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 12074 | /*GILLT_v8s16*//*Label 776*/ GIMT_Encode4(32185), |
| 12075 | // Label 772: @32014 |
| 12076 | GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(32051), // Rule ID 682 // |
| 12077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 12078 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 12079 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 12080 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 12081 | // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 12082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZH), |
| 12083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 12084 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 12085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12086 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12087 | GIR_RootConstrainSelectedInstOperands, |
| 12088 | // GIR_Coverage, 682, |
| 12089 | GIR_EraseRootFromParent_Done, |
| 12090 | // Label 778: @32051 |
| 12091 | GIM_Reject, |
| 12092 | // Label 773: @32052 |
| 12093 | GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(32089), // Rule ID 683 // |
| 12094 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 12095 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 12096 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 12097 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 12098 | // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 12099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZS), |
| 12100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 12101 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 12102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12103 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12104 | GIR_RootConstrainSelectedInstOperands, |
| 12105 | // GIR_Coverage, 683, |
| 12106 | GIR_EraseRootFromParent_Done, |
| 12107 | // Label 779: @32089 |
| 12108 | GIM_Reject, |
| 12109 | // Label 774: @32090 |
| 12110 | GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(32127), // Rule ID 684 // |
| 12111 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 12112 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12113 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12114 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12115 | // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 12116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZD), |
| 12117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 12118 | GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 12119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12120 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12121 | GIR_RootConstrainSelectedInstOperands, |
| 12122 | // GIR_Coverage, 684, |
| 12123 | GIR_EraseRootFromParent_Done, |
| 12124 | // Label 780: @32127 |
| 12125 | GIM_Reject, |
| 12126 | // Label 775: @32128 |
| 12127 | GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(32184), // Rule ID 4097 // |
| 12128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 12129 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12130 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12131 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12132 | // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 12133 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12134 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12135 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 12136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z), |
| 12137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12138 | GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 12139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12140 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12141 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12142 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12143 | GIR_RootConstrainSelectedInstOperands, |
| 12144 | // GIR_Coverage, 4097, |
| 12145 | GIR_EraseRootFromParent_Done, |
| 12146 | // Label 781: @32184 |
| 12147 | GIM_Reject, |
| 12148 | // Label 776: @32185 |
| 12149 | GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(32241), // Rule ID 4085 // |
| 12150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 12151 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12153 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12154 | // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 12155 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12156 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12157 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 12158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z), |
| 12159 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12160 | GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 12161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12162 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12163 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12164 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12165 | GIR_RootConstrainSelectedInstOperands, |
| 12166 | // GIR_Coverage, 4085, |
| 12167 | GIR_EraseRootFromParent_Done, |
| 12168 | // Label 782: @32241 |
| 12169 | GIM_Reject, |
| 12170 | // Label 777: @32242 |
| 12171 | GIM_Reject, |
| 12172 | // Label 11: @32243 |
| 12173 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 788*/ GIMT_Encode4(32501), |
| 12174 | /*GILLT_s16*//*Label 783*/ GIMT_Encode4(32306), |
| 12175 | /*GILLT_s32*//*Label 784*/ GIMT_Encode4(32333), |
| 12176 | /*GILLT_s64*//*Label 785*/ GIMT_Encode4(32360), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 12177 | /*GILLT_v4s32*//*Label 786*/ GIMT_Encode4(32387), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 12178 | /*GILLT_v8s16*//*Label 787*/ GIMT_Encode4(32444), |
| 12179 | // Label 783: @32306 |
| 12180 | GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(32332), // Rule ID 691 // |
| 12181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 12182 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 12183 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 12184 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 12185 | // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 12186 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAH), |
| 12187 | GIR_RootConstrainSelectedInstOperands, |
| 12188 | // GIR_Coverage, 691, |
| 12189 | GIR_Done, |
| 12190 | // Label 789: @32332 |
| 12191 | GIM_Reject, |
| 12192 | // Label 784: @32333 |
| 12193 | GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(32359), // Rule ID 692 // |
| 12194 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 12195 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 12196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 12197 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 12198 | // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 12199 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAS), |
| 12200 | GIR_RootConstrainSelectedInstOperands, |
| 12201 | // GIR_Coverage, 692, |
| 12202 | GIR_Done, |
| 12203 | // Label 790: @32359 |
| 12204 | GIM_Reject, |
| 12205 | // Label 785: @32360 |
| 12206 | GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(32386), // Rule ID 693 // |
| 12207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 12208 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12209 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12210 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12211 | // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 12212 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAD), |
| 12213 | GIR_RootConstrainSelectedInstOperands, |
| 12214 | // GIR_Coverage, 693, |
| 12215 | GIR_Done, |
| 12216 | // Label 791: @32386 |
| 12217 | GIM_Reject, |
| 12218 | // Label 786: @32387 |
| 12219 | GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(32443), // Rule ID 4095 // |
| 12220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 12221 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12222 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12223 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12224 | // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 12225 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12226 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12227 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 12228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A), |
| 12229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12230 | GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 12231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12232 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12233 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12234 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12235 | GIR_RootConstrainSelectedInstOperands, |
| 12236 | // GIR_Coverage, 4095, |
| 12237 | GIR_EraseRootFromParent_Done, |
| 12238 | // Label 792: @32443 |
| 12239 | GIM_Reject, |
| 12240 | // Label 787: @32444 |
| 12241 | GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(32500), // Rule ID 4083 // |
| 12242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 12243 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12244 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12245 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12246 | // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 12247 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12248 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12249 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 12250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A), |
| 12251 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12252 | GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 12253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12254 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12255 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12256 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12257 | GIR_RootConstrainSelectedInstOperands, |
| 12258 | // GIR_Coverage, 4083, |
| 12259 | GIR_EraseRootFromParent_Done, |
| 12260 | // Label 793: @32500 |
| 12261 | GIM_Reject, |
| 12262 | // Label 788: @32501 |
| 12263 | GIM_Reject, |
| 12264 | // Label 12: @32502 |
| 12265 | GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(32522), // Rule ID 5538 // |
| 12266 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 12267 | // MIs[0] Operand 0 |
| 12268 | GIM_CheckIsImm, /*MI*/0, /*Op*/0, |
| 12269 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, |
| 12270 | // (atomic_fence (timm:{ *:[i32] }), 0:{ *:[i32] }) => (MEMBARRIER) |
| 12271 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::MEMBARRIER), |
| 12272 | GIR_RootConstrainSelectedInstOperands, |
| 12273 | // GIR_Coverage, 5538, |
| 12274 | GIR_EraseRootFromParent_Done, |
| 12275 | // Label 794: @32522 |
| 12276 | GIM_Reject, |
| 12277 | // Label 13: @32523 |
| 12278 | GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(38325), |
| 12279 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 12280 | GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(32579), // Rule ID 1880 // |
| 12281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 12282 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16), |
| 12283 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 12284 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 12285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 12286 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 12287 | // (intrinsic_wo_chain:{ *:[i32] } 3614:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 12288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 12289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 12290 | GIR_RootToRootCopy, /*OpIdx*/2, // Src |
| 12291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12293 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12294 | GIR_RootConstrainSelectedInstOperands, |
| 12295 | // GIR_Coverage, 1880, |
| 12296 | GIR_EraseRootFromParent_Done, |
| 12297 | // Label 796: @32579 |
| 12298 | GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(32627), // Rule ID 2117 // |
| 12299 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 12300 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16), |
| 12301 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 12302 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 12303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 12304 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 12305 | // (intrinsic_wo_chain:{ *:[i32] } 3614:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 12306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 12307 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 12308 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 12309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12311 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12312 | GIR_RootConstrainSelectedInstOperands, |
| 12313 | // GIR_Coverage, 2117, |
| 12314 | GIR_EraseRootFromParent_Done, |
| 12315 | // Label 797: @32627 |
| 12316 | GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(32663), // Rule ID 694 // |
| 12317 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 12318 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 12319 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 12320 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 12321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 12322 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 12323 | // (intrinsic_wo_chain:{ *:[f16] } 3500:{ *:[iPTR] }, HPR:{ *:[f16] }:$Sm) => (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 12324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNH), |
| 12325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 12326 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 12327 | GIR_RootConstrainSelectedInstOperands, |
| 12328 | // GIR_Coverage, 694, |
| 12329 | GIR_EraseRootFromParent_Done, |
| 12330 | // Label 798: @32663 |
| 12331 | GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(32699), // Rule ID 695 // |
| 12332 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 12333 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 12334 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 12335 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 12336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 12337 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 12338 | // (intrinsic_wo_chain:{ *:[f32] } 3500:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 12339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNS), |
| 12340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 12341 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 12342 | GIR_RootConstrainSelectedInstOperands, |
| 12343 | // GIR_Coverage, 695, |
| 12344 | GIR_EraseRootFromParent_Done, |
| 12345 | // Label 799: @32699 |
| 12346 | GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(32735), // Rule ID 696 // |
| 12347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 12348 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 12349 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 12350 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 12351 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12352 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12353 | // (intrinsic_wo_chain:{ *:[f64] } 3500:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 12354 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTND), |
| 12355 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 12356 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 12357 | GIR_RootConstrainSelectedInstOperands, |
| 12358 | // GIR_Coverage, 696, |
| 12359 | GIR_EraseRootFromParent_Done, |
| 12360 | // Label 800: @32735 |
| 12361 | GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(32780), // Rule ID 710 // |
| 12362 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 12363 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr), |
| 12364 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 12365 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 12366 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 12367 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12368 | // (intrinsic_wo_chain:{ *:[f32] } 3615:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 12369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRD), |
| 12370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 12371 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 12372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12373 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12374 | GIR_RootConstrainSelectedInstOperands, |
| 12375 | // GIR_Coverage, 710, |
| 12376 | GIR_EraseRootFromParent_Done, |
| 12377 | // Label 801: @32780 |
| 12378 | GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(32825), // Rule ID 711 // |
| 12379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 12380 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr), |
| 12381 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 12382 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 12383 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 12384 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 12385 | // (intrinsic_wo_chain:{ *:[f32] } 3615:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 12386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRS), |
| 12387 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 12388 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 12389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12390 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12391 | GIR_RootConstrainSelectedInstOperands, |
| 12392 | // GIR_Coverage, 711, |
| 12393 | GIR_EraseRootFromParent_Done, |
| 12394 | // Label 802: @32825 |
| 12395 | GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(32870), // Rule ID 712 // |
| 12396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 12397 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru), |
| 12398 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 12399 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 12400 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 12401 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12402 | // (intrinsic_wo_chain:{ *:[f32] } 3616:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 12403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRD), |
| 12404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 12405 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 12406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12407 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12408 | GIR_RootConstrainSelectedInstOperands, |
| 12409 | // GIR_Coverage, 712, |
| 12410 | GIR_EraseRootFromParent_Done, |
| 12411 | // Label 803: @32870 |
| 12412 | GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(32915), // Rule ID 713 // |
| 12413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 12414 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru), |
| 12415 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 12416 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 12417 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 12418 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 12419 | // (intrinsic_wo_chain:{ *:[f32] } 3616:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 12420 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRS), |
| 12421 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 12422 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 12423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12424 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12425 | GIR_RootConstrainSelectedInstOperands, |
| 12426 | // GIR_Coverage, 713, |
| 12427 | GIR_EraseRootFromParent_Done, |
| 12428 | // Label 804: @32915 |
| 12429 | GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(32960), // Rule ID 1261 // |
| 12430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12431 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 12432 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 12433 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 12434 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12435 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12436 | // (intrinsic_wo_chain:{ *:[v4i16] } 3466:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) |
| 12437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i8), |
| 12438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12439 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12441 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12442 | GIR_RootConstrainSelectedInstOperands, |
| 12443 | // GIR_Coverage, 1261, |
| 12444 | GIR_EraseRootFromParent_Done, |
| 12445 | // Label 805: @32960 |
| 12446 | GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(33005), // Rule ID 1262 // |
| 12447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12448 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 12449 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 12450 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12451 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12452 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12453 | // (intrinsic_wo_chain:{ *:[v2i32] } 3466:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) |
| 12454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i16), |
| 12455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12456 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12458 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12459 | GIR_RootConstrainSelectedInstOperands, |
| 12460 | // GIR_Coverage, 1262, |
| 12461 | GIR_EraseRootFromParent_Done, |
| 12462 | // Label 806: @33005 |
| 12463 | GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(33050), // Rule ID 1263 // |
| 12464 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12465 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 12466 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 12467 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 12468 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12469 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12470 | // (intrinsic_wo_chain:{ *:[v1i64] } 3466:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) |
| 12471 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv2i32), |
| 12472 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12473 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12475 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12476 | GIR_RootConstrainSelectedInstOperands, |
| 12477 | // GIR_Coverage, 1263, |
| 12478 | GIR_EraseRootFromParent_Done, |
| 12479 | // Label 807: @33050 |
| 12480 | GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(33095), // Rule ID 1264 // |
| 12481 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12482 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 12483 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 12484 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 12485 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12486 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12487 | // (intrinsic_wo_chain:{ *:[v8i16] } 3466:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) |
| 12488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv16i8), |
| 12489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12490 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12492 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12493 | GIR_RootConstrainSelectedInstOperands, |
| 12494 | // GIR_Coverage, 1264, |
| 12495 | GIR_EraseRootFromParent_Done, |
| 12496 | // Label 808: @33095 |
| 12497 | GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(33140), // Rule ID 1265 // |
| 12498 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12499 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 12500 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 12501 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 12502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12503 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12504 | // (intrinsic_wo_chain:{ *:[v4i32] } 3466:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) |
| 12505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i16), |
| 12506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12507 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12509 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12510 | GIR_RootConstrainSelectedInstOperands, |
| 12511 | // GIR_Coverage, 1265, |
| 12512 | GIR_EraseRootFromParent_Done, |
| 12513 | // Label 809: @33140 |
| 12514 | GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(33185), // Rule ID 1266 // |
| 12515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12516 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 12517 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 12518 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12520 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12521 | // (intrinsic_wo_chain:{ *:[v2i64] } 3466:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) |
| 12522 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i32), |
| 12523 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12524 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12526 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12527 | GIR_RootConstrainSelectedInstOperands, |
| 12528 | // GIR_Coverage, 1266, |
| 12529 | GIR_EraseRootFromParent_Done, |
| 12530 | // Label 810: @33185 |
| 12531 | GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(33230), // Rule ID 1267 // |
| 12532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12533 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 12534 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 12535 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 12536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12537 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12538 | // (intrinsic_wo_chain:{ *:[v4i16] } 3467:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) |
| 12539 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i8), |
| 12540 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12541 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12543 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12544 | GIR_RootConstrainSelectedInstOperands, |
| 12545 | // GIR_Coverage, 1267, |
| 12546 | GIR_EraseRootFromParent_Done, |
| 12547 | // Label 811: @33230 |
| 12548 | GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(33275), // Rule ID 1268 // |
| 12549 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12550 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 12551 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 12552 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12553 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12554 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12555 | // (intrinsic_wo_chain:{ *:[v2i32] } 3467:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) |
| 12556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i16), |
| 12557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12558 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12560 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12561 | GIR_RootConstrainSelectedInstOperands, |
| 12562 | // GIR_Coverage, 1268, |
| 12563 | GIR_EraseRootFromParent_Done, |
| 12564 | // Label 812: @33275 |
| 12565 | GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(33320), // Rule ID 1269 // |
| 12566 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12567 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 12568 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 12569 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 12570 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12571 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12572 | // (intrinsic_wo_chain:{ *:[v1i64] } 3467:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) |
| 12573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv2i32), |
| 12574 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12575 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12577 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12578 | GIR_RootConstrainSelectedInstOperands, |
| 12579 | // GIR_Coverage, 1269, |
| 12580 | GIR_EraseRootFromParent_Done, |
| 12581 | // Label 813: @33320 |
| 12582 | GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(33365), // Rule ID 1270 // |
| 12583 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12584 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 12585 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 12586 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 12587 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12588 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12589 | // (intrinsic_wo_chain:{ *:[v8i16] } 3467:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) |
| 12590 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv16i8), |
| 12591 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12592 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12594 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12595 | GIR_RootConstrainSelectedInstOperands, |
| 12596 | // GIR_Coverage, 1270, |
| 12597 | GIR_EraseRootFromParent_Done, |
| 12598 | // Label 814: @33365 |
| 12599 | GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(33410), // Rule ID 1271 // |
| 12600 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12601 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 12602 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 12603 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 12604 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12605 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12606 | // (intrinsic_wo_chain:{ *:[v4i32] } 3467:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) |
| 12607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i16), |
| 12608 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12609 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12611 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12612 | GIR_RootConstrainSelectedInstOperands, |
| 12613 | // GIR_Coverage, 1271, |
| 12614 | GIR_EraseRootFromParent_Done, |
| 12615 | // Label 815: @33410 |
| 12616 | GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(33455), // Rule ID 1272 // |
| 12617 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12618 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 12619 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 12620 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12621 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12622 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12623 | // (intrinsic_wo_chain:{ *:[v2i64] } 3467:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) |
| 12624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i32), |
| 12625 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12626 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12628 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12629 | GIR_RootConstrainSelectedInstOperands, |
| 12630 | // GIR_Coverage, 1272, |
| 12631 | GIR_EraseRootFromParent_Done, |
| 12632 | // Label 816: @33455 |
| 12633 | GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(33500), // Rule ID 1301 // |
| 12634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12635 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 12636 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 12637 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 12638 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12639 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12640 | // (intrinsic_wo_chain:{ *:[v2i32] } 3494:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 12641 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEd), |
| 12642 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12643 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12645 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12646 | GIR_RootConstrainSelectedInstOperands, |
| 12647 | // GIR_Coverage, 1301, |
| 12648 | GIR_EraseRootFromParent_Done, |
| 12649 | // Label 817: @33500 |
| 12650 | GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(33545), // Rule ID 1302 // |
| 12651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12652 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 12653 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 12654 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12655 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12656 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12657 | // (intrinsic_wo_chain:{ *:[v4i32] } 3494:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 12658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEq), |
| 12659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12660 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12662 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12663 | GIR_RootConstrainSelectedInstOperands, |
| 12664 | // GIR_Coverage, 1302, |
| 12665 | GIR_EraseRootFromParent_Done, |
| 12666 | // Label 818: @33545 |
| 12667 | GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(33590), // Rule ID 1303 // |
| 12668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12669 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 12670 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 12671 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 12672 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12673 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12674 | // (intrinsic_wo_chain:{ *:[v2f32] } 3494:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 12675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfd), |
| 12676 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12677 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12679 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12680 | GIR_RootConstrainSelectedInstOperands, |
| 12681 | // GIR_Coverage, 1303, |
| 12682 | GIR_EraseRootFromParent_Done, |
| 12683 | // Label 819: @33590 |
| 12684 | GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(33635), // Rule ID 1304 // |
| 12685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12686 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 12687 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 12688 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12689 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12690 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12691 | // (intrinsic_wo_chain:{ *:[v4f32] } 3494:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 12692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfq), |
| 12693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12694 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12696 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12697 | GIR_RootConstrainSelectedInstOperands, |
| 12698 | // GIR_Coverage, 1304, |
| 12699 | GIR_EraseRootFromParent_Done, |
| 12700 | // Label 820: @33635 |
| 12701 | GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(33680), // Rule ID 1305 // |
| 12702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 12703 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 12704 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 12705 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12707 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12708 | // (intrinsic_wo_chain:{ *:[v4f16] } 3494:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 12709 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhd), |
| 12710 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12711 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12713 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12714 | GIR_RootConstrainSelectedInstOperands, |
| 12715 | // GIR_Coverage, 1305, |
| 12716 | GIR_EraseRootFromParent_Done, |
| 12717 | // Label 821: @33680 |
| 12718 | GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(33725), // Rule ID 1306 // |
| 12719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 12720 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 12721 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 12722 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 12723 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12724 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12725 | // (intrinsic_wo_chain:{ *:[v8f16] } 3494:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 12726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhq), |
| 12727 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12728 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12730 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12731 | GIR_RootConstrainSelectedInstOperands, |
| 12732 | // GIR_Coverage, 1306, |
| 12733 | GIR_EraseRootFromParent_Done, |
| 12734 | // Label 822: @33725 |
| 12735 | GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(33770), // Rule ID 1311 // |
| 12736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12737 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 12738 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 12739 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 12740 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12741 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12742 | // (intrinsic_wo_chain:{ *:[v2i32] } 3507:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 12743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEd), |
| 12744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12745 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12747 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12748 | GIR_RootConstrainSelectedInstOperands, |
| 12749 | // GIR_Coverage, 1311, |
| 12750 | GIR_EraseRootFromParent_Done, |
| 12751 | // Label 823: @33770 |
| 12752 | GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(33815), // Rule ID 1312 // |
| 12753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12754 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 12755 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 12756 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12757 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12758 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12759 | // (intrinsic_wo_chain:{ *:[v4i32] } 3507:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 12760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEq), |
| 12761 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12762 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12764 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12765 | GIR_RootConstrainSelectedInstOperands, |
| 12766 | // GIR_Coverage, 1312, |
| 12767 | GIR_EraseRootFromParent_Done, |
| 12768 | // Label 824: @33815 |
| 12769 | GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(33860), // Rule ID 1313 // |
| 12770 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12771 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 12772 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 12773 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 12774 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12775 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12776 | // (intrinsic_wo_chain:{ *:[v2f32] } 3507:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 12777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfd), |
| 12778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12779 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12781 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12782 | GIR_RootConstrainSelectedInstOperands, |
| 12783 | // GIR_Coverage, 1313, |
| 12784 | GIR_EraseRootFromParent_Done, |
| 12785 | // Label 825: @33860 |
| 12786 | GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(33905), // Rule ID 1314 // |
| 12787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12788 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 12789 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 12790 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12792 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12793 | // (intrinsic_wo_chain:{ *:[v4f32] } 3507:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 12794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfq), |
| 12795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12796 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12798 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12799 | GIR_RootConstrainSelectedInstOperands, |
| 12800 | // GIR_Coverage, 1314, |
| 12801 | GIR_EraseRootFromParent_Done, |
| 12802 | // Label 826: @33905 |
| 12803 | GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(33950), // Rule ID 1315 // |
| 12804 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 12805 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 12806 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 12807 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12809 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12810 | // (intrinsic_wo_chain:{ *:[v4f16] } 3507:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 12811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhd), |
| 12812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12813 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12815 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12816 | GIR_RootConstrainSelectedInstOperands, |
| 12817 | // GIR_Coverage, 1315, |
| 12818 | GIR_EraseRootFromParent_Done, |
| 12819 | // Label 827: @33950 |
| 12820 | GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(33995), // Rule ID 1316 // |
| 12821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 12822 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 12823 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 12824 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 12825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12826 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12827 | // (intrinsic_wo_chain:{ *:[v8f16] } 3507:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 12828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhq), |
| 12829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12830 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12832 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12833 | GIR_RootConstrainSelectedInstOperands, |
| 12834 | // GIR_Coverage, 1316, |
| 12835 | GIR_EraseRootFromParent_Done, |
| 12836 | // Label 828: @33995 |
| 12837 | GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(34040), // Rule ID 1537 // |
| 12838 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12839 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 12840 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 12841 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 12842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12843 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12844 | // (intrinsic_wo_chain:{ *:[v8i8] } 3472:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 12845 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i8), |
| 12846 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12847 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12849 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12850 | GIR_RootConstrainSelectedInstOperands, |
| 12851 | // GIR_Coverage, 1537, |
| 12852 | GIR_EraseRootFromParent_Done, |
| 12853 | // Label 829: @34040 |
| 12854 | GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(34085), // Rule ID 1538 // |
| 12855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12856 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 12857 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 12858 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12860 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12861 | // (intrinsic_wo_chain:{ *:[v4i16] } 3472:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 12862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i16), |
| 12863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12864 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12866 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12867 | GIR_RootConstrainSelectedInstOperands, |
| 12868 | // GIR_Coverage, 1538, |
| 12869 | GIR_EraseRootFromParent_Done, |
| 12870 | // Label 830: @34085 |
| 12871 | GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(34130), // Rule ID 1539 // |
| 12872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12873 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 12874 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 12875 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 12876 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12877 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12878 | // (intrinsic_wo_chain:{ *:[v2i32] } 3472:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 12879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv2i32), |
| 12880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12881 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12883 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12884 | GIR_RootConstrainSelectedInstOperands, |
| 12885 | // GIR_Coverage, 1539, |
| 12886 | GIR_EraseRootFromParent_Done, |
| 12887 | // Label 831: @34130 |
| 12888 | GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(34175), // Rule ID 1540 // |
| 12889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12890 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 12891 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 12892 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 12893 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12894 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12895 | // (intrinsic_wo_chain:{ *:[v16i8] } 3472:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 12896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv16i8), |
| 12897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12898 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12900 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12901 | GIR_RootConstrainSelectedInstOperands, |
| 12902 | // GIR_Coverage, 1540, |
| 12903 | GIR_EraseRootFromParent_Done, |
| 12904 | // Label 832: @34175 |
| 12905 | GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(34220), // Rule ID 1541 // |
| 12906 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12907 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 12908 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 12909 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 12910 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12911 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12912 | // (intrinsic_wo_chain:{ *:[v8i16] } 3472:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 12913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i16), |
| 12914 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12915 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12917 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12918 | GIR_RootConstrainSelectedInstOperands, |
| 12919 | // GIR_Coverage, 1541, |
| 12920 | GIR_EraseRootFromParent_Done, |
| 12921 | // Label 833: @34220 |
| 12922 | GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(34265), // Rule ID 1542 // |
| 12923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12924 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 12925 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 12926 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12927 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12928 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12929 | // (intrinsic_wo_chain:{ *:[v4i32] } 3472:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 12930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i32), |
| 12931 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12932 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12933 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12934 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12935 | GIR_RootConstrainSelectedInstOperands, |
| 12936 | // GIR_Coverage, 1542, |
| 12937 | GIR_EraseRootFromParent_Done, |
| 12938 | // Label 834: @34265 |
| 12939 | GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(34310), // Rule ID 1553 // |
| 12940 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12941 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 12942 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 12943 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 12944 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12945 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12946 | // (intrinsic_wo_chain:{ *:[v8i8] } 3478:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 12947 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i8), |
| 12948 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12949 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12951 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12952 | GIR_RootConstrainSelectedInstOperands, |
| 12953 | // GIR_Coverage, 1553, |
| 12954 | GIR_EraseRootFromParent_Done, |
| 12955 | // Label 835: @34310 |
| 12956 | GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(34355), // Rule ID 1554 // |
| 12957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12958 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 12959 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 12960 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12961 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12962 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12963 | // (intrinsic_wo_chain:{ *:[v4i16] } 3478:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 12964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i16), |
| 12965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12966 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12968 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12969 | GIR_RootConstrainSelectedInstOperands, |
| 12970 | // GIR_Coverage, 1554, |
| 12971 | GIR_EraseRootFromParent_Done, |
| 12972 | // Label 836: @34355 |
| 12973 | GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(34400), // Rule ID 1555 // |
| 12974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12975 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 12976 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 12977 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 12978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12979 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12980 | // (intrinsic_wo_chain:{ *:[v2i32] } 3478:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 12981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv2i32), |
| 12982 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12983 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 12984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12985 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12986 | GIR_RootConstrainSelectedInstOperands, |
| 12987 | // GIR_Coverage, 1555, |
| 12988 | GIR_EraseRootFromParent_Done, |
| 12989 | // Label 837: @34400 |
| 12990 | GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(34445), // Rule ID 1556 // |
| 12991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 12992 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 12993 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 12994 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 12995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12996 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12997 | // (intrinsic_wo_chain:{ *:[v16i8] } 3478:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 12998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv16i8), |
| 12999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13000 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13002 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13003 | GIR_RootConstrainSelectedInstOperands, |
| 13004 | // GIR_Coverage, 1556, |
| 13005 | GIR_EraseRootFromParent_Done, |
| 13006 | // Label 838: @34445 |
| 13007 | GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(34490), // Rule ID 1557 // |
| 13008 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13009 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 13010 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13011 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13012 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13013 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13014 | // (intrinsic_wo_chain:{ *:[v8i16] } 3478:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 13015 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i16), |
| 13016 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13017 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13019 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13020 | GIR_RootConstrainSelectedInstOperands, |
| 13021 | // GIR_Coverage, 1557, |
| 13022 | GIR_EraseRootFromParent_Done, |
| 13023 | // Label 839: @34490 |
| 13024 | GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(34535), // Rule ID 1558 // |
| 13025 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13026 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 13027 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13028 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13029 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13030 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13031 | // (intrinsic_wo_chain:{ *:[v4i32] } 3478:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 13032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i32), |
| 13033 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13034 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13036 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13037 | GIR_RootConstrainSelectedInstOperands, |
| 13038 | // GIR_Coverage, 1558, |
| 13039 | GIR_EraseRootFromParent_Done, |
| 13040 | // Label 840: @34535 |
| 13041 | GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(34580), // Rule ID 1559 // |
| 13042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13043 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls), |
| 13044 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 13045 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13047 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13048 | // (intrinsic_wo_chain:{ *:[v8i8] } 3419:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 13049 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i8), |
| 13050 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13051 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13053 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13054 | GIR_RootConstrainSelectedInstOperands, |
| 13055 | // GIR_Coverage, 1559, |
| 13056 | GIR_EraseRootFromParent_Done, |
| 13057 | // Label 841: @34580 |
| 13058 | GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(34625), // Rule ID 1560 // |
| 13059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13060 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls), |
| 13061 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13062 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13064 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13065 | // (intrinsic_wo_chain:{ *:[v4i16] } 3419:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 13066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i16), |
| 13067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13068 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13070 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13071 | GIR_RootConstrainSelectedInstOperands, |
| 13072 | // GIR_Coverage, 1560, |
| 13073 | GIR_EraseRootFromParent_Done, |
| 13074 | // Label 842: @34625 |
| 13075 | GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(34670), // Rule ID 1561 // |
| 13076 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13077 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls), |
| 13078 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13079 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13081 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13082 | // (intrinsic_wo_chain:{ *:[v2i32] } 3419:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 13083 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv2i32), |
| 13084 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13085 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13087 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13088 | GIR_RootConstrainSelectedInstOperands, |
| 13089 | // GIR_Coverage, 1561, |
| 13090 | GIR_EraseRootFromParent_Done, |
| 13091 | // Label 843: @34670 |
| 13092 | GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(34715), // Rule ID 1562 // |
| 13093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13094 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls), |
| 13095 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 13096 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 13097 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13098 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13099 | // (intrinsic_wo_chain:{ *:[v16i8] } 3419:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 13100 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv16i8), |
| 13101 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13102 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13104 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13105 | GIR_RootConstrainSelectedInstOperands, |
| 13106 | // GIR_Coverage, 1562, |
| 13107 | GIR_EraseRootFromParent_Done, |
| 13108 | // Label 844: @34715 |
| 13109 | GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(34760), // Rule ID 1563 // |
| 13110 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13111 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls), |
| 13112 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13113 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13114 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13115 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13116 | // (intrinsic_wo_chain:{ *:[v8i16] } 3419:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 13117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i16), |
| 13118 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13119 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13121 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13122 | GIR_RootConstrainSelectedInstOperands, |
| 13123 | // GIR_Coverage, 1563, |
| 13124 | GIR_EraseRootFromParent_Done, |
| 13125 | // Label 845: @34760 |
| 13126 | GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(34805), // Rule ID 1564 // |
| 13127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13128 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls), |
| 13129 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13130 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13131 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13132 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13133 | // (intrinsic_wo_chain:{ *:[v4i32] } 3419:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 13134 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i32), |
| 13135 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13136 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13138 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13139 | GIR_RootConstrainSelectedInstOperands, |
| 13140 | // GIR_Coverage, 1564, |
| 13141 | GIR_EraseRootFromParent_Done, |
| 13142 | // Label 846: @34805 |
| 13143 | GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(34850), // Rule ID 1608 // |
| 13144 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13145 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns), |
| 13146 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 13147 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13148 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13149 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13150 | // (intrinsic_wo_chain:{ *:[v8i8] } 3475:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 13151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv8i8), |
| 13152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13153 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13155 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13156 | GIR_RootConstrainSelectedInstOperands, |
| 13157 | // GIR_Coverage, 1608, |
| 13158 | GIR_EraseRootFromParent_Done, |
| 13159 | // Label 847: @34850 |
| 13160 | GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(34895), // Rule ID 1609 // |
| 13161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13162 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns), |
| 13163 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13164 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13166 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13167 | // (intrinsic_wo_chain:{ *:[v4i16] } 3475:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 13168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv4i16), |
| 13169 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13170 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13172 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13173 | GIR_RootConstrainSelectedInstOperands, |
| 13174 | // GIR_Coverage, 1609, |
| 13175 | GIR_EraseRootFromParent_Done, |
| 13176 | // Label 848: @34895 |
| 13177 | GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(34940), // Rule ID 1610 // |
| 13178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13179 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns), |
| 13180 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13181 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 13182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13183 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13184 | // (intrinsic_wo_chain:{ *:[v2i32] } 3475:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 13185 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv2i32), |
| 13186 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13187 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13189 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13190 | GIR_RootConstrainSelectedInstOperands, |
| 13191 | // GIR_Coverage, 1610, |
| 13192 | GIR_EraseRootFromParent_Done, |
| 13193 | // Label 849: @34940 |
| 13194 | GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(34985), // Rule ID 1611 // |
| 13195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13196 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu), |
| 13197 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 13198 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13200 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13201 | // (intrinsic_wo_chain:{ *:[v8i8] } 3477:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 13202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv8i8), |
| 13203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13204 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13206 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13207 | GIR_RootConstrainSelectedInstOperands, |
| 13208 | // GIR_Coverage, 1611, |
| 13209 | GIR_EraseRootFromParent_Done, |
| 13210 | // Label 850: @34985 |
| 13211 | GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(35030), // Rule ID 1612 // |
| 13212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13213 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu), |
| 13214 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13215 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13217 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13218 | // (intrinsic_wo_chain:{ *:[v4i16] } 3477:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 13219 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv4i16), |
| 13220 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13221 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13223 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13224 | GIR_RootConstrainSelectedInstOperands, |
| 13225 | // GIR_Coverage, 1612, |
| 13226 | GIR_EraseRootFromParent_Done, |
| 13227 | // Label 851: @35030 |
| 13228 | GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(35075), // Rule ID 1613 // |
| 13229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13230 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu), |
| 13231 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13232 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 13233 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13234 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13235 | // (intrinsic_wo_chain:{ *:[v2i32] } 3477:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 13236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv2i32), |
| 13237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13238 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13240 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13241 | GIR_RootConstrainSelectedInstOperands, |
| 13242 | // GIR_Coverage, 1613, |
| 13243 | GIR_EraseRootFromParent_Done, |
| 13244 | // Label 852: @35075 |
| 13245 | GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(35120), // Rule ID 1614 // |
| 13246 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13247 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu), |
| 13248 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 13249 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13250 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13251 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13252 | // (intrinsic_wo_chain:{ *:[v8i8] } 3476:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 13253 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv8i8), |
| 13254 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13255 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13257 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13258 | GIR_RootConstrainSelectedInstOperands, |
| 13259 | // GIR_Coverage, 1614, |
| 13260 | GIR_EraseRootFromParent_Done, |
| 13261 | // Label 853: @35120 |
| 13262 | GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(35165), // Rule ID 1615 // |
| 13263 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13264 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu), |
| 13265 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13266 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13267 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13268 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13269 | // (intrinsic_wo_chain:{ *:[v4i16] } 3476:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 13270 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv4i16), |
| 13271 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13272 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13274 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13275 | GIR_RootConstrainSelectedInstOperands, |
| 13276 | // GIR_Coverage, 1615, |
| 13277 | GIR_EraseRootFromParent_Done, |
| 13278 | // Label 854: @35165 |
| 13279 | GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(35210), // Rule ID 1616 // |
| 13280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13281 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu), |
| 13282 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13283 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 13284 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13285 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13286 | // (intrinsic_wo_chain:{ *:[v2i32] } 3476:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 13287 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv2i32), |
| 13288 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13289 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13291 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13292 | GIR_RootConstrainSelectedInstOperands, |
| 13293 | // GIR_Coverage, 1616, |
| 13294 | GIR_EraseRootFromParent_Done, |
| 13295 | // Label 855: @35210 |
| 13296 | GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(35246), // Rule ID 1639 // |
| 13297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13298 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 13299 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13300 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13301 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13302 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13303 | // (intrinsic_wo_chain:{ *:[v2i32] } 3420:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 13304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDf), |
| 13305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13306 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13307 | GIR_RootConstrainSelectedInstOperands, |
| 13308 | // GIR_Coverage, 1639, |
| 13309 | GIR_EraseRootFromParent_Done, |
| 13310 | // Label 856: @35246 |
| 13311 | GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(35282), // Rule ID 1640 // |
| 13312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13313 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 13314 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13315 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13317 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13318 | // (intrinsic_wo_chain:{ *:[v4i32] } 3420:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 13319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQf), |
| 13320 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13321 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13322 | GIR_RootConstrainSelectedInstOperands, |
| 13323 | // GIR_Coverage, 1640, |
| 13324 | GIR_EraseRootFromParent_Done, |
| 13325 | // Label 857: @35282 |
| 13326 | GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(35318), // Rule ID 1641 // |
| 13327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13328 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 13329 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13330 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13332 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13333 | // (intrinsic_wo_chain:{ *:[v2i32] } 3421:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 13334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDf), |
| 13335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13336 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13337 | GIR_RootConstrainSelectedInstOperands, |
| 13338 | // GIR_Coverage, 1641, |
| 13339 | GIR_EraseRootFromParent_Done, |
| 13340 | // Label 858: @35318 |
| 13341 | GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(35354), // Rule ID 1642 // |
| 13342 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13343 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 13344 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13345 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13346 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13347 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13348 | // (intrinsic_wo_chain:{ *:[v4i32] } 3421:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 13349 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQf), |
| 13350 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13351 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13352 | GIR_RootConstrainSelectedInstOperands, |
| 13353 | // GIR_Coverage, 1642, |
| 13354 | GIR_EraseRootFromParent_Done, |
| 13355 | // Label 859: @35354 |
| 13356 | GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(35390), // Rule ID 1643 // |
| 13357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13358 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 13359 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13360 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13361 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13362 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13363 | // (intrinsic_wo_chain:{ *:[v4i16] } 3420:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 13364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDh), |
| 13365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13366 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13367 | GIR_RootConstrainSelectedInstOperands, |
| 13368 | // GIR_Coverage, 1643, |
| 13369 | GIR_EraseRootFromParent_Done, |
| 13370 | // Label 860: @35390 |
| 13371 | GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(35426), // Rule ID 1644 // |
| 13372 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13373 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 13374 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13375 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13376 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13377 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13378 | // (intrinsic_wo_chain:{ *:[v8i16] } 3420:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 13379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQh), |
| 13380 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13381 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13382 | GIR_RootConstrainSelectedInstOperands, |
| 13383 | // GIR_Coverage, 1644, |
| 13384 | GIR_EraseRootFromParent_Done, |
| 13385 | // Label 861: @35426 |
| 13386 | GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(35462), // Rule ID 1645 // |
| 13387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13388 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 13389 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13390 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13391 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13392 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13393 | // (intrinsic_wo_chain:{ *:[v4i16] } 3421:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 13394 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDh), |
| 13395 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13396 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13397 | GIR_RootConstrainSelectedInstOperands, |
| 13398 | // GIR_Coverage, 1645, |
| 13399 | GIR_EraseRootFromParent_Done, |
| 13400 | // Label 862: @35462 |
| 13401 | GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(35498), // Rule ID 1646 // |
| 13402 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13403 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 13404 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13405 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13407 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13408 | // (intrinsic_wo_chain:{ *:[v8i16] } 3421:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 13409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQh), |
| 13410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13411 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13412 | GIR_RootConstrainSelectedInstOperands, |
| 13413 | // GIR_Coverage, 1646, |
| 13414 | GIR_EraseRootFromParent_Done, |
| 13415 | // Label 863: @35498 |
| 13416 | GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(35534), // Rule ID 1647 // |
| 13417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13418 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 13419 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13420 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13421 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13422 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13423 | // (intrinsic_wo_chain:{ *:[v2i32] } 3432:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 13424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDf), |
| 13425 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13426 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13427 | GIR_RootConstrainSelectedInstOperands, |
| 13428 | // GIR_Coverage, 1647, |
| 13429 | GIR_EraseRootFromParent_Done, |
| 13430 | // Label 864: @35534 |
| 13431 | GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(35570), // Rule ID 1648 // |
| 13432 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13433 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 13434 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13435 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13436 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13437 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13438 | // (intrinsic_wo_chain:{ *:[v4i32] } 3432:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 13439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQf), |
| 13440 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13441 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13442 | GIR_RootConstrainSelectedInstOperands, |
| 13443 | // GIR_Coverage, 1648, |
| 13444 | GIR_EraseRootFromParent_Done, |
| 13445 | // Label 865: @35570 |
| 13446 | GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(35606), // Rule ID 1649 // |
| 13447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13448 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 13449 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13450 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13451 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13452 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13453 | // (intrinsic_wo_chain:{ *:[v2i32] } 3433:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 13454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDf), |
| 13455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13456 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13457 | GIR_RootConstrainSelectedInstOperands, |
| 13458 | // GIR_Coverage, 1649, |
| 13459 | GIR_EraseRootFromParent_Done, |
| 13460 | // Label 866: @35606 |
| 13461 | GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(35642), // Rule ID 1650 // |
| 13462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13463 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 13464 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13465 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13466 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13467 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13468 | // (intrinsic_wo_chain:{ *:[v4i32] } 3433:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 13469 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQf), |
| 13470 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13471 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13472 | GIR_RootConstrainSelectedInstOperands, |
| 13473 | // GIR_Coverage, 1650, |
| 13474 | GIR_EraseRootFromParent_Done, |
| 13475 | // Label 867: @35642 |
| 13476 | GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(35678), // Rule ID 1651 // |
| 13477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13478 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 13479 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13480 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13482 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13483 | // (intrinsic_wo_chain:{ *:[v4i16] } 3432:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 13484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDh), |
| 13485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13486 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13487 | GIR_RootConstrainSelectedInstOperands, |
| 13488 | // GIR_Coverage, 1651, |
| 13489 | GIR_EraseRootFromParent_Done, |
| 13490 | // Label 868: @35678 |
| 13491 | GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(35714), // Rule ID 1652 // |
| 13492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13493 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 13494 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13495 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13496 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13497 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13498 | // (intrinsic_wo_chain:{ *:[v8i16] } 3432:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 13499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQh), |
| 13500 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13501 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13502 | GIR_RootConstrainSelectedInstOperands, |
| 13503 | // GIR_Coverage, 1652, |
| 13504 | GIR_EraseRootFromParent_Done, |
| 13505 | // Label 869: @35714 |
| 13506 | GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(35750), // Rule ID 1653 // |
| 13507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13508 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 13509 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13510 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13511 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13512 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13513 | // (intrinsic_wo_chain:{ *:[v4i16] } 3433:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 13514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDh), |
| 13515 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13516 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13517 | GIR_RootConstrainSelectedInstOperands, |
| 13518 | // GIR_Coverage, 1653, |
| 13519 | GIR_EraseRootFromParent_Done, |
| 13520 | // Label 870: @35750 |
| 13521 | GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(35786), // Rule ID 1654 // |
| 13522 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13523 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 13524 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13525 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13526 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13527 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13528 | // (intrinsic_wo_chain:{ *:[v8i16] } 3433:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 13529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQh), |
| 13530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13531 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13532 | GIR_RootConstrainSelectedInstOperands, |
| 13533 | // GIR_Coverage, 1654, |
| 13534 | GIR_EraseRootFromParent_Done, |
| 13535 | // Label 871: @35786 |
| 13536 | GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(35822), // Rule ID 1655 // |
| 13537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13538 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 13539 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13540 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13541 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13542 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13543 | // (intrinsic_wo_chain:{ *:[v2i32] } 3434:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 13544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDf), |
| 13545 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13546 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13547 | GIR_RootConstrainSelectedInstOperands, |
| 13548 | // GIR_Coverage, 1655, |
| 13549 | GIR_EraseRootFromParent_Done, |
| 13550 | // Label 872: @35822 |
| 13551 | GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(35858), // Rule ID 1656 // |
| 13552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13553 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 13554 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13555 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13556 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13557 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13558 | // (intrinsic_wo_chain:{ *:[v4i32] } 3434:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 13559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQf), |
| 13560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13561 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13562 | GIR_RootConstrainSelectedInstOperands, |
| 13563 | // GIR_Coverage, 1656, |
| 13564 | GIR_EraseRootFromParent_Done, |
| 13565 | // Label 873: @35858 |
| 13566 | GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(35894), // Rule ID 1657 // |
| 13567 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13568 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 13569 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13570 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13571 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13572 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13573 | // (intrinsic_wo_chain:{ *:[v2i32] } 3435:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 13574 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDf), |
| 13575 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13576 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13577 | GIR_RootConstrainSelectedInstOperands, |
| 13578 | // GIR_Coverage, 1657, |
| 13579 | GIR_EraseRootFromParent_Done, |
| 13580 | // Label 874: @35894 |
| 13581 | GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(35930), // Rule ID 1658 // |
| 13582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13583 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 13584 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13585 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13586 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13587 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13588 | // (intrinsic_wo_chain:{ *:[v4i32] } 3435:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 13589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQf), |
| 13590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13591 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13592 | GIR_RootConstrainSelectedInstOperands, |
| 13593 | // GIR_Coverage, 1658, |
| 13594 | GIR_EraseRootFromParent_Done, |
| 13595 | // Label 875: @35930 |
| 13596 | GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(35966), // Rule ID 1659 // |
| 13597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13598 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 13599 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13600 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13601 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13602 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13603 | // (intrinsic_wo_chain:{ *:[v4i16] } 3434:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 13604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDh), |
| 13605 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13606 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13607 | GIR_RootConstrainSelectedInstOperands, |
| 13608 | // GIR_Coverage, 1659, |
| 13609 | GIR_EraseRootFromParent_Done, |
| 13610 | // Label 876: @35966 |
| 13611 | GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(36002), // Rule ID 1660 // |
| 13612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13613 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 13614 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13615 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13616 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13617 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13618 | // (intrinsic_wo_chain:{ *:[v8i16] } 3434:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 13619 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQh), |
| 13620 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13621 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13622 | GIR_RootConstrainSelectedInstOperands, |
| 13623 | // GIR_Coverage, 1660, |
| 13624 | GIR_EraseRootFromParent_Done, |
| 13625 | // Label 877: @36002 |
| 13626 | GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(36038), // Rule ID 1661 // |
| 13627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13628 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 13629 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13630 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13631 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13632 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13633 | // (intrinsic_wo_chain:{ *:[v4i16] } 3435:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 13634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDh), |
| 13635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13636 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13637 | GIR_RootConstrainSelectedInstOperands, |
| 13638 | // GIR_Coverage, 1661, |
| 13639 | GIR_EraseRootFromParent_Done, |
| 13640 | // Label 878: @36038 |
| 13641 | GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(36074), // Rule ID 1662 // |
| 13642 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13643 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 13644 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13645 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13646 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13647 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13648 | // (intrinsic_wo_chain:{ *:[v8i16] } 3435:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 13649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQh), |
| 13650 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13651 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13652 | GIR_RootConstrainSelectedInstOperands, |
| 13653 | // GIR_Coverage, 1662, |
| 13654 | GIR_EraseRootFromParent_Done, |
| 13655 | // Label 879: @36074 |
| 13656 | GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(36110), // Rule ID 1663 // |
| 13657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13658 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 13659 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13660 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13661 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13662 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13663 | // (intrinsic_wo_chain:{ *:[v2i32] } 3430:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 13664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDf), |
| 13665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13666 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13667 | GIR_RootConstrainSelectedInstOperands, |
| 13668 | // GIR_Coverage, 1663, |
| 13669 | GIR_EraseRootFromParent_Done, |
| 13670 | // Label 880: @36110 |
| 13671 | GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(36146), // Rule ID 1664 // |
| 13672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13673 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 13674 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13675 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13677 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13678 | // (intrinsic_wo_chain:{ *:[v4i32] } 3430:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 13679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQf), |
| 13680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13681 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13682 | GIR_RootConstrainSelectedInstOperands, |
| 13683 | // GIR_Coverage, 1664, |
| 13684 | GIR_EraseRootFromParent_Done, |
| 13685 | // Label 881: @36146 |
| 13686 | GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(36182), // Rule ID 1665 // |
| 13687 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13688 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 13689 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13690 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13691 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13692 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13693 | // (intrinsic_wo_chain:{ *:[v2i32] } 3431:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 13694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDf), |
| 13695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13696 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13697 | GIR_RootConstrainSelectedInstOperands, |
| 13698 | // GIR_Coverage, 1665, |
| 13699 | GIR_EraseRootFromParent_Done, |
| 13700 | // Label 882: @36182 |
| 13701 | GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(36218), // Rule ID 1666 // |
| 13702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13703 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 13704 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13705 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13707 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13708 | // (intrinsic_wo_chain:{ *:[v4i32] } 3431:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 13709 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQf), |
| 13710 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13711 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13712 | GIR_RootConstrainSelectedInstOperands, |
| 13713 | // GIR_Coverage, 1666, |
| 13714 | GIR_EraseRootFromParent_Done, |
| 13715 | // Label 883: @36218 |
| 13716 | GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(36254), // Rule ID 1667 // |
| 13717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13718 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 13719 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13720 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13721 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13722 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13723 | // (intrinsic_wo_chain:{ *:[v4i16] } 3430:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 13724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDh), |
| 13725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13726 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13727 | GIR_RootConstrainSelectedInstOperands, |
| 13728 | // GIR_Coverage, 1667, |
| 13729 | GIR_EraseRootFromParent_Done, |
| 13730 | // Label 884: @36254 |
| 13731 | GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(36290), // Rule ID 1668 // |
| 13732 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13733 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 13734 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13735 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13736 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13737 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13738 | // (intrinsic_wo_chain:{ *:[v8i16] } 3430:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 13739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQh), |
| 13740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13741 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13742 | GIR_RootConstrainSelectedInstOperands, |
| 13743 | // GIR_Coverage, 1668, |
| 13744 | GIR_EraseRootFromParent_Done, |
| 13745 | // Label 885: @36290 |
| 13746 | GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(36326), // Rule ID 1669 // |
| 13747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13748 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 13749 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13750 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13751 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13752 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13753 | // (intrinsic_wo_chain:{ *:[v4i16] } 3431:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 13754 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDh), |
| 13755 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13756 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13757 | GIR_RootConstrainSelectedInstOperands, |
| 13758 | // GIR_Coverage, 1669, |
| 13759 | GIR_EraseRootFromParent_Done, |
| 13760 | // Label 886: @36326 |
| 13761 | GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(36362), // Rule ID 1670 // |
| 13762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13763 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 13764 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13765 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13767 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13768 | // (intrinsic_wo_chain:{ *:[v8i16] } 3431:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 13769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQh), |
| 13770 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13771 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13772 | GIR_RootConstrainSelectedInstOperands, |
| 13773 | // GIR_Coverage, 1670, |
| 13774 | GIR_EraseRootFromParent_Done, |
| 13775 | // Label 887: @36362 |
| 13776 | GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(36407), // Rule ID 1687 // |
| 13777 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16_HasNEON), |
| 13778 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2hf), |
| 13779 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13780 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13781 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13782 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13783 | // (intrinsic_wo_chain:{ *:[v4i16] } 3426:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm) |
| 13784 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h), |
| 13785 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13786 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13788 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13789 | GIR_RootConstrainSelectedInstOperands, |
| 13790 | // GIR_Coverage, 1687, |
| 13791 | GIR_EraseRootFromParent_Done, |
| 13792 | // Label 888: @36407 |
| 13793 | GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(36452), // Rule ID 1688 // |
| 13794 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16_HasNEON), |
| 13795 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvthf2fp), |
| 13796 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13797 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13798 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13799 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13800 | // (intrinsic_wo_chain:{ *:[v4f32] } 3429:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm) |
| 13801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f), |
| 13802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13803 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13805 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13806 | GIR_RootConstrainSelectedInstOperands, |
| 13807 | // GIR_Coverage, 1688, |
| 13808 | GIR_EraseRootFromParent_Done, |
| 13809 | // Label 889: @36452 |
| 13810 | GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(36488), // Rule ID 1710 // |
| 13811 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13812 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 13813 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13814 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13815 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13816 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13817 | // (intrinsic_wo_chain:{ *:[v2f32] } 3500:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 13818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDf), |
| 13819 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13820 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13821 | GIR_RootConstrainSelectedInstOperands, |
| 13822 | // GIR_Coverage, 1710, |
| 13823 | GIR_EraseRootFromParent_Done, |
| 13824 | // Label 890: @36488 |
| 13825 | GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(36524), // Rule ID 1711 // |
| 13826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13827 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 13828 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13829 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13831 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13832 | // (intrinsic_wo_chain:{ *:[v4f32] } 3500:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 13833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQf), |
| 13834 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13835 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13836 | GIR_RootConstrainSelectedInstOperands, |
| 13837 | // GIR_Coverage, 1711, |
| 13838 | GIR_EraseRootFromParent_Done, |
| 13839 | // Label 891: @36524 |
| 13840 | GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(36560), // Rule ID 1712 // |
| 13841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13842 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 13843 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13844 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13846 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13847 | // (intrinsic_wo_chain:{ *:[v4f16] } 3500:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 13848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDh), |
| 13849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13850 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13851 | GIR_RootConstrainSelectedInstOperands, |
| 13852 | // GIR_Coverage, 1712, |
| 13853 | GIR_EraseRootFromParent_Done, |
| 13854 | // Label 892: @36560 |
| 13855 | GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(36596), // Rule ID 1713 // |
| 13856 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13857 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 13858 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13859 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13860 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13861 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13862 | // (intrinsic_wo_chain:{ *:[v8f16] } 3500:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 13863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQh), |
| 13864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13865 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13866 | GIR_RootConstrainSelectedInstOperands, |
| 13867 | // GIR_Coverage, 1713, |
| 13868 | GIR_EraseRootFromParent_Done, |
| 13869 | // Label 893: @36596 |
| 13870 | GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(36632), // Rule ID 1714 // |
| 13871 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13872 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintx), |
| 13873 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13874 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13876 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13877 | // (intrinsic_wo_chain:{ *:[v2f32] } 3502:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 13878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDf), |
| 13879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13880 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13881 | GIR_RootConstrainSelectedInstOperands, |
| 13882 | // GIR_Coverage, 1714, |
| 13883 | GIR_EraseRootFromParent_Done, |
| 13884 | // Label 894: @36632 |
| 13885 | GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(36668), // Rule ID 1715 // |
| 13886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13887 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintx), |
| 13888 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13889 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13891 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13892 | // (intrinsic_wo_chain:{ *:[v4f32] } 3502:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 13893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQf), |
| 13894 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13895 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13896 | GIR_RootConstrainSelectedInstOperands, |
| 13897 | // GIR_Coverage, 1715, |
| 13898 | GIR_EraseRootFromParent_Done, |
| 13899 | // Label 895: @36668 |
| 13900 | GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(36704), // Rule ID 1716 // |
| 13901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13902 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintx), |
| 13903 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13904 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13905 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13906 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13907 | // (intrinsic_wo_chain:{ *:[v4f16] } 3502:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 13908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDh), |
| 13909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13910 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13911 | GIR_RootConstrainSelectedInstOperands, |
| 13912 | // GIR_Coverage, 1716, |
| 13913 | GIR_EraseRootFromParent_Done, |
| 13914 | // Label 896: @36704 |
| 13915 | GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(36740), // Rule ID 1717 // |
| 13916 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13917 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintx), |
| 13918 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13919 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13921 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13922 | // (intrinsic_wo_chain:{ *:[v8f16] } 3502:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 13923 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQh), |
| 13924 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13925 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13926 | GIR_RootConstrainSelectedInstOperands, |
| 13927 | // GIR_Coverage, 1717, |
| 13928 | GIR_EraseRootFromParent_Done, |
| 13929 | // Label 897: @36740 |
| 13930 | GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(36776), // Rule ID 1718 // |
| 13931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13932 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrinta), |
| 13933 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13934 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13936 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13937 | // (intrinsic_wo_chain:{ *:[v2f32] } 3498:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 13938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTANDf), |
| 13939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13940 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13941 | GIR_RootConstrainSelectedInstOperands, |
| 13942 | // GIR_Coverage, 1718, |
| 13943 | GIR_EraseRootFromParent_Done, |
| 13944 | // Label 898: @36776 |
| 13945 | GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(36812), // Rule ID 1719 // |
| 13946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13947 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrinta), |
| 13948 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13949 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13950 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13951 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13952 | // (intrinsic_wo_chain:{ *:[v4f32] } 3498:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 13953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTANQf), |
| 13954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13955 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13956 | GIR_RootConstrainSelectedInstOperands, |
| 13957 | // GIR_Coverage, 1719, |
| 13958 | GIR_EraseRootFromParent_Done, |
| 13959 | // Label 899: @36812 |
| 13960 | GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(36848), // Rule ID 1720 // |
| 13961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13962 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrinta), |
| 13963 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13964 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13965 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13966 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13967 | // (intrinsic_wo_chain:{ *:[v4f16] } 3498:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 13968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTANDh), |
| 13969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13970 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13971 | GIR_RootConstrainSelectedInstOperands, |
| 13972 | // GIR_Coverage, 1720, |
| 13973 | GIR_EraseRootFromParent_Done, |
| 13974 | // Label 900: @36848 |
| 13975 | GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(36884), // Rule ID 1721 // |
| 13976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13977 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrinta), |
| 13978 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13979 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13980 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13981 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13982 | // (intrinsic_wo_chain:{ *:[v8f16] } 3498:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 13983 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTANQh), |
| 13984 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13985 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13986 | GIR_RootConstrainSelectedInstOperands, |
| 13987 | // GIR_Coverage, 1721, |
| 13988 | GIR_EraseRootFromParent_Done, |
| 13989 | // Label 901: @36884 |
| 13990 | GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(36920), // Rule ID 1722 // |
| 13991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13992 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintz), |
| 13993 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13994 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13996 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13997 | // (intrinsic_wo_chain:{ *:[v2f32] } 3503:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 13998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDf), |
| 13999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14000 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14001 | GIR_RootConstrainSelectedInstOperands, |
| 14002 | // GIR_Coverage, 1722, |
| 14003 | GIR_EraseRootFromParent_Done, |
| 14004 | // Label 902: @36920 |
| 14005 | GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(36956), // Rule ID 1723 // |
| 14006 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14007 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintz), |
| 14008 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14009 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14011 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14012 | // (intrinsic_wo_chain:{ *:[v4f32] } 3503:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 14013 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQf), |
| 14014 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14015 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14016 | GIR_RootConstrainSelectedInstOperands, |
| 14017 | // GIR_Coverage, 1723, |
| 14018 | GIR_EraseRootFromParent_Done, |
| 14019 | // Label 903: @36956 |
| 14020 | GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(36992), // Rule ID 1724 // |
| 14021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14022 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintz), |
| 14023 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14024 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14026 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14027 | // (intrinsic_wo_chain:{ *:[v4f16] } 3503:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 14028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDh), |
| 14029 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14030 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14031 | GIR_RootConstrainSelectedInstOperands, |
| 14032 | // GIR_Coverage, 1724, |
| 14033 | GIR_EraseRootFromParent_Done, |
| 14034 | // Label 904: @36992 |
| 14035 | GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(37028), // Rule ID 1725 // |
| 14036 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14037 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintz), |
| 14038 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14039 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14040 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14041 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14042 | // (intrinsic_wo_chain:{ *:[v8f16] } 3503:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 14043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQh), |
| 14044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14045 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14046 | GIR_RootConstrainSelectedInstOperands, |
| 14047 | // GIR_Coverage, 1725, |
| 14048 | GIR_EraseRootFromParent_Done, |
| 14049 | // Label 905: @37028 |
| 14050 | GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(37064), // Rule ID 1726 // |
| 14051 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14052 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintm), |
| 14053 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14054 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14056 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14057 | // (intrinsic_wo_chain:{ *:[v2f32] } 3499:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 14058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDf), |
| 14059 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14060 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14061 | GIR_RootConstrainSelectedInstOperands, |
| 14062 | // GIR_Coverage, 1726, |
| 14063 | GIR_EraseRootFromParent_Done, |
| 14064 | // Label 906: @37064 |
| 14065 | GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(37100), // Rule ID 1727 // |
| 14066 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14067 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintm), |
| 14068 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14069 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14070 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14071 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14072 | // (intrinsic_wo_chain:{ *:[v4f32] } 3499:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 14073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQf), |
| 14074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14075 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14076 | GIR_RootConstrainSelectedInstOperands, |
| 14077 | // GIR_Coverage, 1727, |
| 14078 | GIR_EraseRootFromParent_Done, |
| 14079 | // Label 907: @37100 |
| 14080 | GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(37136), // Rule ID 1728 // |
| 14081 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14082 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintm), |
| 14083 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14084 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14086 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14087 | // (intrinsic_wo_chain:{ *:[v4f16] } 3499:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 14088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDh), |
| 14089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14090 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14091 | GIR_RootConstrainSelectedInstOperands, |
| 14092 | // GIR_Coverage, 1728, |
| 14093 | GIR_EraseRootFromParent_Done, |
| 14094 | // Label 908: @37136 |
| 14095 | GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(37172), // Rule ID 1729 // |
| 14096 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14097 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintm), |
| 14098 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14099 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14101 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14102 | // (intrinsic_wo_chain:{ *:[v8f16] } 3499:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 14103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQh), |
| 14104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14105 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14106 | GIR_RootConstrainSelectedInstOperands, |
| 14107 | // GIR_Coverage, 1729, |
| 14108 | GIR_EraseRootFromParent_Done, |
| 14109 | // Label 909: @37172 |
| 14110 | GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(37208), // Rule ID 1730 // |
| 14111 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14112 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintp), |
| 14113 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14114 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14116 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14117 | // (intrinsic_wo_chain:{ *:[v2f32] } 3501:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 14118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDf), |
| 14119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14120 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14121 | GIR_RootConstrainSelectedInstOperands, |
| 14122 | // GIR_Coverage, 1730, |
| 14123 | GIR_EraseRootFromParent_Done, |
| 14124 | // Label 910: @37208 |
| 14125 | GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(37244), // Rule ID 1731 // |
| 14126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14127 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintp), |
| 14128 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14129 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14130 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14131 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14132 | // (intrinsic_wo_chain:{ *:[v4f32] } 3501:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 14133 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQf), |
| 14134 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14135 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14136 | GIR_RootConstrainSelectedInstOperands, |
| 14137 | // GIR_Coverage, 1731, |
| 14138 | GIR_EraseRootFromParent_Done, |
| 14139 | // Label 911: @37244 |
| 14140 | GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(37280), // Rule ID 1732 // |
| 14141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14142 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintp), |
| 14143 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14144 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14146 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14147 | // (intrinsic_wo_chain:{ *:[v4f16] } 3501:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 14148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDh), |
| 14149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14150 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14151 | GIR_RootConstrainSelectedInstOperands, |
| 14152 | // GIR_Coverage, 1732, |
| 14153 | GIR_EraseRootFromParent_Done, |
| 14154 | // Label 912: @37280 |
| 14155 | GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(37316), // Rule ID 1733 // |
| 14156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14157 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintp), |
| 14158 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14159 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14161 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14162 | // (intrinsic_wo_chain:{ *:[v8f16] } 3501:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 14163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQh), |
| 14164 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14165 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14166 | GIR_RootConstrainSelectedInstOperands, |
| 14167 | // GIR_Coverage, 1733, |
| 14168 | GIR_EraseRootFromParent_Done, |
| 14169 | // Label 913: @37316 |
| 14170 | GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(37352), // Rule ID 1736 // |
| 14171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 14172 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesimc), |
| 14173 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 14174 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14175 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14176 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14177 | // (intrinsic_wo_chain:{ *:[v16i8] } 3389:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 14178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESIMC), |
| 14179 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14180 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14181 | GIR_RootConstrainSelectedInstOperands, |
| 14182 | // GIR_Coverage, 1736, |
| 14183 | GIR_EraseRootFromParent_Done, |
| 14184 | // Label 914: @37352 |
| 14185 | GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(37388), // Rule ID 1737 // |
| 14186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 14187 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesmc), |
| 14188 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 14189 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14191 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14192 | // (intrinsic_wo_chain:{ *:[v16i8] } 3390:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 14193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESMC), |
| 14194 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14195 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14196 | GIR_RootConstrainSelectedInstOperands, |
| 14197 | // GIR_Coverage, 1737, |
| 14198 | GIR_EraseRootFromParent_Done, |
| 14199 | // Label 915: @37388 |
| 14200 | GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(37436), // Rule ID 1875 // |
| 14201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 14202 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16), |
| 14203 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14204 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14205 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14206 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 14207 | // (intrinsic_wo_chain:{ *:[i32] } 3589:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 14208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB16), |
| 14209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14210 | GIR_RootToRootCopy, /*OpIdx*/2, // Src |
| 14211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14213 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14214 | GIR_RootConstrainSelectedInstOperands, |
| 14215 | // GIR_Coverage, 1875, |
| 14216 | GIR_EraseRootFromParent_Done, |
| 14217 | // Label 916: @37436 |
| 14218 | GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(37484), // Rule ID 2106 // |
| 14219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 14220 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16), |
| 14221 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14222 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14223 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14224 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14225 | // (intrinsic_wo_chain:{ *:[i32] } 3589:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] }) |
| 14226 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB16), |
| 14227 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14228 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 14229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14231 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14232 | GIR_RootConstrainSelectedInstOperands, |
| 14233 | // GIR_Coverage, 2106, |
| 14234 | GIR_EraseRootFromParent_Done, |
| 14235 | // Label 917: @37484 |
| 14236 | GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(37548), // Rule ID 3763 // |
| 14237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 14238 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcls), |
| 14239 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 14240 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14242 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14243 | // (intrinsic_wo_chain:{ *:[v16i8] } 3271:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$val) => (MVE_VCLSs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) |
| 14244 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14245 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14246 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14247 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs8), |
| 14248 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14249 | GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 14250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14251 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14252 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14253 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14254 | GIR_RootConstrainSelectedInstOperands, |
| 14255 | // GIR_Coverage, 3763, |
| 14256 | GIR_EraseRootFromParent_Done, |
| 14257 | // Label 918: @37548 |
| 14258 | GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(37612), // Rule ID 3765 // |
| 14259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 14260 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcls), |
| 14261 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14262 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14263 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14264 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14265 | // (intrinsic_wo_chain:{ *:[v8i16] } 3271:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$val) => (MVE_VCLSs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) |
| 14266 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14267 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14268 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs16), |
| 14270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14271 | GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 14272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14273 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14274 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14275 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14276 | GIR_RootConstrainSelectedInstOperands, |
| 14277 | // GIR_Coverage, 3765, |
| 14278 | GIR_EraseRootFromParent_Done, |
| 14279 | // Label 919: @37612 |
| 14280 | GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(37676), // Rule ID 3767 // |
| 14281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 14282 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcls), |
| 14283 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14284 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14286 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14287 | // (intrinsic_wo_chain:{ *:[v4i32] } 3271:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$val) => (MVE_VCLSs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) |
| 14288 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14289 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14290 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14291 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs32), |
| 14292 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14293 | GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 14294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14295 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14296 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14297 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14298 | GIR_RootConstrainSelectedInstOperands, |
| 14299 | // GIR_Coverage, 3767, |
| 14300 | GIR_EraseRootFromParent_Done, |
| 14301 | // Label 920: @37676 |
| 14302 | GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(37740), // Rule ID 4079 // |
| 14303 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14304 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn), |
| 14305 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14306 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14307 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14308 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14309 | // (intrinsic_wo_chain:{ *:[v8f16] } 3353:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 14310 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14311 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14312 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N), |
| 14314 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14315 | GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 14316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14317 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14318 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14319 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14320 | GIR_RootConstrainSelectedInstOperands, |
| 14321 | // GIR_Coverage, 4079, |
| 14322 | GIR_EraseRootFromParent_Done, |
| 14323 | // Label 921: @37740 |
| 14324 | GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(37804), // Rule ID 4091 // |
| 14325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14326 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn), |
| 14327 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14328 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14329 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14330 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14331 | // (intrinsic_wo_chain:{ *:[v4f32] } 3353:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 14332 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14333 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14334 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14335 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N), |
| 14336 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14337 | GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 14338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14339 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14340 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14341 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14342 | GIR_RootConstrainSelectedInstOperands, |
| 14343 | // GIR_Coverage, 4091, |
| 14344 | GIR_EraseRootFromParent_Done, |
| 14345 | // Label 922: @37804 |
| 14346 | GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(37855), // Rule ID 4981 // |
| 14347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 14348 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp8), |
| 14349 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s1, |
| 14350 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14351 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 14352 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14353 | // (intrinsic_wo_chain:{ *:[v16i1] } 3279:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn) |
| 14354 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP8), |
| 14355 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 14356 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 14357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14358 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14359 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14360 | GIR_RootConstrainSelectedInstOperands, |
| 14361 | // GIR_Coverage, 4981, |
| 14362 | GIR_EraseRootFromParent_Done, |
| 14363 | // Label 923: @37855 |
| 14364 | GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(37906), // Rule ID 4983 // |
| 14365 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 14366 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp16), |
| 14367 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1, |
| 14368 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14369 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 14370 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14371 | // (intrinsic_wo_chain:{ *:[v8i1] } 3276:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn) |
| 14372 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP16), |
| 14373 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 14374 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 14375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14376 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14377 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14378 | GIR_RootConstrainSelectedInstOperands, |
| 14379 | // GIR_Coverage, 4983, |
| 14380 | GIR_EraseRootFromParent_Done, |
| 14381 | // Label 924: @37906 |
| 14382 | GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(37957), // Rule ID 4985 // |
| 14383 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 14384 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp32), |
| 14385 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1, |
| 14386 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14387 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 14388 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14389 | // (intrinsic_wo_chain:{ *:[v4i1] } 3277:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn) |
| 14390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP32), |
| 14391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 14392 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 14393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14394 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14395 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14396 | GIR_RootConstrainSelectedInstOperands, |
| 14397 | // GIR_Coverage, 4985, |
| 14398 | GIR_EraseRootFromParent_Done, |
| 14399 | // Label 925: @37957 |
| 14400 | GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(38008), // Rule ID 4987 // |
| 14401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 14402 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp64), |
| 14403 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s1, |
| 14404 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 14406 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14407 | // (intrinsic_wo_chain:{ *:[v2i1] } 3278:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP64:{ *:[v2i1] } rGPR:{ *:[i32] }:$Rn) |
| 14408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP64), |
| 14409 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 14410 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 14411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14412 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14413 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14414 | GIR_RootConstrainSelectedInstOperands, |
| 14415 | // GIR_Coverage, 4987, |
| 14416 | GIR_EraseRootFromParent_Done, |
| 14417 | // Label 926: @38008 |
| 14418 | GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(38054), // Rule ID 617 // |
| 14419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), |
| 14420 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tt), |
| 14421 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14423 | // MIs[0] Rn |
| 14424 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 14425 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14426 | // (intrinsic_wo_chain:{ *:[i32] } 3161:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 14427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TT), |
| 14428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 14429 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 14430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14431 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14432 | GIR_RootConstrainSelectedInstOperands, |
| 14433 | // GIR_Coverage, 617, |
| 14434 | GIR_EraseRootFromParent_Done, |
| 14435 | // Label 927: @38054 |
| 14436 | GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(38100), // Rule ID 618 // |
| 14437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), |
| 14438 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttt), |
| 14439 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14440 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14441 | // MIs[0] Rn |
| 14442 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 14443 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14444 | // (intrinsic_wo_chain:{ *:[i32] } 3164:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 14445 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTT), |
| 14446 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 14447 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 14448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14449 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14450 | GIR_RootConstrainSelectedInstOperands, |
| 14451 | // GIR_Coverage, 618, |
| 14452 | GIR_EraseRootFromParent_Done, |
| 14453 | // Label 928: @38100 |
| 14454 | GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(38146), // Rule ID 619 // |
| 14455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), |
| 14456 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tta), |
| 14457 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14459 | // MIs[0] Rn |
| 14460 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 14461 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14462 | // (intrinsic_wo_chain:{ *:[i32] } 3162:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 14463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTA), |
| 14464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 14465 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 14466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14467 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14468 | GIR_RootConstrainSelectedInstOperands, |
| 14469 | // GIR_Coverage, 619, |
| 14470 | GIR_EraseRootFromParent_Done, |
| 14471 | // Label 929: @38146 |
| 14472 | GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(38192), // Rule ID 620 // |
| 14473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), |
| 14474 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttat), |
| 14475 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14477 | // MIs[0] Rn |
| 14478 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 14479 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14480 | // (intrinsic_wo_chain:{ *:[i32] } 3163:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 14481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTAT), |
| 14482 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 14483 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 14484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14485 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14486 | GIR_RootConstrainSelectedInstOperands, |
| 14487 | // GIR_Coverage, 620, |
| 14488 | GIR_EraseRootFromParent_Done, |
| 14489 | // Label 930: @38192 |
| 14490 | GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(38324), // Rule ID 2711 // |
| 14491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14492 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1h), |
| 14493 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14494 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 14496 | // (intrinsic_wo_chain:{ *:[i32] } 3397:{ *:[iPTR] }, i32:{ *:[i32] }:$Rn) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f32] } (SHA1H:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$Rn, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }), GPR:{ *:[i32] }) |
| 14497 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 14498 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 14499 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, |
| 14500 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 14501 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14502 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14503 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 14504 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 14505 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 14506 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14507 | GIR_AddImm8, /*InsnID*/3, /*Imm*/0, |
| 14508 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 14509 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 14510 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 14511 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 14512 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::SHA1H), |
| 14513 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14514 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 14515 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 14516 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14517 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14518 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 14519 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 14520 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::MQPRRegClassID), |
| 14521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14522 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 14523 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14524 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 14525 | // GIR_Coverage, 2711, |
| 14526 | GIR_EraseRootFromParent_Done, |
| 14527 | // Label 931: @38324 |
| 14528 | GIM_Reject, |
| 14529 | // Label 795: @38325 |
| 14530 | GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(58791), |
| 14531 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 14532 | GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(38390), // Rule ID 2124 // |
| 14533 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 14534 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16), |
| 14535 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14536 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14537 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14539 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14540 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14541 | // (intrinsic_wo_chain:{ *:[i32] } 3613:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 14542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB16), |
| 14543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14544 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 14545 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 14546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14548 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14549 | GIR_RootConstrainSelectedInstOperands, |
| 14550 | // GIR_Coverage, 2124, |
| 14551 | GIR_EraseRootFromParent_Done, |
| 14552 | // Label 933: @38390 |
| 14553 | GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(38489), // Rule ID 1912 // |
| 14554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 14555 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 14556 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14557 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14558 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14559 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14560 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14561 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 14562 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 14563 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 14564 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14565 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14566 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14567 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 14568 | // MIs[2] Operand 1 |
| 14569 | // No operand predicates |
| 14570 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3] |
| 14571 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14572 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 14573 | // MIs[3] Operand 1 |
| 14574 | // No operand predicates |
| 14575 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 14576 | // (intrinsic_wo_chain:{ *:[i32] } 3608:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft) |
| 14577 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT), |
| 14578 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14579 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos |
| 14580 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 14581 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft |
| 14582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14583 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14584 | GIR_RootConstrainSelectedInstOperands, |
| 14585 | // GIR_Coverage, 1912, |
| 14586 | GIR_EraseRootFromParent_Done, |
| 14587 | // Label 934: @38489 |
| 14588 | GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(38588), // Rule ID 2161 // |
| 14589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 14590 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 14591 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14592 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14593 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14595 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14596 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 14597 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 14598 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 14599 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14600 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14601 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14602 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 14603 | // MIs[2] Operand 1 |
| 14604 | // No operand predicates |
| 14605 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3] |
| 14606 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14607 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 14608 | // MIs[3] Operand 1 |
| 14609 | // No operand predicates |
| 14610 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 14611 | // (intrinsic_wo_chain:{ *:[i32] } 3608:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft) |
| 14612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT), |
| 14613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14614 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos |
| 14615 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 14616 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft |
| 14617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14618 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14619 | GIR_RootConstrainSelectedInstOperands, |
| 14620 | // GIR_Coverage, 2161, |
| 14621 | GIR_EraseRootFromParent_Done, |
| 14622 | // Label 935: @38588 |
| 14623 | GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(38672), // Rule ID 5547 // |
| 14624 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 14625 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 14626 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14627 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14628 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14629 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14630 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14631 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 14632 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 14633 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 14634 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 14635 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14636 | // MIs[1] Rn |
| 14637 | GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 14638 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14639 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14640 | // (intrinsic_wo_chain:{ *:[i32] } 3531:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 3531:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn), GPRnopc:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 14641 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 14642 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14643 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 14644 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 14645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14646 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14647 | GIR_RootConstrainSelectedInstOperands, |
| 14648 | // GIR_Coverage, 5547, |
| 14649 | GIR_EraseRootFromParent_Done, |
| 14650 | // Label 936: @38672 |
| 14651 | GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(38756), // Rule ID 5804 // |
| 14652 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 14653 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 14654 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14655 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14656 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14657 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14658 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14659 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 14660 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 14661 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 14662 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 14663 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14664 | // MIs[1] Rn |
| 14665 | GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 14666 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14667 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14668 | // (intrinsic_wo_chain:{ *:[i32] } 3531:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 3531:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 14669 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 14670 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14671 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 14672 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 14673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14674 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14675 | GIR_RootConstrainSelectedInstOperands, |
| 14676 | // GIR_Coverage, 5804, |
| 14677 | GIR_EraseRootFromParent_Done, |
| 14678 | // Label 937: @38756 |
| 14679 | GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(38840), // Rule ID 109 // |
| 14680 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 14681 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 14682 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14683 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14684 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14686 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14687 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 14688 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 14689 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 14690 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 14691 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 14692 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14693 | // MIs[1] Rn |
| 14694 | GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 14695 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14696 | // (intrinsic_wo_chain:{ *:[i32] } 3531:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 3531:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 14697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 14698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14699 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 14700 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 14701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14702 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14703 | GIR_RootConstrainSelectedInstOperands, |
| 14704 | // GIR_Coverage, 109, |
| 14705 | GIR_EraseRootFromParent_Done, |
| 14706 | // Label 938: @38840 |
| 14707 | GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(38924), // Rule ID 110 // |
| 14708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 14709 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 14710 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14711 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14712 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14713 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14714 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14715 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 14716 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 14717 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 14718 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 14719 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 14720 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14721 | // MIs[1] Rn |
| 14722 | GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 14723 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14724 | // (intrinsic_wo_chain:{ *:[i32] } 3536:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 3531:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 14725 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB), |
| 14726 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14727 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 14728 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 14729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14730 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14731 | GIR_RootConstrainSelectedInstOperands, |
| 14732 | // GIR_Coverage, 110, |
| 14733 | GIR_EraseRootFromParent_Done, |
| 14734 | // Label 939: @38924 |
| 14735 | GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(39008), // Rule ID 2139 // |
| 14736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 14737 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 14738 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14739 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14740 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14741 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14742 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14743 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 14744 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 14745 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 14746 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 14747 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 14748 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14749 | // MIs[1] Rn |
| 14750 | GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 14751 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14752 | // (intrinsic_wo_chain:{ *:[i32] } 3531:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 3531:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 14753 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 14754 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14755 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 14756 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 14757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14758 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14759 | GIR_RootConstrainSelectedInstOperands, |
| 14760 | // GIR_Coverage, 2139, |
| 14761 | GIR_EraseRootFromParent_Done, |
| 14762 | // Label 940: @39008 |
| 14763 | GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(39092), // Rule ID 2140 // |
| 14764 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 14765 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 14766 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14767 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14768 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14769 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14770 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14771 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 14772 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 14773 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 14774 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 14775 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 14776 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14777 | // MIs[1] Rn |
| 14778 | GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 14779 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14780 | // (intrinsic_wo_chain:{ *:[i32] } 3536:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 3531:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 14781 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB), |
| 14782 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14783 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 14784 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 14785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14786 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14787 | GIR_RootConstrainSelectedInstOperands, |
| 14788 | // GIR_Coverage, 2140, |
| 14789 | GIR_EraseRootFromParent_Done, |
| 14790 | // Label 941: @39092 |
| 14791 | GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(39163), // Rule ID 4173 // |
| 14792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14793 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 14794 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14795 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14796 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 14797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14798 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 14799 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14800 | // (intrinsic_wo_chain:{ *:[v8i16] } 3287:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 14801 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14802 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14803 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16a), |
| 14805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14806 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 14807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14808 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14809 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14810 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14811 | GIR_RootConstrainSelectedInstOperands, |
| 14812 | // GIR_Coverage, 4173, |
| 14813 | GIR_EraseRootFromParent_Done, |
| 14814 | // Label 942: @39163 |
| 14815 | GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(39234), // Rule ID 4175 // |
| 14816 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14817 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 14818 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14819 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14820 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 14821 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14822 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 14823 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14824 | // (intrinsic_wo_chain:{ *:[v8i16] } 3291:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 14825 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14826 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14827 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16n), |
| 14829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14830 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 14831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14832 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14833 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14834 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14835 | GIR_RootConstrainSelectedInstOperands, |
| 14836 | // GIR_Coverage, 4175, |
| 14837 | GIR_EraseRootFromParent_Done, |
| 14838 | // Label 943: @39234 |
| 14839 | GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(39305), // Rule ID 4177 // |
| 14840 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14841 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 14842 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14843 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14844 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 14845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14846 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 14847 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14848 | // (intrinsic_wo_chain:{ *:[v8i16] } 3293:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 14849 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14850 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14851 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16p), |
| 14853 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14854 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 14855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14856 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14857 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14858 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14859 | GIR_RootConstrainSelectedInstOperands, |
| 14860 | // GIR_Coverage, 4177, |
| 14861 | GIR_EraseRootFromParent_Done, |
| 14862 | // Label 944: @39305 |
| 14863 | GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(39376), // Rule ID 4179 // |
| 14864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14865 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 14866 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14867 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14868 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 14869 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14870 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 14871 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14872 | // (intrinsic_wo_chain:{ *:[v8i16] } 3289:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 14873 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14874 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14875 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16m), |
| 14877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14878 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 14879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14880 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14881 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14882 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14883 | GIR_RootConstrainSelectedInstOperands, |
| 14884 | // GIR_Coverage, 4179, |
| 14885 | GIR_EraseRootFromParent_Done, |
| 14886 | // Label 945: @39376 |
| 14887 | GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(39447), // Rule ID 4181 // |
| 14888 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14889 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 14890 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14891 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14892 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 14893 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14894 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 14895 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14896 | // (intrinsic_wo_chain:{ *:[v8i16] } 3287:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 14897 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14898 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14899 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16a), |
| 14901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14902 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 14903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14904 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14905 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14906 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14907 | GIR_RootConstrainSelectedInstOperands, |
| 14908 | // GIR_Coverage, 4181, |
| 14909 | GIR_EraseRootFromParent_Done, |
| 14910 | // Label 946: @39447 |
| 14911 | GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(39518), // Rule ID 4183 // |
| 14912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14913 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 14914 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14915 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14916 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 14917 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14918 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 14919 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14920 | // (intrinsic_wo_chain:{ *:[v8i16] } 3291:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 14921 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14922 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14923 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16n), |
| 14925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14926 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 14927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14928 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14929 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14930 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14931 | GIR_RootConstrainSelectedInstOperands, |
| 14932 | // GIR_Coverage, 4183, |
| 14933 | GIR_EraseRootFromParent_Done, |
| 14934 | // Label 947: @39518 |
| 14935 | GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(39589), // Rule ID 4185 // |
| 14936 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14937 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 14938 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14939 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14940 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 14941 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14942 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 14943 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14944 | // (intrinsic_wo_chain:{ *:[v8i16] } 3293:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 14945 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14946 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14947 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16p), |
| 14949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14950 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 14951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14952 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14953 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14954 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14955 | GIR_RootConstrainSelectedInstOperands, |
| 14956 | // GIR_Coverage, 4185, |
| 14957 | GIR_EraseRootFromParent_Done, |
| 14958 | // Label 948: @39589 |
| 14959 | GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(39660), // Rule ID 4187 // |
| 14960 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14961 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 14962 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14963 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14964 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 14965 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14966 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 14967 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14968 | // (intrinsic_wo_chain:{ *:[v8i16] } 3289:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 14969 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14970 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14971 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16m), |
| 14973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14974 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 14975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14976 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14977 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14978 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14979 | GIR_RootConstrainSelectedInstOperands, |
| 14980 | // GIR_Coverage, 4187, |
| 14981 | GIR_EraseRootFromParent_Done, |
| 14982 | // Label 949: @39660 |
| 14983 | GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(39731), // Rule ID 4189 // |
| 14984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 14985 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 14986 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14987 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14988 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 14989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14990 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 14991 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14992 | // (intrinsic_wo_chain:{ *:[v4i32] } 3287:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 14993 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14994 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14995 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 14996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32a), |
| 14997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14998 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 14999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15000 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15001 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15002 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15003 | GIR_RootConstrainSelectedInstOperands, |
| 15004 | // GIR_Coverage, 4189, |
| 15005 | GIR_EraseRootFromParent_Done, |
| 15006 | // Label 950: @39731 |
| 15007 | GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(39802), // Rule ID 4191 // |
| 15008 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15009 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 15010 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15011 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15012 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15013 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15014 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 15015 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15016 | // (intrinsic_wo_chain:{ *:[v4i32] } 3291:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15017 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15018 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15019 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 15020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32n), |
| 15021 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15022 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15024 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15025 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15026 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15027 | GIR_RootConstrainSelectedInstOperands, |
| 15028 | // GIR_Coverage, 4191, |
| 15029 | GIR_EraseRootFromParent_Done, |
| 15030 | // Label 951: @39802 |
| 15031 | GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(39873), // Rule ID 4193 // |
| 15032 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15033 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 15034 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15035 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15036 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15037 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15038 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 15039 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15040 | // (intrinsic_wo_chain:{ *:[v4i32] } 3293:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15041 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15042 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15043 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 15044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32p), |
| 15045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15046 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15048 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15049 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15050 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15051 | GIR_RootConstrainSelectedInstOperands, |
| 15052 | // GIR_Coverage, 4193, |
| 15053 | GIR_EraseRootFromParent_Done, |
| 15054 | // Label 952: @39873 |
| 15055 | GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(39944), // Rule ID 4195 // |
| 15056 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15057 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 15058 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15059 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15060 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15061 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15062 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 15063 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15064 | // (intrinsic_wo_chain:{ *:[v4i32] } 3289:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15065 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15066 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15067 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 15068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32m), |
| 15069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15070 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15072 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15073 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15074 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15075 | GIR_RootConstrainSelectedInstOperands, |
| 15076 | // GIR_Coverage, 4195, |
| 15077 | GIR_EraseRootFromParent_Done, |
| 15078 | // Label 953: @39944 |
| 15079 | GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(40015), // Rule ID 4197 // |
| 15080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15081 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 15082 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15083 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15084 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15086 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 15087 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15088 | // (intrinsic_wo_chain:{ *:[v4i32] } 3287:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15089 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15090 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15091 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 15092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32a), |
| 15093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15094 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15096 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15097 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15098 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15099 | GIR_RootConstrainSelectedInstOperands, |
| 15100 | // GIR_Coverage, 4197, |
| 15101 | GIR_EraseRootFromParent_Done, |
| 15102 | // Label 954: @40015 |
| 15103 | GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(40086), // Rule ID 4199 // |
| 15104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15105 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 15106 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15107 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15108 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15109 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15110 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 15111 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15112 | // (intrinsic_wo_chain:{ *:[v4i32] } 3291:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15113 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15114 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15115 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 15116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32n), |
| 15117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15118 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15120 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15121 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15122 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15123 | GIR_RootConstrainSelectedInstOperands, |
| 15124 | // GIR_Coverage, 4199, |
| 15125 | GIR_EraseRootFromParent_Done, |
| 15126 | // Label 955: @40086 |
| 15127 | GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(40157), // Rule ID 4201 // |
| 15128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15129 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 15130 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15131 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15132 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15133 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15134 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 15135 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15136 | // (intrinsic_wo_chain:{ *:[v4i32] } 3293:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15137 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15138 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15139 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 15140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32p), |
| 15141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15142 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15144 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15145 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15146 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15147 | GIR_RootConstrainSelectedInstOperands, |
| 15148 | // GIR_Coverage, 4201, |
| 15149 | GIR_EraseRootFromParent_Done, |
| 15150 | // Label 956: @40157 |
| 15151 | GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(40228), // Rule ID 4203 // |
| 15152 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15153 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 15154 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15155 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15156 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15157 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15158 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 15159 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15160 | // (intrinsic_wo_chain:{ *:[v4i32] } 3289:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15161 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15162 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15163 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 15164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32m), |
| 15165 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15166 | GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15168 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15169 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15170 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15171 | GIR_RootConstrainSelectedInstOperands, |
| 15172 | // GIR_Coverage, 4203, |
| 15173 | GIR_EraseRootFromParent_Done, |
| 15174 | // Label 957: @40228 |
| 15175 | GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(40299), // Rule ID 4647 // |
| 15176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15177 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen), |
| 15178 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15179 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15180 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15181 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15182 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15183 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 15184 | // (intrinsic_wo_chain:{ *:[v4f32] } 3285:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf32f16bh:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm) |
| 15185 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15186 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15187 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 15188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16bh), |
| 15189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15190 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 15191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15192 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15193 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15194 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15195 | GIR_RootConstrainSelectedInstOperands, |
| 15196 | // GIR_Coverage, 4647, |
| 15197 | GIR_EraseRootFromParent_Done, |
| 15198 | // Label 958: @40299 |
| 15199 | GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(40370), // Rule ID 4653 // |
| 15200 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15201 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen), |
| 15202 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15203 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15204 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15205 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15206 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15207 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 15208 | // (intrinsic_wo_chain:{ *:[v4f32] } 3285:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf32f16th:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm) |
| 15209 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15210 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15211 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 15212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16th), |
| 15213 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15214 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 15215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15216 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15217 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15218 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15219 | GIR_RootConstrainSelectedInstOperands, |
| 15220 | // GIR_Coverage, 4653, |
| 15221 | GIR_EraseRootFromParent_Done, |
| 15222 | // Label 959: @40370 |
| 15223 | GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(40438), // Rule ID 1905 // |
| 15224 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 15225 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 15226 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15227 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15228 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15230 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15231 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15232 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15233 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 15234 | // MIs[1] Operand 1 |
| 15235 | // No operand predicates |
| 15236 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15237 | // (intrinsic_wo_chain:{ *:[i32] } 3608:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] }) |
| 15238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT), |
| 15239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15240 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 15241 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 15242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15244 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15245 | GIR_RootConstrainSelectedInstOperands, |
| 15246 | // GIR_Coverage, 1905, |
| 15247 | GIR_EraseRootFromParent_Done, |
| 15248 | // Label 960: @40438 |
| 15249 | GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(40503), // Rule ID 1909 // |
| 15250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 15251 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16), |
| 15252 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15253 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15254 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15256 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15257 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15258 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15259 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 15260 | // MIs[1] Operand 1 |
| 15261 | // No operand predicates |
| 15262 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15263 | // (intrinsic_wo_chain:{ *:[i32] } 3609:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a) |
| 15264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT16), |
| 15265 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15266 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 15267 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 15268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15269 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15270 | GIR_RootConstrainSelectedInstOperands, |
| 15271 | // GIR_Coverage, 1909, |
| 15272 | GIR_EraseRootFromParent_Done, |
| 15273 | // Label 961: @40503 |
| 15274 | GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(40571), // Rule ID 2156 // |
| 15275 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 15276 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 15277 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15278 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15279 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15280 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15281 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 15282 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15283 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15284 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 15285 | // MIs[1] Operand 1 |
| 15286 | // No operand predicates |
| 15287 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15288 | // (intrinsic_wo_chain:{ *:[i32] } 3608:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] }) |
| 15289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT), |
| 15290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15291 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 15292 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 15293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15295 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15296 | GIR_RootConstrainSelectedInstOperands, |
| 15297 | // GIR_Coverage, 2156, |
| 15298 | GIR_EraseRootFromParent_Done, |
| 15299 | // Label 962: @40571 |
| 15300 | GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(40636), // Rule ID 2158 // |
| 15301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 15302 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16), |
| 15303 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15304 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15305 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15307 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 15308 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15309 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15310 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 15311 | // MIs[1] Operand 1 |
| 15312 | // No operand predicates |
| 15313 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15314 | // (intrinsic_wo_chain:{ *:[i32] } 3609:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a) |
| 15315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT16), |
| 15316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15317 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 15318 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 15319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15320 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15321 | GIR_RootConstrainSelectedInstOperands, |
| 15322 | // GIR_Coverage, 2158, |
| 15323 | GIR_EraseRootFromParent_Done, |
| 15324 | // Label 963: @40636 |
| 15325 | GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(40717), // Rule ID 4043 // |
| 15326 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm), |
| 15327 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 15328 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15329 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15330 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15331 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15332 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15333 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15334 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 15335 | // MIs[1] Operand 1 |
| 15336 | // No operand predicates |
| 15337 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15338 | // (intrinsic_wo_chain:{ *:[v16i8] } 3346:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 15339 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15340 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15341 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 15342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms8), |
| 15343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15344 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 15345 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 15346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15347 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15348 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15349 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15350 | GIR_RootConstrainSelectedInstOperands, |
| 15351 | // GIR_Coverage, 4043, |
| 15352 | GIR_EraseRootFromParent_Done, |
| 15353 | // Label 964: @40717 |
| 15354 | GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(40798), // Rule ID 4045 // |
| 15355 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm), |
| 15356 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15357 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15358 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15359 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15360 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15361 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15362 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15363 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 15364 | // MIs[1] Operand 1 |
| 15365 | // No operand predicates |
| 15366 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15367 | // (intrinsic_wo_chain:{ *:[v8i16] } 3346:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 15368 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15369 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15370 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 15371 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms16), |
| 15372 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15373 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 15374 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 15375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15376 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15377 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15378 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15379 | GIR_RootConstrainSelectedInstOperands, |
| 15380 | // GIR_Coverage, 4045, |
| 15381 | GIR_EraseRootFromParent_Done, |
| 15382 | // Label 965: @40798 |
| 15383 | GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(40879), // Rule ID 4047 // |
| 15384 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm), |
| 15385 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15386 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15387 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15388 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15389 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15390 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15391 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15392 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 15393 | // MIs[1] Operand 1 |
| 15394 | // No operand predicates |
| 15395 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15396 | // (intrinsic_wo_chain:{ *:[v4i32] } 3346:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 15397 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15398 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15399 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 15400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms32), |
| 15401 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15402 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 15403 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 15404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15405 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15406 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15407 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15408 | GIR_RootConstrainSelectedInstOperands, |
| 15409 | // GIR_Coverage, 4047, |
| 15410 | GIR_EraseRootFromParent_Done, |
| 15411 | // Label 966: @40879 |
| 15412 | GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(40940), // Rule ID 1671 // |
| 15413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15414 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 15415 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15416 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15417 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15419 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15420 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15421 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15422 | // MIs[1] Operand 1 |
| 15423 | // No operand predicates |
| 15424 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15425 | // (intrinsic_wo_chain:{ *:[v2i32] } 3424:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsd), |
| 15427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15428 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15429 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15431 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15432 | GIR_RootConstrainSelectedInstOperands, |
| 15433 | // GIR_Coverage, 1671, |
| 15434 | GIR_EraseRootFromParent_Done, |
| 15435 | // Label 967: @40940 |
| 15436 | GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(41001), // Rule ID 1672 // |
| 15437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15438 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 15439 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15440 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15441 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15443 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15444 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15445 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15446 | // MIs[1] Operand 1 |
| 15447 | // No operand predicates |
| 15448 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15449 | // (intrinsic_wo_chain:{ *:[v2i32] } 3425:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xud), |
| 15451 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15452 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15453 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15455 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15456 | GIR_RootConstrainSelectedInstOperands, |
| 15457 | // GIR_Coverage, 1672, |
| 15458 | GIR_EraseRootFromParent_Done, |
| 15459 | // Label 968: @41001 |
| 15460 | GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(41062), // Rule ID 1673 // |
| 15461 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15462 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 15463 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15464 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15465 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15466 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15467 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15468 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15469 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15470 | // MIs[1] Operand 1 |
| 15471 | // No operand predicates |
| 15472 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15473 | // (intrinsic_wo_chain:{ *:[v2f32] } 3427:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fd), |
| 15475 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15476 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15477 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15479 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15480 | GIR_RootConstrainSelectedInstOperands, |
| 15481 | // GIR_Coverage, 1673, |
| 15482 | GIR_EraseRootFromParent_Done, |
| 15483 | // Label 969: @41062 |
| 15484 | GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(41123), // Rule ID 1674 // |
| 15485 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15486 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 15487 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 15488 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15489 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15490 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15491 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15492 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15493 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15494 | // MIs[1] Operand 1 |
| 15495 | // No operand predicates |
| 15496 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15497 | // (intrinsic_wo_chain:{ *:[v2f32] } 3428:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fd), |
| 15499 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15500 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15501 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15503 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15504 | GIR_RootConstrainSelectedInstOperands, |
| 15505 | // GIR_Coverage, 1674, |
| 15506 | GIR_EraseRootFromParent_Done, |
| 15507 | // Label 970: @41123 |
| 15508 | GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(41184), // Rule ID 1675 // |
| 15509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 15510 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 15511 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15512 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15513 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15515 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15516 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15517 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15518 | // MIs[1] Operand 1 |
| 15519 | // No operand predicates |
| 15520 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15521 | // (intrinsic_wo_chain:{ *:[v4i16] } 3424:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15522 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsd), |
| 15523 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15524 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15525 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15527 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15528 | GIR_RootConstrainSelectedInstOperands, |
| 15529 | // GIR_Coverage, 1675, |
| 15530 | GIR_EraseRootFromParent_Done, |
| 15531 | // Label 971: @41184 |
| 15532 | GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(41245), // Rule ID 1676 // |
| 15533 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 15534 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 15535 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15536 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15537 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15539 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15540 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15541 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15542 | // MIs[1] Operand 1 |
| 15543 | // No operand predicates |
| 15544 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15545 | // (intrinsic_wo_chain:{ *:[v4i16] } 3425:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xud), |
| 15547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15548 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15549 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15551 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15552 | GIR_RootConstrainSelectedInstOperands, |
| 15553 | // GIR_Coverage, 1676, |
| 15554 | GIR_EraseRootFromParent_Done, |
| 15555 | // Label 972: @41245 |
| 15556 | GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(41306), // Rule ID 1677 // |
| 15557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 15558 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 15559 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15560 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15561 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15562 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15563 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15564 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15565 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15566 | // MIs[1] Operand 1 |
| 15567 | // No operand predicates |
| 15568 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15569 | // (intrinsic_wo_chain:{ *:[v4f16] } 3427:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hd), |
| 15571 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15572 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15573 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15575 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15576 | GIR_RootConstrainSelectedInstOperands, |
| 15577 | // GIR_Coverage, 1677, |
| 15578 | GIR_EraseRootFromParent_Done, |
| 15579 | // Label 973: @41306 |
| 15580 | GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(41367), // Rule ID 1678 // |
| 15581 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 15582 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 15583 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15584 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15585 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15586 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15587 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15588 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15589 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15590 | // MIs[1] Operand 1 |
| 15591 | // No operand predicates |
| 15592 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15593 | // (intrinsic_wo_chain:{ *:[v4f16] } 3428:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15594 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hd), |
| 15595 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15596 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15597 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15599 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15600 | GIR_RootConstrainSelectedInstOperands, |
| 15601 | // GIR_Coverage, 1678, |
| 15602 | GIR_EraseRootFromParent_Done, |
| 15603 | // Label 974: @41367 |
| 15604 | GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(41428), // Rule ID 1679 // |
| 15605 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15606 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 15607 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15608 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15609 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15610 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15611 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15612 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15613 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15614 | // MIs[1] Operand 1 |
| 15615 | // No operand predicates |
| 15616 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15617 | // (intrinsic_wo_chain:{ *:[v4i32] } 3424:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsq), |
| 15619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15620 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15621 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15623 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15624 | GIR_RootConstrainSelectedInstOperands, |
| 15625 | // GIR_Coverage, 1679, |
| 15626 | GIR_EraseRootFromParent_Done, |
| 15627 | // Label 975: @41428 |
| 15628 | GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(41489), // Rule ID 1680 // |
| 15629 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15630 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 15631 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15632 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15633 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15635 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15636 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15637 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15638 | // MIs[1] Operand 1 |
| 15639 | // No operand predicates |
| 15640 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15641 | // (intrinsic_wo_chain:{ *:[v4i32] } 3425:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xuq), |
| 15643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15644 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15645 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15647 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15648 | GIR_RootConstrainSelectedInstOperands, |
| 15649 | // GIR_Coverage, 1680, |
| 15650 | GIR_EraseRootFromParent_Done, |
| 15651 | // Label 976: @41489 |
| 15652 | GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(41550), // Rule ID 1681 // |
| 15653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15654 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 15655 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15656 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15657 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15659 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15660 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15661 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15662 | // MIs[1] Operand 1 |
| 15663 | // No operand predicates |
| 15664 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15665 | // (intrinsic_wo_chain:{ *:[v4f32] } 3427:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fq), |
| 15667 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15668 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15669 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15671 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15672 | GIR_RootConstrainSelectedInstOperands, |
| 15673 | // GIR_Coverage, 1681, |
| 15674 | GIR_EraseRootFromParent_Done, |
| 15675 | // Label 977: @41550 |
| 15676 | GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(41611), // Rule ID 1682 // |
| 15677 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15678 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 15679 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15680 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15681 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15683 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15684 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15685 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15686 | // MIs[1] Operand 1 |
| 15687 | // No operand predicates |
| 15688 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15689 | // (intrinsic_wo_chain:{ *:[v4f32] } 3428:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fq), |
| 15691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15692 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15693 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15695 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15696 | GIR_RootConstrainSelectedInstOperands, |
| 15697 | // GIR_Coverage, 1682, |
| 15698 | GIR_EraseRootFromParent_Done, |
| 15699 | // Label 978: @41611 |
| 15700 | GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(41672), // Rule ID 1683 // |
| 15701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 15702 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 15703 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15704 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15705 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15707 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15708 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15709 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15710 | // MIs[1] Operand 1 |
| 15711 | // No operand predicates |
| 15712 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15713 | // (intrinsic_wo_chain:{ *:[v8i16] } 3424:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsq), |
| 15715 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15716 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15717 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15719 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15720 | GIR_RootConstrainSelectedInstOperands, |
| 15721 | // GIR_Coverage, 1683, |
| 15722 | GIR_EraseRootFromParent_Done, |
| 15723 | // Label 979: @41672 |
| 15724 | GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(41733), // Rule ID 1684 // |
| 15725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 15726 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 15727 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15728 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15729 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15730 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15731 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15732 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15733 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15734 | // MIs[1] Operand 1 |
| 15735 | // No operand predicates |
| 15736 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15737 | // (intrinsic_wo_chain:{ *:[v8i16] } 3425:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15738 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xuq), |
| 15739 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15740 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15741 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15743 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15744 | GIR_RootConstrainSelectedInstOperands, |
| 15745 | // GIR_Coverage, 1684, |
| 15746 | GIR_EraseRootFromParent_Done, |
| 15747 | // Label 980: @41733 |
| 15748 | GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(41794), // Rule ID 1685 // |
| 15749 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 15750 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 15751 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15752 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15753 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15755 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15756 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15757 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15758 | // MIs[1] Operand 1 |
| 15759 | // No operand predicates |
| 15760 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15761 | // (intrinsic_wo_chain:{ *:[v8f16] } 3427:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15762 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hq), |
| 15763 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15764 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15765 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15767 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15768 | GIR_RootConstrainSelectedInstOperands, |
| 15769 | // GIR_Coverage, 1685, |
| 15770 | GIR_EraseRootFromParent_Done, |
| 15771 | // Label 981: @41794 |
| 15772 | GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(41855), // Rule ID 1686 // |
| 15773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 15774 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 15775 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15776 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15777 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15779 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15780 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15781 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15782 | // MIs[1] Operand 1 |
| 15783 | // No operand predicates |
| 15784 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15785 | // (intrinsic_wo_chain:{ *:[v8f16] } 3428:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 15786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hq), |
| 15787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15788 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15789 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 15790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15791 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15792 | GIR_RootConstrainSelectedInstOperands, |
| 15793 | // GIR_Coverage, 1686, |
| 15794 | GIR_EraseRootFromParent_Done, |
| 15795 | // Label 982: @41855 |
| 15796 | GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(41916), // Rule ID 1749 // |
| 15797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 15798 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqshl), |
| 15799 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15800 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15801 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15803 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15804 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15805 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15806 | // MIs[1] Operand 1 |
| 15807 | // No operand predicates |
| 15808 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15809 | // (intrinsic_wo_chain:{ *:[i32] } 3251:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 15810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQSHL), |
| 15811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 15812 | GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 15813 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 15814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15815 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15816 | GIR_RootConstrainSelectedInstOperands, |
| 15817 | // GIR_Coverage, 1749, |
| 15818 | GIR_EraseRootFromParent_Done, |
| 15819 | // Label 983: @41916 |
| 15820 | GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(41977), // Rule ID 1750 // |
| 15821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 15822 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_srshr), |
| 15823 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15824 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15825 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15826 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15827 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15828 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15829 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15830 | // MIs[1] Operand 1 |
| 15831 | // No operand predicates |
| 15832 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15833 | // (intrinsic_wo_chain:{ *:[i32] } 3253:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 15834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SRSHR), |
| 15835 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 15836 | GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 15837 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 15838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15839 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15840 | GIR_RootConstrainSelectedInstOperands, |
| 15841 | // GIR_Coverage, 1750, |
| 15842 | GIR_EraseRootFromParent_Done, |
| 15843 | // Label 984: @41977 |
| 15844 | GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(42038), // Rule ID 1751 // |
| 15845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 15846 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqshl), |
| 15847 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15848 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15849 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15851 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15852 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15853 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15854 | // MIs[1] Operand 1 |
| 15855 | // No operand predicates |
| 15856 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15857 | // (intrinsic_wo_chain:{ *:[i32] } 3258:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 15858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQSHL), |
| 15859 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 15860 | GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 15861 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 15862 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15863 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15864 | GIR_RootConstrainSelectedInstOperands, |
| 15865 | // GIR_Coverage, 1751, |
| 15866 | GIR_EraseRootFromParent_Done, |
| 15867 | // Label 985: @42038 |
| 15868 | GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(42099), // Rule ID 1752 // |
| 15869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 15870 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_urshr), |
| 15871 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15872 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15873 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15874 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15875 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15876 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15877 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15878 | // MIs[1] Operand 1 |
| 15879 | // No operand predicates |
| 15880 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15881 | // (intrinsic_wo_chain:{ *:[i32] } 3260:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 15882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_URSHR), |
| 15883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 15884 | GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 15885 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 15886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15887 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15888 | GIR_RootConstrainSelectedInstOperands, |
| 15889 | // GIR_Coverage, 1752, |
| 15890 | GIR_EraseRootFromParent_Done, |
| 15891 | // Label 986: @42099 |
| 15892 | GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(42153), // Rule ID 105 // |
| 15893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 15894 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8), |
| 15895 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15896 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15897 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15899 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15900 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15901 | // (intrinsic_wo_chain:{ *:[i32] } 3533:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 15902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD8), |
| 15903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15904 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15905 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 15906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15907 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15908 | GIR_RootConstrainSelectedInstOperands, |
| 15909 | // GIR_Coverage, 105, |
| 15910 | GIR_EraseRootFromParent_Done, |
| 15911 | // Label 987: @42153 |
| 15912 | GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(42207), // Rule ID 106 // |
| 15913 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 15914 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16), |
| 15915 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15916 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15917 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15918 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15919 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15920 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15921 | // (intrinsic_wo_chain:{ *:[i32] } 3532:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 15922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD16), |
| 15923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15924 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15925 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 15926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15927 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15928 | GIR_RootConstrainSelectedInstOperands, |
| 15929 | // GIR_Coverage, 106, |
| 15930 | GIR_EraseRootFromParent_Done, |
| 15931 | // Label 988: @42207 |
| 15932 | GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(42261), // Rule ID 107 // |
| 15933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 15934 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16), |
| 15935 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15936 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15937 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15939 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15940 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15941 | // (intrinsic_wo_chain:{ *:[i32] } 3537:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 15942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB16), |
| 15943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15944 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15945 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 15946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15947 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15948 | GIR_RootConstrainSelectedInstOperands, |
| 15949 | // GIR_Coverage, 107, |
| 15950 | GIR_EraseRootFromParent_Done, |
| 15951 | // Label 989: @42261 |
| 15952 | GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(42315), // Rule ID 108 // |
| 15953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 15954 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8), |
| 15955 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15956 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15957 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15959 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15960 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15961 | // (intrinsic_wo_chain:{ *:[i32] } 3538:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 15962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB8), |
| 15963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15964 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15965 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 15966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15967 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15968 | GIR_RootConstrainSelectedInstOperands, |
| 15969 | // GIR_Coverage, 108, |
| 15970 | GIR_EraseRootFromParent_Done, |
| 15971 | // Label 990: @42315 |
| 15972 | GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(42369), // Rule ID 111 // |
| 15973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 15974 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 15975 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15976 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15977 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15979 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15980 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15981 | // (intrinsic_wo_chain:{ *:[i32] } 3536:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 15982 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB), |
| 15983 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15984 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 15985 | GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 15986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15987 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15988 | GIR_RootConstrainSelectedInstOperands, |
| 15989 | // GIR_Coverage, 111, |
| 15990 | GIR_EraseRootFromParent_Done, |
| 15991 | // Label 991: @42369 |
| 15992 | GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(42423), // Rule ID 112 // |
| 15993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 15994 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 15995 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15996 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15997 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15998 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15999 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16000 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16001 | // (intrinsic_wo_chain:{ *:[i32] } 3531:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 16002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD), |
| 16003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16004 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 16005 | GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 16006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16007 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16008 | GIR_RootConstrainSelectedInstOperands, |
| 16009 | // GIR_Coverage, 112, |
| 16010 | GIR_EraseRootFromParent_Done, |
| 16011 | // Label 992: @42423 |
| 16012 | GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(42477), // Rule ID 113 // |
| 16013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16014 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16), |
| 16015 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16016 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16017 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16018 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16019 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16020 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16021 | // (intrinsic_wo_chain:{ *:[i32] } 3600:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD16), |
| 16023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16024 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16025 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16027 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16028 | GIR_RootConstrainSelectedInstOperands, |
| 16029 | // GIR_Coverage, 113, |
| 16030 | GIR_EraseRootFromParent_Done, |
| 16031 | // Label 993: @42477 |
| 16032 | GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(42531), // Rule ID 114 // |
| 16033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16034 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8), |
| 16035 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16036 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16037 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16039 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16040 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16041 | // (intrinsic_wo_chain:{ *:[i32] } 3601:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD8), |
| 16043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16044 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16045 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16047 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16048 | GIR_RootConstrainSelectedInstOperands, |
| 16049 | // GIR_Coverage, 114, |
| 16050 | GIR_EraseRootFromParent_Done, |
| 16051 | // Label 994: @42531 |
| 16052 | GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(42585), // Rule ID 115 // |
| 16053 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16054 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16), |
| 16055 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16056 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16057 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16059 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16060 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16061 | // (intrinsic_wo_chain:{ *:[i32] } 3604:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB16), |
| 16063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16064 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16065 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16067 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16068 | GIR_RootConstrainSelectedInstOperands, |
| 16069 | // GIR_Coverage, 115, |
| 16070 | GIR_EraseRootFromParent_Done, |
| 16071 | // Label 995: @42585 |
| 16072 | GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(42639), // Rule ID 116 // |
| 16073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16074 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8), |
| 16075 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16076 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16077 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16078 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16079 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16080 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16081 | // (intrinsic_wo_chain:{ *:[i32] } 3605:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB8), |
| 16083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16084 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16085 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16087 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16088 | GIR_RootConstrainSelectedInstOperands, |
| 16089 | // GIR_Coverage, 116, |
| 16090 | GIR_EraseRootFromParent_Done, |
| 16091 | // Label 996: @42639 |
| 16092 | GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(42693), // Rule ID 117 // |
| 16093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16094 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx), |
| 16095 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16096 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16097 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16098 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16099 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16100 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16101 | // (intrinsic_wo_chain:{ *:[i32] } 3534:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QASX), |
| 16103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16104 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16105 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16107 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16108 | GIR_RootConstrainSelectedInstOperands, |
| 16109 | // GIR_Coverage, 117, |
| 16110 | GIR_EraseRootFromParent_Done, |
| 16111 | // Label 997: @42693 |
| 16112 | GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(42747), // Rule ID 118 // |
| 16113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16114 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax), |
| 16115 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16116 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16117 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16118 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16119 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16120 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16121 | // (intrinsic_wo_chain:{ *:[i32] } 3535:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSAX), |
| 16123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16124 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16125 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16127 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16128 | GIR_RootConstrainSelectedInstOperands, |
| 16129 | // GIR_Coverage, 118, |
| 16130 | GIR_EraseRootFromParent_Done, |
| 16131 | // Label 998: @42747 |
| 16132 | GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(42801), // Rule ID 119 // |
| 16133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16134 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx), |
| 16135 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16136 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16137 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16139 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16140 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16141 | // (intrinsic_wo_chain:{ *:[i32] } 3602:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQASX), |
| 16143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16144 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16145 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16147 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16148 | GIR_RootConstrainSelectedInstOperands, |
| 16149 | // GIR_Coverage, 119, |
| 16150 | GIR_EraseRootFromParent_Done, |
| 16151 | // Label 999: @42801 |
| 16152 | GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(42855), // Rule ID 120 // |
| 16153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16154 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax), |
| 16155 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16156 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16157 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16158 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16159 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16160 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16161 | // (intrinsic_wo_chain:{ *:[i32] } 3603:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSAX), |
| 16163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16164 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16165 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16167 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16168 | GIR_RootConstrainSelectedInstOperands, |
| 16169 | // GIR_Coverage, 120, |
| 16170 | GIR_EraseRootFromParent_Done, |
| 16171 | // Label 1000: @42855 |
| 16172 | GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(42909), // Rule ID 133 // |
| 16173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16174 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx), |
| 16175 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16176 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16177 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16178 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16179 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16180 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16181 | // (intrinsic_wo_chain:{ *:[i32] } 3546:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHASX), |
| 16183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16184 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16185 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16187 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16188 | GIR_RootConstrainSelectedInstOperands, |
| 16189 | // GIR_Coverage, 133, |
| 16190 | GIR_EraseRootFromParent_Done, |
| 16191 | // Label 1001: @42909 |
| 16192 | GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(42963), // Rule ID 134 // |
| 16193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16194 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16), |
| 16195 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16196 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16197 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16198 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16199 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16200 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16201 | // (intrinsic_wo_chain:{ *:[i32] } 3544:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD16), |
| 16203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16204 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16205 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16207 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16208 | GIR_RootConstrainSelectedInstOperands, |
| 16209 | // GIR_Coverage, 134, |
| 16210 | GIR_EraseRootFromParent_Done, |
| 16211 | // Label 1002: @42963 |
| 16212 | GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(43017), // Rule ID 135 // |
| 16213 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16214 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8), |
| 16215 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16216 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16217 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16219 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16220 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16221 | // (intrinsic_wo_chain:{ *:[i32] } 3545:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD8), |
| 16223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16224 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16225 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16227 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16228 | GIR_RootConstrainSelectedInstOperands, |
| 16229 | // GIR_Coverage, 135, |
| 16230 | GIR_EraseRootFromParent_Done, |
| 16231 | // Label 1003: @43017 |
| 16232 | GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(43071), // Rule ID 136 // |
| 16233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16234 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax), |
| 16235 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16236 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16237 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16239 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16240 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16241 | // (intrinsic_wo_chain:{ *:[i32] } 3547:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSAX), |
| 16243 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16244 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16245 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16247 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16248 | GIR_RootConstrainSelectedInstOperands, |
| 16249 | // GIR_Coverage, 136, |
| 16250 | GIR_EraseRootFromParent_Done, |
| 16251 | // Label 1004: @43071 |
| 16252 | GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(43125), // Rule ID 137 // |
| 16253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16254 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16), |
| 16255 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16256 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16257 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16259 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16260 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16261 | // (intrinsic_wo_chain:{ *:[i32] } 3548:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB16), |
| 16263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16264 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16265 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16267 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16268 | GIR_RootConstrainSelectedInstOperands, |
| 16269 | // GIR_Coverage, 137, |
| 16270 | GIR_EraseRootFromParent_Done, |
| 16271 | // Label 1005: @43125 |
| 16272 | GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(43179), // Rule ID 138 // |
| 16273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16274 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8), |
| 16275 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16276 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16277 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16278 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16279 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16280 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16281 | // (intrinsic_wo_chain:{ *:[i32] } 3549:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB8), |
| 16283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16284 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16285 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16287 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16288 | GIR_RootConstrainSelectedInstOperands, |
| 16289 | // GIR_Coverage, 138, |
| 16290 | GIR_EraseRootFromParent_Done, |
| 16291 | // Label 1006: @43179 |
| 16292 | GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(43233), // Rule ID 139 // |
| 16293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16294 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx), |
| 16295 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16296 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16297 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16299 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16300 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16301 | // (intrinsic_wo_chain:{ *:[i32] } 3595:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHASX), |
| 16303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16304 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16305 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16307 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16308 | GIR_RootConstrainSelectedInstOperands, |
| 16309 | // GIR_Coverage, 139, |
| 16310 | GIR_EraseRootFromParent_Done, |
| 16311 | // Label 1007: @43233 |
| 16312 | GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(43287), // Rule ID 140 // |
| 16313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16314 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16), |
| 16315 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16316 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16317 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16318 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16319 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16320 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16321 | // (intrinsic_wo_chain:{ *:[i32] } 3593:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16322 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD16), |
| 16323 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16324 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16325 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16327 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16328 | GIR_RootConstrainSelectedInstOperands, |
| 16329 | // GIR_Coverage, 140, |
| 16330 | GIR_EraseRootFromParent_Done, |
| 16331 | // Label 1008: @43287 |
| 16332 | GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(43341), // Rule ID 141 // |
| 16333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16334 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8), |
| 16335 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16336 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16337 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16339 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16340 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16341 | // (intrinsic_wo_chain:{ *:[i32] } 3594:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD8), |
| 16343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16344 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16345 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16347 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16348 | GIR_RootConstrainSelectedInstOperands, |
| 16349 | // GIR_Coverage, 141, |
| 16350 | GIR_EraseRootFromParent_Done, |
| 16351 | // Label 1009: @43341 |
| 16352 | GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(43395), // Rule ID 142 // |
| 16353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16354 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax), |
| 16355 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16356 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16357 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16359 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16360 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16361 | // (intrinsic_wo_chain:{ *:[i32] } 3596:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSAX), |
| 16363 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16364 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16365 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16367 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16368 | GIR_RootConstrainSelectedInstOperands, |
| 16369 | // GIR_Coverage, 142, |
| 16370 | GIR_EraseRootFromParent_Done, |
| 16371 | // Label 1010: @43395 |
| 16372 | GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(43449), // Rule ID 143 // |
| 16373 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16374 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16), |
| 16375 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16376 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16377 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16379 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16380 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16381 | // (intrinsic_wo_chain:{ *:[i32] } 3597:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB16), |
| 16383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16384 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16385 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16387 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16388 | GIR_RootConstrainSelectedInstOperands, |
| 16389 | // GIR_Coverage, 143, |
| 16390 | GIR_EraseRootFromParent_Done, |
| 16391 | // Label 1011: @43449 |
| 16392 | GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(43503), // Rule ID 144 // |
| 16393 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16394 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8), |
| 16395 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16396 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16397 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16399 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16400 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16401 | // (intrinsic_wo_chain:{ *:[i32] } 3598:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB8), |
| 16403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16404 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16405 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16407 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16408 | GIR_RootConstrainSelectedInstOperands, |
| 16409 | // GIR_Coverage, 144, |
| 16410 | GIR_EraseRootFromParent_Done, |
| 16411 | // Label 1012: @43503 |
| 16412 | GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(43557), // Rule ID 145 // |
| 16413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 16414 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8), |
| 16415 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16416 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16417 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 16419 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 16420 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 16421 | // (intrinsic_wo_chain:{ *:[i32] } 3606:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 16422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAD8), |
| 16423 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16424 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16425 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16427 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16428 | GIR_RootConstrainSelectedInstOperands, |
| 16429 | // GIR_Coverage, 145, |
| 16430 | GIR_EraseRootFromParent_Done, |
| 16431 | // Label 1013: @43557 |
| 16432 | GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(43602), // Rule ID 204 // |
| 16433 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 16434 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b), |
| 16435 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16436 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16437 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16438 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16439 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16440 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16441 | // (intrinsic_wo_chain:{ *:[i32] } 3165:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32B), |
| 16443 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16444 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16445 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16446 | GIR_RootConstrainSelectedInstOperands, |
| 16447 | // GIR_Coverage, 204, |
| 16448 | GIR_EraseRootFromParent_Done, |
| 16449 | // Label 1014: @43602 |
| 16450 | GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(43647), // Rule ID 205 // |
| 16451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 16452 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb), |
| 16453 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16454 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16455 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16457 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16458 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16459 | // (intrinsic_wo_chain:{ *:[i32] } 3166:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CB), |
| 16461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16462 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16463 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16464 | GIR_RootConstrainSelectedInstOperands, |
| 16465 | // GIR_Coverage, 205, |
| 16466 | GIR_EraseRootFromParent_Done, |
| 16467 | // Label 1015: @43647 |
| 16468 | GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(43692), // Rule ID 206 // |
| 16469 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 16470 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h), |
| 16471 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16472 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16473 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16475 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16476 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16477 | // (intrinsic_wo_chain:{ *:[i32] } 3169:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32H), |
| 16479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16480 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16481 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16482 | GIR_RootConstrainSelectedInstOperands, |
| 16483 | // GIR_Coverage, 206, |
| 16484 | GIR_EraseRootFromParent_Done, |
| 16485 | // Label 1016: @43692 |
| 16486 | GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(43737), // Rule ID 207 // |
| 16487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 16488 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch), |
| 16489 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16490 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16491 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16492 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16493 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16494 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16495 | // (intrinsic_wo_chain:{ *:[i32] } 3167:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CH), |
| 16497 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16498 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16499 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16500 | GIR_RootConstrainSelectedInstOperands, |
| 16501 | // GIR_Coverage, 207, |
| 16502 | GIR_EraseRootFromParent_Done, |
| 16503 | // Label 1017: @43737 |
| 16504 | GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(43782), // Rule ID 208 // |
| 16505 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 16506 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w), |
| 16507 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16508 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16509 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16510 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16511 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16512 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16513 | // (intrinsic_wo_chain:{ *:[i32] } 3170:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32W), |
| 16515 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16516 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16517 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16518 | GIR_RootConstrainSelectedInstOperands, |
| 16519 | // GIR_Coverage, 208, |
| 16520 | GIR_EraseRootFromParent_Done, |
| 16521 | // Label 1018: @43782 |
| 16522 | GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(43827), // Rule ID 209 // |
| 16523 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 16524 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw), |
| 16525 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16526 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16527 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16528 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16529 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16530 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16531 | // (intrinsic_wo_chain:{ *:[i32] } 3168:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CW), |
| 16533 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16534 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16535 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16536 | GIR_RootConstrainSelectedInstOperands, |
| 16537 | // GIR_Coverage, 209, |
| 16538 | GIR_EraseRootFromParent_Done, |
| 16539 | // Label 1019: @43827 |
| 16540 | GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(43881), // Rule ID 440 // |
| 16541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16542 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16), |
| 16543 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16544 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16545 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16546 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16547 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16548 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16549 | // (intrinsic_wo_chain:{ *:[i32] } 3532:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16550 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD16), |
| 16551 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16552 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16553 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16554 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16555 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16556 | GIR_RootConstrainSelectedInstOperands, |
| 16557 | // GIR_Coverage, 440, |
| 16558 | GIR_EraseRootFromParent_Done, |
| 16559 | // Label 1020: @43881 |
| 16560 | GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(43935), // Rule ID 441 // |
| 16561 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16562 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8), |
| 16563 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16564 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16565 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16567 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16568 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16569 | // (intrinsic_wo_chain:{ *:[i32] } 3533:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD8), |
| 16571 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16572 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16573 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16575 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16576 | GIR_RootConstrainSelectedInstOperands, |
| 16577 | // GIR_Coverage, 441, |
| 16578 | GIR_EraseRootFromParent_Done, |
| 16579 | // Label 1021: @43935 |
| 16580 | GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(43989), // Rule ID 442 // |
| 16581 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16582 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx), |
| 16583 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16584 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16585 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16586 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16587 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16588 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16589 | // (intrinsic_wo_chain:{ *:[i32] } 3534:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16590 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QASX), |
| 16591 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16592 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16593 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16595 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16596 | GIR_RootConstrainSelectedInstOperands, |
| 16597 | // GIR_Coverage, 442, |
| 16598 | GIR_EraseRootFromParent_Done, |
| 16599 | // Label 1022: @43989 |
| 16600 | GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(44043), // Rule ID 443 // |
| 16601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16602 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8), |
| 16603 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16604 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16605 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16606 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16607 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16608 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16609 | // (intrinsic_wo_chain:{ *:[i32] } 3605:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB8), |
| 16611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16612 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16613 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16615 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16616 | GIR_RootConstrainSelectedInstOperands, |
| 16617 | // GIR_Coverage, 443, |
| 16618 | GIR_EraseRootFromParent_Done, |
| 16619 | // Label 1023: @44043 |
| 16620 | GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(44097), // Rule ID 444 // |
| 16621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16622 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax), |
| 16623 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16624 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16625 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16626 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16627 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16628 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16629 | // (intrinsic_wo_chain:{ *:[i32] } 3535:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16630 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSAX), |
| 16631 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16632 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16633 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16634 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16635 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16636 | GIR_RootConstrainSelectedInstOperands, |
| 16637 | // GIR_Coverage, 444, |
| 16638 | GIR_EraseRootFromParent_Done, |
| 16639 | // Label 1024: @44097 |
| 16640 | GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(44151), // Rule ID 445 // |
| 16641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16642 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16), |
| 16643 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16644 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16645 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16646 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16647 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16648 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16649 | // (intrinsic_wo_chain:{ *:[i32] } 3537:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB16), |
| 16651 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16652 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16653 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16655 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16656 | GIR_RootConstrainSelectedInstOperands, |
| 16657 | // GIR_Coverage, 445, |
| 16658 | GIR_EraseRootFromParent_Done, |
| 16659 | // Label 1025: @44151 |
| 16660 | GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(44205), // Rule ID 446 // |
| 16661 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16662 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8), |
| 16663 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16664 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16665 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16667 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16668 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16669 | // (intrinsic_wo_chain:{ *:[i32] } 3538:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB8), |
| 16671 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16672 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16673 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16675 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16676 | GIR_RootConstrainSelectedInstOperands, |
| 16677 | // GIR_Coverage, 446, |
| 16678 | GIR_EraseRootFromParent_Done, |
| 16679 | // Label 1026: @44205 |
| 16680 | GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(44259), // Rule ID 447 // |
| 16681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16682 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16), |
| 16683 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16684 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16685 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16686 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16687 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16688 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16689 | // (intrinsic_wo_chain:{ *:[i32] } 3600:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD16), |
| 16691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16692 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16693 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16695 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16696 | GIR_RootConstrainSelectedInstOperands, |
| 16697 | // GIR_Coverage, 447, |
| 16698 | GIR_EraseRootFromParent_Done, |
| 16699 | // Label 1027: @44259 |
| 16700 | GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(44313), // Rule ID 448 // |
| 16701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16702 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8), |
| 16703 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16704 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16705 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16707 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16708 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16709 | // (intrinsic_wo_chain:{ *:[i32] } 3601:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD8), |
| 16711 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16712 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16713 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16715 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16716 | GIR_RootConstrainSelectedInstOperands, |
| 16717 | // GIR_Coverage, 448, |
| 16718 | GIR_EraseRootFromParent_Done, |
| 16719 | // Label 1028: @44313 |
| 16720 | GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(44367), // Rule ID 449 // |
| 16721 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16722 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx), |
| 16723 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16724 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16725 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16726 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16727 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16728 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16729 | // (intrinsic_wo_chain:{ *:[i32] } 3602:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQASX), |
| 16731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16732 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16733 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16735 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16736 | GIR_RootConstrainSelectedInstOperands, |
| 16737 | // GIR_Coverage, 449, |
| 16738 | GIR_EraseRootFromParent_Done, |
| 16739 | // Label 1029: @44367 |
| 16740 | GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(44421), // Rule ID 450 // |
| 16741 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16742 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax), |
| 16743 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16744 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16745 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16746 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16747 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16748 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16749 | // (intrinsic_wo_chain:{ *:[i32] } 3603:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSAX), |
| 16751 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16752 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16753 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16755 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16756 | GIR_RootConstrainSelectedInstOperands, |
| 16757 | // GIR_Coverage, 450, |
| 16758 | GIR_EraseRootFromParent_Done, |
| 16759 | // Label 1030: @44421 |
| 16760 | GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(44475), // Rule ID 451 // |
| 16761 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16762 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16), |
| 16763 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16764 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16765 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16767 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16768 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16769 | // (intrinsic_wo_chain:{ *:[i32] } 3604:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB16), |
| 16771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16772 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16773 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16775 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16776 | GIR_RootConstrainSelectedInstOperands, |
| 16777 | // GIR_Coverage, 451, |
| 16778 | GIR_EraseRootFromParent_Done, |
| 16779 | // Label 1031: @44475 |
| 16780 | GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(44529), // Rule ID 464 // |
| 16781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16782 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx), |
| 16783 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16784 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16785 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16786 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16787 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16788 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16789 | // (intrinsic_wo_chain:{ *:[i32] } 3546:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHASX), |
| 16791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16792 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16793 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16795 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16796 | GIR_RootConstrainSelectedInstOperands, |
| 16797 | // GIR_Coverage, 464, |
| 16798 | GIR_EraseRootFromParent_Done, |
| 16799 | // Label 1032: @44529 |
| 16800 | GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(44583), // Rule ID 465 // |
| 16801 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16802 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16), |
| 16803 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16804 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16805 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16807 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16808 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16809 | // (intrinsic_wo_chain:{ *:[i32] } 3544:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD16), |
| 16811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16812 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16813 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16815 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16816 | GIR_RootConstrainSelectedInstOperands, |
| 16817 | // GIR_Coverage, 465, |
| 16818 | GIR_EraseRootFromParent_Done, |
| 16819 | // Label 1033: @44583 |
| 16820 | GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(44637), // Rule ID 466 // |
| 16821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16822 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8), |
| 16823 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16824 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16825 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16826 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16827 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16828 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16829 | // (intrinsic_wo_chain:{ *:[i32] } 3545:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD8), |
| 16831 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16832 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16833 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16835 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16836 | GIR_RootConstrainSelectedInstOperands, |
| 16837 | // GIR_Coverage, 466, |
| 16838 | GIR_EraseRootFromParent_Done, |
| 16839 | // Label 1034: @44637 |
| 16840 | GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(44691), // Rule ID 467 // |
| 16841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16842 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax), |
| 16843 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16844 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16845 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16846 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16847 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16848 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16849 | // (intrinsic_wo_chain:{ *:[i32] } 3547:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSAX), |
| 16851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16852 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16853 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16855 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16856 | GIR_RootConstrainSelectedInstOperands, |
| 16857 | // GIR_Coverage, 467, |
| 16858 | GIR_EraseRootFromParent_Done, |
| 16859 | // Label 1035: @44691 |
| 16860 | GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(44745), // Rule ID 468 // |
| 16861 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16862 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16), |
| 16863 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16864 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16865 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16867 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16868 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16869 | // (intrinsic_wo_chain:{ *:[i32] } 3548:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16870 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB16), |
| 16871 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16872 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16873 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16875 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16876 | GIR_RootConstrainSelectedInstOperands, |
| 16877 | // GIR_Coverage, 468, |
| 16878 | GIR_EraseRootFromParent_Done, |
| 16879 | // Label 1036: @44745 |
| 16880 | GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(44799), // Rule ID 469 // |
| 16881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16882 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8), |
| 16883 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16884 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16885 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16887 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16888 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16889 | // (intrinsic_wo_chain:{ *:[i32] } 3549:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB8), |
| 16891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16892 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16893 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16895 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16896 | GIR_RootConstrainSelectedInstOperands, |
| 16897 | // GIR_Coverage, 469, |
| 16898 | GIR_EraseRootFromParent_Done, |
| 16899 | // Label 1037: @44799 |
| 16900 | GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(44853), // Rule ID 470 // |
| 16901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16902 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx), |
| 16903 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16904 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16905 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16907 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16908 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16909 | // (intrinsic_wo_chain:{ *:[i32] } 3595:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHASX), |
| 16911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16912 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16913 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16915 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16916 | GIR_RootConstrainSelectedInstOperands, |
| 16917 | // GIR_Coverage, 470, |
| 16918 | GIR_EraseRootFromParent_Done, |
| 16919 | // Label 1038: @44853 |
| 16920 | GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(44907), // Rule ID 471 // |
| 16921 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16922 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16), |
| 16923 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16924 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16925 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16927 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16928 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16929 | // (intrinsic_wo_chain:{ *:[i32] } 3593:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD16), |
| 16931 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16932 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16933 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16934 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16935 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16936 | GIR_RootConstrainSelectedInstOperands, |
| 16937 | // GIR_Coverage, 471, |
| 16938 | GIR_EraseRootFromParent_Done, |
| 16939 | // Label 1039: @44907 |
| 16940 | GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(44961), // Rule ID 472 // |
| 16941 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16942 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8), |
| 16943 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16944 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16945 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16947 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16948 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16949 | // (intrinsic_wo_chain:{ *:[i32] } 3594:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD8), |
| 16951 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16952 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16953 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16955 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16956 | GIR_RootConstrainSelectedInstOperands, |
| 16957 | // GIR_Coverage, 472, |
| 16958 | GIR_EraseRootFromParent_Done, |
| 16959 | // Label 1040: @44961 |
| 16960 | GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(45015), // Rule ID 473 // |
| 16961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16962 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax), |
| 16963 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16964 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16965 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16967 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16968 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16969 | // (intrinsic_wo_chain:{ *:[i32] } 3596:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSAX), |
| 16971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16972 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16973 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16975 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16976 | GIR_RootConstrainSelectedInstOperands, |
| 16977 | // GIR_Coverage, 473, |
| 16978 | GIR_EraseRootFromParent_Done, |
| 16979 | // Label 1041: @45015 |
| 16980 | GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(45069), // Rule ID 474 // |
| 16981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 16982 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16), |
| 16983 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16984 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16985 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16987 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16988 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16989 | // (intrinsic_wo_chain:{ *:[i32] } 3597:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 16990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB16), |
| 16991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16992 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16993 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16995 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16996 | GIR_RootConstrainSelectedInstOperands, |
| 16997 | // GIR_Coverage, 474, |
| 16998 | GIR_EraseRootFromParent_Done, |
| 16999 | // Label 1042: @45069 |
| 17000 | GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(45123), // Rule ID 475 // |
| 17001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17002 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8), |
| 17003 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17004 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17005 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17007 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17008 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17009 | // (intrinsic_wo_chain:{ *:[i32] } 3598:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB8), |
| 17011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17012 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17013 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17015 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17016 | GIR_RootConstrainSelectedInstOperands, |
| 17017 | // GIR_Coverage, 475, |
| 17018 | GIR_EraseRootFromParent_Done, |
| 17019 | // Label 1043: @45123 |
| 17020 | GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(45177), // Rule ID 476 // |
| 17021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17022 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8), |
| 17023 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17024 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17025 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17027 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17028 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17029 | // (intrinsic_wo_chain:{ *:[i32] } 3606:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAD8), |
| 17031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17032 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17033 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17035 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17036 | GIR_RootConstrainSelectedInstOperands, |
| 17037 | // GIR_Coverage, 476, |
| 17038 | GIR_EraseRootFromParent_Done, |
| 17039 | // Label 1044: @45177 |
| 17040 | GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(45231), // Rule ID 532 // |
| 17041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17042 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad), |
| 17043 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17044 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17045 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17047 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17048 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17049 | // (intrinsic_wo_chain:{ *:[i32] } 3564:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUAD), |
| 17051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17052 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17053 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17055 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17056 | GIR_RootConstrainSelectedInstOperands, |
| 17057 | // GIR_Coverage, 532, |
| 17058 | GIR_EraseRootFromParent_Done, |
| 17059 | // Label 1045: @45231 |
| 17060 | GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(45285), // Rule ID 533 // |
| 17061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17062 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx), |
| 17063 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17064 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17065 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17067 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17068 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17069 | // (intrinsic_wo_chain:{ *:[i32] } 3565:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17070 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUADX), |
| 17071 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17072 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17073 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17075 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17076 | GIR_RootConstrainSelectedInstOperands, |
| 17077 | // GIR_Coverage, 533, |
| 17078 | GIR_EraseRootFromParent_Done, |
| 17079 | // Label 1046: @45285 |
| 17080 | GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(45339), // Rule ID 534 // |
| 17081 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17082 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd), |
| 17083 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17084 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17085 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17086 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17087 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17088 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17089 | // (intrinsic_wo_chain:{ *:[i32] } 3572:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSD), |
| 17091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17092 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17093 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17095 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17096 | GIR_RootConstrainSelectedInstOperands, |
| 17097 | // GIR_Coverage, 534, |
| 17098 | GIR_EraseRootFromParent_Done, |
| 17099 | // Label 1047: @45339 |
| 17100 | GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(45393), // Rule ID 535 // |
| 17101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17102 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx), |
| 17103 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17104 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17105 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17107 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17108 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17109 | // (intrinsic_wo_chain:{ *:[i32] } 3573:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSDX), |
| 17111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17112 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17113 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17115 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17116 | GIR_RootConstrainSelectedInstOperands, |
| 17117 | // GIR_Coverage, 535, |
| 17118 | GIR_EraseRootFromParent_Done, |
| 17119 | // Label 1048: @45393 |
| 17120 | GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(45438), // Rule ID 549 // |
| 17121 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 17122 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b), |
| 17123 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17124 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17125 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17126 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17127 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17128 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17129 | // (intrinsic_wo_chain:{ *:[i32] } 3165:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32B), |
| 17131 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17132 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17133 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17134 | GIR_RootConstrainSelectedInstOperands, |
| 17135 | // GIR_Coverage, 549, |
| 17136 | GIR_EraseRootFromParent_Done, |
| 17137 | // Label 1049: @45438 |
| 17138 | GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(45483), // Rule ID 550 // |
| 17139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 17140 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb), |
| 17141 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17142 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17143 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17144 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17145 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17146 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17147 | // (intrinsic_wo_chain:{ *:[i32] } 3166:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CB), |
| 17149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17150 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17151 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17152 | GIR_RootConstrainSelectedInstOperands, |
| 17153 | // GIR_Coverage, 550, |
| 17154 | GIR_EraseRootFromParent_Done, |
| 17155 | // Label 1050: @45483 |
| 17156 | GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(45528), // Rule ID 551 // |
| 17157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 17158 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h), |
| 17159 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17160 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17161 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17163 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17164 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17165 | // (intrinsic_wo_chain:{ *:[i32] } 3169:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32H), |
| 17167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17168 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17169 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17170 | GIR_RootConstrainSelectedInstOperands, |
| 17171 | // GIR_Coverage, 551, |
| 17172 | GIR_EraseRootFromParent_Done, |
| 17173 | // Label 1051: @45528 |
| 17174 | GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(45573), // Rule ID 552 // |
| 17175 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 17176 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch), |
| 17177 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17178 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17179 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17181 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17182 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17183 | // (intrinsic_wo_chain:{ *:[i32] } 3167:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CH), |
| 17185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17186 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17187 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17188 | GIR_RootConstrainSelectedInstOperands, |
| 17189 | // GIR_Coverage, 552, |
| 17190 | GIR_EraseRootFromParent_Done, |
| 17191 | // Label 1052: @45573 |
| 17192 | GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(45618), // Rule ID 553 // |
| 17193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 17194 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w), |
| 17195 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17196 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17197 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17198 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17199 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17200 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17201 | // (intrinsic_wo_chain:{ *:[i32] } 3170:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32W), |
| 17203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17204 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17205 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17206 | GIR_RootConstrainSelectedInstOperands, |
| 17207 | // GIR_Coverage, 553, |
| 17208 | GIR_EraseRootFromParent_Done, |
| 17209 | // Label 1053: @45618 |
| 17210 | GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(45663), // Rule ID 554 // |
| 17211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 17212 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw), |
| 17213 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17214 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17215 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17217 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17218 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17219 | // (intrinsic_wo_chain:{ *:[i32] } 3168:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CW), |
| 17221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17222 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17223 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17224 | GIR_RootConstrainSelectedInstOperands, |
| 17225 | // GIR_Coverage, 554, |
| 17226 | GIR_EraseRootFromParent_Done, |
| 17227 | // Label 1054: @45663 |
| 17228 | GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(45717), // Rule ID 809 // |
| 17229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17230 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 17231 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17232 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17233 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 17234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17235 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17236 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17237 | // (intrinsic_wo_chain:{ *:[v4i16] } 3436:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 17238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i16), |
| 17239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17240 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17241 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17243 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17244 | GIR_RootConstrainSelectedInstOperands, |
| 17245 | // GIR_Coverage, 809, |
| 17246 | GIR_EraseRootFromParent_Done, |
| 17247 | // Label 1055: @45717 |
| 17248 | GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(45771), // Rule ID 810 // |
| 17249 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17250 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 17251 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17252 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17253 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 17254 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17255 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17256 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17257 | // (intrinsic_wo_chain:{ *:[v2i32] } 3436:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 17258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv2i32), |
| 17259 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17260 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17261 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17263 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17264 | GIR_RootConstrainSelectedInstOperands, |
| 17265 | // GIR_Coverage, 810, |
| 17266 | GIR_EraseRootFromParent_Done, |
| 17267 | // Label 1056: @45771 |
| 17268 | GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(45825), // Rule ID 811 // |
| 17269 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17270 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 17271 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17272 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17273 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17275 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17276 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17277 | // (intrinsic_wo_chain:{ *:[v8i16] } 3436:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 17278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i16), |
| 17279 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17280 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17281 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17283 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17284 | GIR_RootConstrainSelectedInstOperands, |
| 17285 | // GIR_Coverage, 811, |
| 17286 | GIR_EraseRootFromParent_Done, |
| 17287 | // Label 1057: @45825 |
| 17288 | GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(45879), // Rule ID 812 // |
| 17289 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17290 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 17291 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17292 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17293 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17294 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17295 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17296 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17297 | // (intrinsic_wo_chain:{ *:[v4i32] } 3436:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 17298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i32), |
| 17299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17300 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17301 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17303 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17304 | GIR_RootConstrainSelectedInstOperands, |
| 17305 | // GIR_Coverage, 812, |
| 17306 | GIR_EraseRootFromParent_Done, |
| 17307 | // Label 1058: @45879 |
| 17308 | GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(45933), // Rule ID 813 // |
| 17309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17310 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 17311 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 17312 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 17313 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 17314 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17315 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17316 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17317 | // (intrinsic_wo_chain:{ *:[v8i8] } 3436:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 17318 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i8), |
| 17319 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17320 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17321 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17323 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17324 | GIR_RootConstrainSelectedInstOperands, |
| 17325 | // GIR_Coverage, 813, |
| 17326 | GIR_EraseRootFromParent_Done, |
| 17327 | // Label 1059: @45933 |
| 17328 | GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(45987), // Rule ID 814 // |
| 17329 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17330 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 17331 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 17332 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 17333 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 17334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17335 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17336 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17337 | // (intrinsic_wo_chain:{ *:[v16i8] } 3436:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 17338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv16i8), |
| 17339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17340 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17341 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17343 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17344 | GIR_RootConstrainSelectedInstOperands, |
| 17345 | // GIR_Coverage, 814, |
| 17346 | GIR_EraseRootFromParent_Done, |
| 17347 | // Label 1060: @45987 |
| 17348 | GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(46041), // Rule ID 815 // |
| 17349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17350 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 17351 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17352 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17353 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 17354 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17355 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17356 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17357 | // (intrinsic_wo_chain:{ *:[v4i16] } 3437:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 17358 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i16), |
| 17359 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17360 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17361 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17363 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17364 | GIR_RootConstrainSelectedInstOperands, |
| 17365 | // GIR_Coverage, 815, |
| 17366 | GIR_EraseRootFromParent_Done, |
| 17367 | // Label 1061: @46041 |
| 17368 | GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(46095), // Rule ID 816 // |
| 17369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17370 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 17371 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17372 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17373 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 17374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17375 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17376 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17377 | // (intrinsic_wo_chain:{ *:[v2i32] } 3437:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 17378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv2i32), |
| 17379 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17380 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17381 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17383 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17384 | GIR_RootConstrainSelectedInstOperands, |
| 17385 | // GIR_Coverage, 816, |
| 17386 | GIR_EraseRootFromParent_Done, |
| 17387 | // Label 1062: @46095 |
| 17388 | GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(46149), // Rule ID 817 // |
| 17389 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17390 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 17391 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17392 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17393 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17395 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17396 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17397 | // (intrinsic_wo_chain:{ *:[v8i16] } 3437:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 17398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i16), |
| 17399 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17400 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17401 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17403 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17404 | GIR_RootConstrainSelectedInstOperands, |
| 17405 | // GIR_Coverage, 817, |
| 17406 | GIR_EraseRootFromParent_Done, |
| 17407 | // Label 1063: @46149 |
| 17408 | GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(46203), // Rule ID 818 // |
| 17409 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17410 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 17411 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17412 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17413 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17414 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17415 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17416 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17417 | // (intrinsic_wo_chain:{ *:[v4i32] } 3437:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 17418 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i32), |
| 17419 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17420 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17421 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17423 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17424 | GIR_RootConstrainSelectedInstOperands, |
| 17425 | // GIR_Coverage, 818, |
| 17426 | GIR_EraseRootFromParent_Done, |
| 17427 | // Label 1064: @46203 |
| 17428 | GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(46257), // Rule ID 819 // |
| 17429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17430 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 17431 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 17432 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 17433 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 17434 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17435 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17436 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17437 | // (intrinsic_wo_chain:{ *:[v8i8] } 3437:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 17438 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i8), |
| 17439 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17440 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17441 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17443 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17444 | GIR_RootConstrainSelectedInstOperands, |
| 17445 | // GIR_Coverage, 819, |
| 17446 | GIR_EraseRootFromParent_Done, |
| 17447 | // Label 1065: @46257 |
| 17448 | GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(46311), // Rule ID 820 // |
| 17449 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17450 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 17451 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 17452 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 17453 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 17454 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17455 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17456 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17457 | // (intrinsic_wo_chain:{ *:[v16i8] } 3437:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 17458 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv16i8), |
| 17459 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17460 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17461 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17463 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17464 | GIR_RootConstrainSelectedInstOperands, |
| 17465 | // GIR_Coverage, 820, |
| 17466 | GIR_EraseRootFromParent_Done, |
| 17467 | // Label 1066: @46311 |
| 17468 | GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(46365), // Rule ID 821 // |
| 17469 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17470 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 17471 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17472 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17473 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 17474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17475 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17476 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17477 | // (intrinsic_wo_chain:{ *:[v4i16] } 3496:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 17478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i16), |
| 17479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17480 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17481 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17483 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17484 | GIR_RootConstrainSelectedInstOperands, |
| 17485 | // GIR_Coverage, 821, |
| 17486 | GIR_EraseRootFromParent_Done, |
| 17487 | // Label 1067: @46365 |
| 17488 | GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(46419), // Rule ID 822 // |
| 17489 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17490 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 17491 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17492 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17493 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 17494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17495 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17496 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17497 | // (intrinsic_wo_chain:{ *:[v2i32] } 3496:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 17498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv2i32), |
| 17499 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17500 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17501 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17503 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17504 | GIR_RootConstrainSelectedInstOperands, |
| 17505 | // GIR_Coverage, 822, |
| 17506 | GIR_EraseRootFromParent_Done, |
| 17507 | // Label 1068: @46419 |
| 17508 | GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(46473), // Rule ID 823 // |
| 17509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17510 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 17511 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17512 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17513 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17515 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17516 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17517 | // (intrinsic_wo_chain:{ *:[v8i16] } 3496:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 17518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i16), |
| 17519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17520 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17521 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17523 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17524 | GIR_RootConstrainSelectedInstOperands, |
| 17525 | // GIR_Coverage, 823, |
| 17526 | GIR_EraseRootFromParent_Done, |
| 17527 | // Label 1069: @46473 |
| 17528 | GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(46527), // Rule ID 824 // |
| 17529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17530 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 17531 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17532 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17533 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17535 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17536 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17537 | // (intrinsic_wo_chain:{ *:[v4i32] } 3496:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 17538 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i32), |
| 17539 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17540 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17541 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17543 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17544 | GIR_RootConstrainSelectedInstOperands, |
| 17545 | // GIR_Coverage, 824, |
| 17546 | GIR_EraseRootFromParent_Done, |
| 17547 | // Label 1070: @46527 |
| 17548 | GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(46581), // Rule ID 825 // |
| 17549 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17550 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 17551 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 17552 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 17553 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 17554 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17555 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17556 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17557 | // (intrinsic_wo_chain:{ *:[v8i8] } 3496:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 17558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i8), |
| 17559 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17560 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17561 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17563 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17564 | GIR_RootConstrainSelectedInstOperands, |
| 17565 | // GIR_Coverage, 825, |
| 17566 | GIR_EraseRootFromParent_Done, |
| 17567 | // Label 1071: @46581 |
| 17568 | GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(46635), // Rule ID 826 // |
| 17569 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17570 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 17571 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 17572 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 17573 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 17574 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17575 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17576 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17577 | // (intrinsic_wo_chain:{ *:[v16i8] } 3496:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 17578 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv16i8), |
| 17579 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17580 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17581 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17583 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17584 | GIR_RootConstrainSelectedInstOperands, |
| 17585 | // GIR_Coverage, 826, |
| 17586 | GIR_EraseRootFromParent_Done, |
| 17587 | // Label 1072: @46635 |
| 17588 | GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(46689), // Rule ID 827 // |
| 17589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17590 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 17591 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17592 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17593 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 17594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17595 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17596 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17597 | // (intrinsic_wo_chain:{ *:[v4i16] } 3497:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 17598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i16), |
| 17599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17600 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17601 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17603 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17604 | GIR_RootConstrainSelectedInstOperands, |
| 17605 | // GIR_Coverage, 827, |
| 17606 | GIR_EraseRootFromParent_Done, |
| 17607 | // Label 1073: @46689 |
| 17608 | GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(46743), // Rule ID 828 // |
| 17609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17610 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 17611 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17612 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17613 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 17614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17615 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17616 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17617 | // (intrinsic_wo_chain:{ *:[v2i32] } 3497:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 17618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv2i32), |
| 17619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17620 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17621 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17623 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17624 | GIR_RootConstrainSelectedInstOperands, |
| 17625 | // GIR_Coverage, 828, |
| 17626 | GIR_EraseRootFromParent_Done, |
| 17627 | // Label 1074: @46743 |
| 17628 | GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(46797), // Rule ID 829 // |
| 17629 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17630 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 17631 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17632 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17633 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17635 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17636 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17637 | // (intrinsic_wo_chain:{ *:[v8i16] } 3497:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 17638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i16), |
| 17639 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17640 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17641 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17643 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17644 | GIR_RootConstrainSelectedInstOperands, |
| 17645 | // GIR_Coverage, 829, |
| 17646 | GIR_EraseRootFromParent_Done, |
| 17647 | // Label 1075: @46797 |
| 17648 | GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(46851), // Rule ID 830 // |
| 17649 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17650 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 17651 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17652 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17653 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17654 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17655 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17656 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17657 | // (intrinsic_wo_chain:{ *:[v4i32] } 3497:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 17658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i32), |
| 17659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17660 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17661 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17663 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17664 | GIR_RootConstrainSelectedInstOperands, |
| 17665 | // GIR_Coverage, 830, |
| 17666 | GIR_EraseRootFromParent_Done, |
| 17667 | // Label 1076: @46851 |
| 17668 | GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(46905), // Rule ID 831 // |
| 17669 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17670 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 17671 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 17672 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 17673 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 17674 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17675 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17676 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17677 | // (intrinsic_wo_chain:{ *:[v8i8] } 3497:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 17678 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i8), |
| 17679 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17680 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17681 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17683 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17684 | GIR_RootConstrainSelectedInstOperands, |
| 17685 | // GIR_Coverage, 831, |
| 17686 | GIR_EraseRootFromParent_Done, |
| 17687 | // Label 1077: @46905 |
| 17688 | GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(46959), // Rule ID 832 // |
| 17689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17690 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 17691 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 17692 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 17693 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 17694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17695 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17696 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17697 | // (intrinsic_wo_chain:{ *:[v16i8] } 3497:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 17698 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv16i8), |
| 17699 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17700 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17701 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17703 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17704 | GIR_RootConstrainSelectedInstOperands, |
| 17705 | // GIR_Coverage, 832, |
| 17706 | GIR_EraseRootFromParent_Done, |
| 17707 | // Label 1078: @46959 |
| 17708 | GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(47013), // Rule ID 849 // |
| 17709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17710 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn), |
| 17711 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 17712 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17713 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17714 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17715 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17716 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17717 | // (intrinsic_wo_chain:{ *:[v8i8] } 3493:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 17718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv8i8), |
| 17719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17720 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17721 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17723 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17724 | GIR_RootConstrainSelectedInstOperands, |
| 17725 | // GIR_Coverage, 849, |
| 17726 | GIR_EraseRootFromParent_Done, |
| 17727 | // Label 1079: @47013 |
| 17728 | GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(47067), // Rule ID 850 // |
| 17729 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17730 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn), |
| 17731 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17732 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17733 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17735 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17736 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17737 | // (intrinsic_wo_chain:{ *:[v4i16] } 3493:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 17738 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv4i16), |
| 17739 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17740 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17741 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17743 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17744 | GIR_RootConstrainSelectedInstOperands, |
| 17745 | // GIR_Coverage, 850, |
| 17746 | GIR_EraseRootFromParent_Done, |
| 17747 | // Label 1080: @47067 |
| 17748 | GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(47121), // Rule ID 851 // |
| 17749 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17750 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn), |
| 17751 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17752 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 17753 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 17754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17755 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17756 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17757 | // (intrinsic_wo_chain:{ *:[v2i32] } 3493:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 17758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv2i32), |
| 17759 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17760 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17761 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17763 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17764 | GIR_RootConstrainSelectedInstOperands, |
| 17765 | // GIR_Coverage, 851, |
| 17766 | GIR_EraseRootFromParent_Done, |
| 17767 | // Label 1081: @47121 |
| 17768 | GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(47175), // Rule ID 858 // |
| 17769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17770 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp), |
| 17771 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 17772 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 17773 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 17774 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17775 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17776 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17777 | // (intrinsic_wo_chain:{ *:[v8i8] } 3462:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 17778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpd), |
| 17779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17780 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17781 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17783 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17784 | GIR_RootConstrainSelectedInstOperands, |
| 17785 | // GIR_Coverage, 858, |
| 17786 | GIR_EraseRootFromParent_Done, |
| 17787 | // Label 1082: @47175 |
| 17788 | GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(47229), // Rule ID 859 // |
| 17789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17790 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp), |
| 17791 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 17792 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 17793 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 17794 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17795 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17796 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17797 | // (intrinsic_wo_chain:{ *:[v16i8] } 3462:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 17798 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpq), |
| 17799 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17800 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17801 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17803 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17804 | GIR_RootConstrainSelectedInstOperands, |
| 17805 | // GIR_Coverage, 859, |
| 17806 | GIR_EraseRootFromParent_Done, |
| 17807 | // Label 1083: @47229 |
| 17808 | GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(47283), // Rule ID 872 // |
| 17809 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17810 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 17811 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17812 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17813 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 17814 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17815 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17816 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17817 | // (intrinsic_wo_chain:{ *:[v4i16] } 3473:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 17818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i16), |
| 17819 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17820 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17821 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17823 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17824 | GIR_RootConstrainSelectedInstOperands, |
| 17825 | // GIR_Coverage, 872, |
| 17826 | GIR_EraseRootFromParent_Done, |
| 17827 | // Label 1084: @47283 |
| 17828 | GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(47337), // Rule ID 873 // |
| 17829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17830 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 17831 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17832 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17833 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 17834 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17835 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17836 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17837 | // (intrinsic_wo_chain:{ *:[v2i32] } 3473:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 17838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv2i32), |
| 17839 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17840 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17841 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17843 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17844 | GIR_RootConstrainSelectedInstOperands, |
| 17845 | // GIR_Coverage, 873, |
| 17846 | GIR_EraseRootFromParent_Done, |
| 17847 | // Label 1085: @47337 |
| 17848 | GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(47391), // Rule ID 874 // |
| 17849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17850 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 17851 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17852 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17853 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17854 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17855 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17856 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17857 | // (intrinsic_wo_chain:{ *:[v8i16] } 3473:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 17858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv8i16), |
| 17859 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17860 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17861 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17862 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17863 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17864 | GIR_RootConstrainSelectedInstOperands, |
| 17865 | // GIR_Coverage, 874, |
| 17866 | GIR_EraseRootFromParent_Done, |
| 17867 | // Label 1086: @47391 |
| 17868 | GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(47445), // Rule ID 875 // |
| 17869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17870 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 17871 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17872 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17873 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17874 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17875 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17876 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17877 | // (intrinsic_wo_chain:{ *:[v4i32] } 3473:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 17878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i32), |
| 17879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17880 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17881 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17883 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17884 | GIR_RootConstrainSelectedInstOperands, |
| 17885 | // GIR_Coverage, 875, |
| 17886 | GIR_EraseRootFromParent_Done, |
| 17887 | // Label 1087: @47445 |
| 17888 | GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(47499), // Rule ID 880 // |
| 17889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17890 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 17891 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17892 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17893 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 17894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17895 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17896 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17897 | // (intrinsic_wo_chain:{ *:[v4i16] } 3481:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 17898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i16), |
| 17899 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17900 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17901 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17903 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17904 | GIR_RootConstrainSelectedInstOperands, |
| 17905 | // GIR_Coverage, 880, |
| 17906 | GIR_EraseRootFromParent_Done, |
| 17907 | // Label 1088: @47499 |
| 17908 | GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(47553), // Rule ID 881 // |
| 17909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17910 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 17911 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17912 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17913 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 17914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17915 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17916 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17917 | // (intrinsic_wo_chain:{ *:[v2i32] } 3481:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 17918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv2i32), |
| 17919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17920 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17921 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17923 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17924 | GIR_RootConstrainSelectedInstOperands, |
| 17925 | // GIR_Coverage, 881, |
| 17926 | GIR_EraseRootFromParent_Done, |
| 17927 | // Label 1089: @47553 |
| 17928 | GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(47607), // Rule ID 882 // |
| 17929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17930 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 17931 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17932 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17933 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 17934 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17935 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17936 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17937 | // (intrinsic_wo_chain:{ *:[v8i16] } 3481:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 17938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv8i16), |
| 17939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17940 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17941 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17943 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17944 | GIR_RootConstrainSelectedInstOperands, |
| 17945 | // GIR_Coverage, 882, |
| 17946 | GIR_EraseRootFromParent_Done, |
| 17947 | // Label 1090: @47607 |
| 17948 | GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(47661), // Rule ID 883 // |
| 17949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17950 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 17951 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17952 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17953 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17954 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17955 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17956 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17957 | // (intrinsic_wo_chain:{ *:[v4i32] } 3481:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 17958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i32), |
| 17959 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17960 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17961 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17963 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17964 | GIR_RootConstrainSelectedInstOperands, |
| 17965 | // GIR_Coverage, 883, |
| 17966 | GIR_EraseRootFromParent_Done, |
| 17967 | // Label 1091: @47661 |
| 17968 | GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(47715), // Rule ID 894 // |
| 17969 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 17970 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp), |
| 17971 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17972 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 17973 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 17974 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17975 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17976 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17977 | // (intrinsic_wo_chain:{ *:[v8i16] } 3459:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 17978 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp8), |
| 17979 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17980 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 17981 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 17982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17983 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17984 | GIR_RootConstrainSelectedInstOperands, |
| 17985 | // GIR_Coverage, 894, |
| 17986 | GIR_EraseRootFromParent_Done, |
| 17987 | // Label 1092: @47715 |
| 17988 | GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(47760), // Rule ID 895 // |
| 17989 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 17990 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp), |
| 17991 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 17992 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 17993 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 17994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17995 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17996 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17997 | // (intrinsic_wo_chain:{ *:[v2i64] } 3459:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 17998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp64), |
| 17999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18000 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18001 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18002 | GIR_RootConstrainSelectedInstOperands, |
| 18003 | // GIR_Coverage, 895, |
| 18004 | GIR_EraseRootFromParent_Done, |
| 18005 | // Label 1093: @47760 |
| 18006 | GIM_Try, /*On fail goto*//*Label 1094*/ GIMT_Encode4(47814), // Rule ID 900 // |
| 18007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18008 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 18009 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18010 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18011 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18012 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18013 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18014 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18015 | // (intrinsic_wo_chain:{ *:[v4i32] } 3474:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv4i32), |
| 18017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18018 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18019 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18021 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18022 | GIR_RootConstrainSelectedInstOperands, |
| 18023 | // GIR_Coverage, 900, |
| 18024 | GIR_EraseRootFromParent_Done, |
| 18025 | // Label 1094: @47814 |
| 18026 | GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(47868), // Rule ID 901 // |
| 18027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18028 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 18029 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 18030 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18031 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18032 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18033 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18034 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18035 | // (intrinsic_wo_chain:{ *:[v2i64] } 3474:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 18036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv2i64), |
| 18037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18038 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18039 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18041 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18042 | GIR_RootConstrainSelectedInstOperands, |
| 18043 | // GIR_Coverage, 901, |
| 18044 | GIR_EraseRootFromParent_Done, |
| 18045 | // Label 1095: @47868 |
| 18046 | GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(47922), // Rule ID 1013 // |
| 18047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18048 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 18049 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18050 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18051 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18052 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18053 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18054 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18055 | // (intrinsic_wo_chain:{ *:[v4i16] } 3438:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i16), |
| 18057 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18058 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18059 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18061 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18062 | GIR_RootConstrainSelectedInstOperands, |
| 18063 | // GIR_Coverage, 1013, |
| 18064 | GIR_EraseRootFromParent_Done, |
| 18065 | // Label 1096: @47922 |
| 18066 | GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(47976), // Rule ID 1014 // |
| 18067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18068 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 18069 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18070 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18071 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18073 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18074 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18075 | // (intrinsic_wo_chain:{ *:[v2i32] } 3438:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 18076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv2i32), |
| 18077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18078 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18079 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18081 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18082 | GIR_RootConstrainSelectedInstOperands, |
| 18083 | // GIR_Coverage, 1014, |
| 18084 | GIR_EraseRootFromParent_Done, |
| 18085 | // Label 1097: @47976 |
| 18086 | GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(48030), // Rule ID 1015 // |
| 18087 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18088 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 18089 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18090 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18091 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18092 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18093 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18094 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18095 | // (intrinsic_wo_chain:{ *:[v8i16] } 3438:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 18096 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i16), |
| 18097 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18098 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18099 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18101 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18102 | GIR_RootConstrainSelectedInstOperands, |
| 18103 | // GIR_Coverage, 1015, |
| 18104 | GIR_EraseRootFromParent_Done, |
| 18105 | // Label 1098: @48030 |
| 18106 | GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(48084), // Rule ID 1016 // |
| 18107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18108 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 18109 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18110 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18111 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18113 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18114 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18115 | // (intrinsic_wo_chain:{ *:[v4i32] } 3438:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 18116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i32), |
| 18117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18118 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18119 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18121 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18122 | GIR_RootConstrainSelectedInstOperands, |
| 18123 | // GIR_Coverage, 1016, |
| 18124 | GIR_EraseRootFromParent_Done, |
| 18125 | // Label 1099: @48084 |
| 18126 | GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(48138), // Rule ID 1017 // |
| 18127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18128 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 18129 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 18130 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 18131 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18132 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18133 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18134 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18135 | // (intrinsic_wo_chain:{ *:[v8i8] } 3438:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 18136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i8), |
| 18137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18138 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18139 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18141 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18142 | GIR_RootConstrainSelectedInstOperands, |
| 18143 | // GIR_Coverage, 1017, |
| 18144 | GIR_EraseRootFromParent_Done, |
| 18145 | // Label 1100: @48138 |
| 18146 | GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(48192), // Rule ID 1018 // |
| 18147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18148 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 18149 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 18150 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 18151 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 18152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18153 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18154 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18155 | // (intrinsic_wo_chain:{ *:[v16i8] } 3438:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 18156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv16i8), |
| 18157 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18158 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18159 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18161 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18162 | GIR_RootConstrainSelectedInstOperands, |
| 18163 | // GIR_Coverage, 1018, |
| 18164 | GIR_EraseRootFromParent_Done, |
| 18165 | // Label 1101: @48192 |
| 18166 | GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(48246), // Rule ID 1019 // |
| 18167 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18168 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 18169 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18170 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18171 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18173 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18174 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18175 | // (intrinsic_wo_chain:{ *:[v4i16] } 3439:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i16), |
| 18177 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18178 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18179 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18180 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18181 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18182 | GIR_RootConstrainSelectedInstOperands, |
| 18183 | // GIR_Coverage, 1019, |
| 18184 | GIR_EraseRootFromParent_Done, |
| 18185 | // Label 1102: @48246 |
| 18186 | GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(48300), // Rule ID 1020 // |
| 18187 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18188 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 18189 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18190 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18191 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18192 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18193 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18194 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18195 | // (intrinsic_wo_chain:{ *:[v2i32] } 3439:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 18196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv2i32), |
| 18197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18198 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18199 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18201 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18202 | GIR_RootConstrainSelectedInstOperands, |
| 18203 | // GIR_Coverage, 1020, |
| 18204 | GIR_EraseRootFromParent_Done, |
| 18205 | // Label 1103: @48300 |
| 18206 | GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(48354), // Rule ID 1021 // |
| 18207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18208 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 18209 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18210 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18211 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18213 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18214 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18215 | // (intrinsic_wo_chain:{ *:[v8i16] } 3439:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 18216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i16), |
| 18217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18218 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18219 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18221 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18222 | GIR_RootConstrainSelectedInstOperands, |
| 18223 | // GIR_Coverage, 1021, |
| 18224 | GIR_EraseRootFromParent_Done, |
| 18225 | // Label 1104: @48354 |
| 18226 | GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(48408), // Rule ID 1022 // |
| 18227 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18228 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 18229 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18230 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18231 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18233 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18234 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18235 | // (intrinsic_wo_chain:{ *:[v4i32] } 3439:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 18236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i32), |
| 18237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18238 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18239 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18241 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18242 | GIR_RootConstrainSelectedInstOperands, |
| 18243 | // GIR_Coverage, 1022, |
| 18244 | GIR_EraseRootFromParent_Done, |
| 18245 | // Label 1105: @48408 |
| 18246 | GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(48462), // Rule ID 1023 // |
| 18247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18248 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 18249 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 18250 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 18251 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18252 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18253 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18254 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18255 | // (intrinsic_wo_chain:{ *:[v8i8] } 3439:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 18256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i8), |
| 18257 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18258 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18259 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18261 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18262 | GIR_RootConstrainSelectedInstOperands, |
| 18263 | // GIR_Coverage, 1023, |
| 18264 | GIR_EraseRootFromParent_Done, |
| 18265 | // Label 1106: @48462 |
| 18266 | GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(48516), // Rule ID 1024 // |
| 18267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18268 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 18269 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 18270 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 18271 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 18272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18273 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18274 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18275 | // (intrinsic_wo_chain:{ *:[v16i8] } 3439:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 18276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv16i8), |
| 18277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18278 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18279 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18281 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18282 | GIR_RootConstrainSelectedInstOperands, |
| 18283 | // GIR_Coverage, 1024, |
| 18284 | GIR_EraseRootFromParent_Done, |
| 18285 | // Label 1107: @48516 |
| 18286 | GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(48570), // Rule ID 1041 // |
| 18287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18288 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn), |
| 18289 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 18290 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18291 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18293 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18294 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18295 | // (intrinsic_wo_chain:{ *:[v8i8] } 3509:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 18296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv8i8), |
| 18297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18298 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18299 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18301 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18302 | GIR_RootConstrainSelectedInstOperands, |
| 18303 | // GIR_Coverage, 1041, |
| 18304 | GIR_EraseRootFromParent_Done, |
| 18305 | // Label 1108: @48570 |
| 18306 | GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(48624), // Rule ID 1042 // |
| 18307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18308 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn), |
| 18309 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18310 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18311 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18313 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18314 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18315 | // (intrinsic_wo_chain:{ *:[v4i16] } 3509:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 18316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv4i16), |
| 18317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18318 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18319 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18321 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18322 | GIR_RootConstrainSelectedInstOperands, |
| 18323 | // GIR_Coverage, 1042, |
| 18324 | GIR_EraseRootFromParent_Done, |
| 18325 | // Label 1109: @48624 |
| 18326 | GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(48678), // Rule ID 1043 // |
| 18327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18328 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn), |
| 18329 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18330 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 18331 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 18332 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18333 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18334 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18335 | // (intrinsic_wo_chain:{ *:[v2i32] } 3509:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 18336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv2i32), |
| 18337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18338 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18339 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18341 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18342 | GIR_RootConstrainSelectedInstOperands, |
| 18343 | // GIR_Coverage, 1043, |
| 18344 | GIR_EraseRootFromParent_Done, |
| 18345 | // Label 1110: @48678 |
| 18346 | GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(48732), // Rule ID 1136 // |
| 18347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18348 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 18349 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18350 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18351 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18353 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18354 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18355 | // (intrinsic_wo_chain:{ *:[v2i32] } 3414:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 18356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfd), |
| 18357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18358 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18359 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18361 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18362 | GIR_RootConstrainSelectedInstOperands, |
| 18363 | // GIR_Coverage, 1136, |
| 18364 | GIR_EraseRootFromParent_Done, |
| 18365 | // Label 1111: @48732 |
| 18366 | GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(48786), // Rule ID 1137 // |
| 18367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18368 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 18369 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18370 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18371 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18372 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18373 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18374 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18375 | // (intrinsic_wo_chain:{ *:[v4i32] } 3414:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 18376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfq), |
| 18377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18378 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18379 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18381 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18382 | GIR_RootConstrainSelectedInstOperands, |
| 18383 | // GIR_Coverage, 1137, |
| 18384 | GIR_EraseRootFromParent_Done, |
| 18385 | // Label 1112: @48786 |
| 18386 | GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(48840), // Rule ID 1138 // |
| 18387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18388 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 18389 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18390 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18391 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18392 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18393 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18394 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18395 | // (intrinsic_wo_chain:{ *:[v4i16] } 3414:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 18396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhd), |
| 18397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18398 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18399 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18401 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18402 | GIR_RootConstrainSelectedInstOperands, |
| 18403 | // GIR_Coverage, 1138, |
| 18404 | GIR_EraseRootFromParent_Done, |
| 18405 | // Label 1113: @48840 |
| 18406 | GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(48894), // Rule ID 1139 // |
| 18407 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18408 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 18409 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18410 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18411 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18412 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18413 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18414 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18415 | // (intrinsic_wo_chain:{ *:[v8i16] } 3414:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 18416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhq), |
| 18417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18418 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18419 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18421 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18422 | GIR_RootConstrainSelectedInstOperands, |
| 18423 | // GIR_Coverage, 1139, |
| 18424 | GIR_EraseRootFromParent_Done, |
| 18425 | // Label 1114: @48894 |
| 18426 | GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(48948), // Rule ID 1140 // |
| 18427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18428 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 18429 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18430 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18431 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18432 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18433 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18434 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18435 | // (intrinsic_wo_chain:{ *:[v2i32] } 3415:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 18436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfd), |
| 18437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18438 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18439 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18441 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18442 | GIR_RootConstrainSelectedInstOperands, |
| 18443 | // GIR_Coverage, 1140, |
| 18444 | GIR_EraseRootFromParent_Done, |
| 18445 | // Label 1115: @48948 |
| 18446 | GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(49002), // Rule ID 1141 // |
| 18447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18448 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 18449 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18450 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18451 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18452 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18453 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18454 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18455 | // (intrinsic_wo_chain:{ *:[v4i32] } 3415:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 18456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfq), |
| 18457 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18458 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18459 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18461 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18462 | GIR_RootConstrainSelectedInstOperands, |
| 18463 | // GIR_Coverage, 1141, |
| 18464 | GIR_EraseRootFromParent_Done, |
| 18465 | // Label 1116: @49002 |
| 18466 | GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(49056), // Rule ID 1142 // |
| 18467 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18468 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 18469 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18470 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18471 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18472 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18473 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18474 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18475 | // (intrinsic_wo_chain:{ *:[v4i16] } 3415:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 18476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThd), |
| 18477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18478 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18479 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18481 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18482 | GIR_RootConstrainSelectedInstOperands, |
| 18483 | // GIR_Coverage, 1142, |
| 18484 | GIR_EraseRootFromParent_Done, |
| 18485 | // Label 1117: @49056 |
| 18486 | GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(49110), // Rule ID 1143 // |
| 18487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18488 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 18489 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18490 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18491 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18492 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18493 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18494 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18495 | // (intrinsic_wo_chain:{ *:[v8i16] } 3415:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 18496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThq), |
| 18497 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18498 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18499 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18501 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18502 | GIR_RootConstrainSelectedInstOperands, |
| 18503 | // GIR_Coverage, 1143, |
| 18504 | GIR_EraseRootFromParent_Done, |
| 18505 | // Label 1118: @49110 |
| 18506 | GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(49164), // Rule ID 1188 // |
| 18507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18508 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 18509 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18510 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18511 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18513 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18514 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18515 | // (intrinsic_wo_chain:{ *:[v2f32] } 3411:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 18516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfd), |
| 18517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18518 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18519 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18521 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18522 | GIR_RootConstrainSelectedInstOperands, |
| 18523 | // GIR_Coverage, 1188, |
| 18524 | GIR_EraseRootFromParent_Done, |
| 18525 | // Label 1119: @49164 |
| 18526 | GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(49218), // Rule ID 1189 // |
| 18527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18528 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 18529 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18530 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18531 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18532 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18533 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18534 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18535 | // (intrinsic_wo_chain:{ *:[v4f32] } 3411:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 18536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfq), |
| 18537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18538 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18539 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18541 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18542 | GIR_RootConstrainSelectedInstOperands, |
| 18543 | // GIR_Coverage, 1189, |
| 18544 | GIR_EraseRootFromParent_Done, |
| 18545 | // Label 1120: @49218 |
| 18546 | GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(49272), // Rule ID 1190 // |
| 18547 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18548 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 18549 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18550 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18551 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18552 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18553 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18554 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18555 | // (intrinsic_wo_chain:{ *:[v4f16] } 3411:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 18556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhd), |
| 18557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18558 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18559 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18560 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18561 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18562 | GIR_RootConstrainSelectedInstOperands, |
| 18563 | // GIR_Coverage, 1190, |
| 18564 | GIR_EraseRootFromParent_Done, |
| 18565 | // Label 1121: @49272 |
| 18566 | GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(49326), // Rule ID 1191 // |
| 18567 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18568 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 18569 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18570 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18571 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18573 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18574 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18575 | // (intrinsic_wo_chain:{ *:[v8f16] } 3411:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 18576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhq), |
| 18577 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18578 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18579 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18581 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18582 | GIR_RootConstrainSelectedInstOperands, |
| 18583 | // GIR_Coverage, 1191, |
| 18584 | GIR_EraseRootFromParent_Done, |
| 18585 | // Label 1122: @49326 |
| 18586 | GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(49380), // Rule ID 1256 // |
| 18587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18588 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 18589 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 18590 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 18591 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18592 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18593 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18594 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18595 | // (intrinsic_wo_chain:{ *:[v8i8] } 3465:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 18596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi8), |
| 18597 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18598 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18599 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18601 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18602 | GIR_RootConstrainSelectedInstOperands, |
| 18603 | // GIR_Coverage, 1256, |
| 18604 | GIR_EraseRootFromParent_Done, |
| 18605 | // Label 1123: @49380 |
| 18606 | GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(49434), // Rule ID 1257 // |
| 18607 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18608 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 18609 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18610 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18611 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18613 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18614 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18615 | // (intrinsic_wo_chain:{ *:[v4i16] } 3465:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi16), |
| 18617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18618 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18619 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18621 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18622 | GIR_RootConstrainSelectedInstOperands, |
| 18623 | // GIR_Coverage, 1257, |
| 18624 | GIR_EraseRootFromParent_Done, |
| 18625 | // Label 1124: @49434 |
| 18626 | GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(49488), // Rule ID 1258 // |
| 18627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18628 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 18629 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18630 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18631 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18633 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18634 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18635 | // (intrinsic_wo_chain:{ *:[v2i32] } 3465:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 18636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi32), |
| 18637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18638 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18639 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18641 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18642 | GIR_RootConstrainSelectedInstOperands, |
| 18643 | // GIR_Coverage, 1258, |
| 18644 | GIR_EraseRootFromParent_Done, |
| 18645 | // Label 1125: @49488 |
| 18646 | GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(49542), // Rule ID 1259 // |
| 18647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18648 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 18649 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18650 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18651 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18652 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18653 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18654 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18655 | // (intrinsic_wo_chain:{ *:[v2f32] } 3465:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 18656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDf), |
| 18657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18658 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18659 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18661 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18662 | GIR_RootConstrainSelectedInstOperands, |
| 18663 | // GIR_Coverage, 1259, |
| 18664 | GIR_EraseRootFromParent_Done, |
| 18665 | // Label 1126: @49542 |
| 18666 | GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(49596), // Rule ID 1260 // |
| 18667 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 18668 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 18669 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18670 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18671 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18672 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18673 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18674 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18675 | // (intrinsic_wo_chain:{ *:[v4f16] } 3465:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 18676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDh), |
| 18677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18678 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18679 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18680 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18681 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18682 | GIR_RootConstrainSelectedInstOperands, |
| 18683 | // GIR_Coverage, 1260, |
| 18684 | GIR_EraseRootFromParent_Done, |
| 18685 | // Label 1127: @49596 |
| 18686 | GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(49650), // Rule ID 1273 // |
| 18687 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18688 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 18689 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18690 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18691 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18693 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18694 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18695 | // (intrinsic_wo_chain:{ *:[v4i16] } 3463:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) |
| 18696 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i8), |
| 18697 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18698 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 18699 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18701 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18702 | GIR_RootConstrainSelectedInstOperands, |
| 18703 | // GIR_Coverage, 1273, |
| 18704 | GIR_EraseRootFromParent_Done, |
| 18705 | // Label 1128: @49650 |
| 18706 | GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(49704), // Rule ID 1274 // |
| 18707 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18708 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 18709 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18710 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18711 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18713 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18714 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18715 | // (intrinsic_wo_chain:{ *:[v2i32] } 3463:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) |
| 18716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i16), |
| 18717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18718 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 18719 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18721 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18722 | GIR_RootConstrainSelectedInstOperands, |
| 18723 | // GIR_Coverage, 1274, |
| 18724 | GIR_EraseRootFromParent_Done, |
| 18725 | // Label 1129: @49704 |
| 18726 | GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(49758), // Rule ID 1275 // |
| 18727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18728 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 18729 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 18730 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 18731 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18732 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18733 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18734 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18735 | // (intrinsic_wo_chain:{ *:[v1i64] } 3463:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) |
| 18736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv2i32), |
| 18737 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18738 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 18739 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18741 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18742 | GIR_RootConstrainSelectedInstOperands, |
| 18743 | // GIR_Coverage, 1275, |
| 18744 | GIR_EraseRootFromParent_Done, |
| 18745 | // Label 1130: @49758 |
| 18746 | GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(49812), // Rule ID 1276 // |
| 18747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18748 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 18749 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18750 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18751 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 18752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18753 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18754 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18755 | // (intrinsic_wo_chain:{ *:[v8i16] } 3463:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) |
| 18756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv16i8), |
| 18757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18758 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 18759 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18761 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18762 | GIR_RootConstrainSelectedInstOperands, |
| 18763 | // GIR_Coverage, 1276, |
| 18764 | GIR_EraseRootFromParent_Done, |
| 18765 | // Label 1131: @49812 |
| 18766 | GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(49866), // Rule ID 1277 // |
| 18767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18768 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 18769 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18770 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18771 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18772 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18773 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18774 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18775 | // (intrinsic_wo_chain:{ *:[v4i32] } 3463:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) |
| 18776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i16), |
| 18777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18778 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 18779 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18781 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18782 | GIR_RootConstrainSelectedInstOperands, |
| 18783 | // GIR_Coverage, 1277, |
| 18784 | GIR_EraseRootFromParent_Done, |
| 18785 | // Label 1132: @49866 |
| 18786 | GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(49920), // Rule ID 1278 // |
| 18787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18788 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 18789 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 18790 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 18791 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18793 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18794 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18795 | // (intrinsic_wo_chain:{ *:[v2i64] } 3463:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) |
| 18796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i32), |
| 18797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18798 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 18799 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18801 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18802 | GIR_RootConstrainSelectedInstOperands, |
| 18803 | // GIR_Coverage, 1278, |
| 18804 | GIR_EraseRootFromParent_Done, |
| 18805 | // Label 1133: @49920 |
| 18806 | GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(49974), // Rule ID 1279 // |
| 18807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18808 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 18809 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18810 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18811 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18812 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18813 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18814 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18815 | // (intrinsic_wo_chain:{ *:[v4i16] } 3464:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) |
| 18816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i8), |
| 18817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18818 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 18819 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18821 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18822 | GIR_RootConstrainSelectedInstOperands, |
| 18823 | // GIR_Coverage, 1279, |
| 18824 | GIR_EraseRootFromParent_Done, |
| 18825 | // Label 1134: @49974 |
| 18826 | GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(50028), // Rule ID 1280 // |
| 18827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18828 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 18829 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18830 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18831 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18832 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18833 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18834 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18835 | // (intrinsic_wo_chain:{ *:[v2i32] } 3464:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) |
| 18836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i16), |
| 18837 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18838 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 18839 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18841 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18842 | GIR_RootConstrainSelectedInstOperands, |
| 18843 | // GIR_Coverage, 1280, |
| 18844 | GIR_EraseRootFromParent_Done, |
| 18845 | // Label 1135: @50028 |
| 18846 | GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(50082), // Rule ID 1281 // |
| 18847 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18848 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 18849 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 18850 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 18851 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18853 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18854 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18855 | // (intrinsic_wo_chain:{ *:[v1i64] } 3464:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) |
| 18856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv2i32), |
| 18857 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18858 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 18859 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18861 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18862 | GIR_RootConstrainSelectedInstOperands, |
| 18863 | // GIR_Coverage, 1281, |
| 18864 | GIR_EraseRootFromParent_Done, |
| 18865 | // Label 1136: @50082 |
| 18866 | GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(50136), // Rule ID 1282 // |
| 18867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18868 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 18869 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18870 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18871 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 18872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18873 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18874 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18875 | // (intrinsic_wo_chain:{ *:[v8i16] } 3464:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) |
| 18876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv16i8), |
| 18877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18878 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 18879 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18881 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18882 | GIR_RootConstrainSelectedInstOperands, |
| 18883 | // GIR_Coverage, 1282, |
| 18884 | GIR_EraseRootFromParent_Done, |
| 18885 | // Label 1137: @50136 |
| 18886 | GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(50190), // Rule ID 1283 // |
| 18887 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18888 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 18889 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18890 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18891 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18892 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18893 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18894 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18895 | // (intrinsic_wo_chain:{ *:[v4i32] } 3464:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) |
| 18896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i16), |
| 18897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18898 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 18899 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18901 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18902 | GIR_RootConstrainSelectedInstOperands, |
| 18903 | // GIR_Coverage, 1283, |
| 18904 | GIR_EraseRootFromParent_Done, |
| 18905 | // Label 1138: @50190 |
| 18906 | GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(50244), // Rule ID 1284 // |
| 18907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18908 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 18909 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 18910 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 18911 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18912 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18913 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18914 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18915 | // (intrinsic_wo_chain:{ *:[v2i64] } 3464:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) |
| 18916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i32), |
| 18917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18918 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 18919 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18921 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18922 | GIR_RootConstrainSelectedInstOperands, |
| 18923 | // GIR_Coverage, 1284, |
| 18924 | GIR_EraseRootFromParent_Done, |
| 18925 | // Label 1139: @50244 |
| 18926 | GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(50298), // Rule ID 1285 // |
| 18927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18928 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 18929 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 18930 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 18931 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18933 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18934 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18935 | // (intrinsic_wo_chain:{ *:[v8i8] } 3468:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 18936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs8), |
| 18937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18938 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18939 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18941 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18942 | GIR_RootConstrainSelectedInstOperands, |
| 18943 | // GIR_Coverage, 1285, |
| 18944 | GIR_EraseRootFromParent_Done, |
| 18945 | // Label 1140: @50298 |
| 18946 | GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(50352), // Rule ID 1286 // |
| 18947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18948 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 18949 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18950 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18951 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18952 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18953 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18954 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18955 | // (intrinsic_wo_chain:{ *:[v4i16] } 3468:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs16), |
| 18957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18958 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18959 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18961 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18962 | GIR_RootConstrainSelectedInstOperands, |
| 18963 | // GIR_Coverage, 1286, |
| 18964 | GIR_EraseRootFromParent_Done, |
| 18965 | // Label 1141: @50352 |
| 18966 | GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(50406), // Rule ID 1287 // |
| 18967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18968 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 18969 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18970 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18971 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18972 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18973 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18974 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18975 | // (intrinsic_wo_chain:{ *:[v2i32] } 3468:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 18976 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs32), |
| 18977 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18978 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18979 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18981 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18982 | GIR_RootConstrainSelectedInstOperands, |
| 18983 | // GIR_Coverage, 1287, |
| 18984 | GIR_EraseRootFromParent_Done, |
| 18985 | // Label 1142: @50406 |
| 18986 | GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(50460), // Rule ID 1288 // |
| 18987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18988 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu), |
| 18989 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 18990 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 18991 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18992 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18993 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18994 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18995 | // (intrinsic_wo_chain:{ *:[v8i8] } 3469:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 18996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu8), |
| 18997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18998 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18999 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19001 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19002 | GIR_RootConstrainSelectedInstOperands, |
| 19003 | // GIR_Coverage, 1288, |
| 19004 | GIR_EraseRootFromParent_Done, |
| 19005 | // Label 1143: @50460 |
| 19006 | GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(50514), // Rule ID 1289 // |
| 19007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19008 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu), |
| 19009 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19010 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19011 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19012 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19013 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19014 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19015 | // (intrinsic_wo_chain:{ *:[v4i16] } 3469:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu16), |
| 19017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19018 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19019 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19021 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19022 | GIR_RootConstrainSelectedInstOperands, |
| 19023 | // GIR_Coverage, 1289, |
| 19024 | GIR_EraseRootFromParent_Done, |
| 19025 | // Label 1144: @50514 |
| 19026 | GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(50568), // Rule ID 1290 // |
| 19027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19028 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu), |
| 19029 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19030 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19031 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19032 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19033 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19034 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19035 | // (intrinsic_wo_chain:{ *:[v2i32] } 3469:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu32), |
| 19037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19038 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19039 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19041 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19042 | GIR_RootConstrainSelectedInstOperands, |
| 19043 | // GIR_Coverage, 1290, |
| 19044 | GIR_EraseRootFromParent_Done, |
| 19045 | // Label 1145: @50568 |
| 19046 | GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(50622), // Rule ID 1291 // |
| 19047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19048 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 19049 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19050 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19051 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19052 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19053 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19054 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19055 | // (intrinsic_wo_chain:{ *:[v2f32] } 3468:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 19056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXf), |
| 19057 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19058 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19059 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19061 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19062 | GIR_RootConstrainSelectedInstOperands, |
| 19063 | // GIR_Coverage, 1291, |
| 19064 | GIR_EraseRootFromParent_Done, |
| 19065 | // Label 1146: @50622 |
| 19066 | GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(50676), // Rule ID 1292 // |
| 19067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19068 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 19069 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19070 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19071 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19073 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19074 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19075 | // (intrinsic_wo_chain:{ *:[v4f16] } 3468:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 19076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXh), |
| 19077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19078 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19079 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19081 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19082 | GIR_RootConstrainSelectedInstOperands, |
| 19083 | // GIR_Coverage, 1292, |
| 19084 | GIR_EraseRootFromParent_Done, |
| 19085 | // Label 1147: @50676 |
| 19086 | GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(50730), // Rule ID 1293 // |
| 19087 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19088 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 19089 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 19090 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19091 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19092 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19093 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19094 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19095 | // (intrinsic_wo_chain:{ *:[v8i8] } 3470:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19096 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs8), |
| 19097 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19098 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19099 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19101 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19102 | GIR_RootConstrainSelectedInstOperands, |
| 19103 | // GIR_Coverage, 1293, |
| 19104 | GIR_EraseRootFromParent_Done, |
| 19105 | // Label 1148: @50730 |
| 19106 | GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(50784), // Rule ID 1294 // |
| 19107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19108 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 19109 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19110 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19111 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19113 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19114 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19115 | // (intrinsic_wo_chain:{ *:[v4i16] } 3470:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs16), |
| 19117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19118 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19119 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19121 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19122 | GIR_RootConstrainSelectedInstOperands, |
| 19123 | // GIR_Coverage, 1294, |
| 19124 | GIR_EraseRootFromParent_Done, |
| 19125 | // Label 1149: @50784 |
| 19126 | GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(50838), // Rule ID 1295 // |
| 19127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19128 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 19129 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19130 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19131 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19132 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19133 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19134 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19135 | // (intrinsic_wo_chain:{ *:[v2i32] } 3470:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs32), |
| 19137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19138 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19139 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19141 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19142 | GIR_RootConstrainSelectedInstOperands, |
| 19143 | // GIR_Coverage, 1295, |
| 19144 | GIR_EraseRootFromParent_Done, |
| 19145 | // Label 1150: @50838 |
| 19146 | GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(50892), // Rule ID 1296 // |
| 19147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19148 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu), |
| 19149 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 19150 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19151 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19153 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19154 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19155 | // (intrinsic_wo_chain:{ *:[v8i8] } 3471:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu8), |
| 19157 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19158 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19159 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19161 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19162 | GIR_RootConstrainSelectedInstOperands, |
| 19163 | // GIR_Coverage, 1296, |
| 19164 | GIR_EraseRootFromParent_Done, |
| 19165 | // Label 1151: @50892 |
| 19166 | GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(50946), // Rule ID 1297 // |
| 19167 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19168 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu), |
| 19169 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19170 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19171 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19173 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19174 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19175 | // (intrinsic_wo_chain:{ *:[v4i16] } 3471:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu16), |
| 19177 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19178 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19179 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19180 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19181 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19182 | GIR_RootConstrainSelectedInstOperands, |
| 19183 | // GIR_Coverage, 1297, |
| 19184 | GIR_EraseRootFromParent_Done, |
| 19185 | // Label 1152: @50946 |
| 19186 | GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(51000), // Rule ID 1298 // |
| 19187 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19188 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu), |
| 19189 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19190 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19191 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19192 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19193 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19194 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19195 | // (intrinsic_wo_chain:{ *:[v2i32] } 3471:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu32), |
| 19197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19198 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19199 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19201 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19202 | GIR_RootConstrainSelectedInstOperands, |
| 19203 | // GIR_Coverage, 1298, |
| 19204 | GIR_EraseRootFromParent_Done, |
| 19205 | // Label 1153: @51000 |
| 19206 | GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(51054), // Rule ID 1299 // |
| 19207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19208 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 19209 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19210 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19211 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19213 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19214 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19215 | // (intrinsic_wo_chain:{ *:[v2f32] } 3470:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 19216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINf), |
| 19217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19218 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19219 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19221 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19222 | GIR_RootConstrainSelectedInstOperands, |
| 19223 | // GIR_Coverage, 1299, |
| 19224 | GIR_EraseRootFromParent_Done, |
| 19225 | // Label 1154: @51054 |
| 19226 | GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(51108), // Rule ID 1300 // |
| 19227 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19228 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 19229 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19230 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19231 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19233 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19234 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19235 | // (intrinsic_wo_chain:{ *:[v4f16] } 3470:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 19236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINh), |
| 19237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19238 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19239 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19241 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19242 | GIR_RootConstrainSelectedInstOperands, |
| 19243 | // GIR_Coverage, 1300, |
| 19244 | GIR_EraseRootFromParent_Done, |
| 19245 | // Label 1155: @51108 |
| 19246 | GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(51162), // Rule ID 1307 // |
| 19247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19248 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 19249 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19250 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19251 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19252 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19253 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19254 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19255 | // (intrinsic_wo_chain:{ *:[v2f32] } 3495:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 19256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfd), |
| 19257 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19258 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19259 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19261 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19262 | GIR_RootConstrainSelectedInstOperands, |
| 19263 | // GIR_Coverage, 1307, |
| 19264 | GIR_EraseRootFromParent_Done, |
| 19265 | // Label 1156: @51162 |
| 19266 | GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(51216), // Rule ID 1308 // |
| 19267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19268 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 19269 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 19270 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19271 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19273 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19274 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19275 | // (intrinsic_wo_chain:{ *:[v4f32] } 3495:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 19276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfq), |
| 19277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19278 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19279 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19281 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19282 | GIR_RootConstrainSelectedInstOperands, |
| 19283 | // GIR_Coverage, 1308, |
| 19284 | GIR_EraseRootFromParent_Done, |
| 19285 | // Label 1157: @51216 |
| 19286 | GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(51270), // Rule ID 1309 // |
| 19287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19288 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 19289 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19290 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19291 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19293 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19294 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19295 | // (intrinsic_wo_chain:{ *:[v4f16] } 3495:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 19296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShd), |
| 19297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19298 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19299 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19301 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19302 | GIR_RootConstrainSelectedInstOperands, |
| 19303 | // GIR_Coverage, 1309, |
| 19304 | GIR_EraseRootFromParent_Done, |
| 19305 | // Label 1158: @51270 |
| 19306 | GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(51324), // Rule ID 1310 // |
| 19307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19308 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 19309 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 19310 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19311 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19313 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19314 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19315 | // (intrinsic_wo_chain:{ *:[v8f16] } 3495:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 19316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShq), |
| 19317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19318 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19319 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19321 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19322 | GIR_RootConstrainSelectedInstOperands, |
| 19323 | // GIR_Coverage, 1310, |
| 19324 | GIR_EraseRootFromParent_Done, |
| 19325 | // Label 1159: @51324 |
| 19326 | GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(51378), // Rule ID 1317 // |
| 19327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19328 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 19329 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19330 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19331 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19332 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19333 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19334 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19335 | // (intrinsic_wo_chain:{ *:[v2f32] } 3508:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 19336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfd), |
| 19337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19338 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19339 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19341 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19342 | GIR_RootConstrainSelectedInstOperands, |
| 19343 | // GIR_Coverage, 1317, |
| 19344 | GIR_EraseRootFromParent_Done, |
| 19345 | // Label 1160: @51378 |
| 19346 | GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(51432), // Rule ID 1318 // |
| 19347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19348 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 19349 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 19350 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19351 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19353 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19354 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19355 | // (intrinsic_wo_chain:{ *:[v4f32] } 3508:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 19356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfq), |
| 19357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19358 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19359 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19361 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19362 | GIR_RootConstrainSelectedInstOperands, |
| 19363 | // GIR_Coverage, 1318, |
| 19364 | GIR_EraseRootFromParent_Done, |
| 19365 | // Label 1161: @51432 |
| 19366 | GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(51486), // Rule ID 1319 // |
| 19367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19368 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 19369 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19370 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19371 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19372 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19373 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19374 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19375 | // (intrinsic_wo_chain:{ *:[v4f16] } 3508:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 19376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShd), |
| 19377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19378 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19379 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19381 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19382 | GIR_RootConstrainSelectedInstOperands, |
| 19383 | // GIR_Coverage, 1319, |
| 19384 | GIR_EraseRootFromParent_Done, |
| 19385 | // Label 1162: @51486 |
| 19386 | GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(51540), // Rule ID 1320 // |
| 19387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19388 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 19389 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 19390 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19391 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19392 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19393 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19394 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19395 | // (intrinsic_wo_chain:{ *:[v8f16] } 3508:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 19396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShq), |
| 19397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19398 | GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19399 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19401 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19402 | GIR_RootConstrainSelectedInstOperands, |
| 19403 | // GIR_Coverage, 1320, |
| 19404 | GIR_EraseRootFromParent_Done, |
| 19405 | // Label 1163: @51540 |
| 19406 | GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(51594), // Rule ID 1321 // |
| 19407 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19408 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 19409 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19410 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19411 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19412 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19413 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19414 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19415 | // (intrinsic_wo_chain:{ *:[v4i16] } 3511:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 19416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i16), |
| 19417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19418 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19419 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19421 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19422 | GIR_RootConstrainSelectedInstOperands, |
| 19423 | // GIR_Coverage, 1321, |
| 19424 | GIR_EraseRootFromParent_Done, |
| 19425 | // Label 1164: @51594 |
| 19426 | GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(51648), // Rule ID 1322 // |
| 19427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19428 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 19429 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19430 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19431 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19432 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19433 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19434 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19435 | // (intrinsic_wo_chain:{ *:[v2i32] } 3511:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 19436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i32), |
| 19437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19438 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19439 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19441 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19442 | GIR_RootConstrainSelectedInstOperands, |
| 19443 | // GIR_Coverage, 1322, |
| 19444 | GIR_EraseRootFromParent_Done, |
| 19445 | // Label 1165: @51648 |
| 19446 | GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(51702), // Rule ID 1323 // |
| 19447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19448 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 19449 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 19450 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19451 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19452 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19453 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19454 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19455 | // (intrinsic_wo_chain:{ *:[v8i16] } 3511:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 19456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i16), |
| 19457 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19458 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19459 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19461 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19462 | GIR_RootConstrainSelectedInstOperands, |
| 19463 | // GIR_Coverage, 1323, |
| 19464 | GIR_EraseRootFromParent_Done, |
| 19465 | // Label 1166: @51702 |
| 19466 | GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(51756), // Rule ID 1324 // |
| 19467 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19468 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 19469 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 19470 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19471 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19472 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19473 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19474 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19475 | // (intrinsic_wo_chain:{ *:[v4i32] } 3511:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 19476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i32), |
| 19477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19478 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19479 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19481 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19482 | GIR_RootConstrainSelectedInstOperands, |
| 19483 | // GIR_Coverage, 1324, |
| 19484 | GIR_EraseRootFromParent_Done, |
| 19485 | // Label 1167: @51756 |
| 19486 | GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(51810), // Rule ID 1325 // |
| 19487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19488 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 19489 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 19490 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19491 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19492 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19493 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19494 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19495 | // (intrinsic_wo_chain:{ *:[v8i8] } 3511:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 19496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i8), |
| 19497 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19498 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19499 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19501 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19502 | GIR_RootConstrainSelectedInstOperands, |
| 19503 | // GIR_Coverage, 1325, |
| 19504 | GIR_EraseRootFromParent_Done, |
| 19505 | // Label 1168: @51810 |
| 19506 | GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(51864), // Rule ID 1326 // |
| 19507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19508 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 19509 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 19510 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19511 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19513 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19514 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19515 | // (intrinsic_wo_chain:{ *:[v16i8] } 3511:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 19516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv16i8), |
| 19517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19518 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19519 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19521 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19522 | GIR_RootConstrainSelectedInstOperands, |
| 19523 | // GIR_Coverage, 1326, |
| 19524 | GIR_EraseRootFromParent_Done, |
| 19525 | // Label 1169: @51864 |
| 19526 | GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(51918), // Rule ID 1327 // |
| 19527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19528 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 19529 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 19530 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 19531 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 19532 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19533 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19534 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19535 | // (intrinsic_wo_chain:{ *:[v1i64] } 3511:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 19536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv1i64), |
| 19537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19538 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19539 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19541 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19542 | GIR_RootConstrainSelectedInstOperands, |
| 19543 | // GIR_Coverage, 1327, |
| 19544 | GIR_EraseRootFromParent_Done, |
| 19545 | // Label 1170: @51918 |
| 19546 | GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(51972), // Rule ID 1328 // |
| 19547 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19548 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 19549 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 19550 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19551 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 19552 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19553 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19554 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19555 | // (intrinsic_wo_chain:{ *:[v2i64] } 3511:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 19556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i64), |
| 19557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19558 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19559 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19560 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19561 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19562 | GIR_RootConstrainSelectedInstOperands, |
| 19563 | // GIR_Coverage, 1328, |
| 19564 | GIR_EraseRootFromParent_Done, |
| 19565 | // Label 1171: @51972 |
| 19566 | GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(52026), // Rule ID 1329 // |
| 19567 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19568 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 19569 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19570 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19571 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19573 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19574 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19575 | // (intrinsic_wo_chain:{ *:[v4i16] } 3512:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 19576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i16), |
| 19577 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19578 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19579 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19581 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19582 | GIR_RootConstrainSelectedInstOperands, |
| 19583 | // GIR_Coverage, 1329, |
| 19584 | GIR_EraseRootFromParent_Done, |
| 19585 | // Label 1172: @52026 |
| 19586 | GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(52080), // Rule ID 1330 // |
| 19587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19588 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 19589 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19590 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19591 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19592 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19593 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19594 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19595 | // (intrinsic_wo_chain:{ *:[v2i32] } 3512:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 19596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i32), |
| 19597 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19598 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19599 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19601 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19602 | GIR_RootConstrainSelectedInstOperands, |
| 19603 | // GIR_Coverage, 1330, |
| 19604 | GIR_EraseRootFromParent_Done, |
| 19605 | // Label 1173: @52080 |
| 19606 | GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(52134), // Rule ID 1331 // |
| 19607 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19608 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 19609 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 19610 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19611 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19613 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19614 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19615 | // (intrinsic_wo_chain:{ *:[v8i16] } 3512:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 19616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i16), |
| 19617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19618 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19619 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19621 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19622 | GIR_RootConstrainSelectedInstOperands, |
| 19623 | // GIR_Coverage, 1331, |
| 19624 | GIR_EraseRootFromParent_Done, |
| 19625 | // Label 1174: @52134 |
| 19626 | GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(52188), // Rule ID 1332 // |
| 19627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19628 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 19629 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 19630 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19631 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19633 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19634 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19635 | // (intrinsic_wo_chain:{ *:[v4i32] } 3512:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 19636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i32), |
| 19637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19638 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19639 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19641 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19642 | GIR_RootConstrainSelectedInstOperands, |
| 19643 | // GIR_Coverage, 1332, |
| 19644 | GIR_EraseRootFromParent_Done, |
| 19645 | // Label 1175: @52188 |
| 19646 | GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(52242), // Rule ID 1333 // |
| 19647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19648 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 19649 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 19650 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19651 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19652 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19653 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19654 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19655 | // (intrinsic_wo_chain:{ *:[v8i8] } 3512:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 19656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i8), |
| 19657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19658 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19659 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19661 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19662 | GIR_RootConstrainSelectedInstOperands, |
| 19663 | // GIR_Coverage, 1333, |
| 19664 | GIR_EraseRootFromParent_Done, |
| 19665 | // Label 1176: @52242 |
| 19666 | GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(52296), // Rule ID 1334 // |
| 19667 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19668 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 19669 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 19670 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19671 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19672 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19673 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19674 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19675 | // (intrinsic_wo_chain:{ *:[v16i8] } 3512:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 19676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv16i8), |
| 19677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19678 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19679 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19680 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19681 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19682 | GIR_RootConstrainSelectedInstOperands, |
| 19683 | // GIR_Coverage, 1334, |
| 19684 | GIR_EraseRootFromParent_Done, |
| 19685 | // Label 1177: @52296 |
| 19686 | GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(52350), // Rule ID 1335 // |
| 19687 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19688 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 19689 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 19690 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 19691 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 19692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19693 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19694 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19695 | // (intrinsic_wo_chain:{ *:[v1i64] } 3512:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 19696 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv1i64), |
| 19697 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19698 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19699 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19701 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19702 | GIR_RootConstrainSelectedInstOperands, |
| 19703 | // GIR_Coverage, 1335, |
| 19704 | GIR_EraseRootFromParent_Done, |
| 19705 | // Label 1178: @52350 |
| 19706 | GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(52404), // Rule ID 1336 // |
| 19707 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19708 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 19709 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 19710 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19711 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 19712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19713 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19714 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19715 | // (intrinsic_wo_chain:{ *:[v2i64] } 3512:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 19716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i64), |
| 19717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19718 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19719 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19721 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19722 | GIR_RootConstrainSelectedInstOperands, |
| 19723 | // GIR_Coverage, 1336, |
| 19724 | GIR_EraseRootFromParent_Done, |
| 19725 | // Label 1179: @52404 |
| 19726 | GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(52458), // Rule ID 1370 // |
| 19727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19728 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 19729 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19730 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19731 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19732 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19733 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19734 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19735 | // (intrinsic_wo_chain:{ *:[v4i16] } 3505:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 19736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i16), |
| 19737 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19738 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19739 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19741 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19742 | GIR_RootConstrainSelectedInstOperands, |
| 19743 | // GIR_Coverage, 1370, |
| 19744 | GIR_EraseRootFromParent_Done, |
| 19745 | // Label 1180: @52458 |
| 19746 | GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(52512), // Rule ID 1371 // |
| 19747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19748 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 19749 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19750 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19751 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19753 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19754 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19755 | // (intrinsic_wo_chain:{ *:[v2i32] } 3505:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 19756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i32), |
| 19757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19758 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19759 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19761 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19762 | GIR_RootConstrainSelectedInstOperands, |
| 19763 | // GIR_Coverage, 1371, |
| 19764 | GIR_EraseRootFromParent_Done, |
| 19765 | // Label 1181: @52512 |
| 19766 | GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(52566), // Rule ID 1372 // |
| 19767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19768 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 19769 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 19770 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19771 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19772 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19773 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19774 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19775 | // (intrinsic_wo_chain:{ *:[v8i16] } 3505:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 19776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i16), |
| 19777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19778 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19779 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19781 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19782 | GIR_RootConstrainSelectedInstOperands, |
| 19783 | // GIR_Coverage, 1372, |
| 19784 | GIR_EraseRootFromParent_Done, |
| 19785 | // Label 1182: @52566 |
| 19786 | GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(52620), // Rule ID 1373 // |
| 19787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19788 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 19789 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 19790 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19791 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19793 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19794 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19795 | // (intrinsic_wo_chain:{ *:[v4i32] } 3505:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 19796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i32), |
| 19797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19798 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19799 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19801 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19802 | GIR_RootConstrainSelectedInstOperands, |
| 19803 | // GIR_Coverage, 1373, |
| 19804 | GIR_EraseRootFromParent_Done, |
| 19805 | // Label 1183: @52620 |
| 19806 | GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(52674), // Rule ID 1374 // |
| 19807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19808 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 19809 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 19810 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19811 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19812 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19813 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19814 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19815 | // (intrinsic_wo_chain:{ *:[v8i8] } 3505:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 19816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i8), |
| 19817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19818 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19819 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19821 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19822 | GIR_RootConstrainSelectedInstOperands, |
| 19823 | // GIR_Coverage, 1374, |
| 19824 | GIR_EraseRootFromParent_Done, |
| 19825 | // Label 1184: @52674 |
| 19826 | GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(52728), // Rule ID 1375 // |
| 19827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19828 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 19829 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 19830 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19831 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19832 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19833 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19834 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19835 | // (intrinsic_wo_chain:{ *:[v16i8] } 3505:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 19836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv16i8), |
| 19837 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19838 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19839 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19841 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19842 | GIR_RootConstrainSelectedInstOperands, |
| 19843 | // GIR_Coverage, 1375, |
| 19844 | GIR_EraseRootFromParent_Done, |
| 19845 | // Label 1185: @52728 |
| 19846 | GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(52782), // Rule ID 1376 // |
| 19847 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19848 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 19849 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 19850 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 19851 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 19852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19853 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19854 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19855 | // (intrinsic_wo_chain:{ *:[v1i64] } 3505:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 19856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv1i64), |
| 19857 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19858 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19859 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19861 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19862 | GIR_RootConstrainSelectedInstOperands, |
| 19863 | // GIR_Coverage, 1376, |
| 19864 | GIR_EraseRootFromParent_Done, |
| 19865 | // Label 1186: @52782 |
| 19866 | GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(52836), // Rule ID 1377 // |
| 19867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19868 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 19869 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 19870 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19871 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 19872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19873 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19874 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19875 | // (intrinsic_wo_chain:{ *:[v2i64] } 3505:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 19876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i64), |
| 19877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19878 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19879 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19881 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19882 | GIR_RootConstrainSelectedInstOperands, |
| 19883 | // GIR_Coverage, 1377, |
| 19884 | GIR_EraseRootFromParent_Done, |
| 19885 | // Label 1187: @52836 |
| 19886 | GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(52890), // Rule ID 1378 // |
| 19887 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19888 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 19889 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19890 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19891 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19892 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19893 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19894 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19895 | // (intrinsic_wo_chain:{ *:[v4i16] } 3506:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 19896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i16), |
| 19897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19898 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19899 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19901 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19902 | GIR_RootConstrainSelectedInstOperands, |
| 19903 | // GIR_Coverage, 1378, |
| 19904 | GIR_EraseRootFromParent_Done, |
| 19905 | // Label 1188: @52890 |
| 19906 | GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(52944), // Rule ID 1379 // |
| 19907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19908 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 19909 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19910 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19911 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19912 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19913 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19914 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19915 | // (intrinsic_wo_chain:{ *:[v2i32] } 3506:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 19916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i32), |
| 19917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19918 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19919 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19921 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19922 | GIR_RootConstrainSelectedInstOperands, |
| 19923 | // GIR_Coverage, 1379, |
| 19924 | GIR_EraseRootFromParent_Done, |
| 19925 | // Label 1189: @52944 |
| 19926 | GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(52998), // Rule ID 1380 // |
| 19927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19928 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 19929 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 19930 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19931 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19933 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19934 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19935 | // (intrinsic_wo_chain:{ *:[v8i16] } 3506:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 19936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i16), |
| 19937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19938 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19939 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19941 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19942 | GIR_RootConstrainSelectedInstOperands, |
| 19943 | // GIR_Coverage, 1380, |
| 19944 | GIR_EraseRootFromParent_Done, |
| 19945 | // Label 1190: @52998 |
| 19946 | GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(53052), // Rule ID 1381 // |
| 19947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19948 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 19949 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 19950 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19951 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19952 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19953 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19954 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19955 | // (intrinsic_wo_chain:{ *:[v4i32] } 3506:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 19956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i32), |
| 19957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19958 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19959 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19961 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19962 | GIR_RootConstrainSelectedInstOperands, |
| 19963 | // GIR_Coverage, 1381, |
| 19964 | GIR_EraseRootFromParent_Done, |
| 19965 | // Label 1191: @53052 |
| 19966 | GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(53106), // Rule ID 1382 // |
| 19967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19968 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 19969 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 19970 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19971 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19972 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19973 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19974 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19975 | // (intrinsic_wo_chain:{ *:[v8i8] } 3506:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 19976 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i8), |
| 19977 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19978 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19979 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 19980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19981 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19982 | GIR_RootConstrainSelectedInstOperands, |
| 19983 | // GIR_Coverage, 1382, |
| 19984 | GIR_EraseRootFromParent_Done, |
| 19985 | // Label 1192: @53106 |
| 19986 | GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(53160), // Rule ID 1383 // |
| 19987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19988 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 19989 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 19990 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19991 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19992 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19993 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19994 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19995 | // (intrinsic_wo_chain:{ *:[v16i8] } 3506:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 19996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv16i8), |
| 19997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19998 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 19999 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20001 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20002 | GIR_RootConstrainSelectedInstOperands, |
| 20003 | // GIR_Coverage, 1383, |
| 20004 | GIR_EraseRootFromParent_Done, |
| 20005 | // Label 1193: @53160 |
| 20006 | GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(53214), // Rule ID 1384 // |
| 20007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20008 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 20009 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 20010 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20011 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 20012 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20013 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20014 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20015 | // (intrinsic_wo_chain:{ *:[v1i64] } 3506:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 20016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv1i64), |
| 20017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20018 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20019 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20021 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20022 | GIR_RootConstrainSelectedInstOperands, |
| 20023 | // GIR_Coverage, 1384, |
| 20024 | GIR_EraseRootFromParent_Done, |
| 20025 | // Label 1194: @53214 |
| 20026 | GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(53268), // Rule ID 1385 // |
| 20027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20028 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 20029 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 20030 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20031 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 20032 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20033 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20034 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20035 | // (intrinsic_wo_chain:{ *:[v2i64] } 3506:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 20036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i64), |
| 20037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20038 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20039 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20041 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20042 | GIR_RootConstrainSelectedInstOperands, |
| 20043 | // GIR_Coverage, 1385, |
| 20044 | GIR_EraseRootFromParent_Done, |
| 20045 | // Label 1195: @53268 |
| 20046 | GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(53322), // Rule ID 1405 // |
| 20047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20048 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20049 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20050 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20051 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20052 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20053 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20054 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20055 | // (intrinsic_wo_chain:{ *:[v4i16] } 3490:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 20056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i16), |
| 20057 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20058 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20059 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20061 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20062 | GIR_RootConstrainSelectedInstOperands, |
| 20063 | // GIR_Coverage, 1405, |
| 20064 | GIR_EraseRootFromParent_Done, |
| 20065 | // Label 1196: @53322 |
| 20066 | GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(53376), // Rule ID 1406 // |
| 20067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20068 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20069 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20070 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20071 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20073 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20074 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20075 | // (intrinsic_wo_chain:{ *:[v2i32] } 3490:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 20076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i32), |
| 20077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20078 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20079 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20081 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20082 | GIR_RootConstrainSelectedInstOperands, |
| 20083 | // GIR_Coverage, 1406, |
| 20084 | GIR_EraseRootFromParent_Done, |
| 20085 | // Label 1197: @53376 |
| 20086 | GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(53430), // Rule ID 1407 // |
| 20087 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20088 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20089 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20090 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20091 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20092 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20093 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20094 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20095 | // (intrinsic_wo_chain:{ *:[v8i16] } 3490:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 20096 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i16), |
| 20097 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20098 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20099 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20101 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20102 | GIR_RootConstrainSelectedInstOperands, |
| 20103 | // GIR_Coverage, 1407, |
| 20104 | GIR_EraseRootFromParent_Done, |
| 20105 | // Label 1198: @53430 |
| 20106 | GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(53484), // Rule ID 1408 // |
| 20107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20108 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20109 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20110 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20111 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20113 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20114 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20115 | // (intrinsic_wo_chain:{ *:[v4i32] } 3490:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 20116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i32), |
| 20117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20118 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20119 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20121 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20122 | GIR_RootConstrainSelectedInstOperands, |
| 20123 | // GIR_Coverage, 1408, |
| 20124 | GIR_EraseRootFromParent_Done, |
| 20125 | // Label 1199: @53484 |
| 20126 | GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(53538), // Rule ID 1409 // |
| 20127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20128 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20129 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20130 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20131 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20132 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20133 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20134 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20135 | // (intrinsic_wo_chain:{ *:[v8i8] } 3490:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 20136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i8), |
| 20137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20138 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20139 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20141 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20142 | GIR_RootConstrainSelectedInstOperands, |
| 20143 | // GIR_Coverage, 1409, |
| 20144 | GIR_EraseRootFromParent_Done, |
| 20145 | // Label 1200: @53538 |
| 20146 | GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(53592), // Rule ID 1410 // |
| 20147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20148 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20149 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20150 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20151 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20153 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20154 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20155 | // (intrinsic_wo_chain:{ *:[v16i8] } 3490:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 20156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv16i8), |
| 20157 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20158 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20159 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20161 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20162 | GIR_RootConstrainSelectedInstOperands, |
| 20163 | // GIR_Coverage, 1410, |
| 20164 | GIR_EraseRootFromParent_Done, |
| 20165 | // Label 1201: @53592 |
| 20166 | GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(53646), // Rule ID 1411 // |
| 20167 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20168 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20169 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 20170 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20171 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 20172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20173 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20174 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20175 | // (intrinsic_wo_chain:{ *:[v1i64] } 3490:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 20176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv1i64), |
| 20177 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20178 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20179 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20180 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20181 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20182 | GIR_RootConstrainSelectedInstOperands, |
| 20183 | // GIR_Coverage, 1411, |
| 20184 | GIR_EraseRootFromParent_Done, |
| 20185 | // Label 1202: @53646 |
| 20186 | GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(53700), // Rule ID 1412 // |
| 20187 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20188 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20189 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 20190 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20191 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 20192 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20193 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20194 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20195 | // (intrinsic_wo_chain:{ *:[v2i64] } 3490:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 20196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i64), |
| 20197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20198 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20199 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20201 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20202 | GIR_RootConstrainSelectedInstOperands, |
| 20203 | // GIR_Coverage, 1412, |
| 20204 | GIR_EraseRootFromParent_Done, |
| 20205 | // Label 1203: @53700 |
| 20206 | GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(53754), // Rule ID 1413 // |
| 20207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20208 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 20209 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20210 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20211 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20213 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20214 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20215 | // (intrinsic_wo_chain:{ *:[v4i16] } 3492:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 20216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i16), |
| 20217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20218 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20219 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20221 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20222 | GIR_RootConstrainSelectedInstOperands, |
| 20223 | // GIR_Coverage, 1413, |
| 20224 | GIR_EraseRootFromParent_Done, |
| 20225 | // Label 1204: @53754 |
| 20226 | GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(53808), // Rule ID 1414 // |
| 20227 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20228 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 20229 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20230 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20231 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20233 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20234 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20235 | // (intrinsic_wo_chain:{ *:[v2i32] } 3492:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 20236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i32), |
| 20237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20238 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20239 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20241 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20242 | GIR_RootConstrainSelectedInstOperands, |
| 20243 | // GIR_Coverage, 1414, |
| 20244 | GIR_EraseRootFromParent_Done, |
| 20245 | // Label 1205: @53808 |
| 20246 | GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(53862), // Rule ID 1415 // |
| 20247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20248 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 20249 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20250 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20251 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20252 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20253 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20254 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20255 | // (intrinsic_wo_chain:{ *:[v8i16] } 3492:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 20256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i16), |
| 20257 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20258 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20259 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20261 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20262 | GIR_RootConstrainSelectedInstOperands, |
| 20263 | // GIR_Coverage, 1415, |
| 20264 | GIR_EraseRootFromParent_Done, |
| 20265 | // Label 1206: @53862 |
| 20266 | GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(53916), // Rule ID 1416 // |
| 20267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20268 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 20269 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20270 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20271 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20273 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20274 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20275 | // (intrinsic_wo_chain:{ *:[v4i32] } 3492:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 20276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i32), |
| 20277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20278 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20279 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20281 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20282 | GIR_RootConstrainSelectedInstOperands, |
| 20283 | // GIR_Coverage, 1416, |
| 20284 | GIR_EraseRootFromParent_Done, |
| 20285 | // Label 1207: @53916 |
| 20286 | GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(53970), // Rule ID 1417 // |
| 20287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20288 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 20289 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20290 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20291 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20293 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20294 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20295 | // (intrinsic_wo_chain:{ *:[v8i8] } 3492:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 20296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i8), |
| 20297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20298 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20299 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20301 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20302 | GIR_RootConstrainSelectedInstOperands, |
| 20303 | // GIR_Coverage, 1417, |
| 20304 | GIR_EraseRootFromParent_Done, |
| 20305 | // Label 1208: @53970 |
| 20306 | GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(54024), // Rule ID 1418 // |
| 20307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20308 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 20309 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20310 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20311 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20313 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20314 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20315 | // (intrinsic_wo_chain:{ *:[v16i8] } 3492:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 20316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv16i8), |
| 20317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20318 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20319 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20321 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20322 | GIR_RootConstrainSelectedInstOperands, |
| 20323 | // GIR_Coverage, 1418, |
| 20324 | GIR_EraseRootFromParent_Done, |
| 20325 | // Label 1209: @54024 |
| 20326 | GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(54078), // Rule ID 1419 // |
| 20327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20328 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 20329 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 20330 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20331 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 20332 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20333 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20334 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20335 | // (intrinsic_wo_chain:{ *:[v1i64] } 3492:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 20336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv1i64), |
| 20337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20338 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20339 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20341 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20342 | GIR_RootConstrainSelectedInstOperands, |
| 20343 | // GIR_Coverage, 1419, |
| 20344 | GIR_EraseRootFromParent_Done, |
| 20345 | // Label 1210: @54078 |
| 20346 | GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(54132), // Rule ID 1420 // |
| 20347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20348 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 20349 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 20350 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20351 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 20352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20353 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20354 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20355 | // (intrinsic_wo_chain:{ *:[v2i64] } 3492:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 20356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i64), |
| 20357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20358 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20359 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20361 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20362 | GIR_RootConstrainSelectedInstOperands, |
| 20363 | // GIR_Coverage, 1420, |
| 20364 | GIR_EraseRootFromParent_Done, |
| 20365 | // Label 1211: @54132 |
| 20366 | GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(54186), // Rule ID 1454 // |
| 20367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20368 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 20369 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20370 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20371 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20372 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20373 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20374 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20375 | // (intrinsic_wo_chain:{ *:[v4i16] } 3485:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 20376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i16), |
| 20377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20378 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20379 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20381 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20382 | GIR_RootConstrainSelectedInstOperands, |
| 20383 | // GIR_Coverage, 1454, |
| 20384 | GIR_EraseRootFromParent_Done, |
| 20385 | // Label 1212: @54186 |
| 20386 | GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(54240), // Rule ID 1455 // |
| 20387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20388 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 20389 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20390 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20391 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20392 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20393 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20394 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20395 | // (intrinsic_wo_chain:{ *:[v2i32] } 3485:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 20396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i32), |
| 20397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20398 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20399 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20401 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20402 | GIR_RootConstrainSelectedInstOperands, |
| 20403 | // GIR_Coverage, 1455, |
| 20404 | GIR_EraseRootFromParent_Done, |
| 20405 | // Label 1213: @54240 |
| 20406 | GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(54294), // Rule ID 1456 // |
| 20407 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20408 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 20409 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20410 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20411 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20412 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20413 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20414 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20415 | // (intrinsic_wo_chain:{ *:[v8i16] } 3485:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 20416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i16), |
| 20417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20418 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20419 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20421 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20422 | GIR_RootConstrainSelectedInstOperands, |
| 20423 | // GIR_Coverage, 1456, |
| 20424 | GIR_EraseRootFromParent_Done, |
| 20425 | // Label 1214: @54294 |
| 20426 | GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(54348), // Rule ID 1457 // |
| 20427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20428 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 20429 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20430 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20431 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20432 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20433 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20434 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20435 | // (intrinsic_wo_chain:{ *:[v4i32] } 3485:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 20436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i32), |
| 20437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20438 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20439 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20441 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20442 | GIR_RootConstrainSelectedInstOperands, |
| 20443 | // GIR_Coverage, 1457, |
| 20444 | GIR_EraseRootFromParent_Done, |
| 20445 | // Label 1215: @54348 |
| 20446 | GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(54402), // Rule ID 1458 // |
| 20447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20448 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 20449 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20450 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20451 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20452 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20453 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20454 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20455 | // (intrinsic_wo_chain:{ *:[v8i8] } 3485:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 20456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i8), |
| 20457 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20458 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20459 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20461 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20462 | GIR_RootConstrainSelectedInstOperands, |
| 20463 | // GIR_Coverage, 1458, |
| 20464 | GIR_EraseRootFromParent_Done, |
| 20465 | // Label 1216: @54402 |
| 20466 | GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(54456), // Rule ID 1459 // |
| 20467 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20468 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 20469 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20470 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20471 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20472 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20473 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20474 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20475 | // (intrinsic_wo_chain:{ *:[v16i8] } 3485:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 20476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv16i8), |
| 20477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20478 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20479 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20481 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20482 | GIR_RootConstrainSelectedInstOperands, |
| 20483 | // GIR_Coverage, 1459, |
| 20484 | GIR_EraseRootFromParent_Done, |
| 20485 | // Label 1217: @54456 |
| 20486 | GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(54510), // Rule ID 1460 // |
| 20487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20488 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 20489 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 20490 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20491 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 20492 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20493 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20494 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20495 | // (intrinsic_wo_chain:{ *:[v1i64] } 3485:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 20496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv1i64), |
| 20497 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20498 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20499 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20501 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20502 | GIR_RootConstrainSelectedInstOperands, |
| 20503 | // GIR_Coverage, 1460, |
| 20504 | GIR_EraseRootFromParent_Done, |
| 20505 | // Label 1218: @54510 |
| 20506 | GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(54564), // Rule ID 1461 // |
| 20507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20508 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 20509 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 20510 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20511 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 20512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20513 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20514 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20515 | // (intrinsic_wo_chain:{ *:[v2i64] } 3485:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 20516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i64), |
| 20517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20518 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20519 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20521 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20522 | GIR_RootConstrainSelectedInstOperands, |
| 20523 | // GIR_Coverage, 1461, |
| 20524 | GIR_EraseRootFromParent_Done, |
| 20525 | // Label 1219: @54564 |
| 20526 | GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(54618), // Rule ID 1462 // |
| 20527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20528 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 20529 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20530 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20531 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20532 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20533 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20534 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20535 | // (intrinsic_wo_chain:{ *:[v4i16] } 3486:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 20536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i16), |
| 20537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20538 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20539 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20541 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20542 | GIR_RootConstrainSelectedInstOperands, |
| 20543 | // GIR_Coverage, 1462, |
| 20544 | GIR_EraseRootFromParent_Done, |
| 20545 | // Label 1220: @54618 |
| 20546 | GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(54672), // Rule ID 1463 // |
| 20547 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20548 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 20549 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20550 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20551 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20552 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20553 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20554 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20555 | // (intrinsic_wo_chain:{ *:[v2i32] } 3486:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 20556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i32), |
| 20557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20558 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20559 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20560 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20561 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20562 | GIR_RootConstrainSelectedInstOperands, |
| 20563 | // GIR_Coverage, 1463, |
| 20564 | GIR_EraseRootFromParent_Done, |
| 20565 | // Label 1221: @54672 |
| 20566 | GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(54726), // Rule ID 1464 // |
| 20567 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20568 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 20569 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20570 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20571 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20573 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20574 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20575 | // (intrinsic_wo_chain:{ *:[v8i16] } 3486:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 20576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i16), |
| 20577 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20578 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20579 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20581 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20582 | GIR_RootConstrainSelectedInstOperands, |
| 20583 | // GIR_Coverage, 1464, |
| 20584 | GIR_EraseRootFromParent_Done, |
| 20585 | // Label 1222: @54726 |
| 20586 | GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(54780), // Rule ID 1465 // |
| 20587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20588 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 20589 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20590 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20591 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20592 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20593 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20594 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20595 | // (intrinsic_wo_chain:{ *:[v4i32] } 3486:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 20596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i32), |
| 20597 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20598 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20599 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20601 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20602 | GIR_RootConstrainSelectedInstOperands, |
| 20603 | // GIR_Coverage, 1465, |
| 20604 | GIR_EraseRootFromParent_Done, |
| 20605 | // Label 1223: @54780 |
| 20606 | GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(54834), // Rule ID 1466 // |
| 20607 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20608 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 20609 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20610 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20611 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20613 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20614 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20615 | // (intrinsic_wo_chain:{ *:[v8i8] } 3486:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 20616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i8), |
| 20617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20618 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20619 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20621 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20622 | GIR_RootConstrainSelectedInstOperands, |
| 20623 | // GIR_Coverage, 1466, |
| 20624 | GIR_EraseRootFromParent_Done, |
| 20625 | // Label 1224: @54834 |
| 20626 | GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(54888), // Rule ID 1467 // |
| 20627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20628 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 20629 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20630 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20631 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20633 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20634 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20635 | // (intrinsic_wo_chain:{ *:[v16i8] } 3486:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 20636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv16i8), |
| 20637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20638 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20639 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20641 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20642 | GIR_RootConstrainSelectedInstOperands, |
| 20643 | // GIR_Coverage, 1467, |
| 20644 | GIR_EraseRootFromParent_Done, |
| 20645 | // Label 1225: @54888 |
| 20646 | GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(54942), // Rule ID 1468 // |
| 20647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20648 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 20649 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 20650 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20651 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 20652 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20653 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20654 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20655 | // (intrinsic_wo_chain:{ *:[v1i64] } 3486:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 20656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv1i64), |
| 20657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20658 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20659 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20661 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20662 | GIR_RootConstrainSelectedInstOperands, |
| 20663 | // GIR_Coverage, 1468, |
| 20664 | GIR_EraseRootFromParent_Done, |
| 20665 | // Label 1226: @54942 |
| 20666 | GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(54996), // Rule ID 1469 // |
| 20667 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20668 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 20669 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 20670 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20671 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 20672 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20673 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20674 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20675 | // (intrinsic_wo_chain:{ *:[v2i64] } 3486:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 20676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i64), |
| 20677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20678 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20679 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20680 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20681 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20682 | GIR_RootConstrainSelectedInstOperands, |
| 20683 | // GIR_Coverage, 1469, |
| 20684 | GIR_EraseRootFromParent_Done, |
| 20685 | // Label 1227: @54996 |
| 20686 | GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(55041), // Rule ID 1734 // |
| 20687 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 20688 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesd), |
| 20689 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20690 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20691 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20693 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20694 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20695 | // (intrinsic_wo_chain:{ *:[v16i8] } 3387:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) |
| 20696 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESD), |
| 20697 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20698 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 20699 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20700 | GIR_RootConstrainSelectedInstOperands, |
| 20701 | // GIR_Coverage, 1734, |
| 20702 | GIR_EraseRootFromParent_Done, |
| 20703 | // Label 1228: @55041 |
| 20704 | GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(55086), // Rule ID 1735 // |
| 20705 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 20706 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aese), |
| 20707 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20708 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20709 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20710 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20711 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20712 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20713 | // (intrinsic_wo_chain:{ *:[v16i8] } 3388:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) |
| 20714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESE), |
| 20715 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20716 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 20717 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20718 | GIR_RootConstrainSelectedInstOperands, |
| 20719 | // GIR_Coverage, 1735, |
| 20720 | GIR_EraseRootFromParent_Done, |
| 20721 | // Label 1229: @55086 |
| 20722 | GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(55131), // Rule ID 1738 // |
| 20723 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 20724 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su1), |
| 20725 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20726 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20727 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20728 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20729 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20730 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20731 | // (intrinsic_wo_chain:{ *:[v4i32] } 3401:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) |
| 20732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU1), |
| 20733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20734 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 20735 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20736 | GIR_RootConstrainSelectedInstOperands, |
| 20737 | // GIR_Coverage, 1738, |
| 20738 | GIR_EraseRootFromParent_Done, |
| 20739 | // Label 1230: @55131 |
| 20740 | GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(55176), // Rule ID 1739 // |
| 20741 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 20742 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su0), |
| 20743 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20744 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20745 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20746 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20747 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20748 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20749 | // (intrinsic_wo_chain:{ *:[v4i32] } 3404:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) |
| 20750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU0), |
| 20751 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20752 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 20753 | GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20754 | GIR_RootConstrainSelectedInstOperands, |
| 20755 | // GIR_Coverage, 1739, |
| 20756 | GIR_EraseRootFromParent_Done, |
| 20757 | // Label 1231: @55176 |
| 20758 | GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(55230), // Rule ID 1753 // |
| 20759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 20760 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqrshr), |
| 20761 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 20762 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20763 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 20764 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 20765 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 20766 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 20767 | // (intrinsic_wo_chain:{ *:[i32] } 3249:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) |
| 20768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQRSHR), |
| 20769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 20770 | GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 20771 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 20772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20773 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20774 | GIR_RootConstrainSelectedInstOperands, |
| 20775 | // GIR_Coverage, 1753, |
| 20776 | GIR_EraseRootFromParent_Done, |
| 20777 | // Label 1232: @55230 |
| 20778 | GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(55284), // Rule ID 1754 // |
| 20779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 20780 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqrshl), |
| 20781 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 20782 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20783 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 20784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 20785 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 20786 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 20787 | // (intrinsic_wo_chain:{ *:[i32] } 3256:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) |
| 20788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQRSHL), |
| 20789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 20790 | GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 20791 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 20792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20793 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20794 | GIR_RootConstrainSelectedInstOperands, |
| 20795 | // GIR_Coverage, 1754, |
| 20796 | GIR_EraseRootFromParent_Done, |
| 20797 | // Label 1233: @55284 |
| 20798 | GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(55341), // Rule ID 1877 // |
| 20799 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 20800 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16), |
| 20801 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 20802 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20803 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 20804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20805 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20806 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20807 | // (intrinsic_wo_chain:{ *:[i32] } 3588:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] }) |
| 20808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB16), |
| 20809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 20810 | GIR_RootToRootCopy, /*OpIdx*/2, // LHS |
| 20811 | GIR_RootToRootCopy, /*OpIdx*/3, // RHS |
| 20812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20814 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20815 | GIR_RootConstrainSelectedInstOperands, |
| 20816 | // GIR_Coverage, 1877, |
| 20817 | GIR_EraseRootFromParent_Done, |
| 20818 | // Label 1234: @55341 |
| 20819 | GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(55398), // Rule ID 1884 // |
| 20820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 20821 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16), |
| 20822 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 20823 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20824 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 20825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20826 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20827 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20828 | // (intrinsic_wo_chain:{ *:[i32] } 3613:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] }) |
| 20829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB16), |
| 20830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 20831 | GIR_RootToRootCopy, /*OpIdx*/2, // LHS |
| 20832 | GIR_RootToRootCopy, /*OpIdx*/3, // RHS |
| 20833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20835 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20836 | GIR_RootConstrainSelectedInstOperands, |
| 20837 | // GIR_Coverage, 1884, |
| 20838 | GIR_EraseRootFromParent_Done, |
| 20839 | // Label 1235: @55398 |
| 20840 | GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(55452), // Rule ID 1931 // |
| 20841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 20842 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad), |
| 20843 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 20844 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20845 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 20846 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20847 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20848 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20849 | // (intrinsic_wo_chain:{ *:[i32] } 3564:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 20850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUAD), |
| 20851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 20852 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 20853 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 20854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20855 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20856 | GIR_RootConstrainSelectedInstOperands, |
| 20857 | // GIR_Coverage, 1931, |
| 20858 | GIR_EraseRootFromParent_Done, |
| 20859 | // Label 1236: @55452 |
| 20860 | GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(55506), // Rule ID 1932 // |
| 20861 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 20862 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx), |
| 20863 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 20864 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20865 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 20866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20867 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20868 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20869 | // (intrinsic_wo_chain:{ *:[i32] } 3565:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 20870 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUADX), |
| 20871 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 20872 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 20873 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 20874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20875 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20876 | GIR_RootConstrainSelectedInstOperands, |
| 20877 | // GIR_Coverage, 1932, |
| 20878 | GIR_EraseRootFromParent_Done, |
| 20879 | // Label 1237: @55506 |
| 20880 | GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(55560), // Rule ID 1933 // |
| 20881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 20882 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd), |
| 20883 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 20884 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20885 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 20886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20887 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20888 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20889 | // (intrinsic_wo_chain:{ *:[i32] } 3572:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 20890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSD), |
| 20891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 20892 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 20893 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 20894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20895 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20896 | GIR_RootConstrainSelectedInstOperands, |
| 20897 | // GIR_Coverage, 1933, |
| 20898 | GIR_EraseRootFromParent_Done, |
| 20899 | // Label 1238: @55560 |
| 20900 | GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(55614), // Rule ID 1934 // |
| 20901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 20902 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx), |
| 20903 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 20904 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20905 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 20906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20907 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20908 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 20909 | // (intrinsic_wo_chain:{ *:[i32] } 3573:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 20910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSDX), |
| 20911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 20912 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 20913 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 20914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20915 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20916 | GIR_RootConstrainSelectedInstOperands, |
| 20917 | // GIR_Coverage, 1934, |
| 20918 | GIR_EraseRootFromParent_Done, |
| 20919 | // Label 1239: @55614 |
| 20920 | GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(55668), // Rule ID 1999 // |
| 20921 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 20922 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb), |
| 20923 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 20924 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20925 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 20926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20927 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20928 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20929 | // (intrinsic_wo_chain:{ *:[i32] } 3566:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 20930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB), |
| 20931 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 20932 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 20933 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 20934 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20935 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20936 | GIR_RootConstrainSelectedInstOperands, |
| 20937 | // GIR_Coverage, 1999, |
| 20938 | GIR_EraseRootFromParent_Done, |
| 20939 | // Label 1240: @55668 |
| 20940 | GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(55722), // Rule ID 2000 // |
| 20941 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 20942 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt), |
| 20943 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 20944 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20945 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 20946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20947 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20948 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20949 | // (intrinsic_wo_chain:{ *:[i32] } 3567:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 20950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT), |
| 20951 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 20952 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 20953 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 20954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20955 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20956 | GIR_RootConstrainSelectedInstOperands, |
| 20957 | // GIR_Coverage, 2000, |
| 20958 | GIR_EraseRootFromParent_Done, |
| 20959 | // Label 1241: @55722 |
| 20960 | GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(55776), // Rule ID 2001 // |
| 20961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 20962 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb), |
| 20963 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 20964 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20965 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 20966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20967 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20968 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20969 | // (intrinsic_wo_chain:{ *:[i32] } 3568:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 20970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB), |
| 20971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 20972 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 20973 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 20974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20975 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20976 | GIR_RootConstrainSelectedInstOperands, |
| 20977 | // GIR_Coverage, 2001, |
| 20978 | GIR_EraseRootFromParent_Done, |
| 20979 | // Label 1242: @55776 |
| 20980 | GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(55830), // Rule ID 2002 // |
| 20981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 20982 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt), |
| 20983 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 20984 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20985 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 20986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20987 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20988 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 20989 | // (intrinsic_wo_chain:{ *:[i32] } 3569:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 20990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT), |
| 20991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 20992 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 20993 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 20994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20995 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20996 | GIR_RootConstrainSelectedInstOperands, |
| 20997 | // GIR_Coverage, 2002, |
| 20998 | GIR_EraseRootFromParent_Done, |
| 20999 | // Label 1243: @55830 |
| 21000 | GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(55884), // Rule ID 2003 // |
| 21001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 21002 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb), |
| 21003 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21004 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21005 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21007 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21008 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21009 | // (intrinsic_wo_chain:{ *:[i32] } 3570:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 21010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWB), |
| 21011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21012 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 21013 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 21014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21015 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21016 | GIR_RootConstrainSelectedInstOperands, |
| 21017 | // GIR_Coverage, 2003, |
| 21018 | GIR_EraseRootFromParent_Done, |
| 21019 | // Label 1244: @55884 |
| 21020 | GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(55938), // Rule ID 2004 // |
| 21021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 21022 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt), |
| 21023 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21024 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21025 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21027 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21028 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21029 | // (intrinsic_wo_chain:{ *:[i32] } 3571:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 21030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWT), |
| 21031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21032 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 21033 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 21034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21035 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21036 | GIR_RootConstrainSelectedInstOperands, |
| 21037 | // GIR_Coverage, 2004, |
| 21038 | GIR_EraseRootFromParent_Done, |
| 21039 | // Label 1245: @55938 |
| 21040 | GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(55995), // Rule ID 2107 // |
| 21041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21042 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16), |
| 21043 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21044 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21045 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21047 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21048 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21049 | // (intrinsic_wo_chain:{ *:[i32] } 3588:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 21050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB16), |
| 21051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21052 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21053 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21056 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21057 | GIR_RootConstrainSelectedInstOperands, |
| 21058 | // GIR_Coverage, 2107, |
| 21059 | GIR_EraseRootFromParent_Done, |
| 21060 | // Label 1246: @55995 |
| 21061 | GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(56049), // Rule ID 2137 // |
| 21062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21063 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 21064 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21065 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21066 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21068 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21069 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21070 | // (intrinsic_wo_chain:{ *:[i32] } 3531:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 21071 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD), |
| 21072 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21073 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 21074 | GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 21075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21076 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21077 | GIR_RootConstrainSelectedInstOperands, |
| 21078 | // GIR_Coverage, 2137, |
| 21079 | GIR_EraseRootFromParent_Done, |
| 21080 | // Label 1247: @56049 |
| 21081 | GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(56103), // Rule ID 2138 // |
| 21082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21083 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 21084 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21085 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21086 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21087 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21088 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21089 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21090 | // (intrinsic_wo_chain:{ *:[i32] } 3536:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 21091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB), |
| 21092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21093 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 21094 | GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 21095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21096 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21097 | GIR_RootConstrainSelectedInstOperands, |
| 21098 | // GIR_Coverage, 2138, |
| 21099 | GIR_EraseRootFromParent_Done, |
| 21100 | // Label 1248: @56103 |
| 21101 | GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(56157), // Rule ID 2178 // |
| 21102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21103 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb), |
| 21104 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21105 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21106 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21108 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21109 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21110 | // (intrinsic_wo_chain:{ *:[i32] } 3566:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 21111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB), |
| 21112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21113 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21114 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21116 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21117 | GIR_RootConstrainSelectedInstOperands, |
| 21118 | // GIR_Coverage, 2178, |
| 21119 | GIR_EraseRootFromParent_Done, |
| 21120 | // Label 1249: @56157 |
| 21121 | GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(56211), // Rule ID 2179 // |
| 21122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21123 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt), |
| 21124 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21125 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21126 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21128 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21129 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21130 | // (intrinsic_wo_chain:{ *:[i32] } 3567:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 21131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT), |
| 21132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21133 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21134 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21136 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21137 | GIR_RootConstrainSelectedInstOperands, |
| 21138 | // GIR_Coverage, 2179, |
| 21139 | GIR_EraseRootFromParent_Done, |
| 21140 | // Label 1250: @56211 |
| 21141 | GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(56265), // Rule ID 2180 // |
| 21142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21143 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb), |
| 21144 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21145 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21146 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21147 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21148 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21149 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21150 | // (intrinsic_wo_chain:{ *:[i32] } 3568:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 21151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB), |
| 21152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21153 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21154 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21156 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21157 | GIR_RootConstrainSelectedInstOperands, |
| 21158 | // GIR_Coverage, 2180, |
| 21159 | GIR_EraseRootFromParent_Done, |
| 21160 | // Label 1251: @56265 |
| 21161 | GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(56319), // Rule ID 2181 // |
| 21162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21163 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt), |
| 21164 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21165 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21166 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21167 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21168 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21169 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21170 | // (intrinsic_wo_chain:{ *:[i32] } 3569:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 21171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT), |
| 21172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21173 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21174 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21176 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21177 | GIR_RootConstrainSelectedInstOperands, |
| 21178 | // GIR_Coverage, 2181, |
| 21179 | GIR_EraseRootFromParent_Done, |
| 21180 | // Label 1252: @56319 |
| 21181 | GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(56373), // Rule ID 2182 // |
| 21182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21183 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb), |
| 21184 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21185 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21186 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21188 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21189 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21190 | // (intrinsic_wo_chain:{ *:[i32] } 3570:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 21191 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWB), |
| 21192 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21193 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21194 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21196 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21197 | GIR_RootConstrainSelectedInstOperands, |
| 21198 | // GIR_Coverage, 2182, |
| 21199 | GIR_EraseRootFromParent_Done, |
| 21200 | // Label 1253: @56373 |
| 21201 | GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(56427), // Rule ID 2183 // |
| 21202 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21203 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt), |
| 21204 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21205 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21206 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21207 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21208 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21209 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21210 | // (intrinsic_wo_chain:{ *:[i32] } 3571:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 21211 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWT), |
| 21212 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21213 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21214 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21216 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21217 | GIR_RootConstrainSelectedInstOperands, |
| 21218 | // GIR_Coverage, 2183, |
| 21219 | GIR_EraseRootFromParent_Done, |
| 21220 | // Label 1254: @56427 |
| 21221 | GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(56475), // Rule ID 2510 // |
| 21222 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), |
| 21223 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 21224 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21225 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21226 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21227 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21228 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21229 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21230 | // (intrinsic_wo_chain:{ *:[v4f16] } 3418:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] }) |
| 21231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16), |
| 21232 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21233 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21234 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21236 | GIR_RootConstrainSelectedInstOperands, |
| 21237 | // GIR_Coverage, 2510, |
| 21238 | GIR_EraseRootFromParent_Done, |
| 21239 | // Label 1255: @56475 |
| 21240 | GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(56523), // Rule ID 2511 // |
| 21241 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), |
| 21242 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 21243 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21244 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21245 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21246 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21247 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21248 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21249 | // (intrinsic_wo_chain:{ *:[v4f16] } 3417:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] }) |
| 21250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16), |
| 21251 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21252 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21253 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 21255 | GIR_RootConstrainSelectedInstOperands, |
| 21256 | // GIR_Coverage, 2511, |
| 21257 | GIR_EraseRootFromParent_Done, |
| 21258 | // Label 1256: @56523 |
| 21259 | GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(56571), // Rule ID 2512 // |
| 21260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), |
| 21261 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 21262 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21263 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21264 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21265 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21266 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21267 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21268 | // (intrinsic_wo_chain:{ *:[v8f16] } 3418:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] }) |
| 21269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16), |
| 21270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21271 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21272 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21274 | GIR_RootConstrainSelectedInstOperands, |
| 21275 | // GIR_Coverage, 2512, |
| 21276 | GIR_EraseRootFromParent_Done, |
| 21277 | // Label 1257: @56571 |
| 21278 | GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(56619), // Rule ID 2513 // |
| 21279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), |
| 21280 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 21281 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21282 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21283 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21284 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21285 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21286 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21287 | // (intrinsic_wo_chain:{ *:[v8f16] } 3417:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] }) |
| 21288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16), |
| 21289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21290 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21291 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 21293 | GIR_RootConstrainSelectedInstOperands, |
| 21294 | // GIR_Coverage, 2513, |
| 21295 | GIR_EraseRootFromParent_Done, |
| 21296 | // Label 1258: @56619 |
| 21297 | GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(56667), // Rule ID 2514 // |
| 21298 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), |
| 21299 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 21300 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21301 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21302 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21304 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21305 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21306 | // (intrinsic_wo_chain:{ *:[v2f32] } 3418:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] }) |
| 21307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32), |
| 21308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21309 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21310 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21312 | GIR_RootConstrainSelectedInstOperands, |
| 21313 | // GIR_Coverage, 2514, |
| 21314 | GIR_EraseRootFromParent_Done, |
| 21315 | // Label 1259: @56667 |
| 21316 | GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(56715), // Rule ID 2515 // |
| 21317 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), |
| 21318 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 21319 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21320 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21321 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21322 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21323 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21324 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21325 | // (intrinsic_wo_chain:{ *:[v2f32] } 3417:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] }) |
| 21326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32), |
| 21327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21328 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21329 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 21331 | GIR_RootConstrainSelectedInstOperands, |
| 21332 | // GIR_Coverage, 2515, |
| 21333 | GIR_EraseRootFromParent_Done, |
| 21334 | // Label 1260: @56715 |
| 21335 | GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(56763), // Rule ID 2516 // |
| 21336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), |
| 21337 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 21338 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21339 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21340 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21341 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21342 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21343 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21344 | // (intrinsic_wo_chain:{ *:[v4f32] } 3418:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] }) |
| 21345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32), |
| 21346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21347 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21348 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21350 | GIR_RootConstrainSelectedInstOperands, |
| 21351 | // GIR_Coverage, 2516, |
| 21352 | GIR_EraseRootFromParent_Done, |
| 21353 | // Label 1261: @56763 |
| 21354 | GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(56811), // Rule ID 2517 // |
| 21355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), |
| 21356 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 21357 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21358 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21359 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21360 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21361 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21362 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21363 | // (intrinsic_wo_chain:{ *:[v4f32] } 3417:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] }) |
| 21364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32), |
| 21365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21366 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21367 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 21369 | GIR_RootConstrainSelectedInstOperands, |
| 21370 | // GIR_Coverage, 2517, |
| 21371 | GIR_EraseRootFromParent_Done, |
| 21372 | // Label 1262: @56811 |
| 21373 | GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(56913), // Rule ID 3202 // |
| 21374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 21375 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv), |
| 21376 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21377 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21378 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21379 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 21380 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 21381 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21382 | // (intrinsic_wo_chain:{ *:[f32] } 3225:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 21383 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21384 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 21385 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21386 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21387 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 21388 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21389 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf32), |
| 21390 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21391 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 21392 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 21393 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 21394 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21395 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21396 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21398 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 21399 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21400 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 21401 | // GIR_Coverage, 3202, |
| 21402 | GIR_EraseRootFromParent_Done, |
| 21403 | // Label 1263: @56913 |
| 21404 | GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(57015), // Rule ID 3204 // |
| 21405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 21406 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv), |
| 21407 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 21408 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 21409 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21410 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 21411 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 21412 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21413 | // (intrinsic_wo_chain:{ *:[f16] } 3225:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 21414 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21415 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 21416 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21417 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21418 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 21419 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21420 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf16), |
| 21421 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21422 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 21423 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 21424 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 21425 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21426 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21427 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 21430 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21431 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 21432 | // GIR_Coverage, 3204, |
| 21433 | GIR_EraseRootFromParent_Done, |
| 21434 | // Label 1264: @57015 |
| 21435 | GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(57117), // Rule ID 3206 // |
| 21436 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 21437 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv), |
| 21438 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21439 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21440 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21441 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 21442 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 21443 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21444 | // (intrinsic_wo_chain:{ *:[f32] } 3216:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 21445 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21446 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 21447 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21448 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21449 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 21450 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21451 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf32), |
| 21452 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21453 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 21454 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 21455 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 21456 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21457 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21458 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21460 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 21461 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21462 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 21463 | // GIR_Coverage, 3206, |
| 21464 | GIR_EraseRootFromParent_Done, |
| 21465 | // Label 1265: @57117 |
| 21466 | GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(57219), // Rule ID 3208 // |
| 21467 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 21468 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv), |
| 21469 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 21470 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 21471 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21472 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 21473 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 21474 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21475 | // (intrinsic_wo_chain:{ *:[f16] } 3216:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 21476 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21477 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 21478 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21479 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21480 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 21481 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21482 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf16), |
| 21483 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21484 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 21485 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 21486 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 21487 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21488 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21489 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21490 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21491 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 21492 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21493 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 21494 | // GIR_Coverage, 3208, |
| 21495 | GIR_EraseRootFromParent_Done, |
| 21496 | // Label 1266: @57219 |
| 21497 | GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(57321), // Rule ID 3210 // |
| 21498 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 21499 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav), |
| 21500 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21501 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21502 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21503 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 21504 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 21505 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21506 | // (intrinsic_wo_chain:{ *:[f32] } 3223:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 21507 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21508 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 21509 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21510 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21511 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 21512 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21513 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf32), |
| 21514 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21515 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 21516 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 21517 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 21518 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21519 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21520 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21522 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 21523 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21524 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 21525 | // GIR_Coverage, 3210, |
| 21526 | GIR_EraseRootFromParent_Done, |
| 21527 | // Label 1267: @57321 |
| 21528 | GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(57423), // Rule ID 3212 // |
| 21529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 21530 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav), |
| 21531 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 21532 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 21533 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 21535 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 21536 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21537 | // (intrinsic_wo_chain:{ *:[f16] } 3223:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 21538 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21539 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 21540 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21541 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21542 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 21543 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21544 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf16), |
| 21545 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21546 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 21547 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 21548 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 21549 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21550 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21551 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 21554 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21555 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 21556 | // GIR_Coverage, 3212, |
| 21557 | GIR_EraseRootFromParent_Done, |
| 21558 | // Label 1268: @57423 |
| 21559 | GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(57525), // Rule ID 3214 // |
| 21560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 21561 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav), |
| 21562 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21563 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21564 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21565 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 21566 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 21567 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21568 | // (intrinsic_wo_chain:{ *:[f32] } 3214:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 21569 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21570 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 21571 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21572 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21573 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 21574 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21575 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf32), |
| 21576 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21577 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 21578 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 21579 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 21580 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21581 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21582 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 21585 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21586 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 21587 | // GIR_Coverage, 3214, |
| 21588 | GIR_EraseRootFromParent_Done, |
| 21589 | // Label 1269: @57525 |
| 21590 | GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(57627), // Rule ID 3216 // |
| 21591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 21592 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav), |
| 21593 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 21594 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 21595 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21596 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 21597 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 21598 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21599 | // (intrinsic_wo_chain:{ *:[f16] } 3214:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 21600 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21601 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 21602 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21603 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21604 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 21605 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21606 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf16), |
| 21607 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21608 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 21609 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 21610 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 21611 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21612 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21613 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 21616 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21617 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 21618 | // GIR_Coverage, 3216, |
| 21619 | GIR_EraseRootFromParent_Done, |
| 21620 | // Label 1270: @57627 |
| 21621 | GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(57687), // Rule ID 3266 // |
| 21622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21623 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav), |
| 21624 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21625 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21626 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21627 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21628 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21629 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21630 | // (intrinsic_wo_chain:{ *:[i32] } 3221:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMINAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 21631 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs8), |
| 21632 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 21633 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 21634 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 21635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21636 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21637 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21638 | GIR_RootConstrainSelectedInstOperands, |
| 21639 | // GIR_Coverage, 3266, |
| 21640 | GIR_EraseRootFromParent_Done, |
| 21641 | // Label 1271: @57687 |
| 21642 | GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(57747), // Rule ID 3268 // |
| 21643 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21644 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav), |
| 21645 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21646 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21647 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21649 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21650 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21651 | // (intrinsic_wo_chain:{ *:[i32] } 3221:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMINAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 21652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs16), |
| 21653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 21654 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 21655 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 21656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21657 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21658 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21659 | GIR_RootConstrainSelectedInstOperands, |
| 21660 | // GIR_Coverage, 3268, |
| 21661 | GIR_EraseRootFromParent_Done, |
| 21662 | // Label 1272: @57747 |
| 21663 | GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(57807), // Rule ID 3270 // |
| 21664 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21665 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav), |
| 21666 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21667 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21668 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21669 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21670 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21671 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21672 | // (intrinsic_wo_chain:{ *:[i32] } 3221:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMINAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 21673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs32), |
| 21674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 21675 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 21676 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 21677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21678 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21679 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21680 | GIR_RootConstrainSelectedInstOperands, |
| 21681 | // GIR_Coverage, 3270, |
| 21682 | GIR_EraseRootFromParent_Done, |
| 21683 | // Label 1273: @57807 |
| 21684 | GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(57867), // Rule ID 3272 // |
| 21685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21686 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav), |
| 21687 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21688 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21689 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21690 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21691 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21692 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21693 | // (intrinsic_wo_chain:{ *:[i32] } 3212:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMAXAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 21694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs8), |
| 21695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 21696 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 21697 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 21698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21699 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21700 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21701 | GIR_RootConstrainSelectedInstOperands, |
| 21702 | // GIR_Coverage, 3272, |
| 21703 | GIR_EraseRootFromParent_Done, |
| 21704 | // Label 1274: @57867 |
| 21705 | GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(57927), // Rule ID 3274 // |
| 21706 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21707 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav), |
| 21708 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21709 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21710 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21712 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21713 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21714 | // (intrinsic_wo_chain:{ *:[i32] } 3212:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMAXAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 21715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs16), |
| 21716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 21717 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 21718 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 21719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21720 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21721 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21722 | GIR_RootConstrainSelectedInstOperands, |
| 21723 | // GIR_Coverage, 3274, |
| 21724 | GIR_EraseRootFromParent_Done, |
| 21725 | // Label 1275: @57927 |
| 21726 | GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(57987), // Rule ID 3276 // |
| 21727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21728 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav), |
| 21729 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21730 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21731 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21732 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21733 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21734 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21735 | // (intrinsic_wo_chain:{ *:[i32] } 3212:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMAXAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 21736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs32), |
| 21737 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 21738 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 21739 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 21740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21741 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21742 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21743 | GIR_RootConstrainSelectedInstOperands, |
| 21744 | // GIR_Coverage, 3276, |
| 21745 | GIR_EraseRootFromParent_Done, |
| 21746 | // Label 1276: @57987 |
| 21747 | GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(58060), // Rule ID 3567 // |
| 21748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21749 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh), |
| 21750 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 21751 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21752 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21753 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21754 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21755 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21756 | // (intrinsic_wo_chain:{ *:[v16i8] } 3334:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 21757 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 21758 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21759 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 21760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi8), |
| 21761 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 21762 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 21763 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 21764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21765 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21766 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21767 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21768 | GIR_RootConstrainSelectedInstOperands, |
| 21769 | // GIR_Coverage, 3567, |
| 21770 | GIR_EraseRootFromParent_Done, |
| 21771 | // Label 1277: @58060 |
| 21772 | GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(58133), // Rule ID 3574 // |
| 21773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21774 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh), |
| 21775 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21776 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21777 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21779 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21780 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21781 | // (intrinsic_wo_chain:{ *:[v8i16] } 3334:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 21782 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 21783 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21784 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 21785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi16), |
| 21786 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 21787 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 21788 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 21789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21790 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21791 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21792 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21793 | GIR_RootConstrainSelectedInstOperands, |
| 21794 | // GIR_Coverage, 3574, |
| 21795 | GIR_EraseRootFromParent_Done, |
| 21796 | // Label 1278: @58133 |
| 21797 | GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(58206), // Rule ID 3578 // |
| 21798 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21799 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh), |
| 21800 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21801 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21802 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21803 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21804 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21805 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21806 | // (intrinsic_wo_chain:{ *:[v4i32] } 3334:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 21807 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 21808 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21809 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 21810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi32), |
| 21811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 21812 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 21813 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 21814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21815 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21816 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21817 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21818 | GIR_RootConstrainSelectedInstOperands, |
| 21819 | // GIR_Coverage, 3578, |
| 21820 | GIR_EraseRootFromParent_Done, |
| 21821 | // Label 1279: @58206 |
| 21822 | GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(58279), // Rule ID 3580 // |
| 21823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21824 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh), |
| 21825 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 21826 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21827 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21829 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21830 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21831 | // (intrinsic_wo_chain:{ *:[v16i8] } 3343:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 21832 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 21833 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21834 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 21835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi8), |
| 21836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 21837 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 21838 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 21839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21840 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21841 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21842 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21843 | GIR_RootConstrainSelectedInstOperands, |
| 21844 | // GIR_Coverage, 3580, |
| 21845 | GIR_EraseRootFromParent_Done, |
| 21846 | // Label 1280: @58279 |
| 21847 | GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(58352), // Rule ID 3582 // |
| 21848 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21849 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh), |
| 21850 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21851 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21852 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21853 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21854 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21855 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21856 | // (intrinsic_wo_chain:{ *:[v8i16] } 3343:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 21857 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 21858 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21859 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 21860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi16), |
| 21861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 21862 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 21863 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 21864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21865 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21866 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21867 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21868 | GIR_RootConstrainSelectedInstOperands, |
| 21869 | // GIR_Coverage, 3582, |
| 21870 | GIR_EraseRootFromParent_Done, |
| 21871 | // Label 1281: @58352 |
| 21872 | GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(58425), // Rule ID 3584 // |
| 21873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21874 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh), |
| 21875 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21876 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21877 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21878 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21879 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21880 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21881 | // (intrinsic_wo_chain:{ *:[v4i32] } 3343:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 21882 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 21883 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21884 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 21885 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi32), |
| 21886 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 21887 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 21888 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 21889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21890 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21891 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21892 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21893 | GIR_RootConstrainSelectedInstOperands, |
| 21894 | // GIR_Coverage, 3584, |
| 21895 | GIR_EraseRootFromParent_Done, |
| 21896 | // Label 1282: @58425 |
| 21897 | GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(58498), // Rule ID 4870 // |
| 21898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21899 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 21900 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 21901 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21902 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21903 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21904 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21905 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21906 | // (intrinsic_wo_chain:{ *:[v16i8] } 3267:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 21907 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 21908 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21909 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 21910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8), |
| 21911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 21912 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 21913 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21915 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21916 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21917 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21918 | GIR_RootConstrainSelectedInstOperands, |
| 21919 | // GIR_Coverage, 4870, |
| 21920 | GIR_EraseRootFromParent_Done, |
| 21921 | // Label 1283: @58498 |
| 21922 | GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(58571), // Rule ID 4875 // |
| 21923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21924 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 21925 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21926 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21927 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21928 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21929 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21930 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21931 | // (intrinsic_wo_chain:{ *:[v8i16] } 3267:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 21932 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 21933 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21934 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 21935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 21936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 21937 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 21938 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21940 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21941 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21942 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21943 | GIR_RootConstrainSelectedInstOperands, |
| 21944 | // GIR_Coverage, 4875, |
| 21945 | GIR_EraseRootFromParent_Done, |
| 21946 | // Label 1284: @58571 |
| 21947 | GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(58644), // Rule ID 4877 // |
| 21948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 21949 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 21950 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21951 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21952 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21953 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21954 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21955 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21956 | // (intrinsic_wo_chain:{ *:[v4i32] } 3267:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 21957 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 21958 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21959 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 21960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 21961 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 21962 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 21963 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21965 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21966 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21967 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21968 | GIR_RootConstrainSelectedInstOperands, |
| 21969 | // GIR_Coverage, 4877, |
| 21970 | GIR_EraseRootFromParent_Done, |
| 21971 | // Label 1285: @58644 |
| 21972 | GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(58717), // Rule ID 4879 // |
| 21973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 21974 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 21975 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21976 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21977 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21979 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 21980 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21981 | // (intrinsic_wo_chain:{ *:[v8f16] } 3267:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 21982 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 21983 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 21984 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 21985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 21986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 21987 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 21988 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21990 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21991 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21992 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21993 | GIR_RootConstrainSelectedInstOperands, |
| 21994 | // GIR_Coverage, 4879, |
| 21995 | GIR_EraseRootFromParent_Done, |
| 21996 | // Label 1286: @58717 |
| 21997 | GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(58790), // Rule ID 4881 // |
| 21998 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 21999 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 22000 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22001 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22002 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22004 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22005 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22006 | // (intrinsic_wo_chain:{ *:[v4f32] } 3267:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 22007 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22008 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22009 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 22011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22012 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 22013 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22015 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22016 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22017 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22018 | GIR_RootConstrainSelectedInstOperands, |
| 22019 | // GIR_Coverage, 4881, |
| 22020 | GIR_EraseRootFromParent_Done, |
| 22021 | // Label 1287: @58790 |
| 22022 | GIM_Reject, |
| 22023 | // Label 932: @58791 |
| 22024 | GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(70469), |
| 22025 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 22026 | GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(58887), // Rule ID 4031 // |
| 22027 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 22028 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22029 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22030 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22031 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22032 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22033 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22034 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22035 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22036 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 22037 | // MIs[1] Operand 1 |
| 22038 | // No operand predicates |
| 22039 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22040 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22041 | // (intrinsic_wo_chain:{ *:[v16i8] } 3344:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 22042 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22043 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22044 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22045 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms8), |
| 22046 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22047 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22048 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22050 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22051 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22052 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22053 | GIR_RootConstrainSelectedInstOperands, |
| 22054 | // GIR_Coverage, 4031, |
| 22055 | GIR_EraseRootFromParent_Done, |
| 22056 | // Label 1289: @58887 |
| 22057 | GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(58975), // Rule ID 4033 // |
| 22058 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 22059 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22060 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22061 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22062 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22064 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22065 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22066 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22067 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 22068 | // MIs[1] Operand 1 |
| 22069 | // No operand predicates |
| 22070 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22071 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22072 | // (intrinsic_wo_chain:{ *:[v16i8] } 3344:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 22073 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22074 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22075 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu8), |
| 22077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22078 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22079 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22081 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22082 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22083 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22084 | GIR_RootConstrainSelectedInstOperands, |
| 22085 | // GIR_Coverage, 4033, |
| 22086 | GIR_EraseRootFromParent_Done, |
| 22087 | // Label 1290: @58975 |
| 22088 | GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(59063), // Rule ID 4035 // |
| 22089 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 22090 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22091 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22092 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22093 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22094 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22095 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22096 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22097 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22098 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 22099 | // MIs[1] Operand 1 |
| 22100 | // No operand predicates |
| 22101 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22102 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22103 | // (intrinsic_wo_chain:{ *:[v8i16] } 3344:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 22104 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22105 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22106 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22107 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms16), |
| 22108 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22109 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22110 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22112 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22113 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22114 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22115 | GIR_RootConstrainSelectedInstOperands, |
| 22116 | // GIR_Coverage, 4035, |
| 22117 | GIR_EraseRootFromParent_Done, |
| 22118 | // Label 1291: @59063 |
| 22119 | GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(59151), // Rule ID 4037 // |
| 22120 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 22121 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22122 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22123 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22124 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22126 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22127 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22128 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22129 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 22130 | // MIs[1] Operand 1 |
| 22131 | // No operand predicates |
| 22132 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22133 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22134 | // (intrinsic_wo_chain:{ *:[v8i16] } 3344:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 22135 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22136 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22137 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu16), |
| 22139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22140 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22141 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22143 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22144 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22145 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22146 | GIR_RootConstrainSelectedInstOperands, |
| 22147 | // GIR_Coverage, 4037, |
| 22148 | GIR_EraseRootFromParent_Done, |
| 22149 | // Label 1292: @59151 |
| 22150 | GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(59239), // Rule ID 4039 // |
| 22151 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 22152 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22153 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22154 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22155 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22157 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22158 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22159 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22160 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 22161 | // MIs[1] Operand 1 |
| 22162 | // No operand predicates |
| 22163 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22164 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22165 | // (intrinsic_wo_chain:{ *:[v4i32] } 3344:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 22166 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22167 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22168 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms32), |
| 22170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22171 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22172 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22174 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22175 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22176 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22177 | GIR_RootConstrainSelectedInstOperands, |
| 22178 | // GIR_Coverage, 4039, |
| 22179 | GIR_EraseRootFromParent_Done, |
| 22180 | // Label 1293: @59239 |
| 22181 | GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(59327), // Rule ID 4041 // |
| 22182 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 22183 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22184 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22185 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22186 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22188 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22189 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22190 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22191 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 22192 | // MIs[1] Operand 1 |
| 22193 | // No operand predicates |
| 22194 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22195 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22196 | // (intrinsic_wo_chain:{ *:[v4i32] } 3344:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 22197 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22198 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22199 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu32), |
| 22201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22202 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22203 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22205 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22206 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22207 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22208 | GIR_RootConstrainSelectedInstOperands, |
| 22209 | // GIR_Coverage, 4041, |
| 22210 | GIR_EraseRootFromParent_Done, |
| 22211 | // Label 1294: @59327 |
| 22212 | GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(59415), // Rule ID 4049 // |
| 22213 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 22214 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22215 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22216 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22217 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22219 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22220 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22221 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22222 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 22223 | // MIs[1] Operand 1 |
| 22224 | // No operand predicates |
| 22225 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22226 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22227 | // (intrinsic_wo_chain:{ *:[v16i8] } 3361:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) |
| 22228 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22229 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22230 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms8), |
| 22232 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22233 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22234 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22236 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22237 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22238 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22239 | GIR_RootConstrainSelectedInstOperands, |
| 22240 | // GIR_Coverage, 4049, |
| 22241 | GIR_EraseRootFromParent_Done, |
| 22242 | // Label 1295: @59415 |
| 22243 | GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(59503), // Rule ID 4051 // |
| 22244 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 22245 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22246 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22247 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22248 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22249 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22250 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22251 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22252 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22253 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 22254 | // MIs[1] Operand 1 |
| 22255 | // No operand predicates |
| 22256 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22257 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22258 | // (intrinsic_wo_chain:{ *:[v16i8] } 3361:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) |
| 22259 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22260 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22261 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu8), |
| 22263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22264 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22265 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22267 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22268 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22269 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22270 | GIR_RootConstrainSelectedInstOperands, |
| 22271 | // GIR_Coverage, 4051, |
| 22272 | GIR_EraseRootFromParent_Done, |
| 22273 | // Label 1296: @59503 |
| 22274 | GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(59591), // Rule ID 4053 // |
| 22275 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 22276 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22277 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22278 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22279 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22280 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22281 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22282 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22283 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22284 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 22285 | // MIs[1] Operand 1 |
| 22286 | // No operand predicates |
| 22287 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22288 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22289 | // (intrinsic_wo_chain:{ *:[v8i16] } 3361:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) |
| 22290 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22291 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22292 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms16), |
| 22294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22295 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22296 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22298 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22299 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22300 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22301 | GIR_RootConstrainSelectedInstOperands, |
| 22302 | // GIR_Coverage, 4053, |
| 22303 | GIR_EraseRootFromParent_Done, |
| 22304 | // Label 1297: @59591 |
| 22305 | GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(59679), // Rule ID 4055 // |
| 22306 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 22307 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22308 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22309 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22310 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22311 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22312 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22313 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22314 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22315 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 22316 | // MIs[1] Operand 1 |
| 22317 | // No operand predicates |
| 22318 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22319 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22320 | // (intrinsic_wo_chain:{ *:[v8i16] } 3361:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) |
| 22321 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22322 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22323 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu16), |
| 22325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22326 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22327 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22329 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22330 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22331 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22332 | GIR_RootConstrainSelectedInstOperands, |
| 22333 | // GIR_Coverage, 4055, |
| 22334 | GIR_EraseRootFromParent_Done, |
| 22335 | // Label 1298: @59679 |
| 22336 | GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(59767), // Rule ID 4057 // |
| 22337 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 22338 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22339 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22340 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22341 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22342 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22343 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22344 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22345 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22346 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32), |
| 22347 | // MIs[1] Operand 1 |
| 22348 | // No operand predicates |
| 22349 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22350 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22351 | // (intrinsic_wo_chain:{ *:[v4i32] } 3361:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) |
| 22352 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22353 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22354 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22355 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms32), |
| 22356 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22357 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22358 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22360 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22361 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22362 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22363 | GIR_RootConstrainSelectedInstOperands, |
| 22364 | // GIR_Coverage, 4057, |
| 22365 | GIR_EraseRootFromParent_Done, |
| 22366 | // Label 1299: @59767 |
| 22367 | GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(59855), // Rule ID 4059 // |
| 22368 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 22369 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22370 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22371 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22372 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22373 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22374 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22375 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22376 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22377 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32), |
| 22378 | // MIs[1] Operand 1 |
| 22379 | // No operand predicates |
| 22380 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22381 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22382 | // (intrinsic_wo_chain:{ *:[v4i32] } 3361:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) |
| 22383 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22384 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22385 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu32), |
| 22387 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22388 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22389 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22391 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22392 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22393 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22394 | GIR_RootConstrainSelectedInstOperands, |
| 22395 | // GIR_Coverage, 4059, |
| 22396 | GIR_EraseRootFromParent_Done, |
| 22397 | // Label 1300: @59855 |
| 22398 | GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(59942), // Rule ID 4157 // |
| 22399 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22400 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 22401 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22402 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22403 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22404 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22406 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 22407 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22408 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 22409 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22410 | // MIs[1] Operand 1 |
| 22411 | // No operand predicates |
| 22412 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22413 | // (intrinsic_wo_chain:{ *:[v8f16] } 3280:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16s16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 22414 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22415 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22416 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16_fix), |
| 22418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22419 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 22420 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 22421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22422 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22423 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22424 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22425 | GIR_RootConstrainSelectedInstOperands, |
| 22426 | // GIR_Coverage, 4157, |
| 22427 | GIR_EraseRootFromParent_Done, |
| 22428 | // Label 1301: @59942 |
| 22429 | GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(60029), // Rule ID 4159 // |
| 22430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22431 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 22432 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22433 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22434 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22435 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22436 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22437 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 22438 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22439 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 22440 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22441 | // MIs[1] Operand 1 |
| 22442 | // No operand predicates |
| 22443 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22444 | // (intrinsic_wo_chain:{ *:[v8i16] } 3280:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 22445 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22446 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22447 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16_fix), |
| 22449 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22450 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 22451 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 22452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22453 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22454 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22455 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22456 | GIR_RootConstrainSelectedInstOperands, |
| 22457 | // GIR_Coverage, 4159, |
| 22458 | GIR_EraseRootFromParent_Done, |
| 22459 | // Label 1302: @60029 |
| 22460 | GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(60116), // Rule ID 4161 // |
| 22461 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22462 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 22463 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22464 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22465 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22466 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22467 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22468 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 22469 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22470 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 22471 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22472 | // MIs[1] Operand 1 |
| 22473 | // No operand predicates |
| 22474 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22475 | // (intrinsic_wo_chain:{ *:[v8f16] } 3280:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16u16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 22476 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22477 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22478 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22479 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16_fix), |
| 22480 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22481 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 22482 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 22483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22484 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22485 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22486 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22487 | GIR_RootConstrainSelectedInstOperands, |
| 22488 | // GIR_Coverage, 4161, |
| 22489 | GIR_EraseRootFromParent_Done, |
| 22490 | // Label 1303: @60116 |
| 22491 | GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(60203), // Rule ID 4163 // |
| 22492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22493 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 22494 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22495 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22496 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22497 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22499 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 22500 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22501 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 22502 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22503 | // MIs[1] Operand 1 |
| 22504 | // No operand predicates |
| 22505 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22506 | // (intrinsic_wo_chain:{ *:[v8i16] } 3280:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 22507 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22508 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22509 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16_fix), |
| 22511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22512 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 22513 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 22514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22515 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22516 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22517 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22518 | GIR_RootConstrainSelectedInstOperands, |
| 22519 | // GIR_Coverage, 4163, |
| 22520 | GIR_EraseRootFromParent_Done, |
| 22521 | // Label 1304: @60203 |
| 22522 | GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(60290), // Rule ID 4165 // |
| 22523 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22524 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 22525 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22526 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22527 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22528 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22529 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22530 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 22531 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22532 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 22533 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22534 | // MIs[1] Operand 1 |
| 22535 | // No operand predicates |
| 22536 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22537 | // (intrinsic_wo_chain:{ *:[v4f32] } 3280:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32s32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 22538 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22539 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22540 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32_fix), |
| 22542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22543 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 22544 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 22545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22546 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22547 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22548 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22549 | GIR_RootConstrainSelectedInstOperands, |
| 22550 | // GIR_Coverage, 4165, |
| 22551 | GIR_EraseRootFromParent_Done, |
| 22552 | // Label 1305: @60290 |
| 22553 | GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(60377), // Rule ID 4167 // |
| 22554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22555 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 22556 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22557 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22558 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22559 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22560 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22561 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 22562 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22563 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 22564 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22565 | // MIs[1] Operand 1 |
| 22566 | // No operand predicates |
| 22567 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22568 | // (intrinsic_wo_chain:{ *:[v4i32] } 3280:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 22569 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22570 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22571 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32_fix), |
| 22573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22574 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 22575 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 22576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22577 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22578 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22579 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22580 | GIR_RootConstrainSelectedInstOperands, |
| 22581 | // GIR_Coverage, 4167, |
| 22582 | GIR_EraseRootFromParent_Done, |
| 22583 | // Label 1306: @60377 |
| 22584 | GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(60464), // Rule ID 4169 // |
| 22585 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22586 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 22587 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22588 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22589 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22590 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22591 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22592 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 22593 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22594 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 22595 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22596 | // MIs[1] Operand 1 |
| 22597 | // No operand predicates |
| 22598 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22599 | // (intrinsic_wo_chain:{ *:[v4f32] } 3280:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32u32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 22600 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22601 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22602 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22603 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32_fix), |
| 22604 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22605 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 22606 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 22607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22608 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22609 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22610 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22611 | GIR_RootConstrainSelectedInstOperands, |
| 22612 | // GIR_Coverage, 4169, |
| 22613 | GIR_EraseRootFromParent_Done, |
| 22614 | // Label 1307: @60464 |
| 22615 | GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(60551), // Rule ID 4171 // |
| 22616 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22617 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 22618 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22619 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22620 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22621 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22623 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 22624 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22625 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 22626 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22627 | // MIs[1] Operand 1 |
| 22628 | // No operand predicates |
| 22629 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22630 | // (intrinsic_wo_chain:{ *:[v4i32] } 3280:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 22631 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22632 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22633 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32_fix), |
| 22635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22636 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 22637 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 22638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22639 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22640 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22641 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22642 | GIR_RootConstrainSelectedInstOperands, |
| 22643 | // GIR_Coverage, 4171, |
| 22644 | GIR_EraseRootFromParent_Done, |
| 22645 | // Label 1308: @60551 |
| 22646 | GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(60618), // Rule ID 3218 // |
| 22647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22648 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 22649 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22650 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22651 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22652 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22653 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22654 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22655 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22656 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22657 | // (intrinsic_wo_chain:{ *:[i32] } 3227:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 22658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8), |
| 22659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22660 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22661 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22663 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22664 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22665 | GIR_RootConstrainSelectedInstOperands, |
| 22666 | // GIR_Coverage, 3218, |
| 22667 | GIR_EraseRootFromParent_Done, |
| 22668 | // Label 1309: @60618 |
| 22669 | GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(60685), // Rule ID 3220 // |
| 22670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22671 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 22672 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22673 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22674 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22675 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22677 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22678 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22679 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22680 | // (intrinsic_wo_chain:{ *:[i32] } 3227:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 22681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16), |
| 22682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22683 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22684 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22686 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22687 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22688 | GIR_RootConstrainSelectedInstOperands, |
| 22689 | // GIR_Coverage, 3220, |
| 22690 | GIR_EraseRootFromParent_Done, |
| 22691 | // Label 1310: @60685 |
| 22692 | GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(60752), // Rule ID 3222 // |
| 22693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22694 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 22695 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22696 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22697 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22698 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22699 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22700 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22701 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22702 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22703 | // (intrinsic_wo_chain:{ *:[i32] } 3227:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 22704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32), |
| 22705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22706 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22707 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22709 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22710 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22711 | GIR_RootConstrainSelectedInstOperands, |
| 22712 | // GIR_Coverage, 3222, |
| 22713 | GIR_EraseRootFromParent_Done, |
| 22714 | // Label 1311: @60752 |
| 22715 | GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(60819), // Rule ID 3224 // |
| 22716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22717 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 22718 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22719 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22720 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22721 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22723 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22724 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22725 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22726 | // (intrinsic_wo_chain:{ *:[i32] } 3227:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 22727 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8), |
| 22728 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22729 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22730 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22732 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22733 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22734 | GIR_RootConstrainSelectedInstOperands, |
| 22735 | // GIR_Coverage, 3224, |
| 22736 | GIR_EraseRootFromParent_Done, |
| 22737 | // Label 1312: @60819 |
| 22738 | GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(60886), // Rule ID 3226 // |
| 22739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22740 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 22741 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22742 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22743 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22744 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22745 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22746 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22747 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22748 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22749 | // (intrinsic_wo_chain:{ *:[i32] } 3227:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 22750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16), |
| 22751 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22752 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22753 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22755 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22756 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22757 | GIR_RootConstrainSelectedInstOperands, |
| 22758 | // GIR_Coverage, 3226, |
| 22759 | GIR_EraseRootFromParent_Done, |
| 22760 | // Label 1313: @60886 |
| 22761 | GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(60953), // Rule ID 3228 // |
| 22762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22763 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 22764 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22765 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22766 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22767 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22769 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22770 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22771 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22772 | // (intrinsic_wo_chain:{ *:[i32] } 3227:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 22773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32), |
| 22774 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22775 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22776 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22778 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22779 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22780 | GIR_RootConstrainSelectedInstOperands, |
| 22781 | // GIR_Coverage, 3228, |
| 22782 | GIR_EraseRootFromParent_Done, |
| 22783 | // Label 1314: @60953 |
| 22784 | GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(61020), // Rule ID 3230 // |
| 22785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22786 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 22787 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22788 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22789 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22790 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22792 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22793 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22794 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22795 | // (intrinsic_wo_chain:{ *:[i32] } 3218:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 22796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8), |
| 22797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22798 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22799 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22801 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22802 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22803 | GIR_RootConstrainSelectedInstOperands, |
| 22804 | // GIR_Coverage, 3230, |
| 22805 | GIR_EraseRootFromParent_Done, |
| 22806 | // Label 1315: @61020 |
| 22807 | GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(61087), // Rule ID 3232 // |
| 22808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22809 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 22810 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22811 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22812 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22813 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22814 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22815 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22816 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22817 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22818 | // (intrinsic_wo_chain:{ *:[i32] } 3218:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 22819 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16), |
| 22820 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22821 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22822 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22824 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22825 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22826 | GIR_RootConstrainSelectedInstOperands, |
| 22827 | // GIR_Coverage, 3232, |
| 22828 | GIR_EraseRootFromParent_Done, |
| 22829 | // Label 1316: @61087 |
| 22830 | GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(61154), // Rule ID 3234 // |
| 22831 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22832 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 22833 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22834 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22835 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22836 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22837 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22838 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22839 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22840 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22841 | // (intrinsic_wo_chain:{ *:[i32] } 3218:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 22842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32), |
| 22843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22844 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22845 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22847 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22848 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22849 | GIR_RootConstrainSelectedInstOperands, |
| 22850 | // GIR_Coverage, 3234, |
| 22851 | GIR_EraseRootFromParent_Done, |
| 22852 | // Label 1317: @61154 |
| 22853 | GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(61221), // Rule ID 3236 // |
| 22854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22855 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 22856 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22857 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22858 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22859 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22860 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22861 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22862 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22863 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22864 | // (intrinsic_wo_chain:{ *:[i32] } 3218:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 22865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8), |
| 22866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22867 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22868 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22870 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22871 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22872 | GIR_RootConstrainSelectedInstOperands, |
| 22873 | // GIR_Coverage, 3236, |
| 22874 | GIR_EraseRootFromParent_Done, |
| 22875 | // Label 1318: @61221 |
| 22876 | GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(61288), // Rule ID 3238 // |
| 22877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22878 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 22879 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22880 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22881 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22882 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22883 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22884 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22885 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22886 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22887 | // (intrinsic_wo_chain:{ *:[i32] } 3218:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 22888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16), |
| 22889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22890 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22891 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22893 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22894 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22895 | GIR_RootConstrainSelectedInstOperands, |
| 22896 | // GIR_Coverage, 3238, |
| 22897 | GIR_EraseRootFromParent_Done, |
| 22898 | // Label 1319: @61288 |
| 22899 | GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(61355), // Rule ID 3240 // |
| 22900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22901 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 22902 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22903 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22904 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22905 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22907 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22908 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22909 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22910 | // (intrinsic_wo_chain:{ *:[i32] } 3218:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 22911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32), |
| 22912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22913 | GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22914 | GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22916 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22917 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22918 | GIR_RootConstrainSelectedInstOperands, |
| 22919 | // GIR_Coverage, 3240, |
| 22920 | GIR_EraseRootFromParent_Done, |
| 22921 | // Label 1320: @61355 |
| 22922 | GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(61435), // Rule ID 3645 // |
| 22923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22924 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 22925 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22926 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22927 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22928 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22930 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22931 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22932 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22933 | // (intrinsic_wo_chain:{ *:[v16i8] } 3264:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 22934 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22935 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22936 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22937 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8), |
| 22938 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22939 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 22940 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 22941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22942 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22943 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22944 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22945 | GIR_RootConstrainSelectedInstOperands, |
| 22946 | // GIR_Coverage, 3645, |
| 22947 | GIR_EraseRootFromParent_Done, |
| 22948 | // Label 1321: @61435 |
| 22949 | GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(61515), // Rule ID 3652 // |
| 22950 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22951 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 22952 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22953 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22954 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22955 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22957 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22958 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22959 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22960 | // (intrinsic_wo_chain:{ *:[v8i16] } 3264:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 22961 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22962 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22963 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16), |
| 22965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22966 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 22967 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 22968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22969 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22970 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22971 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22972 | GIR_RootConstrainSelectedInstOperands, |
| 22973 | // GIR_Coverage, 3652, |
| 22974 | GIR_EraseRootFromParent_Done, |
| 22975 | // Label 1322: @61515 |
| 22976 | GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(61595), // Rule ID 3656 // |
| 22977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22978 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 22979 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22980 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22981 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22982 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22983 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22984 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22985 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22986 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22987 | // (intrinsic_wo_chain:{ *:[v4i32] } 3264:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 22988 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22989 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22990 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 22991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32), |
| 22992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22993 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 22994 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 22995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22996 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22997 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22998 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22999 | GIR_RootConstrainSelectedInstOperands, |
| 23000 | // GIR_Coverage, 3656, |
| 23001 | GIR_EraseRootFromParent_Done, |
| 23002 | // Label 1323: @61595 |
| 23003 | GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(61675), // Rule ID 3660 // |
| 23004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23005 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 23006 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23007 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23008 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23009 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23011 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23012 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23013 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23014 | // (intrinsic_wo_chain:{ *:[v16i8] } 3264:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23015 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23016 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23017 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23018 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8), |
| 23019 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23020 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23021 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23023 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23024 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23025 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23026 | GIR_RootConstrainSelectedInstOperands, |
| 23027 | // GIR_Coverage, 3660, |
| 23028 | GIR_EraseRootFromParent_Done, |
| 23029 | // Label 1324: @61675 |
| 23030 | GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(61755), // Rule ID 3664 // |
| 23031 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23032 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 23033 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23034 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23035 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23036 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23037 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23038 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23039 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23040 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23041 | // (intrinsic_wo_chain:{ *:[v8i16] } 3264:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23042 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23043 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23044 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23045 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16), |
| 23046 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23047 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23048 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23050 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23051 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23052 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23053 | GIR_RootConstrainSelectedInstOperands, |
| 23054 | // GIR_Coverage, 3664, |
| 23055 | GIR_EraseRootFromParent_Done, |
| 23056 | // Label 1325: @61755 |
| 23057 | GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(61835), // Rule ID 3668 // |
| 23058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23059 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 23060 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23061 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23062 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23063 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23065 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23066 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23067 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23068 | // (intrinsic_wo_chain:{ *:[v4i32] } 3264:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23069 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23070 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23071 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32), |
| 23073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23074 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23075 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23077 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23078 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23079 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23080 | GIR_RootConstrainSelectedInstOperands, |
| 23081 | // GIR_Coverage, 3668, |
| 23082 | GIR_EraseRootFromParent_Done, |
| 23083 | // Label 1326: @61835 |
| 23084 | GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(61915), // Rule ID 3669 // |
| 23085 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23086 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 23087 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23088 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23089 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23090 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23092 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23093 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23094 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23095 | // (intrinsic_wo_chain:{ *:[v16i8] } 3350:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23096 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23097 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23098 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8), |
| 23100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23101 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23102 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23104 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23105 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23106 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23107 | GIR_RootConstrainSelectedInstOperands, |
| 23108 | // GIR_Coverage, 3669, |
| 23109 | GIR_EraseRootFromParent_Done, |
| 23110 | // Label 1327: @61915 |
| 23111 | GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(61995), // Rule ID 3676 // |
| 23112 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23113 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 23114 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23115 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23116 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23117 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23118 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23119 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23120 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23121 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23122 | // (intrinsic_wo_chain:{ *:[v8i16] } 3350:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23123 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23124 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23125 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16), |
| 23127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23128 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23129 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23131 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23132 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23133 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23134 | GIR_RootConstrainSelectedInstOperands, |
| 23135 | // GIR_Coverage, 3676, |
| 23136 | GIR_EraseRootFromParent_Done, |
| 23137 | // Label 1328: @61995 |
| 23138 | GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(62075), // Rule ID 3680 // |
| 23139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23140 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 23141 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23142 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23143 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23144 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23146 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23147 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23148 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23149 | // (intrinsic_wo_chain:{ *:[v4i32] } 3350:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23150 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23151 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23152 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23153 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32), |
| 23154 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23155 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23156 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23158 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23159 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23160 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23161 | GIR_RootConstrainSelectedInstOperands, |
| 23162 | // GIR_Coverage, 3680, |
| 23163 | GIR_EraseRootFromParent_Done, |
| 23164 | // Label 1329: @62075 |
| 23165 | GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(62155), // Rule ID 3684 // |
| 23166 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23167 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 23168 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23169 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23170 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23171 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23173 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23174 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23175 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23176 | // (intrinsic_wo_chain:{ *:[v16i8] } 3350:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23177 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23178 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23179 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23180 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8), |
| 23181 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23182 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23183 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23185 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23186 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23187 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23188 | GIR_RootConstrainSelectedInstOperands, |
| 23189 | // GIR_Coverage, 3684, |
| 23190 | GIR_EraseRootFromParent_Done, |
| 23191 | // Label 1330: @62155 |
| 23192 | GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(62235), // Rule ID 3688 // |
| 23193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23194 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 23195 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23196 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23197 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23198 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23200 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23201 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23202 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23203 | // (intrinsic_wo_chain:{ *:[v8i16] } 3350:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23204 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23205 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23206 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23207 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16), |
| 23208 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23209 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23210 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23212 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23213 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23214 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23215 | GIR_RootConstrainSelectedInstOperands, |
| 23216 | // GIR_Coverage, 3688, |
| 23217 | GIR_EraseRootFromParent_Done, |
| 23218 | // Label 1331: @62235 |
| 23219 | GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(62315), // Rule ID 3692 // |
| 23220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23221 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 23222 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23223 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23224 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23225 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23226 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23227 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23228 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23229 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23230 | // (intrinsic_wo_chain:{ *:[v4i32] } 3350:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23231 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23232 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23233 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23234 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32), |
| 23235 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23236 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23237 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23239 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23240 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23241 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23242 | GIR_RootConstrainSelectedInstOperands, |
| 23243 | // GIR_Coverage, 3692, |
| 23244 | GIR_EraseRootFromParent_Done, |
| 23245 | // Label 1332: @62315 |
| 23246 | GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(62395), // Rule ID 3705 // |
| 23247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23248 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 23249 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23250 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23251 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23252 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23253 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23254 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23255 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23256 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23257 | // (intrinsic_wo_chain:{ *:[v16i8] } 3299:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23258 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23259 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23260 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23261 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8), |
| 23262 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23263 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23264 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23266 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23267 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23268 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23269 | GIR_RootConstrainSelectedInstOperands, |
| 23270 | // GIR_Coverage, 3705, |
| 23271 | GIR_EraseRootFromParent_Done, |
| 23272 | // Label 1333: @62395 |
| 23273 | GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(62475), // Rule ID 3713 // |
| 23274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23275 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 23276 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23277 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23278 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23279 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23280 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23281 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23282 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23283 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23284 | // (intrinsic_wo_chain:{ *:[v8i16] } 3299:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23285 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23286 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23287 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16), |
| 23289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23290 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23291 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23293 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23294 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23295 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23296 | GIR_RootConstrainSelectedInstOperands, |
| 23297 | // GIR_Coverage, 3713, |
| 23298 | GIR_EraseRootFromParent_Done, |
| 23299 | // Label 1334: @62475 |
| 23300 | GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(62555), // Rule ID 3718 // |
| 23301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23302 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 23303 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23304 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23305 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23306 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23307 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23308 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23309 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23310 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23311 | // (intrinsic_wo_chain:{ *:[v4i32] } 3299:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23312 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23313 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23314 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32), |
| 23316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23317 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23318 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23320 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23321 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23322 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23323 | GIR_RootConstrainSelectedInstOperands, |
| 23324 | // GIR_Coverage, 3718, |
| 23325 | GIR_EraseRootFromParent_Done, |
| 23326 | // Label 1335: @62555 |
| 23327 | GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(62635), // Rule ID 3723 // |
| 23328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23329 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 23330 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23331 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23332 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23333 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23335 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23336 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23337 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23338 | // (intrinsic_wo_chain:{ *:[v16i8] } 3299:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23339 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23340 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23341 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8), |
| 23343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23344 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23345 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23347 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23348 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23349 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23350 | GIR_RootConstrainSelectedInstOperands, |
| 23351 | // GIR_Coverage, 3723, |
| 23352 | GIR_EraseRootFromParent_Done, |
| 23353 | // Label 1336: @62635 |
| 23354 | GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(62715), // Rule ID 3728 // |
| 23355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23356 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 23357 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23358 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23359 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23360 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23361 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23362 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23363 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23364 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23365 | // (intrinsic_wo_chain:{ *:[v8i16] } 3299:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23366 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23367 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23368 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16), |
| 23370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23371 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23372 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23374 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23375 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23376 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23377 | GIR_RootConstrainSelectedInstOperands, |
| 23378 | // GIR_Coverage, 3728, |
| 23379 | GIR_EraseRootFromParent_Done, |
| 23380 | // Label 1337: @62715 |
| 23381 | GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(62795), // Rule ID 3733 // |
| 23382 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23383 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 23384 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23385 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23386 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23387 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23388 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23389 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23390 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23391 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23392 | // (intrinsic_wo_chain:{ *:[v4i32] } 3299:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23393 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23394 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23395 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32), |
| 23397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23398 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23399 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23401 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23402 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23403 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23404 | GIR_RootConstrainSelectedInstOperands, |
| 23405 | // GIR_Coverage, 3733, |
| 23406 | GIR_EraseRootFromParent_Done, |
| 23407 | // Label 1338: @62795 |
| 23408 | GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(62875), // Rule ID 3735 // |
| 23409 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23410 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 23411 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23412 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23413 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23414 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23415 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23416 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23417 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23418 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23419 | // (intrinsic_wo_chain:{ *:[v16i8] } 3300:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23420 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23421 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23422 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs8), |
| 23424 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23425 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23426 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23428 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23429 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23430 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23431 | GIR_RootConstrainSelectedInstOperands, |
| 23432 | // GIR_Coverage, 3735, |
| 23433 | GIR_EraseRootFromParent_Done, |
| 23434 | // Label 1339: @62875 |
| 23435 | GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(62955), // Rule ID 3738 // |
| 23436 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23437 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 23438 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23439 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23440 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23441 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23443 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23444 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23445 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23446 | // (intrinsic_wo_chain:{ *:[v8i16] } 3300:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23447 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23448 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23449 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs16), |
| 23451 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23452 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23453 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23455 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23456 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23457 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23458 | GIR_RootConstrainSelectedInstOperands, |
| 23459 | // GIR_Coverage, 3738, |
| 23460 | GIR_EraseRootFromParent_Done, |
| 23461 | // Label 1340: @62955 |
| 23462 | GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(63035), // Rule ID 3741 // |
| 23463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23464 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 23465 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23466 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23467 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23468 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23469 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23470 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23471 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23472 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23473 | // (intrinsic_wo_chain:{ *:[v4i32] } 3300:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23474 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23475 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23476 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs32), |
| 23478 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23479 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23480 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23482 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23483 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23484 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23485 | GIR_RootConstrainSelectedInstOperands, |
| 23486 | // GIR_Coverage, 3741, |
| 23487 | GIR_EraseRootFromParent_Done, |
| 23488 | // Label 1341: @63035 |
| 23489 | GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(63115), // Rule ID 3744 // |
| 23490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23491 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 23492 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23493 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23494 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23495 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23496 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23497 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23498 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23499 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23500 | // (intrinsic_wo_chain:{ *:[v16i8] } 3300:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23501 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23502 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23503 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu8), |
| 23505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23506 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23507 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23509 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23510 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23511 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23512 | GIR_RootConstrainSelectedInstOperands, |
| 23513 | // GIR_Coverage, 3744, |
| 23514 | GIR_EraseRootFromParent_Done, |
| 23515 | // Label 1342: @63115 |
| 23516 | GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(63195), // Rule ID 3747 // |
| 23517 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23518 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 23519 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23520 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23521 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23522 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23523 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23524 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23525 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23526 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23527 | // (intrinsic_wo_chain:{ *:[v8i16] } 3300:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23528 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23529 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23530 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu16), |
| 23532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23533 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23534 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23536 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23537 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23538 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23539 | GIR_RootConstrainSelectedInstOperands, |
| 23540 | // GIR_Coverage, 3747, |
| 23541 | GIR_EraseRootFromParent_Done, |
| 23542 | // Label 1343: @63195 |
| 23543 | GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(63275), // Rule ID 3750 // |
| 23544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23545 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 23546 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23547 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23548 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23549 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23550 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23551 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23552 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23553 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23554 | // (intrinsic_wo_chain:{ *:[v4i32] } 3300:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23555 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23556 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23557 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu32), |
| 23559 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23560 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23561 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23563 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23564 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23565 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23566 | GIR_RootConstrainSelectedInstOperands, |
| 23567 | // GIR_Coverage, 3750, |
| 23568 | GIR_EraseRootFromParent_Done, |
| 23569 | // Label 1344: @63275 |
| 23570 | GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(63355), // Rule ID 4151 // |
| 23571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 23572 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 23573 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23574 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23575 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23576 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23578 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23579 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23580 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23581 | // (intrinsic_wo_chain:{ *:[v4f32] } 3264:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 23582 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23583 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23584 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32), |
| 23586 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23587 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23588 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23590 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23591 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23592 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23593 | GIR_RootConstrainSelectedInstOperands, |
| 23594 | // GIR_Coverage, 4151, |
| 23595 | GIR_EraseRootFromParent_Done, |
| 23596 | // Label 1345: @63355 |
| 23597 | GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(63435), // Rule ID 4153 // |
| 23598 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 23599 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 23600 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23601 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23602 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23603 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23604 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23605 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23606 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23607 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23608 | // (intrinsic_wo_chain:{ *:[v8f16] } 3264:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 23609 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23610 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23611 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16), |
| 23613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23614 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23615 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23617 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23618 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23619 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23620 | GIR_RootConstrainSelectedInstOperands, |
| 23621 | // GIR_Coverage, 4153, |
| 23622 | GIR_EraseRootFromParent_Done, |
| 23623 | // Label 1346: @63435 |
| 23624 | GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(63515), // Rule ID 4526 // |
| 23625 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23626 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 23627 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23628 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23629 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23630 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23631 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23632 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23633 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23634 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23635 | // (intrinsic_wo_chain:{ *:[v8i16] } 3327:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23636 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23637 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23638 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp8), |
| 23640 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23641 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23642 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23644 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23645 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23646 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23647 | GIR_RootConstrainSelectedInstOperands, |
| 23648 | // GIR_Coverage, 4526, |
| 23649 | GIR_EraseRootFromParent_Done, |
| 23650 | // Label 1347: @63515 |
| 23651 | GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(63595), // Rule ID 4528 // |
| 23652 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23653 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 23654 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23655 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23656 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23657 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23659 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23660 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23661 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23662 | // (intrinsic_wo_chain:{ *:[v8i16] } 3327:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23663 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23664 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23665 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp8), |
| 23667 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23668 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23669 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23671 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23672 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23673 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23674 | GIR_RootConstrainSelectedInstOperands, |
| 23675 | // GIR_Coverage, 4528, |
| 23676 | GIR_EraseRootFromParent_Done, |
| 23677 | // Label 1348: @63595 |
| 23678 | GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(63675), // Rule ID 4530 // |
| 23679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23680 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 23681 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23682 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23683 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23684 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23686 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23687 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23688 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23689 | // (intrinsic_wo_chain:{ *:[v4i32] } 3327:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23690 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23691 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23692 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp16), |
| 23694 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23695 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23696 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23698 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23699 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23700 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23701 | GIR_RootConstrainSelectedInstOperands, |
| 23702 | // GIR_Coverage, 4530, |
| 23703 | GIR_EraseRootFromParent_Done, |
| 23704 | // Label 1349: @63675 |
| 23705 | GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(63755), // Rule ID 4532 // |
| 23706 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23707 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 23708 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23709 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23710 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23711 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23713 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23714 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23715 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23716 | // (intrinsic_wo_chain:{ *:[v4i32] } 3327:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23717 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23718 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23719 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp16), |
| 23721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23722 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23723 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23725 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23726 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23727 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23728 | GIR_RootConstrainSelectedInstOperands, |
| 23729 | // GIR_Coverage, 4532, |
| 23730 | GIR_EraseRootFromParent_Done, |
| 23731 | // Label 1350: @63755 |
| 23732 | GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(63835), // Rule ID 4559 // |
| 23733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23734 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 23735 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23736 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23737 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23738 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23740 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23741 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23742 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23743 | // (intrinsic_wo_chain:{ *:[v16i8] } 3325:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23744 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23745 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23746 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23747 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8), |
| 23748 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23749 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23750 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23752 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23753 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23754 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23755 | GIR_RootConstrainSelectedInstOperands, |
| 23756 | // GIR_Coverage, 4559, |
| 23757 | GIR_EraseRootFromParent_Done, |
| 23758 | // Label 1351: @63835 |
| 23759 | GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(63915), // Rule ID 4566 // |
| 23760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23761 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 23762 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23763 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23764 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23765 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23767 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23768 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23769 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23770 | // (intrinsic_wo_chain:{ *:[v8i16] } 3325:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23771 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23772 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23773 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16), |
| 23775 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23776 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23777 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23779 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23780 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23781 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23782 | GIR_RootConstrainSelectedInstOperands, |
| 23783 | // GIR_Coverage, 4566, |
| 23784 | GIR_EraseRootFromParent_Done, |
| 23785 | // Label 1352: @63915 |
| 23786 | GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(63995), // Rule ID 4570 // |
| 23787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23788 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 23789 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23790 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23791 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23792 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23793 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23794 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23795 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23796 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23797 | // (intrinsic_wo_chain:{ *:[v4i32] } 3325:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23798 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23799 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23800 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32), |
| 23802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23803 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23804 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23806 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23807 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23808 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23809 | GIR_RootConstrainSelectedInstOperands, |
| 23810 | // GIR_Coverage, 4570, |
| 23811 | GIR_EraseRootFromParent_Done, |
| 23812 | // Label 1353: @63995 |
| 23813 | GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(64075), // Rule ID 4574 // |
| 23814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23815 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 23816 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23817 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23818 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23819 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23820 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23821 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23822 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23823 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23824 | // (intrinsic_wo_chain:{ *:[v16i8] } 3325:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23825 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23826 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23827 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8), |
| 23829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23830 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23831 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23833 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23834 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23835 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23836 | GIR_RootConstrainSelectedInstOperands, |
| 23837 | // GIR_Coverage, 4574, |
| 23838 | GIR_EraseRootFromParent_Done, |
| 23839 | // Label 1354: @64075 |
| 23840 | GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(64155), // Rule ID 4578 // |
| 23841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23842 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 23843 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23844 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23845 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23846 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23848 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23849 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23850 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23851 | // (intrinsic_wo_chain:{ *:[v8i16] } 3325:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23852 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23853 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23854 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23855 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16), |
| 23856 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23857 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23858 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23860 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23861 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23862 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23863 | GIR_RootConstrainSelectedInstOperands, |
| 23864 | // GIR_Coverage, 4578, |
| 23865 | GIR_EraseRootFromParent_Done, |
| 23866 | // Label 1355: @64155 |
| 23867 | GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(64235), // Rule ID 4582 // |
| 23868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23869 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 23870 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23871 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23872 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23873 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23874 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23875 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23876 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23877 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23878 | // (intrinsic_wo_chain:{ *:[v4i32] } 3325:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23879 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23880 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23881 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32), |
| 23883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23884 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23885 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23887 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23888 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23889 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23890 | GIR_RootConstrainSelectedInstOperands, |
| 23891 | // GIR_Coverage, 4582, |
| 23892 | GIR_EraseRootFromParent_Done, |
| 23893 | // Label 1356: @64235 |
| 23894 | GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(64315), // Rule ID 4583 // |
| 23895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23896 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 23897 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23898 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23899 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23900 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23901 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23902 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23903 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23904 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23905 | // (intrinsic_wo_chain:{ *:[v16i8] } 3360:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23906 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23907 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23908 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs8), |
| 23910 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23911 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23912 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23914 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23915 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23916 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23917 | GIR_RootConstrainSelectedInstOperands, |
| 23918 | // GIR_Coverage, 4583, |
| 23919 | GIR_EraseRootFromParent_Done, |
| 23920 | // Label 1357: @64315 |
| 23921 | GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(64395), // Rule ID 4585 // |
| 23922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23923 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 23924 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23925 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23926 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23927 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23928 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23929 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23930 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23931 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23932 | // (intrinsic_wo_chain:{ *:[v8i16] } 3360:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23933 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23934 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23935 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs16), |
| 23937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23938 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23939 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23941 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23942 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23943 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23944 | GIR_RootConstrainSelectedInstOperands, |
| 23945 | // GIR_Coverage, 4585, |
| 23946 | GIR_EraseRootFromParent_Done, |
| 23947 | // Label 1358: @64395 |
| 23948 | GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(64475), // Rule ID 4587 // |
| 23949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23950 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 23951 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23952 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23953 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23954 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23955 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23956 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23957 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23958 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23959 | // (intrinsic_wo_chain:{ *:[v4i32] } 3360:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23960 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23961 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23962 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs32), |
| 23964 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23965 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23966 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23968 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23969 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23970 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23971 | GIR_RootConstrainSelectedInstOperands, |
| 23972 | // GIR_Coverage, 4587, |
| 23973 | GIR_EraseRootFromParent_Done, |
| 23974 | // Label 1359: @64475 |
| 23975 | GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(64555), // Rule ID 4589 // |
| 23976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23977 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 23978 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23979 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23980 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23981 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23982 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23983 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23984 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23985 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23986 | // (intrinsic_wo_chain:{ *:[v16i8] } 3360:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23987 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23988 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23989 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 23990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu8), |
| 23991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23992 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23993 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23995 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23996 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23997 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23998 | GIR_RootConstrainSelectedInstOperands, |
| 23999 | // GIR_Coverage, 4589, |
| 24000 | GIR_EraseRootFromParent_Done, |
| 24001 | // Label 1360: @64555 |
| 24002 | GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(64635), // Rule ID 4591 // |
| 24003 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24004 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 24005 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24006 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24007 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24008 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24009 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24010 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24011 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24012 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24013 | // (intrinsic_wo_chain:{ *:[v8i16] } 3360:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24014 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24015 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24016 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 24017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu16), |
| 24018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24019 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24020 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24022 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24023 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24024 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24025 | GIR_RootConstrainSelectedInstOperands, |
| 24026 | // GIR_Coverage, 4591, |
| 24027 | GIR_EraseRootFromParent_Done, |
| 24028 | // Label 1361: @64635 |
| 24029 | GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(64715), // Rule ID 4593 // |
| 24030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24031 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 24032 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24033 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24034 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24035 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24036 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24037 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24038 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24039 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24040 | // (intrinsic_wo_chain:{ *:[v4i32] } 3360:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24041 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24042 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24043 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 24044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu32), |
| 24045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24046 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24047 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24049 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24050 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24051 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24052 | GIR_RootConstrainSelectedInstOperands, |
| 24053 | // GIR_Coverage, 4593, |
| 24054 | GIR_EraseRootFromParent_Done, |
| 24055 | // Label 1362: @64715 |
| 24056 | GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(64782), // Rule ID 4644 // |
| 24057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24058 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow), |
| 24059 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24060 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24061 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24062 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24064 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24065 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24066 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24067 | // (intrinsic_wo_chain:{ *:[v8f16] } 3283:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm) |
| 24068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32bh), |
| 24069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24070 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 24071 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 24072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24073 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24074 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24075 | GIR_RootConstrainSelectedInstOperands, |
| 24076 | // GIR_Coverage, 4644, |
| 24077 | GIR_EraseRootFromParent_Done, |
| 24078 | // Label 1363: @64782 |
| 24079 | GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(64849), // Rule ID 4650 // |
| 24080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24081 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow), |
| 24082 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24083 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24084 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24085 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24086 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24087 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24088 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24089 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24090 | // (intrinsic_wo_chain:{ *:[v8f16] } 3283:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm) |
| 24091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32th), |
| 24092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24093 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 24094 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 24095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24096 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24097 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24098 | GIR_RootConstrainSelectedInstOperands, |
| 24099 | // GIR_Coverage, 4650, |
| 24100 | GIR_EraseRootFromParent_Done, |
| 24101 | // Label 1364: @64849 |
| 24102 | GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(64929), // Rule ID 4668 // |
| 24103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24104 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 24105 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24106 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24107 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24108 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24109 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24110 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24111 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24112 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24113 | // (intrinsic_wo_chain:{ *:[v4i32] } 3335:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24114 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24115 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24116 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 24117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16bh), |
| 24118 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24119 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24120 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24122 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24123 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24124 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24125 | GIR_RootConstrainSelectedInstOperands, |
| 24126 | // GIR_Coverage, 4668, |
| 24127 | GIR_EraseRootFromParent_Done, |
| 24128 | // Label 1365: @64929 |
| 24129 | GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(65009), // Rule ID 4670 // |
| 24130 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24131 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 24132 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24133 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24134 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24135 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24137 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24138 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24139 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24140 | // (intrinsic_wo_chain:{ *:[v4i32] } 3335:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24141 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24142 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24143 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 24144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16th), |
| 24145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24146 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24147 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24149 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24150 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24151 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24152 | GIR_RootConstrainSelectedInstOperands, |
| 24153 | // GIR_Coverage, 4670, |
| 24154 | GIR_EraseRootFromParent_Done, |
| 24155 | // Label 1366: @65009 |
| 24156 | GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(65089), // Rule ID 4672 // |
| 24157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24158 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 24159 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 24160 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24161 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24162 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24163 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24164 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24165 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24166 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24167 | // (intrinsic_wo_chain:{ *:[v2i64] } 3335:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs32bh:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24168 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24169 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24170 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 24171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32bh), |
| 24172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24173 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24174 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24176 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24177 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24178 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24179 | GIR_RootConstrainSelectedInstOperands, |
| 24180 | // GIR_Coverage, 4672, |
| 24181 | GIR_EraseRootFromParent_Done, |
| 24182 | // Label 1367: @65089 |
| 24183 | GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(65169), // Rule ID 4674 // |
| 24184 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24185 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 24186 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 24187 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24188 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24189 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24191 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24192 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24193 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24194 | // (intrinsic_wo_chain:{ *:[v2i64] } 3335:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs32th:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24195 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24196 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24197 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 24198 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32th), |
| 24199 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24200 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24201 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24203 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24204 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24205 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24206 | GIR_RootConstrainSelectedInstOperands, |
| 24207 | // GIR_Coverage, 4674, |
| 24208 | GIR_EraseRootFromParent_Done, |
| 24209 | // Label 1368: @65169 |
| 24210 | GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(65246), // Rule ID 4019 // |
| 24211 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli), |
| 24212 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 24213 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24214 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24215 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24217 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24218 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24219 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 24220 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24221 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 24222 | // MIs[1] Operand 1 |
| 24223 | // No operand predicates |
| 24224 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24225 | // (intrinsic_wo_chain:{ *:[v16i8] } 3375:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VSLIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 24226 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm8), |
| 24227 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24228 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 24229 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 24230 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24232 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24233 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24234 | GIR_RootConstrainSelectedInstOperands, |
| 24235 | // GIR_Coverage, 4019, |
| 24236 | GIR_EraseRootFromParent_Done, |
| 24237 | // Label 1369: @65246 |
| 24238 | GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(65323), // Rule ID 4021 // |
| 24239 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli), |
| 24240 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24241 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24242 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24243 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24244 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24245 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24246 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24247 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 24248 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24249 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 24250 | // MIs[1] Operand 1 |
| 24251 | // No operand predicates |
| 24252 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24253 | // (intrinsic_wo_chain:{ *:[v8i16] } 3375:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VSLIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 24254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm16), |
| 24255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24256 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 24257 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 24258 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24260 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24261 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24262 | GIR_RootConstrainSelectedInstOperands, |
| 24263 | // GIR_Coverage, 4021, |
| 24264 | GIR_EraseRootFromParent_Done, |
| 24265 | // Label 1370: @65323 |
| 24266 | GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(65400), // Rule ID 4023 // |
| 24267 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli), |
| 24268 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24269 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24270 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24271 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24273 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24274 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24275 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 24276 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24277 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 24278 | // MIs[1] Operand 1 |
| 24279 | // No operand predicates |
| 24280 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24281 | // (intrinsic_wo_chain:{ *:[v4i32] } 3375:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VSLIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 24282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm32), |
| 24283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24284 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 24285 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 24286 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24288 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24289 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24290 | GIR_RootConstrainSelectedInstOperands, |
| 24291 | // GIR_Coverage, 4023, |
| 24292 | GIR_EraseRootFromParent_Done, |
| 24293 | // Label 1371: @65400 |
| 24294 | GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(65477), // Rule ID 4025 // |
| 24295 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri), |
| 24296 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 24297 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24298 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24299 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24300 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24301 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24302 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24303 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 24304 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24305 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 24306 | // MIs[1] Operand 1 |
| 24307 | // No operand predicates |
| 24308 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24309 | // (intrinsic_wo_chain:{ *:[v16i8] } 3377:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) => (MVE_VSRIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) |
| 24310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm8), |
| 24311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24312 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 24313 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 24314 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24316 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24317 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24318 | GIR_RootConstrainSelectedInstOperands, |
| 24319 | // GIR_Coverage, 4025, |
| 24320 | GIR_EraseRootFromParent_Done, |
| 24321 | // Label 1372: @65477 |
| 24322 | GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(65554), // Rule ID 4027 // |
| 24323 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri), |
| 24324 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24325 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24326 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24327 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24328 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24329 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24330 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24331 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 24332 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24333 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 24334 | // MIs[1] Operand 1 |
| 24335 | // No operand predicates |
| 24336 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24337 | // (intrinsic_wo_chain:{ *:[v8i16] } 3377:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) => (MVE_VSRIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) |
| 24338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm16), |
| 24339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24340 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 24341 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 24342 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24344 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24345 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24346 | GIR_RootConstrainSelectedInstOperands, |
| 24347 | // GIR_Coverage, 4027, |
| 24348 | GIR_EraseRootFromParent_Done, |
| 24349 | // Label 1373: @65554 |
| 24350 | GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(65631), // Rule ID 4029 // |
| 24351 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri), |
| 24352 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24353 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24354 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24355 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24357 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24358 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24359 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 24360 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24361 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32), |
| 24362 | // MIs[1] Operand 1 |
| 24363 | // No operand predicates |
| 24364 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24365 | // (intrinsic_wo_chain:{ *:[v4i32] } 3377:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) => (MVE_VSRIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) |
| 24366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm32), |
| 24367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24368 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 24369 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 24370 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24372 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24373 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24374 | GIR_RootConstrainSelectedInstOperands, |
| 24375 | // GIR_Coverage, 4029, |
| 24376 | GIR_EraseRootFromParent_Done, |
| 24377 | // Label 1374: @65631 |
| 24378 | GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(65720), // Rule ID 4498 // |
| 24379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24380 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq), |
| 24381 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24382 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24383 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24384 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 24385 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24386 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 24387 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24388 | // MIs[1] Operand 1 |
| 24389 | // No operand predicates |
| 24390 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24391 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24392 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24393 | // (intrinsic_wo_chain:{ *:[v8f16] } 3274:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 24394 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24395 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24396 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 24397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf16), |
| 24398 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24399 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24400 | GIR_RootToRootCopy, /*OpIdx*/4, // Qm |
| 24401 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 24402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24403 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24404 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24405 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24406 | GIR_RootConstrainSelectedInstOperands, |
| 24407 | // GIR_Coverage, 4498, |
| 24408 | GIR_EraseRootFromParent_Done, |
| 24409 | // Label 1375: @65720 |
| 24410 | GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(65809), // Rule ID 4500 // |
| 24411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24412 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq), |
| 24413 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24414 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24415 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24416 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 24417 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24418 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 24419 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24420 | // MIs[1] Operand 1 |
| 24421 | // No operand predicates |
| 24422 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24423 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24424 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24425 | // (intrinsic_wo_chain:{ *:[v4f32] } 3274:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 24426 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24427 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24428 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 24429 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf32), |
| 24430 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24431 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24432 | GIR_RootToRootCopy, /*OpIdx*/4, // Qm |
| 24433 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 24434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24435 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24436 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24437 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24438 | GIR_RootConstrainSelectedInstOperands, |
| 24439 | // GIR_Coverage, 4500, |
| 24440 | GIR_EraseRootFromParent_Done, |
| 24441 | // Label 1376: @65809 |
| 24442 | GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(65872), // Rule ID 146 // |
| 24443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 24444 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8), |
| 24445 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24446 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24447 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24448 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24449 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 24450 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 24451 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 24452 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 24453 | // (intrinsic_wo_chain:{ *:[i32] } 3607:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 24454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USADA8), |
| 24455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 24456 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24457 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24458 | GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 24459 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 24460 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24461 | GIR_RootConstrainSelectedInstOperands, |
| 24462 | // GIR_Coverage, 146, |
| 24463 | GIR_EraseRootFromParent_Done, |
| 24464 | // Label 1377: @65872 |
| 24465 | GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(65935), // Rule ID 477 // |
| 24466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 24467 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8), |
| 24468 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24469 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24470 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24471 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24472 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24473 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24474 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24475 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24476 | // (intrinsic_wo_chain:{ *:[i32] } 3607:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 24477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USADA8), |
| 24478 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 24479 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24480 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24481 | GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 24482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 24483 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24484 | GIR_RootConstrainSelectedInstOperands, |
| 24485 | // GIR_Coverage, 477, |
| 24486 | GIR_EraseRootFromParent_Done, |
| 24487 | // Label 1378: @65935 |
| 24488 | GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(65998), // Rule ID 536 // |
| 24489 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 24490 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad), |
| 24491 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24492 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24493 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24494 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24496 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24497 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24498 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24499 | // (intrinsic_wo_chain:{ *:[i32] } 3552:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 24500 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAD), |
| 24501 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 24502 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24503 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24504 | GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 24505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 24506 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24507 | GIR_RootConstrainSelectedInstOperands, |
| 24508 | // GIR_Coverage, 536, |
| 24509 | GIR_EraseRootFromParent_Done, |
| 24510 | // Label 1379: @65998 |
| 24511 | GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(66061), // Rule ID 537 // |
| 24512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 24513 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx), |
| 24514 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24515 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24516 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24517 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24518 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24519 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24520 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24521 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24522 | // (intrinsic_wo_chain:{ *:[i32] } 3553:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 24523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLADX), |
| 24524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 24525 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24526 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24527 | GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 24528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 24529 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24530 | GIR_RootConstrainSelectedInstOperands, |
| 24531 | // GIR_Coverage, 537, |
| 24532 | GIR_EraseRootFromParent_Done, |
| 24533 | // Label 1380: @66061 |
| 24534 | GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(66124), // Rule ID 538 // |
| 24535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 24536 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd), |
| 24537 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24538 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24539 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24540 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24541 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24542 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24543 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24544 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24545 | // (intrinsic_wo_chain:{ *:[i32] } 3560:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 24546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSD), |
| 24547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 24548 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24549 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24550 | GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 24551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 24552 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24553 | GIR_RootConstrainSelectedInstOperands, |
| 24554 | // GIR_Coverage, 538, |
| 24555 | GIR_EraseRootFromParent_Done, |
| 24556 | // Label 1381: @66124 |
| 24557 | GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(66187), // Rule ID 539 // |
| 24558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 24559 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx), |
| 24560 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24561 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24562 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24563 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24565 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24566 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24567 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24568 | // (intrinsic_wo_chain:{ *:[i32] } 3561:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 24569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSDX), |
| 24570 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 24571 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24572 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24573 | GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 24574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 24575 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24576 | GIR_RootConstrainSelectedInstOperands, |
| 24577 | // GIR_Coverage, 539, |
| 24578 | GIR_EraseRootFromParent_Done, |
| 24579 | // Label 1382: @66187 |
| 24580 | GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(66241), // Rule ID 968 // |
| 24581 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd), |
| 24582 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot), |
| 24583 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 24584 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 24585 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 24586 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 24587 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24588 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24589 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24590 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24591 | // (intrinsic_wo_chain:{ *:[v2i32] } 3407:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 24592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTD), |
| 24593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24594 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24595 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24596 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24597 | GIR_RootConstrainSelectedInstOperands, |
| 24598 | // GIR_Coverage, 968, |
| 24599 | GIR_EraseRootFromParent_Done, |
| 24600 | // Label 1383: @66241 |
| 24601 | GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(66295), // Rule ID 969 // |
| 24602 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd), |
| 24603 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot), |
| 24604 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 24605 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 24606 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 24607 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 24608 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24609 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24610 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24611 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24612 | // (intrinsic_wo_chain:{ *:[v2i32] } 3395:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 24613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTD), |
| 24614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24615 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24616 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24617 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24618 | GIR_RootConstrainSelectedInstOperands, |
| 24619 | // GIR_Coverage, 969, |
| 24620 | GIR_EraseRootFromParent_Done, |
| 24621 | // Label 1384: @66295 |
| 24622 | GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(66349), // Rule ID 970 // |
| 24623 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd), |
| 24624 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot), |
| 24625 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24626 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24627 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24628 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 24629 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24630 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24631 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24632 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24633 | // (intrinsic_wo_chain:{ *:[v4i32] } 3407:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 24634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTQ), |
| 24635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24636 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24637 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24638 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24639 | GIR_RootConstrainSelectedInstOperands, |
| 24640 | // GIR_Coverage, 970, |
| 24641 | GIR_EraseRootFromParent_Done, |
| 24642 | // Label 1385: @66349 |
| 24643 | GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(66403), // Rule ID 971 // |
| 24644 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd), |
| 24645 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot), |
| 24646 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24647 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24648 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24649 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 24650 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24651 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24652 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24653 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24654 | // (intrinsic_wo_chain:{ *:[v4i32] } 3395:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 24655 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTQ), |
| 24656 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24657 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24658 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24659 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24660 | GIR_RootConstrainSelectedInstOperands, |
| 24661 | // GIR_Coverage, 971, |
| 24662 | GIR_EraseRootFromParent_Done, |
| 24663 | // Label 1386: @66403 |
| 24664 | GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(66457), // Rule ID 972 // |
| 24665 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 24666 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_smmla), |
| 24667 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24668 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24669 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24670 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 24671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24672 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24673 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24674 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24675 | // (intrinsic_wo_chain:{ *:[v4i32] } 3406:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 24676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSMMLA), |
| 24677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24678 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24679 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24680 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24681 | GIR_RootConstrainSelectedInstOperands, |
| 24682 | // GIR_Coverage, 972, |
| 24683 | GIR_EraseRootFromParent_Done, |
| 24684 | // Label 1387: @66457 |
| 24685 | GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(66511), // Rule ID 973 // |
| 24686 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 24687 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_ummla), |
| 24688 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24689 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24690 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24691 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 24692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24693 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24694 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24695 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24696 | // (intrinsic_wo_chain:{ *:[v4i32] } 3408:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 24697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUMMLA), |
| 24698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24699 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24700 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24701 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24702 | GIR_RootConstrainSelectedInstOperands, |
| 24703 | // GIR_Coverage, 973, |
| 24704 | GIR_EraseRootFromParent_Done, |
| 24705 | // Label 1388: @66511 |
| 24706 | GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(66565), // Rule ID 974 // |
| 24707 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 24708 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usmmla), |
| 24709 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24710 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24711 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24712 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 24713 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24714 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24715 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24716 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24717 | // (intrinsic_wo_chain:{ *:[v4i32] } 3410:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 24718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSMMLA), |
| 24719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24720 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24721 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24722 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24723 | GIR_RootConstrainSelectedInstOperands, |
| 24724 | // GIR_Coverage, 974, |
| 24725 | GIR_EraseRootFromParent_Done, |
| 24726 | // Label 1389: @66565 |
| 24727 | GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(66619), // Rule ID 975 // |
| 24728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 24729 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot), |
| 24730 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 24731 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 24732 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 24733 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 24734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24735 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24736 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24737 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24738 | // (intrinsic_wo_chain:{ *:[v2i32] } 3409:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 24739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTD), |
| 24740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24741 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24742 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24743 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24744 | GIR_RootConstrainSelectedInstOperands, |
| 24745 | // GIR_Coverage, 975, |
| 24746 | GIR_EraseRootFromParent_Done, |
| 24747 | // Label 1390: @66619 |
| 24748 | GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(66673), // Rule ID 976 // |
| 24749 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 24750 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot), |
| 24751 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24752 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24753 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24754 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 24755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24756 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24757 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24758 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24759 | // (intrinsic_wo_chain:{ *:[v4i32] } 3409:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 24760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTQ), |
| 24761 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24762 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24763 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24764 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24765 | GIR_RootConstrainSelectedInstOperands, |
| 24766 | // GIR_Coverage, 976, |
| 24767 | GIR_EraseRootFromParent_Done, |
| 24768 | // Label 1391: @66673 |
| 24769 | GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(66736), // Rule ID 1709 // |
| 24770 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 24771 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx1), |
| 24772 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 24773 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 24774 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 24775 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 24776 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24777 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24778 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24779 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24780 | // (intrinsic_wo_chain:{ *:[v8i8] } 3527:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 24781 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX1), |
| 24782 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 24783 | GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 24784 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24785 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24786 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 24787 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24788 | GIR_RootConstrainSelectedInstOperands, |
| 24789 | // GIR_Coverage, 1709, |
| 24790 | GIR_EraseRootFromParent_Done, |
| 24791 | // Label 1392: @66736 |
| 24792 | GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(66790), // Rule ID 1740 // |
| 24793 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 24794 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su0), |
| 24795 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24796 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24797 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24798 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 24799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24800 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24801 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24802 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24803 | // (intrinsic_wo_chain:{ *:[v4i32] } 3400:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 24804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU0), |
| 24805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 24806 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24807 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24808 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24809 | GIR_RootConstrainSelectedInstOperands, |
| 24810 | // GIR_Coverage, 1740, |
| 24811 | GIR_EraseRootFromParent_Done, |
| 24812 | // Label 1393: @66790 |
| 24813 | GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(66844), // Rule ID 1741 // |
| 24814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 24815 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h), |
| 24816 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24817 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24818 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24819 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 24820 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24821 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24822 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24823 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24824 | // (intrinsic_wo_chain:{ *:[v4i32] } 3402:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 24825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H), |
| 24826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 24827 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24828 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24829 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24830 | GIR_RootConstrainSelectedInstOperands, |
| 24831 | // GIR_Coverage, 1741, |
| 24832 | GIR_EraseRootFromParent_Done, |
| 24833 | // Label 1394: @66844 |
| 24834 | GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(66898), // Rule ID 1742 // |
| 24835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 24836 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h2), |
| 24837 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24838 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24839 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24840 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 24841 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24842 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24843 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24844 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24845 | // (intrinsic_wo_chain:{ *:[v4i32] } 3403:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 24846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H2), |
| 24847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 24848 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24849 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24850 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24851 | GIR_RootConstrainSelectedInstOperands, |
| 24852 | // GIR_Coverage, 1742, |
| 24853 | GIR_EraseRootFromParent_Done, |
| 24854 | // Label 1395: @66898 |
| 24855 | GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(66952), // Rule ID 1743 // |
| 24856 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 24857 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su1), |
| 24858 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24859 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24860 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24861 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 24862 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24863 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24864 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24865 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24866 | // (intrinsic_wo_chain:{ *:[v4i32] } 3405:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 24867 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU1), |
| 24868 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 24869 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24870 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24871 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24872 | GIR_RootConstrainSelectedInstOperands, |
| 24873 | // GIR_Coverage, 1743, |
| 24874 | GIR_EraseRootFromParent_Done, |
| 24875 | // Label 1396: @66952 |
| 24876 | GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(67006), // Rule ID 1744 // |
| 24877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON), |
| 24878 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_bfdot), |
| 24879 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 24880 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 24881 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 24882 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 24883 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24884 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24885 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24886 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 24887 | // (intrinsic_wo_chain:{ *:[v2f32] } 3391:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vd, DPR:{ *:[v4bf16] }:$Vn, DPR:{ *:[v4bf16] }:$Vm) => (BF16VDOTS_VDOTD:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vd, DPR:{ *:[v4bf16] }:$Vn, DPR:{ *:[v4bf16] }:$Vm) |
| 24888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BF16VDOTS_VDOTD), |
| 24889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24890 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24891 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24892 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24893 | GIR_RootConstrainSelectedInstOperands, |
| 24894 | // GIR_Coverage, 1744, |
| 24895 | GIR_EraseRootFromParent_Done, |
| 24896 | // Label 1397: @67006 |
| 24897 | GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(67060), // Rule ID 1745 // |
| 24898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON), |
| 24899 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_bfdot), |
| 24900 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24901 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24902 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24903 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 24904 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24905 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24906 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24907 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24908 | // (intrinsic_wo_chain:{ *:[v4f32] } 3391:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm) => (BF16VDOTS_VDOTQ:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm) |
| 24909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BF16VDOTS_VDOTQ), |
| 24910 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24911 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24912 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24913 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24914 | GIR_RootConstrainSelectedInstOperands, |
| 24915 | // GIR_Coverage, 1745, |
| 24916 | GIR_EraseRootFromParent_Done, |
| 24917 | // Label 1398: @67060 |
| 24918 | GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(67114), // Rule ID 1746 // |
| 24919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON), |
| 24920 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_bfmmla), |
| 24921 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24922 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24923 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24924 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 24925 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24926 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24927 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24928 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24929 | // (intrinsic_wo_chain:{ *:[v4f32] } 3394:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm) => (VMMLA:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm) |
| 24930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMMLA), |
| 24931 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24932 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24933 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24934 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24935 | GIR_RootConstrainSelectedInstOperands, |
| 24936 | // GIR_Coverage, 1746, |
| 24937 | GIR_EraseRootFromParent_Done, |
| 24938 | // Label 1399: @67114 |
| 24939 | GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(67168), // Rule ID 1747 // |
| 24940 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON), |
| 24941 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_bfmlalt), |
| 24942 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24943 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24944 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24945 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 24946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24947 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24948 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24949 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24950 | // (intrinsic_wo_chain:{ *:[v4f32] } 3393:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm) => (VBF16MALTQ:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm) |
| 24951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VBF16MALTQ), |
| 24952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24953 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24954 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24955 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24956 | GIR_RootConstrainSelectedInstOperands, |
| 24957 | // GIR_Coverage, 1747, |
| 24958 | GIR_EraseRootFromParent_Done, |
| 24959 | // Label 1400: @67168 |
| 24960 | GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(67222), // Rule ID 1748 // |
| 24961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON), |
| 24962 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_bfmlalb), |
| 24963 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24964 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24965 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24966 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 24967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24968 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24969 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24970 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 24971 | // (intrinsic_wo_chain:{ *:[v4f32] } 3392:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm) => (VBF16MALBQ:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm) |
| 24972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VBF16MALBQ), |
| 24973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 24974 | GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 24975 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 24976 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 24977 | GIR_RootConstrainSelectedInstOperands, |
| 24978 | // GIR_Coverage, 1748, |
| 24979 | GIR_EraseRootFromParent_Done, |
| 24980 | // Label 1401: @67222 |
| 24981 | GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(67285), // Rule ID 1923 // |
| 24982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 24983 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad), |
| 24984 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 24985 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24986 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24987 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 24989 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 24990 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 24991 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 24992 | // (intrinsic_wo_chain:{ *:[i32] } 3552:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 24993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAD), |
| 24994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 24995 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 24996 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24997 | GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 24998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 24999 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25000 | GIR_RootConstrainSelectedInstOperands, |
| 25001 | // GIR_Coverage, 1923, |
| 25002 | GIR_EraseRootFromParent_Done, |
| 25003 | // Label 1402: @67285 |
| 25004 | GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(67348), // Rule ID 1924 // |
| 25005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 25006 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx), |
| 25007 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25008 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25009 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25010 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25011 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25012 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25013 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25014 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25015 | // (intrinsic_wo_chain:{ *:[i32] } 3553:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 25016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLADX), |
| 25017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25018 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 25019 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25020 | GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 25021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25022 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25023 | GIR_RootConstrainSelectedInstOperands, |
| 25024 | // GIR_Coverage, 1924, |
| 25025 | GIR_EraseRootFromParent_Done, |
| 25026 | // Label 1403: @67348 |
| 25027 | GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(67411), // Rule ID 1925 // |
| 25028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 25029 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd), |
| 25030 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25031 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25032 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25033 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25035 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25036 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25037 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25038 | // (intrinsic_wo_chain:{ *:[i32] } 3560:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 25039 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSD), |
| 25040 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25041 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 25042 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25043 | GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 25044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25045 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25046 | GIR_RootConstrainSelectedInstOperands, |
| 25047 | // GIR_Coverage, 1925, |
| 25048 | GIR_EraseRootFromParent_Done, |
| 25049 | // Label 1404: @67411 |
| 25050 | GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(67474), // Rule ID 1926 // |
| 25051 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 25052 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx), |
| 25053 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25054 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25055 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25056 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25057 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25058 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25059 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25060 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25061 | // (intrinsic_wo_chain:{ *:[i32] } 3561:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 25062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSDX), |
| 25063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25064 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 25065 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25066 | GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 25067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25068 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25069 | GIR_RootConstrainSelectedInstOperands, |
| 25070 | // GIR_Coverage, 1926, |
| 25071 | GIR_EraseRootFromParent_Done, |
| 25072 | // Label 1405: @67474 |
| 25073 | GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(67537), // Rule ID 2005 // |
| 25074 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 25075 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb), |
| 25076 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25077 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25078 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25079 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25081 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25082 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25083 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25084 | // (intrinsic_wo_chain:{ *:[i32] } 3550:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB), |
| 25086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25087 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25088 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25089 | GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25091 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25092 | GIR_RootConstrainSelectedInstOperands, |
| 25093 | // GIR_Coverage, 2005, |
| 25094 | GIR_EraseRootFromParent_Done, |
| 25095 | // Label 1406: @67537 |
| 25096 | GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(67600), // Rule ID 2006 // |
| 25097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 25098 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt), |
| 25099 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25100 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25101 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25102 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25104 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25105 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25106 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25107 | // (intrinsic_wo_chain:{ *:[i32] } 3551:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 25109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25110 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25111 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25112 | GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25114 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25115 | GIR_RootConstrainSelectedInstOperands, |
| 25116 | // GIR_Coverage, 2006, |
| 25117 | GIR_EraseRootFromParent_Done, |
| 25118 | // Label 1407: @67600 |
| 25119 | GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(67663), // Rule ID 2007 // |
| 25120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 25121 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb), |
| 25122 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25123 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25124 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25125 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25126 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25127 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25128 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25129 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25130 | // (intrinsic_wo_chain:{ *:[i32] } 3556:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB), |
| 25132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25133 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25134 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25135 | GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25137 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25138 | GIR_RootConstrainSelectedInstOperands, |
| 25139 | // GIR_Coverage, 2007, |
| 25140 | GIR_EraseRootFromParent_Done, |
| 25141 | // Label 1408: @67663 |
| 25142 | GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(67726), // Rule ID 2008 // |
| 25143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 25144 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt), |
| 25145 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25146 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25147 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25148 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25149 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25150 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25151 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25152 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25153 | // (intrinsic_wo_chain:{ *:[i32] } 3557:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 25155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25156 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25157 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25158 | GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25160 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25161 | GIR_RootConstrainSelectedInstOperands, |
| 25162 | // GIR_Coverage, 2008, |
| 25163 | GIR_EraseRootFromParent_Done, |
| 25164 | // Label 1409: @67726 |
| 25165 | GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(67789), // Rule ID 2009 // |
| 25166 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 25167 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb), |
| 25168 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25169 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25170 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25171 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25173 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25174 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25175 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25176 | // (intrinsic_wo_chain:{ *:[i32] } 3558:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25177 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWB), |
| 25178 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25179 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25180 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25181 | GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25183 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25184 | GIR_RootConstrainSelectedInstOperands, |
| 25185 | // GIR_Coverage, 2009, |
| 25186 | GIR_EraseRootFromParent_Done, |
| 25187 | // Label 1410: @67789 |
| 25188 | GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(67852), // Rule ID 2010 // |
| 25189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 25190 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt), |
| 25191 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25192 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25193 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25194 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25196 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25197 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25198 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25199 | // (intrinsic_wo_chain:{ *:[i32] } 3559:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWT), |
| 25201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25202 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25203 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25204 | GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25206 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25207 | GIR_RootConstrainSelectedInstOperands, |
| 25208 | // GIR_Coverage, 2010, |
| 25209 | GIR_EraseRootFromParent_Done, |
| 25210 | // Label 1411: @67852 |
| 25211 | GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(67915), // Rule ID 2188 // |
| 25212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25213 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb), |
| 25214 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25215 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25216 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25217 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25219 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25220 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25221 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25222 | // (intrinsic_wo_chain:{ *:[i32] } 3550:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25223 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB), |
| 25224 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25225 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25226 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25227 | GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25229 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25230 | GIR_RootConstrainSelectedInstOperands, |
| 25231 | // GIR_Coverage, 2188, |
| 25232 | GIR_EraseRootFromParent_Done, |
| 25233 | // Label 1412: @67915 |
| 25234 | GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(67978), // Rule ID 2189 // |
| 25235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25236 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt), |
| 25237 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25238 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25239 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25240 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25242 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25243 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25244 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25245 | // (intrinsic_wo_chain:{ *:[i32] } 3551:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 25247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25248 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25249 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25250 | GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25252 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25253 | GIR_RootConstrainSelectedInstOperands, |
| 25254 | // GIR_Coverage, 2189, |
| 25255 | GIR_EraseRootFromParent_Done, |
| 25256 | // Label 1413: @67978 |
| 25257 | GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(68041), // Rule ID 2190 // |
| 25258 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25259 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb), |
| 25260 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25261 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25262 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25263 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25264 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25265 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25266 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25267 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25268 | // (intrinsic_wo_chain:{ *:[i32] } 3556:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB), |
| 25270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25271 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25272 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25273 | GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25275 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25276 | GIR_RootConstrainSelectedInstOperands, |
| 25277 | // GIR_Coverage, 2190, |
| 25278 | GIR_EraseRootFromParent_Done, |
| 25279 | // Label 1414: @68041 |
| 25280 | GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(68104), // Rule ID 2191 // |
| 25281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25282 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt), |
| 25283 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25284 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25285 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25286 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25287 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25288 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25289 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25290 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25291 | // (intrinsic_wo_chain:{ *:[i32] } 3557:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 25293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25294 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25295 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25296 | GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25298 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25299 | GIR_RootConstrainSelectedInstOperands, |
| 25300 | // GIR_Coverage, 2191, |
| 25301 | GIR_EraseRootFromParent_Done, |
| 25302 | // Label 1415: @68104 |
| 25303 | GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(68167), // Rule ID 2192 // |
| 25304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25305 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb), |
| 25306 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25307 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25308 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25309 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25310 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25311 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25312 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25313 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25314 | // (intrinsic_wo_chain:{ *:[i32] } 3558:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWB), |
| 25316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25317 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25318 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25319 | GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25321 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25322 | GIR_RootConstrainSelectedInstOperands, |
| 25323 | // GIR_Coverage, 2192, |
| 25324 | GIR_EraseRootFromParent_Done, |
| 25325 | // Label 1416: @68167 |
| 25326 | GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(68230), // Rule ID 2193 // |
| 25327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25328 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt), |
| 25329 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25330 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25331 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25332 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25333 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25334 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25335 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25336 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25337 | // (intrinsic_wo_chain:{ *:[i32] } 3559:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWT), |
| 25339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25340 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25341 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25342 | GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25344 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25345 | GIR_RootConstrainSelectedInstOperands, |
| 25346 | // GIR_Coverage, 2193, |
| 25347 | GIR_EraseRootFromParent_Done, |
| 25348 | // Label 1417: @68230 |
| 25349 | GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(68293), // Rule ID 2469 // |
| 25350 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 25351 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 25352 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 25353 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 25354 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 25355 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 25356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25357 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25358 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25359 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25360 | // (intrinsic_wo_chain:{ *:[v4i16] } 3479:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 25361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i16), |
| 25362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25363 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25364 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25365 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25367 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25368 | GIR_RootConstrainSelectedInstOperands, |
| 25369 | // GIR_Coverage, 2469, |
| 25370 | GIR_EraseRootFromParent_Done, |
| 25371 | // Label 1418: @68293 |
| 25372 | GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(68356), // Rule ID 2470 // |
| 25373 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 25374 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 25375 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 25376 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 25377 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 25378 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32, |
| 25379 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25380 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25381 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25382 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25383 | // (intrinsic_wo_chain:{ *:[v2i32] } 3479:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 25384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv2i32), |
| 25385 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25386 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25387 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25388 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25390 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25391 | GIR_RootConstrainSelectedInstOperands, |
| 25392 | // GIR_Coverage, 2470, |
| 25393 | GIR_EraseRootFromParent_Done, |
| 25394 | // Label 1419: @68356 |
| 25395 | GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(68419), // Rule ID 2471 // |
| 25396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 25397 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 25398 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25399 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25400 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25401 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 25402 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25403 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25404 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25405 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25406 | // (intrinsic_wo_chain:{ *:[v8i16] } 3479:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 25407 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv8i16), |
| 25408 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25409 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25410 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25411 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25413 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25414 | GIR_RootConstrainSelectedInstOperands, |
| 25415 | // GIR_Coverage, 2471, |
| 25416 | GIR_EraseRootFromParent_Done, |
| 25417 | // Label 1420: @68419 |
| 25418 | GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(68482), // Rule ID 2472 // |
| 25419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 25420 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 25421 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25422 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25423 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25424 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 25425 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25426 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25427 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25428 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25429 | // (intrinsic_wo_chain:{ *:[v4i32] } 3479:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 25430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i32), |
| 25431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25432 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25433 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25434 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25436 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25437 | GIR_RootConstrainSelectedInstOperands, |
| 25438 | // GIR_Coverage, 2472, |
| 25439 | GIR_EraseRootFromParent_Done, |
| 25440 | // Label 1421: @68482 |
| 25441 | GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(68545), // Rule ID 2477 // |
| 25442 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 25443 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 25444 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 25445 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 25446 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 25447 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 25448 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25449 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25450 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25451 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25452 | // (intrinsic_wo_chain:{ *:[v4i16] } 3480:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLSHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 25453 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i16), |
| 25454 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25455 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25456 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25457 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25458 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25459 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25460 | GIR_RootConstrainSelectedInstOperands, |
| 25461 | // GIR_Coverage, 2477, |
| 25462 | GIR_EraseRootFromParent_Done, |
| 25463 | // Label 1422: @68545 |
| 25464 | GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(68608), // Rule ID 2478 // |
| 25465 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 25466 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 25467 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 25468 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 25469 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 25470 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32, |
| 25471 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25472 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25473 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25474 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25475 | // (intrinsic_wo_chain:{ *:[v2i32] } 3480:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLSHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 25476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv2i32), |
| 25477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25478 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25479 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25480 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25482 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25483 | GIR_RootConstrainSelectedInstOperands, |
| 25484 | // GIR_Coverage, 2478, |
| 25485 | GIR_EraseRootFromParent_Done, |
| 25486 | // Label 1423: @68608 |
| 25487 | GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(68671), // Rule ID 2479 // |
| 25488 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 25489 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 25490 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25491 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25492 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25493 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 25494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25495 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25496 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25497 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25498 | // (intrinsic_wo_chain:{ *:[v8i16] } 3480:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLSHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 25499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv8i16), |
| 25500 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25501 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25502 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25503 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25505 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25506 | GIR_RootConstrainSelectedInstOperands, |
| 25507 | // GIR_Coverage, 2479, |
| 25508 | GIR_EraseRootFromParent_Done, |
| 25509 | // Label 1424: @68671 |
| 25510 | GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(68734), // Rule ID 2480 // |
| 25511 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 25512 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 25513 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25514 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25515 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25516 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 25517 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25518 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25519 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25520 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25521 | // (intrinsic_wo_chain:{ *:[v4i32] } 3480:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLSHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 25522 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i32), |
| 25523 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25524 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25525 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25526 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25528 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25529 | GIR_RootConstrainSelectedInstOperands, |
| 25530 | // GIR_Coverage, 2480, |
| 25531 | GIR_EraseRootFromParent_Done, |
| 25532 | // Label 1425: @68734 |
| 25533 | GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(68797), // Rule ID 2557 // |
| 25534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 25535 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl), |
| 25536 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 25537 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 25538 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 25539 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 25540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25541 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25542 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25543 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25544 | // (intrinsic_wo_chain:{ *:[v8i8] } 3416:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VBSPd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 25545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VBSPd), |
| 25546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25547 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25548 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25549 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25551 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25552 | GIR_RootConstrainSelectedInstOperands, |
| 25553 | // GIR_Coverage, 2557, |
| 25554 | GIR_EraseRootFromParent_Done, |
| 25555 | // Label 1426: @68797 |
| 25556 | GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(68860), // Rule ID 2558 // |
| 25557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 25558 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl), |
| 25559 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 25560 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 25561 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 25562 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 25563 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25564 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25565 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25566 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25567 | // (intrinsic_wo_chain:{ *:[v4i16] } 3416:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VBSPd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 25568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VBSPd), |
| 25569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25570 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25571 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25572 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25574 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25575 | GIR_RootConstrainSelectedInstOperands, |
| 25576 | // GIR_Coverage, 2558, |
| 25577 | GIR_EraseRootFromParent_Done, |
| 25578 | // Label 1427: @68860 |
| 25579 | GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(68923), // Rule ID 2559 // |
| 25580 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 25581 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl), |
| 25582 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 25583 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 25584 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 25585 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32, |
| 25586 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25587 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25588 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25589 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25590 | // (intrinsic_wo_chain:{ *:[v2i32] } 3416:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VBSPd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 25591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VBSPd), |
| 25592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25593 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25594 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25595 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25597 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25598 | GIR_RootConstrainSelectedInstOperands, |
| 25599 | // GIR_Coverage, 2559, |
| 25600 | GIR_EraseRootFromParent_Done, |
| 25601 | // Label 1428: @68923 |
| 25602 | GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(68986), // Rule ID 2560 // |
| 25603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 25604 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl), |
| 25605 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 25606 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 25607 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 25608 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32, |
| 25609 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25610 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25611 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25612 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25613 | // (intrinsic_wo_chain:{ *:[v2f32] } 3416:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VBSPd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 25614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VBSPd), |
| 25615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25616 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25617 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25618 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25620 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25621 | GIR_RootConstrainSelectedInstOperands, |
| 25622 | // GIR_Coverage, 2560, |
| 25623 | GIR_EraseRootFromParent_Done, |
| 25624 | // Label 1429: @68986 |
| 25625 | GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(69049), // Rule ID 2561 // |
| 25626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 25627 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl), |
| 25628 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 25629 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 25630 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 25631 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 25632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25633 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25634 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25635 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25636 | // (intrinsic_wo_chain:{ *:[v1i64] } 3416:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VBSPd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 25637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VBSPd), |
| 25638 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25639 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25640 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25641 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25643 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25644 | GIR_RootConstrainSelectedInstOperands, |
| 25645 | // GIR_Coverage, 2561, |
| 25646 | GIR_EraseRootFromParent_Done, |
| 25647 | // Label 1430: @69049 |
| 25648 | GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(69112), // Rule ID 2566 // |
| 25649 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 25650 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl), |
| 25651 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 25652 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25653 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25654 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 25655 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25656 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25657 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25658 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25659 | // (intrinsic_wo_chain:{ *:[v16i8] } 3416:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VBSPq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 25660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VBSPq), |
| 25661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25662 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25663 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25664 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25666 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25667 | GIR_RootConstrainSelectedInstOperands, |
| 25668 | // GIR_Coverage, 2566, |
| 25669 | GIR_EraseRootFromParent_Done, |
| 25670 | // Label 1431: @69112 |
| 25671 | GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(69175), // Rule ID 2567 // |
| 25672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 25673 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl), |
| 25674 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25675 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25676 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25677 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 25678 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25679 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25680 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25681 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25682 | // (intrinsic_wo_chain:{ *:[v8i16] } 3416:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VBSPq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 25683 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VBSPq), |
| 25684 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25685 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25686 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25687 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25689 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25690 | GIR_RootConstrainSelectedInstOperands, |
| 25691 | // GIR_Coverage, 2567, |
| 25692 | GIR_EraseRootFromParent_Done, |
| 25693 | // Label 1432: @69175 |
| 25694 | GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(69238), // Rule ID 2568 // |
| 25695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 25696 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl), |
| 25697 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25698 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25699 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25700 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 25701 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25702 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25703 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25704 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25705 | // (intrinsic_wo_chain:{ *:[v4i32] } 3416:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VBSPq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 25706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VBSPq), |
| 25707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25708 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25709 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25710 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25712 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25713 | GIR_RootConstrainSelectedInstOperands, |
| 25714 | // GIR_Coverage, 2568, |
| 25715 | GIR_EraseRootFromParent_Done, |
| 25716 | // Label 1433: @69238 |
| 25717 | GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(69301), // Rule ID 2569 // |
| 25718 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 25719 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl), |
| 25720 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25721 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25722 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25723 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 25724 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25725 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25726 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25727 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25728 | // (intrinsic_wo_chain:{ *:[v4f32] } 3416:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VBSPq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 25729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VBSPq), |
| 25730 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25731 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25732 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25733 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25735 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25736 | GIR_RootConstrainSelectedInstOperands, |
| 25737 | // GIR_Coverage, 2569, |
| 25738 | GIR_EraseRootFromParent_Done, |
| 25739 | // Label 1434: @69301 |
| 25740 | GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(69364), // Rule ID 2570 // |
| 25741 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 25742 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vbsl), |
| 25743 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 25744 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 25745 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 25746 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, |
| 25747 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25748 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25749 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25750 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25751 | // (intrinsic_wo_chain:{ *:[v2i64] } 3416:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VBSPq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 25752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VBSPq), |
| 25753 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25754 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 25755 | GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25756 | GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25758 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25759 | GIR_RootConstrainSelectedInstOperands, |
| 25760 | // GIR_Coverage, 2570, |
| 25761 | GIR_EraseRootFromParent_Done, |
| 25762 | // Label 1435: @69364 |
| 25763 | GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(69433), // Rule ID 4957 // |
| 25764 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25765 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah), |
| 25766 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 25767 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25768 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25769 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25770 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25771 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25772 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25773 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25774 | // (intrinsic_wo_chain:{ *:[v16i8] } 3330:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 25775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs8), |
| 25776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25777 | GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25778 | GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25779 | GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 25780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25781 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25782 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25783 | GIR_RootConstrainSelectedInstOperands, |
| 25784 | // GIR_Coverage, 4957, |
| 25785 | GIR_EraseRootFromParent_Done, |
| 25786 | // Label 1436: @69433 |
| 25787 | GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(69502), // Rule ID 4959 // |
| 25788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25789 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah), |
| 25790 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25791 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25792 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25793 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25794 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25795 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25796 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25797 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25798 | // (intrinsic_wo_chain:{ *:[v8i16] } 3330:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 25799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs16), |
| 25800 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25801 | GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25802 | GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25803 | GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 25804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25805 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25806 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25807 | GIR_RootConstrainSelectedInstOperands, |
| 25808 | // GIR_Coverage, 4959, |
| 25809 | GIR_EraseRootFromParent_Done, |
| 25810 | // Label 1437: @69502 |
| 25811 | GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(69571), // Rule ID 4961 // |
| 25812 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25813 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah), |
| 25814 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25815 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25816 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25817 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25818 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25819 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25820 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25821 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25822 | // (intrinsic_wo_chain:{ *:[v4i32] } 3330:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 25823 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs32), |
| 25824 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25825 | GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25826 | GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25827 | GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 25828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25829 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25830 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25831 | GIR_RootConstrainSelectedInstOperands, |
| 25832 | // GIR_Coverage, 4961, |
| 25833 | GIR_EraseRootFromParent_Done, |
| 25834 | // Label 1438: @69571 |
| 25835 | GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(69640), // Rule ID 4963 // |
| 25836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25837 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah), |
| 25838 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 25839 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25840 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25841 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25843 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25844 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25845 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25846 | // (intrinsic_wo_chain:{ *:[v16i8] } 3339:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 25847 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs8), |
| 25848 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25849 | GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25850 | GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25851 | GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 25852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25853 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25854 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25855 | GIR_RootConstrainSelectedInstOperands, |
| 25856 | // GIR_Coverage, 4963, |
| 25857 | GIR_EraseRootFromParent_Done, |
| 25858 | // Label 1439: @69640 |
| 25859 | GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(69709), // Rule ID 4965 // |
| 25860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25861 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah), |
| 25862 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25863 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25864 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25865 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25867 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25868 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25869 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25870 | // (intrinsic_wo_chain:{ *:[v8i16] } 3339:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 25871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs16), |
| 25872 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25873 | GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25874 | GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25875 | GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 25876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25877 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25878 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25879 | GIR_RootConstrainSelectedInstOperands, |
| 25880 | // GIR_Coverage, 4965, |
| 25881 | GIR_EraseRootFromParent_Done, |
| 25882 | // Label 1440: @69709 |
| 25883 | GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(69778), // Rule ID 4967 // |
| 25884 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25885 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah), |
| 25886 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25887 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25888 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25889 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25891 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25892 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25893 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25894 | // (intrinsic_wo_chain:{ *:[v4i32] } 3339:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 25895 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs32), |
| 25896 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25897 | GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25898 | GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25899 | GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 25900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25901 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25902 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25903 | GIR_RootConstrainSelectedInstOperands, |
| 25904 | // GIR_Coverage, 4967, |
| 25905 | GIR_EraseRootFromParent_Done, |
| 25906 | // Label 1441: @69778 |
| 25907 | GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(69847), // Rule ID 4969 // |
| 25908 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25909 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash), |
| 25910 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 25911 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25912 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25913 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25915 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25916 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25917 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25918 | // (intrinsic_wo_chain:{ *:[v16i8] } 3332:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 25919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs8), |
| 25920 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25921 | GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25922 | GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25923 | GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 25924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25925 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25926 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25927 | GIR_RootConstrainSelectedInstOperands, |
| 25928 | // GIR_Coverage, 4969, |
| 25929 | GIR_EraseRootFromParent_Done, |
| 25930 | // Label 1442: @69847 |
| 25931 | GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(69916), // Rule ID 4971 // |
| 25932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25933 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash), |
| 25934 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25935 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25936 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25937 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25939 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25940 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25941 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25942 | // (intrinsic_wo_chain:{ *:[v8i16] } 3332:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 25943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs16), |
| 25944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25945 | GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25946 | GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25947 | GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 25948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25949 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25950 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25951 | GIR_RootConstrainSelectedInstOperands, |
| 25952 | // GIR_Coverage, 4971, |
| 25953 | GIR_EraseRootFromParent_Done, |
| 25954 | // Label 1443: @69916 |
| 25955 | GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(69985), // Rule ID 4973 // |
| 25956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25957 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash), |
| 25958 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25959 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25960 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25961 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25962 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25963 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25964 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25965 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25966 | // (intrinsic_wo_chain:{ *:[v4i32] } 3332:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 25967 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs32), |
| 25968 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25969 | GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25970 | GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25971 | GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 25972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25973 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25974 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25975 | GIR_RootConstrainSelectedInstOperands, |
| 25976 | // GIR_Coverage, 4973, |
| 25977 | GIR_EraseRootFromParent_Done, |
| 25978 | // Label 1444: @69985 |
| 25979 | GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(70054), // Rule ID 4975 // |
| 25980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25981 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash), |
| 25982 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 25983 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25984 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25985 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25987 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25988 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25989 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25990 | // (intrinsic_wo_chain:{ *:[v16i8] } 3341:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 25991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs8), |
| 25992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25993 | GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 25994 | GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 25995 | GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 25996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25997 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25998 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25999 | GIR_RootConstrainSelectedInstOperands, |
| 26000 | // GIR_Coverage, 4975, |
| 26001 | GIR_EraseRootFromParent_Done, |
| 26002 | // Label 1445: @70054 |
| 26003 | GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(70123), // Rule ID 4977 // |
| 26004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26005 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash), |
| 26006 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26007 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26008 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26009 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26011 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26012 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26013 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26014 | // (intrinsic_wo_chain:{ *:[v8i16] } 3341:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26015 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs16), |
| 26016 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26017 | GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26018 | GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26019 | GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26021 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26022 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26023 | GIR_RootConstrainSelectedInstOperands, |
| 26024 | // GIR_Coverage, 4977, |
| 26025 | GIR_EraseRootFromParent_Done, |
| 26026 | // Label 1446: @70123 |
| 26027 | GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(70192), // Rule ID 4979 // |
| 26028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26029 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash), |
| 26030 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26031 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26032 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26033 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26035 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26036 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26037 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26038 | // (intrinsic_wo_chain:{ *:[v4i32] } 3341:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26039 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs32), |
| 26040 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26041 | GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26042 | GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26043 | GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26045 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26046 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26047 | GIR_RootConstrainSelectedInstOperands, |
| 26048 | // GIR_Coverage, 4979, |
| 26049 | GIR_EraseRootFromParent_Done, |
| 26050 | // Label 1447: @70192 |
| 26051 | GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(70284), // Rule ID 2712 // |
| 26052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 26053 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1c), |
| 26054 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26055 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26056 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26057 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26059 | // (intrinsic_wo_chain:{ *:[v4i32] } 3396:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 26060 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 26061 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 26062 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 26063 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26064 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 26065 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 26066 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 26067 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26068 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 26069 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 26070 | GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 26071 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 26072 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 26073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1C), |
| 26074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26075 | GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 26076 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26077 | GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 26078 | GIR_RootConstrainSelectedInstOperands, |
| 26079 | // GIR_Coverage, 2712, |
| 26080 | GIR_EraseRootFromParent_Done, |
| 26081 | // Label 1448: @70284 |
| 26082 | GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(70376), // Rule ID 2713 // |
| 26083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 26084 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1m), |
| 26085 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26086 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26087 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26088 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26090 | // (intrinsic_wo_chain:{ *:[v4i32] } 3398:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 26091 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 26092 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 26093 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 26094 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26095 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 26096 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 26097 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 26098 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26099 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 26100 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 26101 | GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 26102 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 26103 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 26104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1M), |
| 26105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26106 | GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 26107 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26108 | GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 26109 | GIR_RootConstrainSelectedInstOperands, |
| 26110 | // GIR_Coverage, 2713, |
| 26111 | GIR_EraseRootFromParent_Done, |
| 26112 | // Label 1449: @70376 |
| 26113 | GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(70468), // Rule ID 2714 // |
| 26114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 26115 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1p), |
| 26116 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26117 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26118 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26119 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26121 | // (intrinsic_wo_chain:{ *:[v4i32] } 3399:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 26122 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 26123 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 26124 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 26125 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26126 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 26127 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 26128 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 26129 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26130 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 26131 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 26132 | GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 26133 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 26134 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 26135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1P), |
| 26136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26137 | GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 26138 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26139 | GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 26140 | GIR_RootConstrainSelectedInstOperands, |
| 26141 | // GIR_Coverage, 2714, |
| 26142 | GIR_EraseRootFromParent_Done, |
| 26143 | // Label 1450: @70468 |
| 26144 | GIM_Reject, |
| 26145 | // Label 1288: @70469 |
| 26146 | GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(73799), |
| 26147 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 26148 | GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(70559), // Rule ID 3842 // |
| 26149 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26150 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26151 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26152 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26153 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26154 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26155 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26156 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26157 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 26158 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26159 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26160 | // (intrinsic_wo_chain:{ *:[v8i16] } 3371:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 26161 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26162 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26163 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8bh), |
| 26165 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26166 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26168 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26169 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26170 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26171 | GIR_RootConstrainSelectedInstOperands, |
| 26172 | // GIR_Coverage, 3842, |
| 26173 | GIR_EraseRootFromParent_Done, |
| 26174 | // Label 1452: @70559 |
| 26175 | GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(70641), // Rule ID 3846 // |
| 26176 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26177 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26178 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26179 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26180 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26181 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26183 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26184 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 26185 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26186 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26187 | // (intrinsic_wo_chain:{ *:[v8i16] } 3371:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 26188 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26189 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26190 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26191 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8th), |
| 26192 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26193 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26195 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26196 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26197 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26198 | GIR_RootConstrainSelectedInstOperands, |
| 26199 | // GIR_Coverage, 3846, |
| 26200 | GIR_EraseRootFromParent_Done, |
| 26201 | // Label 1453: @70641 |
| 26202 | GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(70723), // Rule ID 3850 // |
| 26203 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26204 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26205 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26206 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26207 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26208 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26209 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26210 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26211 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 26212 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26213 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26214 | // (intrinsic_wo_chain:{ *:[v4i32] } 3371:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 26215 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26216 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26217 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16bh), |
| 26219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26220 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26222 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26223 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26224 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26225 | GIR_RootConstrainSelectedInstOperands, |
| 26226 | // GIR_Coverage, 3850, |
| 26227 | GIR_EraseRootFromParent_Done, |
| 26228 | // Label 1454: @70723 |
| 26229 | GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(70805), // Rule ID 3854 // |
| 26230 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26231 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26232 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26233 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26234 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26235 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26237 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26238 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 26239 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26240 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26241 | // (intrinsic_wo_chain:{ *:[v4i32] } 3371:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 26242 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26243 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26244 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16th), |
| 26246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26247 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26249 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26250 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26251 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26252 | GIR_RootConstrainSelectedInstOperands, |
| 26253 | // GIR_Coverage, 3854, |
| 26254 | GIR_EraseRootFromParent_Done, |
| 26255 | // Label 1455: @70805 |
| 26256 | GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(70887), // Rule ID 3858 // |
| 26257 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26258 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26259 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26260 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26261 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26262 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26263 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26264 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26265 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 26266 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26267 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26268 | // (intrinsic_wo_chain:{ *:[v8i16] } 3371:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 26269 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26270 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26271 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8bh), |
| 26273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26274 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26276 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26277 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26278 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26279 | GIR_RootConstrainSelectedInstOperands, |
| 26280 | // GIR_Coverage, 3858, |
| 26281 | GIR_EraseRootFromParent_Done, |
| 26282 | // Label 1456: @70887 |
| 26283 | GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(70969), // Rule ID 3862 // |
| 26284 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26285 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26286 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26287 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26288 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26289 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26290 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26291 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26292 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 26293 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26294 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26295 | // (intrinsic_wo_chain:{ *:[v8i16] } 3371:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 26296 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26297 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26298 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8th), |
| 26300 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26301 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26303 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26304 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26305 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26306 | GIR_RootConstrainSelectedInstOperands, |
| 26307 | // GIR_Coverage, 3862, |
| 26308 | GIR_EraseRootFromParent_Done, |
| 26309 | // Label 1457: @70969 |
| 26310 | GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(71051), // Rule ID 3866 // |
| 26311 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26312 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26313 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26314 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26315 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26316 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26318 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26319 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 26320 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26321 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26322 | // (intrinsic_wo_chain:{ *:[v4i32] } 3371:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 26323 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26324 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26325 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16bh), |
| 26327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26328 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26330 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26331 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26332 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26333 | GIR_RootConstrainSelectedInstOperands, |
| 26334 | // GIR_Coverage, 3866, |
| 26335 | GIR_EraseRootFromParent_Done, |
| 26336 | // Label 1458: @71051 |
| 26337 | GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(71133), // Rule ID 3870 // |
| 26338 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26339 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26340 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26341 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26342 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26343 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26344 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26345 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26346 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 26347 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26348 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26349 | // (intrinsic_wo_chain:{ *:[v4i32] } 3371:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 26350 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26351 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26352 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16th), |
| 26354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26355 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26356 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26357 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26358 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26359 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26360 | GIR_RootConstrainSelectedInstOperands, |
| 26361 | // GIR_Coverage, 3870, |
| 26362 | GIR_EraseRootFromParent_Done, |
| 26363 | // Label 1459: @71133 |
| 26364 | GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(71220), // Rule ID 4502 // |
| 26365 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26366 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26367 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26368 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26369 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26370 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26371 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26372 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26373 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26374 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26375 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26376 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26377 | // (intrinsic_wo_chain:{ *:[v8i16] } 3326:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26378 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26379 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26380 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8), |
| 26382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26383 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26384 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26386 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26387 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26388 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26389 | GIR_RootConstrainSelectedInstOperands, |
| 26390 | // GIR_Coverage, 4502, |
| 26391 | GIR_EraseRootFromParent_Done, |
| 26392 | // Label 1460: @71220 |
| 26393 | GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(71307), // Rule ID 4504 // |
| 26394 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26395 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26396 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26397 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26398 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26399 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26400 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26401 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26402 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26403 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26404 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26405 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26406 | // (intrinsic_wo_chain:{ *:[v8i16] } 3326:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26407 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26408 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26409 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs8), |
| 26411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26412 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26413 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26415 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26416 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26417 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26418 | GIR_RootConstrainSelectedInstOperands, |
| 26419 | // GIR_Coverage, 4504, |
| 26420 | GIR_EraseRootFromParent_Done, |
| 26421 | // Label 1461: @71307 |
| 26422 | GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(71394), // Rule ID 4506 // |
| 26423 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26424 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26425 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26426 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26427 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26428 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26429 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26430 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26431 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26432 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26433 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26434 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26435 | // (intrinsic_wo_chain:{ *:[v4i32] } 3326:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26436 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26437 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26438 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16), |
| 26440 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26441 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26442 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26444 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26445 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26446 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26447 | GIR_RootConstrainSelectedInstOperands, |
| 26448 | // GIR_Coverage, 4506, |
| 26449 | GIR_EraseRootFromParent_Done, |
| 26450 | // Label 1462: @71394 |
| 26451 | GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(71481), // Rule ID 4508 // |
| 26452 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26453 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26454 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26455 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26456 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26457 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26458 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26459 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26460 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26461 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26462 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26463 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26464 | // (intrinsic_wo_chain:{ *:[v4i32] } 3326:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26465 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26466 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26467 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs16), |
| 26469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26470 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26471 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26473 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26474 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26475 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26476 | GIR_RootConstrainSelectedInstOperands, |
| 26477 | // GIR_Coverage, 4508, |
| 26478 | GIR_EraseRootFromParent_Done, |
| 26479 | // Label 1463: @71481 |
| 26480 | GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(71568), // Rule ID 4510 // |
| 26481 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26482 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26483 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 26484 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26485 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26486 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26487 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26489 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26490 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26491 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26492 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26493 | // (intrinsic_wo_chain:{ *:[v2i64] } 3326:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26494 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26495 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26496 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs32), |
| 26498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26499 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26500 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26502 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26503 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26504 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26505 | GIR_RootConstrainSelectedInstOperands, |
| 26506 | // GIR_Coverage, 4510, |
| 26507 | GIR_EraseRootFromParent_Done, |
| 26508 | // Label 1464: @71568 |
| 26509 | GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(71655), // Rule ID 4512 // |
| 26510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26511 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26512 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 26513 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26514 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26515 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26516 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26517 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26518 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26519 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26520 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26521 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26522 | // (intrinsic_wo_chain:{ *:[v2i64] } 3326:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26523 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26524 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26525 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs32), |
| 26527 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26528 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26529 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26531 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26532 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26533 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26534 | GIR_RootConstrainSelectedInstOperands, |
| 26535 | // GIR_Coverage, 4512, |
| 26536 | GIR_EraseRootFromParent_Done, |
| 26537 | // Label 1465: @71655 |
| 26538 | GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(71742), // Rule ID 4514 // |
| 26539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26540 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26541 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26542 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26543 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26544 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26545 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26546 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26547 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26548 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26549 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26550 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26551 | // (intrinsic_wo_chain:{ *:[v8i16] } 3326:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26552 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26553 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26554 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26555 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu8), |
| 26556 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26557 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26558 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26560 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26561 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26562 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26563 | GIR_RootConstrainSelectedInstOperands, |
| 26564 | // GIR_Coverage, 4514, |
| 26565 | GIR_EraseRootFromParent_Done, |
| 26566 | // Label 1466: @71742 |
| 26567 | GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(71829), // Rule ID 4516 // |
| 26568 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26569 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26570 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26571 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26572 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26573 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26574 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26575 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26576 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26577 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26578 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26579 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26580 | // (intrinsic_wo_chain:{ *:[v8i16] } 3326:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26581 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26582 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26583 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu8), |
| 26585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26586 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26587 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26589 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26590 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26591 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26592 | GIR_RootConstrainSelectedInstOperands, |
| 26593 | // GIR_Coverage, 4516, |
| 26594 | GIR_EraseRootFromParent_Done, |
| 26595 | // Label 1467: @71829 |
| 26596 | GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(71916), // Rule ID 4518 // |
| 26597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26598 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26599 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26600 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26601 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26602 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26603 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26604 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26605 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26606 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26607 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26608 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26609 | // (intrinsic_wo_chain:{ *:[v4i32] } 3326:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26610 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26611 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26612 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu16), |
| 26614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26615 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26616 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26618 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26619 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26620 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26621 | GIR_RootConstrainSelectedInstOperands, |
| 26622 | // GIR_Coverage, 4518, |
| 26623 | GIR_EraseRootFromParent_Done, |
| 26624 | // Label 1468: @71916 |
| 26625 | GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(72003), // Rule ID 4520 // |
| 26626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26627 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26628 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26629 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26630 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26631 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26632 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26634 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26635 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26636 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26637 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26638 | // (intrinsic_wo_chain:{ *:[v4i32] } 3326:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26639 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26640 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26641 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu16), |
| 26643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26644 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26645 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26647 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26648 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26649 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26650 | GIR_RootConstrainSelectedInstOperands, |
| 26651 | // GIR_Coverage, 4520, |
| 26652 | GIR_EraseRootFromParent_Done, |
| 26653 | // Label 1469: @72003 |
| 26654 | GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(72090), // Rule ID 4522 // |
| 26655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26656 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26657 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 26658 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26659 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26660 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26661 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26663 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26664 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26665 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26666 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26667 | // (intrinsic_wo_chain:{ *:[v2i64] } 3326:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26668 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26669 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26670 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26671 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu32), |
| 26672 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26673 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26674 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26676 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26677 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26678 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26679 | GIR_RootConstrainSelectedInstOperands, |
| 26680 | // GIR_Coverage, 4522, |
| 26681 | GIR_EraseRootFromParent_Done, |
| 26682 | // Label 1470: @72090 |
| 26683 | GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(72177), // Rule ID 4524 // |
| 26684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26685 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26686 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 26687 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26688 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26689 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26690 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26691 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26692 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26693 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26694 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26695 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26696 | // (intrinsic_wo_chain:{ *:[v2i64] } 3326:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26697 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26698 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26699 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu32), |
| 26701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26702 | GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26703 | GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26705 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26706 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26707 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26708 | GIR_RootConstrainSelectedInstOperands, |
| 26709 | // GIR_Coverage, 4524, |
| 26710 | GIR_EraseRootFromParent_Done, |
| 26711 | // Label 1471: @72177 |
| 26712 | GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(72273), // Rule ID 4147 // |
| 26713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 26714 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 26715 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26716 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26717 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26718 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 26719 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 26720 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26721 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 26722 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 26723 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 26724 | // MIs[1] Operand 1 |
| 26725 | // No operand predicates |
| 26726 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26727 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26728 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26729 | // (intrinsic_wo_chain:{ *:[v8f16] } 3269:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 26730 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26731 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26732 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf16), |
| 26734 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26735 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 26736 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 26737 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 26738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26739 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26740 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26741 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26742 | GIR_RootConstrainSelectedInstOperands, |
| 26743 | // GIR_Coverage, 4147, |
| 26744 | GIR_EraseRootFromParent_Done, |
| 26745 | // Label 1472: @72273 |
| 26746 | GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(72369), // Rule ID 4149 // |
| 26747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 26748 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 26749 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26750 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26751 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26752 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26753 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 26754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26755 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 26756 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 26757 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 26758 | // MIs[1] Operand 1 |
| 26759 | // No operand predicates |
| 26760 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26761 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26762 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26763 | // (intrinsic_wo_chain:{ *:[v4f32] } 3269:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 26764 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26765 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26766 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26767 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf32), |
| 26768 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26769 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 26770 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 26771 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 26772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26773 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26774 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26775 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26776 | GIR_RootConstrainSelectedInstOperands, |
| 26777 | // GIR_Coverage, 4149, |
| 26778 | GIR_EraseRootFromParent_Done, |
| 26779 | // Label 1473: @72369 |
| 26780 | GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(72465), // Rule ID 4656 // |
| 26781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26782 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 26783 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26784 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26785 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26786 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 26787 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 26788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26789 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 26790 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 26791 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 26792 | // MIs[1] Operand 1 |
| 26793 | // No operand predicates |
| 26794 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26795 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26796 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26797 | // (intrinsic_wo_chain:{ *:[v16i8] } 3269:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 26798 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26799 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26800 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi8), |
| 26802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26803 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 26804 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 26805 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 26806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26807 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26808 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26809 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26810 | GIR_RootConstrainSelectedInstOperands, |
| 26811 | // GIR_Coverage, 4656, |
| 26812 | GIR_EraseRootFromParent_Done, |
| 26813 | // Label 1474: @72465 |
| 26814 | GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(72561), // Rule ID 4658 // |
| 26815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26816 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 26817 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26818 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26819 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26820 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 26821 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 26822 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26823 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 26824 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 26825 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 26826 | // MIs[1] Operand 1 |
| 26827 | // No operand predicates |
| 26828 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26829 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26830 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26831 | // (intrinsic_wo_chain:{ *:[v8i16] } 3269:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 26832 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26833 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26834 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi16), |
| 26836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26837 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 26838 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 26839 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 26840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26841 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26842 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26843 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26844 | GIR_RootConstrainSelectedInstOperands, |
| 26845 | // GIR_Coverage, 4658, |
| 26846 | GIR_EraseRootFromParent_Done, |
| 26847 | // Label 1475: @72561 |
| 26848 | GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(72657), // Rule ID 4660 // |
| 26849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26850 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 26851 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26852 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26853 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26854 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26855 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 26856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26857 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 26858 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 26859 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 26860 | // MIs[1] Operand 1 |
| 26861 | // No operand predicates |
| 26862 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26863 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26864 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26865 | // (intrinsic_wo_chain:{ *:[v4i32] } 3269:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 26866 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26867 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26868 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi32), |
| 26870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26871 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 26872 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 26873 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 26874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26875 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26876 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26877 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26878 | GIR_RootConstrainSelectedInstOperands, |
| 26879 | // GIR_Coverage, 4660, |
| 26880 | GIR_EraseRootFromParent_Done, |
| 26881 | // Label 1476: @72657 |
| 26882 | GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(72753), // Rule ID 4662 // |
| 26883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26884 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 26885 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26886 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26887 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26888 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 26889 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 26890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26891 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 26892 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 26893 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 26894 | // MIs[1] Operand 1 |
| 26895 | // No operand predicates |
| 26896 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26897 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26898 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26899 | // (intrinsic_wo_chain:{ *:[v16i8] } 3269:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 26900 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26901 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26902 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26903 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs8), |
| 26904 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26905 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 26906 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 26907 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 26908 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26909 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26910 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26911 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26912 | GIR_RootConstrainSelectedInstOperands, |
| 26913 | // GIR_Coverage, 4662, |
| 26914 | GIR_EraseRootFromParent_Done, |
| 26915 | // Label 1477: @72753 |
| 26916 | GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(72849), // Rule ID 4664 // |
| 26917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26918 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 26919 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26920 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26921 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26922 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 26923 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 26924 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26925 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 26926 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 26927 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 26928 | // MIs[1] Operand 1 |
| 26929 | // No operand predicates |
| 26930 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26931 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26932 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26933 | // (intrinsic_wo_chain:{ *:[v8i16] } 3269:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 26934 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26935 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26936 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26937 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs16), |
| 26938 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26939 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 26940 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 26941 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 26942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26943 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26944 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26945 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26946 | GIR_RootConstrainSelectedInstOperands, |
| 26947 | // GIR_Coverage, 4664, |
| 26948 | GIR_EraseRootFromParent_Done, |
| 26949 | // Label 1478: @72849 |
| 26950 | GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(72945), // Rule ID 4666 // |
| 26951 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26952 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 26953 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26954 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26955 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26956 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26957 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 26958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26959 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 26960 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 26961 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 26962 | // MIs[1] Operand 1 |
| 26963 | // No operand predicates |
| 26964 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26965 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26966 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26967 | // (intrinsic_wo_chain:{ *:[v4i32] } 3269:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 26968 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26969 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26970 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 26971 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs32), |
| 26972 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26973 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 26974 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 26975 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 26976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26977 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26978 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26979 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26980 | GIR_RootConstrainSelectedInstOperands, |
| 26981 | // GIR_Coverage, 4666, |
| 26982 | GIR_EraseRootFromParent_Done, |
| 26983 | // Label 1479: @72945 |
| 26984 | GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(73021), // Rule ID 3134 // |
| 26985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26986 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 26987 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26988 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26989 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26990 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 26991 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 26992 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26993 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 26994 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26995 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26996 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26997 | // (intrinsic_wo_chain:{ *:[i32] } 3262:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 26998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs8), |
| 26999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 27000 | GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 27001 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27002 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27004 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27005 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27006 | GIR_RootConstrainSelectedInstOperands, |
| 27007 | // GIR_Coverage, 3134, |
| 27008 | GIR_EraseRootFromParent_Done, |
| 27009 | // Label 1480: @73021 |
| 27010 | GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(73097), // Rule ID 3136 // |
| 27011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27012 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 27013 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27014 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27015 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27016 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27017 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 27018 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27019 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 27020 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27021 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27022 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27023 | // (intrinsic_wo_chain:{ *:[i32] } 3262:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 27024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs16), |
| 27025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 27026 | GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 27027 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27028 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27030 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27031 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27032 | GIR_RootConstrainSelectedInstOperands, |
| 27033 | // GIR_Coverage, 3136, |
| 27034 | GIR_EraseRootFromParent_Done, |
| 27035 | // Label 1481: @73097 |
| 27036 | GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(73173), // Rule ID 3138 // |
| 27037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27038 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 27039 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27040 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27041 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27042 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27043 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 27044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27045 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 27046 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27047 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27048 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27049 | // (intrinsic_wo_chain:{ *:[i32] } 3262:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 27050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs32), |
| 27051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 27052 | GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 27053 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27054 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27056 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27057 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27058 | GIR_RootConstrainSelectedInstOperands, |
| 27059 | // GIR_Coverage, 3138, |
| 27060 | GIR_EraseRootFromParent_Done, |
| 27061 | // Label 1482: @73173 |
| 27062 | GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(73249), // Rule ID 3140 // |
| 27063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27064 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 27065 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27066 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27067 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27068 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27069 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 27070 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27071 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 27072 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27073 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27074 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27075 | // (intrinsic_wo_chain:{ *:[i32] } 3262:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 27076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu8), |
| 27077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 27078 | GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 27079 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27080 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27082 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27083 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27084 | GIR_RootConstrainSelectedInstOperands, |
| 27085 | // GIR_Coverage, 3140, |
| 27086 | GIR_EraseRootFromParent_Done, |
| 27087 | // Label 1483: @73249 |
| 27088 | GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(73325), // Rule ID 3142 // |
| 27089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27090 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 27091 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27092 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27093 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27094 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27095 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 27096 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27097 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 27098 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27099 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27100 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27101 | // (intrinsic_wo_chain:{ *:[i32] } 3262:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 27102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu16), |
| 27103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 27104 | GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 27105 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27106 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27108 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27109 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27110 | GIR_RootConstrainSelectedInstOperands, |
| 27111 | // GIR_Coverage, 3142, |
| 27112 | GIR_EraseRootFromParent_Done, |
| 27113 | // Label 1484: @73325 |
| 27114 | GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(73401), // Rule ID 3144 // |
| 27115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27116 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 27117 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27118 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27119 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27120 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27121 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 27122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27123 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 27124 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27125 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27126 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27127 | // (intrinsic_wo_chain:{ *:[i32] } 3262:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 27128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu32), |
| 27129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 27130 | GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 27131 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27132 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27134 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27135 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27136 | GIR_RootConstrainSelectedInstOperands, |
| 27137 | // GIR_Coverage, 3144, |
| 27138 | GIR_EraseRootFromParent_Done, |
| 27139 | // Label 1485: @73401 |
| 27140 | GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(73486), // Rule ID 4111 // |
| 27141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27142 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq), |
| 27143 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27144 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27145 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27146 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27147 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 27148 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27149 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 27150 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27151 | // MIs[1] Operand 1 |
| 27152 | // No operand predicates |
| 27153 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27154 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27155 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27156 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27157 | // (intrinsic_wo_chain:{ *:[v8f16] } 3272:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16), |
| 27159 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27160 | GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src |
| 27161 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27162 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27163 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27165 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27166 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27167 | GIR_RootConstrainSelectedInstOperands, |
| 27168 | // GIR_Coverage, 4111, |
| 27169 | GIR_EraseRootFromParent_Done, |
| 27170 | // Label 1486: @73486 |
| 27171 | GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(73571), // Rule ID 4114 // |
| 27172 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27173 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq), |
| 27174 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27175 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27176 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27177 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27178 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 27179 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27180 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 27181 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27182 | // MIs[1] Operand 1 |
| 27183 | // No operand predicates |
| 27184 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27185 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27186 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27187 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27188 | // (intrinsic_wo_chain:{ *:[v4f32] } 3272:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32), |
| 27190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27191 | GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src |
| 27192 | GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27193 | GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27194 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27196 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27197 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27198 | GIR_RootConstrainSelectedInstOperands, |
| 27199 | // GIR_Coverage, 4114, |
| 27200 | GIR_EraseRootFromParent_Done, |
| 27201 | // Label 1487: @73571 |
| 27202 | GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(73667), // Rule ID 2706 // |
| 27203 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 27204 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx2), |
| 27205 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 27206 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 27207 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 27208 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 27209 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 27210 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27211 | // (intrinsic_wo_chain:{ *:[v8i8] } 3528:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm) => (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 27212 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 27213 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 27214 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27215 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 27216 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 27217 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 27218 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 27219 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 27220 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 27221 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 27222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX2), |
| 27223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27224 | GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 27225 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27226 | GIR_RootToRootCopy, /*OpIdx*/5, // Vm |
| 27227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27228 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27229 | GIR_RootConstrainSelectedInstOperands, |
| 27230 | // GIR_Coverage, 2706, |
| 27231 | GIR_EraseRootFromParent_Done, |
| 27232 | // Label 1488: @73667 |
| 27233 | GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(73798), // Rule ID 2707 // |
| 27234 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 27235 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl3), |
| 27236 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 27237 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 27238 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 27239 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 27240 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 27241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27242 | // (intrinsic_wo_chain:{ *:[v8i8] } 3525:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 27243 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 27244 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8, |
| 27245 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27246 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27247 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 27248 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 27249 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27250 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0 |
| 27251 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 27252 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1 |
| 27253 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 27254 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2 |
| 27255 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 27256 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 27257 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 27258 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 27259 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 27260 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 27261 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 27262 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 27263 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL3Pseudo), |
| 27264 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27265 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27266 | GIR_RootToRootCopy, /*OpIdx*/5, // Vm |
| 27267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27268 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27269 | GIR_RootConstrainSelectedInstOperands, |
| 27270 | // GIR_Coverage, 2707, |
| 27271 | GIR_EraseRootFromParent_Done, |
| 27272 | // Label 1489: @73798 |
| 27273 | GIM_Reject, |
| 27274 | // Label 1451: @73799 |
| 27275 | GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(79057), |
| 27276 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 27277 | GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(73898), // Rule ID 3953 // |
| 27278 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27279 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27280 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27281 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27282 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27283 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27284 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27286 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27287 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27288 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27289 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27290 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27291 | // (intrinsic_wo_chain:{ *:[v16i8] } 3367:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 27292 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27293 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27294 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs8), |
| 27296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27297 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27298 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27300 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27301 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27302 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27303 | GIR_RootConstrainSelectedInstOperands, |
| 27304 | // GIR_Coverage, 3953, |
| 27305 | GIR_EraseRootFromParent_Done, |
| 27306 | // Label 1491: @73898 |
| 27307 | GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(73989), // Rule ID 3955 // |
| 27308 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27309 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27310 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27311 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27312 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27313 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27314 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27315 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27316 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27317 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27318 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27319 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27320 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27321 | // (intrinsic_wo_chain:{ *:[v8i16] } 3367:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 27322 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27323 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27324 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs16), |
| 27326 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27327 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27328 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27330 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27331 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27332 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27333 | GIR_RootConstrainSelectedInstOperands, |
| 27334 | // GIR_Coverage, 3955, |
| 27335 | GIR_EraseRootFromParent_Done, |
| 27336 | // Label 1492: @73989 |
| 27337 | GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(74080), // Rule ID 3957 // |
| 27338 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27339 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27340 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27341 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27342 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27343 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27344 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27345 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27346 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27347 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27348 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27349 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27350 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27351 | // (intrinsic_wo_chain:{ *:[v4i32] } 3367:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 27352 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27353 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27354 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27355 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs32), |
| 27356 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27357 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27358 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27360 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27361 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27362 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27363 | GIR_RootConstrainSelectedInstOperands, |
| 27364 | // GIR_Coverage, 3957, |
| 27365 | GIR_EraseRootFromParent_Done, |
| 27366 | // Label 1493: @74080 |
| 27367 | GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(74171), // Rule ID 3959 // |
| 27368 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27369 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27370 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27371 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27372 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27373 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27374 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27376 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27377 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27378 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27379 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27380 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27381 | // (intrinsic_wo_chain:{ *:[v16i8] } 3367:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 27382 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27383 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27384 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27385 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu8), |
| 27386 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27387 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27388 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27390 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27391 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27392 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27393 | GIR_RootConstrainSelectedInstOperands, |
| 27394 | // GIR_Coverage, 3959, |
| 27395 | GIR_EraseRootFromParent_Done, |
| 27396 | // Label 1494: @74171 |
| 27397 | GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(74262), // Rule ID 3961 // |
| 27398 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27399 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27400 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27401 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27402 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27403 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27404 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27406 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27407 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27408 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27409 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27410 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27411 | // (intrinsic_wo_chain:{ *:[v8i16] } 3367:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 27412 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27413 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27414 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu16), |
| 27416 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27417 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27418 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27420 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27421 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27422 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27423 | GIR_RootConstrainSelectedInstOperands, |
| 27424 | // GIR_Coverage, 3961, |
| 27425 | GIR_EraseRootFromParent_Done, |
| 27426 | // Label 1495: @74262 |
| 27427 | GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(74353), // Rule ID 3963 // |
| 27428 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27429 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27430 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27431 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27432 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27433 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27434 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27435 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27436 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27437 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27438 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27439 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27440 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27441 | // (intrinsic_wo_chain:{ *:[v4i32] } 3367:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 27442 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27443 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27444 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27445 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu32), |
| 27446 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27447 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27448 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27450 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27451 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27452 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27453 | GIR_RootConstrainSelectedInstOperands, |
| 27454 | // GIR_Coverage, 3963, |
| 27455 | GIR_EraseRootFromParent_Done, |
| 27456 | // Label 1496: @74353 |
| 27457 | GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(74444), // Rule ID 3965 // |
| 27458 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27459 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27460 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27461 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27462 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27463 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27464 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27465 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27466 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27467 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27468 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27469 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27470 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27471 | // (intrinsic_wo_chain:{ *:[v16i8] } 3367:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 27472 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27473 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27474 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27475 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs8), |
| 27476 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27477 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27478 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27480 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27481 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27482 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27483 | GIR_RootConstrainSelectedInstOperands, |
| 27484 | // GIR_Coverage, 3965, |
| 27485 | GIR_EraseRootFromParent_Done, |
| 27486 | // Label 1497: @74444 |
| 27487 | GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(74535), // Rule ID 3967 // |
| 27488 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27489 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27490 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27491 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27492 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27493 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27494 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27496 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27497 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27498 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27499 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27500 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27501 | // (intrinsic_wo_chain:{ *:[v8i16] } 3367:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 27502 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27503 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27504 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs16), |
| 27506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27507 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27508 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27510 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27511 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27512 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27513 | GIR_RootConstrainSelectedInstOperands, |
| 27514 | // GIR_Coverage, 3967, |
| 27515 | GIR_EraseRootFromParent_Done, |
| 27516 | // Label 1498: @74535 |
| 27517 | GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(74626), // Rule ID 3969 // |
| 27518 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27519 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27520 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27521 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27522 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27523 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27524 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27525 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27526 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27527 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27528 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27529 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27530 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27531 | // (intrinsic_wo_chain:{ *:[v4i32] } 3367:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 27532 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27533 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27534 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs32), |
| 27536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27537 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27538 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27540 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27541 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27542 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27543 | GIR_RootConstrainSelectedInstOperands, |
| 27544 | // GIR_Coverage, 3969, |
| 27545 | GIR_EraseRootFromParent_Done, |
| 27546 | // Label 1499: @74626 |
| 27547 | GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(74717), // Rule ID 3971 // |
| 27548 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27549 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27550 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27551 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27552 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27553 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27554 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27556 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27557 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27558 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27559 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27560 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27561 | // (intrinsic_wo_chain:{ *:[v16i8] } 3367:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 27562 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27563 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27564 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu8), |
| 27566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27567 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27568 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27570 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27571 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27572 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27573 | GIR_RootConstrainSelectedInstOperands, |
| 27574 | // GIR_Coverage, 3971, |
| 27575 | GIR_EraseRootFromParent_Done, |
| 27576 | // Label 1500: @74717 |
| 27577 | GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(74808), // Rule ID 3973 // |
| 27578 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27579 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27580 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27581 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27582 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27583 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27584 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27585 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27586 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27587 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27588 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27589 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27590 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27591 | // (intrinsic_wo_chain:{ *:[v8i16] } 3367:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 27592 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27593 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27594 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27595 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu16), |
| 27596 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27597 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27598 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27600 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27601 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27602 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27603 | GIR_RootConstrainSelectedInstOperands, |
| 27604 | // GIR_Coverage, 3973, |
| 27605 | GIR_EraseRootFromParent_Done, |
| 27606 | // Label 1501: @74808 |
| 27607 | GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(74899), // Rule ID 3975 // |
| 27608 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27609 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27610 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27611 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27612 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27613 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27614 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27615 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27616 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27617 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27618 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27619 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27620 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27621 | // (intrinsic_wo_chain:{ *:[v4i32] } 3367:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 27622 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27623 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27624 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu32), |
| 27626 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27627 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27628 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27630 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27631 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27632 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27633 | GIR_RootConstrainSelectedInstOperands, |
| 27634 | // GIR_Coverage, 3975, |
| 27635 | GIR_EraseRootFromParent_Done, |
| 27636 | // Label 1502: @74899 |
| 27637 | GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(74990), // Rule ID 3977 // |
| 27638 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27639 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27640 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27641 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27642 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27643 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27644 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27645 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27646 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27647 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27648 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27649 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27650 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27651 | // (intrinsic_wo_chain:{ *:[v16i8] } 3367:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 27652 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27653 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27654 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27655 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs8), |
| 27656 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27657 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27658 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27660 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27661 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27662 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27663 | GIR_RootConstrainSelectedInstOperands, |
| 27664 | // GIR_Coverage, 3977, |
| 27665 | GIR_EraseRootFromParent_Done, |
| 27666 | // Label 1503: @74990 |
| 27667 | GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(75081), // Rule ID 3979 // |
| 27668 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27669 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27670 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27671 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27672 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27673 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27674 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27675 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27676 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27677 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27678 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27679 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27680 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27681 | // (intrinsic_wo_chain:{ *:[v8i16] } 3367:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 27682 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27683 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27684 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27685 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs16), |
| 27686 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27687 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27688 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27690 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27691 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27692 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27693 | GIR_RootConstrainSelectedInstOperands, |
| 27694 | // GIR_Coverage, 3979, |
| 27695 | GIR_EraseRootFromParent_Done, |
| 27696 | // Label 1504: @75081 |
| 27697 | GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(75172), // Rule ID 3981 // |
| 27698 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27699 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27700 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27701 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27702 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27703 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27704 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27705 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27706 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27707 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27708 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27709 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27710 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27711 | // (intrinsic_wo_chain:{ *:[v4i32] } 3367:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 27712 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27713 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27714 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs32), |
| 27716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27717 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27718 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27720 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27721 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27722 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27723 | GIR_RootConstrainSelectedInstOperands, |
| 27724 | // GIR_Coverage, 3981, |
| 27725 | GIR_EraseRootFromParent_Done, |
| 27726 | // Label 1505: @75172 |
| 27727 | GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(75263), // Rule ID 3983 // |
| 27728 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27729 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27730 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27731 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27732 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27733 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27734 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27735 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27736 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27737 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27738 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27739 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27740 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27741 | // (intrinsic_wo_chain:{ *:[v16i8] } 3367:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 27742 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27743 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27744 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27745 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu8), |
| 27746 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27747 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27748 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27750 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27751 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27752 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27753 | GIR_RootConstrainSelectedInstOperands, |
| 27754 | // GIR_Coverage, 3983, |
| 27755 | GIR_EraseRootFromParent_Done, |
| 27756 | // Label 1506: @75263 |
| 27757 | GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(75354), // Rule ID 3985 // |
| 27758 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27759 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27760 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27761 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27762 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27763 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27764 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27765 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27766 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27767 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27768 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27769 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27770 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27771 | // (intrinsic_wo_chain:{ *:[v8i16] } 3367:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 27772 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27773 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27774 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu16), |
| 27776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27777 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27778 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27780 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27781 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27782 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27783 | GIR_RootConstrainSelectedInstOperands, |
| 27784 | // GIR_Coverage, 3985, |
| 27785 | GIR_EraseRootFromParent_Done, |
| 27786 | // Label 1507: @75354 |
| 27787 | GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(75445), // Rule ID 3987 // |
| 27788 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27789 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27790 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27791 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27792 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27793 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27794 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27795 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27796 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27797 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27798 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27799 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27800 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27801 | // (intrinsic_wo_chain:{ *:[v4i32] } 3367:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 27802 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27803 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27804 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27805 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu32), |
| 27806 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27807 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27808 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27810 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27811 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27812 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27813 | GIR_RootConstrainSelectedInstOperands, |
| 27814 | // GIR_Coverage, 3987, |
| 27815 | GIR_EraseRootFromParent_Done, |
| 27816 | // Label 1508: @75445 |
| 27817 | GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(75536), // Rule ID 3989 // |
| 27818 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27819 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27820 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27821 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27822 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27823 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27824 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27826 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27827 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27828 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27829 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27830 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27831 | // (intrinsic_wo_chain:{ *:[v16i8] } 3367:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 27832 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27833 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27834 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs8), |
| 27836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27837 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27838 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27840 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27841 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27842 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27843 | GIR_RootConstrainSelectedInstOperands, |
| 27844 | // GIR_Coverage, 3989, |
| 27845 | GIR_EraseRootFromParent_Done, |
| 27846 | // Label 1509: @75536 |
| 27847 | GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(75627), // Rule ID 3991 // |
| 27848 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27849 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27850 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27851 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27852 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27853 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27854 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27855 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27856 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27857 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27858 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27859 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27860 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27861 | // (intrinsic_wo_chain:{ *:[v8i16] } 3367:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 27862 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27863 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27864 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs16), |
| 27866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27867 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27868 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27870 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27871 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27872 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27873 | GIR_RootConstrainSelectedInstOperands, |
| 27874 | // GIR_Coverage, 3991, |
| 27875 | GIR_EraseRootFromParent_Done, |
| 27876 | // Label 1510: @75627 |
| 27877 | GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(75718), // Rule ID 3993 // |
| 27878 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27879 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27880 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27881 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27882 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27883 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27884 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27886 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27887 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27888 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27889 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27890 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27891 | // (intrinsic_wo_chain:{ *:[v4i32] } 3367:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 27892 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27893 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27894 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27895 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs32), |
| 27896 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27897 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27898 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27900 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27901 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27902 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27903 | GIR_RootConstrainSelectedInstOperands, |
| 27904 | // GIR_Coverage, 3993, |
| 27905 | GIR_EraseRootFromParent_Done, |
| 27906 | // Label 1511: @75718 |
| 27907 | GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(75809), // Rule ID 3995 // |
| 27908 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27909 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27910 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27911 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27912 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27913 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27914 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27916 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27917 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27918 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27919 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27920 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27921 | // (intrinsic_wo_chain:{ *:[v16i8] } 3367:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 27922 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27923 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27924 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27925 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu8), |
| 27926 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27927 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27928 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27930 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27931 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27932 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27933 | GIR_RootConstrainSelectedInstOperands, |
| 27934 | // GIR_Coverage, 3995, |
| 27935 | GIR_EraseRootFromParent_Done, |
| 27936 | // Label 1512: @75809 |
| 27937 | GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(75900), // Rule ID 3997 // |
| 27938 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27939 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27940 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27941 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27942 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27943 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27944 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27946 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27947 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27948 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27949 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27950 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27951 | // (intrinsic_wo_chain:{ *:[v8i16] } 3367:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 27952 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27953 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27954 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu16), |
| 27956 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27957 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27958 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27960 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27961 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27962 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27963 | GIR_RootConstrainSelectedInstOperands, |
| 27964 | // GIR_Coverage, 3997, |
| 27965 | GIR_EraseRootFromParent_Done, |
| 27966 | // Label 1513: @75900 |
| 27967 | GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(75991), // Rule ID 3999 // |
| 27968 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27969 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27970 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27971 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27972 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27973 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27974 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27976 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27977 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27978 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27979 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27980 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27981 | // (intrinsic_wo_chain:{ *:[v4i32] } 3367:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 27982 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27983 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27984 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 27985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu32), |
| 27986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27987 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27988 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27990 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27991 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27992 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27993 | GIR_RootConstrainSelectedInstOperands, |
| 27994 | // GIR_Coverage, 3999, |
| 27995 | GIR_EraseRootFromParent_Done, |
| 27996 | // Label 1514: @75991 |
| 27997 | GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(76069), // Rule ID 4604 // |
| 27998 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 27999 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28000 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28001 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28002 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28003 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28004 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28006 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28007 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28008 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28009 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28010 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28011 | // (intrinsic_wo_chain:{ *:[v8i16] } 3337:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 28012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32bh), |
| 28013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28014 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28015 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28017 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28018 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28019 | GIR_RootConstrainSelectedInstOperands, |
| 28020 | // GIR_Coverage, 4604, |
| 28021 | GIR_EraseRootFromParent_Done, |
| 28022 | // Label 1515: @76069 |
| 28023 | GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(76147), // Rule ID 4606 // |
| 28024 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28025 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28026 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28027 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28028 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28029 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28030 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28031 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28032 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28033 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28034 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28035 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28036 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28037 | // (intrinsic_wo_chain:{ *:[v8i16] } 3337:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 28038 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32th), |
| 28039 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28040 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28041 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28043 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28044 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28045 | GIR_RootConstrainSelectedInstOperands, |
| 28046 | // GIR_Coverage, 4606, |
| 28047 | GIR_EraseRootFromParent_Done, |
| 28048 | // Label 1516: @76147 |
| 28049 | GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(76225), // Rule ID 4608 // |
| 28050 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28051 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28052 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28053 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28054 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28055 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28056 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28057 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28058 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28059 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28060 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28061 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28062 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28063 | // (intrinsic_wo_chain:{ *:[v16i8] } 3337:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 28064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16bh), |
| 28065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28066 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28067 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28069 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28070 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28071 | GIR_RootConstrainSelectedInstOperands, |
| 28072 | // GIR_Coverage, 4608, |
| 28073 | GIR_EraseRootFromParent_Done, |
| 28074 | // Label 1517: @76225 |
| 28075 | GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(76303), // Rule ID 4610 // |
| 28076 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28077 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28078 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28079 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28080 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28081 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28082 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28083 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28084 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28085 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28086 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28087 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28088 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28089 | // (intrinsic_wo_chain:{ *:[v16i8] } 3337:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 28090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16th), |
| 28091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28092 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28093 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28095 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28096 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28097 | GIR_RootConstrainSelectedInstOperands, |
| 28098 | // GIR_Coverage, 4610, |
| 28099 | GIR_EraseRootFromParent_Done, |
| 28100 | // Label 1518: @76303 |
| 28101 | GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(76381), // Rule ID 4612 // |
| 28102 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28103 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28104 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28105 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28106 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28107 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28108 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28109 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28110 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28111 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28112 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28113 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28114 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28115 | // (intrinsic_wo_chain:{ *:[v8i16] } 3337:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 28116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32bh), |
| 28117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28118 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28119 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28121 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28122 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28123 | GIR_RootConstrainSelectedInstOperands, |
| 28124 | // GIR_Coverage, 4612, |
| 28125 | GIR_EraseRootFromParent_Done, |
| 28126 | // Label 1519: @76381 |
| 28127 | GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(76459), // Rule ID 4614 // |
| 28128 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28129 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28130 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28131 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28132 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28133 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28134 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28135 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28136 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28137 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28138 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28139 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28140 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28141 | // (intrinsic_wo_chain:{ *:[v8i16] } 3337:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 28142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32th), |
| 28143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28144 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28145 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28147 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28148 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28149 | GIR_RootConstrainSelectedInstOperands, |
| 28150 | // GIR_Coverage, 4614, |
| 28151 | GIR_EraseRootFromParent_Done, |
| 28152 | // Label 1520: @76459 |
| 28153 | GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(76537), // Rule ID 4616 // |
| 28154 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28155 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28156 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28157 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28158 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28159 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28160 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28161 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28162 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28163 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28164 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28165 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28166 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28167 | // (intrinsic_wo_chain:{ *:[v16i8] } 3337:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 28168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16bh), |
| 28169 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28170 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28171 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28173 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28174 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28175 | GIR_RootConstrainSelectedInstOperands, |
| 28176 | // GIR_Coverage, 4616, |
| 28177 | GIR_EraseRootFromParent_Done, |
| 28178 | // Label 1521: @76537 |
| 28179 | GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(76615), // Rule ID 4618 // |
| 28180 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28181 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28182 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28183 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28184 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28185 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28186 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28188 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28189 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28190 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28191 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28192 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28193 | // (intrinsic_wo_chain:{ *:[v16i8] } 3337:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 28194 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16th), |
| 28195 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28196 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28197 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28199 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28200 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28201 | GIR_RootConstrainSelectedInstOperands, |
| 28202 | // GIR_Coverage, 4618, |
| 28203 | GIR_EraseRootFromParent_Done, |
| 28204 | // Label 1522: @76615 |
| 28205 | GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(76693), // Rule ID 4620 // |
| 28206 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28207 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28208 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28209 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28210 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28211 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28212 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28213 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28214 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28215 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28216 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28217 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28218 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28219 | // (intrinsic_wo_chain:{ *:[v8i16] } 3337:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 28220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32bh), |
| 28221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28222 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28223 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28225 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28226 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28227 | GIR_RootConstrainSelectedInstOperands, |
| 28228 | // GIR_Coverage, 4620, |
| 28229 | GIR_EraseRootFromParent_Done, |
| 28230 | // Label 1523: @76693 |
| 28231 | GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(76771), // Rule ID 4622 // |
| 28232 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28233 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28234 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28235 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28236 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28237 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28238 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28240 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28241 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28242 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28243 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28244 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28245 | // (intrinsic_wo_chain:{ *:[v8i16] } 3337:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 28246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32th), |
| 28247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28248 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28249 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28251 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28252 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28253 | GIR_RootConstrainSelectedInstOperands, |
| 28254 | // GIR_Coverage, 4622, |
| 28255 | GIR_EraseRootFromParent_Done, |
| 28256 | // Label 1524: @76771 |
| 28257 | GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(76849), // Rule ID 4624 // |
| 28258 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28259 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28260 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28261 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28262 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28263 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28264 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28265 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28266 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28267 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28268 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28269 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28270 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28271 | // (intrinsic_wo_chain:{ *:[v16i8] } 3337:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 28272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16bh), |
| 28273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28274 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28275 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28277 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28278 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28279 | GIR_RootConstrainSelectedInstOperands, |
| 28280 | // GIR_Coverage, 4624, |
| 28281 | GIR_EraseRootFromParent_Done, |
| 28282 | // Label 1525: @76849 |
| 28283 | GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(76927), // Rule ID 4626 // |
| 28284 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28285 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28286 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28287 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28288 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28289 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28290 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28291 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28292 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28293 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28294 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28295 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28296 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28297 | // (intrinsic_wo_chain:{ *:[v16i8] } 3337:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 28298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16th), |
| 28299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28300 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28301 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28303 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28304 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28305 | GIR_RootConstrainSelectedInstOperands, |
| 28306 | // GIR_Coverage, 4626, |
| 28307 | GIR_EraseRootFromParent_Done, |
| 28308 | // Label 1526: @76927 |
| 28309 | GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(77005), // Rule ID 4816 // |
| 28310 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28311 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28312 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28313 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28314 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28315 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28316 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28318 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28319 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28320 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28321 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28322 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28323 | // (intrinsic_wo_chain:{ *:[v16i8] } 3365:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs8), |
| 28325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28326 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28327 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28329 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28330 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28331 | GIR_RootConstrainSelectedInstOperands, |
| 28332 | // GIR_Coverage, 4816, |
| 28333 | GIR_EraseRootFromParent_Done, |
| 28334 | // Label 1527: @77005 |
| 28335 | GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(77083), // Rule ID 4818 // |
| 28336 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28337 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28338 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28339 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28340 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28341 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28342 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28343 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28344 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28345 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28346 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28347 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28348 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28349 | // (intrinsic_wo_chain:{ *:[v8i16] } 3365:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs16), |
| 28351 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28352 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28353 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28355 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28356 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28357 | GIR_RootConstrainSelectedInstOperands, |
| 28358 | // GIR_Coverage, 4818, |
| 28359 | GIR_EraseRootFromParent_Done, |
| 28360 | // Label 1528: @77083 |
| 28361 | GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(77161), // Rule ID 4820 // |
| 28362 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28363 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28364 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28365 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28366 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28367 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28368 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28369 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28370 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28371 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28372 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28373 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28374 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28375 | // (intrinsic_wo_chain:{ *:[v4i32] } 3365:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs32), |
| 28377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28378 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28379 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28381 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28382 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28383 | GIR_RootConstrainSelectedInstOperands, |
| 28384 | // GIR_Coverage, 4820, |
| 28385 | GIR_EraseRootFromParent_Done, |
| 28386 | // Label 1529: @77161 |
| 28387 | GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(77239), // Rule ID 4822 // |
| 28388 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28389 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28390 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28391 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28392 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28393 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28394 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28395 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28396 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28397 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28398 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28399 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28400 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28401 | // (intrinsic_wo_chain:{ *:[v16i8] } 3365:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru8), |
| 28403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28404 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28405 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28407 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28408 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28409 | GIR_RootConstrainSelectedInstOperands, |
| 28410 | // GIR_Coverage, 4822, |
| 28411 | GIR_EraseRootFromParent_Done, |
| 28412 | // Label 1530: @77239 |
| 28413 | GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(77317), // Rule ID 4824 // |
| 28414 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28415 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28416 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28417 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28418 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28419 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28420 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28421 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28422 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28423 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28424 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28425 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28426 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28427 | // (intrinsic_wo_chain:{ *:[v8i16] } 3365:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru16), |
| 28429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28430 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28431 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28433 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28434 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28435 | GIR_RootConstrainSelectedInstOperands, |
| 28436 | // GIR_Coverage, 4824, |
| 28437 | GIR_EraseRootFromParent_Done, |
| 28438 | // Label 1531: @77317 |
| 28439 | GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(77395), // Rule ID 4826 // |
| 28440 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28441 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28442 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28443 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28444 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28445 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28446 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28448 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28449 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28450 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28451 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28452 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28453 | // (intrinsic_wo_chain:{ *:[v4i32] } 3365:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru32), |
| 28455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28456 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28457 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28458 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28459 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28460 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28461 | GIR_RootConstrainSelectedInstOperands, |
| 28462 | // GIR_Coverage, 4826, |
| 28463 | GIR_EraseRootFromParent_Done, |
| 28464 | // Label 1532: @77395 |
| 28465 | GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(77473), // Rule ID 4828 // |
| 28466 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28467 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28468 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28469 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28470 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28471 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28472 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28473 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28474 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28475 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28476 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28477 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28478 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28479 | // (intrinsic_wo_chain:{ *:[v16i8] } 3365:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs8), |
| 28481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28482 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28483 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28485 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28486 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28487 | GIR_RootConstrainSelectedInstOperands, |
| 28488 | // GIR_Coverage, 4828, |
| 28489 | GIR_EraseRootFromParent_Done, |
| 28490 | // Label 1533: @77473 |
| 28491 | GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(77551), // Rule ID 4830 // |
| 28492 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28493 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28494 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28495 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28496 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28497 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28498 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28499 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28500 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28501 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28502 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28503 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28504 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28505 | // (intrinsic_wo_chain:{ *:[v8i16] } 3365:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs16), |
| 28507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28508 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28509 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28511 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28512 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28513 | GIR_RootConstrainSelectedInstOperands, |
| 28514 | // GIR_Coverage, 4830, |
| 28515 | GIR_EraseRootFromParent_Done, |
| 28516 | // Label 1534: @77551 |
| 28517 | GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(77629), // Rule ID 4832 // |
| 28518 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28519 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28520 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28521 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28522 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28523 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28524 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28525 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28526 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28527 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28528 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28529 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28530 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28531 | // (intrinsic_wo_chain:{ *:[v4i32] } 3365:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs32), |
| 28533 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28534 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28535 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28537 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28538 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28539 | GIR_RootConstrainSelectedInstOperands, |
| 28540 | // GIR_Coverage, 4832, |
| 28541 | GIR_EraseRootFromParent_Done, |
| 28542 | // Label 1535: @77629 |
| 28543 | GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(77707), // Rule ID 4834 // |
| 28544 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28545 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28546 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28547 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28548 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28549 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28550 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28552 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28553 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28554 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28555 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28556 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28557 | // (intrinsic_wo_chain:{ *:[v16i8] } 3365:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru8), |
| 28559 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28560 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28561 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28563 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28564 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28565 | GIR_RootConstrainSelectedInstOperands, |
| 28566 | // GIR_Coverage, 4834, |
| 28567 | GIR_EraseRootFromParent_Done, |
| 28568 | // Label 1536: @77707 |
| 28569 | GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(77785), // Rule ID 4836 // |
| 28570 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28571 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28572 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28573 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28574 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28575 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28576 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28578 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28579 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28580 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28581 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28582 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28583 | // (intrinsic_wo_chain:{ *:[v8i16] } 3365:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru16), |
| 28585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28586 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28587 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28589 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28590 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28591 | GIR_RootConstrainSelectedInstOperands, |
| 28592 | // GIR_Coverage, 4836, |
| 28593 | GIR_EraseRootFromParent_Done, |
| 28594 | // Label 1537: @77785 |
| 28595 | GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(77863), // Rule ID 4838 // |
| 28596 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28597 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28598 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28599 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28600 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28601 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28602 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28603 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28604 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28605 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28606 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28607 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28608 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28609 | // (intrinsic_wo_chain:{ *:[v4i32] } 3365:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru32), |
| 28611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28612 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28613 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28615 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28616 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28617 | GIR_RootConstrainSelectedInstOperands, |
| 28618 | // GIR_Coverage, 4838, |
| 28619 | GIR_EraseRootFromParent_Done, |
| 28620 | // Label 1538: @77863 |
| 28621 | GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(77941), // Rule ID 4840 // |
| 28622 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28623 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28624 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28625 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28626 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28627 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28628 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28629 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28630 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28631 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28632 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28633 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28634 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28635 | // (intrinsic_wo_chain:{ *:[v16i8] } 3365:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs8), |
| 28637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28638 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28639 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28641 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28642 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28643 | GIR_RootConstrainSelectedInstOperands, |
| 28644 | // GIR_Coverage, 4840, |
| 28645 | GIR_EraseRootFromParent_Done, |
| 28646 | // Label 1539: @77941 |
| 28647 | GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(78019), // Rule ID 4842 // |
| 28648 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28649 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28650 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28651 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28652 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28653 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28654 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28655 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28656 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28657 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28658 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28659 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28660 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28661 | // (intrinsic_wo_chain:{ *:[v8i16] } 3365:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28662 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs16), |
| 28663 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28664 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28665 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28667 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28668 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28669 | GIR_RootConstrainSelectedInstOperands, |
| 28670 | // GIR_Coverage, 4842, |
| 28671 | GIR_EraseRootFromParent_Done, |
| 28672 | // Label 1540: @78019 |
| 28673 | GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(78097), // Rule ID 4844 // |
| 28674 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28675 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28676 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28677 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28678 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28679 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28680 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28681 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28682 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28683 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28684 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28685 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28686 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28687 | // (intrinsic_wo_chain:{ *:[v4i32] } 3365:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs32), |
| 28689 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28690 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28691 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28693 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28694 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28695 | GIR_RootConstrainSelectedInstOperands, |
| 28696 | // GIR_Coverage, 4844, |
| 28697 | GIR_EraseRootFromParent_Done, |
| 28698 | // Label 1541: @78097 |
| 28699 | GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(78175), // Rule ID 4846 // |
| 28700 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28701 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28702 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28703 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28704 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28705 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28706 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28707 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28708 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28709 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28710 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28711 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28712 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28713 | // (intrinsic_wo_chain:{ *:[v16i8] } 3365:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru8), |
| 28715 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28716 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28717 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28719 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28720 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28721 | GIR_RootConstrainSelectedInstOperands, |
| 28722 | // GIR_Coverage, 4846, |
| 28723 | GIR_EraseRootFromParent_Done, |
| 28724 | // Label 1542: @78175 |
| 28725 | GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(78253), // Rule ID 4848 // |
| 28726 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28727 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28728 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28729 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28730 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28731 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28732 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28733 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28734 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28735 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28736 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28737 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28738 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28739 | // (intrinsic_wo_chain:{ *:[v8i16] } 3365:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru16), |
| 28741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28742 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28743 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28745 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28746 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28747 | GIR_RootConstrainSelectedInstOperands, |
| 28748 | // GIR_Coverage, 4848, |
| 28749 | GIR_EraseRootFromParent_Done, |
| 28750 | // Label 1543: @78253 |
| 28751 | GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(78331), // Rule ID 4850 // |
| 28752 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28753 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28754 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28755 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28756 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28757 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28758 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28759 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28760 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28761 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28762 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28763 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28764 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28765 | // (intrinsic_wo_chain:{ *:[v4i32] } 3365:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru32), |
| 28767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28768 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28769 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28771 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28772 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28773 | GIR_RootConstrainSelectedInstOperands, |
| 28774 | // GIR_Coverage, 4850, |
| 28775 | GIR_EraseRootFromParent_Done, |
| 28776 | // Label 1544: @78331 |
| 28777 | GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(78409), // Rule ID 4852 // |
| 28778 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28779 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28780 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28781 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28782 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28783 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28784 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28786 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28787 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28788 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28789 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28790 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28791 | // (intrinsic_wo_chain:{ *:[v16i8] } 3365:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs8), |
| 28793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28794 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28795 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28797 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28798 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28799 | GIR_RootConstrainSelectedInstOperands, |
| 28800 | // GIR_Coverage, 4852, |
| 28801 | GIR_EraseRootFromParent_Done, |
| 28802 | // Label 1545: @78409 |
| 28803 | GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(78487), // Rule ID 4854 // |
| 28804 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28805 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28806 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28807 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28808 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28809 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28810 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28811 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28812 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28813 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28814 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28815 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28816 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28817 | // (intrinsic_wo_chain:{ *:[v8i16] } 3365:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs16), |
| 28819 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28820 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28821 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28823 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28824 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28825 | GIR_RootConstrainSelectedInstOperands, |
| 28826 | // GIR_Coverage, 4854, |
| 28827 | GIR_EraseRootFromParent_Done, |
| 28828 | // Label 1546: @78487 |
| 28829 | GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(78565), // Rule ID 4856 // |
| 28830 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28831 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28832 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28833 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28834 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28835 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28836 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28837 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28838 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28839 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28840 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28841 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28842 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28843 | // (intrinsic_wo_chain:{ *:[v4i32] } 3365:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs32), |
| 28845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28846 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28847 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28849 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28850 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28851 | GIR_RootConstrainSelectedInstOperands, |
| 28852 | // GIR_Coverage, 4856, |
| 28853 | GIR_EraseRootFromParent_Done, |
| 28854 | // Label 1547: @78565 |
| 28855 | GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(78643), // Rule ID 4858 // |
| 28856 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28857 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28858 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28859 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28860 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28861 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28862 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28864 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28865 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28866 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28867 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28868 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28869 | // (intrinsic_wo_chain:{ *:[v16i8] } 3365:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28870 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru8), |
| 28871 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28872 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28873 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28875 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28876 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28877 | GIR_RootConstrainSelectedInstOperands, |
| 28878 | // GIR_Coverage, 4858, |
| 28879 | GIR_EraseRootFromParent_Done, |
| 28880 | // Label 1548: @78643 |
| 28881 | GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(78721), // Rule ID 4860 // |
| 28882 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28883 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28884 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28885 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28886 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28887 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28888 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28889 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28890 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28891 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28892 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28893 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28894 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28895 | // (intrinsic_wo_chain:{ *:[v8i16] } 3365:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru16), |
| 28897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28898 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28899 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28901 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28902 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28903 | GIR_RootConstrainSelectedInstOperands, |
| 28904 | // GIR_Coverage, 4860, |
| 28905 | GIR_EraseRootFromParent_Done, |
| 28906 | // Label 1549: @78721 |
| 28907 | GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(78799), // Rule ID 4862 // |
| 28908 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28909 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28910 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28911 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28912 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28913 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28914 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28916 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28917 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28918 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28919 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28920 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28921 | // (intrinsic_wo_chain:{ *:[v4i32] } 3365:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru32), |
| 28923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28924 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28925 | GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28927 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28928 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28929 | GIR_RootConstrainSelectedInstOperands, |
| 28930 | // GIR_Coverage, 4862, |
| 28931 | GIR_EraseRootFromParent_Done, |
| 28932 | // Label 1550: @78799 |
| 28933 | GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(78935), // Rule ID 2708 // |
| 28934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 28935 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx3), |
| 28936 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 28937 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 28938 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 28939 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 28940 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 28941 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 28942 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28943 | // (intrinsic_wo_chain:{ *:[v8i8] } 3529:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 28944 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 28945 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8, |
| 28946 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28947 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28948 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 28949 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 28950 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28951 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 28952 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 28953 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 28954 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 28955 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2 |
| 28956 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 28957 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 28958 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 28959 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 28960 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 28961 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 28962 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 28963 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 28964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX3Pseudo), |
| 28965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 28966 | GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 28967 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28968 | GIR_RootToRootCopy, /*OpIdx*/6, // Vm |
| 28969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 28970 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28971 | GIR_RootConstrainSelectedInstOperands, |
| 28972 | // GIR_Coverage, 2708, |
| 28973 | GIR_EraseRootFromParent_Done, |
| 28974 | // Label 1551: @78935 |
| 28975 | GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(79056), // Rule ID 2709 // |
| 28976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 28977 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl4), |
| 28978 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 28979 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 28980 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 28981 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 28982 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 28983 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 28984 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 28985 | // (intrinsic_wo_chain:{ *:[v8i8] } 3526:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 28986 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 28987 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 28988 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28989 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0 |
| 28990 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 28991 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1 |
| 28992 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 28993 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2 |
| 28994 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 28995 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3 |
| 28996 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 28997 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 28998 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 28999 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 29000 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 29001 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 29002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL4Pseudo), |
| 29003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 29004 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29005 | GIR_RootToRootCopy, /*OpIdx*/6, // Vm |
| 29006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 29007 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29008 | GIR_RootConstrainSelectedInstOperands, |
| 29009 | // GIR_Coverage, 2709, |
| 29010 | GIR_EraseRootFromParent_Done, |
| 29011 | // Label 1552: @79056 |
| 29012 | GIM_Reject, |
| 29013 | // Label 1490: @79057 |
| 29014 | GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(83950), |
| 29015 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/8, |
| 29016 | GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(79153), // Rule ID 3278 // |
| 29017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29018 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29019 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29020 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29021 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29022 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29023 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29024 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29025 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29027 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29028 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29029 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29030 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29031 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29032 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29033 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs8), |
| 29035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29036 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29037 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29039 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29040 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29041 | GIR_RootConstrainSelectedInstOperands, |
| 29042 | // GIR_Coverage, 3278, |
| 29043 | GIR_EraseRootFromParent_Done, |
| 29044 | // Label 1554: @79153 |
| 29045 | GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(79241), // Rule ID 3282 // |
| 29046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29047 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29048 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29049 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29050 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29051 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29052 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29053 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29054 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29056 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29057 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29058 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29059 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29060 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29061 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29062 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29063 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs8), |
| 29064 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29065 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29066 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29068 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29069 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29070 | GIR_RootConstrainSelectedInstOperands, |
| 29071 | // GIR_Coverage, 3282, |
| 29072 | GIR_EraseRootFromParent_Done, |
| 29073 | // Label 1555: @79241 |
| 29074 | GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(79329), // Rule ID 3286 // |
| 29075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29076 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29077 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29078 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29079 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29080 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29081 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29082 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29083 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29085 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29086 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29087 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29088 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29089 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29090 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29091 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8), |
| 29093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29094 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29095 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29097 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29098 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29099 | GIR_RootConstrainSelectedInstOperands, |
| 29100 | // GIR_Coverage, 3286, |
| 29101 | GIR_EraseRootFromParent_Done, |
| 29102 | // Label 1556: @79329 |
| 29103 | GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(79417), // Rule ID 3290 // |
| 29104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29105 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29106 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29107 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29108 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29109 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29110 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29111 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29112 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29113 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29114 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29115 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29116 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29117 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29118 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29119 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29120 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29121 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs16), |
| 29122 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29123 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29124 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29126 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29127 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29128 | GIR_RootConstrainSelectedInstOperands, |
| 29129 | // GIR_Coverage, 3290, |
| 29130 | GIR_EraseRootFromParent_Done, |
| 29131 | // Label 1557: @79417 |
| 29132 | GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(79505), // Rule ID 3294 // |
| 29133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29134 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29135 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29136 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29137 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29138 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29139 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29140 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29141 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29143 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29144 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29145 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29146 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29147 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29148 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29149 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs16), |
| 29151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29152 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29153 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29155 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29156 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29157 | GIR_RootConstrainSelectedInstOperands, |
| 29158 | // GIR_Coverage, 3294, |
| 29159 | GIR_EraseRootFromParent_Done, |
| 29160 | // Label 1558: @79505 |
| 29161 | GIM_Try, /*On fail goto*//*Label 1559*/ GIMT_Encode4(79593), // Rule ID 3298 // |
| 29162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29163 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29164 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29165 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29166 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29167 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29168 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29169 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29170 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29171 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29172 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29173 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29174 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29175 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29176 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29177 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29178 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16), |
| 29180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29181 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29182 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29184 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29185 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29186 | GIR_RootConstrainSelectedInstOperands, |
| 29187 | // GIR_Coverage, 3298, |
| 29188 | GIR_EraseRootFromParent_Done, |
| 29189 | // Label 1559: @79593 |
| 29190 | GIM_Try, /*On fail goto*//*Label 1560*/ GIMT_Encode4(79681), // Rule ID 3302 // |
| 29191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29192 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29193 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29194 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29195 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29196 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29197 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29198 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29199 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29201 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29202 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29203 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29204 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29205 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29206 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29207 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs32), |
| 29209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29210 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29211 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29213 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29214 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29215 | GIR_RootConstrainSelectedInstOperands, |
| 29216 | // GIR_Coverage, 3302, |
| 29217 | GIR_EraseRootFromParent_Done, |
| 29218 | // Label 1560: @79681 |
| 29219 | GIM_Try, /*On fail goto*//*Label 1561*/ GIMT_Encode4(79769), // Rule ID 3306 // |
| 29220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29221 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29222 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29223 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29224 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29225 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29226 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29227 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29228 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29230 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29231 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29232 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29233 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29234 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29235 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29236 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29237 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs32), |
| 29238 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29239 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29240 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29242 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29243 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29244 | GIR_RootConstrainSelectedInstOperands, |
| 29245 | // GIR_Coverage, 3306, |
| 29246 | GIR_EraseRootFromParent_Done, |
| 29247 | // Label 1561: @79769 |
| 29248 | GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(79857), // Rule ID 3310 // |
| 29249 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29250 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29251 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29252 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29253 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29254 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29255 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29256 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29257 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29259 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29260 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29261 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29262 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29263 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29264 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29265 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32), |
| 29267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29268 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29269 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29271 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29272 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29273 | GIR_RootConstrainSelectedInstOperands, |
| 29274 | // GIR_Coverage, 3310, |
| 29275 | GIR_EraseRootFromParent_Done, |
| 29276 | // Label 1562: @79857 |
| 29277 | GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(79945), // Rule ID 3314 // |
| 29278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29279 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29280 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29281 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29282 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29283 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29284 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29285 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29286 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29287 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29288 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29289 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29290 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29291 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29292 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29293 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29294 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs8), |
| 29296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29297 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29298 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29300 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29301 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29302 | GIR_RootConstrainSelectedInstOperands, |
| 29303 | // GIR_Coverage, 3314, |
| 29304 | GIR_EraseRootFromParent_Done, |
| 29305 | // Label 1563: @79945 |
| 29306 | GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(80033), // Rule ID 3318 // |
| 29307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29308 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29309 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29310 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29311 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29312 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29313 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29314 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29315 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29317 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29318 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29319 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29320 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29321 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29322 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29323 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs8), |
| 29325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29326 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29327 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29329 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29330 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29331 | GIR_RootConstrainSelectedInstOperands, |
| 29332 | // GIR_Coverage, 3318, |
| 29333 | GIR_EraseRootFromParent_Done, |
| 29334 | // Label 1564: @80033 |
| 29335 | GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(80121), // Rule ID 3322 // |
| 29336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29337 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29338 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29339 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29340 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29341 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29342 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29343 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29344 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29345 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29346 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29347 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29348 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29349 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29350 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29351 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29352 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs16), |
| 29354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29355 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29356 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29358 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29359 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29360 | GIR_RootConstrainSelectedInstOperands, |
| 29361 | // GIR_Coverage, 3322, |
| 29362 | GIR_EraseRootFromParent_Done, |
| 29363 | // Label 1565: @80121 |
| 29364 | GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(80209), // Rule ID 3326 // |
| 29365 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29366 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29367 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29368 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29369 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29370 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29371 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29372 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29373 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29375 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29376 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29377 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29378 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29379 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29380 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29381 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs16), |
| 29383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29384 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29385 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29387 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29388 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29389 | GIR_RootConstrainSelectedInstOperands, |
| 29390 | // GIR_Coverage, 3326, |
| 29391 | GIR_EraseRootFromParent_Done, |
| 29392 | // Label 1566: @80209 |
| 29393 | GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(80297), // Rule ID 3330 // |
| 29394 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29395 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29396 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29397 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29398 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29399 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29400 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29401 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29402 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29404 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29405 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29406 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29407 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29408 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29409 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29410 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs32), |
| 29412 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29413 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29414 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29416 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29417 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29418 | GIR_RootConstrainSelectedInstOperands, |
| 29419 | // GIR_Coverage, 3330, |
| 29420 | GIR_EraseRootFromParent_Done, |
| 29421 | // Label 1567: @80297 |
| 29422 | GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(80385), // Rule ID 3334 // |
| 29423 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29424 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29425 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29426 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29427 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29428 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29429 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29430 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29431 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29432 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29433 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29434 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29435 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29436 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29437 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29438 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29439 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs32), |
| 29441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29442 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29443 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29445 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29446 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29447 | GIR_RootConstrainSelectedInstOperands, |
| 29448 | // GIR_Coverage, 3334, |
| 29449 | GIR_EraseRootFromParent_Done, |
| 29450 | // Label 1568: @80385 |
| 29451 | GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(80475), // Rule ID 3280 // |
| 29452 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29453 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29454 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29455 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29456 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29457 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29458 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29459 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29460 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29461 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29462 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29463 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29464 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29465 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29466 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29467 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29468 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29469 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas8), |
| 29470 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29471 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29472 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29473 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29475 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29476 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29477 | GIR_RootConstrainSelectedInstOperands, |
| 29478 | // GIR_Coverage, 3280, |
| 29479 | GIR_EraseRootFromParent_Done, |
| 29480 | // Label 1569: @80475 |
| 29481 | GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(80565), // Rule ID 3284 // |
| 29482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29483 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29484 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29485 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29486 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29487 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29488 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29489 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29490 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29491 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29492 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29493 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29494 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29495 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29496 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29497 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29498 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs8), |
| 29500 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29501 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29502 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29503 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29505 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29506 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29507 | GIR_RootConstrainSelectedInstOperands, |
| 29508 | // GIR_Coverage, 3284, |
| 29509 | GIR_EraseRootFromParent_Done, |
| 29510 | // Label 1570: @80565 |
| 29511 | GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(80655), // Rule ID 3288 // |
| 29512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29513 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29514 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29515 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29516 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29517 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29518 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29519 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29520 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29522 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29523 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29524 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29525 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29526 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29527 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29528 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8), |
| 29530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29531 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29532 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29533 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29535 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29536 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29537 | GIR_RootConstrainSelectedInstOperands, |
| 29538 | // GIR_Coverage, 3288, |
| 29539 | GIR_EraseRootFromParent_Done, |
| 29540 | // Label 1571: @80655 |
| 29541 | GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(80745), // Rule ID 3292 // |
| 29542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29543 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29544 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29545 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29546 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29547 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29548 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29549 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29550 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29552 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29553 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29554 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29555 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29556 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29557 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29558 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas16), |
| 29560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29561 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29562 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29563 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29565 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29566 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29567 | GIR_RootConstrainSelectedInstOperands, |
| 29568 | // GIR_Coverage, 3292, |
| 29569 | GIR_EraseRootFromParent_Done, |
| 29570 | // Label 1572: @80745 |
| 29571 | GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(80835), // Rule ID 3296 // |
| 29572 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29573 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29574 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29575 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29576 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29577 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29578 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29579 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29580 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29581 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29582 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29583 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29584 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29585 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29586 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29587 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29588 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs16), |
| 29590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29591 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29592 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29593 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29595 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29596 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29597 | GIR_RootConstrainSelectedInstOperands, |
| 29598 | // GIR_Coverage, 3296, |
| 29599 | GIR_EraseRootFromParent_Done, |
| 29600 | // Label 1573: @80835 |
| 29601 | GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(80925), // Rule ID 3300 // |
| 29602 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29603 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29604 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29605 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29606 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29607 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29608 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29609 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29610 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29611 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29612 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29613 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29614 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29615 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29616 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29617 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29618 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29619 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16), |
| 29620 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29621 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29622 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29623 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29625 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29626 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29627 | GIR_RootConstrainSelectedInstOperands, |
| 29628 | // GIR_Coverage, 3300, |
| 29629 | GIR_EraseRootFromParent_Done, |
| 29630 | // Label 1574: @80925 |
| 29631 | GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(81015), // Rule ID 3304 // |
| 29632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29633 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29634 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29635 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29636 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29637 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29638 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29639 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29640 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29641 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29642 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29643 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29644 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29645 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29646 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29647 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29648 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas32), |
| 29650 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29651 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29652 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29653 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29655 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29656 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29657 | GIR_RootConstrainSelectedInstOperands, |
| 29658 | // GIR_Coverage, 3304, |
| 29659 | GIR_EraseRootFromParent_Done, |
| 29660 | // Label 1575: @81015 |
| 29661 | GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(81105), // Rule ID 3308 // |
| 29662 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29663 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29664 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29665 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29666 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29667 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29668 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29669 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29670 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29672 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29673 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29674 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29675 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29676 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29677 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29678 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs32), |
| 29680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29681 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29682 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29683 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29685 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29686 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29687 | GIR_RootConstrainSelectedInstOperands, |
| 29688 | // GIR_Coverage, 3308, |
| 29689 | GIR_EraseRootFromParent_Done, |
| 29690 | // Label 1576: @81105 |
| 29691 | GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(81195), // Rule ID 3312 // |
| 29692 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29693 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29694 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29695 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29696 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29697 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29698 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29699 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29700 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29701 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29702 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29703 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29704 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29705 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29706 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29707 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29708 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29709 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32), |
| 29710 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29711 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29712 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29713 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29715 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29716 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29717 | GIR_RootConstrainSelectedInstOperands, |
| 29718 | // GIR_Coverage, 3312, |
| 29719 | GIR_EraseRootFromParent_Done, |
| 29720 | // Label 1577: @81195 |
| 29721 | GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(81285), // Rule ID 3316 // |
| 29722 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29723 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29724 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29725 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29726 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29727 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29728 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29729 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29730 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29731 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29732 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29733 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29734 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29735 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29736 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29737 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29738 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas8), |
| 29740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29741 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29742 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29743 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29745 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29746 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29747 | GIR_RootConstrainSelectedInstOperands, |
| 29748 | // GIR_Coverage, 3316, |
| 29749 | GIR_EraseRootFromParent_Done, |
| 29750 | // Label 1578: @81285 |
| 29751 | GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(81375), // Rule ID 3320 // |
| 29752 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29753 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29754 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29755 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29756 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29757 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29758 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29759 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29760 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29762 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29763 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29764 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29765 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29766 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29767 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29768 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs8), |
| 29770 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29771 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29772 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29773 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29775 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29776 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29777 | GIR_RootConstrainSelectedInstOperands, |
| 29778 | // GIR_Coverage, 3320, |
| 29779 | GIR_EraseRootFromParent_Done, |
| 29780 | // Label 1579: @81375 |
| 29781 | GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(81465), // Rule ID 3324 // |
| 29782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29783 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29784 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29785 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29786 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29787 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29788 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29789 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29790 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29792 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29793 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29794 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29795 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29796 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29797 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29798 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas16), |
| 29800 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29801 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29802 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29803 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29805 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29806 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29807 | GIR_RootConstrainSelectedInstOperands, |
| 29808 | // GIR_Coverage, 3324, |
| 29809 | GIR_EraseRootFromParent_Done, |
| 29810 | // Label 1580: @81465 |
| 29811 | GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(81555), // Rule ID 3328 // |
| 29812 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29813 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29814 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29815 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29816 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29817 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29818 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29819 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29820 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29821 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29822 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29823 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29824 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29825 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29826 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29827 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29828 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs16), |
| 29830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29831 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29832 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29833 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29835 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29836 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29837 | GIR_RootConstrainSelectedInstOperands, |
| 29838 | // GIR_Coverage, 3328, |
| 29839 | GIR_EraseRootFromParent_Done, |
| 29840 | // Label 1581: @81555 |
| 29841 | GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(81645), // Rule ID 3332 // |
| 29842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29843 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29844 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29845 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29846 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29847 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29848 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29849 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29850 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29852 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29853 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29854 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29855 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29856 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29857 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29858 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas32), |
| 29860 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29861 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29862 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29863 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29865 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29866 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29867 | GIR_RootConstrainSelectedInstOperands, |
| 29868 | // GIR_Coverage, 3332, |
| 29869 | GIR_EraseRootFromParent_Done, |
| 29870 | // Label 1582: @81645 |
| 29871 | GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(81735), // Rule ID 3336 // |
| 29872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29873 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29874 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29875 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29876 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29877 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29878 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29879 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29880 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29881 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29882 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29883 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29884 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29885 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29886 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29887 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29888 | // (intrinsic_wo_chain:{ *:[i32] } 3319:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29889 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs32), |
| 29890 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29891 | GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29892 | GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29893 | GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29895 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29896 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29897 | GIR_RootConstrainSelectedInstOperands, |
| 29898 | // GIR_Coverage, 3336, |
| 29899 | GIR_EraseRootFromParent_Done, |
| 29900 | // Label 1583: @81735 |
| 29901 | GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(81822), // Rule ID 4450 // |
| 29902 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 29903 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 29904 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29905 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 29906 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 29907 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29908 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29909 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 29910 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29911 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29912 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29913 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29914 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29915 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29916 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 29917 | // (intrinsic_wo_chain:{ *:[v16i8] } 3328:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 29918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs8), |
| 29919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29920 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 29921 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 29922 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 29923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29924 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29925 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29926 | GIR_RootConstrainSelectedInstOperands, |
| 29927 | // GIR_Coverage, 4450, |
| 29928 | GIR_EraseRootFromParent_Done, |
| 29929 | // Label 1584: @81822 |
| 29930 | GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(81909), // Rule ID 4452 // |
| 29931 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 29932 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29933 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29934 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 29935 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 29936 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29937 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29938 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 29939 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29940 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29941 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29942 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29943 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29944 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29945 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 29946 | // (intrinsic_wo_chain:{ *:[v8i16] } 3328:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 29947 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs16), |
| 29948 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29949 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 29950 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 29951 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 29952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29953 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29954 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29955 | GIR_RootConstrainSelectedInstOperands, |
| 29956 | // GIR_Coverage, 4452, |
| 29957 | GIR_EraseRootFromParent_Done, |
| 29958 | // Label 1585: @81909 |
| 29959 | GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(81996), // Rule ID 4454 // |
| 29960 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 29961 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29962 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29963 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29964 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 29965 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29966 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29967 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 29968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29969 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29970 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29971 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29972 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29973 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29974 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 29975 | // (intrinsic_wo_chain:{ *:[v4i32] } 3328:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 29976 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs32), |
| 29977 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29978 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 29979 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 29980 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 29981 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29982 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29983 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29984 | GIR_RootConstrainSelectedInstOperands, |
| 29985 | // GIR_Coverage, 4454, |
| 29986 | GIR_EraseRootFromParent_Done, |
| 29987 | // Label 1586: @81996 |
| 29988 | GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(82083), // Rule ID 4456 // |
| 29989 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 29990 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 29991 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29992 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 29993 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 29994 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29995 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29996 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 29997 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29998 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29999 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30000 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30001 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30002 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30003 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30004 | // (intrinsic_wo_chain:{ *:[v16i8] } 3328:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs8), |
| 30006 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30007 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30008 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30009 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30011 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30012 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30013 | GIR_RootConstrainSelectedInstOperands, |
| 30014 | // GIR_Coverage, 4456, |
| 30015 | GIR_EraseRootFromParent_Done, |
| 30016 | // Label 1587: @82083 |
| 30017 | GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(82170), // Rule ID 4458 // |
| 30018 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30019 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30020 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30021 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30022 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30023 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30024 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30025 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30027 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30028 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30029 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30030 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30031 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30032 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30033 | // (intrinsic_wo_chain:{ *:[v8i16] } 3328:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs16), |
| 30035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30036 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30037 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30038 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30040 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30041 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30042 | GIR_RootConstrainSelectedInstOperands, |
| 30043 | // GIR_Coverage, 4458, |
| 30044 | GIR_EraseRootFromParent_Done, |
| 30045 | // Label 1588: @82170 |
| 30046 | GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(82257), // Rule ID 4460 // |
| 30047 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30048 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30049 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30050 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30051 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30052 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30053 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30054 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30056 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30057 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30058 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30059 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30060 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30061 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30062 | // (intrinsic_wo_chain:{ *:[v4i32] } 3328:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30063 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs32), |
| 30064 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30065 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30066 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30067 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30069 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30070 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30071 | GIR_RootConstrainSelectedInstOperands, |
| 30072 | // GIR_Coverage, 4460, |
| 30073 | GIR_EraseRootFromParent_Done, |
| 30074 | // Label 1589: @82257 |
| 30075 | GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(82344), // Rule ID 4462 // |
| 30076 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30077 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30078 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30079 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30080 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30081 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30082 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30083 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30085 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30086 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30087 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30088 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30089 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30090 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30091 | // (intrinsic_wo_chain:{ *:[v16i8] } 3328:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs8), |
| 30093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30094 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30095 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30096 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30098 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30099 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30100 | GIR_RootConstrainSelectedInstOperands, |
| 30101 | // GIR_Coverage, 4462, |
| 30102 | GIR_EraseRootFromParent_Done, |
| 30103 | // Label 1590: @82344 |
| 30104 | GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(82431), // Rule ID 4464 // |
| 30105 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30106 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30107 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30108 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30109 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30110 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30111 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30112 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30113 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30114 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30115 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30116 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30117 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30118 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30119 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30120 | // (intrinsic_wo_chain:{ *:[v8i16] } 3328:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30121 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs16), |
| 30122 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30123 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30124 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30125 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30127 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30128 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30129 | GIR_RootConstrainSelectedInstOperands, |
| 30130 | // GIR_Coverage, 4464, |
| 30131 | GIR_EraseRootFromParent_Done, |
| 30132 | // Label 1591: @82431 |
| 30133 | GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(82518), // Rule ID 4466 // |
| 30134 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30135 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30136 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30137 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30138 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30139 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30140 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30141 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30143 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30144 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30145 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30146 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30147 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30148 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30149 | // (intrinsic_wo_chain:{ *:[v4i32] } 3328:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs32), |
| 30151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30152 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30153 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30154 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30156 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30157 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30158 | GIR_RootConstrainSelectedInstOperands, |
| 30159 | // GIR_Coverage, 4466, |
| 30160 | GIR_EraseRootFromParent_Done, |
| 30161 | // Label 1592: @82518 |
| 30162 | GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(82605), // Rule ID 4468 // |
| 30163 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30164 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30165 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30166 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30167 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30168 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30169 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30170 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30171 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30172 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30173 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30174 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30175 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30176 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30177 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30178 | // (intrinsic_wo_chain:{ *:[v16i8] } 3328:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs8), |
| 30180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30181 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30182 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30183 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30185 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30186 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30187 | GIR_RootConstrainSelectedInstOperands, |
| 30188 | // GIR_Coverage, 4468, |
| 30189 | GIR_EraseRootFromParent_Done, |
| 30190 | // Label 1593: @82605 |
| 30191 | GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(82692), // Rule ID 4470 // |
| 30192 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30193 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30194 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30195 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30196 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30197 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30198 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30199 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30201 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30202 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30203 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30204 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30205 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30206 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30207 | // (intrinsic_wo_chain:{ *:[v8i16] } 3328:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs16), |
| 30209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30210 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30211 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30212 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30214 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30215 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30216 | GIR_RootConstrainSelectedInstOperands, |
| 30217 | // GIR_Coverage, 4470, |
| 30218 | GIR_EraseRootFromParent_Done, |
| 30219 | // Label 1594: @82692 |
| 30220 | GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(82779), // Rule ID 4472 // |
| 30221 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30222 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30223 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30224 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30225 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30226 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30227 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30228 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30230 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30231 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30232 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30233 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30234 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30235 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30236 | // (intrinsic_wo_chain:{ *:[v4i32] } 3328:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30237 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs32), |
| 30238 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30239 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30240 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30241 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30243 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30244 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30245 | GIR_RootConstrainSelectedInstOperands, |
| 30246 | // GIR_Coverage, 4472, |
| 30247 | GIR_EraseRootFromParent_Done, |
| 30248 | // Label 1595: @82779 |
| 30249 | GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(82866), // Rule ID 4474 // |
| 30250 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30251 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30252 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30253 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30254 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30255 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30256 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30257 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30259 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30260 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30261 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30262 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30263 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30264 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30265 | // (intrinsic_wo_chain:{ *:[v16i8] } 3328:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs8), |
| 30267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30268 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30269 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30270 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30272 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30273 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30274 | GIR_RootConstrainSelectedInstOperands, |
| 30275 | // GIR_Coverage, 4474, |
| 30276 | GIR_EraseRootFromParent_Done, |
| 30277 | // Label 1596: @82866 |
| 30278 | GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(82953), // Rule ID 4476 // |
| 30279 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30280 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30281 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30282 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30283 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30284 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30285 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30286 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30287 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30288 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30289 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30290 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30291 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30292 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30293 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30294 | // (intrinsic_wo_chain:{ *:[v8i16] } 3328:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs16), |
| 30296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30297 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30298 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30299 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30301 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30302 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30303 | GIR_RootConstrainSelectedInstOperands, |
| 30304 | // GIR_Coverage, 4476, |
| 30305 | GIR_EraseRootFromParent_Done, |
| 30306 | // Label 1597: @82953 |
| 30307 | GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(83040), // Rule ID 4478 // |
| 30308 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30309 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30310 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30311 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30312 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30313 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30314 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30315 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30317 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30318 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30319 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30320 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30321 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30322 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30323 | // (intrinsic_wo_chain:{ *:[v4i32] } 3328:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs32), |
| 30325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30326 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30327 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30328 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30330 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30331 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30332 | GIR_RootConstrainSelectedInstOperands, |
| 30333 | // GIR_Coverage, 4478, |
| 30334 | GIR_EraseRootFromParent_Done, |
| 30335 | // Label 1598: @83040 |
| 30336 | GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(83127), // Rule ID 4480 // |
| 30337 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30338 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30339 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30340 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30341 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30342 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30343 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30344 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30345 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30346 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30347 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30348 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30349 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30350 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30351 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30352 | // (intrinsic_wo_chain:{ *:[v16i8] } 3328:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs8), |
| 30354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30355 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30356 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30357 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30359 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30360 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30361 | GIR_RootConstrainSelectedInstOperands, |
| 30362 | // GIR_Coverage, 4480, |
| 30363 | GIR_EraseRootFromParent_Done, |
| 30364 | // Label 1599: @83127 |
| 30365 | GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(83214), // Rule ID 4482 // |
| 30366 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30367 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30368 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30369 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30370 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30371 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30372 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30373 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30375 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30376 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30377 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30378 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30379 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30380 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30381 | // (intrinsic_wo_chain:{ *:[v8i16] } 3328:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs16), |
| 30383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30384 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30385 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30386 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30388 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30389 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30390 | GIR_RootConstrainSelectedInstOperands, |
| 30391 | // GIR_Coverage, 4482, |
| 30392 | GIR_EraseRootFromParent_Done, |
| 30393 | // Label 1600: @83214 |
| 30394 | GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(83301), // Rule ID 4484 // |
| 30395 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30396 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30397 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30398 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30399 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30400 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30401 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30402 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30404 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30405 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30406 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30407 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30408 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30409 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30410 | // (intrinsic_wo_chain:{ *:[v4i32] } 3328:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs32), |
| 30412 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30413 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30414 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30415 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30417 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30418 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30419 | GIR_RootConstrainSelectedInstOperands, |
| 30420 | // GIR_Coverage, 4484, |
| 30421 | GIR_EraseRootFromParent_Done, |
| 30422 | // Label 1601: @83301 |
| 30423 | GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(83388), // Rule ID 4486 // |
| 30424 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30425 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30426 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30427 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30428 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30429 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30430 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30431 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30432 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30433 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30434 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30435 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30436 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30437 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30438 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30439 | // (intrinsic_wo_chain:{ *:[v16i8] } 3328:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs8), |
| 30441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30442 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30443 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30444 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30446 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30447 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30448 | GIR_RootConstrainSelectedInstOperands, |
| 30449 | // GIR_Coverage, 4486, |
| 30450 | GIR_EraseRootFromParent_Done, |
| 30451 | // Label 1602: @83388 |
| 30452 | GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(83475), // Rule ID 4488 // |
| 30453 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30454 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30455 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30456 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30457 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30458 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30459 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30460 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30461 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30462 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30463 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30464 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30465 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30466 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30467 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30468 | // (intrinsic_wo_chain:{ *:[v8i16] } 3328:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30469 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs16), |
| 30470 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30471 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30472 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30473 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30475 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30476 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30477 | GIR_RootConstrainSelectedInstOperands, |
| 30478 | // GIR_Coverage, 4488, |
| 30479 | GIR_EraseRootFromParent_Done, |
| 30480 | // Label 1603: @83475 |
| 30481 | GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(83562), // Rule ID 4490 // |
| 30482 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30483 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30484 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30485 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30486 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30487 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30488 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30489 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30490 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30491 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30492 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30493 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30494 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30495 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30496 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30497 | // (intrinsic_wo_chain:{ *:[v4i32] } 3328:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs32), |
| 30499 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30500 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30501 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30502 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30504 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30505 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30506 | GIR_RootConstrainSelectedInstOperands, |
| 30507 | // GIR_Coverage, 4490, |
| 30508 | GIR_EraseRootFromParent_Done, |
| 30509 | // Label 1604: @83562 |
| 30510 | GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(83649), // Rule ID 4492 // |
| 30511 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30512 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30513 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30514 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30515 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30516 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30517 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30518 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30520 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30521 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30522 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30523 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30524 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30525 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30526 | // (intrinsic_wo_chain:{ *:[v16i8] } 3328:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs8), |
| 30528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30529 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30530 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30531 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30533 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30534 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30535 | GIR_RootConstrainSelectedInstOperands, |
| 30536 | // GIR_Coverage, 4492, |
| 30537 | GIR_EraseRootFromParent_Done, |
| 30538 | // Label 1605: @83649 |
| 30539 | GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(83736), // Rule ID 4494 // |
| 30540 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30541 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30542 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30543 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30544 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30545 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30546 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30547 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30548 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30549 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30550 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30551 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30552 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30553 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30554 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30555 | // (intrinsic_wo_chain:{ *:[v8i16] } 3328:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs16), |
| 30557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30558 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30559 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30560 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30562 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30563 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30564 | GIR_RootConstrainSelectedInstOperands, |
| 30565 | // GIR_Coverage, 4494, |
| 30566 | GIR_EraseRootFromParent_Done, |
| 30567 | // Label 1606: @83736 |
| 30568 | GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(83823), // Rule ID 4496 // |
| 30569 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30570 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30571 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30572 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30573 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30574 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30575 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30576 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30578 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30579 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30580 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30581 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30582 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30583 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30584 | // (intrinsic_wo_chain:{ *:[v4i32] } 3328:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs32), |
| 30586 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30587 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30588 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30589 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30591 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30592 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30593 | GIR_RootConstrainSelectedInstOperands, |
| 30594 | // GIR_Coverage, 4496, |
| 30595 | GIR_EraseRootFromParent_Done, |
| 30596 | // Label 1607: @83823 |
| 30597 | GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(83949), // Rule ID 2710 // |
| 30598 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 30599 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx4), |
| 30600 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 30601 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 30602 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 30603 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 30604 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 30605 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 30606 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s8, |
| 30607 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 30608 | // (intrinsic_wo_chain:{ *:[v8i8] } 3530:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 30609 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 30610 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 30611 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30612 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 30613 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 30614 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 30615 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 30616 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2 |
| 30617 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 30618 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3 |
| 30619 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 30620 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 30621 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 30622 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 30623 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 30624 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 30625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX4Pseudo), |
| 30626 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 30627 | GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 30628 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30629 | GIR_RootToRootCopy, /*OpIdx*/7, // Vm |
| 30630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 30631 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30632 | GIR_RootConstrainSelectedInstOperands, |
| 30633 | // GIR_Coverage, 2710, |
| 30634 | GIR_EraseRootFromParent_Done, |
| 30635 | // Label 1608: @83949 |
| 30636 | GIM_Reject, |
| 30637 | // Label 1553: @83950 |
| 30638 | GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(88244), |
| 30639 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/10, |
| 30640 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshrn), |
| 30641 | GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(84070), // Rule ID 3873 // |
| 30642 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30643 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30644 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30645 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30646 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30647 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30648 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30649 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 30650 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 30651 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30652 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30653 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30654 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 30655 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30656 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 30657 | // MIs[1] Operand 1 |
| 30658 | // No operand predicates |
| 30659 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30660 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30661 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30662 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 30663 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 30664 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30665 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 30666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh), |
| 30667 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30668 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 30669 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30670 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 30671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30672 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30673 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30674 | GIR_RootConstrainSelectedInstOperands, |
| 30675 | // GIR_Coverage, 3873, |
| 30676 | GIR_EraseRootFromParent_Done, |
| 30677 | // Label 1610: @84070 |
| 30678 | GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(84177), // Rule ID 3875 // |
| 30679 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30680 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30681 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30682 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30683 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30684 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30685 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30686 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 30687 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 30688 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30689 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30690 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30691 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 30692 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30693 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 30694 | // MIs[1] Operand 1 |
| 30695 | // No operand predicates |
| 30696 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30697 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30698 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30699 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 30700 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 30701 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30702 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 30703 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th), |
| 30704 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30705 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 30706 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30707 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 30708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30709 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30710 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30711 | GIR_RootConstrainSelectedInstOperands, |
| 30712 | // GIR_Coverage, 3875, |
| 30713 | GIR_EraseRootFromParent_Done, |
| 30714 | // Label 1611: @84177 |
| 30715 | GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(84284), // Rule ID 3877 // |
| 30716 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30717 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30718 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30719 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30720 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30721 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30722 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30723 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 30724 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 30725 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30726 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30727 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30728 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 30729 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30730 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 30731 | // MIs[1] Operand 1 |
| 30732 | // No operand predicates |
| 30733 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30734 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30735 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30736 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 30737 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 30738 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30739 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 30740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh), |
| 30741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30742 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 30743 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30744 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 30745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30746 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30747 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30748 | GIR_RootConstrainSelectedInstOperands, |
| 30749 | // GIR_Coverage, 3877, |
| 30750 | GIR_EraseRootFromParent_Done, |
| 30751 | // Label 1612: @84284 |
| 30752 | GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(84391), // Rule ID 3879 // |
| 30753 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30754 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30755 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30756 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30757 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30758 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30759 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30760 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 30761 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 30762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30763 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30764 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30765 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 30766 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30767 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 30768 | // MIs[1] Operand 1 |
| 30769 | // No operand predicates |
| 30770 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30771 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30772 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30773 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 30774 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 30775 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30776 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 30777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th), |
| 30778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30779 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 30780 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30781 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 30782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30783 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30784 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30785 | GIR_RootConstrainSelectedInstOperands, |
| 30786 | // GIR_Coverage, 3879, |
| 30787 | GIR_EraseRootFromParent_Done, |
| 30788 | // Label 1613: @84391 |
| 30789 | GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(84498), // Rule ID 3881 // |
| 30790 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30791 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30792 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30793 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30794 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30795 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30796 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30797 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 30798 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 30799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30800 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30801 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30802 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 30803 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30804 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 30805 | // MIs[1] Operand 1 |
| 30806 | // No operand predicates |
| 30807 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30808 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30809 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30810 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 30811 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 30812 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30813 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 30814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh), |
| 30815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30816 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 30817 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30818 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 30819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30820 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30821 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30822 | GIR_RootConstrainSelectedInstOperands, |
| 30823 | // GIR_Coverage, 3881, |
| 30824 | GIR_EraseRootFromParent_Done, |
| 30825 | // Label 1614: @84498 |
| 30826 | GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(84605), // Rule ID 3883 // |
| 30827 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30828 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30829 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30830 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30831 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30832 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30833 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30834 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 30835 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 30836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30837 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30838 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30839 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 30840 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30841 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 30842 | // MIs[1] Operand 1 |
| 30843 | // No operand predicates |
| 30844 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30845 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30846 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30847 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 30848 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 30849 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30850 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 30851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th), |
| 30852 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30853 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 30854 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30855 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 30856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30857 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30858 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30859 | GIR_RootConstrainSelectedInstOperands, |
| 30860 | // GIR_Coverage, 3883, |
| 30861 | GIR_EraseRootFromParent_Done, |
| 30862 | // Label 1615: @84605 |
| 30863 | GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(84712), // Rule ID 3885 // |
| 30864 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30865 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30866 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30867 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30868 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30869 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30870 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30871 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 30872 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 30873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30874 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30875 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30876 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 30877 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30878 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 30879 | // MIs[1] Operand 1 |
| 30880 | // No operand predicates |
| 30881 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30882 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30883 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30884 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 30885 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 30886 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30887 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 30888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh), |
| 30889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30890 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 30891 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30892 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 30893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30894 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30895 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30896 | GIR_RootConstrainSelectedInstOperands, |
| 30897 | // GIR_Coverage, 3885, |
| 30898 | GIR_EraseRootFromParent_Done, |
| 30899 | // Label 1616: @84712 |
| 30900 | GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(84819), // Rule ID 3887 // |
| 30901 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30902 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30903 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30904 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30905 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30906 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30907 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30908 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 30909 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 30910 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30911 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30912 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30913 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 30914 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30915 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 30916 | // MIs[1] Operand 1 |
| 30917 | // No operand predicates |
| 30918 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30919 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30920 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30921 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 30922 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 30923 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30924 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 30925 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th), |
| 30926 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30927 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 30928 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30929 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 30930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30931 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30932 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30933 | GIR_RootConstrainSelectedInstOperands, |
| 30934 | // GIR_Coverage, 3887, |
| 30935 | GIR_EraseRootFromParent_Done, |
| 30936 | // Label 1617: @84819 |
| 30937 | GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(84926), // Rule ID 3889 // |
| 30938 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30939 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30940 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30941 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30942 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30943 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30944 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30945 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 30946 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 30947 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30948 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30949 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30950 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 30951 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30952 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 30953 | // MIs[1] Operand 1 |
| 30954 | // No operand predicates |
| 30955 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30956 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30957 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30958 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 30959 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 30960 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30961 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 30962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh), |
| 30963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30964 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 30965 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30966 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 30967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30968 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30969 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30970 | GIR_RootConstrainSelectedInstOperands, |
| 30971 | // GIR_Coverage, 3889, |
| 30972 | GIR_EraseRootFromParent_Done, |
| 30973 | // Label 1618: @84926 |
| 30974 | GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(85033), // Rule ID 3891 // |
| 30975 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30976 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30977 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30978 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30979 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30980 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30981 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30982 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 30983 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 30984 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30985 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30986 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30987 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 30988 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 30989 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 30990 | // MIs[1] Operand 1 |
| 30991 | // No operand predicates |
| 30992 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30993 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30994 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30995 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 30996 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 30997 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 30998 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 30999 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th), |
| 31000 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31001 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31002 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31003 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31005 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31006 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31007 | GIR_RootConstrainSelectedInstOperands, |
| 31008 | // GIR_Coverage, 3891, |
| 31009 | GIR_EraseRootFromParent_Done, |
| 31010 | // Label 1619: @85033 |
| 31011 | GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(85140), // Rule ID 3893 // |
| 31012 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31013 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31014 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31015 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31016 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31017 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31018 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31019 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31020 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31021 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31022 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31023 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31024 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31025 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31026 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31027 | // MIs[1] Operand 1 |
| 31028 | // No operand predicates |
| 31029 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31030 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31031 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31032 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31033 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31034 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31035 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh), |
| 31037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31038 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31039 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31040 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31042 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31043 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31044 | GIR_RootConstrainSelectedInstOperands, |
| 31045 | // GIR_Coverage, 3893, |
| 31046 | GIR_EraseRootFromParent_Done, |
| 31047 | // Label 1620: @85140 |
| 31048 | GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(85247), // Rule ID 3895 // |
| 31049 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31050 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31051 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31052 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31053 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31054 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31055 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31056 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31057 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31059 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31060 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31061 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31062 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31063 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31064 | // MIs[1] Operand 1 |
| 31065 | // No operand predicates |
| 31066 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31067 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31068 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31069 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31070 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31071 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31072 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th), |
| 31074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31075 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31076 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31077 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31079 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31080 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31081 | GIR_RootConstrainSelectedInstOperands, |
| 31082 | // GIR_Coverage, 3895, |
| 31083 | GIR_EraseRootFromParent_Done, |
| 31084 | // Label 1621: @85247 |
| 31085 | GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(85354), // Rule ID 3897 // |
| 31086 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31087 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31088 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31089 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31090 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31091 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31092 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31093 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31094 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31095 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31096 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31097 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31098 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31099 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31100 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31101 | // MIs[1] Operand 1 |
| 31102 | // No operand predicates |
| 31103 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31104 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31105 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31106 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31107 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31108 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31109 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh), |
| 31111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31112 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31113 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31114 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31116 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31117 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31118 | GIR_RootConstrainSelectedInstOperands, |
| 31119 | // GIR_Coverage, 3897, |
| 31120 | GIR_EraseRootFromParent_Done, |
| 31121 | // Label 1622: @85354 |
| 31122 | GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(85461), // Rule ID 3899 // |
| 31123 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31124 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31125 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31126 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31127 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31128 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31129 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31130 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31131 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31132 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31133 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31134 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31135 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31136 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31137 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31138 | // MIs[1] Operand 1 |
| 31139 | // No operand predicates |
| 31140 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31141 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31142 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31143 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31144 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31145 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31146 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th), |
| 31148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31149 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31150 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31151 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31153 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31154 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31155 | GIR_RootConstrainSelectedInstOperands, |
| 31156 | // GIR_Coverage, 3899, |
| 31157 | GIR_EraseRootFromParent_Done, |
| 31158 | // Label 1623: @85461 |
| 31159 | GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(85568), // Rule ID 3901 // |
| 31160 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31161 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31162 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31163 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31164 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31165 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31166 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31167 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31168 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31169 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31170 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31171 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31172 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31173 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31174 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31175 | // MIs[1] Operand 1 |
| 31176 | // No operand predicates |
| 31177 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31178 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31179 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31180 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31181 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31182 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31183 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh), |
| 31185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31186 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31187 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31188 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31190 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31191 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31192 | GIR_RootConstrainSelectedInstOperands, |
| 31193 | // GIR_Coverage, 3901, |
| 31194 | GIR_EraseRootFromParent_Done, |
| 31195 | // Label 1624: @85568 |
| 31196 | GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(85675), // Rule ID 3903 // |
| 31197 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31198 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31199 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31200 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31201 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31202 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31203 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31204 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31205 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31206 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31207 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31208 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31209 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31210 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31211 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31212 | // MIs[1] Operand 1 |
| 31213 | // No operand predicates |
| 31214 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31215 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31216 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31217 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31218 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31219 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31220 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31221 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th), |
| 31222 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31223 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31224 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31225 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31227 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31228 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31229 | GIR_RootConstrainSelectedInstOperands, |
| 31230 | // GIR_Coverage, 3903, |
| 31231 | GIR_EraseRootFromParent_Done, |
| 31232 | // Label 1625: @85675 |
| 31233 | GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(85782), // Rule ID 3905 // |
| 31234 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31235 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31236 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31237 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31238 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31239 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31240 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31241 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31242 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31244 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31245 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31246 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31247 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31248 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31249 | // MIs[1] Operand 1 |
| 31250 | // No operand predicates |
| 31251 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31252 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31253 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31254 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31255 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31256 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31257 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs16), |
| 31259 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31260 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31261 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31262 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31264 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31265 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31266 | GIR_RootConstrainSelectedInstOperands, |
| 31267 | // GIR_Coverage, 3905, |
| 31268 | GIR_EraseRootFromParent_Done, |
| 31269 | // Label 1626: @85782 |
| 31270 | GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(85889), // Rule ID 3907 // |
| 31271 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31272 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31273 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31274 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31275 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31276 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31277 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31278 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31279 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31280 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31281 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31282 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31283 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31284 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31285 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31286 | // MIs[1] Operand 1 |
| 31287 | // No operand predicates |
| 31288 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31289 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31290 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31291 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31292 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31293 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31294 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths16), |
| 31296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31297 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31298 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31299 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31301 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31302 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31303 | GIR_RootConstrainSelectedInstOperands, |
| 31304 | // GIR_Coverage, 3907, |
| 31305 | GIR_EraseRootFromParent_Done, |
| 31306 | // Label 1627: @85889 |
| 31307 | GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(85996), // Rule ID 3909 // |
| 31308 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31309 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31310 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31311 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31312 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31313 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31314 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31315 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31316 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31318 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31319 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31320 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31321 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31322 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31323 | // MIs[1] Operand 1 |
| 31324 | // No operand predicates |
| 31325 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31326 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31327 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31328 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31329 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31330 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31331 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs32), |
| 31333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31334 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31335 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31336 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31338 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31339 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31340 | GIR_RootConstrainSelectedInstOperands, |
| 31341 | // GIR_Coverage, 3909, |
| 31342 | GIR_EraseRootFromParent_Done, |
| 31343 | // Label 1628: @85996 |
| 31344 | GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(86103), // Rule ID 3911 // |
| 31345 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31346 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31347 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31348 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31349 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31350 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31351 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31352 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31353 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31354 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31355 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31356 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31357 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31358 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31359 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31360 | // MIs[1] Operand 1 |
| 31361 | // No operand predicates |
| 31362 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31363 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31364 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31365 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31366 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31367 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31368 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths32), |
| 31370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31371 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31372 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31373 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31375 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31376 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31377 | GIR_RootConstrainSelectedInstOperands, |
| 31378 | // GIR_Coverage, 3911, |
| 31379 | GIR_EraseRootFromParent_Done, |
| 31380 | // Label 1629: @86103 |
| 31381 | GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(86210), // Rule ID 3913 // |
| 31382 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31383 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31384 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31385 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31386 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31387 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31388 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31389 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31390 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31391 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31392 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31393 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31394 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31395 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31396 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31397 | // MIs[1] Operand 1 |
| 31398 | // No operand predicates |
| 31399 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31400 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31401 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31402 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31403 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31404 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31405 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31406 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu16), |
| 31407 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31408 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31409 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31410 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31412 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31413 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31414 | GIR_RootConstrainSelectedInstOperands, |
| 31415 | // GIR_Coverage, 3913, |
| 31416 | GIR_EraseRootFromParent_Done, |
| 31417 | // Label 1630: @86210 |
| 31418 | GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(86317), // Rule ID 3915 // |
| 31419 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31420 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31421 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31422 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31423 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31424 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31425 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31426 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31427 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31428 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31429 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31430 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31431 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31432 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31433 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31434 | // MIs[1] Operand 1 |
| 31435 | // No operand predicates |
| 31436 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31437 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31438 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31439 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31440 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31441 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31442 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31443 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu16), |
| 31444 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31445 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31446 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31447 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31449 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31450 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31451 | GIR_RootConstrainSelectedInstOperands, |
| 31452 | // GIR_Coverage, 3915, |
| 31453 | GIR_EraseRootFromParent_Done, |
| 31454 | // Label 1631: @86317 |
| 31455 | GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(86424), // Rule ID 3917 // |
| 31456 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31457 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31458 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31459 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31460 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31461 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31462 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31463 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31464 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31465 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31466 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31467 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31468 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31469 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31470 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31471 | // MIs[1] Operand 1 |
| 31472 | // No operand predicates |
| 31473 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31474 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31475 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31476 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31477 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31478 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31479 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu32), |
| 31481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31482 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31483 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31484 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31486 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31487 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31488 | GIR_RootConstrainSelectedInstOperands, |
| 31489 | // GIR_Coverage, 3917, |
| 31490 | GIR_EraseRootFromParent_Done, |
| 31491 | // Label 1632: @86424 |
| 31492 | GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(86531), // Rule ID 3919 // |
| 31493 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31494 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31495 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31496 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31497 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31498 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31499 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31500 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31501 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31503 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31504 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31505 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31506 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31507 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31508 | // MIs[1] Operand 1 |
| 31509 | // No operand predicates |
| 31510 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31511 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31512 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31513 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31514 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31515 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31516 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu32), |
| 31518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31519 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31520 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31521 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31523 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31524 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31525 | GIR_RootConstrainSelectedInstOperands, |
| 31526 | // GIR_Coverage, 3919, |
| 31527 | GIR_EraseRootFromParent_Done, |
| 31528 | // Label 1633: @86531 |
| 31529 | GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(86638), // Rule ID 3921 // |
| 31530 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31531 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31532 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31533 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31534 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31535 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31536 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31537 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31538 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31539 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31540 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31541 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31542 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31543 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31544 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31545 | // MIs[1] Operand 1 |
| 31546 | // No operand predicates |
| 31547 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31548 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31549 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31550 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31551 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31552 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31553 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs16), |
| 31555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31556 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31557 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31558 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31560 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31561 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31562 | GIR_RootConstrainSelectedInstOperands, |
| 31563 | // GIR_Coverage, 3921, |
| 31564 | GIR_EraseRootFromParent_Done, |
| 31565 | // Label 1634: @86638 |
| 31566 | GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(86745), // Rule ID 3923 // |
| 31567 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31568 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31569 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31570 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31571 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31572 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31573 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31574 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31575 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31577 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31578 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31579 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31580 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31581 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31582 | // MIs[1] Operand 1 |
| 31583 | // No operand predicates |
| 31584 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31585 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31586 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31587 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31588 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31589 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31590 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths16), |
| 31592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31593 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31594 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31595 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31597 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31598 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31599 | GIR_RootConstrainSelectedInstOperands, |
| 31600 | // GIR_Coverage, 3923, |
| 31601 | GIR_EraseRootFromParent_Done, |
| 31602 | // Label 1635: @86745 |
| 31603 | GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(86852), // Rule ID 3925 // |
| 31604 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31605 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31606 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31607 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31608 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31609 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31610 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31611 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31612 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31613 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31614 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31615 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31616 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31617 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31618 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31619 | // MIs[1] Operand 1 |
| 31620 | // No operand predicates |
| 31621 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31622 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31623 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31624 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31625 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31626 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31627 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs32), |
| 31629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31630 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31631 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31632 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31634 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31635 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31636 | GIR_RootConstrainSelectedInstOperands, |
| 31637 | // GIR_Coverage, 3925, |
| 31638 | GIR_EraseRootFromParent_Done, |
| 31639 | // Label 1636: @86852 |
| 31640 | GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(86959), // Rule ID 3927 // |
| 31641 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31642 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31643 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31644 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31645 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31646 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31647 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31648 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31649 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31650 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31651 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31652 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31653 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31654 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31655 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31656 | // MIs[1] Operand 1 |
| 31657 | // No operand predicates |
| 31658 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31659 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31660 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31661 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31662 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31663 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31664 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31665 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths32), |
| 31666 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31667 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31668 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31669 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31671 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31672 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31673 | GIR_RootConstrainSelectedInstOperands, |
| 31674 | // GIR_Coverage, 3927, |
| 31675 | GIR_EraseRootFromParent_Done, |
| 31676 | // Label 1637: @86959 |
| 31677 | GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(87066), // Rule ID 3929 // |
| 31678 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31679 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31680 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31681 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31682 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31683 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31684 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31685 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31686 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31687 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31688 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31689 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31690 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31691 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31692 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31693 | // MIs[1] Operand 1 |
| 31694 | // No operand predicates |
| 31695 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31696 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31697 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31698 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31699 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31700 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31701 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu16), |
| 31703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31704 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31705 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31706 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31708 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31709 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31710 | GIR_RootConstrainSelectedInstOperands, |
| 31711 | // GIR_Coverage, 3929, |
| 31712 | GIR_EraseRootFromParent_Done, |
| 31713 | // Label 1638: @87066 |
| 31714 | GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(87173), // Rule ID 3931 // |
| 31715 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31716 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31717 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31718 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31719 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31720 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31721 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31722 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31723 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31724 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31725 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31726 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31727 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31728 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31729 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31730 | // MIs[1] Operand 1 |
| 31731 | // No operand predicates |
| 31732 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31733 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31734 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31735 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31736 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31737 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31738 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu16), |
| 31740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31741 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31742 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31743 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31745 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31746 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31747 | GIR_RootConstrainSelectedInstOperands, |
| 31748 | // GIR_Coverage, 3931, |
| 31749 | GIR_EraseRootFromParent_Done, |
| 31750 | // Label 1639: @87173 |
| 31751 | GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(87280), // Rule ID 3933 // |
| 31752 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31753 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31754 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31755 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31756 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31757 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31758 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31759 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31760 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31762 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31763 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31764 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31765 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31766 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31767 | // MIs[1] Operand 1 |
| 31768 | // No operand predicates |
| 31769 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31770 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31771 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31772 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31773 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31774 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31775 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu32), |
| 31777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31778 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31779 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31780 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31782 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31783 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31784 | GIR_RootConstrainSelectedInstOperands, |
| 31785 | // GIR_Coverage, 3933, |
| 31786 | GIR_EraseRootFromParent_Done, |
| 31787 | // Label 1640: @87280 |
| 31788 | GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(87387), // Rule ID 3935 // |
| 31789 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31790 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31791 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31792 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31793 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31794 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31795 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31796 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31797 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31798 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31799 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31800 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31801 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31802 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31803 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31804 | // MIs[1] Operand 1 |
| 31805 | // No operand predicates |
| 31806 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31807 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31808 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31809 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31810 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31811 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31812 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu32), |
| 31814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31815 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31816 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31817 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31819 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31820 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31821 | GIR_RootConstrainSelectedInstOperands, |
| 31822 | // GIR_Coverage, 3935, |
| 31823 | GIR_EraseRootFromParent_Done, |
| 31824 | // Label 1641: @87387 |
| 31825 | GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(87494), // Rule ID 3937 // |
| 31826 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31827 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31828 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31829 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31830 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31831 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31832 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31833 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31834 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31836 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31837 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31838 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31839 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31840 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31841 | // MIs[1] Operand 1 |
| 31842 | // No operand predicates |
| 31843 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31844 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31845 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31846 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31847 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31848 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31849 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16bh), |
| 31851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31852 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31853 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31854 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31856 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31857 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31858 | GIR_RootConstrainSelectedInstOperands, |
| 31859 | // GIR_Coverage, 3937, |
| 31860 | GIR_EraseRootFromParent_Done, |
| 31861 | // Label 1642: @87494 |
| 31862 | GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(87601), // Rule ID 3939 // |
| 31863 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31864 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31865 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31866 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31867 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31868 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31869 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31870 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31871 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31873 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31874 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31875 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31876 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31877 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31878 | // MIs[1] Operand 1 |
| 31879 | // No operand predicates |
| 31880 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31881 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31882 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31883 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31884 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31885 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31886 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16th), |
| 31888 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31889 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31890 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31891 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31893 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31894 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31895 | GIR_RootConstrainSelectedInstOperands, |
| 31896 | // GIR_Coverage, 3939, |
| 31897 | GIR_EraseRootFromParent_Done, |
| 31898 | // Label 1643: @87601 |
| 31899 | GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(87708), // Rule ID 3941 // |
| 31900 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31901 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31902 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31903 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31904 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31905 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31906 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31907 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31908 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31910 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31911 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31912 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31913 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31914 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31915 | // MIs[1] Operand 1 |
| 31916 | // No operand predicates |
| 31917 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31918 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31919 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31920 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31921 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31922 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31923 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32bh), |
| 31925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31926 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31927 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31928 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31930 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31931 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31932 | GIR_RootConstrainSelectedInstOperands, |
| 31933 | // GIR_Coverage, 3941, |
| 31934 | GIR_EraseRootFromParent_Done, |
| 31935 | // Label 1644: @87708 |
| 31936 | GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(87815), // Rule ID 3943 // |
| 31937 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31938 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31939 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31940 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31941 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31942 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31943 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31944 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31945 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31947 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31948 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31949 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31950 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31951 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31952 | // MIs[1] Operand 1 |
| 31953 | // No operand predicates |
| 31954 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31955 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31956 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31957 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31958 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31959 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31960 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31961 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32th), |
| 31962 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31963 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31964 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31965 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31967 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31968 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31969 | GIR_RootConstrainSelectedInstOperands, |
| 31970 | // GIR_Coverage, 3943, |
| 31971 | GIR_EraseRootFromParent_Done, |
| 31972 | // Label 1645: @87815 |
| 31973 | GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(87922), // Rule ID 3945 // |
| 31974 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31975 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31976 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31977 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31978 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31979 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31980 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31981 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31982 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31983 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31984 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31985 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31986 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31987 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31988 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31989 | // MIs[1] Operand 1 |
| 31990 | // No operand predicates |
| 31991 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31992 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31993 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31994 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31995 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31996 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31997 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16bh), |
| 31999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32000 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32001 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32002 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32004 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32005 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32006 | GIR_RootConstrainSelectedInstOperands, |
| 32007 | // GIR_Coverage, 3945, |
| 32008 | GIR_EraseRootFromParent_Done, |
| 32009 | // Label 1646: @87922 |
| 32010 | GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(88029), // Rule ID 3947 // |
| 32011 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 32012 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 32013 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 32014 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32015 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32016 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32017 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32018 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32019 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32021 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32022 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32023 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32024 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32025 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32026 | // MIs[1] Operand 1 |
| 32027 | // No operand predicates |
| 32028 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32029 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32030 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32031 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32032 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32033 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32034 | // (intrinsic_wo_chain:{ *:[v16i8] } 3373:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16th), |
| 32036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32037 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32038 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32039 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32041 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32042 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32043 | GIR_RootConstrainSelectedInstOperands, |
| 32044 | // GIR_Coverage, 3947, |
| 32045 | GIR_EraseRootFromParent_Done, |
| 32046 | // Label 1647: @88029 |
| 32047 | GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(88136), // Rule ID 3949 // |
| 32048 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 32049 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 32050 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32051 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32052 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32053 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32054 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32055 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32056 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32057 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32058 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32059 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32060 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32061 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32062 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32063 | // MIs[1] Operand 1 |
| 32064 | // No operand predicates |
| 32065 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32066 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32067 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32068 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32069 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32070 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32071 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32bh), |
| 32073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32074 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32075 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32076 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32078 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32079 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32080 | GIR_RootConstrainSelectedInstOperands, |
| 32081 | // GIR_Coverage, 3949, |
| 32082 | GIR_EraseRootFromParent_Done, |
| 32083 | // Label 1648: @88136 |
| 32084 | GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(88243), // Rule ID 3951 // |
| 32085 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 32086 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 32087 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32088 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32089 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32090 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32091 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32092 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32093 | GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32094 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32095 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32096 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32097 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32098 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32099 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32100 | // MIs[1] Operand 1 |
| 32101 | // No operand predicates |
| 32102 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32103 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32104 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32105 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32106 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32107 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32108 | // (intrinsic_wo_chain:{ *:[v8i16] } 3373:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32th), |
| 32110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32111 | GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32112 | GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32113 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32115 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32116 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32117 | GIR_RootConstrainSelectedInstOperands, |
| 32118 | // GIR_Coverage, 3951, |
| 32119 | GIR_EraseRootFromParent_Done, |
| 32120 | // Label 1649: @88243 |
| 32121 | GIM_Reject, |
| 32122 | // Label 1609: @88244 |
| 32123 | GIM_Reject, |
| 32124 | // Label 14: @88245 |
| 32125 | GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(88302), |
| 32126 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, |
| 32127 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_clrex), |
| 32128 | GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(88275), // Rule ID 252 // |
| 32129 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6K_IsARM), |
| 32130 | // (intrinsic_void 3158:{ *:[iPTR] }) => (CLREX) |
| 32131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLREX), |
| 32132 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32133 | GIR_RootConstrainSelectedInstOperands, |
| 32134 | // GIR_Coverage, 252, |
| 32135 | GIR_EraseRootFromParent_Done, |
| 32136 | // Label 1651: @88275 |
| 32137 | GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(88301), // Rule ID 591 // |
| 32138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV7Clrex_IsThumb), |
| 32139 | // (intrinsic_void 3158:{ *:[iPTR] }) => (t2CLREX) |
| 32140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLREX), |
| 32141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32142 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32143 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32144 | GIR_RootConstrainSelectedInstOperands, |
| 32145 | // GIR_Coverage, 591, |
| 32146 | GIR_EraseRootFromParent_Done, |
| 32147 | // Label 1652: @88301 |
| 32148 | GIM_Reject, |
| 32149 | // Label 1650: @88302 |
| 32150 | GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(89104), |
| 32151 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, |
| 32152 | GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(88346), // Rule ID 351 // |
| 32153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsWindows), |
| 32154 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32155 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32156 | GIM_CheckConstantInt, /*MI*/0, /*Op*/1, GIMT_Encode8(249), |
| 32157 | // (intrinsic_void 3599:{ *:[iPTR] }, 249:{ *:[i32] }) => (t__brkdiv0) |
| 32158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t__brkdiv0), |
| 32159 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32160 | GIR_RootConstrainSelectedInstOperands, |
| 32161 | // GIR_Coverage, 351, |
| 32162 | GIR_EraseRootFromParent_Done, |
| 32163 | // Label 1654: @88346 |
| 32164 | GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(88398), // Rule ID 2 // |
| 32165 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 32166 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 32167 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32168 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32169 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32170 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239), |
| 32171 | // MIs[1] Operand 1 |
| 32172 | // No operand predicates |
| 32173 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32174 | // (intrinsic_void 3176:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (HINT (imm:{ *:[i32] }):$imm) |
| 32175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::HINT), |
| 32176 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32178 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32179 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32180 | GIR_RootConstrainSelectedInstOperands, |
| 32181 | // GIR_Coverage, 2, |
| 32182 | GIR_EraseRootFromParent_Done, |
| 32183 | // Label 1655: @88398 |
| 32184 | GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(88450), // Rule ID 10 // |
| 32185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV7_IsARM), |
| 32186 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg), |
| 32187 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32188 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32189 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32190 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32191 | // MIs[1] Operand 1 |
| 32192 | // No operand predicates |
| 32193 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32194 | // (intrinsic_void 3171:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DBG (imm:{ *:[i32] }):$opt) |
| 32195 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DBG), |
| 32196 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32198 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32199 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32200 | GIR_RootConstrainSelectedInstOperands, |
| 32201 | // GIR_Coverage, 10, |
| 32202 | GIR_EraseRootFromParent_Done, |
| 32203 | // Label 1656: @88450 |
| 32204 | GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(88493), // Rule ID 11 // |
| 32205 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32206 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32207 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32208 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32209 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32210 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 32211 | // MIs[1] Operand 1 |
| 32212 | // No operand predicates |
| 32213 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32214 | // (intrinsic_void 3599:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (UDF (imm:{ *:[i32] }):$imm16) |
| 32215 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF), |
| 32216 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 32217 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32218 | GIR_RootConstrainSelectedInstOperands, |
| 32219 | // GIR_Coverage, 11, |
| 32220 | GIR_EraseRootFromParent_Done, |
| 32221 | // Label 1657: @88493 |
| 32222 | GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(88536), // Rule ID 235 // |
| 32223 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM), |
| 32224 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb), |
| 32225 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32226 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32227 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32228 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32229 | // MIs[1] Operand 1 |
| 32230 | // No operand predicates |
| 32231 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32232 | // (intrinsic_void 3172:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DMB (imm:{ *:[i32] }):$opt) |
| 32233 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DMB), |
| 32234 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32235 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32236 | GIR_RootConstrainSelectedInstOperands, |
| 32237 | // GIR_Coverage, 235, |
| 32238 | GIR_EraseRootFromParent_Done, |
| 32239 | // Label 1658: @88536 |
| 32240 | GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(88579), // Rule ID 236 // |
| 32241 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM), |
| 32242 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb), |
| 32243 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32244 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32245 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32246 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32247 | // MIs[1] Operand 1 |
| 32248 | // No operand predicates |
| 32249 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32250 | // (intrinsic_void 3173:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DSB (imm:{ *:[i32] }):$opt) |
| 32251 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DSB), |
| 32252 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32253 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32254 | GIR_RootConstrainSelectedInstOperands, |
| 32255 | // GIR_Coverage, 236, |
| 32256 | GIR_EraseRootFromParent_Done, |
| 32257 | // Label 1659: @88579 |
| 32258 | GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(88622), // Rule ID 237 // |
| 32259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM), |
| 32260 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb), |
| 32261 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32262 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32263 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32264 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32265 | // MIs[1] Operand 1 |
| 32266 | // No operand predicates |
| 32267 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32268 | // (intrinsic_void 3177:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (ISB (imm:{ *:[i32] }):$opt) |
| 32269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ISB), |
| 32270 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32271 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32272 | GIR_RootConstrainSelectedInstOperands, |
| 32273 | // GIR_Coverage, 237, |
| 32274 | GIR_EraseRootFromParent_Done, |
| 32275 | // Label 1660: @88622 |
| 32276 | GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(88674), // Rule ID 283 // |
| 32277 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6M_IsThumb), |
| 32278 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 32279 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32280 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32281 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32282 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32283 | // MIs[1] Operand 1 |
| 32284 | // No operand predicates |
| 32285 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32286 | // (intrinsic_void 3176:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (tHINT (imm:{ *:[i32] }):$imm) |
| 32287 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tHINT), |
| 32288 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32290 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32291 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32292 | GIR_RootConstrainSelectedInstOperands, |
| 32293 | // GIR_Coverage, 283, |
| 32294 | GIR_EraseRootFromParent_Done, |
| 32295 | // Label 1661: @88674 |
| 32296 | GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(88717), // Rule ID 350 // |
| 32297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb), |
| 32298 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32299 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32300 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32301 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32302 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255), |
| 32303 | // MIs[1] Operand 1 |
| 32304 | // No operand predicates |
| 32305 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32306 | // (intrinsic_void 3599:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8) => (tUDF (imm:{ *:[i32] }):$imm8) |
| 32307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF), |
| 32308 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8 |
| 32309 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32310 | GIR_RootConstrainSelectedInstOperands, |
| 32311 | // GIR_Coverage, 350, |
| 32312 | GIR_EraseRootFromParent_Done, |
| 32313 | // Label 1662: @88717 |
| 32314 | GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(88760), // Rule ID 502 // |
| 32315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 32316 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32317 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32318 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32319 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32320 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 32321 | // MIs[1] Operand 1 |
| 32322 | // No operand predicates |
| 32323 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32324 | // (intrinsic_void 3599:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (t2UDF (imm:{ *:[i32] }):$imm16) |
| 32325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDF), |
| 32326 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 32327 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32328 | GIR_RootConstrainSelectedInstOperands, |
| 32329 | // GIR_Coverage, 502, |
| 32330 | GIR_EraseRootFromParent_Done, |
| 32331 | // Label 1663: @88760 |
| 32332 | GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(88812), // Rule ID 576 // |
| 32333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb), |
| 32334 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb), |
| 32335 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32336 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32337 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32338 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32339 | // MIs[1] Operand 1 |
| 32340 | // No operand predicates |
| 32341 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32342 | // (intrinsic_void 3172:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DMB (imm:{ *:[i32] }):$opt) |
| 32343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DMB), |
| 32344 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32346 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32347 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32348 | GIR_RootConstrainSelectedInstOperands, |
| 32349 | // GIR_Coverage, 576, |
| 32350 | GIR_EraseRootFromParent_Done, |
| 32351 | // Label 1664: @88812 |
| 32352 | GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(88864), // Rule ID 577 // |
| 32353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb), |
| 32354 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb), |
| 32355 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32356 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32357 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32358 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32359 | // MIs[1] Operand 1 |
| 32360 | // No operand predicates |
| 32361 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32362 | // (intrinsic_void 3173:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DSB (imm:{ *:[i32] }):$opt) |
| 32363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DSB), |
| 32364 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32366 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32367 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32368 | GIR_RootConstrainSelectedInstOperands, |
| 32369 | // GIR_Coverage, 577, |
| 32370 | GIR_EraseRootFromParent_Done, |
| 32371 | // Label 1665: @88864 |
| 32372 | GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(88916), // Rule ID 578 // |
| 32373 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb), |
| 32374 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb), |
| 32375 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32376 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32377 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32378 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32379 | // MIs[1] Operand 1 |
| 32380 | // No operand predicates |
| 32381 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32382 | // (intrinsic_void 3177:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2ISB (imm:{ *:[i32] }):$opt) |
| 32383 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ISB), |
| 32384 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32386 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32387 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32388 | GIR_RootConstrainSelectedInstOperands, |
| 32389 | // GIR_Coverage, 578, |
| 32390 | GIR_EraseRootFromParent_Done, |
| 32391 | // Label 1666: @88916 |
| 32392 | GIM_Try, /*On fail goto*//*Label 1667*/ GIMT_Encode4(88968), // Rule ID 596 // |
| 32393 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 32394 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 32395 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32396 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32397 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32398 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239), |
| 32399 | // MIs[1] Operand 1 |
| 32400 | // No operand predicates |
| 32401 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32402 | // (intrinsic_void 3176:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (t2HINT (imm:{ *:[i32] }):$imm) |
| 32403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2HINT), |
| 32404 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32406 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32407 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32408 | GIR_RootConstrainSelectedInstOperands, |
| 32409 | // GIR_Coverage, 596, |
| 32410 | GIR_EraseRootFromParent_Done, |
| 32411 | // Label 1667: @88968 |
| 32412 | GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(89020), // Rule ID 597 // |
| 32413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 32414 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg), |
| 32415 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32416 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32417 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32418 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32419 | // MIs[1] Operand 1 |
| 32420 | // No operand predicates |
| 32421 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32422 | // (intrinsic_void 3171:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DBG (imm:{ *:[i32] }):$opt) |
| 32423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DBG), |
| 32424 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32426 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32427 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32428 | GIR_RootConstrainSelectedInstOperands, |
| 32429 | // GIR_Coverage, 597, |
| 32430 | GIR_EraseRootFromParent_Done, |
| 32431 | // Label 1668: @89020 |
| 32432 | GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(89060), // Rule ID 742 // |
| 32433 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs), |
| 32434 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_get_fpscr), |
| 32435 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32436 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32437 | // (intrinsic_w_chain:{ *:[i32] } 3174:{ *:[iPTR] }) => (VMRS:{ *:[i32] }) |
| 32438 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 32439 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 32440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32441 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32442 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32443 | GIR_RootConstrainSelectedInstOperands, |
| 32444 | // GIR_Coverage, 742, |
| 32445 | GIR_EraseRootFromParent_Done, |
| 32446 | // Label 1669: @89060 |
| 32447 | GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(89103), // Rule ID 743 // |
| 32448 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs), |
| 32449 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_set_fpscr), |
| 32450 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32451 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32452 | // (intrinsic_void 3543:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt) => (VMSR GPRnopc:{ *:[i32] }:$Rt) |
| 32453 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 32454 | GIR_RootToRootCopy, /*OpIdx*/1, // Rt |
| 32455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32456 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32457 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 32458 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32459 | GIR_RootConstrainSelectedInstOperands, |
| 32460 | // GIR_Coverage, 743, |
| 32461 | GIR_EraseRootFromParent_Done, |
| 32462 | // Label 1670: @89103 |
| 32463 | GIM_Reject, |
| 32464 | // Label 1653: @89104 |
| 32465 | GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(89147), // Rule ID 621 // |
| 32466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLOB_HasV8_1MMainline_IsThumb2), |
| 32467 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 32468 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::start_loop_iterations), |
| 32469 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32470 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32471 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRlrRegClassID), |
| 32472 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 32473 | // (intrinsic_w_chain:{ *:[i32] } 333:{ *:[iPTR] }, rGPR:{ *:[i32] }:$tc) => (t2DoLoopStart:{ *:[i32] } rGPR:{ *:[i32] }:$tc) |
| 32474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DoLoopStart), |
| 32475 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[X] |
| 32476 | GIR_RootToRootCopy, /*OpIdx*/2, // tc |
| 32477 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32478 | GIR_RootConstrainSelectedInstOperands, |
| 32479 | // GIR_Coverage, 621, |
| 32480 | GIR_EraseRootFromParent_Done, |
| 32481 | // Label 1671: @89147 |
| 32482 | GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(91138), |
| 32483 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 32484 | GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(89209), // Rule ID 5168 // |
| 32485 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 32486 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 32487 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 32488 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32489 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32490 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32491 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 32492 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32493 | // MIs[1] Operand 1 |
| 32494 | // No operand predicates |
| 32495 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32496 | // (intrinsic_w_chain:{ *:[v4i32] } 3307:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 32497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi), |
| 32498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32499 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 32500 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 32501 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32502 | GIR_RootConstrainSelectedInstOperands, |
| 32503 | // GIR_Coverage, 5168, |
| 32504 | GIR_EraseRootFromParent_Done, |
| 32505 | // Label 1673: @89209 |
| 32506 | GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(89263), // Rule ID 5174 // |
| 32507 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 32508 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 32509 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 32510 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32511 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32512 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32513 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 32514 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32515 | // MIs[1] Operand 1 |
| 32516 | // No operand predicates |
| 32517 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32518 | // (intrinsic_w_chain:{ *:[v4f32] } 3307:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 32519 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi), |
| 32520 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32521 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 32522 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 32523 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32524 | GIR_RootConstrainSelectedInstOperands, |
| 32525 | // GIR_Coverage, 5174, |
| 32526 | GIR_EraseRootFromParent_Done, |
| 32527 | // Label 1674: @89263 |
| 32528 | GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(89317), // Rule ID 5176 // |
| 32529 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 32530 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 32531 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 32532 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32533 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32534 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32535 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 32536 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32537 | // MIs[1] Operand 1 |
| 32538 | // No operand predicates |
| 32539 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32540 | // (intrinsic_w_chain:{ *:[v2i64] } 3307:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 32541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi), |
| 32542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32543 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 32544 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 32545 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32546 | GIR_RootConstrainSelectedInstOperands, |
| 32547 | // GIR_Coverage, 5176, |
| 32548 | GIR_EraseRootFromParent_Done, |
| 32549 | // Label 1675: @89317 |
| 32550 | GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(89371), // Rule ID 5178 // |
| 32551 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 32552 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 32553 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 32554 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32556 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32557 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 32558 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32559 | // MIs[1] Operand 1 |
| 32560 | // No operand predicates |
| 32561 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32562 | // (intrinsic_w_chain:{ *:[v2f64] } 3307:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 32563 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi), |
| 32564 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32565 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 32566 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 32567 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32568 | GIR_RootConstrainSelectedInstOperands, |
| 32569 | // GIR_Coverage, 5178, |
| 32570 | GIR_EraseRootFromParent_Done, |
| 32571 | // Label 1676: @89371 |
| 32572 | GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(89413), // Rule ID 1765 // |
| 32573 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_space), |
| 32574 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32575 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 32577 | // MIs[0] size |
| 32578 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 32579 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 32580 | // (intrinsic_w_chain:{ *:[i32] } 3574:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) => (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) |
| 32581 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SPACE), |
| 32582 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32583 | GIR_RootToRootCopy, /*OpIdx*/2, // size |
| 32584 | GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 32585 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32586 | GIR_RootConstrainSelectedInstOperands, |
| 32587 | // GIR_Coverage, 1765, |
| 32588 | GIR_EraseRootFromParent_Done, |
| 32589 | // Label 1677: @89413 |
| 32590 | GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(89467), // Rule ID 5170 // |
| 32591 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 32592 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 32593 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32594 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32595 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32596 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 32597 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32598 | // MIs[1] Operand 1 |
| 32599 | // No operand predicates |
| 32600 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32601 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32602 | // (intrinsic_void 3381:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 32603 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi), |
| 32604 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 32605 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 32606 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 32607 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32608 | GIR_RootConstrainSelectedInstOperands, |
| 32609 | // GIR_Coverage, 5170, |
| 32610 | GIR_EraseRootFromParent_Done, |
| 32611 | // Label 1678: @89467 |
| 32612 | GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(89521), // Rule ID 5180 // |
| 32613 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 32614 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 32615 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32616 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32617 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32618 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 32619 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32620 | // MIs[1] Operand 1 |
| 32621 | // No operand predicates |
| 32622 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32623 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32624 | // (intrinsic_void 3381:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 32625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi), |
| 32626 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 32627 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 32628 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 32629 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32630 | GIR_RootConstrainSelectedInstOperands, |
| 32631 | // GIR_Coverage, 5180, |
| 32632 | GIR_EraseRootFromParent_Done, |
| 32633 | // Label 1679: @89521 |
| 32634 | GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(89575), // Rule ID 5184 // |
| 32635 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 32636 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 32637 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32638 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 32639 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32640 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 32641 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32642 | // MIs[1] Operand 1 |
| 32643 | // No operand predicates |
| 32644 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32645 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32646 | // (intrinsic_void 3381:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 32647 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi), |
| 32648 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 32649 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 32650 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 32651 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32652 | GIR_RootConstrainSelectedInstOperands, |
| 32653 | // GIR_Coverage, 5184, |
| 32654 | GIR_EraseRootFromParent_Done, |
| 32655 | // Label 1680: @89575 |
| 32656 | GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(89629), // Rule ID 5188 // |
| 32657 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 32658 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 32659 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32660 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 32661 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32662 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 32663 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32664 | // MIs[1] Operand 1 |
| 32665 | // No operand predicates |
| 32666 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32667 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32668 | // (intrinsic_void 3381:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 32669 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi), |
| 32670 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 32671 | GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 32672 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 32673 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32674 | GIR_RootConstrainSelectedInstOperands, |
| 32675 | // GIR_Coverage, 5188, |
| 32676 | GIR_EraseRootFromParent_Done, |
| 32677 | // Label 1681: @89629 |
| 32678 | GIM_Try, /*On fail goto*//*Label 1682*/ GIMT_Encode4(89687), // Rule ID 3 // |
| 32679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 32680 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel), |
| 32681 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32682 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32683 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32684 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 32685 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 32686 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 32687 | // (intrinsic_w_chain:{ *:[i32] } 3542:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 32688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SEL), |
| 32689 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32690 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32691 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32693 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32694 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32695 | GIR_RootConstrainSelectedInstOperands, |
| 32696 | // GIR_Coverage, 3, |
| 32697 | GIR_EraseRootFromParent_Done, |
| 32698 | // Label 1682: @89687 |
| 32699 | GIM_Try, /*On fail goto*//*Label 1683*/ GIMT_Encode4(89745), // Rule ID 121 // |
| 32700 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32701 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx), |
| 32702 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32703 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32704 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32705 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32706 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32707 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32708 | // (intrinsic_w_chain:{ *:[i32] } 3541:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 32709 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SASX), |
| 32710 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32711 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32712 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32714 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32715 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32716 | GIR_RootConstrainSelectedInstOperands, |
| 32717 | // GIR_Coverage, 121, |
| 32718 | GIR_EraseRootFromParent_Done, |
| 32719 | // Label 1683: @89745 |
| 32720 | GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(89803), // Rule ID 122 // |
| 32721 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32722 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16), |
| 32723 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32724 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32725 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32726 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32727 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32728 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32729 | // (intrinsic_w_chain:{ *:[i32] } 3539:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 32730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD16), |
| 32731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32732 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32733 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32735 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32736 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32737 | GIR_RootConstrainSelectedInstOperands, |
| 32738 | // GIR_Coverage, 122, |
| 32739 | GIR_EraseRootFromParent_Done, |
| 32740 | // Label 1684: @89803 |
| 32741 | GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(89861), // Rule ID 123 // |
| 32742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32743 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8), |
| 32744 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32745 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32746 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32747 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32748 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32749 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32750 | // (intrinsic_w_chain:{ *:[i32] } 3540:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 32751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD8), |
| 32752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32753 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32754 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32756 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32757 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32758 | GIR_RootConstrainSelectedInstOperands, |
| 32759 | // GIR_Coverage, 123, |
| 32760 | GIR_EraseRootFromParent_Done, |
| 32761 | // Label 1685: @89861 |
| 32762 | GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(89919), // Rule ID 124 // |
| 32763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32764 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax), |
| 32765 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32766 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32767 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32769 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32770 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32771 | // (intrinsic_w_chain:{ *:[i32] } 3577:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 32772 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSAX), |
| 32773 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32774 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32775 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32777 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32778 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32779 | GIR_RootConstrainSelectedInstOperands, |
| 32780 | // GIR_Coverage, 124, |
| 32781 | GIR_EraseRootFromParent_Done, |
| 32782 | // Label 1686: @89919 |
| 32783 | GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(89977), // Rule ID 125 // |
| 32784 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32785 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16), |
| 32786 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32787 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32788 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32789 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32790 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32791 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32792 | // (intrinsic_w_chain:{ *:[i32] } 3578:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 32793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB16), |
| 32794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32795 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32796 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32798 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32799 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32800 | GIR_RootConstrainSelectedInstOperands, |
| 32801 | // GIR_Coverage, 125, |
| 32802 | GIR_EraseRootFromParent_Done, |
| 32803 | // Label 1687: @89977 |
| 32804 | GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(90035), // Rule ID 126 // |
| 32805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32806 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8), |
| 32807 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32808 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32809 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32811 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32812 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32813 | // (intrinsic_w_chain:{ *:[i32] } 3579:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 32814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB8), |
| 32815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32816 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32817 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32819 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32820 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32821 | GIR_RootConstrainSelectedInstOperands, |
| 32822 | // GIR_Coverage, 126, |
| 32823 | GIR_EraseRootFromParent_Done, |
| 32824 | // Label 1688: @90035 |
| 32825 | GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(90093), // Rule ID 127 // |
| 32826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32827 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx), |
| 32828 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32829 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32830 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32832 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32833 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32834 | // (intrinsic_w_chain:{ *:[i32] } 3592:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 32835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UASX), |
| 32836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32837 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32838 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32840 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32841 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32842 | GIR_RootConstrainSelectedInstOperands, |
| 32843 | // GIR_Coverage, 127, |
| 32844 | GIR_EraseRootFromParent_Done, |
| 32845 | // Label 1689: @90093 |
| 32846 | GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(90151), // Rule ID 128 // |
| 32847 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32848 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16), |
| 32849 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32850 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32851 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32853 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32854 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32855 | // (intrinsic_w_chain:{ *:[i32] } 3590:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 32856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD16), |
| 32857 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32858 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32859 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32861 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32862 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32863 | GIR_RootConstrainSelectedInstOperands, |
| 32864 | // GIR_Coverage, 128, |
| 32865 | GIR_EraseRootFromParent_Done, |
| 32866 | // Label 1690: @90151 |
| 32867 | GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(90209), // Rule ID 129 // |
| 32868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32869 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8), |
| 32870 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32871 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32872 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32874 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32875 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32876 | // (intrinsic_w_chain:{ *:[i32] } 3591:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 32877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD8), |
| 32878 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32879 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32880 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32882 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32883 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32884 | GIR_RootConstrainSelectedInstOperands, |
| 32885 | // GIR_Coverage, 129, |
| 32886 | GIR_EraseRootFromParent_Done, |
| 32887 | // Label 1691: @90209 |
| 32888 | GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(90267), // Rule ID 130 // |
| 32889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32890 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax), |
| 32891 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32892 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32893 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32895 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32896 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32897 | // (intrinsic_w_chain:{ *:[i32] } 3610:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 32898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAX), |
| 32899 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32900 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32901 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32903 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32904 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32905 | GIR_RootConstrainSelectedInstOperands, |
| 32906 | // GIR_Coverage, 130, |
| 32907 | GIR_EraseRootFromParent_Done, |
| 32908 | // Label 1692: @90267 |
| 32909 | GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(90325), // Rule ID 131 // |
| 32910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32911 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16), |
| 32912 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32913 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32914 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32916 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32917 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32918 | // (intrinsic_w_chain:{ *:[i32] } 3611:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 32919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB16), |
| 32920 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32921 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32922 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32924 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32925 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32926 | GIR_RootConstrainSelectedInstOperands, |
| 32927 | // GIR_Coverage, 131, |
| 32928 | GIR_EraseRootFromParent_Done, |
| 32929 | // Label 1693: @90325 |
| 32930 | GIM_Try, /*On fail goto*//*Label 1694*/ GIMT_Encode4(90383), // Rule ID 132 // |
| 32931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32932 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8), |
| 32933 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32934 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32935 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32937 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32938 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32939 | // (intrinsic_w_chain:{ *:[i32] } 3612:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 32940 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB8), |
| 32941 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32942 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32943 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32945 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32946 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32947 | GIR_RootConstrainSelectedInstOperands, |
| 32948 | // GIR_Coverage, 132, |
| 32949 | GIR_EraseRootFromParent_Done, |
| 32950 | // Label 1694: @90383 |
| 32951 | GIM_Try, /*On fail goto*//*Label 1695*/ GIMT_Encode4(90441), // Rule ID 439 // |
| 32952 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 32953 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel), |
| 32954 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32955 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32956 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32957 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 32958 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 32959 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 32960 | // (intrinsic_w_chain:{ *:[i32] } 3542:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 32961 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SEL), |
| 32962 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32963 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32964 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32966 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32967 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32968 | GIR_RootConstrainSelectedInstOperands, |
| 32969 | // GIR_Coverage, 439, |
| 32970 | GIR_EraseRootFromParent_Done, |
| 32971 | // Label 1695: @90441 |
| 32972 | GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(90499), // Rule ID 452 // |
| 32973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 32974 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx), |
| 32975 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32976 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32977 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 32979 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 32980 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 32981 | // (intrinsic_w_chain:{ *:[i32] } 3541:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 32982 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SASX), |
| 32983 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 32984 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 32985 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 32986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32987 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32988 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32989 | GIR_RootConstrainSelectedInstOperands, |
| 32990 | // GIR_Coverage, 452, |
| 32991 | GIR_EraseRootFromParent_Done, |
| 32992 | // Label 1696: @90499 |
| 32993 | GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(90557), // Rule ID 453 // |
| 32994 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 32995 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16), |
| 32996 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32997 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32998 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32999 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33000 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33001 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33002 | // (intrinsic_w_chain:{ *:[i32] } 3539:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD16), |
| 33004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33005 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33006 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33008 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33009 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33010 | GIR_RootConstrainSelectedInstOperands, |
| 33011 | // GIR_Coverage, 453, |
| 33012 | GIR_EraseRootFromParent_Done, |
| 33013 | // Label 1697: @90557 |
| 33014 | GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(90615), // Rule ID 454 // |
| 33015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33016 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8), |
| 33017 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33018 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33019 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33021 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33022 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33023 | // (intrinsic_w_chain:{ *:[i32] } 3540:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD8), |
| 33025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33026 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33027 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33029 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33030 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33031 | GIR_RootConstrainSelectedInstOperands, |
| 33032 | // GIR_Coverage, 454, |
| 33033 | GIR_EraseRootFromParent_Done, |
| 33034 | // Label 1698: @90615 |
| 33035 | GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(90673), // Rule ID 455 // |
| 33036 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33037 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax), |
| 33038 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33039 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33040 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33041 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33042 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33043 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33044 | // (intrinsic_w_chain:{ *:[i32] } 3577:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33045 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSAX), |
| 33046 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33047 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33048 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33050 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33051 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33052 | GIR_RootConstrainSelectedInstOperands, |
| 33053 | // GIR_Coverage, 455, |
| 33054 | GIR_EraseRootFromParent_Done, |
| 33055 | // Label 1699: @90673 |
| 33056 | GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(90731), // Rule ID 456 // |
| 33057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33058 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16), |
| 33059 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33060 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33061 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33062 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33063 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33064 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33065 | // (intrinsic_w_chain:{ *:[i32] } 3578:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB16), |
| 33067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33068 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33069 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33071 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33072 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33073 | GIR_RootConstrainSelectedInstOperands, |
| 33074 | // GIR_Coverage, 456, |
| 33075 | GIR_EraseRootFromParent_Done, |
| 33076 | // Label 1700: @90731 |
| 33077 | GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(90789), // Rule ID 457 // |
| 33078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33079 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8), |
| 33080 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33081 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33082 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33083 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33084 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33085 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33086 | // (intrinsic_w_chain:{ *:[i32] } 3579:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33087 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB8), |
| 33088 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33089 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33090 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33092 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33093 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33094 | GIR_RootConstrainSelectedInstOperands, |
| 33095 | // GIR_Coverage, 457, |
| 33096 | GIR_EraseRootFromParent_Done, |
| 33097 | // Label 1701: @90789 |
| 33098 | GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(90847), // Rule ID 458 // |
| 33099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33100 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx), |
| 33101 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33102 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33103 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33104 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33105 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33106 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33107 | // (intrinsic_w_chain:{ *:[i32] } 3592:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UASX), |
| 33109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33110 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33111 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33113 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33114 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33115 | GIR_RootConstrainSelectedInstOperands, |
| 33116 | // GIR_Coverage, 458, |
| 33117 | GIR_EraseRootFromParent_Done, |
| 33118 | // Label 1702: @90847 |
| 33119 | GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(90905), // Rule ID 459 // |
| 33120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33121 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16), |
| 33122 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33123 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33124 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33126 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33127 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33128 | // (intrinsic_w_chain:{ *:[i32] } 3590:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD16), |
| 33130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33131 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33132 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33134 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33135 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33136 | GIR_RootConstrainSelectedInstOperands, |
| 33137 | // GIR_Coverage, 459, |
| 33138 | GIR_EraseRootFromParent_Done, |
| 33139 | // Label 1703: @90905 |
| 33140 | GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(90963), // Rule ID 460 // |
| 33141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33142 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8), |
| 33143 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33144 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33145 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33147 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33148 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33149 | // (intrinsic_w_chain:{ *:[i32] } 3591:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD8), |
| 33151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33152 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33153 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33155 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33156 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33157 | GIR_RootConstrainSelectedInstOperands, |
| 33158 | // GIR_Coverage, 460, |
| 33159 | GIR_EraseRootFromParent_Done, |
| 33160 | // Label 1704: @90963 |
| 33161 | GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(91021), // Rule ID 461 // |
| 33162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33163 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax), |
| 33164 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33165 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33166 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33167 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33168 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33169 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33170 | // (intrinsic_w_chain:{ *:[i32] } 3610:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAX), |
| 33172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33173 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33174 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33176 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33177 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33178 | GIR_RootConstrainSelectedInstOperands, |
| 33179 | // GIR_Coverage, 461, |
| 33180 | GIR_EraseRootFromParent_Done, |
| 33181 | // Label 1705: @91021 |
| 33182 | GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(91079), // Rule ID 462 // |
| 33183 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33184 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16), |
| 33185 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33186 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33187 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33188 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33189 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33190 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33191 | // (intrinsic_w_chain:{ *:[i32] } 3611:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB16), |
| 33193 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33194 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33195 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33197 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33198 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33199 | GIR_RootConstrainSelectedInstOperands, |
| 33200 | // GIR_Coverage, 462, |
| 33201 | GIR_EraseRootFromParent_Done, |
| 33202 | // Label 1706: @91079 |
| 33203 | GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(91137), // Rule ID 463 // |
| 33204 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33205 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8), |
| 33206 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33207 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33208 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33209 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33210 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33211 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33212 | // (intrinsic_w_chain:{ *:[i32] } 3612:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33213 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB8), |
| 33214 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33215 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33216 | GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33218 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33219 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33220 | GIR_RootConstrainSelectedInstOperands, |
| 33221 | // GIR_Coverage, 463, |
| 33222 | GIR_EraseRootFromParent_Done, |
| 33223 | // Label 1707: @91137 |
| 33224 | GIM_Reject, |
| 33225 | // Label 1672: @91138 |
| 33226 | GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(91384), |
| 33227 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 33228 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base_wb), |
| 33229 | GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(91209), // Rule ID 5172 // |
| 33230 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 33231 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33232 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33233 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33235 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33236 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33237 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33238 | // MIs[1] Operand 1 |
| 33239 | // No operand predicates |
| 33240 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33241 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33242 | // (intrinsic_w_chain:{ *:[v4i32] } 3383:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre), |
| 33244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33245 | GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33246 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33247 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33248 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33249 | GIR_RootConstrainSelectedInstOperands, |
| 33250 | // GIR_Coverage, 5172, |
| 33251 | GIR_EraseRootFromParent_Done, |
| 33252 | // Label 1709: @91209 |
| 33253 | GIM_Try, /*On fail goto*//*Label 1710*/ GIMT_Encode4(91267), // Rule ID 5182 // |
| 33254 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 33255 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33256 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33257 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33259 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33260 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33261 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33262 | // MIs[1] Operand 1 |
| 33263 | // No operand predicates |
| 33264 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33265 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33266 | // (intrinsic_w_chain:{ *:[v4i32] } 3383:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre), |
| 33268 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33269 | GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33270 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33271 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33272 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33273 | GIR_RootConstrainSelectedInstOperands, |
| 33274 | // GIR_Coverage, 5182, |
| 33275 | GIR_EraseRootFromParent_Done, |
| 33276 | // Label 1710: @91267 |
| 33277 | GIM_Try, /*On fail goto*//*Label 1711*/ GIMT_Encode4(91325), // Rule ID 5186 // |
| 33278 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 33279 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 33280 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33281 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, |
| 33282 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33283 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33284 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33285 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33286 | // MIs[1] Operand 1 |
| 33287 | // No operand predicates |
| 33288 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33289 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33290 | // (intrinsic_w_chain:{ *:[v2i64] } 3383:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33291 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre), |
| 33292 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33293 | GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33294 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33295 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33296 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33297 | GIR_RootConstrainSelectedInstOperands, |
| 33298 | // GIR_Coverage, 5186, |
| 33299 | GIR_EraseRootFromParent_Done, |
| 33300 | // Label 1711: @91325 |
| 33301 | GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(91383), // Rule ID 5190 // |
| 33302 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 33303 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 33304 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33305 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, |
| 33306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33307 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33308 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33309 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33310 | // MIs[1] Operand 1 |
| 33311 | // No operand predicates |
| 33312 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33313 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33314 | // (intrinsic_w_chain:{ *:[v2i64] } 3383:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre), |
| 33316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33317 | GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33318 | GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33319 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33320 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33321 | GIR_RootConstrainSelectedInstOperands, |
| 33322 | // GIR_Coverage, 5190, |
| 33323 | GIR_EraseRootFromParent_Done, |
| 33324 | // Label 1712: @91383 |
| 33325 | GIM_Reject, |
| 33326 | // Label 1708: @91384 |
| 33327 | GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(92555), |
| 33328 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 33329 | GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(91453), // Rule ID 5060 // |
| 33330 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33331 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33332 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33333 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33334 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33335 | // MIs[0] base |
| 33336 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33337 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33338 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33339 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33340 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33341 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33342 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u), |
| 33344 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33345 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33346 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33347 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33348 | GIR_RootConstrainSelectedInstOperands, |
| 33349 | // GIR_Coverage, 5060, |
| 33350 | GIR_EraseRootFromParent_Done, |
| 33351 | // Label 1714: @91453 |
| 33352 | GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(91514), // Rule ID 5061 // |
| 33353 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33354 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33355 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33356 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33357 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33358 | // MIs[0] base |
| 33359 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33360 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33361 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33362 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33363 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33364 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33365 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq), |
| 33367 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33368 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33369 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33370 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33371 | GIR_RootConstrainSelectedInstOperands, |
| 33372 | // GIR_Coverage, 5061, |
| 33373 | GIR_EraseRootFromParent_Done, |
| 33374 | // Label 1715: @91514 |
| 33375 | GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(91575), // Rule ID 5064 // |
| 33376 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33377 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33378 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33379 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33380 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33381 | // MIs[0] base |
| 33382 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33383 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33384 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33385 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33386 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 33387 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33388 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 33389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB8_rq), |
| 33390 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33391 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33392 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33393 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33394 | GIR_RootConstrainSelectedInstOperands, |
| 33395 | // GIR_Coverage, 5064, |
| 33396 | GIR_EraseRootFromParent_Done, |
| 33397 | // Label 1716: @91575 |
| 33398 | GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(91636), // Rule ID 5144 // |
| 33399 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33400 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33401 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33402 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33403 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33404 | // MIs[0] base |
| 33405 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33406 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33407 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33408 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33409 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 33410 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33411 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB16_rq), |
| 33413 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33414 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33415 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33416 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33417 | GIR_RootConstrainSelectedInstOperands, |
| 33418 | // GIR_Coverage, 5144, |
| 33419 | GIR_EraseRootFromParent_Done, |
| 33420 | // Label 1717: @91636 |
| 33421 | GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(91697), // Rule ID 5146 // |
| 33422 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33423 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33424 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33425 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33426 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33427 | // MIs[0] base |
| 33428 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33429 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33430 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33431 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33432 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 33433 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33434 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 33435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB32_rq), |
| 33436 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33437 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33438 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33439 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33440 | GIR_RootConstrainSelectedInstOperands, |
| 33441 | // GIR_Coverage, 5146, |
| 33442 | GIR_EraseRootFromParent_Done, |
| 33443 | // Label 1718: @91697 |
| 33444 | GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(91758), // Rule ID 5148 // |
| 33445 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33446 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33447 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33448 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33449 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33450 | // MIs[0] base |
| 33451 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33452 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33453 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33454 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33455 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33456 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33457 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33458 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u), |
| 33459 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33460 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33461 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33462 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33463 | GIR_RootConstrainSelectedInstOperands, |
| 33464 | // GIR_Coverage, 5148, |
| 33465 | GIR_EraseRootFromParent_Done, |
| 33466 | // Label 1719: @91758 |
| 33467 | GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(91819), // Rule ID 5149 // |
| 33468 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33469 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33470 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33471 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33472 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33473 | // MIs[0] base |
| 33474 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33475 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33476 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33477 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33478 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33479 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33480 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq), |
| 33482 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33483 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33484 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33485 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33486 | GIR_RootConstrainSelectedInstOperands, |
| 33487 | // GIR_Coverage, 5149, |
| 33488 | GIR_EraseRootFromParent_Done, |
| 33489 | // Label 1720: @91819 |
| 33490 | GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(91880), // Rule ID 5152 // |
| 33491 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33492 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33493 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33494 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33495 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33496 | // MIs[0] base |
| 33497 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33498 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33499 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33500 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33501 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33502 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33503 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 33504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq_u), |
| 33505 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33506 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33507 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33508 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33509 | GIR_RootConstrainSelectedInstOperands, |
| 33510 | // GIR_Coverage, 5152, |
| 33511 | GIR_EraseRootFromParent_Done, |
| 33512 | // Label 1721: @91880 |
| 33513 | GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(91941), // Rule ID 5153 // |
| 33514 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33515 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33516 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33517 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33518 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33519 | // MIs[0] base |
| 33520 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33521 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33522 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33523 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33524 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33525 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33526 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 33527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq), |
| 33528 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33529 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33530 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33531 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33532 | GIR_RootConstrainSelectedInstOperands, |
| 33533 | // GIR_Coverage, 5153, |
| 33534 | GIR_EraseRootFromParent_Done, |
| 33535 | // Label 1722: @91941 |
| 33536 | GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(92002), // Rule ID 5156 // |
| 33537 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33538 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33539 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33540 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33541 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33542 | // MIs[0] base |
| 33543 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33544 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33545 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33546 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33547 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 33548 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33549 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 33550 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u), |
| 33551 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33552 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33553 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33554 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33555 | GIR_RootConstrainSelectedInstOperands, |
| 33556 | // GIR_Coverage, 5156, |
| 33557 | GIR_EraseRootFromParent_Done, |
| 33558 | // Label 1723: @92002 |
| 33559 | GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(92063), // Rule ID 5157 // |
| 33560 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33561 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33562 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33563 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33564 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33565 | // MIs[0] base |
| 33566 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33567 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33568 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33569 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33570 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 33571 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 33572 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 33573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq), |
| 33574 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33575 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33576 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33577 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33578 | GIR_RootConstrainSelectedInstOperands, |
| 33579 | // GIR_Coverage, 5157, |
| 33580 | GIR_EraseRootFromParent_Done, |
| 33581 | // Label 1724: @92063 |
| 33582 | GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(92124), // Rule ID 5160 // |
| 33583 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33584 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33585 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33586 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33587 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33588 | // MIs[0] base |
| 33589 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33590 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33591 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33592 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33593 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 33594 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33595 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 33596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u), |
| 33597 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33598 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33599 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33600 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33601 | GIR_RootConstrainSelectedInstOperands, |
| 33602 | // GIR_Coverage, 5160, |
| 33603 | GIR_EraseRootFromParent_Done, |
| 33604 | // Label 1725: @92124 |
| 33605 | GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(92185), // Rule ID 5161 // |
| 33606 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33607 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33608 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33609 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33610 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33611 | // MIs[0] base |
| 33612 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33613 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33614 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33615 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33616 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 33617 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 33618 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 33619 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq), |
| 33620 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33621 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33622 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33623 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33624 | GIR_RootConstrainSelectedInstOperands, |
| 33625 | // GIR_Coverage, 5161, |
| 33626 | GIR_EraseRootFromParent_Done, |
| 33627 | // Label 1726: @92185 |
| 33628 | GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(92246), // Rule ID 5164 // |
| 33629 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33630 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 33631 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 33632 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33633 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33634 | // MIs[0] base |
| 33635 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33636 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33637 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33638 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33639 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 33640 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33641 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 33642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq_u), |
| 33643 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33644 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33645 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33646 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33647 | GIR_RootConstrainSelectedInstOperands, |
| 33648 | // GIR_Coverage, 5164, |
| 33649 | GIR_EraseRootFromParent_Done, |
| 33650 | // Label 1727: @92246 |
| 33651 | GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(92307), // Rule ID 5165 // |
| 33652 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33653 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 33654 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 33655 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33656 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33657 | // MIs[0] base |
| 33658 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33659 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33660 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33661 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33662 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 33663 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 33664 | // (intrinsic_void 3385:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] }) => (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 33665 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq), |
| 33666 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33667 | GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33668 | GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33669 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33670 | GIR_RootConstrainSelectedInstOperands, |
| 33671 | // GIR_Coverage, 5165, |
| 33672 | GIR_EraseRootFromParent_Done, |
| 33673 | // Label 1728: @92307 |
| 33674 | GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(92371), // Rule ID 265 // |
| 33675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 33676 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr), |
| 33677 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33678 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33679 | // MIs[0] cop |
| 33680 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 33681 | // MIs[0] opc1 |
| 33682 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33683 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33684 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33685 | // MIs[0] CRm |
| 33686 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 33687 | // (intrinsic_void 3188:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 33688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR), |
| 33689 | GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 33690 | GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 33691 | GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 33692 | GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 33693 | GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 33694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33695 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33696 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33697 | GIR_RootConstrainSelectedInstOperands, |
| 33698 | // GIR_Coverage, 265, |
| 33699 | GIR_EraseRootFromParent_Done, |
| 33700 | // Label 1729: @92371 |
| 33701 | GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(92426), // Rule ID 266 // |
| 33702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8), |
| 33703 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2), |
| 33704 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33705 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33706 | // MIs[0] cop |
| 33707 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 33708 | // MIs[0] opc1 |
| 33709 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33710 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33711 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33712 | // MIs[0] CRm |
| 33713 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 33714 | // (intrinsic_void 3189:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 33715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR2), |
| 33716 | GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 33717 | GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 33718 | GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 33719 | GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 33720 | GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 33721 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33722 | GIR_RootConstrainSelectedInstOperands, |
| 33723 | // GIR_Coverage, 266, |
| 33724 | GIR_EraseRootFromParent_Done, |
| 33725 | // Label 1730: @92426 |
| 33726 | GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(92490), // Rule ID 613 // |
| 33727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 33728 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr), |
| 33729 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33730 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33731 | // MIs[0] cop |
| 33732 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 33733 | // MIs[0] opc1 |
| 33734 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33735 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33736 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33737 | // MIs[0] CRm |
| 33738 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 33739 | // (intrinsic_void 3188:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 33740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR), |
| 33741 | GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 33742 | GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 33743 | GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 33744 | GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 33745 | GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 33746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33747 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33748 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33749 | GIR_RootConstrainSelectedInstOperands, |
| 33750 | // GIR_Coverage, 613, |
| 33751 | GIR_EraseRootFromParent_Done, |
| 33752 | // Label 1731: @92490 |
| 33753 | GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(92554), // Rule ID 614 // |
| 33754 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8), |
| 33755 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2), |
| 33756 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33757 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33758 | // MIs[0] cop |
| 33759 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 33760 | // MIs[0] opc1 |
| 33761 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33762 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33763 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33764 | // MIs[0] CRm |
| 33765 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 33766 | // (intrinsic_void 3189:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 33767 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR2), |
| 33768 | GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 33769 | GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 33770 | GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 33771 | GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 33772 | GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 33773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33774 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33775 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33776 | GIR_RootConstrainSelectedInstOperands, |
| 33777 | // GIR_Coverage, 614, |
| 33778 | GIR_EraseRootFromParent_Done, |
| 33779 | // Label 1732: @92554 |
| 33780 | GIM_Reject, |
| 33781 | // Label 1713: @92555 |
| 33782 | GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(95906), |
| 33783 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 33784 | GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(92624), // Rule ID 253 // |
| 33785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8), |
| 33786 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp), |
| 33787 | // MIs[0] cop |
| 33788 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 33789 | // MIs[0] opc1 |
| 33790 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33791 | // MIs[0] CRd |
| 33792 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 33793 | // MIs[0] CRn |
| 33794 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 33795 | // MIs[0] CRm |
| 33796 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 33797 | // MIs[0] opc2 |
| 33798 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 33799 | // (intrinsic_void 3156:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 33800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP), |
| 33801 | GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 33802 | GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 33803 | GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 33804 | GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 33805 | GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 33806 | GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 33807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33808 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33809 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33810 | GIR_RootConstrainSelectedInstOperands, |
| 33811 | // GIR_Coverage, 253, |
| 33812 | GIR_EraseRootFromParent_Done, |
| 33813 | // Label 1734: @92624 |
| 33814 | GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(92676), // Rule ID 254 // |
| 33815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8), |
| 33816 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2), |
| 33817 | // MIs[0] cop |
| 33818 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 33819 | // MIs[0] opc1 |
| 33820 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33821 | // MIs[0] CRd |
| 33822 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 33823 | // MIs[0] CRn |
| 33824 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 33825 | // MIs[0] CRm |
| 33826 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 33827 | // MIs[0] opc2 |
| 33828 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 33829 | // (intrinsic_void 3157:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 33830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP2), |
| 33831 | GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 33832 | GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 33833 | GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 33834 | GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 33835 | GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 33836 | GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 33837 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33838 | GIR_RootConstrainSelectedInstOperands, |
| 33839 | // GIR_Coverage, 254, |
| 33840 | GIR_EraseRootFromParent_Done, |
| 33841 | // Label 1735: @92676 |
| 33842 | GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(92737), // Rule ID 615 // |
| 33843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8), |
| 33844 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp), |
| 33845 | // MIs[0] cop |
| 33846 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 33847 | // MIs[0] opc1 |
| 33848 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33849 | // MIs[0] CRd |
| 33850 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 33851 | // MIs[0] CRn |
| 33852 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 33853 | // MIs[0] CRm |
| 33854 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 33855 | // MIs[0] opc2 |
| 33856 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 33857 | // (intrinsic_void 3156:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 33858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP), |
| 33859 | GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 33860 | GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 33861 | GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 33862 | GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 33863 | GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 33864 | GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 33865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33866 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33867 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33868 | GIR_RootConstrainSelectedInstOperands, |
| 33869 | // GIR_Coverage, 615, |
| 33870 | GIR_EraseRootFromParent_Done, |
| 33871 | // Label 1736: @92737 |
| 33872 | GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(92798), // Rule ID 616 // |
| 33873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8), |
| 33874 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2), |
| 33875 | // MIs[0] cop |
| 33876 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 33877 | // MIs[0] opc1 |
| 33878 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33879 | // MIs[0] CRd |
| 33880 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 33881 | // MIs[0] CRn |
| 33882 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 33883 | // MIs[0] CRm |
| 33884 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 33885 | // MIs[0] opc2 |
| 33886 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 33887 | // (intrinsic_void 3157:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 33888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP2), |
| 33889 | GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 33890 | GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 33891 | GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 33892 | GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 33893 | GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 33894 | GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 33895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33896 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33897 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33898 | GIR_RootConstrainSelectedInstOperands, |
| 33899 | // GIR_Coverage, 616, |
| 33900 | GIR_EraseRootFromParent_Done, |
| 33901 | // Label 1737: @92798 |
| 33902 | GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(92866), // Rule ID 5054 // |
| 33903 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 33904 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 33905 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33906 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33907 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33908 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33910 | // MIs[0] base |
| 33911 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 33912 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33913 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33914 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33915 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33916 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33917 | // (intrinsic_w_chain:{ *:[v8i16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 33919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33920 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 33921 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 33922 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33923 | GIR_RootConstrainSelectedInstOperands, |
| 33924 | // GIR_Coverage, 5054, |
| 33925 | GIR_EraseRootFromParent_Done, |
| 33926 | // Label 1738: @92866 |
| 33927 | GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(92934), // Rule ID 5055 // |
| 33928 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 33929 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 33930 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33931 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33932 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33933 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33934 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33935 | // MIs[0] base |
| 33936 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 33937 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33938 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33939 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33940 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33941 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33942 | // (intrinsic_w_chain:{ *:[v8i16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 33944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33945 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 33946 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 33947 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33948 | GIR_RootConstrainSelectedInstOperands, |
| 33949 | // GIR_Coverage, 5055, |
| 33950 | GIR_EraseRootFromParent_Done, |
| 33951 | // Label 1739: @92934 |
| 33952 | GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(93002), // Rule ID 5058 // |
| 33953 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 33954 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33955 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33956 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33957 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33958 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33959 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33960 | // MIs[0] base |
| 33961 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 33962 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33963 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33964 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 33965 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33966 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 33967 | // (intrinsic_w_chain:{ *:[v16i8] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 33968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq), |
| 33969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33970 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 33971 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 33972 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33973 | GIR_RootConstrainSelectedInstOperands, |
| 33974 | // GIR_Coverage, 5058, |
| 33975 | GIR_EraseRootFromParent_Done, |
| 33976 | // Label 1740: @93002 |
| 33977 | GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(93070), // Rule ID 5066 // |
| 33978 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 33979 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33980 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33981 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33982 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33983 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 33984 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33985 | // MIs[0] base |
| 33986 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 33987 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33988 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33989 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 33990 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33991 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 33992 | // (intrinsic_w_chain:{ *:[v16i8] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 33993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq), |
| 33994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33995 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 33996 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 33997 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33998 | GIR_RootConstrainSelectedInstOperands, |
| 33999 | // GIR_Coverage, 5066, |
| 34000 | GIR_EraseRootFromParent_Done, |
| 34001 | // Label 1741: @93070 |
| 34002 | GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(93138), // Rule ID 5068 // |
| 34003 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34004 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34005 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34006 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34007 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34008 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34009 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34010 | // MIs[0] base |
| 34011 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34012 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34013 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34014 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34015 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34016 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34017 | // (intrinsic_w_chain:{ *:[v8i16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34018 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU16_rq), |
| 34019 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34020 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34021 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34022 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34023 | GIR_RootConstrainSelectedInstOperands, |
| 34024 | // GIR_Coverage, 5068, |
| 34025 | GIR_EraseRootFromParent_Done, |
| 34026 | // Label 1742: @93138 |
| 34027 | GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(93206), // Rule ID 5070 // |
| 34028 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34029 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34030 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34031 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34032 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34033 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34035 | // MIs[0] base |
| 34036 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34037 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34038 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34039 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34040 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34041 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34042 | // (intrinsic_w_chain:{ *:[v8i16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS16_rq), |
| 34044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34045 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34046 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34047 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34048 | GIR_RootConstrainSelectedInstOperands, |
| 34049 | // GIR_Coverage, 5070, |
| 34050 | GIR_EraseRootFromParent_Done, |
| 34051 | // Label 1743: @93206 |
| 34052 | GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(93274), // Rule ID 5072 // |
| 34053 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34054 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34055 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34056 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34057 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34058 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34059 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34060 | // MIs[0] base |
| 34061 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34062 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34063 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34064 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34065 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34066 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34067 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU32_rq), |
| 34069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34070 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34071 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34072 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34073 | GIR_RootConstrainSelectedInstOperands, |
| 34074 | // GIR_Coverage, 5072, |
| 34075 | GIR_EraseRootFromParent_Done, |
| 34076 | // Label 1744: @93274 |
| 34077 | GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(93342), // Rule ID 5074 // |
| 34078 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34079 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34080 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34081 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34082 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34083 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34085 | // MIs[0] base |
| 34086 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34087 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34088 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34089 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34090 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34091 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34092 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS32_rq), |
| 34094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34095 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34096 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34097 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34098 | GIR_RootConstrainSelectedInstOperands, |
| 34099 | // GIR_Coverage, 5074, |
| 34100 | GIR_EraseRootFromParent_Done, |
| 34101 | // Label 1745: @93342 |
| 34102 | GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(93410), // Rule ID 5076 // |
| 34103 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34104 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34105 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34106 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34107 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34108 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34109 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34110 | // MIs[0] base |
| 34111 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34112 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34113 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34114 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34115 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34116 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34117 | // (intrinsic_w_chain:{ *:[v8i16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34120 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34121 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34122 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34123 | GIR_RootConstrainSelectedInstOperands, |
| 34124 | // GIR_Coverage, 5076, |
| 34125 | GIR_EraseRootFromParent_Done, |
| 34126 | // Label 1746: @93410 |
| 34127 | GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(93478), // Rule ID 5077 // |
| 34128 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34129 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34130 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34131 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34132 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34133 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34135 | // MIs[0] base |
| 34136 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34137 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34138 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34139 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34140 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34141 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34142 | // (intrinsic_w_chain:{ *:[v8i16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34144 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34145 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34146 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34147 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34148 | GIR_RootConstrainSelectedInstOperands, |
| 34149 | // GIR_Coverage, 5077, |
| 34150 | GIR_EraseRootFromParent_Done, |
| 34151 | // Label 1747: @93478 |
| 34152 | GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(93546), // Rule ID 5080 // |
| 34153 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34154 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34155 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34156 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34157 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34158 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34160 | // MIs[0] base |
| 34161 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34162 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34163 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34164 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34165 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34166 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34167 | // (intrinsic_w_chain:{ *:[v8i16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34169 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34170 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34171 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34172 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34173 | GIR_RootConstrainSelectedInstOperands, |
| 34174 | // GIR_Coverage, 5080, |
| 34175 | GIR_EraseRootFromParent_Done, |
| 34176 | // Label 1748: @93546 |
| 34177 | GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(93614), // Rule ID 5081 // |
| 34178 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34179 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34180 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34181 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34182 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34183 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34185 | // MIs[0] base |
| 34186 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34187 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34188 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34189 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34190 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34191 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34192 | // (intrinsic_w_chain:{ *:[v8i16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34194 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34195 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34196 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34197 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34198 | GIR_RootConstrainSelectedInstOperands, |
| 34199 | // GIR_Coverage, 5081, |
| 34200 | GIR_EraseRootFromParent_Done, |
| 34201 | // Label 1749: @93614 |
| 34202 | GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(93682), // Rule ID 5084 // |
| 34203 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34204 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34205 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34206 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34207 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34208 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34209 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34210 | // MIs[0] base |
| 34211 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34212 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34213 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34214 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34215 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34216 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34217 | // (intrinsic_w_chain:{ *:[v8i16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34220 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34221 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34222 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34223 | GIR_RootConstrainSelectedInstOperands, |
| 34224 | // GIR_Coverage, 5084, |
| 34225 | GIR_EraseRootFromParent_Done, |
| 34226 | // Label 1750: @93682 |
| 34227 | GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(93750), // Rule ID 5085 // |
| 34228 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34229 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34230 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34231 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34232 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34233 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34235 | // MIs[0] base |
| 34236 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34237 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34238 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34239 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34240 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34241 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34242 | // (intrinsic_w_chain:{ *:[v8i16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34245 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34246 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34247 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34248 | GIR_RootConstrainSelectedInstOperands, |
| 34249 | // GIR_Coverage, 5085, |
| 34250 | GIR_EraseRootFromParent_Done, |
| 34251 | // Label 1751: @93750 |
| 34252 | GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(93818), // Rule ID 5088 // |
| 34253 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34254 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34255 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34256 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34257 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34258 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34259 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34260 | // MIs[0] base |
| 34261 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34262 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34263 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34264 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34265 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34266 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34267 | // (intrinsic_w_chain:{ *:[v8f16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34270 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34271 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34272 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34273 | GIR_RootConstrainSelectedInstOperands, |
| 34274 | // GIR_Coverage, 5088, |
| 34275 | GIR_EraseRootFromParent_Done, |
| 34276 | // Label 1752: @93818 |
| 34277 | GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(93886), // Rule ID 5089 // |
| 34278 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34279 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34280 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34281 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34282 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34283 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34284 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34285 | // MIs[0] base |
| 34286 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34287 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34288 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34289 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34290 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34291 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34292 | // (intrinsic_w_chain:{ *:[v8f16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34295 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34296 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34297 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34298 | GIR_RootConstrainSelectedInstOperands, |
| 34299 | // GIR_Coverage, 5089, |
| 34300 | GIR_EraseRootFromParent_Done, |
| 34301 | // Label 1753: @93886 |
| 34302 | GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(93954), // Rule ID 5092 // |
| 34303 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34304 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34305 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34306 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34307 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34308 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34309 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34310 | // MIs[0] base |
| 34311 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34312 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34313 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34314 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34315 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34316 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34317 | // (intrinsic_w_chain:{ *:[v8f16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34318 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34319 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34320 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34321 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34322 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34323 | GIR_RootConstrainSelectedInstOperands, |
| 34324 | // GIR_Coverage, 5092, |
| 34325 | GIR_EraseRootFromParent_Done, |
| 34326 | // Label 1754: @93954 |
| 34327 | GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(94022), // Rule ID 5093 // |
| 34328 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34329 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34330 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34331 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34332 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34333 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34335 | // MIs[0] base |
| 34336 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34337 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34338 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34339 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34340 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34341 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34342 | // (intrinsic_w_chain:{ *:[v8f16] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34345 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34346 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34347 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34348 | GIR_RootConstrainSelectedInstOperands, |
| 34349 | // GIR_Coverage, 5093, |
| 34350 | GIR_EraseRootFromParent_Done, |
| 34351 | // Label 1755: @94022 |
| 34352 | GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(94090), // Rule ID 5096 // |
| 34353 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34354 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34355 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34356 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34357 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34358 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34359 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34360 | // MIs[0] base |
| 34361 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34362 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34363 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34364 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34365 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34366 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34367 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq_u), |
| 34369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34370 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34371 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34372 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34373 | GIR_RootConstrainSelectedInstOperands, |
| 34374 | // GIR_Coverage, 5096, |
| 34375 | GIR_EraseRootFromParent_Done, |
| 34376 | // Label 1756: @94090 |
| 34377 | GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(94158), // Rule ID 5097 // |
| 34378 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34379 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34380 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34381 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34382 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34383 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34385 | // MIs[0] base |
| 34386 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34387 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34388 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34389 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34390 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34391 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34392 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq), |
| 34394 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34395 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34396 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34397 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34398 | GIR_RootConstrainSelectedInstOperands, |
| 34399 | // GIR_Coverage, 5097, |
| 34400 | GIR_EraseRootFromParent_Done, |
| 34401 | // Label 1757: @94158 |
| 34402 | GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(94226), // Rule ID 5100 // |
| 34403 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34404 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34405 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34406 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34407 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34408 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34409 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34410 | // MIs[0] base |
| 34411 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34412 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34413 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34414 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34415 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34416 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34417 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34418 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq_u), |
| 34419 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34420 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34421 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34422 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34423 | GIR_RootConstrainSelectedInstOperands, |
| 34424 | // GIR_Coverage, 5100, |
| 34425 | GIR_EraseRootFromParent_Done, |
| 34426 | // Label 1758: @94226 |
| 34427 | GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(94294), // Rule ID 5101 // |
| 34428 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34429 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34430 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34431 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34432 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34433 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34434 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34435 | // MIs[0] base |
| 34436 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34437 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34438 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34439 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34440 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34441 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34442 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34443 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq), |
| 34444 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34445 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34446 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34447 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34448 | GIR_RootConstrainSelectedInstOperands, |
| 34449 | // GIR_Coverage, 5101, |
| 34450 | GIR_EraseRootFromParent_Done, |
| 34451 | // Label 1759: @94294 |
| 34452 | GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(94362), // Rule ID 5104 // |
| 34453 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34454 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34455 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34456 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34457 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34458 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34459 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34460 | // MIs[0] base |
| 34461 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34462 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34463 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34464 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34465 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34466 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34467 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34470 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34471 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34472 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34473 | GIR_RootConstrainSelectedInstOperands, |
| 34474 | // GIR_Coverage, 5104, |
| 34475 | GIR_EraseRootFromParent_Done, |
| 34476 | // Label 1760: @94362 |
| 34477 | GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(94430), // Rule ID 5105 // |
| 34478 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34479 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34480 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34481 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34482 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34483 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34485 | // MIs[0] base |
| 34486 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34487 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34488 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34489 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34490 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34491 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34492 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34494 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34495 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34496 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34497 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34498 | GIR_RootConstrainSelectedInstOperands, |
| 34499 | // GIR_Coverage, 5105, |
| 34500 | GIR_EraseRootFromParent_Done, |
| 34501 | // Label 1761: @94430 |
| 34502 | GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(94498), // Rule ID 5108 // |
| 34503 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34504 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34505 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34506 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34507 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34508 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34509 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34510 | // MIs[0] base |
| 34511 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34512 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34513 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34514 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34515 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34516 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34517 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34520 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34521 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34522 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34523 | GIR_RootConstrainSelectedInstOperands, |
| 34524 | // GIR_Coverage, 5108, |
| 34525 | GIR_EraseRootFromParent_Done, |
| 34526 | // Label 1762: @94498 |
| 34527 | GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(94566), // Rule ID 5109 // |
| 34528 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34529 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34530 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34531 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34532 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34533 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34535 | // MIs[0] base |
| 34536 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34537 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34538 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34539 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34540 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34541 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34542 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34545 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34546 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34547 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34548 | GIR_RootConstrainSelectedInstOperands, |
| 34549 | // GIR_Coverage, 5109, |
| 34550 | GIR_EraseRootFromParent_Done, |
| 34551 | // Label 1763: @94566 |
| 34552 | GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(94634), // Rule ID 5112 // |
| 34553 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34554 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34555 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34556 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34557 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34558 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34559 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34560 | // MIs[0] base |
| 34561 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34562 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34563 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34564 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34565 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34566 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34567 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34570 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34571 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34572 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34573 | GIR_RootConstrainSelectedInstOperands, |
| 34574 | // GIR_Coverage, 5112, |
| 34575 | GIR_EraseRootFromParent_Done, |
| 34576 | // Label 1764: @94634 |
| 34577 | GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(94702), // Rule ID 5113 // |
| 34578 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34579 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34580 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34581 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34582 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34583 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34585 | // MIs[0] base |
| 34586 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34587 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34588 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34589 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34590 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34591 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34592 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34593 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34594 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34595 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34596 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34597 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34598 | GIR_RootConstrainSelectedInstOperands, |
| 34599 | // GIR_Coverage, 5113, |
| 34600 | GIR_EraseRootFromParent_Done, |
| 34601 | // Label 1765: @94702 |
| 34602 | GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(94770), // Rule ID 5116 // |
| 34603 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34604 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34605 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34606 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34607 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34608 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34609 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34610 | // MIs[0] base |
| 34611 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34612 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34613 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34614 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34615 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34616 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34617 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34620 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34621 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34622 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34623 | GIR_RootConstrainSelectedInstOperands, |
| 34624 | // GIR_Coverage, 5116, |
| 34625 | GIR_EraseRootFromParent_Done, |
| 34626 | // Label 1766: @94770 |
| 34627 | GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(94838), // Rule ID 5117 // |
| 34628 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34629 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34630 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34631 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34632 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34633 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34635 | // MIs[0] base |
| 34636 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34637 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34638 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34639 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34640 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34641 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34642 | // (intrinsic_w_chain:{ *:[v4i32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34643 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34644 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34645 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34646 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34647 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34648 | GIR_RootConstrainSelectedInstOperands, |
| 34649 | // GIR_Coverage, 5117, |
| 34650 | GIR_EraseRootFromParent_Done, |
| 34651 | // Label 1767: @94838 |
| 34652 | GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(94906), // Rule ID 5120 // |
| 34653 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34654 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34655 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34656 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34657 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34658 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34659 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34660 | // MIs[0] base |
| 34661 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34662 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34663 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34664 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34665 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34666 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34667 | // (intrinsic_w_chain:{ *:[v4f32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34670 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34671 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34672 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34673 | GIR_RootConstrainSelectedInstOperands, |
| 34674 | // GIR_Coverage, 5120, |
| 34675 | GIR_EraseRootFromParent_Done, |
| 34676 | // Label 1768: @94906 |
| 34677 | GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(94974), // Rule ID 5121 // |
| 34678 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34679 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34680 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34681 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34682 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34683 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34684 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34685 | // MIs[0] base |
| 34686 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34687 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34688 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34689 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34690 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34691 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34692 | // (intrinsic_w_chain:{ *:[v4f32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34694 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34695 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34696 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34697 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34698 | GIR_RootConstrainSelectedInstOperands, |
| 34699 | // GIR_Coverage, 5121, |
| 34700 | GIR_EraseRootFromParent_Done, |
| 34701 | // Label 1769: @94974 |
| 34702 | GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(95042), // Rule ID 5124 // |
| 34703 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34704 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34705 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34706 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34707 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34708 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34709 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34710 | // MIs[0] base |
| 34711 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34712 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34713 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34714 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34715 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34716 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34717 | // (intrinsic_w_chain:{ *:[v4f32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34720 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34721 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34722 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34723 | GIR_RootConstrainSelectedInstOperands, |
| 34724 | // GIR_Coverage, 5124, |
| 34725 | GIR_EraseRootFromParent_Done, |
| 34726 | // Label 1770: @95042 |
| 34727 | GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(95110), // Rule ID 5125 // |
| 34728 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34729 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34730 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34731 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34732 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34733 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34735 | // MIs[0] base |
| 34736 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34737 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34738 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34739 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34740 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34741 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34742 | // (intrinsic_w_chain:{ *:[v4f32] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34745 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34746 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34747 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34748 | GIR_RootConstrainSelectedInstOperands, |
| 34749 | // GIR_Coverage, 5125, |
| 34750 | GIR_EraseRootFromParent_Done, |
| 34751 | // Label 1771: @95110 |
| 34752 | GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(95178), // Rule ID 5128 // |
| 34753 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34754 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 34755 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34756 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34757 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34758 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34759 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34760 | // MIs[0] base |
| 34761 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34762 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34763 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34764 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34765 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34766 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34767 | // (intrinsic_w_chain:{ *:[v2i64] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 34769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34770 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34771 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34772 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34773 | GIR_RootConstrainSelectedInstOperands, |
| 34774 | // GIR_Coverage, 5128, |
| 34775 | GIR_EraseRootFromParent_Done, |
| 34776 | // Label 1772: @95178 |
| 34777 | GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(95246), // Rule ID 5129 // |
| 34778 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34779 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 34780 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34781 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34782 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34783 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34785 | // MIs[0] base |
| 34786 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34787 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34788 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34789 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34790 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 34791 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34792 | // (intrinsic_w_chain:{ *:[v2i64] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 34794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34795 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34796 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34797 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34798 | GIR_RootConstrainSelectedInstOperands, |
| 34799 | // GIR_Coverage, 5129, |
| 34800 | GIR_EraseRootFromParent_Done, |
| 34801 | // Label 1773: @95246 |
| 34802 | GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(95314), // Rule ID 5132 // |
| 34803 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34804 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 34805 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34806 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34807 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34808 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34810 | // MIs[0] base |
| 34811 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34812 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34813 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34814 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34815 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34816 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34817 | // (intrinsic_w_chain:{ *:[v2i64] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 34819 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34820 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34821 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34822 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34823 | GIR_RootConstrainSelectedInstOperands, |
| 34824 | // GIR_Coverage, 5132, |
| 34825 | GIR_EraseRootFromParent_Done, |
| 34826 | // Label 1774: @95314 |
| 34827 | GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(95382), // Rule ID 5133 // |
| 34828 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34829 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 34830 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34831 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34832 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34833 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34834 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34835 | // MIs[0] base |
| 34836 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34837 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34838 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34839 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34840 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 34841 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34842 | // (intrinsic_w_chain:{ *:[v2i64] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 34844 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34845 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34846 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34847 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34848 | GIR_RootConstrainSelectedInstOperands, |
| 34849 | // GIR_Coverage, 5133, |
| 34850 | GIR_EraseRootFromParent_Done, |
| 34851 | // Label 1775: @95382 |
| 34852 | GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(95450), // Rule ID 5136 // |
| 34853 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34854 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 34855 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34856 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34857 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34858 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34860 | // MIs[0] base |
| 34861 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34862 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34863 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34864 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34865 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34866 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34867 | // (intrinsic_w_chain:{ *:[v2i64] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 34869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34870 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34871 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34872 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34873 | GIR_RootConstrainSelectedInstOperands, |
| 34874 | // GIR_Coverage, 5136, |
| 34875 | GIR_EraseRootFromParent_Done, |
| 34876 | // Label 1776: @95450 |
| 34877 | GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(95518), // Rule ID 5137 // |
| 34878 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34879 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 34880 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34881 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34882 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34883 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34884 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34885 | // MIs[0] base |
| 34886 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34887 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34888 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34889 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34890 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 34891 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34892 | // (intrinsic_w_chain:{ *:[v2i64] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 34894 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34895 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34896 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34897 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34898 | GIR_RootConstrainSelectedInstOperands, |
| 34899 | // GIR_Coverage, 5137, |
| 34900 | GIR_EraseRootFromParent_Done, |
| 34901 | // Label 1777: @95518 |
| 34902 | GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(95586), // Rule ID 5140 // |
| 34903 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34904 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 34905 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34906 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34907 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34908 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34910 | // MIs[0] base |
| 34911 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34912 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34913 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34914 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34915 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34916 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34917 | // (intrinsic_w_chain:{ *:[v2i64] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 34919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34920 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34921 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34922 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34923 | GIR_RootConstrainSelectedInstOperands, |
| 34924 | // GIR_Coverage, 5140, |
| 34925 | GIR_EraseRootFromParent_Done, |
| 34926 | // Label 1778: @95586 |
| 34927 | GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(95654), // Rule ID 5141 // |
| 34928 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34929 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 34930 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34931 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34932 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34933 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34934 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34935 | // MIs[0] base |
| 34936 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34937 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34938 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34939 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34940 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 34941 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34942 | // (intrinsic_w_chain:{ *:[v2i64] } 3311:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 34944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34945 | GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34946 | GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34947 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34948 | GIR_RootConstrainSelectedInstOperands, |
| 34949 | // GIR_Coverage, 5141, |
| 34950 | GIR_EraseRootFromParent_Done, |
| 34951 | // Label 1779: @95654 |
| 34952 | GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(95719), // Rule ID 263 // |
| 34953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 34954 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr), |
| 34955 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34956 | // MIs[0] cop |
| 34957 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34958 | // MIs[0] opc1 |
| 34959 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34960 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34961 | // MIs[0] CRn |
| 34962 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34963 | // MIs[0] CRm |
| 34964 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34965 | // MIs[0] opc2 |
| 34966 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34967 | // (intrinsic_void 3186:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR), |
| 34969 | GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34970 | GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34971 | GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 34972 | GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 34973 | GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34974 | GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 34975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34976 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34977 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34978 | GIR_RootConstrainSelectedInstOperands, |
| 34979 | // GIR_Coverage, 263, |
| 34980 | GIR_EraseRootFromParent_Done, |
| 34981 | // Label 1780: @95719 |
| 34982 | GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(95775), // Rule ID 264 // |
| 34983 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8), |
| 34984 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2), |
| 34985 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34986 | // MIs[0] cop |
| 34987 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34988 | // MIs[0] opc1 |
| 34989 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34990 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34991 | // MIs[0] CRn |
| 34992 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34993 | // MIs[0] CRm |
| 34994 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34995 | // MIs[0] opc2 |
| 34996 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34997 | // (intrinsic_void 3187:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR2), |
| 34999 | GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35000 | GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35001 | GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35002 | GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35003 | GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35004 | GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35005 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35006 | GIR_RootConstrainSelectedInstOperands, |
| 35007 | // GIR_Coverage, 264, |
| 35008 | GIR_EraseRootFromParent_Done, |
| 35009 | // Label 1781: @95775 |
| 35010 | GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(95840), // Rule ID 611 // |
| 35011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35012 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr), |
| 35013 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35014 | // MIs[0] cop |
| 35015 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35016 | // MIs[0] opc1 |
| 35017 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35018 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35019 | // MIs[0] CRn |
| 35020 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35021 | // MIs[0] CRm |
| 35022 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35023 | // MIs[0] opc2 |
| 35024 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35025 | // (intrinsic_void 3186:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR), |
| 35027 | GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35028 | GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35029 | GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35030 | GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35031 | GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35032 | GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35034 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35035 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35036 | GIR_RootConstrainSelectedInstOperands, |
| 35037 | // GIR_Coverage, 611, |
| 35038 | GIR_EraseRootFromParent_Done, |
| 35039 | // Label 1782: @95840 |
| 35040 | GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(95905), // Rule ID 612 // |
| 35041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8), |
| 35042 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2), |
| 35043 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35044 | // MIs[0] cop |
| 35045 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35046 | // MIs[0] opc1 |
| 35047 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35048 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35049 | // MIs[0] CRn |
| 35050 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35051 | // MIs[0] CRm |
| 35052 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35053 | // MIs[0] opc2 |
| 35054 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35055 | // (intrinsic_void 3187:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR2), |
| 35057 | GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35058 | GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35059 | GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35060 | GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35061 | GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35062 | GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35064 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35065 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35066 | GIR_RootConstrainSelectedInstOperands, |
| 35067 | // GIR_Coverage, 612, |
| 35068 | GIR_EraseRootFromParent_Done, |
| 35069 | // Label 1783: @95905 |
| 35070 | GIM_Reject, |
| 35071 | // Label 1733: @95906 |
| 35072 | GIM_Reject, |
| 35073 | // Label 15: @95907 |
| 35074 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 1787*/ GIMT_Encode4(96064), |
| 35075 | /*GILLT_v2s64*//*Label 1784*/ GIMT_Encode4(95950), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35076 | /*GILLT_v4s32*//*Label 1785*/ GIMT_Encode4(95988), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35077 | /*GILLT_v8s16*//*Label 1786*/ GIMT_Encode4(96026), |
| 35078 | // Label 1784: @95950 |
| 35079 | GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(95987), // Rule ID 2679 // |
| 35080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35081 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35083 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35084 | // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 35085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64), |
| 35086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35087 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35089 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35090 | GIR_RootConstrainSelectedInstOperands, |
| 35091 | // GIR_Coverage, 2679, |
| 35092 | GIR_EraseRootFromParent_Done, |
| 35093 | // Label 1788: @95987 |
| 35094 | GIM_Reject, |
| 35095 | // Label 1785: @95988 |
| 35096 | GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(96025), // Rule ID 2678 // |
| 35097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35098 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35099 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35100 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35101 | // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 35102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32), |
| 35103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35104 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35106 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35107 | GIR_RootConstrainSelectedInstOperands, |
| 35108 | // GIR_Coverage, 2678, |
| 35109 | GIR_EraseRootFromParent_Done, |
| 35110 | // Label 1789: @96025 |
| 35111 | GIM_Reject, |
| 35112 | // Label 1786: @96026 |
| 35113 | GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(96063), // Rule ID 2677 // |
| 35114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35115 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35117 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35118 | // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 35119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16), |
| 35120 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35121 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35123 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35124 | GIR_RootConstrainSelectedInstOperands, |
| 35125 | // GIR_Coverage, 2677, |
| 35126 | GIR_EraseRootFromParent_Done, |
| 35127 | // Label 1790: @96063 |
| 35128 | GIM_Reject, |
| 35129 | // Label 1787: @96064 |
| 35130 | GIM_Reject, |
| 35131 | // Label 16: @96065 |
| 35132 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(12), /*)*//*default:*//*Label 1794*/ GIMT_Encode4(96222), |
| 35133 | /*GILLT_v2s32*//*Label 1791*/ GIMT_Encode4(96108), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35134 | /*GILLT_v4s16*//*Label 1792*/ GIMT_Encode4(96146), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35135 | /*GILLT_v8s8*//*Label 1793*/ GIMT_Encode4(96184), |
| 35136 | // Label 1791: @96108 |
| 35137 | GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(96145), // Rule ID 1607 // |
| 35138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35139 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 35140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35141 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35142 | // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) => (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 35143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv2i32), |
| 35144 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35145 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35147 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35148 | GIR_RootConstrainSelectedInstOperands, |
| 35149 | // GIR_Coverage, 1607, |
| 35150 | GIR_EraseRootFromParent_Done, |
| 35151 | // Label 1795: @96145 |
| 35152 | GIM_Reject, |
| 35153 | // Label 1792: @96146 |
| 35154 | GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(96183), // Rule ID 1606 // |
| 35155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35156 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 35157 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35158 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35159 | // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) => (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 35160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv4i16), |
| 35161 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35162 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35164 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35165 | GIR_RootConstrainSelectedInstOperands, |
| 35166 | // GIR_Coverage, 1606, |
| 35167 | GIR_EraseRootFromParent_Done, |
| 35168 | // Label 1796: @96183 |
| 35169 | GIM_Reject, |
| 35170 | // Label 1793: @96184 |
| 35171 | GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(96221), // Rule ID 1605 // |
| 35172 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35173 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 35174 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35175 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35176 | // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) => (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 35177 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv8i8), |
| 35178 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35179 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35180 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35181 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35182 | GIR_RootConstrainSelectedInstOperands, |
| 35183 | // GIR_Coverage, 1605, |
| 35184 | GIR_EraseRootFromParent_Done, |
| 35185 | // Label 1797: @96221 |
| 35186 | GIM_Reject, |
| 35187 | // Label 1794: @96222 |
| 35188 | GIM_Reject, |
| 35189 | // Label 17: @96223 |
| 35190 | GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(96502), |
| 35191 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35192 | GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(96272), // Rule ID 412 // |
| 35193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35194 | GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 35195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35196 | // MIs[0] Operand 1 |
| 35197 | // No operand predicates |
| 35198 | // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm => (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 35200 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35201 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35203 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35204 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35205 | GIR_RootConstrainSelectedInstOperands, |
| 35206 | // GIR_Coverage, 412, |
| 35207 | GIR_EraseRootFromParent_Done, |
| 35208 | // Label 1799: @96272 |
| 35209 | GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(96313), // Rule ID 57 // |
| 35210 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35211 | GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 35212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35213 | // MIs[0] Operand 1 |
| 35214 | // No operand predicates |
| 35215 | // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm => (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi), |
| 35217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35218 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35220 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35221 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35222 | GIR_RootConstrainSelectedInstOperands, |
| 35223 | // GIR_Coverage, 57, |
| 35224 | GIR_EraseRootFromParent_Done, |
| 35225 | // Label 1800: @96313 |
| 35226 | GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(96348), // Rule ID 58 // |
| 35227 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), |
| 35228 | GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 35229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35230 | // MIs[0] Operand 1 |
| 35231 | // No operand predicates |
| 35232 | // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35233 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi16), |
| 35234 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35235 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35237 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35238 | GIR_RootConstrainSelectedInstOperands, |
| 35239 | // GIR_Coverage, 58, |
| 35240 | GIR_EraseRootFromParent_Done, |
| 35241 | // Label 1801: @96348 |
| 35242 | GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(96391), // Rule ID 168 // |
| 35243 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35244 | GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not), |
| 35245 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35246 | // MIs[0] Operand 1 |
| 35247 | // No operand predicates |
| 35248 | // (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm => (MVNi:{ *:[i32] } (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) |
| 35249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNi), |
| 35250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35251 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm |
| 35252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35253 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35254 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35255 | GIR_RootConstrainSelectedInstOperands, |
| 35256 | // GIR_Coverage, 168, |
| 35257 | GIR_EraseRootFromParent_Done, |
| 35258 | // Label 1802: @96391 |
| 35259 | GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(96417), // Rule ID 275 // |
| 35260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35261 | GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_arm_i32imm), |
| 35262 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35263 | // MIs[0] Operand 1 |
| 35264 | // No operand predicates |
| 35265 | // (imm:{ *:[i32] })<<P:Predicate_arm_i32imm>>:$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 35266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi32imm), |
| 35267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 35268 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 35269 | GIR_RootConstrainSelectedInstOperands, |
| 35270 | // GIR_Coverage, 275, |
| 35271 | GIR_EraseRootFromParent_Done, |
| 35272 | // Label 1803: @96417 |
| 35273 | GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(96452), // Rule ID 413 // |
| 35274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), |
| 35275 | GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 35276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35277 | // MIs[0] Operand 1 |
| 35278 | // No operand predicates |
| 35279 | // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 35281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35282 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35284 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35285 | GIR_RootConstrainSelectedInstOperands, |
| 35286 | // GIR_Coverage, 413, |
| 35287 | GIR_EraseRootFromParent_Done, |
| 35288 | // Label 1804: @96452 |
| 35289 | GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(96501), |
| 35290 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35291 | GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(96482), // Rule ID 361 // |
| 35292 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only), |
| 35293 | // MIs[0] Operand 1 |
| 35294 | // No operand predicates |
| 35295 | // (imm:{ *:[i32] }):$src => (tMOVi32imm:{ *:[i32] }:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 35296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi32imm), |
| 35297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 35298 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 35299 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::CPSR*/0, |
| 35300 | GIR_RootConstrainSelectedInstOperands, |
| 35301 | // GIR_Coverage, 361, |
| 35302 | GIR_EraseRootFromParent_Done, |
| 35303 | // Label 1806: @96482 |
| 35304 | GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(96500), // Rule ID 599 // |
| 35305 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_UseMovt), |
| 35306 | // MIs[0] Operand 1 |
| 35307 | // No operand predicates |
| 35308 | // (imm:{ *:[i32] }):$src => (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 35309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm), |
| 35310 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 35311 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 35312 | GIR_RootConstrainSelectedInstOperands, |
| 35313 | // GIR_Coverage, 599, |
| 35314 | GIR_EraseRootFromParent_Done, |
| 35315 | // Label 1807: @96500 |
| 35316 | GIM_Reject, |
| 35317 | // Label 1805: @96501 |
| 35318 | GIM_Reject, |
| 35319 | // Label 1798: @96502 |
| 35320 | GIM_Reject, |
| 35321 | // Label 18: @96503 |
| 35322 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1810*/ GIMT_Encode4(96598), |
| 35323 | /*GILLT_s32*//*Label 1808*/ GIMT_Encode4(96522), |
| 35324 | /*GILLT_s64*//*Label 1809*/ GIMT_Encode4(96560), |
| 35325 | // Label 1808: @96522 |
| 35326 | GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(96559), // Rule ID 745 // |
| 35327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP3), |
| 35328 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 35329 | // MIs[0] Operand 1 |
| 35330 | // No operand predicates |
| 35331 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f32imm), |
| 35332 | // (fpimm:{ *:[f32] })<<P:Predicate_vfp_f32imm>><<X:vfp_f32imm_xform>>:$imm => (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm)) |
| 35333 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTS), |
| 35334 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 35335 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF32Imm), // imm |
| 35336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35337 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35338 | GIR_RootConstrainSelectedInstOperands, |
| 35339 | // GIR_Coverage, 745, |
| 35340 | GIR_EraseRootFromParent_Done, |
| 35341 | // Label 1811: @96559 |
| 35342 | GIM_Reject, |
| 35343 | // Label 1809: @96560 |
| 35344 | GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(96597), // Rule ID 744 // |
| 35345 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP3), |
| 35346 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35347 | // MIs[0] Operand 1 |
| 35348 | // No operand predicates |
| 35349 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f64imm), |
| 35350 | // (fpimm:{ *:[f64] })<<P:Predicate_vfp_f64imm>><<X:vfp_f64imm_xform>>:$imm => (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm)) |
| 35351 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTD), |
| 35352 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 35353 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF64Imm), // imm |
| 35354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35355 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35356 | GIR_RootConstrainSelectedInstOperands, |
| 35357 | // GIR_Coverage, 744, |
| 35358 | GIR_EraseRootFromParent_Done, |
| 35359 | // Label 1812: @96597 |
| 35360 | GIM_Reject, |
| 35361 | // Label 1810: @96598 |
| 35362 | GIM_Reject, |
| 35363 | // Label 19: @96599 |
| 35364 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 1816*/ GIMT_Encode4(96756), |
| 35365 | /*GILLT_v2s64*//*Label 1813*/ GIMT_Encode4(96642), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35366 | /*GILLT_v4s32*//*Label 1814*/ GIMT_Encode4(96680), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35367 | /*GILLT_v8s16*//*Label 1815*/ GIMT_Encode4(96718), |
| 35368 | // Label 1813: @96642 |
| 35369 | GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(96679), // Rule ID 1619 // |
| 35370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35371 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35372 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35373 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35374 | // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 35375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv2i64), |
| 35376 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35377 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35379 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35380 | GIR_RootConstrainSelectedInstOperands, |
| 35381 | // GIR_Coverage, 1619, |
| 35382 | GIR_EraseRootFromParent_Done, |
| 35383 | // Label 1817: @96679 |
| 35384 | GIM_Reject, |
| 35385 | // Label 1814: @96680 |
| 35386 | GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(96717), // Rule ID 1618 // |
| 35387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35388 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35389 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35390 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35391 | // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 35392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv4i32), |
| 35393 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35394 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35396 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35397 | GIR_RootConstrainSelectedInstOperands, |
| 35398 | // GIR_Coverage, 1618, |
| 35399 | GIR_EraseRootFromParent_Done, |
| 35400 | // Label 1818: @96717 |
| 35401 | GIM_Reject, |
| 35402 | // Label 1815: @96718 |
| 35403 | GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(96755), // Rule ID 1617 // |
| 35404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35405 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35407 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35408 | // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 35409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv8i16), |
| 35410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35411 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35413 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35414 | GIR_RootConstrainSelectedInstOperands, |
| 35415 | // GIR_Coverage, 1617, |
| 35416 | GIR_EraseRootFromParent_Done, |
| 35417 | // Label 1819: @96755 |
| 35418 | GIM_Reject, |
| 35419 | // Label 1816: @96756 |
| 35420 | GIM_Reject, |
| 35421 | // Label 20: @96757 |
| 35422 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 1823*/ GIMT_Encode4(96914), |
| 35423 | /*GILLT_v2s64*//*Label 1820*/ GIMT_Encode4(96800), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35424 | /*GILLT_v4s32*//*Label 1821*/ GIMT_Encode4(96838), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35425 | /*GILLT_v8s16*//*Label 1822*/ GIMT_Encode4(96876), |
| 35426 | // Label 1820: @96800 |
| 35427 | GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(96837), // Rule ID 1622 // |
| 35428 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35429 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35430 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35431 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35432 | // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 35433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64), |
| 35434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35435 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35437 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35438 | GIR_RootConstrainSelectedInstOperands, |
| 35439 | // GIR_Coverage, 1622, |
| 35440 | GIR_EraseRootFromParent_Done, |
| 35441 | // Label 1824: @96837 |
| 35442 | GIM_Reject, |
| 35443 | // Label 1821: @96838 |
| 35444 | GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(96875), // Rule ID 1621 // |
| 35445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35446 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35448 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35449 | // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 35450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32), |
| 35451 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35452 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35454 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35455 | GIR_RootConstrainSelectedInstOperands, |
| 35456 | // GIR_Coverage, 1621, |
| 35457 | GIR_EraseRootFromParent_Done, |
| 35458 | // Label 1825: @96875 |
| 35459 | GIM_Reject, |
| 35460 | // Label 1822: @96876 |
| 35461 | GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(96913), // Rule ID 1620 // |
| 35462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35463 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35464 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35465 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35466 | // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 35467 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16), |
| 35468 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35469 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35471 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35472 | GIR_RootConstrainSelectedInstOperands, |
| 35473 | // GIR_Coverage, 1620, |
| 35474 | GIR_EraseRootFromParent_Done, |
| 35475 | // Label 1826: @96913 |
| 35476 | GIM_Reject, |
| 35477 | // Label 1823: @96914 |
| 35478 | GIM_Reject, |
| 35479 | // Label 21: @96915 |
| 35480 | GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(97025), |
| 35481 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35482 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35483 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35485 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35486 | GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(96986), // Rule ID 478 // |
| 35487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35488 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 35489 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35490 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31), |
| 35491 | // MIs[1] Operand 1 |
| 35492 | // No operand predicates |
| 35493 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35494 | // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 35495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLri), |
| 35496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35497 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 35498 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35500 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35501 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35502 | GIR_RootConstrainSelectedInstOperands, |
| 35503 | // GIR_Coverage, 478, |
| 35504 | GIR_EraseRootFromParent_Done, |
| 35505 | // Label 1828: @96986 |
| 35506 | GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(97024), // Rule ID 479 // |
| 35507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35508 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35509 | // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 35510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLrr), |
| 35511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35512 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 35513 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 35514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35515 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35516 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35517 | GIR_RootConstrainSelectedInstOperands, |
| 35518 | // GIR_Coverage, 479, |
| 35519 | GIR_EraseRootFromParent_Done, |
| 35520 | // Label 1829: @97024 |
| 35521 | GIM_Reject, |
| 35522 | // Label 1827: @97025 |
| 35523 | GIM_Reject, |
| 35524 | // Label 22: @97026 |
| 35525 | GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(97081), // Rule ID 481 // |
| 35526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35527 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35528 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35529 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35531 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35532 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35533 | // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 35534 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSRrr), |
| 35535 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35536 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 35537 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 35538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35539 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35540 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35541 | GIR_RootConstrainSelectedInstOperands, |
| 35542 | // GIR_Coverage, 481, |
| 35543 | GIR_EraseRootFromParent_Done, |
| 35544 | // Label 1830: @97081 |
| 35545 | GIM_Reject, |
| 35546 | // Label 23: @97082 |
| 35547 | GIM_Try, /*On fail goto*//*Label 1831*/ GIMT_Encode4(97310), |
| 35548 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35549 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35550 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35551 | GIM_Try, /*On fail goto*//*Label 1832*/ GIMT_Encode4(97151), // Rule ID 201 // |
| 35552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 35553 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35554 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35555 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 35556 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 35557 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35558 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 35559 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35560 | // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 35561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 35562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35563 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 35564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35565 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35566 | GIR_RootConstrainSelectedInstOperands, |
| 35567 | // GIR_Coverage, 201, |
| 35568 | GIR_EraseRootFromParent_Done, |
| 35569 | // Label 1832: @97151 |
| 35570 | GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(97206), // Rule ID 335 // |
| 35571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 35572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35573 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35574 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 35575 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 35576 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35577 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 35578 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35579 | // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 35580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREVSH), |
| 35581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35582 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 35583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35584 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35585 | GIR_RootConstrainSelectedInstOperands, |
| 35586 | // GIR_Coverage, 335, |
| 35587 | GIR_EraseRootFromParent_Done, |
| 35588 | // Label 1833: @97206 |
| 35589 | GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(97309), |
| 35590 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35591 | GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(97266), // Rule ID 546 // |
| 35592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35593 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35594 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 35595 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 35596 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35597 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 35598 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35599 | // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 35600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 35601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 35603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35604 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35605 | GIR_RootConstrainSelectedInstOperands, |
| 35606 | // GIR_Coverage, 546, |
| 35607 | GIR_EraseRootFromParent_Done, |
| 35608 | // Label 1835: @97266 |
| 35609 | GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(97308), // Rule ID 483 // |
| 35610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35611 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35612 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35613 | // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 35614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ASRrr), |
| 35615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35616 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 35617 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 35618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35619 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35620 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35621 | GIR_RootConstrainSelectedInstOperands, |
| 35622 | // GIR_Coverage, 483, |
| 35623 | GIR_EraseRootFromParent_Done, |
| 35624 | // Label 1836: @97308 |
| 35625 | GIM_Reject, |
| 35626 | // Label 1834: @97309 |
| 35627 | GIM_Reject, |
| 35628 | // Label 1831: @97310 |
| 35629 | GIM_Reject, |
| 35630 | // Label 24: @97311 |
| 35631 | GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(97592), |
| 35632 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35633 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35634 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35635 | GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(97380), // Rule ID 200 // |
| 35636 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 35637 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35638 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35639 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 35640 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 35641 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35642 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 35643 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35644 | // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REV16:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 35645 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV16), |
| 35646 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35647 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 35648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35649 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35650 | GIR_RootConstrainSelectedInstOperands, |
| 35651 | // GIR_Coverage, 200, |
| 35652 | GIR_EraseRootFromParent_Done, |
| 35653 | // Label 1838: @97380 |
| 35654 | GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(97435), // Rule ID 334 // |
| 35655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 35656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35657 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35658 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 35659 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 35660 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35661 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 35662 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35663 | // (rotr:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREV16:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 35664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV16), |
| 35665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35666 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 35667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35668 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35669 | GIR_RootConstrainSelectedInstOperands, |
| 35670 | // GIR_Coverage, 334, |
| 35671 | GIR_EraseRootFromParent_Done, |
| 35672 | // Label 1839: @97435 |
| 35673 | GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(97591), |
| 35674 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35675 | GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(97495), // Rule ID 545 // |
| 35676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35677 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35678 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 35679 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 35680 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35681 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 35682 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35683 | // (rotr:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REV16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 35684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV16), |
| 35685 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35686 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 35687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35688 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35689 | GIR_RootConstrainSelectedInstOperands, |
| 35690 | // GIR_Coverage, 545, |
| 35691 | GIR_EraseRootFromParent_Done, |
| 35692 | // Label 1841: @97495 |
| 35693 | GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(97548), // Rule ID 484 // |
| 35694 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35695 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35696 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 35697 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35698 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31), |
| 35699 | // MIs[1] Operand 1 |
| 35700 | // No operand predicates |
| 35701 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35702 | // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2RORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 35703 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORri), |
| 35704 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35705 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 35706 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35708 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35709 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35710 | GIR_RootConstrainSelectedInstOperands, |
| 35711 | // GIR_Coverage, 484, |
| 35712 | GIR_EraseRootFromParent_Done, |
| 35713 | // Label 1842: @97548 |
| 35714 | GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(97590), // Rule ID 485 // |
| 35715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35716 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35717 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35718 | // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2RORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 35719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORrr), |
| 35720 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35721 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 35722 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 35723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35724 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35725 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35726 | GIR_RootConstrainSelectedInstOperands, |
| 35727 | // GIR_Coverage, 485, |
| 35728 | GIR_EraseRootFromParent_Done, |
| 35729 | // Label 1843: @97590 |
| 35730 | GIM_Reject, |
| 35731 | // Label 1840: @97591 |
| 35732 | GIM_Reject, |
| 35733 | // Label 1837: @97592 |
| 35734 | GIM_Reject, |
| 35735 | // Label 25: @97593 |
| 35736 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 1847*/ GIMT_Encode4(97834), |
| 35737 | /*GILLT_v4s32*//*Label 1844*/ GIMT_Encode4(97636), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35738 | /*GILLT_v8s16*//*Label 1845*/ GIMT_Encode4(97702), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35739 | /*GILLT_v16s8*//*Label 1846*/ GIMT_Encode4(97768), |
| 35740 | // Label 1844: @97636 |
| 35741 | GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(97701), // Rule ID 4579 // |
| 35742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 35743 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 35744 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35745 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35746 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35747 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35748 | // (mulhu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 35749 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 35750 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35751 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 35752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32), |
| 35753 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35754 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 35755 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 35756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35757 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35758 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35759 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 35760 | GIR_RootConstrainSelectedInstOperands, |
| 35761 | // GIR_Coverage, 4579, |
| 35762 | GIR_EraseRootFromParent_Done, |
| 35763 | // Label 1848: @97701 |
| 35764 | GIM_Reject, |
| 35765 | // Label 1845: @97702 |
| 35766 | GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(97767), // Rule ID 4575 // |
| 35767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 35768 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 35769 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35770 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35771 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35772 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35773 | // (mulhu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 35774 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 35775 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35776 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 35777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16), |
| 35778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35779 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 35780 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 35781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35782 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35783 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35784 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 35785 | GIR_RootConstrainSelectedInstOperands, |
| 35786 | // GIR_Coverage, 4575, |
| 35787 | GIR_EraseRootFromParent_Done, |
| 35788 | // Label 1849: @97767 |
| 35789 | GIM_Reject, |
| 35790 | // Label 1846: @97768 |
| 35791 | GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(97833), // Rule ID 4571 // |
| 35792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 35793 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 35794 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 35795 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35796 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35797 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35798 | // (mulhu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 35799 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 35800 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35801 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 35802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8), |
| 35803 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35804 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 35805 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 35806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35807 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35808 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35809 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 35810 | GIR_RootConstrainSelectedInstOperands, |
| 35811 | // GIR_Coverage, 4571, |
| 35812 | GIR_EraseRootFromParent_Done, |
| 35813 | // Label 1850: @97833 |
| 35814 | GIM_Reject, |
| 35815 | // Label 1847: @97834 |
| 35816 | GIM_Reject, |
| 35817 | // Label 26: @97835 |
| 35818 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 1855*/ GIMT_Encode4(98197), |
| 35819 | /*GILLT_s32*//*Label 1851*/ GIMT_Encode4(97906), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35820 | /*GILLT_v4s32*//*Label 1852*/ GIMT_Encode4(97999), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35821 | /*GILLT_v8s16*//*Label 1853*/ GIMT_Encode4(98065), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35822 | /*GILLT_v16s8*//*Label 1854*/ GIMT_Encode4(98131), |
| 35823 | // Label 1851: @97906 |
| 35824 | GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(97998), |
| 35825 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35826 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35827 | GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(97957), // Rule ID 178 // |
| 35828 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 35829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35830 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35831 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35832 | // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 35833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMUL), |
| 35834 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35835 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 35836 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 35837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35838 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35839 | GIR_RootConstrainSelectedInstOperands, |
| 35840 | // GIR_Coverage, 178, |
| 35841 | GIR_EraseRootFromParent_Done, |
| 35842 | // Label 1857: @97957 |
| 35843 | GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(97997), // Rule ID 515 // |
| 35844 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 35845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35846 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35847 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35848 | // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 35849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMUL), |
| 35850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35851 | GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 35852 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 35853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35854 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35855 | GIR_RootConstrainSelectedInstOperands, |
| 35856 | // GIR_Coverage, 515, |
| 35857 | GIR_EraseRootFromParent_Done, |
| 35858 | // Label 1858: @97997 |
| 35859 | GIM_Reject, |
| 35860 | // Label 1856: @97998 |
| 35861 | GIM_Reject, |
| 35862 | // Label 1852: @97999 |
| 35863 | GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(98064), // Rule ID 4567 // |
| 35864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 35865 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 35866 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35867 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35868 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35869 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35870 | // (mulhs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 35871 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 35872 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35873 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 35874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32), |
| 35875 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35876 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 35877 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 35878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35879 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35880 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35881 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 35882 | GIR_RootConstrainSelectedInstOperands, |
| 35883 | // GIR_Coverage, 4567, |
| 35884 | GIR_EraseRootFromParent_Done, |
| 35885 | // Label 1859: @98064 |
| 35886 | GIM_Reject, |
| 35887 | // Label 1853: @98065 |
| 35888 | GIM_Try, /*On fail goto*//*Label 1860*/ GIMT_Encode4(98130), // Rule ID 4563 // |
| 35889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 35890 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 35891 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35892 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35893 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35894 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35895 | // (mulhs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 35896 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 35897 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35898 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 35899 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16), |
| 35900 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35901 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 35902 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 35903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35904 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35905 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35906 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 35907 | GIR_RootConstrainSelectedInstOperands, |
| 35908 | // GIR_Coverage, 4563, |
| 35909 | GIR_EraseRootFromParent_Done, |
| 35910 | // Label 1860: @98130 |
| 35911 | GIM_Reject, |
| 35912 | // Label 1854: @98131 |
| 35913 | GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(98196), // Rule ID 4560 // |
| 35914 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 35915 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 35916 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 35917 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35918 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35919 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35920 | // (mulhs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 35921 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 35922 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35923 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 35924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8), |
| 35925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35926 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 35927 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 35928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35929 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35930 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35931 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 35932 | GIR_RootConstrainSelectedInstOperands, |
| 35933 | // GIR_Coverage, 4560, |
| 35934 | GIR_EraseRootFromParent_Done, |
| 35935 | // Label 1861: @98196 |
| 35936 | GIM_Reject, |
| 35937 | // Label 1855: @98197 |
| 35938 | GIM_Reject, |
| 35939 | // Label 27: @98198 |
| 35940 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(16), /*)*//*default:*//*Label 1870*/ GIMT_Encode4(98836), |
| 35941 | /*GILLT_s64*//*Label 1862*/ GIMT_Encode4(98265), GIMT_Encode4(0), |
| 35942 | /*GILLT_v2s32*//*Label 1863*/ GIMT_Encode4(98312), |
| 35943 | /*GILLT_v2s64*//*Label 1864*/ GIMT_Encode4(98359), GIMT_Encode4(0), |
| 35944 | /*GILLT_v4s16*//*Label 1865*/ GIMT_Encode4(98406), |
| 35945 | /*GILLT_v4s32*//*Label 1866*/ GIMT_Encode4(98453), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35946 | /*GILLT_v8s8*//*Label 1867*/ GIMT_Encode4(98565), |
| 35947 | /*GILLT_v8s16*//*Label 1868*/ GIMT_Encode4(98612), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35948 | /*GILLT_v16s8*//*Label 1869*/ GIMT_Encode4(98724), |
| 35949 | // Label 1862: @98265 |
| 35950 | GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(98311), // Rule ID 847 // |
| 35951 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35952 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 35953 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 35954 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35955 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35956 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35957 | // (uaddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 35958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv1i64), |
| 35959 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35960 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 35961 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 35962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35963 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35964 | GIR_RootConstrainSelectedInstOperands, |
| 35965 | // GIR_Coverage, 847, |
| 35966 | GIR_EraseRootFromParent_Done, |
| 35967 | // Label 1871: @98311 |
| 35968 | GIM_Reject, |
| 35969 | // Label 1863: @98312 |
| 35970 | GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(98358), // Rule ID 842 // |
| 35971 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35972 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35973 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35974 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35975 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35976 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35977 | // (uaddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 35978 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i32), |
| 35979 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35980 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 35981 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 35982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35983 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35984 | GIR_RootConstrainSelectedInstOperands, |
| 35985 | // GIR_Coverage, 842, |
| 35986 | GIR_EraseRootFromParent_Done, |
| 35987 | // Label 1872: @98358 |
| 35988 | GIM_Reject, |
| 35989 | // Label 1864: @98359 |
| 35990 | GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(98405), // Rule ID 848 // |
| 35991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35992 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 35993 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35995 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35996 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35997 | // (uaddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 35998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i64), |
| 35999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36000 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36001 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36003 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36004 | GIR_RootConstrainSelectedInstOperands, |
| 36005 | // GIR_Coverage, 848, |
| 36006 | GIR_EraseRootFromParent_Done, |
| 36007 | // Label 1873: @98405 |
| 36008 | GIM_Reject, |
| 36009 | // Label 1865: @98406 |
| 36010 | GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(98452), // Rule ID 841 // |
| 36011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36012 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 36013 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36014 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36015 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36016 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36017 | // (uaddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 36018 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i16), |
| 36019 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36020 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36021 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36023 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36024 | GIR_RootConstrainSelectedInstOperands, |
| 36025 | // GIR_Coverage, 841, |
| 36026 | GIR_EraseRootFromParent_Done, |
| 36027 | // Label 1874: @98452 |
| 36028 | GIM_Reject, |
| 36029 | // Label 1866: @98453 |
| 36030 | GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(98564), |
| 36031 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36032 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36033 | GIM_Try, /*On fail goto*//*Label 1876*/ GIMT_Encode4(98504), // Rule ID 844 // |
| 36034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36035 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36036 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36037 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36038 | // (uaddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 36039 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i32), |
| 36040 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36041 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36042 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36044 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36045 | GIR_RootConstrainSelectedInstOperands, |
| 36046 | // GIR_Coverage, 844, |
| 36047 | GIR_EraseRootFromParent_Done, |
| 36048 | // Label 1876: @98504 |
| 36049 | GIM_Try, /*On fail goto*//*Label 1877*/ GIMT_Encode4(98563), // Rule ID 3624 // |
| 36050 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36051 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36052 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36053 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36054 | // (uaddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 36055 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36056 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36057 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 36058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu32), |
| 36059 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36060 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36061 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36063 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36064 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36065 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36066 | GIR_RootConstrainSelectedInstOperands, |
| 36067 | // GIR_Coverage, 3624, |
| 36068 | GIR_EraseRootFromParent_Done, |
| 36069 | // Label 1877: @98563 |
| 36070 | GIM_Reject, |
| 36071 | // Label 1875: @98564 |
| 36072 | GIM_Reject, |
| 36073 | // Label 1867: @98565 |
| 36074 | GIM_Try, /*On fail goto*//*Label 1878*/ GIMT_Encode4(98611), // Rule ID 845 // |
| 36075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36076 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 36077 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 36078 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36079 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36080 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36081 | // (uaddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 36082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i8), |
| 36083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36084 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36085 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36087 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36088 | GIR_RootConstrainSelectedInstOperands, |
| 36089 | // GIR_Coverage, 845, |
| 36090 | GIR_EraseRootFromParent_Done, |
| 36091 | // Label 1878: @98611 |
| 36092 | GIM_Reject, |
| 36093 | // Label 1868: @98612 |
| 36094 | GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(98723), |
| 36095 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36096 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36097 | GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(98663), // Rule ID 843 // |
| 36098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36099 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36100 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36101 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36102 | // (uaddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 36103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i16), |
| 36104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36105 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36106 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36108 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36109 | GIR_RootConstrainSelectedInstOperands, |
| 36110 | // GIR_Coverage, 843, |
| 36111 | GIR_EraseRootFromParent_Done, |
| 36112 | // Label 1880: @98663 |
| 36113 | GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(98722), // Rule ID 3621 // |
| 36114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36116 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36117 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36118 | // (uaddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36119 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36120 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36121 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 36122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu16), |
| 36123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36124 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36125 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36127 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36128 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36129 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36130 | GIR_RootConstrainSelectedInstOperands, |
| 36131 | // GIR_Coverage, 3621, |
| 36132 | GIR_EraseRootFromParent_Done, |
| 36133 | // Label 1881: @98722 |
| 36134 | GIM_Reject, |
| 36135 | // Label 1879: @98723 |
| 36136 | GIM_Reject, |
| 36137 | // Label 1869: @98724 |
| 36138 | GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(98835), |
| 36139 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36140 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36141 | GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(98775), // Rule ID 846 // |
| 36142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36143 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36144 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36145 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36146 | // (uaddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 36147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv16i8), |
| 36148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36149 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36150 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36152 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36153 | GIR_RootConstrainSelectedInstOperands, |
| 36154 | // GIR_Coverage, 846, |
| 36155 | GIR_EraseRootFromParent_Done, |
| 36156 | // Label 1883: @98775 |
| 36157 | GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(98834), // Rule ID 3618 // |
| 36158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36160 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36161 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36162 | // (uaddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36163 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36164 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36165 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 36166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu8), |
| 36167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36168 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36169 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36171 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36172 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36173 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36174 | GIR_RootConstrainSelectedInstOperands, |
| 36175 | // GIR_Coverage, 3618, |
| 36176 | GIR_EraseRootFromParent_Done, |
| 36177 | // Label 1884: @98834 |
| 36178 | GIM_Reject, |
| 36179 | // Label 1882: @98835 |
| 36180 | GIM_Reject, |
| 36181 | // Label 1870: @98836 |
| 36182 | GIM_Reject, |
| 36183 | // Label 28: @98837 |
| 36184 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 1894*/ GIMT_Encode4(100130), |
| 36185 | /*GILLT_s32*//*Label 1885*/ GIMT_Encode4(98908), |
| 36186 | /*GILLT_s64*//*Label 1886*/ GIMT_Encode4(99249), GIMT_Encode4(0), |
| 36187 | /*GILLT_v2s32*//*Label 1887*/ GIMT_Encode4(99296), |
| 36188 | /*GILLT_v2s64*//*Label 1888*/ GIMT_Encode4(99343), GIMT_Encode4(0), |
| 36189 | /*GILLT_v4s16*//*Label 1889*/ GIMT_Encode4(99544), |
| 36190 | /*GILLT_v4s32*//*Label 1890*/ GIMT_Encode4(99591), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36191 | /*GILLT_v8s8*//*Label 1891*/ GIMT_Encode4(99859), |
| 36192 | /*GILLT_v8s16*//*Label 1892*/ GIMT_Encode4(99906), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36193 | /*GILLT_v16s8*//*Label 1893*/ GIMT_Encode4(100018), |
| 36194 | // Label 1885: @98908 |
| 36195 | GIM_Try, /*On fail goto*//*Label 1895*/ GIMT_Encode4(99248), |
| 36196 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36197 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36198 | GIM_Try, /*On fail goto*//*Label 1896*/ GIMT_Encode4(98981), // Rule ID 5771 // |
| 36199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 36200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36201 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36202 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36203 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36204 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36205 | // MIs[1] Rn |
| 36206 | GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36207 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36208 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36209 | // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 36211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36212 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36215 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36216 | GIR_RootConstrainSelectedInstOperands, |
| 36217 | // GIR_Coverage, 5771, |
| 36218 | GIR_EraseRootFromParent_Done, |
| 36219 | // Label 1896: @98981 |
| 36220 | GIM_Try, /*On fail goto*//*Label 1897*/ GIMT_Encode4(99043), // Rule ID 5805 // |
| 36221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36222 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36223 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36224 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36225 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36226 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36227 | // MIs[1] Rn |
| 36228 | GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36229 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36230 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36231 | // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36232 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 36233 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36234 | GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36235 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36237 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36238 | GIR_RootConstrainSelectedInstOperands, |
| 36239 | // GIR_Coverage, 5805, |
| 36240 | GIR_EraseRootFromParent_Done, |
| 36241 | // Label 1897: @99043 |
| 36242 | GIM_Try, /*On fail goto*//*Label 1898*/ GIMT_Encode4(99105), // Rule ID 1894 // |
| 36243 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 36244 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36245 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36246 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36247 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36248 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36249 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36250 | // MIs[1] Rn |
| 36251 | GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36252 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36253 | // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 36255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36256 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36257 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36258 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36259 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36260 | GIR_RootConstrainSelectedInstOperands, |
| 36261 | // GIR_Coverage, 1894, |
| 36262 | GIR_EraseRootFromParent_Done, |
| 36263 | // Label 1898: @99105 |
| 36264 | GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(99167), // Rule ID 2143 // |
| 36265 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36266 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36267 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36268 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36269 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36270 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36271 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36272 | // MIs[1] Rn |
| 36273 | GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36274 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36275 | // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 36277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36278 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36279 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36281 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36282 | GIR_RootConstrainSelectedInstOperands, |
| 36283 | // GIR_Coverage, 2143, |
| 36284 | GIR_EraseRootFromParent_Done, |
| 36285 | // Label 1899: @99167 |
| 36286 | GIM_Try, /*On fail goto*//*Label 1900*/ GIMT_Encode4(99207), // Rule ID 1892 // |
| 36287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 36288 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36289 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36290 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36291 | // (saddsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QADD:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 36292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD), |
| 36293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36294 | GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 36295 | GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 36296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36297 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36298 | GIR_RootConstrainSelectedInstOperands, |
| 36299 | // GIR_Coverage, 1892, |
| 36300 | GIR_EraseRootFromParent_Done, |
| 36301 | // Label 1900: @99207 |
| 36302 | GIM_Try, /*On fail goto*//*Label 1901*/ GIMT_Encode4(99247), // Rule ID 2141 // |
| 36303 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36304 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36305 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36306 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36307 | // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD), |
| 36309 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36310 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36311 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36313 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36314 | GIR_RootConstrainSelectedInstOperands, |
| 36315 | // GIR_Coverage, 2141, |
| 36316 | GIR_EraseRootFromParent_Done, |
| 36317 | // Label 1901: @99247 |
| 36318 | GIM_Reject, |
| 36319 | // Label 1895: @99248 |
| 36320 | GIM_Reject, |
| 36321 | // Label 1886: @99249 |
| 36322 | GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(99295), // Rule ID 839 // |
| 36323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36324 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 36325 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 36326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36327 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36328 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36329 | // (saddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 36330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv1i64), |
| 36331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36332 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36333 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36335 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36336 | GIR_RootConstrainSelectedInstOperands, |
| 36337 | // GIR_Coverage, 839, |
| 36338 | GIR_EraseRootFromParent_Done, |
| 36339 | // Label 1902: @99295 |
| 36340 | GIM_Reject, |
| 36341 | // Label 1887: @99296 |
| 36342 | GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(99342), // Rule ID 834 // |
| 36343 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36344 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 36345 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36346 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36347 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36348 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36349 | // (saddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 36350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i32), |
| 36351 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36352 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36353 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36355 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36356 | GIR_RootConstrainSelectedInstOperands, |
| 36357 | // GIR_Coverage, 834, |
| 36358 | GIR_EraseRootFromParent_Done, |
| 36359 | // Label 1903: @99342 |
| 36360 | GIM_Reject, |
| 36361 | // Label 1888: @99343 |
| 36362 | GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(99543), |
| 36363 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 36364 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36365 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36366 | GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(99432), // Rule ID 5862 // |
| 36367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36368 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36369 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 36370 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 36371 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 36372 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36373 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 36374 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36375 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36376 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36377 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36378 | // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 3474:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$src1) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 36379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64), |
| 36380 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36381 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 36382 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 36383 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 36384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36385 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36386 | GIR_RootConstrainSelectedInstOperands, |
| 36387 | // GIR_Coverage, 5862, |
| 36388 | GIR_EraseRootFromParent_Done, |
| 36389 | // Label 1905: @99432 |
| 36390 | GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(99506), // Rule ID 2486 // |
| 36391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36392 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36393 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36394 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 36395 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 36396 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 36397 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36398 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 36399 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36400 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36401 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36402 | // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 3474:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 36403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64), |
| 36404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36405 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 36406 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 36407 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 36408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36409 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36410 | GIR_RootConstrainSelectedInstOperands, |
| 36411 | // GIR_Coverage, 2486, |
| 36412 | GIR_EraseRootFromParent_Done, |
| 36413 | // Label 1906: @99506 |
| 36414 | GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(99542), // Rule ID 840 // |
| 36415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36416 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36417 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36418 | // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 36419 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i64), |
| 36420 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36421 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36422 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36424 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36425 | GIR_RootConstrainSelectedInstOperands, |
| 36426 | // GIR_Coverage, 840, |
| 36427 | GIR_EraseRootFromParent_Done, |
| 36428 | // Label 1907: @99542 |
| 36429 | GIM_Reject, |
| 36430 | // Label 1904: @99543 |
| 36431 | GIM_Reject, |
| 36432 | // Label 1889: @99544 |
| 36433 | GIM_Try, /*On fail goto*//*Label 1908*/ GIMT_Encode4(99590), // Rule ID 833 // |
| 36434 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36435 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 36436 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36438 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36439 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36440 | // (saddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 36441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i16), |
| 36442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36443 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36444 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36446 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36447 | GIR_RootConstrainSelectedInstOperands, |
| 36448 | // GIR_Coverage, 833, |
| 36449 | GIR_EraseRootFromParent_Done, |
| 36450 | // Label 1908: @99590 |
| 36451 | GIM_Reject, |
| 36452 | // Label 1890: @99591 |
| 36453 | GIM_Try, /*On fail goto*//*Label 1909*/ GIMT_Encode4(99858), |
| 36454 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36455 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36456 | GIM_Try, /*On fail goto*//*Label 1910*/ GIMT_Encode4(99680), // Rule ID 5861 // |
| 36457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36459 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36460 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 36461 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 36462 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 36463 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36464 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 36465 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36466 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36467 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36468 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36469 | // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 3474:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 36470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32), |
| 36471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36472 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 36473 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 36474 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 36475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36476 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36477 | GIR_RootConstrainSelectedInstOperands, |
| 36478 | // GIR_Coverage, 5861, |
| 36479 | GIR_EraseRootFromParent_Done, |
| 36480 | // Label 1910: @99680 |
| 36481 | GIM_Try, /*On fail goto*//*Label 1911*/ GIMT_Encode4(99758), // Rule ID 2485 // |
| 36482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36483 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36484 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36485 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36486 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 36487 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 36488 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 36489 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36490 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 36491 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36492 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36493 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36494 | // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 3474:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 36495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32), |
| 36496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36497 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 36498 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 36499 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 36500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36501 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36502 | GIR_RootConstrainSelectedInstOperands, |
| 36503 | // GIR_Coverage, 2485, |
| 36504 | GIR_EraseRootFromParent_Done, |
| 36505 | // Label 1911: @99758 |
| 36506 | GIM_Try, /*On fail goto*//*Label 1912*/ GIMT_Encode4(99798), // Rule ID 836 // |
| 36507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36508 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36509 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36510 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36511 | // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 36512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i32), |
| 36513 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36514 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36515 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36517 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36518 | GIR_RootConstrainSelectedInstOperands, |
| 36519 | // GIR_Coverage, 836, |
| 36520 | GIR_EraseRootFromParent_Done, |
| 36521 | // Label 1912: @99798 |
| 36522 | GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(99857), // Rule ID 3615 // |
| 36523 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36525 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36526 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36527 | // (saddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 36528 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36529 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36530 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 36531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs32), |
| 36532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36533 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36534 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36536 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36537 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36538 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36539 | GIR_RootConstrainSelectedInstOperands, |
| 36540 | // GIR_Coverage, 3615, |
| 36541 | GIR_EraseRootFromParent_Done, |
| 36542 | // Label 1913: @99857 |
| 36543 | GIM_Reject, |
| 36544 | // Label 1909: @99858 |
| 36545 | GIM_Reject, |
| 36546 | // Label 1891: @99859 |
| 36547 | GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(99905), // Rule ID 837 // |
| 36548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36549 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 36550 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 36551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36552 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36553 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36554 | // (saddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 36555 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i8), |
| 36556 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36557 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36558 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36560 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36561 | GIR_RootConstrainSelectedInstOperands, |
| 36562 | // GIR_Coverage, 837, |
| 36563 | GIR_EraseRootFromParent_Done, |
| 36564 | // Label 1914: @99905 |
| 36565 | GIM_Reject, |
| 36566 | // Label 1892: @99906 |
| 36567 | GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(100017), |
| 36568 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36569 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36570 | GIM_Try, /*On fail goto*//*Label 1916*/ GIMT_Encode4(99957), // Rule ID 835 // |
| 36571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36573 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36574 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36575 | // (saddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 36576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i16), |
| 36577 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36578 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36579 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36581 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36582 | GIR_RootConstrainSelectedInstOperands, |
| 36583 | // GIR_Coverage, 835, |
| 36584 | GIR_EraseRootFromParent_Done, |
| 36585 | // Label 1916: @99957 |
| 36586 | GIM_Try, /*On fail goto*//*Label 1917*/ GIMT_Encode4(100016), // Rule ID 3612 // |
| 36587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36589 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36590 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36591 | // (saddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36592 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36593 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36594 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 36595 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs16), |
| 36596 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36597 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36598 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36600 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36601 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36602 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36603 | GIR_RootConstrainSelectedInstOperands, |
| 36604 | // GIR_Coverage, 3612, |
| 36605 | GIR_EraseRootFromParent_Done, |
| 36606 | // Label 1917: @100016 |
| 36607 | GIM_Reject, |
| 36608 | // Label 1915: @100017 |
| 36609 | GIM_Reject, |
| 36610 | // Label 1893: @100018 |
| 36611 | GIM_Try, /*On fail goto*//*Label 1918*/ GIMT_Encode4(100129), |
| 36612 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36613 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36614 | GIM_Try, /*On fail goto*//*Label 1919*/ GIMT_Encode4(100069), // Rule ID 838 // |
| 36615 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36616 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36617 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36618 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36619 | // (saddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 36620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv16i8), |
| 36621 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36622 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36623 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36625 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36626 | GIR_RootConstrainSelectedInstOperands, |
| 36627 | // GIR_Coverage, 838, |
| 36628 | GIR_EraseRootFromParent_Done, |
| 36629 | // Label 1919: @100069 |
| 36630 | GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(100128), // Rule ID 3609 // |
| 36631 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36633 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36634 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36635 | // (saddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36636 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36637 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36638 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 36639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs8), |
| 36640 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36641 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36642 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36644 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36645 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36646 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36647 | GIR_RootConstrainSelectedInstOperands, |
| 36648 | // GIR_Coverage, 3609, |
| 36649 | GIR_EraseRootFromParent_Done, |
| 36650 | // Label 1920: @100128 |
| 36651 | GIM_Reject, |
| 36652 | // Label 1918: @100129 |
| 36653 | GIM_Reject, |
| 36654 | // Label 1894: @100130 |
| 36655 | GIM_Reject, |
| 36656 | // Label 29: @100131 |
| 36657 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(16), /*)*//*default:*//*Label 1929*/ GIMT_Encode4(100769), |
| 36658 | /*GILLT_s64*//*Label 1921*/ GIMT_Encode4(100198), GIMT_Encode4(0), |
| 36659 | /*GILLT_v2s32*//*Label 1922*/ GIMT_Encode4(100245), |
| 36660 | /*GILLT_v2s64*//*Label 1923*/ GIMT_Encode4(100292), GIMT_Encode4(0), |
| 36661 | /*GILLT_v4s16*//*Label 1924*/ GIMT_Encode4(100339), |
| 36662 | /*GILLT_v4s32*//*Label 1925*/ GIMT_Encode4(100386), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36663 | /*GILLT_v8s8*//*Label 1926*/ GIMT_Encode4(100498), |
| 36664 | /*GILLT_v8s16*//*Label 1927*/ GIMT_Encode4(100545), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36665 | /*GILLT_v16s8*//*Label 1928*/ GIMT_Encode4(100657), |
| 36666 | // Label 1921: @100198 |
| 36667 | GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(100244), // Rule ID 1039 // |
| 36668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36669 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 36670 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 36671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36672 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36673 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36674 | // (usubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 36675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv1i64), |
| 36676 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36677 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36678 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36679 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36680 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36681 | GIR_RootConstrainSelectedInstOperands, |
| 36682 | // GIR_Coverage, 1039, |
| 36683 | GIR_EraseRootFromParent_Done, |
| 36684 | // Label 1930: @100244 |
| 36685 | GIM_Reject, |
| 36686 | // Label 1922: @100245 |
| 36687 | GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(100291), // Rule ID 1034 // |
| 36688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36689 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 36690 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36691 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36692 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36693 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36694 | // (usubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 36695 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i32), |
| 36696 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36697 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36698 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36700 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36701 | GIR_RootConstrainSelectedInstOperands, |
| 36702 | // GIR_Coverage, 1034, |
| 36703 | GIR_EraseRootFromParent_Done, |
| 36704 | // Label 1931: @100291 |
| 36705 | GIM_Reject, |
| 36706 | // Label 1923: @100292 |
| 36707 | GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(100338), // Rule ID 1040 // |
| 36708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36709 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 36710 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36712 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36713 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36714 | // (usubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 36715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i64), |
| 36716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36717 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36718 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36720 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36721 | GIR_RootConstrainSelectedInstOperands, |
| 36722 | // GIR_Coverage, 1040, |
| 36723 | GIR_EraseRootFromParent_Done, |
| 36724 | // Label 1932: @100338 |
| 36725 | GIM_Reject, |
| 36726 | // Label 1924: @100339 |
| 36727 | GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(100385), // Rule ID 1033 // |
| 36728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36729 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 36730 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36731 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36732 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36733 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36734 | // (usubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 36735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i16), |
| 36736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36737 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36738 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36740 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36741 | GIR_RootConstrainSelectedInstOperands, |
| 36742 | // GIR_Coverage, 1033, |
| 36743 | GIR_EraseRootFromParent_Done, |
| 36744 | // Label 1933: @100385 |
| 36745 | GIM_Reject, |
| 36746 | // Label 1925: @100386 |
| 36747 | GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(100497), |
| 36748 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36749 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36750 | GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(100437), // Rule ID 1036 // |
| 36751 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36753 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36754 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36755 | // (usubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 36756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i32), |
| 36757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36758 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36759 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36761 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36762 | GIR_RootConstrainSelectedInstOperands, |
| 36763 | // GIR_Coverage, 1036, |
| 36764 | GIR_EraseRootFromParent_Done, |
| 36765 | // Label 1935: @100437 |
| 36766 | GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(100496), // Rule ID 3642 // |
| 36767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36769 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36770 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36771 | // (usubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 36772 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36773 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36774 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 36775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu32), |
| 36776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36777 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36778 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36780 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36781 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36782 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36783 | GIR_RootConstrainSelectedInstOperands, |
| 36784 | // GIR_Coverage, 3642, |
| 36785 | GIR_EraseRootFromParent_Done, |
| 36786 | // Label 1936: @100496 |
| 36787 | GIM_Reject, |
| 36788 | // Label 1934: @100497 |
| 36789 | GIM_Reject, |
| 36790 | // Label 1926: @100498 |
| 36791 | GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(100544), // Rule ID 1037 // |
| 36792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36793 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 36794 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 36795 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36796 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36797 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36798 | // (usubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 36799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i8), |
| 36800 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36801 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36802 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36804 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36805 | GIR_RootConstrainSelectedInstOperands, |
| 36806 | // GIR_Coverage, 1037, |
| 36807 | GIR_EraseRootFromParent_Done, |
| 36808 | // Label 1937: @100544 |
| 36809 | GIM_Reject, |
| 36810 | // Label 1927: @100545 |
| 36811 | GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(100656), |
| 36812 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36813 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36814 | GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(100596), // Rule ID 1035 // |
| 36815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36816 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36817 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36818 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36819 | // (usubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 36820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i16), |
| 36821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36822 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36823 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36825 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36826 | GIR_RootConstrainSelectedInstOperands, |
| 36827 | // GIR_Coverage, 1035, |
| 36828 | GIR_EraseRootFromParent_Done, |
| 36829 | // Label 1939: @100596 |
| 36830 | GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(100655), // Rule ID 3639 // |
| 36831 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36832 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36833 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36834 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36835 | // (usubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36836 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36837 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36838 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 36839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu16), |
| 36840 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36841 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36842 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36844 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36845 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36846 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36847 | GIR_RootConstrainSelectedInstOperands, |
| 36848 | // GIR_Coverage, 3639, |
| 36849 | GIR_EraseRootFromParent_Done, |
| 36850 | // Label 1940: @100655 |
| 36851 | GIM_Reject, |
| 36852 | // Label 1938: @100656 |
| 36853 | GIM_Reject, |
| 36854 | // Label 1928: @100657 |
| 36855 | GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(100768), |
| 36856 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36857 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36858 | GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(100708), // Rule ID 1038 // |
| 36859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36860 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36861 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36862 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36863 | // (usubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 36864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv16i8), |
| 36865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36866 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36867 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36869 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36870 | GIR_RootConstrainSelectedInstOperands, |
| 36871 | // GIR_Coverage, 1038, |
| 36872 | GIR_EraseRootFromParent_Done, |
| 36873 | // Label 1942: @100708 |
| 36874 | GIM_Try, /*On fail goto*//*Label 1943*/ GIMT_Encode4(100767), // Rule ID 3636 // |
| 36875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36876 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36877 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36878 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36879 | // (usubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36880 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36881 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36882 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 36883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu8), |
| 36884 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36885 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36886 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36888 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36889 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36890 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36891 | GIR_RootConstrainSelectedInstOperands, |
| 36892 | // GIR_Coverage, 3636, |
| 36893 | GIR_EraseRootFromParent_Done, |
| 36894 | // Label 1943: @100767 |
| 36895 | GIM_Reject, |
| 36896 | // Label 1941: @100768 |
| 36897 | GIM_Reject, |
| 36898 | // Label 1929: @100769 |
| 36899 | GIM_Reject, |
| 36900 | // Label 30: @100770 |
| 36901 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 1953*/ GIMT_Encode4(101783), |
| 36902 | /*GILLT_s32*//*Label 1944*/ GIMT_Encode4(100841), |
| 36903 | /*GILLT_s64*//*Label 1945*/ GIMT_Encode4(101058), GIMT_Encode4(0), |
| 36904 | /*GILLT_v2s32*//*Label 1946*/ GIMT_Encode4(101105), |
| 36905 | /*GILLT_v2s64*//*Label 1947*/ GIMT_Encode4(101152), GIMT_Encode4(0), |
| 36906 | /*GILLT_v4s16*//*Label 1948*/ GIMT_Encode4(101275), |
| 36907 | /*GILLT_v4s32*//*Label 1949*/ GIMT_Encode4(101322), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36908 | /*GILLT_v8s8*//*Label 1950*/ GIMT_Encode4(101512), |
| 36909 | /*GILLT_v8s16*//*Label 1951*/ GIMT_Encode4(101559), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36910 | /*GILLT_v16s8*//*Label 1952*/ GIMT_Encode4(101671), |
| 36911 | // Label 1944: @100841 |
| 36912 | GIM_Try, /*On fail goto*//*Label 1954*/ GIMT_Encode4(101057), |
| 36913 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36914 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36915 | GIM_Try, /*On fail goto*//*Label 1955*/ GIMT_Encode4(100914), // Rule ID 1895 // |
| 36916 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 36917 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36918 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36919 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36920 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36921 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36922 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36923 | // MIs[1] Rn |
| 36924 | GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36925 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36926 | // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB), |
| 36928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36929 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36930 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36932 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36933 | GIR_RootConstrainSelectedInstOperands, |
| 36934 | // GIR_Coverage, 1895, |
| 36935 | GIR_EraseRootFromParent_Done, |
| 36936 | // Label 1955: @100914 |
| 36937 | GIM_Try, /*On fail goto*//*Label 1956*/ GIMT_Encode4(100976), // Rule ID 2144 // |
| 36938 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36939 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36940 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36941 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36942 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36943 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36944 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36945 | // MIs[1] Rn |
| 36946 | GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36947 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36948 | // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB), |
| 36950 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36951 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36952 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36954 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36955 | GIR_RootConstrainSelectedInstOperands, |
| 36956 | // GIR_Coverage, 2144, |
| 36957 | GIR_EraseRootFromParent_Done, |
| 36958 | // Label 1956: @100976 |
| 36959 | GIM_Try, /*On fail goto*//*Label 1957*/ GIMT_Encode4(101016), // Rule ID 1893 // |
| 36960 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 36961 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36962 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36963 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36964 | // (ssubsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QSUB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 36965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB), |
| 36966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36967 | GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 36968 | GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 36969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36970 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36971 | GIR_RootConstrainSelectedInstOperands, |
| 36972 | // GIR_Coverage, 1893, |
| 36973 | GIR_EraseRootFromParent_Done, |
| 36974 | // Label 1957: @101016 |
| 36975 | GIM_Try, /*On fail goto*//*Label 1958*/ GIMT_Encode4(101056), // Rule ID 2142 // |
| 36976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36978 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36979 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36980 | // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB), |
| 36982 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36983 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36984 | GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36986 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36987 | GIR_RootConstrainSelectedInstOperands, |
| 36988 | // GIR_Coverage, 2142, |
| 36989 | GIR_EraseRootFromParent_Done, |
| 36990 | // Label 1958: @101056 |
| 36991 | GIM_Reject, |
| 36992 | // Label 1954: @101057 |
| 36993 | GIM_Reject, |
| 36994 | // Label 1945: @101058 |
| 36995 | GIM_Try, /*On fail goto*//*Label 1959*/ GIMT_Encode4(101104), // Rule ID 1031 // |
| 36996 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36997 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 36998 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 36999 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37000 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37001 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37002 | // (ssubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 37003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv1i64), |
| 37004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37005 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37006 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37008 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37009 | GIR_RootConstrainSelectedInstOperands, |
| 37010 | // GIR_Coverage, 1031, |
| 37011 | GIR_EraseRootFromParent_Done, |
| 37012 | // Label 1959: @101104 |
| 37013 | GIM_Reject, |
| 37014 | // Label 1946: @101105 |
| 37015 | GIM_Try, /*On fail goto*//*Label 1960*/ GIMT_Encode4(101151), // Rule ID 1026 // |
| 37016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37017 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 37018 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37019 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37020 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37021 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37022 | // (ssubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37023 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i32), |
| 37024 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37025 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37026 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37028 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37029 | GIR_RootConstrainSelectedInstOperands, |
| 37030 | // GIR_Coverage, 1026, |
| 37031 | GIR_EraseRootFromParent_Done, |
| 37032 | // Label 1960: @101151 |
| 37033 | GIM_Reject, |
| 37034 | // Label 1947: @101152 |
| 37035 | GIM_Try, /*On fail goto*//*Label 1961*/ GIMT_Encode4(101274), |
| 37036 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 37037 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37039 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37040 | GIM_Try, /*On fail goto*//*Label 1962*/ GIMT_Encode4(101241), // Rule ID 2493 // |
| 37041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37042 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37043 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37044 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37045 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37046 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37047 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 37048 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37049 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37050 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37051 | // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 3474:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLSLv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37052 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv2i64), |
| 37053 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37054 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37055 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37058 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37059 | GIR_RootConstrainSelectedInstOperands, |
| 37060 | // GIR_Coverage, 2493, |
| 37061 | GIR_EraseRootFromParent_Done, |
| 37062 | // Label 1962: @101241 |
| 37063 | GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(101273), // Rule ID 1032 // |
| 37064 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37065 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37066 | // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 37067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i64), |
| 37068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37069 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37070 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37072 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37073 | GIR_RootConstrainSelectedInstOperands, |
| 37074 | // GIR_Coverage, 1032, |
| 37075 | GIR_EraseRootFromParent_Done, |
| 37076 | // Label 1963: @101273 |
| 37077 | GIM_Reject, |
| 37078 | // Label 1961: @101274 |
| 37079 | GIM_Reject, |
| 37080 | // Label 1948: @101275 |
| 37081 | GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(101321), // Rule ID 1025 // |
| 37082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37083 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 37084 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37086 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37087 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37088 | // (ssubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i16), |
| 37090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37091 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37092 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37094 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37095 | GIR_RootConstrainSelectedInstOperands, |
| 37096 | // GIR_Coverage, 1025, |
| 37097 | GIR_EraseRootFromParent_Done, |
| 37098 | // Label 1964: @101321 |
| 37099 | GIM_Reject, |
| 37100 | // Label 1949: @101322 |
| 37101 | GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(101511), |
| 37102 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 37103 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 37104 | GIM_Try, /*On fail goto*//*Label 1966*/ GIMT_Encode4(101411), // Rule ID 2492 // |
| 37105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37107 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37108 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37109 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37110 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37111 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37112 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37113 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 37114 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37115 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37116 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37117 | // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 3474:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLSLv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv4i32), |
| 37119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37120 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37121 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37122 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37124 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37125 | GIR_RootConstrainSelectedInstOperands, |
| 37126 | // GIR_Coverage, 2492, |
| 37127 | GIR_EraseRootFromParent_Done, |
| 37128 | // Label 1966: @101411 |
| 37129 | GIM_Try, /*On fail goto*//*Label 1967*/ GIMT_Encode4(101451), // Rule ID 1028 // |
| 37130 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37131 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37132 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37133 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37134 | // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 37135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i32), |
| 37136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37137 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37138 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37140 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37141 | GIR_RootConstrainSelectedInstOperands, |
| 37142 | // GIR_Coverage, 1028, |
| 37143 | GIR_EraseRootFromParent_Done, |
| 37144 | // Label 1967: @101451 |
| 37145 | GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(101510), // Rule ID 3633 // |
| 37146 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 37147 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37148 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37149 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37150 | // (ssubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 37151 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37152 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37153 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 37154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs32), |
| 37155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37156 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37157 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37159 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37160 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37161 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37162 | GIR_RootConstrainSelectedInstOperands, |
| 37163 | // GIR_Coverage, 3633, |
| 37164 | GIR_EraseRootFromParent_Done, |
| 37165 | // Label 1968: @101510 |
| 37166 | GIM_Reject, |
| 37167 | // Label 1965: @101511 |
| 37168 | GIM_Reject, |
| 37169 | // Label 1950: @101512 |
| 37170 | GIM_Try, /*On fail goto*//*Label 1969*/ GIMT_Encode4(101558), // Rule ID 1029 // |
| 37171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37172 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 37173 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 37174 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37175 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37176 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37177 | // (ssubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 37178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i8), |
| 37179 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37180 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37181 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37183 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37184 | GIR_RootConstrainSelectedInstOperands, |
| 37185 | // GIR_Coverage, 1029, |
| 37186 | GIR_EraseRootFromParent_Done, |
| 37187 | // Label 1969: @101558 |
| 37188 | GIM_Reject, |
| 37189 | // Label 1951: @101559 |
| 37190 | GIM_Try, /*On fail goto*//*Label 1970*/ GIMT_Encode4(101670), |
| 37191 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 37192 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 37193 | GIM_Try, /*On fail goto*//*Label 1971*/ GIMT_Encode4(101610), // Rule ID 1027 // |
| 37194 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37196 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37197 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37198 | // (ssubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 37199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i16), |
| 37200 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37201 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37202 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37204 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37205 | GIR_RootConstrainSelectedInstOperands, |
| 37206 | // GIR_Coverage, 1027, |
| 37207 | GIR_EraseRootFromParent_Done, |
| 37208 | // Label 1971: @101610 |
| 37209 | GIM_Try, /*On fail goto*//*Label 1972*/ GIMT_Encode4(101669), // Rule ID 3630 // |
| 37210 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 37211 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37212 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37213 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37214 | // (ssubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 37215 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37216 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37217 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 37218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs16), |
| 37219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37220 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37221 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37223 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37224 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37225 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37226 | GIR_RootConstrainSelectedInstOperands, |
| 37227 | // GIR_Coverage, 3630, |
| 37228 | GIR_EraseRootFromParent_Done, |
| 37229 | // Label 1972: @101669 |
| 37230 | GIM_Reject, |
| 37231 | // Label 1970: @101670 |
| 37232 | GIM_Reject, |
| 37233 | // Label 1952: @101671 |
| 37234 | GIM_Try, /*On fail goto*//*Label 1973*/ GIMT_Encode4(101782), |
| 37235 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 37236 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 37237 | GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(101722), // Rule ID 1030 // |
| 37238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37240 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37241 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37242 | // (ssubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 37243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv16i8), |
| 37244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37245 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37246 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37248 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37249 | GIR_RootConstrainSelectedInstOperands, |
| 37250 | // GIR_Coverage, 1030, |
| 37251 | GIR_EraseRootFromParent_Done, |
| 37252 | // Label 1974: @101722 |
| 37253 | GIM_Try, /*On fail goto*//*Label 1975*/ GIMT_Encode4(101781), // Rule ID 3627 // |
| 37254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 37255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37256 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37257 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37258 | // (ssubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 37259 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37260 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37261 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 37262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs8), |
| 37263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37264 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37265 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37267 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37268 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37269 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37270 | GIR_RootConstrainSelectedInstOperands, |
| 37271 | // GIR_Coverage, 3627, |
| 37272 | GIR_EraseRootFromParent_Done, |
| 37273 | // Label 1975: @101781 |
| 37274 | GIM_Reject, |
| 37275 | // Label 1973: @101782 |
| 37276 | GIM_Reject, |
| 37277 | // Label 1953: @101783 |
| 37278 | GIM_Reject, |
| 37279 | // Label 31: @101784 |
| 37280 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 1983*/ GIMT_Encode4(104095), |
| 37281 | /*GILLT_s16*//*Label 1976*/ GIMT_Encode4(101847), |
| 37282 | /*GILLT_s32*//*Label 1977*/ GIMT_Encode4(101894), |
| 37283 | /*GILLT_s64*//*Label 1978*/ GIMT_Encode4(103452), GIMT_Encode4(0), |
| 37284 | /*GILLT_v2s32*//*Label 1979*/ GIMT_Encode4(103499), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37285 | /*GILLT_v4s16*//*Label 1980*/ GIMT_Encode4(103546), |
| 37286 | /*GILLT_v4s32*//*Label 1981*/ GIMT_Encode4(103731), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37287 | /*GILLT_v8s16*//*Label 1982*/ GIMT_Encode4(103843), |
| 37288 | // Label 1976: @101847 |
| 37289 | GIM_Try, /*On fail goto*//*Label 1984*/ GIMT_Encode4(101893), // Rule ID 631 // |
| 37290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 37291 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 37292 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 37293 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 37294 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 37295 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 37296 | // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 37297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH), |
| 37298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 37299 | GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 37300 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 37301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37302 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37303 | GIR_RootConstrainSelectedInstOperands, |
| 37304 | // GIR_Coverage, 631, |
| 37305 | GIR_EraseRootFromParent_Done, |
| 37306 | // Label 1984: @101893 |
| 37307 | GIM_Reject, |
| 37308 | // Label 1977: @101894 |
| 37309 | GIM_Try, /*On fail goto*//*Label 1985*/ GIMT_Encode4(103451), |
| 37310 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 37311 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 37312 | GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(102225), // Rule ID 6038 // |
| 37313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), |
| 37314 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37315 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37316 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37317 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37318 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 37319 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37320 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37321 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37322 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37323 | // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 37324 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 37325 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 37326 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 37327 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 37328 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 37329 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 37330 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 37331 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 37332 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 37333 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 37334 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 37335 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37336 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37337 | GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 37338 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37339 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37340 | GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 37341 | GIR_ConstrainSelectedInstOperands, /*InsnID*/10, |
| 37342 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37343 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37344 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 37345 | GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 37346 | GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 37347 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37348 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37349 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37350 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37351 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37352 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 37353 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37354 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37355 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 37356 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 37357 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37358 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37359 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 37360 | GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 37361 | GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 37362 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37363 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37364 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37365 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37366 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37367 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 37368 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37369 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37370 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 37371 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 37372 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37373 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37374 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 37375 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc |
| 37376 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 37377 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37378 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37379 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37380 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd), |
| 37381 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37382 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 37383 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 37384 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 37385 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 37386 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37387 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37388 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37389 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37390 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 37391 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 37392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37393 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 37394 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 37395 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 37396 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37397 | // GIR_Coverage, 6038, |
| 37398 | GIR_EraseRootFromParent_Done, |
| 37399 | // Label 1986: @102225 |
| 37400 | GIM_Try, /*On fail goto*//*Label 1987*/ GIMT_Encode4(102545), // Rule ID 6039 // |
| 37401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), |
| 37402 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37403 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37404 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37405 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37406 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 37407 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37408 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37409 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37410 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37411 | // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 37412 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 37413 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 37414 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 37415 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 37416 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 37417 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 37418 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 37419 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 37420 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 37421 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 37422 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 37423 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37424 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37425 | GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 37426 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37427 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37428 | GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 37429 | GIR_ConstrainSelectedInstOperands, /*InsnID*/10, |
| 37430 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37431 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37432 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 37433 | GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 37434 | GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 37435 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37436 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37437 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37438 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37439 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37440 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 37441 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37442 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37443 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 37444 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 37445 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37446 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37447 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 37448 | GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 37449 | GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 37450 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37451 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37452 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37453 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37454 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37455 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 37456 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37457 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37458 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 37459 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 37460 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37461 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37462 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 37463 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc |
| 37464 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 37465 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37466 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37467 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37468 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 37469 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37470 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 37471 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 37472 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 37473 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 37474 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37475 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37476 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37477 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37478 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 37479 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 37480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 37482 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 37483 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 37484 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37485 | // GIR_Coverage, 6039, |
| 37486 | GIR_EraseRootFromParent_Done, |
| 37487 | // Label 1987: @102545 |
| 37488 | GIM_Try, /*On fail goto*//*Label 1988*/ GIMT_Encode4(102865), // Rule ID 2718 // |
| 37489 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), |
| 37490 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37491 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37492 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37493 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37494 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37495 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 37496 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37497 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37498 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37499 | // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 37500 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 37501 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 37502 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 37503 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 37504 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 37505 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 37506 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 37507 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 37508 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 37509 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 37510 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 37511 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37512 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37513 | GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 37514 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37515 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37516 | GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 37517 | GIR_ConstrainSelectedInstOperands, /*InsnID*/10, |
| 37518 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37519 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37520 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 37521 | GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 37522 | GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 37523 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37524 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37525 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37526 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37527 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37528 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 37529 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37530 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37531 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 37532 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 37533 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37534 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37535 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 37536 | GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 37537 | GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 37538 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37539 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37540 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37541 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37542 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37543 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 37544 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37545 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37546 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 37547 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 37548 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37549 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37550 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 37551 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 37552 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 37553 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37554 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37555 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37556 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd), |
| 37557 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37558 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 37559 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 37560 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 37561 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 37562 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37563 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37564 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37565 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37566 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 37567 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 37568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 37570 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 37571 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 37572 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37573 | // GIR_Coverage, 2718, |
| 37574 | GIR_EraseRootFromParent_Done, |
| 37575 | // Label 1988: @102865 |
| 37576 | GIM_Try, /*On fail goto*//*Label 1989*/ GIMT_Encode4(103185), // Rule ID 2720 // |
| 37577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), |
| 37578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37579 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37580 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37581 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37582 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37583 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 37584 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37585 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37586 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37587 | // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 37588 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 37589 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 37590 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 37591 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 37592 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 37593 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 37594 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 37595 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 37596 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 37597 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 37598 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 37599 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37600 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37601 | GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 37602 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37603 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37604 | GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 37605 | GIR_ConstrainSelectedInstOperands, /*InsnID*/10, |
| 37606 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37607 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37608 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 37609 | GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 37610 | GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 37611 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37612 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37613 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37614 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37615 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37616 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 37617 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37618 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37619 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 37620 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 37621 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37622 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37623 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 37624 | GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 37625 | GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 37626 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37627 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37628 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37629 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37630 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37631 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 37632 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37633 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37634 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 37635 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 37636 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37637 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37638 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 37639 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 37640 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 37641 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37642 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37643 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37644 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 37645 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37646 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 37647 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 37648 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 37649 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 37650 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37651 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37652 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37653 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37654 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 37655 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 37656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 37658 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 37659 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 37660 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37661 | // GIR_Coverage, 2720, |
| 37662 | GIR_EraseRootFromParent_Done, |
| 37663 | // Label 1989: @103185 |
| 37664 | GIM_Try, /*On fail goto*//*Label 1990*/ GIMT_Encode4(103225), // Rule ID 630 // |
| 37665 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 37666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37667 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37668 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37669 | // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 37670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS), |
| 37671 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 37672 | GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 37673 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 37674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37675 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37676 | GIR_RootConstrainSelectedInstOperands, |
| 37677 | // GIR_Coverage, 630, |
| 37678 | GIR_EraseRootFromParent_Done, |
| 37679 | // Label 1990: @103225 |
| 37680 | GIM_Try, /*On fail goto*//*Label 1991*/ GIMT_Encode4(103450), // Rule ID 2715 // |
| 37681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 37682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37683 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37684 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37685 | // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VADDfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 37686 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 37687 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 37688 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 37689 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 37690 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 37691 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 37692 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 37693 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 37694 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37695 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37696 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 37697 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37698 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37699 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 37700 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 37701 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37702 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37703 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 37704 | GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 37705 | GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 37706 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37707 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37708 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37709 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37710 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37711 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 37712 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37713 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37714 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 37715 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 37716 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37717 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37718 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 37719 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 37720 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 37721 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37722 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37723 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37724 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VADDfd), |
| 37725 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37726 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 37727 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 37728 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 37729 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37730 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37731 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37732 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37733 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 37734 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 37735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 37737 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 37738 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 37739 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37740 | // GIR_Coverage, 2715, |
| 37741 | GIR_EraseRootFromParent_Done, |
| 37742 | // Label 1991: @103450 |
| 37743 | GIM_Reject, |
| 37744 | // Label 1985: @103451 |
| 37745 | GIM_Reject, |
| 37746 | // Label 1978: @103452 |
| 37747 | GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(103498), // Rule ID 629 // |
| 37748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 37749 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 37750 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 37751 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37752 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37753 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37754 | // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 37755 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD), |
| 37756 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 37757 | GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 37758 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 37759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37760 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37761 | GIR_RootConstrainSelectedInstOperands, |
| 37762 | // GIR_Coverage, 629, |
| 37763 | GIR_EraseRootFromParent_Done, |
| 37764 | // Label 1992: @103498 |
| 37765 | GIM_Reject, |
| 37766 | // Label 1979: @103499 |
| 37767 | GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(103545), // Rule ID 781 // |
| 37768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37769 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 37770 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37772 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37773 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37774 | // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 37775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfd), |
| 37776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37777 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37778 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37780 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37781 | GIR_RootConstrainSelectedInstOperands, |
| 37782 | // GIR_Coverage, 781, |
| 37783 | GIR_EraseRootFromParent_Done, |
| 37784 | // Label 1993: @103545 |
| 37785 | GIM_Reject, |
| 37786 | // Label 1980: @103546 |
| 37787 | GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(103730), |
| 37788 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 37789 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37791 | GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(103627), // Rule ID 5701 // |
| 37792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 37793 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37794 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37795 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 37796 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37797 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37798 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37799 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37800 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37801 | // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm), DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 37802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 37803 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37804 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 37805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 37806 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 37807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37808 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37809 | GIR_RootConstrainSelectedInstOperands, |
| 37810 | // GIR_Coverage, 5701, |
| 37811 | GIR_EraseRootFromParent_Done, |
| 37812 | // Label 1995: @103627 |
| 37813 | GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(103693), // Rule ID 962 // |
| 37814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 37815 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37816 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37817 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37818 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 37819 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37820 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37821 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37822 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37823 | // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 37824 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 37825 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37826 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37827 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 37828 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 37829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37830 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37831 | GIR_RootConstrainSelectedInstOperands, |
| 37832 | // GIR_Coverage, 962, |
| 37833 | GIR_EraseRootFromParent_Done, |
| 37834 | // Label 1996: @103693 |
| 37835 | GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(103729), // Rule ID 783 // |
| 37836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 37837 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37838 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37839 | // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 37840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhd), |
| 37841 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37842 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37843 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37844 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37845 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37846 | GIR_RootConstrainSelectedInstOperands, |
| 37847 | // GIR_Coverage, 783, |
| 37848 | GIR_EraseRootFromParent_Done, |
| 37849 | // Label 1997: @103729 |
| 37850 | GIM_Reject, |
| 37851 | // Label 1994: @103730 |
| 37852 | GIM_Reject, |
| 37853 | // Label 1981: @103731 |
| 37854 | GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(103842), |
| 37855 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 37856 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 37857 | GIM_Try, /*On fail goto*//*Label 1999*/ GIMT_Encode4(103782), // Rule ID 782 // |
| 37858 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37860 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37861 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37862 | // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 37863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfq), |
| 37864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37865 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37866 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37868 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37869 | GIR_RootConstrainSelectedInstOperands, |
| 37870 | // GIR_Coverage, 782, |
| 37871 | GIR_EraseRootFromParent_Done, |
| 37872 | // Label 1999: @103782 |
| 37873 | GIM_Try, /*On fail goto*//*Label 2000*/ GIMT_Encode4(103841), // Rule ID 4131 // |
| 37874 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 37875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37876 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37877 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37878 | // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 37879 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37880 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37881 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 37882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32), |
| 37883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37884 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37885 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37887 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37888 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37889 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37890 | GIR_RootConstrainSelectedInstOperands, |
| 37891 | // GIR_Coverage, 4131, |
| 37892 | GIR_EraseRootFromParent_Done, |
| 37893 | // Label 2000: @103841 |
| 37894 | GIM_Reject, |
| 37895 | // Label 1998: @103842 |
| 37896 | GIM_Reject, |
| 37897 | // Label 1982: @103843 |
| 37898 | GIM_Try, /*On fail goto*//*Label 2001*/ GIMT_Encode4(104094), |
| 37899 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 37900 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 37901 | GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(103924), // Rule ID 5702 // |
| 37902 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 37903 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37904 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37905 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37906 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 37907 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 37908 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37909 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37910 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37911 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37912 | // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm), QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 37913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 37914 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37915 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 37916 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 37917 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 37918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37919 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37920 | GIR_RootConstrainSelectedInstOperands, |
| 37921 | // GIR_Coverage, 5702, |
| 37922 | GIR_EraseRootFromParent_Done, |
| 37923 | // Label 2002: @103924 |
| 37924 | GIM_Try, /*On fail goto*//*Label 2003*/ GIMT_Encode4(103994), // Rule ID 963 // |
| 37925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 37926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37927 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37928 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37929 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37930 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 37931 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 37932 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37933 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37934 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37935 | // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 37936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 37937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37938 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37939 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 37940 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 37941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37942 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37943 | GIR_RootConstrainSelectedInstOperands, |
| 37944 | // GIR_Coverage, 963, |
| 37945 | GIR_EraseRootFromParent_Done, |
| 37946 | // Label 2003: @103994 |
| 37947 | GIM_Try, /*On fail goto*//*Label 2004*/ GIMT_Encode4(104034), // Rule ID 784 // |
| 37948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 37949 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37950 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37951 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37952 | // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 37953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhq), |
| 37954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37955 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37956 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37958 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37959 | GIR_RootConstrainSelectedInstOperands, |
| 37960 | // GIR_Coverage, 784, |
| 37961 | GIR_EraseRootFromParent_Done, |
| 37962 | // Label 2004: @104034 |
| 37963 | GIM_Try, /*On fail goto*//*Label 2005*/ GIMT_Encode4(104093), // Rule ID 4135 // |
| 37964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 37965 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37966 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37967 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37968 | // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 37969 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37970 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37971 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 37972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16), |
| 37973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37974 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37975 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37977 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37978 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37979 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37980 | GIR_RootConstrainSelectedInstOperands, |
| 37981 | // GIR_Coverage, 4135, |
| 37982 | GIR_EraseRootFromParent_Done, |
| 37983 | // Label 2005: @104093 |
| 37984 | GIM_Reject, |
| 37985 | // Label 2001: @104094 |
| 37986 | GIM_Reject, |
| 37987 | // Label 1983: @104095 |
| 37988 | GIM_Reject, |
| 37989 | // Label 32: @104096 |
| 37990 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2013*/ GIMT_Encode4(105759), |
| 37991 | /*GILLT_s16*//*Label 2006*/ GIMT_Encode4(104159), |
| 37992 | /*GILLT_s32*//*Label 2007*/ GIMT_Encode4(104206), |
| 37993 | /*GILLT_s64*//*Label 2008*/ GIMT_Encode4(105124), GIMT_Encode4(0), |
| 37994 | /*GILLT_v2s32*//*Label 2009*/ GIMT_Encode4(105171), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37995 | /*GILLT_v4s16*//*Label 2010*/ GIMT_Encode4(105218), |
| 37996 | /*GILLT_v4s32*//*Label 2011*/ GIMT_Encode4(105395), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37997 | /*GILLT_v8s16*//*Label 2012*/ GIMT_Encode4(105507), |
| 37998 | // Label 2006: @104159 |
| 37999 | GIM_Try, /*On fail goto*//*Label 2014*/ GIMT_Encode4(104205), // Rule ID 634 // |
| 38000 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 38001 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 38002 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 38003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38004 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38005 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38006 | // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 38007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH), |
| 38008 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38009 | GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38010 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38012 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38013 | GIR_RootConstrainSelectedInstOperands, |
| 38014 | // GIR_Coverage, 634, |
| 38015 | GIR_EraseRootFromParent_Done, |
| 38016 | // Label 2014: @104205 |
| 38017 | GIM_Reject, |
| 38018 | // Label 2007: @104206 |
| 38019 | GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(105123), |
| 38020 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 38021 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 38022 | GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(104537), // Rule ID 2719 // |
| 38023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), |
| 38024 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38025 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38026 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38027 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38028 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38029 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38030 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38031 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38032 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38033 | // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38034 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38035 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38036 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38037 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38038 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38039 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38040 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38041 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38042 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38043 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38044 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38045 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38046 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38047 | GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38048 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38049 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38050 | GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38051 | GIR_ConstrainSelectedInstOperands, /*InsnID*/10, |
| 38052 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38053 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38054 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38055 | GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38056 | GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38057 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38058 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38059 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38060 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38061 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38062 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38063 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38064 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38065 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38066 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 38067 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38068 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38069 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38070 | GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38071 | GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38072 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38073 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38074 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38075 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38076 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38077 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38078 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38079 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38080 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38081 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 38082 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38083 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38084 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38085 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 38086 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38087 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38088 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38089 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38090 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLSfd), |
| 38091 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38092 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38093 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38094 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38095 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38096 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38097 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38098 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38099 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38100 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38101 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 38102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38104 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38105 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38106 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38107 | // GIR_Coverage, 2719, |
| 38108 | GIR_EraseRootFromParent_Done, |
| 38109 | // Label 2016: @104537 |
| 38110 | GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(104857), // Rule ID 2721 // |
| 38111 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), |
| 38112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38113 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38114 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38115 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38116 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38117 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38118 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38119 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38120 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38121 | // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38122 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38123 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38124 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38125 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38126 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38127 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38128 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38129 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38130 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38131 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38132 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38133 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38134 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38135 | GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38136 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38137 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38138 | GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/10, |
| 38140 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38141 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38142 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38143 | GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38144 | GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38145 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38146 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38147 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38148 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38149 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38150 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38151 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38152 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38153 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38154 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 38155 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38156 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38157 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38158 | GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38159 | GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38160 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38161 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38162 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38163 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38164 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38165 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38166 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38167 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38168 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38169 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 38170 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38171 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38172 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38173 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 38174 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38175 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38176 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38177 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38178 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 38179 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38180 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38181 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38182 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38183 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38184 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38185 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38186 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38187 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38188 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38189 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 38190 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38191 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38192 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38193 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38194 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38195 | // GIR_Coverage, 2721, |
| 38196 | GIR_EraseRootFromParent_Done, |
| 38197 | // Label 2017: @104857 |
| 38198 | GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(104897), // Rule ID 633 // |
| 38199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 38200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38201 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38202 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38203 | // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 38204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS), |
| 38205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38206 | GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38207 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38209 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38210 | GIR_RootConstrainSelectedInstOperands, |
| 38211 | // GIR_Coverage, 633, |
| 38212 | GIR_EraseRootFromParent_Done, |
| 38213 | // Label 2018: @104897 |
| 38214 | GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(105122), // Rule ID 2716 // |
| 38215 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 38216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38217 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38218 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38219 | // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VSUBfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38220 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38221 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38222 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38223 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38224 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38225 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38226 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38227 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38228 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38229 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38230 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38231 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38232 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38233 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38234 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 38235 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38236 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38237 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38238 | GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 38239 | GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38240 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38241 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38242 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38243 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38244 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38245 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38246 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38247 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38248 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38249 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 38250 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38251 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38252 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38253 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 38254 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38255 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38256 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38257 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38258 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VSUBfd), |
| 38259 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38260 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38261 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38262 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38263 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38264 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38265 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38266 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38267 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38268 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 38269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38271 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38272 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38273 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38274 | // GIR_Coverage, 2716, |
| 38275 | GIR_EraseRootFromParent_Done, |
| 38276 | // Label 2019: @105122 |
| 38277 | GIM_Reject, |
| 38278 | // Label 2015: @105123 |
| 38279 | GIM_Reject, |
| 38280 | // Label 2008: @105124 |
| 38281 | GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(105170), // Rule ID 632 // |
| 38282 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 38283 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 38284 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 38285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38286 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38287 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38288 | // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 38289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD), |
| 38290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 38291 | GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 38292 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 38293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38294 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38295 | GIR_RootConstrainSelectedInstOperands, |
| 38296 | // GIR_Coverage, 632, |
| 38297 | GIR_EraseRootFromParent_Done, |
| 38298 | // Label 2020: @105170 |
| 38299 | GIM_Reject, |
| 38300 | // Label 2009: @105171 |
| 38301 | GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(105217), // Rule ID 985 // |
| 38302 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38303 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 38304 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38306 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38307 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38308 | // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 38309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfd), |
| 38310 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38311 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38312 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38314 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38315 | GIR_RootConstrainSelectedInstOperands, |
| 38316 | // GIR_Coverage, 985, |
| 38317 | GIR_EraseRootFromParent_Done, |
| 38318 | // Label 2021: @105217 |
| 38319 | GIM_Reject, |
| 38320 | // Label 2010: @105218 |
| 38321 | GIM_Try, /*On fail goto*//*Label 2022*/ GIMT_Encode4(105394), |
| 38322 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38323 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38325 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38326 | GIM_Try, /*On fail goto*//*Label 2023*/ GIMT_Encode4(105299), // Rule ID 940 // |
| 38327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), |
| 38328 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38329 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38330 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38331 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38332 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38333 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38334 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38335 | // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShd), |
| 38337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38338 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38339 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38340 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38342 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38343 | GIR_RootConstrainSelectedInstOperands, |
| 38344 | // GIR_Coverage, 940, |
| 38345 | GIR_EraseRootFromParent_Done, |
| 38346 | // Label 2023: @105299 |
| 38347 | GIM_Try, /*On fail goto*//*Label 2024*/ GIMT_Encode4(105361), // Rule ID 966 // |
| 38348 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 38349 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38350 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38351 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38352 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38353 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38354 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38355 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38356 | // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShd), |
| 38358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38359 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38360 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38361 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38363 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38364 | GIR_RootConstrainSelectedInstOperands, |
| 38365 | // GIR_Coverage, 966, |
| 38366 | GIR_EraseRootFromParent_Done, |
| 38367 | // Label 2024: @105361 |
| 38368 | GIM_Try, /*On fail goto*//*Label 2025*/ GIMT_Encode4(105393), // Rule ID 987 // |
| 38369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 38370 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38371 | // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38372 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhd), |
| 38373 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38374 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38375 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38377 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38378 | GIR_RootConstrainSelectedInstOperands, |
| 38379 | // GIR_Coverage, 987, |
| 38380 | GIR_EraseRootFromParent_Done, |
| 38381 | // Label 2025: @105393 |
| 38382 | GIM_Reject, |
| 38383 | // Label 2022: @105394 |
| 38384 | GIM_Reject, |
| 38385 | // Label 2011: @105395 |
| 38386 | GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(105506), |
| 38387 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38388 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38389 | GIM_Try, /*On fail goto*//*Label 2027*/ GIMT_Encode4(105446), // Rule ID 986 // |
| 38390 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38391 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38392 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38393 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38394 | // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 38395 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfq), |
| 38396 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38397 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38398 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38400 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38401 | GIR_RootConstrainSelectedInstOperands, |
| 38402 | // GIR_Coverage, 986, |
| 38403 | GIR_EraseRootFromParent_Done, |
| 38404 | // Label 2027: @105446 |
| 38405 | GIM_Try, /*On fail goto*//*Label 2028*/ GIMT_Encode4(105505), // Rule ID 4139 // |
| 38406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 38407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38408 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38409 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38410 | // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 38411 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38412 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38413 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 38414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32), |
| 38415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38416 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38417 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38419 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38420 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38421 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38422 | GIR_RootConstrainSelectedInstOperands, |
| 38423 | // GIR_Coverage, 4139, |
| 38424 | GIR_EraseRootFromParent_Done, |
| 38425 | // Label 2028: @105505 |
| 38426 | GIM_Reject, |
| 38427 | // Label 2026: @105506 |
| 38428 | GIM_Reject, |
| 38429 | // Label 2012: @105507 |
| 38430 | GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(105758), |
| 38431 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38432 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38433 | GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(105588), // Rule ID 941 // |
| 38434 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), |
| 38435 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38436 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38437 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38438 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38439 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38440 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38441 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38442 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38443 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38444 | // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38445 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShq), |
| 38446 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38447 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38448 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38449 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38451 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38452 | GIR_RootConstrainSelectedInstOperands, |
| 38453 | // GIR_Coverage, 941, |
| 38454 | GIR_EraseRootFromParent_Done, |
| 38455 | // Label 2030: @105588 |
| 38456 | GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(105658), // Rule ID 967 // |
| 38457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 38458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38459 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38460 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38461 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38462 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38463 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38464 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38465 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38466 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38467 | // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShq), |
| 38469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38470 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38471 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38472 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38474 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38475 | GIR_RootConstrainSelectedInstOperands, |
| 38476 | // GIR_Coverage, 967, |
| 38477 | GIR_EraseRootFromParent_Done, |
| 38478 | // Label 2031: @105658 |
| 38479 | GIM_Try, /*On fail goto*//*Label 2032*/ GIMT_Encode4(105698), // Rule ID 988 // |
| 38480 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 38481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38482 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38483 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38484 | // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhq), |
| 38486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38487 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38488 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38490 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38491 | GIR_RootConstrainSelectedInstOperands, |
| 38492 | // GIR_Coverage, 988, |
| 38493 | GIR_EraseRootFromParent_Done, |
| 38494 | // Label 2032: @105698 |
| 38495 | GIM_Try, /*On fail goto*//*Label 2033*/ GIMT_Encode4(105757), // Rule ID 4143 // |
| 38496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 38497 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38498 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38499 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38500 | // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 38501 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38502 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38503 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 38504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16), |
| 38505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38506 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38507 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38509 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38510 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38511 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38512 | GIR_RootConstrainSelectedInstOperands, |
| 38513 | // GIR_Coverage, 4143, |
| 38514 | GIR_EraseRootFromParent_Done, |
| 38515 | // Label 2033: @105757 |
| 38516 | GIM_Reject, |
| 38517 | // Label 2029: @105758 |
| 38518 | GIM_Reject, |
| 38519 | // Label 2013: @105759 |
| 38520 | GIM_Reject, |
| 38521 | // Label 33: @105760 |
| 38522 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2041*/ GIMT_Encode4(106739), |
| 38523 | /*GILLT_s16*//*Label 2034*/ GIMT_Encode4(105823), |
| 38524 | /*GILLT_s32*//*Label 2035*/ GIMT_Encode4(105870), |
| 38525 | /*GILLT_s64*//*Label 2036*/ GIMT_Encode4(106262), GIMT_Encode4(0), |
| 38526 | /*GILLT_v2s32*//*Label 2037*/ GIMT_Encode4(106421), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38527 | /*GILLT_v4s16*//*Label 2038*/ GIMT_Encode4(106468), |
| 38528 | /*GILLT_v4s32*//*Label 2039*/ GIMT_Encode4(106515), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38529 | /*GILLT_v8s16*//*Label 2040*/ GIMT_Encode4(106627), |
| 38530 | // Label 2034: @105823 |
| 38531 | GIM_Try, /*On fail goto*//*Label 2042*/ GIMT_Encode4(105869), // Rule ID 640 // |
| 38532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 38533 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 38534 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 38535 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38536 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38537 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38538 | // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 38539 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH), |
| 38540 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38541 | GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38542 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38544 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38545 | GIR_RootConstrainSelectedInstOperands, |
| 38546 | // GIR_Coverage, 640, |
| 38547 | GIR_EraseRootFromParent_Done, |
| 38548 | // Label 2042: @105869 |
| 38549 | GIM_Reject, |
| 38550 | // Label 2035: @105870 |
| 38551 | GIM_Try, /*On fail goto*//*Label 2043*/ GIMT_Encode4(106261), |
| 38552 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 38553 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 38554 | GIM_Try, /*On fail goto*//*Label 2044*/ GIMT_Encode4(105938), // Rule ID 2298 // |
| 38555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NoHonorSignDependentRounding), |
| 38556 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38557 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38558 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 38559 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38560 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38561 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38562 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38563 | // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) |
| 38564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 38565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38566 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38567 | GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 38568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38569 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38570 | GIR_RootConstrainSelectedInstOperands, |
| 38571 | // GIR_Coverage, 2298, |
| 38572 | GIR_EraseRootFromParent_Done, |
| 38573 | // Label 2044: @105938 |
| 38574 | GIM_Try, /*On fail goto*//*Label 2045*/ GIMT_Encode4(105995), // Rule ID 5828 // |
| 38575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NoHonorSignDependentRounding), |
| 38576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38577 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38578 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38579 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 38580 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38581 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38582 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38583 | // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) |
| 38584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 38585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38586 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38587 | GIR_RootToRootCopy, /*OpIdx*/1, // b |
| 38588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38589 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38590 | GIR_RootConstrainSelectedInstOperands, |
| 38591 | // GIR_Coverage, 5828, |
| 38592 | GIR_EraseRootFromParent_Done, |
| 38593 | // Label 2045: @105995 |
| 38594 | GIM_Try, /*On fail goto*//*Label 2046*/ GIMT_Encode4(106035), // Rule ID 639 // |
| 38595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 38596 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38597 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38598 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38599 | // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 38600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS), |
| 38601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38602 | GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38603 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38605 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38606 | GIR_RootConstrainSelectedInstOperands, |
| 38607 | // GIR_Coverage, 639, |
| 38608 | GIR_EraseRootFromParent_Done, |
| 38609 | // Label 2046: @106035 |
| 38610 | GIM_Try, /*On fail goto*//*Label 2047*/ GIMT_Encode4(106260), // Rule ID 2717 // |
| 38611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 38612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38613 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38614 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38615 | // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMULfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38616 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38617 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38618 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38619 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38620 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38621 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38622 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38623 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38624 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38625 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38626 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38627 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38628 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38629 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38630 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 38631 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38632 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38633 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38634 | GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 38635 | GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38636 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38637 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38638 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38639 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38640 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38641 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38642 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38643 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38644 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38645 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 38646 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38647 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38648 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38649 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 38650 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38651 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38652 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38653 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38654 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMULfd), |
| 38655 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38656 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38657 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38658 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38659 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38660 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38661 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38662 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38663 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38664 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 38665 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38666 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38667 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38668 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38669 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38670 | // GIR_Coverage, 2717, |
| 38671 | GIR_EraseRootFromParent_Done, |
| 38672 | // Label 2047: @106260 |
| 38673 | GIM_Reject, |
| 38674 | // Label 2043: @106261 |
| 38675 | GIM_Reject, |
| 38676 | // Label 2036: @106262 |
| 38677 | GIM_Try, /*On fail goto*//*Label 2048*/ GIMT_Encode4(106420), |
| 38678 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 38679 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 38680 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38681 | GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(106330), // Rule ID 2297 // |
| 38682 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding), |
| 38683 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38684 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 38685 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 38686 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38687 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38688 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38689 | // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b) |
| 38690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 38691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 38692 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38693 | GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 38694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38695 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38696 | GIR_RootConstrainSelectedInstOperands, |
| 38697 | // GIR_Coverage, 2297, |
| 38698 | GIR_EraseRootFromParent_Done, |
| 38699 | // Label 2049: @106330 |
| 38700 | GIM_Try, /*On fail goto*//*Label 2050*/ GIMT_Encode4(106383), // Rule ID 5827 // |
| 38701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding), |
| 38702 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38703 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38704 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 38705 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 38706 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38707 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38708 | // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b) |
| 38709 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 38710 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 38711 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38712 | GIR_RootToRootCopy, /*OpIdx*/1, // b |
| 38713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38714 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38715 | GIR_RootConstrainSelectedInstOperands, |
| 38716 | // GIR_Coverage, 5827, |
| 38717 | GIR_EraseRootFromParent_Done, |
| 38718 | // Label 2050: @106383 |
| 38719 | GIM_Try, /*On fail goto*//*Label 2051*/ GIMT_Encode4(106419), // Rule ID 638 // |
| 38720 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 38721 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38722 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38723 | // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 38724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD), |
| 38725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 38726 | GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 38727 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 38728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38729 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38730 | GIR_RootConstrainSelectedInstOperands, |
| 38731 | // GIR_Coverage, 638, |
| 38732 | GIR_EraseRootFromParent_Done, |
| 38733 | // Label 2051: @106419 |
| 38734 | GIM_Reject, |
| 38735 | // Label 2048: @106420 |
| 38736 | GIM_Reject, |
| 38737 | // Label 2037: @106421 |
| 38738 | GIM_Try, /*On fail goto*//*Label 2052*/ GIMT_Encode4(106467), // Rule ID 860 // |
| 38739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38740 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 38741 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38742 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38743 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38744 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38745 | // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 38746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfd), |
| 38747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38748 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38749 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38751 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38752 | GIR_RootConstrainSelectedInstOperands, |
| 38753 | // GIR_Coverage, 860, |
| 38754 | GIR_EraseRootFromParent_Done, |
| 38755 | // Label 2052: @106467 |
| 38756 | GIM_Reject, |
| 38757 | // Label 2038: @106468 |
| 38758 | GIM_Try, /*On fail goto*//*Label 2053*/ GIMT_Encode4(106514), // Rule ID 862 // |
| 38759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 38760 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38761 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38763 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38764 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38765 | // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhd), |
| 38767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38768 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38769 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38771 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38772 | GIR_RootConstrainSelectedInstOperands, |
| 38773 | // GIR_Coverage, 862, |
| 38774 | GIR_EraseRootFromParent_Done, |
| 38775 | // Label 2053: @106514 |
| 38776 | GIM_Reject, |
| 38777 | // Label 2039: @106515 |
| 38778 | GIM_Try, /*On fail goto*//*Label 2054*/ GIMT_Encode4(106626), |
| 38779 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38780 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38781 | GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(106566), // Rule ID 861 // |
| 38782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38783 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38784 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38785 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38786 | // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 38787 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfq), |
| 38788 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38789 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38790 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38792 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38793 | GIR_RootConstrainSelectedInstOperands, |
| 38794 | // GIR_Coverage, 861, |
| 38795 | GIR_EraseRootFromParent_Done, |
| 38796 | // Label 2055: @106566 |
| 38797 | GIM_Try, /*On fail goto*//*Label 2056*/ GIMT_Encode4(106625), // Rule ID 4103 // |
| 38798 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 38799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38800 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38801 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38802 | // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 38803 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38804 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38805 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 38806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32), |
| 38807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38808 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38809 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38811 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38812 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38813 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38814 | GIR_RootConstrainSelectedInstOperands, |
| 38815 | // GIR_Coverage, 4103, |
| 38816 | GIR_EraseRootFromParent_Done, |
| 38817 | // Label 2056: @106625 |
| 38818 | GIM_Reject, |
| 38819 | // Label 2054: @106626 |
| 38820 | GIM_Reject, |
| 38821 | // Label 2040: @106627 |
| 38822 | GIM_Try, /*On fail goto*//*Label 2057*/ GIMT_Encode4(106738), |
| 38823 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38824 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38825 | GIM_Try, /*On fail goto*//*Label 2058*/ GIMT_Encode4(106678), // Rule ID 863 // |
| 38826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 38827 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38828 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38829 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38830 | // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38831 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhq), |
| 38832 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38833 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38834 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38836 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38837 | GIR_RootConstrainSelectedInstOperands, |
| 38838 | // GIR_Coverage, 863, |
| 38839 | GIR_EraseRootFromParent_Done, |
| 38840 | // Label 2058: @106678 |
| 38841 | GIM_Try, /*On fail goto*//*Label 2059*/ GIMT_Encode4(106737), // Rule ID 4107 // |
| 38842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 38843 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38844 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38845 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38846 | // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 38847 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38848 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38849 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 38850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16), |
| 38851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38852 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38853 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38855 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38856 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38857 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38858 | GIR_RootConstrainSelectedInstOperands, |
| 38859 | // GIR_Coverage, 4107, |
| 38860 | GIR_EraseRootFromParent_Done, |
| 38861 | // Label 2059: @106737 |
| 38862 | GIM_Reject, |
| 38863 | // Label 2057: @106738 |
| 38864 | GIM_Reject, |
| 38865 | // Label 2041: @106739 |
| 38866 | GIM_Reject, |
| 38867 | // Label 34: @106740 |
| 38868 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2067*/ GIMT_Encode4(108554), |
| 38869 | /*GILLT_s16*//*Label 2060*/ GIMT_Encode4(106803), |
| 38870 | /*GILLT_s32*//*Label 2061*/ GIMT_Encode4(107190), |
| 38871 | /*GILLT_s64*//*Label 2062*/ GIMT_Encode4(107577), GIMT_Encode4(0), |
| 38872 | /*GILLT_v2s32*//*Label 2063*/ GIMT_Encode4(107964), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38873 | /*GILLT_v4s16*//*Label 2064*/ GIMT_Encode4(108144), |
| 38874 | /*GILLT_v4s32*//*Label 2065*/ GIMT_Encode4(108200), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38875 | /*GILLT_v8s16*//*Label 2066*/ GIMT_Encode4(108440), |
| 38876 | // Label 2060: @106803 |
| 38877 | GIM_Try, /*On fail goto*//*Label 2068*/ GIMT_Encode4(107189), |
| 38878 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 38879 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 38880 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 38881 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38882 | GIM_Try, /*On fail goto*//*Label 2069*/ GIMT_Encode4(106895), // Rule ID 2404 // |
| 38883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 38884 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38885 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 38886 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 38887 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38888 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38889 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 38890 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 38891 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 38892 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38893 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 38894 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 38895 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 38896 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38897 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 38898 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 38899 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38901 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38902 | GIR_RootConstrainSelectedInstOperands, |
| 38903 | // GIR_Coverage, 2404, |
| 38904 | GIR_EraseRootFromParent_Done, |
| 38905 | // Label 2069: @106895 |
| 38906 | GIM_Try, /*On fail goto*//*Label 2070*/ GIMT_Encode4(106969), // Rule ID 5836 // |
| 38907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 38908 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38909 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38910 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 38911 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 38912 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38913 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 38914 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 38915 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 38916 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38917 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 38918 | // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 38919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 38920 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38921 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 38922 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 38923 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 38924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38925 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38926 | GIR_RootConstrainSelectedInstOperands, |
| 38927 | // GIR_Coverage, 5836, |
| 38928 | GIR_EraseRootFromParent_Done, |
| 38929 | // Label 2070: @106969 |
| 38930 | GIM_Try, /*On fail goto*//*Label 2071*/ GIMT_Encode4(107028), // Rule ID 2396 // |
| 38931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 38932 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38933 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 38934 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 38935 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38936 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38937 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38938 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38939 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 38940 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 38941 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38942 | GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 38943 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 38944 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38946 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38947 | GIR_RootConstrainSelectedInstOperands, |
| 38948 | // GIR_Coverage, 2396, |
| 38949 | GIR_EraseRootFromParent_Done, |
| 38950 | // Label 2071: @107028 |
| 38951 | GIM_Try, /*On fail goto*//*Label 2072*/ GIMT_Encode4(107087), // Rule ID 5833 // |
| 38952 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 38953 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38954 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38955 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 38956 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 38957 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38958 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38959 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38960 | // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 38961 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 38962 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38963 | GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 38964 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 38965 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 38966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38967 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38968 | GIR_RootConstrainSelectedInstOperands, |
| 38969 | // GIR_Coverage, 5833, |
| 38970 | GIR_EraseRootFromParent_Done, |
| 38971 | // Label 2072: @107087 |
| 38972 | GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(107146), // Rule ID 2409 // |
| 38973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 38974 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38975 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38976 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38977 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 38978 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 38979 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38980 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38981 | // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 38982 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 38983 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38984 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 38985 | GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38986 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38988 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38989 | GIR_RootConstrainSelectedInstOperands, |
| 38990 | // GIR_Coverage, 2409, |
| 38991 | GIR_EraseRootFromParent_Done, |
| 38992 | // Label 2073: @107146 |
| 38993 | GIM_Try, /*On fail goto*//*Label 2074*/ GIMT_Encode4(107188), // Rule ID 2390 // |
| 38994 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 38995 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38996 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38997 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38998 | // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 38999 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH), |
| 39000 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39001 | GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39002 | GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39003 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39005 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39006 | GIR_RootConstrainSelectedInstOperands, |
| 39007 | // GIR_Coverage, 2390, |
| 39008 | GIR_EraseRootFromParent_Done, |
| 39009 | // Label 2074: @107188 |
| 39010 | GIM_Reject, |
| 39011 | // Label 2068: @107189 |
| 39012 | GIM_Reject, |
| 39013 | // Label 2061: @107190 |
| 39014 | GIM_Try, /*On fail goto*//*Label 2075*/ GIMT_Encode4(107576), |
| 39015 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39016 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39017 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 39018 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39019 | GIM_Try, /*On fail goto*//*Label 2076*/ GIMT_Encode4(107282), // Rule ID 2403 // |
| 39020 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39021 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39022 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39023 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39024 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39025 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39026 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39027 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39028 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 39029 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39030 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39031 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 39033 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39034 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39035 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39036 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39038 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39039 | GIR_RootConstrainSelectedInstOperands, |
| 39040 | // GIR_Coverage, 2403, |
| 39041 | GIR_EraseRootFromParent_Done, |
| 39042 | // Label 2076: @107282 |
| 39043 | GIM_Try, /*On fail goto*//*Label 2077*/ GIMT_Encode4(107356), // Rule ID 5835 // |
| 39044 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39045 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39046 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39047 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39048 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39049 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39050 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39051 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39052 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 39053 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39054 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39055 | // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 39057 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39059 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39060 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39062 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39063 | GIR_RootConstrainSelectedInstOperands, |
| 39064 | // GIR_Coverage, 5835, |
| 39065 | GIR_EraseRootFromParent_Done, |
| 39066 | // Label 2077: @107356 |
| 39067 | GIM_Try, /*On fail goto*//*Label 2078*/ GIMT_Encode4(107415), // Rule ID 2395 // |
| 39068 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39069 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39070 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39071 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39072 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39073 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39074 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39075 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39076 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39077 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 39078 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39079 | GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39080 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39081 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39083 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39084 | GIR_RootConstrainSelectedInstOperands, |
| 39085 | // GIR_Coverage, 2395, |
| 39086 | GIR_EraseRootFromParent_Done, |
| 39087 | // Label 2078: @107415 |
| 39088 | GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(107474), // Rule ID 5832 // |
| 39089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39090 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39091 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39092 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39093 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39094 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39095 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39096 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39097 | // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 39099 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39100 | GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39101 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39102 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39104 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39105 | GIR_RootConstrainSelectedInstOperands, |
| 39106 | // GIR_Coverage, 5832, |
| 39107 | GIR_EraseRootFromParent_Done, |
| 39108 | // Label 2079: @107474 |
| 39109 | GIM_Try, /*On fail goto*//*Label 2080*/ GIMT_Encode4(107533), // Rule ID 2408 // |
| 39110 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39111 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39112 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39113 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39114 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39115 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39116 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39117 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39118 | // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 39120 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39121 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 39122 | GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39123 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39125 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39126 | GIR_RootConstrainSelectedInstOperands, |
| 39127 | // GIR_Coverage, 2408, |
| 39128 | GIR_EraseRootFromParent_Done, |
| 39129 | // Label 2080: @107533 |
| 39130 | GIM_Try, /*On fail goto*//*Label 2081*/ GIMT_Encode4(107575), // Rule ID 2389 // |
| 39131 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39132 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39133 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39134 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39135 | // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS), |
| 39137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39138 | GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39139 | GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39140 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39142 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39143 | GIR_RootConstrainSelectedInstOperands, |
| 39144 | // GIR_Coverage, 2389, |
| 39145 | GIR_EraseRootFromParent_Done, |
| 39146 | // Label 2081: @107575 |
| 39147 | GIM_Reject, |
| 39148 | // Label 2075: @107576 |
| 39149 | GIM_Reject, |
| 39150 | // Label 2062: @107577 |
| 39151 | GIM_Try, /*On fail goto*//*Label 2082*/ GIMT_Encode4(107963), |
| 39152 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 39153 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 39154 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 39155 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39156 | GIM_Try, /*On fail goto*//*Label 2083*/ GIMT_Encode4(107669), // Rule ID 2402 // |
| 39157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 39158 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39159 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39160 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39161 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39162 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39163 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39164 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39165 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 39166 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39167 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39168 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 39170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39171 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 39172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39173 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39175 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39176 | GIR_RootConstrainSelectedInstOperands, |
| 39177 | // GIR_Coverage, 2402, |
| 39178 | GIR_EraseRootFromParent_Done, |
| 39179 | // Label 2083: @107669 |
| 39180 | GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(107743), // Rule ID 5834 // |
| 39181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 39182 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39183 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39184 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39185 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39186 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39187 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39188 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39189 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 39190 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39191 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39192 | // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 39194 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39195 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 39196 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39197 | GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 39198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39199 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39200 | GIR_RootConstrainSelectedInstOperands, |
| 39201 | // GIR_Coverage, 5834, |
| 39202 | GIR_EraseRootFromParent_Done, |
| 39203 | // Label 2084: @107743 |
| 39204 | GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(107802), // Rule ID 2394 // |
| 39205 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 39206 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39207 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39208 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39209 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39210 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39211 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39212 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39213 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 39215 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39216 | GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 39217 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39218 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39220 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39221 | GIR_RootConstrainSelectedInstOperands, |
| 39222 | // GIR_Coverage, 2394, |
| 39223 | GIR_EraseRootFromParent_Done, |
| 39224 | // Label 2085: @107802 |
| 39225 | GIM_Try, /*On fail goto*//*Label 2086*/ GIMT_Encode4(107861), // Rule ID 5831 // |
| 39226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 39227 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39228 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39229 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39230 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39231 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39232 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39233 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39234 | // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39235 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 39236 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39237 | GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 39238 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39239 | GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 39240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39241 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39242 | GIR_RootConstrainSelectedInstOperands, |
| 39243 | // GIR_Coverage, 5831, |
| 39244 | GIR_EraseRootFromParent_Done, |
| 39245 | // Label 2086: @107861 |
| 39246 | GIM_Try, /*On fail goto*//*Label 2087*/ GIMT_Encode4(107920), // Rule ID 2407 // |
| 39247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 39248 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39249 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39250 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39251 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39252 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39253 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39254 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39255 | // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 39257 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin |
| 39259 | GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 39260 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39262 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39263 | GIR_RootConstrainSelectedInstOperands, |
| 39264 | // GIR_Coverage, 2407, |
| 39265 | GIR_EraseRootFromParent_Done, |
| 39266 | // Label 2087: @107920 |
| 39267 | GIM_Try, /*On fail goto*//*Label 2088*/ GIMT_Encode4(107962), // Rule ID 2388 // |
| 39268 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 39269 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39270 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39271 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39272 | // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD), |
| 39274 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39275 | GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 39276 | GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 39277 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39279 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39280 | GIR_RootConstrainSelectedInstOperands, |
| 39281 | // GIR_Coverage, 2388, |
| 39282 | GIR_EraseRootFromParent_Done, |
| 39283 | // Label 2088: @107962 |
| 39284 | GIM_Reject, |
| 39285 | // Label 2082: @107963 |
| 39286 | GIM_Reject, |
| 39287 | // Label 2063: @107964 |
| 39288 | GIM_Try, /*On fail goto*//*Label 2089*/ GIMT_Encode4(108143), |
| 39289 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39290 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39291 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 39292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39293 | GIM_Try, /*On fail goto*//*Label 2090*/ GIMT_Encode4(108041), // Rule ID 2500 // |
| 39294 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 39295 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39296 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39297 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39298 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39299 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39300 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39301 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39302 | // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 39303 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 39304 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39305 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39306 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 39307 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39309 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39310 | GIR_RootConstrainSelectedInstOperands, |
| 39311 | // GIR_Coverage, 2500, |
| 39312 | GIR_EraseRootFromParent_Done, |
| 39313 | // Label 2090: @108041 |
| 39314 | GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(108100), // Rule ID 5874 // |
| 39315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 39316 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39317 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39318 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39319 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39320 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39321 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39322 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39323 | // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm, (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 39324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 39325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39326 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39327 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 39328 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 39329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39330 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39331 | GIR_RootConstrainSelectedInstOperands, |
| 39332 | // GIR_Coverage, 5874, |
| 39333 | GIR_EraseRootFromParent_Done, |
| 39334 | // Label 2091: @108100 |
| 39335 | GIM_Try, /*On fail goto*//*Label 2092*/ GIMT_Encode4(108142), // Rule ID 2498 // |
| 39336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 39337 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39338 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39339 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39340 | // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 39341 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 39342 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39343 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39344 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39345 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39347 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39348 | GIR_RootConstrainSelectedInstOperands, |
| 39349 | // GIR_Coverage, 2498, |
| 39350 | GIR_EraseRootFromParent_Done, |
| 39351 | // Label 2092: @108142 |
| 39352 | GIM_Reject, |
| 39353 | // Label 2089: @108143 |
| 39354 | GIM_Reject, |
| 39355 | // Label 2064: @108144 |
| 39356 | GIM_Try, /*On fail goto*//*Label 2093*/ GIMT_Encode4(108199), // Rule ID 2496 // |
| 39357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 39358 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 39359 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39360 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 39361 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39362 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39363 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39364 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39365 | // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 39366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 39367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39368 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39369 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39370 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39372 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39373 | GIR_RootConstrainSelectedInstOperands, |
| 39374 | // GIR_Coverage, 2496, |
| 39375 | GIR_EraseRootFromParent_Done, |
| 39376 | // Label 2093: @108199 |
| 39377 | GIM_Reject, |
| 39378 | // Label 2065: @108200 |
| 39379 | GIM_Try, /*On fail goto*//*Label 2094*/ GIMT_Encode4(108439), |
| 39380 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39381 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39382 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 39383 | GIM_Try, /*On fail goto*//*Label 2095*/ GIMT_Encode4(108277), // Rule ID 2501 // |
| 39384 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 39385 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39386 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39387 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39388 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39389 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39390 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39391 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39392 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39393 | // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 39394 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq), |
| 39395 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39396 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39397 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 39398 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39400 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39401 | GIR_RootConstrainSelectedInstOperands, |
| 39402 | // GIR_Coverage, 2501, |
| 39403 | GIR_EraseRootFromParent_Done, |
| 39404 | // Label 2095: @108277 |
| 39405 | GIM_Try, /*On fail goto*//*Label 2096*/ GIMT_Encode4(108340), // Rule ID 5875 // |
| 39406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 39407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39408 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39409 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39410 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39411 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39412 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39413 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39414 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39415 | // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm, (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 39416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq), |
| 39417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39418 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39419 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 39420 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 39421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39422 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39423 | GIR_RootConstrainSelectedInstOperands, |
| 39424 | // GIR_Coverage, 5875, |
| 39425 | GIR_EraseRootFromParent_Done, |
| 39426 | // Label 2096: @108340 |
| 39427 | GIM_Try, /*On fail goto*//*Label 2097*/ GIMT_Encode4(108386), // Rule ID 2499 // |
| 39428 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 39429 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39430 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39431 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39432 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39433 | // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 39434 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfq), |
| 39435 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39436 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39437 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39438 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39440 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39441 | GIR_RootConstrainSelectedInstOperands, |
| 39442 | // GIR_Coverage, 2499, |
| 39443 | GIR_EraseRootFromParent_Done, |
| 39444 | // Label 2097: @108386 |
| 39445 | GIM_Try, /*On fail goto*//*Label 2098*/ GIMT_Encode4(108438), // Rule ID 4121 // |
| 39446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 39447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39448 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39449 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39450 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39451 | // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 39452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32), |
| 39453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39454 | GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 39455 | GIR_RootToRootCopy, /*OpIdx*/1, // m1 |
| 39456 | GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 39457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39458 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39459 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39460 | GIR_RootConstrainSelectedInstOperands, |
| 39461 | // GIR_Coverage, 4121, |
| 39462 | GIR_EraseRootFromParent_Done, |
| 39463 | // Label 2098: @108438 |
| 39464 | GIM_Reject, |
| 39465 | // Label 2094: @108439 |
| 39466 | GIM_Reject, |
| 39467 | // Label 2066: @108440 |
| 39468 | GIM_Try, /*On fail goto*//*Label 2099*/ GIMT_Encode4(108553), |
| 39469 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39470 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39471 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 39472 | GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(108500), // Rule ID 2497 // |
| 39473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 39474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39475 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39476 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39477 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39478 | // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 39479 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 39480 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39481 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39482 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39483 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39485 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39486 | GIR_RootConstrainSelectedInstOperands, |
| 39487 | // GIR_Coverage, 2497, |
| 39488 | GIR_EraseRootFromParent_Done, |
| 39489 | // Label 2100: @108500 |
| 39490 | GIM_Try, /*On fail goto*//*Label 2101*/ GIMT_Encode4(108552), // Rule ID 4124 // |
| 39491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 39492 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39493 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39494 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39495 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39496 | // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 39497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16), |
| 39498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39499 | GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 39500 | GIR_RootToRootCopy, /*OpIdx*/1, // m1 |
| 39501 | GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 39502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39503 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39504 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39505 | GIR_RootConstrainSelectedInstOperands, |
| 39506 | // GIR_Coverage, 4124, |
| 39507 | GIR_EraseRootFromParent_Done, |
| 39508 | // Label 2101: @108552 |
| 39509 | GIM_Reject, |
| 39510 | // Label 2099: @108553 |
| 39511 | GIM_Reject, |
| 39512 | // Label 2067: @108554 |
| 39513 | GIM_Reject, |
| 39514 | // Label 35: @108555 |
| 39515 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2105*/ GIMT_Encode4(108719), |
| 39516 | /*GILLT_s16*//*Label 2102*/ GIMT_Encode4(108578), |
| 39517 | /*GILLT_s32*//*Label 2103*/ GIMT_Encode4(108625), |
| 39518 | /*GILLT_s64*//*Label 2104*/ GIMT_Encode4(108672), |
| 39519 | // Label 2102: @108578 |
| 39520 | GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(108624), // Rule ID 637 // |
| 39521 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 39522 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 39523 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 39524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39525 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39526 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39527 | // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39528 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH), |
| 39529 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39530 | GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39531 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39533 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39534 | GIR_RootConstrainSelectedInstOperands, |
| 39535 | // GIR_Coverage, 637, |
| 39536 | GIR_EraseRootFromParent_Done, |
| 39537 | // Label 2106: @108624 |
| 39538 | GIM_Reject, |
| 39539 | // Label 2103: @108625 |
| 39540 | GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(108671), // Rule ID 636 // |
| 39541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2), |
| 39542 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39543 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39544 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39545 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39546 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39547 | // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS), |
| 39549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39550 | GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39551 | GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39553 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39554 | GIR_RootConstrainSelectedInstOperands, |
| 39555 | // GIR_Coverage, 636, |
| 39556 | GIR_EraseRootFromParent_Done, |
| 39557 | // Label 2107: @108671 |
| 39558 | GIM_Reject, |
| 39559 | // Label 2104: @108672 |
| 39560 | GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(108718), // Rule ID 635 // |
| 39561 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 39562 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 39563 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 39564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39565 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39566 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39567 | // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD), |
| 39569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39570 | GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 39571 | GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39573 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39574 | GIR_RootConstrainSelectedInstOperands, |
| 39575 | // GIR_Coverage, 635, |
| 39576 | GIR_EraseRootFromParent_Done, |
| 39577 | // Label 2108: @108718 |
| 39578 | GIM_Reject, |
| 39579 | // Label 2105: @108719 |
| 39580 | GIM_Reject, |
| 39581 | // Label 36: @108720 |
| 39582 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2116*/ GIMT_Encode4(110260), |
| 39583 | /*GILLT_s16*//*Label 2109*/ GIMT_Encode4(108783), |
| 39584 | /*GILLT_s32*//*Label 2110*/ GIMT_Encode4(109130), |
| 39585 | /*GILLT_s64*//*Label 2111*/ GIMT_Encode4(109643), GIMT_Encode4(0), |
| 39586 | /*GILLT_v2s32*//*Label 2112*/ GIMT_Encode4(109990), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39587 | /*GILLT_v4s16*//*Label 2113*/ GIMT_Encode4(110028), |
| 39588 | /*GILLT_v4s32*//*Label 2114*/ GIMT_Encode4(110066), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39589 | /*GILLT_v8s16*//*Label 2115*/ GIMT_Encode4(110163), |
| 39590 | // Label 2109: @108783 |
| 39591 | GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(109129), |
| 39592 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 39593 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39594 | GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(108880), // Rule ID 2412 // |
| 39595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 39596 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39597 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 39598 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39599 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 39600 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 39601 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 39602 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39603 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 39604 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39605 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39606 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39607 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39608 | // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 39610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39611 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 39612 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 39613 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 39614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39615 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39616 | GIR_RootConstrainSelectedInstOperands, |
| 39617 | // GIR_Coverage, 2412, |
| 39618 | GIR_EraseRootFromParent_Done, |
| 39619 | // Label 2118: @108880 |
| 39620 | GIM_Try, /*On fail goto*//*Label 2119*/ GIMT_Encode4(108965), // Rule ID 5839 // |
| 39621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 39622 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39623 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 39624 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39625 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 39626 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 39627 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39628 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39629 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39630 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 39631 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39632 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39633 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39634 | // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 39636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39637 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 39638 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 39639 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 39640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39641 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39642 | GIR_RootConstrainSelectedInstOperands, |
| 39643 | // GIR_Coverage, 5839, |
| 39644 | GIR_EraseRootFromParent_Done, |
| 39645 | // Label 2119: @108965 |
| 39646 | GIM_Try, /*On fail goto*//*Label 2120*/ GIMT_Encode4(109038), // Rule ID 2401 // |
| 39647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 39648 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39649 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 39650 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39651 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 39652 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 39653 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39654 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39655 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39656 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39657 | // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 39659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 39661 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39662 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 39663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39664 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39665 | GIR_RootConstrainSelectedInstOperands, |
| 39666 | // GIR_Coverage, 2401, |
| 39667 | GIR_EraseRootFromParent_Done, |
| 39668 | // Label 2120: @109038 |
| 39669 | GIM_Try, /*On fail goto*//*Label 2121*/ GIMT_Encode4(109098), // Rule ID 643 // |
| 39670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 39671 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39672 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 39673 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39674 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 39675 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39676 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39677 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39678 | // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH), |
| 39680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39681 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 39683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39684 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39685 | GIR_RootConstrainSelectedInstOperands, |
| 39686 | // GIR_Coverage, 643, |
| 39687 | GIR_EraseRootFromParent_Done, |
| 39688 | // Label 2121: @109098 |
| 39689 | GIM_Try, /*On fail goto*//*Label 2122*/ GIMT_Encode4(109128), // Rule ID 681 // |
| 39690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 39691 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39692 | // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 39693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGH), |
| 39694 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39695 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39697 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39698 | GIR_RootConstrainSelectedInstOperands, |
| 39699 | // GIR_Coverage, 681, |
| 39700 | GIR_EraseRootFromParent_Done, |
| 39701 | // Label 2122: @109128 |
| 39702 | GIM_Reject, |
| 39703 | // Label 2117: @109129 |
| 39704 | GIM_Reject, |
| 39705 | // Label 2110: @109130 |
| 39706 | GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(109642), |
| 39707 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39708 | GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(109227), // Rule ID 2411 // |
| 39709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39710 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39711 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39712 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 39713 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39714 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 39715 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 39716 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 39717 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39718 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 39719 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39720 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39721 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39722 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39723 | // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 39725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39726 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 39727 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 39728 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 39729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39730 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39731 | GIR_RootConstrainSelectedInstOperands, |
| 39732 | // GIR_Coverage, 2411, |
| 39733 | GIR_EraseRootFromParent_Done, |
| 39734 | // Label 2124: @109227 |
| 39735 | GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(109316), // Rule ID 5838 // |
| 39736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39737 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39738 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39739 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 39740 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39741 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 39742 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 39743 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39744 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39745 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39746 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 39747 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39748 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39749 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39750 | // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 39752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39753 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 39754 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 39755 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 39756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39757 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39758 | GIR_RootConstrainSelectedInstOperands, |
| 39759 | // GIR_Coverage, 5838, |
| 39760 | GIR_EraseRootFromParent_Done, |
| 39761 | // Label 2125: @109316 |
| 39762 | GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(109393), // Rule ID 2400 // |
| 39763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39764 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39765 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39766 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 39767 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39768 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 39769 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 39770 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39771 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39772 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39773 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39774 | // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 39776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39777 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 39778 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 39780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39781 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39782 | GIR_RootConstrainSelectedInstOperands, |
| 39783 | // GIR_Coverage, 2400, |
| 39784 | GIR_EraseRootFromParent_Done, |
| 39785 | // Label 2126: @109393 |
| 39786 | GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(109457), // Rule ID 642 // |
| 39787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2), |
| 39788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39789 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39790 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 39791 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39792 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 39793 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39794 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39795 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39796 | // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39797 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 39798 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39799 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39800 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 39801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39802 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39803 | GIR_RootConstrainSelectedInstOperands, |
| 39804 | // GIR_Coverage, 642, |
| 39805 | GIR_EraseRootFromParent_Done, |
| 39806 | // Label 2127: @109457 |
| 39807 | GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(109491), // Rule ID 680 // |
| 39808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 39809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39810 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39811 | // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 39812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGS), |
| 39813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39814 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39816 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39817 | GIR_RootConstrainSelectedInstOperands, |
| 39818 | // GIR_Coverage, 680, |
| 39819 | GIR_EraseRootFromParent_Done, |
| 39820 | // Label 2128: @109491 |
| 39821 | GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(109641), // Rule ID 2723 // |
| 39822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 39823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39824 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39825 | // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VNEGfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 39826 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 39827 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 39828 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 39829 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 39830 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 39831 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39832 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39833 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 39834 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39835 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39836 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 39837 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 39838 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 39839 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39840 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 39841 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 39842 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 39843 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39844 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39845 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 39846 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VNEGfd), |
| 39847 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39848 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 39849 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 39850 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39851 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 39852 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39853 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39854 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 39855 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 39856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39857 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 39858 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 39859 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 39860 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39861 | // GIR_Coverage, 2723, |
| 39862 | GIR_EraseRootFromParent_Done, |
| 39863 | // Label 2129: @109641 |
| 39864 | GIM_Reject, |
| 39865 | // Label 2123: @109642 |
| 39866 | GIM_Reject, |
| 39867 | // Label 2111: @109643 |
| 39868 | GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(109989), |
| 39869 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 39870 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39871 | GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(109740), // Rule ID 2410 // |
| 39872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 39873 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39874 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 39875 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39876 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39877 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 39878 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 39879 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39880 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 39881 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39882 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39883 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39884 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39885 | // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 39887 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39888 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 39889 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 39890 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 39891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39892 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39893 | GIR_RootConstrainSelectedInstOperands, |
| 39894 | // GIR_Coverage, 2410, |
| 39895 | GIR_EraseRootFromParent_Done, |
| 39896 | // Label 2131: @109740 |
| 39897 | GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(109825), // Rule ID 5837 // |
| 39898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 39899 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39900 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 39901 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39902 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39903 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 39904 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39905 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39906 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39907 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 39908 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39909 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39910 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39911 | // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 39913 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39914 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 39915 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 39916 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm |
| 39917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39918 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39919 | GIR_RootConstrainSelectedInstOperands, |
| 39920 | // GIR_Coverage, 5837, |
| 39921 | GIR_EraseRootFromParent_Done, |
| 39922 | // Label 2132: @109825 |
| 39923 | GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(109898), // Rule ID 2399 // |
| 39924 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 39925 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39926 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 39927 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39928 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39929 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 39930 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39931 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39932 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39933 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39934 | // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 39936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 39938 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39939 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 39940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39941 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39942 | GIR_RootConstrainSelectedInstOperands, |
| 39943 | // GIR_Coverage, 2399, |
| 39944 | GIR_EraseRootFromParent_Done, |
| 39945 | // Label 2133: @109898 |
| 39946 | GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(109958), // Rule ID 641 // |
| 39947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 39948 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39949 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 39950 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39951 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39952 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39953 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39954 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39955 | // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 39957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39958 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 39960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39961 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39962 | GIR_RootConstrainSelectedInstOperands, |
| 39963 | // GIR_Coverage, 641, |
| 39964 | GIR_EraseRootFromParent_Done, |
| 39965 | // Label 2134: @109958 |
| 39966 | GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(109988), // Rule ID 679 // |
| 39967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 39968 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39969 | // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 39970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGD), |
| 39971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39972 | GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 39973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39974 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39975 | GIR_RootConstrainSelectedInstOperands, |
| 39976 | // GIR_Coverage, 679, |
| 39977 | GIR_EraseRootFromParent_Done, |
| 39978 | // Label 2135: @109988 |
| 39979 | GIM_Reject, |
| 39980 | // Label 2130: @109989 |
| 39981 | GIM_Reject, |
| 39982 | // Label 2112: @109990 |
| 39983 | GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(110027), // Rule ID 1549 // |
| 39984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39985 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39987 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39988 | // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 39989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGfd), |
| 39990 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39991 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 39992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39993 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39994 | GIR_RootConstrainSelectedInstOperands, |
| 39995 | // GIR_Coverage, 1549, |
| 39996 | GIR_EraseRootFromParent_Done, |
| 39997 | // Label 2136: @110027 |
| 39998 | GIM_Reject, |
| 39999 | // Label 2113: @110028 |
| 40000 | GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(110065), // Rule ID 1551 // |
| 40001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 40002 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 40003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40004 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40005 | // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 40006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhd), |
| 40007 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40008 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40010 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40011 | GIR_RootConstrainSelectedInstOperands, |
| 40012 | // GIR_Coverage, 1551, |
| 40013 | GIR_EraseRootFromParent_Done, |
| 40014 | // Label 2137: @110065 |
| 40015 | GIM_Reject, |
| 40016 | // Label 2114: @110066 |
| 40017 | GIM_Try, /*On fail goto*//*Label 2138*/ GIMT_Encode4(110162), |
| 40018 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40019 | GIM_Try, /*On fail goto*//*Label 2139*/ GIMT_Encode4(110108), // Rule ID 1550 // |
| 40020 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40021 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40022 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40023 | // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 40024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGf32q), |
| 40025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40026 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40028 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40029 | GIR_RootConstrainSelectedInstOperands, |
| 40030 | // GIR_Coverage, 1550, |
| 40031 | GIR_EraseRootFromParent_Done, |
| 40032 | // Label 2139: @110108 |
| 40033 | GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(110161), // Rule ID 4231 // |
| 40034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 40035 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40036 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40037 | // (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VNEGf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v) |
| 40038 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40039 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40040 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 40041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf32), |
| 40042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40043 | GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 40044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40045 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40046 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40047 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40048 | GIR_RootConstrainSelectedInstOperands, |
| 40049 | // GIR_Coverage, 4231, |
| 40050 | GIR_EraseRootFromParent_Done, |
| 40051 | // Label 2140: @110161 |
| 40052 | GIM_Reject, |
| 40053 | // Label 2138: @110162 |
| 40054 | GIM_Reject, |
| 40055 | // Label 2115: @110163 |
| 40056 | GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(110259), |
| 40057 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 40058 | GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(110205), // Rule ID 1552 // |
| 40059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 40060 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40061 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40062 | // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 40063 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhq), |
| 40064 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40065 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40067 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40068 | GIR_RootConstrainSelectedInstOperands, |
| 40069 | // GIR_Coverage, 1552, |
| 40070 | GIR_EraseRootFromParent_Done, |
| 40071 | // Label 2142: @110205 |
| 40072 | GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(110258), // Rule ID 4229 // |
| 40073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 40074 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40075 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40076 | // (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VNEGf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v) |
| 40077 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40078 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40079 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 40080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf16), |
| 40081 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40082 | GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 40083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40084 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40085 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40086 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40087 | GIR_RootConstrainSelectedInstOperands, |
| 40088 | // GIR_Coverage, 4229, |
| 40089 | GIR_EraseRootFromParent_Done, |
| 40090 | // Label 2143: @110258 |
| 40091 | GIM_Reject, |
| 40092 | // Label 2141: @110259 |
| 40093 | GIM_Reject, |
| 40094 | // Label 2116: @110260 |
| 40095 | GIM_Reject, |
| 40096 | // Label 37: @110261 |
| 40097 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 2147*/ GIMT_Encode4(110490), |
| 40098 | /*GILLT_s32*//*Label 2144*/ GIMT_Encode4(110304), |
| 40099 | /*GILLT_s64*//*Label 2145*/ GIMT_Encode4(110361), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40100 | /*GILLT_v4s32*//*Label 2146*/ GIMT_Encode4(110455), |
| 40101 | // Label 2144: @110304 |
| 40102 | GIM_Try, /*On fail goto*//*Label 2148*/ GIMT_Encode4(110360), // Rule ID 2299 // |
| 40103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16), |
| 40104 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40105 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40106 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40107 | // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm) => (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] })) |
| 40108 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40109 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40110 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40111 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 40112 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHS), |
| 40114 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40115 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40117 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40118 | GIR_RootConstrainSelectedInstOperands, |
| 40119 | // GIR_Coverage, 2299, |
| 40120 | GIR_EraseRootFromParent_Done, |
| 40121 | // Label 2148: @110360 |
| 40122 | GIM_Reject, |
| 40123 | // Label 2145: @110361 |
| 40124 | GIM_Try, /*On fail goto*//*Label 2149*/ GIMT_Encode4(110398), // Rule ID 677 // |
| 40125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 40126 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40128 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40129 | // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm) => (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm) |
| 40130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTDS), |
| 40131 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40132 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 40133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40134 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40135 | GIR_RootConstrainSelectedInstOperands, |
| 40136 | // GIR_Coverage, 677, |
| 40137 | GIR_EraseRootFromParent_Done, |
| 40138 | // Label 2149: @110398 |
| 40139 | GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(110454), // Rule ID 2309 // |
| 40140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 40141 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40143 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40144 | // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm) => (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] })) |
| 40145 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40146 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40147 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40148 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 40149 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHD), |
| 40151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40152 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40154 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40155 | GIR_RootConstrainSelectedInstOperands, |
| 40156 | // GIR_Coverage, 2309, |
| 40157 | GIR_EraseRootFromParent_Done, |
| 40158 | // Label 2150: @110454 |
| 40159 | GIM_Reject, |
| 40160 | // Label 2146: @110455 |
| 40161 | GIM_Try, /*On fail goto*//*Label 2151*/ GIMT_Encode4(110489), // Rule ID 2681 // |
| 40162 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 40163 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40164 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40165 | // (fpextend:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) |
| 40166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f), |
| 40167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40168 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 40169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40170 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40171 | GIR_RootConstrainSelectedInstOperands, |
| 40172 | // GIR_Coverage, 2681, |
| 40173 | GIR_EraseRootFromParent_Done, |
| 40174 | // Label 2151: @110489 |
| 40175 | GIM_Reject, |
| 40176 | // Label 2147: @110490 |
| 40177 | GIM_Reject, |
| 40178 | // Label 38: @110491 |
| 40179 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 2155*/ GIMT_Encode4(110762), |
| 40180 | /*GILLT_s16*//*Label 2152*/ GIMT_Encode4(110534), |
| 40181 | /*GILLT_s32*//*Label 2153*/ GIMT_Encode4(110689), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40182 | /*GILLT_v4s16*//*Label 2154*/ GIMT_Encode4(110727), |
| 40183 | // Label 2152: @110534 |
| 40184 | GIM_Try, /*On fail goto*//*Label 2156*/ GIMT_Encode4(110611), // Rule ID 2301 // |
| 40185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16), |
| 40186 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40188 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40189 | // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] }) |
| 40190 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40191 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 40192 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40193 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40194 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 40195 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBSH), |
| 40196 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40197 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 40198 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 40199 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 40200 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40201 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40204 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40205 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 40206 | // GIR_Coverage, 2301, |
| 40207 | GIR_EraseRootFromParent_Done, |
| 40208 | // Label 2156: @110611 |
| 40209 | GIM_Try, /*On fail goto*//*Label 2157*/ GIMT_Encode4(110688), // Rule ID 2311 // |
| 40210 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 40211 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40213 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40214 | // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] }) |
| 40215 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40216 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 40217 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40218 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40219 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 40220 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBDH), |
| 40221 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40222 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 40223 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm |
| 40224 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 40225 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40226 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40227 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40228 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40229 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40230 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 40231 | // GIR_Coverage, 2311, |
| 40232 | GIR_EraseRootFromParent_Done, |
| 40233 | // Label 2157: @110688 |
| 40234 | GIM_Reject, |
| 40235 | // Label 2153: @110689 |
| 40236 | GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(110726), // Rule ID 678 // |
| 40237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 40238 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40240 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40241 | // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm) => (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 40242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTSD), |
| 40243 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40244 | GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 40245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40246 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40247 | GIR_RootConstrainSelectedInstOperands, |
| 40248 | // GIR_Coverage, 678, |
| 40249 | GIR_EraseRootFromParent_Done, |
| 40250 | // Label 2158: @110726 |
| 40251 | GIM_Reject, |
| 40252 | // Label 2154: @110727 |
| 40253 | GIM_Try, /*On fail goto*//*Label 2159*/ GIMT_Encode4(110761), // Rule ID 2680 // |
| 40254 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40256 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40257 | // (fpround:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) => (VCVTf2h:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) |
| 40258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h), |
| 40259 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40260 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 40261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40262 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40263 | GIR_RootConstrainSelectedInstOperands, |
| 40264 | // GIR_Coverage, 2680, |
| 40265 | GIR_EraseRootFromParent_Done, |
| 40266 | // Label 2159: @110761 |
| 40267 | GIM_Reject, |
| 40268 | // Label 2155: @110762 |
| 40269 | GIM_Reject, |
| 40270 | // Label 39: @110763 |
| 40271 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2167*/ GIMT_Encode4(112092), |
| 40272 | /*GILLT_s32*//*Label 2160*/ GIMT_Encode4(110822), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40273 | /*GILLT_v2s32*//*Label 2161*/ GIMT_Encode4(111716), GIMT_Encode4(0), |
| 40274 | /*GILLT_v4s1*//*Label 2162*/ GIMT_Encode4(111754), |
| 40275 | /*GILLT_v4s16*//*Label 2163*/ GIMT_Encode4(111807), |
| 40276 | /*GILLT_v4s32*//*Label 2164*/ GIMT_Encode4(111845), GIMT_Encode4(0), |
| 40277 | /*GILLT_v8s1*//*Label 2165*/ GIMT_Encode4(111942), GIMT_Encode4(0), |
| 40278 | /*GILLT_v8s16*//*Label 2166*/ GIMT_Encode4(111995), |
| 40279 | // Label 2160: @110822 |
| 40280 | GIM_Try, /*On fail goto*//*Label 2168*/ GIMT_Encode4(110888), // Rule ID 2319 // |
| 40281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 40282 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40283 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40284 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40285 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 40286 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40287 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40288 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40289 | // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 40290 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40291 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSH), |
| 40292 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40293 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40294 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40297 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40298 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40299 | // GIR_Coverage, 2319, |
| 40300 | GIR_EraseRootFromParent_Done, |
| 40301 | // Label 2168: @110888 |
| 40302 | GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(110954), // Rule ID 2321 // |
| 40303 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 40304 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40306 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40307 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 40308 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40309 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40310 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40311 | // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 40312 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40313 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSS), |
| 40314 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40315 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40316 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40317 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40318 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40319 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40320 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40321 | // GIR_Coverage, 2321, |
| 40322 | GIR_EraseRootFromParent_Done, |
| 40323 | // Label 2169: @110954 |
| 40324 | GIM_Try, /*On fail goto*//*Label 2170*/ GIMT_Encode4(111020), // Rule ID 2323 // |
| 40325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 40326 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40327 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40328 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40329 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 40330 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40331 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40332 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40333 | // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 40334 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40335 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSD), |
| 40336 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40337 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40338 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40341 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40342 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40343 | // GIR_Coverage, 2323, |
| 40344 | GIR_EraseRootFromParent_Done, |
| 40345 | // Label 2170: @111020 |
| 40346 | GIM_Try, /*On fail goto*//*Label 2171*/ GIMT_Encode4(111086), // Rule ID 2325 // |
| 40347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 40348 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40349 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40350 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40351 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 40352 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40353 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40354 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40355 | // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 40356 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40357 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSH), |
| 40358 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40359 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40360 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40363 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40364 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40365 | // GIR_Coverage, 2325, |
| 40366 | GIR_EraseRootFromParent_Done, |
| 40367 | // Label 2171: @111086 |
| 40368 | GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(111152), // Rule ID 2327 // |
| 40369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 40370 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40371 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40372 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40373 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 40374 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40375 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40376 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40377 | // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 40378 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40379 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSS), |
| 40380 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40381 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40382 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40383 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40384 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40385 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40386 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40387 | // GIR_Coverage, 2327, |
| 40388 | GIR_EraseRootFromParent_Done, |
| 40389 | // Label 2172: @111152 |
| 40390 | GIM_Try, /*On fail goto*//*Label 2173*/ GIMT_Encode4(111218), // Rule ID 2329 // |
| 40391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 40392 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40393 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40394 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40395 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 40396 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40397 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40398 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40399 | // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 40400 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40401 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSD), |
| 40402 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40403 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40404 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40405 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40406 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40407 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40408 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40409 | // GIR_Coverage, 2329, |
| 40410 | GIR_EraseRootFromParent_Done, |
| 40411 | // Label 2173: @111218 |
| 40412 | GIM_Try, /*On fail goto*//*Label 2174*/ GIMT_Encode4(111284), // Rule ID 2313 // |
| 40413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 40414 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40415 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40416 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40417 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 40418 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40419 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40420 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40421 | // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 40422 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40423 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASH), |
| 40424 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40425 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40426 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40429 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40430 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40431 | // GIR_Coverage, 2313, |
| 40432 | GIR_EraseRootFromParent_Done, |
| 40433 | // Label 2174: @111284 |
| 40434 | GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(111350), // Rule ID 2315 // |
| 40435 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 40436 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40438 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40439 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 40440 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40441 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40442 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40443 | // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 40444 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40445 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASS), |
| 40446 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40447 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40448 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40450 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40451 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40452 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40453 | // GIR_Coverage, 2315, |
| 40454 | GIR_EraseRootFromParent_Done, |
| 40455 | // Label 2175: @111350 |
| 40456 | GIM_Try, /*On fail goto*//*Label 2176*/ GIMT_Encode4(111416), // Rule ID 2317 // |
| 40457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 40458 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40459 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40460 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40461 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 40462 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40463 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40464 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40465 | // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 40466 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40467 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASD), |
| 40468 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40469 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40470 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40471 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40472 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40473 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40474 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40475 | // GIR_Coverage, 2317, |
| 40476 | GIR_EraseRootFromParent_Done, |
| 40477 | // Label 2176: @111416 |
| 40478 | GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(111476), // Rule ID 2350 // |
| 40479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 40480 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40482 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40483 | // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 40484 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40485 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD), |
| 40486 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40487 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 40488 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 40489 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40490 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40491 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40492 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40493 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40494 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40495 | // GIR_Coverage, 2350, |
| 40496 | GIR_EraseRootFromParent_Done, |
| 40497 | // Label 2177: @111476 |
| 40498 | GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(111536), // Rule ID 2354 // |
| 40499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 40500 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40501 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40502 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40503 | // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 40504 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40505 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS), |
| 40506 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40507 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 40508 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 40509 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40510 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40513 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40514 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40515 | // GIR_Coverage, 2354, |
| 40516 | GIR_EraseRootFromParent_Done, |
| 40517 | // Label 2178: @111536 |
| 40518 | GIM_Try, /*On fail goto*//*Label 2179*/ GIMT_Encode4(111596), // Rule ID 2358 // |
| 40519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 40520 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40522 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40523 | // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 40524 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40525 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH), |
| 40526 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40527 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 40528 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 40529 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40530 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40533 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40534 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40535 | // GIR_Coverage, 2358, |
| 40536 | GIR_EraseRootFromParent_Done, |
| 40537 | // Label 2179: @111596 |
| 40538 | GIM_Try, /*On fail goto*//*Label 2180*/ GIMT_Encode4(111715), // Rule ID 2728 // |
| 40539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 40540 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40541 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40542 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40543 | // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2sd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 40544 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 40545 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 40546 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 40547 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40548 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40549 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 40550 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 40551 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40552 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 40553 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 40554 | GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 40555 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40556 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40557 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 40558 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd), |
| 40559 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40560 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 40561 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 40562 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40563 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40566 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 40567 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 40568 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40569 | // GIR_Coverage, 2728, |
| 40570 | GIR_EraseRootFromParent_Done, |
| 40571 | // Label 2180: @111715 |
| 40572 | GIM_Reject, |
| 40573 | // Label 2161: @111716 |
| 40574 | GIM_Try, /*On fail goto*//*Label 2181*/ GIMT_Encode4(111753), // Rule ID 1623 // |
| 40575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40576 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 40577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40578 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40579 | // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 40580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd), |
| 40581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40582 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40584 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40585 | GIR_RootConstrainSelectedInstOperands, |
| 40586 | // GIR_Coverage, 1623, |
| 40587 | GIR_EraseRootFromParent_Done, |
| 40588 | // Label 2181: @111753 |
| 40589 | GIM_Reject, |
| 40590 | // Label 2162: @111754 |
| 40591 | GIM_Try, /*On fail goto*//*Label 2182*/ GIMT_Encode4(111806), // Rule ID 5222 // |
| 40592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 40593 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 40595 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40596 | // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 40597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r), |
| 40598 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 40599 | GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 40600 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 40602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40603 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40604 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40605 | GIR_RootConstrainSelectedInstOperands, |
| 40606 | // GIR_Coverage, 5222, |
| 40607 | GIR_EraseRootFromParent_Done, |
| 40608 | // Label 2182: @111806 |
| 40609 | GIM_Reject, |
| 40610 | // Label 2163: @111807 |
| 40611 | GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(111844), // Rule ID 1631 // |
| 40612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 40613 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 40614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40615 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40616 | // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 40617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sd), |
| 40618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40619 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40621 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40622 | GIR_RootConstrainSelectedInstOperands, |
| 40623 | // GIR_Coverage, 1631, |
| 40624 | GIR_EraseRootFromParent_Done, |
| 40625 | // Label 2183: @111844 |
| 40626 | GIM_Reject, |
| 40627 | // Label 2164: @111845 |
| 40628 | GIM_Try, /*On fail goto*//*Label 2184*/ GIMT_Encode4(111941), |
| 40629 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40630 | GIM_Try, /*On fail goto*//*Label 2185*/ GIMT_Encode4(111887), // Rule ID 1627 // |
| 40631 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40633 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40634 | // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 40635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sq), |
| 40636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40637 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40639 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40640 | GIR_RootConstrainSelectedInstOperands, |
| 40641 | // GIR_Coverage, 1627, |
| 40642 | GIR_EraseRootFromParent_Done, |
| 40643 | // Label 2185: @111887 |
| 40644 | GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(111940), // Rule ID 4209 // |
| 40645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 40646 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40647 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40648 | // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 40649 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40650 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40651 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 40652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z), |
| 40653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40654 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 40655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40656 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40657 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40658 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40659 | GIR_RootConstrainSelectedInstOperands, |
| 40660 | // GIR_Coverage, 4209, |
| 40661 | GIR_EraseRootFromParent_Done, |
| 40662 | // Label 2186: @111940 |
| 40663 | GIM_Reject, |
| 40664 | // Label 2184: @111941 |
| 40665 | GIM_Reject, |
| 40666 | // Label 2165: @111942 |
| 40667 | GIM_Try, /*On fail goto*//*Label 2187*/ GIMT_Encode4(111994), // Rule ID 5223 // |
| 40668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 40669 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 40670 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 40671 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40672 | // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 40673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r), |
| 40674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 40675 | GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 40676 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 40678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40679 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40680 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40681 | GIR_RootConstrainSelectedInstOperands, |
| 40682 | // GIR_Coverage, 5223, |
| 40683 | GIR_EraseRootFromParent_Done, |
| 40684 | // Label 2187: @111994 |
| 40685 | GIM_Reject, |
| 40686 | // Label 2166: @111995 |
| 40687 | GIM_Try, /*On fail goto*//*Label 2188*/ GIMT_Encode4(112091), |
| 40688 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 40689 | GIM_Try, /*On fail goto*//*Label 2189*/ GIMT_Encode4(112037), // Rule ID 1635 // |
| 40690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 40691 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40692 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40693 | // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 40694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sq), |
| 40695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40696 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40698 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40699 | GIR_RootConstrainSelectedInstOperands, |
| 40700 | // GIR_Coverage, 1635, |
| 40701 | GIR_EraseRootFromParent_Done, |
| 40702 | // Label 2189: @112037 |
| 40703 | GIM_Try, /*On fail goto*//*Label 2190*/ GIMT_Encode4(112090), // Rule ID 4205 // |
| 40704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 40705 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40706 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40707 | // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 40708 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40709 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40710 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 40711 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z), |
| 40712 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40713 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 40714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40715 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40716 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40717 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40718 | GIR_RootConstrainSelectedInstOperands, |
| 40719 | // GIR_Coverage, 4205, |
| 40720 | GIR_EraseRootFromParent_Done, |
| 40721 | // Label 2190: @112090 |
| 40722 | GIM_Reject, |
| 40723 | // Label 2188: @112091 |
| 40724 | GIM_Reject, |
| 40725 | // Label 2167: @112092 |
| 40726 | GIM_Reject, |
| 40727 | // Label 40: @112093 |
| 40728 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2198*/ GIMT_Encode4(113422), |
| 40729 | /*GILLT_s32*//*Label 2191*/ GIMT_Encode4(112152), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40730 | /*GILLT_v2s32*//*Label 2192*/ GIMT_Encode4(113046), GIMT_Encode4(0), |
| 40731 | /*GILLT_v4s1*//*Label 2193*/ GIMT_Encode4(113084), |
| 40732 | /*GILLT_v4s16*//*Label 2194*/ GIMT_Encode4(113137), |
| 40733 | /*GILLT_v4s32*//*Label 2195*/ GIMT_Encode4(113175), GIMT_Encode4(0), |
| 40734 | /*GILLT_v8s1*//*Label 2196*/ GIMT_Encode4(113272), GIMT_Encode4(0), |
| 40735 | /*GILLT_v8s16*//*Label 2197*/ GIMT_Encode4(113325), |
| 40736 | // Label 2191: @112152 |
| 40737 | GIM_Try, /*On fail goto*//*Label 2199*/ GIMT_Encode4(112218), // Rule ID 2320 // |
| 40738 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 40739 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40740 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40741 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40742 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 40743 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40744 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40745 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40746 | // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 40747 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40748 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUH), |
| 40749 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40750 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40751 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40753 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40754 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40755 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40756 | // GIR_Coverage, 2320, |
| 40757 | GIR_EraseRootFromParent_Done, |
| 40758 | // Label 2199: @112218 |
| 40759 | GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(112284), // Rule ID 2322 // |
| 40760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 40761 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40763 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40764 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 40765 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40766 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40767 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40768 | // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 40769 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40770 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUS), |
| 40771 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40772 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40773 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40775 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40776 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40777 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40778 | // GIR_Coverage, 2322, |
| 40779 | GIR_EraseRootFromParent_Done, |
| 40780 | // Label 2200: @112284 |
| 40781 | GIM_Try, /*On fail goto*//*Label 2201*/ GIMT_Encode4(112350), // Rule ID 2324 // |
| 40782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 40783 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40785 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40786 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 40787 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40788 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40789 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40790 | // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 40791 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40792 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUD), |
| 40793 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40794 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40798 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40799 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40800 | // GIR_Coverage, 2324, |
| 40801 | GIR_EraseRootFromParent_Done, |
| 40802 | // Label 2201: @112350 |
| 40803 | GIM_Try, /*On fail goto*//*Label 2202*/ GIMT_Encode4(112416), // Rule ID 2326 // |
| 40804 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 40805 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40807 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40808 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 40809 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40810 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40811 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40812 | // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 40813 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40814 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUH), |
| 40815 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40816 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40817 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40819 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40820 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40821 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40822 | // GIR_Coverage, 2326, |
| 40823 | GIR_EraseRootFromParent_Done, |
| 40824 | // Label 2202: @112416 |
| 40825 | GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(112482), // Rule ID 2328 // |
| 40826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 40827 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40829 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40830 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 40831 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40832 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40833 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40834 | // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 40835 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40836 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUS), |
| 40837 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40838 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40839 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40841 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40842 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40843 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40844 | // GIR_Coverage, 2328, |
| 40845 | GIR_EraseRootFromParent_Done, |
| 40846 | // Label 2203: @112482 |
| 40847 | GIM_Try, /*On fail goto*//*Label 2204*/ GIMT_Encode4(112548), // Rule ID 2330 // |
| 40848 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 40849 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40851 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40852 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 40853 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40854 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40855 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40856 | // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 40857 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40858 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUD), |
| 40859 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40860 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40861 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40864 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40865 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40866 | // GIR_Coverage, 2330, |
| 40867 | GIR_EraseRootFromParent_Done, |
| 40868 | // Label 2204: @112548 |
| 40869 | GIM_Try, /*On fail goto*//*Label 2205*/ GIMT_Encode4(112614), // Rule ID 2314 // |
| 40870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 40871 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40873 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40874 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 40875 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40876 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40877 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40878 | // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 40879 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40880 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUH), |
| 40881 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40882 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40883 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40886 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40887 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40888 | // GIR_Coverage, 2314, |
| 40889 | GIR_EraseRootFromParent_Done, |
| 40890 | // Label 2205: @112614 |
| 40891 | GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(112680), // Rule ID 2316 // |
| 40892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 40893 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40895 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40896 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 40897 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40898 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40899 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40900 | // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 40901 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40902 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUS), |
| 40903 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40904 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40905 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40908 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40909 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40910 | // GIR_Coverage, 2316, |
| 40911 | GIR_EraseRootFromParent_Done, |
| 40912 | // Label 2206: @112680 |
| 40913 | GIM_Try, /*On fail goto*//*Label 2207*/ GIMT_Encode4(112746), // Rule ID 2318 // |
| 40914 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 40915 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40917 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40918 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 40919 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40920 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40921 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40922 | // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 40923 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40924 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUD), |
| 40925 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40926 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 40927 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40928 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40929 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40930 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40931 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40932 | // GIR_Coverage, 2318, |
| 40933 | GIR_EraseRootFromParent_Done, |
| 40934 | // Label 2207: @112746 |
| 40935 | GIM_Try, /*On fail goto*//*Label 2208*/ GIMT_Encode4(112806), // Rule ID 2360 // |
| 40936 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 40937 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40939 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40940 | // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 40941 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40942 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD), |
| 40943 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40944 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 40945 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 40946 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40947 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40950 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40951 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40952 | // GIR_Coverage, 2360, |
| 40953 | GIR_EraseRootFromParent_Done, |
| 40954 | // Label 2208: @112806 |
| 40955 | GIM_Try, /*On fail goto*//*Label 2209*/ GIMT_Encode4(112866), // Rule ID 2364 // |
| 40956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 40957 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40959 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40960 | // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 40961 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40962 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS), |
| 40963 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40964 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 40965 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 40966 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40967 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40970 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40971 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40972 | // GIR_Coverage, 2364, |
| 40973 | GIR_EraseRootFromParent_Done, |
| 40974 | // Label 2209: @112866 |
| 40975 | GIM_Try, /*On fail goto*//*Label 2210*/ GIMT_Encode4(112926), // Rule ID 2368 // |
| 40976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 40977 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 40979 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40980 | // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 40981 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40982 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH), |
| 40983 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40984 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 40985 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 40986 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40987 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40990 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40991 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 40992 | // GIR_Coverage, 2368, |
| 40993 | GIR_EraseRootFromParent_Done, |
| 40994 | // Label 2210: @112926 |
| 40995 | GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(113045), // Rule ID 2729 // |
| 40996 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 40997 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40998 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40999 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41000 | // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2ud:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 41001 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41002 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 41003 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41004 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41005 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41006 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 41007 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41008 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41009 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41010 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41011 | GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 41012 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41013 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41014 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41015 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud), |
| 41016 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41017 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41018 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41019 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41020 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41023 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41024 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41025 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41026 | // GIR_Coverage, 2729, |
| 41027 | GIR_EraseRootFromParent_Done, |
| 41028 | // Label 2211: @113045 |
| 41029 | GIM_Reject, |
| 41030 | // Label 2192: @113046 |
| 41031 | GIM_Try, /*On fail goto*//*Label 2212*/ GIMT_Encode4(113083), // Rule ID 1624 // |
| 41032 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41033 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 41034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41035 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41036 | // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 41037 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud), |
| 41038 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41039 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41041 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41042 | GIR_RootConstrainSelectedInstOperands, |
| 41043 | // GIR_Coverage, 1624, |
| 41044 | GIR_EraseRootFromParent_Done, |
| 41045 | // Label 2212: @113083 |
| 41046 | GIM_Reject, |
| 41047 | // Label 2193: @113084 |
| 41048 | GIM_Try, /*On fail goto*//*Label 2213*/ GIMT_Encode4(113136), // Rule ID 5220 // |
| 41049 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41050 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41051 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41052 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41053 | // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41054 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r), |
| 41055 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41056 | GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 41057 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 41059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41060 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41061 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41062 | GIR_RootConstrainSelectedInstOperands, |
| 41063 | // GIR_Coverage, 5220, |
| 41064 | GIR_EraseRootFromParent_Done, |
| 41065 | // Label 2213: @113136 |
| 41066 | GIM_Reject, |
| 41067 | // Label 2194: @113137 |
| 41068 | GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(113174), // Rule ID 1632 // |
| 41069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41070 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41071 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41072 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41073 | // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 41074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2ud), |
| 41075 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41076 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41078 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41079 | GIR_RootConstrainSelectedInstOperands, |
| 41080 | // GIR_Coverage, 1632, |
| 41081 | GIR_EraseRootFromParent_Done, |
| 41082 | // Label 2214: @113174 |
| 41083 | GIM_Reject, |
| 41084 | // Label 2195: @113175 |
| 41085 | GIM_Try, /*On fail goto*//*Label 2215*/ GIMT_Encode4(113271), |
| 41086 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41087 | GIM_Try, /*On fail goto*//*Label 2216*/ GIMT_Encode4(113217), // Rule ID 1628 // |
| 41088 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41090 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41091 | // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 41092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2uq), |
| 41093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41094 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41096 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41097 | GIR_RootConstrainSelectedInstOperands, |
| 41098 | // GIR_Coverage, 1628, |
| 41099 | GIR_EraseRootFromParent_Done, |
| 41100 | // Label 2216: @113217 |
| 41101 | GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(113270), // Rule ID 4211 // |
| 41102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41104 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41105 | // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 41106 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41107 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41108 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 41109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z), |
| 41110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41111 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41113 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41114 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41115 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41116 | GIR_RootConstrainSelectedInstOperands, |
| 41117 | // GIR_Coverage, 4211, |
| 41118 | GIR_EraseRootFromParent_Done, |
| 41119 | // Label 2217: @113270 |
| 41120 | GIM_Reject, |
| 41121 | // Label 2215: @113271 |
| 41122 | GIM_Reject, |
| 41123 | // Label 2196: @113272 |
| 41124 | GIM_Try, /*On fail goto*//*Label 2218*/ GIMT_Encode4(113324), // Rule ID 5221 // |
| 41125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41126 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41128 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41129 | // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r), |
| 41131 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41132 | GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 41133 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 41135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41136 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41137 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41138 | GIR_RootConstrainSelectedInstOperands, |
| 41139 | // GIR_Coverage, 5221, |
| 41140 | GIR_EraseRootFromParent_Done, |
| 41141 | // Label 2218: @113324 |
| 41142 | GIM_Reject, |
| 41143 | // Label 2197: @113325 |
| 41144 | GIM_Try, /*On fail goto*//*Label 2219*/ GIMT_Encode4(113421), |
| 41145 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41146 | GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(113367), // Rule ID 1636 // |
| 41147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41148 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41149 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41150 | // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 41151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2uq), |
| 41152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41153 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41155 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41156 | GIR_RootConstrainSelectedInstOperands, |
| 41157 | // GIR_Coverage, 1636, |
| 41158 | GIR_EraseRootFromParent_Done, |
| 41159 | // Label 2220: @113367 |
| 41160 | GIM_Try, /*On fail goto*//*Label 2221*/ GIMT_Encode4(113420), // Rule ID 4207 // |
| 41161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41163 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41164 | // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 41165 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41166 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41167 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 41168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z), |
| 41169 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41170 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41172 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41173 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41174 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41175 | GIR_RootConstrainSelectedInstOperands, |
| 41176 | // GIR_Coverage, 4207, |
| 41177 | GIR_EraseRootFromParent_Done, |
| 41178 | // Label 2221: @113420 |
| 41179 | GIM_Reject, |
| 41180 | // Label 2219: @113421 |
| 41181 | GIM_Reject, |
| 41182 | // Label 2198: @113422 |
| 41183 | GIM_Reject, |
| 41184 | // Label 41: @113423 |
| 41185 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2229*/ GIMT_Encode4(114066), |
| 41186 | /*GILLT_s16*//*Label 2222*/ GIMT_Encode4(113486), |
| 41187 | /*GILLT_s32*//*Label 2223*/ GIMT_Encode4(113543), |
| 41188 | /*GILLT_s64*//*Label 2224*/ GIMT_Encode4(113739), GIMT_Encode4(0), |
| 41189 | /*GILLT_v2s32*//*Label 2225*/ GIMT_Encode4(113796), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41190 | /*GILLT_v4s16*//*Label 2226*/ GIMT_Encode4(113834), |
| 41191 | /*GILLT_v4s32*//*Label 2227*/ GIMT_Encode4(113872), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41192 | /*GILLT_v8s16*//*Label 2228*/ GIMT_Encode4(113969), |
| 41193 | // Label 2222: @113486 |
| 41194 | GIM_Try, /*On fail goto*//*Label 2230*/ GIMT_Encode4(113542), // Rule ID 2344 // |
| 41195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 41196 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41197 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41198 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41199 | // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 41200 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41201 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41202 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41203 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41204 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41205 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOH), |
| 41206 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41207 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41209 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41210 | GIR_RootConstrainSelectedInstOperands, |
| 41211 | // GIR_Coverage, 2344, |
| 41212 | GIR_EraseRootFromParent_Done, |
| 41213 | // Label 2230: @113542 |
| 41214 | GIM_Reject, |
| 41215 | // Label 2223: @113543 |
| 41216 | GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(113738), |
| 41217 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41218 | GIM_Try, /*On fail goto*//*Label 2232*/ GIMT_Encode4(113604), // Rule ID 2342 // |
| 41219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 41220 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41221 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41222 | // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 41223 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41224 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41225 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41226 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41227 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOS), |
| 41229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41230 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41232 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41233 | GIR_RootConstrainSelectedInstOperands, |
| 41234 | // GIR_Coverage, 2342, |
| 41235 | GIR_EraseRootFromParent_Done, |
| 41236 | // Label 2232: @113604 |
| 41237 | GIM_Try, /*On fail goto*//*Label 2233*/ GIMT_Encode4(113737), // Rule ID 2730 // |
| 41238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 41239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41240 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41241 | // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTs2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 41242 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41243 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 41244 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41245 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 41246 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41247 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41248 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41249 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 41250 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41251 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41252 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 41253 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41254 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41255 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41256 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 41257 | GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 41258 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41259 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41260 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41261 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd), |
| 41262 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41263 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41264 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41265 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41266 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41268 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41269 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41270 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41271 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41272 | // GIR_Coverage, 2730, |
| 41273 | GIR_EraseRootFromParent_Done, |
| 41274 | // Label 2233: @113737 |
| 41275 | GIM_Reject, |
| 41276 | // Label 2231: @113738 |
| 41277 | GIM_Reject, |
| 41278 | // Label 2224: @113739 |
| 41279 | GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(113795), // Rule ID 2340 // |
| 41280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 41281 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41282 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41283 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41284 | // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 41285 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41286 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41287 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41288 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41289 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOD), |
| 41291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 41292 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41294 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41295 | GIR_RootConstrainSelectedInstOperands, |
| 41296 | // GIR_Coverage, 2340, |
| 41297 | GIR_EraseRootFromParent_Done, |
| 41298 | // Label 2234: @113795 |
| 41299 | GIM_Reject, |
| 41300 | // Label 2225: @113796 |
| 41301 | GIM_Try, /*On fail goto*//*Label 2235*/ GIMT_Encode4(113833), // Rule ID 1625 // |
| 41302 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41303 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 41304 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41305 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41306 | // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) |
| 41307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd), |
| 41308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41309 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41311 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41312 | GIR_RootConstrainSelectedInstOperands, |
| 41313 | // GIR_Coverage, 1625, |
| 41314 | GIR_EraseRootFromParent_Done, |
| 41315 | // Label 2235: @113833 |
| 41316 | GIM_Reject, |
| 41317 | // Label 2226: @113834 |
| 41318 | GIM_Try, /*On fail goto*//*Label 2236*/ GIMT_Encode4(113871), // Rule ID 1633 // |
| 41319 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41320 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41322 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41323 | // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) |
| 41324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hd), |
| 41325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41326 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41328 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41329 | GIR_RootConstrainSelectedInstOperands, |
| 41330 | // GIR_Coverage, 1633, |
| 41331 | GIR_EraseRootFromParent_Done, |
| 41332 | // Label 2236: @113871 |
| 41333 | GIM_Reject, |
| 41334 | // Label 2227: @113872 |
| 41335 | GIM_Try, /*On fail goto*//*Label 2237*/ GIMT_Encode4(113968), |
| 41336 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41337 | GIM_Try, /*On fail goto*//*Label 2238*/ GIMT_Encode4(113914), // Rule ID 1629 // |
| 41338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41339 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41340 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41341 | // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) |
| 41342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fq), |
| 41343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41344 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41346 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41347 | GIR_RootConstrainSelectedInstOperands, |
| 41348 | // GIR_Coverage, 1629, |
| 41349 | GIR_EraseRootFromParent_Done, |
| 41350 | // Label 2238: @113914 |
| 41351 | GIM_Try, /*On fail goto*//*Label 2239*/ GIMT_Encode4(113967), // Rule ID 4217 // |
| 41352 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41353 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41354 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41355 | // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 41356 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41357 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41358 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 41359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n), |
| 41360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41361 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41363 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41364 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41365 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41366 | GIR_RootConstrainSelectedInstOperands, |
| 41367 | // GIR_Coverage, 4217, |
| 41368 | GIR_EraseRootFromParent_Done, |
| 41369 | // Label 2239: @113967 |
| 41370 | GIM_Reject, |
| 41371 | // Label 2237: @113968 |
| 41372 | GIM_Reject, |
| 41373 | // Label 2228: @113969 |
| 41374 | GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(114065), |
| 41375 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41376 | GIM_Try, /*On fail goto*//*Label 2241*/ GIMT_Encode4(114011), // Rule ID 1637 // |
| 41377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41379 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41380 | // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) |
| 41381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hq), |
| 41382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41383 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41385 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41386 | GIR_RootConstrainSelectedInstOperands, |
| 41387 | // GIR_Coverage, 1637, |
| 41388 | GIR_EraseRootFromParent_Done, |
| 41389 | // Label 2241: @114011 |
| 41390 | GIM_Try, /*On fail goto*//*Label 2242*/ GIMT_Encode4(114064), // Rule ID 4213 // |
| 41391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41392 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41393 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41394 | // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 41395 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41396 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41397 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 41398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n), |
| 41399 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41400 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41401 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41402 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41403 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41404 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41405 | GIR_RootConstrainSelectedInstOperands, |
| 41406 | // GIR_Coverage, 4213, |
| 41407 | GIR_EraseRootFromParent_Done, |
| 41408 | // Label 2242: @114064 |
| 41409 | GIM_Reject, |
| 41410 | // Label 2240: @114065 |
| 41411 | GIM_Reject, |
| 41412 | // Label 2229: @114066 |
| 41413 | GIM_Reject, |
| 41414 | // Label 42: @114067 |
| 41415 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2250*/ GIMT_Encode4(114710), |
| 41416 | /*GILLT_s16*//*Label 2243*/ GIMT_Encode4(114130), |
| 41417 | /*GILLT_s32*//*Label 2244*/ GIMT_Encode4(114187), |
| 41418 | /*GILLT_s64*//*Label 2245*/ GIMT_Encode4(114383), GIMT_Encode4(0), |
| 41419 | /*GILLT_v2s32*//*Label 2246*/ GIMT_Encode4(114440), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41420 | /*GILLT_v4s16*//*Label 2247*/ GIMT_Encode4(114478), |
| 41421 | /*GILLT_v4s32*//*Label 2248*/ GIMT_Encode4(114516), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41422 | /*GILLT_v8s16*//*Label 2249*/ GIMT_Encode4(114613), |
| 41423 | // Label 2243: @114130 |
| 41424 | GIM_Try, /*On fail goto*//*Label 2251*/ GIMT_Encode4(114186), // Rule ID 2349 // |
| 41425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 41426 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41427 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41428 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41429 | // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 41430 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41431 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41432 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41433 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41434 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOH), |
| 41436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41437 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41439 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41440 | GIR_RootConstrainSelectedInstOperands, |
| 41441 | // GIR_Coverage, 2349, |
| 41442 | GIR_EraseRootFromParent_Done, |
| 41443 | // Label 2251: @114186 |
| 41444 | GIM_Reject, |
| 41445 | // Label 2244: @114187 |
| 41446 | GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(114382), |
| 41447 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41448 | GIM_Try, /*On fail goto*//*Label 2253*/ GIMT_Encode4(114248), // Rule ID 2347 // |
| 41449 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 41450 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41451 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41452 | // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 41453 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41454 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41455 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41456 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41457 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41458 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOS), |
| 41459 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41460 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41462 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41463 | GIR_RootConstrainSelectedInstOperands, |
| 41464 | // GIR_Coverage, 2347, |
| 41465 | GIR_EraseRootFromParent_Done, |
| 41466 | // Label 2253: @114248 |
| 41467 | GIM_Try, /*On fail goto*//*Label 2254*/ GIMT_Encode4(114381), // Rule ID 2731 // |
| 41468 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 41469 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41470 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41471 | // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTu2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 41472 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41473 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 41474 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41475 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 41476 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41477 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41478 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41479 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 41480 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41481 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41482 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 41483 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41484 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41485 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41486 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 41487 | GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 41488 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41489 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41490 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41491 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd), |
| 41492 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41493 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41494 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41495 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41496 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41499 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41500 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41501 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41502 | // GIR_Coverage, 2731, |
| 41503 | GIR_EraseRootFromParent_Done, |
| 41504 | // Label 2254: @114381 |
| 41505 | GIM_Reject, |
| 41506 | // Label 2252: @114382 |
| 41507 | GIM_Reject, |
| 41508 | // Label 2245: @114383 |
| 41509 | GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(114439), // Rule ID 2345 // |
| 41510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 41511 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41513 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41514 | // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 41515 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41516 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41517 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41518 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41519 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOD), |
| 41521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 41522 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41524 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41525 | GIR_RootConstrainSelectedInstOperands, |
| 41526 | // GIR_Coverage, 2345, |
| 41527 | GIR_EraseRootFromParent_Done, |
| 41528 | // Label 2255: @114439 |
| 41529 | GIM_Reject, |
| 41530 | // Label 2246: @114440 |
| 41531 | GIM_Try, /*On fail goto*//*Label 2256*/ GIMT_Encode4(114477), // Rule ID 1626 // |
| 41532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41533 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 41534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41535 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41536 | // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) |
| 41537 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd), |
| 41538 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41539 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41541 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41542 | GIR_RootConstrainSelectedInstOperands, |
| 41543 | // GIR_Coverage, 1626, |
| 41544 | GIR_EraseRootFromParent_Done, |
| 41545 | // Label 2256: @114477 |
| 41546 | GIM_Reject, |
| 41547 | // Label 2247: @114478 |
| 41548 | GIM_Try, /*On fail goto*//*Label 2257*/ GIMT_Encode4(114515), // Rule ID 1634 // |
| 41549 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41550 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41552 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41553 | // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) |
| 41554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hd), |
| 41555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41556 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41558 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41559 | GIR_RootConstrainSelectedInstOperands, |
| 41560 | // GIR_Coverage, 1634, |
| 41561 | GIR_EraseRootFromParent_Done, |
| 41562 | // Label 2257: @114515 |
| 41563 | GIM_Reject, |
| 41564 | // Label 2248: @114516 |
| 41565 | GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(114612), |
| 41566 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41567 | GIM_Try, /*On fail goto*//*Label 2259*/ GIMT_Encode4(114558), // Rule ID 1630 // |
| 41568 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41569 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41570 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41571 | // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) |
| 41572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fq), |
| 41573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41574 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41576 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41577 | GIR_RootConstrainSelectedInstOperands, |
| 41578 | // GIR_Coverage, 1630, |
| 41579 | GIR_EraseRootFromParent_Done, |
| 41580 | // Label 2259: @114558 |
| 41581 | GIM_Try, /*On fail goto*//*Label 2260*/ GIMT_Encode4(114611), // Rule ID 4219 // |
| 41582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41583 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41584 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41585 | // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 41586 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41587 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41588 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 41589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n), |
| 41590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41591 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41593 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41594 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41595 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41596 | GIR_RootConstrainSelectedInstOperands, |
| 41597 | // GIR_Coverage, 4219, |
| 41598 | GIR_EraseRootFromParent_Done, |
| 41599 | // Label 2260: @114611 |
| 41600 | GIM_Reject, |
| 41601 | // Label 2258: @114612 |
| 41602 | GIM_Reject, |
| 41603 | // Label 2249: @114613 |
| 41604 | GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(114709), |
| 41605 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41606 | GIM_Try, /*On fail goto*//*Label 2262*/ GIMT_Encode4(114655), // Rule ID 1638 // |
| 41607 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41608 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41609 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41610 | // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) |
| 41611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hq), |
| 41612 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41613 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41615 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41616 | GIR_RootConstrainSelectedInstOperands, |
| 41617 | // GIR_Coverage, 1638, |
| 41618 | GIR_EraseRootFromParent_Done, |
| 41619 | // Label 2262: @114655 |
| 41620 | GIM_Try, /*On fail goto*//*Label 2263*/ GIMT_Encode4(114708), // Rule ID 4215 // |
| 41621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41623 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41624 | // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 41625 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41626 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41627 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 41628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n), |
| 41629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41630 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41632 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41633 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41634 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41635 | GIR_RootConstrainSelectedInstOperands, |
| 41636 | // GIR_Coverage, 4215, |
| 41637 | GIR_EraseRootFromParent_Done, |
| 41638 | // Label 2263: @114708 |
| 41639 | GIM_Reject, |
| 41640 | // Label 2261: @114709 |
| 41641 | GIM_Reject, |
| 41642 | // Label 2250: @114710 |
| 41643 | GIM_Reject, |
| 41644 | // Label 43: @114711 |
| 41645 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2271*/ GIMT_Encode4(115480), |
| 41646 | /*GILLT_s16*//*Label 2264*/ GIMT_Encode4(114774), |
| 41647 | /*GILLT_s32*//*Label 2265*/ GIMT_Encode4(114812), |
| 41648 | /*GILLT_s64*//*Label 2266*/ GIMT_Encode4(115006), GIMT_Encode4(0), |
| 41649 | /*GILLT_v2s32*//*Label 2267*/ GIMT_Encode4(115044), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41650 | /*GILLT_v4s16*//*Label 2268*/ GIMT_Encode4(115082), |
| 41651 | /*GILLT_v4s32*//*Label 2269*/ GIMT_Encode4(115120), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41652 | /*GILLT_v8s16*//*Label 2270*/ GIMT_Encode4(115300), |
| 41653 | // Label 2264: @114774 |
| 41654 | GIM_Try, /*On fail goto*//*Label 2272*/ GIMT_Encode4(114811), // Rule ID 670 // |
| 41655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 41656 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 41657 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41658 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41659 | // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 41660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSH), |
| 41661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41662 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 41663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41664 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41665 | GIR_RootConstrainSelectedInstOperands, |
| 41666 | // GIR_Coverage, 670, |
| 41667 | GIR_EraseRootFromParent_Done, |
| 41668 | // Label 2272: @114811 |
| 41669 | GIM_Reject, |
| 41670 | // Label 2265: @114812 |
| 41671 | GIM_Try, /*On fail goto*//*Label 2273*/ GIMT_Encode4(115005), |
| 41672 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41673 | GIM_Try, /*On fail goto*//*Label 2274*/ GIMT_Encode4(114854), // Rule ID 669 // |
| 41674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 41675 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41676 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41677 | // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 41678 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSS), |
| 41679 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41680 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 41681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41682 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41683 | GIR_RootConstrainSelectedInstOperands, |
| 41684 | // GIR_Coverage, 669, |
| 41685 | GIR_EraseRootFromParent_Done, |
| 41686 | // Label 2274: @114854 |
| 41687 | GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(115004), // Rule ID 2722 // |
| 41688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 41689 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41690 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41691 | // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VABSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 41692 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41693 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 41694 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41695 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 41696 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 41697 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41698 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41699 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 41700 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41701 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41702 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 41703 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 41704 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41705 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41706 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 41707 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41708 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 41709 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41710 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41711 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41712 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VABSfd), |
| 41713 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41714 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41715 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 41716 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41717 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41718 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41719 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41720 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41721 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41724 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41725 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41726 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41727 | // GIR_Coverage, 2722, |
| 41728 | GIR_EraseRootFromParent_Done, |
| 41729 | // Label 2275: @115004 |
| 41730 | GIM_Reject, |
| 41731 | // Label 2273: @115005 |
| 41732 | GIM_Reject, |
| 41733 | // Label 2266: @115006 |
| 41734 | GIM_Try, /*On fail goto*//*Label 2276*/ GIMT_Encode4(115043), // Rule ID 668 // |
| 41735 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 41736 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41737 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41738 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41739 | // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 41740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSD), |
| 41741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 41742 | GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 41743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41744 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41745 | GIR_RootConstrainSelectedInstOperands, |
| 41746 | // GIR_Coverage, 668, |
| 41747 | GIR_EraseRootFromParent_Done, |
| 41748 | // Label 2276: @115043 |
| 41749 | GIM_Reject, |
| 41750 | // Label 2267: @115044 |
| 41751 | GIM_Try, /*On fail goto*//*Label 2277*/ GIMT_Encode4(115081), // Rule ID 1533 // |
| 41752 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41753 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 41754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41755 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41756 | // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 41757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfd), |
| 41758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41759 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41761 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41762 | GIR_RootConstrainSelectedInstOperands, |
| 41763 | // GIR_Coverage, 1533, |
| 41764 | GIR_EraseRootFromParent_Done, |
| 41765 | // Label 2277: @115081 |
| 41766 | GIM_Reject, |
| 41767 | // Label 2268: @115082 |
| 41768 | GIM_Try, /*On fail goto*//*Label 2278*/ GIMT_Encode4(115119), // Rule ID 1535 // |
| 41769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41770 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41772 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41773 | // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 41774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShd), |
| 41775 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41776 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41778 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41779 | GIR_RootConstrainSelectedInstOperands, |
| 41780 | // GIR_Coverage, 1535, |
| 41781 | GIR_EraseRootFromParent_Done, |
| 41782 | // Label 2278: @115119 |
| 41783 | GIM_Reject, |
| 41784 | // Label 2269: @115120 |
| 41785 | GIM_Try, /*On fail goto*//*Label 2279*/ GIMT_Encode4(115299), |
| 41786 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41787 | GIM_Try, /*On fail goto*//*Label 2280*/ GIMT_Encode4(115211), // Rule ID 4156 // |
| 41788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41789 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41790 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41791 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB), |
| 41792 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41793 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 41794 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41795 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41796 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41797 | // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 41798 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41799 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41800 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 41801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32), |
| 41802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41803 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 41804 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn |
| 41805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41806 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41807 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41808 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41809 | GIR_RootConstrainSelectedInstOperands, |
| 41810 | // GIR_Coverage, 4156, |
| 41811 | GIR_EraseRootFromParent_Done, |
| 41812 | // Label 2280: @115211 |
| 41813 | GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(115245), // Rule ID 1534 // |
| 41814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41815 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41816 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41817 | // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 41818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfq), |
| 41819 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41820 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41822 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41823 | GIR_RootConstrainSelectedInstOperands, |
| 41824 | // GIR_Coverage, 1534, |
| 41825 | GIR_EraseRootFromParent_Done, |
| 41826 | // Label 2281: @115245 |
| 41827 | GIM_Try, /*On fail goto*//*Label 2282*/ GIMT_Encode4(115298), // Rule ID 4227 // |
| 41828 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 41829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41830 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41831 | // (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VABSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v) |
| 41832 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41833 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41834 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 41835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf32), |
| 41836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41837 | GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 41838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41839 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41840 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41841 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41842 | GIR_RootConstrainSelectedInstOperands, |
| 41843 | // GIR_Coverage, 4227, |
| 41844 | GIR_EraseRootFromParent_Done, |
| 41845 | // Label 2282: @115298 |
| 41846 | GIM_Reject, |
| 41847 | // Label 2279: @115299 |
| 41848 | GIM_Reject, |
| 41849 | // Label 2270: @115300 |
| 41850 | GIM_Try, /*On fail goto*//*Label 2283*/ GIMT_Encode4(115479), |
| 41851 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41852 | GIM_Try, /*On fail goto*//*Label 2284*/ GIMT_Encode4(115391), // Rule ID 4155 // |
| 41853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41854 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41855 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41856 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB), |
| 41857 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41858 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 41859 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41860 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41861 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41862 | // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 41863 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41864 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41865 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 41866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16), |
| 41867 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41868 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 41869 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn |
| 41870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41871 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41872 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41873 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41874 | GIR_RootConstrainSelectedInstOperands, |
| 41875 | // GIR_Coverage, 4155, |
| 41876 | GIR_EraseRootFromParent_Done, |
| 41877 | // Label 2284: @115391 |
| 41878 | GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(115425), // Rule ID 1536 // |
| 41879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41881 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41882 | // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 41883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShq), |
| 41884 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41885 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41887 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41888 | GIR_RootConstrainSelectedInstOperands, |
| 41889 | // GIR_Coverage, 1536, |
| 41890 | GIR_EraseRootFromParent_Done, |
| 41891 | // Label 2285: @115425 |
| 41892 | GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(115478), // Rule ID 4225 // |
| 41893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 41894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41895 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41896 | // (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VABSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v) |
| 41897 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41898 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41899 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 41900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf16), |
| 41901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41902 | GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 41903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41904 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41905 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41906 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41907 | GIR_RootConstrainSelectedInstOperands, |
| 41908 | // GIR_Coverage, 4225, |
| 41909 | GIR_EraseRootFromParent_Done, |
| 41910 | // Label 2286: @115478 |
| 41911 | GIM_Reject, |
| 41912 | // Label 2283: @115479 |
| 41913 | GIM_Reject, |
| 41914 | // Label 2271: @115480 |
| 41915 | GIM_Reject, |
| 41916 | // Label 44: @115481 |
| 41917 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2294*/ GIMT_Encode4(116068), |
| 41918 | /*GILLT_s16*//*Label 2287*/ GIMT_Encode4(115544), |
| 41919 | /*GILLT_s32*//*Label 2288*/ GIMT_Encode4(115578), |
| 41920 | /*GILLT_s64*//*Label 2289*/ GIMT_Encode4(115612), GIMT_Encode4(0), |
| 41921 | /*GILLT_v2s32*//*Label 2290*/ GIMT_Encode4(115646), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41922 | /*GILLT_v4s16*//*Label 2291*/ GIMT_Encode4(115680), |
| 41923 | /*GILLT_v4s32*//*Label 2292*/ GIMT_Encode4(115714), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41924 | /*GILLT_v8s16*//*Label 2293*/ GIMT_Encode4(115891), |
| 41925 | // Label 2287: @115544 |
| 41926 | GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(115577), // Rule ID 659 // |
| 41927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 41928 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 41929 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 41930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41931 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41932 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41933 | // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 41934 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMH), |
| 41935 | GIR_RootConstrainSelectedInstOperands, |
| 41936 | // GIR_Coverage, 659, |
| 41937 | GIR_Done, |
| 41938 | // Label 2295: @115577 |
| 41939 | GIM_Reject, |
| 41940 | // Label 2288: @115578 |
| 41941 | GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(115611), // Rule ID 660 // |
| 41942 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 41943 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41944 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 41945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41947 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41948 | // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 41949 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMS), |
| 41950 | GIR_RootConstrainSelectedInstOperands, |
| 41951 | // GIR_Coverage, 660, |
| 41952 | GIR_Done, |
| 41953 | // Label 2296: @115611 |
| 41954 | GIM_Reject, |
| 41955 | // Label 2289: @115612 |
| 41956 | GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(115645), // Rule ID 661 // |
| 41957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 41958 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41959 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 41960 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41961 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41962 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41963 | // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 41964 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMD), |
| 41965 | GIR_RootConstrainSelectedInstOperands, |
| 41966 | // GIR_Coverage, 661, |
| 41967 | GIR_Done, |
| 41968 | // Label 2297: @115645 |
| 41969 | GIM_Reject, |
| 41970 | // Label 2290: @115646 |
| 41971 | GIM_Try, /*On fail goto*//*Label 2298*/ GIMT_Encode4(115679), // Rule ID 1252 // |
| 41972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), |
| 41973 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 41974 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 41975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41976 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41977 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41978 | // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 41979 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDf), |
| 41980 | GIR_RootConstrainSelectedInstOperands, |
| 41981 | // GIR_Coverage, 1252, |
| 41982 | GIR_Done, |
| 41983 | // Label 2298: @115679 |
| 41984 | GIM_Reject, |
| 41985 | // Label 2291: @115680 |
| 41986 | GIM_Try, /*On fail goto*//*Label 2299*/ GIMT_Encode4(115713), // Rule ID 1254 // |
| 41987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), |
| 41988 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41989 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 41990 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41991 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41992 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41993 | // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 41994 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDh), |
| 41995 | GIR_RootConstrainSelectedInstOperands, |
| 41996 | // GIR_Coverage, 1254, |
| 41997 | GIR_Done, |
| 41998 | // Label 2299: @115713 |
| 41999 | GIM_Reject, |
| 42000 | // Label 2292: @115714 |
| 42001 | GIM_Try, /*On fail goto*//*Label 2300*/ GIMT_Encode4(115890), |
| 42002 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42003 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42004 | GIM_Try, /*On fail goto*//*Label 2301*/ GIMT_Encode4(115803), // Rule ID 4237 // |
| 42005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 42006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42007 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42008 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42009 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42010 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42011 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 42012 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42013 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42014 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42015 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42016 | // (fminnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 42017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32), |
| 42018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42019 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 42020 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 42021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42022 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42023 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42024 | GIR_RootConstrainSelectedInstOperands, |
| 42025 | // GIR_Coverage, 4237, |
| 42026 | GIR_EraseRootFromParent_Done, |
| 42027 | // Label 2301: @115803 |
| 42028 | GIM_Try, /*On fail goto*//*Label 2302*/ GIMT_Encode4(115830), // Rule ID 1253 // |
| 42029 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), |
| 42030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42031 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42032 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42033 | // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 42034 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQf), |
| 42035 | GIR_RootConstrainSelectedInstOperands, |
| 42036 | // GIR_Coverage, 1253, |
| 42037 | GIR_Done, |
| 42038 | // Label 2302: @115830 |
| 42039 | GIM_Try, /*On fail goto*//*Label 2303*/ GIMT_Encode4(115889), // Rule ID 3385 // |
| 42040 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42041 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42042 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42043 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42044 | // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 42045 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42046 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42047 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 42048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32), |
| 42049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42050 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 42051 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 42052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42053 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42054 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42055 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42056 | GIR_RootConstrainSelectedInstOperands, |
| 42057 | // GIR_Coverage, 3385, |
| 42058 | GIR_EraseRootFromParent_Done, |
| 42059 | // Label 2303: @115889 |
| 42060 | GIM_Reject, |
| 42061 | // Label 2300: @115890 |
| 42062 | GIM_Reject, |
| 42063 | // Label 2293: @115891 |
| 42064 | GIM_Try, /*On fail goto*//*Label 2304*/ GIMT_Encode4(116067), |
| 42065 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42066 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42067 | GIM_Try, /*On fail goto*//*Label 2305*/ GIMT_Encode4(115980), // Rule ID 4239 // |
| 42068 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 42069 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42070 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42071 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42072 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42073 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42074 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 42075 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42076 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42077 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42078 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42079 | // (fminnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 42080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16), |
| 42081 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42082 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 42083 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 42084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42085 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42086 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42087 | GIR_RootConstrainSelectedInstOperands, |
| 42088 | // GIR_Coverage, 4239, |
| 42089 | GIR_EraseRootFromParent_Done, |
| 42090 | // Label 2305: @115980 |
| 42091 | GIM_Try, /*On fail goto*//*Label 2306*/ GIMT_Encode4(116007), // Rule ID 1255 // |
| 42092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), |
| 42093 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42094 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42095 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42096 | // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 42097 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQh), |
| 42098 | GIR_RootConstrainSelectedInstOperands, |
| 42099 | // GIR_Coverage, 1255, |
| 42100 | GIR_Done, |
| 42101 | // Label 2306: @116007 |
| 42102 | GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(116066), // Rule ID 3388 // |
| 42103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42104 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42105 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42106 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42107 | // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 42108 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42109 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42110 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 42111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16), |
| 42112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42113 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 42114 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 42115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42116 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42117 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42118 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42119 | GIR_RootConstrainSelectedInstOperands, |
| 42120 | // GIR_Coverage, 3388, |
| 42121 | GIR_EraseRootFromParent_Done, |
| 42122 | // Label 2307: @116066 |
| 42123 | GIM_Reject, |
| 42124 | // Label 2304: @116067 |
| 42125 | GIM_Reject, |
| 42126 | // Label 2294: @116068 |
| 42127 | GIM_Reject, |
| 42128 | // Label 45: @116069 |
| 42129 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2315*/ GIMT_Encode4(116656), |
| 42130 | /*GILLT_s16*//*Label 2308*/ GIMT_Encode4(116132), |
| 42131 | /*GILLT_s32*//*Label 2309*/ GIMT_Encode4(116166), |
| 42132 | /*GILLT_s64*//*Label 2310*/ GIMT_Encode4(116200), GIMT_Encode4(0), |
| 42133 | /*GILLT_v2s32*//*Label 2311*/ GIMT_Encode4(116234), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42134 | /*GILLT_v4s16*//*Label 2312*/ GIMT_Encode4(116268), |
| 42135 | /*GILLT_v4s32*//*Label 2313*/ GIMT_Encode4(116302), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42136 | /*GILLT_v8s16*//*Label 2314*/ GIMT_Encode4(116479), |
| 42137 | // Label 2308: @116132 |
| 42138 | GIM_Try, /*On fail goto*//*Label 2316*/ GIMT_Encode4(116165), // Rule ID 656 // |
| 42139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 42140 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 42141 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 42142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42143 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42144 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42145 | // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 42146 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMH), |
| 42147 | GIR_RootConstrainSelectedInstOperands, |
| 42148 | // GIR_Coverage, 656, |
| 42149 | GIR_Done, |
| 42150 | // Label 2316: @116165 |
| 42151 | GIM_Reject, |
| 42152 | // Label 2309: @116166 |
| 42153 | GIM_Try, /*On fail goto*//*Label 2317*/ GIMT_Encode4(116199), // Rule ID 657 // |
| 42154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 42155 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42156 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42157 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42158 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42159 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42160 | // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 42161 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMS), |
| 42162 | GIR_RootConstrainSelectedInstOperands, |
| 42163 | // GIR_Coverage, 657, |
| 42164 | GIR_Done, |
| 42165 | // Label 2317: @116199 |
| 42166 | GIM_Reject, |
| 42167 | // Label 2310: @116200 |
| 42168 | GIM_Try, /*On fail goto*//*Label 2318*/ GIMT_Encode4(116233), // Rule ID 658 // |
| 42169 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 42170 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 42171 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42173 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42174 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42175 | // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 42176 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMD), |
| 42177 | GIR_RootConstrainSelectedInstOperands, |
| 42178 | // GIR_Coverage, 658, |
| 42179 | GIR_Done, |
| 42180 | // Label 2318: @116233 |
| 42181 | GIM_Reject, |
| 42182 | // Label 2311: @116234 |
| 42183 | GIM_Try, /*On fail goto*//*Label 2319*/ GIMT_Encode4(116267), // Rule ID 1232 // |
| 42184 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), |
| 42185 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42186 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42188 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42189 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42190 | // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 42191 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDf), |
| 42192 | GIR_RootConstrainSelectedInstOperands, |
| 42193 | // GIR_Coverage, 1232, |
| 42194 | GIR_Done, |
| 42195 | // Label 2319: @116267 |
| 42196 | GIM_Reject, |
| 42197 | // Label 2312: @116268 |
| 42198 | GIM_Try, /*On fail goto*//*Label 2320*/ GIMT_Encode4(116301), // Rule ID 1234 // |
| 42199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), |
| 42200 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42201 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42202 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42203 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42204 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42205 | // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 42206 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDh), |
| 42207 | GIR_RootConstrainSelectedInstOperands, |
| 42208 | // GIR_Coverage, 1234, |
| 42209 | GIR_Done, |
| 42210 | // Label 2320: @116301 |
| 42211 | GIM_Reject, |
| 42212 | // Label 2313: @116302 |
| 42213 | GIM_Try, /*On fail goto*//*Label 2321*/ GIMT_Encode4(116478), |
| 42214 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42215 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42216 | GIM_Try, /*On fail goto*//*Label 2322*/ GIMT_Encode4(116391), // Rule ID 4233 // |
| 42217 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 42218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42219 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42220 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42221 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42222 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42223 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 42224 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42225 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42226 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42227 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42228 | // (fmaxnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 42229 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32), |
| 42230 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42231 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 42232 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 42233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42234 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42235 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42236 | GIR_RootConstrainSelectedInstOperands, |
| 42237 | // GIR_Coverage, 4233, |
| 42238 | GIR_EraseRootFromParent_Done, |
| 42239 | // Label 2322: @116391 |
| 42240 | GIM_Try, /*On fail goto*//*Label 2323*/ GIMT_Encode4(116418), // Rule ID 1233 // |
| 42241 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), |
| 42242 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42243 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42244 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42245 | // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 42246 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQf), |
| 42247 | GIR_RootConstrainSelectedInstOperands, |
| 42248 | // GIR_Coverage, 1233, |
| 42249 | GIR_Done, |
| 42250 | // Label 2323: @116418 |
| 42251 | GIM_Try, /*On fail goto*//*Label 2324*/ GIMT_Encode4(116477), // Rule ID 3127 // |
| 42252 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42253 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42254 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42255 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42256 | // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 42257 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42258 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42259 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 42260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32), |
| 42261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42262 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 42263 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 42264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42265 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42266 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42267 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42268 | GIR_RootConstrainSelectedInstOperands, |
| 42269 | // GIR_Coverage, 3127, |
| 42270 | GIR_EraseRootFromParent_Done, |
| 42271 | // Label 2324: @116477 |
| 42272 | GIM_Reject, |
| 42273 | // Label 2321: @116478 |
| 42274 | GIM_Reject, |
| 42275 | // Label 2314: @116479 |
| 42276 | GIM_Try, /*On fail goto*//*Label 2325*/ GIMT_Encode4(116655), |
| 42277 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42278 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42279 | GIM_Try, /*On fail goto*//*Label 2326*/ GIMT_Encode4(116568), // Rule ID 4235 // |
| 42280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 42281 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42282 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42283 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42284 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42285 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42286 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 42287 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42288 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42289 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42290 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42291 | // (fmaxnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 42292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16), |
| 42293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42294 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 42295 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 42296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42297 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42298 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42299 | GIR_RootConstrainSelectedInstOperands, |
| 42300 | // GIR_Coverage, 4235, |
| 42301 | GIR_EraseRootFromParent_Done, |
| 42302 | // Label 2326: @116568 |
| 42303 | GIM_Try, /*On fail goto*//*Label 2327*/ GIMT_Encode4(116595), // Rule ID 1235 // |
| 42304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), |
| 42305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42306 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42307 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42308 | // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 42309 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQh), |
| 42310 | GIR_RootConstrainSelectedInstOperands, |
| 42311 | // GIR_Coverage, 1235, |
| 42312 | GIR_Done, |
| 42313 | // Label 2327: @116595 |
| 42314 | GIM_Try, /*On fail goto*//*Label 2328*/ GIMT_Encode4(116654), // Rule ID 3382 // |
| 42315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42317 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42318 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42319 | // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 42320 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42321 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42322 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 42323 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16), |
| 42324 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42325 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 42326 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 42327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42328 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42329 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42330 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42331 | GIR_RootConstrainSelectedInstOperands, |
| 42332 | // GIR_Coverage, 3382, |
| 42333 | GIR_EraseRootFromParent_Done, |
| 42334 | // Label 2328: @116654 |
| 42335 | GIM_Reject, |
| 42336 | // Label 2325: @116655 |
| 42337 | GIM_Reject, |
| 42338 | // Label 2315: @116656 |
| 42339 | GIM_Reject, |
| 42340 | // Label 46: @116657 |
| 42341 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2335*/ GIMT_Encode4(117372), |
| 42342 | /*GILLT_s16*//*Label 2329*/ GIMT_Encode4(116720), |
| 42343 | /*GILLT_s32*//*Label 2330*/ GIMT_Encode4(116952), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42344 | /*GILLT_v2s32*//*Label 2331*/ GIMT_Encode4(117184), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42345 | /*GILLT_v4s16*//*Label 2332*/ GIMT_Encode4(117231), |
| 42346 | /*GILLT_v4s32*//*Label 2333*/ GIMT_Encode4(117278), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42347 | /*GILLT_v8s16*//*Label 2334*/ GIMT_Encode4(117325), |
| 42348 | // Label 2329: @116720 |
| 42349 | GIM_Try, /*On fail goto*//*Label 2336*/ GIMT_Encode4(116951), // Rule ID 2725 // |
| 42350 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 42351 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 42352 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 42353 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42354 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42355 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42356 | // (fminimum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMINhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 42357 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16, |
| 42358 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 42359 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16, |
| 42360 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16, |
| 42361 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16, |
| 42362 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16, |
| 42363 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16, |
| 42364 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16, |
| 42365 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42366 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42367 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 42368 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42369 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42370 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 42371 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 42372 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42373 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42374 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 42375 | GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 42376 | GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 42377 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42378 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42379 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 42380 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42381 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42382 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 42383 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42384 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42385 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 42386 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 42387 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42388 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42389 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 42390 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42391 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 42392 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42393 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42394 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 42395 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINhd), |
| 42396 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42397 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 42398 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 42399 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 42400 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42401 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 42402 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42403 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42404 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 42405 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42406 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42407 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42408 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 42409 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42410 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42411 | // GIR_Coverage, 2725, |
| 42412 | GIR_EraseRootFromParent_Done, |
| 42413 | // Label 2336: @116951 |
| 42414 | GIM_Reject, |
| 42415 | // Label 2330: @116952 |
| 42416 | GIM_Try, /*On fail goto*//*Label 2337*/ GIMT_Encode4(117183), // Rule ID 2727 // |
| 42417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42418 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42419 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42420 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42421 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42422 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42423 | // (fminimum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMINfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 42424 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 42425 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 42426 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 42427 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 42428 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 42429 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 42430 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 42431 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 42432 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42433 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42434 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 42435 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42436 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42437 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 42438 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 42439 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42440 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42441 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 42442 | GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 42443 | GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 42444 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42445 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42446 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42447 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42448 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42449 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 42450 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42451 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42452 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 42453 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 42454 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42455 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42456 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 42457 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42458 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 42459 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42460 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42461 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42462 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINfd), |
| 42463 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42464 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 42465 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 42466 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 42467 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42468 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 42469 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42470 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42471 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 42472 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42473 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42474 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42475 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 42476 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42477 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42478 | // GIR_Coverage, 2727, |
| 42479 | GIR_EraseRootFromParent_Done, |
| 42480 | // Label 2337: @117183 |
| 42481 | GIM_Reject, |
| 42482 | // Label 2331: @117184 |
| 42483 | GIM_Try, /*On fail goto*//*Label 2338*/ GIMT_Encode4(117230), // Rule ID 1248 // |
| 42484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42485 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42486 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42487 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42488 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42489 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42490 | // (fminimum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMINfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 42491 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfd), |
| 42492 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42493 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42494 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42496 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42497 | GIR_RootConstrainSelectedInstOperands, |
| 42498 | // GIR_Coverage, 1248, |
| 42499 | GIR_EraseRootFromParent_Done, |
| 42500 | // Label 2338: @117230 |
| 42501 | GIM_Reject, |
| 42502 | // Label 2332: @117231 |
| 42503 | GIM_Try, /*On fail goto*//*Label 2339*/ GIMT_Encode4(117277), // Rule ID 1250 // |
| 42504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42505 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42506 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42508 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42509 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42510 | // (fminimum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMINhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 42511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhd), |
| 42512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42513 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42514 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42516 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42517 | GIR_RootConstrainSelectedInstOperands, |
| 42518 | // GIR_Coverage, 1250, |
| 42519 | GIR_EraseRootFromParent_Done, |
| 42520 | // Label 2339: @117277 |
| 42521 | GIM_Reject, |
| 42522 | // Label 2333: @117278 |
| 42523 | GIM_Try, /*On fail goto*//*Label 2340*/ GIMT_Encode4(117324), // Rule ID 1249 // |
| 42524 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42525 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42526 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42527 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42528 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42529 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42530 | // (fminimum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMINfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 42531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfq), |
| 42532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42533 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42534 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42536 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42537 | GIR_RootConstrainSelectedInstOperands, |
| 42538 | // GIR_Coverage, 1249, |
| 42539 | GIR_EraseRootFromParent_Done, |
| 42540 | // Label 2340: @117324 |
| 42541 | GIM_Reject, |
| 42542 | // Label 2334: @117325 |
| 42543 | GIM_Try, /*On fail goto*//*Label 2341*/ GIMT_Encode4(117371), // Rule ID 1251 // |
| 42544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42545 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42546 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42547 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42548 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42549 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42550 | // (fminimum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMINhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 42551 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhq), |
| 42552 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42553 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42554 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42556 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42557 | GIR_RootConstrainSelectedInstOperands, |
| 42558 | // GIR_Coverage, 1251, |
| 42559 | GIR_EraseRootFromParent_Done, |
| 42560 | // Label 2341: @117371 |
| 42561 | GIM_Reject, |
| 42562 | // Label 2335: @117372 |
| 42563 | GIM_Reject, |
| 42564 | // Label 47: @117373 |
| 42565 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2348*/ GIMT_Encode4(118088), |
| 42566 | /*GILLT_s16*//*Label 2342*/ GIMT_Encode4(117436), |
| 42567 | /*GILLT_s32*//*Label 2343*/ GIMT_Encode4(117668), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42568 | /*GILLT_v2s32*//*Label 2344*/ GIMT_Encode4(117900), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42569 | /*GILLT_v4s16*//*Label 2345*/ GIMT_Encode4(117947), |
| 42570 | /*GILLT_v4s32*//*Label 2346*/ GIMT_Encode4(117994), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42571 | /*GILLT_v8s16*//*Label 2347*/ GIMT_Encode4(118041), |
| 42572 | // Label 2342: @117436 |
| 42573 | GIM_Try, /*On fail goto*//*Label 2349*/ GIMT_Encode4(117667), // Rule ID 2724 // |
| 42574 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 42575 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 42576 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 42577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42578 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42579 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42580 | // (fmaximum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMAXhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 42581 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16, |
| 42582 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 42583 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16, |
| 42584 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16, |
| 42585 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16, |
| 42586 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16, |
| 42587 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16, |
| 42588 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16, |
| 42589 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42590 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 42592 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42593 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42594 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 42595 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 42596 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42597 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42598 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 42599 | GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 42600 | GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 42601 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42602 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42603 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 42604 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42605 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42606 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 42607 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42608 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42609 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 42610 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 42611 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42612 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42613 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 42614 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42615 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 42616 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42617 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42618 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 42619 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXhd), |
| 42620 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42621 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 42622 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 42623 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 42624 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42625 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 42626 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42627 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42628 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 42629 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42630 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42631 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42632 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 42633 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42634 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42635 | // GIR_Coverage, 2724, |
| 42636 | GIR_EraseRootFromParent_Done, |
| 42637 | // Label 2349: @117667 |
| 42638 | GIM_Reject, |
| 42639 | // Label 2343: @117668 |
| 42640 | GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(117899), // Rule ID 2726 // |
| 42641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42642 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42643 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42644 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42645 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42646 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42647 | // (fmaximum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMAXfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 42648 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 42649 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 42650 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 42651 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 42652 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 42653 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 42654 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 42655 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 42656 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42657 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42658 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 42659 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42660 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42661 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 42662 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 42663 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42664 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42665 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 42666 | GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 42667 | GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 42668 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42669 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42670 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42671 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42672 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42673 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 42674 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42675 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42676 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 42677 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 42678 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42679 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42680 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 42681 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42682 | GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 42683 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42684 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42685 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42686 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXfd), |
| 42687 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42688 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 42689 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 42690 | GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 42691 | GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42692 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 42693 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42694 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42695 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 42696 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42699 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 42700 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42701 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42702 | // GIR_Coverage, 2726, |
| 42703 | GIR_EraseRootFromParent_Done, |
| 42704 | // Label 2350: @117899 |
| 42705 | GIM_Reject, |
| 42706 | // Label 2344: @117900 |
| 42707 | GIM_Try, /*On fail goto*//*Label 2351*/ GIMT_Encode4(117946), // Rule ID 1228 // |
| 42708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42709 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42710 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42712 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42713 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42714 | // (fmaximum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMAXfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 42715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfd), |
| 42716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42717 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42718 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42720 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42721 | GIR_RootConstrainSelectedInstOperands, |
| 42722 | // GIR_Coverage, 1228, |
| 42723 | GIR_EraseRootFromParent_Done, |
| 42724 | // Label 2351: @117946 |
| 42725 | GIM_Reject, |
| 42726 | // Label 2345: @117947 |
| 42727 | GIM_Try, /*On fail goto*//*Label 2352*/ GIMT_Encode4(117993), // Rule ID 1230 // |
| 42728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42729 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42730 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42731 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42732 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42733 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42734 | // (fmaximum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMAXhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 42735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhd), |
| 42736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42737 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42738 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42740 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42741 | GIR_RootConstrainSelectedInstOperands, |
| 42742 | // GIR_Coverage, 1230, |
| 42743 | GIR_EraseRootFromParent_Done, |
| 42744 | // Label 2352: @117993 |
| 42745 | GIM_Reject, |
| 42746 | // Label 2346: @117994 |
| 42747 | GIM_Try, /*On fail goto*//*Label 2353*/ GIMT_Encode4(118040), // Rule ID 1229 // |
| 42748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42749 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42750 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42751 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42752 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42753 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42754 | // (fmaximum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMAXfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 42755 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfq), |
| 42756 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42757 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42758 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42760 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42761 | GIR_RootConstrainSelectedInstOperands, |
| 42762 | // GIR_Coverage, 1229, |
| 42763 | GIR_EraseRootFromParent_Done, |
| 42764 | // Label 2353: @118040 |
| 42765 | GIM_Reject, |
| 42766 | // Label 2347: @118041 |
| 42767 | GIM_Try, /*On fail goto*//*Label 2354*/ GIMT_Encode4(118087), // Rule ID 1231 // |
| 42768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42769 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42770 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42772 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42773 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42774 | // (fmaximum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMAXhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 42775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhq), |
| 42776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42777 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42778 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42780 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42781 | GIR_RootConstrainSelectedInstOperands, |
| 42782 | // GIR_Coverage, 1231, |
| 42783 | GIR_EraseRootFromParent_Done, |
| 42784 | // Label 2354: @118087 |
| 42785 | GIM_Reject, |
| 42786 | // Label 2348: @118088 |
| 42787 | GIM_Reject, |
| 42788 | // Label 48: @118089 |
| 42789 | GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(118121), // Rule ID 2414 // |
| 42790 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 42792 | // (get_fpenv:{ *:[i32] }) => (VMRS:{ *:[i32] }) |
| 42793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 42794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 42795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42796 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42797 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42798 | GIR_RootConstrainSelectedInstOperands, |
| 42799 | // GIR_Coverage, 2414, |
| 42800 | GIR_EraseRootFromParent_Done, |
| 42801 | // Label 2355: @118121 |
| 42802 | GIM_Reject, |
| 42803 | // Label 49: @118122 |
| 42804 | GIM_Try, /*On fail goto*//*Label 2356*/ GIMT_Encode4(118157), // Rule ID 2415 // |
| 42805 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 42807 | // (set_fpenv GPRnopc:{ *:[i32] }:$Rt) => (VMSR GPRnopc:{ *:[i32] }:$Rt) |
| 42808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 42809 | GIR_RootToRootCopy, /*OpIdx*/0, // Rt |
| 42810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42811 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42812 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 42813 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42814 | GIR_RootConstrainSelectedInstOperands, |
| 42815 | // GIR_Coverage, 2415, |
| 42816 | GIR_EraseRootFromParent_Done, |
| 42817 | // Label 2356: @118157 |
| 42818 | GIM_Reject, |
| 42819 | // Label 50: @118158 |
| 42820 | GIM_Try, /*On fail goto*//*Label 2357*/ GIMT_Encode4(118222), // Rule ID 2416 // |
| 42821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 42822 | // (reset_fpenv) => (VMSR (MOVi:{ *:[i32] } 0:{ *:[i32] })) |
| 42823 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42824 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MOVi), |
| 42825 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42826 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 42827 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42828 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42829 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42830 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42831 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 42832 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42834 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42835 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 42836 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42837 | GIR_RootConstrainSelectedInstOperands, |
| 42838 | // GIR_Coverage, 2416, |
| 42839 | GIR_EraseRootFromParent_Done, |
| 42840 | // Label 2357: @118222 |
| 42841 | GIM_Reject, |
| 42842 | // Label 51: @118223 |
| 42843 | GIM_Try, /*On fail goto*//*Label 2358*/ GIMT_Encode4(118255), // Rule ID 2418 // |
| 42844 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 42845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 42846 | // (get_fpmode:{ *:[i32] }) => (VMRS:{ *:[i32] }) |
| 42847 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 42848 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 42849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42850 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42851 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42852 | GIR_RootConstrainSelectedInstOperands, |
| 42853 | // GIR_Coverage, 2418, |
| 42854 | GIR_EraseRootFromParent_Done, |
| 42855 | // Label 2358: @118255 |
| 42856 | GIM_Reject, |
| 42857 | // Label 52: @118256 |
| 42858 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2365*/ GIMT_Encode4(118792), |
| 42859 | /*GILLT_v2s32*//*Label 2359*/ GIMT_Encode4(118315), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42860 | /*GILLT_v4s16*//*Label 2360*/ GIMT_Encode4(118362), |
| 42861 | /*GILLT_v4s32*//*Label 2361*/ GIMT_Encode4(118409), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42862 | /*GILLT_v8s8*//*Label 2362*/ GIMT_Encode4(118521), |
| 42863 | /*GILLT_v8s16*//*Label 2363*/ GIMT_Encode4(118568), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42864 | /*GILLT_v16s8*//*Label 2364*/ GIMT_Encode4(118680), |
| 42865 | // Label 2359: @118315 |
| 42866 | GIM_Try, /*On fail goto*//*Label 2366*/ GIMT_Encode4(118361), // Rule ID 1237 // |
| 42867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42868 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42869 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42870 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42871 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42872 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42873 | // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 42874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv2i32), |
| 42875 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42876 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42877 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42879 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42880 | GIR_RootConstrainSelectedInstOperands, |
| 42881 | // GIR_Coverage, 1237, |
| 42882 | GIR_EraseRootFromParent_Done, |
| 42883 | // Label 2366: @118361 |
| 42884 | GIM_Reject, |
| 42885 | // Label 2360: @118362 |
| 42886 | GIM_Try, /*On fail goto*//*Label 2367*/ GIMT_Encode4(118408), // Rule ID 1236 // |
| 42887 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42888 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42889 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42891 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42892 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42893 | // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 42894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i16), |
| 42895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42896 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42897 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42899 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42900 | GIR_RootConstrainSelectedInstOperands, |
| 42901 | // GIR_Coverage, 1236, |
| 42902 | GIR_EraseRootFromParent_Done, |
| 42903 | // Label 2367: @118408 |
| 42904 | GIM_Reject, |
| 42905 | // Label 2361: @118409 |
| 42906 | GIM_Try, /*On fail goto*//*Label 2368*/ GIMT_Encode4(118520), |
| 42907 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42908 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42909 | GIM_Try, /*On fail goto*//*Label 2369*/ GIMT_Encode4(118460), // Rule ID 1239 // |
| 42910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42911 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42912 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42913 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42914 | // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 42915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i32), |
| 42916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42917 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42918 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42920 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42921 | GIR_RootConstrainSelectedInstOperands, |
| 42922 | // GIR_Coverage, 1239, |
| 42923 | GIR_EraseRootFromParent_Done, |
| 42924 | // Label 2369: @118460 |
| 42925 | GIM_Try, /*On fail goto*//*Label 2370*/ GIMT_Encode4(118519), // Rule ID 3397 // |
| 42926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 42927 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42928 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42929 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42930 | // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 42931 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42932 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42933 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 42934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs32), |
| 42935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42936 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 42937 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 42938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42939 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42940 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42941 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42942 | GIR_RootConstrainSelectedInstOperands, |
| 42943 | // GIR_Coverage, 3397, |
| 42944 | GIR_EraseRootFromParent_Done, |
| 42945 | // Label 2370: @118519 |
| 42946 | GIM_Reject, |
| 42947 | // Label 2368: @118520 |
| 42948 | GIM_Reject, |
| 42949 | // Label 2362: @118521 |
| 42950 | GIM_Try, /*On fail goto*//*Label 2371*/ GIMT_Encode4(118567), // Rule ID 1240 // |
| 42951 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42952 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 42953 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 42954 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42955 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42956 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42957 | // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 42958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i8), |
| 42959 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42960 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42961 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42963 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42964 | GIR_RootConstrainSelectedInstOperands, |
| 42965 | // GIR_Coverage, 1240, |
| 42966 | GIR_EraseRootFromParent_Done, |
| 42967 | // Label 2371: @118567 |
| 42968 | GIM_Reject, |
| 42969 | // Label 2363: @118568 |
| 42970 | GIM_Try, /*On fail goto*//*Label 2372*/ GIMT_Encode4(118679), |
| 42971 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42972 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42973 | GIM_Try, /*On fail goto*//*Label 2373*/ GIMT_Encode4(118619), // Rule ID 1238 // |
| 42974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42976 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42977 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42978 | // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 42979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i16), |
| 42980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42981 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 42982 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 42983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42984 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42985 | GIR_RootConstrainSelectedInstOperands, |
| 42986 | // GIR_Coverage, 1238, |
| 42987 | GIR_EraseRootFromParent_Done, |
| 42988 | // Label 2373: @118619 |
| 42989 | GIM_Try, /*On fail goto*//*Label 2374*/ GIMT_Encode4(118678), // Rule ID 3394 // |
| 42990 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 42991 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42992 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42993 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42994 | // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 42995 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42996 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42997 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 42998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs16), |
| 42999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43000 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43001 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43003 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43004 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43005 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43006 | GIR_RootConstrainSelectedInstOperands, |
| 43007 | // GIR_Coverage, 3394, |
| 43008 | GIR_EraseRootFromParent_Done, |
| 43009 | // Label 2374: @118678 |
| 43010 | GIM_Reject, |
| 43011 | // Label 2372: @118679 |
| 43012 | GIM_Reject, |
| 43013 | // Label 2364: @118680 |
| 43014 | GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(118791), |
| 43015 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 43016 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 43017 | GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(118731), // Rule ID 1241 // |
| 43018 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43019 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43020 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43021 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43022 | // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 43023 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv16i8), |
| 43024 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43025 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43026 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43028 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43029 | GIR_RootConstrainSelectedInstOperands, |
| 43030 | // GIR_Coverage, 1241, |
| 43031 | GIR_EraseRootFromParent_Done, |
| 43032 | // Label 2376: @118731 |
| 43033 | GIM_Try, /*On fail goto*//*Label 2377*/ GIMT_Encode4(118790), // Rule ID 3391 // |
| 43034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43035 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43036 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43037 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43038 | // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 43039 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43040 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43041 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 43042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs8), |
| 43043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43044 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43045 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43047 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43048 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43049 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43050 | GIR_RootConstrainSelectedInstOperands, |
| 43051 | // GIR_Coverage, 3391, |
| 43052 | GIR_EraseRootFromParent_Done, |
| 43053 | // Label 2377: @118790 |
| 43054 | GIM_Reject, |
| 43055 | // Label 2375: @118791 |
| 43056 | GIM_Reject, |
| 43057 | // Label 2365: @118792 |
| 43058 | GIM_Reject, |
| 43059 | // Label 53: @118793 |
| 43060 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2384*/ GIMT_Encode4(119329), |
| 43061 | /*GILLT_v2s32*//*Label 2378*/ GIMT_Encode4(118852), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43062 | /*GILLT_v4s16*//*Label 2379*/ GIMT_Encode4(118899), |
| 43063 | /*GILLT_v4s32*//*Label 2380*/ GIMT_Encode4(118946), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43064 | /*GILLT_v8s8*//*Label 2381*/ GIMT_Encode4(119058), |
| 43065 | /*GILLT_v8s16*//*Label 2382*/ GIMT_Encode4(119105), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43066 | /*GILLT_v16s8*//*Label 2383*/ GIMT_Encode4(119217), |
| 43067 | // Label 2378: @118852 |
| 43068 | GIM_Try, /*On fail goto*//*Label 2385*/ GIMT_Encode4(118898), // Rule ID 1217 // |
| 43069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43070 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43071 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43073 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43074 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43075 | // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 43076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv2i32), |
| 43077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43078 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43079 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43081 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43082 | GIR_RootConstrainSelectedInstOperands, |
| 43083 | // GIR_Coverage, 1217, |
| 43084 | GIR_EraseRootFromParent_Done, |
| 43085 | // Label 2385: @118898 |
| 43086 | GIM_Reject, |
| 43087 | // Label 2379: @118899 |
| 43088 | GIM_Try, /*On fail goto*//*Label 2386*/ GIMT_Encode4(118945), // Rule ID 1216 // |
| 43089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43090 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43091 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43092 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43093 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43094 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43095 | // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 43096 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i16), |
| 43097 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43098 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43099 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43101 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43102 | GIR_RootConstrainSelectedInstOperands, |
| 43103 | // GIR_Coverage, 1216, |
| 43104 | GIR_EraseRootFromParent_Done, |
| 43105 | // Label 2386: @118945 |
| 43106 | GIM_Reject, |
| 43107 | // Label 2380: @118946 |
| 43108 | GIM_Try, /*On fail goto*//*Label 2387*/ GIMT_Encode4(119057), |
| 43109 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43110 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43111 | GIM_Try, /*On fail goto*//*Label 2388*/ GIMT_Encode4(118997), // Rule ID 1219 // |
| 43112 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43113 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43114 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43115 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43116 | // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 43117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i32), |
| 43118 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43119 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43120 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43122 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43123 | GIR_RootConstrainSelectedInstOperands, |
| 43124 | // GIR_Coverage, 1219, |
| 43125 | GIR_EraseRootFromParent_Done, |
| 43126 | // Label 2388: @118997 |
| 43127 | GIM_Try, /*On fail goto*//*Label 2389*/ GIMT_Encode4(119056), // Rule ID 3415 // |
| 43128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43129 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43130 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43131 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43132 | // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 43133 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43134 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43135 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 43136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs32), |
| 43137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43138 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43139 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43141 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43142 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43143 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43144 | GIR_RootConstrainSelectedInstOperands, |
| 43145 | // GIR_Coverage, 3415, |
| 43146 | GIR_EraseRootFromParent_Done, |
| 43147 | // Label 2389: @119056 |
| 43148 | GIM_Reject, |
| 43149 | // Label 2387: @119057 |
| 43150 | GIM_Reject, |
| 43151 | // Label 2381: @119058 |
| 43152 | GIM_Try, /*On fail goto*//*Label 2390*/ GIMT_Encode4(119104), // Rule ID 1220 // |
| 43153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43154 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 43155 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 43156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43157 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43158 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43159 | // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 43160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i8), |
| 43161 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43162 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43163 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43165 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43166 | GIR_RootConstrainSelectedInstOperands, |
| 43167 | // GIR_Coverage, 1220, |
| 43168 | GIR_EraseRootFromParent_Done, |
| 43169 | // Label 2390: @119104 |
| 43170 | GIM_Reject, |
| 43171 | // Label 2382: @119105 |
| 43172 | GIM_Try, /*On fail goto*//*Label 2391*/ GIMT_Encode4(119216), |
| 43173 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43174 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43175 | GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(119156), // Rule ID 1218 // |
| 43176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43178 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43179 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43180 | // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 43181 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i16), |
| 43182 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43183 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43184 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43186 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43187 | GIR_RootConstrainSelectedInstOperands, |
| 43188 | // GIR_Coverage, 1218, |
| 43189 | GIR_EraseRootFromParent_Done, |
| 43190 | // Label 2392: @119156 |
| 43191 | GIM_Try, /*On fail goto*//*Label 2393*/ GIMT_Encode4(119215), // Rule ID 3412 // |
| 43192 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43193 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43194 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43195 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43196 | // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 43197 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43198 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43199 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 43200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs16), |
| 43201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43202 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43203 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43205 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43206 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43207 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43208 | GIR_RootConstrainSelectedInstOperands, |
| 43209 | // GIR_Coverage, 3412, |
| 43210 | GIR_EraseRootFromParent_Done, |
| 43211 | // Label 2393: @119215 |
| 43212 | GIM_Reject, |
| 43213 | // Label 2391: @119216 |
| 43214 | GIM_Reject, |
| 43215 | // Label 2383: @119217 |
| 43216 | GIM_Try, /*On fail goto*//*Label 2394*/ GIMT_Encode4(119328), |
| 43217 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 43218 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 43219 | GIM_Try, /*On fail goto*//*Label 2395*/ GIMT_Encode4(119268), // Rule ID 1221 // |
| 43220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43221 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43222 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43223 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43224 | // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 43225 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv16i8), |
| 43226 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43227 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43228 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43230 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43231 | GIR_RootConstrainSelectedInstOperands, |
| 43232 | // GIR_Coverage, 1221, |
| 43233 | GIR_EraseRootFromParent_Done, |
| 43234 | // Label 2395: @119268 |
| 43235 | GIM_Try, /*On fail goto*//*Label 2396*/ GIMT_Encode4(119327), // Rule ID 3409 // |
| 43236 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43237 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43238 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43239 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43240 | // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 43241 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43242 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43243 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 43244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs8), |
| 43245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43246 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43247 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43249 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43250 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43251 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43252 | GIR_RootConstrainSelectedInstOperands, |
| 43253 | // GIR_Coverage, 3409, |
| 43254 | GIR_EraseRootFromParent_Done, |
| 43255 | // Label 2396: @119327 |
| 43256 | GIM_Reject, |
| 43257 | // Label 2394: @119328 |
| 43258 | GIM_Reject, |
| 43259 | // Label 2384: @119329 |
| 43260 | GIM_Reject, |
| 43261 | // Label 54: @119330 |
| 43262 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2403*/ GIMT_Encode4(120244), |
| 43263 | /*GILLT_v2s32*//*Label 2397*/ GIMT_Encode4(119389), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43264 | /*GILLT_v4s16*//*Label 2398*/ GIMT_Encode4(119436), |
| 43265 | /*GILLT_v4s32*//*Label 2399*/ GIMT_Encode4(119483), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43266 | /*GILLT_v8s8*//*Label 2400*/ GIMT_Encode4(119721), |
| 43267 | /*GILLT_v8s16*//*Label 2401*/ GIMT_Encode4(119768), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43268 | /*GILLT_v16s8*//*Label 2402*/ GIMT_Encode4(120006), |
| 43269 | // Label 2397: @119389 |
| 43270 | GIM_Try, /*On fail goto*//*Label 2404*/ GIMT_Encode4(119435), // Rule ID 1243 // |
| 43271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43272 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43273 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43275 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43276 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43277 | // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 43278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv2i32), |
| 43279 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43280 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43281 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43283 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43284 | GIR_RootConstrainSelectedInstOperands, |
| 43285 | // GIR_Coverage, 1243, |
| 43286 | GIR_EraseRootFromParent_Done, |
| 43287 | // Label 2404: @119435 |
| 43288 | GIM_Reject, |
| 43289 | // Label 2398: @119436 |
| 43290 | GIM_Try, /*On fail goto*//*Label 2405*/ GIMT_Encode4(119482), // Rule ID 1242 // |
| 43291 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43292 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43293 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43294 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43295 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43296 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43297 | // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 43298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i16), |
| 43299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43300 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43301 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43303 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43304 | GIR_RootConstrainSelectedInstOperands, |
| 43305 | // GIR_Coverage, 1242, |
| 43306 | GIR_EraseRootFromParent_Done, |
| 43307 | // Label 2405: @119482 |
| 43308 | GIM_Reject, |
| 43309 | // Label 2399: @119483 |
| 43310 | GIM_Try, /*On fail goto*//*Label 2406*/ GIMT_Encode4(119720), |
| 43311 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43312 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43313 | GIM_Try, /*On fail goto*//*Label 2407*/ GIMT_Encode4(119557), // Rule ID 6156 // |
| 43314 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43315 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43316 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43317 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 43318 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43319 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43320 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43321 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43322 | // (umin:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 43323 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32), |
| 43324 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43325 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 43326 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 43327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43328 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43329 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43330 | GIR_RootConstrainSelectedInstOperands, |
| 43331 | // GIR_Coverage, 6156, |
| 43332 | GIR_EraseRootFromParent_Done, |
| 43333 | // Label 2407: @119557 |
| 43334 | GIM_Try, /*On fail goto*//*Label 2408*/ GIMT_Encode4(119620), // Rule ID 3812 // |
| 43335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43337 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43338 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 43339 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 43340 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43341 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43342 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43343 | // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 43344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32), |
| 43345 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43346 | GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 43347 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 43348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43349 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43350 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43351 | GIR_RootConstrainSelectedInstOperands, |
| 43352 | // GIR_Coverage, 3812, |
| 43353 | GIR_EraseRootFromParent_Done, |
| 43354 | // Label 2408: @119620 |
| 43355 | GIM_Try, /*On fail goto*//*Label 2409*/ GIMT_Encode4(119660), // Rule ID 1245 // |
| 43356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43357 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43358 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43359 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43360 | // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 43361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i32), |
| 43362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43363 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43364 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43366 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43367 | GIR_RootConstrainSelectedInstOperands, |
| 43368 | // GIR_Coverage, 1245, |
| 43369 | GIR_EraseRootFromParent_Done, |
| 43370 | // Label 2409: @119660 |
| 43371 | GIM_Try, /*On fail goto*//*Label 2410*/ GIMT_Encode4(119719), // Rule ID 3406 // |
| 43372 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43373 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43374 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43375 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43376 | // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 43377 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43378 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43379 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 43380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu32), |
| 43381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43382 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43383 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43385 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43386 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43387 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43388 | GIR_RootConstrainSelectedInstOperands, |
| 43389 | // GIR_Coverage, 3406, |
| 43390 | GIR_EraseRootFromParent_Done, |
| 43391 | // Label 2410: @119719 |
| 43392 | GIM_Reject, |
| 43393 | // Label 2406: @119720 |
| 43394 | GIM_Reject, |
| 43395 | // Label 2400: @119721 |
| 43396 | GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(119767), // Rule ID 1246 // |
| 43397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43398 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 43399 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 43400 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43401 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43402 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43403 | // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 43404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i8), |
| 43405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43406 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43407 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43409 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43410 | GIR_RootConstrainSelectedInstOperands, |
| 43411 | // GIR_Coverage, 1246, |
| 43412 | GIR_EraseRootFromParent_Done, |
| 43413 | // Label 2411: @119767 |
| 43414 | GIM_Reject, |
| 43415 | // Label 2401: @119768 |
| 43416 | GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(120005), |
| 43417 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43418 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43419 | GIM_Try, /*On fail goto*//*Label 2413*/ GIMT_Encode4(119842), // Rule ID 6155 // |
| 43420 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43421 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43422 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43423 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 43424 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43425 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43426 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43427 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43428 | // (umin:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 43429 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16), |
| 43430 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43431 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 43432 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 43433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43434 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43435 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43436 | GIR_RootConstrainSelectedInstOperands, |
| 43437 | // GIR_Coverage, 6155, |
| 43438 | GIR_EraseRootFromParent_Done, |
| 43439 | // Label 2413: @119842 |
| 43440 | GIM_Try, /*On fail goto*//*Label 2414*/ GIMT_Encode4(119905), // Rule ID 3810 // |
| 43441 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43443 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43444 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 43445 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 43446 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43447 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43448 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43449 | // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 43450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16), |
| 43451 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43452 | GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 43453 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 43454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43455 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43456 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43457 | GIR_RootConstrainSelectedInstOperands, |
| 43458 | // GIR_Coverage, 3810, |
| 43459 | GIR_EraseRootFromParent_Done, |
| 43460 | // Label 2414: @119905 |
| 43461 | GIM_Try, /*On fail goto*//*Label 2415*/ GIMT_Encode4(119945), // Rule ID 1244 // |
| 43462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43463 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43464 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43465 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43466 | // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 43467 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i16), |
| 43468 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43469 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43470 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43472 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43473 | GIR_RootConstrainSelectedInstOperands, |
| 43474 | // GIR_Coverage, 1244, |
| 43475 | GIR_EraseRootFromParent_Done, |
| 43476 | // Label 2415: @119945 |
| 43477 | GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(120004), // Rule ID 3403 // |
| 43478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43479 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43480 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43481 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43482 | // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 43483 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43484 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43485 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 43486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu16), |
| 43487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43488 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43489 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43491 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43492 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43493 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43494 | GIR_RootConstrainSelectedInstOperands, |
| 43495 | // GIR_Coverage, 3403, |
| 43496 | GIR_EraseRootFromParent_Done, |
| 43497 | // Label 2416: @120004 |
| 43498 | GIM_Reject, |
| 43499 | // Label 2412: @120005 |
| 43500 | GIM_Reject, |
| 43501 | // Label 2402: @120006 |
| 43502 | GIM_Try, /*On fail goto*//*Label 2417*/ GIMT_Encode4(120243), |
| 43503 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 43504 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 43505 | GIM_Try, /*On fail goto*//*Label 2418*/ GIMT_Encode4(120080), // Rule ID 6154 // |
| 43506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43508 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43509 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 43510 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 43511 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43512 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43513 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43514 | // (umin:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 43515 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8), |
| 43516 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43517 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 43518 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 43519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43520 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43521 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43522 | GIR_RootConstrainSelectedInstOperands, |
| 43523 | // GIR_Coverage, 6154, |
| 43524 | GIR_EraseRootFromParent_Done, |
| 43525 | // Label 2418: @120080 |
| 43526 | GIM_Try, /*On fail goto*//*Label 2419*/ GIMT_Encode4(120143), // Rule ID 3808 // |
| 43527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43528 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43529 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43530 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 43531 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 43532 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 43533 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43534 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43535 | // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 43536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8), |
| 43537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43538 | GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 43539 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 43540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43541 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43542 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43543 | GIR_RootConstrainSelectedInstOperands, |
| 43544 | // GIR_Coverage, 3808, |
| 43545 | GIR_EraseRootFromParent_Done, |
| 43546 | // Label 2419: @120143 |
| 43547 | GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(120183), // Rule ID 1247 // |
| 43548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43549 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43550 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43551 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43552 | // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 43553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv16i8), |
| 43554 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43555 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43556 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43558 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43559 | GIR_RootConstrainSelectedInstOperands, |
| 43560 | // GIR_Coverage, 1247, |
| 43561 | GIR_EraseRootFromParent_Done, |
| 43562 | // Label 2420: @120183 |
| 43563 | GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(120242), // Rule ID 3400 // |
| 43564 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43565 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43566 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43567 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43568 | // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 43569 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43570 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43571 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 43572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu8), |
| 43573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43574 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43575 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43577 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43578 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43579 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43580 | GIR_RootConstrainSelectedInstOperands, |
| 43581 | // GIR_Coverage, 3400, |
| 43582 | GIR_EraseRootFromParent_Done, |
| 43583 | // Label 2421: @120242 |
| 43584 | GIM_Reject, |
| 43585 | // Label 2417: @120243 |
| 43586 | GIM_Reject, |
| 43587 | // Label 2403: @120244 |
| 43588 | GIM_Reject, |
| 43589 | // Label 55: @120245 |
| 43590 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2428*/ GIMT_Encode4(121159), |
| 43591 | /*GILLT_v2s32*//*Label 2422*/ GIMT_Encode4(120304), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43592 | /*GILLT_v4s16*//*Label 2423*/ GIMT_Encode4(120351), |
| 43593 | /*GILLT_v4s32*//*Label 2424*/ GIMT_Encode4(120398), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43594 | /*GILLT_v8s8*//*Label 2425*/ GIMT_Encode4(120636), |
| 43595 | /*GILLT_v8s16*//*Label 2426*/ GIMT_Encode4(120683), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43596 | /*GILLT_v16s8*//*Label 2427*/ GIMT_Encode4(120921), |
| 43597 | // Label 2422: @120304 |
| 43598 | GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(120350), // Rule ID 1223 // |
| 43599 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43600 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43601 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43603 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43604 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43605 | // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 43606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv2i32), |
| 43607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43608 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43609 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43611 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43612 | GIR_RootConstrainSelectedInstOperands, |
| 43613 | // GIR_Coverage, 1223, |
| 43614 | GIR_EraseRootFromParent_Done, |
| 43615 | // Label 2429: @120350 |
| 43616 | GIM_Reject, |
| 43617 | // Label 2423: @120351 |
| 43618 | GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(120397), // Rule ID 1222 // |
| 43619 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43620 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43621 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43623 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43624 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43625 | // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 43626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i16), |
| 43627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43628 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43629 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43631 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43632 | GIR_RootConstrainSelectedInstOperands, |
| 43633 | // GIR_Coverage, 1222, |
| 43634 | GIR_EraseRootFromParent_Done, |
| 43635 | // Label 2430: @120397 |
| 43636 | GIM_Reject, |
| 43637 | // Label 2424: @120398 |
| 43638 | GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(120635), |
| 43639 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43640 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43641 | GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(120472), // Rule ID 6159 // |
| 43642 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43643 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43644 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43645 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 43646 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43647 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43648 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43649 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43650 | // (umax:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 43651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32), |
| 43652 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43653 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 43654 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 43655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43656 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43657 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43658 | GIR_RootConstrainSelectedInstOperands, |
| 43659 | // GIR_Coverage, 6159, |
| 43660 | GIR_EraseRootFromParent_Done, |
| 43661 | // Label 2432: @120472 |
| 43662 | GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(120535), // Rule ID 3818 // |
| 43663 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43664 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43665 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43666 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 43667 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 43668 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43669 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43670 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43671 | // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 43672 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32), |
| 43673 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43674 | GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 43675 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 43676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43677 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43678 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43679 | GIR_RootConstrainSelectedInstOperands, |
| 43680 | // GIR_Coverage, 3818, |
| 43681 | GIR_EraseRootFromParent_Done, |
| 43682 | // Label 2433: @120535 |
| 43683 | GIM_Try, /*On fail goto*//*Label 2434*/ GIMT_Encode4(120575), // Rule ID 1225 // |
| 43684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43686 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43687 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43688 | // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 43689 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i32), |
| 43690 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43691 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43692 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43694 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43695 | GIR_RootConstrainSelectedInstOperands, |
| 43696 | // GIR_Coverage, 1225, |
| 43697 | GIR_EraseRootFromParent_Done, |
| 43698 | // Label 2434: @120575 |
| 43699 | GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(120634), // Rule ID 3424 // |
| 43700 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43701 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43702 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43703 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43704 | // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 43705 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43706 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43707 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 43708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu32), |
| 43709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43710 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43711 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43713 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43714 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43715 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43716 | GIR_RootConstrainSelectedInstOperands, |
| 43717 | // GIR_Coverage, 3424, |
| 43718 | GIR_EraseRootFromParent_Done, |
| 43719 | // Label 2435: @120634 |
| 43720 | GIM_Reject, |
| 43721 | // Label 2431: @120635 |
| 43722 | GIM_Reject, |
| 43723 | // Label 2425: @120636 |
| 43724 | GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(120682), // Rule ID 1226 // |
| 43725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43726 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 43727 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 43728 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43729 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43730 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43731 | // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 43732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i8), |
| 43733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43734 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43735 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43737 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43738 | GIR_RootConstrainSelectedInstOperands, |
| 43739 | // GIR_Coverage, 1226, |
| 43740 | GIR_EraseRootFromParent_Done, |
| 43741 | // Label 2436: @120682 |
| 43742 | GIM_Reject, |
| 43743 | // Label 2426: @120683 |
| 43744 | GIM_Try, /*On fail goto*//*Label 2437*/ GIMT_Encode4(120920), |
| 43745 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43746 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43747 | GIM_Try, /*On fail goto*//*Label 2438*/ GIMT_Encode4(120757), // Rule ID 6158 // |
| 43748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43749 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43750 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43751 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 43752 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43753 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43754 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43755 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43756 | // (umax:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 43757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16), |
| 43758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43759 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 43760 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 43761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43762 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43763 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43764 | GIR_RootConstrainSelectedInstOperands, |
| 43765 | // GIR_Coverage, 6158, |
| 43766 | GIR_EraseRootFromParent_Done, |
| 43767 | // Label 2438: @120757 |
| 43768 | GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(120820), // Rule ID 3816 // |
| 43769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43770 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43771 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43772 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 43773 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 43774 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43775 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43776 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43777 | // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 43778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16), |
| 43779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43780 | GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 43781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 43782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43783 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43784 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43785 | GIR_RootConstrainSelectedInstOperands, |
| 43786 | // GIR_Coverage, 3816, |
| 43787 | GIR_EraseRootFromParent_Done, |
| 43788 | // Label 2439: @120820 |
| 43789 | GIM_Try, /*On fail goto*//*Label 2440*/ GIMT_Encode4(120860), // Rule ID 1224 // |
| 43790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43792 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43793 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43794 | // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 43795 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i16), |
| 43796 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43797 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43798 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43800 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43801 | GIR_RootConstrainSelectedInstOperands, |
| 43802 | // GIR_Coverage, 1224, |
| 43803 | GIR_EraseRootFromParent_Done, |
| 43804 | // Label 2440: @120860 |
| 43805 | GIM_Try, /*On fail goto*//*Label 2441*/ GIMT_Encode4(120919), // Rule ID 3421 // |
| 43806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43807 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43808 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43809 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43810 | // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 43811 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43812 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43813 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 43814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu16), |
| 43815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43816 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43817 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43819 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43820 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43821 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43822 | GIR_RootConstrainSelectedInstOperands, |
| 43823 | // GIR_Coverage, 3421, |
| 43824 | GIR_EraseRootFromParent_Done, |
| 43825 | // Label 2441: @120919 |
| 43826 | GIM_Reject, |
| 43827 | // Label 2437: @120920 |
| 43828 | GIM_Reject, |
| 43829 | // Label 2427: @120921 |
| 43830 | GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(121158), |
| 43831 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 43832 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 43833 | GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(120995), // Rule ID 6157 // |
| 43834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43836 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43837 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 43838 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 43839 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43840 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43841 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43842 | // (umax:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 43843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8), |
| 43844 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43845 | GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 43846 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 43847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43848 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43849 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43850 | GIR_RootConstrainSelectedInstOperands, |
| 43851 | // GIR_Coverage, 6157, |
| 43852 | GIR_EraseRootFromParent_Done, |
| 43853 | // Label 2443: @120995 |
| 43854 | GIM_Try, /*On fail goto*//*Label 2444*/ GIMT_Encode4(121058), // Rule ID 3814 // |
| 43855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43857 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43858 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 43859 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 43860 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 43861 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43862 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 43863 | // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 43864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8), |
| 43865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43866 | GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 43867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 43868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43869 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43870 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43871 | GIR_RootConstrainSelectedInstOperands, |
| 43872 | // GIR_Coverage, 3814, |
| 43873 | GIR_EraseRootFromParent_Done, |
| 43874 | // Label 2444: @121058 |
| 43875 | GIM_Try, /*On fail goto*//*Label 2445*/ GIMT_Encode4(121098), // Rule ID 1227 // |
| 43876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43878 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43879 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43880 | // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 43881 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv16i8), |
| 43882 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43883 | GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43884 | GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43886 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43887 | GIR_RootConstrainSelectedInstOperands, |
| 43888 | // GIR_Coverage, 1227, |
| 43889 | GIR_EraseRootFromParent_Done, |
| 43890 | // Label 2445: @121098 |
| 43891 | GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(121157), // Rule ID 3418 // |
| 43892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43893 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43894 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43895 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43896 | // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 43897 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43898 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43899 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 43900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu8), |
| 43901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43902 | GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43903 | GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43905 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43906 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43907 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43908 | GIR_RootConstrainSelectedInstOperands, |
| 43909 | // GIR_Coverage, 3418, |
| 43910 | GIR_EraseRootFromParent_Done, |
| 43911 | // Label 2446: @121157 |
| 43912 | GIM_Reject, |
| 43913 | // Label 2442: @121158 |
| 43914 | GIM_Reject, |
| 43915 | // Label 2428: @121159 |
| 43916 | GIM_Reject, |
| 43917 | // Label 56: @121160 |
| 43918 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2453*/ GIMT_Encode4(121624), |
| 43919 | /*GILLT_v2s32*//*Label 2447*/ GIMT_Encode4(121219), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43920 | /*GILLT_v4s16*//*Label 2448*/ GIMT_Encode4(121257), |
| 43921 | /*GILLT_v4s32*//*Label 2449*/ GIMT_Encode4(121295), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43922 | /*GILLT_v8s8*//*Label 2450*/ GIMT_Encode4(121392), |
| 43923 | /*GILLT_v8s16*//*Label 2451*/ GIMT_Encode4(121430), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43924 | /*GILLT_v16s8*//*Label 2452*/ GIMT_Encode4(121527), |
| 43925 | // Label 2447: @121219 |
| 43926 | GIM_Try, /*On fail goto*//*Label 2454*/ GIMT_Encode4(121256), // Rule ID 1529 // |
| 43927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43928 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43930 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43931 | // (abs:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 43932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv2i32), |
| 43933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43934 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 43935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43936 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43937 | GIR_RootConstrainSelectedInstOperands, |
| 43938 | // GIR_Coverage, 1529, |
| 43939 | GIR_EraseRootFromParent_Done, |
| 43940 | // Label 2454: @121256 |
| 43941 | GIM_Reject, |
| 43942 | // Label 2448: @121257 |
| 43943 | GIM_Try, /*On fail goto*//*Label 2455*/ GIMT_Encode4(121294), // Rule ID 1528 // |
| 43944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43945 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43947 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43948 | // (abs:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 43949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i16), |
| 43950 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43951 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 43952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43953 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43954 | GIR_RootConstrainSelectedInstOperands, |
| 43955 | // GIR_Coverage, 1528, |
| 43956 | GIR_EraseRootFromParent_Done, |
| 43957 | // Label 2455: @121294 |
| 43958 | GIM_Reject, |
| 43959 | // Label 2449: @121295 |
| 43960 | GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(121391), |
| 43961 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43962 | GIM_Try, /*On fail goto*//*Label 2457*/ GIMT_Encode4(121337), // Rule ID 1532 // |
| 43963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43964 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43965 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43966 | // (abs:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 43967 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i32), |
| 43968 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43969 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 43970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43971 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43972 | GIR_RootConstrainSelectedInstOperands, |
| 43973 | // GIR_Coverage, 1532, |
| 43974 | GIR_EraseRootFromParent_Done, |
| 43975 | // Label 2457: @121337 |
| 43976 | GIM_Try, /*On fail goto*//*Label 2458*/ GIMT_Encode4(121390), // Rule ID 3787 // |
| 43977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43979 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43980 | // (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v) => (MVE_VABSs32:{ *:[v4i32] } ?:{ *:[v4i32] }:$v) |
| 43981 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43982 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43983 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 43984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs32), |
| 43985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43986 | GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 43987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43988 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43989 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43990 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43991 | GIR_RootConstrainSelectedInstOperands, |
| 43992 | // GIR_Coverage, 3787, |
| 43993 | GIR_EraseRootFromParent_Done, |
| 43994 | // Label 2458: @121390 |
| 43995 | GIM_Reject, |
| 43996 | // Label 2456: @121391 |
| 43997 | GIM_Reject, |
| 43998 | // Label 2450: @121392 |
| 43999 | GIM_Try, /*On fail goto*//*Label 2459*/ GIMT_Encode4(121429), // Rule ID 1527 // |
| 44000 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44001 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44003 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44004 | // (abs:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 44005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i8), |
| 44006 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44007 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44009 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44010 | GIR_RootConstrainSelectedInstOperands, |
| 44011 | // GIR_Coverage, 1527, |
| 44012 | GIR_EraseRootFromParent_Done, |
| 44013 | // Label 2459: @121429 |
| 44014 | GIM_Reject, |
| 44015 | // Label 2451: @121430 |
| 44016 | GIM_Try, /*On fail goto*//*Label 2460*/ GIMT_Encode4(121526), |
| 44017 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44018 | GIM_Try, /*On fail goto*//*Label 2461*/ GIMT_Encode4(121472), // Rule ID 1531 // |
| 44019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44021 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44022 | // (abs:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 44023 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i16), |
| 44024 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44025 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44027 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44028 | GIR_RootConstrainSelectedInstOperands, |
| 44029 | // GIR_Coverage, 1531, |
| 44030 | GIR_EraseRootFromParent_Done, |
| 44031 | // Label 2461: @121472 |
| 44032 | GIM_Try, /*On fail goto*//*Label 2462*/ GIMT_Encode4(121525), // Rule ID 3781 // |
| 44033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44035 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44036 | // (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v) => (MVE_VABSs16:{ *:[v8i16] } ?:{ *:[v8i16] }:$v) |
| 44037 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44038 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44039 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 44040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs16), |
| 44041 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44042 | GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 44043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44044 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44045 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44046 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44047 | GIR_RootConstrainSelectedInstOperands, |
| 44048 | // GIR_Coverage, 3781, |
| 44049 | GIR_EraseRootFromParent_Done, |
| 44050 | // Label 2462: @121525 |
| 44051 | GIM_Reject, |
| 44052 | // Label 2460: @121526 |
| 44053 | GIM_Reject, |
| 44054 | // Label 2452: @121527 |
| 44055 | GIM_Try, /*On fail goto*//*Label 2463*/ GIMT_Encode4(121623), |
| 44056 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44057 | GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(121569), // Rule ID 1530 // |
| 44058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44059 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44060 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44061 | // (abs:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 44062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv16i8), |
| 44063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44064 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44065 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44066 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44067 | GIR_RootConstrainSelectedInstOperands, |
| 44068 | // GIR_Coverage, 1530, |
| 44069 | GIR_EraseRootFromParent_Done, |
| 44070 | // Label 2464: @121569 |
| 44071 | GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(121622), // Rule ID 3775 // |
| 44072 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44073 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44074 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44075 | // (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v) => (MVE_VABSs8:{ *:[v16i8] } ?:{ *:[v16i8] }:$v) |
| 44076 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44077 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44078 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 44079 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs8), |
| 44080 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44081 | GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 44082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44083 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44084 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44085 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44086 | GIR_RootConstrainSelectedInstOperands, |
| 44087 | // GIR_Coverage, 3775, |
| 44088 | GIR_EraseRootFromParent_Done, |
| 44089 | // Label 2465: @121622 |
| 44090 | GIM_Reject, |
| 44091 | // Label 2463: @121623 |
| 44092 | GIM_Reject, |
| 44093 | // Label 2453: @121624 |
| 44094 | GIM_Reject, |
| 44095 | // Label 57: @121625 |
| 44096 | GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(121697), |
| 44097 | GIM_CheckIsMBB, /*MI*/0, /*Op*/0, |
| 44098 | GIM_Try, /*On fail goto*//*Label 2467*/ GIMT_Encode4(121648), // Rule ID 32 // |
| 44099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 44100 | // (br (bb:{ *:[Other] }):$target) => (B (bb:{ *:[Other] }):$target) |
| 44101 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::B), |
| 44102 | GIR_RootConstrainSelectedInstOperands, |
| 44103 | // GIR_Coverage, 32, |
| 44104 | GIR_Done, |
| 44105 | // Label 2467: @121648 |
| 44106 | GIM_Try, /*On fail goto*//*Label 2468*/ GIMT_Encode4(121672), // Rule ID 290 // |
| 44107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 44108 | // (br (bb:{ *:[Other] }):$target) => (tB (bb:{ *:[Other] }):$target) |
| 44109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tB), |
| 44110 | GIR_RootToRootCopy, /*OpIdx*/0, // target |
| 44111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44112 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44113 | GIR_RootConstrainSelectedInstOperands, |
| 44114 | // GIR_Coverage, 290, |
| 44115 | GIR_EraseRootFromParent_Done, |
| 44116 | // Label 2468: @121672 |
| 44117 | GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(121696), // Rule ID 594 // |
| 44118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), |
| 44119 | // (br (bb:{ *:[Other] }):$target) => (t2B (bb:{ *:[Other] }):$target) |
| 44120 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2B), |
| 44121 | GIR_RootToRootCopy, /*OpIdx*/0, // target |
| 44122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44123 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44124 | GIR_RootConstrainSelectedInstOperands, |
| 44125 | // GIR_Coverage, 594, |
| 44126 | GIR_EraseRootFromParent_Done, |
| 44127 | // Label 2469: @121696 |
| 44128 | GIM_Reject, |
| 44129 | // Label 2466: @121697 |
| 44130 | GIM_Reject, |
| 44131 | // Label 58: @121698 |
| 44132 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(16), /*)*//*default:*//*Label 2474*/ GIMT_Encode4(121997), |
| 44133 | /*GILLT_v4s16*//*Label 2470*/ GIMT_Encode4(121745), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44134 | /*GILLT_v8s8*//*Label 2471*/ GIMT_Encode4(121808), |
| 44135 | /*GILLT_v8s16*//*Label 2472*/ GIMT_Encode4(121871), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44136 | /*GILLT_v16s8*//*Label 2473*/ GIMT_Encode4(121934), |
| 44137 | // Label 2470: @121745 |
| 44138 | GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(121807), // Rule ID 1591 // |
| 44139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44140 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44141 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44142 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44143 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44144 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44145 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44146 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 44147 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 44148 | // MIs[1] Operand 1 |
| 44149 | // No operand predicates |
| 44150 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44151 | // (vector_insert:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) |
| 44152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi16), |
| 44153 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V] |
| 44154 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 44155 | GIR_RootToRootCopy, /*OpIdx*/2, // R |
| 44156 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 44157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44158 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44159 | GIR_RootConstrainSelectedInstOperands, |
| 44160 | // GIR_Coverage, 1591, |
| 44161 | GIR_EraseRootFromParent_Done, |
| 44162 | // Label 2475: @121807 |
| 44163 | GIM_Reject, |
| 44164 | // Label 2471: @121808 |
| 44165 | GIM_Try, /*On fail goto*//*Label 2476*/ GIMT_Encode4(121870), // Rule ID 1590 // |
| 44166 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44167 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44168 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44169 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44170 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44171 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44172 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44173 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 44174 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 44175 | // MIs[1] Operand 1 |
| 44176 | // No operand predicates |
| 44177 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44178 | // (vector_insert:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) |
| 44179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi8), |
| 44180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V] |
| 44181 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 44182 | GIR_RootToRootCopy, /*OpIdx*/2, // R |
| 44183 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 44184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44185 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44186 | GIR_RootConstrainSelectedInstOperands, |
| 44187 | // GIR_Coverage, 1590, |
| 44188 | GIR_EraseRootFromParent_Done, |
| 44189 | // Label 2476: @121870 |
| 44190 | GIM_Reject, |
| 44191 | // Label 2472: @121871 |
| 44192 | GIM_Try, /*On fail goto*//*Label 2477*/ GIMT_Encode4(121933), // Rule ID 3533 // |
| 44193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44194 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44195 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44196 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44197 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44198 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44199 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 44200 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 44201 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 44202 | // MIs[1] Operand 1 |
| 44203 | // No operand predicates |
| 44204 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44205 | // (vector_insert:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) |
| 44206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_16), |
| 44207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44208 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 44209 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 44210 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 44211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44212 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44213 | GIR_RootConstrainSelectedInstOperands, |
| 44214 | // GIR_Coverage, 3533, |
| 44215 | GIR_EraseRootFromParent_Done, |
| 44216 | // Label 2477: @121933 |
| 44217 | GIM_Reject, |
| 44218 | // Label 2473: @121934 |
| 44219 | GIM_Try, /*On fail goto*//*Label 2478*/ GIMT_Encode4(121996), // Rule ID 3532 // |
| 44220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44221 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44222 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44223 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44225 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44226 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 44227 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 44228 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 44229 | // MIs[1] Operand 1 |
| 44230 | // No operand predicates |
| 44231 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44232 | // (vector_insert:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) |
| 44233 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_8), |
| 44234 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44235 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 44236 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 44237 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 44238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44239 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44240 | GIR_RootConstrainSelectedInstOperands, |
| 44241 | // GIR_Coverage, 3532, |
| 44242 | GIR_EraseRootFromParent_Done, |
| 44243 | // Label 2478: @121996 |
| 44244 | GIM_Reject, |
| 44245 | // Label 2474: @121997 |
| 44246 | GIM_Reject, |
| 44247 | // Label 59: @121998 |
| 44248 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 2481*/ GIMT_Encode4(122152), |
| 44249 | /*GILLT_s16*//*Label 2479*/ GIMT_Encode4(122017), |
| 44250 | /*GILLT_s32*//*Label 2480*/ GIMT_Encode4(122098), |
| 44251 | // Label 2479: @122017 |
| 44252 | GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(122097), // Rule ID 2634 // |
| 44253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON), |
| 44254 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44255 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44256 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44257 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44258 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44259 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 44260 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm_odd), |
| 44261 | // MIs[1] Operand 1 |
| 44262 | // No operand predicates |
| 44263 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44264 | // (extractelt:{ *:[bf16] } DPR:{ *:[v4bf16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm_odd>>:$lane) => (COPY_TO_REGCLASS:{ *:[bf16] } (VGETLNu16:{ *:[i32] } DPR:{ *:[v4bf16] }:$src, (imm:{ *:[i32] }):$lane), HPR:{ *:[i32] }) |
| 44265 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44266 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VGETLNu16), |
| 44267 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44268 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 44269 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // lane |
| 44270 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44271 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44272 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 44274 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 44275 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44276 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 44277 | // GIR_Coverage, 2634, |
| 44278 | GIR_EraseRootFromParent_Done, |
| 44279 | // Label 2482: @122097 |
| 44280 | GIM_Reject, |
| 44281 | // Label 2480: @122098 |
| 44282 | GIM_Try, /*On fail goto*//*Label 2483*/ GIMT_Encode4(122151), // Rule ID 1589 // |
| 44283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs_HasFastVGETLNi32), |
| 44284 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44285 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44286 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44287 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44288 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44289 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 44290 | // MIs[1] Operand 1 |
| 44291 | // No operand predicates |
| 44292 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44293 | // (extractelt:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) => (VGETLNi32:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) |
| 44294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VGETLNi32), |
| 44295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[R] |
| 44296 | GIR_RootToRootCopy, /*OpIdx*/1, // V |
| 44297 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 44298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44299 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44300 | GIR_RootConstrainSelectedInstOperands, |
| 44301 | // GIR_Coverage, 1589, |
| 44302 | GIR_EraseRootFromParent_Done, |
| 44303 | // Label 2483: @122151 |
| 44304 | GIM_Reject, |
| 44305 | // Label 2481: @122152 |
| 44306 | GIM_Reject, |
| 44307 | // Label 60: @122153 |
| 44308 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2491*/ GIMT_Encode4(122707), |
| 44309 | /*GILLT_s32*//*Label 2484*/ GIMT_Encode4(122224), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44310 | /*GILLT_v2s32*//*Label 2485*/ GIMT_Encode4(122302), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44311 | /*GILLT_v4s16*//*Label 2486*/ GIMT_Encode4(122340), |
| 44312 | /*GILLT_v4s32*//*Label 2487*/ GIMT_Encode4(122378), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44313 | /*GILLT_v8s8*//*Label 2488*/ GIMT_Encode4(122475), |
| 44314 | /*GILLT_v8s16*//*Label 2489*/ GIMT_Encode4(122513), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44315 | /*GILLT_v16s8*//*Label 2490*/ GIMT_Encode4(122610), |
| 44316 | // Label 2484: @122224 |
| 44317 | GIM_Try, /*On fail goto*//*Label 2492*/ GIMT_Encode4(122301), |
| 44318 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44319 | GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(122266), // Rule ID 197 // |
| 44320 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsARM), |
| 44321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44322 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44323 | // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 44324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLZ), |
| 44325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 44326 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 44327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44328 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44329 | GIR_RootConstrainSelectedInstOperands, |
| 44330 | // GIR_Coverage, 197, |
| 44331 | GIR_EraseRootFromParent_Done, |
| 44332 | // Label 2493: @122266 |
| 44333 | GIM_Try, /*On fail goto*//*Label 2494*/ GIMT_Encode4(122300), // Rule ID 542 // |
| 44334 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 44335 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 44336 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 44337 | // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 44338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLZ), |
| 44339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 44340 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 44341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44342 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44343 | GIR_RootConstrainSelectedInstOperands, |
| 44344 | // GIR_Coverage, 542, |
| 44345 | GIR_EraseRootFromParent_Done, |
| 44346 | // Label 2494: @122300 |
| 44347 | GIM_Reject, |
| 44348 | // Label 2492: @122301 |
| 44349 | GIM_Reject, |
| 44350 | // Label 2485: @122302 |
| 44351 | GIM_Try, /*On fail goto*//*Label 2495*/ GIMT_Encode4(122339), // Rule ID 1567 // |
| 44352 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44353 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44354 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44355 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44356 | // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 44357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv2i32), |
| 44358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44359 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44361 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44362 | GIR_RootConstrainSelectedInstOperands, |
| 44363 | // GIR_Coverage, 1567, |
| 44364 | GIR_EraseRootFromParent_Done, |
| 44365 | // Label 2495: @122339 |
| 44366 | GIM_Reject, |
| 44367 | // Label 2486: @122340 |
| 44368 | GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(122377), // Rule ID 1566 // |
| 44369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44370 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44371 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44372 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44373 | // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 44374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i16), |
| 44375 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44376 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44377 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44378 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44379 | GIR_RootConstrainSelectedInstOperands, |
| 44380 | // GIR_Coverage, 1566, |
| 44381 | GIR_EraseRootFromParent_Done, |
| 44382 | // Label 2496: @122377 |
| 44383 | GIM_Reject, |
| 44384 | // Label 2487: @122378 |
| 44385 | GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(122474), |
| 44386 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44387 | GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(122420), // Rule ID 1570 // |
| 44388 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44389 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44390 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44391 | // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 44392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i32), |
| 44393 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44394 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44396 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44397 | GIR_RootConstrainSelectedInstOperands, |
| 44398 | // GIR_Coverage, 1570, |
| 44399 | GIR_EraseRootFromParent_Done, |
| 44400 | // Label 2498: @122420 |
| 44401 | GIM_Try, /*On fail goto*//*Label 2499*/ GIMT_Encode4(122473), // Rule ID 3773 // |
| 44402 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44404 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44405 | // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) |
| 44406 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44407 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44408 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 44409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs32), |
| 44410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44411 | GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 44412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44413 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44414 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44415 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44416 | GIR_RootConstrainSelectedInstOperands, |
| 44417 | // GIR_Coverage, 3773, |
| 44418 | GIR_EraseRootFromParent_Done, |
| 44419 | // Label 2499: @122473 |
| 44420 | GIM_Reject, |
| 44421 | // Label 2497: @122474 |
| 44422 | GIM_Reject, |
| 44423 | // Label 2488: @122475 |
| 44424 | GIM_Try, /*On fail goto*//*Label 2500*/ GIMT_Encode4(122512), // Rule ID 1565 // |
| 44425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44426 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44427 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44428 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44429 | // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 44430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i8), |
| 44431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44432 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44434 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44435 | GIR_RootConstrainSelectedInstOperands, |
| 44436 | // GIR_Coverage, 1565, |
| 44437 | GIR_EraseRootFromParent_Done, |
| 44438 | // Label 2500: @122512 |
| 44439 | GIM_Reject, |
| 44440 | // Label 2489: @122513 |
| 44441 | GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(122609), |
| 44442 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44443 | GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(122555), // Rule ID 1569 // |
| 44444 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44446 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44447 | // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 44448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i16), |
| 44449 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44450 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44452 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44453 | GIR_RootConstrainSelectedInstOperands, |
| 44454 | // GIR_Coverage, 1569, |
| 44455 | GIR_EraseRootFromParent_Done, |
| 44456 | // Label 2502: @122555 |
| 44457 | GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(122608), // Rule ID 3771 // |
| 44458 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44459 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44460 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44461 | // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) |
| 44462 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44463 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44464 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 44465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs16), |
| 44466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44467 | GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 44468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44469 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44470 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44471 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44472 | GIR_RootConstrainSelectedInstOperands, |
| 44473 | // GIR_Coverage, 3771, |
| 44474 | GIR_EraseRootFromParent_Done, |
| 44475 | // Label 2503: @122608 |
| 44476 | GIM_Reject, |
| 44477 | // Label 2501: @122609 |
| 44478 | GIM_Reject, |
| 44479 | // Label 2490: @122610 |
| 44480 | GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(122706), |
| 44481 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44482 | GIM_Try, /*On fail goto*//*Label 2505*/ GIMT_Encode4(122652), // Rule ID 1568 // |
| 44483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44485 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44486 | // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 44487 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv16i8), |
| 44488 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44489 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44491 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44492 | GIR_RootConstrainSelectedInstOperands, |
| 44493 | // GIR_Coverage, 1568, |
| 44494 | GIR_EraseRootFromParent_Done, |
| 44495 | // Label 2505: @122652 |
| 44496 | GIM_Try, /*On fail goto*//*Label 2506*/ GIMT_Encode4(122705), // Rule ID 3769 // |
| 44497 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44499 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44500 | // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) |
| 44501 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44502 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44503 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 44504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs8), |
| 44505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44506 | GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 44507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44508 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44509 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44510 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44511 | GIR_RootConstrainSelectedInstOperands, |
| 44512 | // GIR_Coverage, 3769, |
| 44513 | GIR_EraseRootFromParent_Done, |
| 44514 | // Label 2506: @122705 |
| 44515 | GIM_Reject, |
| 44516 | // Label 2504: @122706 |
| 44517 | GIM_Reject, |
| 44518 | // Label 2491: @122707 |
| 44519 | GIM_Reject, |
| 44520 | // Label 61: @122708 |
| 44521 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(16), /*)*//*default:*//*Label 2509*/ GIMT_Encode4(122815), |
| 44522 | /*GILLT_v8s8*//*Label 2507*/ GIMT_Encode4(122739), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44523 | /*GILLT_v16s8*//*Label 2508*/ GIMT_Encode4(122777), |
| 44524 | // Label 2507: @122739 |
| 44525 | GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(122776), // Rule ID 1571 // |
| 44526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44527 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44528 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44529 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44530 | // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 44531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTd), |
| 44532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44533 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44535 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44536 | GIR_RootConstrainSelectedInstOperands, |
| 44537 | // GIR_Coverage, 1571, |
| 44538 | GIR_EraseRootFromParent_Done, |
| 44539 | // Label 2510: @122776 |
| 44540 | GIM_Reject, |
| 44541 | // Label 2508: @122777 |
| 44542 | GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(122814), // Rule ID 1572 // |
| 44543 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44544 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44545 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44546 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44547 | // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 44548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTq), |
| 44549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44550 | GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44552 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44553 | GIR_RootConstrainSelectedInstOperands, |
| 44554 | // GIR_Coverage, 1572, |
| 44555 | GIR_EraseRootFromParent_Done, |
| 44556 | // Label 2511: @122814 |
| 44557 | GIM_Reject, |
| 44558 | // Label 2509: @122815 |
| 44559 | GIM_Reject, |
| 44560 | // Label 62: @122816 |
| 44561 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2515*/ GIMT_Encode4(123101), |
| 44562 | /*GILLT_s32*//*Label 2512*/ GIMT_Encode4(122875), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44563 | /*GILLT_v4s32*//*Label 2513*/ GIMT_Encode4(122987), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44564 | /*GILLT_v8s16*//*Label 2514*/ GIMT_Encode4(123044), |
| 44565 | // Label 2512: @122875 |
| 44566 | GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(122986), |
| 44567 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44568 | GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(122917), // Rule ID 199 // |
| 44569 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 44570 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44571 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44572 | // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 44573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV), |
| 44574 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 44575 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 44576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44577 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44578 | GIR_RootConstrainSelectedInstOperands, |
| 44579 | // GIR_Coverage, 199, |
| 44580 | GIR_EraseRootFromParent_Done, |
| 44581 | // Label 2517: @122917 |
| 44582 | GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(122951), // Rule ID 333 // |
| 44583 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 44584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 44585 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 44586 | // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) => (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 44587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV), |
| 44588 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 44589 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 44590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44591 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44592 | GIR_RootConstrainSelectedInstOperands, |
| 44593 | // GIR_Coverage, 333, |
| 44594 | GIR_EraseRootFromParent_Done, |
| 44595 | // Label 2518: @122951 |
| 44596 | GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(122985), // Rule ID 544 // |
| 44597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 44598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 44599 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 44600 | // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 44601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV), |
| 44602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 44603 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 44604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44605 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44606 | GIR_RootConstrainSelectedInstOperands, |
| 44607 | // GIR_Coverage, 544, |
| 44608 | GIR_EraseRootFromParent_Done, |
| 44609 | // Label 2519: @122985 |
| 44610 | GIM_Reject, |
| 44611 | // Label 2516: @122986 |
| 44612 | GIM_Reject, |
| 44613 | // Label 2513: @122987 |
| 44614 | GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(123043), // Rule ID 3428 // |
| 44615 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44616 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44617 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44618 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44619 | // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) |
| 44620 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44621 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44622 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 44623 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 44624 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44625 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 44626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44627 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44628 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44629 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44630 | GIR_RootConstrainSelectedInstOperands, |
| 44631 | // GIR_Coverage, 3428, |
| 44632 | GIR_EraseRootFromParent_Done, |
| 44633 | // Label 2520: @123043 |
| 44634 | GIM_Reject, |
| 44635 | // Label 2514: @123044 |
| 44636 | GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(123100), // Rule ID 3427 // |
| 44637 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44638 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44639 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44640 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44641 | // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) |
| 44642 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44643 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44644 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 44645 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 44646 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44647 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 44648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44649 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44650 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44651 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44652 | GIR_RootConstrainSelectedInstOperands, |
| 44653 | // GIR_Coverage, 3427, |
| 44654 | GIR_EraseRootFromParent_Done, |
| 44655 | // Label 2521: @123100 |
| 44656 | GIM_Reject, |
| 44657 | // Label 2515: @123101 |
| 44658 | GIM_Reject, |
| 44659 | // Label 63: @123102 |
| 44660 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2526*/ GIMT_Encode4(123527), |
| 44661 | /*GILLT_s32*//*Label 2522*/ GIMT_Encode4(123173), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44662 | /*GILLT_v4s32*//*Label 2523*/ GIMT_Encode4(123251), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44663 | /*GILLT_v8s16*//*Label 2524*/ GIMT_Encode4(123343), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44664 | /*GILLT_v16s8*//*Label 2525*/ GIMT_Encode4(123435), |
| 44665 | // Label 2522: @123173 |
| 44666 | GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(123250), |
| 44667 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44668 | GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(123215), // Rule ID 198 // |
| 44669 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), |
| 44670 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44671 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44672 | // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 44673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RBIT), |
| 44674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 44675 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 44676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44677 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44678 | GIR_RootConstrainSelectedInstOperands, |
| 44679 | // GIR_Coverage, 198, |
| 44680 | GIR_EraseRootFromParent_Done, |
| 44681 | // Label 2528: @123215 |
| 44682 | GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(123249), // Rule ID 543 // |
| 44683 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 44684 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 44685 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 44686 | // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 44687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RBIT), |
| 44688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 44689 | GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 44690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44691 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44692 | GIR_RootConstrainSelectedInstOperands, |
| 44693 | // GIR_Coverage, 543, |
| 44694 | GIR_EraseRootFromParent_Done, |
| 44695 | // Label 2529: @123249 |
| 44696 | GIM_Reject, |
| 44697 | // Label 2527: @123250 |
| 44698 | GIM_Reject, |
| 44699 | // Label 2523: @123251 |
| 44700 | GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(123342), // Rule ID 4873 // |
| 44701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44702 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44703 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44704 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44705 | // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] })) |
| 44706 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44707 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 44708 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44709 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/1, |
| 44710 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 44711 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44712 | GIR_AddImm8, /*InsnID*/1, /*Imm*/32, |
| 44713 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44714 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44715 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44716 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 44718 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44719 | GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 44720 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44722 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44723 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44724 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 44725 | GIR_RootConstrainSelectedInstOperands, |
| 44726 | // GIR_Coverage, 4873, |
| 44727 | GIR_EraseRootFromParent_Done, |
| 44728 | // Label 2530: @123342 |
| 44729 | GIM_Reject, |
| 44730 | // Label 2524: @123343 |
| 44731 | GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(123434), // Rule ID 4874 // |
| 44732 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44733 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44735 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44736 | // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] })) |
| 44737 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44738 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 44739 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44740 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/1, |
| 44741 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 44742 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44743 | GIR_AddImm8, /*InsnID*/1, /*Imm*/16, |
| 44744 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44745 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44746 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44747 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 44749 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44750 | GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 44751 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44753 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44754 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44755 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 44756 | GIR_RootConstrainSelectedInstOperands, |
| 44757 | // GIR_Coverage, 4874, |
| 44758 | GIR_EraseRootFromParent_Done, |
| 44759 | // Label 2531: @123434 |
| 44760 | GIM_Reject, |
| 44761 | // Label 2525: @123435 |
| 44762 | GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(123526), // Rule ID 4872 // |
| 44763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44764 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44765 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44766 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44767 | // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] })) |
| 44768 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 44769 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 44770 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44771 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/1, |
| 44772 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 44773 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44774 | GIR_AddImm8, /*InsnID*/1, /*Imm*/8, |
| 44775 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 44776 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44777 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44778 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 44779 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8), |
| 44780 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44781 | GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 44782 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44784 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44785 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44786 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 44787 | GIR_RootConstrainSelectedInstOperands, |
| 44788 | // GIR_Coverage, 4872, |
| 44789 | GIR_EraseRootFromParent_Done, |
| 44790 | // Label 2532: @123526 |
| 44791 | GIM_Reject, |
| 44792 | // Label 2526: @123527 |
| 44793 | GIM_Reject, |
| 44794 | // Label 64: @123528 |
| 44795 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2538*/ GIMT_Encode4(123786), |
| 44796 | /*GILLT_s16*//*Label 2533*/ GIMT_Encode4(123591), |
| 44797 | /*GILLT_s32*//*Label 2534*/ GIMT_Encode4(123618), |
| 44798 | /*GILLT_s64*//*Label 2535*/ GIMT_Encode4(123645), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44799 | /*GILLT_v4s32*//*Label 2536*/ GIMT_Encode4(123672), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44800 | /*GILLT_v8s16*//*Label 2537*/ GIMT_Encode4(123729), |
| 44801 | // Label 2533: @123591 |
| 44802 | GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(123617), // Rule ID 697 // |
| 44803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 44804 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 44805 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44806 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44807 | // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 44808 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPH), |
| 44809 | GIR_RootConstrainSelectedInstOperands, |
| 44810 | // GIR_Coverage, 697, |
| 44811 | GIR_Done, |
| 44812 | // Label 2539: @123617 |
| 44813 | GIM_Reject, |
| 44814 | // Label 2534: @123618 |
| 44815 | GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(123644), // Rule ID 698 // |
| 44816 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 44817 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44818 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44819 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44820 | // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 44821 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPS), |
| 44822 | GIR_RootConstrainSelectedInstOperands, |
| 44823 | // GIR_Coverage, 698, |
| 44824 | GIR_Done, |
| 44825 | // Label 2540: @123644 |
| 44826 | GIM_Reject, |
| 44827 | // Label 2535: @123645 |
| 44828 | GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(123671), // Rule ID 699 // |
| 44829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 44830 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 44831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44832 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44833 | // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 44834 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPD), |
| 44835 | GIR_RootConstrainSelectedInstOperands, |
| 44836 | // GIR_Coverage, 699, |
| 44837 | GIR_Done, |
| 44838 | // Label 2541: @123671 |
| 44839 | GIM_Reject, |
| 44840 | // Label 2536: @123672 |
| 44841 | GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(123728), // Rule ID 4101 // |
| 44842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 44843 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44844 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44845 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44846 | // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 44847 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44848 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44849 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 44850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P), |
| 44851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44852 | GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 44853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44854 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44855 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44856 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44857 | GIR_RootConstrainSelectedInstOperands, |
| 44858 | // GIR_Coverage, 4101, |
| 44859 | GIR_EraseRootFromParent_Done, |
| 44860 | // Label 2542: @123728 |
| 44861 | GIM_Reject, |
| 44862 | // Label 2537: @123729 |
| 44863 | GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(123785), // Rule ID 4089 // |
| 44864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 44865 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44867 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44868 | // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 44869 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44870 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44871 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 44872 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P), |
| 44873 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44874 | GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 44875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44876 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44877 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44878 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44879 | GIR_RootConstrainSelectedInstOperands, |
| 44880 | // GIR_Coverage, 4089, |
| 44881 | GIR_EraseRootFromParent_Done, |
| 44882 | // Label 2543: @123785 |
| 44883 | GIM_Reject, |
| 44884 | // Label 2538: @123786 |
| 44885 | GIM_Reject, |
| 44886 | // Label 65: @123787 |
| 44887 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2547*/ GIMT_Encode4(123924), |
| 44888 | /*GILLT_s16*//*Label 2544*/ GIMT_Encode4(123810), |
| 44889 | /*GILLT_s32*//*Label 2545*/ GIMT_Encode4(123848), |
| 44890 | /*GILLT_s64*//*Label 2546*/ GIMT_Encode4(123886), |
| 44891 | // Label 2544: @123810 |
| 44892 | GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(123847), // Rule ID 705 // |
| 44893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 44894 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 44895 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44896 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44897 | // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 44898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH), |
| 44899 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 44900 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 44901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44902 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44903 | GIR_RootConstrainSelectedInstOperands, |
| 44904 | // GIR_Coverage, 705, |
| 44905 | GIR_EraseRootFromParent_Done, |
| 44906 | // Label 2548: @123847 |
| 44907 | GIM_Reject, |
| 44908 | // Label 2545: @123848 |
| 44909 | GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(123885), // Rule ID 704 // |
| 44910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2), |
| 44911 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44912 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44913 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44914 | // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 44915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS), |
| 44916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 44917 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 44918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44919 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44920 | GIR_RootConstrainSelectedInstOperands, |
| 44921 | // GIR_Coverage, 704, |
| 44922 | GIR_EraseRootFromParent_Done, |
| 44923 | // Label 2549: @123885 |
| 44924 | GIM_Reject, |
| 44925 | // Label 2546: @123886 |
| 44926 | GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(123923), // Rule ID 703 // |
| 44927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 44928 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 44929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44930 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44931 | // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 44932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD), |
| 44933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 44934 | GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 44935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44936 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44937 | GIR_RootConstrainSelectedInstOperands, |
| 44938 | // GIR_Coverage, 703, |
| 44939 | GIR_EraseRootFromParent_Done, |
| 44940 | // Label 2550: @123923 |
| 44941 | GIM_Reject, |
| 44942 | // Label 2547: @123924 |
| 44943 | GIM_Reject, |
| 44944 | // Label 66: @123925 |
| 44945 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2556*/ GIMT_Encode4(124183), |
| 44946 | /*GILLT_s16*//*Label 2551*/ GIMT_Encode4(123988), |
| 44947 | /*GILLT_s32*//*Label 2552*/ GIMT_Encode4(124015), |
| 44948 | /*GILLT_s64*//*Label 2553*/ GIMT_Encode4(124042), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44949 | /*GILLT_v4s32*//*Label 2554*/ GIMT_Encode4(124069), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44950 | /*GILLT_v8s16*//*Label 2555*/ GIMT_Encode4(124126), |
| 44951 | // Label 2551: @123988 |
| 44952 | GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(124014), // Rule ID 700 // |
| 44953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 44954 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 44955 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44956 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 44957 | // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 44958 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMH), |
| 44959 | GIR_RootConstrainSelectedInstOperands, |
| 44960 | // GIR_Coverage, 700, |
| 44961 | GIR_Done, |
| 44962 | // Label 2557: @124014 |
| 44963 | GIM_Reject, |
| 44964 | // Label 2552: @124015 |
| 44965 | GIM_Try, /*On fail goto*//*Label 2558*/ GIMT_Encode4(124041), // Rule ID 701 // |
| 44966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 44967 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 44968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44969 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 44970 | // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 44971 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMS), |
| 44972 | GIR_RootConstrainSelectedInstOperands, |
| 44973 | // GIR_Coverage, 701, |
| 44974 | GIR_Done, |
| 44975 | // Label 2558: @124041 |
| 44976 | GIM_Reject, |
| 44977 | // Label 2553: @124042 |
| 44978 | GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(124068), // Rule ID 702 // |
| 44979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 44980 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 44981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44982 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44983 | // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 44984 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMD), |
| 44985 | GIR_RootConstrainSelectedInstOperands, |
| 44986 | // GIR_Coverage, 702, |
| 44987 | GIR_Done, |
| 44988 | // Label 2559: @124068 |
| 44989 | GIM_Reject, |
| 44990 | // Label 2554: @124069 |
| 44991 | GIM_Try, /*On fail goto*//*Label 2560*/ GIMT_Encode4(124125), // Rule ID 4099 // |
| 44992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 44993 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44995 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44996 | // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 44997 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44998 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44999 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 45000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M), |
| 45001 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45002 | GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45004 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45005 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45006 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45007 | GIR_RootConstrainSelectedInstOperands, |
| 45008 | // GIR_Coverage, 4099, |
| 45009 | GIR_EraseRootFromParent_Done, |
| 45010 | // Label 2560: @124125 |
| 45011 | GIM_Reject, |
| 45012 | // Label 2555: @124126 |
| 45013 | GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(124182), // Rule ID 4087 // |
| 45014 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45015 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45017 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45018 | // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 45019 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45020 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45021 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 45022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M), |
| 45023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45024 | GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45026 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45027 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45028 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45029 | GIR_RootConstrainSelectedInstOperands, |
| 45030 | // GIR_Coverage, 4087, |
| 45031 | GIR_EraseRootFromParent_Done, |
| 45032 | // Label 2561: @124182 |
| 45033 | GIM_Reject, |
| 45034 | // Label 2556: @124183 |
| 45035 | GIM_Reject, |
| 45036 | // Label 67: @124184 |
| 45037 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2567*/ GIMT_Encode4(124475), |
| 45038 | /*GILLT_s16*//*Label 2562*/ GIMT_Encode4(124247), |
| 45039 | /*GILLT_s32*//*Label 2563*/ GIMT_Encode4(124285), |
| 45040 | /*GILLT_s64*//*Label 2564*/ GIMT_Encode4(124323), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45041 | /*GILLT_v4s32*//*Label 2565*/ GIMT_Encode4(124361), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45042 | /*GILLT_v8s16*//*Label 2566*/ GIMT_Encode4(124418), |
| 45043 | // Label 2562: @124247 |
| 45044 | GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(124284), // Rule ID 688 // |
| 45045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 45046 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 45047 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45048 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45049 | // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 45050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXH), |
| 45051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45052 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 45053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45054 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45055 | GIR_RootConstrainSelectedInstOperands, |
| 45056 | // GIR_Coverage, 688, |
| 45057 | GIR_EraseRootFromParent_Done, |
| 45058 | // Label 2568: @124284 |
| 45059 | GIM_Reject, |
| 45060 | // Label 2563: @124285 |
| 45061 | GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(124322), // Rule ID 689 // |
| 45062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 45063 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45065 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45066 | // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 45067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXS), |
| 45068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45069 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 45070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45071 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45072 | GIR_RootConstrainSelectedInstOperands, |
| 45073 | // GIR_Coverage, 689, |
| 45074 | GIR_EraseRootFromParent_Done, |
| 45075 | // Label 2569: @124322 |
| 45076 | GIM_Reject, |
| 45077 | // Label 2564: @124323 |
| 45078 | GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(124360), // Rule ID 690 // |
| 45079 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 45080 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 45081 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45082 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45083 | // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 45084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXD), |
| 45085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 45086 | GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 45087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45088 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45089 | GIR_RootConstrainSelectedInstOperands, |
| 45090 | // GIR_Coverage, 690, |
| 45091 | GIR_EraseRootFromParent_Done, |
| 45092 | // Label 2570: @124360 |
| 45093 | GIM_Reject, |
| 45094 | // Label 2565: @124361 |
| 45095 | GIM_Try, /*On fail goto*//*Label 2571*/ GIMT_Encode4(124417), // Rule ID 4093 // |
| 45096 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45097 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45098 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45099 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45100 | // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 45101 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45102 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45103 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 45104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X), |
| 45105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45106 | GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45108 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45109 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45110 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45111 | GIR_RootConstrainSelectedInstOperands, |
| 45112 | // GIR_Coverage, 4093, |
| 45113 | GIR_EraseRootFromParent_Done, |
| 45114 | // Label 2571: @124417 |
| 45115 | GIM_Reject, |
| 45116 | // Label 2566: @124418 |
| 45117 | GIM_Try, /*On fail goto*//*Label 2572*/ GIMT_Encode4(124474), // Rule ID 4081 // |
| 45118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45119 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45121 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45122 | // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 45123 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45124 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45125 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, |
| 45126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X), |
| 45127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45128 | GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45130 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45131 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45132 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45133 | GIR_RootConstrainSelectedInstOperands, |
| 45134 | // GIR_Coverage, 4081, |
| 45135 | GIR_EraseRootFromParent_Done, |
| 45136 | // Label 2572: @124474 |
| 45137 | GIM_Reject, |
| 45138 | // Label 2567: @124475 |
| 45139 | GIM_Reject, |
| 45140 | // Label 68: @124476 |
| 45141 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2576*/ GIMT_Encode4(124613), |
| 45142 | /*GILLT_s16*//*Label 2573*/ GIMT_Encode4(124499), |
| 45143 | /*GILLT_s32*//*Label 2574*/ GIMT_Encode4(124537), |
| 45144 | /*GILLT_s64*//*Label 2575*/ GIMT_Encode4(124575), |
| 45145 | // Label 2573: @124499 |
| 45146 | GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(124536), // Rule ID 685 // |
| 45147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 45148 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 45149 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45150 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45151 | // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 45152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRH), |
| 45153 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45154 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 45155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45156 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45157 | GIR_RootConstrainSelectedInstOperands, |
| 45158 | // GIR_Coverage, 685, |
| 45159 | GIR_EraseRootFromParent_Done, |
| 45160 | // Label 2577: @124536 |
| 45161 | GIM_Reject, |
| 45162 | // Label 2574: @124537 |
| 45163 | GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(124574), // Rule ID 686 // |
| 45164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 45165 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45167 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45168 | // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 45169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRS), |
| 45170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45171 | GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 45172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45173 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45174 | GIR_RootConstrainSelectedInstOperands, |
| 45175 | // GIR_Coverage, 686, |
| 45176 | GIR_EraseRootFromParent_Done, |
| 45177 | // Label 2578: @124574 |
| 45178 | GIM_Reject, |
| 45179 | // Label 2575: @124575 |
| 45180 | GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(124612), // Rule ID 687 // |
| 45181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 45182 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 45183 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45184 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45185 | // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 45186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRD), |
| 45187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 45188 | GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 45189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45190 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45191 | GIR_RootConstrainSelectedInstOperands, |
| 45192 | // GIR_Coverage, 687, |
| 45193 | GIR_EraseRootFromParent_Done, |
| 45194 | // Label 2579: @124612 |
| 45195 | GIM_Reject, |
| 45196 | // Label 2576: @124613 |
| 45197 | GIM_Reject, |
| 45198 | // Label 69: @124614 |
| 45199 | GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(124629), // Rule ID 12 // |
| 45200 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_UseNaClTrap), |
| 45201 | // (trap) => (TRAPNaCl) |
| 45202 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::TRAPNaCl), |
| 45203 | GIR_RootConstrainSelectedInstOperands, |
| 45204 | // GIR_Coverage, 12, |
| 45205 | GIR_Done, |
| 45206 | // Label 2580: @124629 |
| 45207 | GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(124644), // Rule ID 13 // |
| 45208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNaClTrap_IsARM), |
| 45209 | // (trap) => (TRAP) |
| 45210 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::TRAP), |
| 45211 | GIR_RootConstrainSelectedInstOperands, |
| 45212 | // GIR_Coverage, 13, |
| 45213 | GIR_Done, |
| 45214 | // Label 2581: @124644 |
| 45215 | GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(124659), // Rule ID 292 // |
| 45216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb), |
| 45217 | // (trap) => (tTRAP) |
| 45218 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tTRAP), |
| 45219 | GIR_RootConstrainSelectedInstOperands, |
| 45220 | // GIR_Coverage, 292, |
| 45221 | GIR_Done, |
| 45222 | // Label 2582: @124659 |
| 45223 | GIM_Reject, |
| 45224 | // Label 70: @124660 |
| 45225 | GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(124676), // Rule ID 1862 // |
| 45226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsARM), |
| 45227 | // (debugtrap) => (BKPT 0:{ *:[i32] }) |
| 45228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BKPT), |
| 45229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45230 | GIR_RootConstrainSelectedInstOperands, |
| 45231 | // GIR_Coverage, 1862, |
| 45232 | GIR_EraseRootFromParent_Done, |
| 45233 | // Label 2583: @124676 |
| 45234 | GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(124703), // Rule ID 1863 // |
| 45235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV5T), |
| 45236 | // (debugtrap) => (UDF 254:{ *:[i32] }) |
| 45237 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF), |
| 45238 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254), |
| 45239 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45240 | GIR_RootConstrainSelectedInstOperands, |
| 45241 | // GIR_Coverage, 1863, |
| 45242 | GIR_EraseRootFromParent_Done, |
| 45243 | // Label 2584: @124703 |
| 45244 | GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(124719), // Rule ID 2036 // |
| 45245 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsThumb), |
| 45246 | // (debugtrap) => (tBKPT 0:{ *:[i32] }) |
| 45247 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBKPT), |
| 45248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45249 | GIR_RootConstrainSelectedInstOperands, |
| 45250 | // GIR_Coverage, 2036, |
| 45251 | GIR_EraseRootFromParent_Done, |
| 45252 | // Label 2585: @124719 |
| 45253 | GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(124746), // Rule ID 2037 // |
| 45254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_NoV5T), |
| 45255 | // (debugtrap) => (tUDF 254:{ *:[i32] }) |
| 45256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF), |
| 45257 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254), |
| 45258 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45259 | GIR_RootConstrainSelectedInstOperands, |
| 45260 | // GIR_Coverage, 2037, |
| 45261 | GIR_EraseRootFromParent_Done, |
| 45262 | // Label 2586: @124746 |
| 45263 | GIM_Reject, |
| 45264 | // Label 71: @124747 |
| 45265 | GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(124922), |
| 45266 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 45267 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2591*/ GIMT_Encode4(124921), |
| 45268 | /*GILLT_v4s32*//*Label 2588*/ GIMT_Encode4(124798), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45269 | /*GILLT_v8s16*//*Label 2589*/ GIMT_Encode4(124839), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45270 | /*GILLT_v16s8*//*Label 2590*/ GIMT_Encode4(124880), |
| 45271 | // Label 2588: @124798 |
| 45272 | GIM_Try, /*On fail goto*//*Label 2592*/ GIMT_Encode4(124838), // Rule ID 3184 // |
| 45273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 45275 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45276 | // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec) => (MVE_VADDVu32no_acc:{ *:[i32] } ?:{ *:[v4i32] }:$vec) |
| 45277 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32no_acc), |
| 45278 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 45279 | GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 45280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45281 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45282 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45283 | GIR_RootConstrainSelectedInstOperands, |
| 45284 | // GIR_Coverage, 3184, |
| 45285 | GIR_EraseRootFromParent_Done, |
| 45286 | // Label 2592: @124838 |
| 45287 | GIM_Reject, |
| 45288 | // Label 2589: @124839 |
| 45289 | GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(124879), // Rule ID 3174 // |
| 45290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45291 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 45292 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45293 | // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec) => (MVE_VADDVu16no_acc:{ *:[i32] } ?:{ *:[v8i16] }:$vec) |
| 45294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16no_acc), |
| 45295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 45296 | GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 45297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45298 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45299 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45300 | GIR_RootConstrainSelectedInstOperands, |
| 45301 | // GIR_Coverage, 3174, |
| 45302 | GIR_EraseRootFromParent_Done, |
| 45303 | // Label 2593: @124879 |
| 45304 | GIM_Reject, |
| 45305 | // Label 2590: @124880 |
| 45306 | GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(124920), // Rule ID 3146 // |
| 45307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45308 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 45309 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45310 | // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec) => (MVE_VADDVu8no_acc:{ *:[i32] } ?:{ *:[v16i8] }:$vec) |
| 45311 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8no_acc), |
| 45312 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 45313 | GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 45314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45315 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45316 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45317 | GIR_RootConstrainSelectedInstOperands, |
| 45318 | // GIR_Coverage, 3146, |
| 45319 | GIR_EraseRootFromParent_Done, |
| 45320 | // Label 2594: @124920 |
| 45321 | GIM_Reject, |
| 45322 | // Label 2591: @124921 |
| 45323 | GIM_Reject, |
| 45324 | // Label 2587: @124922 |
| 45325 | GIM_Reject, |
| 45326 | // Label 72: @124923 |
| 45327 | GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(125202), |
| 45328 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 45329 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2599*/ GIMT_Encode4(125201), |
| 45330 | /*GILLT_v4s32*//*Label 2596*/ GIMT_Encode4(124974), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45331 | /*GILLT_v8s16*//*Label 2597*/ GIMT_Encode4(125057), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45332 | /*GILLT_v16s8*//*Label 2598*/ GIMT_Encode4(125125), |
| 45333 | // Label 2596: @124974 |
| 45334 | GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(125056), // Rule ID 3244 // |
| 45335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45337 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45338 | // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVs32:{ *:[i32] } (t2MOVi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 45339 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45340 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45341 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45342 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(-2147483648), |
| 45343 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45344 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45345 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45346 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32), |
| 45348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 45349 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45350 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45352 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45353 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45354 | GIR_RootConstrainSelectedInstOperands, |
| 45355 | // GIR_Coverage, 3244, |
| 45356 | GIR_EraseRootFromParent_Done, |
| 45357 | // Label 2600: @125056 |
| 45358 | GIM_Reject, |
| 45359 | // Label 2597: @125057 |
| 45360 | GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(125124), // Rule ID 3243 // |
| 45361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45363 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45364 | // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVs16:{ *:[i32] } (t2MOVi32imm:{ *:[i32] } -32768:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 45365 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45366 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm), |
| 45367 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45368 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(-32768), |
| 45369 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16), |
| 45371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 45372 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45373 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45375 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45376 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45377 | GIR_RootConstrainSelectedInstOperands, |
| 45378 | // GIR_Coverage, 3243, |
| 45379 | GIR_EraseRootFromParent_Done, |
| 45380 | // Label 2601: @125124 |
| 45381 | GIM_Reject, |
| 45382 | // Label 2598: @125125 |
| 45383 | GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(125200), // Rule ID 3242 // |
| 45384 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45385 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45386 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45387 | // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVs8:{ *:[i32] } (t2MVNi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 45388 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45389 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 45390 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45391 | GIR_AddImm8, /*InsnID*/1, /*Imm*/127, |
| 45392 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45393 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45394 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45395 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8), |
| 45397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 45398 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45399 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45401 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45402 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45403 | GIR_RootConstrainSelectedInstOperands, |
| 45404 | // GIR_Coverage, 3242, |
| 45405 | GIR_EraseRootFromParent_Done, |
| 45406 | // Label 2602: @125200 |
| 45407 | GIM_Reject, |
| 45408 | // Label 2599: @125201 |
| 45409 | GIM_Reject, |
| 45410 | // Label 2595: @125202 |
| 45411 | GIM_Reject, |
| 45412 | // Label 73: @125203 |
| 45413 | GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(125491), |
| 45414 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 45415 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2607*/ GIMT_Encode4(125490), |
| 45416 | /*GILLT_v4s32*//*Label 2604*/ GIMT_Encode4(125254), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45417 | /*GILLT_v8s16*//*Label 2605*/ GIMT_Encode4(125337), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45418 | /*GILLT_v16s8*//*Label 2606*/ GIMT_Encode4(125414), |
| 45419 | // Label 2604: @125254 |
| 45420 | GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(125336), // Rule ID 3250 // |
| 45421 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45423 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45424 | // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVs32:{ *:[i32] } (t2MVNi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 45425 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45426 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 45427 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45428 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(-2147483648), |
| 45429 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45430 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45431 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45432 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32), |
| 45434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 45435 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45436 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45438 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45439 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45440 | GIR_RootConstrainSelectedInstOperands, |
| 45441 | // GIR_Coverage, 3250, |
| 45442 | GIR_EraseRootFromParent_Done, |
| 45443 | // Label 2608: @125336 |
| 45444 | GIM_Reject, |
| 45445 | // Label 2605: @125337 |
| 45446 | GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(125413), // Rule ID 3249 // |
| 45447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45448 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45449 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45450 | // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVs16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 32767:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 45451 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45452 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 45453 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45454 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767), |
| 45455 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45456 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45457 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45458 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16), |
| 45459 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 45460 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45461 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45463 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45464 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45465 | GIR_RootConstrainSelectedInstOperands, |
| 45466 | // GIR_Coverage, 3249, |
| 45467 | GIR_EraseRootFromParent_Done, |
| 45468 | // Label 2609: @125413 |
| 45469 | GIM_Reject, |
| 45470 | // Label 2606: @125414 |
| 45471 | GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(125489), // Rule ID 3248 // |
| 45472 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45473 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45474 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45475 | // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVs8:{ *:[i32] } (t2MOVi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 45476 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45477 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45478 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45479 | GIR_AddImm8, /*InsnID*/1, /*Imm*/127, |
| 45480 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45481 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45482 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45483 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8), |
| 45485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 45486 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45487 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45489 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45490 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45491 | GIR_RootConstrainSelectedInstOperands, |
| 45492 | // GIR_Coverage, 3248, |
| 45493 | GIR_EraseRootFromParent_Done, |
| 45494 | // Label 2610: @125489 |
| 45495 | GIM_Reject, |
| 45496 | // Label 2607: @125490 |
| 45497 | GIM_Reject, |
| 45498 | // Label 2603: @125491 |
| 45499 | GIM_Reject, |
| 45500 | // Label 74: @125492 |
| 45501 | GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(125772), |
| 45502 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 45503 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2615*/ GIMT_Encode4(125771), |
| 45504 | /*GILLT_v4s32*//*Label 2612*/ GIMT_Encode4(125543), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45505 | /*GILLT_v8s16*//*Label 2613*/ GIMT_Encode4(125619), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45506 | /*GILLT_v16s8*//*Label 2614*/ GIMT_Encode4(125695), |
| 45507 | // Label 2612: @125543 |
| 45508 | GIM_Try, /*On fail goto*//*Label 2616*/ GIMT_Encode4(125618), // Rule ID 3247 // |
| 45509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45510 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45511 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45512 | // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 45513 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45514 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45515 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45516 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 45517 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45518 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45519 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45520 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32), |
| 45522 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 45523 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45524 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45526 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45527 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45528 | GIR_RootConstrainSelectedInstOperands, |
| 45529 | // GIR_Coverage, 3247, |
| 45530 | GIR_EraseRootFromParent_Done, |
| 45531 | // Label 2616: @125618 |
| 45532 | GIM_Reject, |
| 45533 | // Label 2613: @125619 |
| 45534 | GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(125694), // Rule ID 3246 // |
| 45535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45537 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45538 | // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVu16:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 45539 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45540 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45541 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45542 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 45543 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45544 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45545 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45546 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16), |
| 45548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 45549 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45550 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45552 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45553 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45554 | GIR_RootConstrainSelectedInstOperands, |
| 45555 | // GIR_Coverage, 3246, |
| 45556 | GIR_EraseRootFromParent_Done, |
| 45557 | // Label 2617: @125694 |
| 45558 | GIM_Reject, |
| 45559 | // Label 2614: @125695 |
| 45560 | GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(125770), // Rule ID 3245 // |
| 45561 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45562 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45563 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45564 | // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 45565 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45566 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45567 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45568 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 45569 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45570 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45571 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45572 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8), |
| 45574 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 45575 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45576 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45578 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45579 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45580 | GIR_RootConstrainSelectedInstOperands, |
| 45581 | // GIR_Coverage, 3245, |
| 45582 | GIR_EraseRootFromParent_Done, |
| 45583 | // Label 2618: @125770 |
| 45584 | GIM_Reject, |
| 45585 | // Label 2615: @125771 |
| 45586 | GIM_Reject, |
| 45587 | // Label 2611: @125772 |
| 45588 | GIM_Reject, |
| 45589 | // Label 75: @125773 |
| 45590 | GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(126068), |
| 45591 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 45592 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2623*/ GIMT_Encode4(126067), |
| 45593 | /*GILLT_v4s32*//*Label 2620*/ GIMT_Encode4(125824), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45594 | /*GILLT_v8s16*//*Label 2621*/ GIMT_Encode4(125907), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45595 | /*GILLT_v16s8*//*Label 2622*/ GIMT_Encode4(125984), |
| 45596 | // Label 2620: @125824 |
| 45597 | GIM_Try, /*On fail goto*//*Label 2624*/ GIMT_Encode4(125906), // Rule ID 3253 // |
| 45598 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45599 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45600 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45601 | // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 4294967295:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 45602 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45603 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45604 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45605 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(4294967295), |
| 45606 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45607 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45608 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45609 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32), |
| 45611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 45612 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45613 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45615 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45616 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45617 | GIR_RootConstrainSelectedInstOperands, |
| 45618 | // GIR_Coverage, 3253, |
| 45619 | GIR_EraseRootFromParent_Done, |
| 45620 | // Label 2624: @125906 |
| 45621 | GIM_Reject, |
| 45622 | // Label 2621: @125907 |
| 45623 | GIM_Try, /*On fail goto*//*Label 2625*/ GIMT_Encode4(125983), // Rule ID 3252 // |
| 45624 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45625 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45626 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45627 | // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVu16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 65535:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 45628 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45629 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 45630 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45631 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535), |
| 45632 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45633 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45634 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16), |
| 45636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 45637 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45638 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45640 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45641 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45642 | GIR_RootConstrainSelectedInstOperands, |
| 45643 | // GIR_Coverage, 3252, |
| 45644 | GIR_EraseRootFromParent_Done, |
| 45645 | // Label 2625: @125983 |
| 45646 | GIM_Reject, |
| 45647 | // Label 2622: @125984 |
| 45648 | GIM_Try, /*On fail goto*//*Label 2626*/ GIMT_Encode4(126066), // Rule ID 3251 // |
| 45649 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45650 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45651 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45652 | // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 255:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 45653 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45654 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45655 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45656 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(255), |
| 45657 | GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45658 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45659 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45660 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8), |
| 45662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 45663 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45664 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45666 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45667 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45668 | GIR_RootConstrainSelectedInstOperands, |
| 45669 | // GIR_Coverage, 3251, |
| 45670 | GIR_EraseRootFromParent_Done, |
| 45671 | // Label 2626: @126066 |
| 45672 | GIM_Reject, |
| 45673 | // Label 2623: @126067 |
| 45674 | GIM_Reject, |
| 45675 | // Label 2619: @126068 |
| 45676 | GIM_Reject, |
| 45677 | // Label 76: @126069 |
| 45678 | GIM_Reject, |
| 45679 | }; // Size: 126070 bytes |
| 45680 | return MatchTable0; |
| 45681 | } |
| 45682 | #undef GIMT_Encode2 |
| 45683 | #undef GIMT_Encode4 |
| 45684 | #undef GIMT_Encode8 |
| 45685 | |
| 45686 | #endif // ifdef GET_GLOBALISEL_IMPL |
| 45687 | |
| 45688 | #ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 45689 | PredicateBitset AvailableModuleFeatures; |
| 45690 | mutable PredicateBitset AvailableFunctionFeatures; |
| 45691 | PredicateBitset getAvailableFeatures() const { |
| 45692 | return AvailableModuleFeatures | AvailableFunctionFeatures; |
| 45693 | } |
| 45694 | PredicateBitset |
| 45695 | computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const; |
| 45696 | PredicateBitset |
| 45697 | computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, |
| 45698 | const MachineFunction *MF) const; |
| 45699 | void setupGeneratedPerFunctionState(MachineFunction &MF) override; |
| 45700 | #endif // ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 45701 | #ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 45702 | AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), |
| 45703 | AvailableFunctionFeatures() |
| 45704 | #endif // ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 45705 |
Generated while processing llvm_projects/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
Generated on 2024-Oct-10 from project llvm_projects revision release-19.x-64075837b
Powered by 
Code Browser 2.1
Generator usage only permitted with license.