| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Target Instruction Enum Values and Descriptors *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_INSTRINFO_ENUM |
| 10 | #undef GET_INSTRINFO_ENUM |
| 11 | namespace llvm { |
| 12 | |
| 13 | namespace ARM { |
| 14 | enum { |
| 15 | PHI = 0, |
| 16 | INLINEASM = 1, |
| 17 | INLINEASM_BR = 2, |
| 18 | CFI_INSTRUCTION = 3, |
| 19 | EH_LABEL = 4, |
| 20 | GC_LABEL = 5, |
| 21 | ANNOTATION_LABEL = 6, |
| 22 | KILL = 7, |
| 23 | EXTRACT_SUBREG = 8, |
| 24 | INSERT_SUBREG = 9, |
| 25 | IMPLICIT_DEF = 10, |
| 26 | SUBREG_TO_REG = 11, |
| 27 | COPY_TO_REGCLASS = 12, |
| 28 | DBG_VALUE = 13, |
| 29 | DBG_VALUE_LIST = 14, |
| 30 | DBG_INSTR_REF = 15, |
| 31 | DBG_PHI = 16, |
| 32 | DBG_LABEL = 17, |
| 33 | REG_SEQUENCE = 18, |
| 34 | COPY = 19, |
| 35 | BUNDLE = 20, |
| 36 | LIFETIME_START = 21, |
| 37 | LIFETIME_END = 22, |
| 38 | PSEUDO_PROBE = 23, |
| 39 | ARITH_FENCE = 24, |
| 40 | STACKMAP = 25, |
| 41 | FENTRY_CALL = 26, |
| 42 | PATCHPOINT = 27, |
| 43 | LOAD_STACK_GUARD = 28, |
| 44 | PREALLOCATED_SETUP = 29, |
| 45 | PREALLOCATED_ARG = 30, |
| 46 | STATEPOINT = 31, |
| 47 | LOCAL_ESCAPE = 32, |
| 48 | FAULTING_OP = 33, |
| 49 | PATCHABLE_OP = 34, |
| 50 | PATCHABLE_FUNCTION_ENTER = 35, |
| 51 | PATCHABLE_RET = 36, |
| 52 | PATCHABLE_FUNCTION_EXIT = 37, |
| 53 | PATCHABLE_TAIL_CALL = 38, |
| 54 | PATCHABLE_EVENT_CALL = 39, |
| 55 | PATCHABLE_TYPED_EVENT_CALL = 40, |
| 56 | ICALL_BRANCH_FUNNEL = 41, |
| 57 | MEMBARRIER = 42, |
| 58 | JUMP_TABLE_DEBUG_INFO = 43, |
| 59 | CONVERGENCECTRL_ENTRY = 44, |
| 60 | CONVERGENCECTRL_ANCHOR = 45, |
| 61 | CONVERGENCECTRL_LOOP = 46, |
| 62 | CONVERGENCECTRL_GLUE = 47, |
| 63 | G_ASSERT_SEXT = 48, |
| 64 | G_ASSERT_ZEXT = 49, |
| 65 | G_ASSERT_ALIGN = 50, |
| 66 | G_ADD = 51, |
| 67 | G_SUB = 52, |
| 68 | G_MUL = 53, |
| 69 | G_SDIV = 54, |
| 70 | G_UDIV = 55, |
| 71 | G_SREM = 56, |
| 72 | G_UREM = 57, |
| 73 | G_SDIVREM = 58, |
| 74 | G_UDIVREM = 59, |
| 75 | G_AND = 60, |
| 76 | G_OR = 61, |
| 77 | G_XOR = 62, |
| 78 | G_IMPLICIT_DEF = 63, |
| 79 | G_PHI = 64, |
| 80 | G_FRAME_INDEX = 65, |
| 81 | G_GLOBAL_VALUE = 66, |
| 82 | G_PTRAUTH_GLOBAL_VALUE = 67, |
| 83 | G_CONSTANT_POOL = 68, |
| 84 | G_EXTRACT = 69, |
| 85 | G_UNMERGE_VALUES = 70, |
| 86 | G_INSERT = 71, |
| 87 | G_MERGE_VALUES = 72, |
| 88 | G_BUILD_VECTOR = 73, |
| 89 | G_BUILD_VECTOR_TRUNC = 74, |
| 90 | G_CONCAT_VECTORS = 75, |
| 91 | G_PTRTOINT = 76, |
| 92 | G_INTTOPTR = 77, |
| 93 | G_BITCAST = 78, |
| 94 | G_FREEZE = 79, |
| 95 | G_CONSTANT_FOLD_BARRIER = 80, |
| 96 | G_INTRINSIC_FPTRUNC_ROUND = 81, |
| 97 | G_INTRINSIC_TRUNC = 82, |
| 98 | G_INTRINSIC_ROUND = 83, |
| 99 | G_INTRINSIC_LRINT = 84, |
| 100 | G_INTRINSIC_LLRINT = 85, |
| 101 | G_INTRINSIC_ROUNDEVEN = 86, |
| 102 | G_READCYCLECOUNTER = 87, |
| 103 | G_READSTEADYCOUNTER = 88, |
| 104 | G_LOAD = 89, |
| 105 | G_SEXTLOAD = 90, |
| 106 | G_ZEXTLOAD = 91, |
| 107 | G_INDEXED_LOAD = 92, |
| 108 | G_INDEXED_SEXTLOAD = 93, |
| 109 | G_INDEXED_ZEXTLOAD = 94, |
| 110 | G_STORE = 95, |
| 111 | G_INDEXED_STORE = 96, |
| 112 | G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97, |
| 113 | G_ATOMIC_CMPXCHG = 98, |
| 114 | G_ATOMICRMW_XCHG = 99, |
| 115 | G_ATOMICRMW_ADD = 100, |
| 116 | G_ATOMICRMW_SUB = 101, |
| 117 | G_ATOMICRMW_AND = 102, |
| 118 | G_ATOMICRMW_NAND = 103, |
| 119 | G_ATOMICRMW_OR = 104, |
| 120 | G_ATOMICRMW_XOR = 105, |
| 121 | G_ATOMICRMW_MAX = 106, |
| 122 | G_ATOMICRMW_MIN = 107, |
| 123 | G_ATOMICRMW_UMAX = 108, |
| 124 | G_ATOMICRMW_UMIN = 109, |
| 125 | G_ATOMICRMW_FADD = 110, |
| 126 | G_ATOMICRMW_FSUB = 111, |
| 127 | G_ATOMICRMW_FMAX = 112, |
| 128 | G_ATOMICRMW_FMIN = 113, |
| 129 | G_ATOMICRMW_UINC_WRAP = 114, |
| 130 | G_ATOMICRMW_UDEC_WRAP = 115, |
| 131 | G_FENCE = 116, |
| 132 | G_PREFETCH = 117, |
| 133 | G_BRCOND = 118, |
| 134 | G_BRINDIRECT = 119, |
| 135 | G_INVOKE_REGION_START = 120, |
| 136 | G_INTRINSIC = 121, |
| 137 | G_INTRINSIC_W_SIDE_EFFECTS = 122, |
| 138 | G_INTRINSIC_CONVERGENT = 123, |
| 139 | G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124, |
| 140 | G_ANYEXT = 125, |
| 141 | G_TRUNC = 126, |
| 142 | G_CONSTANT = 127, |
| 143 | G_FCONSTANT = 128, |
| 144 | G_VASTART = 129, |
| 145 | G_VAARG = 130, |
| 146 | G_SEXT = 131, |
| 147 | G_SEXT_INREG = 132, |
| 148 | G_ZEXT = 133, |
| 149 | G_SHL = 134, |
| 150 | G_LSHR = 135, |
| 151 | G_ASHR = 136, |
| 152 | G_FSHL = 137, |
| 153 | G_FSHR = 138, |
| 154 | G_ROTR = 139, |
| 155 | G_ROTL = 140, |
| 156 | G_ICMP = 141, |
| 157 | G_FCMP = 142, |
| 158 | G_SCMP = 143, |
| 159 | G_UCMP = 144, |
| 160 | G_SELECT = 145, |
| 161 | G_UADDO = 146, |
| 162 | G_UADDE = 147, |
| 163 | G_USUBO = 148, |
| 164 | G_USUBE = 149, |
| 165 | G_SADDO = 150, |
| 166 | G_SADDE = 151, |
| 167 | G_SSUBO = 152, |
| 168 | G_SSUBE = 153, |
| 169 | G_UMULO = 154, |
| 170 | G_SMULO = 155, |
| 171 | G_UMULH = 156, |
| 172 | G_SMULH = 157, |
| 173 | G_UADDSAT = 158, |
| 174 | G_SADDSAT = 159, |
| 175 | G_USUBSAT = 160, |
| 176 | G_SSUBSAT = 161, |
| 177 | G_USHLSAT = 162, |
| 178 | G_SSHLSAT = 163, |
| 179 | G_SMULFIX = 164, |
| 180 | G_UMULFIX = 165, |
| 181 | G_SMULFIXSAT = 166, |
| 182 | G_UMULFIXSAT = 167, |
| 183 | G_SDIVFIX = 168, |
| 184 | G_UDIVFIX = 169, |
| 185 | G_SDIVFIXSAT = 170, |
| 186 | G_UDIVFIXSAT = 171, |
| 187 | G_FADD = 172, |
| 188 | G_FSUB = 173, |
| 189 | G_FMUL = 174, |
| 190 | G_FMA = 175, |
| 191 | G_FMAD = 176, |
| 192 | G_FDIV = 177, |
| 193 | G_FREM = 178, |
| 194 | G_FPOW = 179, |
| 195 | G_FPOWI = 180, |
| 196 | G_FEXP = 181, |
| 197 | G_FEXP2 = 182, |
| 198 | G_FEXP10 = 183, |
| 199 | G_FLOG = 184, |
| 200 | G_FLOG2 = 185, |
| 201 | G_FLOG10 = 186, |
| 202 | G_FLDEXP = 187, |
| 203 | G_FFREXP = 188, |
| 204 | G_FNEG = 189, |
| 205 | G_FPEXT = 190, |
| 206 | G_FPTRUNC = 191, |
| 207 | G_FPTOSI = 192, |
| 208 | G_FPTOUI = 193, |
| 209 | G_SITOFP = 194, |
| 210 | G_UITOFP = 195, |
| 211 | G_FABS = 196, |
| 212 | G_FCOPYSIGN = 197, |
| 213 | G_IS_FPCLASS = 198, |
| 214 | G_FCANONICALIZE = 199, |
| 215 | G_FMINNUM = 200, |
| 216 | G_FMAXNUM = 201, |
| 217 | G_FMINNUM_IEEE = 202, |
| 218 | G_FMAXNUM_IEEE = 203, |
| 219 | G_FMINIMUM = 204, |
| 220 | G_FMAXIMUM = 205, |
| 221 | G_GET_FPENV = 206, |
| 222 | G_SET_FPENV = 207, |
| 223 | G_RESET_FPENV = 208, |
| 224 | G_GET_FPMODE = 209, |
| 225 | G_SET_FPMODE = 210, |
| 226 | G_RESET_FPMODE = 211, |
| 227 | G_PTR_ADD = 212, |
| 228 | G_PTRMASK = 213, |
| 229 | G_SMIN = 214, |
| 230 | G_SMAX = 215, |
| 231 | G_UMIN = 216, |
| 232 | G_UMAX = 217, |
| 233 | G_ABS = 218, |
| 234 | G_LROUND = 219, |
| 235 | G_LLROUND = 220, |
| 236 | G_BR = 221, |
| 237 | G_BRJT = 222, |
| 238 | G_VSCALE = 223, |
| 239 | G_INSERT_SUBVECTOR = 224, |
| 240 | G_EXTRACT_SUBVECTOR = 225, |
| 241 | G_INSERT_VECTOR_ELT = 226, |
| 242 | G_EXTRACT_VECTOR_ELT = 227, |
| 243 | G_SHUFFLE_VECTOR = 228, |
| 244 | G_SPLAT_VECTOR = 229, |
| 245 | G_VECTOR_COMPRESS = 230, |
| 246 | G_CTTZ = 231, |
| 247 | G_CTTZ_ZERO_UNDEF = 232, |
| 248 | G_CTLZ = 233, |
| 249 | G_CTLZ_ZERO_UNDEF = 234, |
| 250 | G_CTPOP = 235, |
| 251 | G_BSWAP = 236, |
| 252 | G_BITREVERSE = 237, |
| 253 | G_FCEIL = 238, |
| 254 | G_FCOS = 239, |
| 255 | G_FSIN = 240, |
| 256 | G_FTAN = 241, |
| 257 | G_FACOS = 242, |
| 258 | G_FASIN = 243, |
| 259 | G_FATAN = 244, |
| 260 | G_FCOSH = 245, |
| 261 | G_FSINH = 246, |
| 262 | G_FTANH = 247, |
| 263 | G_FSQRT = 248, |
| 264 | G_FFLOOR = 249, |
| 265 | G_FRINT = 250, |
| 266 | G_FNEARBYINT = 251, |
| 267 | G_ADDRSPACE_CAST = 252, |
| 268 | G_BLOCK_ADDR = 253, |
| 269 | G_JUMP_TABLE = 254, |
| 270 | G_DYN_STACKALLOC = 255, |
| 271 | G_STACKSAVE = 256, |
| 272 | G_STACKRESTORE = 257, |
| 273 | G_STRICT_FADD = 258, |
| 274 | G_STRICT_FSUB = 259, |
| 275 | G_STRICT_FMUL = 260, |
| 276 | G_STRICT_FDIV = 261, |
| 277 | G_STRICT_FREM = 262, |
| 278 | G_STRICT_FMA = 263, |
| 279 | G_STRICT_FSQRT = 264, |
| 280 | G_STRICT_FLDEXP = 265, |
| 281 | G_READ_REGISTER = 266, |
| 282 | G_WRITE_REGISTER = 267, |
| 283 | G_MEMCPY = 268, |
| 284 | G_MEMCPY_INLINE = 269, |
| 285 | G_MEMMOVE = 270, |
| 286 | G_MEMSET = 271, |
| 287 | G_BZERO = 272, |
| 288 | G_TRAP = 273, |
| 289 | G_DEBUGTRAP = 274, |
| 290 | G_UBSANTRAP = 275, |
| 291 | G_VECREDUCE_SEQ_FADD = 276, |
| 292 | G_VECREDUCE_SEQ_FMUL = 277, |
| 293 | G_VECREDUCE_FADD = 278, |
| 294 | G_VECREDUCE_FMUL = 279, |
| 295 | G_VECREDUCE_FMAX = 280, |
| 296 | G_VECREDUCE_FMIN = 281, |
| 297 | G_VECREDUCE_FMAXIMUM = 282, |
| 298 | G_VECREDUCE_FMINIMUM = 283, |
| 299 | G_VECREDUCE_ADD = 284, |
| 300 | G_VECREDUCE_MUL = 285, |
| 301 | G_VECREDUCE_AND = 286, |
| 302 | G_VECREDUCE_OR = 287, |
| 303 | G_VECREDUCE_XOR = 288, |
| 304 | G_VECREDUCE_SMAX = 289, |
| 305 | G_VECREDUCE_SMIN = 290, |
| 306 | G_VECREDUCE_UMAX = 291, |
| 307 | G_VECREDUCE_UMIN = 292, |
| 308 | G_SBFX = 293, |
| 309 | G_UBFX = 294, |
| 310 | ABS = 295, |
| 311 | ADDSri = 296, |
| 312 | ADDSrr = 297, |
| 313 | ADDSrsi = 298, |
| 314 | ADDSrsr = 299, |
| 315 | ADJCALLSTACKDOWN = 300, |
| 316 | ADJCALLSTACKUP = 301, |
| 317 | ASRi = 302, |
| 318 | ASRr = 303, |
| 319 | B = 304, |
| 320 | BCCZi64 = 305, |
| 321 | BCCi64 = 306, |
| 322 | BLX_noip = 307, |
| 323 | BLX_pred_noip = 308, |
| 324 | BL_PUSHLR = 309, |
| 325 | BMOVPCB_CALL = 310, |
| 326 | BMOVPCRX_CALL = 311, |
| 327 | BR_JTadd = 312, |
| 328 | BR_JTm_i12 = 313, |
| 329 | BR_JTm_rs = 314, |
| 330 | BR_JTr = 315, |
| 331 | BX_CALL = 316, |
| 332 | CMP_SWAP_16 = 317, |
| 333 | CMP_SWAP_32 = 318, |
| 334 | CMP_SWAP_64 = 319, |
| 335 | CMP_SWAP_8 = 320, |
| 336 | CONSTPOOL_ENTRY = 321, |
| 337 | COPY_STRUCT_BYVAL_I32 = 322, |
| 338 | ITasm = 323, |
| 339 | Int_eh_sjlj_dispatchsetup = 324, |
| 340 | Int_eh_sjlj_longjmp = 325, |
| 341 | Int_eh_sjlj_setjmp = 326, |
| 342 | Int_eh_sjlj_setjmp_nofp = 327, |
| 343 | Int_eh_sjlj_setup_dispatch = 328, |
| 344 | JUMPTABLE_ADDRS = 329, |
| 345 | JUMPTABLE_INSTS = 330, |
| 346 | JUMPTABLE_TBB = 331, |
| 347 | JUMPTABLE_TBH = 332, |
| 348 | LDMIA_RET = 333, |
| 349 | LDRBT_POST = 334, |
| 350 | LDRConstPool = 335, |
| 351 | LDRHTii = 336, |
| 352 | LDRLIT_ga_abs = 337, |
| 353 | LDRLIT_ga_pcrel = 338, |
| 354 | LDRLIT_ga_pcrel_ldr = 339, |
| 355 | LDRSBTii = 340, |
| 356 | LDRSHTii = 341, |
| 357 | LDRT_POST = 342, |
| 358 | LEApcrel = 343, |
| 359 | LEApcrelJT = 344, |
| 360 | LOADDUAL = 345, |
| 361 | LSLi = 346, |
| 362 | LSLr = 347, |
| 363 | LSRi = 348, |
| 364 | LSRr = 349, |
| 365 | MEMCPY = 350, |
| 366 | MLAv5 = 351, |
| 367 | MOVCCi = 352, |
| 368 | MOVCCi16 = 353, |
| 369 | MOVCCi32imm = 354, |
| 370 | MOVCCr = 355, |
| 371 | MOVCCsi = 356, |
| 372 | MOVCCsr = 357, |
| 373 | MOVPCRX = 358, |
| 374 | MOVTi16_ga_pcrel = 359, |
| 375 | MOV_ga_pcrel = 360, |
| 376 | MOV_ga_pcrel_ldr = 361, |
| 377 | MOVi16_ga_pcrel = 362, |
| 378 | MOVi32imm = 363, |
| 379 | MOVsra_glue = 364, |
| 380 | MOVsrl_glue = 365, |
| 381 | MQPRCopy = 366, |
| 382 | MQQPRLoad = 367, |
| 383 | MQQPRStore = 368, |
| 384 | MQQQQPRLoad = 369, |
| 385 | MQQQQPRStore = 370, |
| 386 | MULv5 = 371, |
| 387 | MVE_MEMCPYLOOPINST = 372, |
| 388 | MVE_MEMSETLOOPINST = 373, |
| 389 | MVNCCi = 374, |
| 390 | PICADD = 375, |
| 391 | PICLDR = 376, |
| 392 | PICLDRB = 377, |
| 393 | PICLDRH = 378, |
| 394 | PICLDRSB = 379, |
| 395 | PICLDRSH = 380, |
| 396 | PICSTR = 381, |
| 397 | PICSTRB = 382, |
| 398 | PICSTRH = 383, |
| 399 | PseudoARMInitUndefDPR_VFP2 = 384, |
| 400 | PseudoARMInitUndefGPR = 385, |
| 401 | PseudoARMInitUndefMQPR = 386, |
| 402 | PseudoARMInitUndefSPR = 387, |
| 403 | RORi = 388, |
| 404 | RORr = 389, |
| 405 | RRX = 390, |
| 406 | RRXi = 391, |
| 407 | RSBSri = 392, |
| 408 | RSBSrsi = 393, |
| 409 | RSBSrsr = 394, |
| 410 | SEH_EpilogEnd = 395, |
| 411 | SEH_EpilogStart = 396, |
| 412 | SEH_Nop = 397, |
| 413 | SEH_Nop_Ret = 398, |
| 414 | SEH_PrologEnd = 399, |
| 415 | SEH_SaveFRegs = 400, |
| 416 | SEH_SaveLR = 401, |
| 417 | SEH_SaveRegs = 402, |
| 418 | SEH_SaveRegs_Ret = 403, |
| 419 | SEH_SaveSP = 404, |
| 420 | SEH_StackAlloc = 405, |
| 421 | SMLALv5 = 406, |
| 422 | SMULLv5 = 407, |
| 423 | SPACE = 408, |
| 424 | STOREDUAL = 409, |
| 425 | STRBT_POST = 410, |
| 426 | STRBi_preidx = 411, |
| 427 | STRBr_preidx = 412, |
| 428 | STRH_preidx = 413, |
| 429 | STRT_POST = 414, |
| 430 | STRi_preidx = 415, |
| 431 | STRr_preidx = 416, |
| 432 | SUBS_PC_LR = 417, |
| 433 | SUBSri = 418, |
| 434 | SUBSrr = 419, |
| 435 | SUBSrsi = 420, |
| 436 | SUBSrsr = 421, |
| 437 | SpeculationBarrierISBDSBEndBB = 422, |
| 438 | SpeculationBarrierSBEndBB = 423, |
| 439 | TAILJMPd = 424, |
| 440 | TAILJMPr = 425, |
| 441 | TAILJMPr4 = 426, |
| 442 | TCRETURNdi = 427, |
| 443 | TCRETURNri = 428, |
| 444 | TCRETURNrinotr12 = 429, |
| 445 | TPsoft = 430, |
| 446 | UMLALv5 = 431, |
| 447 | UMULLv5 = 432, |
| 448 | VLD1LNdAsm_16 = 433, |
| 449 | VLD1LNdAsm_32 = 434, |
| 450 | VLD1LNdAsm_8 = 435, |
| 451 | VLD1LNdWB_fixed_Asm_16 = 436, |
| 452 | VLD1LNdWB_fixed_Asm_32 = 437, |
| 453 | VLD1LNdWB_fixed_Asm_8 = 438, |
| 454 | VLD1LNdWB_register_Asm_16 = 439, |
| 455 | VLD1LNdWB_register_Asm_32 = 440, |
| 456 | VLD1LNdWB_register_Asm_8 = 441, |
| 457 | VLD2LNdAsm_16 = 442, |
| 458 | VLD2LNdAsm_32 = 443, |
| 459 | VLD2LNdAsm_8 = 444, |
| 460 | VLD2LNdWB_fixed_Asm_16 = 445, |
| 461 | VLD2LNdWB_fixed_Asm_32 = 446, |
| 462 | VLD2LNdWB_fixed_Asm_8 = 447, |
| 463 | VLD2LNdWB_register_Asm_16 = 448, |
| 464 | VLD2LNdWB_register_Asm_32 = 449, |
| 465 | VLD2LNdWB_register_Asm_8 = 450, |
| 466 | VLD2LNqAsm_16 = 451, |
| 467 | VLD2LNqAsm_32 = 452, |
| 468 | VLD2LNqWB_fixed_Asm_16 = 453, |
| 469 | VLD2LNqWB_fixed_Asm_32 = 454, |
| 470 | VLD2LNqWB_register_Asm_16 = 455, |
| 471 | VLD2LNqWB_register_Asm_32 = 456, |
| 472 | VLD3DUPdAsm_16 = 457, |
| 473 | VLD3DUPdAsm_32 = 458, |
| 474 | VLD3DUPdAsm_8 = 459, |
| 475 | VLD3DUPdWB_fixed_Asm_16 = 460, |
| 476 | VLD3DUPdWB_fixed_Asm_32 = 461, |
| 477 | VLD3DUPdWB_fixed_Asm_8 = 462, |
| 478 | VLD3DUPdWB_register_Asm_16 = 463, |
| 479 | VLD3DUPdWB_register_Asm_32 = 464, |
| 480 | VLD3DUPdWB_register_Asm_8 = 465, |
| 481 | VLD3DUPqAsm_16 = 466, |
| 482 | VLD3DUPqAsm_32 = 467, |
| 483 | VLD3DUPqAsm_8 = 468, |
| 484 | VLD3DUPqWB_fixed_Asm_16 = 469, |
| 485 | VLD3DUPqWB_fixed_Asm_32 = 470, |
| 486 | VLD3DUPqWB_fixed_Asm_8 = 471, |
| 487 | VLD3DUPqWB_register_Asm_16 = 472, |
| 488 | VLD3DUPqWB_register_Asm_32 = 473, |
| 489 | VLD3DUPqWB_register_Asm_8 = 474, |
| 490 | VLD3LNdAsm_16 = 475, |
| 491 | VLD3LNdAsm_32 = 476, |
| 492 | VLD3LNdAsm_8 = 477, |
| 493 | VLD3LNdWB_fixed_Asm_16 = 478, |
| 494 | VLD3LNdWB_fixed_Asm_32 = 479, |
| 495 | VLD3LNdWB_fixed_Asm_8 = 480, |
| 496 | VLD3LNdWB_register_Asm_16 = 481, |
| 497 | VLD3LNdWB_register_Asm_32 = 482, |
| 498 | VLD3LNdWB_register_Asm_8 = 483, |
| 499 | VLD3LNqAsm_16 = 484, |
| 500 | VLD3LNqAsm_32 = 485, |
| 501 | VLD3LNqWB_fixed_Asm_16 = 486, |
| 502 | VLD3LNqWB_fixed_Asm_32 = 487, |
| 503 | VLD3LNqWB_register_Asm_16 = 488, |
| 504 | VLD3LNqWB_register_Asm_32 = 489, |
| 505 | VLD3dAsm_16 = 490, |
| 506 | VLD3dAsm_32 = 491, |
| 507 | VLD3dAsm_8 = 492, |
| 508 | VLD3dWB_fixed_Asm_16 = 493, |
| 509 | VLD3dWB_fixed_Asm_32 = 494, |
| 510 | VLD3dWB_fixed_Asm_8 = 495, |
| 511 | VLD3dWB_register_Asm_16 = 496, |
| 512 | VLD3dWB_register_Asm_32 = 497, |
| 513 | VLD3dWB_register_Asm_8 = 498, |
| 514 | VLD3qAsm_16 = 499, |
| 515 | VLD3qAsm_32 = 500, |
| 516 | VLD3qAsm_8 = 501, |
| 517 | VLD3qWB_fixed_Asm_16 = 502, |
| 518 | VLD3qWB_fixed_Asm_32 = 503, |
| 519 | VLD3qWB_fixed_Asm_8 = 504, |
| 520 | VLD3qWB_register_Asm_16 = 505, |
| 521 | VLD3qWB_register_Asm_32 = 506, |
| 522 | VLD3qWB_register_Asm_8 = 507, |
| 523 | VLD4DUPdAsm_16 = 508, |
| 524 | VLD4DUPdAsm_32 = 509, |
| 525 | VLD4DUPdAsm_8 = 510, |
| 526 | VLD4DUPdWB_fixed_Asm_16 = 511, |
| 527 | VLD4DUPdWB_fixed_Asm_32 = 512, |
| 528 | VLD4DUPdWB_fixed_Asm_8 = 513, |
| 529 | VLD4DUPdWB_register_Asm_16 = 514, |
| 530 | VLD4DUPdWB_register_Asm_32 = 515, |
| 531 | VLD4DUPdWB_register_Asm_8 = 516, |
| 532 | VLD4DUPqAsm_16 = 517, |
| 533 | VLD4DUPqAsm_32 = 518, |
| 534 | VLD4DUPqAsm_8 = 519, |
| 535 | VLD4DUPqWB_fixed_Asm_16 = 520, |
| 536 | VLD4DUPqWB_fixed_Asm_32 = 521, |
| 537 | VLD4DUPqWB_fixed_Asm_8 = 522, |
| 538 | VLD4DUPqWB_register_Asm_16 = 523, |
| 539 | VLD4DUPqWB_register_Asm_32 = 524, |
| 540 | VLD4DUPqWB_register_Asm_8 = 525, |
| 541 | VLD4LNdAsm_16 = 526, |
| 542 | VLD4LNdAsm_32 = 527, |
| 543 | VLD4LNdAsm_8 = 528, |
| 544 | VLD4LNdWB_fixed_Asm_16 = 529, |
| 545 | VLD4LNdWB_fixed_Asm_32 = 530, |
| 546 | VLD4LNdWB_fixed_Asm_8 = 531, |
| 547 | VLD4LNdWB_register_Asm_16 = 532, |
| 548 | VLD4LNdWB_register_Asm_32 = 533, |
| 549 | VLD4LNdWB_register_Asm_8 = 534, |
| 550 | VLD4LNqAsm_16 = 535, |
| 551 | VLD4LNqAsm_32 = 536, |
| 552 | VLD4LNqWB_fixed_Asm_16 = 537, |
| 553 | VLD4LNqWB_fixed_Asm_32 = 538, |
| 554 | VLD4LNqWB_register_Asm_16 = 539, |
| 555 | VLD4LNqWB_register_Asm_32 = 540, |
| 556 | VLD4dAsm_16 = 541, |
| 557 | VLD4dAsm_32 = 542, |
| 558 | VLD4dAsm_8 = 543, |
| 559 | VLD4dWB_fixed_Asm_16 = 544, |
| 560 | VLD4dWB_fixed_Asm_32 = 545, |
| 561 | VLD4dWB_fixed_Asm_8 = 546, |
| 562 | VLD4dWB_register_Asm_16 = 547, |
| 563 | VLD4dWB_register_Asm_32 = 548, |
| 564 | VLD4dWB_register_Asm_8 = 549, |
| 565 | VLD4qAsm_16 = 550, |
| 566 | VLD4qAsm_32 = 551, |
| 567 | VLD4qAsm_8 = 552, |
| 568 | VLD4qWB_fixed_Asm_16 = 553, |
| 569 | VLD4qWB_fixed_Asm_32 = 554, |
| 570 | VLD4qWB_fixed_Asm_8 = 555, |
| 571 | VLD4qWB_register_Asm_16 = 556, |
| 572 | VLD4qWB_register_Asm_32 = 557, |
| 573 | VLD4qWB_register_Asm_8 = 558, |
| 574 | VMOVD0 = 559, |
| 575 | VMOVDcc = 560, |
| 576 | VMOVHcc = 561, |
| 577 | VMOVQ0 = 562, |
| 578 | VMOVScc = 563, |
| 579 | VST1LNdAsm_16 = 564, |
| 580 | VST1LNdAsm_32 = 565, |
| 581 | VST1LNdAsm_8 = 566, |
| 582 | VST1LNdWB_fixed_Asm_16 = 567, |
| 583 | VST1LNdWB_fixed_Asm_32 = 568, |
| 584 | VST1LNdWB_fixed_Asm_8 = 569, |
| 585 | VST1LNdWB_register_Asm_16 = 570, |
| 586 | VST1LNdWB_register_Asm_32 = 571, |
| 587 | VST1LNdWB_register_Asm_8 = 572, |
| 588 | VST2LNdAsm_16 = 573, |
| 589 | VST2LNdAsm_32 = 574, |
| 590 | VST2LNdAsm_8 = 575, |
| 591 | VST2LNdWB_fixed_Asm_16 = 576, |
| 592 | VST2LNdWB_fixed_Asm_32 = 577, |
| 593 | VST2LNdWB_fixed_Asm_8 = 578, |
| 594 | VST2LNdWB_register_Asm_16 = 579, |
| 595 | VST2LNdWB_register_Asm_32 = 580, |
| 596 | VST2LNdWB_register_Asm_8 = 581, |
| 597 | VST2LNqAsm_16 = 582, |
| 598 | VST2LNqAsm_32 = 583, |
| 599 | VST2LNqWB_fixed_Asm_16 = 584, |
| 600 | VST2LNqWB_fixed_Asm_32 = 585, |
| 601 | VST2LNqWB_register_Asm_16 = 586, |
| 602 | VST2LNqWB_register_Asm_32 = 587, |
| 603 | VST3LNdAsm_16 = 588, |
| 604 | VST3LNdAsm_32 = 589, |
| 605 | VST3LNdAsm_8 = 590, |
| 606 | VST3LNdWB_fixed_Asm_16 = 591, |
| 607 | VST3LNdWB_fixed_Asm_32 = 592, |
| 608 | VST3LNdWB_fixed_Asm_8 = 593, |
| 609 | VST3LNdWB_register_Asm_16 = 594, |
| 610 | VST3LNdWB_register_Asm_32 = 595, |
| 611 | VST3LNdWB_register_Asm_8 = 596, |
| 612 | VST3LNqAsm_16 = 597, |
| 613 | VST3LNqAsm_32 = 598, |
| 614 | VST3LNqWB_fixed_Asm_16 = 599, |
| 615 | VST3LNqWB_fixed_Asm_32 = 600, |
| 616 | VST3LNqWB_register_Asm_16 = 601, |
| 617 | VST3LNqWB_register_Asm_32 = 602, |
| 618 | VST3dAsm_16 = 603, |
| 619 | VST3dAsm_32 = 604, |
| 620 | VST3dAsm_8 = 605, |
| 621 | VST3dWB_fixed_Asm_16 = 606, |
| 622 | VST3dWB_fixed_Asm_32 = 607, |
| 623 | VST3dWB_fixed_Asm_8 = 608, |
| 624 | VST3dWB_register_Asm_16 = 609, |
| 625 | VST3dWB_register_Asm_32 = 610, |
| 626 | VST3dWB_register_Asm_8 = 611, |
| 627 | VST3qAsm_16 = 612, |
| 628 | VST3qAsm_32 = 613, |
| 629 | VST3qAsm_8 = 614, |
| 630 | VST3qWB_fixed_Asm_16 = 615, |
| 631 | VST3qWB_fixed_Asm_32 = 616, |
| 632 | VST3qWB_fixed_Asm_8 = 617, |
| 633 | VST3qWB_register_Asm_16 = 618, |
| 634 | VST3qWB_register_Asm_32 = 619, |
| 635 | VST3qWB_register_Asm_8 = 620, |
| 636 | VST4LNdAsm_16 = 621, |
| 637 | VST4LNdAsm_32 = 622, |
| 638 | VST4LNdAsm_8 = 623, |
| 639 | VST4LNdWB_fixed_Asm_16 = 624, |
| 640 | VST4LNdWB_fixed_Asm_32 = 625, |
| 641 | VST4LNdWB_fixed_Asm_8 = 626, |
| 642 | VST4LNdWB_register_Asm_16 = 627, |
| 643 | VST4LNdWB_register_Asm_32 = 628, |
| 644 | VST4LNdWB_register_Asm_8 = 629, |
| 645 | VST4LNqAsm_16 = 630, |
| 646 | VST4LNqAsm_32 = 631, |
| 647 | VST4LNqWB_fixed_Asm_16 = 632, |
| 648 | VST4LNqWB_fixed_Asm_32 = 633, |
| 649 | VST4LNqWB_register_Asm_16 = 634, |
| 650 | VST4LNqWB_register_Asm_32 = 635, |
| 651 | VST4dAsm_16 = 636, |
| 652 | VST4dAsm_32 = 637, |
| 653 | VST4dAsm_8 = 638, |
| 654 | VST4dWB_fixed_Asm_16 = 639, |
| 655 | VST4dWB_fixed_Asm_32 = 640, |
| 656 | VST4dWB_fixed_Asm_8 = 641, |
| 657 | VST4dWB_register_Asm_16 = 642, |
| 658 | VST4dWB_register_Asm_32 = 643, |
| 659 | VST4dWB_register_Asm_8 = 644, |
| 660 | VST4qAsm_16 = 645, |
| 661 | VST4qAsm_32 = 646, |
| 662 | VST4qAsm_8 = 647, |
| 663 | VST4qWB_fixed_Asm_16 = 648, |
| 664 | VST4qWB_fixed_Asm_32 = 649, |
| 665 | VST4qWB_fixed_Asm_8 = 650, |
| 666 | VST4qWB_register_Asm_16 = 651, |
| 667 | VST4qWB_register_Asm_32 = 652, |
| 668 | VST4qWB_register_Asm_8 = 653, |
| 669 | WIN__CHKSTK = 654, |
| 670 | WIN__DBZCHK = 655, |
| 671 | t2ABS = 656, |
| 672 | t2ADDSri = 657, |
| 673 | t2ADDSrr = 658, |
| 674 | t2ADDSrs = 659, |
| 675 | t2BF_LabelPseudo = 660, |
| 676 | t2BR_JT = 661, |
| 677 | t2CALL_BTI = 662, |
| 678 | t2DoLoopStart = 663, |
| 679 | t2DoLoopStartTP = 664, |
| 680 | t2LDMIA_RET = 665, |
| 681 | t2LDRB_OFFSET_imm = 666, |
| 682 | t2LDRB_POST_imm = 667, |
| 683 | t2LDRB_PRE_imm = 668, |
| 684 | t2LDRBpcrel = 669, |
| 685 | t2LDRConstPool = 670, |
| 686 | t2LDRH_OFFSET_imm = 671, |
| 687 | t2LDRH_POST_imm = 672, |
| 688 | t2LDRH_PRE_imm = 673, |
| 689 | t2LDRHpcrel = 674, |
| 690 | t2LDRLIT_ga_pcrel = 675, |
| 691 | t2LDRSB_OFFSET_imm = 676, |
| 692 | t2LDRSB_POST_imm = 677, |
| 693 | t2LDRSB_PRE_imm = 678, |
| 694 | t2LDRSBpcrel = 679, |
| 695 | t2LDRSH_OFFSET_imm = 680, |
| 696 | t2LDRSH_POST_imm = 681, |
| 697 | t2LDRSH_PRE_imm = 682, |
| 698 | t2LDRSHpcrel = 683, |
| 699 | t2LDR_POST_imm = 684, |
| 700 | t2LDR_PRE_imm = 685, |
| 701 | t2LDRpci_pic = 686, |
| 702 | t2LDRpcrel = 687, |
| 703 | t2LEApcrel = 688, |
| 704 | t2LEApcrelJT = 689, |
| 705 | t2LoopDec = 690, |
| 706 | t2LoopEnd = 691, |
| 707 | t2LoopEndDec = 692, |
| 708 | t2MOVCCasr = 693, |
| 709 | t2MOVCCi = 694, |
| 710 | t2MOVCCi16 = 695, |
| 711 | t2MOVCCi32imm = 696, |
| 712 | t2MOVCClsl = 697, |
| 713 | t2MOVCClsr = 698, |
| 714 | t2MOVCCr = 699, |
| 715 | t2MOVCCror = 700, |
| 716 | t2MOVSsi = 701, |
| 717 | t2MOVSsr = 702, |
| 718 | t2MOVTi16_ga_pcrel = 703, |
| 719 | t2MOV_ga_pcrel = 704, |
| 720 | t2MOVi16_ga_pcrel = 705, |
| 721 | t2MOVi32imm = 706, |
| 722 | t2MOVsi = 707, |
| 723 | t2MOVsr = 708, |
| 724 | t2MVNCCi = 709, |
| 725 | t2RSBSri = 710, |
| 726 | t2RSBSrs = 711, |
| 727 | t2STRB_OFFSET_imm = 712, |
| 728 | t2STRB_POST_imm = 713, |
| 729 | t2STRB_PRE_imm = 714, |
| 730 | t2STRB_preidx = 715, |
| 731 | t2STRH_OFFSET_imm = 716, |
| 732 | t2STRH_POST_imm = 717, |
| 733 | t2STRH_PRE_imm = 718, |
| 734 | t2STRH_preidx = 719, |
| 735 | t2STR_POST_imm = 720, |
| 736 | t2STR_PRE_imm = 721, |
| 737 | t2STR_preidx = 722, |
| 738 | t2SUBSri = 723, |
| 739 | t2SUBSrr = 724, |
| 740 | t2SUBSrs = 725, |
| 741 | t2SpeculationBarrierISBDSBEndBB = 726, |
| 742 | t2SpeculationBarrierSBEndBB = 727, |
| 743 | t2TBB_JT = 728, |
| 744 | t2TBH_JT = 729, |
| 745 | t2WhileLoopSetup = 730, |
| 746 | t2WhileLoopStart = 731, |
| 747 | t2WhileLoopStartLR = 732, |
| 748 | t2WhileLoopStartTP = 733, |
| 749 | tADCS = 734, |
| 750 | tADDSi3 = 735, |
| 751 | tADDSi8 = 736, |
| 752 | tADDSrr = 737, |
| 753 | tADDframe = 738, |
| 754 | tADJCALLSTACKDOWN = 739, |
| 755 | tADJCALLSTACKUP = 740, |
| 756 | tBLXNS_CALL = 741, |
| 757 | tBLXr_noip = 742, |
| 758 | tBL_PUSHLR = 743, |
| 759 | tBRIND = 744, |
| 760 | tBR_JTr = 745, |
| 761 | tBXNS_RET = 746, |
| 762 | tBX_CALL = 747, |
| 763 | tBX_RET = 748, |
| 764 | tBX_RET_vararg = 749, |
| 765 | tBfar = 750, |
| 766 | tCMP_SWAP_16 = 751, |
| 767 | tCMP_SWAP_32 = 752, |
| 768 | tCMP_SWAP_8 = 753, |
| 769 | tLDMIA_UPD = 754, |
| 770 | tLDRConstPool = 755, |
| 771 | tLDRLIT_ga_abs = 756, |
| 772 | tLDRLIT_ga_pcrel = 757, |
| 773 | tLDR_postidx = 758, |
| 774 | tLDRpci_pic = 759, |
| 775 | tLEApcrel = 760, |
| 776 | tLEApcrelJT = 761, |
| 777 | tLSLSri = 762, |
| 778 | tMOVCCr_pseudo = 763, |
| 779 | tMOVi32imm = 764, |
| 780 | tPOP_RET = 765, |
| 781 | tRSBS = 766, |
| 782 | tSBCS = 767, |
| 783 | tSUBSi3 = 768, |
| 784 | tSUBSi8 = 769, |
| 785 | tSUBSrr = 770, |
| 786 | tTAILJMPd = 771, |
| 787 | tTAILJMPdND = 772, |
| 788 | tTAILJMPr = 773, |
| 789 | tTBB_JT = 774, |
| 790 | tTBH_JT = 775, |
| 791 | tTPsoft = 776, |
| 792 | ADCri = 777, |
| 793 | ADCrr = 778, |
| 794 | ADCrsi = 779, |
| 795 | ADCrsr = 780, |
| 796 | ADDri = 781, |
| 797 | ADDrr = 782, |
| 798 | ADDrsi = 783, |
| 799 | ADDrsr = 784, |
| 800 | ADR = 785, |
| 801 | AESD = 786, |
| 802 | AESE = 787, |
| 803 | AESIMC = 788, |
| 804 | AESMC = 789, |
| 805 | ANDri = 790, |
| 806 | ANDrr = 791, |
| 807 | ANDrsi = 792, |
| 808 | ANDrsr = 793, |
| 809 | BF16VDOTI_VDOTD = 794, |
| 810 | BF16VDOTI_VDOTQ = 795, |
| 811 | BF16VDOTS_VDOTD = 796, |
| 812 | BF16VDOTS_VDOTQ = 797, |
| 813 | BF16_VCVT = 798, |
| 814 | BF16_VCVTB = 799, |
| 815 | BF16_VCVTT = 800, |
| 816 | BFC = 801, |
| 817 | BFI = 802, |
| 818 | BICri = 803, |
| 819 | BICrr = 804, |
| 820 | BICrsi = 805, |
| 821 | BICrsr = 806, |
| 822 | BKPT = 807, |
| 823 | BL = 808, |
| 824 | BLX = 809, |
| 825 | BLX_pred = 810, |
| 826 | BLXi = 811, |
| 827 | BL_pred = 812, |
| 828 | BX = 813, |
| 829 | BXJ = 814, |
| 830 | BX_RET = 815, |
| 831 | BX_pred = 816, |
| 832 | Bcc = 817, |
| 833 | CDE_CX1 = 818, |
| 834 | CDE_CX1A = 819, |
| 835 | CDE_CX1D = 820, |
| 836 | CDE_CX1DA = 821, |
| 837 | CDE_CX2 = 822, |
| 838 | CDE_CX2A = 823, |
| 839 | CDE_CX2D = 824, |
| 840 | CDE_CX2DA = 825, |
| 841 | CDE_CX3 = 826, |
| 842 | CDE_CX3A = 827, |
| 843 | CDE_CX3D = 828, |
| 844 | CDE_CX3DA = 829, |
| 845 | CDE_VCX1A_fpdp = 830, |
| 846 | CDE_VCX1A_fpsp = 831, |
| 847 | CDE_VCX1A_vec = 832, |
| 848 | CDE_VCX1_fpdp = 833, |
| 849 | CDE_VCX1_fpsp = 834, |
| 850 | CDE_VCX1_vec = 835, |
| 851 | CDE_VCX2A_fpdp = 836, |
| 852 | CDE_VCX2A_fpsp = 837, |
| 853 | CDE_VCX2A_vec = 838, |
| 854 | CDE_VCX2_fpdp = 839, |
| 855 | CDE_VCX2_fpsp = 840, |
| 856 | CDE_VCX2_vec = 841, |
| 857 | CDE_VCX3A_fpdp = 842, |
| 858 | CDE_VCX3A_fpsp = 843, |
| 859 | CDE_VCX3A_vec = 844, |
| 860 | CDE_VCX3_fpdp = 845, |
| 861 | CDE_VCX3_fpsp = 846, |
| 862 | CDE_VCX3_vec = 847, |
| 863 | CDP = 848, |
| 864 | CDP2 = 849, |
| 865 | CLREX = 850, |
| 866 | CLZ = 851, |
| 867 | CMNri = 852, |
| 868 | CMNzrr = 853, |
| 869 | CMNzrsi = 854, |
| 870 | CMNzrsr = 855, |
| 871 | CMPri = 856, |
| 872 | CMPrr = 857, |
| 873 | CMPrsi = 858, |
| 874 | CMPrsr = 859, |
| 875 | CPS1p = 860, |
| 876 | CPS2p = 861, |
| 877 | CPS3p = 862, |
| 878 | CRC32B = 863, |
| 879 | CRC32CB = 864, |
| 880 | CRC32CH = 865, |
| 881 | CRC32CW = 866, |
| 882 | CRC32H = 867, |
| 883 | CRC32W = 868, |
| 884 | DBG = 869, |
| 885 | DMB = 870, |
| 886 | DSB = 871, |
| 887 | EORri = 872, |
| 888 | EORrr = 873, |
| 889 | EORrsi = 874, |
| 890 | EORrsr = 875, |
| 891 | ERET = 876, |
| 892 | FCONSTD = 877, |
| 893 | FCONSTH = 878, |
| 894 | FCONSTS = 879, |
| 895 | FLDMXDB_UPD = 880, |
| 896 | FLDMXIA = 881, |
| 897 | FLDMXIA_UPD = 882, |
| 898 | FMSTAT = 883, |
| 899 | FSTMXDB_UPD = 884, |
| 900 | FSTMXIA = 885, |
| 901 | FSTMXIA_UPD = 886, |
| 902 | HINT = 887, |
| 903 | HLT = 888, |
| 904 | HVC = 889, |
| 905 | ISB = 890, |
| 906 | LDA = 891, |
| 907 | LDAB = 892, |
| 908 | LDAEX = 893, |
| 909 | LDAEXB = 894, |
| 910 | LDAEXD = 895, |
| 911 | LDAEXH = 896, |
| 912 | LDAH = 897, |
| 913 | LDC2L_OFFSET = 898, |
| 914 | LDC2L_OPTION = 899, |
| 915 | LDC2L_POST = 900, |
| 916 | LDC2L_PRE = 901, |
| 917 | LDC2_OFFSET = 902, |
| 918 | LDC2_OPTION = 903, |
| 919 | LDC2_POST = 904, |
| 920 | LDC2_PRE = 905, |
| 921 | LDCL_OFFSET = 906, |
| 922 | LDCL_OPTION = 907, |
| 923 | LDCL_POST = 908, |
| 924 | LDCL_PRE = 909, |
| 925 | LDC_OFFSET = 910, |
| 926 | LDC_OPTION = 911, |
| 927 | LDC_POST = 912, |
| 928 | LDC_PRE = 913, |
| 929 | LDMDA = 914, |
| 930 | LDMDA_UPD = 915, |
| 931 | LDMDB = 916, |
| 932 | LDMDB_UPD = 917, |
| 933 | LDMIA = 918, |
| 934 | LDMIA_UPD = 919, |
| 935 | LDMIB = 920, |
| 936 | LDMIB_UPD = 921, |
| 937 | LDRBT_POST_IMM = 922, |
| 938 | LDRBT_POST_REG = 923, |
| 939 | LDRB_POST_IMM = 924, |
| 940 | LDRB_POST_REG = 925, |
| 941 | LDRB_PRE_IMM = 926, |
| 942 | LDRB_PRE_REG = 927, |
| 943 | LDRBi12 = 928, |
| 944 | LDRBrs = 929, |
| 945 | LDRD = 930, |
| 946 | LDRD_POST = 931, |
| 947 | LDRD_PRE = 932, |
| 948 | LDREX = 933, |
| 949 | LDREXB = 934, |
| 950 | LDREXD = 935, |
| 951 | LDREXH = 936, |
| 952 | LDRH = 937, |
| 953 | LDRHTi = 938, |
| 954 | LDRHTr = 939, |
| 955 | LDRH_POST = 940, |
| 956 | LDRH_PRE = 941, |
| 957 | LDRSB = 942, |
| 958 | LDRSBTi = 943, |
| 959 | LDRSBTr = 944, |
| 960 | LDRSB_POST = 945, |
| 961 | LDRSB_PRE = 946, |
| 962 | LDRSH = 947, |
| 963 | LDRSHTi = 948, |
| 964 | LDRSHTr = 949, |
| 965 | LDRSH_POST = 950, |
| 966 | LDRSH_PRE = 951, |
| 967 | LDRT_POST_IMM = 952, |
| 968 | LDRT_POST_REG = 953, |
| 969 | LDR_POST_IMM = 954, |
| 970 | LDR_POST_REG = 955, |
| 971 | LDR_PRE_IMM = 956, |
| 972 | LDR_PRE_REG = 957, |
| 973 | LDRcp = 958, |
| 974 | LDRi12 = 959, |
| 975 | LDRrs = 960, |
| 976 | MCR = 961, |
| 977 | MCR2 = 962, |
| 978 | MCRR = 963, |
| 979 | MCRR2 = 964, |
| 980 | MLA = 965, |
| 981 | MLS = 966, |
| 982 | MOVPCLR = 967, |
| 983 | MOVTi16 = 968, |
| 984 | MOVi = 969, |
| 985 | MOVi16 = 970, |
| 986 | MOVr = 971, |
| 987 | MOVr_TC = 972, |
| 988 | MOVsi = 973, |
| 989 | MOVsr = 974, |
| 990 | MRC = 975, |
| 991 | MRC2 = 976, |
| 992 | MRRC = 977, |
| 993 | MRRC2 = 978, |
| 994 | MRS = 979, |
| 995 | MRSbanked = 980, |
| 996 | MRSsys = 981, |
| 997 | MSR = 982, |
| 998 | MSRbanked = 983, |
| 999 | MSRi = 984, |
| 1000 | MUL = 985, |
| 1001 | MVE_ASRLi = 986, |
| 1002 | MVE_ASRLr = 987, |
| 1003 | MVE_DLSTP_16 = 988, |
| 1004 | MVE_DLSTP_32 = 989, |
| 1005 | MVE_DLSTP_64 = 990, |
| 1006 | MVE_DLSTP_8 = 991, |
| 1007 | MVE_LCTP = 992, |
| 1008 | MVE_LETP = 993, |
| 1009 | MVE_LSLLi = 994, |
| 1010 | MVE_LSLLr = 995, |
| 1011 | MVE_LSRL = 996, |
| 1012 | MVE_SQRSHR = 997, |
| 1013 | MVE_SQRSHRL = 998, |
| 1014 | MVE_SQSHL = 999, |
| 1015 | MVE_SQSHLL = 1000, |
| 1016 | MVE_SRSHR = 1001, |
| 1017 | MVE_SRSHRL = 1002, |
| 1018 | MVE_UQRSHL = 1003, |
| 1019 | MVE_UQRSHLL = 1004, |
| 1020 | MVE_UQSHL = 1005, |
| 1021 | MVE_UQSHLL = 1006, |
| 1022 | MVE_URSHR = 1007, |
| 1023 | MVE_URSHRL = 1008, |
| 1024 | MVE_VABAVs16 = 1009, |
| 1025 | MVE_VABAVs32 = 1010, |
| 1026 | MVE_VABAVs8 = 1011, |
| 1027 | MVE_VABAVu16 = 1012, |
| 1028 | MVE_VABAVu32 = 1013, |
| 1029 | MVE_VABAVu8 = 1014, |
| 1030 | MVE_VABDf16 = 1015, |
| 1031 | MVE_VABDf32 = 1016, |
| 1032 | MVE_VABDs16 = 1017, |
| 1033 | MVE_VABDs32 = 1018, |
| 1034 | MVE_VABDs8 = 1019, |
| 1035 | MVE_VABDu16 = 1020, |
| 1036 | MVE_VABDu32 = 1021, |
| 1037 | MVE_VABDu8 = 1022, |
| 1038 | MVE_VABSf16 = 1023, |
| 1039 | MVE_VABSf32 = 1024, |
| 1040 | MVE_VABSs16 = 1025, |
| 1041 | MVE_VABSs32 = 1026, |
| 1042 | MVE_VABSs8 = 1027, |
| 1043 | MVE_VADC = 1028, |
| 1044 | MVE_VADCI = 1029, |
| 1045 | MVE_VADDLVs32acc = 1030, |
| 1046 | MVE_VADDLVs32no_acc = 1031, |
| 1047 | MVE_VADDLVu32acc = 1032, |
| 1048 | MVE_VADDLVu32no_acc = 1033, |
| 1049 | MVE_VADDVs16acc = 1034, |
| 1050 | MVE_VADDVs16no_acc = 1035, |
| 1051 | MVE_VADDVs32acc = 1036, |
| 1052 | MVE_VADDVs32no_acc = 1037, |
| 1053 | MVE_VADDVs8acc = 1038, |
| 1054 | MVE_VADDVs8no_acc = 1039, |
| 1055 | MVE_VADDVu16acc = 1040, |
| 1056 | MVE_VADDVu16no_acc = 1041, |
| 1057 | MVE_VADDVu32acc = 1042, |
| 1058 | MVE_VADDVu32no_acc = 1043, |
| 1059 | MVE_VADDVu8acc = 1044, |
| 1060 | MVE_VADDVu8no_acc = 1045, |
| 1061 | MVE_VADD_qr_f16 = 1046, |
| 1062 | MVE_VADD_qr_f32 = 1047, |
| 1063 | MVE_VADD_qr_i16 = 1048, |
| 1064 | MVE_VADD_qr_i32 = 1049, |
| 1065 | MVE_VADD_qr_i8 = 1050, |
| 1066 | MVE_VADDf16 = 1051, |
| 1067 | MVE_VADDf32 = 1052, |
| 1068 | MVE_VADDi16 = 1053, |
| 1069 | MVE_VADDi32 = 1054, |
| 1070 | MVE_VADDi8 = 1055, |
| 1071 | MVE_VAND = 1056, |
| 1072 | MVE_VBIC = 1057, |
| 1073 | MVE_VBICimmi16 = 1058, |
| 1074 | MVE_VBICimmi32 = 1059, |
| 1075 | MVE_VBRSR16 = 1060, |
| 1076 | MVE_VBRSR32 = 1061, |
| 1077 | MVE_VBRSR8 = 1062, |
| 1078 | MVE_VCADDf16 = 1063, |
| 1079 | MVE_VCADDf32 = 1064, |
| 1080 | MVE_VCADDi16 = 1065, |
| 1081 | MVE_VCADDi32 = 1066, |
| 1082 | MVE_VCADDi8 = 1067, |
| 1083 | MVE_VCLSs16 = 1068, |
| 1084 | MVE_VCLSs32 = 1069, |
| 1085 | MVE_VCLSs8 = 1070, |
| 1086 | MVE_VCLZs16 = 1071, |
| 1087 | MVE_VCLZs32 = 1072, |
| 1088 | MVE_VCLZs8 = 1073, |
| 1089 | MVE_VCMLAf16 = 1074, |
| 1090 | MVE_VCMLAf32 = 1075, |
| 1091 | MVE_VCMPf16 = 1076, |
| 1092 | MVE_VCMPf16r = 1077, |
| 1093 | MVE_VCMPf32 = 1078, |
| 1094 | MVE_VCMPf32r = 1079, |
| 1095 | MVE_VCMPi16 = 1080, |
| 1096 | MVE_VCMPi16r = 1081, |
| 1097 | MVE_VCMPi32 = 1082, |
| 1098 | MVE_VCMPi32r = 1083, |
| 1099 | MVE_VCMPi8 = 1084, |
| 1100 | MVE_VCMPi8r = 1085, |
| 1101 | MVE_VCMPs16 = 1086, |
| 1102 | MVE_VCMPs16r = 1087, |
| 1103 | MVE_VCMPs32 = 1088, |
| 1104 | MVE_VCMPs32r = 1089, |
| 1105 | MVE_VCMPs8 = 1090, |
| 1106 | MVE_VCMPs8r = 1091, |
| 1107 | MVE_VCMPu16 = 1092, |
| 1108 | MVE_VCMPu16r = 1093, |
| 1109 | MVE_VCMPu32 = 1094, |
| 1110 | MVE_VCMPu32r = 1095, |
| 1111 | MVE_VCMPu8 = 1096, |
| 1112 | MVE_VCMPu8r = 1097, |
| 1113 | MVE_VCMULf16 = 1098, |
| 1114 | MVE_VCMULf32 = 1099, |
| 1115 | MVE_VCTP16 = 1100, |
| 1116 | MVE_VCTP32 = 1101, |
| 1117 | MVE_VCTP64 = 1102, |
| 1118 | MVE_VCTP8 = 1103, |
| 1119 | MVE_VCVTf16f32bh = 1104, |
| 1120 | MVE_VCVTf16f32th = 1105, |
| 1121 | MVE_VCVTf16s16_fix = 1106, |
| 1122 | MVE_VCVTf16s16n = 1107, |
| 1123 | MVE_VCVTf16u16_fix = 1108, |
| 1124 | MVE_VCVTf16u16n = 1109, |
| 1125 | MVE_VCVTf32f16bh = 1110, |
| 1126 | MVE_VCVTf32f16th = 1111, |
| 1127 | MVE_VCVTf32s32_fix = 1112, |
| 1128 | MVE_VCVTf32s32n = 1113, |
| 1129 | MVE_VCVTf32u32_fix = 1114, |
| 1130 | MVE_VCVTf32u32n = 1115, |
| 1131 | MVE_VCVTs16f16_fix = 1116, |
| 1132 | MVE_VCVTs16f16a = 1117, |
| 1133 | MVE_VCVTs16f16m = 1118, |
| 1134 | MVE_VCVTs16f16n = 1119, |
| 1135 | MVE_VCVTs16f16p = 1120, |
| 1136 | MVE_VCVTs16f16z = 1121, |
| 1137 | MVE_VCVTs32f32_fix = 1122, |
| 1138 | MVE_VCVTs32f32a = 1123, |
| 1139 | MVE_VCVTs32f32m = 1124, |
| 1140 | MVE_VCVTs32f32n = 1125, |
| 1141 | MVE_VCVTs32f32p = 1126, |
| 1142 | MVE_VCVTs32f32z = 1127, |
| 1143 | MVE_VCVTu16f16_fix = 1128, |
| 1144 | MVE_VCVTu16f16a = 1129, |
| 1145 | MVE_VCVTu16f16m = 1130, |
| 1146 | MVE_VCVTu16f16n = 1131, |
| 1147 | MVE_VCVTu16f16p = 1132, |
| 1148 | MVE_VCVTu16f16z = 1133, |
| 1149 | MVE_VCVTu32f32_fix = 1134, |
| 1150 | MVE_VCVTu32f32a = 1135, |
| 1151 | MVE_VCVTu32f32m = 1136, |
| 1152 | MVE_VCVTu32f32n = 1137, |
| 1153 | MVE_VCVTu32f32p = 1138, |
| 1154 | MVE_VCVTu32f32z = 1139, |
| 1155 | MVE_VDDUPu16 = 1140, |
| 1156 | MVE_VDDUPu32 = 1141, |
| 1157 | MVE_VDDUPu8 = 1142, |
| 1158 | MVE_VDUP16 = 1143, |
| 1159 | MVE_VDUP32 = 1144, |
| 1160 | MVE_VDUP8 = 1145, |
| 1161 | MVE_VDWDUPu16 = 1146, |
| 1162 | MVE_VDWDUPu32 = 1147, |
| 1163 | MVE_VDWDUPu8 = 1148, |
| 1164 | MVE_VEOR = 1149, |
| 1165 | MVE_VFMA_qr_Sf16 = 1150, |
| 1166 | MVE_VFMA_qr_Sf32 = 1151, |
| 1167 | MVE_VFMA_qr_f16 = 1152, |
| 1168 | MVE_VFMA_qr_f32 = 1153, |
| 1169 | MVE_VFMAf16 = 1154, |
| 1170 | MVE_VFMAf32 = 1155, |
| 1171 | MVE_VFMSf16 = 1156, |
| 1172 | MVE_VFMSf32 = 1157, |
| 1173 | MVE_VHADD_qr_s16 = 1158, |
| 1174 | MVE_VHADD_qr_s32 = 1159, |
| 1175 | MVE_VHADD_qr_s8 = 1160, |
| 1176 | MVE_VHADD_qr_u16 = 1161, |
| 1177 | MVE_VHADD_qr_u32 = 1162, |
| 1178 | MVE_VHADD_qr_u8 = 1163, |
| 1179 | MVE_VHADDs16 = 1164, |
| 1180 | MVE_VHADDs32 = 1165, |
| 1181 | MVE_VHADDs8 = 1166, |
| 1182 | MVE_VHADDu16 = 1167, |
| 1183 | MVE_VHADDu32 = 1168, |
| 1184 | MVE_VHADDu8 = 1169, |
| 1185 | MVE_VHCADDs16 = 1170, |
| 1186 | MVE_VHCADDs32 = 1171, |
| 1187 | MVE_VHCADDs8 = 1172, |
| 1188 | MVE_VHSUB_qr_s16 = 1173, |
| 1189 | MVE_VHSUB_qr_s32 = 1174, |
| 1190 | MVE_VHSUB_qr_s8 = 1175, |
| 1191 | MVE_VHSUB_qr_u16 = 1176, |
| 1192 | MVE_VHSUB_qr_u32 = 1177, |
| 1193 | MVE_VHSUB_qr_u8 = 1178, |
| 1194 | MVE_VHSUBs16 = 1179, |
| 1195 | MVE_VHSUBs32 = 1180, |
| 1196 | MVE_VHSUBs8 = 1181, |
| 1197 | MVE_VHSUBu16 = 1182, |
| 1198 | MVE_VHSUBu32 = 1183, |
| 1199 | MVE_VHSUBu8 = 1184, |
| 1200 | MVE_VIDUPu16 = 1185, |
| 1201 | MVE_VIDUPu32 = 1186, |
| 1202 | MVE_VIDUPu8 = 1187, |
| 1203 | MVE_VIWDUPu16 = 1188, |
| 1204 | MVE_VIWDUPu32 = 1189, |
| 1205 | MVE_VIWDUPu8 = 1190, |
| 1206 | MVE_VLD20_16 = 1191, |
| 1207 | MVE_VLD20_16_wb = 1192, |
| 1208 | MVE_VLD20_32 = 1193, |
| 1209 | MVE_VLD20_32_wb = 1194, |
| 1210 | MVE_VLD20_8 = 1195, |
| 1211 | MVE_VLD20_8_wb = 1196, |
| 1212 | MVE_VLD21_16 = 1197, |
| 1213 | MVE_VLD21_16_wb = 1198, |
| 1214 | MVE_VLD21_32 = 1199, |
| 1215 | MVE_VLD21_32_wb = 1200, |
| 1216 | MVE_VLD21_8 = 1201, |
| 1217 | MVE_VLD21_8_wb = 1202, |
| 1218 | MVE_VLD40_16 = 1203, |
| 1219 | MVE_VLD40_16_wb = 1204, |
| 1220 | MVE_VLD40_32 = 1205, |
| 1221 | MVE_VLD40_32_wb = 1206, |
| 1222 | MVE_VLD40_8 = 1207, |
| 1223 | MVE_VLD40_8_wb = 1208, |
| 1224 | MVE_VLD41_16 = 1209, |
| 1225 | MVE_VLD41_16_wb = 1210, |
| 1226 | MVE_VLD41_32 = 1211, |
| 1227 | MVE_VLD41_32_wb = 1212, |
| 1228 | MVE_VLD41_8 = 1213, |
| 1229 | MVE_VLD41_8_wb = 1214, |
| 1230 | MVE_VLD42_16 = 1215, |
| 1231 | MVE_VLD42_16_wb = 1216, |
| 1232 | MVE_VLD42_32 = 1217, |
| 1233 | MVE_VLD42_32_wb = 1218, |
| 1234 | MVE_VLD42_8 = 1219, |
| 1235 | MVE_VLD42_8_wb = 1220, |
| 1236 | MVE_VLD43_16 = 1221, |
| 1237 | MVE_VLD43_16_wb = 1222, |
| 1238 | MVE_VLD43_32 = 1223, |
| 1239 | MVE_VLD43_32_wb = 1224, |
| 1240 | MVE_VLD43_8 = 1225, |
| 1241 | MVE_VLD43_8_wb = 1226, |
| 1242 | MVE_VLDRBS16 = 1227, |
| 1243 | MVE_VLDRBS16_post = 1228, |
| 1244 | MVE_VLDRBS16_pre = 1229, |
| 1245 | MVE_VLDRBS16_rq = 1230, |
| 1246 | MVE_VLDRBS32 = 1231, |
| 1247 | MVE_VLDRBS32_post = 1232, |
| 1248 | MVE_VLDRBS32_pre = 1233, |
| 1249 | MVE_VLDRBS32_rq = 1234, |
| 1250 | MVE_VLDRBU16 = 1235, |
| 1251 | MVE_VLDRBU16_post = 1236, |
| 1252 | MVE_VLDRBU16_pre = 1237, |
| 1253 | MVE_VLDRBU16_rq = 1238, |
| 1254 | MVE_VLDRBU32 = 1239, |
| 1255 | MVE_VLDRBU32_post = 1240, |
| 1256 | MVE_VLDRBU32_pre = 1241, |
| 1257 | MVE_VLDRBU32_rq = 1242, |
| 1258 | MVE_VLDRBU8 = 1243, |
| 1259 | MVE_VLDRBU8_post = 1244, |
| 1260 | MVE_VLDRBU8_pre = 1245, |
| 1261 | MVE_VLDRBU8_rq = 1246, |
| 1262 | MVE_VLDRDU64_qi = 1247, |
| 1263 | MVE_VLDRDU64_qi_pre = 1248, |
| 1264 | MVE_VLDRDU64_rq = 1249, |
| 1265 | MVE_VLDRDU64_rq_u = 1250, |
| 1266 | MVE_VLDRHS32 = 1251, |
| 1267 | MVE_VLDRHS32_post = 1252, |
| 1268 | MVE_VLDRHS32_pre = 1253, |
| 1269 | MVE_VLDRHS32_rq = 1254, |
| 1270 | MVE_VLDRHS32_rq_u = 1255, |
| 1271 | MVE_VLDRHU16 = 1256, |
| 1272 | MVE_VLDRHU16_post = 1257, |
| 1273 | MVE_VLDRHU16_pre = 1258, |
| 1274 | MVE_VLDRHU16_rq = 1259, |
| 1275 | MVE_VLDRHU16_rq_u = 1260, |
| 1276 | MVE_VLDRHU32 = 1261, |
| 1277 | MVE_VLDRHU32_post = 1262, |
| 1278 | MVE_VLDRHU32_pre = 1263, |
| 1279 | MVE_VLDRHU32_rq = 1264, |
| 1280 | MVE_VLDRHU32_rq_u = 1265, |
| 1281 | MVE_VLDRWU32 = 1266, |
| 1282 | MVE_VLDRWU32_post = 1267, |
| 1283 | MVE_VLDRWU32_pre = 1268, |
| 1284 | MVE_VLDRWU32_qi = 1269, |
| 1285 | MVE_VLDRWU32_qi_pre = 1270, |
| 1286 | MVE_VLDRWU32_rq = 1271, |
| 1287 | MVE_VLDRWU32_rq_u = 1272, |
| 1288 | MVE_VMAXAVs16 = 1273, |
| 1289 | MVE_VMAXAVs32 = 1274, |
| 1290 | MVE_VMAXAVs8 = 1275, |
| 1291 | MVE_VMAXAs16 = 1276, |
| 1292 | MVE_VMAXAs32 = 1277, |
| 1293 | MVE_VMAXAs8 = 1278, |
| 1294 | MVE_VMAXNMAVf16 = 1279, |
| 1295 | MVE_VMAXNMAVf32 = 1280, |
| 1296 | MVE_VMAXNMAf16 = 1281, |
| 1297 | MVE_VMAXNMAf32 = 1282, |
| 1298 | MVE_VMAXNMVf16 = 1283, |
| 1299 | MVE_VMAXNMVf32 = 1284, |
| 1300 | MVE_VMAXNMf16 = 1285, |
| 1301 | MVE_VMAXNMf32 = 1286, |
| 1302 | MVE_VMAXVs16 = 1287, |
| 1303 | MVE_VMAXVs32 = 1288, |
| 1304 | MVE_VMAXVs8 = 1289, |
| 1305 | MVE_VMAXVu16 = 1290, |
| 1306 | MVE_VMAXVu32 = 1291, |
| 1307 | MVE_VMAXVu8 = 1292, |
| 1308 | MVE_VMAXs16 = 1293, |
| 1309 | MVE_VMAXs32 = 1294, |
| 1310 | MVE_VMAXs8 = 1295, |
| 1311 | MVE_VMAXu16 = 1296, |
| 1312 | MVE_VMAXu32 = 1297, |
| 1313 | MVE_VMAXu8 = 1298, |
| 1314 | MVE_VMINAVs16 = 1299, |
| 1315 | MVE_VMINAVs32 = 1300, |
| 1316 | MVE_VMINAVs8 = 1301, |
| 1317 | MVE_VMINAs16 = 1302, |
| 1318 | MVE_VMINAs32 = 1303, |
| 1319 | MVE_VMINAs8 = 1304, |
| 1320 | MVE_VMINNMAVf16 = 1305, |
| 1321 | MVE_VMINNMAVf32 = 1306, |
| 1322 | MVE_VMINNMAf16 = 1307, |
| 1323 | MVE_VMINNMAf32 = 1308, |
| 1324 | MVE_VMINNMVf16 = 1309, |
| 1325 | MVE_VMINNMVf32 = 1310, |
| 1326 | MVE_VMINNMf16 = 1311, |
| 1327 | MVE_VMINNMf32 = 1312, |
| 1328 | MVE_VMINVs16 = 1313, |
| 1329 | MVE_VMINVs32 = 1314, |
| 1330 | MVE_VMINVs8 = 1315, |
| 1331 | MVE_VMINVu16 = 1316, |
| 1332 | MVE_VMINVu32 = 1317, |
| 1333 | MVE_VMINVu8 = 1318, |
| 1334 | MVE_VMINs16 = 1319, |
| 1335 | MVE_VMINs32 = 1320, |
| 1336 | MVE_VMINs8 = 1321, |
| 1337 | MVE_VMINu16 = 1322, |
| 1338 | MVE_VMINu32 = 1323, |
| 1339 | MVE_VMINu8 = 1324, |
| 1340 | MVE_VMLADAVas16 = 1325, |
| 1341 | MVE_VMLADAVas32 = 1326, |
| 1342 | MVE_VMLADAVas8 = 1327, |
| 1343 | MVE_VMLADAVau16 = 1328, |
| 1344 | MVE_VMLADAVau32 = 1329, |
| 1345 | MVE_VMLADAVau8 = 1330, |
| 1346 | MVE_VMLADAVaxs16 = 1331, |
| 1347 | MVE_VMLADAVaxs32 = 1332, |
| 1348 | MVE_VMLADAVaxs8 = 1333, |
| 1349 | MVE_VMLADAVs16 = 1334, |
| 1350 | MVE_VMLADAVs32 = 1335, |
| 1351 | MVE_VMLADAVs8 = 1336, |
| 1352 | MVE_VMLADAVu16 = 1337, |
| 1353 | MVE_VMLADAVu32 = 1338, |
| 1354 | MVE_VMLADAVu8 = 1339, |
| 1355 | MVE_VMLADAVxs16 = 1340, |
| 1356 | MVE_VMLADAVxs32 = 1341, |
| 1357 | MVE_VMLADAVxs8 = 1342, |
| 1358 | MVE_VMLALDAVas16 = 1343, |
| 1359 | MVE_VMLALDAVas32 = 1344, |
| 1360 | MVE_VMLALDAVau16 = 1345, |
| 1361 | MVE_VMLALDAVau32 = 1346, |
| 1362 | MVE_VMLALDAVaxs16 = 1347, |
| 1363 | MVE_VMLALDAVaxs32 = 1348, |
| 1364 | MVE_VMLALDAVs16 = 1349, |
| 1365 | MVE_VMLALDAVs32 = 1350, |
| 1366 | MVE_VMLALDAVu16 = 1351, |
| 1367 | MVE_VMLALDAVu32 = 1352, |
| 1368 | MVE_VMLALDAVxs16 = 1353, |
| 1369 | MVE_VMLALDAVxs32 = 1354, |
| 1370 | MVE_VMLAS_qr_i16 = 1355, |
| 1371 | MVE_VMLAS_qr_i32 = 1356, |
| 1372 | MVE_VMLAS_qr_i8 = 1357, |
| 1373 | MVE_VMLA_qr_i16 = 1358, |
| 1374 | MVE_VMLA_qr_i32 = 1359, |
| 1375 | MVE_VMLA_qr_i8 = 1360, |
| 1376 | MVE_VMLSDAVas16 = 1361, |
| 1377 | MVE_VMLSDAVas32 = 1362, |
| 1378 | MVE_VMLSDAVas8 = 1363, |
| 1379 | MVE_VMLSDAVaxs16 = 1364, |
| 1380 | MVE_VMLSDAVaxs32 = 1365, |
| 1381 | MVE_VMLSDAVaxs8 = 1366, |
| 1382 | MVE_VMLSDAVs16 = 1367, |
| 1383 | MVE_VMLSDAVs32 = 1368, |
| 1384 | MVE_VMLSDAVs8 = 1369, |
| 1385 | MVE_VMLSDAVxs16 = 1370, |
| 1386 | MVE_VMLSDAVxs32 = 1371, |
| 1387 | MVE_VMLSDAVxs8 = 1372, |
| 1388 | MVE_VMLSLDAVas16 = 1373, |
| 1389 | MVE_VMLSLDAVas32 = 1374, |
| 1390 | MVE_VMLSLDAVaxs16 = 1375, |
| 1391 | MVE_VMLSLDAVaxs32 = 1376, |
| 1392 | MVE_VMLSLDAVs16 = 1377, |
| 1393 | MVE_VMLSLDAVs32 = 1378, |
| 1394 | MVE_VMLSLDAVxs16 = 1379, |
| 1395 | MVE_VMLSLDAVxs32 = 1380, |
| 1396 | MVE_VMOVLs16bh = 1381, |
| 1397 | MVE_VMOVLs16th = 1382, |
| 1398 | MVE_VMOVLs8bh = 1383, |
| 1399 | MVE_VMOVLs8th = 1384, |
| 1400 | MVE_VMOVLu16bh = 1385, |
| 1401 | MVE_VMOVLu16th = 1386, |
| 1402 | MVE_VMOVLu8bh = 1387, |
| 1403 | MVE_VMOVLu8th = 1388, |
| 1404 | MVE_VMOVNi16bh = 1389, |
| 1405 | MVE_VMOVNi16th = 1390, |
| 1406 | MVE_VMOVNi32bh = 1391, |
| 1407 | MVE_VMOVNi32th = 1392, |
| 1408 | MVE_VMOV_from_lane_32 = 1393, |
| 1409 | MVE_VMOV_from_lane_s16 = 1394, |
| 1410 | MVE_VMOV_from_lane_s8 = 1395, |
| 1411 | MVE_VMOV_from_lane_u16 = 1396, |
| 1412 | MVE_VMOV_from_lane_u8 = 1397, |
| 1413 | MVE_VMOV_q_rr = 1398, |
| 1414 | MVE_VMOV_rr_q = 1399, |
| 1415 | MVE_VMOV_to_lane_16 = 1400, |
| 1416 | MVE_VMOV_to_lane_32 = 1401, |
| 1417 | MVE_VMOV_to_lane_8 = 1402, |
| 1418 | MVE_VMOVimmf32 = 1403, |
| 1419 | MVE_VMOVimmi16 = 1404, |
| 1420 | MVE_VMOVimmi32 = 1405, |
| 1421 | MVE_VMOVimmi64 = 1406, |
| 1422 | MVE_VMOVimmi8 = 1407, |
| 1423 | MVE_VMULHs16 = 1408, |
| 1424 | MVE_VMULHs32 = 1409, |
| 1425 | MVE_VMULHs8 = 1410, |
| 1426 | MVE_VMULHu16 = 1411, |
| 1427 | MVE_VMULHu32 = 1412, |
| 1428 | MVE_VMULHu8 = 1413, |
| 1429 | MVE_VMULLBp16 = 1414, |
| 1430 | MVE_VMULLBp8 = 1415, |
| 1431 | MVE_VMULLBs16 = 1416, |
| 1432 | MVE_VMULLBs32 = 1417, |
| 1433 | MVE_VMULLBs8 = 1418, |
| 1434 | MVE_VMULLBu16 = 1419, |
| 1435 | MVE_VMULLBu32 = 1420, |
| 1436 | MVE_VMULLBu8 = 1421, |
| 1437 | MVE_VMULLTp16 = 1422, |
| 1438 | MVE_VMULLTp8 = 1423, |
| 1439 | MVE_VMULLTs16 = 1424, |
| 1440 | MVE_VMULLTs32 = 1425, |
| 1441 | MVE_VMULLTs8 = 1426, |
| 1442 | MVE_VMULLTu16 = 1427, |
| 1443 | MVE_VMULLTu32 = 1428, |
| 1444 | MVE_VMULLTu8 = 1429, |
| 1445 | MVE_VMUL_qr_f16 = 1430, |
| 1446 | MVE_VMUL_qr_f32 = 1431, |
| 1447 | MVE_VMUL_qr_i16 = 1432, |
| 1448 | MVE_VMUL_qr_i32 = 1433, |
| 1449 | MVE_VMUL_qr_i8 = 1434, |
| 1450 | MVE_VMULf16 = 1435, |
| 1451 | MVE_VMULf32 = 1436, |
| 1452 | MVE_VMULi16 = 1437, |
| 1453 | MVE_VMULi32 = 1438, |
| 1454 | MVE_VMULi8 = 1439, |
| 1455 | MVE_VMVN = 1440, |
| 1456 | MVE_VMVNimmi16 = 1441, |
| 1457 | MVE_VMVNimmi32 = 1442, |
| 1458 | MVE_VNEGf16 = 1443, |
| 1459 | MVE_VNEGf32 = 1444, |
| 1460 | MVE_VNEGs16 = 1445, |
| 1461 | MVE_VNEGs32 = 1446, |
| 1462 | MVE_VNEGs8 = 1447, |
| 1463 | MVE_VORN = 1448, |
| 1464 | MVE_VORR = 1449, |
| 1465 | MVE_VORRimmi16 = 1450, |
| 1466 | MVE_VORRimmi32 = 1451, |
| 1467 | MVE_VPNOT = 1452, |
| 1468 | MVE_VPSEL = 1453, |
| 1469 | MVE_VPST = 1454, |
| 1470 | MVE_VPTv16i8 = 1455, |
| 1471 | MVE_VPTv16i8r = 1456, |
| 1472 | MVE_VPTv16s8 = 1457, |
| 1473 | MVE_VPTv16s8r = 1458, |
| 1474 | MVE_VPTv16u8 = 1459, |
| 1475 | MVE_VPTv16u8r = 1460, |
| 1476 | MVE_VPTv4f32 = 1461, |
| 1477 | MVE_VPTv4f32r = 1462, |
| 1478 | MVE_VPTv4i32 = 1463, |
| 1479 | MVE_VPTv4i32r = 1464, |
| 1480 | MVE_VPTv4s32 = 1465, |
| 1481 | MVE_VPTv4s32r = 1466, |
| 1482 | MVE_VPTv4u32 = 1467, |
| 1483 | MVE_VPTv4u32r = 1468, |
| 1484 | MVE_VPTv8f16 = 1469, |
| 1485 | MVE_VPTv8f16r = 1470, |
| 1486 | MVE_VPTv8i16 = 1471, |
| 1487 | MVE_VPTv8i16r = 1472, |
| 1488 | MVE_VPTv8s16 = 1473, |
| 1489 | MVE_VPTv8s16r = 1474, |
| 1490 | MVE_VPTv8u16 = 1475, |
| 1491 | MVE_VPTv8u16r = 1476, |
| 1492 | MVE_VQABSs16 = 1477, |
| 1493 | MVE_VQABSs32 = 1478, |
| 1494 | MVE_VQABSs8 = 1479, |
| 1495 | MVE_VQADD_qr_s16 = 1480, |
| 1496 | MVE_VQADD_qr_s32 = 1481, |
| 1497 | MVE_VQADD_qr_s8 = 1482, |
| 1498 | MVE_VQADD_qr_u16 = 1483, |
| 1499 | MVE_VQADD_qr_u32 = 1484, |
| 1500 | MVE_VQADD_qr_u8 = 1485, |
| 1501 | MVE_VQADDs16 = 1486, |
| 1502 | MVE_VQADDs32 = 1487, |
| 1503 | MVE_VQADDs8 = 1488, |
| 1504 | MVE_VQADDu16 = 1489, |
| 1505 | MVE_VQADDu32 = 1490, |
| 1506 | MVE_VQADDu8 = 1491, |
| 1507 | MVE_VQDMLADHXs16 = 1492, |
| 1508 | MVE_VQDMLADHXs32 = 1493, |
| 1509 | MVE_VQDMLADHXs8 = 1494, |
| 1510 | MVE_VQDMLADHs16 = 1495, |
| 1511 | MVE_VQDMLADHs32 = 1496, |
| 1512 | MVE_VQDMLADHs8 = 1497, |
| 1513 | MVE_VQDMLAH_qrs16 = 1498, |
| 1514 | MVE_VQDMLAH_qrs32 = 1499, |
| 1515 | MVE_VQDMLAH_qrs8 = 1500, |
| 1516 | MVE_VQDMLASH_qrs16 = 1501, |
| 1517 | MVE_VQDMLASH_qrs32 = 1502, |
| 1518 | MVE_VQDMLASH_qrs8 = 1503, |
| 1519 | MVE_VQDMLSDHXs16 = 1504, |
| 1520 | MVE_VQDMLSDHXs32 = 1505, |
| 1521 | MVE_VQDMLSDHXs8 = 1506, |
| 1522 | MVE_VQDMLSDHs16 = 1507, |
| 1523 | MVE_VQDMLSDHs32 = 1508, |
| 1524 | MVE_VQDMLSDHs8 = 1509, |
| 1525 | MVE_VQDMULH_qr_s16 = 1510, |
| 1526 | MVE_VQDMULH_qr_s32 = 1511, |
| 1527 | MVE_VQDMULH_qr_s8 = 1512, |
| 1528 | MVE_VQDMULHi16 = 1513, |
| 1529 | MVE_VQDMULHi32 = 1514, |
| 1530 | MVE_VQDMULHi8 = 1515, |
| 1531 | MVE_VQDMULL_qr_s16bh = 1516, |
| 1532 | MVE_VQDMULL_qr_s16th = 1517, |
| 1533 | MVE_VQDMULL_qr_s32bh = 1518, |
| 1534 | MVE_VQDMULL_qr_s32th = 1519, |
| 1535 | MVE_VQDMULLs16bh = 1520, |
| 1536 | MVE_VQDMULLs16th = 1521, |
| 1537 | MVE_VQDMULLs32bh = 1522, |
| 1538 | MVE_VQDMULLs32th = 1523, |
| 1539 | MVE_VQMOVNs16bh = 1524, |
| 1540 | MVE_VQMOVNs16th = 1525, |
| 1541 | MVE_VQMOVNs32bh = 1526, |
| 1542 | MVE_VQMOVNs32th = 1527, |
| 1543 | MVE_VQMOVNu16bh = 1528, |
| 1544 | MVE_VQMOVNu16th = 1529, |
| 1545 | MVE_VQMOVNu32bh = 1530, |
| 1546 | MVE_VQMOVNu32th = 1531, |
| 1547 | MVE_VQMOVUNs16bh = 1532, |
| 1548 | MVE_VQMOVUNs16th = 1533, |
| 1549 | MVE_VQMOVUNs32bh = 1534, |
| 1550 | MVE_VQMOVUNs32th = 1535, |
| 1551 | MVE_VQNEGs16 = 1536, |
| 1552 | MVE_VQNEGs32 = 1537, |
| 1553 | MVE_VQNEGs8 = 1538, |
| 1554 | MVE_VQRDMLADHXs16 = 1539, |
| 1555 | MVE_VQRDMLADHXs32 = 1540, |
| 1556 | MVE_VQRDMLADHXs8 = 1541, |
| 1557 | MVE_VQRDMLADHs16 = 1542, |
| 1558 | MVE_VQRDMLADHs32 = 1543, |
| 1559 | MVE_VQRDMLADHs8 = 1544, |
| 1560 | MVE_VQRDMLAH_qrs16 = 1545, |
| 1561 | MVE_VQRDMLAH_qrs32 = 1546, |
| 1562 | MVE_VQRDMLAH_qrs8 = 1547, |
| 1563 | MVE_VQRDMLASH_qrs16 = 1548, |
| 1564 | MVE_VQRDMLASH_qrs32 = 1549, |
| 1565 | MVE_VQRDMLASH_qrs8 = 1550, |
| 1566 | MVE_VQRDMLSDHXs16 = 1551, |
| 1567 | MVE_VQRDMLSDHXs32 = 1552, |
| 1568 | MVE_VQRDMLSDHXs8 = 1553, |
| 1569 | MVE_VQRDMLSDHs16 = 1554, |
| 1570 | MVE_VQRDMLSDHs32 = 1555, |
| 1571 | MVE_VQRDMLSDHs8 = 1556, |
| 1572 | MVE_VQRDMULH_qr_s16 = 1557, |
| 1573 | MVE_VQRDMULH_qr_s32 = 1558, |
| 1574 | MVE_VQRDMULH_qr_s8 = 1559, |
| 1575 | MVE_VQRDMULHi16 = 1560, |
| 1576 | MVE_VQRDMULHi32 = 1561, |
| 1577 | MVE_VQRDMULHi8 = 1562, |
| 1578 | MVE_VQRSHL_by_vecs16 = 1563, |
| 1579 | MVE_VQRSHL_by_vecs32 = 1564, |
| 1580 | MVE_VQRSHL_by_vecs8 = 1565, |
| 1581 | MVE_VQRSHL_by_vecu16 = 1566, |
| 1582 | MVE_VQRSHL_by_vecu32 = 1567, |
| 1583 | MVE_VQRSHL_by_vecu8 = 1568, |
| 1584 | MVE_VQRSHL_qrs16 = 1569, |
| 1585 | MVE_VQRSHL_qrs32 = 1570, |
| 1586 | MVE_VQRSHL_qrs8 = 1571, |
| 1587 | MVE_VQRSHL_qru16 = 1572, |
| 1588 | MVE_VQRSHL_qru32 = 1573, |
| 1589 | MVE_VQRSHL_qru8 = 1574, |
| 1590 | MVE_VQRSHRNbhs16 = 1575, |
| 1591 | MVE_VQRSHRNbhs32 = 1576, |
| 1592 | MVE_VQRSHRNbhu16 = 1577, |
| 1593 | MVE_VQRSHRNbhu32 = 1578, |
| 1594 | MVE_VQRSHRNths16 = 1579, |
| 1595 | MVE_VQRSHRNths32 = 1580, |
| 1596 | MVE_VQRSHRNthu16 = 1581, |
| 1597 | MVE_VQRSHRNthu32 = 1582, |
| 1598 | MVE_VQRSHRUNs16bh = 1583, |
| 1599 | MVE_VQRSHRUNs16th = 1584, |
| 1600 | MVE_VQRSHRUNs32bh = 1585, |
| 1601 | MVE_VQRSHRUNs32th = 1586, |
| 1602 | MVE_VQSHLU_imms16 = 1587, |
| 1603 | MVE_VQSHLU_imms32 = 1588, |
| 1604 | MVE_VQSHLU_imms8 = 1589, |
| 1605 | MVE_VQSHL_by_vecs16 = 1590, |
| 1606 | MVE_VQSHL_by_vecs32 = 1591, |
| 1607 | MVE_VQSHL_by_vecs8 = 1592, |
| 1608 | MVE_VQSHL_by_vecu16 = 1593, |
| 1609 | MVE_VQSHL_by_vecu32 = 1594, |
| 1610 | MVE_VQSHL_by_vecu8 = 1595, |
| 1611 | MVE_VQSHL_qrs16 = 1596, |
| 1612 | MVE_VQSHL_qrs32 = 1597, |
| 1613 | MVE_VQSHL_qrs8 = 1598, |
| 1614 | MVE_VQSHL_qru16 = 1599, |
| 1615 | MVE_VQSHL_qru32 = 1600, |
| 1616 | MVE_VQSHL_qru8 = 1601, |
| 1617 | MVE_VQSHLimms16 = 1602, |
| 1618 | MVE_VQSHLimms32 = 1603, |
| 1619 | MVE_VQSHLimms8 = 1604, |
| 1620 | MVE_VQSHLimmu16 = 1605, |
| 1621 | MVE_VQSHLimmu32 = 1606, |
| 1622 | MVE_VQSHLimmu8 = 1607, |
| 1623 | MVE_VQSHRNbhs16 = 1608, |
| 1624 | MVE_VQSHRNbhs32 = 1609, |
| 1625 | MVE_VQSHRNbhu16 = 1610, |
| 1626 | MVE_VQSHRNbhu32 = 1611, |
| 1627 | MVE_VQSHRNths16 = 1612, |
| 1628 | MVE_VQSHRNths32 = 1613, |
| 1629 | MVE_VQSHRNthu16 = 1614, |
| 1630 | MVE_VQSHRNthu32 = 1615, |
| 1631 | MVE_VQSHRUNs16bh = 1616, |
| 1632 | MVE_VQSHRUNs16th = 1617, |
| 1633 | MVE_VQSHRUNs32bh = 1618, |
| 1634 | MVE_VQSHRUNs32th = 1619, |
| 1635 | MVE_VQSUB_qr_s16 = 1620, |
| 1636 | MVE_VQSUB_qr_s32 = 1621, |
| 1637 | MVE_VQSUB_qr_s8 = 1622, |
| 1638 | MVE_VQSUB_qr_u16 = 1623, |
| 1639 | MVE_VQSUB_qr_u32 = 1624, |
| 1640 | MVE_VQSUB_qr_u8 = 1625, |
| 1641 | MVE_VQSUBs16 = 1626, |
| 1642 | MVE_VQSUBs32 = 1627, |
| 1643 | MVE_VQSUBs8 = 1628, |
| 1644 | MVE_VQSUBu16 = 1629, |
| 1645 | MVE_VQSUBu32 = 1630, |
| 1646 | MVE_VQSUBu8 = 1631, |
| 1647 | MVE_VREV16_8 = 1632, |
| 1648 | MVE_VREV32_16 = 1633, |
| 1649 | MVE_VREV32_8 = 1634, |
| 1650 | MVE_VREV64_16 = 1635, |
| 1651 | MVE_VREV64_32 = 1636, |
| 1652 | MVE_VREV64_8 = 1637, |
| 1653 | MVE_VRHADDs16 = 1638, |
| 1654 | MVE_VRHADDs32 = 1639, |
| 1655 | MVE_VRHADDs8 = 1640, |
| 1656 | MVE_VRHADDu16 = 1641, |
| 1657 | MVE_VRHADDu32 = 1642, |
| 1658 | MVE_VRHADDu8 = 1643, |
| 1659 | MVE_VRINTf16A = 1644, |
| 1660 | MVE_VRINTf16M = 1645, |
| 1661 | MVE_VRINTf16N = 1646, |
| 1662 | MVE_VRINTf16P = 1647, |
| 1663 | MVE_VRINTf16X = 1648, |
| 1664 | MVE_VRINTf16Z = 1649, |
| 1665 | MVE_VRINTf32A = 1650, |
| 1666 | MVE_VRINTf32M = 1651, |
| 1667 | MVE_VRINTf32N = 1652, |
| 1668 | MVE_VRINTf32P = 1653, |
| 1669 | MVE_VRINTf32X = 1654, |
| 1670 | MVE_VRINTf32Z = 1655, |
| 1671 | MVE_VRMLALDAVHas32 = 1656, |
| 1672 | MVE_VRMLALDAVHau32 = 1657, |
| 1673 | MVE_VRMLALDAVHaxs32 = 1658, |
| 1674 | MVE_VRMLALDAVHs32 = 1659, |
| 1675 | MVE_VRMLALDAVHu32 = 1660, |
| 1676 | MVE_VRMLALDAVHxs32 = 1661, |
| 1677 | MVE_VRMLSLDAVHas32 = 1662, |
| 1678 | MVE_VRMLSLDAVHaxs32 = 1663, |
| 1679 | MVE_VRMLSLDAVHs32 = 1664, |
| 1680 | MVE_VRMLSLDAVHxs32 = 1665, |
| 1681 | MVE_VRMULHs16 = 1666, |
| 1682 | MVE_VRMULHs32 = 1667, |
| 1683 | MVE_VRMULHs8 = 1668, |
| 1684 | MVE_VRMULHu16 = 1669, |
| 1685 | MVE_VRMULHu32 = 1670, |
| 1686 | MVE_VRMULHu8 = 1671, |
| 1687 | MVE_VRSHL_by_vecs16 = 1672, |
| 1688 | MVE_VRSHL_by_vecs32 = 1673, |
| 1689 | MVE_VRSHL_by_vecs8 = 1674, |
| 1690 | MVE_VRSHL_by_vecu16 = 1675, |
| 1691 | MVE_VRSHL_by_vecu32 = 1676, |
| 1692 | MVE_VRSHL_by_vecu8 = 1677, |
| 1693 | MVE_VRSHL_qrs16 = 1678, |
| 1694 | MVE_VRSHL_qrs32 = 1679, |
| 1695 | MVE_VRSHL_qrs8 = 1680, |
| 1696 | MVE_VRSHL_qru16 = 1681, |
| 1697 | MVE_VRSHL_qru32 = 1682, |
| 1698 | MVE_VRSHL_qru8 = 1683, |
| 1699 | MVE_VRSHRNi16bh = 1684, |
| 1700 | MVE_VRSHRNi16th = 1685, |
| 1701 | MVE_VRSHRNi32bh = 1686, |
| 1702 | MVE_VRSHRNi32th = 1687, |
| 1703 | MVE_VRSHR_imms16 = 1688, |
| 1704 | MVE_VRSHR_imms32 = 1689, |
| 1705 | MVE_VRSHR_imms8 = 1690, |
| 1706 | MVE_VRSHR_immu16 = 1691, |
| 1707 | MVE_VRSHR_immu32 = 1692, |
| 1708 | MVE_VRSHR_immu8 = 1693, |
| 1709 | MVE_VSBC = 1694, |
| 1710 | MVE_VSBCI = 1695, |
| 1711 | MVE_VSHLC = 1696, |
| 1712 | MVE_VSHLL_imms16bh = 1697, |
| 1713 | MVE_VSHLL_imms16th = 1698, |
| 1714 | MVE_VSHLL_imms8bh = 1699, |
| 1715 | MVE_VSHLL_imms8th = 1700, |
| 1716 | MVE_VSHLL_immu16bh = 1701, |
| 1717 | MVE_VSHLL_immu16th = 1702, |
| 1718 | MVE_VSHLL_immu8bh = 1703, |
| 1719 | MVE_VSHLL_immu8th = 1704, |
| 1720 | MVE_VSHLL_lws16bh = 1705, |
| 1721 | MVE_VSHLL_lws16th = 1706, |
| 1722 | MVE_VSHLL_lws8bh = 1707, |
| 1723 | MVE_VSHLL_lws8th = 1708, |
| 1724 | MVE_VSHLL_lwu16bh = 1709, |
| 1725 | MVE_VSHLL_lwu16th = 1710, |
| 1726 | MVE_VSHLL_lwu8bh = 1711, |
| 1727 | MVE_VSHLL_lwu8th = 1712, |
| 1728 | MVE_VSHL_by_vecs16 = 1713, |
| 1729 | MVE_VSHL_by_vecs32 = 1714, |
| 1730 | MVE_VSHL_by_vecs8 = 1715, |
| 1731 | MVE_VSHL_by_vecu16 = 1716, |
| 1732 | MVE_VSHL_by_vecu32 = 1717, |
| 1733 | MVE_VSHL_by_vecu8 = 1718, |
| 1734 | MVE_VSHL_immi16 = 1719, |
| 1735 | MVE_VSHL_immi32 = 1720, |
| 1736 | MVE_VSHL_immi8 = 1721, |
| 1737 | MVE_VSHL_qrs16 = 1722, |
| 1738 | MVE_VSHL_qrs32 = 1723, |
| 1739 | MVE_VSHL_qrs8 = 1724, |
| 1740 | MVE_VSHL_qru16 = 1725, |
| 1741 | MVE_VSHL_qru32 = 1726, |
| 1742 | MVE_VSHL_qru8 = 1727, |
| 1743 | MVE_VSHRNi16bh = 1728, |
| 1744 | MVE_VSHRNi16th = 1729, |
| 1745 | MVE_VSHRNi32bh = 1730, |
| 1746 | MVE_VSHRNi32th = 1731, |
| 1747 | MVE_VSHR_imms16 = 1732, |
| 1748 | MVE_VSHR_imms32 = 1733, |
| 1749 | MVE_VSHR_imms8 = 1734, |
| 1750 | MVE_VSHR_immu16 = 1735, |
| 1751 | MVE_VSHR_immu32 = 1736, |
| 1752 | MVE_VSHR_immu8 = 1737, |
| 1753 | MVE_VSLIimm16 = 1738, |
| 1754 | MVE_VSLIimm32 = 1739, |
| 1755 | MVE_VSLIimm8 = 1740, |
| 1756 | MVE_VSRIimm16 = 1741, |
| 1757 | MVE_VSRIimm32 = 1742, |
| 1758 | MVE_VSRIimm8 = 1743, |
| 1759 | MVE_VST20_16 = 1744, |
| 1760 | MVE_VST20_16_wb = 1745, |
| 1761 | MVE_VST20_32 = 1746, |
| 1762 | MVE_VST20_32_wb = 1747, |
| 1763 | MVE_VST20_8 = 1748, |
| 1764 | MVE_VST20_8_wb = 1749, |
| 1765 | MVE_VST21_16 = 1750, |
| 1766 | MVE_VST21_16_wb = 1751, |
| 1767 | MVE_VST21_32 = 1752, |
| 1768 | MVE_VST21_32_wb = 1753, |
| 1769 | MVE_VST21_8 = 1754, |
| 1770 | MVE_VST21_8_wb = 1755, |
| 1771 | MVE_VST40_16 = 1756, |
| 1772 | MVE_VST40_16_wb = 1757, |
| 1773 | MVE_VST40_32 = 1758, |
| 1774 | MVE_VST40_32_wb = 1759, |
| 1775 | MVE_VST40_8 = 1760, |
| 1776 | MVE_VST40_8_wb = 1761, |
| 1777 | MVE_VST41_16 = 1762, |
| 1778 | MVE_VST41_16_wb = 1763, |
| 1779 | MVE_VST41_32 = 1764, |
| 1780 | MVE_VST41_32_wb = 1765, |
| 1781 | MVE_VST41_8 = 1766, |
| 1782 | MVE_VST41_8_wb = 1767, |
| 1783 | MVE_VST42_16 = 1768, |
| 1784 | MVE_VST42_16_wb = 1769, |
| 1785 | MVE_VST42_32 = 1770, |
| 1786 | MVE_VST42_32_wb = 1771, |
| 1787 | MVE_VST42_8 = 1772, |
| 1788 | MVE_VST42_8_wb = 1773, |
| 1789 | MVE_VST43_16 = 1774, |
| 1790 | MVE_VST43_16_wb = 1775, |
| 1791 | MVE_VST43_32 = 1776, |
| 1792 | MVE_VST43_32_wb = 1777, |
| 1793 | MVE_VST43_8 = 1778, |
| 1794 | MVE_VST43_8_wb = 1779, |
| 1795 | MVE_VSTRB16 = 1780, |
| 1796 | MVE_VSTRB16_post = 1781, |
| 1797 | MVE_VSTRB16_pre = 1782, |
| 1798 | MVE_VSTRB16_rq = 1783, |
| 1799 | MVE_VSTRB32 = 1784, |
| 1800 | MVE_VSTRB32_post = 1785, |
| 1801 | MVE_VSTRB32_pre = 1786, |
| 1802 | MVE_VSTRB32_rq = 1787, |
| 1803 | MVE_VSTRB8_rq = 1788, |
| 1804 | MVE_VSTRBU8 = 1789, |
| 1805 | MVE_VSTRBU8_post = 1790, |
| 1806 | MVE_VSTRBU8_pre = 1791, |
| 1807 | MVE_VSTRD64_qi = 1792, |
| 1808 | MVE_VSTRD64_qi_pre = 1793, |
| 1809 | MVE_VSTRD64_rq = 1794, |
| 1810 | MVE_VSTRD64_rq_u = 1795, |
| 1811 | MVE_VSTRH16_rq = 1796, |
| 1812 | MVE_VSTRH16_rq_u = 1797, |
| 1813 | MVE_VSTRH32 = 1798, |
| 1814 | MVE_VSTRH32_post = 1799, |
| 1815 | MVE_VSTRH32_pre = 1800, |
| 1816 | MVE_VSTRH32_rq = 1801, |
| 1817 | MVE_VSTRH32_rq_u = 1802, |
| 1818 | MVE_VSTRHU16 = 1803, |
| 1819 | MVE_VSTRHU16_post = 1804, |
| 1820 | MVE_VSTRHU16_pre = 1805, |
| 1821 | MVE_VSTRW32_qi = 1806, |
| 1822 | MVE_VSTRW32_qi_pre = 1807, |
| 1823 | MVE_VSTRW32_rq = 1808, |
| 1824 | MVE_VSTRW32_rq_u = 1809, |
| 1825 | MVE_VSTRWU32 = 1810, |
| 1826 | MVE_VSTRWU32_post = 1811, |
| 1827 | MVE_VSTRWU32_pre = 1812, |
| 1828 | MVE_VSUB_qr_f16 = 1813, |
| 1829 | MVE_VSUB_qr_f32 = 1814, |
| 1830 | MVE_VSUB_qr_i16 = 1815, |
| 1831 | MVE_VSUB_qr_i32 = 1816, |
| 1832 | MVE_VSUB_qr_i8 = 1817, |
| 1833 | MVE_VSUBf16 = 1818, |
| 1834 | MVE_VSUBf32 = 1819, |
| 1835 | MVE_VSUBi16 = 1820, |
| 1836 | MVE_VSUBi32 = 1821, |
| 1837 | MVE_VSUBi8 = 1822, |
| 1838 | MVE_WLSTP_16 = 1823, |
| 1839 | MVE_WLSTP_32 = 1824, |
| 1840 | MVE_WLSTP_64 = 1825, |
| 1841 | MVE_WLSTP_8 = 1826, |
| 1842 | MVNi = 1827, |
| 1843 | MVNr = 1828, |
| 1844 | MVNsi = 1829, |
| 1845 | MVNsr = 1830, |
| 1846 | NEON_VMAXNMNDf = 1831, |
| 1847 | NEON_VMAXNMNDh = 1832, |
| 1848 | NEON_VMAXNMNQf = 1833, |
| 1849 | NEON_VMAXNMNQh = 1834, |
| 1850 | NEON_VMINNMNDf = 1835, |
| 1851 | NEON_VMINNMNDh = 1836, |
| 1852 | NEON_VMINNMNQf = 1837, |
| 1853 | NEON_VMINNMNQh = 1838, |
| 1854 | ORRri = 1839, |
| 1855 | ORRrr = 1840, |
| 1856 | ORRrsi = 1841, |
| 1857 | ORRrsr = 1842, |
| 1858 | PKHBT = 1843, |
| 1859 | PKHTB = 1844, |
| 1860 | PLDWi12 = 1845, |
| 1861 | PLDWrs = 1846, |
| 1862 | PLDi12 = 1847, |
| 1863 | PLDrs = 1848, |
| 1864 | PLIi12 = 1849, |
| 1865 | PLIrs = 1850, |
| 1866 | QADD = 1851, |
| 1867 | QADD16 = 1852, |
| 1868 | QADD8 = 1853, |
| 1869 | QASX = 1854, |
| 1870 | QDADD = 1855, |
| 1871 | QDSUB = 1856, |
| 1872 | QSAX = 1857, |
| 1873 | QSUB = 1858, |
| 1874 | QSUB16 = 1859, |
| 1875 | QSUB8 = 1860, |
| 1876 | RBIT = 1861, |
| 1877 | REV = 1862, |
| 1878 | REV16 = 1863, |
| 1879 | REVSH = 1864, |
| 1880 | RFEDA = 1865, |
| 1881 | RFEDA_UPD = 1866, |
| 1882 | RFEDB = 1867, |
| 1883 | RFEDB_UPD = 1868, |
| 1884 | RFEIA = 1869, |
| 1885 | RFEIA_UPD = 1870, |
| 1886 | RFEIB = 1871, |
| 1887 | RFEIB_UPD = 1872, |
| 1888 | RSBri = 1873, |
| 1889 | RSBrr = 1874, |
| 1890 | RSBrsi = 1875, |
| 1891 | RSBrsr = 1876, |
| 1892 | RSCri = 1877, |
| 1893 | RSCrr = 1878, |
| 1894 | RSCrsi = 1879, |
| 1895 | RSCrsr = 1880, |
| 1896 | SADD16 = 1881, |
| 1897 | SADD8 = 1882, |
| 1898 | SASX = 1883, |
| 1899 | SB = 1884, |
| 1900 | SBCri = 1885, |
| 1901 | SBCrr = 1886, |
| 1902 | SBCrsi = 1887, |
| 1903 | SBCrsr = 1888, |
| 1904 | SBFX = 1889, |
| 1905 | SDIV = 1890, |
| 1906 | SEL = 1891, |
| 1907 | SETEND = 1892, |
| 1908 | SETPAN = 1893, |
| 1909 | SHA1C = 1894, |
| 1910 | SHA1H = 1895, |
| 1911 | SHA1M = 1896, |
| 1912 | SHA1P = 1897, |
| 1913 | SHA1SU0 = 1898, |
| 1914 | SHA1SU1 = 1899, |
| 1915 | SHA256H = 1900, |
| 1916 | SHA256H2 = 1901, |
| 1917 | SHA256SU0 = 1902, |
| 1918 | SHA256SU1 = 1903, |
| 1919 | SHADD16 = 1904, |
| 1920 | SHADD8 = 1905, |
| 1921 | SHASX = 1906, |
| 1922 | SHSAX = 1907, |
| 1923 | SHSUB16 = 1908, |
| 1924 | SHSUB8 = 1909, |
| 1925 | SMC = 1910, |
| 1926 | SMLABB = 1911, |
| 1927 | SMLABT = 1912, |
| 1928 | SMLAD = 1913, |
| 1929 | SMLADX = 1914, |
| 1930 | SMLAL = 1915, |
| 1931 | SMLALBB = 1916, |
| 1932 | SMLALBT = 1917, |
| 1933 | SMLALD = 1918, |
| 1934 | SMLALDX = 1919, |
| 1935 | SMLALTB = 1920, |
| 1936 | SMLALTT = 1921, |
| 1937 | SMLATB = 1922, |
| 1938 | SMLATT = 1923, |
| 1939 | SMLAWB = 1924, |
| 1940 | SMLAWT = 1925, |
| 1941 | SMLSD = 1926, |
| 1942 | SMLSDX = 1927, |
| 1943 | SMLSLD = 1928, |
| 1944 | SMLSLDX = 1929, |
| 1945 | SMMLA = 1930, |
| 1946 | SMMLAR = 1931, |
| 1947 | SMMLS = 1932, |
| 1948 | SMMLSR = 1933, |
| 1949 | SMMUL = 1934, |
| 1950 | SMMULR = 1935, |
| 1951 | SMUAD = 1936, |
| 1952 | SMUADX = 1937, |
| 1953 | SMULBB = 1938, |
| 1954 | SMULBT = 1939, |
| 1955 | SMULL = 1940, |
| 1956 | SMULTB = 1941, |
| 1957 | SMULTT = 1942, |
| 1958 | SMULWB = 1943, |
| 1959 | SMULWT = 1944, |
| 1960 | SMUSD = 1945, |
| 1961 | SMUSDX = 1946, |
| 1962 | SRSDA = 1947, |
| 1963 | SRSDA_UPD = 1948, |
| 1964 | SRSDB = 1949, |
| 1965 | SRSDB_UPD = 1950, |
| 1966 | SRSIA = 1951, |
| 1967 | SRSIA_UPD = 1952, |
| 1968 | SRSIB = 1953, |
| 1969 | SRSIB_UPD = 1954, |
| 1970 | SSAT = 1955, |
| 1971 | SSAT16 = 1956, |
| 1972 | SSAX = 1957, |
| 1973 | SSUB16 = 1958, |
| 1974 | SSUB8 = 1959, |
| 1975 | STC2L_OFFSET = 1960, |
| 1976 | STC2L_OPTION = 1961, |
| 1977 | STC2L_POST = 1962, |
| 1978 | STC2L_PRE = 1963, |
| 1979 | STC2_OFFSET = 1964, |
| 1980 | STC2_OPTION = 1965, |
| 1981 | STC2_POST = 1966, |
| 1982 | STC2_PRE = 1967, |
| 1983 | STCL_OFFSET = 1968, |
| 1984 | STCL_OPTION = 1969, |
| 1985 | STCL_POST = 1970, |
| 1986 | STCL_PRE = 1971, |
| 1987 | STC_OFFSET = 1972, |
| 1988 | STC_OPTION = 1973, |
| 1989 | STC_POST = 1974, |
| 1990 | STC_PRE = 1975, |
| 1991 | STL = 1976, |
| 1992 | STLB = 1977, |
| 1993 | STLEX = 1978, |
| 1994 | STLEXB = 1979, |
| 1995 | STLEXD = 1980, |
| 1996 | STLEXH = 1981, |
| 1997 | STLH = 1982, |
| 1998 | STMDA = 1983, |
| 1999 | STMDA_UPD = 1984, |
| 2000 | STMDB = 1985, |
| 2001 | STMDB_UPD = 1986, |
| 2002 | STMIA = 1987, |
| 2003 | STMIA_UPD = 1988, |
| 2004 | STMIB = 1989, |
| 2005 | STMIB_UPD = 1990, |
| 2006 | STRBT_POST_IMM = 1991, |
| 2007 | STRBT_POST_REG = 1992, |
| 2008 | STRB_POST_IMM = 1993, |
| 2009 | STRB_POST_REG = 1994, |
| 2010 | STRB_PRE_IMM = 1995, |
| 2011 | STRB_PRE_REG = 1996, |
| 2012 | STRBi12 = 1997, |
| 2013 | STRBrs = 1998, |
| 2014 | STRD = 1999, |
| 2015 | STRD_POST = 2000, |
| 2016 | STRD_PRE = 2001, |
| 2017 | STREX = 2002, |
| 2018 | STREXB = 2003, |
| 2019 | STREXD = 2004, |
| 2020 | STREXH = 2005, |
| 2021 | STRH = 2006, |
| 2022 | STRHTi = 2007, |
| 2023 | STRHTr = 2008, |
| 2024 | STRH_POST = 2009, |
| 2025 | STRH_PRE = 2010, |
| 2026 | STRT_POST_IMM = 2011, |
| 2027 | STRT_POST_REG = 2012, |
| 2028 | STR_POST_IMM = 2013, |
| 2029 | STR_POST_REG = 2014, |
| 2030 | STR_PRE_IMM = 2015, |
| 2031 | STR_PRE_REG = 2016, |
| 2032 | STRi12 = 2017, |
| 2033 | STRrs = 2018, |
| 2034 | SUBri = 2019, |
| 2035 | SUBrr = 2020, |
| 2036 | SUBrsi = 2021, |
| 2037 | SUBrsr = 2022, |
| 2038 | SVC = 2023, |
| 2039 | SWP = 2024, |
| 2040 | SWPB = 2025, |
| 2041 | SXTAB = 2026, |
| 2042 | SXTAB16 = 2027, |
| 2043 | SXTAH = 2028, |
| 2044 | SXTB = 2029, |
| 2045 | SXTB16 = 2030, |
| 2046 | SXTH = 2031, |
| 2047 | TEQri = 2032, |
| 2048 | TEQrr = 2033, |
| 2049 | TEQrsi = 2034, |
| 2050 | TEQrsr = 2035, |
| 2051 | TRAP = 2036, |
| 2052 | TRAPNaCl = 2037, |
| 2053 | TSB = 2038, |
| 2054 | TSTri = 2039, |
| 2055 | TSTrr = 2040, |
| 2056 | TSTrsi = 2041, |
| 2057 | TSTrsr = 2042, |
| 2058 | UADD16 = 2043, |
| 2059 | UADD8 = 2044, |
| 2060 | UASX = 2045, |
| 2061 | UBFX = 2046, |
| 2062 | UDF = 2047, |
| 2063 | UDIV = 2048, |
| 2064 | UHADD16 = 2049, |
| 2065 | UHADD8 = 2050, |
| 2066 | UHASX = 2051, |
| 2067 | UHSAX = 2052, |
| 2068 | UHSUB16 = 2053, |
| 2069 | UHSUB8 = 2054, |
| 2070 | UMAAL = 2055, |
| 2071 | UMLAL = 2056, |
| 2072 | UMULL = 2057, |
| 2073 | UQADD16 = 2058, |
| 2074 | UQADD8 = 2059, |
| 2075 | UQASX = 2060, |
| 2076 | UQSAX = 2061, |
| 2077 | UQSUB16 = 2062, |
| 2078 | UQSUB8 = 2063, |
| 2079 | USAD8 = 2064, |
| 2080 | USADA8 = 2065, |
| 2081 | USAT = 2066, |
| 2082 | USAT16 = 2067, |
| 2083 | USAX = 2068, |
| 2084 | USUB16 = 2069, |
| 2085 | USUB8 = 2070, |
| 2086 | UXTAB = 2071, |
| 2087 | UXTAB16 = 2072, |
| 2088 | UXTAH = 2073, |
| 2089 | UXTB = 2074, |
| 2090 | UXTB16 = 2075, |
| 2091 | UXTH = 2076, |
| 2092 | VABALsv2i64 = 2077, |
| 2093 | VABALsv4i32 = 2078, |
| 2094 | VABALsv8i16 = 2079, |
| 2095 | VABALuv2i64 = 2080, |
| 2096 | VABALuv4i32 = 2081, |
| 2097 | VABALuv8i16 = 2082, |
| 2098 | VABAsv16i8 = 2083, |
| 2099 | VABAsv2i32 = 2084, |
| 2100 | VABAsv4i16 = 2085, |
| 2101 | VABAsv4i32 = 2086, |
| 2102 | VABAsv8i16 = 2087, |
| 2103 | VABAsv8i8 = 2088, |
| 2104 | VABAuv16i8 = 2089, |
| 2105 | VABAuv2i32 = 2090, |
| 2106 | VABAuv4i16 = 2091, |
| 2107 | VABAuv4i32 = 2092, |
| 2108 | VABAuv8i16 = 2093, |
| 2109 | VABAuv8i8 = 2094, |
| 2110 | VABDLsv2i64 = 2095, |
| 2111 | VABDLsv4i32 = 2096, |
| 2112 | VABDLsv8i16 = 2097, |
| 2113 | VABDLuv2i64 = 2098, |
| 2114 | VABDLuv4i32 = 2099, |
| 2115 | VABDLuv8i16 = 2100, |
| 2116 | VABDfd = 2101, |
| 2117 | VABDfq = 2102, |
| 2118 | VABDhd = 2103, |
| 2119 | VABDhq = 2104, |
| 2120 | VABDsv16i8 = 2105, |
| 2121 | VABDsv2i32 = 2106, |
| 2122 | VABDsv4i16 = 2107, |
| 2123 | VABDsv4i32 = 2108, |
| 2124 | VABDsv8i16 = 2109, |
| 2125 | VABDsv8i8 = 2110, |
| 2126 | VABDuv16i8 = 2111, |
| 2127 | VABDuv2i32 = 2112, |
| 2128 | VABDuv4i16 = 2113, |
| 2129 | VABDuv4i32 = 2114, |
| 2130 | VABDuv8i16 = 2115, |
| 2131 | VABDuv8i8 = 2116, |
| 2132 | VABSD = 2117, |
| 2133 | VABSH = 2118, |
| 2134 | VABSS = 2119, |
| 2135 | VABSfd = 2120, |
| 2136 | VABSfq = 2121, |
| 2137 | VABShd = 2122, |
| 2138 | VABShq = 2123, |
| 2139 | VABSv16i8 = 2124, |
| 2140 | VABSv2i32 = 2125, |
| 2141 | VABSv4i16 = 2126, |
| 2142 | VABSv4i32 = 2127, |
| 2143 | VABSv8i16 = 2128, |
| 2144 | VABSv8i8 = 2129, |
| 2145 | VACGEfd = 2130, |
| 2146 | VACGEfq = 2131, |
| 2147 | VACGEhd = 2132, |
| 2148 | VACGEhq = 2133, |
| 2149 | VACGTfd = 2134, |
| 2150 | VACGTfq = 2135, |
| 2151 | VACGThd = 2136, |
| 2152 | VACGThq = 2137, |
| 2153 | VADDD = 2138, |
| 2154 | VADDH = 2139, |
| 2155 | VADDHNv2i32 = 2140, |
| 2156 | VADDHNv4i16 = 2141, |
| 2157 | VADDHNv8i8 = 2142, |
| 2158 | VADDLsv2i64 = 2143, |
| 2159 | VADDLsv4i32 = 2144, |
| 2160 | VADDLsv8i16 = 2145, |
| 2161 | VADDLuv2i64 = 2146, |
| 2162 | VADDLuv4i32 = 2147, |
| 2163 | VADDLuv8i16 = 2148, |
| 2164 | VADDS = 2149, |
| 2165 | VADDWsv2i64 = 2150, |
| 2166 | VADDWsv4i32 = 2151, |
| 2167 | VADDWsv8i16 = 2152, |
| 2168 | VADDWuv2i64 = 2153, |
| 2169 | VADDWuv4i32 = 2154, |
| 2170 | VADDWuv8i16 = 2155, |
| 2171 | VADDfd = 2156, |
| 2172 | VADDfq = 2157, |
| 2173 | VADDhd = 2158, |
| 2174 | VADDhq = 2159, |
| 2175 | VADDv16i8 = 2160, |
| 2176 | VADDv1i64 = 2161, |
| 2177 | VADDv2i32 = 2162, |
| 2178 | VADDv2i64 = 2163, |
| 2179 | VADDv4i16 = 2164, |
| 2180 | VADDv4i32 = 2165, |
| 2181 | VADDv8i16 = 2166, |
| 2182 | VADDv8i8 = 2167, |
| 2183 | VANDd = 2168, |
| 2184 | VANDq = 2169, |
| 2185 | VBF16MALBQ = 2170, |
| 2186 | VBF16MALBQI = 2171, |
| 2187 | VBF16MALTQ = 2172, |
| 2188 | VBF16MALTQI = 2173, |
| 2189 | VBICd = 2174, |
| 2190 | VBICiv2i32 = 2175, |
| 2191 | VBICiv4i16 = 2176, |
| 2192 | VBICiv4i32 = 2177, |
| 2193 | VBICiv8i16 = 2178, |
| 2194 | VBICq = 2179, |
| 2195 | VBIFd = 2180, |
| 2196 | VBIFq = 2181, |
| 2197 | VBITd = 2182, |
| 2198 | VBITq = 2183, |
| 2199 | VBSLd = 2184, |
| 2200 | VBSLq = 2185, |
| 2201 | VBSPd = 2186, |
| 2202 | VBSPq = 2187, |
| 2203 | VCADDv2f32 = 2188, |
| 2204 | VCADDv4f16 = 2189, |
| 2205 | VCADDv4f32 = 2190, |
| 2206 | VCADDv8f16 = 2191, |
| 2207 | VCEQfd = 2192, |
| 2208 | VCEQfq = 2193, |
| 2209 | VCEQhd = 2194, |
| 2210 | VCEQhq = 2195, |
| 2211 | VCEQv16i8 = 2196, |
| 2212 | VCEQv2i32 = 2197, |
| 2213 | VCEQv4i16 = 2198, |
| 2214 | VCEQv4i32 = 2199, |
| 2215 | VCEQv8i16 = 2200, |
| 2216 | VCEQv8i8 = 2201, |
| 2217 | VCEQzv16i8 = 2202, |
| 2218 | VCEQzv2f32 = 2203, |
| 2219 | VCEQzv2i32 = 2204, |
| 2220 | VCEQzv4f16 = 2205, |
| 2221 | VCEQzv4f32 = 2206, |
| 2222 | VCEQzv4i16 = 2207, |
| 2223 | VCEQzv4i32 = 2208, |
| 2224 | VCEQzv8f16 = 2209, |
| 2225 | VCEQzv8i16 = 2210, |
| 2226 | VCEQzv8i8 = 2211, |
| 2227 | VCGEfd = 2212, |
| 2228 | VCGEfq = 2213, |
| 2229 | VCGEhd = 2214, |
| 2230 | VCGEhq = 2215, |
| 2231 | VCGEsv16i8 = 2216, |
| 2232 | VCGEsv2i32 = 2217, |
| 2233 | VCGEsv4i16 = 2218, |
| 2234 | VCGEsv4i32 = 2219, |
| 2235 | VCGEsv8i16 = 2220, |
| 2236 | VCGEsv8i8 = 2221, |
| 2237 | VCGEuv16i8 = 2222, |
| 2238 | VCGEuv2i32 = 2223, |
| 2239 | VCGEuv4i16 = 2224, |
| 2240 | VCGEuv4i32 = 2225, |
| 2241 | VCGEuv8i16 = 2226, |
| 2242 | VCGEuv8i8 = 2227, |
| 2243 | VCGEzv16i8 = 2228, |
| 2244 | VCGEzv2f32 = 2229, |
| 2245 | VCGEzv2i32 = 2230, |
| 2246 | VCGEzv4f16 = 2231, |
| 2247 | VCGEzv4f32 = 2232, |
| 2248 | VCGEzv4i16 = 2233, |
| 2249 | VCGEzv4i32 = 2234, |
| 2250 | VCGEzv8f16 = 2235, |
| 2251 | VCGEzv8i16 = 2236, |
| 2252 | VCGEzv8i8 = 2237, |
| 2253 | VCGTfd = 2238, |
| 2254 | VCGTfq = 2239, |
| 2255 | VCGThd = 2240, |
| 2256 | VCGThq = 2241, |
| 2257 | VCGTsv16i8 = 2242, |
| 2258 | VCGTsv2i32 = 2243, |
| 2259 | VCGTsv4i16 = 2244, |
| 2260 | VCGTsv4i32 = 2245, |
| 2261 | VCGTsv8i16 = 2246, |
| 2262 | VCGTsv8i8 = 2247, |
| 2263 | VCGTuv16i8 = 2248, |
| 2264 | VCGTuv2i32 = 2249, |
| 2265 | VCGTuv4i16 = 2250, |
| 2266 | VCGTuv4i32 = 2251, |
| 2267 | VCGTuv8i16 = 2252, |
| 2268 | VCGTuv8i8 = 2253, |
| 2269 | VCGTzv16i8 = 2254, |
| 2270 | VCGTzv2f32 = 2255, |
| 2271 | VCGTzv2i32 = 2256, |
| 2272 | VCGTzv4f16 = 2257, |
| 2273 | VCGTzv4f32 = 2258, |
| 2274 | VCGTzv4i16 = 2259, |
| 2275 | VCGTzv4i32 = 2260, |
| 2276 | VCGTzv8f16 = 2261, |
| 2277 | VCGTzv8i16 = 2262, |
| 2278 | VCGTzv8i8 = 2263, |
| 2279 | VCLEzv16i8 = 2264, |
| 2280 | VCLEzv2f32 = 2265, |
| 2281 | VCLEzv2i32 = 2266, |
| 2282 | VCLEzv4f16 = 2267, |
| 2283 | VCLEzv4f32 = 2268, |
| 2284 | VCLEzv4i16 = 2269, |
| 2285 | VCLEzv4i32 = 2270, |
| 2286 | VCLEzv8f16 = 2271, |
| 2287 | VCLEzv8i16 = 2272, |
| 2288 | VCLEzv8i8 = 2273, |
| 2289 | VCLSv16i8 = 2274, |
| 2290 | VCLSv2i32 = 2275, |
| 2291 | VCLSv4i16 = 2276, |
| 2292 | VCLSv4i32 = 2277, |
| 2293 | VCLSv8i16 = 2278, |
| 2294 | VCLSv8i8 = 2279, |
| 2295 | VCLTzv16i8 = 2280, |
| 2296 | VCLTzv2f32 = 2281, |
| 2297 | VCLTzv2i32 = 2282, |
| 2298 | VCLTzv4f16 = 2283, |
| 2299 | VCLTzv4f32 = 2284, |
| 2300 | VCLTzv4i16 = 2285, |
| 2301 | VCLTzv4i32 = 2286, |
| 2302 | VCLTzv8f16 = 2287, |
| 2303 | VCLTzv8i16 = 2288, |
| 2304 | VCLTzv8i8 = 2289, |
| 2305 | VCLZv16i8 = 2290, |
| 2306 | VCLZv2i32 = 2291, |
| 2307 | VCLZv4i16 = 2292, |
| 2308 | VCLZv4i32 = 2293, |
| 2309 | VCLZv8i16 = 2294, |
| 2310 | VCLZv8i8 = 2295, |
| 2311 | VCMLAv2f32 = 2296, |
| 2312 | VCMLAv2f32_indexed = 2297, |
| 2313 | VCMLAv4f16 = 2298, |
| 2314 | VCMLAv4f16_indexed = 2299, |
| 2315 | VCMLAv4f32 = 2300, |
| 2316 | VCMLAv4f32_indexed = 2301, |
| 2317 | VCMLAv8f16 = 2302, |
| 2318 | VCMLAv8f16_indexed = 2303, |
| 2319 | VCMPD = 2304, |
| 2320 | VCMPED = 2305, |
| 2321 | VCMPEH = 2306, |
| 2322 | VCMPES = 2307, |
| 2323 | VCMPEZD = 2308, |
| 2324 | VCMPEZH = 2309, |
| 2325 | VCMPEZS = 2310, |
| 2326 | VCMPH = 2311, |
| 2327 | VCMPS = 2312, |
| 2328 | VCMPZD = 2313, |
| 2329 | VCMPZH = 2314, |
| 2330 | VCMPZS = 2315, |
| 2331 | VCNTd = 2316, |
| 2332 | VCNTq = 2317, |
| 2333 | VCVTANSDf = 2318, |
| 2334 | VCVTANSDh = 2319, |
| 2335 | VCVTANSQf = 2320, |
| 2336 | VCVTANSQh = 2321, |
| 2337 | VCVTANUDf = 2322, |
| 2338 | VCVTANUDh = 2323, |
| 2339 | VCVTANUQf = 2324, |
| 2340 | VCVTANUQh = 2325, |
| 2341 | VCVTASD = 2326, |
| 2342 | VCVTASH = 2327, |
| 2343 | VCVTASS = 2328, |
| 2344 | VCVTAUD = 2329, |
| 2345 | VCVTAUH = 2330, |
| 2346 | VCVTAUS = 2331, |
| 2347 | VCVTBDH = 2332, |
| 2348 | VCVTBHD = 2333, |
| 2349 | VCVTBHS = 2334, |
| 2350 | VCVTBSH = 2335, |
| 2351 | VCVTDS = 2336, |
| 2352 | VCVTMNSDf = 2337, |
| 2353 | VCVTMNSDh = 2338, |
| 2354 | VCVTMNSQf = 2339, |
| 2355 | VCVTMNSQh = 2340, |
| 2356 | VCVTMNUDf = 2341, |
| 2357 | VCVTMNUDh = 2342, |
| 2358 | VCVTMNUQf = 2343, |
| 2359 | VCVTMNUQh = 2344, |
| 2360 | VCVTMSD = 2345, |
| 2361 | VCVTMSH = 2346, |
| 2362 | VCVTMSS = 2347, |
| 2363 | VCVTMUD = 2348, |
| 2364 | VCVTMUH = 2349, |
| 2365 | VCVTMUS = 2350, |
| 2366 | VCVTNNSDf = 2351, |
| 2367 | VCVTNNSDh = 2352, |
| 2368 | VCVTNNSQf = 2353, |
| 2369 | VCVTNNSQh = 2354, |
| 2370 | VCVTNNUDf = 2355, |
| 2371 | VCVTNNUDh = 2356, |
| 2372 | VCVTNNUQf = 2357, |
| 2373 | VCVTNNUQh = 2358, |
| 2374 | VCVTNSD = 2359, |
| 2375 | VCVTNSH = 2360, |
| 2376 | VCVTNSS = 2361, |
| 2377 | VCVTNUD = 2362, |
| 2378 | VCVTNUH = 2363, |
| 2379 | VCVTNUS = 2364, |
| 2380 | VCVTPNSDf = 2365, |
| 2381 | VCVTPNSDh = 2366, |
| 2382 | VCVTPNSQf = 2367, |
| 2383 | VCVTPNSQh = 2368, |
| 2384 | VCVTPNUDf = 2369, |
| 2385 | VCVTPNUDh = 2370, |
| 2386 | VCVTPNUQf = 2371, |
| 2387 | VCVTPNUQh = 2372, |
| 2388 | VCVTPSD = 2373, |
| 2389 | VCVTPSH = 2374, |
| 2390 | VCVTPSS = 2375, |
| 2391 | VCVTPUD = 2376, |
| 2392 | VCVTPUH = 2377, |
| 2393 | VCVTPUS = 2378, |
| 2394 | VCVTSD = 2379, |
| 2395 | VCVTTDH = 2380, |
| 2396 | VCVTTHD = 2381, |
| 2397 | VCVTTHS = 2382, |
| 2398 | VCVTTSH = 2383, |
| 2399 | VCVTf2h = 2384, |
| 2400 | VCVTf2sd = 2385, |
| 2401 | VCVTf2sq = 2386, |
| 2402 | VCVTf2ud = 2387, |
| 2403 | VCVTf2uq = 2388, |
| 2404 | VCVTf2xsd = 2389, |
| 2405 | VCVTf2xsq = 2390, |
| 2406 | VCVTf2xud = 2391, |
| 2407 | VCVTf2xuq = 2392, |
| 2408 | VCVTh2f = 2393, |
| 2409 | VCVTh2sd = 2394, |
| 2410 | VCVTh2sq = 2395, |
| 2411 | VCVTh2ud = 2396, |
| 2412 | VCVTh2uq = 2397, |
| 2413 | VCVTh2xsd = 2398, |
| 2414 | VCVTh2xsq = 2399, |
| 2415 | VCVTh2xud = 2400, |
| 2416 | VCVTh2xuq = 2401, |
| 2417 | VCVTs2fd = 2402, |
| 2418 | VCVTs2fq = 2403, |
| 2419 | VCVTs2hd = 2404, |
| 2420 | VCVTs2hq = 2405, |
| 2421 | VCVTu2fd = 2406, |
| 2422 | VCVTu2fq = 2407, |
| 2423 | VCVTu2hd = 2408, |
| 2424 | VCVTu2hq = 2409, |
| 2425 | VCVTxs2fd = 2410, |
| 2426 | VCVTxs2fq = 2411, |
| 2427 | VCVTxs2hd = 2412, |
| 2428 | VCVTxs2hq = 2413, |
| 2429 | VCVTxu2fd = 2414, |
| 2430 | VCVTxu2fq = 2415, |
| 2431 | VCVTxu2hd = 2416, |
| 2432 | VCVTxu2hq = 2417, |
| 2433 | VDIVD = 2418, |
| 2434 | VDIVH = 2419, |
| 2435 | VDIVS = 2420, |
| 2436 | VDUP16d = 2421, |
| 2437 | VDUP16q = 2422, |
| 2438 | VDUP32d = 2423, |
| 2439 | VDUP32q = 2424, |
| 2440 | VDUP8d = 2425, |
| 2441 | VDUP8q = 2426, |
| 2442 | VDUPLN16d = 2427, |
| 2443 | VDUPLN16q = 2428, |
| 2444 | VDUPLN32d = 2429, |
| 2445 | VDUPLN32q = 2430, |
| 2446 | VDUPLN8d = 2431, |
| 2447 | VDUPLN8q = 2432, |
| 2448 | VEORd = 2433, |
| 2449 | VEORq = 2434, |
| 2450 | VEXTd16 = 2435, |
| 2451 | VEXTd32 = 2436, |
| 2452 | VEXTd8 = 2437, |
| 2453 | VEXTq16 = 2438, |
| 2454 | VEXTq32 = 2439, |
| 2455 | VEXTq64 = 2440, |
| 2456 | VEXTq8 = 2441, |
| 2457 | VFMAD = 2442, |
| 2458 | VFMAH = 2443, |
| 2459 | VFMALD = 2444, |
| 2460 | VFMALDI = 2445, |
| 2461 | VFMALQ = 2446, |
| 2462 | VFMALQI = 2447, |
| 2463 | VFMAS = 2448, |
| 2464 | VFMAfd = 2449, |
| 2465 | VFMAfq = 2450, |
| 2466 | VFMAhd = 2451, |
| 2467 | VFMAhq = 2452, |
| 2468 | VFMSD = 2453, |
| 2469 | VFMSH = 2454, |
| 2470 | VFMSLD = 2455, |
| 2471 | VFMSLDI = 2456, |
| 2472 | VFMSLQ = 2457, |
| 2473 | VFMSLQI = 2458, |
| 2474 | VFMSS = 2459, |
| 2475 | VFMSfd = 2460, |
| 2476 | VFMSfq = 2461, |
| 2477 | VFMShd = 2462, |
| 2478 | VFMShq = 2463, |
| 2479 | VFNMAD = 2464, |
| 2480 | VFNMAH = 2465, |
| 2481 | VFNMAS = 2466, |
| 2482 | VFNMSD = 2467, |
| 2483 | VFNMSH = 2468, |
| 2484 | VFNMSS = 2469, |
| 2485 | VFP_VMAXNMD = 2470, |
| 2486 | VFP_VMAXNMH = 2471, |
| 2487 | VFP_VMAXNMS = 2472, |
| 2488 | VFP_VMINNMD = 2473, |
| 2489 | VFP_VMINNMH = 2474, |
| 2490 | VFP_VMINNMS = 2475, |
| 2491 | VGETLNi32 = 2476, |
| 2492 | VGETLNs16 = 2477, |
| 2493 | VGETLNs8 = 2478, |
| 2494 | VGETLNu16 = 2479, |
| 2495 | VGETLNu8 = 2480, |
| 2496 | VHADDsv16i8 = 2481, |
| 2497 | VHADDsv2i32 = 2482, |
| 2498 | VHADDsv4i16 = 2483, |
| 2499 | VHADDsv4i32 = 2484, |
| 2500 | VHADDsv8i16 = 2485, |
| 2501 | VHADDsv8i8 = 2486, |
| 2502 | VHADDuv16i8 = 2487, |
| 2503 | VHADDuv2i32 = 2488, |
| 2504 | VHADDuv4i16 = 2489, |
| 2505 | VHADDuv4i32 = 2490, |
| 2506 | VHADDuv8i16 = 2491, |
| 2507 | VHADDuv8i8 = 2492, |
| 2508 | VHSUBsv16i8 = 2493, |
| 2509 | VHSUBsv2i32 = 2494, |
| 2510 | VHSUBsv4i16 = 2495, |
| 2511 | VHSUBsv4i32 = 2496, |
| 2512 | VHSUBsv8i16 = 2497, |
| 2513 | VHSUBsv8i8 = 2498, |
| 2514 | VHSUBuv16i8 = 2499, |
| 2515 | VHSUBuv2i32 = 2500, |
| 2516 | VHSUBuv4i16 = 2501, |
| 2517 | VHSUBuv4i32 = 2502, |
| 2518 | VHSUBuv8i16 = 2503, |
| 2519 | VHSUBuv8i8 = 2504, |
| 2520 | VINSH = 2505, |
| 2521 | VJCVT = 2506, |
| 2522 | VLD1DUPd16 = 2507, |
| 2523 | VLD1DUPd16wb_fixed = 2508, |
| 2524 | VLD1DUPd16wb_register = 2509, |
| 2525 | VLD1DUPd32 = 2510, |
| 2526 | VLD1DUPd32wb_fixed = 2511, |
| 2527 | VLD1DUPd32wb_register = 2512, |
| 2528 | VLD1DUPd8 = 2513, |
| 2529 | VLD1DUPd8wb_fixed = 2514, |
| 2530 | VLD1DUPd8wb_register = 2515, |
| 2531 | VLD1DUPq16 = 2516, |
| 2532 | VLD1DUPq16wb_fixed = 2517, |
| 2533 | VLD1DUPq16wb_register = 2518, |
| 2534 | VLD1DUPq32 = 2519, |
| 2535 | VLD1DUPq32wb_fixed = 2520, |
| 2536 | VLD1DUPq32wb_register = 2521, |
| 2537 | VLD1DUPq8 = 2522, |
| 2538 | VLD1DUPq8wb_fixed = 2523, |
| 2539 | VLD1DUPq8wb_register = 2524, |
| 2540 | VLD1LNd16 = 2525, |
| 2541 | VLD1LNd16_UPD = 2526, |
| 2542 | VLD1LNd32 = 2527, |
| 2543 | VLD1LNd32_UPD = 2528, |
| 2544 | VLD1LNd8 = 2529, |
| 2545 | VLD1LNd8_UPD = 2530, |
| 2546 | VLD1LNq16Pseudo = 2531, |
| 2547 | VLD1LNq16Pseudo_UPD = 2532, |
| 2548 | VLD1LNq32Pseudo = 2533, |
| 2549 | VLD1LNq32Pseudo_UPD = 2534, |
| 2550 | VLD1LNq8Pseudo = 2535, |
| 2551 | VLD1LNq8Pseudo_UPD = 2536, |
| 2552 | VLD1d16 = 2537, |
| 2553 | VLD1d16Q = 2538, |
| 2554 | VLD1d16QPseudo = 2539, |
| 2555 | VLD1d16QPseudoWB_fixed = 2540, |
| 2556 | VLD1d16QPseudoWB_register = 2541, |
| 2557 | VLD1d16Qwb_fixed = 2542, |
| 2558 | VLD1d16Qwb_register = 2543, |
| 2559 | VLD1d16T = 2544, |
| 2560 | VLD1d16TPseudo = 2545, |
| 2561 | VLD1d16TPseudoWB_fixed = 2546, |
| 2562 | VLD1d16TPseudoWB_register = 2547, |
| 2563 | VLD1d16Twb_fixed = 2548, |
| 2564 | VLD1d16Twb_register = 2549, |
| 2565 | VLD1d16wb_fixed = 2550, |
| 2566 | VLD1d16wb_register = 2551, |
| 2567 | VLD1d32 = 2552, |
| 2568 | VLD1d32Q = 2553, |
| 2569 | VLD1d32QPseudo = 2554, |
| 2570 | VLD1d32QPseudoWB_fixed = 2555, |
| 2571 | VLD1d32QPseudoWB_register = 2556, |
| 2572 | VLD1d32Qwb_fixed = 2557, |
| 2573 | VLD1d32Qwb_register = 2558, |
| 2574 | VLD1d32T = 2559, |
| 2575 | VLD1d32TPseudo = 2560, |
| 2576 | VLD1d32TPseudoWB_fixed = 2561, |
| 2577 | VLD1d32TPseudoWB_register = 2562, |
| 2578 | VLD1d32Twb_fixed = 2563, |
| 2579 | VLD1d32Twb_register = 2564, |
| 2580 | VLD1d32wb_fixed = 2565, |
| 2581 | VLD1d32wb_register = 2566, |
| 2582 | VLD1d64 = 2567, |
| 2583 | VLD1d64Q = 2568, |
| 2584 | VLD1d64QPseudo = 2569, |
| 2585 | VLD1d64QPseudoWB_fixed = 2570, |
| 2586 | VLD1d64QPseudoWB_register = 2571, |
| 2587 | VLD1d64Qwb_fixed = 2572, |
| 2588 | VLD1d64Qwb_register = 2573, |
| 2589 | VLD1d64T = 2574, |
| 2590 | VLD1d64TPseudo = 2575, |
| 2591 | VLD1d64TPseudoWB_fixed = 2576, |
| 2592 | VLD1d64TPseudoWB_register = 2577, |
| 2593 | VLD1d64Twb_fixed = 2578, |
| 2594 | VLD1d64Twb_register = 2579, |
| 2595 | VLD1d64wb_fixed = 2580, |
| 2596 | VLD1d64wb_register = 2581, |
| 2597 | VLD1d8 = 2582, |
| 2598 | VLD1d8Q = 2583, |
| 2599 | VLD1d8QPseudo = 2584, |
| 2600 | VLD1d8QPseudoWB_fixed = 2585, |
| 2601 | VLD1d8QPseudoWB_register = 2586, |
| 2602 | VLD1d8Qwb_fixed = 2587, |
| 2603 | VLD1d8Qwb_register = 2588, |
| 2604 | VLD1d8T = 2589, |
| 2605 | VLD1d8TPseudo = 2590, |
| 2606 | VLD1d8TPseudoWB_fixed = 2591, |
| 2607 | VLD1d8TPseudoWB_register = 2592, |
| 2608 | VLD1d8Twb_fixed = 2593, |
| 2609 | VLD1d8Twb_register = 2594, |
| 2610 | VLD1d8wb_fixed = 2595, |
| 2611 | VLD1d8wb_register = 2596, |
| 2612 | VLD1q16 = 2597, |
| 2613 | VLD1q16HighQPseudo = 2598, |
| 2614 | VLD1q16HighQPseudo_UPD = 2599, |
| 2615 | VLD1q16HighTPseudo = 2600, |
| 2616 | VLD1q16HighTPseudo_UPD = 2601, |
| 2617 | VLD1q16LowQPseudo_UPD = 2602, |
| 2618 | VLD1q16LowTPseudo_UPD = 2603, |
| 2619 | VLD1q16wb_fixed = 2604, |
| 2620 | VLD1q16wb_register = 2605, |
| 2621 | VLD1q32 = 2606, |
| 2622 | VLD1q32HighQPseudo = 2607, |
| 2623 | VLD1q32HighQPseudo_UPD = 2608, |
| 2624 | VLD1q32HighTPseudo = 2609, |
| 2625 | VLD1q32HighTPseudo_UPD = 2610, |
| 2626 | VLD1q32LowQPseudo_UPD = 2611, |
| 2627 | VLD1q32LowTPseudo_UPD = 2612, |
| 2628 | VLD1q32wb_fixed = 2613, |
| 2629 | VLD1q32wb_register = 2614, |
| 2630 | VLD1q64 = 2615, |
| 2631 | VLD1q64HighQPseudo = 2616, |
| 2632 | VLD1q64HighQPseudo_UPD = 2617, |
| 2633 | VLD1q64HighTPseudo = 2618, |
| 2634 | VLD1q64HighTPseudo_UPD = 2619, |
| 2635 | VLD1q64LowQPseudo_UPD = 2620, |
| 2636 | VLD1q64LowTPseudo_UPD = 2621, |
| 2637 | VLD1q64wb_fixed = 2622, |
| 2638 | VLD1q64wb_register = 2623, |
| 2639 | VLD1q8 = 2624, |
| 2640 | VLD1q8HighQPseudo = 2625, |
| 2641 | VLD1q8HighQPseudo_UPD = 2626, |
| 2642 | VLD1q8HighTPseudo = 2627, |
| 2643 | VLD1q8HighTPseudo_UPD = 2628, |
| 2644 | VLD1q8LowQPseudo_UPD = 2629, |
| 2645 | VLD1q8LowTPseudo_UPD = 2630, |
| 2646 | VLD1q8wb_fixed = 2631, |
| 2647 | VLD1q8wb_register = 2632, |
| 2648 | VLD2DUPd16 = 2633, |
| 2649 | VLD2DUPd16wb_fixed = 2634, |
| 2650 | VLD2DUPd16wb_register = 2635, |
| 2651 | VLD2DUPd16x2 = 2636, |
| 2652 | VLD2DUPd16x2wb_fixed = 2637, |
| 2653 | VLD2DUPd16x2wb_register = 2638, |
| 2654 | VLD2DUPd32 = 2639, |
| 2655 | VLD2DUPd32wb_fixed = 2640, |
| 2656 | VLD2DUPd32wb_register = 2641, |
| 2657 | VLD2DUPd32x2 = 2642, |
| 2658 | VLD2DUPd32x2wb_fixed = 2643, |
| 2659 | VLD2DUPd32x2wb_register = 2644, |
| 2660 | VLD2DUPd8 = 2645, |
| 2661 | VLD2DUPd8wb_fixed = 2646, |
| 2662 | VLD2DUPd8wb_register = 2647, |
| 2663 | VLD2DUPd8x2 = 2648, |
| 2664 | VLD2DUPd8x2wb_fixed = 2649, |
| 2665 | VLD2DUPd8x2wb_register = 2650, |
| 2666 | VLD2DUPq16EvenPseudo = 2651, |
| 2667 | VLD2DUPq16OddPseudo = 2652, |
| 2668 | VLD2DUPq16OddPseudoWB_fixed = 2653, |
| 2669 | VLD2DUPq16OddPseudoWB_register = 2654, |
| 2670 | VLD2DUPq32EvenPseudo = 2655, |
| 2671 | VLD2DUPq32OddPseudo = 2656, |
| 2672 | VLD2DUPq32OddPseudoWB_fixed = 2657, |
| 2673 | VLD2DUPq32OddPseudoWB_register = 2658, |
| 2674 | VLD2DUPq8EvenPseudo = 2659, |
| 2675 | VLD2DUPq8OddPseudo = 2660, |
| 2676 | VLD2DUPq8OddPseudoWB_fixed = 2661, |
| 2677 | VLD2DUPq8OddPseudoWB_register = 2662, |
| 2678 | VLD2LNd16 = 2663, |
| 2679 | VLD2LNd16Pseudo = 2664, |
| 2680 | VLD2LNd16Pseudo_UPD = 2665, |
| 2681 | VLD2LNd16_UPD = 2666, |
| 2682 | VLD2LNd32 = 2667, |
| 2683 | VLD2LNd32Pseudo = 2668, |
| 2684 | VLD2LNd32Pseudo_UPD = 2669, |
| 2685 | VLD2LNd32_UPD = 2670, |
| 2686 | VLD2LNd8 = 2671, |
| 2687 | VLD2LNd8Pseudo = 2672, |
| 2688 | VLD2LNd8Pseudo_UPD = 2673, |
| 2689 | VLD2LNd8_UPD = 2674, |
| 2690 | VLD2LNq16 = 2675, |
| 2691 | VLD2LNq16Pseudo = 2676, |
| 2692 | VLD2LNq16Pseudo_UPD = 2677, |
| 2693 | VLD2LNq16_UPD = 2678, |
| 2694 | VLD2LNq32 = 2679, |
| 2695 | VLD2LNq32Pseudo = 2680, |
| 2696 | VLD2LNq32Pseudo_UPD = 2681, |
| 2697 | VLD2LNq32_UPD = 2682, |
| 2698 | VLD2b16 = 2683, |
| 2699 | VLD2b16wb_fixed = 2684, |
| 2700 | VLD2b16wb_register = 2685, |
| 2701 | VLD2b32 = 2686, |
| 2702 | VLD2b32wb_fixed = 2687, |
| 2703 | VLD2b32wb_register = 2688, |
| 2704 | VLD2b8 = 2689, |
| 2705 | VLD2b8wb_fixed = 2690, |
| 2706 | VLD2b8wb_register = 2691, |
| 2707 | VLD2d16 = 2692, |
| 2708 | VLD2d16wb_fixed = 2693, |
| 2709 | VLD2d16wb_register = 2694, |
| 2710 | VLD2d32 = 2695, |
| 2711 | VLD2d32wb_fixed = 2696, |
| 2712 | VLD2d32wb_register = 2697, |
| 2713 | VLD2d8 = 2698, |
| 2714 | VLD2d8wb_fixed = 2699, |
| 2715 | VLD2d8wb_register = 2700, |
| 2716 | VLD2q16 = 2701, |
| 2717 | VLD2q16Pseudo = 2702, |
| 2718 | VLD2q16PseudoWB_fixed = 2703, |
| 2719 | VLD2q16PseudoWB_register = 2704, |
| 2720 | VLD2q16wb_fixed = 2705, |
| 2721 | VLD2q16wb_register = 2706, |
| 2722 | VLD2q32 = 2707, |
| 2723 | VLD2q32Pseudo = 2708, |
| 2724 | VLD2q32PseudoWB_fixed = 2709, |
| 2725 | VLD2q32PseudoWB_register = 2710, |
| 2726 | VLD2q32wb_fixed = 2711, |
| 2727 | VLD2q32wb_register = 2712, |
| 2728 | VLD2q8 = 2713, |
| 2729 | VLD2q8Pseudo = 2714, |
| 2730 | VLD2q8PseudoWB_fixed = 2715, |
| 2731 | VLD2q8PseudoWB_register = 2716, |
| 2732 | VLD2q8wb_fixed = 2717, |
| 2733 | VLD2q8wb_register = 2718, |
| 2734 | VLD3DUPd16 = 2719, |
| 2735 | VLD3DUPd16Pseudo = 2720, |
| 2736 | VLD3DUPd16Pseudo_UPD = 2721, |
| 2737 | VLD3DUPd16_UPD = 2722, |
| 2738 | VLD3DUPd32 = 2723, |
| 2739 | VLD3DUPd32Pseudo = 2724, |
| 2740 | VLD3DUPd32Pseudo_UPD = 2725, |
| 2741 | VLD3DUPd32_UPD = 2726, |
| 2742 | VLD3DUPd8 = 2727, |
| 2743 | VLD3DUPd8Pseudo = 2728, |
| 2744 | VLD3DUPd8Pseudo_UPD = 2729, |
| 2745 | VLD3DUPd8_UPD = 2730, |
| 2746 | VLD3DUPq16 = 2731, |
| 2747 | VLD3DUPq16EvenPseudo = 2732, |
| 2748 | VLD3DUPq16OddPseudo = 2733, |
| 2749 | VLD3DUPq16OddPseudo_UPD = 2734, |
| 2750 | VLD3DUPq16_UPD = 2735, |
| 2751 | VLD3DUPq32 = 2736, |
| 2752 | VLD3DUPq32EvenPseudo = 2737, |
| 2753 | VLD3DUPq32OddPseudo = 2738, |
| 2754 | VLD3DUPq32OddPseudo_UPD = 2739, |
| 2755 | VLD3DUPq32_UPD = 2740, |
| 2756 | VLD3DUPq8 = 2741, |
| 2757 | VLD3DUPq8EvenPseudo = 2742, |
| 2758 | VLD3DUPq8OddPseudo = 2743, |
| 2759 | VLD3DUPq8OddPseudo_UPD = 2744, |
| 2760 | VLD3DUPq8_UPD = 2745, |
| 2761 | VLD3LNd16 = 2746, |
| 2762 | VLD3LNd16Pseudo = 2747, |
| 2763 | VLD3LNd16Pseudo_UPD = 2748, |
| 2764 | VLD3LNd16_UPD = 2749, |
| 2765 | VLD3LNd32 = 2750, |
| 2766 | VLD3LNd32Pseudo = 2751, |
| 2767 | VLD3LNd32Pseudo_UPD = 2752, |
| 2768 | VLD3LNd32_UPD = 2753, |
| 2769 | VLD3LNd8 = 2754, |
| 2770 | VLD3LNd8Pseudo = 2755, |
| 2771 | VLD3LNd8Pseudo_UPD = 2756, |
| 2772 | VLD3LNd8_UPD = 2757, |
| 2773 | VLD3LNq16 = 2758, |
| 2774 | VLD3LNq16Pseudo = 2759, |
| 2775 | VLD3LNq16Pseudo_UPD = 2760, |
| 2776 | VLD3LNq16_UPD = 2761, |
| 2777 | VLD3LNq32 = 2762, |
| 2778 | VLD3LNq32Pseudo = 2763, |
| 2779 | VLD3LNq32Pseudo_UPD = 2764, |
| 2780 | VLD3LNq32_UPD = 2765, |
| 2781 | VLD3d16 = 2766, |
| 2782 | VLD3d16Pseudo = 2767, |
| 2783 | VLD3d16Pseudo_UPD = 2768, |
| 2784 | VLD3d16_UPD = 2769, |
| 2785 | VLD3d32 = 2770, |
| 2786 | VLD3d32Pseudo = 2771, |
| 2787 | VLD3d32Pseudo_UPD = 2772, |
| 2788 | VLD3d32_UPD = 2773, |
| 2789 | VLD3d8 = 2774, |
| 2790 | VLD3d8Pseudo = 2775, |
| 2791 | VLD3d8Pseudo_UPD = 2776, |
| 2792 | VLD3d8_UPD = 2777, |
| 2793 | VLD3q16 = 2778, |
| 2794 | VLD3q16Pseudo_UPD = 2779, |
| 2795 | VLD3q16_UPD = 2780, |
| 2796 | VLD3q16oddPseudo = 2781, |
| 2797 | VLD3q16oddPseudo_UPD = 2782, |
| 2798 | VLD3q32 = 2783, |
| 2799 | VLD3q32Pseudo_UPD = 2784, |
| 2800 | VLD3q32_UPD = 2785, |
| 2801 | VLD3q32oddPseudo = 2786, |
| 2802 | VLD3q32oddPseudo_UPD = 2787, |
| 2803 | VLD3q8 = 2788, |
| 2804 | VLD3q8Pseudo_UPD = 2789, |
| 2805 | VLD3q8_UPD = 2790, |
| 2806 | VLD3q8oddPseudo = 2791, |
| 2807 | VLD3q8oddPseudo_UPD = 2792, |
| 2808 | VLD4DUPd16 = 2793, |
| 2809 | VLD4DUPd16Pseudo = 2794, |
| 2810 | VLD4DUPd16Pseudo_UPD = 2795, |
| 2811 | VLD4DUPd16_UPD = 2796, |
| 2812 | VLD4DUPd32 = 2797, |
| 2813 | VLD4DUPd32Pseudo = 2798, |
| 2814 | VLD4DUPd32Pseudo_UPD = 2799, |
| 2815 | VLD4DUPd32_UPD = 2800, |
| 2816 | VLD4DUPd8 = 2801, |
| 2817 | VLD4DUPd8Pseudo = 2802, |
| 2818 | VLD4DUPd8Pseudo_UPD = 2803, |
| 2819 | VLD4DUPd8_UPD = 2804, |
| 2820 | VLD4DUPq16 = 2805, |
| 2821 | VLD4DUPq16EvenPseudo = 2806, |
| 2822 | VLD4DUPq16OddPseudo = 2807, |
| 2823 | VLD4DUPq16OddPseudo_UPD = 2808, |
| 2824 | VLD4DUPq16_UPD = 2809, |
| 2825 | VLD4DUPq32 = 2810, |
| 2826 | VLD4DUPq32EvenPseudo = 2811, |
| 2827 | VLD4DUPq32OddPseudo = 2812, |
| 2828 | VLD4DUPq32OddPseudo_UPD = 2813, |
| 2829 | VLD4DUPq32_UPD = 2814, |
| 2830 | VLD4DUPq8 = 2815, |
| 2831 | VLD4DUPq8EvenPseudo = 2816, |
| 2832 | VLD4DUPq8OddPseudo = 2817, |
| 2833 | VLD4DUPq8OddPseudo_UPD = 2818, |
| 2834 | VLD4DUPq8_UPD = 2819, |
| 2835 | VLD4LNd16 = 2820, |
| 2836 | VLD4LNd16Pseudo = 2821, |
| 2837 | VLD4LNd16Pseudo_UPD = 2822, |
| 2838 | VLD4LNd16_UPD = 2823, |
| 2839 | VLD4LNd32 = 2824, |
| 2840 | VLD4LNd32Pseudo = 2825, |
| 2841 | VLD4LNd32Pseudo_UPD = 2826, |
| 2842 | VLD4LNd32_UPD = 2827, |
| 2843 | VLD4LNd8 = 2828, |
| 2844 | VLD4LNd8Pseudo = 2829, |
| 2845 | VLD4LNd8Pseudo_UPD = 2830, |
| 2846 | VLD4LNd8_UPD = 2831, |
| 2847 | VLD4LNq16 = 2832, |
| 2848 | VLD4LNq16Pseudo = 2833, |
| 2849 | VLD4LNq16Pseudo_UPD = 2834, |
| 2850 | VLD4LNq16_UPD = 2835, |
| 2851 | VLD4LNq32 = 2836, |
| 2852 | VLD4LNq32Pseudo = 2837, |
| 2853 | VLD4LNq32Pseudo_UPD = 2838, |
| 2854 | VLD4LNq32_UPD = 2839, |
| 2855 | VLD4d16 = 2840, |
| 2856 | VLD4d16Pseudo = 2841, |
| 2857 | VLD4d16Pseudo_UPD = 2842, |
| 2858 | VLD4d16_UPD = 2843, |
| 2859 | VLD4d32 = 2844, |
| 2860 | VLD4d32Pseudo = 2845, |
| 2861 | VLD4d32Pseudo_UPD = 2846, |
| 2862 | VLD4d32_UPD = 2847, |
| 2863 | VLD4d8 = 2848, |
| 2864 | VLD4d8Pseudo = 2849, |
| 2865 | VLD4d8Pseudo_UPD = 2850, |
| 2866 | VLD4d8_UPD = 2851, |
| 2867 | VLD4q16 = 2852, |
| 2868 | VLD4q16Pseudo_UPD = 2853, |
| 2869 | VLD4q16_UPD = 2854, |
| 2870 | VLD4q16oddPseudo = 2855, |
| 2871 | VLD4q16oddPseudo_UPD = 2856, |
| 2872 | VLD4q32 = 2857, |
| 2873 | VLD4q32Pseudo_UPD = 2858, |
| 2874 | VLD4q32_UPD = 2859, |
| 2875 | VLD4q32oddPseudo = 2860, |
| 2876 | VLD4q32oddPseudo_UPD = 2861, |
| 2877 | VLD4q8 = 2862, |
| 2878 | VLD4q8Pseudo_UPD = 2863, |
| 2879 | VLD4q8_UPD = 2864, |
| 2880 | VLD4q8oddPseudo = 2865, |
| 2881 | VLD4q8oddPseudo_UPD = 2866, |
| 2882 | VLDMDDB_UPD = 2867, |
| 2883 | VLDMDIA = 2868, |
| 2884 | VLDMDIA_UPD = 2869, |
| 2885 | VLDMQIA = 2870, |
| 2886 | VLDMSDB_UPD = 2871, |
| 2887 | VLDMSIA = 2872, |
| 2888 | VLDMSIA_UPD = 2873, |
| 2889 | VLDRD = 2874, |
| 2890 | VLDRH = 2875, |
| 2891 | VLDRS = 2876, |
| 2892 | VLDR_FPCXTNS_off = 2877, |
| 2893 | VLDR_FPCXTNS_post = 2878, |
| 2894 | VLDR_FPCXTNS_pre = 2879, |
| 2895 | VLDR_FPCXTS_off = 2880, |
| 2896 | VLDR_FPCXTS_post = 2881, |
| 2897 | VLDR_FPCXTS_pre = 2882, |
| 2898 | VLDR_FPSCR_NZCVQC_off = 2883, |
| 2899 | VLDR_FPSCR_NZCVQC_post = 2884, |
| 2900 | VLDR_FPSCR_NZCVQC_pre = 2885, |
| 2901 | VLDR_FPSCR_off = 2886, |
| 2902 | VLDR_FPSCR_post = 2887, |
| 2903 | VLDR_FPSCR_pre = 2888, |
| 2904 | VLDR_P0_off = 2889, |
| 2905 | VLDR_P0_post = 2890, |
| 2906 | VLDR_P0_pre = 2891, |
| 2907 | VLDR_VPR_off = 2892, |
| 2908 | VLDR_VPR_post = 2893, |
| 2909 | VLDR_VPR_pre = 2894, |
| 2910 | VLLDM = 2895, |
| 2911 | VLLDM_T2 = 2896, |
| 2912 | VLSTM = 2897, |
| 2913 | VLSTM_T2 = 2898, |
| 2914 | VMAXfd = 2899, |
| 2915 | VMAXfq = 2900, |
| 2916 | VMAXhd = 2901, |
| 2917 | VMAXhq = 2902, |
| 2918 | VMAXsv16i8 = 2903, |
| 2919 | VMAXsv2i32 = 2904, |
| 2920 | VMAXsv4i16 = 2905, |
| 2921 | VMAXsv4i32 = 2906, |
| 2922 | VMAXsv8i16 = 2907, |
| 2923 | VMAXsv8i8 = 2908, |
| 2924 | VMAXuv16i8 = 2909, |
| 2925 | VMAXuv2i32 = 2910, |
| 2926 | VMAXuv4i16 = 2911, |
| 2927 | VMAXuv4i32 = 2912, |
| 2928 | VMAXuv8i16 = 2913, |
| 2929 | VMAXuv8i8 = 2914, |
| 2930 | VMINfd = 2915, |
| 2931 | VMINfq = 2916, |
| 2932 | VMINhd = 2917, |
| 2933 | VMINhq = 2918, |
| 2934 | VMINsv16i8 = 2919, |
| 2935 | VMINsv2i32 = 2920, |
| 2936 | VMINsv4i16 = 2921, |
| 2937 | VMINsv4i32 = 2922, |
| 2938 | VMINsv8i16 = 2923, |
| 2939 | VMINsv8i8 = 2924, |
| 2940 | VMINuv16i8 = 2925, |
| 2941 | VMINuv2i32 = 2926, |
| 2942 | VMINuv4i16 = 2927, |
| 2943 | VMINuv4i32 = 2928, |
| 2944 | VMINuv8i16 = 2929, |
| 2945 | VMINuv8i8 = 2930, |
| 2946 | VMLAD = 2931, |
| 2947 | VMLAH = 2932, |
| 2948 | VMLALslsv2i32 = 2933, |
| 2949 | VMLALslsv4i16 = 2934, |
| 2950 | VMLALsluv2i32 = 2935, |
| 2951 | VMLALsluv4i16 = 2936, |
| 2952 | VMLALsv2i64 = 2937, |
| 2953 | VMLALsv4i32 = 2938, |
| 2954 | VMLALsv8i16 = 2939, |
| 2955 | VMLALuv2i64 = 2940, |
| 2956 | VMLALuv4i32 = 2941, |
| 2957 | VMLALuv8i16 = 2942, |
| 2958 | VMLAS = 2943, |
| 2959 | VMLAfd = 2944, |
| 2960 | VMLAfq = 2945, |
| 2961 | VMLAhd = 2946, |
| 2962 | VMLAhq = 2947, |
| 2963 | VMLAslfd = 2948, |
| 2964 | VMLAslfq = 2949, |
| 2965 | VMLAslhd = 2950, |
| 2966 | VMLAslhq = 2951, |
| 2967 | VMLAslv2i32 = 2952, |
| 2968 | VMLAslv4i16 = 2953, |
| 2969 | VMLAslv4i32 = 2954, |
| 2970 | VMLAslv8i16 = 2955, |
| 2971 | VMLAv16i8 = 2956, |
| 2972 | VMLAv2i32 = 2957, |
| 2973 | VMLAv4i16 = 2958, |
| 2974 | VMLAv4i32 = 2959, |
| 2975 | VMLAv8i16 = 2960, |
| 2976 | VMLAv8i8 = 2961, |
| 2977 | VMLSD = 2962, |
| 2978 | VMLSH = 2963, |
| 2979 | VMLSLslsv2i32 = 2964, |
| 2980 | VMLSLslsv4i16 = 2965, |
| 2981 | VMLSLsluv2i32 = 2966, |
| 2982 | VMLSLsluv4i16 = 2967, |
| 2983 | VMLSLsv2i64 = 2968, |
| 2984 | VMLSLsv4i32 = 2969, |
| 2985 | VMLSLsv8i16 = 2970, |
| 2986 | VMLSLuv2i64 = 2971, |
| 2987 | VMLSLuv4i32 = 2972, |
| 2988 | VMLSLuv8i16 = 2973, |
| 2989 | VMLSS = 2974, |
| 2990 | VMLSfd = 2975, |
| 2991 | VMLSfq = 2976, |
| 2992 | VMLShd = 2977, |
| 2993 | VMLShq = 2978, |
| 2994 | VMLSslfd = 2979, |
| 2995 | VMLSslfq = 2980, |
| 2996 | VMLSslhd = 2981, |
| 2997 | VMLSslhq = 2982, |
| 2998 | VMLSslv2i32 = 2983, |
| 2999 | VMLSslv4i16 = 2984, |
| 3000 | VMLSslv4i32 = 2985, |
| 3001 | VMLSslv8i16 = 2986, |
| 3002 | VMLSv16i8 = 2987, |
| 3003 | VMLSv2i32 = 2988, |
| 3004 | VMLSv4i16 = 2989, |
| 3005 | VMLSv4i32 = 2990, |
| 3006 | VMLSv8i16 = 2991, |
| 3007 | VMLSv8i8 = 2992, |
| 3008 | VMMLA = 2993, |
| 3009 | VMOVD = 2994, |
| 3010 | VMOVDRR = 2995, |
| 3011 | VMOVH = 2996, |
| 3012 | VMOVHR = 2997, |
| 3013 | VMOVLsv2i64 = 2998, |
| 3014 | VMOVLsv4i32 = 2999, |
| 3015 | VMOVLsv8i16 = 3000, |
| 3016 | VMOVLuv2i64 = 3001, |
| 3017 | VMOVLuv4i32 = 3002, |
| 3018 | VMOVLuv8i16 = 3003, |
| 3019 | VMOVNv2i32 = 3004, |
| 3020 | VMOVNv4i16 = 3005, |
| 3021 | VMOVNv8i8 = 3006, |
| 3022 | VMOVRH = 3007, |
| 3023 | VMOVRRD = 3008, |
| 3024 | VMOVRRS = 3009, |
| 3025 | VMOVRS = 3010, |
| 3026 | VMOVS = 3011, |
| 3027 | VMOVSR = 3012, |
| 3028 | VMOVSRR = 3013, |
| 3029 | VMOVv16i8 = 3014, |
| 3030 | VMOVv1i64 = 3015, |
| 3031 | VMOVv2f32 = 3016, |
| 3032 | VMOVv2i32 = 3017, |
| 3033 | VMOVv2i64 = 3018, |
| 3034 | VMOVv4f32 = 3019, |
| 3035 | VMOVv4i16 = 3020, |
| 3036 | VMOVv4i32 = 3021, |
| 3037 | VMOVv8i16 = 3022, |
| 3038 | VMOVv8i8 = 3023, |
| 3039 | VMRS = 3024, |
| 3040 | VMRS_FPCXTNS = 3025, |
| 3041 | VMRS_FPCXTS = 3026, |
| 3042 | VMRS_FPEXC = 3027, |
| 3043 | VMRS_FPINST = 3028, |
| 3044 | VMRS_FPINST2 = 3029, |
| 3045 | VMRS_FPSCR_NZCVQC = 3030, |
| 3046 | VMRS_FPSID = 3031, |
| 3047 | VMRS_MVFR0 = 3032, |
| 3048 | VMRS_MVFR1 = 3033, |
| 3049 | VMRS_MVFR2 = 3034, |
| 3050 | VMRS_P0 = 3035, |
| 3051 | VMRS_VPR = 3036, |
| 3052 | VMSR = 3037, |
| 3053 | VMSR_FPCXTNS = 3038, |
| 3054 | VMSR_FPCXTS = 3039, |
| 3055 | VMSR_FPEXC = 3040, |
| 3056 | VMSR_FPINST = 3041, |
| 3057 | VMSR_FPINST2 = 3042, |
| 3058 | VMSR_FPSCR_NZCVQC = 3043, |
| 3059 | VMSR_FPSID = 3044, |
| 3060 | VMSR_P0 = 3045, |
| 3061 | VMSR_VPR = 3046, |
| 3062 | VMULD = 3047, |
| 3063 | VMULH = 3048, |
| 3064 | VMULLp64 = 3049, |
| 3065 | VMULLp8 = 3050, |
| 3066 | VMULLslsv2i32 = 3051, |
| 3067 | VMULLslsv4i16 = 3052, |
| 3068 | VMULLsluv2i32 = 3053, |
| 3069 | VMULLsluv4i16 = 3054, |
| 3070 | VMULLsv2i64 = 3055, |
| 3071 | VMULLsv4i32 = 3056, |
| 3072 | VMULLsv8i16 = 3057, |
| 3073 | VMULLuv2i64 = 3058, |
| 3074 | VMULLuv4i32 = 3059, |
| 3075 | VMULLuv8i16 = 3060, |
| 3076 | VMULS = 3061, |
| 3077 | VMULfd = 3062, |
| 3078 | VMULfq = 3063, |
| 3079 | VMULhd = 3064, |
| 3080 | VMULhq = 3065, |
| 3081 | VMULpd = 3066, |
| 3082 | VMULpq = 3067, |
| 3083 | VMULslfd = 3068, |
| 3084 | VMULslfq = 3069, |
| 3085 | VMULslhd = 3070, |
| 3086 | VMULslhq = 3071, |
| 3087 | VMULslv2i32 = 3072, |
| 3088 | VMULslv4i16 = 3073, |
| 3089 | VMULslv4i32 = 3074, |
| 3090 | VMULslv8i16 = 3075, |
| 3091 | VMULv16i8 = 3076, |
| 3092 | VMULv2i32 = 3077, |
| 3093 | VMULv4i16 = 3078, |
| 3094 | VMULv4i32 = 3079, |
| 3095 | VMULv8i16 = 3080, |
| 3096 | VMULv8i8 = 3081, |
| 3097 | VMVNd = 3082, |
| 3098 | VMVNq = 3083, |
| 3099 | VMVNv2i32 = 3084, |
| 3100 | VMVNv4i16 = 3085, |
| 3101 | VMVNv4i32 = 3086, |
| 3102 | VMVNv8i16 = 3087, |
| 3103 | VNEGD = 3088, |
| 3104 | VNEGH = 3089, |
| 3105 | VNEGS = 3090, |
| 3106 | VNEGf32q = 3091, |
| 3107 | VNEGfd = 3092, |
| 3108 | VNEGhd = 3093, |
| 3109 | VNEGhq = 3094, |
| 3110 | VNEGs16d = 3095, |
| 3111 | VNEGs16q = 3096, |
| 3112 | VNEGs32d = 3097, |
| 3113 | VNEGs32q = 3098, |
| 3114 | VNEGs8d = 3099, |
| 3115 | VNEGs8q = 3100, |
| 3116 | VNMLAD = 3101, |
| 3117 | VNMLAH = 3102, |
| 3118 | VNMLAS = 3103, |
| 3119 | VNMLSD = 3104, |
| 3120 | VNMLSH = 3105, |
| 3121 | VNMLSS = 3106, |
| 3122 | VNMULD = 3107, |
| 3123 | VNMULH = 3108, |
| 3124 | VNMULS = 3109, |
| 3125 | VORNd = 3110, |
| 3126 | VORNq = 3111, |
| 3127 | VORRd = 3112, |
| 3128 | VORRiv2i32 = 3113, |
| 3129 | VORRiv4i16 = 3114, |
| 3130 | VORRiv4i32 = 3115, |
| 3131 | VORRiv8i16 = 3116, |
| 3132 | VORRq = 3117, |
| 3133 | VPADALsv16i8 = 3118, |
| 3134 | VPADALsv2i32 = 3119, |
| 3135 | VPADALsv4i16 = 3120, |
| 3136 | VPADALsv4i32 = 3121, |
| 3137 | VPADALsv8i16 = 3122, |
| 3138 | VPADALsv8i8 = 3123, |
| 3139 | VPADALuv16i8 = 3124, |
| 3140 | VPADALuv2i32 = 3125, |
| 3141 | VPADALuv4i16 = 3126, |
| 3142 | VPADALuv4i32 = 3127, |
| 3143 | VPADALuv8i16 = 3128, |
| 3144 | VPADALuv8i8 = 3129, |
| 3145 | VPADDLsv16i8 = 3130, |
| 3146 | VPADDLsv2i32 = 3131, |
| 3147 | VPADDLsv4i16 = 3132, |
| 3148 | VPADDLsv4i32 = 3133, |
| 3149 | VPADDLsv8i16 = 3134, |
| 3150 | VPADDLsv8i8 = 3135, |
| 3151 | VPADDLuv16i8 = 3136, |
| 3152 | VPADDLuv2i32 = 3137, |
| 3153 | VPADDLuv4i16 = 3138, |
| 3154 | VPADDLuv4i32 = 3139, |
| 3155 | VPADDLuv8i16 = 3140, |
| 3156 | VPADDLuv8i8 = 3141, |
| 3157 | VPADDf = 3142, |
| 3158 | VPADDh = 3143, |
| 3159 | VPADDi16 = 3144, |
| 3160 | VPADDi32 = 3145, |
| 3161 | VPADDi8 = 3146, |
| 3162 | VPMAXf = 3147, |
| 3163 | VPMAXh = 3148, |
| 3164 | VPMAXs16 = 3149, |
| 3165 | VPMAXs32 = 3150, |
| 3166 | VPMAXs8 = 3151, |
| 3167 | VPMAXu16 = 3152, |
| 3168 | VPMAXu32 = 3153, |
| 3169 | VPMAXu8 = 3154, |
| 3170 | VPMINf = 3155, |
| 3171 | VPMINh = 3156, |
| 3172 | VPMINs16 = 3157, |
| 3173 | VPMINs32 = 3158, |
| 3174 | VPMINs8 = 3159, |
| 3175 | VPMINu16 = 3160, |
| 3176 | VPMINu32 = 3161, |
| 3177 | VPMINu8 = 3162, |
| 3178 | VQABSv16i8 = 3163, |
| 3179 | VQABSv2i32 = 3164, |
| 3180 | VQABSv4i16 = 3165, |
| 3181 | VQABSv4i32 = 3166, |
| 3182 | VQABSv8i16 = 3167, |
| 3183 | VQABSv8i8 = 3168, |
| 3184 | VQADDsv16i8 = 3169, |
| 3185 | VQADDsv1i64 = 3170, |
| 3186 | VQADDsv2i32 = 3171, |
| 3187 | VQADDsv2i64 = 3172, |
| 3188 | VQADDsv4i16 = 3173, |
| 3189 | VQADDsv4i32 = 3174, |
| 3190 | VQADDsv8i16 = 3175, |
| 3191 | VQADDsv8i8 = 3176, |
| 3192 | VQADDuv16i8 = 3177, |
| 3193 | VQADDuv1i64 = 3178, |
| 3194 | VQADDuv2i32 = 3179, |
| 3195 | VQADDuv2i64 = 3180, |
| 3196 | VQADDuv4i16 = 3181, |
| 3197 | VQADDuv4i32 = 3182, |
| 3198 | VQADDuv8i16 = 3183, |
| 3199 | VQADDuv8i8 = 3184, |
| 3200 | VQDMLALslv2i32 = 3185, |
| 3201 | VQDMLALslv4i16 = 3186, |
| 3202 | VQDMLALv2i64 = 3187, |
| 3203 | VQDMLALv4i32 = 3188, |
| 3204 | VQDMLSLslv2i32 = 3189, |
| 3205 | VQDMLSLslv4i16 = 3190, |
| 3206 | VQDMLSLv2i64 = 3191, |
| 3207 | VQDMLSLv4i32 = 3192, |
| 3208 | VQDMULHslv2i32 = 3193, |
| 3209 | VQDMULHslv4i16 = 3194, |
| 3210 | VQDMULHslv4i32 = 3195, |
| 3211 | VQDMULHslv8i16 = 3196, |
| 3212 | VQDMULHv2i32 = 3197, |
| 3213 | VQDMULHv4i16 = 3198, |
| 3214 | VQDMULHv4i32 = 3199, |
| 3215 | VQDMULHv8i16 = 3200, |
| 3216 | VQDMULLslv2i32 = 3201, |
| 3217 | VQDMULLslv4i16 = 3202, |
| 3218 | VQDMULLv2i64 = 3203, |
| 3219 | VQDMULLv4i32 = 3204, |
| 3220 | VQMOVNsuv2i32 = 3205, |
| 3221 | VQMOVNsuv4i16 = 3206, |
| 3222 | VQMOVNsuv8i8 = 3207, |
| 3223 | VQMOVNsv2i32 = 3208, |
| 3224 | VQMOVNsv4i16 = 3209, |
| 3225 | VQMOVNsv8i8 = 3210, |
| 3226 | VQMOVNuv2i32 = 3211, |
| 3227 | VQMOVNuv4i16 = 3212, |
| 3228 | VQMOVNuv8i8 = 3213, |
| 3229 | VQNEGv16i8 = 3214, |
| 3230 | VQNEGv2i32 = 3215, |
| 3231 | VQNEGv4i16 = 3216, |
| 3232 | VQNEGv4i32 = 3217, |
| 3233 | VQNEGv8i16 = 3218, |
| 3234 | VQNEGv8i8 = 3219, |
| 3235 | VQRDMLAHslv2i32 = 3220, |
| 3236 | VQRDMLAHslv4i16 = 3221, |
| 3237 | VQRDMLAHslv4i32 = 3222, |
| 3238 | VQRDMLAHslv8i16 = 3223, |
| 3239 | VQRDMLAHv2i32 = 3224, |
| 3240 | VQRDMLAHv4i16 = 3225, |
| 3241 | VQRDMLAHv4i32 = 3226, |
| 3242 | VQRDMLAHv8i16 = 3227, |
| 3243 | VQRDMLSHslv2i32 = 3228, |
| 3244 | VQRDMLSHslv4i16 = 3229, |
| 3245 | VQRDMLSHslv4i32 = 3230, |
| 3246 | VQRDMLSHslv8i16 = 3231, |
| 3247 | VQRDMLSHv2i32 = 3232, |
| 3248 | VQRDMLSHv4i16 = 3233, |
| 3249 | VQRDMLSHv4i32 = 3234, |
| 3250 | VQRDMLSHv8i16 = 3235, |
| 3251 | VQRDMULHslv2i32 = 3236, |
| 3252 | VQRDMULHslv4i16 = 3237, |
| 3253 | VQRDMULHslv4i32 = 3238, |
| 3254 | VQRDMULHslv8i16 = 3239, |
| 3255 | VQRDMULHv2i32 = 3240, |
| 3256 | VQRDMULHv4i16 = 3241, |
| 3257 | VQRDMULHv4i32 = 3242, |
| 3258 | VQRDMULHv8i16 = 3243, |
| 3259 | VQRSHLsv16i8 = 3244, |
| 3260 | VQRSHLsv1i64 = 3245, |
| 3261 | VQRSHLsv2i32 = 3246, |
| 3262 | VQRSHLsv2i64 = 3247, |
| 3263 | VQRSHLsv4i16 = 3248, |
| 3264 | VQRSHLsv4i32 = 3249, |
| 3265 | VQRSHLsv8i16 = 3250, |
| 3266 | VQRSHLsv8i8 = 3251, |
| 3267 | VQRSHLuv16i8 = 3252, |
| 3268 | VQRSHLuv1i64 = 3253, |
| 3269 | VQRSHLuv2i32 = 3254, |
| 3270 | VQRSHLuv2i64 = 3255, |
| 3271 | VQRSHLuv4i16 = 3256, |
| 3272 | VQRSHLuv4i32 = 3257, |
| 3273 | VQRSHLuv8i16 = 3258, |
| 3274 | VQRSHLuv8i8 = 3259, |
| 3275 | VQRSHRNsv2i32 = 3260, |
| 3276 | VQRSHRNsv4i16 = 3261, |
| 3277 | VQRSHRNsv8i8 = 3262, |
| 3278 | VQRSHRNuv2i32 = 3263, |
| 3279 | VQRSHRNuv4i16 = 3264, |
| 3280 | VQRSHRNuv8i8 = 3265, |
| 3281 | VQRSHRUNv2i32 = 3266, |
| 3282 | VQRSHRUNv4i16 = 3267, |
| 3283 | VQRSHRUNv8i8 = 3268, |
| 3284 | VQSHLsiv16i8 = 3269, |
| 3285 | VQSHLsiv1i64 = 3270, |
| 3286 | VQSHLsiv2i32 = 3271, |
| 3287 | VQSHLsiv2i64 = 3272, |
| 3288 | VQSHLsiv4i16 = 3273, |
| 3289 | VQSHLsiv4i32 = 3274, |
| 3290 | VQSHLsiv8i16 = 3275, |
| 3291 | VQSHLsiv8i8 = 3276, |
| 3292 | VQSHLsuv16i8 = 3277, |
| 3293 | VQSHLsuv1i64 = 3278, |
| 3294 | VQSHLsuv2i32 = 3279, |
| 3295 | VQSHLsuv2i64 = 3280, |
| 3296 | VQSHLsuv4i16 = 3281, |
| 3297 | VQSHLsuv4i32 = 3282, |
| 3298 | VQSHLsuv8i16 = 3283, |
| 3299 | VQSHLsuv8i8 = 3284, |
| 3300 | VQSHLsv16i8 = 3285, |
| 3301 | VQSHLsv1i64 = 3286, |
| 3302 | VQSHLsv2i32 = 3287, |
| 3303 | VQSHLsv2i64 = 3288, |
| 3304 | VQSHLsv4i16 = 3289, |
| 3305 | VQSHLsv4i32 = 3290, |
| 3306 | VQSHLsv8i16 = 3291, |
| 3307 | VQSHLsv8i8 = 3292, |
| 3308 | VQSHLuiv16i8 = 3293, |
| 3309 | VQSHLuiv1i64 = 3294, |
| 3310 | VQSHLuiv2i32 = 3295, |
| 3311 | VQSHLuiv2i64 = 3296, |
| 3312 | VQSHLuiv4i16 = 3297, |
| 3313 | VQSHLuiv4i32 = 3298, |
| 3314 | VQSHLuiv8i16 = 3299, |
| 3315 | VQSHLuiv8i8 = 3300, |
| 3316 | VQSHLuv16i8 = 3301, |
| 3317 | VQSHLuv1i64 = 3302, |
| 3318 | VQSHLuv2i32 = 3303, |
| 3319 | VQSHLuv2i64 = 3304, |
| 3320 | VQSHLuv4i16 = 3305, |
| 3321 | VQSHLuv4i32 = 3306, |
| 3322 | VQSHLuv8i16 = 3307, |
| 3323 | VQSHLuv8i8 = 3308, |
| 3324 | VQSHRNsv2i32 = 3309, |
| 3325 | VQSHRNsv4i16 = 3310, |
| 3326 | VQSHRNsv8i8 = 3311, |
| 3327 | VQSHRNuv2i32 = 3312, |
| 3328 | VQSHRNuv4i16 = 3313, |
| 3329 | VQSHRNuv8i8 = 3314, |
| 3330 | VQSHRUNv2i32 = 3315, |
| 3331 | VQSHRUNv4i16 = 3316, |
| 3332 | VQSHRUNv8i8 = 3317, |
| 3333 | VQSUBsv16i8 = 3318, |
| 3334 | VQSUBsv1i64 = 3319, |
| 3335 | VQSUBsv2i32 = 3320, |
| 3336 | VQSUBsv2i64 = 3321, |
| 3337 | VQSUBsv4i16 = 3322, |
| 3338 | VQSUBsv4i32 = 3323, |
| 3339 | VQSUBsv8i16 = 3324, |
| 3340 | VQSUBsv8i8 = 3325, |
| 3341 | VQSUBuv16i8 = 3326, |
| 3342 | VQSUBuv1i64 = 3327, |
| 3343 | VQSUBuv2i32 = 3328, |
| 3344 | VQSUBuv2i64 = 3329, |
| 3345 | VQSUBuv4i16 = 3330, |
| 3346 | VQSUBuv4i32 = 3331, |
| 3347 | VQSUBuv8i16 = 3332, |
| 3348 | VQSUBuv8i8 = 3333, |
| 3349 | VRADDHNv2i32 = 3334, |
| 3350 | VRADDHNv4i16 = 3335, |
| 3351 | VRADDHNv8i8 = 3336, |
| 3352 | VRECPEd = 3337, |
| 3353 | VRECPEfd = 3338, |
| 3354 | VRECPEfq = 3339, |
| 3355 | VRECPEhd = 3340, |
| 3356 | VRECPEhq = 3341, |
| 3357 | VRECPEq = 3342, |
| 3358 | VRECPSfd = 3343, |
| 3359 | VRECPSfq = 3344, |
| 3360 | VRECPShd = 3345, |
| 3361 | VRECPShq = 3346, |
| 3362 | VREV16d8 = 3347, |
| 3363 | VREV16q8 = 3348, |
| 3364 | VREV32d16 = 3349, |
| 3365 | VREV32d8 = 3350, |
| 3366 | VREV32q16 = 3351, |
| 3367 | VREV32q8 = 3352, |
| 3368 | VREV64d16 = 3353, |
| 3369 | VREV64d32 = 3354, |
| 3370 | VREV64d8 = 3355, |
| 3371 | VREV64q16 = 3356, |
| 3372 | VREV64q32 = 3357, |
| 3373 | VREV64q8 = 3358, |
| 3374 | VRHADDsv16i8 = 3359, |
| 3375 | VRHADDsv2i32 = 3360, |
| 3376 | VRHADDsv4i16 = 3361, |
| 3377 | VRHADDsv4i32 = 3362, |
| 3378 | VRHADDsv8i16 = 3363, |
| 3379 | VRHADDsv8i8 = 3364, |
| 3380 | VRHADDuv16i8 = 3365, |
| 3381 | VRHADDuv2i32 = 3366, |
| 3382 | VRHADDuv4i16 = 3367, |
| 3383 | VRHADDuv4i32 = 3368, |
| 3384 | VRHADDuv8i16 = 3369, |
| 3385 | VRHADDuv8i8 = 3370, |
| 3386 | VRINTAD = 3371, |
| 3387 | VRINTAH = 3372, |
| 3388 | VRINTANDf = 3373, |
| 3389 | VRINTANDh = 3374, |
| 3390 | VRINTANQf = 3375, |
| 3391 | VRINTANQh = 3376, |
| 3392 | VRINTAS = 3377, |
| 3393 | VRINTMD = 3378, |
| 3394 | VRINTMH = 3379, |
| 3395 | VRINTMNDf = 3380, |
| 3396 | VRINTMNDh = 3381, |
| 3397 | VRINTMNQf = 3382, |
| 3398 | VRINTMNQh = 3383, |
| 3399 | VRINTMS = 3384, |
| 3400 | VRINTND = 3385, |
| 3401 | VRINTNH = 3386, |
| 3402 | VRINTNNDf = 3387, |
| 3403 | VRINTNNDh = 3388, |
| 3404 | VRINTNNQf = 3389, |
| 3405 | VRINTNNQh = 3390, |
| 3406 | VRINTNS = 3391, |
| 3407 | VRINTPD = 3392, |
| 3408 | VRINTPH = 3393, |
| 3409 | VRINTPNDf = 3394, |
| 3410 | VRINTPNDh = 3395, |
| 3411 | VRINTPNQf = 3396, |
| 3412 | VRINTPNQh = 3397, |
| 3413 | VRINTPS = 3398, |
| 3414 | VRINTRD = 3399, |
| 3415 | VRINTRH = 3400, |
| 3416 | VRINTRS = 3401, |
| 3417 | VRINTXD = 3402, |
| 3418 | VRINTXH = 3403, |
| 3419 | VRINTXNDf = 3404, |
| 3420 | VRINTXNDh = 3405, |
| 3421 | VRINTXNQf = 3406, |
| 3422 | VRINTXNQh = 3407, |
| 3423 | VRINTXS = 3408, |
| 3424 | VRINTZD = 3409, |
| 3425 | VRINTZH = 3410, |
| 3426 | VRINTZNDf = 3411, |
| 3427 | VRINTZNDh = 3412, |
| 3428 | VRINTZNQf = 3413, |
| 3429 | VRINTZNQh = 3414, |
| 3430 | VRINTZS = 3415, |
| 3431 | VRSHLsv16i8 = 3416, |
| 3432 | VRSHLsv1i64 = 3417, |
| 3433 | VRSHLsv2i32 = 3418, |
| 3434 | VRSHLsv2i64 = 3419, |
| 3435 | VRSHLsv4i16 = 3420, |
| 3436 | VRSHLsv4i32 = 3421, |
| 3437 | VRSHLsv8i16 = 3422, |
| 3438 | VRSHLsv8i8 = 3423, |
| 3439 | VRSHLuv16i8 = 3424, |
| 3440 | VRSHLuv1i64 = 3425, |
| 3441 | VRSHLuv2i32 = 3426, |
| 3442 | VRSHLuv2i64 = 3427, |
| 3443 | VRSHLuv4i16 = 3428, |
| 3444 | VRSHLuv4i32 = 3429, |
| 3445 | VRSHLuv8i16 = 3430, |
| 3446 | VRSHLuv8i8 = 3431, |
| 3447 | VRSHRNv2i32 = 3432, |
| 3448 | VRSHRNv4i16 = 3433, |
| 3449 | VRSHRNv8i8 = 3434, |
| 3450 | VRSHRsv16i8 = 3435, |
| 3451 | VRSHRsv1i64 = 3436, |
| 3452 | VRSHRsv2i32 = 3437, |
| 3453 | VRSHRsv2i64 = 3438, |
| 3454 | VRSHRsv4i16 = 3439, |
| 3455 | VRSHRsv4i32 = 3440, |
| 3456 | VRSHRsv8i16 = 3441, |
| 3457 | VRSHRsv8i8 = 3442, |
| 3458 | VRSHRuv16i8 = 3443, |
| 3459 | VRSHRuv1i64 = 3444, |
| 3460 | VRSHRuv2i32 = 3445, |
| 3461 | VRSHRuv2i64 = 3446, |
| 3462 | VRSHRuv4i16 = 3447, |
| 3463 | VRSHRuv4i32 = 3448, |
| 3464 | VRSHRuv8i16 = 3449, |
| 3465 | VRSHRuv8i8 = 3450, |
| 3466 | VRSQRTEd = 3451, |
| 3467 | VRSQRTEfd = 3452, |
| 3468 | VRSQRTEfq = 3453, |
| 3469 | VRSQRTEhd = 3454, |
| 3470 | VRSQRTEhq = 3455, |
| 3471 | VRSQRTEq = 3456, |
| 3472 | VRSQRTSfd = 3457, |
| 3473 | VRSQRTSfq = 3458, |
| 3474 | VRSQRTShd = 3459, |
| 3475 | VRSQRTShq = 3460, |
| 3476 | VRSRAsv16i8 = 3461, |
| 3477 | VRSRAsv1i64 = 3462, |
| 3478 | VRSRAsv2i32 = 3463, |
| 3479 | VRSRAsv2i64 = 3464, |
| 3480 | VRSRAsv4i16 = 3465, |
| 3481 | VRSRAsv4i32 = 3466, |
| 3482 | VRSRAsv8i16 = 3467, |
| 3483 | VRSRAsv8i8 = 3468, |
| 3484 | VRSRAuv16i8 = 3469, |
| 3485 | VRSRAuv1i64 = 3470, |
| 3486 | VRSRAuv2i32 = 3471, |
| 3487 | VRSRAuv2i64 = 3472, |
| 3488 | VRSRAuv4i16 = 3473, |
| 3489 | VRSRAuv4i32 = 3474, |
| 3490 | VRSRAuv8i16 = 3475, |
| 3491 | VRSRAuv8i8 = 3476, |
| 3492 | VRSUBHNv2i32 = 3477, |
| 3493 | VRSUBHNv4i16 = 3478, |
| 3494 | VRSUBHNv8i8 = 3479, |
| 3495 | VSCCLRMD = 3480, |
| 3496 | VSCCLRMS = 3481, |
| 3497 | VSDOTD = 3482, |
| 3498 | VSDOTDI = 3483, |
| 3499 | VSDOTQ = 3484, |
| 3500 | VSDOTQI = 3485, |
| 3501 | VSELEQD = 3486, |
| 3502 | VSELEQH = 3487, |
| 3503 | VSELEQS = 3488, |
| 3504 | VSELGED = 3489, |
| 3505 | VSELGEH = 3490, |
| 3506 | VSELGES = 3491, |
| 3507 | VSELGTD = 3492, |
| 3508 | VSELGTH = 3493, |
| 3509 | VSELGTS = 3494, |
| 3510 | VSELVSD = 3495, |
| 3511 | VSELVSH = 3496, |
| 3512 | VSELVSS = 3497, |
| 3513 | VSETLNi16 = 3498, |
| 3514 | VSETLNi32 = 3499, |
| 3515 | VSETLNi8 = 3500, |
| 3516 | VSHLLi16 = 3501, |
| 3517 | VSHLLi32 = 3502, |
| 3518 | VSHLLi8 = 3503, |
| 3519 | VSHLLsv2i64 = 3504, |
| 3520 | VSHLLsv4i32 = 3505, |
| 3521 | VSHLLsv8i16 = 3506, |
| 3522 | VSHLLuv2i64 = 3507, |
| 3523 | VSHLLuv4i32 = 3508, |
| 3524 | VSHLLuv8i16 = 3509, |
| 3525 | VSHLiv16i8 = 3510, |
| 3526 | VSHLiv1i64 = 3511, |
| 3527 | VSHLiv2i32 = 3512, |
| 3528 | VSHLiv2i64 = 3513, |
| 3529 | VSHLiv4i16 = 3514, |
| 3530 | VSHLiv4i32 = 3515, |
| 3531 | VSHLiv8i16 = 3516, |
| 3532 | VSHLiv8i8 = 3517, |
| 3533 | VSHLsv16i8 = 3518, |
| 3534 | VSHLsv1i64 = 3519, |
| 3535 | VSHLsv2i32 = 3520, |
| 3536 | VSHLsv2i64 = 3521, |
| 3537 | VSHLsv4i16 = 3522, |
| 3538 | VSHLsv4i32 = 3523, |
| 3539 | VSHLsv8i16 = 3524, |
| 3540 | VSHLsv8i8 = 3525, |
| 3541 | VSHLuv16i8 = 3526, |
| 3542 | VSHLuv1i64 = 3527, |
| 3543 | VSHLuv2i32 = 3528, |
| 3544 | VSHLuv2i64 = 3529, |
| 3545 | VSHLuv4i16 = 3530, |
| 3546 | VSHLuv4i32 = 3531, |
| 3547 | VSHLuv8i16 = 3532, |
| 3548 | VSHLuv8i8 = 3533, |
| 3549 | VSHRNv2i32 = 3534, |
| 3550 | VSHRNv4i16 = 3535, |
| 3551 | VSHRNv8i8 = 3536, |
| 3552 | VSHRsv16i8 = 3537, |
| 3553 | VSHRsv1i64 = 3538, |
| 3554 | VSHRsv2i32 = 3539, |
| 3555 | VSHRsv2i64 = 3540, |
| 3556 | VSHRsv4i16 = 3541, |
| 3557 | VSHRsv4i32 = 3542, |
| 3558 | VSHRsv8i16 = 3543, |
| 3559 | VSHRsv8i8 = 3544, |
| 3560 | VSHRuv16i8 = 3545, |
| 3561 | VSHRuv1i64 = 3546, |
| 3562 | VSHRuv2i32 = 3547, |
| 3563 | VSHRuv2i64 = 3548, |
| 3564 | VSHRuv4i16 = 3549, |
| 3565 | VSHRuv4i32 = 3550, |
| 3566 | VSHRuv8i16 = 3551, |
| 3567 | VSHRuv8i8 = 3552, |
| 3568 | VSHTOD = 3553, |
| 3569 | VSHTOH = 3554, |
| 3570 | VSHTOS = 3555, |
| 3571 | VSITOD = 3556, |
| 3572 | VSITOH = 3557, |
| 3573 | VSITOS = 3558, |
| 3574 | VSLIv16i8 = 3559, |
| 3575 | VSLIv1i64 = 3560, |
| 3576 | VSLIv2i32 = 3561, |
| 3577 | VSLIv2i64 = 3562, |
| 3578 | VSLIv4i16 = 3563, |
| 3579 | VSLIv4i32 = 3564, |
| 3580 | VSLIv8i16 = 3565, |
| 3581 | VSLIv8i8 = 3566, |
| 3582 | VSLTOD = 3567, |
| 3583 | VSLTOH = 3568, |
| 3584 | VSLTOS = 3569, |
| 3585 | VSMMLA = 3570, |
| 3586 | VSQRTD = 3571, |
| 3587 | VSQRTH = 3572, |
| 3588 | VSQRTS = 3573, |
| 3589 | VSRAsv16i8 = 3574, |
| 3590 | VSRAsv1i64 = 3575, |
| 3591 | VSRAsv2i32 = 3576, |
| 3592 | VSRAsv2i64 = 3577, |
| 3593 | VSRAsv4i16 = 3578, |
| 3594 | VSRAsv4i32 = 3579, |
| 3595 | VSRAsv8i16 = 3580, |
| 3596 | VSRAsv8i8 = 3581, |
| 3597 | VSRAuv16i8 = 3582, |
| 3598 | VSRAuv1i64 = 3583, |
| 3599 | VSRAuv2i32 = 3584, |
| 3600 | VSRAuv2i64 = 3585, |
| 3601 | VSRAuv4i16 = 3586, |
| 3602 | VSRAuv4i32 = 3587, |
| 3603 | VSRAuv8i16 = 3588, |
| 3604 | VSRAuv8i8 = 3589, |
| 3605 | VSRIv16i8 = 3590, |
| 3606 | VSRIv1i64 = 3591, |
| 3607 | VSRIv2i32 = 3592, |
| 3608 | VSRIv2i64 = 3593, |
| 3609 | VSRIv4i16 = 3594, |
| 3610 | VSRIv4i32 = 3595, |
| 3611 | VSRIv8i16 = 3596, |
| 3612 | VSRIv8i8 = 3597, |
| 3613 | VST1LNd16 = 3598, |
| 3614 | VST1LNd16_UPD = 3599, |
| 3615 | VST1LNd32 = 3600, |
| 3616 | VST1LNd32_UPD = 3601, |
| 3617 | VST1LNd8 = 3602, |
| 3618 | VST1LNd8_UPD = 3603, |
| 3619 | VST1LNq16Pseudo = 3604, |
| 3620 | VST1LNq16Pseudo_UPD = 3605, |
| 3621 | VST1LNq32Pseudo = 3606, |
| 3622 | VST1LNq32Pseudo_UPD = 3607, |
| 3623 | VST1LNq8Pseudo = 3608, |
| 3624 | VST1LNq8Pseudo_UPD = 3609, |
| 3625 | VST1d16 = 3610, |
| 3626 | VST1d16Q = 3611, |
| 3627 | VST1d16QPseudo = 3612, |
| 3628 | VST1d16QPseudoWB_fixed = 3613, |
| 3629 | VST1d16QPseudoWB_register = 3614, |
| 3630 | VST1d16Qwb_fixed = 3615, |
| 3631 | VST1d16Qwb_register = 3616, |
| 3632 | VST1d16T = 3617, |
| 3633 | VST1d16TPseudo = 3618, |
| 3634 | VST1d16TPseudoWB_fixed = 3619, |
| 3635 | VST1d16TPseudoWB_register = 3620, |
| 3636 | VST1d16Twb_fixed = 3621, |
| 3637 | VST1d16Twb_register = 3622, |
| 3638 | VST1d16wb_fixed = 3623, |
| 3639 | VST1d16wb_register = 3624, |
| 3640 | VST1d32 = 3625, |
| 3641 | VST1d32Q = 3626, |
| 3642 | VST1d32QPseudo = 3627, |
| 3643 | VST1d32QPseudoWB_fixed = 3628, |
| 3644 | VST1d32QPseudoWB_register = 3629, |
| 3645 | VST1d32Qwb_fixed = 3630, |
| 3646 | VST1d32Qwb_register = 3631, |
| 3647 | VST1d32T = 3632, |
| 3648 | VST1d32TPseudo = 3633, |
| 3649 | VST1d32TPseudoWB_fixed = 3634, |
| 3650 | VST1d32TPseudoWB_register = 3635, |
| 3651 | VST1d32Twb_fixed = 3636, |
| 3652 | VST1d32Twb_register = 3637, |
| 3653 | VST1d32wb_fixed = 3638, |
| 3654 | VST1d32wb_register = 3639, |
| 3655 | VST1d64 = 3640, |
| 3656 | VST1d64Q = 3641, |
| 3657 | VST1d64QPseudo = 3642, |
| 3658 | VST1d64QPseudoWB_fixed = 3643, |
| 3659 | VST1d64QPseudoWB_register = 3644, |
| 3660 | VST1d64Qwb_fixed = 3645, |
| 3661 | VST1d64Qwb_register = 3646, |
| 3662 | VST1d64T = 3647, |
| 3663 | VST1d64TPseudo = 3648, |
| 3664 | VST1d64TPseudoWB_fixed = 3649, |
| 3665 | VST1d64TPseudoWB_register = 3650, |
| 3666 | VST1d64Twb_fixed = 3651, |
| 3667 | VST1d64Twb_register = 3652, |
| 3668 | VST1d64wb_fixed = 3653, |
| 3669 | VST1d64wb_register = 3654, |
| 3670 | VST1d8 = 3655, |
| 3671 | VST1d8Q = 3656, |
| 3672 | VST1d8QPseudo = 3657, |
| 3673 | VST1d8QPseudoWB_fixed = 3658, |
| 3674 | VST1d8QPseudoWB_register = 3659, |
| 3675 | VST1d8Qwb_fixed = 3660, |
| 3676 | VST1d8Qwb_register = 3661, |
| 3677 | VST1d8T = 3662, |
| 3678 | VST1d8TPseudo = 3663, |
| 3679 | VST1d8TPseudoWB_fixed = 3664, |
| 3680 | VST1d8TPseudoWB_register = 3665, |
| 3681 | VST1d8Twb_fixed = 3666, |
| 3682 | VST1d8Twb_register = 3667, |
| 3683 | VST1d8wb_fixed = 3668, |
| 3684 | VST1d8wb_register = 3669, |
| 3685 | VST1q16 = 3670, |
| 3686 | VST1q16HighQPseudo = 3671, |
| 3687 | VST1q16HighQPseudo_UPD = 3672, |
| 3688 | VST1q16HighTPseudo = 3673, |
| 3689 | VST1q16HighTPseudo_UPD = 3674, |
| 3690 | VST1q16LowQPseudo_UPD = 3675, |
| 3691 | VST1q16LowTPseudo_UPD = 3676, |
| 3692 | VST1q16wb_fixed = 3677, |
| 3693 | VST1q16wb_register = 3678, |
| 3694 | VST1q32 = 3679, |
| 3695 | VST1q32HighQPseudo = 3680, |
| 3696 | VST1q32HighQPseudo_UPD = 3681, |
| 3697 | VST1q32HighTPseudo = 3682, |
| 3698 | VST1q32HighTPseudo_UPD = 3683, |
| 3699 | VST1q32LowQPseudo_UPD = 3684, |
| 3700 | VST1q32LowTPseudo_UPD = 3685, |
| 3701 | VST1q32wb_fixed = 3686, |
| 3702 | VST1q32wb_register = 3687, |
| 3703 | VST1q64 = 3688, |
| 3704 | VST1q64HighQPseudo = 3689, |
| 3705 | VST1q64HighQPseudo_UPD = 3690, |
| 3706 | VST1q64HighTPseudo = 3691, |
| 3707 | VST1q64HighTPseudo_UPD = 3692, |
| 3708 | VST1q64LowQPseudo_UPD = 3693, |
| 3709 | VST1q64LowTPseudo_UPD = 3694, |
| 3710 | VST1q64wb_fixed = 3695, |
| 3711 | VST1q64wb_register = 3696, |
| 3712 | VST1q8 = 3697, |
| 3713 | VST1q8HighQPseudo = 3698, |
| 3714 | VST1q8HighQPseudo_UPD = 3699, |
| 3715 | VST1q8HighTPseudo = 3700, |
| 3716 | VST1q8HighTPseudo_UPD = 3701, |
| 3717 | VST1q8LowQPseudo_UPD = 3702, |
| 3718 | VST1q8LowTPseudo_UPD = 3703, |
| 3719 | VST1q8wb_fixed = 3704, |
| 3720 | VST1q8wb_register = 3705, |
| 3721 | VST2LNd16 = 3706, |
| 3722 | VST2LNd16Pseudo = 3707, |
| 3723 | VST2LNd16Pseudo_UPD = 3708, |
| 3724 | VST2LNd16_UPD = 3709, |
| 3725 | VST2LNd32 = 3710, |
| 3726 | VST2LNd32Pseudo = 3711, |
| 3727 | VST2LNd32Pseudo_UPD = 3712, |
| 3728 | VST2LNd32_UPD = 3713, |
| 3729 | VST2LNd8 = 3714, |
| 3730 | VST2LNd8Pseudo = 3715, |
| 3731 | VST2LNd8Pseudo_UPD = 3716, |
| 3732 | VST2LNd8_UPD = 3717, |
| 3733 | VST2LNq16 = 3718, |
| 3734 | VST2LNq16Pseudo = 3719, |
| 3735 | VST2LNq16Pseudo_UPD = 3720, |
| 3736 | VST2LNq16_UPD = 3721, |
| 3737 | VST2LNq32 = 3722, |
| 3738 | VST2LNq32Pseudo = 3723, |
| 3739 | VST2LNq32Pseudo_UPD = 3724, |
| 3740 | VST2LNq32_UPD = 3725, |
| 3741 | VST2b16 = 3726, |
| 3742 | VST2b16wb_fixed = 3727, |
| 3743 | VST2b16wb_register = 3728, |
| 3744 | VST2b32 = 3729, |
| 3745 | VST2b32wb_fixed = 3730, |
| 3746 | VST2b32wb_register = 3731, |
| 3747 | VST2b8 = 3732, |
| 3748 | VST2b8wb_fixed = 3733, |
| 3749 | VST2b8wb_register = 3734, |
| 3750 | VST2d16 = 3735, |
| 3751 | VST2d16wb_fixed = 3736, |
| 3752 | VST2d16wb_register = 3737, |
| 3753 | VST2d32 = 3738, |
| 3754 | VST2d32wb_fixed = 3739, |
| 3755 | VST2d32wb_register = 3740, |
| 3756 | VST2d8 = 3741, |
| 3757 | VST2d8wb_fixed = 3742, |
| 3758 | VST2d8wb_register = 3743, |
| 3759 | VST2q16 = 3744, |
| 3760 | VST2q16Pseudo = 3745, |
| 3761 | VST2q16PseudoWB_fixed = 3746, |
| 3762 | VST2q16PseudoWB_register = 3747, |
| 3763 | VST2q16wb_fixed = 3748, |
| 3764 | VST2q16wb_register = 3749, |
| 3765 | VST2q32 = 3750, |
| 3766 | VST2q32Pseudo = 3751, |
| 3767 | VST2q32PseudoWB_fixed = 3752, |
| 3768 | VST2q32PseudoWB_register = 3753, |
| 3769 | VST2q32wb_fixed = 3754, |
| 3770 | VST2q32wb_register = 3755, |
| 3771 | VST2q8 = 3756, |
| 3772 | VST2q8Pseudo = 3757, |
| 3773 | VST2q8PseudoWB_fixed = 3758, |
| 3774 | VST2q8PseudoWB_register = 3759, |
| 3775 | VST2q8wb_fixed = 3760, |
| 3776 | VST2q8wb_register = 3761, |
| 3777 | VST3LNd16 = 3762, |
| 3778 | VST3LNd16Pseudo = 3763, |
| 3779 | VST3LNd16Pseudo_UPD = 3764, |
| 3780 | VST3LNd16_UPD = 3765, |
| 3781 | VST3LNd32 = 3766, |
| 3782 | VST3LNd32Pseudo = 3767, |
| 3783 | VST3LNd32Pseudo_UPD = 3768, |
| 3784 | VST3LNd32_UPD = 3769, |
| 3785 | VST3LNd8 = 3770, |
| 3786 | VST3LNd8Pseudo = 3771, |
| 3787 | VST3LNd8Pseudo_UPD = 3772, |
| 3788 | VST3LNd8_UPD = 3773, |
| 3789 | VST3LNq16 = 3774, |
| 3790 | VST3LNq16Pseudo = 3775, |
| 3791 | VST3LNq16Pseudo_UPD = 3776, |
| 3792 | VST3LNq16_UPD = 3777, |
| 3793 | VST3LNq32 = 3778, |
| 3794 | VST3LNq32Pseudo = 3779, |
| 3795 | VST3LNq32Pseudo_UPD = 3780, |
| 3796 | VST3LNq32_UPD = 3781, |
| 3797 | VST3d16 = 3782, |
| 3798 | VST3d16Pseudo = 3783, |
| 3799 | VST3d16Pseudo_UPD = 3784, |
| 3800 | VST3d16_UPD = 3785, |
| 3801 | VST3d32 = 3786, |
| 3802 | VST3d32Pseudo = 3787, |
| 3803 | VST3d32Pseudo_UPD = 3788, |
| 3804 | VST3d32_UPD = 3789, |
| 3805 | VST3d8 = 3790, |
| 3806 | VST3d8Pseudo = 3791, |
| 3807 | VST3d8Pseudo_UPD = 3792, |
| 3808 | VST3d8_UPD = 3793, |
| 3809 | VST3q16 = 3794, |
| 3810 | VST3q16Pseudo_UPD = 3795, |
| 3811 | VST3q16_UPD = 3796, |
| 3812 | VST3q16oddPseudo = 3797, |
| 3813 | VST3q16oddPseudo_UPD = 3798, |
| 3814 | VST3q32 = 3799, |
| 3815 | VST3q32Pseudo_UPD = 3800, |
| 3816 | VST3q32_UPD = 3801, |
| 3817 | VST3q32oddPseudo = 3802, |
| 3818 | VST3q32oddPseudo_UPD = 3803, |
| 3819 | VST3q8 = 3804, |
| 3820 | VST3q8Pseudo_UPD = 3805, |
| 3821 | VST3q8_UPD = 3806, |
| 3822 | VST3q8oddPseudo = 3807, |
| 3823 | VST3q8oddPseudo_UPD = 3808, |
| 3824 | VST4LNd16 = 3809, |
| 3825 | VST4LNd16Pseudo = 3810, |
| 3826 | VST4LNd16Pseudo_UPD = 3811, |
| 3827 | VST4LNd16_UPD = 3812, |
| 3828 | VST4LNd32 = 3813, |
| 3829 | VST4LNd32Pseudo = 3814, |
| 3830 | VST4LNd32Pseudo_UPD = 3815, |
| 3831 | VST4LNd32_UPD = 3816, |
| 3832 | VST4LNd8 = 3817, |
| 3833 | VST4LNd8Pseudo = 3818, |
| 3834 | VST4LNd8Pseudo_UPD = 3819, |
| 3835 | VST4LNd8_UPD = 3820, |
| 3836 | VST4LNq16 = 3821, |
| 3837 | VST4LNq16Pseudo = 3822, |
| 3838 | VST4LNq16Pseudo_UPD = 3823, |
| 3839 | VST4LNq16_UPD = 3824, |
| 3840 | VST4LNq32 = 3825, |
| 3841 | VST4LNq32Pseudo = 3826, |
| 3842 | VST4LNq32Pseudo_UPD = 3827, |
| 3843 | VST4LNq32_UPD = 3828, |
| 3844 | VST4d16 = 3829, |
| 3845 | VST4d16Pseudo = 3830, |
| 3846 | VST4d16Pseudo_UPD = 3831, |
| 3847 | VST4d16_UPD = 3832, |
| 3848 | VST4d32 = 3833, |
| 3849 | VST4d32Pseudo = 3834, |
| 3850 | VST4d32Pseudo_UPD = 3835, |
| 3851 | VST4d32_UPD = 3836, |
| 3852 | VST4d8 = 3837, |
| 3853 | VST4d8Pseudo = 3838, |
| 3854 | VST4d8Pseudo_UPD = 3839, |
| 3855 | VST4d8_UPD = 3840, |
| 3856 | VST4q16 = 3841, |
| 3857 | VST4q16Pseudo_UPD = 3842, |
| 3858 | VST4q16_UPD = 3843, |
| 3859 | VST4q16oddPseudo = 3844, |
| 3860 | VST4q16oddPseudo_UPD = 3845, |
| 3861 | VST4q32 = 3846, |
| 3862 | VST4q32Pseudo_UPD = 3847, |
| 3863 | VST4q32_UPD = 3848, |
| 3864 | VST4q32oddPseudo = 3849, |
| 3865 | VST4q32oddPseudo_UPD = 3850, |
| 3866 | VST4q8 = 3851, |
| 3867 | VST4q8Pseudo_UPD = 3852, |
| 3868 | VST4q8_UPD = 3853, |
| 3869 | VST4q8oddPseudo = 3854, |
| 3870 | VST4q8oddPseudo_UPD = 3855, |
| 3871 | VSTMDDB_UPD = 3856, |
| 3872 | VSTMDIA = 3857, |
| 3873 | VSTMDIA_UPD = 3858, |
| 3874 | VSTMQIA = 3859, |
| 3875 | VSTMSDB_UPD = 3860, |
| 3876 | VSTMSIA = 3861, |
| 3877 | VSTMSIA_UPD = 3862, |
| 3878 | VSTRD = 3863, |
| 3879 | VSTRH = 3864, |
| 3880 | VSTRS = 3865, |
| 3881 | VSTR_FPCXTNS_off = 3866, |
| 3882 | VSTR_FPCXTNS_post = 3867, |
| 3883 | VSTR_FPCXTNS_pre = 3868, |
| 3884 | VSTR_FPCXTS_off = 3869, |
| 3885 | VSTR_FPCXTS_post = 3870, |
| 3886 | VSTR_FPCXTS_pre = 3871, |
| 3887 | VSTR_FPSCR_NZCVQC_off = 3872, |
| 3888 | VSTR_FPSCR_NZCVQC_post = 3873, |
| 3889 | VSTR_FPSCR_NZCVQC_pre = 3874, |
| 3890 | VSTR_FPSCR_off = 3875, |
| 3891 | VSTR_FPSCR_post = 3876, |
| 3892 | VSTR_FPSCR_pre = 3877, |
| 3893 | VSTR_P0_off = 3878, |
| 3894 | VSTR_P0_post = 3879, |
| 3895 | VSTR_P0_pre = 3880, |
| 3896 | VSTR_VPR_off = 3881, |
| 3897 | VSTR_VPR_post = 3882, |
| 3898 | VSTR_VPR_pre = 3883, |
| 3899 | VSUBD = 3884, |
| 3900 | VSUBH = 3885, |
| 3901 | VSUBHNv2i32 = 3886, |
| 3902 | VSUBHNv4i16 = 3887, |
| 3903 | VSUBHNv8i8 = 3888, |
| 3904 | VSUBLsv2i64 = 3889, |
| 3905 | VSUBLsv4i32 = 3890, |
| 3906 | VSUBLsv8i16 = 3891, |
| 3907 | VSUBLuv2i64 = 3892, |
| 3908 | VSUBLuv4i32 = 3893, |
| 3909 | VSUBLuv8i16 = 3894, |
| 3910 | VSUBS = 3895, |
| 3911 | VSUBWsv2i64 = 3896, |
| 3912 | VSUBWsv4i32 = 3897, |
| 3913 | VSUBWsv8i16 = 3898, |
| 3914 | VSUBWuv2i64 = 3899, |
| 3915 | VSUBWuv4i32 = 3900, |
| 3916 | VSUBWuv8i16 = 3901, |
| 3917 | VSUBfd = 3902, |
| 3918 | VSUBfq = 3903, |
| 3919 | VSUBhd = 3904, |
| 3920 | VSUBhq = 3905, |
| 3921 | VSUBv16i8 = 3906, |
| 3922 | VSUBv1i64 = 3907, |
| 3923 | VSUBv2i32 = 3908, |
| 3924 | VSUBv2i64 = 3909, |
| 3925 | VSUBv4i16 = 3910, |
| 3926 | VSUBv4i32 = 3911, |
| 3927 | VSUBv8i16 = 3912, |
| 3928 | VSUBv8i8 = 3913, |
| 3929 | VSUDOTDI = 3914, |
| 3930 | VSUDOTQI = 3915, |
| 3931 | VSWPd = 3916, |
| 3932 | VSWPq = 3917, |
| 3933 | VTBL1 = 3918, |
| 3934 | VTBL2 = 3919, |
| 3935 | VTBL3 = 3920, |
| 3936 | VTBL3Pseudo = 3921, |
| 3937 | VTBL4 = 3922, |
| 3938 | VTBL4Pseudo = 3923, |
| 3939 | VTBX1 = 3924, |
| 3940 | VTBX2 = 3925, |
| 3941 | VTBX3 = 3926, |
| 3942 | VTBX3Pseudo = 3927, |
| 3943 | VTBX4 = 3928, |
| 3944 | VTBX4Pseudo = 3929, |
| 3945 | VTOSHD = 3930, |
| 3946 | VTOSHH = 3931, |
| 3947 | VTOSHS = 3932, |
| 3948 | VTOSIRD = 3933, |
| 3949 | VTOSIRH = 3934, |
| 3950 | VTOSIRS = 3935, |
| 3951 | VTOSIZD = 3936, |
| 3952 | VTOSIZH = 3937, |
| 3953 | VTOSIZS = 3938, |
| 3954 | VTOSLD = 3939, |
| 3955 | VTOSLH = 3940, |
| 3956 | VTOSLS = 3941, |
| 3957 | VTOUHD = 3942, |
| 3958 | VTOUHH = 3943, |
| 3959 | VTOUHS = 3944, |
| 3960 | VTOUIRD = 3945, |
| 3961 | VTOUIRH = 3946, |
| 3962 | VTOUIRS = 3947, |
| 3963 | VTOUIZD = 3948, |
| 3964 | VTOUIZH = 3949, |
| 3965 | VTOUIZS = 3950, |
| 3966 | VTOULD = 3951, |
| 3967 | VTOULH = 3952, |
| 3968 | VTOULS = 3953, |
| 3969 | VTRNd16 = 3954, |
| 3970 | VTRNd32 = 3955, |
| 3971 | VTRNd8 = 3956, |
| 3972 | VTRNq16 = 3957, |
| 3973 | VTRNq32 = 3958, |
| 3974 | VTRNq8 = 3959, |
| 3975 | VTSTv16i8 = 3960, |
| 3976 | VTSTv2i32 = 3961, |
| 3977 | VTSTv4i16 = 3962, |
| 3978 | VTSTv4i32 = 3963, |
| 3979 | VTSTv8i16 = 3964, |
| 3980 | VTSTv8i8 = 3965, |
| 3981 | VUDOTD = 3966, |
| 3982 | VUDOTDI = 3967, |
| 3983 | VUDOTQ = 3968, |
| 3984 | VUDOTQI = 3969, |
| 3985 | VUHTOD = 3970, |
| 3986 | VUHTOH = 3971, |
| 3987 | VUHTOS = 3972, |
| 3988 | VUITOD = 3973, |
| 3989 | VUITOH = 3974, |
| 3990 | VUITOS = 3975, |
| 3991 | VULTOD = 3976, |
| 3992 | VULTOH = 3977, |
| 3993 | VULTOS = 3978, |
| 3994 | VUMMLA = 3979, |
| 3995 | VUSDOTD = 3980, |
| 3996 | VUSDOTDI = 3981, |
| 3997 | VUSDOTQ = 3982, |
| 3998 | VUSDOTQI = 3983, |
| 3999 | VUSMMLA = 3984, |
| 4000 | VUZPd16 = 3985, |
| 4001 | VUZPd8 = 3986, |
| 4002 | VUZPq16 = 3987, |
| 4003 | VUZPq32 = 3988, |
| 4004 | VUZPq8 = 3989, |
| 4005 | VZIPd16 = 3990, |
| 4006 | VZIPd8 = 3991, |
| 4007 | VZIPq16 = 3992, |
| 4008 | VZIPq32 = 3993, |
| 4009 | VZIPq8 = 3994, |
| 4010 | sysLDMDA = 3995, |
| 4011 | sysLDMDA_UPD = 3996, |
| 4012 | sysLDMDB = 3997, |
| 4013 | sysLDMDB_UPD = 3998, |
| 4014 | sysLDMIA = 3999, |
| 4015 | sysLDMIA_UPD = 4000, |
| 4016 | sysLDMIB = 4001, |
| 4017 | sysLDMIB_UPD = 4002, |
| 4018 | sysSTMDA = 4003, |
| 4019 | sysSTMDA_UPD = 4004, |
| 4020 | sysSTMDB = 4005, |
| 4021 | sysSTMDB_UPD = 4006, |
| 4022 | sysSTMIA = 4007, |
| 4023 | sysSTMIA_UPD = 4008, |
| 4024 | sysSTMIB = 4009, |
| 4025 | sysSTMIB_UPD = 4010, |
| 4026 | t2ADCri = 4011, |
| 4027 | t2ADCrr = 4012, |
| 4028 | t2ADCrs = 4013, |
| 4029 | t2ADDri = 4014, |
| 4030 | t2ADDri12 = 4015, |
| 4031 | t2ADDrr = 4016, |
| 4032 | t2ADDrs = 4017, |
| 4033 | t2ADDspImm = 4018, |
| 4034 | t2ADDspImm12 = 4019, |
| 4035 | t2ADR = 4020, |
| 4036 | t2ANDri = 4021, |
| 4037 | t2ANDrr = 4022, |
| 4038 | t2ANDrs = 4023, |
| 4039 | t2ASRri = 4024, |
| 4040 | t2ASRrr = 4025, |
| 4041 | t2AUT = 4026, |
| 4042 | t2AUTG = 4027, |
| 4043 | t2B = 4028, |
| 4044 | t2BFC = 4029, |
| 4045 | t2BFI = 4030, |
| 4046 | t2BFLi = 4031, |
| 4047 | t2BFLr = 4032, |
| 4048 | t2BFi = 4033, |
| 4049 | t2BFic = 4034, |
| 4050 | t2BFr = 4035, |
| 4051 | t2BICri = 4036, |
| 4052 | t2BICrr = 4037, |
| 4053 | t2BICrs = 4038, |
| 4054 | t2BTI = 4039, |
| 4055 | t2BXAUT = 4040, |
| 4056 | t2BXJ = 4041, |
| 4057 | t2Bcc = 4042, |
| 4058 | t2CDP = 4043, |
| 4059 | t2CDP2 = 4044, |
| 4060 | t2CLREX = 4045, |
| 4061 | t2CLRM = 4046, |
| 4062 | t2CLZ = 4047, |
| 4063 | t2CMNri = 4048, |
| 4064 | t2CMNzrr = 4049, |
| 4065 | t2CMNzrs = 4050, |
| 4066 | t2CMPri = 4051, |
| 4067 | t2CMPrr = 4052, |
| 4068 | t2CMPrs = 4053, |
| 4069 | t2CPS1p = 4054, |
| 4070 | t2CPS2p = 4055, |
| 4071 | t2CPS3p = 4056, |
| 4072 | t2CRC32B = 4057, |
| 4073 | t2CRC32CB = 4058, |
| 4074 | t2CRC32CH = 4059, |
| 4075 | t2CRC32CW = 4060, |
| 4076 | t2CRC32H = 4061, |
| 4077 | t2CRC32W = 4062, |
| 4078 | t2CSEL = 4063, |
| 4079 | t2CSINC = 4064, |
| 4080 | t2CSINV = 4065, |
| 4081 | t2CSNEG = 4066, |
| 4082 | t2DBG = 4067, |
| 4083 | t2DCPS1 = 4068, |
| 4084 | t2DCPS2 = 4069, |
| 4085 | t2DCPS3 = 4070, |
| 4086 | t2DLS = 4071, |
| 4087 | t2DMB = 4072, |
| 4088 | t2DSB = 4073, |
| 4089 | t2EORri = 4074, |
| 4090 | t2EORrr = 4075, |
| 4091 | t2EORrs = 4076, |
| 4092 | t2HINT = 4077, |
| 4093 | t2HVC = 4078, |
| 4094 | t2ISB = 4079, |
| 4095 | t2IT = 4080, |
| 4096 | t2Int_eh_sjlj_setjmp = 4081, |
| 4097 | t2Int_eh_sjlj_setjmp_nofp = 4082, |
| 4098 | t2LDA = 4083, |
| 4099 | t2LDAB = 4084, |
| 4100 | t2LDAEX = 4085, |
| 4101 | t2LDAEXB = 4086, |
| 4102 | t2LDAEXD = 4087, |
| 4103 | t2LDAEXH = 4088, |
| 4104 | t2LDAH = 4089, |
| 4105 | t2LDC2L_OFFSET = 4090, |
| 4106 | t2LDC2L_OPTION = 4091, |
| 4107 | t2LDC2L_POST = 4092, |
| 4108 | t2LDC2L_PRE = 4093, |
| 4109 | t2LDC2_OFFSET = 4094, |
| 4110 | t2LDC2_OPTION = 4095, |
| 4111 | t2LDC2_POST = 4096, |
| 4112 | t2LDC2_PRE = 4097, |
| 4113 | t2LDCL_OFFSET = 4098, |
| 4114 | t2LDCL_OPTION = 4099, |
| 4115 | t2LDCL_POST = 4100, |
| 4116 | t2LDCL_PRE = 4101, |
| 4117 | t2LDC_OFFSET = 4102, |
| 4118 | t2LDC_OPTION = 4103, |
| 4119 | t2LDC_POST = 4104, |
| 4120 | t2LDC_PRE = 4105, |
| 4121 | t2LDMDB = 4106, |
| 4122 | t2LDMDB_UPD = 4107, |
| 4123 | t2LDMIA = 4108, |
| 4124 | t2LDMIA_UPD = 4109, |
| 4125 | t2LDRBT = 4110, |
| 4126 | t2LDRB_POST = 4111, |
| 4127 | t2LDRB_PRE = 4112, |
| 4128 | t2LDRBi12 = 4113, |
| 4129 | t2LDRBi8 = 4114, |
| 4130 | t2LDRBpci = 4115, |
| 4131 | t2LDRBs = 4116, |
| 4132 | t2LDRD_POST = 4117, |
| 4133 | t2LDRD_PRE = 4118, |
| 4134 | t2LDRDi8 = 4119, |
| 4135 | t2LDREX = 4120, |
| 4136 | t2LDREXB = 4121, |
| 4137 | t2LDREXD = 4122, |
| 4138 | t2LDREXH = 4123, |
| 4139 | t2LDRHT = 4124, |
| 4140 | t2LDRH_POST = 4125, |
| 4141 | t2LDRH_PRE = 4126, |
| 4142 | t2LDRHi12 = 4127, |
| 4143 | t2LDRHi8 = 4128, |
| 4144 | t2LDRHpci = 4129, |
| 4145 | t2LDRHs = 4130, |
| 4146 | t2LDRSBT = 4131, |
| 4147 | t2LDRSB_POST = 4132, |
| 4148 | t2LDRSB_PRE = 4133, |
| 4149 | t2LDRSBi12 = 4134, |
| 4150 | t2LDRSBi8 = 4135, |
| 4151 | t2LDRSBpci = 4136, |
| 4152 | t2LDRSBs = 4137, |
| 4153 | t2LDRSHT = 4138, |
| 4154 | t2LDRSH_POST = 4139, |
| 4155 | t2LDRSH_PRE = 4140, |
| 4156 | t2LDRSHi12 = 4141, |
| 4157 | t2LDRSHi8 = 4142, |
| 4158 | t2LDRSHpci = 4143, |
| 4159 | t2LDRSHs = 4144, |
| 4160 | t2LDRT = 4145, |
| 4161 | t2LDR_POST = 4146, |
| 4162 | t2LDR_PRE = 4147, |
| 4163 | t2LDRi12 = 4148, |
| 4164 | t2LDRi8 = 4149, |
| 4165 | t2LDRpci = 4150, |
| 4166 | t2LDRs = 4151, |
| 4167 | t2LE = 4152, |
| 4168 | t2LEUpdate = 4153, |
| 4169 | t2LSLri = 4154, |
| 4170 | t2LSLrr = 4155, |
| 4171 | t2LSRri = 4156, |
| 4172 | t2LSRrr = 4157, |
| 4173 | t2MCR = 4158, |
| 4174 | t2MCR2 = 4159, |
| 4175 | t2MCRR = 4160, |
| 4176 | t2MCRR2 = 4161, |
| 4177 | t2MLA = 4162, |
| 4178 | t2MLS = 4163, |
| 4179 | t2MOVTi16 = 4164, |
| 4180 | t2MOVi = 4165, |
| 4181 | t2MOVi16 = 4166, |
| 4182 | t2MOVr = 4167, |
| 4183 | t2MOVsra_glue = 4168, |
| 4184 | t2MOVsrl_glue = 4169, |
| 4185 | t2MRC = 4170, |
| 4186 | t2MRC2 = 4171, |
| 4187 | t2MRRC = 4172, |
| 4188 | t2MRRC2 = 4173, |
| 4189 | t2MRS_AR = 4174, |
| 4190 | t2MRS_M = 4175, |
| 4191 | t2MRSbanked = 4176, |
| 4192 | t2MRSsys_AR = 4177, |
| 4193 | t2MSR_AR = 4178, |
| 4194 | t2MSR_M = 4179, |
| 4195 | t2MSRbanked = 4180, |
| 4196 | t2MUL = 4181, |
| 4197 | t2MVNi = 4182, |
| 4198 | t2MVNr = 4183, |
| 4199 | t2MVNs = 4184, |
| 4200 | t2ORNri = 4185, |
| 4201 | t2ORNrr = 4186, |
| 4202 | t2ORNrs = 4187, |
| 4203 | t2ORRri = 4188, |
| 4204 | t2ORRrr = 4189, |
| 4205 | t2ORRrs = 4190, |
| 4206 | t2PAC = 4191, |
| 4207 | t2PACBTI = 4192, |
| 4208 | t2PACG = 4193, |
| 4209 | t2PKHBT = 4194, |
| 4210 | t2PKHTB = 4195, |
| 4211 | t2PLDWi12 = 4196, |
| 4212 | t2PLDWi8 = 4197, |
| 4213 | t2PLDWs = 4198, |
| 4214 | t2PLDi12 = 4199, |
| 4215 | t2PLDi8 = 4200, |
| 4216 | t2PLDpci = 4201, |
| 4217 | t2PLDs = 4202, |
| 4218 | t2PLIi12 = 4203, |
| 4219 | t2PLIi8 = 4204, |
| 4220 | t2PLIpci = 4205, |
| 4221 | t2PLIs = 4206, |
| 4222 | t2QADD = 4207, |
| 4223 | t2QADD16 = 4208, |
| 4224 | t2QADD8 = 4209, |
| 4225 | t2QASX = 4210, |
| 4226 | t2QDADD = 4211, |
| 4227 | t2QDSUB = 4212, |
| 4228 | t2QSAX = 4213, |
| 4229 | t2QSUB = 4214, |
| 4230 | t2QSUB16 = 4215, |
| 4231 | t2QSUB8 = 4216, |
| 4232 | t2RBIT = 4217, |
| 4233 | t2REV = 4218, |
| 4234 | t2REV16 = 4219, |
| 4235 | t2REVSH = 4220, |
| 4236 | t2RFEDB = 4221, |
| 4237 | t2RFEDBW = 4222, |
| 4238 | t2RFEIA = 4223, |
| 4239 | t2RFEIAW = 4224, |
| 4240 | t2RORri = 4225, |
| 4241 | t2RORrr = 4226, |
| 4242 | t2RRX = 4227, |
| 4243 | t2RSBri = 4228, |
| 4244 | t2RSBrr = 4229, |
| 4245 | t2RSBrs = 4230, |
| 4246 | t2SADD16 = 4231, |
| 4247 | t2SADD8 = 4232, |
| 4248 | t2SASX = 4233, |
| 4249 | t2SB = 4234, |
| 4250 | t2SBCri = 4235, |
| 4251 | t2SBCrr = 4236, |
| 4252 | t2SBCrs = 4237, |
| 4253 | t2SBFX = 4238, |
| 4254 | t2SDIV = 4239, |
| 4255 | t2SEL = 4240, |
| 4256 | t2SETPAN = 4241, |
| 4257 | t2SG = 4242, |
| 4258 | t2SHADD16 = 4243, |
| 4259 | t2SHADD8 = 4244, |
| 4260 | t2SHASX = 4245, |
| 4261 | t2SHSAX = 4246, |
| 4262 | t2SHSUB16 = 4247, |
| 4263 | t2SHSUB8 = 4248, |
| 4264 | t2SMC = 4249, |
| 4265 | t2SMLABB = 4250, |
| 4266 | t2SMLABT = 4251, |
| 4267 | t2SMLAD = 4252, |
| 4268 | t2SMLADX = 4253, |
| 4269 | t2SMLAL = 4254, |
| 4270 | t2SMLALBB = 4255, |
| 4271 | t2SMLALBT = 4256, |
| 4272 | t2SMLALD = 4257, |
| 4273 | t2SMLALDX = 4258, |
| 4274 | t2SMLALTB = 4259, |
| 4275 | t2SMLALTT = 4260, |
| 4276 | t2SMLATB = 4261, |
| 4277 | t2SMLATT = 4262, |
| 4278 | t2SMLAWB = 4263, |
| 4279 | t2SMLAWT = 4264, |
| 4280 | t2SMLSD = 4265, |
| 4281 | t2SMLSDX = 4266, |
| 4282 | t2SMLSLD = 4267, |
| 4283 | t2SMLSLDX = 4268, |
| 4284 | t2SMMLA = 4269, |
| 4285 | t2SMMLAR = 4270, |
| 4286 | t2SMMLS = 4271, |
| 4287 | t2SMMLSR = 4272, |
| 4288 | t2SMMUL = 4273, |
| 4289 | t2SMMULR = 4274, |
| 4290 | t2SMUAD = 4275, |
| 4291 | t2SMUADX = 4276, |
| 4292 | t2SMULBB = 4277, |
| 4293 | t2SMULBT = 4278, |
| 4294 | t2SMULL = 4279, |
| 4295 | t2SMULTB = 4280, |
| 4296 | t2SMULTT = 4281, |
| 4297 | t2SMULWB = 4282, |
| 4298 | t2SMULWT = 4283, |
| 4299 | t2SMUSD = 4284, |
| 4300 | t2SMUSDX = 4285, |
| 4301 | t2SRSDB = 4286, |
| 4302 | t2SRSDB_UPD = 4287, |
| 4303 | t2SRSIA = 4288, |
| 4304 | t2SRSIA_UPD = 4289, |
| 4305 | t2SSAT = 4290, |
| 4306 | t2SSAT16 = 4291, |
| 4307 | t2SSAX = 4292, |
| 4308 | t2SSUB16 = 4293, |
| 4309 | t2SSUB8 = 4294, |
| 4310 | t2STC2L_OFFSET = 4295, |
| 4311 | t2STC2L_OPTION = 4296, |
| 4312 | t2STC2L_POST = 4297, |
| 4313 | t2STC2L_PRE = 4298, |
| 4314 | t2STC2_OFFSET = 4299, |
| 4315 | t2STC2_OPTION = 4300, |
| 4316 | t2STC2_POST = 4301, |
| 4317 | t2STC2_PRE = 4302, |
| 4318 | t2STCL_OFFSET = 4303, |
| 4319 | t2STCL_OPTION = 4304, |
| 4320 | t2STCL_POST = 4305, |
| 4321 | t2STCL_PRE = 4306, |
| 4322 | t2STC_OFFSET = 4307, |
| 4323 | t2STC_OPTION = 4308, |
| 4324 | t2STC_POST = 4309, |
| 4325 | t2STC_PRE = 4310, |
| 4326 | t2STL = 4311, |
| 4327 | t2STLB = 4312, |
| 4328 | t2STLEX = 4313, |
| 4329 | t2STLEXB = 4314, |
| 4330 | t2STLEXD = 4315, |
| 4331 | t2STLEXH = 4316, |
| 4332 | t2STLH = 4317, |
| 4333 | t2STMDB = 4318, |
| 4334 | t2STMDB_UPD = 4319, |
| 4335 | t2STMIA = 4320, |
| 4336 | t2STMIA_UPD = 4321, |
| 4337 | t2STRBT = 4322, |
| 4338 | t2STRB_POST = 4323, |
| 4339 | t2STRB_PRE = 4324, |
| 4340 | t2STRBi12 = 4325, |
| 4341 | t2STRBi8 = 4326, |
| 4342 | t2STRBs = 4327, |
| 4343 | t2STRD_POST = 4328, |
| 4344 | t2STRD_PRE = 4329, |
| 4345 | t2STRDi8 = 4330, |
| 4346 | t2STREX = 4331, |
| 4347 | t2STREXB = 4332, |
| 4348 | t2STREXD = 4333, |
| 4349 | t2STREXH = 4334, |
| 4350 | t2STRHT = 4335, |
| 4351 | t2STRH_POST = 4336, |
| 4352 | t2STRH_PRE = 4337, |
| 4353 | t2STRHi12 = 4338, |
| 4354 | t2STRHi8 = 4339, |
| 4355 | t2STRHs = 4340, |
| 4356 | t2STRT = 4341, |
| 4357 | t2STR_POST = 4342, |
| 4358 | t2STR_PRE = 4343, |
| 4359 | t2STRi12 = 4344, |
| 4360 | t2STRi8 = 4345, |
| 4361 | t2STRs = 4346, |
| 4362 | t2SUBS_PC_LR = 4347, |
| 4363 | t2SUBri = 4348, |
| 4364 | t2SUBri12 = 4349, |
| 4365 | t2SUBrr = 4350, |
| 4366 | t2SUBrs = 4351, |
| 4367 | t2SUBspImm = 4352, |
| 4368 | t2SUBspImm12 = 4353, |
| 4369 | t2SXTAB = 4354, |
| 4370 | t2SXTAB16 = 4355, |
| 4371 | t2SXTAH = 4356, |
| 4372 | t2SXTB = 4357, |
| 4373 | t2SXTB16 = 4358, |
| 4374 | t2SXTH = 4359, |
| 4375 | t2TBB = 4360, |
| 4376 | t2TBH = 4361, |
| 4377 | t2TEQri = 4362, |
| 4378 | t2TEQrr = 4363, |
| 4379 | t2TEQrs = 4364, |
| 4380 | t2TSB = 4365, |
| 4381 | t2TSTri = 4366, |
| 4382 | t2TSTrr = 4367, |
| 4383 | t2TSTrs = 4368, |
| 4384 | t2TT = 4369, |
| 4385 | t2TTA = 4370, |
| 4386 | t2TTAT = 4371, |
| 4387 | t2TTT = 4372, |
| 4388 | t2UADD16 = 4373, |
| 4389 | t2UADD8 = 4374, |
| 4390 | t2UASX = 4375, |
| 4391 | t2UBFX = 4376, |
| 4392 | t2UDF = 4377, |
| 4393 | t2UDIV = 4378, |
| 4394 | t2UHADD16 = 4379, |
| 4395 | t2UHADD8 = 4380, |
| 4396 | t2UHASX = 4381, |
| 4397 | t2UHSAX = 4382, |
| 4398 | t2UHSUB16 = 4383, |
| 4399 | t2UHSUB8 = 4384, |
| 4400 | t2UMAAL = 4385, |
| 4401 | t2UMLAL = 4386, |
| 4402 | t2UMULL = 4387, |
| 4403 | t2UQADD16 = 4388, |
| 4404 | t2UQADD8 = 4389, |
| 4405 | t2UQASX = 4390, |
| 4406 | t2UQSAX = 4391, |
| 4407 | t2UQSUB16 = 4392, |
| 4408 | t2UQSUB8 = 4393, |
| 4409 | t2USAD8 = 4394, |
| 4410 | t2USADA8 = 4395, |
| 4411 | t2USAT = 4396, |
| 4412 | t2USAT16 = 4397, |
| 4413 | t2USAX = 4398, |
| 4414 | t2USUB16 = 4399, |
| 4415 | t2USUB8 = 4400, |
| 4416 | t2UXTAB = 4401, |
| 4417 | t2UXTAB16 = 4402, |
| 4418 | t2UXTAH = 4403, |
| 4419 | t2UXTB = 4404, |
| 4420 | t2UXTB16 = 4405, |
| 4421 | t2UXTH = 4406, |
| 4422 | t2WLS = 4407, |
| 4423 | tADC = 4408, |
| 4424 | tADDhirr = 4409, |
| 4425 | tADDi3 = 4410, |
| 4426 | tADDi8 = 4411, |
| 4427 | tADDrSP = 4412, |
| 4428 | tADDrSPi = 4413, |
| 4429 | tADDrr = 4414, |
| 4430 | tADDspi = 4415, |
| 4431 | tADDspr = 4416, |
| 4432 | tADR = 4417, |
| 4433 | tAND = 4418, |
| 4434 | tASRri = 4419, |
| 4435 | tASRrr = 4420, |
| 4436 | tB = 4421, |
| 4437 | tBIC = 4422, |
| 4438 | tBKPT = 4423, |
| 4439 | tBL = 4424, |
| 4440 | tBLXNSr = 4425, |
| 4441 | tBLXi = 4426, |
| 4442 | tBLXr = 4427, |
| 4443 | tBX = 4428, |
| 4444 | tBXNS = 4429, |
| 4445 | tBcc = 4430, |
| 4446 | tCBNZ = 4431, |
| 4447 | tCBZ = 4432, |
| 4448 | tCMNz = 4433, |
| 4449 | tCMPhir = 4434, |
| 4450 | tCMPi8 = 4435, |
| 4451 | tCMPr = 4436, |
| 4452 | tCPS = 4437, |
| 4453 | tEOR = 4438, |
| 4454 | tHINT = 4439, |
| 4455 | tHLT = 4440, |
| 4456 | tInt_WIN_eh_sjlj_longjmp = 4441, |
| 4457 | tInt_eh_sjlj_longjmp = 4442, |
| 4458 | tInt_eh_sjlj_setjmp = 4443, |
| 4459 | tLDMIA = 4444, |
| 4460 | tLDRBi = 4445, |
| 4461 | tLDRBr = 4446, |
| 4462 | tLDRHi = 4447, |
| 4463 | tLDRHr = 4448, |
| 4464 | tLDRSB = 4449, |
| 4465 | tLDRSH = 4450, |
| 4466 | tLDRi = 4451, |
| 4467 | tLDRpci = 4452, |
| 4468 | tLDRr = 4453, |
| 4469 | tLDRspi = 4454, |
| 4470 | tLSLri = 4455, |
| 4471 | tLSLrr = 4456, |
| 4472 | tLSRri = 4457, |
| 4473 | tLSRrr = 4458, |
| 4474 | tMOVSr = 4459, |
| 4475 | tMOVi8 = 4460, |
| 4476 | tMOVr = 4461, |
| 4477 | tMUL = 4462, |
| 4478 | tMVN = 4463, |
| 4479 | tORR = 4464, |
| 4480 | tPICADD = 4465, |
| 4481 | tPOP = 4466, |
| 4482 | tPUSH = 4467, |
| 4483 | tREV = 4468, |
| 4484 | tREV16 = 4469, |
| 4485 | tREVSH = 4470, |
| 4486 | tROR = 4471, |
| 4487 | tRSB = 4472, |
| 4488 | tSBC = 4473, |
| 4489 | tSETEND = 4474, |
| 4490 | tSTMIA_UPD = 4475, |
| 4491 | tSTRBi = 4476, |
| 4492 | tSTRBr = 4477, |
| 4493 | tSTRHi = 4478, |
| 4494 | tSTRHr = 4479, |
| 4495 | tSTRi = 4480, |
| 4496 | tSTRr = 4481, |
| 4497 | tSTRspi = 4482, |
| 4498 | tSUBi3 = 4483, |
| 4499 | tSUBi8 = 4484, |
| 4500 | tSUBrr = 4485, |
| 4501 | tSUBspi = 4486, |
| 4502 | tSVC = 4487, |
| 4503 | tSXTB = 4488, |
| 4504 | tSXTH = 4489, |
| 4505 | tTRAP = 4490, |
| 4506 | tTST = 4491, |
| 4507 | tUDF = 4492, |
| 4508 | tUXTB = 4493, |
| 4509 | tUXTH = 4494, |
| 4510 | t__brkdiv0 = 4495, |
| 4511 | INSTRUCTION_LIST_END = 4496 |
| 4512 | }; |
| 4513 | |
| 4514 | } // end namespace ARM |
| 4515 | } // end namespace llvm |
| 4516 | #endif // GET_INSTRINFO_ENUM |
| 4517 | |
| 4518 | #ifdef GET_INSTRINFO_SCHED_ENUM |
| 4519 | #undef GET_INSTRINFO_SCHED_ENUM |
| 4520 | namespace llvm { |
| 4521 | |
| 4522 | namespace ARM { |
| 4523 | namespace Sched { |
| 4524 | enum { |
| 4525 | NoInstrModel = 0, |
| 4526 | IIC_iALUi_WriteALU_ReadALU = 1, |
| 4527 | IIC_iALUr_WriteALU_ReadALU_ReadALU = 2, |
| 4528 | IIC_iALUsr_WriteALUsi_ReadALU = 3, |
| 4529 | IIC_iALUsr_WriteALUSsr_ReadALUsr = 4, |
| 4530 | IIC_Br_WriteBr = 5, |
| 4531 | IIC_Br_WriteBrL = 6, |
| 4532 | IIC_Br_WriteBrTbl = 7, |
| 4533 | IIC_iLoad_mBr = 8, |
| 4534 | IIC_iLoad_i = 9, |
| 4535 | IIC_iLoadiALU = 10, |
| 4536 | IIC_iLoad_d_r = 11, |
| 4537 | IIC_iMAC32_WriteMAC32_ReadMUL_ReadMUL_ReadMAC = 12, |
| 4538 | IIC_iCMOVi_WriteALU = 13, |
| 4539 | IIC_iMOVi_WriteALU = 14, |
| 4540 | IIC_iCMOVix2 = 15, |
| 4541 | IIC_iCMOVr_WriteALU = 16, |
| 4542 | IIC_iCMOVsr_WriteALU = 17, |
| 4543 | IIC_iMOVix2addpc = 18, |
| 4544 | IIC_iMOVix2ld = 19, |
| 4545 | IIC_iMOVix2 = 20, |
| 4546 | IIC_iMOVsi_WriteALU = 21, |
| 4547 | IIC_iMUL32_WriteMUL32_ReadMUL_ReadMUL = 22, |
| 4548 | IIC_iALUr_WriteALU_ReadALU = 23, |
| 4549 | IIC_iLoad_r = 24, |
| 4550 | IIC_iLoad_bh_r = 25, |
| 4551 | IIC_iStore_r = 26, |
| 4552 | IIC_iStore_bh_r = 27, |
| 4553 | IIC_iMAC64_WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL_ReadMAC_ReadMAC = 28, |
| 4554 | IIC_iMUL64_WriteMUL64Lo_WriteMUL64Hi_ReadMUL_ReadMUL = 29, |
| 4555 | IIC_iStore_d_r = 30, |
| 4556 | IIC_iStore_ru = 31, |
| 4557 | IIC_Br = 32, |
| 4558 | IIC_VMOVImm = 33, |
| 4559 | IIC_fpUNA64 = 34, |
| 4560 | IIC_fpUNA16 = 35, |
| 4561 | IIC_fpUNA32 = 36, |
| 4562 | IIC_iALUsi_WriteALUsi_ReadALUsr = 37, |
| 4563 | IIC_iCMOVsi_WriteALU = 38, |
| 4564 | IIC_iALUsi_WriteALUsi_ReadALU = 39, |
| 4565 | IIC_iStore_ru_WriteST = 40, |
| 4566 | IIC_iALUr_WriteALU = 41, |
| 4567 | IIC_iALUi_WriteALU = 42, |
| 4568 | IIC_iLoad_mu = 43, |
| 4569 | IIC_iPop_Br_WriteBrL = 44, |
| 4570 | IIC_iALUsr_WriteALUsr_ReadALUsr = 45, |
| 4571 | IIC_iBITi_WriteALU_ReadALU = 46, |
| 4572 | IIC_iBITr_WriteALU_ReadALU_ReadALU = 47, |
| 4573 | IIC_iBITsr_WriteALUsi_ReadALU = 48, |
| 4574 | IIC_iBITsr_WriteALUsr_ReadALUsr = 49, |
| 4575 | IIC_VDOTPROD = 50, |
| 4576 | IIC_iUNAsi = 51, |
| 4577 | WriteBrL = 52, |
| 4578 | WriteBr = 53, |
| 4579 | IIC_iUNAr_WriteALU = 54, |
| 4580 | IIC_iCMPi_WriteCMP_ReadALU = 55, |
| 4581 | IIC_iCMPr_WriteCMP_ReadALU_ReadALU = 56, |
| 4582 | IIC_iCMPsr_WriteCMPsi_ReadALU = 57, |
| 4583 | IIC_iCMPsr_WriteCMPsr_ReadALU = 58, |
| 4584 | IIC_fpSTAT = 59, |
| 4585 | IIC_iLoad_m = 60, |
| 4586 | IIC_iLoad_bh_ru = 61, |
| 4587 | IIC_iLoad_bh_iu = 62, |
| 4588 | IIC_iLoad_bh_si = 63, |
| 4589 | IIC_iLoad_d_ru = 64, |
| 4590 | IIC_iLoad_ru = 65, |
| 4591 | IIC_iLoad_iu = 66, |
| 4592 | IIC_iLoad_si = 67, |
| 4593 | IIC_iMOVr_WriteALU = 68, |
| 4594 | IIC_iMOVsr_WriteALU = 69, |
| 4595 | IIC_iMVNi_WriteALU = 70, |
| 4596 | IIC_iMVNr_WriteALU = 71, |
| 4597 | IIC_iMVNsr_WriteALU = 72, |
| 4598 | IIC_iBITsi_WriteALUsi_ReadALU = 73, |
| 4599 | IIC_Preload_WritePreLd = 74, |
| 4600 | IIC_iDIV_WriteDIV = 75, |
| 4601 | IIC_iMAC16_WriteMAC16_ReadMUL_ReadMUL_ReadMAC = 76, |
| 4602 | WriteMAC32_ReadMUL_ReadMUL_ReadMAC = 77, |
| 4603 | WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL_ReadMAC_ReadMAC = 78, |
| 4604 | WriteMUL64Lo_WriteMUL64Hi_ReadMUL_ReadMUL = 79, |
| 4605 | WriteMUL32_ReadMUL_ReadMUL = 80, |
| 4606 | IIC_iMUL16_WriteMUL16_ReadMUL_ReadMUL = 81, |
| 4607 | IIC_iStore_m = 82, |
| 4608 | IIC_iStore_mu = 83, |
| 4609 | IIC_iStore_bh_ru = 84, |
| 4610 | IIC_iStore_bh_iu = 85, |
| 4611 | IIC_iStore_bh_si = 86, |
| 4612 | IIC_iStore_d_ru = 87, |
| 4613 | IIC_iStore_iu = 88, |
| 4614 | IIC_iStore_si = 89, |
| 4615 | IIC_iEXTAr_WriteALUsr = 90, |
| 4616 | IIC_iEXTr_WriteALUsi = 91, |
| 4617 | IIC_iTSTi_WriteCMP_ReadALU = 92, |
| 4618 | IIC_iTSTr_WriteCMP_ReadALU_ReadALU = 93, |
| 4619 | IIC_iTSTsr_WriteCMPsi_ReadALU = 94, |
| 4620 | IIC_iTSTsr_WriteCMPsr_ReadALU = 95, |
| 4621 | IIC_iMUL64_WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL = 96, |
| 4622 | WriteALU_ReadALU_ReadALU = 97, |
| 4623 | IIC_VABAD = 98, |
| 4624 | IIC_VABAQ = 99, |
| 4625 | IIC_VSUBi4Q = 100, |
| 4626 | IIC_VBIND = 101, |
| 4627 | IIC_VBINQ = 102, |
| 4628 | IIC_VSUBi4D = 103, |
| 4629 | IIC_VUNAD = 104, |
| 4630 | IIC_VUNAQ = 105, |
| 4631 | IIC_VUNAiQ = 106, |
| 4632 | IIC_VUNAiD = 107, |
| 4633 | IIC_fpALU64_WriteFPALU64 = 108, |
| 4634 | IIC_fpALU16_WriteFPALU32 = 109, |
| 4635 | IIC_VBINi4D = 110, |
| 4636 | IIC_VSHLiD = 111, |
| 4637 | IIC_fpALU32_WriteFPALU32 = 112, |
| 4638 | IIC_VSUBiD = 113, |
| 4639 | IIC_VBINiQ = 114, |
| 4640 | IIC_VBINiD = 115, |
| 4641 | IIC_VMACD = 116, |
| 4642 | IIC_VMACQ = 117, |
| 4643 | IIC_VCNTiQ = 118, |
| 4644 | IIC_VCNTiD = 119, |
| 4645 | IIC_fpCMP64 = 120, |
| 4646 | IIC_fpCMP16 = 121, |
| 4647 | IIC_fpCMP32 = 122, |
| 4648 | WriteFPCVT = 123, |
| 4649 | IIC_fpCVTSH_WriteFPCVT = 124, |
| 4650 | IIC_fpCVTHS_WriteFPCVT = 125, |
| 4651 | IIC_fpCVTDS_WriteFPCVT = 126, |
| 4652 | IIC_fpCVTSD_WriteFPCVT = 127, |
| 4653 | IIC_fpDIV64_WriteFPDIV64 = 128, |
| 4654 | IIC_fpDIV16_WriteFPDIV32 = 129, |
| 4655 | IIC_fpDIV32_WriteFPDIV32 = 130, |
| 4656 | IIC_VMOVIS = 131, |
| 4657 | IIC_VMOVD = 132, |
| 4658 | IIC_VMOVQ = 133, |
| 4659 | IIC_VEXTD = 134, |
| 4660 | IIC_VEXTQ = 135, |
| 4661 | IIC_fpFMAC64_WriteFPMAC64_ReadFPMAC_ReadFPMUL_ReadFPMUL = 136, |
| 4662 | IIC_fpFMAC16_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 137, |
| 4663 | IIC_fpFMAC32_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 138, |
| 4664 | IIC_VFMACD = 139, |
| 4665 | IIC_VFMACQ = 140, |
| 4666 | IIC_VMOVSI = 141, |
| 4667 | IIC_VBINi4Q = 142, |
| 4668 | IIC_fpCVTDI = 143, |
| 4669 | IIC_VLD1dup_WriteVLD2 = 144, |
| 4670 | IIC_VLD1dupu = 145, |
| 4671 | IIC_VLD1dup = 146, |
| 4672 | IIC_VLD1dupu_WriteVLD1 = 147, |
| 4673 | IIC_VLD1ln = 148, |
| 4674 | IIC_VLD1lnu_WriteVLD1 = 149, |
| 4675 | IIC_VLD1ln_WriteVLD1 = 150, |
| 4676 | IIC_VLD1_WriteVLD1 = 151, |
| 4677 | IIC_VLD1x4_WriteVLD4 = 152, |
| 4678 | IIC_VLD1x2u_WriteVLD4 = 153, |
| 4679 | IIC_VLD1x3_WriteVLD3 = 154, |
| 4680 | IIC_VLD1x2u_WriteVLD3 = 155, |
| 4681 | IIC_VLD1u_WriteVLD1 = 156, |
| 4682 | IIC_VLD1x2_WriteVLD2 = 157, |
| 4683 | IIC_VLD1x2u_WriteVLD2 = 158, |
| 4684 | IIC_VLD2dup = 159, |
| 4685 | IIC_VLD2dupu_WriteVLD1 = 160, |
| 4686 | IIC_VLD2dup_WriteVLD2 = 161, |
| 4687 | IIC_VLD2ln_WriteVLD1 = 162, |
| 4688 | IIC_VLD2lnu_WriteVLD1 = 163, |
| 4689 | IIC_VLD2lnu = 164, |
| 4690 | IIC_VLD2_WriteVLD2 = 165, |
| 4691 | IIC_VLD2u_WriteVLD2 = 166, |
| 4692 | IIC_VLD2x2_WriteVLD4 = 167, |
| 4693 | IIC_VLD2x2u_WriteVLD4 = 168, |
| 4694 | IIC_VLD3dup_WriteVLD2 = 169, |
| 4695 | IIC_VLD3dupu_WriteVLD2 = 170, |
| 4696 | IIC_VLD3ln_WriteVLD2 = 171, |
| 4697 | IIC_VLD3lnu_WriteVLD2 = 172, |
| 4698 | IIC_VLD3_WriteVLD3 = 173, |
| 4699 | IIC_VLD3u_WriteVLD3 = 174, |
| 4700 | IIC_VLD4dup = 175, |
| 4701 | IIC_VLD4dup_WriteVLD2 = 176, |
| 4702 | IIC_VLD4dupu_WriteVLD2 = 177, |
| 4703 | IIC_VLD4ln_WriteVLD2 = 178, |
| 4704 | IIC_VLD4lnu_WriteVLD2 = 179, |
| 4705 | IIC_VLD4lnu = 180, |
| 4706 | IIC_VLD4_WriteVLD4 = 181, |
| 4707 | IIC_VLD4u_WriteVLD4 = 182, |
| 4708 | IIC_fpLoad_mu = 183, |
| 4709 | IIC_fpLoad_m = 184, |
| 4710 | IIC_fpLoad64 = 185, |
| 4711 | IIC_fpLoad16 = 186, |
| 4712 | IIC_fpLoad32 = 187, |
| 4713 | IIC_fpMAC64_WriteFPMAC64_ReadFPMAC_ReadFPMUL_ReadFPMUL = 188, |
| 4714 | IIC_fpMAC16 = 189, |
| 4715 | IIC_VMACi32D = 190, |
| 4716 | IIC_VMACi16D = 191, |
| 4717 | IIC_fpMAC32_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 192, |
| 4718 | IIC_VMACi32Q = 193, |
| 4719 | IIC_VMACi16Q = 194, |
| 4720 | IIC_fpMOVID_WriteFPMOV = 195, |
| 4721 | IIC_fpMOVIS_WriteFPMOV = 196, |
| 4722 | IIC_VQUNAiD = 197, |
| 4723 | IIC_VMOVN = 198, |
| 4724 | IIC_fpMOVSI_WriteFPMOV = 199, |
| 4725 | IIC_fpMOVDI_WriteFPMOV = 200, |
| 4726 | IIC_fpMUL64_WriteFPMUL64_ReadFPMUL_ReadFPMUL = 201, |
| 4727 | IIC_fpMUL16_WriteFPMUL32_ReadFPMUL_ReadFPMUL = 202, |
| 4728 | IIC_VMULi16D = 203, |
| 4729 | IIC_VMULi32D = 204, |
| 4730 | IIC_fpMUL32_WriteFPMUL32_ReadFPMUL_ReadFPMUL = 205, |
| 4731 | IIC_VFMULD = 206, |
| 4732 | IIC_VFMULQ = 207, |
| 4733 | IIC_VMULi16Q = 208, |
| 4734 | IIC_VMULi32Q = 209, |
| 4735 | IIC_VSHLiQ = 210, |
| 4736 | IIC_VPALiQ = 211, |
| 4737 | IIC_VPALiD = 212, |
| 4738 | IIC_VPBIND = 213, |
| 4739 | IIC_VQUNAiQ = 214, |
| 4740 | IIC_VSHLi4Q = 215, |
| 4741 | IIC_VSHLi4D = 216, |
| 4742 | IIC_VRECSD = 217, |
| 4743 | IIC_VRECSQ = 218, |
| 4744 | IIC_VMOVISL = 219, |
| 4745 | IIC_fpCVTID_WriteFPCVT = 220, |
| 4746 | IIC_fpCVTIH_WriteFPCVT = 221, |
| 4747 | IIC_fpCVTIS_WriteFPCVT = 222, |
| 4748 | IIC_fpSQRT64_WriteFPSQRT64 = 223, |
| 4749 | IIC_fpSQRT16 = 224, |
| 4750 | IIC_fpSQRT32_WriteFPSQRT32 = 225, |
| 4751 | IIC_VST1ln_WriteVST1 = 226, |
| 4752 | IIC_VST1lnu_WriteVST1 = 227, |
| 4753 | IIC_VST1_WriteVST1 = 228, |
| 4754 | IIC_VST1x4_WriteVST4 = 229, |
| 4755 | IIC_VST1x4u_WriteVST4 = 230, |
| 4756 | IIC_VLD1x4u_WriteVST4 = 231, |
| 4757 | IIC_VST1x3_WriteVST3 = 232, |
| 4758 | IIC_VST1x3u_WriteVST3 = 233, |
| 4759 | IIC_VLD1x3u_WriteVST3 = 234, |
| 4760 | IIC_VLD1u_WriteVST1 = 235, |
| 4761 | IIC_VST1x2_WriteVST2 = 236, |
| 4762 | IIC_VLD1x2u_WriteVST2 = 237, |
| 4763 | IIC_VST2ln_WriteVST1 = 238, |
| 4764 | IIC_VST2lnu_WriteVST1 = 239, |
| 4765 | IIC_VST2lnu = 240, |
| 4766 | IIC_VST2 = 241, |
| 4767 | IIC_VLD1u_WriteVST2 = 242, |
| 4768 | IIC_VST2_WriteVST2 = 243, |
| 4769 | IIC_VST2x2_WriteVST4 = 244, |
| 4770 | IIC_VST2x2u_WriteVST4 = 245, |
| 4771 | IIC_VLD1u_WriteVST4 = 246, |
| 4772 | IIC_VST3ln_WriteVST2 = 247, |
| 4773 | IIC_VST3lnu_WriteVST2 = 248, |
| 4774 | IIC_VST3lnu = 249, |
| 4775 | IIC_VST3ln = 250, |
| 4776 | IIC_VST3_WriteVST3 = 251, |
| 4777 | IIC_VST3u_WriteVST3 = 252, |
| 4778 | IIC_VST4ln_WriteVST2 = 253, |
| 4779 | IIC_VST4lnu_WriteVST2 = 254, |
| 4780 | IIC_VST4lnu = 255, |
| 4781 | IIC_VST4_WriteVST4 = 256, |
| 4782 | IIC_VST4u_WriteVST4 = 257, |
| 4783 | IIC_fpStore_mu = 258, |
| 4784 | IIC_fpStore_m = 259, |
| 4785 | IIC_fpStore64 = 260, |
| 4786 | IIC_fpStore16 = 261, |
| 4787 | IIC_fpStore32 = 262, |
| 4788 | IIC_VSUBiQ = 263, |
| 4789 | IIC_VTB1 = 264, |
| 4790 | IIC_VTB2 = 265, |
| 4791 | IIC_VTB3 = 266, |
| 4792 | IIC_VTB4 = 267, |
| 4793 | IIC_VTBX1 = 268, |
| 4794 | IIC_VTBX2 = 269, |
| 4795 | IIC_VTBX3 = 270, |
| 4796 | IIC_VTBX4 = 271, |
| 4797 | IIC_fpCVTDI_WriteFPCVT = 272, |
| 4798 | IIC_fpCVTHI_WriteFPCVT = 273, |
| 4799 | IIC_fpCVTSI_WriteFPCVT = 274, |
| 4800 | IIC_VPERMD = 275, |
| 4801 | IIC_VPERMQ = 276, |
| 4802 | IIC_VPERMQ3 = 277, |
| 4803 | IIC_iUNAsi_WriteALU = 278, |
| 4804 | IIC_iBITi_WriteALU = 279, |
| 4805 | IIC_iCMPsi_WriteCMPsi_ReadALU_ReadALU = 280, |
| 4806 | IIC_iCMPi_WriteCMP = 281, |
| 4807 | IIC_iCMPr_WriteCMP = 282, |
| 4808 | IIC_iCMPsi_WriteCMPsi = 283, |
| 4809 | IIC_iALUx = 284, |
| 4810 | WriteLd = 285, |
| 4811 | IIC_iLoad_bh_i_WriteLd = 286, |
| 4812 | IIC_iLoad_bh_iu_WriteLd = 287, |
| 4813 | IIC_iLoad_bh_si_WriteLd = 288, |
| 4814 | IIC_iLoad_d_ru_WriteLd = 289, |
| 4815 | IIC_iLoad_d_i_WriteLd = 290, |
| 4816 | IIC_iLoad_i_WriteLd = 291, |
| 4817 | IIC_iLoad_iu_WriteLd = 292, |
| 4818 | IIC_iLoad_si_WriteLd = 293, |
| 4819 | IIC_iMVNsi_WriteALU = 294, |
| 4820 | IIC_iALUsir_WriteALUsi_ReadALU = 295, |
| 4821 | IIC_iMUL16_WriteMAC16_ReadMUL_ReadMUL_ReadMAC = 296, |
| 4822 | IIC_iMAC32 = 297, |
| 4823 | WriteALU = 298, |
| 4824 | WriteST = 299, |
| 4825 | IIC_iStore_bh_i_WriteST = 300, |
| 4826 | IIC_iStore_bh_iu_WriteST = 301, |
| 4827 | IIC_iStore_bh_si_WriteST = 302, |
| 4828 | IIC_iStore_d_ru_WriteST = 303, |
| 4829 | IIC_iStore_d_r_WriteST = 304, |
| 4830 | IIC_iStore_iu_WriteST = 305, |
| 4831 | IIC_iStore_i_WriteST = 306, |
| 4832 | IIC_iStore_si_WriteST = 307, |
| 4833 | IIC_iEXTAsr_WriteALU_ReadALU = 308, |
| 4834 | IIC_iEXTr_WriteALU_ReadALU = 309, |
| 4835 | IIC_iTSTi_WriteCMP = 310, |
| 4836 | IIC_iTSTr_WriteCMP = 311, |
| 4837 | IIC_iTSTsi_WriteCMPsi = 312, |
| 4838 | IIC_iBITr_WriteALU = 313, |
| 4839 | IIC_iLoad_bh_r_WriteLd = 314, |
| 4840 | IIC_iLoad_r_WriteLd = 315, |
| 4841 | IIC_iPop_WriteLd = 316, |
| 4842 | IIC_iStore_m_WriteST = 317, |
| 4843 | IIC_iStore_bh_r_WriteST = 318, |
| 4844 | IIC_iStore_r_WriteST = 319, |
| 4845 | IIC_iTSTr_WriteALU = 320, |
| 4846 | ANDri_ORRri_EORri_BICri = 321, |
| 4847 | ANDrr_ORRrr_EORrr_BICrr = 322, |
| 4848 | ANDrsi_ORRrsi_EORrsi_BICrsi = 323, |
| 4849 | ANDrsr_ORRrsr_EORrsr_BICrsr = 324, |
| 4850 | MOVsra_glue_MOVsrl_glue = 325, |
| 4851 | MOVsr_MOVsi = 326, |
| 4852 | MVNsr = 327, |
| 4853 | MOVCCsi_MOVCCsr = 328, |
| 4854 | MVNr = 329, |
| 4855 | MOVCCi32imm = 330, |
| 4856 | MOVi32imm = 331, |
| 4857 | MOV_ga_pcrel = 332, |
| 4858 | MOV_ga_pcrel_ldr = 333, |
| 4859 | SEL = 334, |
| 4860 | BFC_BFI_UBFX_SBFX = 335, |
| 4861 | MULv5_MUL_SMMUL_SMMULR = 336, |
| 4862 | MLAv5_MLA_MLS_SMMLA_SMMLAR_SMMLS_SMMLSR = 337, |
| 4863 | SMULLv5_SMULL_UMULLv5 = 338, |
| 4864 | UMULL = 339, |
| 4865 | SMLAL_UMLALv5_UMLAL_UMAAL_SMLALv5_SMLALBB_SMLALBT_SMLALTB_SMLALTT = 340, |
| 4866 | SMLAD_SMLADX_SMLSD_SMLSDX = 341, |
| 4867 | SMLALD_SMLSLD = 342, |
| 4868 | SMLALDX_SMLSLDX = 343, |
| 4869 | SMUAD_SMUADX_SMUSD_SMUSDX = 344, |
| 4870 | SMULBB_SMULBT_SMULTB_SMULTT_SMULWB_SMULWT = 345, |
| 4871 | SMLABB_SMLABT_SMLATB_SMLATT_SMLAWB_SMLAWT = 346, |
| 4872 | LDRi12_PICLDR = 347, |
| 4873 | LDRrs = 348, |
| 4874 | LDRBi12_PICLDRH_PICLDRB_PICLDRSH_PICLDRSB_LDRH_LDRSH_LDRSB = 349, |
| 4875 | LDRHTii_LDRSHTii_LDRSBTii = 350, |
| 4876 | LDRHTi_LDRHTr_LDRH_POST_LDRH_PRE_LDRSHTi_LDRSHTr_LDRSH_POST_LDRSH_PRE_LDRSBTi_LDRSBTr_LDRSB_POST_LDRSB_PRE = 351, |
| 4877 | SXTB_SXTB16_SXTH_UXTB_UXTB16_UXTH = 352, |
| 4878 | t2SXTB_t2SXTB16_t2SXTH_t2UXTB_t2UXTB16_t2UXTH = 353, |
| 4879 | t2MOVCCi32imm = 354, |
| 4880 | t2MOVi32imm = 355, |
| 4881 | t2MOV_ga_pcrel = 356, |
| 4882 | t2MOVi16_ga_pcrel = 357, |
| 4883 | t2SEL = 358, |
| 4884 | t2BFC_t2UBFX_t2SBFX = 359, |
| 4885 | t2BFI = 360, |
| 4886 | QADD_QADD16_QADD8_QSUB_QSUB16_QSUB8_QDADD_QDSUB_QASX_QSAX_UQADD8_UQADD16_UQSUB8_UQSUB16_UQASX_UQSAX = 361, |
| 4887 | SSAT_SSAT16_USAT_USAT16_t2QADD_t2QADD16_t2QADD8_t2QSUB_t2QSUB16_t2QSUB8_t2QDADD_t2QDSUB_t2QASX_t2QSAX_t2UQADD8_t2UQADD16_t2UQSUB8_t2UQSUB16_t2UQASX_t2UQSAX = 362, |
| 4888 | t2SSAT_t2SSAT16_t2USAT_t2USAT16 = 363, |
| 4889 | SADD8_SADD16_SSUB8_SSUB16_SASX_SSAX_UADD8_UADD16_USUB8_USUB16_UASX_USAX = 364, |
| 4890 | t2SADD8_t2SADD16_t2SSUB8_t2SSUB16_t2SASX_t2SSAX_t2UADD8_t2UADD16_t2USUB8_t2USUB16_t2UASX_t2USAX = 365, |
| 4891 | SHADD8_SHADD16_SHSUB8_SHSUB16_SHASX_SHSAX_UHADD8_UHADD16_UHSUB8_UHSUB16_UHASX_UHSAX = 366, |
| 4892 | SXTAB_SXTAB16_SXTAH_UXTAB_UXTAB16_UXTAH = 367, |
| 4893 | t2SHADD8_t2SHADD16_t2SHSUB8_t2SHSUB16_t2SHASX_t2SHSAX_t2UHADD8_t2UHADD16_t2UHSUB8_t2UHSUB16_t2UHASX_t2UHSAX = 368, |
| 4894 | t2SXTAB_t2SXTAB16_t2SXTAH_t2UXTAB_t2UXTAB16_t2UXTAH = 369, |
| 4895 | USAD8 = 370, |
| 4896 | USADA8 = 371, |
| 4897 | SMUSD_SMUSDX = 372, |
| 4898 | t2MUL_t2SMMUL_t2SMMULR = 373, |
| 4899 | t2SMULBB_t2SMULBT_t2SMULTB_t2SMULTT_t2SMULWB_t2SMULWT = 374, |
| 4900 | t2SMUSD_t2SMUSDX = 375, |
| 4901 | t2MLA_t2MLS_t2SMMLA_t2SMMLAR_t2SMMLS_t2SMMLSR = 376, |
| 4902 | t2SMUAD_t2SMUADX = 377, |
| 4903 | SMLSD_SMLSDX = 378, |
| 4904 | t2SMLABB_t2SMLABT_t2SMLATB_t2SMLATT_t2SMLAWB_t2SMLAWT = 379, |
| 4905 | t2SMLSD_t2SMLSDX = 380, |
| 4906 | t2SMLAD_t2SMLADX = 381, |
| 4907 | SMULL = 382, |
| 4908 | t2SMULL_t2UMULL = 383, |
| 4909 | t2SMLAL_t2SMLALBB_t2SMLALBT_t2SMLALD_t2SMLALDX_t2SMLALTB_t2SMLALTT_t2UMLAL_t2SMLSLD_t2SMLSLDX_t2UMAAL = 384, |
| 4910 | SDIV_UDIV_t2SDIV_t2UDIV = 385, |
| 4911 | LDRi12 = 386, |
| 4912 | LDRBi12 = 387, |
| 4913 | LDRBrs = 388, |
| 4914 | t2LDRpci_pic = 389, |
| 4915 | t2LDRi12_t2LDRi8_t2LDRpci_tLDRi_tLDRpci_tLDRspi = 390, |
| 4916 | t2LDRs = 391, |
| 4917 | t2LDRBi12_t2LDRBi8_t2LDRBpci_t2LDRHi12_t2LDRHi8_t2LDRHpci_tLDRBi_tLDRHi = 392, |
| 4918 | t2LDRBs_t2LDRHs = 393, |
| 4919 | LDREX_LDREXB_LDREXD_LDREXH_tLDRpci_pic = 394, |
| 4920 | tLDRBr_tLDRHr = 395, |
| 4921 | tLDRr = 396, |
| 4922 | LDRH_PICLDRB_PICLDRH = 397, |
| 4923 | LDRcp = 398, |
| 4924 | t2LDRSBpcrel_t2LDRSHpcrel = 399, |
| 4925 | t2LDRSBi12_t2LDRSBi8_t2LDRSBpci_t2LDRSHi12_t2LDRSHi8_t2LDRSHpci = 400, |
| 4926 | t2LDRSBs_t2LDRSHs = 401, |
| 4927 | tLDRSB_tLDRSH = 402, |
| 4928 | LDRBT_POST_IMM_LDRBT_POST_REG_LDRB_POST_REG_LDRB_PRE_REG = 403, |
| 4929 | LDRB_POST_IMM_LDRB_PRE_IMM = 404, |
| 4930 | LDRT_POST_IMM_LDRT_POST_REG_LDR_POST_REG_LDR_PRE_REG = 405, |
| 4931 | LDR_POST_IMM_LDR_PRE_IMM = 406, |
| 4932 | LDRH_POST_LDRH_PRE_LDRHTi_LDRHTr = 407, |
| 4933 | LDRHTii = 408, |
| 4934 | t2LDRB_POST_imm_t2LDRB_PRE_imm_t2LDRH_POST_imm_t2LDRH_PRE_imm_t2LDR_POST_imm_t2LDR_PRE_imm = 409, |
| 4935 | t2LDRB_POST_t2LDRB_PRE_t2LDRH_POST_t2LDRH_PRE = 410, |
| 4936 | t2LDR_POST_t2LDR_PRE = 411, |
| 4937 | t2LDRBT_t2LDRHT = 412, |
| 4938 | t2LDRT = 413, |
| 4939 | t2LDRSB_POST_imm_t2LDRSB_PRE_imm_t2LDRSH_POST_imm_t2LDRSH_PRE_imm = 414, |
| 4940 | t2LDRSB_POST_t2LDRSB_PRE_t2LDRSH_POST_t2LDRSH_PRE = 415, |
| 4941 | t2LDRSBT_t2LDRSHT = 416, |
| 4942 | t2LDRDi8 = 417, |
| 4943 | LDRD = 418, |
| 4944 | LDRD_POST_LDRD_PRE = 419, |
| 4945 | t2LDRD_POST_t2LDRD_PRE = 420, |
| 4946 | LDMDA_LDMDB_LDMIA_LDMIB_t2LDMDB_t2LDMIA_sysLDMDA_sysLDMDB_sysLDMIA_sysLDMIB_tLDMIA = 421, |
| 4947 | LDMDA_UPD_LDMDB_UPD_LDMIA_UPD_LDMIB_UPD_tLDMIA_UPD_sysLDMDA_UPD_sysLDMDB_UPD_sysLDMIA_UPD_sysLDMIB_UPD_t2LDMDB_UPD_t2LDMIA_UPD = 422, |
| 4948 | LDMIA_RET_t2LDMIA_RET = 423, |
| 4949 | tPOP_RET = 424, |
| 4950 | tPOP = 425, |
| 4951 | PICSTR_STRi12 = 426, |
| 4952 | PICSTRB_PICSTRH_STRBi12_STRH = 427, |
| 4953 | STRrs = 428, |
| 4954 | STRBrs = 429, |
| 4955 | STREX_STREXB_STREXD_STREXH = 430, |
| 4956 | t2STRi12_t2STRi8_tSTRi_tSTRspi = 431, |
| 4957 | t2STRs = 432, |
| 4958 | t2STRBi12_t2STRBi8_t2STRHi12_t2STRHi8_tSTRBi_tSTRHi = 433, |
| 4959 | t2STRBs_t2STRHs = 434, |
| 4960 | tSTRBr_tSTRHr = 435, |
| 4961 | tSTRr = 436, |
| 4962 | STRBT_POST_IMM_STRBT_POST_REG_STRB_POST_REG_STRB_PRE_REG_STRH_POST_STRH_PRE_STRHTi_STRHTr = 437, |
| 4963 | STRB_POST_IMM_STRB_PRE_IMM = 438, |
| 4964 | STRT_POST_IMM_STRT_POST_REG_STR_POST_REG_STR_PRE_REG_STRi_preidx_STRr_preidx_STRBi_preidx_STRBr_preidx_STRH_preidx = 439, |
| 4965 | STR_POST_IMM_STR_PRE_IMM = 440, |
| 4966 | STRBT_POST_STRT_POST_t2STR_POST_imm_t2STR_PRE_imm_t2STRB_POST_imm_t2STRB_PRE_imm_t2STRH_POST_imm_t2STRH_PRE_imm = 441, |
| 4967 | t2STR_POST_t2STR_PRE_t2STRH_PRE = 442, |
| 4968 | t2STRB_POST_t2STRB_PRE_t2STRH_POST = 443, |
| 4969 | t2STR_preidx_t2STRB_preidx_t2STRH_preidx = 444, |
| 4970 | t2STRBT_t2STRHT = 445, |
| 4971 | t2STRT = 446, |
| 4972 | STRD = 447, |
| 4973 | t2STRDi8 = 448, |
| 4974 | t2STRD_POST_t2STRD_PRE = 449, |
| 4975 | STRD_POST_STRD_PRE = 450, |
| 4976 | STMDA_STMDB_STMIA_STMIB_sysSTMDA_sysSTMDB_sysSTMIA_sysSTMIB_t2STMDB_t2STMIA = 451, |
| 4977 | STMDA_UPD_STMDB_UPD_STMIA_UPD_STMIB_UPD_sysSTMDA_UPD_sysSTMDB_UPD_sysSTMIA_UPD_sysSTMIB_UPD_t2STMDB_UPD_t2STMIA_UPD_tSTMIA_UPD = 452, |
| 4978 | tPUSH = 453, |
| 4979 | LDRLIT_ga_abs_tLDRLIT_ga_abs = 454, |
| 4980 | LDRLIT_ga_pcrel_tLDRLIT_ga_pcrel = 455, |
| 4981 | LDRLIT_ga_pcrel_ldr = 456, |
| 4982 | t2IT = 457, |
| 4983 | ITasm = 458, |
| 4984 | VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16_VANDq_VBICq_VEORq_VORNq_VORRq_VBIFq_VBITq_VBSLq_VBSPq = 459, |
| 4985 | VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8_VANDd_VBICd_VEORd_VORNd_VORRd_VBIFd_VBITd_VBSLd_VBSPd = 460, |
| 4986 | VSUBv16i8_VSUBv2i64_VSUBv4i32_VSUBv8i16 = 461, |
| 4987 | VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8_VADDWsv2i64_VADDWsv4i32_VADDWsv8i16_VADDWuv2i64_VADDWuv4i32_VADDWuv8i16_VSUBWsv2i64_VSUBWsv4i32_VSUBWsv8i16_VSUBWuv2i64_VSUBWuv4i32_VSUBWuv8i16 = 462, |
| 4988 | VNEGf32q = 463, |
| 4989 | VNEGfd = 464, |
| 4990 | VNEGs16d_VNEGs32d_VNEGs8d_VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16_VPADDi16_VPADDi32_VPADDi8_VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLsv1i64_VSHLsv2i32_VSHLsv4i16_VSHLsv8i8_VSHLuv1i64_VSHLuv2i32_VSHLuv4i16_VSHLuv8i8_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8_VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8 = 465, |
| 4991 | VNEGs16q_VNEGs32q_VNEGs8q_VSHLsv16i8_VSHLsv2i64_VSHLsv4i32_VSHLsv8i16_VSHLuv16i8_VSHLuv2i64_VSHLuv4i32_VSHLuv8i16_VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 466, |
| 4992 | VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16_VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16_VTSTv16i8_VTSTv4i32_VTSTv8i16 = 467, |
| 4993 | VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8_VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8_VTSTv2i32_VTSTv4i16_VTSTv8i8 = 468, |
| 4994 | VHSUBsv16i8_VHSUBsv4i32_VHSUBsv8i16_VHSUBuv16i8_VHSUBuv4i32_VHSUBuv8i16 = 469, |
| 4995 | VHSUBsv2i32_VHSUBsv4i16_VHSUBsv8i8_VHSUBuv2i32_VHSUBuv4i16_VHSUBuv8i8 = 470, |
| 4996 | VBICiv2i32_VBICiv4i16_VBICiv4i32_VBICiv8i16_VORRiv2i32_VORRiv4i16_VORRiv4i32_VORRiv8i16 = 471, |
| 4997 | VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLsv1i64_VQSHLsv2i32_VQSHLsv4i16_VQSHLsv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8_VQSHLuv1i64_VQSHLuv2i32_VQSHLuv4i16_VQSHLuv8i8 = 472, |
| 4998 | VQSHLsv16i8_VQSHLsv2i64_VQSHLsv4i32_VQSHLsv8i16_VQSHLuv16i8_VQSHLuv2i64_VQSHLuv4i32_VQSHLuv8i16 = 473, |
| 4999 | VCLSv16i8_VCLSv4i32_VCLSv8i16_VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 474, |
| 5000 | VCLSv2i32_VCLSv4i16_VCLSv8i8_VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd = 475, |
| 5001 | VEXTd16_VEXTd32_VEXTd8 = 476, |
| 5002 | VEXTq16_VEXTq32_VEXTq64_VEXTq8 = 477, |
| 5003 | VREV16d8_VREV32d16_VREV32d8_VREV64d16_VREV64d32_VREV64d8 = 478, |
| 5004 | VREV16q8_VREV32q16_VREV32q8_VREV64q16_VREV64q32_VREV64q8 = 479, |
| 5005 | VABALsv2i64_VABALsv4i32_VABALsv8i16_VABALuv2i64_VABALuv4i32_VABALuv8i16_VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 480, |
| 5006 | VABAsv16i8_VABAsv4i32_VABAsv8i16_VABAuv16i8_VABAuv4i32_VABAuv8i16 = 481, |
| 5007 | VPADALsv16i8_VPADALsv4i32_VPADALsv8i16_VPADALuv16i8_VPADALuv4i32_VPADALuv8i16 = 482, |
| 5008 | VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8_VRSRAsv16i8_VRSRAsv1i64_VRSRAsv2i32_VRSRAsv2i64_VRSRAsv4i16_VRSRAsv4i32_VRSRAsv8i16_VRSRAsv8i8_VRSRAuv16i8_VRSRAuv1i64_VRSRAuv2i32_VRSRAuv2i64_VRSRAuv4i16_VRSRAuv4i32_VRSRAuv8i16_VRSRAuv8i8_VSRAsv16i8_VSRAsv1i64_VSRAsv2i32_VSRAsv2i64_VSRAsv4i16_VSRAsv4i32_VSRAsv8i16_VSRAsv8i8_VSRAuv16i8_VSRAuv1i64_VSRAuv2i32_VSRAuv2i64_VSRAuv4i16_VSRAuv4i32_VSRAuv8i16_VSRAuv8i8 = 483, |
| 5009 | VACGEfd_VACGEhd_VACGTfd_VACGThd_VCEQfd_VCEQhd_VCGEfd_VCGEhd_VCGTfd_VCGThd = 484, |
| 5010 | VACGEfq_VACGEhq_VACGTfq_VACGThq_VCEQfq_VCEQhq_VCGEfq_VCGEhq_VCGTfq_VCGThq = 485, |
| 5011 | VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16_VQSUBsv16i8_VQSUBsv2i64_VQSUBsv4i32_VQSUBsv8i16_VQSUBuv16i8_VQSUBuv2i64_VQSUBuv4i32_VQSUBuv8i16 = 486, |
| 5012 | VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8_VQSUBsv1i64_VQSUBsv2i32_VQSUBsv4i16_VQSUBsv8i8_VQSUBuv1i64_VQSUBuv2i32_VQSUBuv4i16_VQSUBuv8i8 = 487, |
| 5013 | VCEQzv16i8_VCEQzv2f32_VCEQzv2i32_VCEQzv4f16_VCEQzv4f32_VCEQzv4i16_VCEQzv4i32_VCEQzv8f16_VCEQzv8i16_VCEQzv8i8_VCGEzv16i8_VCGEzv2f32_VCGEzv2i32_VCGEzv4f16_VCGEzv4f32_VCGEzv4i16_VCGEzv4i32_VCGEzv8f16_VCGEzv8i16_VCGEzv8i8_VCGTzv16i8_VCGTzv2f32_VCGTzv2i32_VCGTzv4f16_VCGTzv4f32_VCGTzv4i16_VCGTzv4i32_VCGTzv8f16_VCGTzv8i16_VCGTzv8i8_VCLEzv16i8_VCLEzv2f32_VCLEzv2i32_VCLEzv4f16_VCLEzv4f32_VCLEzv4i16_VCLEzv4i32_VCLEzv8f16_VCLEzv8i16_VCLEzv8i8_VCLTzv16i8_VCLTzv2f32_VCLTzv2i32_VCLTzv4f16_VCLTzv4f32_VCLTzv4i16_VCLTzv4i32_VCLTzv8f16_VCLTzv8i16_VCLTzv8i8 = 488, |
| 5014 | VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16_VQRSHLsv16i8_VQRSHLsv2i64_VQRSHLsv4i32_VQRSHLsv8i16_VQRSHLuv16i8_VQRSHLuv2i64_VQRSHLuv4i32_VQRSHLuv8i16 = 489, |
| 5015 | VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VQRSHLsv1i64_VQRSHLsv2i32_VQRSHLsv4i16_VQRSHLsv8i8_VQRSHLuv1i64_VQRSHLuv2i32_VQRSHLuv4i16_VQRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 490, |
| 5016 | VABSfd = 491, |
| 5017 | VABSfq = 492, |
| 5018 | VABSv16i8_VABSv4i32_VABSv8i16 = 493, |
| 5019 | VABSv2i32_VABSv4i16_VABSv8i8 = 494, |
| 5020 | VQABSv16i8_VQABSv4i32_VQABSv8i16_VQNEGv16i8_VQNEGv4i32_VQNEGv8i16 = 495, |
| 5021 | VQABSv2i32_VQABSv4i16_VQABSv8i8_VQNEGv2i32_VQNEGv4i16_VQNEGv8i8 = 496, |
| 5022 | VQADDsv16i8_VQADDsv2i64_VQADDsv4i32_VQADDsv8i16_VQADDuv16i8_VQADDuv2i64_VQADDuv4i32_VQADDuv8i16 = 497, |
| 5023 | VQADDsv1i64_VQADDsv2i32_VQADDsv4i16_VQADDsv8i8_VQADDuv1i64_VQADDuv2i32_VQADDuv4i16_VQADDuv8i8 = 498, |
| 5024 | VRECPEd_VRECPEfd_VRECPEhd_VRSQRTEd_VRSQRTEfd_VRSQRTEhd = 499, |
| 5025 | VRECPEfq_VRECPEhq_VRECPEq_VRSQRTEfq_VRSQRTEhq_VRSQRTEq = 500, |
| 5026 | VADDHNv2i32_VADDHNv4i16_VADDHNv8i8_VSUBHNv2i32_VSUBHNv4i16_VSUBHNv8i8 = 501, |
| 5027 | VSHRNv2i32_VSHRNv4i16_VSHRNv8i8 = 502, |
| 5028 | VRADDHNv2i32_VRADDHNv4i16_VRADDHNv8i8_VRSUBHNv2i32_VRSUBHNv4i16_VRSUBHNv8i8 = 503, |
| 5029 | VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8_VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8_VQSHRUNv2i32_VQSHRUNv4i16_VQSHRUNv8i8_VQRSHRNsv2i32_VQRSHRNsv4i16_VQRSHRNsv8i8_VQRSHRNuv2i32_VQRSHRNuv4i16_VQRSHRNuv8i8_VQRSHRUNv2i32_VQRSHRUNv4i16_VQRSHRUNv8i8 = 504, |
| 5030 | VTBL1 = 505, |
| 5031 | VTBX1 = 506, |
| 5032 | VTBL2 = 507, |
| 5033 | VTBX2 = 508, |
| 5034 | VTBL3_VTBL3Pseudo = 509, |
| 5035 | VTBX3_VTBX3Pseudo = 510, |
| 5036 | VTBL4_VTBL4Pseudo = 511, |
| 5037 | VTBX4_VTBX4Pseudo = 512, |
| 5038 | VSWPd_VSWPq = 513, |
| 5039 | VTRNd16_VTRNd32_VTRNd8_VUZPd16_VUZPd8_VZIPd16_VZIPd8 = 514, |
| 5040 | VTRNq16_VTRNq32_VTRNq8 = 515, |
| 5041 | VUZPq16_VUZPq32_VUZPq8_VZIPq16_VZIPq32_VZIPq8 = 516, |
| 5042 | VABSD_VNEGD = 517, |
| 5043 | VABSS_VNEGS = 518, |
| 5044 | VCMPD_VCMPZD_VCMPED_VCMPEZD = 519, |
| 5045 | VCMPS_VCMPZS_VCMPES_VCMPEZS = 520, |
| 5046 | VADDS_VSUBS = 521, |
| 5047 | VADDfd_VSUBfd_VABDfd_VABDhd_VMAXfd_VMAXhd_VMINfd_VMINhd = 522, |
| 5048 | VADDfq_VSUBfq_VABDfq_VABDhq_VMAXfq_VMAXhq_VMINfq_VMINhq = 523, |
| 5049 | VABDLsv2i64_VABDLsv4i32_VABDLsv8i16_VABDLuv2i64_VABDLuv4i32_VABDLuv8i16_VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16_VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 524, |
| 5050 | VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8_VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8_VPMAXs16_VPMAXs32_VPMAXs8_VPMAXu16_VPMAXu32_VPMAXu8_VPMINs16_VPMINs32_VPMINs8_VPMINu16_VPMINu32_VPMINu8 = 525, |
| 5051 | VPADDf_VPMAXf_VPMAXh_VPMINf_VPMINh = 526, |
| 5052 | VADDD_VSUBD = 527, |
| 5053 | VRECPSfd_VRECPShd_VRSQRTSfd_VRSQRTShd = 528, |
| 5054 | VRECPSfq_VRECPShq_VRSQRTSfq_VRSQRTShq = 529, |
| 5055 | VMULS_VNMULS = 530, |
| 5056 | VMULfd = 531, |
| 5057 | VMULfq = 532, |
| 5058 | VMULpd_VMULslhd_VMULslv4i16_VMULv4i16_VMULv8i8_VQDMULHslv4i16_VQDMULHv4i16_VQRDMULHslv4i16_VQRDMULHv4i16_VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32 = 533, |
| 5059 | VMULpq_VMULslhq_VMULslv8i16_VMULv16i8_VMULv8i16_VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 534, |
| 5060 | VMULslfd = 535, |
| 5061 | VMULslfq = 536, |
| 5062 | VMULslv2i32_VMULv2i32_VQDMULHslv2i32_VQDMULHv2i32_VQRDMULHslv2i32_VQRDMULHv2i32_VMULLsv2i64_VMULLuv2i64_VQDMULLv2i64 = 537, |
| 5063 | VMULslv4i32_VMULv4i32_VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 538, |
| 5064 | VMULLp64 = 539, |
| 5065 | VMLAD_VMLSD_VNMLAD_VNMLSD = 540, |
| 5066 | VMLAH_VMLSH_VNMLAH_VNMLSH = 541, |
| 5067 | VMLALslsv2i32_VMLALsluv2i32_VMLALsv2i64_VMLALuv2i64_VMLAslv2i32_VMLAv2i32_VMLSLslsv2i32_VMLSLsluv2i32_VMLSLsv2i64_VMLSLuv2i64_VMLSslv2i32_VMLSv2i32_VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 542, |
| 5068 | VMLALslsv4i16_VMLALsluv4i16_VMLALsv4i32_VMLALsv8i16_VMLALuv4i32_VMLALuv8i16_VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSLslsv4i16_VMLSLsluv4i16_VMLSLsv4i32_VMLSLsv8i16_VMLSLuv4i32_VMLSLuv8i16_VMLSslv4i16_VMLSv4i16_VMLSv8i8_VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 543, |
| 5069 | VMLAS_VMLSS_VNMLAS_VNMLSS = 544, |
| 5070 | VMLAfd_VMLAhd_VMLAslfd_VMLAslhd_VMLSfd_VMLShd_VMLSslfd_VMLSslhd = 545, |
| 5071 | VMLAfq_VMLAhq_VMLAslfq_VMLAslhq_VMLSfq_VMLShq_VMLSslfq_VMLSslhq = 546, |
| 5072 | VMLAslv4i32_VMLAv4i32_VMLSslv4i32_VMLSv4i32 = 547, |
| 5073 | VMLAslv8i16_VMLAv16i8_VMLAv8i16_VMLSslv8i16_VMLSv16i8_VMLSv8i16 = 548, |
| 5074 | VFMAD_VFMSD_VFNMAD_VFNMSD = 549, |
| 5075 | VFMAS_VFMSS_VFNMAS_VFNMSS = 550, |
| 5076 | VFNMAH_VFNMSH = 551, |
| 5077 | VFMAfd_VFMSfd = 552, |
| 5078 | VFMAfq_VFMSfq = 553, |
| 5079 | VCVTANSDf_VCVTANSDh_VCVTANSQf_VCVTANSQh_VCVTANUDf_VCVTANUDh_VCVTANUQf_VCVTANUQh_VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTBDH_VCVTMNSDf_VCVTMNSDh_VCVTMNSQf_VCVTMNSQh_VCVTMNUDf_VCVTMNUDh_VCVTMNUQf_VCVTMNUQh_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNNSDf_VCVTNNSDh_VCVTNNSQf_VCVTNNSQh_VCVTNNUDf_VCVTNNUDh_VCVTNNUQf_VCVTNNUQh_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPNSDf_VCVTPNSDh_VCVTPNSQf_VCVTPNSQh_VCVTPNUDf_VCVTPNUDh_VCVTPNUQf_VCVTPNUQh_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTTDH_VCVTTHD = 554, |
| 5080 | VCVTBHD = 555, |
| 5081 | VCVTBHS_VCVTTHS = 556, |
| 5082 | VCVTBSH_VCVTTSH = 557, |
| 5083 | VCVTDS = 558, |
| 5084 | VCVTSD = 559, |
| 5085 | VCVTf2h_VCVTf2sq_VCVTf2uq_VCVTf2xsq_VCVTf2xuq_VCVTh2f_VCVTh2sq_VCVTh2uq_VCVTh2xsq_VCVTh2xuq_VCVTs2fq_VCVTs2hq_VCVTu2fq_VCVTu2hq_VCVTxs2fq_VCVTxs2hq_VCVTxu2fq_VCVTxu2hq = 560, |
| 5086 | VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTh2sd_VCVTh2ud_VCVTh2xsd_VCVTh2xud_VCVTs2fd_VCVTs2hd_VCVTu2fd_VCVTu2hd_VCVTxs2fd_VCVTxs2hd_VCVTxu2fd_VCVTxu2hd = 561, |
| 5087 | VSITOD_VUITOD = 562, |
| 5088 | VSITOH_VUITOH = 563, |
| 5089 | VSITOS_VUITOS = 564, |
| 5090 | VTOSHD_VTOSIRD_VTOSIZD_VTOSLD_VTOUHD_VTOUIRD_VTOUIZD_VTOULD = 565, |
| 5091 | VTOSHH_VTOSIRH_VTOSIZH_VTOSLH_VTOUHH_VTOUIRH_VTOUIZH_VTOULH = 566, |
| 5092 | VTOSHS_VTOSIRS_VTOSIZS_VTOSLS_VTOUHS_VTOUIRS_VTOUIZS_VTOULS = 567, |
| 5093 | VMOVv16i8_VMOVv1i64_VMOVv2f32_VMOVv2i32_VMOVv2i64_VMOVv4f32_VMOVv4i16_VMOVv4i32_VMOVv8i16_VMOVv8i8_VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16 = 568, |
| 5094 | VMOVD_VMOVDcc_FCONSTD = 569, |
| 5095 | VMOVS_VMOVScc_FCONSTS = 570, |
| 5096 | VMVNd_VMVNq = 571, |
| 5097 | VMOVNv2i32_VMOVNv4i16_VMOVNv8i8 = 572, |
| 5098 | VMOVLsv2i64_VMOVLsv4i32_VMOVLsv8i16_VMOVLuv2i64_VMOVLuv4i32_VMOVLuv8i16 = 573, |
| 5099 | VQMOVNsuv2i32_VQMOVNsuv4i16_VQMOVNsuv8i8_VQMOVNsv2i32_VQMOVNsv4i16_VQMOVNsv8i8_VQMOVNuv2i32_VQMOVNuv4i16_VQMOVNuv8i8 = 574, |
| 5100 | VDUPLN16d_VDUPLN32d_VDUPLN8d = 575, |
| 5101 | VDUPLN16q_VDUPLN32q_VDUPLN8q = 576, |
| 5102 | VDUP16d_VDUP16q_VDUP32d_VDUP32q_VDUP8d_VDUP8q = 577, |
| 5103 | VMOVRS = 578, |
| 5104 | VMOVSR = 579, |
| 5105 | VSETLNi16_VSETLNi32_VSETLNi8 = 580, |
| 5106 | VMOVRRD_VMOVRRS = 581, |
| 5107 | VMOVDRR = 582, |
| 5108 | VMOVSRR = 583, |
| 5109 | VGETLNi32_VGETLNu16_VGETLNu8 = 584, |
| 5110 | VGETLNs16_VGETLNs8 = 585, |
| 5111 | VMRS_VMRS_FPCXTNS_VMRS_FPCXTS_VMRS_FPEXC_VMRS_FPINST_VMRS_FPINST2_VMRS_FPSCR_NZCVQC_VMRS_FPSID_VMRS_MVFR0_VMRS_MVFR1_VMRS_MVFR2_VMRS_P0_VMRS_VPR = 586, |
| 5112 | VMSR_VMSR_FPCXTNS_VMSR_FPCXTS_VMSR_FPEXC_VMSR_FPINST_VMSR_FPINST2_VMSR_FPSCR_NZCVQC_VMSR_FPSID_VMSR_P0_VMSR_VPR = 587, |
| 5113 | FMSTAT = 588, |
| 5114 | VLDRD = 589, |
| 5115 | VLDRS = 590, |
| 5116 | VSTRD = 591, |
| 5117 | VSTRS = 592, |
| 5118 | VLDMQIA = 593, |
| 5119 | VSTMQIA = 594, |
| 5120 | VLDMDIA_VLDMSIA = 595, |
| 5121 | VLDMDDB_UPD_VLDMDIA_UPD_VLDMSDB_UPD_VLDMSIA_UPD = 596, |
| 5122 | VSTMDIA_VSTMSIA = 597, |
| 5123 | VSTMDDB_UPD_VSTMDIA_UPD_VSTMSDB_UPD_VSTMSIA_UPD = 598, |
| 5124 | VLD1d16_VLD1d32_VLD1d64_VLD1d8 = 599, |
| 5125 | VLD1q16_VLD1q32_VLD1q64_VLD1q8 = 600, |
| 5126 | VLD1d16wb_fixed_VLD1d16wb_register_VLD1d32wb_fixed_VLD1d32wb_register_VLD1d64wb_fixed_VLD1d64wb_register_VLD1d8wb_fixed_VLD1d8wb_register = 601, |
| 5127 | VLD1q16wb_fixed_VLD1q16wb_register_VLD1q32wb_fixed_VLD1q32wb_register_VLD1q64wb_fixed_VLD1q64wb_register_VLD1q8wb_fixed_VLD1q8wb_register = 602, |
| 5128 | VLD1d16T_VLD1d32T_VLD1d64T_VLD1d8T_VLD1d64TPseudo_VLD1d64TPseudoWB_fixed_VLD1d64TPseudoWB_register = 603, |
| 5129 | VLD1d16Twb_fixed_VLD1d16Twb_register_VLD1d32Twb_fixed_VLD1d32Twb_register_VLD1d64Twb_fixed_VLD1d64Twb_register_VLD1d8Twb_fixed_VLD1d8Twb_register = 604, |
| 5130 | VLD1d16Q_VLD1d32Q_VLD1d64Q_VLD1d8Q_VLD1d64QPseudo_VLD1d64QPseudoWB_fixed_VLD1d64QPseudoWB_register = 605, |
| 5131 | VLD1d16Qwb_fixed_VLD1d16Qwb_register_VLD1d32Qwb_fixed_VLD1d32Qwb_register_VLD1d64Qwb_fixed_VLD1d64Qwb_register_VLD1d8Qwb_fixed_VLD1d8Qwb_register = 606, |
| 5132 | VLD2b16_VLD2b32_VLD2b8_VLD2d16_VLD2d32_VLD2d8 = 607, |
| 5133 | VLD2q16_VLD2q32_VLD2q8_VLD2q16Pseudo_VLD2q32Pseudo_VLD2q8Pseudo = 608, |
| 5134 | VLD2b16wb_fixed_VLD2b16wb_register_VLD2b32wb_fixed_VLD2b32wb_register_VLD2b8wb_fixed_VLD2b8wb_register_VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register = 609, |
| 5135 | VLD2q16wb_fixed_VLD2q16wb_register_VLD2q32wb_fixed_VLD2q32wb_register_VLD2q8wb_fixed_VLD2q8wb_register_VLD2q16PseudoWB_fixed_VLD2q16PseudoWB_register_VLD2q32PseudoWB_fixed_VLD2q32PseudoWB_register_VLD2q8PseudoWB_fixed_VLD2q8PseudoWB_register = 610, |
| 5136 | VLD3d16_VLD3d32_VLD3d8_VLD3q16_VLD3q32_VLD3q8 = 611, |
| 5137 | VLD3d16Pseudo_VLD3d32Pseudo_VLD3d8Pseudo_VLD3q16oddPseudo_VLD3q32oddPseudo_VLD3q8oddPseudo = 612, |
| 5138 | VLD3d16_UPD_VLD3d32_UPD_VLD3d8_UPD_VLD3q16_UPD_VLD3q32_UPD_VLD3q8_UPD = 613, |
| 5139 | VLD3d16Pseudo_UPD_VLD3d32Pseudo_UPD_VLD3d8Pseudo_UPD_VLD3q16Pseudo_UPD_VLD3q16oddPseudo_UPD_VLD3q32Pseudo_UPD_VLD3q32oddPseudo_UPD_VLD3q8Pseudo_UPD_VLD3q8oddPseudo_UPD = 614, |
| 5140 | VLD4d16_VLD4d32_VLD4d8_VLD4q16_VLD4q32_VLD4q8 = 615, |
| 5141 | VLD4d16Pseudo_VLD4d32Pseudo_VLD4d8Pseudo_VLD4q16oddPseudo_VLD4q32oddPseudo_VLD4q8oddPseudo = 616, |
| 5142 | VLD4d16_UPD_VLD4d32_UPD_VLD4d8_UPD_VLD4q16_UPD_VLD4q32_UPD_VLD4q8_UPD = 617, |
| 5143 | VLD4d16Pseudo_UPD_VLD4d32Pseudo_UPD_VLD4d8Pseudo_UPD_VLD4q16Pseudo_UPD_VLD4q16oddPseudo_UPD_VLD4q32Pseudo_UPD_VLD4q32oddPseudo_UPD_VLD4q8Pseudo_UPD_VLD4q8oddPseudo_UPD = 618, |
| 5144 | VLD1DUPd16_VLD1DUPd32_VLD1DUPd8 = 619, |
| 5145 | VLD1DUPq16_VLD1DUPq32_VLD1DUPq8 = 620, |
| 5146 | VLD1LNd16_VLD1LNd8 = 621, |
| 5147 | VLD1LNd32_VLD1LNq16Pseudo_VLD1LNq32Pseudo_VLD1LNq8Pseudo = 622, |
| 5148 | VLD1DUPd16wb_fixed_VLD1DUPd16wb_register_VLD1DUPd32wb_fixed_VLD1DUPd32wb_register_VLD1DUPd8wb_fixed_VLD1DUPd8wb_register_VLD1DUPq16wb_register_VLD1DUPq32wb_register_VLD1DUPq8wb_register = 623, |
| 5149 | VLD1DUPq16wb_fixed_VLD1DUPq32wb_fixed_VLD1DUPq8wb_fixed = 624, |
| 5150 | VLD1LNd16_UPD_VLD1LNd32_UPD_VLD1LNd8_UPD_VLD1LNq16Pseudo_UPD_VLD1LNq32Pseudo_UPD_VLD1LNq8Pseudo_UPD = 625, |
| 5151 | VLD2DUPd16_VLD2DUPd16x2_VLD2DUPd32_VLD2DUPd32x2_VLD2DUPd8_VLD2DUPd8x2 = 626, |
| 5152 | VLD2LNd16_VLD2LNd32_VLD2LNd8_VLD2LNq16_VLD2LNq32_VLD2LNd16Pseudo_VLD2LNd32Pseudo_VLD2LNd8Pseudo_VLD2LNq16Pseudo_VLD2LNq32Pseudo = 627, |
| 5153 | VLD2LNd16_UPD_VLD2LNd32_UPD_VLD2LNd8_UPD_VLD2LNq16_UPD_VLD2LNq32_UPD = 628, |
| 5154 | VLD2DUPd16wb_fixed_VLD2DUPd16wb_register_VLD2DUPd16x2wb_fixed_VLD2DUPd16x2wb_register_VLD2DUPd32wb_fixed_VLD2DUPd32wb_register_VLD2DUPd32x2wb_fixed_VLD2DUPd32x2wb_register_VLD2DUPd8wb_fixed_VLD2DUPd8wb_register_VLD2DUPd8x2wb_fixed_VLD2DUPd8x2wb_register = 629, |
| 5155 | VLD2LNd16Pseudo_UPD_VLD2LNd32Pseudo_UPD_VLD2LNd8Pseudo_UPD_VLD2LNq16Pseudo_UPD_VLD2LNq32Pseudo_UPD = 630, |
| 5156 | VLD3DUPd16_VLD3DUPd32_VLD3DUPd8_VLD3DUPq16_VLD3DUPq32_VLD3DUPq8_VLD3DUPd16Pseudo_VLD3DUPd32Pseudo_VLD3DUPd8Pseudo = 631, |
| 5157 | VLD3LNd16_VLD3LNd32_VLD3LNd8_VLD3LNq16_VLD3LNq32_VLD3LNd16Pseudo_VLD3LNd32Pseudo_VLD3LNd8Pseudo_VLD3LNq16Pseudo_VLD3LNq32Pseudo = 632, |
| 5158 | VLD3DUPd16_UPD_VLD3DUPd32_UPD_VLD3DUPd8_UPD_VLD3DUPq16_UPD_VLD3DUPq32_UPD_VLD3DUPq8_UPD = 633, |
| 5159 | VLD3LNd16_UPD_VLD3LNd32_UPD_VLD3LNd8_UPD_VLD3LNq16_UPD_VLD3LNq32_UPD = 634, |
| 5160 | VLD3DUPd16Pseudo_UPD_VLD3DUPd32Pseudo_UPD_VLD3DUPd8Pseudo_UPD = 635, |
| 5161 | VLD3LNd16Pseudo_UPD_VLD3LNd32Pseudo_UPD_VLD3LNd8Pseudo_UPD_VLD3LNq16Pseudo_UPD_VLD3LNq32Pseudo_UPD = 636, |
| 5162 | VLD4DUPd16_VLD4DUPd32_VLD4DUPd8_VLD4DUPq16_VLD4DUPq32_VLD4DUPq8 = 637, |
| 5163 | VLD4LNd16_VLD4LNd32_VLD4LNd8_VLD4LNq16_VLD4LNq32_VLD4LNd16Pseudo_VLD4LNd32Pseudo_VLD4LNd8Pseudo_VLD4LNq16Pseudo_VLD4LNq32Pseudo = 638, |
| 5164 | VLD4DUPd16Pseudo_VLD4DUPd32Pseudo_VLD4DUPd8Pseudo = 639, |
| 5165 | VLD4DUPd16_UPD_VLD4DUPd32_UPD_VLD4DUPd8_UPD_VLD4DUPq16_UPD_VLD4DUPq32_UPD_VLD4DUPq8_UPD = 640, |
| 5166 | VLD4LNd16_UPD_VLD4LNd32_UPD_VLD4LNd8_UPD_VLD4LNq16_UPD_VLD4LNq32_UPD = 641, |
| 5167 | VLD4DUPd16Pseudo_UPD_VLD4DUPd32Pseudo_UPD_VLD4DUPd8Pseudo_UPD = 642, |
| 5168 | VLD4LNd16Pseudo_UPD_VLD4LNd32Pseudo_UPD_VLD4LNd8Pseudo_UPD_VLD4LNq16Pseudo_UPD_VLD4LNq32Pseudo_UPD = 643, |
| 5169 | VST1d16_VST1d32_VST1d64_VST1d8 = 644, |
| 5170 | VST1q16_VST1q32_VST1q64_VST1q8 = 645, |
| 5171 | VST1d16wb_fixed_VST1d16wb_register_VST1d32wb_fixed_VST1d32wb_register_VST1d64wb_fixed_VST1d64wb_register_VST1d8wb_fixed_VST1d8wb_register = 646, |
| 5172 | VST1q16wb_fixed_VST1q16wb_register_VST1q32wb_fixed_VST1q32wb_register_VST1q64wb_fixed_VST1q64wb_register_VST1q8wb_fixed_VST1q8wb_register = 647, |
| 5173 | VST1d16T_VST1d32T_VST1d64T_VST1d8T_VST1d64TPseudo = 648, |
| 5174 | VST1d16Twb_fixed_VST1d16Twb_register_VST1d32Twb_fixed_VST1d32Twb_register_VST1d64Twb_fixed_VST1d64Twb_register_VST1d8Twb_fixed_VST1d8Twb_register = 649, |
| 5175 | VST1d64TPseudoWB_fixed_VST1d64TPseudoWB_register = 650, |
| 5176 | VST1d16Q_VST1d16QPseudo_VST1d32Q_VST1d32QPseudo_VST1d64Q_VST1d64QPseudo_VST1d8Q_VST1d8QPseudo = 651, |
| 5177 | VST1d16QPseudoWB_fixed_VST1d16QPseudoWB_register_VST1d32QPseudoWB_fixed_VST1d32QPseudoWB_register_VST1d64QPseudoWB_fixed_VST1d64QPseudoWB_register_VST1d8QPseudoWB_fixed_VST1d8QPseudoWB_register = 652, |
| 5178 | VST1d16Qwb_fixed_VST1d16Qwb_register_VST1d32Qwb_fixed_VST1d32Qwb_register_VST1d64Qwb_fixed_VST1d64Qwb_register_VST1d8Qwb_fixed_VST1d8Qwb_register = 653, |
| 5179 | VST2b16_VST2b32_VST2b8 = 654, |
| 5180 | VST2d16_VST2d32_VST2d8 = 655, |
| 5181 | VST2b16wb_fixed_VST2b16wb_register_VST2b32wb_fixed_VST2b32wb_register_VST2b8wb_fixed_VST2b8wb_register_VST2d16wb_fixed_VST2d16wb_register_VST2d32wb_fixed_VST2d32wb_register_VST2d8wb_fixed_VST2d8wb_register = 656, |
| 5182 | VST2q16_VST2q32_VST2q8_VST2q16Pseudo_VST2q32Pseudo_VST2q8Pseudo = 657, |
| 5183 | VST2q16wb_fixed_VST2q16wb_register_VST2q32wb_fixed_VST2q32wb_register_VST2q8wb_fixed_VST2q8wb_register = 658, |
| 5184 | VST2q16PseudoWB_fixed_VST2q16PseudoWB_register_VST2q32PseudoWB_fixed_VST2q32PseudoWB_register_VST2q8PseudoWB_fixed_VST2q8PseudoWB_register = 659, |
| 5185 | VST3d16_VST3d32_VST3d8_VST3q16_VST3q32_VST3q8_VST3d16Pseudo_VST3d32Pseudo_VST3d8Pseudo_VST3q16oddPseudo_VST3q32oddPseudo_VST3q8oddPseudo = 660, |
| 5186 | VST3d16_UPD_VST3d32_UPD_VST3d8_UPD_VST3q16_UPD_VST3q32_UPD_VST3q8_UPD_VST3d16Pseudo_UPD_VST3d32Pseudo_UPD_VST3d8Pseudo_UPD_VST3q16Pseudo_UPD_VST3q16oddPseudo_UPD_VST3q32Pseudo_UPD_VST3q32oddPseudo_UPD_VST3q8Pseudo_UPD_VST3q8oddPseudo_UPD = 661, |
| 5187 | VST4d16_VST4d32_VST4d8_VST4q16_VST4q32_VST4q8_VST4d16Pseudo_VST4d32Pseudo_VST4d8Pseudo_VST4q16oddPseudo_VST4q32oddPseudo_VST4q8oddPseudo = 662, |
| 5188 | VST4d16_UPD_VST4d32_UPD_VST4d8_UPD_VST4q16_UPD_VST4q32_UPD_VST4q8_UPD_VST4d16Pseudo_UPD_VST4d32Pseudo_UPD_VST4d8Pseudo_UPD_VST4q16Pseudo_UPD_VST4q16oddPseudo_UPD_VST4q32Pseudo_UPD_VST4q32oddPseudo_UPD_VST4q8Pseudo_UPD_VST4q8oddPseudo_UPD = 663, |
| 5189 | VST1LNd16_VST1LNd32_VST1LNd8_VST1LNq16Pseudo_VST1LNq32Pseudo_VST1LNq8Pseudo = 664, |
| 5190 | VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD_VST1LNq16Pseudo_UPD_VST1LNq32Pseudo_UPD_VST1LNq8Pseudo_UPD = 665, |
| 5191 | VST2LNd16_VST2LNd32_VST2LNd8_VST2LNq16_VST2LNq32_VST2LNd16Pseudo_VST2LNd32Pseudo_VST2LNd8Pseudo_VST2LNq16Pseudo_VST2LNq32Pseudo = 666, |
| 5192 | VST2LNd16_UPD_VST2LNd32_UPD_VST2LNd8_UPD_VST2LNq16_UPD_VST2LNq32_UPD = 667, |
| 5193 | VST2LNd16Pseudo_UPD_VST2LNd32Pseudo_UPD_VST2LNd8Pseudo_UPD_VST2LNq16Pseudo_UPD_VST2LNq32Pseudo_UPD = 668, |
| 5194 | VST3LNd16_VST3LNd32_VST3LNd8_VST3LNq16_VST3LNq32_VST3LNd16Pseudo_VST3LNd32Pseudo_VST3LNd8Pseudo = 669, |
| 5195 | VST3LNq16Pseudo_VST3LNq32Pseudo = 670, |
| 5196 | VST3LNd16_UPD_VST3LNd32_UPD_VST3LNd8_UPD_VST3LNq16_UPD_VST3LNq32_UPD = 671, |
| 5197 | VST3LNd16Pseudo_UPD_VST3LNd32Pseudo_UPD_VST3LNd8Pseudo_UPD_VST3LNq16Pseudo_UPD_VST3LNq32Pseudo_UPD = 672, |
| 5198 | VST4LNd16_VST4LNd32_VST4LNd8_VST4LNq16_VST4LNq32_VST4LNd16Pseudo_VST4LNd32Pseudo_VST4LNd8Pseudo_VST4LNq16Pseudo_VST4LNq32Pseudo = 673, |
| 5199 | VST4LNd16_UPD_VST4LNd32_UPD_VST4LNd8_UPD_VST4LNq16_UPD_VST4LNq32_UPD = 674, |
| 5200 | VST4LNd16Pseudo_UPD_VST4LNd32Pseudo_UPD_VST4LNd8Pseudo_UPD_VST4LNq16Pseudo_UPD_VST4LNq32Pseudo_UPD = 675, |
| 5201 | VDIVS = 676, |
| 5202 | VSQRTS = 677, |
| 5203 | VDIVD = 678, |
| 5204 | VSQRTD = 679, |
| 5205 | ABS = 680, |
| 5206 | COPY = 681, |
| 5207 | t2MOVCCi_t2MOVCCi16 = 682, |
| 5208 | t2MOVi_t2MOVi16 = 683, |
| 5209 | t2ABS = 684, |
| 5210 | t2USAD8_t2USADA8 = 685, |
| 5211 | t2SDIV_t2UDIV = 686, |
| 5212 | t2LDREX_t2LDREXB_t2LDREXD_t2LDREXH_t2LDA_t2LDAB_t2LDAEX_t2LDAEXB_t2LDAEXD_t2LDAEXH_t2LDAH = 687, |
| 5213 | LDA_LDAB_LDAEX_LDAEXB_LDAEXD_LDAEXH_LDAH = 688, |
| 5214 | LDRBT_POST = 689, |
| 5215 | MOVsr = 690, |
| 5216 | t2MOVSsr_t2MOVsr = 691, |
| 5217 | t2MOVsra_glue_t2MOVsrl_glue = 692, |
| 5218 | MOVTi16_ga_pcrel_MOVTi16_t2MOVTi16_ga_pcrel_t2MOVTi16 = 693, |
| 5219 | ADDSri_ADCri_ADDri_RSBSri_RSBri_RSCri_SBCri_t2ADDSri_t2ADCri_t2ADDri_t2ADDri12_t2RSBSri_t2RSBri_t2SBCri = 694, |
| 5220 | CLZ_t2CLZ = 695, |
| 5221 | t2ANDri_t2BICri_t2EORri_t2ORRri = 696, |
| 5222 | t2MVNCCi = 697, |
| 5223 | t2MVNi = 698, |
| 5224 | t2MVNr = 699, |
| 5225 | t2MVNs = 700, |
| 5226 | ADDSrr_ADCrr_ADDrr_RSBrr_RSCrr_SBCrr_t2ADDSrr_t2ADCrr_t2ADDrr_t2SBCrr = 701, |
| 5227 | CRC32B_CRC32CB_CRC32CH_CRC32CW_CRC32H_CRC32W_t2CRC32B_t2CRC32CB_t2CRC32CH_t2CRC32CW_t2CRC32H_t2CRC32W = 702, |
| 5228 | t2ANDrr_t2BICrr_t2EORrr = 703, |
| 5229 | ADDSrsi_ADCrsi_ADDrsi_RSBrsi_RSCrsi_SBCrsi = 704, |
| 5230 | t2ADDSrs = 705, |
| 5231 | t2ADCrs_t2ADDrs_t2SBCrs = 706, |
| 5232 | t2ANDrs_t2BICrs_t2EORrs_t2ORRrs = 707, |
| 5233 | t2RSBrs = 708, |
| 5234 | ADDSrsr = 709, |
| 5235 | ADCrsr_ADDrsr_RSBrsr_RSCrsr_SBCrsr = 710, |
| 5236 | ADR = 711, |
| 5237 | MVNi = 712, |
| 5238 | MVNsi = 713, |
| 5239 | t2MOVSsi_t2MOVsi = 714, |
| 5240 | ASRi_RORi = 715, |
| 5241 | ASRr_RORr_LSRi_LSRr_LSLi_LSLr = 716, |
| 5242 | CMPri_CMNri = 717, |
| 5243 | CMPrr_CMNzrr = 718, |
| 5244 | CMPrsi_CMNzrsi = 719, |
| 5245 | CMPrsr_CMNzrsr = 720, |
| 5246 | t2LDC2L_OFFSET_t2LDC2L_OPTION_t2LDC2L_POST_t2LDC2L_PRE_t2LDC2_OFFSET_t2LDC2_OPTION_t2LDC2_POST_t2LDC2_PRE_t2LDCL_OFFSET_t2LDCL_OPTION_t2LDCL_POST_t2LDCL_PRE_t2LDC_OFFSET_t2LDC_OPTION_t2LDC_POST_t2LDC_PRE_RRXi = 721, |
| 5247 | RBIT_REV_REV16_REVSH = 722, |
| 5248 | RRX = 723, |
| 5249 | TSTri = 724, |
| 5250 | TSTrr = 725, |
| 5251 | TSTrsi = 726, |
| 5252 | TSTrsr = 727, |
| 5253 | MRS_MRSbanked_MRSsys = 728, |
| 5254 | MSR_MSRbanked_MSRi = 729, |
| 5255 | SRSDA_SRSDA_UPD_SRSDB_SRSDB_UPD_SRSIA_SRSIA_UPD_SRSIB_SRSIB_UPD_t2SRSDB_t2SRSDB_UPD_t2SRSIA_t2SRSIA_UPD_RFEDA_RFEDA_UPD_RFEDB_RFEDB_UPD_RFEIA_RFEIA_UPD_RFEIB_RFEIB_UPD_t2RFEDB_t2RFEDBW_t2RFEIA_t2RFEIAW = 730, |
| 5256 | t2STREX_t2STREXB_t2STREXD_t2STREXH = 731, |
| 5257 | STL_STLB_STLEX_STLEXB_STLEXD_STLEXH_STLH = 732, |
| 5258 | t2STL_t2STLB_t2STLEX_t2STLEXB_t2STLEXD_t2STLEXH_t2STLH = 733, |
| 5259 | VABDfd_VABDhd = 734, |
| 5260 | VABDfq_VABDhq = 735, |
| 5261 | VABSD = 736, |
| 5262 | VABSH = 737, |
| 5263 | VABSS = 738, |
| 5264 | VABShd = 739, |
| 5265 | VABShq = 740, |
| 5266 | VACGEfd_VACGEhd_VACGTfd_VACGThd = 741, |
| 5267 | VACGEfq_VACGEhq_VACGTfq_VACGThq = 742, |
| 5268 | VADDH_VSUBH = 743, |
| 5269 | VADDfd_VSUBfd = 744, |
| 5270 | VADDhd_VSUBhd = 745, |
| 5271 | VADDfq_VSUBfq = 746, |
| 5272 | VADDhq_VSUBhq = 747, |
| 5273 | VLDRH = 748, |
| 5274 | VLDR_FPCXTNS_off_VLDR_FPCXTNS_post_VLDR_FPCXTNS_pre_VLDR_FPCXTS_off_VLDR_FPCXTS_post_VLDR_FPCXTS_pre_VLDR_FPSCR_NZCVQC_off_VLDR_FPSCR_NZCVQC_post_VLDR_FPSCR_NZCVQC_pre_VLDR_FPSCR_off_VLDR_FPSCR_post_VLDR_FPSCR_pre_VLDR_P0_off_VLDR_P0_post_VLDR_P0_pre_VLDR_VPR_off_VLDR_VPR_post_VLDR_VPR_pre = 749, |
| 5275 | VSTRH = 750, |
| 5276 | VSTR_FPCXTNS_off_VSTR_FPCXTNS_post_VSTR_FPCXTNS_pre_VSTR_FPCXTS_off_VSTR_FPCXTS_post_VSTR_FPCXTS_pre_VSTR_FPSCR_NZCVQC_off_VSTR_FPSCR_NZCVQC_post_VSTR_FPSCR_NZCVQC_pre_VSTR_FPSCR_off_VSTR_FPSCR_post_VSTR_FPSCR_pre_VSTR_P0_off_VSTR_P0_post_VSTR_P0_pre_VSTR_VPR_off_VSTR_VPR_post_VSTR_VPR_pre = 751, |
| 5277 | VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 752, |
| 5278 | VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8 = 753, |
| 5279 | VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16 = 754, |
| 5280 | VABDLsv4i32_VABDLsv8i16_VABDLuv4i32_VABDLuv8i16 = 755, |
| 5281 | VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8 = 756, |
| 5282 | VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8 = 757, |
| 5283 | VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16 = 758, |
| 5284 | VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16 = 759, |
| 5285 | VANDd_VBICd_VEORd = 760, |
| 5286 | VANDq_VBICq_VEORq = 761, |
| 5287 | VBICiv2i32_VBICiv4i16 = 762, |
| 5288 | VBICiv4i32_VBICiv8i16 = 763, |
| 5289 | VBIFd_VBITd_VBSLd_VBSPd = 764, |
| 5290 | VBIFq_VBITq_VBSLq_VBSPq = 765, |
| 5291 | VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16 = 766, |
| 5292 | VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8 = 767, |
| 5293 | VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 768, |
| 5294 | VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd = 769, |
| 5295 | VCMPEH_VCMPEZH_VCMPH_VCMPZH = 770, |
| 5296 | VDUP16d_VDUP32d_VDUP8d = 771, |
| 5297 | VSELEQD_VSELEQH_VSELEQS_VSELGED_VSELGEH_VSELGES_VSELGTD_VSELGTH_VSELGTS_VSELVSD_VSELVSH_VSELVSS = 772, |
| 5298 | VFMAhd_VFMShd = 773, |
| 5299 | VFMAhq_VFMShq = 774, |
| 5300 | VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8 = 775, |
| 5301 | VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16 = 776, |
| 5302 | VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 777, |
| 5303 | VPMAXf_VPMAXh_VPMINf_VPMINh = 778, |
| 5304 | VNEGH = 779, |
| 5305 | VNEGhd = 780, |
| 5306 | VNEGhq = 781, |
| 5307 | VNEGs16d_VNEGs32d_VNEGs8d = 782, |
| 5308 | VNEGs16q_VNEGs32q_VNEGs8q = 783, |
| 5309 | VPADDi16_VPADDi32_VPADDi8 = 784, |
| 5310 | VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8 = 785, |
| 5311 | VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8 = 786, |
| 5312 | VQABSv2i32_VQABSv4i16_VQABSv8i8 = 787, |
| 5313 | VQABSv16i8_VQABSv4i32_VQABSv8i16 = 788, |
| 5314 | VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 789, |
| 5315 | VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 790, |
| 5316 | VQDMULHslv2i32_VQDMULHv2i32_VQDMULLv2i64_VQRDMULHslv2i32_VQRDMULHv2i32 = 791, |
| 5317 | VQDMULHslv4i16_VQDMULHv4i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32_VQRDMULHslv4i16_VQRDMULHv4i16 = 792, |
| 5318 | VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 793, |
| 5319 | VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 794, |
| 5320 | VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8 = 795, |
| 5321 | VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16 = 796, |
| 5322 | VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 797, |
| 5323 | VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8 = 798, |
| 5324 | VST1d16T_VST1d32T_VST1d64T_VST1d8T = 799, |
| 5325 | VST1d16Q_VST1d32Q_VST1d64Q_VST1d8Q = 800, |
| 5326 | VST1d64QPseudo = 801, |
| 5327 | VST1LNd16_VST1LNd32_VST1LNd8 = 802, |
| 5328 | VST1LNdAsm_16_VST1LNdAsm_32_VST1LNdAsm_8 = 803, |
| 5329 | VST1d64QPseudoWB_fixed_VST1d64QPseudoWB_register = 804, |
| 5330 | VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD = 805, |
| 5331 | VST1LNdWB_fixed_Asm_16_VST1LNdWB_fixed_Asm_32_VST1LNdWB_fixed_Asm_8_VST1LNdWB_register_Asm_16_VST1LNdWB_register_Asm_32_VST1LNdWB_register_Asm_8 = 806, |
| 5332 | VST2q16_VST2q32_VST2q8 = 807, |
| 5333 | VST2LNd16_VST2LNd32_VST2LNd8 = 808, |
| 5334 | VST2LNdAsm_16_VST2LNdAsm_32_VST2LNdAsm_8 = 809, |
| 5335 | VST2LNd16Pseudo_VST2LNd32Pseudo_VST2LNd8Pseudo = 810, |
| 5336 | VST2LNq16_VST2LNq32 = 811, |
| 5337 | VST2LNqAsm_16_VST2LNqAsm_32 = 812, |
| 5338 | VST2LNd16_UPD_VST2LNd32_UPD_VST2LNd8_UPD = 813, |
| 5339 | VST2LNdWB_fixed_Asm_16_VST2LNdWB_fixed_Asm_32_VST2LNdWB_fixed_Asm_8_VST2LNdWB_register_Asm_16_VST2LNdWB_register_Asm_32_VST2LNdWB_register_Asm_8 = 814, |
| 5340 | VST2LNd16Pseudo_UPD_VST2LNd32Pseudo_UPD_VST2LNd8Pseudo_UPD = 815, |
| 5341 | VST2LNqWB_fixed_Asm_16_VST2LNqWB_fixed_Asm_32_VST2LNqWB_register_Asm_16_VST2LNqWB_register_Asm_32 = 816, |
| 5342 | VST3d16_VST3d32_VST3d8_VST3q16_VST3q32_VST3q8 = 817, |
| 5343 | VST3dAsm_16_VST3dAsm_32_VST3dAsm_8_VST3qAsm_16_VST3qAsm_32_VST3qAsm_8 = 818, |
| 5344 | VST3d16Pseudo_VST3d32Pseudo_VST3d8Pseudo = 819, |
| 5345 | VST3LNd16_VST3LNd32_VST3LNd8 = 820, |
| 5346 | VST3LNdAsm_16_VST3LNdAsm_32_VST3LNdAsm_8 = 821, |
| 5347 | VST3LNd16Pseudo_VST3LNd32Pseudo_VST3LNd8Pseudo = 822, |
| 5348 | VST3LNqAsm_16_VST3LNqAsm_32 = 823, |
| 5349 | VST3d16_UPD_VST3d32_UPD_VST3d8_UPD_VST3q16_UPD_VST3q32_UPD_VST3q8_UPD = 824, |
| 5350 | VST3dWB_fixed_Asm_16_VST3dWB_fixed_Asm_32_VST3dWB_fixed_Asm_8_VST3dWB_register_Asm_16_VST3dWB_register_Asm_32_VST3dWB_register_Asm_8_VST3qWB_fixed_Asm_16_VST3qWB_fixed_Asm_32_VST3qWB_fixed_Asm_8_VST3qWB_register_Asm_16_VST3qWB_register_Asm_32_VST3qWB_register_Asm_8 = 825, |
| 5351 | VST3LNd16_UPD_VST3LNd32_UPD_VST3LNd8_UPD = 826, |
| 5352 | VST3LNdWB_fixed_Asm_16_VST3LNdWB_fixed_Asm_32_VST3LNdWB_fixed_Asm_8_VST3LNdWB_register_Asm_16_VST3LNdWB_register_Asm_32_VST3LNdWB_register_Asm_8 = 827, |
| 5353 | VST3LNd16Pseudo_UPD_VST3LNd32Pseudo_UPD_VST3LNd8Pseudo_UPD = 828, |
| 5354 | VST3LNqWB_fixed_Asm_16_VST3LNqWB_fixed_Asm_32_VST3LNqWB_register_Asm_16_VST3LNqWB_register_Asm_32 = 829, |
| 5355 | VST4d16_VST4d32_VST4d8_VST4q16_VST4q32_VST4q8 = 830, |
| 5356 | VST4dAsm_16_VST4dAsm_32_VST4dAsm_8_VST4qAsm_16_VST4qAsm_32_VST4qAsm_8 = 831, |
| 5357 | VST4d16Pseudo_VST4d32Pseudo_VST4d8Pseudo = 832, |
| 5358 | VST4LNd16_VST4LNd32_VST4LNd8 = 833, |
| 5359 | VST4LNdAsm_16_VST4LNdAsm_32_VST4LNdAsm_8 = 834, |
| 5360 | VST4LNd16Pseudo_VST4LNd32Pseudo_VST4LNd8Pseudo = 835, |
| 5361 | VST4LNq16_VST4LNq32 = 836, |
| 5362 | VST4LNqAsm_16_VST4LNqAsm_32 = 837, |
| 5363 | VST4d16_UPD_VST4d32_UPD_VST4d8_UPD_VST4q16_UPD_VST4q32_UPD_VST4q8_UPD = 838, |
| 5364 | VST4dWB_fixed_Asm_16_VST4dWB_fixed_Asm_32_VST4dWB_fixed_Asm_8_VST4dWB_register_Asm_16_VST4dWB_register_Asm_32_VST4dWB_register_Asm_8_VST4qWB_fixed_Asm_16_VST4qWB_fixed_Asm_32_VST4qWB_fixed_Asm_8_VST4qWB_register_Asm_16_VST4qWB_register_Asm_32_VST4qWB_register_Asm_8 = 839, |
| 5365 | VST4LNd16_UPD_VST4LNd32_UPD_VST4LNd8_UPD = 840, |
| 5366 | VST4LNdWB_fixed_Asm_16_VST4LNdWB_fixed_Asm_32_VST4LNdWB_fixed_Asm_8_VST4LNdWB_register_Asm_16_VST4LNdWB_register_Asm_32_VST4LNdWB_register_Asm_8 = 841, |
| 5367 | VST4LNd16Pseudo_UPD_VST4LNd32Pseudo_UPD_VST4LNd8Pseudo_UPD = 842, |
| 5368 | VST4LNqWB_fixed_Asm_16_VST4LNqWB_fixed_Asm_32_VST4LNqWB_register_Asm_16_VST4LNqWB_register_Asm_32 = 843, |
| 5369 | BKPT_tBKPT_CDP_CDP2_t2CDP_t2CDP2_CLREX_t2CLREX_CONSTPOOL_ENTRY_COPY_STRUCT_BYVAL_I32_CPS1p_CPS2p_CPS3p_t2CPS1p_t2CPS2p_t2CPS3p_DBG_t2DBG_DMB_t2DMB_DSB_t2DSB_ERET_HINT_t2HINT_tHINT_HLT_tHLT_HVC_ISB_t2ISB_SETEND_tSETEND_SETPAN_t2SETPAN_SMC_t2SMC_SPACE_SWP_SWPB_TRAP_TRAPNaCl_UDF_t2DCPS1_t2DCPS2_t2DCPS3_t2SG_t2TT_t2TTA_t2TTAT_t2TTT_tCPS_CMP_SWAP_16_CMP_SWAP_32_CMP_SWAP_64_CMP_SWAP_8 = 844, |
| 5370 | t2HVC_tTRAP_SVC_tSVC = 845, |
| 5371 | t2UDF_tUDF_t__brkdiv0 = 846, |
| 5372 | LDC2L_OFFSET_LDC2L_OPTION_LDC2L_POST_LDC2L_PRE_LDC2_OFFSET_LDC2_OPTION_LDC2_POST_LDC2_PRE_LDCL_OFFSET_LDCL_OPTION_LDCL_POST_LDCL_PRE_LDC_OFFSET_LDC_OPTION_LDC_POST_LDC_PRE_STC2L_OFFSET_STC2L_OPTION_STC2L_POST_STC2L_PRE_STC2_OFFSET_STC2_OPTION_STC2_POST_STC2_PRE_STCL_OFFSET_STCL_OPTION_STCL_POST_STCL_PRE_STC_OFFSET_STC_OPTION_STC_POST_STC_PRE_t2STC2L_OFFSET_t2STC2L_OPTION_t2STC2L_POST_t2STC2L_PRE_t2STC2_OFFSET_t2STC2_OPTION_t2STC2_POST_t2STC2_PRE_t2STCL_OFFSET_t2STCL_OPTION_t2STCL_POST_t2STCL_PRE_t2STC_OFFSET_t2STC_OPTION_t2STC_POST_t2STC_PRE_MEMCPY = 847, |
| 5373 | t2LDC2L_OFFSET_t2LDC2L_OPTION_t2LDC2L_POST_t2LDC2L_PRE_t2LDC2_OFFSET_t2LDC2_OPTION_t2LDC2_POST_t2LDC2_PRE_t2LDCL_OFFSET_t2LDCL_OPTION_t2LDCL_POST_t2LDCL_PRE_t2LDC_OFFSET_t2LDC_OPTION_t2LDC_POST_t2LDC_PRE = 848, |
| 5374 | LDREX_LDREXB_LDREXD_LDREXH = 849, |
| 5375 | MCR_MCR2_MCRR_MCRR2_t2MCR_t2MCR2_t2MCRR_t2MCRR2_MRC_MRC2_t2MRC_t2MRC2_MRRC_MRRC2_t2MRRC_t2MRRC2_t2MRS_AR_t2MRS_M_t2MRSbanked_t2MRSsys_AR_t2MSR_AR_t2MSR_M_t2MSRbanked = 850, |
| 5376 | FLDMXDB_UPD_FLDMXIA_FLDMXIA_UPD_FSTMXDB_UPD_FSTMXIA_FSTMXIA_UPD = 851, |
| 5377 | ADJCALLSTACKDOWN_tADJCALLSTACKDOWN_ADJCALLSTACKUP_tADJCALLSTACKUP_Int_eh_sjlj_dispatchsetup_Int_eh_sjlj_longjmp_Int_eh_sjlj_setjmp_Int_eh_sjlj_setjmp_nofp_Int_eh_sjlj_setup_dispatch_t2Int_eh_sjlj_setjmp_t2Int_eh_sjlj_setjmp_nofp_tInt_eh_sjlj_longjmp_tInt_eh_sjlj_setjmp_t2SUBS_PC_LR_JUMPTABLE_ADDRS_JUMPTABLE_INSTS_JUMPTABLE_TBB_JUMPTABLE_TBH_tInt_WIN_eh_sjlj_longjmp_VLD1LNdAsm_16_VLD1LNdAsm_32_VLD1LNdAsm_8_VLD1LNdWB_fixed_Asm_16_VLD1LNdWB_fixed_Asm_32_VLD1LNdWB_fixed_Asm_8_VLD1LNdWB_register_Asm_16_VLD1LNdWB_register_Asm_32_VLD1LNdWB_register_Asm_8_VLD2LNdAsm_16_VLD2LNdAsm_32_VLD2LNdAsm_8_VLD2LNdWB_fixed_Asm_16_VLD2LNdWB_fixed_Asm_32_VLD2LNdWB_fixed_Asm_8_VLD2LNdWB_register_Asm_16_VLD2LNdWB_register_Asm_32_VLD2LNdWB_register_Asm_8_VLD2LNqAsm_16_VLD2LNqAsm_32_VLD2LNqWB_fixed_Asm_16_VLD2LNqWB_fixed_Asm_32_VLD2LNqWB_register_Asm_16_VLD2LNqWB_register_Asm_32_VLD3DUPdAsm_16_VLD3DUPdAsm_32_VLD3DUPdAsm_8_VLD3DUPdWB_fixed_Asm_16_VLD3DUPdWB_fixed_Asm_32_VLD3DUPdWB_fixed_Asm_8_VLD3DUPdWB_register_Asm_16_VLD3DUPdWB_register_Asm_32_VLD3DUPdWB_register_Asm_8_VLD3DUPqAsm_16_VLD3DUPqAsm_32_VLD3DUPqAsm_8_VLD3DUPqWB_fixed_Asm_16_VLD3DUPqWB_fixed_Asm_32_VLD3DUPqWB_fixed_Asm_8_VLD3DUPqWB_register_Asm_16_VLD3DUPqWB_register_Asm_32_VLD3DUPqWB_register_Asm_8_VLD3LNdAsm_16_VLD3LNdAsm_32_VLD3LNdAsm_8_VLD3LNdWB_fixed_Asm_16_VLD3LNdWB_fixed_Asm_32_VLD3LNdWB_fixed_Asm_8_VLD3LNdWB_register_Asm_16_VLD3LNdWB_register_Asm_32_VLD3LNdWB_register_Asm_8_VLD3LNqAsm_16_VLD3LNqAsm_32_VLD3LNqWB_fixed_Asm_16_VLD3LNqWB_fixed_Asm_32_VLD3LNqWB_register_Asm_16_VLD3LNqWB_register_Asm_32_VLD3dAsm_16_VLD3dAsm_32_VLD3dAsm_8_VLD3dWB_fixed_Asm_16_VLD3dWB_fixed_Asm_32_VLD3dWB_fixed_Asm_8_VLD3dWB_register_Asm_16_VLD3dWB_register_Asm_32_VLD3dWB_register_Asm_8_VLD3qAsm_16_VLD3qAsm_32_VLD3qAsm_8_VLD3qWB_fixed_Asm_16_VLD3qWB_fixed_Asm_32_VLD3qWB_fixed_Asm_8_VLD3qWB_register_Asm_16_VLD3qWB_register_Asm_32_VLD3qWB_register_Asm_8_VLD4DUPdAsm_16_VLD4DUPdAsm_32_VLD4DUPdAsm_8_VLD4DUPdWB_fixed_Asm_16_VLD4DUPdWB_fixed_Asm_32_VLD4DUPdWB_fixed_Asm_8_VLD4DUPdWB_register_Asm_16_VLD4DUPdWB_register_Asm_32_VLD4DUPdWB_register_Asm_8_VLD4DUPqAsm_16_VLD4DUPqAsm_32_VLD4DUPqAsm_8_VLD4DUPqWB_fixed_Asm_16_VLD4DUPqWB_fixed_Asm_32_VLD4DUPqWB_fixed_Asm_8_VLD4DUPqWB_register_Asm_16_VLD4DUPqWB_register_Asm_32_VLD4DUPqWB_register_Asm_8_VLD4LNdAsm_16_VLD4LNdAsm_32_VLD4LNdAsm_8_VLD4LNdWB_fixed_Asm_16_VLD4LNdWB_fixed_Asm_32_VLD4LNdWB_fixed_Asm_8_VLD4LNdWB_register_Asm_16_VLD4LNdWB_register_Asm_32_VLD4LNdWB_register_Asm_8_VLD4LNqAsm_16_VLD4LNqAsm_32_VLD4LNqWB_fixed_Asm_16_VLD4LNqWB_fixed_Asm_32_VLD4LNqWB_register_Asm_16_VLD4LNqWB_register_Asm_32_VLD4dAsm_16_VLD4dAsm_32_VLD4dAsm_8_VLD4dWB_fixed_Asm_16_VLD4dWB_fixed_Asm_32_VLD4dWB_fixed_Asm_8_VLD4dWB_register_Asm_16_VLD4dWB_register_Asm_32_VLD4dWB_register_Asm_8_VLD4qAsm_16_VLD4qAsm_32_VLD4qAsm_8_VLD4qWB_fixed_Asm_16_VLD4qWB_fixed_Asm_32_VLD4qWB_fixed_Asm_8_VLD4qWB_register_Asm_16_VLD4qWB_register_Asm_32_VLD4qWB_register_Asm_8_WIN__CHKSTK_WIN__DBZCHK = 852, |
| 5378 | SUBS_PC_LR = 853, |
| 5379 | B_t2B_tB_BX_CALL_tBXNS_RET_tBX_CALL_tBX_RET_tBX_RET_vararg_BX_BX_RET_BX_pred_tBX_tBXNS_Bcc_t2Bcc_tBcc_TAILJMPd_TAILJMPr_TAILJMPr4_tTAILJMPd_tTAILJMPdND_tTAILJMPr_TCRETURNdi_TCRETURNri_TCRETURNrinotr12_tCBNZ_tCBZ = 854, |
| 5380 | BXJ = 855, |
| 5381 | tBfar = 856, |
| 5382 | BL_tBL_BL_pred_tBLXi = 857, |
| 5383 | BLXi = 858, |
| 5384 | TPsoft_tTPsoft = 859, |
| 5385 | BLX_noip_BLX_pred_noip_BLX_BLX_pred_tBLXr_noip_tBLXNSr_tBLXr = 860, |
| 5386 | BCCi64_BCCZi64 = 861, |
| 5387 | BR_JTadd_tBR_JTr_t2TBB_t2TBH = 862, |
| 5388 | BR_JTr_t2BR_JT_t2TBB_JT_t2TBH_JT_tBRIND = 863, |
| 5389 | t2BXJ = 864, |
| 5390 | BR_JTm_i12_BR_JTm_rs = 865, |
| 5391 | tADDframe = 866, |
| 5392 | MOVi16_ga_pcrel_MOVi_MOVi16_MOVCCi16_tMOVi8 = 867, |
| 5393 | MOVr_MOVr_TC_tMOVSr_tMOVr = 868, |
| 5394 | MVNCCi_MOVCCi = 869, |
| 5395 | BMOVPCB_CALL_BMOVPCRX_CALL = 870, |
| 5396 | MOVCCr = 871, |
| 5397 | tMOVCCr_pseudo_tMOVi32imm = 872, |
| 5398 | tMVN = 873, |
| 5399 | MOVCCsi = 874, |
| 5400 | t2ASRri_tASRri_t2LSRri_tLSRri_t2LSLri_tLSLri_t2RORri_t2RRX = 875, |
| 5401 | LSRi_LSLi = 876, |
| 5402 | t2MOVCCasr_t2MOVCClsl_t2MOVCClsr_t2MOVCCror = 877, |
| 5403 | t2MOVCCr = 878, |
| 5404 | t2MOVTi16_ga_pcrel_t2MOVTi16 = 879, |
| 5405 | t2MOVr = 880, |
| 5406 | tROR = 881, |
| 5407 | t2ASRrr_tASRrr_t2LSRrr_tLSRrr_t2LSLrr_tLSLrr_t2RORrr = 882, |
| 5408 | MOVPCRX_MOVPCLR = 883, |
| 5409 | tMUL = 884, |
| 5410 | SADD16_SADD8_SSUB16_SSUB8_UADD16_UADD8_USUB16_USUB8 = 885, |
| 5411 | t2SADD16_t2SADD8_t2SSUB16_t2SSUB8_t2UADD16_t2UADD8_t2USUB16_t2USUB8 = 886, |
| 5412 | SHADD16_SHADD8_SHSUB16_SHSUB8_UHADD16_UHADD8_UHSUB16_UHSUB8 = 887, |
| 5413 | t2SHADD16_t2SHADD8_t2SHSUB16_t2SHSUB8_t2UHADD16_t2UHADD8_t2UHSUB16_t2UHSUB8 = 888, |
| 5414 | QADD16_QADD8_QSUB16_QSUB8_UQADD16_UQADD8_UQSUB16_UQSUB8 = 889, |
| 5415 | t2QADD_t2QADD16_t2QADD8_t2UQADD16_t2UQADD8_t2QSUB_t2QSUB16_t2QSUB8_t2UQSUB16_t2UQSUB8 = 890, |
| 5416 | QASX_QSAX_UQASX_UQSAX = 891, |
| 5417 | t2QASX_t2QSAX_t2UQASX_t2UQSAX = 892, |
| 5418 | SSAT_SSAT16_USAT_USAT16 = 893, |
| 5419 | QADD_QSUB = 894, |
| 5420 | SBFX_UBFX = 895, |
| 5421 | t2SBFX_t2UBFX = 896, |
| 5422 | SXTB_SXTH_UXTB_UXTH = 897, |
| 5423 | t2SXTB_t2SXTH_t2UXTB_t2UXTH = 898, |
| 5424 | tSXTB_tSXTH_tUXTB_tUXTH = 899, |
| 5425 | SXTAB_SXTAH_UXTAB_UXTAH = 900, |
| 5426 | t2SXTAB_t2SXTAH_t2UXTAB_t2UXTAH = 901, |
| 5427 | LDRConstPool_t2LDRConstPool_tLDRConstPool = 902, |
| 5428 | PICLDRB_PICLDRH = 903, |
| 5429 | PICLDRSB_PICLDRSH = 904, |
| 5430 | tLDR_postidx = 905, |
| 5431 | tLDRBi_tLDRHi = 906, |
| 5432 | tLDRi_tLDRpci_tLDRspi = 907, |
| 5433 | t2LDRBpcrel_t2LDRHpcrel_t2LDRpcrel = 908, |
| 5434 | LDR_PRE_IMM = 909, |
| 5435 | LDRB_PRE_IMM = 910, |
| 5436 | t2LDRB_PRE_imm = 911, |
| 5437 | t2LDRB_PRE = 912, |
| 5438 | LDR_PRE_REG = 913, |
| 5439 | LDRB_PRE_REG = 914, |
| 5440 | LDRH_PRE = 915, |
| 5441 | LDRSB_PRE_LDRSH_PRE = 916, |
| 5442 | t2LDRH_PRE_imm_t2LDR_PRE_imm = 917, |
| 5443 | t2LDRSB_PRE_imm_t2LDRSH_PRE_imm = 918, |
| 5444 | t2LDRH_PRE = 919, |
| 5445 | t2LDRSB_PRE_t2LDRSH_PRE = 920, |
| 5446 | t2LDR_PRE = 921, |
| 5447 | LDRD_PRE = 922, |
| 5448 | t2LDRD_PRE = 923, |
| 5449 | LDRT_POST_IMM = 924, |
| 5450 | LDRBT_POST_IMM = 925, |
| 5451 | LDRHTi = 926, |
| 5452 | LDRSBTi_LDRSHTi = 927, |
| 5453 | t2LDRB_POST_imm = 928, |
| 5454 | t2LDRB_POST = 929, |
| 5455 | LDRH_POST = 930, |
| 5456 | LDRSB_POST_LDRSH_POST = 931, |
| 5457 | LDR_POST_REG = 932, |
| 5458 | LDRB_POST_REG = 933, |
| 5459 | LDRT_POST = 934, |
| 5460 | PLDi12_t2PLDi12_PLDWi12_t2PLDWi12_t2PLDWi8_t2PLDWs_t2PLDi8_t2PLDpci_t2PLDs_PLIi12_PLIrs_t2PLIi12_t2PLIi8_t2PLIpci_t2PLIs = 935, |
| 5461 | PLDrs_PLDWrs = 936, |
| 5462 | VLLDM_VLLDM_T2 = 937, |
| 5463 | STRBi12_PICSTRB_PICSTRH = 938, |
| 5464 | t2STRBT = 939, |
| 5465 | STR_PRE_IMM = 940, |
| 5466 | STRB_PRE_IMM = 941, |
| 5467 | STRBi_preidx_STRBr_preidx_STRi_preidx_STRr_preidx_STRH_preidx = 942, |
| 5468 | t2STRH_PRE_imm_t2STRB_PRE_imm_t2STR_PRE_imm = 943, |
| 5469 | STRH_PRE = 944, |
| 5470 | t2STRH_PRE_t2STR_PRE = 945, |
| 5471 | t2STRB_PRE = 946, |
| 5472 | t2STRD_PRE = 947, |
| 5473 | STR_PRE_REG = 948, |
| 5474 | STRB_PRE_REG = 949, |
| 5475 | STRD_PRE = 950, |
| 5476 | STRT_POST_IMM = 951, |
| 5477 | STRBT_POST_IMM = 952, |
| 5478 | t2STRB_POST_imm_t2STR_POST_imm = 953, |
| 5479 | t2STRB_POST = 954, |
| 5480 | STRBT_POST_REG_STRB_POST_REG = 955, |
| 5481 | STRBT_POST_STRT_POST = 956, |
| 5482 | VLSTM_VLSTM_T2 = 957, |
| 5483 | VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTBDH_VCVTTDH_VCVTTHD = 958, |
| 5484 | VTOSLS_VTOUHS_VTOULS = 959, |
| 5485 | VJCVT = 960, |
| 5486 | VRINTAD_VRINTAH_VRINTAS_VRINTMD_VRINTMH_VRINTMS_VRINTND_VRINTNH_VRINTNS_VRINTPD_VRINTPH_VRINTPS_VRINTRD_VRINTRH_VRINTRS_VRINTXD_VRINTXH_VRINTXS_VRINTZD_VRINTZH_VRINTZS = 961, |
| 5487 | VSQRTH = 962, |
| 5488 | VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8 = 963, |
| 5489 | VUDOTD_VUDOTDI_VSDOTD_VSDOTDI_VUDOTQ_VUDOTQI_VSDOTQ_VSDOTQI = 964, |
| 5490 | FCONSTD = 965, |
| 5491 | FCONSTH = 966, |
| 5492 | FCONSTS = 967, |
| 5493 | VMOVHcc_VMOVH = 968, |
| 5494 | VINSH = 969, |
| 5495 | VSTMSIA = 970, |
| 5496 | VSTMSDB_UPD_VSTMSIA_UPD = 971, |
| 5497 | VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16 = 972, |
| 5498 | VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8 = 973, |
| 5499 | VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16 = 974, |
| 5500 | VMULpd_VMULv4i16_VMULv8i8_VMULslv4i16 = 975, |
| 5501 | VMULv2i32_VMULslv2i32 = 976, |
| 5502 | VQDMULHslv2i32_VQDMULHv2i32_VQRDMULHslv2i32_VQRDMULHv2i32 = 977, |
| 5503 | VQDMULHslv4i16_VQDMULHv4i16_VQRDMULHslv4i16_VQRDMULHv4i16 = 978, |
| 5504 | VMULpq_VMULv16i8_VMULv8i16_VMULslv8i16 = 979, |
| 5505 | VMLAslv2i32_VMLAv2i32_VMLSslv2i32_VMLSv2i32 = 980, |
| 5506 | VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSslv4i16_VMLSv4i16_VMLSv8i8 = 981, |
| 5507 | VQRDMLAHslv2i32_VQRDMLAHv2i32_VQRDMLSHslv2i32_VQRDMLSHv2i32 = 982, |
| 5508 | VQRDMLAHslv4i16_VQRDMLAHv4i16_VQRDMLSHslv4i16_VQRDMLSHv4i16 = 983, |
| 5509 | VQRDMLAHslv4i32_VQRDMLAHv4i32_VQRDMLSHslv4i32_VQRDMLSHv4i32 = 984, |
| 5510 | VQRDMLAHslv8i16_VQRDMLAHv8i16_VQRDMLSHslv8i16_VQRDMLSHv8i16 = 985, |
| 5511 | VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16 = 986, |
| 5512 | VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8 = 987, |
| 5513 | VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8 = 988, |
| 5514 | VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 989, |
| 5515 | VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8 = 990, |
| 5516 | VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 991, |
| 5517 | VPADDh = 992, |
| 5518 | VCADDv2f32_VCADDv4f16_VCMLAv2f32_VCMLAv2f32_indexed_VCMLAv4f16_VCMLAv4f16_indexed = 993, |
| 5519 | VCADDv4f32_VCADDv8f16_VCMLAv4f32_VCMLAv4f32_indexed_VCMLAv8f16_VCMLAv8f16_indexed = 994, |
| 5520 | VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTs2fd_VCVTu2fd_VCVTxs2fd_VCVTxu2fd = 995, |
| 5521 | VCVTf2sq_VCVTf2uq_VCVTs2fq_VCVTu2fq_VCVTf2xsq_VCVTf2xuq_VCVTxs2fq_VCVTxu2fq = 996, |
| 5522 | NEON_VMAXNMNDf_NEON_VMAXNMNDh_NEON_VMAXNMNQf_NEON_VMAXNMNQh_VFP_VMAXNMD_VFP_VMAXNMH_VFP_VMAXNMS_NEON_VMINNMNDf_NEON_VMINNMNDh_NEON_VMINNMNQf_NEON_VMINNMNQh_VFP_VMINNMD_VFP_VMINNMH_VFP_VMINNMS = 997, |
| 5523 | VMULhd = 998, |
| 5524 | VMULhq = 999, |
| 5525 | VRINTANDf_VRINTANDh_VRINTANQf_VRINTANQh_VRINTMNDf_VRINTMNDh_VRINTMNQf_VRINTMNQh_VRINTNNDf_VRINTNNDh_VRINTNNQf_VRINTNNQh_VRINTPNDf_VRINTPNDh_VRINTPNQf_VRINTPNQh_VRINTXNDf_VRINTXNDh_VRINTXNQf_VRINTXNQh_VRINTZNDf_VRINTZNDh_VRINTZNQf_VRINTZNQh = 1000, |
| 5526 | VMOVD0_VMOVQ0 = 1001, |
| 5527 | VTRNd16_VTRNd32_VTRNd8 = 1002, |
| 5528 | VLD2d16_VLD2d32_VLD2d8 = 1003, |
| 5529 | VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register = 1004, |
| 5530 | VLD3LNd32_VLD3LNq32_VLD3LNd32Pseudo_VLD3LNq32Pseudo = 1005, |
| 5531 | VLD3LNd32_UPD_VLD3LNq32_UPD = 1006, |
| 5532 | VLD3LNd32Pseudo_UPD_VLD3LNq32Pseudo_UPD = 1007, |
| 5533 | VLD4LNd32_VLD4LNq32_VLD4LNd32Pseudo_VLD4LNq32Pseudo = 1008, |
| 5534 | VLD4LNd32_UPD_VLD4LNq32_UPD = 1009, |
| 5535 | VLD4LNd32Pseudo_UPD_VLD4LNq32Pseudo_UPD = 1010, |
| 5536 | AESD_AESE_AESIMC_AESMC = 1011, |
| 5537 | SHA1SU0 = 1012, |
| 5538 | SHA1H_SHA1SU1 = 1013, |
| 5539 | SHA1C_SHA1M_SHA1P = 1014, |
| 5540 | SHA256SU0 = 1015, |
| 5541 | SHA256H_SHA256H2_SHA256SU1 = 1016, |
| 5542 | t2LDMIA_RET = 1017, |
| 5543 | tLDMIA_UPD_t2LDMDB_UPD_t2LDMIA_UPD = 1018, |
| 5544 | t2LDMDB_t2LDMIA_tLDMIA = 1019, |
| 5545 | t2LDRB_OFFSET_imm_t2LDRH_OFFSET_imm_t2LDRSB_OFFSET_imm_t2LDRSH_OFFSET_imm = 1020, |
| 5546 | t2LDRConstPool_tLDRConstPool = 1021, |
| 5547 | t2LDRLIT_ga_pcrel = 1022, |
| 5548 | tLDRLIT_ga_abs = 1023, |
| 5549 | tLDRLIT_ga_pcrel = 1024, |
| 5550 | t2LDREX_t2LDREXB_t2LDREXD_t2LDREXH = 1025, |
| 5551 | t2STMDB_t2STMIA = 1026, |
| 5552 | t2STMDB_UPD_t2STMIA_UPD_tSTMIA_UPD = 1027, |
| 5553 | tMOVSr_tMOVr = 1028, |
| 5554 | tMOVi8 = 1029, |
| 5555 | t2MSR_AR_t2MSR_M_t2MSRbanked_t2MRS_AR_t2MRS_M_t2MRSbanked_t2MRSsys_AR = 1030, |
| 5556 | t2CLREX = 1031, |
| 5557 | t2SMLAL_t2SMLALBB_t2SMLALBT_t2SMLALD_t2SMLALDX_t2SMLALTB_t2SMLALTT_t2SMLSLD_t2SMLSLDX = 1032, |
| 5558 | t2REV_t2REV16_t2REVSH_tREV_tREV16_tREVSH = 1033, |
| 5559 | t2CDP_t2CDP2 = 1034, |
| 5560 | t2MCR_t2MCR2_t2MCRR_t2MCRR2_t2MRC_t2MRC2_t2MRRC_t2MRRC2 = 1035, |
| 5561 | t2STC2L_OFFSET_t2STC2L_OPTION_t2STC2L_POST_t2STC2L_PRE_t2STC2_OFFSET_t2STC2_OPTION_t2STC2_POST_t2STC2_PRE_t2STCL_OFFSET_t2STCL_OPTION_t2STCL_POST_t2STCL_PRE_t2STC_OFFSET_t2STC_OPTION_t2STC_POST_t2STC_PRE = 1036, |
| 5562 | tCPS_t2ISB_t2DSB_t2DMB_t2HINT_tHINT = 1037, |
| 5563 | t2UDF_tUDF = 1038, |
| 5564 | tBKPT_t2DBG = 1039, |
| 5565 | Int_eh_sjlj_dispatchsetup_Int_eh_sjlj_longjmp_Int_eh_sjlj_setjmp_Int_eh_sjlj_setjmp_nofp_Int_eh_sjlj_setup_dispatch_t2Int_eh_sjlj_setjmp_t2Int_eh_sjlj_setjmp_nofp_tInt_eh_sjlj_longjmp_tInt_eh_sjlj_setjmp_ADJCALLSTACKDOWN_ADJCALLSTACKUP_tADJCALLSTACKDOWN_tADJCALLSTACKUP = 1040, |
| 5566 | CMP_SWAP_16_CMP_SWAP_32_CMP_SWAP_64_CMP_SWAP_8 = 1041, |
| 5567 | JUMPTABLE_ADDRS_JUMPTABLE_INSTS_JUMPTABLE_TBB_JUMPTABLE_TBH = 1042, |
| 5568 | MEMCPY = 1043, |
| 5569 | VSETLNi32 = 1044, |
| 5570 | VGETLNi32 = 1045, |
| 5571 | VLD1LNdAsm_16_VLD1LNdAsm_32_VLD1LNdAsm_8_VLD1LNdWB_fixed_Asm_16_VLD1LNdWB_fixed_Asm_32_VLD1LNdWB_fixed_Asm_8_VLD1LNdWB_register_Asm_16_VLD1LNdWB_register_Asm_32_VLD1LNdWB_register_Asm_8_VLD2LNdAsm_16_VLD2LNdAsm_32_VLD2LNdAsm_8_VLD2LNdWB_fixed_Asm_16_VLD2LNdWB_fixed_Asm_32_VLD2LNdWB_fixed_Asm_8_VLD2LNdWB_register_Asm_16_VLD2LNdWB_register_Asm_32_VLD2LNdWB_register_Asm_8_VLD2LNqAsm_16_VLD2LNqAsm_32_VLD2LNqWB_fixed_Asm_16_VLD2LNqWB_fixed_Asm_32_VLD2LNqWB_register_Asm_16_VLD2LNqWB_register_Asm_32_VLD3DUPdAsm_16_VLD3DUPdAsm_32_VLD3DUPdAsm_8_VLD3DUPdWB_fixed_Asm_16_VLD3DUPdWB_fixed_Asm_32_VLD3DUPdWB_fixed_Asm_8_VLD3DUPdWB_register_Asm_16_VLD3DUPdWB_register_Asm_32_VLD3DUPdWB_register_Asm_8_VLD3DUPqAsm_16_VLD3DUPqAsm_32_VLD3DUPqAsm_8_VLD3DUPqWB_fixed_Asm_16_VLD3DUPqWB_fixed_Asm_32_VLD3DUPqWB_fixed_Asm_8_VLD3DUPqWB_register_Asm_16_VLD3DUPqWB_register_Asm_32_VLD3DUPqWB_register_Asm_8_VLD3LNdAsm_16_VLD3LNdAsm_32_VLD3LNdAsm_8_VLD3LNdWB_fixed_Asm_16_VLD3LNdWB_fixed_Asm_32_VLD3LNdWB_fixed_Asm_8_VLD3LNdWB_register_Asm_16_VLD3LNdWB_register_Asm_32_VLD3LNdWB_register_Asm_8_VLD3LNqAsm_16_VLD3LNqAsm_32_VLD3LNqWB_fixed_Asm_16_VLD3LNqWB_fixed_Asm_32_VLD3LNqWB_register_Asm_16_VLD3LNqWB_register_Asm_32_VLD3dAsm_16_VLD3dAsm_32_VLD3dAsm_8_VLD3dWB_fixed_Asm_16_VLD3dWB_fixed_Asm_32_VLD3dWB_fixed_Asm_8_VLD3dWB_register_Asm_16_VLD3dWB_register_Asm_32_VLD3dWB_register_Asm_8_VLD3qAsm_16_VLD3qAsm_32_VLD3qAsm_8_VLD3qWB_fixed_Asm_16_VLD3qWB_fixed_Asm_32_VLD3qWB_fixed_Asm_8_VLD3qWB_register_Asm_16_VLD3qWB_register_Asm_32_VLD3qWB_register_Asm_8_VLD4DUPdAsm_16_VLD4DUPdAsm_32_VLD4DUPdAsm_8_VLD4DUPdWB_fixed_Asm_16_VLD4DUPdWB_fixed_Asm_32_VLD4DUPdWB_fixed_Asm_8_VLD4DUPdWB_register_Asm_16_VLD4DUPdWB_register_Asm_32_VLD4DUPdWB_register_Asm_8_VLD4DUPqAsm_16_VLD4DUPqAsm_32_VLD4DUPqAsm_8_VLD4DUPqWB_fixed_Asm_16_VLD4DUPqWB_fixed_Asm_32_VLD4DUPqWB_fixed_Asm_8_VLD4DUPqWB_register_Asm_16_VLD4DUPqWB_register_Asm_32_VLD4DUPqWB_register_Asm_8_VLD4LNdAsm_16_VLD4LNdAsm_32_VLD4LNdAsm_8_VLD4LNdWB_fixed_Asm_16_VLD4LNdWB_fixed_Asm_32_VLD4LNdWB_fixed_Asm_8_VLD4LNdWB_register_Asm_16_VLD4LNdWB_register_Asm_32_VLD4LNdWB_register_Asm_8_VLD4LNqAsm_16_VLD4LNqAsm_32_VLD4LNqWB_fixed_Asm_16_VLD4LNqWB_fixed_Asm_32_VLD4LNqWB_register_Asm_16_VLD4LNqWB_register_Asm_32_VLD4dAsm_16_VLD4dAsm_32_VLD4dAsm_8_VLD4dWB_fixed_Asm_16_VLD4dWB_fixed_Asm_32_VLD4dWB_fixed_Asm_8_VLD4dWB_register_Asm_16_VLD4dWB_register_Asm_32_VLD4dWB_register_Asm_8_VLD4qAsm_16_VLD4qAsm_32_VLD4qAsm_8_VLD4qWB_fixed_Asm_16_VLD4qWB_fixed_Asm_32_VLD4qWB_fixed_Asm_8_VLD4qWB_register_Asm_16_VLD4qWB_register_Asm_32_VLD4qWB_register_Asm_8 = 1046, |
| 5572 | VLD1d16QPseudo_VLD1d16QPseudoWB_fixed_VLD1d16QPseudoWB_register_VLD1d32QPseudo_VLD1d32QPseudoWB_fixed_VLD1d32QPseudoWB_register_VLD1d8QPseudo_VLD1d8QPseudoWB_fixed_VLD1d8QPseudoWB_register_VLD1q16HighQPseudo_VLD1q16HighQPseudo_UPD_VLD1q16LowQPseudo_UPD_VLD1q32HighQPseudo_VLD1q32HighQPseudo_UPD_VLD1q32LowQPseudo_UPD_VLD1q64HighQPseudo_VLD1q64HighQPseudo_UPD_VLD1q64LowQPseudo_UPD_VLD1q8HighQPseudo_VLD1q8HighQPseudo_UPD_VLD1q8LowQPseudo_UPD = 1047, |
| 5573 | VLD1d16TPseudo_VLD1d16TPseudoWB_fixed_VLD1d16TPseudoWB_register_VLD1d32TPseudo_VLD1d32TPseudoWB_fixed_VLD1d32TPseudoWB_register_VLD1d8TPseudo_VLD1d8TPseudoWB_fixed_VLD1d8TPseudoWB_register_VLD1q16HighTPseudo_VLD1q16HighTPseudo_UPD_VLD1q16LowTPseudo_UPD_VLD1q32HighTPseudo_VLD1q32HighTPseudo_UPD_VLD1q32LowTPseudo_UPD_VLD1q64HighTPseudo_VLD1q64HighTPseudo_UPD_VLD1q64LowTPseudo_UPD_VLD1q8HighTPseudo_VLD1q8HighTPseudo_UPD_VLD1q8LowTPseudo_UPD = 1048, |
| 5574 | VLD2DUPq16EvenPseudo_VLD2DUPq16OddPseudo_VLD2DUPq16OddPseudoWB_fixed_VLD2DUPq16OddPseudoWB_register_VLD2DUPq32EvenPseudo_VLD2DUPq32OddPseudo_VLD2DUPq32OddPseudoWB_fixed_VLD2DUPq32OddPseudoWB_register_VLD2DUPq8EvenPseudo_VLD2DUPq8OddPseudo_VLD2DUPq8OddPseudoWB_fixed_VLD2DUPq8OddPseudoWB_register = 1049, |
| 5575 | VLD3DUPq16EvenPseudo_VLD3DUPq16OddPseudo_VLD3DUPq32EvenPseudo_VLD3DUPq32OddPseudo_VLD3DUPq8EvenPseudo_VLD3DUPq8OddPseudo = 1050, |
| 5576 | VLD3DUPq16OddPseudo_UPD_VLD3DUPq32OddPseudo_UPD_VLD3DUPq8OddPseudo_UPD = 1051, |
| 5577 | VLD4DUPq16EvenPseudo_VLD4DUPq16OddPseudo_VLD4DUPq32EvenPseudo_VLD4DUPq32OddPseudo_VLD4DUPq8EvenPseudo_VLD4DUPq8OddPseudo = 1052, |
| 5578 | VLD4DUPq16OddPseudo_UPD_VLD4DUPq32OddPseudo_UPD_VLD4DUPq8OddPseudo_UPD = 1053, |
| 5579 | VST1d16TPseudo_VST1d32TPseudo_VST1d8TPseudo_VST1q16HighTPseudo_VST1q16HighTPseudo_UPD_VST1q16LowTPseudo_UPD_VST1q32HighTPseudo_VST1q32HighTPseudo_UPD_VST1q32LowTPseudo_UPD_VST1q64HighTPseudo_VST1q64HighTPseudo_UPD_VST1q64LowTPseudo_UPD_VST1q8HighTPseudo_VST1q8HighTPseudo_UPD_VST1q8LowTPseudo_UPD = 1054, |
| 5580 | VST1d16TPseudoWB_fixed_VST1d16TPseudoWB_register_VST1d32TPseudoWB_fixed_VST1d32TPseudoWB_register_VST1d8TPseudoWB_fixed_VST1d8TPseudoWB_register = 1055, |
| 5581 | VST1q16HighQPseudo_VST1q16HighQPseudo_UPD_VST1q16LowQPseudo_UPD_VST1q32HighQPseudo_VST1q32HighQPseudo_UPD_VST1q32LowQPseudo_UPD_VST1q64HighQPseudo_VST1q64HighQPseudo_UPD_VST1q64LowQPseudo_UPD_VST1q8HighQPseudo_VST1q8HighQPseudo_UPD_VST1q8LowQPseudo_UPD = 1056, |
| 5582 | VMOVD0 = 1057, |
| 5583 | t2CPS1p_t2CPS2p_t2CPS3p_t2SG_t2TT_t2TTA_t2TTAT_t2TTT = 1058, |
| 5584 | t2DBG = 1059, |
| 5585 | t2SUBS_PC_LR = 1060, |
| 5586 | COPY_TO_REGCLASS = 1061, |
| 5587 | COPY_STRUCT_BYVAL_I32 = 1062, |
| 5588 | t2CSEL_t2CSINC_t2CSINV_t2CSNEG = 1063, |
| 5589 | t2ADDrr_t2ADDSrr_t2SBCrr = 1064, |
| 5590 | t2ASRri_t2LSLri_t2LSRri = 1065, |
| 5591 | t2ASRrr_t2LSLrr_t2LSRrr_t2RORrr = 1066, |
| 5592 | t2CMNzrr = 1067, |
| 5593 | t2CMPri = 1068, |
| 5594 | t2CMPrr = 1069, |
| 5595 | t2ORRrr = 1070, |
| 5596 | t2REV_t2REV16_t2REVSH = 1071, |
| 5597 | t2RSBri_t2RSBSri = 1072, |
| 5598 | t2RSBrr_t2SUBSrr_t2SUBrr = 1073, |
| 5599 | t2TEQrr_t2TSTrr = 1074, |
| 5600 | t2STRi12 = 1075, |
| 5601 | t2STRBi12_t2STRHi12 = 1076, |
| 5602 | t2STMIA_UPD_t2STMDB_UPD = 1077, |
| 5603 | t2SETPAN_tHLT_tSETEND = 1078, |
| 5604 | tADC_tADDhirr_tADDrSP_tADDrr_tADDspr_tPICADD_tSBC_tSUBrr = 1079, |
| 5605 | tADDrSPi_tADDspi_tADR_tRSB_tSUBspi = 1080, |
| 5606 | tAND_tBIC_tEOR_tORR = 1081, |
| 5607 | tASRri_tLSLri_tLSRri = 1082, |
| 5608 | tCBNZ_tCBZ = 1083, |
| 5609 | tCMNz_tCMPhir_tCMPr = 1084, |
| 5610 | tCMPi8 = 1085, |
| 5611 | tCPS_tHINT = 1086, |
| 5612 | tMOVSr = 1087, |
| 5613 | tSTRBi_tSTRHi = 1088, |
| 5614 | tSTRi_tSTRspi = 1089, |
| 5615 | tSVC_tTRAP = 1090, |
| 5616 | tTST = 1091, |
| 5617 | tUDF = 1092, |
| 5618 | tB_tBX_tBXNS_tBcc = 1093, |
| 5619 | tBLXNSr_tBLXr = 1094, |
| 5620 | t2DMB_t2DSB_t2ISB = 1095, |
| 5621 | t2MCR_t2MCR2_t2MCRR_t2MCRR2_t2MRC_t2MRC2 = 1096, |
| 5622 | t2MOVSsi = 1097, |
| 5623 | t2MOVSsr = 1098, |
| 5624 | t2MUL = 1099, |
| 5625 | t2SMMLA_t2SMMLAR_t2SMMLS_t2SMMLSR = 1100, |
| 5626 | t2UXTAB_t2UXTAH = 1101, |
| 5627 | t2UXTAB16 = 1102, |
| 5628 | MVE_SQRSHR_MVE_SQSHL_MVE_SRSHR_MVE_UQRSHL_MVE_UQSHL_MVE_URSHR = 1103, |
| 5629 | MVE_ASRLi_MVE_ASRLr_MVE_LSLLi_MVE_LSLLr_MVE_LSRL_MVE_SQRSHRL_MVE_SQSHLL_MVE_SRSHRL_MVE_UQRSHLL_MVE_UQSHLL_MVE_URSHRL = 1104, |
| 5630 | t2CLRM = 1105, |
| 5631 | t2LDRBi12_t2LDRHi12 = 1106, |
| 5632 | t2LDRi12 = 1107, |
| 5633 | t2LDMDB_t2LDMIA = 1108, |
| 5634 | t2LDMDB_UPD_t2LDMIA_UPD = 1109, |
| 5635 | tADDi3_tADDi8_tSUBi3_tSUBi8 = 1110, |
| 5636 | t2ADDSri_t2ADDri = 1111, |
| 5637 | t2SUBSri_t2SUBri = 1112, |
| 5638 | t2LoopDec = 1113, |
| 5639 | MVE_VLDRBS16_MVE_VLDRBS32_MVE_VLDRBU16_MVE_VLDRBU32_MVE_VLDRBU8_MVE_VLDRHS32_MVE_VLDRHU16_MVE_VLDRHU32_MVE_VLDRWU32 = 1114, |
| 5640 | MVE_VLDRBS16_post_MVE_VLDRBS16_pre_MVE_VLDRBS32_post_MVE_VLDRBS32_pre_MVE_VLDRBU16_post_MVE_VLDRBU16_pre_MVE_VLDRBU32_post_MVE_VLDRBU32_pre_MVE_VLDRBU8_post_MVE_VLDRBU8_pre_MVE_VLDRHS32_post_MVE_VLDRHS32_pre_MVE_VLDRHU16_post_MVE_VLDRHU16_pre_MVE_VLDRHU32_post_MVE_VLDRHU32_pre_MVE_VLDRWU32_post_MVE_VLDRWU32_pre = 1115, |
| 5641 | MVE_VLDRBS16_rq_MVE_VLDRBS32_rq_MVE_VLDRBU16_rq_MVE_VLDRBU32_rq_MVE_VLDRBU8_rq_MVE_VLDRDU64_rq_MVE_VLDRDU64_rq_u_MVE_VLDRHS32_rq_MVE_VLDRHS32_rq_u_MVE_VLDRHU16_rq_MVE_VLDRHU16_rq_u_MVE_VLDRHU32_rq_MVE_VLDRHU32_rq_u_MVE_VLDRWU32_rq_MVE_VLDRWU32_rq_u = 1116, |
| 5642 | MVE_VLDRDU64_qi_MVE_VLDRWU32_qi = 1117, |
| 5643 | MVE_VLDRDU64_qi_pre_MVE_VLDRWU32_qi_pre = 1118, |
| 5644 | MVE_VLD20_16_MVE_VLD20_32_MVE_VLD20_8_MVE_VLD21_16_MVE_VLD21_32_MVE_VLD21_8_MVE_VLD40_16_MVE_VLD40_32_MVE_VLD40_8_MVE_VLD41_16_MVE_VLD41_32_MVE_VLD41_8_MVE_VLD42_16_MVE_VLD42_32_MVE_VLD42_8_MVE_VLD43_16_MVE_VLD43_32_MVE_VLD43_8 = 1119, |
| 5645 | MVE_VLD20_16_wb_MVE_VLD20_32_wb_MVE_VLD20_8_wb_MVE_VLD21_16_wb_MVE_VLD21_32_wb_MVE_VLD21_8_wb_MVE_VLD40_16_wb_MVE_VLD40_32_wb_MVE_VLD40_8_wb_MVE_VLD41_16_wb_MVE_VLD41_32_wb_MVE_VLD41_8_wb_MVE_VLD42_16_wb_MVE_VLD42_32_wb_MVE_VLD42_8_wb_MVE_VLD43_16_wb_MVE_VLD43_32_wb_MVE_VLD43_8_wb = 1120, |
| 5646 | MVE_VSTRB16_MVE_VSTRB32_MVE_VSTRBU8_MVE_VSTRH32_MVE_VSTRHU16_MVE_VSTRWU32 = 1121, |
| 5647 | MVE_VSTRB16_post_MVE_VSTRB16_pre_MVE_VSTRB32_post_MVE_VSTRB32_pre_MVE_VSTRBU8_post_MVE_VSTRBU8_pre_MVE_VSTRH32_post_MVE_VSTRH32_pre_MVE_VSTRHU16_post_MVE_VSTRHU16_pre_MVE_VSTRWU32_post_MVE_VSTRWU32_pre = 1122, |
| 5648 | MVE_VSTRB16_rq_MVE_VSTRB32_rq_MVE_VSTRB8_rq_MVE_VSTRD64_rq_MVE_VSTRD64_rq_u_MVE_VSTRH16_rq_MVE_VSTRH16_rq_u_MVE_VSTRH32_rq_MVE_VSTRH32_rq_u_MVE_VSTRW32_rq_MVE_VSTRW32_rq_u = 1123, |
| 5649 | MVE_VSTRD64_qi_MVE_VSTRD64_qi_pre_MVE_VSTRW32_qi_MVE_VSTRW32_qi_pre = 1124, |
| 5650 | MVE_VST20_16_MVE_VST20_16_wb_MVE_VST20_32_MVE_VST20_32_wb_MVE_VST20_8_MVE_VST20_8_wb_MVE_VST21_16_MVE_VST21_16_wb_MVE_VST21_32_MVE_VST21_32_wb_MVE_VST21_8_MVE_VST21_8_wb_MVE_VST40_16_MVE_VST40_16_wb_MVE_VST40_32_MVE_VST40_32_wb_MVE_VST40_8_MVE_VST40_8_wb_MVE_VST41_16_MVE_VST41_16_wb_MVE_VST41_32_MVE_VST41_32_wb_MVE_VST41_8_MVE_VST41_8_wb_MVE_VST42_16_MVE_VST42_16_wb_MVE_VST42_32_MVE_VST42_32_wb_MVE_VST42_8_MVE_VST42_8_wb_MVE_VST43_16_MVE_VST43_16_wb_MVE_VST43_32_MVE_VST43_32_wb_MVE_VST43_8_MVE_VST43_8_wb = 1125, |
| 5651 | MVE_VABAVs16_MVE_VABAVs32_MVE_VABAVs8_MVE_VABAVu16_MVE_VABAVu32_MVE_VABAVu8 = 1126, |
| 5652 | MVE_VABDs16_MVE_VABDs32_MVE_VABDs8_MVE_VABDu16_MVE_VABDu32_MVE_VABDu8 = 1127, |
| 5653 | MVE_VABSs16_MVE_VABSs32_MVE_VABSs8 = 1128, |
| 5654 | MVE_VADC_MVE_VADCI = 1129, |
| 5655 | MVE_VADD_qr_i16_MVE_VADD_qr_i32_MVE_VADD_qr_i8_MVE_VADDi16_MVE_VADDi32_MVE_VADDi8 = 1130, |
| 5656 | MVE_VAND = 1131, |
| 5657 | MVE_VBIC_MVE_VBICimmi16_MVE_VBICimmi32 = 1132, |
| 5658 | MVE_VBRSR16_MVE_VBRSR32_MVE_VBRSR8 = 1133, |
| 5659 | MVE_VCADDi16_MVE_VCADDi32_MVE_VCADDi8 = 1134, |
| 5660 | MVE_VCLSs16_MVE_VCLSs32_MVE_VCLSs8 = 1135, |
| 5661 | MVE_VCLZs16_MVE_VCLZs32_MVE_VCLZs8 = 1136, |
| 5662 | MVE_VDDUPu16_MVE_VDDUPu32_MVE_VDDUPu8_MVE_VDUP16_MVE_VDUP32_MVE_VDUP8_MVE_VDWDUPu16_MVE_VDWDUPu32_MVE_VDWDUPu8_MVE_VIDUPu16_MVE_VIDUPu32_MVE_VIDUPu8_MVE_VIWDUPu16_MVE_VIWDUPu32_MVE_VIWDUPu8 = 1137, |
| 5663 | MVE_VEOR = 1138, |
| 5664 | MVE_VHADD_qr_s16_MVE_VHADD_qr_s32_MVE_VHADD_qr_s8_MVE_VHADD_qr_u16_MVE_VHADD_qr_u32_MVE_VHADD_qr_u8_MVE_VHADDs16_MVE_VHADDs32_MVE_VHADDs8_MVE_VHADDu16_MVE_VHADDu32_MVE_VHADDu8 = 1139, |
| 5665 | MVE_VHCADDs16_MVE_VHCADDs32_MVE_VHCADDs8 = 1140, |
| 5666 | MVE_VHSUB_qr_s16_MVE_VHSUB_qr_s32_MVE_VHSUB_qr_s8_MVE_VHSUB_qr_u16_MVE_VHSUB_qr_u32_MVE_VHSUB_qr_u8_MVE_VHSUBs16_MVE_VHSUBs32_MVE_VHSUBs8_MVE_VHSUBu16_MVE_VHSUBu32_MVE_VHSUBu8 = 1141, |
| 5667 | MVE_VMAXAs16_MVE_VMAXAs32_MVE_VMAXAs8_MVE_VMAXs16_MVE_VMAXs32_MVE_VMAXs8_MVE_VMAXu16_MVE_VMAXu32_MVE_VMAXu8_MVE_VMINAs16_MVE_VMINAs32_MVE_VMINAs8_MVE_VMINs16_MVE_VMINs32_MVE_VMINs8_MVE_VMINu16_MVE_VMINu32_MVE_VMINu8 = 1142, |
| 5668 | MVE_VMAXAVs8_MVE_VMAXVs8_MVE_VMAXVu8_MVE_VMINAVs8_MVE_VMINVs8_MVE_VMINVu8 = 1143, |
| 5669 | MVE_VMAXAVs16_MVE_VMAXVs16_MVE_VMAXVu16_MVE_VMINAVs16_MVE_VMINVs16_MVE_VMINVu16 = 1144, |
| 5670 | MVE_VMAXAVs32_MVE_VMAXVs32_MVE_VMAXVu32_MVE_VMINAVs32_MVE_VMINVs32_MVE_VMINVu32 = 1145, |
| 5671 | MVE_VMOVNi16bh_MVE_VMOVNi16th_MVE_VMOVNi32bh_MVE_VMOVNi32th = 1146, |
| 5672 | MVE_VMOVLs16bh_MVE_VMOVLs16th_MVE_VMOVLs8bh_MVE_VMOVLs8th_MVE_VMOVLu16bh_MVE_VMOVLu16th_MVE_VMOVLu8bh_MVE_VMOVLu8th = 1147, |
| 5673 | MVE_VMULLBp16_MVE_VMULLBp8_MVE_VMULLTp16_MVE_VMULLTp8 = 1148, |
| 5674 | MVE_VMVN_MVE_VMVNimmi16_MVE_VMVNimmi32 = 1149, |
| 5675 | MVE_VNEGs16_MVE_VNEGs32_MVE_VNEGs8 = 1150, |
| 5676 | MVE_VORN = 1151, |
| 5677 | MVE_VORR_MVE_VORRimmi16_MVE_VORRimmi32 = 1152, |
| 5678 | MVE_VPSEL = 1153, |
| 5679 | MQPRCopy = 1154, |
| 5680 | MVE_VQABSs16_MVE_VQABSs32_MVE_VQABSs8 = 1155, |
| 5681 | MVE_VQADD_qr_s16_MVE_VQADD_qr_s32_MVE_VQADD_qr_s8_MVE_VQADD_qr_u16_MVE_VQADD_qr_u32_MVE_VQADD_qr_u8_MVE_VQADDs16_MVE_VQADDs32_MVE_VQADDs8_MVE_VQADDu16_MVE_VQADDu32_MVE_VQADDu8 = 1156, |
| 5682 | MVE_VQMOVNs16bh_MVE_VQMOVNs16th_MVE_VQMOVNs32bh_MVE_VQMOVNs32th_MVE_VQMOVNu16bh_MVE_VQMOVNu16th_MVE_VQMOVNu32bh_MVE_VQMOVNu32th_MVE_VQMOVUNs16bh_MVE_VQMOVUNs16th_MVE_VQMOVUNs32bh_MVE_VQMOVUNs32th = 1157, |
| 5683 | MVE_VQNEGs16_MVE_VQNEGs32_MVE_VQNEGs8 = 1158, |
| 5684 | MVE_VSHLC_MVE_VSHLL_imms16bh_MVE_VSHLL_imms16th_MVE_VSHLL_imms8bh_MVE_VSHLL_imms8th_MVE_VSHLL_immu16bh_MVE_VSHLL_immu16th_MVE_VSHLL_immu8bh_MVE_VSHLL_immu8th_MVE_VSHLL_lws16bh_MVE_VSHLL_lws16th_MVE_VSHLL_lws8bh_MVE_VSHLL_lws8th_MVE_VSHLL_lwu16bh_MVE_VSHLL_lwu16th_MVE_VSHLL_lwu8bh_MVE_VSHLL_lwu8th_MVE_VSHL_by_vecs16_MVE_VSHL_by_vecs32_MVE_VSHL_by_vecs8_MVE_VSHL_by_vecu16_MVE_VSHL_by_vecu32_MVE_VSHL_by_vecu8_MVE_VSHL_immi16_MVE_VSHL_immi32_MVE_VSHL_immi8_MVE_VSHL_qrs16_MVE_VSHL_qrs32_MVE_VSHL_qrs8_MVE_VSHL_qru16_MVE_VSHL_qru32_MVE_VSHL_qru8 = 1159, |
| 5685 | MVE_VQSHLU_imms16_MVE_VQSHLU_imms32_MVE_VQSHLU_imms8_MVE_VQSHL_by_vecs16_MVE_VQSHL_by_vecs32_MVE_VQSHL_by_vecs8_MVE_VQSHL_by_vecu16_MVE_VQSHL_by_vecu32_MVE_VQSHL_by_vecu8_MVE_VQSHL_qrs16_MVE_VQSHL_qrs32_MVE_VQSHL_qrs8_MVE_VQSHL_qru16_MVE_VQSHL_qru32_MVE_VQSHL_qru8_MVE_VQSHLimms16_MVE_VQSHLimms32_MVE_VQSHLimms8_MVE_VQSHLimmu16_MVE_VQSHLimmu32_MVE_VQSHLimmu8_MVE_VRSHL_by_vecs16_MVE_VRSHL_by_vecs32_MVE_VRSHL_by_vecs8_MVE_VRSHL_by_vecu16_MVE_VRSHL_by_vecu32_MVE_VRSHL_by_vecu8_MVE_VRSHL_qrs16_MVE_VRSHL_qrs32_MVE_VRSHL_qrs8_MVE_VRSHL_qru16_MVE_VRSHL_qru32_MVE_VRSHL_qru8 = 1160, |
| 5686 | MVE_VQRSHL_by_vecs16_MVE_VQRSHL_by_vecs32_MVE_VQRSHL_by_vecs8_MVE_VQRSHL_by_vecu16_MVE_VQRSHL_by_vecu32_MVE_VQRSHL_by_vecu8_MVE_VQRSHL_qrs16_MVE_VQRSHL_qrs32_MVE_VQRSHL_qrs8_MVE_VQRSHL_qru16_MVE_VQRSHL_qru32_MVE_VQRSHL_qru8 = 1161, |
| 5687 | MVE_VQRSHRNbhs16_MVE_VQRSHRNbhs32_MVE_VQRSHRNbhu16_MVE_VQRSHRNbhu32_MVE_VQRSHRNths16_MVE_VQRSHRNths32_MVE_VQRSHRNthu16_MVE_VQRSHRNthu32_MVE_VQRSHRUNs16bh_MVE_VQRSHRUNs16th_MVE_VQRSHRUNs32bh_MVE_VQRSHRUNs32th_MVE_VQSHRNbhs16_MVE_VQSHRNbhs32_MVE_VQSHRNbhu16_MVE_VQSHRNbhu32_MVE_VQSHRNths16_MVE_VQSHRNths32_MVE_VQSHRNthu16_MVE_VQSHRNthu32_MVE_VQSHRUNs16bh_MVE_VQSHRUNs16th_MVE_VQSHRUNs32bh_MVE_VQSHRUNs32th_MVE_VRSHRNi16bh_MVE_VRSHRNi16th_MVE_VRSHRNi32bh_MVE_VRSHRNi32th_MVE_VSHRNi16bh_MVE_VSHRNi16th_MVE_VSHRNi32bh_MVE_VSHRNi32th = 1162, |
| 5688 | MVE_VSHR_imms16_MVE_VSHR_imms32_MVE_VSHR_imms8_MVE_VSHR_immu16_MVE_VSHR_immu32_MVE_VSHR_immu8 = 1163, |
| 5689 | MVE_VRSHR_imms16_MVE_VRSHR_imms32_MVE_VRSHR_imms8_MVE_VRSHR_immu16_MVE_VRSHR_immu32_MVE_VRSHR_immu8 = 1164, |
| 5690 | MVE_VQSUB_qr_s16_MVE_VQSUB_qr_s32_MVE_VQSUB_qr_s8_MVE_VQSUB_qr_u16_MVE_VQSUB_qr_u32_MVE_VQSUB_qr_u8_MVE_VQSUBs16_MVE_VQSUBs32_MVE_VQSUBs8_MVE_VQSUBu16_MVE_VQSUBu32_MVE_VQSUBu8 = 1165, |
| 5691 | MVE_VREV16_8_MVE_VREV32_16_MVE_VREV32_8_MVE_VREV64_16_MVE_VREV64_32_MVE_VREV64_8 = 1166, |
| 5692 | MVE_VRHADDs16_MVE_VRHADDs32_MVE_VRHADDs8_MVE_VRHADDu16_MVE_VRHADDu32_MVE_VRHADDu8 = 1167, |
| 5693 | MVE_VSBC_MVE_VSBCI = 1168, |
| 5694 | MVE_VSLIimm16_MVE_VSLIimm32_MVE_VSLIimm8 = 1169, |
| 5695 | MVE_VSRIimm16_MVE_VSRIimm32_MVE_VSRIimm8 = 1170, |
| 5696 | MVE_VSUB_qr_i16_MVE_VSUB_qr_i32_MVE_VSUB_qr_i8_MVE_VSUBi16_MVE_VSUBi32_MVE_VSUBi8 = 1171, |
| 5697 | MVE_VABDf16_MVE_VABDf32 = 1172, |
| 5698 | MVE_VABSf16_MVE_VABSf32 = 1173, |
| 5699 | MVE_VADDf16_MVE_VADDf32 = 1174, |
| 5700 | MVE_VADD_qr_f16_MVE_VADD_qr_f32 = 1175, |
| 5701 | MVE_VADDLVs32acc_MVE_VADDLVs32no_acc_MVE_VADDLVu32acc_MVE_VADDLVu32no_acc = 1176, |
| 5702 | MVE_VADDVs16acc_MVE_VADDVs16no_acc_MVE_VADDVs32acc_MVE_VADDVs32no_acc_MVE_VADDVs8acc_MVE_VADDVs8no_acc_MVE_VADDVu16acc_MVE_VADDVu16no_acc_MVE_VADDVu32acc_MVE_VADDVu32no_acc_MVE_VADDVu8acc_MVE_VADDVu8no_acc = 1177, |
| 5703 | MVE_VCADDf16_MVE_VCADDf32 = 1178, |
| 5704 | MVE_VCMLAf16_MVE_VCMLAf32 = 1179, |
| 5705 | MVE_VCMULf16_MVE_VCMULf32 = 1180, |
| 5706 | MVE_VCMPi16_MVE_VCMPi16r_MVE_VCMPi32_MVE_VCMPi32r_MVE_VCMPi8_MVE_VCMPi8r_MVE_VCMPs16_MVE_VCMPs16r_MVE_VCMPs32_MVE_VCMPs32r_MVE_VCMPs8_MVE_VCMPs8r_MVE_VCMPu16_MVE_VCMPu16r_MVE_VCMPu32_MVE_VCMPu32r_MVE_VCMPu8_MVE_VCMPu8r_MVE_VPTv16i8_MVE_VPTv16i8r_MVE_VPTv16s8_MVE_VPTv16s8r_MVE_VPTv16u8_MVE_VPTv16u8r_MVE_VPTv4i32_MVE_VPTv4i32r_MVE_VPTv4s32_MVE_VPTv4s32r_MVE_VPTv4u32_MVE_VPTv4u32r_MVE_VPTv8i16_MVE_VPTv8i16r_MVE_VPTv8s16_MVE_VPTv8s16r_MVE_VPTv8u16_MVE_VPTv8u16r = 1181, |
| 5707 | MVE_VCMPf16_MVE_VCMPf16r_MVE_VCMPf32_MVE_VCMPf32r_MVE_VPTv4f32_MVE_VPTv4f32r_MVE_VPTv8f16_MVE_VPTv8f16r = 1182, |
| 5708 | MVE_VCVTf16s16_fix_MVE_VCVTf16s16n_MVE_VCVTf16u16_fix_MVE_VCVTf16u16n = 1183, |
| 5709 | MVE_VCVTf32s32_fix_MVE_VCVTf32s32n_MVE_VCVTf32u32_fix_MVE_VCVTf32u32n = 1184, |
| 5710 | MVE_VCVTs16f16_fix_MVE_VCVTs16f16a_MVE_VCVTs16f16m_MVE_VCVTs16f16n_MVE_VCVTs16f16p_MVE_VCVTs16f16z_MVE_VCVTu16f16_fix_MVE_VCVTu16f16a_MVE_VCVTu16f16m_MVE_VCVTu16f16n_MVE_VCVTu16f16p_MVE_VCVTu16f16z = 1185, |
| 5711 | MVE_VCVTs32f32_fix_MVE_VCVTs32f32a_MVE_VCVTs32f32m_MVE_VCVTs32f32n_MVE_VCVTs32f32p_MVE_VCVTs32f32z_MVE_VCVTu32f32_fix_MVE_VCVTu32f32a_MVE_VCVTu32f32m_MVE_VCVTu32f32n_MVE_VCVTu32f32p_MVE_VCVTu32f32z = 1186, |
| 5712 | MVE_VCVTf16f32bh_MVE_VCVTf16f32th = 1187, |
| 5713 | MVE_VCVTf32f16bh_MVE_VCVTf32f16th = 1188, |
| 5714 | MVE_VFMA_qr_Sf16_MVE_VFMA_qr_Sf32_MVE_VFMA_qr_f16_MVE_VFMA_qr_f32_MVE_VFMAf16_MVE_VFMAf32_MVE_VFMSf16_MVE_VFMSf32 = 1189, |
| 5715 | MVE_VMAXNMAVf16_MVE_VMAXNMAVf32_MVE_VMAXNMAf16_MVE_VMAXNMAf32_MVE_VMAXNMVf16_MVE_VMAXNMVf32_MVE_VMAXNMf16_MVE_VMAXNMf32_MVE_VMINNMAVf16_MVE_VMINNMAVf32_MVE_VMINNMAf16_MVE_VMINNMAf32_MVE_VMINNMVf16_MVE_VMINNMVf32_MVE_VMINNMf16_MVE_VMINNMf32 = 1190, |
| 5716 | MVE_VMOV_from_lane_32_MVE_VMOV_from_lane_s16_MVE_VMOV_from_lane_s8_MVE_VMOV_from_lane_u16_MVE_VMOV_from_lane_u8 = 1191, |
| 5717 | MVE_VMOV_rr_q = 1192, |
| 5718 | MVE_VMOVimmf32_MVE_VMOVimmi16_MVE_VMOVimmi32_MVE_VMOVimmi64_MVE_VMOVimmi8 = 1193, |
| 5719 | MVE_VMUL_qr_f16_MVE_VMUL_qr_f32_MVE_VMUL_qr_i16_MVE_VMUL_qr_i32_MVE_VMUL_qr_i8_MVE_VMULf16_MVE_VMULf32_MVE_VMULi16_MVE_VMULi32_MVE_VMULi8 = 1194, |
| 5720 | MVE_VMULHs16_MVE_VMULHs32_MVE_VMULHs8_MVE_VMULHu16_MVE_VMULHu32_MVE_VMULHu8_MVE_VQDMULH_qr_s16_MVE_VQDMULH_qr_s32_MVE_VQDMULH_qr_s8_MVE_VQDMULHi16_MVE_VQDMULHi32_MVE_VQDMULHi8_MVE_VQRDMULH_qr_s16_MVE_VQRDMULH_qr_s32_MVE_VQRDMULH_qr_s8_MVE_VQRDMULHi16_MVE_VQRDMULHi32_MVE_VQRDMULHi8_MVE_VRMULHs16_MVE_VRMULHs32_MVE_VRMULHs8_MVE_VRMULHu16_MVE_VRMULHu32_MVE_VRMULHu8 = 1195, |
| 5721 | MVE_VMULLBs16_MVE_VMULLBs32_MVE_VMULLBs8_MVE_VMULLBu16_MVE_VMULLBu32_MVE_VMULLBu8_MVE_VMULLTs16_MVE_VMULLTs32_MVE_VMULLTs8_MVE_VMULLTu16_MVE_VMULLTu32_MVE_VMULLTu8_MVE_VQDMULLs16bh_MVE_VQDMULLs16th_MVE_VQDMULLs32bh_MVE_VQDMULLs32th = 1196, |
| 5722 | MVE_VQDMULL_qr_s16bh_MVE_VQDMULL_qr_s16th_MVE_VQDMULL_qr_s32bh_MVE_VQDMULL_qr_s32th = 1197, |
| 5723 | MVE_VMLADAVas16_MVE_VMLADAVas32_MVE_VMLADAVas8_MVE_VMLADAVau16_MVE_VMLADAVau32_MVE_VMLADAVau8_MVE_VMLADAVaxs16_MVE_VMLADAVaxs32_MVE_VMLADAVaxs8_MVE_VMLADAVs16_MVE_VMLADAVs32_MVE_VMLADAVs8_MVE_VMLADAVu16_MVE_VMLADAVu32_MVE_VMLADAVu8_MVE_VMLADAVxs16_MVE_VMLADAVxs32_MVE_VMLADAVxs8_MVE_VMLAS_qr_i16_MVE_VMLAS_qr_i32_MVE_VMLAS_qr_i8_MVE_VMLA_qr_i16_MVE_VMLA_qr_i32_MVE_VMLA_qr_i8_MVE_VMLSDAVas16_MVE_VMLSDAVas32_MVE_VMLSDAVas8_MVE_VMLSDAVaxs16_MVE_VMLSDAVaxs32_MVE_VMLSDAVaxs8_MVE_VMLSDAVs16_MVE_VMLSDAVs32_MVE_VMLSDAVs8_MVE_VMLSDAVxs16_MVE_VMLSDAVxs32_MVE_VMLSDAVxs8_MVE_VQDMLADHXs16_MVE_VQDMLADHXs32_MVE_VQDMLADHXs8_MVE_VQDMLADHs16_MVE_VQDMLADHs32_MVE_VQDMLADHs8_MVE_VQDMLAH_qrs16_MVE_VQDMLAH_qrs32_MVE_VQDMLAH_qrs8_MVE_VQDMLASH_qrs16_MVE_VQDMLASH_qrs32_MVE_VQDMLASH_qrs8_MVE_VQDMLSDHXs16_MVE_VQDMLSDHXs32_MVE_VQDMLSDHXs8_MVE_VQDMLSDHs16_MVE_VQDMLSDHs32_MVE_VQDMLSDHs8_MVE_VQRDMLADHXs16_MVE_VQRDMLADHXs32_MVE_VQRDMLADHXs8_MVE_VQRDMLADHs16_MVE_VQRDMLADHs32_MVE_VQRDMLADHs8_MVE_VQRDMLAH_qrs16_MVE_VQRDMLAH_qrs32_MVE_VQRDMLAH_qrs8_MVE_VQRDMLASH_qrs16_MVE_VQRDMLASH_qrs32_MVE_VQRDMLASH_qrs8_MVE_VQRDMLSDHXs16_MVE_VQRDMLSDHXs32_MVE_VQRDMLSDHXs8_MVE_VQRDMLSDHs16_MVE_VQRDMLSDHs32_MVE_VQRDMLSDHs8 = 1198, |
| 5724 | MVE_VMLALDAVas16_MVE_VMLALDAVas32_MVE_VMLALDAVau16_MVE_VMLALDAVau32_MVE_VMLALDAVaxs16_MVE_VMLALDAVaxs32_MVE_VMLALDAVs16_MVE_VMLALDAVs32_MVE_VMLALDAVu16_MVE_VMLALDAVu32_MVE_VMLALDAVxs16_MVE_VMLALDAVxs32_MVE_VMLSLDAVas16_MVE_VMLSLDAVas32_MVE_VMLSLDAVaxs16_MVE_VMLSLDAVaxs32_MVE_VMLSLDAVs16_MVE_VMLSLDAVs32_MVE_VMLSLDAVxs16_MVE_VMLSLDAVxs32_MVE_VRMLALDAVHas32_MVE_VRMLALDAVHau32_MVE_VRMLALDAVHaxs32_MVE_VRMLALDAVHs32_MVE_VRMLALDAVHu32_MVE_VRMLALDAVHxs32_MVE_VRMLSLDAVHas32_MVE_VRMLSLDAVHaxs32_MVE_VRMLSLDAVHs32_MVE_VRMLSLDAVHxs32 = 1199, |
| 5725 | MVE_VNEGf16_MVE_VNEGf32 = 1200, |
| 5726 | MVE_VRINTf16A_MVE_VRINTf16M_MVE_VRINTf16N_MVE_VRINTf16P_MVE_VRINTf16X_MVE_VRINTf16Z_MVE_VRINTf32A_MVE_VRINTf32M_MVE_VRINTf32N_MVE_VRINTf32P_MVE_VRINTf32X_MVE_VRINTf32Z = 1201, |
| 5727 | MVE_VSUBf16_MVE_VSUBf32 = 1202, |
| 5728 | MVE_VSUB_qr_f16_MVE_VSUB_qr_f32 = 1203, |
| 5729 | MVE_VMOV_to_lane_16_MVE_VMOV_to_lane_32_MVE_VMOV_to_lane_8_MVE_VMOV_q_rr = 1204, |
| 5730 | MVE_VCTP16_MVE_VCTP32_MVE_VCTP64_MVE_VCTP8 = 1205, |
| 5731 | MVE_VPNOT = 1206, |
| 5732 | MVE_VPST = 1207, |
| 5733 | VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS = 1208, |
| 5734 | VDIVH = 1209, |
| 5735 | VFMAH_VFMSH = 1210, |
| 5736 | VFP_VMAXNMD_VFP_VMAXNMH_VFP_VMAXNMS_VFP_VMINNMD_VFP_VMINNMH_VFP_VMINNMS = 1211, |
| 5737 | VMOVH = 1212, |
| 5738 | VMOVHR = 1213, |
| 5739 | VMOVD = 1214, |
| 5740 | VMOVS = 1215, |
| 5741 | VMOVRH = 1216, |
| 5742 | tSVC = 1217, |
| 5743 | t2HVC = 1218, |
| 5744 | t2SMC_ERET = 1219, |
| 5745 | tHINT = 1220, |
| 5746 | BUNDLE = 1221, |
| 5747 | t2LDRBpcrel_t2LDRHpcrel = 1222, |
| 5748 | t2LDRBpci_t2LDRHpci = 1223, |
| 5749 | t2LDRSBpci_t2LDRSHpci = 1224, |
| 5750 | t2LDRH_POST_imm = 1225, |
| 5751 | t2LDRH_PRE_imm = 1226, |
| 5752 | t2LDREX = 1227, |
| 5753 | t2LDREXB_t2LDREXH = 1228, |
| 5754 | t2STREX_t2STREXB_t2STREXH = 1229, |
| 5755 | t2LDRpci = 1230, |
| 5756 | t2PLDpci_t2PLIpci = 1231, |
| 5757 | tLDRpci = 1232, |
| 5758 | t2PLDWi12_t2PLDWi8_t2PLDi12_t2PLDi8_t2PLIi12_t2PLIi8 = 1233, |
| 5759 | t2PLDs_t2PLIs = 1234, |
| 5760 | t2TBB_JT_t2TBH_JT = 1235, |
| 5761 | t2TBB_t2TBH = 1236, |
| 5762 | t2RSBSrs_t2SUBrs = 1237, |
| 5763 | t2SUBSrs = 1238, |
| 5764 | t2BICrs_t2EORrs_t2ORRrs = 1239, |
| 5765 | t2ORNrs = 1240, |
| 5766 | t2CMNzrs = 1241, |
| 5767 | t2CMPrs = 1242, |
| 5768 | t2TEQrs_t2TSTrs = 1243, |
| 5769 | t2RRX = 1244, |
| 5770 | tLSLSri = 1245, |
| 5771 | t2CLZ = 1246, |
| 5772 | t2USAD8 = 1247, |
| 5773 | t2RBIT = 1248, |
| 5774 | t2PKHBT_t2PKHTB = 1249, |
| 5775 | VCVTASS_VCVTAUS_VCVTMSS_VCVTMUS_VCVTNSS_VCVTNUS_VCVTPSS_VCVTPUS = 1250, |
| 5776 | VFP_VMAXNMS_VFP_VMINNMS = 1251, |
| 5777 | VRINTAS_VRINTMS_VRINTNS_VRINTPS_VRINTRS_VRINTXS_VRINTZS = 1252, |
| 5778 | VCVTASD_VCVTAUD_VCVTMSD_VCVTMUD_VCVTNSD_VCVTNUD_VCVTPSD_VCVTPUD = 1253, |
| 5779 | VCVTTHD = 1254, |
| 5780 | VFP_VMAXNMD_VFP_VMINNMD = 1255, |
| 5781 | VRINTAD_VRINTMD_VRINTND_VRINTPD_VRINTRD_VRINTXD_VRINTZD = 1256, |
| 5782 | VCMPS = 1257, |
| 5783 | VCMPD = 1258, |
| 5784 | VSELEQS_VSELGES_VSELGTS_VSELVSS = 1259, |
| 5785 | VSELEQD_VSELGED_VSELGTD_VSELVSD = 1260, |
| 5786 | VMULD_VNMULD = 1261, |
| 5787 | tLDRspi = 1262, |
| 5788 | t2LDA_t2LDAEX = 1263, |
| 5789 | t2LDAEXD = 1264, |
| 5790 | t2STL_t2STLB_t2STLEX_t2STLEXB_t2STLEXH_t2STLH = 1265, |
| 5791 | MVE_VST20_16_MVE_VST20_32_MVE_VST20_8_MVE_VST21_16_MVE_VST21_32_MVE_VST21_8_MVE_VST40_16_MVE_VST40_32_MVE_VST40_8_MVE_VST41_16_MVE_VST41_32_MVE_VST41_8_MVE_VST42_16_MVE_VST42_32_MVE_VST42_8_MVE_VST43_16_MVE_VST43_32_MVE_VST43_8 = 1266, |
| 5792 | MVE_VSTRD64_qi_MVE_VSTRW32_qi = 1267, |
| 5793 | t2RSBSrs = 1268, |
| 5794 | t2ADCrs_t2SBCrs = 1269, |
| 5795 | t2ADDSrr_t2SBCrr = 1270, |
| 5796 | t2SUBSrr_t2RSBrr = 1271, |
| 5797 | t2ADCrr = 1272, |
| 5798 | t2BICrr_t2EORrr = 1273, |
| 5799 | t2ORNrr = 1274, |
| 5800 | tADDspi_tSUBspi = 1275, |
| 5801 | t2ADDri = 1276, |
| 5802 | t2ADDri12 = 1277, |
| 5803 | t2SUBri = 1278, |
| 5804 | t2SUBri12 = 1279, |
| 5805 | tADDrSP_tADDspr_tADDhirr = 1280, |
| 5806 | tADDrSPi = 1281, |
| 5807 | MVE_ASRLi_MVE_LSLLi_MVE_LSRL_MVE_SQSHLL_MVE_SRSHRL_MVE_UQSHLL_MVE_URSHRL = 1282, |
| 5808 | MVE_SQRSHR_MVE_UQRSHL = 1283, |
| 5809 | t2BF_LabelPseudo_t2BFLi_t2BFLr_t2BFi_t2BFic_t2BFr = 1284, |
| 5810 | MVE_LCTP = 1285, |
| 5811 | t2DLS_t2WLS_MVE_DLSTP_16_MVE_DLSTP_32_MVE_DLSTP_64_MVE_DLSTP_8_MVE_WLSTP_16_MVE_WLSTP_32_MVE_WLSTP_64_MVE_WLSTP_8 = 1286, |
| 5812 | t2LE = 1287, |
| 5813 | t2LEUpdate_MVE_LETP = 1288, |
| 5814 | VSHTOD_VSLTOD_VUHTOD_VULTOD = 1289, |
| 5815 | VMSR_VMSR_FPSCR_NZCVQC_VMSR_P0_VMSR_VPR = 1290, |
| 5816 | VMRS_P0_VMRS_VPR = 1291, |
| 5817 | VMRS_FPSCR_NZCVQC = 1292, |
| 5818 | VMRS = 1293, |
| 5819 | MVE_VMOV_q_rr = 1294, |
| 5820 | MVE_VADC = 1295, |
| 5821 | MVE_VADD_qr_i16_MVE_VADD_qr_i32_MVE_VADD_qr_i8 = 1296, |
| 5822 | MVE_VHADD_qr_s16_MVE_VHADD_qr_s32_MVE_VHADD_qr_s8_MVE_VHADD_qr_u16_MVE_VHADD_qr_u32_MVE_VHADD_qr_u8 = 1297, |
| 5823 | MVE_VHSUB_qr_s16_MVE_VHSUB_qr_s32_MVE_VHSUB_qr_s8_MVE_VHSUB_qr_u16_MVE_VHSUB_qr_u32_MVE_VHSUB_qr_u8 = 1298, |
| 5824 | MVE_VQADD_qr_s16_MVE_VQADD_qr_s32_MVE_VQADD_qr_s8_MVE_VQADD_qr_u16_MVE_VQADD_qr_u32_MVE_VQADD_qr_u8 = 1299, |
| 5825 | MVE_VQSUB_qr_s16_MVE_VQSUB_qr_s32_MVE_VQSUB_qr_s8_MVE_VQSUB_qr_u16_MVE_VQSUB_qr_u32_MVE_VQSUB_qr_u8 = 1300, |
| 5826 | MVE_VSHL_qrs16_MVE_VSHL_qrs32_MVE_VSHL_qrs8_MVE_VSHL_qru16_MVE_VSHL_qru32_MVE_VSHL_qru8 = 1301, |
| 5827 | MVE_VSUB_qr_i16_MVE_VSUB_qr_i32_MVE_VSUB_qr_i8 = 1302, |
| 5828 | MVE_VSHL_by_vecs16_MVE_VSHL_by_vecs32_MVE_VSHL_by_vecs8_MVE_VSHL_by_vecu16_MVE_VSHL_by_vecu32_MVE_VSHL_by_vecu8_MVE_VSHL_immi16_MVE_VSHL_immi32_MVE_VSHL_immi8_MVE_VSHLL_imms16bh_MVE_VSHLL_imms16th_MVE_VSHLL_imms8bh_MVE_VSHLL_imms8th_MVE_VSHLL_immu16bh_MVE_VSHLL_immu16th_MVE_VSHLL_immu8bh_MVE_VSHLL_immu8th_MVE_VSHLL_lws16bh_MVE_VSHLL_lws16th_MVE_VSHLL_lws8bh_MVE_VSHLL_lws8th_MVE_VSHLL_lwu16bh_MVE_VSHLL_lwu16th_MVE_VSHLL_lwu8bh_MVE_VSHLL_lwu8th = 1303, |
| 5829 | MVE_VSHRNi16bh_MVE_VSHRNi16th_MVE_VSHRNi32bh_MVE_VSHRNi32th = 1304, |
| 5830 | MVE_VDWDUPu16_MVE_VDWDUPu32_MVE_VDWDUPu8_MVE_VIWDUPu16_MVE_VIWDUPu32_MVE_VIWDUPu8 = 1305, |
| 5831 | MVE_VDDUPu16_MVE_VDDUPu32_MVE_VDDUPu8_MVE_VIDUPu16_MVE_VIDUPu32_MVE_VIDUPu8 = 1306, |
| 5832 | MVE_VQRSHL_qrs16_MVE_VQRSHL_qrs32_MVE_VQRSHL_qrs8_MVE_VQRSHL_qru16_MVE_VQRSHL_qru32_MVE_VQRSHL_qru8 = 1307, |
| 5833 | MVE_VQSHL_qrs16_MVE_VQSHL_qrs32_MVE_VQSHL_qrs8_MVE_VQSHL_qru16_MVE_VQSHL_qru32_MVE_VQSHL_qru8_MVE_VRSHL_qrs16_MVE_VRSHL_qrs32_MVE_VRSHL_qrs8_MVE_VRSHL_qru16_MVE_VRSHL_qru32_MVE_VRSHL_qru8 = 1308, |
| 5834 | MVE_VMAXNMAf16_MVE_VMAXNMAf32_MVE_VMAXNMf16_MVE_VMAXNMf32_MVE_VMINNMAf16_MVE_VMINNMAf32_MVE_VMINNMf16_MVE_VMINNMf32 = 1309, |
| 5835 | MVE_VADDLVs32acc_MVE_VADDLVu32acc = 1310, |
| 5836 | MVE_VADDVs16acc_MVE_VADDVs32acc_MVE_VADDVs8acc_MVE_VADDVu16acc_MVE_VADDVu32acc_MVE_VADDVu8acc = 1311, |
| 5837 | MVE_VMUL_qr_i16_MVE_VMUL_qr_i32_MVE_VMUL_qr_i8 = 1312, |
| 5838 | MVE_VQDMULH_qr_s16_MVE_VQDMULH_qr_s32_MVE_VQDMULH_qr_s8_MVE_VQRDMULH_qr_s16_MVE_VQRDMULH_qr_s32_MVE_VQRDMULH_qr_s8 = 1313, |
| 5839 | MVE_VMLAS_qr_i16_MVE_VMLAS_qr_i32_MVE_VMLAS_qr_i8_MVE_VMLA_qr_i16_MVE_VMLA_qr_i32_MVE_VMLA_qr_i8 = 1314, |
| 5840 | MVE_VQDMLAH_qrs16_MVE_VQDMLAH_qrs32_MVE_VQDMLAH_qrs8_MVE_VQDMLASH_qrs16_MVE_VQDMLASH_qrs32_MVE_VQDMLASH_qrs8_MVE_VQRDMLAH_qrs16_MVE_VQRDMLAH_qrs32_MVE_VQRDMLAH_qrs8_MVE_VQRDMLASH_qrs16_MVE_VQRDMLASH_qrs32_MVE_VQRDMLASH_qrs8 = 1315, |
| 5841 | MVE_VQDMLADHXs16_MVE_VQDMLADHXs32_MVE_VQDMLADHXs8_MVE_VQDMLADHs16_MVE_VQDMLADHs32_MVE_VQDMLADHs8_MVE_VQDMLSDHXs16_MVE_VQDMLSDHXs32_MVE_VQDMLSDHXs8_MVE_VQDMLSDHs16_MVE_VQDMLSDHs32_MVE_VQDMLSDHs8_MVE_VQRDMLADHXs16_MVE_VQRDMLADHXs32_MVE_VQRDMLADHXs8_MVE_VQRDMLADHs16_MVE_VQRDMLADHs32_MVE_VQRDMLADHs8_MVE_VQRDMLSDHXs16_MVE_VQRDMLSDHXs32_MVE_VQRDMLSDHXs8_MVE_VQRDMLSDHs16_MVE_VQRDMLSDHs32_MVE_VQRDMLSDHs8 = 1316, |
| 5842 | MVE_VMLALDAVas16_MVE_VMLALDAVas32_MVE_VMLALDAVau16_MVE_VMLALDAVau32_MVE_VMLALDAVaxs16_MVE_VMLALDAVaxs32_MVE_VMLSLDAVas16_MVE_VMLSLDAVas32_MVE_VMLSLDAVaxs16_MVE_VMLSLDAVaxs32_MVE_VRMLALDAVHas32_MVE_VRMLALDAVHau32_MVE_VRMLALDAVHaxs32_MVE_VRMLSLDAVHas32_MVE_VRMLSLDAVHaxs32 = 1317, |
| 5843 | MVE_VMLADAVas16_MVE_VMLADAVas32_MVE_VMLADAVas8_MVE_VMLADAVau16_MVE_VMLADAVau32_MVE_VMLADAVau8_MVE_VMLADAVaxs16_MVE_VMLADAVaxs32_MVE_VMLADAVaxs8_MVE_VMLSDAVas16_MVE_VMLSDAVas32_MVE_VMLSDAVas8_MVE_VMLSDAVaxs16_MVE_VMLSDAVaxs32_MVE_VMLSDAVaxs8 = 1318, |
| 5844 | MVE_VMULi16_MVE_VMULi32_MVE_VMULi8 = 1319, |
| 5845 | MVE_VMUL_qr_f16_MVE_VMUL_qr_f32 = 1320, |
| 5846 | MVE_VFMA_qr_Sf16_MVE_VFMA_qr_Sf32_MVE_VFMA_qr_f16_MVE_VFMA_qr_f32 = 1321, |
| 5847 | MVE_VPTv4f32r_MVE_VPTv8f16r = 1322, |
| 5848 | MVE_VPTv16i8r_MVE_VPTv16s8r_MVE_VPTv16u8r_MVE_VPTv4i32r_MVE_VPTv4s32r_MVE_VPTv4u32r_MVE_VPTv8i16r_MVE_VPTv8s16r_MVE_VPTv8u16r = 1323, |
| 5849 | MVE_VCMPi16r_MVE_VCMPi32r_MVE_VCMPi8r_MVE_VCMPs16r_MVE_VCMPs32r_MVE_VCMPs8r_MVE_VCMPu16r_MVE_VCMPu32r_MVE_VCMPu8r = 1324, |
| 5850 | MVE_VCMPf16r_MVE_VCMPf32r = 1325, |
| 5851 | SCHED_LIST_END = 1326 |
| 5852 | }; |
| 5853 | } // end namespace Sched |
| 5854 | } // end namespace ARM |
| 5855 | } // end namespace llvm |
| 5856 | #endif // GET_INSTRINFO_SCHED_ENUM |
| 5857 | |
| 5858 | #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 5859 | namespace llvm { |
| 5860 | |
| 5861 | struct ARMInstrTable { |
| 5862 | MCInstrDesc Insts[4496]; |
| 5863 | static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); |
| 5864 | MCOperandInfo OperandInfo[3077]; |
| 5865 | static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); |
| 5866 | MCPhysReg ImplicitOps[233]; |
| 5867 | }; |
| 5868 | |
| 5869 | } // end namespace llvm |
| 5870 | #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 5871 | |
| 5872 | #ifdef GET_INSTRINFO_MC_DESC |
| 5873 | #undef GET_INSTRINFO_MC_DESC |
| 5874 | namespace llvm { |
| 5875 | |
| 5876 | static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); |
| 5877 | static constexpr unsigned ARMImpOpBase = sizeof ARMInstrTable::OperandInfo / (sizeof(MCPhysReg)); |
| 5878 | |
| 5879 | extern const ARMInstrTable ARMDescs = { |
| 5880 | { |
| 5881 | { 4495, 0, 0, 2, 846, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4495 = t__brkdiv0 |
| 5882 | { 4494, 4, 1, 2, 899, 0, 0, ARMImpOpBase + 0, 3031, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4494 = tUXTH |
| 5883 | { 4493, 4, 1, 2, 899, 0, 0, ARMImpOpBase + 0, 3031, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4493 = tUXTB |
| 5884 | { 4492, 1, 0, 2, 1092, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4492 = tUDF |
| 5885 | { 4491, 4, 0, 2, 1091, 0, 1, ARMImpOpBase + 0, 3031, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // Inst #4491 = tTST |
| 5886 | { 4490, 0, 0, 2, 1090, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4490 = tTRAP |
| 5887 | { 4489, 4, 1, 2, 899, 0, 0, ARMImpOpBase + 0, 3031, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4489 = tSXTH |
| 5888 | { 4488, 4, 1, 2, 899, 0, 0, ARMImpOpBase + 0, 3031, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4488 = tSXTB |
| 5889 | { 4487, 3, 0, 2, 1217, 1, 0, ARMImpOpBase + 54, 861, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4487 = tSVC |
| 5890 | { 4486, 5, 1, 2, 1275, 0, 0, ARMImpOpBase + 0, 3009, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4486 = tSUBspi |
| 5891 | { 4485, 6, 2, 2, 1079, 0, 0, ARMImpOpBase + 0, 3003, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4485 = tSUBrr |
| 5892 | { 4484, 6, 2, 2, 1110, 0, 0, ARMImpOpBase + 0, 2987, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4484 = tSUBi8 |
| 5893 | { 4483, 6, 2, 2, 1110, 0, 0, ARMImpOpBase + 0, 2981, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4483 = tSUBi3 |
| 5894 | { 4482, 5, 0, 2, 1089, 0, 0, ARMImpOpBase + 0, 3053, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8aULL }, // Inst #4482 = tSTRspi |
| 5895 | { 4481, 5, 0, 2, 436, 0, 0, ARMImpOpBase + 0, 3044, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL }, // Inst #4481 = tSTRr |
| 5896 | { 4480, 5, 0, 2, 1089, 0, 0, ARMImpOpBase + 0, 3039, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL }, // Inst #4480 = tSTRi |
| 5897 | { 4479, 5, 0, 2, 435, 0, 0, ARMImpOpBase + 0, 3044, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL }, // Inst #4479 = tSTRHr |
| 5898 | { 4478, 5, 0, 2, 1088, 0, 0, ARMImpOpBase + 0, 3039, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL }, // Inst #4478 = tSTRHi |
| 5899 | { 4477, 5, 0, 2, 435, 0, 0, ARMImpOpBase + 0, 3044, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL }, // Inst #4477 = tSTRBr |
| 5900 | { 4476, 5, 0, 2, 1088, 0, 0, ARMImpOpBase + 0, 3039, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL }, // Inst #4476 = tSTRBi |
| 5901 | { 4475, 5, 1, 2, 1027, 0, 0, ARMImpOpBase + 0, 561, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4475 = tSTMIA_UPD |
| 5902 | { 4474, 1, 0, 2, 1078, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4474 = tSETEND |
| 5903 | { 4473, 6, 2, 2, 1079, 1, 0, ARMImpOpBase + 0, 2975, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x80c80ULL }, // Inst #4473 = tSBC |
| 5904 | { 4472, 5, 2, 2, 1080, 0, 0, ARMImpOpBase + 0, 3069, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4472 = tRSB |
| 5905 | { 4471, 6, 2, 2, 881, 0, 0, ARMImpOpBase + 0, 2975, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4471 = tROR |
| 5906 | { 4470, 4, 1, 2, 1033, 0, 0, ARMImpOpBase + 0, 3031, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4470 = tREVSH |
| 5907 | { 4469, 4, 1, 2, 1033, 0, 0, ARMImpOpBase + 0, 3031, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4469 = tREV16 |
| 5908 | { 4468, 4, 1, 2, 1033, 0, 0, ARMImpOpBase + 0, 3031, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4468 = tREV |
| 5909 | { 4467, 3, 0, 2, 453, 1, 1, ARMImpOpBase + 1, 587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4467 = tPUSH |
| 5910 | { 4466, 3, 0, 2, 425, 1, 1, ARMImpOpBase + 1, 587, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4466 = tPOP |
| 5911 | { 4465, 3, 1, 2, 1079, 0, 0, ARMImpOpBase + 0, 3074, 0|(1ULL<<MCID::NotDuplicable), 0xc80ULL }, // Inst #4465 = tPICADD |
| 5912 | { 4464, 6, 2, 2, 1081, 0, 0, ARMImpOpBase + 0, 2975, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4464 = tORR |
| 5913 | { 4463, 5, 2, 2, 873, 0, 0, ARMImpOpBase + 0, 3069, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4463 = tMVN |
| 5914 | { 4462, 6, 2, 2, 884, 0, 0, ARMImpOpBase + 0, 3063, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4462 = tMUL |
| 5915 | { 4461, 4, 1, 2, 1028, 0, 0, ARMImpOpBase + 0, 840, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4461 = tMOVr |
| 5916 | { 4460, 5, 2, 2, 1029, 0, 0, ARMImpOpBase + 0, 3058, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4460 = tMOVi8 |
| 5917 | { 4459, 2, 1, 2, 1087, 0, 1, ARMImpOpBase + 0, 590, 0|(1ULL<<MCID::MoveReg), 0xc80ULL }, // Inst #4459 = tMOVSr |
| 5918 | { 4458, 6, 2, 2, 882, 0, 0, ARMImpOpBase + 0, 2975, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4458 = tLSRrr |
| 5919 | { 4457, 6, 2, 2, 1082, 0, 0, ARMImpOpBase + 0, 2981, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4457 = tLSRri |
| 5920 | { 4456, 6, 2, 2, 882, 0, 0, ARMImpOpBase + 0, 2975, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4456 = tLSLrr |
| 5921 | { 4455, 6, 2, 2, 1082, 0, 0, ARMImpOpBase + 0, 2981, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4455 = tLSLri |
| 5922 | { 4454, 5, 1, 2, 1262, 0, 0, ARMImpOpBase + 0, 3053, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8aULL }, // Inst #4454 = tLDRspi |
| 5923 | { 4453, 5, 1, 2, 396, 0, 0, ARMImpOpBase + 0, 3044, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL }, // Inst #4453 = tLDRr |
| 5924 | { 4452, 4, 1, 2, 1232, 0, 0, ARMImpOpBase + 0, 3049, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8aULL }, // Inst #4452 = tLDRpci |
| 5925 | { 4451, 5, 1, 2, 907, 0, 0, ARMImpOpBase + 0, 3039, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL }, // Inst #4451 = tLDRi |
| 5926 | { 4450, 5, 1, 2, 402, 0, 0, ARMImpOpBase + 0, 3044, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc88ULL }, // Inst #4450 = tLDRSH |
| 5927 | { 4449, 5, 1, 2, 402, 0, 0, ARMImpOpBase + 0, 3044, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc87ULL }, // Inst #4449 = tLDRSB |
| 5928 | { 4448, 5, 1, 2, 395, 0, 0, ARMImpOpBase + 0, 3044, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL }, // Inst #4448 = tLDRHr |
| 5929 | { 4447, 5, 1, 2, 906, 0, 0, ARMImpOpBase + 0, 3039, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL }, // Inst #4447 = tLDRHi |
| 5930 | { 4446, 5, 1, 2, 395, 0, 0, ARMImpOpBase + 0, 3044, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL }, // Inst #4446 = tLDRBr |
| 5931 | { 4445, 5, 1, 2, 906, 0, 0, ARMImpOpBase + 0, 3039, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL }, // Inst #4445 = tLDRBi |
| 5932 | { 4444, 4, 0, 2, 1019, 0, 0, ARMImpOpBase + 0, 3035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4444 = tLDMIA |
| 5933 | { 4443, 2, 0, 12, 1040, 0, 10, ARMImpOpBase + 223, 590, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4443 = tInt_eh_sjlj_setjmp |
| 5934 | { 4442, 2, 0, 10, 1040, 0, 3, ARMImpOpBase + 5, 590, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #4442 = tInt_eh_sjlj_longjmp |
| 5935 | { 4441, 2, 0, 12, 852, 0, 3, ARMImpOpBase + 220, 152, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #4441 = tInt_WIN_eh_sjlj_longjmp |
| 5936 | { 4440, 1, 0, 2, 1078, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4440 = tHLT |
| 5937 | { 4439, 3, 0, 2, 1220, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4439 = tHINT |
| 5938 | { 4438, 6, 2, 2, 1081, 0, 0, ARMImpOpBase + 0, 2975, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4438 = tEOR |
| 5939 | { 4437, 2, 0, 2, 1086, 0, 0, ARMImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4437 = tCPS |
| 5940 | { 4436, 4, 0, 2, 1084, 0, 1, ARMImpOpBase + 0, 3031, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4436 = tCMPr |
| 5941 | { 4435, 4, 0, 2, 1085, 0, 1, ARMImpOpBase + 0, 566, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4435 = tCMPi8 |
| 5942 | { 4434, 4, 0, 2, 1084, 0, 1, ARMImpOpBase + 0, 840, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4434 = tCMPhir |
| 5943 | { 4433, 4, 0, 2, 1084, 0, 1, ARMImpOpBase + 0, 3031, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4433 = tCMNz |
| 5944 | { 4432, 2, 0, 2, 1083, 0, 0, ARMImpOpBase + 0, 3029, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4432 = tCBZ |
| 5945 | { 4431, 2, 0, 2, 1083, 0, 0, ARMImpOpBase + 0, 3029, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4431 = tCBNZ |
| 5946 | { 4430, 3, 0, 2, 1093, 0, 0, ARMImpOpBase + 0, 548, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4430 = tBcc |
| 5947 | { 4429, 3, 0, 2, 1093, 0, 0, ARMImpOpBase + 0, 538, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4429 = tBXNS |
| 5948 | { 4428, 3, 0, 2, 1093, 0, 0, ARMImpOpBase + 0, 538, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4428 = tBX |
| 5949 | { 4427, 3, 0, 2, 1094, 1, 1, ARMImpOpBase + 3, 3026, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4427 = tBLXr |
| 5950 | { 4426, 3, 0, 4, 857, 1, 1, ARMImpOpBase + 3, 434, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4426 = tBLXi |
| 5951 | { 4425, 3, 0, 2, 1094, 1, 1, ARMImpOpBase + 3, 3023, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4425 = tBLXNSr |
| 5952 | { 4424, 3, 0, 4, 857, 1, 1, ARMImpOpBase + 3, 434, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4424 = tBL |
| 5953 | { 4423, 1, 0, 2, 1039, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4423 = tBKPT |
| 5954 | { 4422, 6, 2, 2, 1081, 0, 0, ARMImpOpBase + 0, 2975, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4422 = tBIC |
| 5955 | { 4421, 3, 0, 2, 1093, 0, 0, ARMImpOpBase + 0, 548, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // Inst #4421 = tB |
| 5956 | { 4420, 6, 2, 2, 882, 0, 0, ARMImpOpBase + 0, 2975, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4420 = tASRrr |
| 5957 | { 4419, 6, 2, 2, 1082, 0, 0, ARMImpOpBase + 0, 2981, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4419 = tASRri |
| 5958 | { 4418, 6, 2, 2, 1081, 0, 0, ARMImpOpBase + 0, 2975, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4418 = tAND |
| 5959 | { 4417, 4, 1, 2, 1080, 0, 0, ARMImpOpBase + 0, 3019, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4417 = tADR |
| 5960 | { 4416, 5, 1, 2, 1280, 0, 0, ARMImpOpBase + 0, 3014, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4416 = tADDspr |
| 5961 | { 4415, 5, 1, 2, 1275, 0, 0, ARMImpOpBase + 0, 3009, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4415 = tADDspi |
| 5962 | { 4414, 6, 2, 2, 1079, 0, 0, ARMImpOpBase + 0, 3003, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4414 = tADDrr |
| 5963 | { 4413, 5, 1, 2, 1281, 0, 0, ARMImpOpBase + 0, 2998, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4413 = tADDrSPi |
| 5964 | { 4412, 5, 1, 2, 1280, 0, 0, ARMImpOpBase + 0, 2993, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4412 = tADDrSP |
| 5965 | { 4411, 6, 2, 2, 1110, 0, 0, ARMImpOpBase + 0, 2987, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4411 = tADDi8 |
| 5966 | { 4410, 6, 2, 2, 1110, 0, 0, ARMImpOpBase + 0, 2981, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4410 = tADDi3 |
| 5967 | { 4409, 5, 1, 2, 1280, 0, 0, ARMImpOpBase + 0, 277, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4409 = tADDhirr |
| 5968 | { 4408, 6, 2, 2, 1079, 1, 0, ARMImpOpBase + 0, 2975, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x80c80ULL }, // Inst #4408 = tADC |
| 5969 | { 4407, 3, 1, 4, 1286, 0, 0, ARMImpOpBase + 0, 514, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4407 = t2WLS |
| 5970 | { 4406, 5, 1, 4, 898, 0, 0, ARMImpOpBase + 0, 497, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4406 = t2UXTH |
| 5971 | { 4405, 5, 1, 4, 353, 0, 0, ARMImpOpBase + 0, 497, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4405 = t2UXTB16 |
| 5972 | { 4404, 5, 1, 4, 898, 0, 0, ARMImpOpBase + 0, 497, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4404 = t2UXTB |
| 5973 | { 4403, 6, 1, 4, 1101, 0, 0, ARMImpOpBase + 0, 2882, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4403 = t2UXTAH |
| 5974 | { 4402, 6, 1, 4, 1102, 0, 0, ARMImpOpBase + 0, 2882, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4402 = t2UXTAB16 |
| 5975 | { 4401, 6, 1, 4, 1101, 0, 0, ARMImpOpBase + 0, 2882, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4401 = t2UXTAB |
| 5976 | { 4400, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4400 = t2USUB8 |
| 5977 | { 4399, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4399 = t2USUB16 |
| 5978 | { 4398, 5, 1, 4, 365, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4398 = t2USAX |
| 5979 | { 4397, 5, 1, 4, 363, 0, 0, ARMImpOpBase + 0, 2920, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4397 = t2USAT16 |
| 5980 | { 4396, 6, 1, 4, 363, 0, 0, ARMImpOpBase + 0, 2914, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4396 = t2USAT |
| 5981 | { 4395, 6, 1, 4, 685, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4395 = t2USADA8 |
| 5982 | { 4394, 5, 1, 4, 1247, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4394 = t2USAD8 |
| 5983 | { 4393, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4393 = t2UQSUB8 |
| 5984 | { 4392, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4392 = t2UQSUB16 |
| 5985 | { 4391, 5, 1, 4, 892, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4391 = t2UQSAX |
| 5986 | { 4390, 5, 1, 4, 892, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4390 = t2UQASX |
| 5987 | { 4389, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4389 = t2UQADD8 |
| 5988 | { 4388, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4388 = t2UQADD16 |
| 5989 | { 4387, 6, 2, 4, 383, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // Inst #4387 = t2UMULL |
| 5990 | { 4386, 8, 2, 4, 384, 0, 0, ARMImpOpBase + 0, 2906, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4386 = t2UMLAL |
| 5991 | { 4385, 8, 2, 4, 384, 0, 0, ARMImpOpBase + 0, 2906, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4385 = t2UMAAL |
| 5992 | { 4384, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4384 = t2UHSUB8 |
| 5993 | { 4383, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4383 = t2UHSUB16 |
| 5994 | { 4382, 5, 1, 4, 368, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4382 = t2UHSAX |
| 5995 | { 4381, 5, 1, 4, 368, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4381 = t2UHASX |
| 5996 | { 4380, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4380 = t2UHADD8 |
| 5997 | { 4379, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4379 = t2UHADD16 |
| 5998 | { 4378, 5, 1, 4, 686, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4378 = t2UDIV |
| 5999 | { 4377, 1, 0, 4, 1038, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4377 = t2UDF |
| 6000 | { 4376, 6, 1, 4, 896, 0, 0, ARMImpOpBase + 0, 2900, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4376 = t2UBFX |
| 6001 | { 4375, 5, 1, 4, 365, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4375 = t2UASX |
| 6002 | { 4374, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4374 = t2UADD8 |
| 6003 | { 4373, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4373 = t2UADD16 |
| 6004 | { 4372, 4, 1, 4, 1058, 0, 0, ARMImpOpBase + 0, 2971, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4372 = t2TTT |
| 6005 | { 4371, 4, 1, 4, 1058, 0, 0, ARMImpOpBase + 0, 2971, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4371 = t2TTAT |
| 6006 | { 4370, 4, 1, 4, 1058, 0, 0, ARMImpOpBase + 0, 2971, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4370 = t2TTA |
| 6007 | { 4369, 4, 1, 4, 1058, 0, 0, ARMImpOpBase + 0, 2971, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4369 = t2TT |
| 6008 | { 4368, 5, 0, 4, 1243, 0, 1, ARMImpOpBase + 0, 482, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4368 = t2TSTrs |
| 6009 | { 4367, 4, 0, 4, 1074, 0, 1, ARMImpOpBase + 0, 2758, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4367 = t2TSTrr |
| 6010 | { 4366, 4, 0, 4, 310, 0, 1, ARMImpOpBase + 0, 2726, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4366 = t2TSTri |
| 6011 | { 4365, 3, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4365 = t2TSB |
| 6012 | { 4364, 5, 0, 4, 1243, 0, 1, ARMImpOpBase + 0, 482, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4364 = t2TEQrs |
| 6013 | { 4363, 4, 0, 4, 1074, 0, 1, ARMImpOpBase + 0, 2758, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4363 = t2TEQrr |
| 6014 | { 4362, 4, 0, 4, 310, 0, 1, ARMImpOpBase + 0, 2726, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4362 = t2TEQri |
| 6015 | { 4361, 4, 0, 4, 1236, 0, 0, ARMImpOpBase + 0, 2967, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4361 = t2TBH |
| 6016 | { 4360, 4, 0, 4, 1236, 0, 0, ARMImpOpBase + 0, 2967, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4360 = t2TBB |
| 6017 | { 4359, 5, 1, 4, 898, 0, 0, ARMImpOpBase + 0, 497, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4359 = t2SXTH |
| 6018 | { 4358, 5, 1, 4, 353, 0, 0, ARMImpOpBase + 0, 497, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4358 = t2SXTB16 |
| 6019 | { 4357, 5, 1, 4, 898, 0, 0, ARMImpOpBase + 0, 497, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4357 = t2SXTB |
| 6020 | { 4356, 6, 1, 4, 901, 0, 0, ARMImpOpBase + 0, 2882, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4356 = t2SXTAH |
| 6021 | { 4355, 6, 1, 4, 369, 0, 0, ARMImpOpBase + 0, 2882, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4355 = t2SXTAB16 |
| 6022 | { 4354, 6, 1, 4, 901, 0, 0, ARMImpOpBase + 0, 2882, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4354 = t2SXTAB |
| 6023 | { 4353, 5, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 2721, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4353 = t2SUBspImm12 |
| 6024 | { 4352, 6, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 2715, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4352 = t2SUBspImm |
| 6025 | { 4351, 7, 1, 4, 1237, 0, 0, ARMImpOpBase + 0, 2708, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4351 = t2SUBrs |
| 6026 | { 4350, 6, 1, 4, 1073, 0, 0, ARMImpOpBase + 0, 2702, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4350 = t2SUBrr |
| 6027 | { 4349, 5, 1, 4, 1279, 0, 0, ARMImpOpBase + 0, 2697, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4349 = t2SUBri12 |
| 6028 | { 4348, 6, 1, 4, 1278, 0, 0, ARMImpOpBase + 0, 2691, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4348 = t2SUBri |
| 6029 | { 4347, 3, 0, 4, 1060, 0, 1, ARMImpOpBase + 66, 861, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // Inst #4347 = t2SUBS_PC_LR |
| 6030 | { 4346, 6, 0, 4, 432, 0, 0, ARMImpOpBase + 0, 2821, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4346 = t2STRs |
| 6031 | { 4345, 5, 0, 4, 431, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4345 = t2STRi8 |
| 6032 | { 4344, 5, 0, 4, 1075, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4344 = t2STRi12 |
| 6033 | { 4343, 6, 1, 4, 945, 0, 0, ARMImpOpBase + 0, 2961, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4343 = t2STR_PRE |
| 6034 | { 4342, 6, 1, 4, 442, 0, 0, ARMImpOpBase + 0, 2961, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4342 = t2STR_POST |
| 6035 | { 4341, 5, 0, 4, 446, 0, 0, ARMImpOpBase + 0, 2784, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4341 = t2STRT |
| 6036 | { 4340, 6, 0, 4, 434, 0, 0, ARMImpOpBase + 0, 2942, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4340 = t2STRHs |
| 6037 | { 4339, 5, 0, 4, 433, 0, 0, ARMImpOpBase + 0, 2784, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4339 = t2STRHi8 |
| 6038 | { 4338, 5, 0, 4, 1076, 0, 0, ARMImpOpBase + 0, 2784, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4338 = t2STRHi12 |
| 6039 | { 4337, 6, 1, 4, 945, 0, 0, ARMImpOpBase + 0, 2936, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4337 = t2STRH_PRE |
| 6040 | { 4336, 6, 1, 4, 443, 0, 0, ARMImpOpBase + 0, 2936, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4336 = t2STRH_POST |
| 6041 | { 4335, 5, 0, 4, 445, 0, 0, ARMImpOpBase + 0, 2784, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4335 = t2STRHT |
| 6042 | { 4334, 5, 1, 4, 1229, 0, 0, ARMImpOpBase + 0, 2925, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4334 = t2STREXH |
| 6043 | { 4333, 6, 1, 4, 731, 0, 0, ARMImpOpBase + 0, 2930, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4333 = t2STREXD |
| 6044 | { 4332, 5, 1, 4, 1229, 0, 0, ARMImpOpBase + 0, 2925, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4332 = t2STREXB |
| 6045 | { 4331, 6, 1, 4, 1229, 0, 0, ARMImpOpBase + 0, 2955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc94ULL }, // Inst #4331 = t2STREX |
| 6046 | { 4330, 6, 0, 4, 448, 0, 0, ARMImpOpBase + 0, 2806, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc91ULL }, // Inst #4330 = t2STRDi8 |
| 6047 | { 4329, 7, 1, 4, 947, 0, 0, ARMImpOpBase + 0, 2948, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc91ULL }, // Inst #4329 = t2STRD_PRE |
| 6048 | { 4328, 7, 1, 4, 449, 0, 0, ARMImpOpBase + 0, 2948, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc91ULL }, // Inst #4328 = t2STRD_POST |
| 6049 | { 4327, 6, 0, 4, 434, 0, 0, ARMImpOpBase + 0, 2942, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4327 = t2STRBs |
| 6050 | { 4326, 5, 0, 4, 433, 0, 0, ARMImpOpBase + 0, 2784, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4326 = t2STRBi8 |
| 6051 | { 4325, 5, 0, 4, 1076, 0, 0, ARMImpOpBase + 0, 2784, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4325 = t2STRBi12 |
| 6052 | { 4324, 6, 1, 4, 946, 0, 0, ARMImpOpBase + 0, 2936, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4324 = t2STRB_PRE |
| 6053 | { 4323, 6, 1, 4, 954, 0, 0, ARMImpOpBase + 0, 2936, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4323 = t2STRB_POST |
| 6054 | { 4322, 5, 0, 4, 939, 0, 0, ARMImpOpBase + 0, 2784, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4322 = t2STRBT |
| 6055 | { 4321, 5, 1, 4, 1077, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4321 = t2STMIA_UPD |
| 6056 | { 4320, 4, 0, 4, 1026, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4320 = t2STMIA |
| 6057 | { 4319, 5, 1, 4, 1077, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4319 = t2STMDB_UPD |
| 6058 | { 4318, 4, 0, 4, 1026, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4318 = t2STMDB |
| 6059 | { 4317, 4, 0, 4, 1265, 0, 0, ARMImpOpBase + 0, 2775, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4317 = t2STLH |
| 6060 | { 4316, 5, 1, 4, 1265, 0, 0, ARMImpOpBase + 0, 2925, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4316 = t2STLEXH |
| 6061 | { 4315, 6, 1, 4, 733, 0, 0, ARMImpOpBase + 0, 2930, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4315 = t2STLEXD |
| 6062 | { 4314, 5, 1, 4, 1265, 0, 0, ARMImpOpBase + 0, 2925, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4314 = t2STLEXB |
| 6063 | { 4313, 5, 1, 4, 1265, 0, 0, ARMImpOpBase + 0, 2925, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4313 = t2STLEX |
| 6064 | { 4312, 4, 0, 4, 1265, 0, 0, ARMImpOpBase + 0, 2775, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4312 = t2STLB |
| 6065 | { 4311, 4, 0, 4, 1265, 0, 0, ARMImpOpBase + 0, 2775, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4311 = t2STL |
| 6066 | { 4310, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4310 = t2STC_PRE |
| 6067 | { 4309, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4309 = t2STC_POST |
| 6068 | { 4308, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 898, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4308 = t2STC_OPTION |
| 6069 | { 4307, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4307 = t2STC_OFFSET |
| 6070 | { 4306, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4306 = t2STCL_PRE |
| 6071 | { 4305, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4305 = t2STCL_POST |
| 6072 | { 4304, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 898, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4304 = t2STCL_OPTION |
| 6073 | { 4303, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4303 = t2STCL_OFFSET |
| 6074 | { 4302, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4302 = t2STC2_PRE |
| 6075 | { 4301, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4301 = t2STC2_POST |
| 6076 | { 4300, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 898, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4300 = t2STC2_OPTION |
| 6077 | { 4299, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4299 = t2STC2_OFFSET |
| 6078 | { 4298, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4298 = t2STC2L_PRE |
| 6079 | { 4297, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4297 = t2STC2L_POST |
| 6080 | { 4296, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 898, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4296 = t2STC2L_OPTION |
| 6081 | { 4295, 6, 0, 4, 1036, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4295 = t2STC2L_OFFSET |
| 6082 | { 4294, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4294 = t2SSUB8 |
| 6083 | { 4293, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4293 = t2SSUB16 |
| 6084 | { 4292, 5, 1, 4, 365, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4292 = t2SSAX |
| 6085 | { 4291, 5, 1, 4, 363, 0, 0, ARMImpOpBase + 0, 2920, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4291 = t2SSAT16 |
| 6086 | { 4290, 6, 1, 4, 363, 0, 0, ARMImpOpBase + 0, 2914, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4290 = t2SSAT |
| 6087 | { 4289, 3, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4289 = t2SRSIA_UPD |
| 6088 | { 4288, 3, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4288 = t2SRSIA |
| 6089 | { 4287, 3, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4287 = t2SRSDB_UPD |
| 6090 | { 4286, 3, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4286 = t2SRSDB |
| 6091 | { 4285, 5, 1, 4, 375, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4285 = t2SMUSDX |
| 6092 | { 4284, 5, 1, 4, 375, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4284 = t2SMUSD |
| 6093 | { 4283, 5, 1, 4, 374, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4283 = t2SMULWT |
| 6094 | { 4282, 5, 1, 4, 374, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4282 = t2SMULWB |
| 6095 | { 4281, 5, 1, 4, 374, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4281 = t2SMULTT |
| 6096 | { 4280, 5, 1, 4, 374, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4280 = t2SMULTB |
| 6097 | { 4279, 6, 2, 4, 383, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // Inst #4279 = t2SMULL |
| 6098 | { 4278, 5, 1, 4, 374, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4278 = t2SMULBT |
| 6099 | { 4277, 5, 1, 4, 374, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4277 = t2SMULBB |
| 6100 | { 4276, 5, 1, 4, 377, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4276 = t2SMUADX |
| 6101 | { 4275, 5, 1, 4, 377, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4275 = t2SMUAD |
| 6102 | { 4274, 5, 1, 4, 373, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4274 = t2SMMULR |
| 6103 | { 4273, 5, 1, 4, 373, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4273 = t2SMMUL |
| 6104 | { 4272, 6, 1, 4, 1100, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4272 = t2SMMLSR |
| 6105 | { 4271, 6, 1, 4, 1100, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4271 = t2SMMLS |
| 6106 | { 4270, 6, 1, 4, 1100, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4270 = t2SMMLAR |
| 6107 | { 4269, 6, 1, 4, 1100, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4269 = t2SMMLA |
| 6108 | { 4268, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2906, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4268 = t2SMLSLDX |
| 6109 | { 4267, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2906, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4267 = t2SMLSLD |
| 6110 | { 4266, 6, 1, 4, 380, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4266 = t2SMLSDX |
| 6111 | { 4265, 6, 1, 4, 380, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4265 = t2SMLSD |
| 6112 | { 4264, 6, 1, 4, 379, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4264 = t2SMLAWT |
| 6113 | { 4263, 6, 1, 4, 379, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4263 = t2SMLAWB |
| 6114 | { 4262, 6, 1, 4, 379, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4262 = t2SMLATT |
| 6115 | { 4261, 6, 1, 4, 379, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4261 = t2SMLATB |
| 6116 | { 4260, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2906, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4260 = t2SMLALTT |
| 6117 | { 4259, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2906, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4259 = t2SMLALTB |
| 6118 | { 4258, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2906, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4258 = t2SMLALDX |
| 6119 | { 4257, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2906, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4257 = t2SMLALD |
| 6120 | { 4256, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2906, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4256 = t2SMLALBT |
| 6121 | { 4255, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2906, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4255 = t2SMLALBB |
| 6122 | { 4254, 8, 2, 4, 1032, 0, 0, ARMImpOpBase + 0, 2906, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4254 = t2SMLAL |
| 6123 | { 4253, 6, 1, 4, 381, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4253 = t2SMLADX |
| 6124 | { 4252, 6, 1, 4, 381, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4252 = t2SMLAD |
| 6125 | { 4251, 6, 1, 4, 379, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4251 = t2SMLABT |
| 6126 | { 4250, 6, 1, 4, 379, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4250 = t2SMLABB |
| 6127 | { 4249, 3, 0, 4, 1219, 1, 0, ARMImpOpBase + 54, 861, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4249 = t2SMC |
| 6128 | { 4248, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4248 = t2SHSUB8 |
| 6129 | { 4247, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4247 = t2SHSUB16 |
| 6130 | { 4246, 5, 1, 4, 368, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4246 = t2SHSAX |
| 6131 | { 4245, 5, 1, 4, 368, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4245 = t2SHASX |
| 6132 | { 4244, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4244 = t2SHADD8 |
| 6133 | { 4243, 5, 1, 4, 888, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4243 = t2SHADD16 |
| 6134 | { 4242, 2, 0, 4, 1058, 0, 0, ARMImpOpBase + 0, 543, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4242 = t2SG |
| 6135 | { 4241, 1, 0, 2, 1078, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4241 = t2SETPAN |
| 6136 | { 4240, 5, 1, 4, 358, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4240 = t2SEL |
| 6137 | { 4239, 5, 1, 4, 686, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4239 = t2SDIV |
| 6138 | { 4238, 6, 1, 4, 896, 0, 0, ARMImpOpBase + 0, 2900, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4238 = t2SBFX |
| 6139 | { 4237, 7, 1, 4, 1269, 1, 1, ARMImpOpBase + 63, 2684, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4237 = t2SBCrs |
| 6140 | { 4236, 6, 1, 4, 1270, 1, 1, ARMImpOpBase + 63, 2678, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4236 = t2SBCrr |
| 6141 | { 4235, 6, 1, 4, 694, 1, 1, ARMImpOpBase + 63, 2672, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4235 = t2SBCri |
| 6142 | { 4234, 0, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4234 = t2SB |
| 6143 | { 4233, 5, 1, 4, 365, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4233 = t2SASX |
| 6144 | { 4232, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4232 = t2SADD8 |
| 6145 | { 4231, 5, 1, 4, 886, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4231 = t2SADD16 |
| 6146 | { 4230, 7, 1, 4, 708, 0, 0, ARMImpOpBase + 0, 2684, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4230 = t2RSBrs |
| 6147 | { 4229, 6, 1, 4, 1271, 0, 0, ARMImpOpBase + 0, 2678, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4229 = t2RSBrr |
| 6148 | { 4228, 6, 1, 4, 1072, 0, 0, ARMImpOpBase + 0, 2672, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4228 = t2RSBri |
| 6149 | { 4227, 5, 1, 4, 1244, 1, 0, ARMImpOpBase + 0, 2866, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4227 = t2RRX |
| 6150 | { 4226, 6, 1, 4, 1066, 0, 0, ARMImpOpBase + 0, 2678, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4226 = t2RORrr |
| 6151 | { 4225, 6, 1, 4, 875, 0, 0, ARMImpOpBase + 0, 2672, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4225 = t2RORri |
| 6152 | { 4224, 3, 0, 4, 730, 0, 1, ARMImpOpBase + 66, 538, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4224 = t2RFEIAW |
| 6153 | { 4223, 3, 0, 4, 730, 0, 1, ARMImpOpBase + 66, 538, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4223 = t2RFEIA |
| 6154 | { 4222, 3, 0, 4, 730, 0, 1, ARMImpOpBase + 66, 538, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4222 = t2RFEDBW |
| 6155 | { 4221, 3, 0, 4, 730, 0, 1, ARMImpOpBase + 66, 538, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4221 = t2RFEDB |
| 6156 | { 4220, 4, 1, 4, 1071, 0, 0, ARMImpOpBase + 0, 2758, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4220 = t2REVSH |
| 6157 | { 4219, 4, 1, 4, 1071, 0, 0, ARMImpOpBase + 0, 2758, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4219 = t2REV16 |
| 6158 | { 4218, 4, 1, 4, 1071, 0, 0, ARMImpOpBase + 0, 2758, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4218 = t2REV |
| 6159 | { 4217, 4, 1, 4, 1248, 0, 0, ARMImpOpBase + 0, 2758, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4217 = t2RBIT |
| 6160 | { 4216, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4216 = t2QSUB8 |
| 6161 | { 4215, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4215 = t2QSUB16 |
| 6162 | { 4214, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4214 = t2QSUB |
| 6163 | { 4213, 5, 1, 4, 892, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4213 = t2QSAX |
| 6164 | { 4212, 5, 1, 4, 362, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4212 = t2QDSUB |
| 6165 | { 4211, 5, 1, 4, 362, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4211 = t2QDADD |
| 6166 | { 4210, 5, 1, 4, 892, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4210 = t2QASX |
| 6167 | { 4209, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4209 = t2QADD8 |
| 6168 | { 4208, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4208 = t2QADD16 |
| 6169 | { 4207, 5, 1, 4, 890, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4207 = t2QADD |
| 6170 | { 4206, 5, 0, 4, 1234, 0, 0, ARMImpOpBase + 0, 2892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4206 = t2PLIs |
| 6171 | { 4205, 3, 0, 4, 1231, 0, 0, ARMImpOpBase + 0, 2897, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc90ULL }, // Inst #4205 = t2PLIpci |
| 6172 | { 4204, 4, 0, 4, 1233, 0, 0, ARMImpOpBase + 0, 2888, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4204 = t2PLIi8 |
| 6173 | { 4203, 4, 0, 4, 1233, 0, 0, ARMImpOpBase + 0, 2888, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4203 = t2PLIi12 |
| 6174 | { 4202, 5, 0, 4, 1234, 0, 0, ARMImpOpBase + 0, 2892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4202 = t2PLDs |
| 6175 | { 4201, 3, 0, 4, 1231, 0, 0, ARMImpOpBase + 0, 2897, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc90ULL }, // Inst #4201 = t2PLDpci |
| 6176 | { 4200, 4, 0, 4, 1233, 0, 0, ARMImpOpBase + 0, 2888, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4200 = t2PLDi8 |
| 6177 | { 4199, 4, 0, 4, 1233, 0, 0, ARMImpOpBase + 0, 2888, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4199 = t2PLDi12 |
| 6178 | { 4198, 5, 0, 4, 935, 0, 0, ARMImpOpBase + 0, 2892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4198 = t2PLDWs |
| 6179 | { 4197, 4, 0, 4, 1233, 0, 0, ARMImpOpBase + 0, 2888, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4197 = t2PLDWi8 |
| 6180 | { 4196, 4, 0, 4, 1233, 0, 0, ARMImpOpBase + 0, 2888, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4196 = t2PLDWi12 |
| 6181 | { 4195, 6, 1, 4, 1249, 0, 0, ARMImpOpBase + 0, 2882, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4195 = t2PKHTB |
| 6182 | { 4194, 6, 1, 4, 1249, 0, 0, ARMImpOpBase + 0, 2882, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4194 = t2PKHBT |
| 6183 | { 4193, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 2877, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4193 = t2PACG |
| 6184 | { 4192, 0, 0, 4, 0, 2, 1, ARMImpOpBase + 217, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4192 = t2PACBTI |
| 6185 | { 4191, 0, 0, 4, 0, 2, 1, ARMImpOpBase + 217, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4191 = t2PAC |
| 6186 | { 4190, 7, 1, 4, 1239, 0, 0, ARMImpOpBase + 0, 2684, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4190 = t2ORRrs |
| 6187 | { 4189, 6, 1, 4, 1070, 0, 0, ARMImpOpBase + 0, 2678, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4189 = t2ORRrr |
| 6188 | { 4188, 6, 1, 4, 696, 0, 0, ARMImpOpBase + 0, 2672, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4188 = t2ORRri |
| 6189 | { 4187, 7, 1, 4, 1240, 0, 0, ARMImpOpBase + 0, 2684, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4187 = t2ORNrs |
| 6190 | { 4186, 6, 1, 4, 1274, 0, 0, ARMImpOpBase + 0, 2678, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4186 = t2ORNrr |
| 6191 | { 4185, 6, 1, 4, 46, 0, 0, ARMImpOpBase + 0, 2672, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4185 = t2ORNri |
| 6192 | { 4184, 6, 1, 4, 700, 0, 0, ARMImpOpBase + 0, 2871, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4184 = t2MVNs |
| 6193 | { 4183, 5, 1, 4, 699, 0, 0, ARMImpOpBase + 0, 2866, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4183 = t2MVNr |
| 6194 | { 4182, 5, 1, 4, 698, 0, 0, ARMImpOpBase + 0, 2840, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL }, // Inst #4182 = t2MVNi |
| 6195 | { 4181, 5, 1, 4, 1099, 0, 0, ARMImpOpBase + 0, 2861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // Inst #4181 = t2MUL |
| 6196 | { 4180, 4, 0, 4, 1030, 0, 0, ARMImpOpBase + 0, 2857, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4180 = t2MSRbanked |
| 6197 | { 4179, 4, 0, 4, 1030, 0, 1, ARMImpOpBase + 0, 2857, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4179 = t2MSR_M |
| 6198 | { 4178, 4, 0, 4, 1030, 0, 1, ARMImpOpBase + 0, 2857, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4178 = t2MSR_AR |
| 6199 | { 4177, 3, 1, 4, 1030, 0, 0, ARMImpOpBase + 0, 538, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4177 = t2MRSsys_AR |
| 6200 | { 4176, 4, 1, 4, 1030, 0, 0, ARMImpOpBase + 0, 2726, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4176 = t2MRSbanked |
| 6201 | { 4175, 4, 1, 4, 1030, 0, 0, ARMImpOpBase + 0, 2726, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4175 = t2MRS_M |
| 6202 | { 4174, 3, 1, 4, 1030, 0, 0, ARMImpOpBase + 0, 538, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4174 = t2MRS_AR |
| 6203 | { 4173, 7, 2, 4, 1035, 0, 0, ARMImpOpBase + 0, 2850, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4173 = t2MRRC2 |
| 6204 | { 4172, 7, 2, 4, 1035, 0, 0, ARMImpOpBase + 0, 2850, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4172 = t2MRRC |
| 6205 | { 4171, 8, 1, 4, 1096, 0, 0, ARMImpOpBase + 0, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4171 = t2MRC2 |
| 6206 | { 4170, 8, 1, 4, 1096, 0, 0, ARMImpOpBase + 0, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4170 = t2MRC |
| 6207 | { 4169, 4, 1, 4, 692, 0, 1, ARMImpOpBase + 0, 2758, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4169 = t2MOVsrl_glue |
| 6208 | { 4168, 4, 1, 4, 692, 0, 1, ARMImpOpBase + 0, 2758, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4168 = t2MOVsra_glue |
| 6209 | { 4167, 5, 1, 4, 880, 0, 0, ARMImpOpBase + 0, 2845, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4167 = t2MOVr |
| 6210 | { 4166, 4, 1, 4, 683, 0, 0, ARMImpOpBase + 0, 2726, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL }, // Inst #4166 = t2MOVi16 |
| 6211 | { 4165, 5, 1, 4, 683, 0, 0, ARMImpOpBase + 0, 2840, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL }, // Inst #4165 = t2MOVi |
| 6212 | { 4164, 5, 1, 4, 879, 0, 0, ARMImpOpBase + 0, 467, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4164 = t2MOVTi16 |
| 6213 | { 4163, 6, 1, 4, 376, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4163 = t2MLS |
| 6214 | { 4162, 6, 1, 4, 376, 0, 0, ARMImpOpBase + 0, 2834, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4162 = t2MLA |
| 6215 | { 4161, 7, 0, 4, 1096, 0, 0, ARMImpOpBase + 0, 2827, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4161 = t2MCRR2 |
| 6216 | { 4160, 7, 0, 4, 1096, 0, 0, ARMImpOpBase + 0, 2827, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4160 = t2MCRR |
| 6217 | { 4159, 8, 0, 4, 1096, 0, 0, ARMImpOpBase + 0, 969, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4159 = t2MCR2 |
| 6218 | { 4158, 8, 0, 4, 1096, 0, 0, ARMImpOpBase + 0, 969, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4158 = t2MCR |
| 6219 | { 4157, 6, 1, 4, 1066, 0, 0, ARMImpOpBase + 0, 2678, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4157 = t2LSRrr |
| 6220 | { 4156, 6, 1, 4, 1065, 0, 0, ARMImpOpBase + 0, 2672, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4156 = t2LSRri |
| 6221 | { 4155, 6, 1, 4, 1066, 0, 0, ARMImpOpBase + 0, 2678, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4155 = t2LSLrr |
| 6222 | { 4154, 6, 1, 4, 1065, 0, 0, ARMImpOpBase + 0, 2672, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4154 = t2LSLri |
| 6223 | { 4153, 3, 1, 4, 1288, 0, 0, ARMImpOpBase + 0, 458, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4153 = t2LEUpdate |
| 6224 | { 4152, 1, 0, 4, 1287, 0, 0, ARMImpOpBase + 0, 193, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4152 = t2LE |
| 6225 | { 4151, 6, 1, 4, 391, 0, 0, ARMImpOpBase + 0, 2821, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8fULL }, // Inst #4151 = t2LDRs |
| 6226 | { 4150, 4, 1, 4, 1230, 0, 0, ARMImpOpBase + 0, 2817, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4150 = t2LDRpci |
| 6227 | { 4149, 5, 1, 4, 390, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL }, // Inst #4149 = t2LDRi8 |
| 6228 | { 4148, 5, 1, 4, 1107, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8bULL }, // Inst #4148 = t2LDRi12 |
| 6229 | { 4147, 6, 2, 4, 921, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4147 = t2LDR_PRE |
| 6230 | { 4146, 6, 2, 4, 411, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4146 = t2LDR_POST |
| 6231 | { 4145, 5, 1, 4, 413, 0, 0, ARMImpOpBase + 0, 2784, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4145 = t2LDRT |
| 6232 | { 4144, 6, 1, 4, 401, 0, 0, ARMImpOpBase + 0, 2793, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4144 = t2LDRSHs |
| 6233 | { 4143, 4, 1, 4, 1224, 0, 0, ARMImpOpBase + 0, 2789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4143 = t2LDRSHpci |
| 6234 | { 4142, 5, 1, 4, 400, 0, 0, ARMImpOpBase + 0, 917, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4142 = t2LDRSHi8 |
| 6235 | { 4141, 5, 1, 4, 400, 0, 0, ARMImpOpBase + 0, 917, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4141 = t2LDRSHi12 |
| 6236 | { 4140, 6, 2, 4, 920, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4140 = t2LDRSH_PRE |
| 6237 | { 4139, 6, 2, 4, 415, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4139 = t2LDRSH_POST |
| 6238 | { 4138, 5, 1, 4, 416, 0, 0, ARMImpOpBase + 0, 2784, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4138 = t2LDRSHT |
| 6239 | { 4137, 6, 1, 4, 401, 0, 0, ARMImpOpBase + 0, 2793, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4137 = t2LDRSBs |
| 6240 | { 4136, 4, 1, 4, 1224, 0, 0, ARMImpOpBase + 0, 2789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4136 = t2LDRSBpci |
| 6241 | { 4135, 5, 1, 4, 400, 0, 0, ARMImpOpBase + 0, 917, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4135 = t2LDRSBi8 |
| 6242 | { 4134, 5, 1, 4, 400, 0, 0, ARMImpOpBase + 0, 917, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4134 = t2LDRSBi12 |
| 6243 | { 4133, 6, 2, 4, 920, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4133 = t2LDRSB_PRE |
| 6244 | { 4132, 6, 2, 4, 415, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4132 = t2LDRSB_POST |
| 6245 | { 4131, 5, 1, 4, 416, 0, 0, ARMImpOpBase + 0, 2784, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4131 = t2LDRSBT |
| 6246 | { 4130, 6, 1, 4, 393, 0, 0, ARMImpOpBase + 0, 2793, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4130 = t2LDRHs |
| 6247 | { 4129, 4, 1, 4, 1223, 0, 0, ARMImpOpBase + 0, 2789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4129 = t2LDRHpci |
| 6248 | { 4128, 5, 1, 4, 392, 0, 0, ARMImpOpBase + 0, 917, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4128 = t2LDRHi8 |
| 6249 | { 4127, 5, 1, 4, 1106, 0, 0, ARMImpOpBase + 0, 917, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4127 = t2LDRHi12 |
| 6250 | { 4126, 6, 2, 4, 919, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4126 = t2LDRH_PRE |
| 6251 | { 4125, 6, 2, 4, 410, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4125 = t2LDRH_POST |
| 6252 | { 4124, 5, 1, 4, 412, 0, 0, ARMImpOpBase + 0, 2784, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4124 = t2LDRHT |
| 6253 | { 4123, 4, 1, 4, 1228, 0, 0, ARMImpOpBase + 0, 2775, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4123 = t2LDREXH |
| 6254 | { 4122, 5, 2, 4, 1025, 0, 0, ARMImpOpBase + 0, 2779, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL }, // Inst #4122 = t2LDREXD |
| 6255 | { 4121, 4, 1, 4, 1228, 0, 0, ARMImpOpBase + 0, 2775, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4121 = t2LDREXB |
| 6256 | { 4120, 5, 1, 4, 1227, 0, 0, ARMImpOpBase + 0, 2812, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc94ULL }, // Inst #4120 = t2LDREX |
| 6257 | { 4119, 6, 2, 4, 417, 0, 0, ARMImpOpBase + 0, 2806, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc91ULL }, // Inst #4119 = t2LDRDi8 |
| 6258 | { 4118, 7, 3, 4, 923, 0, 0, ARMImpOpBase + 0, 2799, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc91ULL }, // Inst #4118 = t2LDRD_PRE |
| 6259 | { 4117, 7, 3, 4, 420, 0, 0, ARMImpOpBase + 0, 2799, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc91ULL }, // Inst #4117 = t2LDRD_POST |
| 6260 | { 4116, 6, 1, 4, 393, 0, 0, ARMImpOpBase + 0, 2793, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4116 = t2LDRBs |
| 6261 | { 4115, 4, 1, 4, 1223, 0, 0, ARMImpOpBase + 0, 2789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4115 = t2LDRBpci |
| 6262 | { 4114, 5, 1, 4, 392, 0, 0, ARMImpOpBase + 0, 917, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4114 = t2LDRBi8 |
| 6263 | { 4113, 5, 1, 4, 1106, 0, 0, ARMImpOpBase + 0, 917, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4113 = t2LDRBi12 |
| 6264 | { 4112, 6, 2, 4, 912, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4112 = t2LDRB_PRE |
| 6265 | { 4111, 6, 2, 4, 929, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4111 = t2LDRB_POST |
| 6266 | { 4110, 5, 1, 4, 412, 0, 0, ARMImpOpBase + 0, 2784, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4110 = t2LDRBT |
| 6267 | { 4109, 5, 1, 4, 1109, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4109 = t2LDMIA_UPD |
| 6268 | { 4108, 4, 0, 4, 1108, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4108 = t2LDMIA |
| 6269 | { 4107, 5, 1, 4, 1109, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4107 = t2LDMDB_UPD |
| 6270 | { 4106, 4, 0, 4, 1108, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4106 = t2LDMDB |
| 6271 | { 4105, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4105 = t2LDC_PRE |
| 6272 | { 4104, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4104 = t2LDC_POST |
| 6273 | { 4103, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 898, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4103 = t2LDC_OPTION |
| 6274 | { 4102, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4102 = t2LDC_OFFSET |
| 6275 | { 4101, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4101 = t2LDCL_PRE |
| 6276 | { 4100, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4100 = t2LDCL_POST |
| 6277 | { 4099, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 898, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4099 = t2LDCL_OPTION |
| 6278 | { 4098, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4098 = t2LDCL_OFFSET |
| 6279 | { 4097, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4097 = t2LDC2_PRE |
| 6280 | { 4096, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4096 = t2LDC2_POST |
| 6281 | { 4095, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 898, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4095 = t2LDC2_OPTION |
| 6282 | { 4094, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4094 = t2LDC2_OFFSET |
| 6283 | { 4093, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4093 = t2LDC2L_PRE |
| 6284 | { 4092, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4092 = t2LDC2L_POST |
| 6285 | { 4091, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 898, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4091 = t2LDC2L_OPTION |
| 6286 | { 4090, 6, 0, 4, 848, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4090 = t2LDC2L_OFFSET |
| 6287 | { 4089, 4, 1, 4, 687, 0, 0, ARMImpOpBase + 0, 2775, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4089 = t2LDAH |
| 6288 | { 4088, 4, 1, 4, 687, 0, 0, ARMImpOpBase + 0, 2775, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4088 = t2LDAEXH |
| 6289 | { 4087, 5, 2, 4, 1264, 0, 0, ARMImpOpBase + 0, 2779, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL }, // Inst #4087 = t2LDAEXD |
| 6290 | { 4086, 4, 1, 4, 687, 0, 0, ARMImpOpBase + 0, 2775, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4086 = t2LDAEXB |
| 6291 | { 4085, 4, 1, 4, 1263, 0, 0, ARMImpOpBase + 0, 2775, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4085 = t2LDAEX |
| 6292 | { 4084, 4, 1, 4, 687, 0, 0, ARMImpOpBase + 0, 2775, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4084 = t2LDAB |
| 6293 | { 4083, 4, 1, 4, 1263, 0, 0, ARMImpOpBase + 0, 2775, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4083 = t2LDA |
| 6294 | { 4082, 2, 0, 12, 1040, 0, 15, ARMImpOpBase + 39, 590, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4082 = t2Int_eh_sjlj_setjmp_nofp |
| 6295 | { 4081, 2, 0, 12, 1040, 0, 27, ARMImpOpBase + 190, 590, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4081 = t2Int_eh_sjlj_setjmp |
| 6296 | { 4080, 2, 0, 2, 457, 0, 1, ARMImpOpBase + 189, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4080 = t2IT |
| 6297 | { 4079, 3, 0, 4, 1095, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4079 = t2ISB |
| 6298 | { 4078, 1, 0, 4, 1218, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4078 = t2HVC |
| 6299 | { 4077, 3, 0, 4, 1037, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4077 = t2HINT |
| 6300 | { 4076, 7, 1, 4, 1239, 0, 0, ARMImpOpBase + 0, 2684, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4076 = t2EORrs |
| 6301 | { 4075, 6, 1, 4, 1273, 0, 0, ARMImpOpBase + 0, 2678, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4075 = t2EORrr |
| 6302 | { 4074, 6, 1, 4, 696, 0, 0, ARMImpOpBase + 0, 2672, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4074 = t2EORri |
| 6303 | { 4073, 3, 0, 4, 1095, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4073 = t2DSB |
| 6304 | { 4072, 3, 0, 4, 1095, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4072 = t2DMB |
| 6305 | { 4071, 2, 1, 4, 1286, 0, 0, ARMImpOpBase + 0, 437, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4071 = t2DLS |
| 6306 | { 4070, 2, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 543, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4070 = t2DCPS3 |
| 6307 | { 4069, 2, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 543, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4069 = t2DCPS2 |
| 6308 | { 4068, 2, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 543, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4068 = t2DCPS1 |
| 6309 | { 4067, 3, 0, 4, 1059, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4067 = t2DBG |
| 6310 | { 4066, 4, 1, 4, 1063, 1, 0, ARMImpOpBase + 0, 2771, 0, 0xc80ULL }, // Inst #4066 = t2CSNEG |
| 6311 | { 4065, 4, 1, 4, 1063, 1, 0, ARMImpOpBase + 0, 2771, 0, 0xc80ULL }, // Inst #4065 = t2CSINV |
| 6312 | { 4064, 4, 1, 4, 1063, 1, 0, ARMImpOpBase + 0, 2771, 0, 0xc80ULL }, // Inst #4064 = t2CSINC |
| 6313 | { 4063, 4, 1, 4, 1063, 1, 0, ARMImpOpBase + 0, 2771, 0, 0xc80ULL }, // Inst #4063 = t2CSEL |
| 6314 | { 4062, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 315, 0, 0xc80ULL }, // Inst #4062 = t2CRC32W |
| 6315 | { 4061, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 315, 0, 0xc80ULL }, // Inst #4061 = t2CRC32H |
| 6316 | { 4060, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 315, 0, 0xc80ULL }, // Inst #4060 = t2CRC32CW |
| 6317 | { 4059, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 315, 0, 0xc80ULL }, // Inst #4059 = t2CRC32CH |
| 6318 | { 4058, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 315, 0, 0xc80ULL }, // Inst #4058 = t2CRC32CB |
| 6319 | { 4057, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 315, 0, 0xc80ULL }, // Inst #4057 = t2CRC32B |
| 6320 | { 4056, 3, 0, 4, 1058, 0, 0, ARMImpOpBase + 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4056 = t2CPS3p |
| 6321 | { 4055, 2, 0, 4, 1058, 0, 0, ARMImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4055 = t2CPS2p |
| 6322 | { 4054, 1, 0, 4, 1058, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4054 = t2CPS1p |
| 6323 | { 4053, 5, 0, 4, 1242, 0, 1, ARMImpOpBase + 0, 2766, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4053 = t2CMPrs |
| 6324 | { 4052, 4, 0, 4, 1069, 0, 1, ARMImpOpBase + 0, 2762, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4052 = t2CMPrr |
| 6325 | { 4051, 4, 0, 4, 1068, 0, 1, ARMImpOpBase + 0, 442, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4051 = t2CMPri |
| 6326 | { 4050, 5, 0, 4, 1241, 0, 1, ARMImpOpBase + 0, 2766, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4050 = t2CMNzrs |
| 6327 | { 4049, 4, 0, 4, 1067, 0, 1, ARMImpOpBase + 0, 2762, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4049 = t2CMNzrr |
| 6328 | { 4048, 4, 0, 4, 55, 0, 1, ARMImpOpBase + 0, 442, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4048 = t2CMNri |
| 6329 | { 4047, 4, 1, 4, 1246, 0, 0, ARMImpOpBase + 0, 2758, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4047 = t2CLZ |
| 6330 | { 4046, 3, 0, 4, 1105, 0, 0, ARMImpOpBase + 0, 587, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4046 = t2CLRM |
| 6331 | { 4045, 2, 0, 4, 1031, 0, 0, ARMImpOpBase + 0, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4045 = t2CLREX |
| 6332 | { 4044, 8, 0, 4, 1034, 0, 0, ARMImpOpBase + 0, 826, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4044 = t2CDP2 |
| 6333 | { 4043, 8, 0, 4, 1034, 0, 0, ARMImpOpBase + 0, 826, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4043 = t2CDP |
| 6334 | { 4042, 3, 0, 4, 854, 0, 0, ARMImpOpBase + 0, 548, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4042 = t2Bcc |
| 6335 | { 4041, 3, 0, 4, 864, 0, 0, ARMImpOpBase + 0, 1062, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4041 = t2BXJ |
| 6336 | { 4040, 5, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 2753, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4040 = t2BXAUT |
| 6337 | { 4039, 0, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4039 = t2BTI |
| 6338 | { 4038, 7, 1, 4, 1239, 0, 0, ARMImpOpBase + 0, 2684, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4038 = t2BICrs |
| 6339 | { 4037, 6, 1, 4, 1273, 0, 0, ARMImpOpBase + 0, 2678, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4037 = t2BICrr |
| 6340 | { 4036, 6, 1, 4, 696, 0, 0, ARMImpOpBase + 0, 2672, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4036 = t2BICri |
| 6341 | { 4035, 4, 0, 4, 1284, 0, 0, ARMImpOpBase + 0, 2745, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4035 = t2BFr |
| 6342 | { 4034, 4, 0, 4, 1284, 0, 0, ARMImpOpBase + 0, 2749, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4034 = t2BFic |
| 6343 | { 4033, 4, 0, 4, 1284, 0, 0, ARMImpOpBase + 0, 2741, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4033 = t2BFi |
| 6344 | { 4032, 4, 0, 4, 1284, 0, 0, ARMImpOpBase + 0, 2745, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4032 = t2BFLr |
| 6345 | { 4031, 4, 0, 4, 1284, 0, 0, ARMImpOpBase + 0, 2741, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4031 = t2BFLi |
| 6346 | { 4030, 6, 1, 4, 360, 0, 0, ARMImpOpBase + 0, 2735, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4030 = t2BFI |
| 6347 | { 4029, 5, 1, 4, 359, 0, 0, ARMImpOpBase + 0, 467, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4029 = t2BFC |
| 6348 | { 4028, 3, 0, 4, 854, 0, 0, ARMImpOpBase + 0, 548, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // Inst #4028 = t2B |
| 6349 | { 4027, 5, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 2730, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4027 = t2AUTG |
| 6350 | { 4026, 0, 0, 4, 0, 3, 0, ARMImpOpBase + 186, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4026 = t2AUT |
| 6351 | { 4025, 6, 1, 4, 1066, 0, 0, ARMImpOpBase + 0, 2678, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4025 = t2ASRrr |
| 6352 | { 4024, 6, 1, 4, 1065, 0, 0, ARMImpOpBase + 0, 2672, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4024 = t2ASRri |
| 6353 | { 4023, 7, 1, 4, 707, 0, 0, ARMImpOpBase + 0, 2684, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4023 = t2ANDrs |
| 6354 | { 4022, 6, 1, 4, 703, 0, 0, ARMImpOpBase + 0, 2678, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4022 = t2ANDrr |
| 6355 | { 4021, 6, 1, 4, 696, 0, 0, ARMImpOpBase + 0, 2672, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4021 = t2ANDri |
| 6356 | { 4020, 4, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 2726, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4020 = t2ADR |
| 6357 | { 4019, 5, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 2721, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4019 = t2ADDspImm12 |
| 6358 | { 4018, 6, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 2715, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4018 = t2ADDspImm |
| 6359 | { 4017, 7, 1, 4, 706, 0, 0, ARMImpOpBase + 0, 2708, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4017 = t2ADDrs |
| 6360 | { 4016, 6, 1, 4, 1064, 0, 0, ARMImpOpBase + 0, 2702, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4016 = t2ADDrr |
| 6361 | { 4015, 5, 1, 4, 1277, 0, 0, ARMImpOpBase + 0, 2697, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4015 = t2ADDri12 |
| 6362 | { 4014, 6, 1, 4, 1276, 0, 0, ARMImpOpBase + 0, 2691, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4014 = t2ADDri |
| 6363 | { 4013, 7, 1, 4, 1269, 1, 1, ARMImpOpBase + 63, 2684, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4013 = t2ADCrs |
| 6364 | { 4012, 6, 1, 4, 1272, 1, 1, ARMImpOpBase + 63, 2678, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4012 = t2ADCrr |
| 6365 | { 4011, 6, 1, 4, 694, 1, 1, ARMImpOpBase + 63, 2672, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4011 = t2ADCri |
| 6366 | { 4010, 5, 1, 4, 452, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #4010 = sysSTMIB_UPD |
| 6367 | { 4009, 4, 0, 4, 451, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #4009 = sysSTMIB |
| 6368 | { 4008, 5, 1, 4, 452, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #4008 = sysSTMIA_UPD |
| 6369 | { 4007, 4, 0, 4, 451, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #4007 = sysSTMIA |
| 6370 | { 4006, 5, 1, 4, 452, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #4006 = sysSTMDB_UPD |
| 6371 | { 4005, 4, 0, 4, 451, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #4005 = sysSTMDB |
| 6372 | { 4004, 5, 1, 4, 452, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #4004 = sysSTMDA_UPD |
| 6373 | { 4003, 4, 0, 4, 451, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #4003 = sysSTMDA |
| 6374 | { 4002, 5, 1, 4, 422, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // Inst #4002 = sysLDMIB_UPD |
| 6375 | { 4001, 4, 0, 4, 421, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // Inst #4001 = sysLDMIB |
| 6376 | { 4000, 5, 1, 4, 422, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // Inst #4000 = sysLDMIA_UPD |
| 6377 | { 3999, 4, 0, 4, 421, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // Inst #3999 = sysLDMIA |
| 6378 | { 3998, 5, 1, 4, 422, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // Inst #3998 = sysLDMDB_UPD |
| 6379 | { 3997, 4, 0, 4, 421, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // Inst #3997 = sysLDMDB |
| 6380 | { 3996, 5, 1, 4, 422, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // Inst #3996 = sysLDMDA_UPD |
| 6381 | { 3995, 4, 0, 4, 421, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // Inst #3995 = sysLDMDA |
| 6382 | { 3994, 6, 2, 4, 516, 0, 0, ARMImpOpBase + 0, 2640, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3994 = VZIPq8 |
| 6383 | { 3993, 6, 2, 4, 516, 0, 0, ARMImpOpBase + 0, 2640, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3993 = VZIPq32 |
| 6384 | { 3992, 6, 2, 4, 516, 0, 0, ARMImpOpBase + 0, 2640, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3992 = VZIPq16 |
| 6385 | { 3991, 6, 2, 4, 514, 0, 0, ARMImpOpBase + 0, 2634, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3991 = VZIPd8 |
| 6386 | { 3990, 6, 2, 4, 514, 0, 0, ARMImpOpBase + 0, 2634, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3990 = VZIPd16 |
| 6387 | { 3989, 6, 2, 4, 516, 0, 0, ARMImpOpBase + 0, 2640, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3989 = VUZPq8 |
| 6388 | { 3988, 6, 2, 4, 516, 0, 0, ARMImpOpBase + 0, 2640, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3988 = VUZPq32 |
| 6389 | { 3987, 6, 2, 4, 516, 0, 0, ARMImpOpBase + 0, 2640, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3987 = VUZPq16 |
| 6390 | { 3986, 6, 2, 4, 514, 0, 0, ARMImpOpBase + 0, 2634, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3986 = VUZPd8 |
| 6391 | { 3985, 6, 2, 4, 514, 0, 0, ARMImpOpBase + 0, 2634, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3985 = VUZPd16 |
| 6392 | { 3984, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #3984 = VUSMMLA |
| 6393 | { 3983, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #3983 = VUSDOTQI |
| 6394 | { 3982, 4, 1, 4, 50, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #3982 = VUSDOTQ |
| 6395 | { 3981, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 630, 0, 0x11280ULL }, // Inst #3981 = VUSDOTDI |
| 6396 | { 3980, 4, 1, 4, 50, 0, 0, ARMImpOpBase + 0, 640, 0, 0x11280ULL }, // Inst #3980 = VUSDOTD |
| 6397 | { 3979, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #3979 = VUMMLA |
| 6398 | { 3978, 5, 1, 4, 222, 0, 0, ARMImpOpBase + 0, 2390, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3978 = VULTOS |
| 6399 | { 3977, 5, 1, 4, 221, 0, 0, ARMImpOpBase + 0, 2390, 0, 0x8880ULL }, // Inst #3977 = VULTOH |
| 6400 | { 3976, 5, 1, 4, 1289, 0, 0, ARMImpOpBase + 0, 2385, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3976 = VULTOD |
| 6401 | { 3975, 4, 1, 4, 564, 0, 0, ARMImpOpBase + 0, 1686, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3975 = VUITOS |
| 6402 | { 3974, 4, 1, 4, 563, 0, 0, ARMImpOpBase + 0, 2395, 0, 0x8880ULL }, // Inst #3974 = VUITOH |
| 6403 | { 3973, 4, 1, 4, 562, 0, 0, ARMImpOpBase + 0, 1805, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3973 = VUITOD |
| 6404 | { 3972, 5, 1, 4, 222, 0, 0, ARMImpOpBase + 0, 2390, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3972 = VUHTOS |
| 6405 | { 3971, 5, 1, 4, 221, 0, 0, ARMImpOpBase + 0, 2390, 0, 0x8880ULL }, // Inst #3971 = VUHTOH |
| 6406 | { 3970, 5, 1, 4, 1289, 0, 0, ARMImpOpBase + 0, 2385, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3970 = VUHTOD |
| 6407 | { 3969, 5, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #3969 = VUDOTQI |
| 6408 | { 3968, 4, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #3968 = VUDOTQ |
| 6409 | { 3967, 5, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 630, 0, 0x11280ULL }, // Inst #3967 = VUDOTDI |
| 6410 | { 3966, 4, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 640, 0, 0x11280ULL }, // Inst #3966 = VUDOTD |
| 6411 | { 3965, 5, 1, 4, 468, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3965 = VTSTv8i8 |
| 6412 | { 3964, 5, 1, 4, 467, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3964 = VTSTv8i16 |
| 6413 | { 3963, 5, 1, 4, 467, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3963 = VTSTv4i32 |
| 6414 | { 3962, 5, 1, 4, 468, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3962 = VTSTv4i16 |
| 6415 | { 3961, 5, 1, 4, 468, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3961 = VTSTv2i32 |
| 6416 | { 3960, 5, 1, 4, 467, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3960 = VTSTv16i8 |
| 6417 | { 3959, 6, 2, 4, 515, 0, 0, ARMImpOpBase + 0, 2640, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3959 = VTRNq8 |
| 6418 | { 3958, 6, 2, 4, 515, 0, 0, ARMImpOpBase + 0, 2640, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3958 = VTRNq32 |
| 6419 | { 3957, 6, 2, 4, 515, 0, 0, ARMImpOpBase + 0, 2640, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3957 = VTRNq16 |
| 6420 | { 3956, 6, 2, 4, 1002, 0, 0, ARMImpOpBase + 0, 2634, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3956 = VTRNd8 |
| 6421 | { 3955, 6, 2, 4, 1002, 0, 0, ARMImpOpBase + 0, 2634, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3955 = VTRNd32 |
| 6422 | { 3954, 6, 2, 4, 1002, 0, 0, ARMImpOpBase + 0, 2634, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3954 = VTRNd16 |
| 6423 | { 3953, 5, 1, 4, 959, 0, 0, ARMImpOpBase + 0, 2390, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3953 = VTOULS |
| 6424 | { 3952, 5, 1, 4, 566, 0, 0, ARMImpOpBase + 0, 2390, 0, 0x8880ULL }, // Inst #3952 = VTOULH |
| 6425 | { 3951, 5, 1, 4, 565, 0, 0, ARMImpOpBase + 0, 2385, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3951 = VTOULD |
| 6426 | { 3950, 4, 1, 4, 567, 0, 0, ARMImpOpBase + 0, 1686, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3950 = VTOUIZS |
| 6427 | { 3949, 4, 1, 4, 566, 0, 0, ARMImpOpBase + 0, 2668, 0, 0x8880ULL }, // Inst #3949 = VTOUIZH |
| 6428 | { 3948, 4, 1, 4, 565, 0, 0, ARMImpOpBase + 0, 1809, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3948 = VTOUIZD |
| 6429 | { 3947, 4, 1, 4, 567, 1, 0, ARMImpOpBase + 71, 1686, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3947 = VTOUIRS |
| 6430 | { 3946, 4, 1, 4, 566, 1, 0, ARMImpOpBase + 71, 1686, 0, 0x8880ULL }, // Inst #3946 = VTOUIRH |
| 6431 | { 3945, 4, 1, 4, 565, 1, 0, ARMImpOpBase + 71, 1809, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3945 = VTOUIRD |
| 6432 | { 3944, 5, 1, 4, 959, 0, 0, ARMImpOpBase + 0, 2390, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3944 = VTOUHS |
| 6433 | { 3943, 5, 1, 4, 566, 0, 0, ARMImpOpBase + 0, 2390, 0, 0x8880ULL }, // Inst #3943 = VTOUHH |
| 6434 | { 3942, 5, 1, 4, 565, 0, 0, ARMImpOpBase + 0, 2385, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3942 = VTOUHD |
| 6435 | { 3941, 5, 1, 4, 959, 0, 0, ARMImpOpBase + 0, 2390, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3941 = VTOSLS |
| 6436 | { 3940, 5, 1, 4, 566, 0, 0, ARMImpOpBase + 0, 2390, 0, 0x8880ULL }, // Inst #3940 = VTOSLH |
| 6437 | { 3939, 5, 1, 4, 565, 0, 0, ARMImpOpBase + 0, 2385, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3939 = VTOSLD |
| 6438 | { 3938, 4, 1, 4, 567, 0, 0, ARMImpOpBase + 0, 1686, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3938 = VTOSIZS |
| 6439 | { 3937, 4, 1, 4, 566, 0, 0, ARMImpOpBase + 0, 2668, 0, 0x8880ULL }, // Inst #3937 = VTOSIZH |
| 6440 | { 3936, 4, 1, 4, 565, 0, 0, ARMImpOpBase + 0, 1809, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3936 = VTOSIZD |
| 6441 | { 3935, 4, 1, 4, 567, 1, 0, ARMImpOpBase + 71, 1686, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3935 = VTOSIRS |
| 6442 | { 3934, 4, 1, 4, 566, 1, 0, ARMImpOpBase + 71, 1686, 0, 0x8880ULL }, // Inst #3934 = VTOSIRH |
| 6443 | { 3933, 4, 1, 4, 565, 1, 0, ARMImpOpBase + 71, 1809, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3933 = VTOSIRD |
| 6444 | { 3932, 5, 1, 4, 567, 0, 0, ARMImpOpBase + 0, 2390, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3932 = VTOSHS |
| 6445 | { 3931, 5, 1, 4, 566, 0, 0, ARMImpOpBase + 0, 2390, 0, 0x8880ULL }, // Inst #3931 = VTOSHH |
| 6446 | { 3930, 5, 1, 4, 565, 0, 0, ARMImpOpBase + 0, 2385, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3930 = VTOSHD |
| 6447 | { 3929, 6, 1, 4, 512, 0, 0, ARMImpOpBase + 0, 2662, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // Inst #3929 = VTBX4Pseudo |
| 6448 | { 3928, 6, 1, 4, 512, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3928 = VTBX4 |
| 6449 | { 3927, 6, 1, 4, 510, 0, 0, ARMImpOpBase + 0, 2662, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // Inst #3927 = VTBX3Pseudo |
| 6450 | { 3926, 6, 1, 4, 510, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3926 = VTBX3 |
| 6451 | { 3925, 6, 1, 4, 508, 0, 0, ARMImpOpBase + 0, 2656, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3925 = VTBX2 |
| 6452 | { 3924, 6, 1, 4, 506, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11480ULL }, // Inst #3924 = VTBX1 |
| 6453 | { 3923, 5, 1, 4, 511, 0, 0, ARMImpOpBase + 0, 2651, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // Inst #3923 = VTBL4Pseudo |
| 6454 | { 3922, 5, 1, 4, 511, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3922 = VTBL4 |
| 6455 | { 3921, 5, 1, 4, 509, 0, 0, ARMImpOpBase + 0, 2651, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // Inst #3921 = VTBL3Pseudo |
| 6456 | { 3920, 5, 1, 4, 509, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3920 = VTBL3 |
| 6457 | { 3919, 5, 1, 4, 507, 0, 0, ARMImpOpBase + 0, 2646, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3919 = VTBL2 |
| 6458 | { 3918, 5, 1, 4, 505, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11480ULL }, // Inst #3918 = VTBL1 |
| 6459 | { 3917, 6, 2, 4, 513, 0, 0, ARMImpOpBase + 0, 2640, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3917 = VSWPq |
| 6460 | { 3916, 6, 2, 4, 513, 0, 0, ARMImpOpBase + 0, 2634, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3916 = VSWPd |
| 6461 | { 3915, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #3915 = VSUDOTQI |
| 6462 | { 3914, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 630, 0, 0x11280ULL }, // Inst #3914 = VSUDOTDI |
| 6463 | { 3913, 5, 1, 4, 757, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3913 = VSUBv8i8 |
| 6464 | { 3912, 5, 1, 4, 461, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3912 = VSUBv8i16 |
| 6465 | { 3911, 5, 1, 4, 461, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3911 = VSUBv4i32 |
| 6466 | { 3910, 5, 1, 4, 757, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3910 = VSUBv4i16 |
| 6467 | { 3909, 5, 1, 4, 461, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3909 = VSUBv2i64 |
| 6468 | { 3908, 5, 1, 4, 757, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3908 = VSUBv2i32 |
| 6469 | { 3907, 5, 1, 4, 757, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3907 = VSUBv1i64 |
| 6470 | { 3906, 5, 1, 4, 461, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3906 = VSUBv16i8 |
| 6471 | { 3905, 5, 1, 4, 747, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3905 = VSUBhq |
| 6472 | { 3904, 5, 1, 4, 745, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3904 = VSUBhd |
| 6473 | { 3903, 5, 1, 4, 746, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3903 = VSUBfq |
| 6474 | { 3902, 5, 1, 4, 744, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3902 = VSUBfd |
| 6475 | { 3901, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1709, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3901 = VSUBWuv8i16 |
| 6476 | { 3900, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1709, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3900 = VSUBWuv4i32 |
| 6477 | { 3899, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1709, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3899 = VSUBWuv2i64 |
| 6478 | { 3898, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1709, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3898 = VSUBWsv8i16 |
| 6479 | { 3897, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1709, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3897 = VSUBWsv4i32 |
| 6480 | { 3896, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1709, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3896 = VSUBWsv2i64 |
| 6481 | { 3895, 5, 1, 4, 521, 0, 0, ARMImpOpBase + 0, 1704, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3895 = VSUBS |
| 6482 | { 3894, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3894 = VSUBLuv8i16 |
| 6483 | { 3893, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3893 = VSUBLuv4i32 |
| 6484 | { 3892, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3892 = VSUBLuv2i64 |
| 6485 | { 3891, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3891 = VSUBLsv8i16 |
| 6486 | { 3890, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3890 = VSUBLsv4i32 |
| 6487 | { 3889, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3889 = VSUBLsv2i64 |
| 6488 | { 3888, 5, 1, 4, 501, 0, 0, ARMImpOpBase + 0, 1699, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3888 = VSUBHNv8i8 |
| 6489 | { 3887, 5, 1, 4, 501, 0, 0, ARMImpOpBase + 0, 1699, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3887 = VSUBHNv4i16 |
| 6490 | { 3886, 5, 1, 4, 501, 0, 0, ARMImpOpBase + 0, 1699, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3886 = VSUBHNv2i32 |
| 6491 | { 3885, 5, 1, 4, 743, 0, 0, ARMImpOpBase + 0, 1694, 0, 0x8800ULL }, // Inst #3885 = VSUBH |
| 6492 | { 3884, 5, 1, 4, 527, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3884 = VSUBD |
| 6493 | { 3883, 5, 1, 4, 751, 1, 0, ARMImpOpBase + 69, 2189, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3883 = VSTR_VPR_pre |
| 6494 | { 3882, 5, 1, 4, 751, 1, 0, ARMImpOpBase + 69, 2189, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3882 = VSTR_VPR_post |
| 6495 | { 3881, 4, 0, 4, 751, 1, 0, ARMImpOpBase + 69, 2185, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3881 = VSTR_VPR_off |
| 6496 | { 3880, 6, 1, 4, 751, 0, 0, ARMImpOpBase + 0, 2628, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3880 = VSTR_P0_pre |
| 6497 | { 3879, 6, 1, 4, 751, 0, 0, ARMImpOpBase + 0, 2628, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3879 = VSTR_P0_post |
| 6498 | { 3878, 5, 0, 4, 751, 0, 0, ARMImpOpBase + 0, 2194, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3878 = VSTR_P0_off |
| 6499 | { 3877, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3877 = VSTR_FPSCR_pre |
| 6500 | { 3876, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3876 = VSTR_FPSCR_post |
| 6501 | { 3875, 4, 0, 4, 751, 0, 1, ARMImpOpBase + 71, 2185, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3875 = VSTR_FPSCR_off |
| 6502 | { 3874, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3874 = VSTR_FPSCR_NZCVQC_pre |
| 6503 | { 3873, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3873 = VSTR_FPSCR_NZCVQC_post |
| 6504 | { 3872, 4, 0, 4, 751, 0, 1, ARMImpOpBase + 71, 2185, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3872 = VSTR_FPSCR_NZCVQC_off |
| 6505 | { 3871, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3871 = VSTR_FPCXTS_pre |
| 6506 | { 3870, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3870 = VSTR_FPCXTS_post |
| 6507 | { 3869, 4, 0, 4, 751, 0, 1, ARMImpOpBase + 71, 2185, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3869 = VSTR_FPCXTS_off |
| 6508 | { 3868, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3868 = VSTR_FPCXTNS_pre |
| 6509 | { 3867, 5, 1, 4, 751, 0, 1, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3867 = VSTR_FPCXTNS_post |
| 6510 | { 3866, 4, 0, 4, 751, 0, 1, ARMImpOpBase + 71, 2185, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3866 = VSTR_FPCXTNS_off |
| 6511 | { 3865, 5, 0, 4, 592, 0, 0, ARMImpOpBase + 0, 2180, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL }, // Inst #3865 = VSTRS |
| 6512 | { 3864, 5, 0, 4, 750, 0, 0, ARMImpOpBase + 0, 2175, 0|(1ULL<<MCID::MayStore), 0x18b13ULL }, // Inst #3864 = VSTRH |
| 6513 | { 3863, 5, 0, 4, 591, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL }, // Inst #3863 = VSTRD |
| 6514 | { 3862, 5, 1, 4, 971, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL }, // Inst #3862 = VSTMSIA_UPD |
| 6515 | { 3861, 4, 0, 4, 970, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18b84ULL }, // Inst #3861 = VSTMSIA |
| 6516 | { 3860, 5, 1, 4, 971, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL }, // Inst #3860 = VSTMSDB_UPD |
| 6517 | { 3859, 4, 0, 4, 594, 0, 0, ARMImpOpBase + 0, 2171, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18004ULL }, // Inst #3859 = VSTMQIA |
| 6518 | { 3858, 5, 1, 4, 598, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL }, // Inst #3858 = VSTMDIA_UPD |
| 6519 | { 3857, 4, 0, 4, 597, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8b84ULL }, // Inst #3857 = VSTMDIA |
| 6520 | { 3856, 5, 1, 4, 598, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL }, // Inst #3856 = VSTMDDB_UPD |
| 6521 | { 3855, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3855 = VST4q8oddPseudo_UPD |
| 6522 | { 3854, 5, 0, 4, 662, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3854 = VST4q8oddPseudo |
| 6523 | { 3853, 10, 1, 4, 838, 0, 0, ARMImpOpBase + 0, 2618, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3853 = VST4q8_UPD |
| 6524 | { 3852, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3852 = VST4q8Pseudo_UPD |
| 6525 | { 3851, 8, 0, 4, 830, 0, 0, ARMImpOpBase + 0, 2610, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3851 = VST4q8 |
| 6526 | { 3850, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3850 = VST4q32oddPseudo_UPD |
| 6527 | { 3849, 5, 0, 4, 662, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3849 = VST4q32oddPseudo |
| 6528 | { 3848, 10, 1, 4, 838, 0, 0, ARMImpOpBase + 0, 2618, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3848 = VST4q32_UPD |
| 6529 | { 3847, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3847 = VST4q32Pseudo_UPD |
| 6530 | { 3846, 8, 0, 4, 830, 0, 0, ARMImpOpBase + 0, 2610, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3846 = VST4q32 |
| 6531 | { 3845, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3845 = VST4q16oddPseudo_UPD |
| 6532 | { 3844, 5, 0, 4, 662, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3844 = VST4q16oddPseudo |
| 6533 | { 3843, 10, 1, 4, 838, 0, 0, ARMImpOpBase + 0, 2618, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3843 = VST4q16_UPD |
| 6534 | { 3842, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3842 = VST4q16Pseudo_UPD |
| 6535 | { 3841, 8, 0, 4, 830, 0, 0, ARMImpOpBase + 0, 2610, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3841 = VST4q16 |
| 6536 | { 3840, 10, 1, 4, 838, 0, 0, ARMImpOpBase + 0, 2618, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3840 = VST4d8_UPD |
| 6537 | { 3839, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3839 = VST4d8Pseudo_UPD |
| 6538 | { 3838, 5, 0, 4, 832, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3838 = VST4d8Pseudo |
| 6539 | { 3837, 8, 0, 4, 830, 0, 0, ARMImpOpBase + 0, 2610, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3837 = VST4d8 |
| 6540 | { 3836, 10, 1, 4, 838, 0, 0, ARMImpOpBase + 0, 2618, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3836 = VST4d32_UPD |
| 6541 | { 3835, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3835 = VST4d32Pseudo_UPD |
| 6542 | { 3834, 5, 0, 4, 832, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3834 = VST4d32Pseudo |
| 6543 | { 3833, 8, 0, 4, 830, 0, 0, ARMImpOpBase + 0, 2610, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3833 = VST4d32 |
| 6544 | { 3832, 10, 1, 4, 838, 0, 0, ARMImpOpBase + 0, 2618, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3832 = VST4d16_UPD |
| 6545 | { 3831, 7, 1, 4, 663, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3831 = VST4d16Pseudo_UPD |
| 6546 | { 3830, 5, 0, 4, 832, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3830 = VST4d16Pseudo |
| 6547 | { 3829, 8, 0, 4, 830, 0, 0, ARMImpOpBase + 0, 2610, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3829 = VST4d16 |
| 6548 | { 3828, 11, 1, 4, 674, 0, 0, ARMImpOpBase + 0, 2599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3828 = VST4LNq32_UPD |
| 6549 | { 3827, 8, 1, 4, 675, 0, 0, ARMImpOpBase + 0, 2566, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3827 = VST4LNq32Pseudo_UPD |
| 6550 | { 3826, 6, 0, 4, 673, 0, 0, ARMImpOpBase + 0, 2560, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3826 = VST4LNq32Pseudo |
| 6551 | { 3825, 9, 0, 4, 836, 0, 0, ARMImpOpBase + 0, 2590, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3825 = VST4LNq32 |
| 6552 | { 3824, 11, 1, 4, 674, 0, 0, ARMImpOpBase + 0, 2599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3824 = VST4LNq16_UPD |
| 6553 | { 3823, 8, 1, 4, 675, 0, 0, ARMImpOpBase + 0, 2566, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3823 = VST4LNq16Pseudo_UPD |
| 6554 | { 3822, 6, 0, 4, 673, 0, 0, ARMImpOpBase + 0, 2560, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3822 = VST4LNq16Pseudo |
| 6555 | { 3821, 9, 0, 4, 836, 0, 0, ARMImpOpBase + 0, 2590, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3821 = VST4LNq16 |
| 6556 | { 3820, 11, 1, 4, 840, 0, 0, ARMImpOpBase + 0, 2599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3820 = VST4LNd8_UPD |
| 6557 | { 3819, 8, 1, 4, 842, 0, 0, ARMImpOpBase + 0, 2527, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3819 = VST4LNd8Pseudo_UPD |
| 6558 | { 3818, 6, 0, 4, 835, 0, 0, ARMImpOpBase + 0, 2521, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3818 = VST4LNd8Pseudo |
| 6559 | { 3817, 9, 0, 4, 833, 0, 0, ARMImpOpBase + 0, 2590, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3817 = VST4LNd8 |
| 6560 | { 3816, 11, 1, 4, 840, 0, 0, ARMImpOpBase + 0, 2599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3816 = VST4LNd32_UPD |
| 6561 | { 3815, 8, 1, 4, 842, 0, 0, ARMImpOpBase + 0, 2527, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3815 = VST4LNd32Pseudo_UPD |
| 6562 | { 3814, 6, 0, 4, 835, 0, 0, ARMImpOpBase + 0, 2521, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3814 = VST4LNd32Pseudo |
| 6563 | { 3813, 9, 0, 4, 833, 0, 0, ARMImpOpBase + 0, 2590, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3813 = VST4LNd32 |
| 6564 | { 3812, 11, 1, 4, 840, 0, 0, ARMImpOpBase + 0, 2599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3812 = VST4LNd16_UPD |
| 6565 | { 3811, 8, 1, 4, 842, 0, 0, ARMImpOpBase + 0, 2527, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3811 = VST4LNd16Pseudo_UPD |
| 6566 | { 3810, 6, 0, 4, 835, 0, 0, ARMImpOpBase + 0, 2521, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3810 = VST4LNd16Pseudo |
| 6567 | { 3809, 9, 0, 4, 833, 0, 0, ARMImpOpBase + 0, 2590, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3809 = VST4LNd16 |
| 6568 | { 3808, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3808 = VST3q8oddPseudo_UPD |
| 6569 | { 3807, 5, 0, 4, 660, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3807 = VST3q8oddPseudo |
| 6570 | { 3806, 9, 1, 4, 824, 0, 0, ARMImpOpBase + 0, 2581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3806 = VST3q8_UPD |
| 6571 | { 3805, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3805 = VST3q8Pseudo_UPD |
| 6572 | { 3804, 7, 0, 4, 817, 0, 0, ARMImpOpBase + 0, 2574, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3804 = VST3q8 |
| 6573 | { 3803, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3803 = VST3q32oddPseudo_UPD |
| 6574 | { 3802, 5, 0, 4, 660, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3802 = VST3q32oddPseudo |
| 6575 | { 3801, 9, 1, 4, 824, 0, 0, ARMImpOpBase + 0, 2581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3801 = VST3q32_UPD |
| 6576 | { 3800, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3800 = VST3q32Pseudo_UPD |
| 6577 | { 3799, 7, 0, 4, 817, 0, 0, ARMImpOpBase + 0, 2574, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3799 = VST3q32 |
| 6578 | { 3798, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3798 = VST3q16oddPseudo_UPD |
| 6579 | { 3797, 5, 0, 4, 660, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3797 = VST3q16oddPseudo |
| 6580 | { 3796, 9, 1, 4, 824, 0, 0, ARMImpOpBase + 0, 2581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3796 = VST3q16_UPD |
| 6581 | { 3795, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3795 = VST3q16Pseudo_UPD |
| 6582 | { 3794, 7, 0, 4, 817, 0, 0, ARMImpOpBase + 0, 2574, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3794 = VST3q16 |
| 6583 | { 3793, 9, 1, 4, 824, 0, 0, ARMImpOpBase + 0, 2581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3793 = VST3d8_UPD |
| 6584 | { 3792, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3792 = VST3d8Pseudo_UPD |
| 6585 | { 3791, 5, 0, 4, 819, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3791 = VST3d8Pseudo |
| 6586 | { 3790, 7, 0, 4, 817, 0, 0, ARMImpOpBase + 0, 2574, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3790 = VST3d8 |
| 6587 | { 3789, 9, 1, 4, 824, 0, 0, ARMImpOpBase + 0, 2581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3789 = VST3d32_UPD |
| 6588 | { 3788, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3788 = VST3d32Pseudo_UPD |
| 6589 | { 3787, 5, 0, 4, 819, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3787 = VST3d32Pseudo |
| 6590 | { 3786, 7, 0, 4, 817, 0, 0, ARMImpOpBase + 0, 2574, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3786 = VST3d32 |
| 6591 | { 3785, 9, 1, 4, 824, 0, 0, ARMImpOpBase + 0, 2581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3785 = VST3d16_UPD |
| 6592 | { 3784, 7, 1, 4, 661, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3784 = VST3d16Pseudo_UPD |
| 6593 | { 3783, 5, 0, 4, 819, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3783 = VST3d16Pseudo |
| 6594 | { 3782, 7, 0, 4, 817, 0, 0, ARMImpOpBase + 0, 2574, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3782 = VST3d16 |
| 6595 | { 3781, 10, 1, 4, 671, 0, 0, ARMImpOpBase + 0, 2550, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3781 = VST3LNq32_UPD |
| 6596 | { 3780, 8, 1, 4, 672, 0, 0, ARMImpOpBase + 0, 2566, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3780 = VST3LNq32Pseudo_UPD |
| 6597 | { 3779, 6, 0, 4, 670, 0, 0, ARMImpOpBase + 0, 2560, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3779 = VST3LNq32Pseudo |
| 6598 | { 3778, 8, 0, 4, 669, 0, 0, ARMImpOpBase + 0, 2542, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3778 = VST3LNq32 |
| 6599 | { 3777, 10, 1, 4, 671, 0, 0, ARMImpOpBase + 0, 2550, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3777 = VST3LNq16_UPD |
| 6600 | { 3776, 8, 1, 4, 672, 0, 0, ARMImpOpBase + 0, 2566, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3776 = VST3LNq16Pseudo_UPD |
| 6601 | { 3775, 6, 0, 4, 670, 0, 0, ARMImpOpBase + 0, 2560, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3775 = VST3LNq16Pseudo |
| 6602 | { 3774, 8, 0, 4, 669, 0, 0, ARMImpOpBase + 0, 2542, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3774 = VST3LNq16 |
| 6603 | { 3773, 10, 1, 4, 826, 0, 0, ARMImpOpBase + 0, 2550, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3773 = VST3LNd8_UPD |
| 6604 | { 3772, 8, 1, 4, 828, 0, 0, ARMImpOpBase + 0, 2527, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3772 = VST3LNd8Pseudo_UPD |
| 6605 | { 3771, 6, 0, 4, 822, 0, 0, ARMImpOpBase + 0, 2521, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3771 = VST3LNd8Pseudo |
| 6606 | { 3770, 8, 0, 4, 820, 0, 0, ARMImpOpBase + 0, 2542, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3770 = VST3LNd8 |
| 6607 | { 3769, 10, 1, 4, 826, 0, 0, ARMImpOpBase + 0, 2550, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3769 = VST3LNd32_UPD |
| 6608 | { 3768, 8, 1, 4, 828, 0, 0, ARMImpOpBase + 0, 2527, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3768 = VST3LNd32Pseudo_UPD |
| 6609 | { 3767, 6, 0, 4, 822, 0, 0, ARMImpOpBase + 0, 2521, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3767 = VST3LNd32Pseudo |
| 6610 | { 3766, 8, 0, 4, 820, 0, 0, ARMImpOpBase + 0, 2542, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3766 = VST3LNd32 |
| 6611 | { 3765, 10, 1, 4, 826, 0, 0, ARMImpOpBase + 0, 2550, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3765 = VST3LNd16_UPD |
| 6612 | { 3764, 8, 1, 4, 828, 0, 0, ARMImpOpBase + 0, 2527, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3764 = VST3LNd16Pseudo_UPD |
| 6613 | { 3763, 6, 0, 4, 822, 0, 0, ARMImpOpBase + 0, 2521, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3763 = VST3LNd16Pseudo |
| 6614 | { 3762, 8, 0, 4, 820, 0, 0, ARMImpOpBase + 0, 2542, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3762 = VST3LNd16 |
| 6615 | { 3761, 7, 1, 4, 658, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3761 = VST2q8wb_register |
| 6616 | { 3760, 6, 1, 4, 658, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3760 = VST2q8wb_fixed |
| 6617 | { 3759, 7, 1, 4, 659, 0, 0, ARMImpOpBase + 0, 2535, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3759 = VST2q8PseudoWB_register |
| 6618 | { 3758, 6, 1, 4, 659, 0, 0, ARMImpOpBase + 0, 2449, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3758 = VST2q8PseudoWB_fixed |
| 6619 | { 3757, 5, 0, 4, 657, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3757 = VST2q8Pseudo |
| 6620 | { 3756, 5, 0, 4, 807, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3756 = VST2q8 |
| 6621 | { 3755, 7, 1, 4, 658, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3755 = VST2q32wb_register |
| 6622 | { 3754, 6, 1, 4, 658, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3754 = VST2q32wb_fixed |
| 6623 | { 3753, 7, 1, 4, 659, 0, 0, ARMImpOpBase + 0, 2535, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3753 = VST2q32PseudoWB_register |
| 6624 | { 3752, 6, 1, 4, 659, 0, 0, ARMImpOpBase + 0, 2449, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3752 = VST2q32PseudoWB_fixed |
| 6625 | { 3751, 5, 0, 4, 657, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3751 = VST2q32Pseudo |
| 6626 | { 3750, 5, 0, 4, 807, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3750 = VST2q32 |
| 6627 | { 3749, 7, 1, 4, 658, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3749 = VST2q16wb_register |
| 6628 | { 3748, 6, 1, 4, 658, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3748 = VST2q16wb_fixed |
| 6629 | { 3747, 7, 1, 4, 659, 0, 0, ARMImpOpBase + 0, 2535, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3747 = VST2q16PseudoWB_register |
| 6630 | { 3746, 6, 1, 4, 659, 0, 0, ARMImpOpBase + 0, 2449, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3746 = VST2q16PseudoWB_fixed |
| 6631 | { 3745, 5, 0, 4, 657, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3745 = VST2q16Pseudo |
| 6632 | { 3744, 5, 0, 4, 807, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3744 = VST2q16 |
| 6633 | { 3743, 7, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2498, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3743 = VST2d8wb_register |
| 6634 | { 3742, 6, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2492, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3742 = VST2d8wb_fixed |
| 6635 | { 3741, 5, 0, 4, 655, 0, 0, ARMImpOpBase + 0, 2475, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3741 = VST2d8 |
| 6636 | { 3740, 7, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2498, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3740 = VST2d32wb_register |
| 6637 | { 3739, 6, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2492, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3739 = VST2d32wb_fixed |
| 6638 | { 3738, 5, 0, 4, 655, 0, 0, ARMImpOpBase + 0, 2475, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3738 = VST2d32 |
| 6639 | { 3737, 7, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2498, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3737 = VST2d16wb_register |
| 6640 | { 3736, 6, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2492, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3736 = VST2d16wb_fixed |
| 6641 | { 3735, 5, 0, 4, 655, 0, 0, ARMImpOpBase + 0, 2475, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3735 = VST2d16 |
| 6642 | { 3734, 7, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2498, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3734 = VST2b8wb_register |
| 6643 | { 3733, 6, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2492, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3733 = VST2b8wb_fixed |
| 6644 | { 3732, 5, 0, 4, 654, 0, 0, ARMImpOpBase + 0, 2475, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3732 = VST2b8 |
| 6645 | { 3731, 7, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2498, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3731 = VST2b32wb_register |
| 6646 | { 3730, 6, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2492, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3730 = VST2b32wb_fixed |
| 6647 | { 3729, 5, 0, 4, 654, 0, 0, ARMImpOpBase + 0, 2475, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3729 = VST2b32 |
| 6648 | { 3728, 7, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2498, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3728 = VST2b16wb_register |
| 6649 | { 3727, 6, 1, 4, 656, 0, 0, ARMImpOpBase + 0, 2492, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3727 = VST2b16wb_fixed |
| 6650 | { 3726, 5, 0, 4, 654, 0, 0, ARMImpOpBase + 0, 2475, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3726 = VST2b16 |
| 6651 | { 3725, 9, 1, 4, 667, 0, 0, ARMImpOpBase + 0, 2512, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3725 = VST2LNq32_UPD |
| 6652 | { 3724, 8, 1, 4, 668, 0, 0, ARMImpOpBase + 0, 2527, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3724 = VST2LNq32Pseudo_UPD |
| 6653 | { 3723, 6, 0, 4, 666, 0, 0, ARMImpOpBase + 0, 2521, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3723 = VST2LNq32Pseudo |
| 6654 | { 3722, 7, 0, 4, 811, 0, 0, ARMImpOpBase + 0, 2505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3722 = VST2LNq32 |
| 6655 | { 3721, 9, 1, 4, 667, 0, 0, ARMImpOpBase + 0, 2512, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3721 = VST2LNq16_UPD |
| 6656 | { 3720, 8, 1, 4, 668, 0, 0, ARMImpOpBase + 0, 2527, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3720 = VST2LNq16Pseudo_UPD |
| 6657 | { 3719, 6, 0, 4, 666, 0, 0, ARMImpOpBase + 0, 2521, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3719 = VST2LNq16Pseudo |
| 6658 | { 3718, 7, 0, 4, 811, 0, 0, ARMImpOpBase + 0, 2505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3718 = VST2LNq16 |
| 6659 | { 3717, 9, 1, 4, 813, 0, 0, ARMImpOpBase + 0, 2512, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3717 = VST2LNd8_UPD |
| 6660 | { 3716, 8, 1, 4, 815, 0, 0, ARMImpOpBase + 0, 2431, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3716 = VST2LNd8Pseudo_UPD |
| 6661 | { 3715, 6, 0, 4, 810, 0, 0, ARMImpOpBase + 0, 2425, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3715 = VST2LNd8Pseudo |
| 6662 | { 3714, 7, 0, 4, 808, 0, 0, ARMImpOpBase + 0, 2505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3714 = VST2LNd8 |
| 6663 | { 3713, 9, 1, 4, 813, 0, 0, ARMImpOpBase + 0, 2512, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3713 = VST2LNd32_UPD |
| 6664 | { 3712, 8, 1, 4, 815, 0, 0, ARMImpOpBase + 0, 2431, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3712 = VST2LNd32Pseudo_UPD |
| 6665 | { 3711, 6, 0, 4, 810, 0, 0, ARMImpOpBase + 0, 2425, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3711 = VST2LNd32Pseudo |
| 6666 | { 3710, 7, 0, 4, 808, 0, 0, ARMImpOpBase + 0, 2505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3710 = VST2LNd32 |
| 6667 | { 3709, 9, 1, 4, 813, 0, 0, ARMImpOpBase + 0, 2512, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3709 = VST2LNd16_UPD |
| 6668 | { 3708, 8, 1, 4, 815, 0, 0, ARMImpOpBase + 0, 2431, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3708 = VST2LNd16Pseudo_UPD |
| 6669 | { 3707, 6, 0, 4, 810, 0, 0, ARMImpOpBase + 0, 2425, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3707 = VST2LNd16Pseudo |
| 6670 | { 3706, 7, 0, 4, 808, 0, 0, ARMImpOpBase + 0, 2505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3706 = VST2LNd16 |
| 6671 | { 3705, 7, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2498, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3705 = VST1q8wb_register |
| 6672 | { 3704, 6, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2492, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3704 = VST1q8wb_fixed |
| 6673 | { 3703, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3703 = VST1q8LowTPseudo_UPD |
| 6674 | { 3702, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3702 = VST1q8LowQPseudo_UPD |
| 6675 | { 3701, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3701 = VST1q8HighTPseudo_UPD |
| 6676 | { 3700, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3700 = VST1q8HighTPseudo |
| 6677 | { 3699, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3699 = VST1q8HighQPseudo_UPD |
| 6678 | { 3698, 5, 0, 4, 1056, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3698 = VST1q8HighQPseudo |
| 6679 | { 3697, 5, 0, 4, 645, 0, 0, ARMImpOpBase + 0, 2475, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3697 = VST1q8 |
| 6680 | { 3696, 7, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2498, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3696 = VST1q64wb_register |
| 6681 | { 3695, 6, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2492, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3695 = VST1q64wb_fixed |
| 6682 | { 3694, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3694 = VST1q64LowTPseudo_UPD |
| 6683 | { 3693, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3693 = VST1q64LowQPseudo_UPD |
| 6684 | { 3692, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3692 = VST1q64HighTPseudo_UPD |
| 6685 | { 3691, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3691 = VST1q64HighTPseudo |
| 6686 | { 3690, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3690 = VST1q64HighQPseudo_UPD |
| 6687 | { 3689, 5, 0, 4, 1056, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3689 = VST1q64HighQPseudo |
| 6688 | { 3688, 5, 0, 4, 645, 0, 0, ARMImpOpBase + 0, 2475, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3688 = VST1q64 |
| 6689 | { 3687, 7, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2498, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3687 = VST1q32wb_register |
| 6690 | { 3686, 6, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2492, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3686 = VST1q32wb_fixed |
| 6691 | { 3685, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3685 = VST1q32LowTPseudo_UPD |
| 6692 | { 3684, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3684 = VST1q32LowQPseudo_UPD |
| 6693 | { 3683, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3683 = VST1q32HighTPseudo_UPD |
| 6694 | { 3682, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3682 = VST1q32HighTPseudo |
| 6695 | { 3681, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3681 = VST1q32HighQPseudo_UPD |
| 6696 | { 3680, 5, 0, 4, 1056, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3680 = VST1q32HighQPseudo |
| 6697 | { 3679, 5, 0, 4, 645, 0, 0, ARMImpOpBase + 0, 2475, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3679 = VST1q32 |
| 6698 | { 3678, 7, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2498, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3678 = VST1q16wb_register |
| 6699 | { 3677, 6, 1, 4, 647, 0, 0, ARMImpOpBase + 0, 2492, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3677 = VST1q16wb_fixed |
| 6700 | { 3676, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3676 = VST1q16LowTPseudo_UPD |
| 6701 | { 3675, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3675 = VST1q16LowQPseudo_UPD |
| 6702 | { 3674, 7, 1, 4, 1054, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3674 = VST1q16HighTPseudo_UPD |
| 6703 | { 3673, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3673 = VST1q16HighTPseudo |
| 6704 | { 3672, 7, 1, 4, 1056, 0, 0, ARMImpOpBase + 0, 2485, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3672 = VST1q16HighQPseudo_UPD |
| 6705 | { 3671, 5, 0, 4, 1056, 0, 0, ARMImpOpBase + 0, 2480, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3671 = VST1q16HighQPseudo |
| 6706 | { 3670, 5, 0, 4, 645, 0, 0, ARMImpOpBase + 0, 2475, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3670 = VST1q16 |
| 6707 | { 3669, 7, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3669 = VST1d8wb_register |
| 6708 | { 3668, 6, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3668 = VST1d8wb_fixed |
| 6709 | { 3667, 7, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3667 = VST1d8Twb_register |
| 6710 | { 3666, 6, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3666 = VST1d8Twb_fixed |
| 6711 | { 3665, 7, 1, 4, 1055, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3665 = VST1d8TPseudoWB_register |
| 6712 | { 3664, 6, 1, 4, 1055, 0, 0, ARMImpOpBase + 0, 2449, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3664 = VST1d8TPseudoWB_fixed |
| 6713 | { 3663, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3663 = VST1d8TPseudo |
| 6714 | { 3662, 5, 0, 4, 799, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3662 = VST1d8T |
| 6715 | { 3661, 7, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3661 = VST1d8Qwb_register |
| 6716 | { 3660, 6, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3660 = VST1d8Qwb_fixed |
| 6717 | { 3659, 7, 1, 4, 652, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3659 = VST1d8QPseudoWB_register |
| 6718 | { 3658, 6, 1, 4, 652, 0, 0, ARMImpOpBase + 0, 2449, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3658 = VST1d8QPseudoWB_fixed |
| 6719 | { 3657, 5, 0, 4, 651, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3657 = VST1d8QPseudo |
| 6720 | { 3656, 5, 0, 4, 800, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3656 = VST1d8Q |
| 6721 | { 3655, 5, 0, 4, 644, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3655 = VST1d8 |
| 6722 | { 3654, 7, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3654 = VST1d64wb_register |
| 6723 | { 3653, 6, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3653 = VST1d64wb_fixed |
| 6724 | { 3652, 7, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3652 = VST1d64Twb_register |
| 6725 | { 3651, 6, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3651 = VST1d64Twb_fixed |
| 6726 | { 3650, 7, 1, 4, 650, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3650 = VST1d64TPseudoWB_register |
| 6727 | { 3649, 6, 1, 4, 650, 0, 0, ARMImpOpBase + 0, 2449, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3649 = VST1d64TPseudoWB_fixed |
| 6728 | { 3648, 5, 0, 4, 648, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3648 = VST1d64TPseudo |
| 6729 | { 3647, 5, 0, 4, 799, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3647 = VST1d64T |
| 6730 | { 3646, 7, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3646 = VST1d64Qwb_register |
| 6731 | { 3645, 6, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3645 = VST1d64Qwb_fixed |
| 6732 | { 3644, 7, 1, 4, 804, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3644 = VST1d64QPseudoWB_register |
| 6733 | { 3643, 6, 1, 4, 804, 0, 0, ARMImpOpBase + 0, 2449, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3643 = VST1d64QPseudoWB_fixed |
| 6734 | { 3642, 5, 0, 4, 801, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3642 = VST1d64QPseudo |
| 6735 | { 3641, 5, 0, 4, 800, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3641 = VST1d64Q |
| 6736 | { 3640, 5, 0, 4, 644, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3640 = VST1d64 |
| 6737 | { 3639, 7, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3639 = VST1d32wb_register |
| 6738 | { 3638, 6, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3638 = VST1d32wb_fixed |
| 6739 | { 3637, 7, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3637 = VST1d32Twb_register |
| 6740 | { 3636, 6, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3636 = VST1d32Twb_fixed |
| 6741 | { 3635, 7, 1, 4, 1055, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3635 = VST1d32TPseudoWB_register |
| 6742 | { 3634, 6, 1, 4, 1055, 0, 0, ARMImpOpBase + 0, 2449, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3634 = VST1d32TPseudoWB_fixed |
| 6743 | { 3633, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3633 = VST1d32TPseudo |
| 6744 | { 3632, 5, 0, 4, 799, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3632 = VST1d32T |
| 6745 | { 3631, 7, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3631 = VST1d32Qwb_register |
| 6746 | { 3630, 6, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3630 = VST1d32Qwb_fixed |
| 6747 | { 3629, 7, 1, 4, 652, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3629 = VST1d32QPseudoWB_register |
| 6748 | { 3628, 6, 1, 4, 652, 0, 0, ARMImpOpBase + 0, 2449, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3628 = VST1d32QPseudoWB_fixed |
| 6749 | { 3627, 5, 0, 4, 651, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3627 = VST1d32QPseudo |
| 6750 | { 3626, 5, 0, 4, 800, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3626 = VST1d32Q |
| 6751 | { 3625, 5, 0, 4, 644, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3625 = VST1d32 |
| 6752 | { 3624, 7, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3624 = VST1d16wb_register |
| 6753 | { 3623, 6, 1, 4, 646, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3623 = VST1d16wb_fixed |
| 6754 | { 3622, 7, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3622 = VST1d16Twb_register |
| 6755 | { 3621, 6, 1, 4, 649, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3621 = VST1d16Twb_fixed |
| 6756 | { 3620, 7, 1, 4, 1055, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3620 = VST1d16TPseudoWB_register |
| 6757 | { 3619, 6, 1, 4, 1055, 0, 0, ARMImpOpBase + 0, 2449, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3619 = VST1d16TPseudoWB_fixed |
| 6758 | { 3618, 5, 0, 4, 1054, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3618 = VST1d16TPseudo |
| 6759 | { 3617, 5, 0, 4, 799, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3617 = VST1d16T |
| 6760 | { 3616, 7, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2468, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3616 = VST1d16Qwb_register |
| 6761 | { 3615, 6, 1, 4, 653, 0, 0, ARMImpOpBase + 0, 2462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3615 = VST1d16Qwb_fixed |
| 6762 | { 3614, 7, 1, 4, 652, 0, 0, ARMImpOpBase + 0, 2455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3614 = VST1d16QPseudoWB_register |
| 6763 | { 3613, 6, 1, 4, 652, 0, 0, ARMImpOpBase + 0, 2449, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3613 = VST1d16QPseudoWB_fixed |
| 6764 | { 3612, 5, 0, 4, 651, 0, 0, ARMImpOpBase + 0, 2444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3612 = VST1d16QPseudo |
| 6765 | { 3611, 5, 0, 4, 800, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3611 = VST1d16Q |
| 6766 | { 3610, 5, 0, 4, 644, 0, 0, ARMImpOpBase + 0, 2439, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3610 = VST1d16 |
| 6767 | { 3609, 8, 1, 4, 665, 0, 0, ARMImpOpBase + 0, 2431, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3609 = VST1LNq8Pseudo_UPD |
| 6768 | { 3608, 6, 0, 4, 664, 0, 0, ARMImpOpBase + 0, 2425, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3608 = VST1LNq8Pseudo |
| 6769 | { 3607, 8, 1, 4, 665, 0, 0, ARMImpOpBase + 0, 2431, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3607 = VST1LNq32Pseudo_UPD |
| 6770 | { 3606, 6, 0, 4, 664, 0, 0, ARMImpOpBase + 0, 2425, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3606 = VST1LNq32Pseudo |
| 6771 | { 3605, 8, 1, 4, 665, 0, 0, ARMImpOpBase + 0, 2431, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3605 = VST1LNq16Pseudo_UPD |
| 6772 | { 3604, 6, 0, 4, 664, 0, 0, ARMImpOpBase + 0, 2425, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3604 = VST1LNq16Pseudo |
| 6773 | { 3603, 8, 1, 4, 805, 0, 0, ARMImpOpBase + 0, 2417, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3603 = VST1LNd8_UPD |
| 6774 | { 3602, 6, 0, 4, 802, 0, 0, ARMImpOpBase + 0, 2411, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3602 = VST1LNd8 |
| 6775 | { 3601, 8, 1, 4, 805, 0, 0, ARMImpOpBase + 0, 2417, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3601 = VST1LNd32_UPD |
| 6776 | { 3600, 6, 0, 4, 802, 0, 0, ARMImpOpBase + 0, 2411, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3600 = VST1LNd32 |
| 6777 | { 3599, 8, 1, 4, 805, 0, 0, ARMImpOpBase + 0, 2417, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3599 = VST1LNd16_UPD |
| 6778 | { 3598, 6, 0, 4, 802, 0, 0, ARMImpOpBase + 0, 2411, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3598 = VST1LNd16 |
| 6779 | { 3597, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3597 = VSRIv8i8 |
| 6780 | { 3596, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3596 = VSRIv8i16 |
| 6781 | { 3595, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3595 = VSRIv4i32 |
| 6782 | { 3594, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3594 = VSRIv4i16 |
| 6783 | { 3593, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3593 = VSRIv2i64 |
| 6784 | { 3592, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3592 = VSRIv2i32 |
| 6785 | { 3591, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3591 = VSRIv1i64 |
| 6786 | { 3590, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3590 = VSRIv16i8 |
| 6787 | { 3589, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3589 = VSRAuv8i8 |
| 6788 | { 3588, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3588 = VSRAuv8i16 |
| 6789 | { 3587, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3587 = VSRAuv4i32 |
| 6790 | { 3586, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3586 = VSRAuv4i16 |
| 6791 | { 3585, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3585 = VSRAuv2i64 |
| 6792 | { 3584, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3584 = VSRAuv2i32 |
| 6793 | { 3583, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3583 = VSRAuv1i64 |
| 6794 | { 3582, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3582 = VSRAuv16i8 |
| 6795 | { 3581, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3581 = VSRAsv8i8 |
| 6796 | { 3580, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3580 = VSRAsv8i16 |
| 6797 | { 3579, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3579 = VSRAsv4i32 |
| 6798 | { 3578, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3578 = VSRAsv4i16 |
| 6799 | { 3577, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3577 = VSRAsv2i64 |
| 6800 | { 3576, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3576 = VSRAsv2i32 |
| 6801 | { 3575, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3575 = VSRAsv1i64 |
| 6802 | { 3574, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3574 = VSRAsv16i8 |
| 6803 | { 3573, 4, 1, 4, 677, 0, 0, ARMImpOpBase + 0, 1686, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3573 = VSQRTS |
| 6804 | { 3572, 4, 1, 4, 962, 0, 0, ARMImpOpBase + 0, 1682, 0, 0x8780ULL }, // Inst #3572 = VSQRTH |
| 6805 | { 3571, 4, 1, 4, 679, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3571 = VSQRTD |
| 6806 | { 3570, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #3570 = VSMMLA |
| 6807 | { 3569, 5, 1, 4, 222, 0, 0, ARMImpOpBase + 0, 2390, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3569 = VSLTOS |
| 6808 | { 3568, 5, 1, 4, 221, 0, 0, ARMImpOpBase + 0, 2390, 0, 0x8880ULL }, // Inst #3568 = VSLTOH |
| 6809 | { 3567, 5, 1, 4, 1289, 0, 0, ARMImpOpBase + 0, 2385, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3567 = VSLTOD |
| 6810 | { 3566, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2405, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3566 = VSLIv8i8 |
| 6811 | { 3565, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2399, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3565 = VSLIv8i16 |
| 6812 | { 3564, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2399, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3564 = VSLIv4i32 |
| 6813 | { 3563, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2405, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3563 = VSLIv4i16 |
| 6814 | { 3562, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2399, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3562 = VSLIv2i64 |
| 6815 | { 3561, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2405, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3561 = VSLIv2i32 |
| 6816 | { 3560, 6, 1, 4, 990, 0, 0, ARMImpOpBase + 0, 2405, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3560 = VSLIv1i64 |
| 6817 | { 3559, 6, 1, 4, 991, 0, 0, ARMImpOpBase + 0, 2399, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3559 = VSLIv16i8 |
| 6818 | { 3558, 4, 1, 4, 564, 0, 0, ARMImpOpBase + 0, 1686, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3558 = VSITOS |
| 6819 | { 3557, 4, 1, 4, 563, 0, 0, ARMImpOpBase + 0, 2395, 0, 0x8880ULL }, // Inst #3557 = VSITOH |
| 6820 | { 3556, 4, 1, 4, 562, 0, 0, ARMImpOpBase + 0, 1805, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3556 = VSITOD |
| 6821 | { 3555, 5, 1, 4, 222, 0, 0, ARMImpOpBase + 0, 2390, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3555 = VSHTOS |
| 6822 | { 3554, 5, 1, 4, 221, 0, 0, ARMImpOpBase + 0, 2390, 0, 0x8880ULL }, // Inst #3554 = VSHTOH |
| 6823 | { 3553, 5, 1, 4, 1289, 0, 0, ARMImpOpBase + 0, 2385, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3553 = VSHTOD |
| 6824 | { 3552, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3552 = VSHRuv8i8 |
| 6825 | { 3551, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3551 = VSHRuv8i16 |
| 6826 | { 3550, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3550 = VSHRuv4i32 |
| 6827 | { 3549, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3549 = VSHRuv4i16 |
| 6828 | { 3548, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3548 = VSHRuv2i64 |
| 6829 | { 3547, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3547 = VSHRuv2i32 |
| 6830 | { 3546, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3546 = VSHRuv1i64 |
| 6831 | { 3545, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3545 = VSHRuv16i8 |
| 6832 | { 3544, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3544 = VSHRsv8i8 |
| 6833 | { 3543, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3543 = VSHRsv8i16 |
| 6834 | { 3542, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3542 = VSHRsv4i32 |
| 6835 | { 3541, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3541 = VSHRsv4i16 |
| 6836 | { 3540, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3540 = VSHRsv2i64 |
| 6837 | { 3539, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3539 = VSHRsv2i32 |
| 6838 | { 3538, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3538 = VSHRsv1i64 |
| 6839 | { 3537, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3537 = VSHRsv16i8 |
| 6840 | { 3536, 5, 1, 4, 502, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3536 = VSHRNv8i8 |
| 6841 | { 3535, 5, 1, 4, 502, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3535 = VSHRNv4i16 |
| 6842 | { 3534, 5, 1, 4, 502, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3534 = VSHRNv2i32 |
| 6843 | { 3533, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3533 = VSHLuv8i8 |
| 6844 | { 3532, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3532 = VSHLuv8i16 |
| 6845 | { 3531, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3531 = VSHLuv4i32 |
| 6846 | { 3530, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3530 = VSHLuv4i16 |
| 6847 | { 3529, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3529 = VSHLuv2i64 |
| 6848 | { 3528, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3528 = VSHLuv2i32 |
| 6849 | { 3527, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3527 = VSHLuv1i64 |
| 6850 | { 3526, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3526 = VSHLuv16i8 |
| 6851 | { 3525, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3525 = VSHLsv8i8 |
| 6852 | { 3524, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3524 = VSHLsv8i16 |
| 6853 | { 3523, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3523 = VSHLsv4i32 |
| 6854 | { 3522, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3522 = VSHLsv4i16 |
| 6855 | { 3521, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3521 = VSHLsv2i64 |
| 6856 | { 3520, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3520 = VSHLsv2i32 |
| 6857 | { 3519, 5, 1, 4, 465, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3519 = VSHLsv1i64 |
| 6858 | { 3518, 5, 1, 4, 466, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3518 = VSHLsv16i8 |
| 6859 | { 3517, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3517 = VSHLiv8i8 |
| 6860 | { 3516, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3516 = VSHLiv8i16 |
| 6861 | { 3515, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3515 = VSHLiv4i32 |
| 6862 | { 3514, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3514 = VSHLiv4i16 |
| 6863 | { 3513, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3513 = VSHLiv2i64 |
| 6864 | { 3512, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3512 = VSHLiv2i32 |
| 6865 | { 3511, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3511 = VSHLiv1i64 |
| 6866 | { 3510, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3510 = VSHLiv16i8 |
| 6867 | { 3509, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1835, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3509 = VSHLLuv8i16 |
| 6868 | { 3508, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1835, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3508 = VSHLLuv4i32 |
| 6869 | { 3507, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1835, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3507 = VSHLLuv2i64 |
| 6870 | { 3506, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1835, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3506 = VSHLLsv8i16 |
| 6871 | { 3505, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1835, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3505 = VSHLLsv4i32 |
| 6872 | { 3504, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1835, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3504 = VSHLLsv2i64 |
| 6873 | { 3503, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1835, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3503 = VSHLLi8 |
| 6874 | { 3502, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1835, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3502 = VSHLLi32 |
| 6875 | { 3501, 5, 1, 4, 987, 0, 0, ARMImpOpBase + 0, 1835, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3501 = VSHLLi16 |
| 6876 | { 3500, 6, 1, 4, 580, 0, 0, ARMImpOpBase + 0, 2379, 0|(1ULL<<MCID::Predicable), 0x10e00ULL }, // Inst #3500 = VSETLNi8 |
| 6877 | { 3499, 6, 1, 4, 1044, 0, 0, ARMImpOpBase + 0, 2379, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::InsertSubreg), 0x10e00ULL }, // Inst #3499 = VSETLNi32 |
| 6878 | { 3498, 6, 1, 4, 580, 0, 0, ARMImpOpBase + 0, 2379, 0|(1ULL<<MCID::Predicable), 0x10e00ULL }, // Inst #3498 = VSETLNi16 |
| 6879 | { 3497, 3, 1, 4, 1259, 1, 0, ARMImpOpBase + 0, 1881, 0, 0x8800ULL }, // Inst #3497 = VSELVSS |
| 6880 | { 3496, 3, 1, 4, 772, 1, 0, ARMImpOpBase + 0, 1878, 0, 0x8800ULL }, // Inst #3496 = VSELVSH |
| 6881 | { 3495, 3, 1, 4, 1260, 1, 0, ARMImpOpBase + 0, 1501, 0, 0x8800ULL }, // Inst #3495 = VSELVSD |
| 6882 | { 3494, 3, 1, 4, 1259, 1, 0, ARMImpOpBase + 0, 1881, 0, 0x8800ULL }, // Inst #3494 = VSELGTS |
| 6883 | { 3493, 3, 1, 4, 772, 1, 0, ARMImpOpBase + 0, 1878, 0, 0x8800ULL }, // Inst #3493 = VSELGTH |
| 6884 | { 3492, 3, 1, 4, 1260, 1, 0, ARMImpOpBase + 0, 1501, 0, 0x8800ULL }, // Inst #3492 = VSELGTD |
| 6885 | { 3491, 3, 1, 4, 1259, 1, 0, ARMImpOpBase + 0, 1881, 0, 0x8800ULL }, // Inst #3491 = VSELGES |
| 6886 | { 3490, 3, 1, 4, 772, 1, 0, ARMImpOpBase + 0, 1878, 0, 0x8800ULL }, // Inst #3490 = VSELGEH |
| 6887 | { 3489, 3, 1, 4, 1260, 1, 0, ARMImpOpBase + 0, 1501, 0, 0x8800ULL }, // Inst #3489 = VSELGED |
| 6888 | { 3488, 3, 1, 4, 1259, 1, 0, ARMImpOpBase + 0, 1881, 0, 0x8800ULL }, // Inst #3488 = VSELEQS |
| 6889 | { 3487, 3, 1, 4, 772, 1, 0, ARMImpOpBase + 0, 1878, 0, 0x8800ULL }, // Inst #3487 = VSELEQH |
| 6890 | { 3486, 3, 1, 4, 1260, 1, 0, ARMImpOpBase + 0, 1501, 0, 0x8800ULL }, // Inst #3486 = VSELEQD |
| 6891 | { 3485, 5, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #3485 = VSDOTQI |
| 6892 | { 3484, 4, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #3484 = VSDOTQ |
| 6893 | { 3483, 5, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 630, 0, 0x11280ULL }, // Inst #3483 = VSDOTDI |
| 6894 | { 3482, 4, 1, 4, 964, 0, 0, ARMImpOpBase + 0, 640, 0, 0x11280ULL }, // Inst #3482 = VSDOTD |
| 6895 | { 3481, 3, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 587, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3481 = VSCCLRMS |
| 6896 | { 3480, 3, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 587, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3480 = VSCCLRMD |
| 6897 | { 3479, 5, 1, 4, 503, 0, 0, ARMImpOpBase + 0, 1699, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3479 = VRSUBHNv8i8 |
| 6898 | { 3478, 5, 1, 4, 503, 0, 0, ARMImpOpBase + 0, 1699, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3478 = VRSUBHNv4i16 |
| 6899 | { 3477, 5, 1, 4, 503, 0, 0, ARMImpOpBase + 0, 1699, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3477 = VRSUBHNv2i32 |
| 6900 | { 3476, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3476 = VRSRAuv8i8 |
| 6901 | { 3475, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3475 = VRSRAuv8i16 |
| 6902 | { 3474, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3474 = VRSRAuv4i32 |
| 6903 | { 3473, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3473 = VRSRAuv4i16 |
| 6904 | { 3472, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3472 = VRSRAuv2i64 |
| 6905 | { 3471, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3471 = VRSRAuv2i32 |
| 6906 | { 3470, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3470 = VRSRAuv1i64 |
| 6907 | { 3469, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3469 = VRSRAuv16i8 |
| 6908 | { 3468, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3468 = VRSRAsv8i8 |
| 6909 | { 3467, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3467 = VRSRAsv8i16 |
| 6910 | { 3466, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3466 = VRSRAsv4i32 |
| 6911 | { 3465, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3465 = VRSRAsv4i16 |
| 6912 | { 3464, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3464 = VRSRAsv2i64 |
| 6913 | { 3463, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3463 = VRSRAsv2i32 |
| 6914 | { 3462, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2373, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3462 = VRSRAsv1i64 |
| 6915 | { 3461, 6, 1, 4, 483, 0, 0, ARMImpOpBase + 0, 2367, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3461 = VRSRAsv16i8 |
| 6916 | { 3460, 5, 1, 4, 529, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3460 = VRSQRTShq |
| 6917 | { 3459, 5, 1, 4, 528, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3459 = VRSQRTShd |
| 6918 | { 3458, 5, 1, 4, 529, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3458 = VRSQRTSfq |
| 6919 | { 3457, 5, 1, 4, 528, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3457 = VRSQRTSfd |
| 6920 | { 3456, 4, 1, 4, 500, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3456 = VRSQRTEq |
| 6921 | { 3455, 4, 1, 4, 500, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3455 = VRSQRTEhq |
| 6922 | { 3454, 4, 1, 4, 499, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3454 = VRSQRTEhd |
| 6923 | { 3453, 4, 1, 4, 500, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3453 = VRSQRTEfq |
| 6924 | { 3452, 4, 1, 4, 499, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3452 = VRSQRTEfd |
| 6925 | { 3451, 4, 1, 4, 499, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3451 = VRSQRTEd |
| 6926 | { 3450, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3450 = VRSHRuv8i8 |
| 6927 | { 3449, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3449 = VRSHRuv8i16 |
| 6928 | { 3448, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3448 = VRSHRuv4i32 |
| 6929 | { 3447, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3447 = VRSHRuv4i16 |
| 6930 | { 3446, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3446 = VRSHRuv2i64 |
| 6931 | { 3445, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3445 = VRSHRuv2i32 |
| 6932 | { 3444, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3444 = VRSHRuv1i64 |
| 6933 | { 3443, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3443 = VRSHRuv16i8 |
| 6934 | { 3442, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3442 = VRSHRsv8i8 |
| 6935 | { 3441, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3441 = VRSHRsv8i16 |
| 6936 | { 3440, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3440 = VRSHRsv4i32 |
| 6937 | { 3439, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3439 = VRSHRsv4i16 |
| 6938 | { 3438, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3438 = VRSHRsv2i64 |
| 6939 | { 3437, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3437 = VRSHRsv2i32 |
| 6940 | { 3436, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3436 = VRSHRsv1i64 |
| 6941 | { 3435, 5, 1, 4, 989, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3435 = VRSHRsv16i8 |
| 6942 | { 3434, 5, 1, 4, 798, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3434 = VRSHRNv8i8 |
| 6943 | { 3433, 5, 1, 4, 798, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3433 = VRSHRNv4i16 |
| 6944 | { 3432, 5, 1, 4, 798, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3432 = VRSHRNv2i32 |
| 6945 | { 3431, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3431 = VRSHLuv8i8 |
| 6946 | { 3430, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3430 = VRSHLuv8i16 |
| 6947 | { 3429, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3429 = VRSHLuv4i32 |
| 6948 | { 3428, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3428 = VRSHLuv4i16 |
| 6949 | { 3427, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3427 = VRSHLuv2i64 |
| 6950 | { 3426, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3426 = VRSHLuv2i32 |
| 6951 | { 3425, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3425 = VRSHLuv1i64 |
| 6952 | { 3424, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3424 = VRSHLuv16i8 |
| 6953 | { 3423, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3423 = VRSHLsv8i8 |
| 6954 | { 3422, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3422 = VRSHLsv8i16 |
| 6955 | { 3421, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3421 = VRSHLsv4i32 |
| 6956 | { 3420, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3420 = VRSHLsv4i16 |
| 6957 | { 3419, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3419 = VRSHLsv2i64 |
| 6958 | { 3418, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3418 = VRSHLsv2i32 |
| 6959 | { 3417, 5, 1, 4, 797, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3417 = VRSHLsv1i64 |
| 6960 | { 3416, 5, 1, 4, 796, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3416 = VRSHLsv16i8 |
| 6961 | { 3415, 4, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1686, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3415 = VRINTZS |
| 6962 | { 3414, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #3414 = VRINTZNQh |
| 6963 | { 3413, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #3413 = VRINTZNQf |
| 6964 | { 3412, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #3412 = VRINTZNDh |
| 6965 | { 3411, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #3411 = VRINTZNDf |
| 6966 | { 3410, 4, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 1682, 0, 0x8780ULL }, // Inst #3410 = VRINTZH |
| 6967 | { 3409, 4, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3409 = VRINTZD |
| 6968 | { 3408, 4, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1686, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3408 = VRINTXS |
| 6969 | { 3407, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #3407 = VRINTXNQh |
| 6970 | { 3406, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #3406 = VRINTXNQf |
| 6971 | { 3405, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #3405 = VRINTXNDh |
| 6972 | { 3404, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #3404 = VRINTXNDf |
| 6973 | { 3403, 4, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 1682, 0, 0x8780ULL }, // Inst #3403 = VRINTXH |
| 6974 | { 3402, 4, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3402 = VRINTXD |
| 6975 | { 3401, 4, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1686, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3401 = VRINTRS |
| 6976 | { 3400, 4, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 1682, 0, 0x8780ULL }, // Inst #3400 = VRINTRH |
| 6977 | { 3399, 4, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3399 = VRINTRD |
| 6978 | { 3398, 2, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1798, 0, 0x8780ULL }, // Inst #3398 = VRINTPS |
| 6979 | { 3397, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #3397 = VRINTPNQh |
| 6980 | { 3396, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #3396 = VRINTPNQf |
| 6981 | { 3395, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #3395 = VRINTPNDh |
| 6982 | { 3394, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #3394 = VRINTPNDf |
| 6983 | { 3393, 2, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 2365, 0, 0x8780ULL }, // Inst #3393 = VRINTPH |
| 6984 | { 3392, 2, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x8780ULL }, // Inst #3392 = VRINTPD |
| 6985 | { 3391, 2, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1798, 0, 0x8780ULL }, // Inst #3391 = VRINTNS |
| 6986 | { 3390, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #3390 = VRINTNNQh |
| 6987 | { 3389, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #3389 = VRINTNNQf |
| 6988 | { 3388, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #3388 = VRINTNNDh |
| 6989 | { 3387, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #3387 = VRINTNNDf |
| 6990 | { 3386, 2, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 2365, 0, 0x8780ULL }, // Inst #3386 = VRINTNH |
| 6991 | { 3385, 2, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x8780ULL }, // Inst #3385 = VRINTND |
| 6992 | { 3384, 2, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1798, 0, 0x8780ULL }, // Inst #3384 = VRINTMS |
| 6993 | { 3383, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #3383 = VRINTMNQh |
| 6994 | { 3382, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #3382 = VRINTMNQf |
| 6995 | { 3381, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #3381 = VRINTMNDh |
| 6996 | { 3380, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #3380 = VRINTMNDf |
| 6997 | { 3379, 2, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 2365, 0, 0x8780ULL }, // Inst #3379 = VRINTMH |
| 6998 | { 3378, 2, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x8780ULL }, // Inst #3378 = VRINTMD |
| 6999 | { 3377, 2, 1, 4, 1252, 0, 0, ARMImpOpBase + 0, 1798, 0, 0x8780ULL }, // Inst #3377 = VRINTAS |
| 7000 | { 3376, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #3376 = VRINTANQh |
| 7001 | { 3375, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #3375 = VRINTANQf |
| 7002 | { 3374, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #3374 = VRINTANDh |
| 7003 | { 3373, 2, 1, 4, 1000, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #3373 = VRINTANDf |
| 7004 | { 3372, 2, 1, 4, 961, 0, 0, ARMImpOpBase + 0, 2365, 0, 0x8780ULL }, // Inst #3372 = VRINTAH |
| 7005 | { 3371, 2, 1, 4, 1256, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x8780ULL }, // Inst #3371 = VRINTAD |
| 7006 | { 3370, 5, 1, 4, 973, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3370 = VRHADDuv8i8 |
| 7007 | { 3369, 5, 1, 4, 972, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3369 = VRHADDuv8i16 |
| 7008 | { 3368, 5, 1, 4, 972, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3368 = VRHADDuv4i32 |
| 7009 | { 3367, 5, 1, 4, 973, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3367 = VRHADDuv4i16 |
| 7010 | { 3366, 5, 1, 4, 973, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3366 = VRHADDuv2i32 |
| 7011 | { 3365, 5, 1, 4, 972, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3365 = VRHADDuv16i8 |
| 7012 | { 3364, 5, 1, 4, 973, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3364 = VRHADDsv8i8 |
| 7013 | { 3363, 5, 1, 4, 972, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3363 = VRHADDsv8i16 |
| 7014 | { 3362, 5, 1, 4, 972, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3362 = VRHADDsv4i32 |
| 7015 | { 3361, 5, 1, 4, 973, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3361 = VRHADDsv4i16 |
| 7016 | { 3360, 5, 1, 4, 973, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3360 = VRHADDsv2i32 |
| 7017 | { 3359, 5, 1, 4, 972, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3359 = VRHADDsv16i8 |
| 7018 | { 3358, 4, 1, 4, 479, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3358 = VREV64q8 |
| 7019 | { 3357, 4, 1, 4, 479, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3357 = VREV64q32 |
| 7020 | { 3356, 4, 1, 4, 479, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3356 = VREV64q16 |
| 7021 | { 3355, 4, 1, 4, 478, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3355 = VREV64d8 |
| 7022 | { 3354, 4, 1, 4, 478, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3354 = VREV64d32 |
| 7023 | { 3353, 4, 1, 4, 478, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3353 = VREV64d16 |
| 7024 | { 3352, 4, 1, 4, 479, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3352 = VREV32q8 |
| 7025 | { 3351, 4, 1, 4, 479, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3351 = VREV32q16 |
| 7026 | { 3350, 4, 1, 4, 478, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3350 = VREV32d8 |
| 7027 | { 3349, 4, 1, 4, 478, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3349 = VREV32d16 |
| 7028 | { 3348, 4, 1, 4, 479, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3348 = VREV16q8 |
| 7029 | { 3347, 4, 1, 4, 478, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3347 = VREV16d8 |
| 7030 | { 3346, 5, 1, 4, 529, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3346 = VRECPShq |
| 7031 | { 3345, 5, 1, 4, 528, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3345 = VRECPShd |
| 7032 | { 3344, 5, 1, 4, 529, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3344 = VRECPSfq |
| 7033 | { 3343, 5, 1, 4, 528, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3343 = VRECPSfd |
| 7034 | { 3342, 4, 1, 4, 500, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3342 = VRECPEq |
| 7035 | { 3341, 4, 1, 4, 500, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3341 = VRECPEhq |
| 7036 | { 3340, 4, 1, 4, 499, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3340 = VRECPEhd |
| 7037 | { 3339, 4, 1, 4, 500, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3339 = VRECPEfq |
| 7038 | { 3338, 4, 1, 4, 499, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3338 = VRECPEfd |
| 7039 | { 3337, 4, 1, 4, 499, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3337 = VRECPEd |
| 7040 | { 3336, 5, 1, 4, 503, 0, 0, ARMImpOpBase + 0, 1699, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3336 = VRADDHNv8i8 |
| 7041 | { 3335, 5, 1, 4, 503, 0, 0, ARMImpOpBase + 0, 1699, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3335 = VRADDHNv4i16 |
| 7042 | { 3334, 5, 1, 4, 503, 0, 0, ARMImpOpBase + 0, 1699, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3334 = VRADDHNv2i32 |
| 7043 | { 3333, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3333 = VQSUBuv8i8 |
| 7044 | { 3332, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3332 = VQSUBuv8i16 |
| 7045 | { 3331, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3331 = VQSUBuv4i32 |
| 7046 | { 3330, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3330 = VQSUBuv4i16 |
| 7047 | { 3329, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3329 = VQSUBuv2i64 |
| 7048 | { 3328, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3328 = VQSUBuv2i32 |
| 7049 | { 3327, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3327 = VQSUBuv1i64 |
| 7050 | { 3326, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3326 = VQSUBuv16i8 |
| 7051 | { 3325, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3325 = VQSUBsv8i8 |
| 7052 | { 3324, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3324 = VQSUBsv8i16 |
| 7053 | { 3323, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3323 = VQSUBsv4i32 |
| 7054 | { 3322, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3322 = VQSUBsv4i16 |
| 7055 | { 3321, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3321 = VQSUBsv2i64 |
| 7056 | { 3320, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3320 = VQSUBsv2i32 |
| 7057 | { 3319, 5, 1, 4, 487, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3319 = VQSUBsv1i64 |
| 7058 | { 3318, 5, 1, 4, 486, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3318 = VQSUBsv16i8 |
| 7059 | { 3317, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3317 = VQSHRUNv8i8 |
| 7060 | { 3316, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3316 = VQSHRUNv4i16 |
| 7061 | { 3315, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3315 = VQSHRUNv2i32 |
| 7062 | { 3314, 5, 1, 4, 795, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3314 = VQSHRNuv8i8 |
| 7063 | { 3313, 5, 1, 4, 795, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3313 = VQSHRNuv4i16 |
| 7064 | { 3312, 5, 1, 4, 795, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3312 = VQSHRNuv2i32 |
| 7065 | { 3311, 5, 1, 4, 795, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3311 = VQSHRNsv8i8 |
| 7066 | { 3310, 5, 1, 4, 795, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3310 = VQSHRNsv4i16 |
| 7067 | { 3309, 5, 1, 4, 795, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3309 = VQSHRNsv2i32 |
| 7068 | { 3308, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3308 = VQSHLuv8i8 |
| 7069 | { 3307, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3307 = VQSHLuv8i16 |
| 7070 | { 3306, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3306 = VQSHLuv4i32 |
| 7071 | { 3305, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3305 = VQSHLuv4i16 |
| 7072 | { 3304, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3304 = VQSHLuv2i64 |
| 7073 | { 3303, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3303 = VQSHLuv2i32 |
| 7074 | { 3302, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3302 = VQSHLuv1i64 |
| 7075 | { 3301, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3301 = VQSHLuv16i8 |
| 7076 | { 3300, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3300 = VQSHLuiv8i8 |
| 7077 | { 3299, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3299 = VQSHLuiv8i16 |
| 7078 | { 3298, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3298 = VQSHLuiv4i32 |
| 7079 | { 3297, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3297 = VQSHLuiv4i16 |
| 7080 | { 3296, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3296 = VQSHLuiv2i64 |
| 7081 | { 3295, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3295 = VQSHLuiv2i32 |
| 7082 | { 3294, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3294 = VQSHLuiv1i64 |
| 7083 | { 3293, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3293 = VQSHLuiv16i8 |
| 7084 | { 3292, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3292 = VQSHLsv8i8 |
| 7085 | { 3291, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3291 = VQSHLsv8i16 |
| 7086 | { 3290, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3290 = VQSHLsv4i32 |
| 7087 | { 3289, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3289 = VQSHLsv4i16 |
| 7088 | { 3288, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3288 = VQSHLsv2i64 |
| 7089 | { 3287, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3287 = VQSHLsv2i32 |
| 7090 | { 3286, 5, 1, 4, 472, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3286 = VQSHLsv1i64 |
| 7091 | { 3285, 5, 1, 4, 473, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3285 = VQSHLsv16i8 |
| 7092 | { 3284, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3284 = VQSHLsuv8i8 |
| 7093 | { 3283, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3283 = VQSHLsuv8i16 |
| 7094 | { 3282, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3282 = VQSHLsuv4i32 |
| 7095 | { 3281, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3281 = VQSHLsuv4i16 |
| 7096 | { 3280, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3280 = VQSHLsuv2i64 |
| 7097 | { 3279, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3279 = VQSHLsuv2i32 |
| 7098 | { 3278, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3278 = VQSHLsuv1i64 |
| 7099 | { 3277, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3277 = VQSHLsuv16i8 |
| 7100 | { 3276, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3276 = VQSHLsiv8i8 |
| 7101 | { 3275, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3275 = VQSHLsiv8i16 |
| 7102 | { 3274, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3274 = VQSHLsiv4i32 |
| 7103 | { 3273, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3273 = VQSHLsiv4i16 |
| 7104 | { 3272, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3272 = VQSHLsiv2i64 |
| 7105 | { 3271, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3271 = VQSHLsiv2i32 |
| 7106 | { 3270, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2360, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3270 = VQSHLsiv1i64 |
| 7107 | { 3269, 5, 1, 4, 988, 0, 0, ARMImpOpBase + 0, 2355, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3269 = VQSHLsiv16i8 |
| 7108 | { 3268, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3268 = VQRSHRUNv8i8 |
| 7109 | { 3267, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3267 = VQRSHRUNv4i16 |
| 7110 | { 3266, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3266 = VQRSHRUNv2i32 |
| 7111 | { 3265, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3265 = VQRSHRNuv8i8 |
| 7112 | { 3264, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3264 = VQRSHRNuv4i16 |
| 7113 | { 3263, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3263 = VQRSHRNuv2i32 |
| 7114 | { 3262, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3262 = VQRSHRNsv8i8 |
| 7115 | { 3261, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3261 = VQRSHRNsv4i16 |
| 7116 | { 3260, 5, 1, 4, 504, 0, 0, ARMImpOpBase + 0, 2350, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3260 = VQRSHRNsv2i32 |
| 7117 | { 3259, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3259 = VQRSHLuv8i8 |
| 7118 | { 3258, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3258 = VQRSHLuv8i16 |
| 7119 | { 3257, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3257 = VQRSHLuv4i32 |
| 7120 | { 3256, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3256 = VQRSHLuv4i16 |
| 7121 | { 3255, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3255 = VQRSHLuv2i64 |
| 7122 | { 3254, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3254 = VQRSHLuv2i32 |
| 7123 | { 3253, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3253 = VQRSHLuv1i64 |
| 7124 | { 3252, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3252 = VQRSHLuv16i8 |
| 7125 | { 3251, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3251 = VQRSHLsv8i8 |
| 7126 | { 3250, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3250 = VQRSHLsv8i16 |
| 7127 | { 3249, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3249 = VQRSHLsv4i32 |
| 7128 | { 3248, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3248 = VQRSHLsv4i16 |
| 7129 | { 3247, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3247 = VQRSHLsv2i64 |
| 7130 | { 3246, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3246 = VQRSHLsv2i32 |
| 7131 | { 3245, 5, 1, 4, 490, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3245 = VQRSHLsv1i64 |
| 7132 | { 3244, 5, 1, 4, 489, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3244 = VQRSHLsv16i8 |
| 7133 | { 3243, 5, 1, 4, 794, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3243 = VQRDMULHv8i16 |
| 7134 | { 3242, 5, 1, 4, 793, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3242 = VQRDMULHv4i32 |
| 7135 | { 3241, 5, 1, 4, 978, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3241 = VQRDMULHv4i16 |
| 7136 | { 3240, 5, 1, 4, 977, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3240 = VQRDMULHv2i32 |
| 7137 | { 3239, 6, 1, 4, 794, 0, 0, ARMImpOpBase + 0, 2339, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3239 = VQRDMULHslv8i16 |
| 7138 | { 3238, 6, 1, 4, 793, 0, 0, ARMImpOpBase + 0, 2327, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3238 = VQRDMULHslv4i32 |
| 7139 | { 3237, 6, 1, 4, 978, 0, 0, ARMImpOpBase + 0, 2333, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3237 = VQRDMULHslv4i16 |
| 7140 | { 3236, 6, 1, 4, 977, 0, 0, ARMImpOpBase + 0, 2321, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3236 = VQRDMULHslv2i32 |
| 7141 | { 3235, 6, 1, 4, 985, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3235 = VQRDMLSHv8i16 |
| 7142 | { 3234, 6, 1, 4, 984, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3234 = VQRDMLSHv4i32 |
| 7143 | { 3233, 6, 1, 4, 983, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3233 = VQRDMLSHv4i16 |
| 7144 | { 3232, 6, 1, 4, 982, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3232 = VQRDMLSHv2i32 |
| 7145 | { 3231, 7, 1, 4, 985, 0, 0, ARMImpOpBase + 0, 2244, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // Inst #3231 = VQRDMLSHslv8i16 |
| 7146 | { 3230, 7, 1, 4, 984, 0, 0, ARMImpOpBase + 0, 2230, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // Inst #3230 = VQRDMLSHslv4i32 |
| 7147 | { 3229, 7, 1, 4, 983, 0, 0, ARMImpOpBase + 0, 2237, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3229 = VQRDMLSHslv4i16 |
| 7148 | { 3228, 7, 1, 4, 982, 0, 0, ARMImpOpBase + 0, 2223, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3228 = VQRDMLSHslv2i32 |
| 7149 | { 3227, 6, 1, 4, 985, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3227 = VQRDMLAHv8i16 |
| 7150 | { 3226, 6, 1, 4, 984, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3226 = VQRDMLAHv4i32 |
| 7151 | { 3225, 6, 1, 4, 983, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3225 = VQRDMLAHv4i16 |
| 7152 | { 3224, 6, 1, 4, 982, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3224 = VQRDMLAHv2i32 |
| 7153 | { 3223, 7, 1, 4, 985, 0, 0, ARMImpOpBase + 0, 2244, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // Inst #3223 = VQRDMLAHslv8i16 |
| 7154 | { 3222, 7, 1, 4, 984, 0, 0, ARMImpOpBase + 0, 2230, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // Inst #3222 = VQRDMLAHslv4i32 |
| 7155 | { 3221, 7, 1, 4, 983, 0, 0, ARMImpOpBase + 0, 2237, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3221 = VQRDMLAHslv4i16 |
| 7156 | { 3220, 7, 1, 4, 982, 0, 0, ARMImpOpBase + 0, 2223, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3220 = VQRDMLAHslv2i32 |
| 7157 | { 3219, 4, 1, 4, 496, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3219 = VQNEGv8i8 |
| 7158 | { 3218, 4, 1, 4, 495, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3218 = VQNEGv8i16 |
| 7159 | { 3217, 4, 1, 4, 495, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3217 = VQNEGv4i32 |
| 7160 | { 3216, 4, 1, 4, 496, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3216 = VQNEGv4i16 |
| 7161 | { 3215, 4, 1, 4, 496, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3215 = VQNEGv2i32 |
| 7162 | { 3214, 4, 1, 4, 495, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3214 = VQNEGv16i8 |
| 7163 | { 3213, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3213 = VQMOVNuv8i8 |
| 7164 | { 3212, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3212 = VQMOVNuv4i16 |
| 7165 | { 3211, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3211 = VQMOVNuv2i32 |
| 7166 | { 3210, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3210 = VQMOVNsv8i8 |
| 7167 | { 3209, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3209 = VQMOVNsv4i16 |
| 7168 | { 3208, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3208 = VQMOVNsv2i32 |
| 7169 | { 3207, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3207 = VQMOVNsuv8i8 |
| 7170 | { 3206, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3206 = VQMOVNsuv4i16 |
| 7171 | { 3205, 4, 1, 4, 574, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3205 = VQMOVNsuv2i32 |
| 7172 | { 3204, 5, 1, 4, 792, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3204 = VQDMULLv4i32 |
| 7173 | { 3203, 5, 1, 4, 791, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3203 = VQDMULLv2i64 |
| 7174 | { 3202, 6, 1, 4, 792, 0, 0, ARMImpOpBase + 0, 2315, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3202 = VQDMULLslv4i16 |
| 7175 | { 3201, 6, 1, 4, 792, 0, 0, ARMImpOpBase + 0, 2309, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3201 = VQDMULLslv2i32 |
| 7176 | { 3200, 5, 1, 4, 794, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3200 = VQDMULHv8i16 |
| 7177 | { 3199, 5, 1, 4, 793, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3199 = VQDMULHv4i32 |
| 7178 | { 3198, 5, 1, 4, 978, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3198 = VQDMULHv4i16 |
| 7179 | { 3197, 5, 1, 4, 977, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3197 = VQDMULHv2i32 |
| 7180 | { 3196, 6, 1, 4, 794, 0, 0, ARMImpOpBase + 0, 2339, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3196 = VQDMULHslv8i16 |
| 7181 | { 3195, 6, 1, 4, 793, 0, 0, ARMImpOpBase + 0, 2327, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3195 = VQDMULHslv4i32 |
| 7182 | { 3194, 6, 1, 4, 978, 0, 0, ARMImpOpBase + 0, 2333, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3194 = VQDMULHslv4i16 |
| 7183 | { 3193, 6, 1, 4, 977, 0, 0, ARMImpOpBase + 0, 2321, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3193 = VQDMULHslv2i32 |
| 7184 | { 3192, 6, 1, 4, 790, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3192 = VQDMLSLv4i32 |
| 7185 | { 3191, 6, 1, 4, 789, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3191 = VQDMLSLv2i64 |
| 7186 | { 3190, 7, 1, 4, 790, 0, 0, ARMImpOpBase + 0, 2216, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3190 = VQDMLSLslv4i16 |
| 7187 | { 3189, 7, 1, 4, 789, 0, 0, ARMImpOpBase + 0, 2209, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3189 = VQDMLSLslv2i32 |
| 7188 | { 3188, 6, 1, 4, 790, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3188 = VQDMLALv4i32 |
| 7189 | { 3187, 6, 1, 4, 789, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3187 = VQDMLALv2i64 |
| 7190 | { 3186, 7, 1, 4, 790, 0, 0, ARMImpOpBase + 0, 2216, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3186 = VQDMLALslv4i16 |
| 7191 | { 3185, 7, 1, 4, 789, 0, 0, ARMImpOpBase + 0, 2209, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3185 = VQDMLALslv2i32 |
| 7192 | { 3184, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3184 = VQADDuv8i8 |
| 7193 | { 3183, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3183 = VQADDuv8i16 |
| 7194 | { 3182, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3182 = VQADDuv4i32 |
| 7195 | { 3181, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3181 = VQADDuv4i16 |
| 7196 | { 3180, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3180 = VQADDuv2i64 |
| 7197 | { 3179, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3179 = VQADDuv2i32 |
| 7198 | { 3178, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3178 = VQADDuv1i64 |
| 7199 | { 3177, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3177 = VQADDuv16i8 |
| 7200 | { 3176, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3176 = VQADDsv8i8 |
| 7201 | { 3175, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3175 = VQADDsv8i16 |
| 7202 | { 3174, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3174 = VQADDsv4i32 |
| 7203 | { 3173, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3173 = VQADDsv4i16 |
| 7204 | { 3172, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3172 = VQADDsv2i64 |
| 7205 | { 3171, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3171 = VQADDsv2i32 |
| 7206 | { 3170, 5, 1, 4, 498, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3170 = VQADDsv1i64 |
| 7207 | { 3169, 5, 1, 4, 497, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3169 = VQADDsv16i8 |
| 7208 | { 3168, 4, 1, 4, 787, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3168 = VQABSv8i8 |
| 7209 | { 3167, 4, 1, 4, 788, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3167 = VQABSv8i16 |
| 7210 | { 3166, 4, 1, 4, 788, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3166 = VQABSv4i32 |
| 7211 | { 3165, 4, 1, 4, 787, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3165 = VQABSv4i16 |
| 7212 | { 3164, 4, 1, 4, 787, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3164 = VQABSv2i32 |
| 7213 | { 3163, 4, 1, 4, 788, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3163 = VQABSv16i8 |
| 7214 | { 3162, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3162 = VPMINu8 |
| 7215 | { 3161, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3161 = VPMINu32 |
| 7216 | { 3160, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3160 = VPMINu16 |
| 7217 | { 3159, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3159 = VPMINs8 |
| 7218 | { 3158, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3158 = VPMINs32 |
| 7219 | { 3157, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3157 = VPMINs16 |
| 7220 | { 3156, 5, 1, 4, 778, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3156 = VPMINh |
| 7221 | { 3155, 5, 1, 4, 778, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3155 = VPMINf |
| 7222 | { 3154, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3154 = VPMAXu8 |
| 7223 | { 3153, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3153 = VPMAXu32 |
| 7224 | { 3152, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3152 = VPMAXu16 |
| 7225 | { 3151, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3151 = VPMAXs8 |
| 7226 | { 3150, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3150 = VPMAXs32 |
| 7227 | { 3149, 5, 1, 4, 525, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3149 = VPMAXs16 |
| 7228 | { 3148, 5, 1, 4, 778, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3148 = VPMAXh |
| 7229 | { 3147, 5, 1, 4, 778, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3147 = VPMAXf |
| 7230 | { 3146, 5, 1, 4, 784, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3146 = VPADDi8 |
| 7231 | { 3145, 5, 1, 4, 784, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3145 = VPADDi32 |
| 7232 | { 3144, 5, 1, 4, 784, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3144 = VPADDi16 |
| 7233 | { 3143, 5, 1, 4, 992, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3143 = VPADDh |
| 7234 | { 3142, 5, 1, 4, 526, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3142 = VPADDf |
| 7235 | { 3141, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3141 = VPADDLuv8i8 |
| 7236 | { 3140, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3140 = VPADDLuv8i16 |
| 7237 | { 3139, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3139 = VPADDLuv4i32 |
| 7238 | { 3138, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3138 = VPADDLuv4i16 |
| 7239 | { 3137, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3137 = VPADDLuv2i32 |
| 7240 | { 3136, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3136 = VPADDLuv16i8 |
| 7241 | { 3135, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3135 = VPADDLsv8i8 |
| 7242 | { 3134, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3134 = VPADDLsv8i16 |
| 7243 | { 3133, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3133 = VPADDLsv4i32 |
| 7244 | { 3132, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3132 = VPADDLsv4i16 |
| 7245 | { 3131, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3131 = VPADDLsv2i32 |
| 7246 | { 3130, 4, 1, 4, 786, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3130 = VPADDLsv16i8 |
| 7247 | { 3129, 5, 1, 4, 785, 0, 0, ARMImpOpBase + 0, 400, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3129 = VPADALuv8i8 |
| 7248 | { 3128, 5, 1, 4, 482, 0, 0, ARMImpOpBase + 0, 2345, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3128 = VPADALuv8i16 |
| 7249 | { 3127, 5, 1, 4, 482, 0, 0, ARMImpOpBase + 0, 2345, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3127 = VPADALuv4i32 |
| 7250 | { 3126, 5, 1, 4, 785, 0, 0, ARMImpOpBase + 0, 400, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3126 = VPADALuv4i16 |
| 7251 | { 3125, 5, 1, 4, 785, 0, 0, ARMImpOpBase + 0, 400, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3125 = VPADALuv2i32 |
| 7252 | { 3124, 5, 1, 4, 482, 0, 0, ARMImpOpBase + 0, 2345, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3124 = VPADALuv16i8 |
| 7253 | { 3123, 5, 1, 4, 785, 0, 0, ARMImpOpBase + 0, 400, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3123 = VPADALsv8i8 |
| 7254 | { 3122, 5, 1, 4, 482, 0, 0, ARMImpOpBase + 0, 2345, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3122 = VPADALsv8i16 |
| 7255 | { 3121, 5, 1, 4, 482, 0, 0, ARMImpOpBase + 0, 2345, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3121 = VPADALsv4i32 |
| 7256 | { 3120, 5, 1, 4, 785, 0, 0, ARMImpOpBase + 0, 400, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3120 = VPADALsv4i16 |
| 7257 | { 3119, 5, 1, 4, 785, 0, 0, ARMImpOpBase + 0, 400, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3119 = VPADALsv2i32 |
| 7258 | { 3118, 5, 1, 4, 482, 0, 0, ARMImpOpBase + 0, 2345, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3118 = VPADALsv16i8 |
| 7259 | { 3117, 5, 1, 4, 459, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3117 = VORRq |
| 7260 | { 3116, 5, 1, 4, 471, 0, 0, ARMImpOpBase + 0, 1724, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #3116 = VORRiv8i16 |
| 7261 | { 3115, 5, 1, 4, 471, 0, 0, ARMImpOpBase + 0, 1724, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #3115 = VORRiv4i32 |
| 7262 | { 3114, 5, 1, 4, 471, 0, 0, ARMImpOpBase + 0, 1719, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #3114 = VORRiv4i16 |
| 7263 | { 3113, 5, 1, 4, 471, 0, 0, ARMImpOpBase + 0, 1719, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #3113 = VORRiv2i32 |
| 7264 | { 3112, 5, 1, 4, 460, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3112 = VORRd |
| 7265 | { 3111, 5, 1, 4, 459, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3111 = VORNq |
| 7266 | { 3110, 5, 1, 4, 460, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3110 = VORNd |
| 7267 | { 3109, 5, 1, 4, 530, 0, 0, ARMImpOpBase + 0, 1704, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3109 = VNMULS |
| 7268 | { 3108, 5, 1, 4, 202, 0, 0, ARMImpOpBase + 0, 1694, 0, 0x8800ULL }, // Inst #3108 = VNMULH |
| 7269 | { 3107, 5, 1, 4, 1261, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3107 = VNMULD |
| 7270 | { 3106, 6, 1, 4, 544, 0, 0, ARMImpOpBase + 0, 1872, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3106 = VNMLSS |
| 7271 | { 3105, 6, 1, 4, 541, 0, 0, ARMImpOpBase + 0, 1852, 0, 0x8800ULL }, // Inst #3105 = VNMLSH |
| 7272 | { 3104, 6, 1, 4, 540, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3104 = VNMLSD |
| 7273 | { 3103, 6, 1, 4, 544, 0, 0, ARMImpOpBase + 0, 1872, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3103 = VNMLAS |
| 7274 | { 3102, 6, 1, 4, 541, 0, 0, ARMImpOpBase + 0, 1852, 0, 0x8800ULL }, // Inst #3102 = VNMLAH |
| 7275 | { 3101, 6, 1, 4, 540, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3101 = VNMLAD |
| 7276 | { 3100, 4, 1, 4, 783, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3100 = VNEGs8q |
| 7277 | { 3099, 4, 1, 4, 782, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3099 = VNEGs8d |
| 7278 | { 3098, 4, 1, 4, 783, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3098 = VNEGs32q |
| 7279 | { 3097, 4, 1, 4, 782, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3097 = VNEGs32d |
| 7280 | { 3096, 4, 1, 4, 783, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3096 = VNEGs16q |
| 7281 | { 3095, 4, 1, 4, 782, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3095 = VNEGs16d |
| 7282 | { 3094, 4, 1, 4, 781, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3094 = VNEGhq |
| 7283 | { 3093, 4, 1, 4, 780, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3093 = VNEGhd |
| 7284 | { 3092, 4, 1, 4, 464, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3092 = VNEGfd |
| 7285 | { 3091, 4, 1, 4, 463, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3091 = VNEGf32q |
| 7286 | { 3090, 4, 1, 4, 518, 0, 0, ARMImpOpBase + 0, 1686, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // Inst #3090 = VNEGS |
| 7287 | { 3089, 4, 1, 4, 779, 0, 0, ARMImpOpBase + 0, 1682, 0, 0x8780ULL }, // Inst #3089 = VNEGH |
| 7288 | { 3088, 4, 1, 4, 517, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3088 = VNEGD |
| 7289 | { 3087, 4, 1, 4, 974, 0, 0, ARMImpOpBase + 0, 2289, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // Inst #3087 = VMVNv8i16 |
| 7290 | { 3086, 4, 1, 4, 974, 0, 0, ARMImpOpBase + 0, 2289, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // Inst #3086 = VMVNv4i32 |
| 7291 | { 3085, 4, 1, 4, 974, 0, 0, ARMImpOpBase + 0, 864, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // Inst #3085 = VMVNv4i16 |
| 7292 | { 3084, 4, 1, 4, 974, 0, 0, ARMImpOpBase + 0, 864, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // Inst #3084 = VMVNv2i32 |
| 7293 | { 3083, 4, 1, 4, 571, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3083 = VMVNq |
| 7294 | { 3082, 4, 1, 4, 571, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3082 = VMVNd |
| 7295 | { 3081, 5, 1, 4, 975, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3081 = VMULv8i8 |
| 7296 | { 3080, 5, 1, 4, 979, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3080 = VMULv8i16 |
| 7297 | { 3079, 5, 1, 4, 538, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3079 = VMULv4i32 |
| 7298 | { 3078, 5, 1, 4, 975, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3078 = VMULv4i16 |
| 7299 | { 3077, 5, 1, 4, 976, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3077 = VMULv2i32 |
| 7300 | { 3076, 5, 1, 4, 979, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3076 = VMULv16i8 |
| 7301 | { 3075, 6, 1, 4, 979, 0, 0, ARMImpOpBase + 0, 2339, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3075 = VMULslv8i16 |
| 7302 | { 3074, 6, 1, 4, 538, 0, 0, ARMImpOpBase + 0, 2327, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3074 = VMULslv4i32 |
| 7303 | { 3073, 6, 1, 4, 975, 0, 0, ARMImpOpBase + 0, 2333, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3073 = VMULslv4i16 |
| 7304 | { 3072, 6, 1, 4, 976, 0, 0, ARMImpOpBase + 0, 2321, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3072 = VMULslv2i32 |
| 7305 | { 3071, 6, 1, 4, 534, 0, 0, ARMImpOpBase + 0, 2339, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3071 = VMULslhq |
| 7306 | { 3070, 6, 1, 4, 533, 0, 0, ARMImpOpBase + 0, 2333, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3070 = VMULslhd |
| 7307 | { 3069, 6, 1, 4, 536, 0, 0, ARMImpOpBase + 0, 2327, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3069 = VMULslfq |
| 7308 | { 3068, 6, 1, 4, 535, 0, 0, ARMImpOpBase + 0, 2321, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3068 = VMULslfd |
| 7309 | { 3067, 5, 1, 4, 979, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3067 = VMULpq |
| 7310 | { 3066, 5, 1, 4, 975, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3066 = VMULpd |
| 7311 | { 3065, 5, 1, 4, 999, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3065 = VMULhq |
| 7312 | { 3064, 5, 1, 4, 998, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3064 = VMULhd |
| 7313 | { 3063, 5, 1, 4, 532, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3063 = VMULfq |
| 7314 | { 3062, 5, 1, 4, 531, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3062 = VMULfd |
| 7315 | { 3061, 5, 1, 4, 530, 0, 0, ARMImpOpBase + 0, 1704, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3061 = VMULS |
| 7316 | { 3060, 5, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3060 = VMULLuv8i16 |
| 7317 | { 3059, 5, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3059 = VMULLuv4i32 |
| 7318 | { 3058, 5, 1, 4, 537, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3058 = VMULLuv2i64 |
| 7319 | { 3057, 5, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3057 = VMULLsv8i16 |
| 7320 | { 3056, 5, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3056 = VMULLsv4i32 |
| 7321 | { 3055, 5, 1, 4, 537, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3055 = VMULLsv2i64 |
| 7322 | { 3054, 6, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 2315, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3054 = VMULLsluv4i16 |
| 7323 | { 3053, 6, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 2309, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3053 = VMULLsluv2i32 |
| 7324 | { 3052, 6, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 2315, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3052 = VMULLslsv4i16 |
| 7325 | { 3051, 6, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 2309, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3051 = VMULLslsv2i32 |
| 7326 | { 3050, 5, 1, 4, 986, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3050 = VMULLp8 |
| 7327 | { 3049, 3, 1, 4, 539, 0, 0, ARMImpOpBase + 0, 1865, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3049 = VMULLp64 |
| 7328 | { 3048, 5, 1, 4, 202, 0, 0, ARMImpOpBase + 0, 1694, 0, 0x8800ULL }, // Inst #3048 = VMULH |
| 7329 | { 3047, 5, 1, 4, 1261, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3047 = VMULD |
| 7330 | { 3046, 3, 0, 4, 1290, 0, 1, ARMImpOpBase + 69, 538, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3046 = VMSR_VPR |
| 7331 | { 3045, 4, 1, 4, 1290, 0, 0, ARMImpOpBase + 0, 2305, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3045 = VMSR_P0 |
| 7332 | { 3044, 3, 0, 4, 587, 0, 1, ARMImpOpBase + 71, 1062, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3044 = VMSR_FPSID |
| 7333 | { 3043, 4, 1, 4, 1290, 0, 0, ARMImpOpBase + 0, 2301, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3043 = VMSR_FPSCR_NZCVQC |
| 7334 | { 3042, 3, 0, 4, 587, 0, 1, ARMImpOpBase + 71, 1062, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3042 = VMSR_FPINST2 |
| 7335 | { 3041, 3, 0, 4, 587, 0, 1, ARMImpOpBase + 71, 1062, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3041 = VMSR_FPINST |
| 7336 | { 3040, 3, 0, 4, 587, 0, 1, ARMImpOpBase + 71, 1062, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3040 = VMSR_FPEXC |
| 7337 | { 3039, 3, 0, 4, 587, 0, 0, ARMImpOpBase + 0, 538, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3039 = VMSR_FPCXTS |
| 7338 | { 3038, 3, 0, 4, 587, 0, 0, ARMImpOpBase + 0, 538, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3038 = VMSR_FPCXTNS |
| 7339 | { 3037, 3, 0, 4, 1290, 0, 1, ARMImpOpBase + 71, 1062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3037 = VMSR |
| 7340 | { 3036, 3, 1, 4, 1291, 1, 0, ARMImpOpBase + 69, 538, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3036 = VMRS_VPR |
| 7341 | { 3035, 4, 1, 4, 1291, 0, 0, ARMImpOpBase + 0, 2297, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3035 = VMRS_P0 |
| 7342 | { 3034, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1062, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3034 = VMRS_MVFR2 |
| 7343 | { 3033, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1062, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3033 = VMRS_MVFR1 |
| 7344 | { 3032, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1062, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3032 = VMRS_MVFR0 |
| 7345 | { 3031, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1062, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3031 = VMRS_FPSID |
| 7346 | { 3030, 4, 1, 4, 1292, 1, 0, ARMImpOpBase + 71, 2293, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3030 = VMRS_FPSCR_NZCVQC |
| 7347 | { 3029, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1062, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3029 = VMRS_FPINST2 |
| 7348 | { 3028, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1062, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3028 = VMRS_FPINST |
| 7349 | { 3027, 3, 1, 4, 586, 1, 0, ARMImpOpBase + 71, 1062, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3027 = VMRS_FPEXC |
| 7350 | { 3026, 3, 1, 4, 586, 0, 0, ARMImpOpBase + 0, 538, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3026 = VMRS_FPCXTS |
| 7351 | { 3025, 3, 1, 4, 586, 0, 0, ARMImpOpBase + 0, 538, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3025 = VMRS_FPCXTNS |
| 7352 | { 3024, 3, 1, 4, 1293, 1, 0, ARMImpOpBase + 71, 1062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3024 = VMRS |
| 7353 | { 3023, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 864, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3023 = VMOVv8i8 |
| 7354 | { 3022, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 2289, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3022 = VMOVv8i16 |
| 7355 | { 3021, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 2289, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3021 = VMOVv4i32 |
| 7356 | { 3020, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 864, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3020 = VMOVv4i16 |
| 7357 | { 3019, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 2289, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3019 = VMOVv4f32 |
| 7358 | { 3018, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 2289, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3018 = VMOVv2i64 |
| 7359 | { 3017, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 864, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3017 = VMOVv2i32 |
| 7360 | { 3016, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 864, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3016 = VMOVv2f32 |
| 7361 | { 3015, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 864, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3015 = VMOVv1i64 |
| 7362 | { 3014, 4, 1, 4, 568, 0, 0, ARMImpOpBase + 0, 2289, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3014 = VMOVv16i8 |
| 7363 | { 3013, 6, 2, 4, 583, 0, 0, ARMImpOpBase + 0, 2283, 0|(1ULL<<MCID::Predicable), 0x18a80ULL }, // Inst #3013 = VMOVSRR |
| 7364 | { 3012, 4, 1, 4, 579, 0, 0, ARMImpOpBase + 0, 2279, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18a00ULL }, // Inst #3012 = VMOVSR |
| 7365 | { 3011, 4, 1, 4, 1215, 0, 0, ARMImpOpBase + 0, 1686, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3011 = VMOVS |
| 7366 | { 3010, 4, 1, 4, 578, 0, 0, ARMImpOpBase + 0, 2275, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18900ULL }, // Inst #3010 = VMOVRS |
| 7367 | { 3009, 6, 2, 4, 581, 0, 0, ARMImpOpBase + 0, 2269, 0|(1ULL<<MCID::Predicable), 0x18980ULL }, // Inst #3009 = VMOVRRS |
| 7368 | { 3008, 5, 2, 4, 581, 0, 0, ARMImpOpBase + 0, 2264, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtractSubreg), 0x18980ULL }, // Inst #3008 = VMOVRRD |
| 7369 | { 3007, 4, 1, 4, 1216, 0, 0, ARMImpOpBase + 0, 2260, 0, 0x8900ULL }, // Inst #3007 = VMOVRH |
| 7370 | { 3006, 4, 1, 4, 572, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3006 = VMOVNv8i8 |
| 7371 | { 3005, 4, 1, 4, 572, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3005 = VMOVNv4i16 |
| 7372 | { 3004, 4, 1, 4, 572, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3004 = VMOVNv2i32 |
| 7373 | { 3003, 4, 1, 4, 573, 0, 0, ARMImpOpBase + 0, 1823, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3003 = VMOVLuv8i16 |
| 7374 | { 3002, 4, 1, 4, 573, 0, 0, ARMImpOpBase + 0, 1823, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3002 = VMOVLuv4i32 |
| 7375 | { 3001, 4, 1, 4, 573, 0, 0, ARMImpOpBase + 0, 1823, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3001 = VMOVLuv2i64 |
| 7376 | { 3000, 4, 1, 4, 573, 0, 0, ARMImpOpBase + 0, 1823, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3000 = VMOVLsv8i16 |
| 7377 | { 2999, 4, 1, 4, 573, 0, 0, ARMImpOpBase + 0, 1823, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2999 = VMOVLsv4i32 |
| 7378 | { 2998, 4, 1, 4, 573, 0, 0, ARMImpOpBase + 0, 1823, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2998 = VMOVLsv2i64 |
| 7379 | { 2997, 4, 1, 4, 1213, 0, 0, ARMImpOpBase + 0, 2256, 0, 0x8a00ULL }, // Inst #2997 = VMOVHR |
| 7380 | { 2996, 2, 1, 4, 1212, 0, 0, ARMImpOpBase + 0, 1798, 0, 0x8780ULL }, // Inst #2996 = VMOVH |
| 7381 | { 2995, 5, 1, 4, 582, 0, 0, ARMImpOpBase + 0, 2251, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::RegSequence), 0x18a80ULL }, // Inst #2995 = VMOVDRR |
| 7382 | { 2994, 4, 1, 4, 1214, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2994 = VMOVD |
| 7383 | { 2993, 4, 1, 4, 50, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #2993 = VMMLA |
| 7384 | { 2992, 6, 1, 4, 981, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2992 = VMLSv8i8 |
| 7385 | { 2991, 6, 1, 4, 548, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2991 = VMLSv8i16 |
| 7386 | { 2990, 6, 1, 4, 547, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2990 = VMLSv4i32 |
| 7387 | { 2989, 6, 1, 4, 981, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2989 = VMLSv4i16 |
| 7388 | { 2988, 6, 1, 4, 980, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2988 = VMLSv2i32 |
| 7389 | { 2987, 6, 1, 4, 548, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2987 = VMLSv16i8 |
| 7390 | { 2986, 7, 1, 4, 548, 0, 0, ARMImpOpBase + 0, 2244, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2986 = VMLSslv8i16 |
| 7391 | { 2985, 7, 1, 4, 547, 0, 0, ARMImpOpBase + 0, 2230, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2985 = VMLSslv4i32 |
| 7392 | { 2984, 7, 1, 4, 981, 0, 0, ARMImpOpBase + 0, 2237, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2984 = VMLSslv4i16 |
| 7393 | { 2983, 7, 1, 4, 980, 0, 0, ARMImpOpBase + 0, 2223, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2983 = VMLSslv2i32 |
| 7394 | { 2982, 7, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 2244, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2982 = VMLSslhq |
| 7395 | { 2981, 7, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 2237, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2981 = VMLSslhd |
| 7396 | { 2980, 7, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 2230, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2980 = VMLSslfq |
| 7397 | { 2979, 7, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 2223, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2979 = VMLSslfd |
| 7398 | { 2978, 6, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2978 = VMLShq |
| 7399 | { 2977, 6, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2977 = VMLShd |
| 7400 | { 2976, 6, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2976 = VMLSfq |
| 7401 | { 2975, 6, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2975 = VMLSfd |
| 7402 | { 2974, 6, 1, 4, 544, 0, 0, ARMImpOpBase + 0, 1872, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #2974 = VMLSS |
| 7403 | { 2973, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2973 = VMLSLuv8i16 |
| 7404 | { 2972, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2972 = VMLSLuv4i32 |
| 7405 | { 2971, 6, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2971 = VMLSLuv2i64 |
| 7406 | { 2970, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2970 = VMLSLsv8i16 |
| 7407 | { 2969, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2969 = VMLSLsv4i32 |
| 7408 | { 2968, 6, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2968 = VMLSLsv2i64 |
| 7409 | { 2967, 7, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 2216, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2967 = VMLSLsluv4i16 |
| 7410 | { 2966, 7, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 2209, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2966 = VMLSLsluv2i32 |
| 7411 | { 2965, 7, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 2216, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2965 = VMLSLslsv4i16 |
| 7412 | { 2964, 7, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 2209, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2964 = VMLSLslsv2i32 |
| 7413 | { 2963, 6, 1, 4, 541, 0, 0, ARMImpOpBase + 0, 1852, 0, 0x8800ULL }, // Inst #2963 = VMLSH |
| 7414 | { 2962, 6, 1, 4, 540, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2962 = VMLSD |
| 7415 | { 2961, 6, 1, 4, 981, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2961 = VMLAv8i8 |
| 7416 | { 2960, 6, 1, 4, 548, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2960 = VMLAv8i16 |
| 7417 | { 2959, 6, 1, 4, 547, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2959 = VMLAv4i32 |
| 7418 | { 2958, 6, 1, 4, 981, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2958 = VMLAv4i16 |
| 7419 | { 2957, 6, 1, 4, 980, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2957 = VMLAv2i32 |
| 7420 | { 2956, 6, 1, 4, 548, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2956 = VMLAv16i8 |
| 7421 | { 2955, 7, 1, 4, 548, 0, 0, ARMImpOpBase + 0, 2244, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2955 = VMLAslv8i16 |
| 7422 | { 2954, 7, 1, 4, 547, 0, 0, ARMImpOpBase + 0, 2230, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2954 = VMLAslv4i32 |
| 7423 | { 2953, 7, 1, 4, 981, 0, 0, ARMImpOpBase + 0, 2237, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2953 = VMLAslv4i16 |
| 7424 | { 2952, 7, 1, 4, 980, 0, 0, ARMImpOpBase + 0, 2223, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2952 = VMLAslv2i32 |
| 7425 | { 2951, 7, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 2244, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2951 = VMLAslhq |
| 7426 | { 2950, 7, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 2237, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2950 = VMLAslhd |
| 7427 | { 2949, 7, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 2230, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2949 = VMLAslfq |
| 7428 | { 2948, 7, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 2223, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2948 = VMLAslfd |
| 7429 | { 2947, 6, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2947 = VMLAhq |
| 7430 | { 2946, 6, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2946 = VMLAhd |
| 7431 | { 2945, 6, 1, 4, 546, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2945 = VMLAfq |
| 7432 | { 2944, 6, 1, 4, 545, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2944 = VMLAfd |
| 7433 | { 2943, 6, 1, 4, 544, 0, 0, ARMImpOpBase + 0, 1872, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #2943 = VMLAS |
| 7434 | { 2942, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2942 = VMLALuv8i16 |
| 7435 | { 2941, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2941 = VMLALuv4i32 |
| 7436 | { 2940, 6, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2940 = VMLALuv2i64 |
| 7437 | { 2939, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2939 = VMLALsv8i16 |
| 7438 | { 2938, 6, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2938 = VMLALsv4i32 |
| 7439 | { 2937, 6, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2937 = VMLALsv2i64 |
| 7440 | { 2936, 7, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 2216, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2936 = VMLALsluv4i16 |
| 7441 | { 2935, 7, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 2209, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2935 = VMLALsluv2i32 |
| 7442 | { 2934, 7, 1, 4, 543, 0, 0, ARMImpOpBase + 0, 2216, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2934 = VMLALslsv4i16 |
| 7443 | { 2933, 7, 1, 4, 542, 0, 0, ARMImpOpBase + 0, 2209, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2933 = VMLALslsv2i32 |
| 7444 | { 2932, 6, 1, 4, 541, 0, 0, ARMImpOpBase + 0, 1852, 0, 0x8800ULL }, // Inst #2932 = VMLAH |
| 7445 | { 2931, 6, 1, 4, 540, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2931 = VMLAD |
| 7446 | { 2930, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2930 = VMINuv8i8 |
| 7447 | { 2929, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2929 = VMINuv8i16 |
| 7448 | { 2928, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2928 = VMINuv4i32 |
| 7449 | { 2927, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2927 = VMINuv4i16 |
| 7450 | { 2926, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2926 = VMINuv2i32 |
| 7451 | { 2925, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2925 = VMINuv16i8 |
| 7452 | { 2924, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2924 = VMINsv8i8 |
| 7453 | { 2923, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2923 = VMINsv8i16 |
| 7454 | { 2922, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2922 = VMINsv4i32 |
| 7455 | { 2921, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2921 = VMINsv4i16 |
| 7456 | { 2920, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2920 = VMINsv2i32 |
| 7457 | { 2919, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2919 = VMINsv16i8 |
| 7458 | { 2918, 5, 1, 4, 523, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2918 = VMINhq |
| 7459 | { 2917, 5, 1, 4, 522, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2917 = VMINhd |
| 7460 | { 2916, 5, 1, 4, 523, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2916 = VMINfq |
| 7461 | { 2915, 5, 1, 4, 522, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2915 = VMINfd |
| 7462 | { 2914, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2914 = VMAXuv8i8 |
| 7463 | { 2913, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2913 = VMAXuv8i16 |
| 7464 | { 2912, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2912 = VMAXuv4i32 |
| 7465 | { 2911, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2911 = VMAXuv4i16 |
| 7466 | { 2910, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2910 = VMAXuv2i32 |
| 7467 | { 2909, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2909 = VMAXuv16i8 |
| 7468 | { 2908, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2908 = VMAXsv8i8 |
| 7469 | { 2907, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2907 = VMAXsv8i16 |
| 7470 | { 2906, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2906 = VMAXsv4i32 |
| 7471 | { 2905, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2905 = VMAXsv4i16 |
| 7472 | { 2904, 5, 1, 4, 963, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2904 = VMAXsv2i32 |
| 7473 | { 2903, 5, 1, 4, 777, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2903 = VMAXsv16i8 |
| 7474 | { 2902, 5, 1, 4, 523, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2902 = VMAXhq |
| 7475 | { 2901, 5, 1, 4, 522, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2901 = VMAXhd |
| 7476 | { 2900, 5, 1, 4, 523, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2900 = VMAXfq |
| 7477 | { 2899, 5, 1, 4, 522, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2899 = VMAXfd |
| 7478 | { 2898, 4, 0, 4, 957, 35, 3, ARMImpOpBase + 148, 2205, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // Inst #2898 = VLSTM_T2 |
| 7479 | { 2897, 4, 0, 4, 957, 19, 3, ARMImpOpBase + 126, 2205, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // Inst #2897 = VLSTM |
| 7480 | { 2896, 4, 0, 4, 937, 0, 35, ARMImpOpBase + 91, 2205, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // Inst #2896 = VLLDM_T2 |
| 7481 | { 2895, 4, 0, 4, 937, 0, 19, ARMImpOpBase + 72, 2205, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // Inst #2895 = VLLDM |
| 7482 | { 2894, 5, 1, 4, 749, 0, 1, ARMImpOpBase + 69, 2189, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2894 = VLDR_VPR_pre |
| 7483 | { 2893, 5, 1, 4, 749, 0, 1, ARMImpOpBase + 69, 2189, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2893 = VLDR_VPR_post |
| 7484 | { 2892, 4, 0, 4, 749, 0, 1, ARMImpOpBase + 69, 2185, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2892 = VLDR_VPR_off |
| 7485 | { 2891, 6, 2, 4, 749, 0, 0, ARMImpOpBase + 0, 2199, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2891 = VLDR_P0_pre |
| 7486 | { 2890, 6, 2, 4, 749, 0, 0, ARMImpOpBase + 0, 2199, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2890 = VLDR_P0_post |
| 7487 | { 2889, 5, 1, 4, 749, 0, 0, ARMImpOpBase + 0, 2194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2889 = VLDR_P0_off |
| 7488 | { 2888, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2888 = VLDR_FPSCR_pre |
| 7489 | { 2887, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2887 = VLDR_FPSCR_post |
| 7490 | { 2886, 4, 0, 4, 749, 1, 0, ARMImpOpBase + 71, 2185, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2886 = VLDR_FPSCR_off |
| 7491 | { 2885, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2885 = VLDR_FPSCR_NZCVQC_pre |
| 7492 | { 2884, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2884 = VLDR_FPSCR_NZCVQC_post |
| 7493 | { 2883, 4, 0, 4, 749, 1, 0, ARMImpOpBase + 71, 2185, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2883 = VLDR_FPSCR_NZCVQC_off |
| 7494 | { 2882, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2882 = VLDR_FPCXTS_pre |
| 7495 | { 2881, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2881 = VLDR_FPCXTS_post |
| 7496 | { 2880, 4, 0, 4, 749, 1, 0, ARMImpOpBase + 71, 2185, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2880 = VLDR_FPCXTS_off |
| 7497 | { 2879, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2879 = VLDR_FPCXTNS_pre |
| 7498 | { 2878, 5, 1, 4, 749, 1, 0, ARMImpOpBase + 71, 2189, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2878 = VLDR_FPCXTNS_post |
| 7499 | { 2877, 4, 0, 4, 749, 1, 0, ARMImpOpBase + 71, 2185, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2877 = VLDR_FPCXTNS_off |
| 7500 | { 2876, 5, 1, 4, 590, 0, 0, ARMImpOpBase + 0, 2180, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL }, // Inst #2876 = VLDRS |
| 7501 | { 2875, 5, 1, 4, 748, 0, 0, ARMImpOpBase + 0, 2175, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x18b13ULL }, // Inst #2875 = VLDRH |
| 7502 | { 2874, 5, 1, 4, 589, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL }, // Inst #2874 = VLDRD |
| 7503 | { 2873, 5, 1, 4, 596, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL }, // Inst #2873 = VLDMSIA_UPD |
| 7504 | { 2872, 4, 0, 4, 595, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18b84ULL }, // Inst #2872 = VLDMSIA |
| 7505 | { 2871, 5, 1, 4, 596, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL }, // Inst #2871 = VLDMSDB_UPD |
| 7506 | { 2870, 4, 1, 4, 593, 0, 0, ARMImpOpBase + 0, 2171, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18004ULL }, // Inst #2870 = VLDMQIA |
| 7507 | { 2869, 5, 1, 4, 596, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL }, // Inst #2869 = VLDMDIA_UPD |
| 7508 | { 2868, 4, 0, 4, 595, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8b84ULL }, // Inst #2868 = VLDMDIA |
| 7509 | { 2867, 5, 1, 4, 596, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL }, // Inst #2867 = VLDMDDB_UPD |
| 7510 | { 2866, 8, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2866 = VLD4q8oddPseudo_UPD |
| 7511 | { 2865, 6, 1, 4, 616, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2865 = VLD4q8oddPseudo |
| 7512 | { 2864, 10, 5, 4, 617, 0, 0, ARMImpOpBase + 0, 2133, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2864 = VLD4q8_UPD |
| 7513 | { 2863, 8, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2863 = VLD4q8Pseudo_UPD |
| 7514 | { 2862, 8, 4, 4, 615, 0, 0, ARMImpOpBase + 0, 2125, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2862 = VLD4q8 |
| 7515 | { 2861, 8, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2861 = VLD4q32oddPseudo_UPD |
| 7516 | { 2860, 6, 1, 4, 616, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2860 = VLD4q32oddPseudo |
| 7517 | { 2859, 10, 5, 4, 617, 0, 0, ARMImpOpBase + 0, 2133, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2859 = VLD4q32_UPD |
| 7518 | { 2858, 8, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2858 = VLD4q32Pseudo_UPD |
| 7519 | { 2857, 8, 4, 4, 615, 0, 0, ARMImpOpBase + 0, 2125, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2857 = VLD4q32 |
| 7520 | { 2856, 8, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2856 = VLD4q16oddPseudo_UPD |
| 7521 | { 2855, 6, 1, 4, 616, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2855 = VLD4q16oddPseudo |
| 7522 | { 2854, 10, 5, 4, 617, 0, 0, ARMImpOpBase + 0, 2133, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2854 = VLD4q16_UPD |
| 7523 | { 2853, 8, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2853 = VLD4q16Pseudo_UPD |
| 7524 | { 2852, 8, 4, 4, 615, 0, 0, ARMImpOpBase + 0, 2125, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2852 = VLD4q16 |
| 7525 | { 2851, 10, 5, 4, 617, 0, 0, ARMImpOpBase + 0, 2133, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2851 = VLD4d8_UPD |
| 7526 | { 2850, 7, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 2069, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2850 = VLD4d8Pseudo_UPD |
| 7527 | { 2849, 5, 1, 4, 616, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2849 = VLD4d8Pseudo |
| 7528 | { 2848, 8, 4, 4, 615, 0, 0, ARMImpOpBase + 0, 2125, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2848 = VLD4d8 |
| 7529 | { 2847, 10, 5, 4, 617, 0, 0, ARMImpOpBase + 0, 2133, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2847 = VLD4d32_UPD |
| 7530 | { 2846, 7, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 2069, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2846 = VLD4d32Pseudo_UPD |
| 7531 | { 2845, 5, 1, 4, 616, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2845 = VLD4d32Pseudo |
| 7532 | { 2844, 8, 4, 4, 615, 0, 0, ARMImpOpBase + 0, 2125, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2844 = VLD4d32 |
| 7533 | { 2843, 10, 5, 4, 617, 0, 0, ARMImpOpBase + 0, 2133, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2843 = VLD4d16_UPD |
| 7534 | { 2842, 7, 2, 4, 618, 0, 0, ARMImpOpBase + 0, 2069, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2842 = VLD4d16Pseudo_UPD |
| 7535 | { 2841, 5, 1, 4, 616, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2841 = VLD4d16Pseudo |
| 7536 | { 2840, 8, 4, 4, 615, 0, 0, ARMImpOpBase + 0, 2125, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2840 = VLD4d16 |
| 7537 | { 2839, 15, 5, 4, 1009, 0, 0, ARMImpOpBase + 0, 2156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2839 = VLD4LNq32_UPD |
| 7538 | { 2838, 9, 2, 4, 1010, 0, 0, ARMImpOpBase + 0, 2116, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2838 = VLD4LNq32Pseudo_UPD |
| 7539 | { 2837, 7, 1, 4, 1008, 0, 0, ARMImpOpBase + 0, 2109, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2837 = VLD4LNq32Pseudo |
| 7540 | { 2836, 13, 4, 4, 1008, 0, 0, ARMImpOpBase + 0, 2143, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2836 = VLD4LNq32 |
| 7541 | { 2835, 15, 5, 4, 641, 0, 0, ARMImpOpBase + 0, 2156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2835 = VLD4LNq16_UPD |
| 7542 | { 2834, 9, 2, 4, 643, 0, 0, ARMImpOpBase + 0, 2116, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2834 = VLD4LNq16Pseudo_UPD |
| 7543 | { 2833, 7, 1, 4, 638, 0, 0, ARMImpOpBase + 0, 2109, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2833 = VLD4LNq16Pseudo |
| 7544 | { 2832, 13, 4, 4, 638, 0, 0, ARMImpOpBase + 0, 2143, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2832 = VLD4LNq16 |
| 7545 | { 2831, 15, 5, 4, 641, 0, 0, ARMImpOpBase + 0, 2156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2831 = VLD4LNd8_UPD |
| 7546 | { 2830, 9, 2, 4, 643, 0, 0, ARMImpOpBase + 0, 2053, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2830 = VLD4LNd8Pseudo_UPD |
| 7547 | { 2829, 7, 1, 4, 638, 0, 0, ARMImpOpBase + 0, 2046, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2829 = VLD4LNd8Pseudo |
| 7548 | { 2828, 13, 4, 4, 638, 0, 0, ARMImpOpBase + 0, 2143, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2828 = VLD4LNd8 |
| 7549 | { 2827, 15, 5, 4, 1009, 0, 0, ARMImpOpBase + 0, 2156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2827 = VLD4LNd32_UPD |
| 7550 | { 2826, 9, 2, 4, 1010, 0, 0, ARMImpOpBase + 0, 2053, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2826 = VLD4LNd32Pseudo_UPD |
| 7551 | { 2825, 7, 1, 4, 1008, 0, 0, ARMImpOpBase + 0, 2046, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2825 = VLD4LNd32Pseudo |
| 7552 | { 2824, 13, 4, 4, 1008, 0, 0, ARMImpOpBase + 0, 2143, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2824 = VLD4LNd32 |
| 7553 | { 2823, 15, 5, 4, 641, 0, 0, ARMImpOpBase + 0, 2156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2823 = VLD4LNd16_UPD |
| 7554 | { 2822, 9, 2, 4, 643, 0, 0, ARMImpOpBase + 0, 2053, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2822 = VLD4LNd16Pseudo_UPD |
| 7555 | { 2821, 7, 1, 4, 638, 0, 0, ARMImpOpBase + 0, 2046, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2821 = VLD4LNd16Pseudo |
| 7556 | { 2820, 13, 4, 4, 638, 0, 0, ARMImpOpBase + 0, 2143, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2820 = VLD4LNd16 |
| 7557 | { 2819, 10, 5, 4, 640, 0, 0, ARMImpOpBase + 0, 2133, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2819 = VLD4DUPq8_UPD |
| 7558 | { 2818, 8, 2, 4, 1053, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2818 = VLD4DUPq8OddPseudo_UPD |
| 7559 | { 2817, 6, 1, 4, 1052, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2817 = VLD4DUPq8OddPseudo |
| 7560 | { 2816, 6, 1, 4, 1052, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2816 = VLD4DUPq8EvenPseudo |
| 7561 | { 2815, 8, 4, 4, 637, 0, 0, ARMImpOpBase + 0, 2125, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2815 = VLD4DUPq8 |
| 7562 | { 2814, 10, 5, 4, 640, 0, 0, ARMImpOpBase + 0, 2133, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2814 = VLD4DUPq32_UPD |
| 7563 | { 2813, 8, 2, 4, 1053, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2813 = VLD4DUPq32OddPseudo_UPD |
| 7564 | { 2812, 6, 1, 4, 1052, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2812 = VLD4DUPq32OddPseudo |
| 7565 | { 2811, 6, 1, 4, 1052, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2811 = VLD4DUPq32EvenPseudo |
| 7566 | { 2810, 8, 4, 4, 637, 0, 0, ARMImpOpBase + 0, 2125, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2810 = VLD4DUPq32 |
| 7567 | { 2809, 10, 5, 4, 640, 0, 0, ARMImpOpBase + 0, 2133, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2809 = VLD4DUPq16_UPD |
| 7568 | { 2808, 8, 2, 4, 1053, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2808 = VLD4DUPq16OddPseudo_UPD |
| 7569 | { 2807, 6, 1, 4, 1052, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2807 = VLD4DUPq16OddPseudo |
| 7570 | { 2806, 6, 1, 4, 1052, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2806 = VLD4DUPq16EvenPseudo |
| 7571 | { 2805, 8, 4, 4, 637, 0, 0, ARMImpOpBase + 0, 2125, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2805 = VLD4DUPq16 |
| 7572 | { 2804, 10, 5, 4, 640, 0, 0, ARMImpOpBase + 0, 2133, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2804 = VLD4DUPd8_UPD |
| 7573 | { 2803, 7, 2, 4, 642, 0, 0, ARMImpOpBase + 0, 2069, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2803 = VLD4DUPd8Pseudo_UPD |
| 7574 | { 2802, 5, 1, 4, 639, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2802 = VLD4DUPd8Pseudo |
| 7575 | { 2801, 8, 4, 4, 637, 0, 0, ARMImpOpBase + 0, 2125, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2801 = VLD4DUPd8 |
| 7576 | { 2800, 10, 5, 4, 640, 0, 0, ARMImpOpBase + 0, 2133, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2800 = VLD4DUPd32_UPD |
| 7577 | { 2799, 7, 2, 4, 642, 0, 0, ARMImpOpBase + 0, 2069, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2799 = VLD4DUPd32Pseudo_UPD |
| 7578 | { 2798, 5, 1, 4, 639, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2798 = VLD4DUPd32Pseudo |
| 7579 | { 2797, 8, 4, 4, 637, 0, 0, ARMImpOpBase + 0, 2125, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2797 = VLD4DUPd32 |
| 7580 | { 2796, 10, 5, 4, 640, 0, 0, ARMImpOpBase + 0, 2133, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2796 = VLD4DUPd16_UPD |
| 7581 | { 2795, 7, 2, 4, 642, 0, 0, ARMImpOpBase + 0, 2069, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2795 = VLD4DUPd16Pseudo_UPD |
| 7582 | { 2794, 5, 1, 4, 639, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2794 = VLD4DUPd16Pseudo |
| 7583 | { 2793, 8, 4, 4, 637, 0, 0, ARMImpOpBase + 0, 2125, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2793 = VLD4DUPd16 |
| 7584 | { 2792, 8, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2792 = VLD3q8oddPseudo_UPD |
| 7585 | { 2791, 6, 1, 4, 612, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2791 = VLD3q8oddPseudo |
| 7586 | { 2790, 9, 4, 4, 613, 0, 0, ARMImpOpBase + 0, 2076, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2790 = VLD3q8_UPD |
| 7587 | { 2789, 8, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2789 = VLD3q8Pseudo_UPD |
| 7588 | { 2788, 7, 3, 4, 611, 0, 0, ARMImpOpBase + 0, 2062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2788 = VLD3q8 |
| 7589 | { 2787, 8, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2787 = VLD3q32oddPseudo_UPD |
| 7590 | { 2786, 6, 1, 4, 612, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2786 = VLD3q32oddPseudo |
| 7591 | { 2785, 9, 4, 4, 613, 0, 0, ARMImpOpBase + 0, 2076, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2785 = VLD3q32_UPD |
| 7592 | { 2784, 8, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2784 = VLD3q32Pseudo_UPD |
| 7593 | { 2783, 7, 3, 4, 611, 0, 0, ARMImpOpBase + 0, 2062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2783 = VLD3q32 |
| 7594 | { 2782, 8, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2782 = VLD3q16oddPseudo_UPD |
| 7595 | { 2781, 6, 1, 4, 612, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2781 = VLD3q16oddPseudo |
| 7596 | { 2780, 9, 4, 4, 613, 0, 0, ARMImpOpBase + 0, 2076, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2780 = VLD3q16_UPD |
| 7597 | { 2779, 8, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2779 = VLD3q16Pseudo_UPD |
| 7598 | { 2778, 7, 3, 4, 611, 0, 0, ARMImpOpBase + 0, 2062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2778 = VLD3q16 |
| 7599 | { 2777, 9, 4, 4, 613, 0, 0, ARMImpOpBase + 0, 2076, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2777 = VLD3d8_UPD |
| 7600 | { 2776, 7, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 2069, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2776 = VLD3d8Pseudo_UPD |
| 7601 | { 2775, 5, 1, 4, 612, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2775 = VLD3d8Pseudo |
| 7602 | { 2774, 7, 3, 4, 611, 0, 0, ARMImpOpBase + 0, 2062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2774 = VLD3d8 |
| 7603 | { 2773, 9, 4, 4, 613, 0, 0, ARMImpOpBase + 0, 2076, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2773 = VLD3d32_UPD |
| 7604 | { 2772, 7, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 2069, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2772 = VLD3d32Pseudo_UPD |
| 7605 | { 2771, 5, 1, 4, 612, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2771 = VLD3d32Pseudo |
| 7606 | { 2770, 7, 3, 4, 611, 0, 0, ARMImpOpBase + 0, 2062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2770 = VLD3d32 |
| 7607 | { 2769, 9, 4, 4, 613, 0, 0, ARMImpOpBase + 0, 2076, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2769 = VLD3d16_UPD |
| 7608 | { 2768, 7, 2, 4, 614, 0, 0, ARMImpOpBase + 0, 2069, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2768 = VLD3d16Pseudo_UPD |
| 7609 | { 2767, 5, 1, 4, 612, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2767 = VLD3d16Pseudo |
| 7610 | { 2766, 7, 3, 4, 611, 0, 0, ARMImpOpBase + 0, 2062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2766 = VLD3d16 |
| 7611 | { 2765, 13, 4, 4, 1006, 0, 0, ARMImpOpBase + 0, 2096, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2765 = VLD3LNq32_UPD |
| 7612 | { 2764, 9, 2, 4, 1007, 0, 0, ARMImpOpBase + 0, 2116, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2764 = VLD3LNq32Pseudo_UPD |
| 7613 | { 2763, 7, 1, 4, 1005, 0, 0, ARMImpOpBase + 0, 2109, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2763 = VLD3LNq32Pseudo |
| 7614 | { 2762, 11, 3, 4, 1005, 0, 0, ARMImpOpBase + 0, 2085, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2762 = VLD3LNq32 |
| 7615 | { 2761, 13, 4, 4, 634, 0, 0, ARMImpOpBase + 0, 2096, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2761 = VLD3LNq16_UPD |
| 7616 | { 2760, 9, 2, 4, 636, 0, 0, ARMImpOpBase + 0, 2116, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2760 = VLD3LNq16Pseudo_UPD |
| 7617 | { 2759, 7, 1, 4, 632, 0, 0, ARMImpOpBase + 0, 2109, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2759 = VLD3LNq16Pseudo |
| 7618 | { 2758, 11, 3, 4, 632, 0, 0, ARMImpOpBase + 0, 2085, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2758 = VLD3LNq16 |
| 7619 | { 2757, 13, 4, 4, 634, 0, 0, ARMImpOpBase + 0, 2096, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2757 = VLD3LNd8_UPD |
| 7620 | { 2756, 9, 2, 4, 636, 0, 0, ARMImpOpBase + 0, 2053, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2756 = VLD3LNd8Pseudo_UPD |
| 7621 | { 2755, 7, 1, 4, 632, 0, 0, ARMImpOpBase + 0, 2046, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2755 = VLD3LNd8Pseudo |
| 7622 | { 2754, 11, 3, 4, 632, 0, 0, ARMImpOpBase + 0, 2085, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2754 = VLD3LNd8 |
| 7623 | { 2753, 13, 4, 4, 1006, 0, 0, ARMImpOpBase + 0, 2096, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2753 = VLD3LNd32_UPD |
| 7624 | { 2752, 9, 2, 4, 1007, 0, 0, ARMImpOpBase + 0, 2053, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2752 = VLD3LNd32Pseudo_UPD |
| 7625 | { 2751, 7, 1, 4, 1005, 0, 0, ARMImpOpBase + 0, 2046, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2751 = VLD3LNd32Pseudo |
| 7626 | { 2750, 11, 3, 4, 1005, 0, 0, ARMImpOpBase + 0, 2085, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2750 = VLD3LNd32 |
| 7627 | { 2749, 13, 4, 4, 634, 0, 0, ARMImpOpBase + 0, 2096, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2749 = VLD3LNd16_UPD |
| 7628 | { 2748, 9, 2, 4, 636, 0, 0, ARMImpOpBase + 0, 2053, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2748 = VLD3LNd16Pseudo_UPD |
| 7629 | { 2747, 7, 1, 4, 632, 0, 0, ARMImpOpBase + 0, 2046, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2747 = VLD3LNd16Pseudo |
| 7630 | { 2746, 11, 3, 4, 632, 0, 0, ARMImpOpBase + 0, 2085, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2746 = VLD3LNd16 |
| 7631 | { 2745, 9, 4, 4, 633, 0, 0, ARMImpOpBase + 0, 2076, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2745 = VLD3DUPq8_UPD |
| 7632 | { 2744, 8, 2, 4, 1051, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2744 = VLD3DUPq8OddPseudo_UPD |
| 7633 | { 2743, 6, 1, 4, 1050, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2743 = VLD3DUPq8OddPseudo |
| 7634 | { 2742, 6, 1, 4, 1050, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2742 = VLD3DUPq8EvenPseudo |
| 7635 | { 2741, 7, 3, 4, 631, 0, 0, ARMImpOpBase + 0, 2062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2741 = VLD3DUPq8 |
| 7636 | { 2740, 9, 4, 4, 633, 0, 0, ARMImpOpBase + 0, 2076, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2740 = VLD3DUPq32_UPD |
| 7637 | { 2739, 8, 2, 4, 1051, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2739 = VLD3DUPq32OddPseudo_UPD |
| 7638 | { 2738, 6, 1, 4, 1050, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2738 = VLD3DUPq32OddPseudo |
| 7639 | { 2737, 6, 1, 4, 1050, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2737 = VLD3DUPq32EvenPseudo |
| 7640 | { 2736, 7, 3, 4, 631, 0, 0, ARMImpOpBase + 0, 2062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2736 = VLD3DUPq32 |
| 7641 | { 2735, 9, 4, 4, 633, 0, 0, ARMImpOpBase + 0, 2076, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2735 = VLD3DUPq16_UPD |
| 7642 | { 2734, 8, 2, 4, 1051, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2734 = VLD3DUPq16OddPseudo_UPD |
| 7643 | { 2733, 6, 1, 4, 1050, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2733 = VLD3DUPq16OddPseudo |
| 7644 | { 2732, 6, 1, 4, 1050, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2732 = VLD3DUPq16EvenPseudo |
| 7645 | { 2731, 7, 3, 4, 631, 0, 0, ARMImpOpBase + 0, 2062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2731 = VLD3DUPq16 |
| 7646 | { 2730, 9, 4, 4, 633, 0, 0, ARMImpOpBase + 0, 2076, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2730 = VLD3DUPd8_UPD |
| 7647 | { 2729, 7, 2, 4, 635, 0, 0, ARMImpOpBase + 0, 2069, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2729 = VLD3DUPd8Pseudo_UPD |
| 7648 | { 2728, 5, 1, 4, 631, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2728 = VLD3DUPd8Pseudo |
| 7649 | { 2727, 7, 3, 4, 631, 0, 0, ARMImpOpBase + 0, 2062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2727 = VLD3DUPd8 |
| 7650 | { 2726, 9, 4, 4, 633, 0, 0, ARMImpOpBase + 0, 2076, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2726 = VLD3DUPd32_UPD |
| 7651 | { 2725, 7, 2, 4, 635, 0, 0, ARMImpOpBase + 0, 2069, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2725 = VLD3DUPd32Pseudo_UPD |
| 7652 | { 2724, 5, 1, 4, 631, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2724 = VLD3DUPd32Pseudo |
| 7653 | { 2723, 7, 3, 4, 631, 0, 0, ARMImpOpBase + 0, 2062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2723 = VLD3DUPd32 |
| 7654 | { 2722, 9, 4, 4, 633, 0, 0, ARMImpOpBase + 0, 2076, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2722 = VLD3DUPd16_UPD |
| 7655 | { 2721, 7, 2, 4, 635, 0, 0, ARMImpOpBase + 0, 2069, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2721 = VLD3DUPd16Pseudo_UPD |
| 7656 | { 2720, 5, 1, 4, 631, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2720 = VLD3DUPd16Pseudo |
| 7657 | { 2719, 7, 3, 4, 631, 0, 0, ARMImpOpBase + 0, 2062, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2719 = VLD3DUPd16 |
| 7658 | { 2718, 7, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2718 = VLD2q8wb_register |
| 7659 | { 2717, 6, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2717 = VLD2q8wb_fixed |
| 7660 | { 2716, 7, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1966, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2716 = VLD2q8PseudoWB_register |
| 7661 | { 2715, 6, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1960, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2715 = VLD2q8PseudoWB_fixed |
| 7662 | { 2714, 5, 1, 4, 608, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2714 = VLD2q8Pseudo |
| 7663 | { 2713, 5, 1, 4, 608, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2713 = VLD2q8 |
| 7664 | { 2712, 7, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2712 = VLD2q32wb_register |
| 7665 | { 2711, 6, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2711 = VLD2q32wb_fixed |
| 7666 | { 2710, 7, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1966, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2710 = VLD2q32PseudoWB_register |
| 7667 | { 2709, 6, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1960, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2709 = VLD2q32PseudoWB_fixed |
| 7668 | { 2708, 5, 1, 4, 608, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2708 = VLD2q32Pseudo |
| 7669 | { 2707, 5, 1, 4, 608, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2707 = VLD2q32 |
| 7670 | { 2706, 7, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2706 = VLD2q16wb_register |
| 7671 | { 2705, 6, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2705 = VLD2q16wb_fixed |
| 7672 | { 2704, 7, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1966, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2704 = VLD2q16PseudoWB_register |
| 7673 | { 2703, 6, 2, 4, 610, 0, 0, ARMImpOpBase + 0, 1960, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2703 = VLD2q16PseudoWB_fixed |
| 7674 | { 2702, 5, 1, 4, 608, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2702 = VLD2q16Pseudo |
| 7675 | { 2701, 5, 1, 4, 608, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2701 = VLD2q16 |
| 7676 | { 2700, 7, 2, 4, 1004, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2700 = VLD2d8wb_register |
| 7677 | { 2699, 6, 2, 4, 1004, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2699 = VLD2d8wb_fixed |
| 7678 | { 2698, 5, 1, 4, 1003, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2698 = VLD2d8 |
| 7679 | { 2697, 7, 2, 4, 1004, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2697 = VLD2d32wb_register |
| 7680 | { 2696, 6, 2, 4, 1004, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2696 = VLD2d32wb_fixed |
| 7681 | { 2695, 5, 1, 4, 1003, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2695 = VLD2d32 |
| 7682 | { 2694, 7, 2, 4, 1004, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2694 = VLD2d16wb_register |
| 7683 | { 2693, 6, 2, 4, 1004, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2693 = VLD2d16wb_fixed |
| 7684 | { 2692, 5, 1, 4, 1003, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2692 = VLD2d16 |
| 7685 | { 2691, 7, 2, 4, 609, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2691 = VLD2b8wb_register |
| 7686 | { 2690, 6, 2, 4, 609, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2690 = VLD2b8wb_fixed |
| 7687 | { 2689, 5, 1, 4, 607, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2689 = VLD2b8 |
| 7688 | { 2688, 7, 2, 4, 609, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2688 = VLD2b32wb_register |
| 7689 | { 2687, 6, 2, 4, 609, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2687 = VLD2b32wb_fixed |
| 7690 | { 2686, 5, 1, 4, 607, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2686 = VLD2b32 |
| 7691 | { 2685, 7, 2, 4, 609, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2685 = VLD2b16wb_register |
| 7692 | { 2684, 6, 2, 4, 609, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2684 = VLD2b16wb_fixed |
| 7693 | { 2683, 5, 1, 4, 607, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2683 = VLD2b16 |
| 7694 | { 2682, 11, 3, 4, 628, 0, 0, ARMImpOpBase + 0, 2035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2682 = VLD2LNq32_UPD |
| 7695 | { 2681, 9, 2, 4, 630, 0, 0, ARMImpOpBase + 0, 2053, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2681 = VLD2LNq32Pseudo_UPD |
| 7696 | { 2680, 7, 1, 4, 627, 0, 0, ARMImpOpBase + 0, 2046, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2680 = VLD2LNq32Pseudo |
| 7697 | { 2679, 9, 2, 4, 627, 0, 0, ARMImpOpBase + 0, 2026, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2679 = VLD2LNq32 |
| 7698 | { 2678, 11, 3, 4, 628, 0, 0, ARMImpOpBase + 0, 2035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2678 = VLD2LNq16_UPD |
| 7699 | { 2677, 9, 2, 4, 630, 0, 0, ARMImpOpBase + 0, 2053, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2677 = VLD2LNq16Pseudo_UPD |
| 7700 | { 2676, 7, 1, 4, 627, 0, 0, ARMImpOpBase + 0, 2046, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2676 = VLD2LNq16Pseudo |
| 7701 | { 2675, 9, 2, 4, 627, 0, 0, ARMImpOpBase + 0, 2026, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2675 = VLD2LNq16 |
| 7702 | { 2674, 11, 3, 4, 628, 0, 0, ARMImpOpBase + 0, 2035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2674 = VLD2LNd8_UPD |
| 7703 | { 2673, 9, 2, 4, 630, 0, 0, ARMImpOpBase + 0, 1946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2673 = VLD2LNd8Pseudo_UPD |
| 7704 | { 2672, 7, 1, 4, 627, 0, 0, ARMImpOpBase + 0, 1939, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2672 = VLD2LNd8Pseudo |
| 7705 | { 2671, 9, 2, 4, 627, 0, 0, ARMImpOpBase + 0, 2026, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2671 = VLD2LNd8 |
| 7706 | { 2670, 11, 3, 4, 628, 0, 0, ARMImpOpBase + 0, 2035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2670 = VLD2LNd32_UPD |
| 7707 | { 2669, 9, 2, 4, 630, 0, 0, ARMImpOpBase + 0, 1946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2669 = VLD2LNd32Pseudo_UPD |
| 7708 | { 2668, 7, 1, 4, 627, 0, 0, ARMImpOpBase + 0, 1939, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2668 = VLD2LNd32Pseudo |
| 7709 | { 2667, 9, 2, 4, 627, 0, 0, ARMImpOpBase + 0, 2026, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2667 = VLD2LNd32 |
| 7710 | { 2666, 11, 3, 4, 628, 0, 0, ARMImpOpBase + 0, 2035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2666 = VLD2LNd16_UPD |
| 7711 | { 2665, 9, 2, 4, 630, 0, 0, ARMImpOpBase + 0, 1946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2665 = VLD2LNd16Pseudo_UPD |
| 7712 | { 2664, 7, 1, 4, 627, 0, 0, ARMImpOpBase + 0, 1939, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2664 = VLD2LNd16Pseudo |
| 7713 | { 2663, 9, 2, 4, 627, 0, 0, ARMImpOpBase + 0, 2026, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2663 = VLD2LNd16 |
| 7714 | { 2662, 8, 2, 4, 1049, 0, 0, ARMImpOpBase + 0, 2018, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2662 = VLD2DUPq8OddPseudoWB_register |
| 7715 | { 2661, 7, 2, 4, 1049, 0, 0, ARMImpOpBase + 0, 2011, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2661 = VLD2DUPq8OddPseudoWB_fixed |
| 7716 | { 2660, 6, 1, 4, 1049, 0, 0, ARMImpOpBase + 0, 2005, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2660 = VLD2DUPq8OddPseudo |
| 7717 | { 2659, 6, 1, 4, 1049, 0, 0, ARMImpOpBase + 0, 2005, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2659 = VLD2DUPq8EvenPseudo |
| 7718 | { 2658, 8, 2, 4, 1049, 0, 0, ARMImpOpBase + 0, 2018, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2658 = VLD2DUPq32OddPseudoWB_register |
| 7719 | { 2657, 7, 2, 4, 1049, 0, 0, ARMImpOpBase + 0, 2011, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2657 = VLD2DUPq32OddPseudoWB_fixed |
| 7720 | { 2656, 6, 1, 4, 1049, 0, 0, ARMImpOpBase + 0, 2005, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2656 = VLD2DUPq32OddPseudo |
| 7721 | { 2655, 6, 1, 4, 1049, 0, 0, ARMImpOpBase + 0, 2005, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2655 = VLD2DUPq32EvenPseudo |
| 7722 | { 2654, 8, 2, 4, 1049, 0, 0, ARMImpOpBase + 0, 2018, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2654 = VLD2DUPq16OddPseudoWB_register |
| 7723 | { 2653, 7, 2, 4, 1049, 0, 0, ARMImpOpBase + 0, 2011, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2653 = VLD2DUPq16OddPseudoWB_fixed |
| 7724 | { 2652, 6, 1, 4, 1049, 0, 0, ARMImpOpBase + 0, 2005, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2652 = VLD2DUPq16OddPseudo |
| 7725 | { 2651, 6, 1, 4, 1049, 0, 0, ARMImpOpBase + 0, 2005, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2651 = VLD2DUPq16EvenPseudo |
| 7726 | { 2650, 7, 2, 4, 629, 0, 0, ARMImpOpBase + 0, 1998, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2650 = VLD2DUPd8x2wb_register |
| 7727 | { 2649, 6, 2, 4, 629, 0, 0, ARMImpOpBase + 0, 1992, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2649 = VLD2DUPd8x2wb_fixed |
| 7728 | { 2648, 5, 1, 4, 626, 0, 0, ARMImpOpBase + 0, 1987, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2648 = VLD2DUPd8x2 |
| 7729 | { 2647, 7, 2, 4, 629, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2647 = VLD2DUPd8wb_register |
| 7730 | { 2646, 6, 2, 4, 629, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2646 = VLD2DUPd8wb_fixed |
| 7731 | { 2645, 5, 1, 4, 626, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2645 = VLD2DUPd8 |
| 7732 | { 2644, 7, 2, 4, 629, 0, 0, ARMImpOpBase + 0, 1998, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2644 = VLD2DUPd32x2wb_register |
| 7733 | { 2643, 6, 2, 4, 629, 0, 0, ARMImpOpBase + 0, 1992, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2643 = VLD2DUPd32x2wb_fixed |
| 7734 | { 2642, 5, 1, 4, 626, 0, 0, ARMImpOpBase + 0, 1987, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2642 = VLD2DUPd32x2 |
| 7735 | { 2641, 7, 2, 4, 629, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2641 = VLD2DUPd32wb_register |
| 7736 | { 2640, 6, 2, 4, 629, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2640 = VLD2DUPd32wb_fixed |
| 7737 | { 2639, 5, 1, 4, 626, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2639 = VLD2DUPd32 |
| 7738 | { 2638, 7, 2, 4, 629, 0, 0, ARMImpOpBase + 0, 1998, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2638 = VLD2DUPd16x2wb_register |
| 7739 | { 2637, 6, 2, 4, 629, 0, 0, ARMImpOpBase + 0, 1992, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2637 = VLD2DUPd16x2wb_fixed |
| 7740 | { 2636, 5, 1, 4, 626, 0, 0, ARMImpOpBase + 0, 1987, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2636 = VLD2DUPd16x2 |
| 7741 | { 2635, 7, 2, 4, 629, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2635 = VLD2DUPd16wb_register |
| 7742 | { 2634, 6, 2, 4, 629, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2634 = VLD2DUPd16wb_fixed |
| 7743 | { 2633, 5, 1, 4, 626, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2633 = VLD2DUPd16 |
| 7744 | { 2632, 7, 2, 4, 602, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2632 = VLD1q8wb_register |
| 7745 | { 2631, 6, 2, 4, 602, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2631 = VLD1q8wb_fixed |
| 7746 | { 2630, 8, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2630 = VLD1q8LowTPseudo_UPD |
| 7747 | { 2629, 8, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2629 = VLD1q8LowQPseudo_UPD |
| 7748 | { 2628, 8, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2628 = VLD1q8HighTPseudo_UPD |
| 7749 | { 2627, 6, 1, 4, 1048, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2627 = VLD1q8HighTPseudo |
| 7750 | { 2626, 8, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2626 = VLD1q8HighQPseudo_UPD |
| 7751 | { 2625, 6, 1, 4, 1047, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2625 = VLD1q8HighQPseudo |
| 7752 | { 2624, 5, 1, 4, 600, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2624 = VLD1q8 |
| 7753 | { 2623, 7, 2, 4, 602, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2623 = VLD1q64wb_register |
| 7754 | { 2622, 6, 2, 4, 602, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2622 = VLD1q64wb_fixed |
| 7755 | { 2621, 8, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2621 = VLD1q64LowTPseudo_UPD |
| 7756 | { 2620, 8, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2620 = VLD1q64LowQPseudo_UPD |
| 7757 | { 2619, 8, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2619 = VLD1q64HighTPseudo_UPD |
| 7758 | { 2618, 6, 1, 4, 1048, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2618 = VLD1q64HighTPseudo |
| 7759 | { 2617, 8, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2617 = VLD1q64HighQPseudo_UPD |
| 7760 | { 2616, 6, 1, 4, 1047, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2616 = VLD1q64HighQPseudo |
| 7761 | { 2615, 5, 1, 4, 600, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2615 = VLD1q64 |
| 7762 | { 2614, 7, 2, 4, 602, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2614 = VLD1q32wb_register |
| 7763 | { 2613, 6, 2, 4, 602, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2613 = VLD1q32wb_fixed |
| 7764 | { 2612, 8, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2612 = VLD1q32LowTPseudo_UPD |
| 7765 | { 2611, 8, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2611 = VLD1q32LowQPseudo_UPD |
| 7766 | { 2610, 8, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2610 = VLD1q32HighTPseudo_UPD |
| 7767 | { 2609, 6, 1, 4, 1048, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2609 = VLD1q32HighTPseudo |
| 7768 | { 2608, 8, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2608 = VLD1q32HighQPseudo_UPD |
| 7769 | { 2607, 6, 1, 4, 1047, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2607 = VLD1q32HighQPseudo |
| 7770 | { 2606, 5, 1, 4, 600, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2606 = VLD1q32 |
| 7771 | { 2605, 7, 2, 4, 602, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2605 = VLD1q16wb_register |
| 7772 | { 2604, 6, 2, 4, 602, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2604 = VLD1q16wb_fixed |
| 7773 | { 2603, 8, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2603 = VLD1q16LowTPseudo_UPD |
| 7774 | { 2602, 8, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2602 = VLD1q16LowQPseudo_UPD |
| 7775 | { 2601, 8, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2601 = VLD1q16HighTPseudo_UPD |
| 7776 | { 2600, 6, 1, 4, 1048, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2600 = VLD1q16HighTPseudo |
| 7777 | { 2599, 8, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2599 = VLD1q16HighQPseudo_UPD |
| 7778 | { 2598, 6, 1, 4, 1047, 0, 0, ARMImpOpBase + 0, 1973, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2598 = VLD1q16HighQPseudo |
| 7779 | { 2597, 5, 1, 4, 600, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2597 = VLD1q16 |
| 7780 | { 2596, 7, 2, 4, 601, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2596 = VLD1d8wb_register |
| 7781 | { 2595, 6, 2, 4, 601, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2595 = VLD1d8wb_fixed |
| 7782 | { 2594, 7, 2, 4, 604, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2594 = VLD1d8Twb_register |
| 7783 | { 2593, 6, 2, 4, 604, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2593 = VLD1d8Twb_fixed |
| 7784 | { 2592, 7, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1966, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2592 = VLD1d8TPseudoWB_register |
| 7785 | { 2591, 6, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1960, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2591 = VLD1d8TPseudoWB_fixed |
| 7786 | { 2590, 5, 1, 4, 1048, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2590 = VLD1d8TPseudo |
| 7787 | { 2589, 5, 1, 4, 603, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2589 = VLD1d8T |
| 7788 | { 2588, 7, 2, 4, 606, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2588 = VLD1d8Qwb_register |
| 7789 | { 2587, 6, 2, 4, 606, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2587 = VLD1d8Qwb_fixed |
| 7790 | { 2586, 7, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1966, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2586 = VLD1d8QPseudoWB_register |
| 7791 | { 2585, 6, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1960, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2585 = VLD1d8QPseudoWB_fixed |
| 7792 | { 2584, 5, 1, 4, 1047, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2584 = VLD1d8QPseudo |
| 7793 | { 2583, 5, 1, 4, 605, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2583 = VLD1d8Q |
| 7794 | { 2582, 5, 1, 4, 599, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2582 = VLD1d8 |
| 7795 | { 2581, 7, 2, 4, 601, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2581 = VLD1d64wb_register |
| 7796 | { 2580, 6, 2, 4, 601, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2580 = VLD1d64wb_fixed |
| 7797 | { 2579, 7, 2, 4, 604, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2579 = VLD1d64Twb_register |
| 7798 | { 2578, 6, 2, 4, 604, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2578 = VLD1d64Twb_fixed |
| 7799 | { 2577, 7, 2, 4, 603, 0, 0, ARMImpOpBase + 0, 1966, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2577 = VLD1d64TPseudoWB_register |
| 7800 | { 2576, 6, 2, 4, 603, 0, 0, ARMImpOpBase + 0, 1960, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2576 = VLD1d64TPseudoWB_fixed |
| 7801 | { 2575, 5, 1, 4, 603, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2575 = VLD1d64TPseudo |
| 7802 | { 2574, 5, 1, 4, 603, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2574 = VLD1d64T |
| 7803 | { 2573, 7, 2, 4, 606, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2573 = VLD1d64Qwb_register |
| 7804 | { 2572, 6, 2, 4, 606, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2572 = VLD1d64Qwb_fixed |
| 7805 | { 2571, 7, 2, 4, 605, 0, 0, ARMImpOpBase + 0, 1966, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2571 = VLD1d64QPseudoWB_register |
| 7806 | { 2570, 6, 2, 4, 605, 0, 0, ARMImpOpBase + 0, 1960, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2570 = VLD1d64QPseudoWB_fixed |
| 7807 | { 2569, 5, 1, 4, 605, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2569 = VLD1d64QPseudo |
| 7808 | { 2568, 5, 1, 4, 605, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2568 = VLD1d64Q |
| 7809 | { 2567, 5, 1, 4, 599, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2567 = VLD1d64 |
| 7810 | { 2566, 7, 2, 4, 601, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2566 = VLD1d32wb_register |
| 7811 | { 2565, 6, 2, 4, 601, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2565 = VLD1d32wb_fixed |
| 7812 | { 2564, 7, 2, 4, 604, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2564 = VLD1d32Twb_register |
| 7813 | { 2563, 6, 2, 4, 604, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2563 = VLD1d32Twb_fixed |
| 7814 | { 2562, 7, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1966, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2562 = VLD1d32TPseudoWB_register |
| 7815 | { 2561, 6, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1960, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2561 = VLD1d32TPseudoWB_fixed |
| 7816 | { 2560, 5, 1, 4, 1048, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2560 = VLD1d32TPseudo |
| 7817 | { 2559, 5, 1, 4, 603, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2559 = VLD1d32T |
| 7818 | { 2558, 7, 2, 4, 606, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2558 = VLD1d32Qwb_register |
| 7819 | { 2557, 6, 2, 4, 606, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2557 = VLD1d32Qwb_fixed |
| 7820 | { 2556, 7, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1966, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2556 = VLD1d32QPseudoWB_register |
| 7821 | { 2555, 6, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1960, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2555 = VLD1d32QPseudoWB_fixed |
| 7822 | { 2554, 5, 1, 4, 1047, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2554 = VLD1d32QPseudo |
| 7823 | { 2553, 5, 1, 4, 605, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2553 = VLD1d32Q |
| 7824 | { 2552, 5, 1, 4, 599, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2552 = VLD1d32 |
| 7825 | { 2551, 7, 2, 4, 601, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2551 = VLD1d16wb_register |
| 7826 | { 2550, 6, 2, 4, 601, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2550 = VLD1d16wb_fixed |
| 7827 | { 2549, 7, 2, 4, 604, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2549 = VLD1d16Twb_register |
| 7828 | { 2548, 6, 2, 4, 604, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2548 = VLD1d16Twb_fixed |
| 7829 | { 2547, 7, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1966, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2547 = VLD1d16TPseudoWB_register |
| 7830 | { 2546, 6, 2, 4, 1048, 0, 0, ARMImpOpBase + 0, 1960, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2546 = VLD1d16TPseudoWB_fixed |
| 7831 | { 2545, 5, 1, 4, 1048, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2545 = VLD1d16TPseudo |
| 7832 | { 2544, 5, 1, 4, 603, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2544 = VLD1d16T |
| 7833 | { 2543, 7, 2, 4, 606, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2543 = VLD1d16Qwb_register |
| 7834 | { 2542, 6, 2, 4, 606, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2542 = VLD1d16Qwb_fixed |
| 7835 | { 2541, 7, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1966, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2541 = VLD1d16QPseudoWB_register |
| 7836 | { 2540, 6, 2, 4, 1047, 0, 0, ARMImpOpBase + 0, 1960, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2540 = VLD1d16QPseudoWB_fixed |
| 7837 | { 2539, 5, 1, 4, 1047, 0, 0, ARMImpOpBase + 0, 1955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2539 = VLD1d16QPseudo |
| 7838 | { 2538, 5, 1, 4, 605, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2538 = VLD1d16Q |
| 7839 | { 2537, 5, 1, 4, 599, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2537 = VLD1d16 |
| 7840 | { 2536, 9, 2, 4, 625, 0, 0, ARMImpOpBase + 0, 1946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2536 = VLD1LNq8Pseudo_UPD |
| 7841 | { 2535, 7, 1, 4, 622, 0, 0, ARMImpOpBase + 0, 1939, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #2535 = VLD1LNq8Pseudo |
| 7842 | { 2534, 9, 2, 4, 625, 0, 0, ARMImpOpBase + 0, 1946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2534 = VLD1LNq32Pseudo_UPD |
| 7843 | { 2533, 7, 1, 4, 622, 0, 0, ARMImpOpBase + 0, 1939, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #2533 = VLD1LNq32Pseudo |
| 7844 | { 2532, 9, 2, 4, 625, 0, 0, ARMImpOpBase + 0, 1946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2532 = VLD1LNq16Pseudo_UPD |
| 7845 | { 2531, 7, 1, 4, 622, 0, 0, ARMImpOpBase + 0, 1939, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #2531 = VLD1LNq16Pseudo |
| 7846 | { 2530, 9, 2, 4, 625, 0, 0, ARMImpOpBase + 0, 1930, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2530 = VLD1LNd8_UPD |
| 7847 | { 2529, 7, 1, 4, 621, 0, 0, ARMImpOpBase + 0, 1923, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2529 = VLD1LNd8 |
| 7848 | { 2528, 9, 2, 4, 625, 0, 0, ARMImpOpBase + 0, 1930, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2528 = VLD1LNd32_UPD |
| 7849 | { 2527, 7, 1, 4, 622, 0, 0, ARMImpOpBase + 0, 1923, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2527 = VLD1LNd32 |
| 7850 | { 2526, 9, 2, 4, 625, 0, 0, ARMImpOpBase + 0, 1930, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2526 = VLD1LNd16_UPD |
| 7851 | { 2525, 7, 1, 4, 621, 0, 0, ARMImpOpBase + 0, 1923, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2525 = VLD1LNd16 |
| 7852 | { 2524, 7, 2, 4, 623, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2524 = VLD1DUPq8wb_register |
| 7853 | { 2523, 6, 2, 4, 624, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2523 = VLD1DUPq8wb_fixed |
| 7854 | { 2522, 5, 1, 4, 620, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2522 = VLD1DUPq8 |
| 7855 | { 2521, 7, 2, 4, 623, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2521 = VLD1DUPq32wb_register |
| 7856 | { 2520, 6, 2, 4, 624, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2520 = VLD1DUPq32wb_fixed |
| 7857 | { 2519, 5, 1, 4, 620, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2519 = VLD1DUPq32 |
| 7858 | { 2518, 7, 2, 4, 623, 0, 0, ARMImpOpBase + 0, 1916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2518 = VLD1DUPq16wb_register |
| 7859 | { 2517, 6, 2, 4, 624, 0, 0, ARMImpOpBase + 0, 1910, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2517 = VLD1DUPq16wb_fixed |
| 7860 | { 2516, 5, 1, 4, 620, 0, 0, ARMImpOpBase + 0, 1905, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2516 = VLD1DUPq16 |
| 7861 | { 2515, 7, 2, 4, 623, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2515 = VLD1DUPd8wb_register |
| 7862 | { 2514, 6, 2, 4, 623, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2514 = VLD1DUPd8wb_fixed |
| 7863 | { 2513, 5, 1, 4, 619, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2513 = VLD1DUPd8 |
| 7864 | { 2512, 7, 2, 4, 623, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2512 = VLD1DUPd32wb_register |
| 7865 | { 2511, 6, 2, 4, 623, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2511 = VLD1DUPd32wb_fixed |
| 7866 | { 2510, 5, 1, 4, 619, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2510 = VLD1DUPd32 |
| 7867 | { 2509, 7, 2, 4, 623, 0, 0, ARMImpOpBase + 0, 1898, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2509 = VLD1DUPd16wb_register |
| 7868 | { 2508, 6, 2, 4, 623, 0, 0, ARMImpOpBase + 0, 1892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2508 = VLD1DUPd16wb_fixed |
| 7869 | { 2507, 5, 1, 4, 619, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2507 = VLD1DUPd16 |
| 7870 | { 2506, 4, 1, 4, 960, 0, 0, ARMImpOpBase + 0, 1809, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #2506 = VJCVT |
| 7871 | { 2505, 3, 1, 4, 969, 0, 0, ARMImpOpBase + 0, 1889, 0, 0x8780ULL }, // Inst #2505 = VINSH |
| 7872 | { 2504, 5, 1, 4, 470, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2504 = VHSUBuv8i8 |
| 7873 | { 2503, 5, 1, 4, 469, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2503 = VHSUBuv8i16 |
| 7874 | { 2502, 5, 1, 4, 469, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2502 = VHSUBuv4i32 |
| 7875 | { 2501, 5, 1, 4, 470, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2501 = VHSUBuv4i16 |
| 7876 | { 2500, 5, 1, 4, 470, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2500 = VHSUBuv2i32 |
| 7877 | { 2499, 5, 1, 4, 469, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2499 = VHSUBuv16i8 |
| 7878 | { 2498, 5, 1, 4, 470, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2498 = VHSUBsv8i8 |
| 7879 | { 2497, 5, 1, 4, 469, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2497 = VHSUBsv8i16 |
| 7880 | { 2496, 5, 1, 4, 469, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2496 = VHSUBsv4i32 |
| 7881 | { 2495, 5, 1, 4, 470, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2495 = VHSUBsv4i16 |
| 7882 | { 2494, 5, 1, 4, 470, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2494 = VHSUBsv2i32 |
| 7883 | { 2493, 5, 1, 4, 469, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2493 = VHSUBsv16i8 |
| 7884 | { 2492, 5, 1, 4, 775, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2492 = VHADDuv8i8 |
| 7885 | { 2491, 5, 1, 4, 776, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2491 = VHADDuv8i16 |
| 7886 | { 2490, 5, 1, 4, 776, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2490 = VHADDuv4i32 |
| 7887 | { 2489, 5, 1, 4, 775, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2489 = VHADDuv4i16 |
| 7888 | { 2488, 5, 1, 4, 775, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2488 = VHADDuv2i32 |
| 7889 | { 2487, 5, 1, 4, 776, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2487 = VHADDuv16i8 |
| 7890 | { 2486, 5, 1, 4, 775, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2486 = VHADDsv8i8 |
| 7891 | { 2485, 5, 1, 4, 776, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2485 = VHADDsv8i16 |
| 7892 | { 2484, 5, 1, 4, 776, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2484 = VHADDsv4i32 |
| 7893 | { 2483, 5, 1, 4, 775, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2483 = VHADDsv4i16 |
| 7894 | { 2482, 5, 1, 4, 775, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2482 = VHADDsv2i32 |
| 7895 | { 2481, 5, 1, 4, 776, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2481 = VHADDsv16i8 |
| 7896 | { 2480, 5, 1, 4, 584, 0, 0, ARMImpOpBase + 0, 1884, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // Inst #2480 = VGETLNu8 |
| 7897 | { 2479, 5, 1, 4, 584, 0, 0, ARMImpOpBase + 0, 1884, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // Inst #2479 = VGETLNu16 |
| 7898 | { 2478, 5, 1, 4, 585, 0, 0, ARMImpOpBase + 0, 1884, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // Inst #2478 = VGETLNs8 |
| 7899 | { 2477, 5, 1, 4, 585, 0, 0, ARMImpOpBase + 0, 1884, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // Inst #2477 = VGETLNs16 |
| 7900 | { 2476, 5, 1, 4, 1045, 0, 0, ARMImpOpBase + 0, 1884, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // Inst #2476 = VGETLNi32 |
| 7901 | { 2475, 3, 1, 4, 1251, 0, 0, ARMImpOpBase + 0, 1881, 0, 0x8800ULL }, // Inst #2475 = VFP_VMINNMS |
| 7902 | { 2474, 3, 1, 4, 1211, 0, 0, ARMImpOpBase + 0, 1878, 0, 0x8800ULL }, // Inst #2474 = VFP_VMINNMH |
| 7903 | { 2473, 3, 1, 4, 1255, 0, 0, ARMImpOpBase + 0, 1501, 0, 0x8800ULL }, // Inst #2473 = VFP_VMINNMD |
| 7904 | { 2472, 3, 1, 4, 1251, 0, 0, ARMImpOpBase + 0, 1881, 0, 0x8800ULL }, // Inst #2472 = VFP_VMAXNMS |
| 7905 | { 2471, 3, 1, 4, 1211, 0, 0, ARMImpOpBase + 0, 1878, 0, 0x8800ULL }, // Inst #2471 = VFP_VMAXNMH |
| 7906 | { 2470, 3, 1, 4, 1255, 0, 0, ARMImpOpBase + 0, 1501, 0, 0x8800ULL }, // Inst #2470 = VFP_VMAXNMD |
| 7907 | { 2469, 6, 1, 4, 550, 0, 0, ARMImpOpBase + 0, 1872, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2469 = VFNMSS |
| 7908 | { 2468, 6, 1, 4, 551, 0, 0, ARMImpOpBase + 0, 1852, 0, 0x8800ULL }, // Inst #2468 = VFNMSH |
| 7909 | { 2467, 6, 1, 4, 549, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2467 = VFNMSD |
| 7910 | { 2466, 6, 1, 4, 550, 0, 0, ARMImpOpBase + 0, 1872, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2466 = VFNMAS |
| 7911 | { 2465, 6, 1, 4, 551, 0, 0, ARMImpOpBase + 0, 1852, 0, 0x8800ULL }, // Inst #2465 = VFNMAH |
| 7912 | { 2464, 6, 1, 4, 549, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2464 = VFNMAD |
| 7913 | { 2463, 6, 1, 4, 774, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2463 = VFMShq |
| 7914 | { 2462, 6, 1, 4, 773, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2462 = VFMShd |
| 7915 | { 2461, 6, 1, 4, 553, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2461 = VFMSfq |
| 7916 | { 2460, 6, 1, 4, 552, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2460 = VFMSfd |
| 7917 | { 2459, 6, 1, 4, 550, 0, 0, ARMImpOpBase + 0, 1872, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2459 = VFMSS |
| 7918 | { 2458, 4, 1, 4, 116, 0, 0, ARMImpOpBase + 0, 1868, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2458 = VFMSLQI |
| 7919 | { 2457, 3, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 1865, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2457 = VFMSLQ |
| 7920 | { 2456, 4, 1, 4, 116, 0, 0, ARMImpOpBase + 0, 1861, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2456 = VFMSLDI |
| 7921 | { 2455, 3, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 1858, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2455 = VFMSLD |
| 7922 | { 2454, 6, 1, 4, 1210, 0, 0, ARMImpOpBase + 0, 1852, 0, 0x8800ULL }, // Inst #2454 = VFMSH |
| 7923 | { 2453, 6, 1, 4, 549, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2453 = VFMSD |
| 7924 | { 2452, 6, 1, 4, 774, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2452 = VFMAhq |
| 7925 | { 2451, 6, 1, 4, 773, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2451 = VFMAhd |
| 7926 | { 2450, 6, 1, 4, 553, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2450 = VFMAfq |
| 7927 | { 2449, 6, 1, 4, 552, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2449 = VFMAfd |
| 7928 | { 2448, 6, 1, 4, 550, 0, 0, ARMImpOpBase + 0, 1872, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2448 = VFMAS |
| 7929 | { 2447, 4, 1, 4, 116, 0, 0, ARMImpOpBase + 0, 1868, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2447 = VFMALQI |
| 7930 | { 2446, 3, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 1865, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2446 = VFMALQ |
| 7931 | { 2445, 4, 1, 4, 116, 0, 0, ARMImpOpBase + 0, 1861, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2445 = VFMALDI |
| 7932 | { 2444, 3, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 1858, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2444 = VFMALD |
| 7933 | { 2443, 6, 1, 4, 1210, 0, 0, ARMImpOpBase + 0, 1852, 0, 0x8800ULL }, // Inst #2443 = VFMAH |
| 7934 | { 2442, 6, 1, 4, 549, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2442 = VFMAD |
| 7935 | { 2441, 6, 1, 4, 477, 0, 0, ARMImpOpBase + 0, 1846, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2441 = VEXTq8 |
| 7936 | { 2440, 6, 1, 4, 477, 0, 0, ARMImpOpBase + 0, 1846, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2440 = VEXTq64 |
| 7937 | { 2439, 6, 1, 4, 477, 0, 0, ARMImpOpBase + 0, 1846, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2439 = VEXTq32 |
| 7938 | { 2438, 6, 1, 4, 477, 0, 0, ARMImpOpBase + 0, 1846, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2438 = VEXTq16 |
| 7939 | { 2437, 6, 1, 4, 476, 0, 0, ARMImpOpBase + 0, 1840, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2437 = VEXTd8 |
| 7940 | { 2436, 6, 1, 4, 476, 0, 0, ARMImpOpBase + 0, 1840, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2436 = VEXTd32 |
| 7941 | { 2435, 6, 1, 4, 476, 0, 0, ARMImpOpBase + 0, 1840, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2435 = VEXTd16 |
| 7942 | { 2434, 5, 1, 4, 761, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2434 = VEORq |
| 7943 | { 2433, 5, 1, 4, 760, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2433 = VEORd |
| 7944 | { 2432, 5, 1, 4, 576, 0, 0, ARMImpOpBase + 0, 1835, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // Inst #2432 = VDUPLN8q |
| 7945 | { 2431, 5, 1, 4, 575, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // Inst #2431 = VDUPLN8d |
| 7946 | { 2430, 5, 1, 4, 576, 0, 0, ARMImpOpBase + 0, 1835, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // Inst #2430 = VDUPLN32q |
| 7947 | { 2429, 5, 1, 4, 575, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // Inst #2429 = VDUPLN32d |
| 7948 | { 2428, 5, 1, 4, 576, 0, 0, ARMImpOpBase + 0, 1835, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // Inst #2428 = VDUPLN16q |
| 7949 | { 2427, 5, 1, 4, 575, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // Inst #2427 = VDUPLN16d |
| 7950 | { 2426, 4, 1, 4, 577, 0, 0, ARMImpOpBase + 0, 1831, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // Inst #2426 = VDUP8q |
| 7951 | { 2425, 4, 1, 4, 771, 0, 0, ARMImpOpBase + 0, 1827, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // Inst #2425 = VDUP8d |
| 7952 | { 2424, 4, 1, 4, 577, 0, 0, ARMImpOpBase + 0, 1831, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // Inst #2424 = VDUP32q |
| 7953 | { 2423, 4, 1, 4, 771, 0, 0, ARMImpOpBase + 0, 1827, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // Inst #2423 = VDUP32d |
| 7954 | { 2422, 4, 1, 4, 577, 0, 0, ARMImpOpBase + 0, 1831, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // Inst #2422 = VDUP16q |
| 7955 | { 2421, 4, 1, 4, 771, 0, 0, ARMImpOpBase + 0, 1827, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // Inst #2421 = VDUP16d |
| 7956 | { 2420, 5, 1, 4, 676, 0, 0, ARMImpOpBase + 0, 1704, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2420 = VDIVS |
| 7957 | { 2419, 5, 1, 4, 1209, 0, 0, ARMImpOpBase + 0, 1694, 0, 0x8800ULL }, // Inst #2419 = VDIVH |
| 7958 | { 2418, 5, 1, 4, 678, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2418 = VDIVD |
| 7959 | { 2417, 5, 1, 4, 560, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2417 = VCVTxu2hq |
| 7960 | { 2416, 5, 1, 4, 561, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2416 = VCVTxu2hd |
| 7961 | { 2415, 5, 1, 4, 996, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2415 = VCVTxu2fq |
| 7962 | { 2414, 5, 1, 4, 995, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2414 = VCVTxu2fd |
| 7963 | { 2413, 5, 1, 4, 560, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2413 = VCVTxs2hq |
| 7964 | { 2412, 5, 1, 4, 561, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2412 = VCVTxs2hd |
| 7965 | { 2411, 5, 1, 4, 996, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2411 = VCVTxs2fq |
| 7966 | { 2410, 5, 1, 4, 995, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2410 = VCVTxs2fd |
| 7967 | { 2409, 4, 1, 4, 560, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2409 = VCVTu2hq |
| 7968 | { 2408, 4, 1, 4, 561, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2408 = VCVTu2hd |
| 7969 | { 2407, 4, 1, 4, 996, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2407 = VCVTu2fq |
| 7970 | { 2406, 4, 1, 4, 995, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2406 = VCVTu2fd |
| 7971 | { 2405, 4, 1, 4, 560, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2405 = VCVTs2hq |
| 7972 | { 2404, 4, 1, 4, 561, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2404 = VCVTs2hd |
| 7973 | { 2403, 4, 1, 4, 996, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2403 = VCVTs2fq |
| 7974 | { 2402, 4, 1, 4, 995, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2402 = VCVTs2fd |
| 7975 | { 2401, 5, 1, 4, 560, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2401 = VCVTh2xuq |
| 7976 | { 2400, 5, 1, 4, 561, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2400 = VCVTh2xud |
| 7977 | { 2399, 5, 1, 4, 560, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2399 = VCVTh2xsq |
| 7978 | { 2398, 5, 1, 4, 561, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2398 = VCVTh2xsd |
| 7979 | { 2397, 4, 1, 4, 560, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2397 = VCVTh2uq |
| 7980 | { 2396, 4, 1, 4, 561, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2396 = VCVTh2ud |
| 7981 | { 2395, 4, 1, 4, 560, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2395 = VCVTh2sq |
| 7982 | { 2394, 4, 1, 4, 561, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2394 = VCVTh2sd |
| 7983 | { 2393, 4, 1, 4, 560, 0, 0, ARMImpOpBase + 0, 1823, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2393 = VCVTh2f |
| 7984 | { 2392, 5, 1, 4, 996, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2392 = VCVTf2xuq |
| 7985 | { 2391, 5, 1, 4, 995, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2391 = VCVTf2xud |
| 7986 | { 2390, 5, 1, 4, 996, 0, 0, ARMImpOpBase + 0, 1818, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2390 = VCVTf2xsq |
| 7987 | { 2389, 5, 1, 4, 995, 0, 0, ARMImpOpBase + 0, 1813, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2389 = VCVTf2xsd |
| 7988 | { 2388, 4, 1, 4, 996, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2388 = VCVTf2uq |
| 7989 | { 2387, 4, 1, 4, 995, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2387 = VCVTf2ud |
| 7990 | { 2386, 4, 1, 4, 996, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2386 = VCVTf2sq |
| 7991 | { 2385, 4, 1, 4, 995, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2385 = VCVTf2sd |
| 7992 | { 2384, 4, 1, 4, 560, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2384 = VCVTf2h |
| 7993 | { 2383, 5, 1, 4, 557, 0, 0, ARMImpOpBase + 0, 411, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2383 = VCVTTSH |
| 7994 | { 2382, 4, 1, 4, 556, 0, 0, ARMImpOpBase + 0, 1686, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2382 = VCVTTHS |
| 7995 | { 2381, 4, 1, 4, 1254, 0, 0, ARMImpOpBase + 0, 1805, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2381 = VCVTTHD |
| 7996 | { 2380, 5, 1, 4, 958, 0, 0, ARMImpOpBase + 0, 1800, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2380 = VCVTTDH |
| 7997 | { 2379, 4, 1, 4, 559, 0, 0, ARMImpOpBase + 0, 1809, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2379 = VCVTSD |
| 7998 | { 2378, 2, 1, 4, 1250, 0, 0, ARMImpOpBase + 0, 1798, 0, 0x8780ULL }, // Inst #2378 = VCVTPUS |
| 7999 | { 2377, 2, 1, 4, 1208, 0, 0, ARMImpOpBase + 0, 1796, 0, 0x8780ULL }, // Inst #2377 = VCVTPUH |
| 8000 | { 2376, 2, 1, 4, 1253, 0, 0, ARMImpOpBase + 0, 1794, 0, 0x8780ULL }, // Inst #2376 = VCVTPUD |
| 8001 | { 2375, 2, 1, 4, 1250, 0, 0, ARMImpOpBase + 0, 1798, 0, 0x8780ULL }, // Inst #2375 = VCVTPSS |
| 8002 | { 2374, 2, 1, 4, 1208, 0, 0, ARMImpOpBase + 0, 1796, 0, 0x8780ULL }, // Inst #2374 = VCVTPSH |
| 8003 | { 2373, 2, 1, 4, 1253, 0, 0, ARMImpOpBase + 0, 1794, 0, 0x8780ULL }, // Inst #2373 = VCVTPSD |
| 8004 | { 2372, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2372 = VCVTPNUQh |
| 8005 | { 2371, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2371 = VCVTPNUQf |
| 8006 | { 2370, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2370 = VCVTPNUDh |
| 8007 | { 2369, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2369 = VCVTPNUDf |
| 8008 | { 2368, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2368 = VCVTPNSQh |
| 8009 | { 2367, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2367 = VCVTPNSQf |
| 8010 | { 2366, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2366 = VCVTPNSDh |
| 8011 | { 2365, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2365 = VCVTPNSDf |
| 8012 | { 2364, 2, 1, 4, 1250, 0, 0, ARMImpOpBase + 0, 1798, 0, 0x8780ULL }, // Inst #2364 = VCVTNUS |
| 8013 | { 2363, 2, 1, 4, 1208, 0, 0, ARMImpOpBase + 0, 1796, 0, 0x8780ULL }, // Inst #2363 = VCVTNUH |
| 8014 | { 2362, 2, 1, 4, 1253, 0, 0, ARMImpOpBase + 0, 1794, 0, 0x8780ULL }, // Inst #2362 = VCVTNUD |
| 8015 | { 2361, 2, 1, 4, 1250, 0, 0, ARMImpOpBase + 0, 1798, 0, 0x8780ULL }, // Inst #2361 = VCVTNSS |
| 8016 | { 2360, 2, 1, 4, 1208, 0, 0, ARMImpOpBase + 0, 1796, 0, 0x8780ULL }, // Inst #2360 = VCVTNSH |
| 8017 | { 2359, 2, 1, 4, 1253, 0, 0, ARMImpOpBase + 0, 1794, 0, 0x8780ULL }, // Inst #2359 = VCVTNSD |
| 8018 | { 2358, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2358 = VCVTNNUQh |
| 8019 | { 2357, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2357 = VCVTNNUQf |
| 8020 | { 2356, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2356 = VCVTNNUDh |
| 8021 | { 2355, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2355 = VCVTNNUDf |
| 8022 | { 2354, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2354 = VCVTNNSQh |
| 8023 | { 2353, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2353 = VCVTNNSQf |
| 8024 | { 2352, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2352 = VCVTNNSDh |
| 8025 | { 2351, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2351 = VCVTNNSDf |
| 8026 | { 2350, 2, 1, 4, 1250, 0, 0, ARMImpOpBase + 0, 1798, 0, 0x8780ULL }, // Inst #2350 = VCVTMUS |
| 8027 | { 2349, 2, 1, 4, 1208, 0, 0, ARMImpOpBase + 0, 1796, 0, 0x8780ULL }, // Inst #2349 = VCVTMUH |
| 8028 | { 2348, 2, 1, 4, 1253, 0, 0, ARMImpOpBase + 0, 1794, 0, 0x8780ULL }, // Inst #2348 = VCVTMUD |
| 8029 | { 2347, 2, 1, 4, 1250, 0, 0, ARMImpOpBase + 0, 1798, 0, 0x8780ULL }, // Inst #2347 = VCVTMSS |
| 8030 | { 2346, 2, 1, 4, 1208, 0, 0, ARMImpOpBase + 0, 1796, 0, 0x8780ULL }, // Inst #2346 = VCVTMSH |
| 8031 | { 2345, 2, 1, 4, 1253, 0, 0, ARMImpOpBase + 0, 1794, 0, 0x8780ULL }, // Inst #2345 = VCVTMSD |
| 8032 | { 2344, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2344 = VCVTMNUQh |
| 8033 | { 2343, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2343 = VCVTMNUQf |
| 8034 | { 2342, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2342 = VCVTMNUDh |
| 8035 | { 2341, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2341 = VCVTMNUDf |
| 8036 | { 2340, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2340 = VCVTMNSQh |
| 8037 | { 2339, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2339 = VCVTMNSQf |
| 8038 | { 2338, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2338 = VCVTMNSDh |
| 8039 | { 2337, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2337 = VCVTMNSDf |
| 8040 | { 2336, 4, 1, 4, 558, 0, 0, ARMImpOpBase + 0, 1805, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2336 = VCVTDS |
| 8041 | { 2335, 5, 1, 4, 557, 0, 0, ARMImpOpBase + 0, 411, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2335 = VCVTBSH |
| 8042 | { 2334, 4, 1, 4, 556, 0, 0, ARMImpOpBase + 0, 1686, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2334 = VCVTBHS |
| 8043 | { 2333, 4, 1, 4, 555, 0, 0, ARMImpOpBase + 0, 1805, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2333 = VCVTBHD |
| 8044 | { 2332, 5, 1, 4, 958, 0, 0, ARMImpOpBase + 0, 1800, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2332 = VCVTBDH |
| 8045 | { 2331, 2, 1, 4, 1250, 0, 0, ARMImpOpBase + 0, 1798, 0, 0x8780ULL }, // Inst #2331 = VCVTAUS |
| 8046 | { 2330, 2, 1, 4, 1208, 0, 0, ARMImpOpBase + 0, 1796, 0, 0x8780ULL }, // Inst #2330 = VCVTAUH |
| 8047 | { 2329, 2, 1, 4, 1253, 0, 0, ARMImpOpBase + 0, 1794, 0, 0x8780ULL }, // Inst #2329 = VCVTAUD |
| 8048 | { 2328, 2, 1, 4, 1250, 0, 0, ARMImpOpBase + 0, 1798, 0, 0x8780ULL }, // Inst #2328 = VCVTASS |
| 8049 | { 2327, 2, 1, 4, 1208, 0, 0, ARMImpOpBase + 0, 1796, 0, 0x8780ULL }, // Inst #2327 = VCVTASH |
| 8050 | { 2326, 2, 1, 4, 1253, 0, 0, ARMImpOpBase + 0, 1794, 0, 0x8780ULL }, // Inst #2326 = VCVTASD |
| 8051 | { 2325, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2325 = VCVTANUQh |
| 8052 | { 2324, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2324 = VCVTANUQf |
| 8053 | { 2323, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2323 = VCVTANUDh |
| 8054 | { 2322, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2322 = VCVTANUDf |
| 8055 | { 2321, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2321 = VCVTANSQh |
| 8056 | { 2320, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #2320 = VCVTANSQf |
| 8057 | { 2319, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2319 = VCVTANSDh |
| 8058 | { 2318, 2, 1, 4, 554, 0, 0, ARMImpOpBase + 0, 1792, 0, 0x11000ULL }, // Inst #2318 = VCVTANSDf |
| 8059 | { 2317, 4, 1, 4, 768, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2317 = VCNTq |
| 8060 | { 2316, 4, 1, 4, 769, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2316 = VCNTd |
| 8061 | { 2315, 3, 0, 4, 520, 0, 1, ARMImpOpBase + 70, 1789, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // Inst #2315 = VCMPZS |
| 8062 | { 2314, 3, 0, 4, 770, 0, 1, ARMImpOpBase + 70, 1786, 0, 0x8780ULL }, // Inst #2314 = VCMPZH |
| 8063 | { 2313, 3, 0, 4, 519, 0, 1, ARMImpOpBase + 70, 1783, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2313 = VCMPZD |
| 8064 | { 2312, 4, 0, 4, 1257, 0, 1, ARMImpOpBase + 70, 1686, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // Inst #2312 = VCMPS |
| 8065 | { 2311, 4, 0, 4, 770, 0, 1, ARMImpOpBase + 70, 1682, 0, 0x8780ULL }, // Inst #2311 = VCMPH |
| 8066 | { 2310, 3, 0, 4, 520, 0, 1, ARMImpOpBase + 70, 1789, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // Inst #2310 = VCMPEZS |
| 8067 | { 2309, 3, 0, 4, 770, 0, 1, ARMImpOpBase + 70, 1786, 0, 0x8780ULL }, // Inst #2309 = VCMPEZH |
| 8068 | { 2308, 3, 0, 4, 519, 0, 1, ARMImpOpBase + 70, 1783, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2308 = VCMPEZD |
| 8069 | { 2307, 4, 0, 4, 520, 0, 1, ARMImpOpBase + 70, 1686, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // Inst #2307 = VCMPES |
| 8070 | { 2306, 4, 0, 4, 770, 0, 1, ARMImpOpBase + 70, 1682, 0, 0x8780ULL }, // Inst #2306 = VCMPEH |
| 8071 | { 2305, 4, 0, 4, 519, 0, 1, ARMImpOpBase + 70, 1678, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2305 = VCMPED |
| 8072 | { 2304, 4, 0, 4, 1258, 0, 1, ARMImpOpBase + 70, 1678, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2304 = VCMPD |
| 8073 | { 2303, 6, 1, 4, 994, 0, 0, ARMImpOpBase + 0, 1777, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2303 = VCMLAv8f16_indexed |
| 8074 | { 2302, 5, 1, 4, 994, 0, 0, ARMImpOpBase + 0, 1766, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2302 = VCMLAv8f16 |
| 8075 | { 2301, 6, 1, 4, 994, 0, 0, ARMImpOpBase + 0, 1771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2301 = VCMLAv4f32_indexed |
| 8076 | { 2300, 5, 1, 4, 994, 0, 0, ARMImpOpBase + 0, 1766, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2300 = VCMLAv4f32 |
| 8077 | { 2299, 6, 1, 4, 993, 0, 0, ARMImpOpBase + 0, 1760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2299 = VCMLAv4f16_indexed |
| 8078 | { 2298, 5, 1, 4, 993, 0, 0, ARMImpOpBase + 0, 1749, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2298 = VCMLAv4f16 |
| 8079 | { 2297, 6, 1, 4, 993, 0, 0, ARMImpOpBase + 0, 1754, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2297 = VCMLAv2f32_indexed |
| 8080 | { 2296, 5, 1, 4, 993, 0, 0, ARMImpOpBase + 0, 1749, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2296 = VCMLAv2f32 |
| 8081 | { 2295, 4, 1, 4, 769, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2295 = VCLZv8i8 |
| 8082 | { 2294, 4, 1, 4, 768, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2294 = VCLZv8i16 |
| 8083 | { 2293, 4, 1, 4, 768, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2293 = VCLZv4i32 |
| 8084 | { 2292, 4, 1, 4, 769, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2292 = VCLZv4i16 |
| 8085 | { 2291, 4, 1, 4, 769, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2291 = VCLZv2i32 |
| 8086 | { 2290, 4, 1, 4, 768, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2290 = VCLZv16i8 |
| 8087 | { 2289, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2289 = VCLTzv8i8 |
| 8088 | { 2288, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2288 = VCLTzv8i16 |
| 8089 | { 2287, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2287 = VCLTzv8f16 |
| 8090 | { 2286, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2286 = VCLTzv4i32 |
| 8091 | { 2285, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2285 = VCLTzv4i16 |
| 8092 | { 2284, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2284 = VCLTzv4f32 |
| 8093 | { 2283, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2283 = VCLTzv4f16 |
| 8094 | { 2282, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2282 = VCLTzv2i32 |
| 8095 | { 2281, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2281 = VCLTzv2f32 |
| 8096 | { 2280, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2280 = VCLTzv16i8 |
| 8097 | { 2279, 4, 1, 4, 475, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2279 = VCLSv8i8 |
| 8098 | { 2278, 4, 1, 4, 474, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2278 = VCLSv8i16 |
| 8099 | { 2277, 4, 1, 4, 474, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2277 = VCLSv4i32 |
| 8100 | { 2276, 4, 1, 4, 475, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2276 = VCLSv4i16 |
| 8101 | { 2275, 4, 1, 4, 475, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2275 = VCLSv2i32 |
| 8102 | { 2274, 4, 1, 4, 474, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2274 = VCLSv16i8 |
| 8103 | { 2273, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2273 = VCLEzv8i8 |
| 8104 | { 2272, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2272 = VCLEzv8i16 |
| 8105 | { 2271, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2271 = VCLEzv8f16 |
| 8106 | { 2270, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2270 = VCLEzv4i32 |
| 8107 | { 2269, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2269 = VCLEzv4i16 |
| 8108 | { 2268, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2268 = VCLEzv4f32 |
| 8109 | { 2267, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2267 = VCLEzv4f16 |
| 8110 | { 2266, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2266 = VCLEzv2i32 |
| 8111 | { 2265, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2265 = VCLEzv2f32 |
| 8112 | { 2264, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2264 = VCLEzv16i8 |
| 8113 | { 2263, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2263 = VCGTzv8i8 |
| 8114 | { 2262, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2262 = VCGTzv8i16 |
| 8115 | { 2261, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2261 = VCGTzv8f16 |
| 8116 | { 2260, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2260 = VCGTzv4i32 |
| 8117 | { 2259, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2259 = VCGTzv4i16 |
| 8118 | { 2258, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2258 = VCGTzv4f32 |
| 8119 | { 2257, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2257 = VCGTzv4f16 |
| 8120 | { 2256, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2256 = VCGTzv2i32 |
| 8121 | { 2255, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2255 = VCGTzv2f32 |
| 8122 | { 2254, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2254 = VCGTzv16i8 |
| 8123 | { 2253, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2253 = VCGTuv8i8 |
| 8124 | { 2252, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2252 = VCGTuv8i16 |
| 8125 | { 2251, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2251 = VCGTuv4i32 |
| 8126 | { 2250, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2250 = VCGTuv4i16 |
| 8127 | { 2249, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2249 = VCGTuv2i32 |
| 8128 | { 2248, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2248 = VCGTuv16i8 |
| 8129 | { 2247, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2247 = VCGTsv8i8 |
| 8130 | { 2246, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2246 = VCGTsv8i16 |
| 8131 | { 2245, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2245 = VCGTsv4i32 |
| 8132 | { 2244, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2244 = VCGTsv4i16 |
| 8133 | { 2243, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2243 = VCGTsv2i32 |
| 8134 | { 2242, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2242 = VCGTsv16i8 |
| 8135 | { 2241, 5, 1, 4, 485, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2241 = VCGThq |
| 8136 | { 2240, 5, 1, 4, 484, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2240 = VCGThd |
| 8137 | { 2239, 5, 1, 4, 485, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2239 = VCGTfq |
| 8138 | { 2238, 5, 1, 4, 484, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2238 = VCGTfd |
| 8139 | { 2237, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2237 = VCGEzv8i8 |
| 8140 | { 2236, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2236 = VCGEzv8i16 |
| 8141 | { 2235, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2235 = VCGEzv8f16 |
| 8142 | { 2234, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2234 = VCGEzv4i32 |
| 8143 | { 2233, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2233 = VCGEzv4i16 |
| 8144 | { 2232, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2232 = VCGEzv4f32 |
| 8145 | { 2231, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2231 = VCGEzv4f16 |
| 8146 | { 2230, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2230 = VCGEzv2i32 |
| 8147 | { 2229, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2229 = VCGEzv2f32 |
| 8148 | { 2228, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2228 = VCGEzv16i8 |
| 8149 | { 2227, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2227 = VCGEuv8i8 |
| 8150 | { 2226, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2226 = VCGEuv8i16 |
| 8151 | { 2225, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2225 = VCGEuv4i32 |
| 8152 | { 2224, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2224 = VCGEuv4i16 |
| 8153 | { 2223, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2223 = VCGEuv2i32 |
| 8154 | { 2222, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2222 = VCGEuv16i8 |
| 8155 | { 2221, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2221 = VCGEsv8i8 |
| 8156 | { 2220, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2220 = VCGEsv8i16 |
| 8157 | { 2219, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2219 = VCGEsv4i32 |
| 8158 | { 2218, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2218 = VCGEsv4i16 |
| 8159 | { 2217, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2217 = VCGEsv2i32 |
| 8160 | { 2216, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2216 = VCGEsv16i8 |
| 8161 | { 2215, 5, 1, 4, 485, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2215 = VCGEhq |
| 8162 | { 2214, 5, 1, 4, 484, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2214 = VCGEhd |
| 8163 | { 2213, 5, 1, 4, 485, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2213 = VCGEfq |
| 8164 | { 2212, 5, 1, 4, 484, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2212 = VCGEfd |
| 8165 | { 2211, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2211 = VCEQzv8i8 |
| 8166 | { 2210, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2210 = VCEQzv8i16 |
| 8167 | { 2209, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2209 = VCEQzv8f16 |
| 8168 | { 2208, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2208 = VCEQzv4i32 |
| 8169 | { 2207, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2207 = VCEQzv4i16 |
| 8170 | { 2206, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2206 = VCEQzv4f32 |
| 8171 | { 2205, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2205 = VCEQzv4f16 |
| 8172 | { 2204, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2204 = VCEQzv2i32 |
| 8173 | { 2203, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2203 = VCEQzv2f32 |
| 8174 | { 2202, 4, 1, 4, 488, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2202 = VCEQzv16i8 |
| 8175 | { 2201, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2201 = VCEQv8i8 |
| 8176 | { 2200, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2200 = VCEQv8i16 |
| 8177 | { 2199, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2199 = VCEQv4i32 |
| 8178 | { 2198, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2198 = VCEQv4i16 |
| 8179 | { 2197, 5, 1, 4, 767, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2197 = VCEQv2i32 |
| 8180 | { 2196, 5, 1, 4, 766, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2196 = VCEQv16i8 |
| 8181 | { 2195, 5, 1, 4, 485, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2195 = VCEQhq |
| 8182 | { 2194, 5, 1, 4, 484, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2194 = VCEQhd |
| 8183 | { 2193, 5, 1, 4, 485, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2193 = VCEQfq |
| 8184 | { 2192, 5, 1, 4, 484, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2192 = VCEQfd |
| 8185 | { 2191, 4, 1, 4, 994, 0, 0, ARMImpOpBase + 0, 1745, 0, 0x11580ULL }, // Inst #2191 = VCADDv8f16 |
| 8186 | { 2190, 4, 1, 4, 994, 0, 0, ARMImpOpBase + 0, 1745, 0, 0x11580ULL }, // Inst #2190 = VCADDv4f32 |
| 8187 | { 2189, 4, 1, 4, 993, 0, 0, ARMImpOpBase + 0, 1741, 0, 0x11580ULL }, // Inst #2189 = VCADDv4f16 |
| 8188 | { 2188, 4, 1, 4, 993, 0, 0, ARMImpOpBase + 0, 1741, 0, 0x11580ULL }, // Inst #2188 = VCADDv2f32 |
| 8189 | { 2187, 6, 1, 4, 765, 0, 0, ARMImpOpBase + 0, 1735, 0|(1ULL<<MCID::Predicable), 0x10000ULL }, // Inst #2187 = VBSPq |
| 8190 | { 2186, 6, 1, 4, 764, 0, 0, ARMImpOpBase + 0, 1729, 0|(1ULL<<MCID::Predicable), 0x10000ULL }, // Inst #2186 = VBSPd |
| 8191 | { 2185, 6, 1, 4, 765, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #2185 = VBSLq |
| 8192 | { 2184, 6, 1, 4, 764, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #2184 = VBSLd |
| 8193 | { 2183, 6, 1, 4, 765, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #2183 = VBITq |
| 8194 | { 2182, 6, 1, 4, 764, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #2182 = VBITd |
| 8195 | { 2181, 6, 1, 4, 765, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #2181 = VBIFq |
| 8196 | { 2180, 6, 1, 4, 764, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #2180 = VBIFd |
| 8197 | { 2179, 5, 1, 4, 761, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2179 = VBICq |
| 8198 | { 2178, 5, 1, 4, 763, 0, 0, ARMImpOpBase + 0, 1724, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #2178 = VBICiv8i16 |
| 8199 | { 2177, 5, 1, 4, 763, 0, 0, ARMImpOpBase + 0, 1724, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #2177 = VBICiv4i32 |
| 8200 | { 2176, 5, 1, 4, 762, 0, 0, ARMImpOpBase + 0, 1719, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #2176 = VBICiv4i16 |
| 8201 | { 2175, 5, 1, 4, 762, 0, 0, ARMImpOpBase + 0, 1719, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #2175 = VBICiv2i32 |
| 8202 | { 2174, 5, 1, 4, 760, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2174 = VBICd |
| 8203 | { 2173, 5, 1, 4, 116, 0, 0, ARMImpOpBase + 0, 1714, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2173 = VBF16MALTQI |
| 8204 | { 2172, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11580ULL }, // Inst #2172 = VBF16MALTQ |
| 8205 | { 2171, 5, 1, 4, 116, 0, 0, ARMImpOpBase + 0, 1714, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2171 = VBF16MALBQI |
| 8206 | { 2170, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11580ULL }, // Inst #2170 = VBF16MALBQ |
| 8207 | { 2169, 5, 1, 4, 761, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2169 = VANDq |
| 8208 | { 2168, 5, 1, 4, 760, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2168 = VANDd |
| 8209 | { 2167, 5, 1, 4, 756, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2167 = VADDv8i8 |
| 8210 | { 2166, 5, 1, 4, 758, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2166 = VADDv8i16 |
| 8211 | { 2165, 5, 1, 4, 758, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2165 = VADDv4i32 |
| 8212 | { 2164, 5, 1, 4, 756, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2164 = VADDv4i16 |
| 8213 | { 2163, 5, 1, 4, 758, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2163 = VADDv2i64 |
| 8214 | { 2162, 5, 1, 4, 756, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2162 = VADDv2i32 |
| 8215 | { 2161, 5, 1, 4, 756, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2161 = VADDv1i64 |
| 8216 | { 2160, 5, 1, 4, 758, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2160 = VADDv16i8 |
| 8217 | { 2159, 5, 1, 4, 747, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2159 = VADDhq |
| 8218 | { 2158, 5, 1, 4, 745, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2158 = VADDhd |
| 8219 | { 2157, 5, 1, 4, 746, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2157 = VADDfq |
| 8220 | { 2156, 5, 1, 4, 744, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2156 = VADDfd |
| 8221 | { 2155, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1709, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2155 = VADDWuv8i16 |
| 8222 | { 2154, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1709, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2154 = VADDWuv4i32 |
| 8223 | { 2153, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1709, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2153 = VADDWuv2i64 |
| 8224 | { 2152, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1709, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2152 = VADDWsv8i16 |
| 8225 | { 2151, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1709, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2151 = VADDWsv4i32 |
| 8226 | { 2150, 5, 1, 4, 462, 0, 0, ARMImpOpBase + 0, 1709, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2150 = VADDWsv2i64 |
| 8227 | { 2149, 5, 1, 4, 521, 0, 0, ARMImpOpBase + 0, 1704, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #2149 = VADDS |
| 8228 | { 2148, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2148 = VADDLuv8i16 |
| 8229 | { 2147, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2147 = VADDLuv4i32 |
| 8230 | { 2146, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2146 = VADDLuv2i64 |
| 8231 | { 2145, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2145 = VADDLsv8i16 |
| 8232 | { 2144, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2144 = VADDLsv4i32 |
| 8233 | { 2143, 5, 1, 4, 759, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2143 = VADDLsv2i64 |
| 8234 | { 2142, 5, 1, 4, 501, 0, 0, ARMImpOpBase + 0, 1699, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2142 = VADDHNv8i8 |
| 8235 | { 2141, 5, 1, 4, 501, 0, 0, ARMImpOpBase + 0, 1699, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2141 = VADDHNv4i16 |
| 8236 | { 2140, 5, 1, 4, 501, 0, 0, ARMImpOpBase + 0, 1699, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2140 = VADDHNv2i32 |
| 8237 | { 2139, 5, 1, 4, 743, 0, 0, ARMImpOpBase + 0, 1694, 0, 0x8800ULL }, // Inst #2139 = VADDH |
| 8238 | { 2138, 5, 1, 4, 527, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2138 = VADDD |
| 8239 | { 2137, 5, 1, 4, 742, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2137 = VACGThq |
| 8240 | { 2136, 5, 1, 4, 741, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2136 = VACGThd |
| 8241 | { 2135, 5, 1, 4, 742, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2135 = VACGTfq |
| 8242 | { 2134, 5, 1, 4, 741, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2134 = VACGTfd |
| 8243 | { 2133, 5, 1, 4, 742, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2133 = VACGEhq |
| 8244 | { 2132, 5, 1, 4, 741, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2132 = VACGEhd |
| 8245 | { 2131, 5, 1, 4, 742, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2131 = VACGEfq |
| 8246 | { 2130, 5, 1, 4, 741, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2130 = VACGEfd |
| 8247 | { 2129, 4, 1, 4, 494, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2129 = VABSv8i8 |
| 8248 | { 2128, 4, 1, 4, 493, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2128 = VABSv8i16 |
| 8249 | { 2127, 4, 1, 4, 493, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2127 = VABSv4i32 |
| 8250 | { 2126, 4, 1, 4, 494, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2126 = VABSv4i16 |
| 8251 | { 2125, 4, 1, 4, 494, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2125 = VABSv2i32 |
| 8252 | { 2124, 4, 1, 4, 493, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2124 = VABSv16i8 |
| 8253 | { 2123, 4, 1, 4, 740, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2123 = VABShq |
| 8254 | { 2122, 4, 1, 4, 739, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2122 = VABShd |
| 8255 | { 2121, 4, 1, 4, 492, 0, 0, ARMImpOpBase + 0, 1690, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2121 = VABSfq |
| 8256 | { 2120, 4, 1, 4, 491, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2120 = VABSfd |
| 8257 | { 2119, 4, 1, 4, 738, 0, 0, ARMImpOpBase + 0, 1686, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // Inst #2119 = VABSS |
| 8258 | { 2118, 4, 1, 4, 737, 0, 0, ARMImpOpBase + 0, 1682, 0, 0x8780ULL }, // Inst #2118 = VABSH |
| 8259 | { 2117, 4, 1, 4, 736, 0, 0, ARMImpOpBase + 0, 1678, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2117 = VABSD |
| 8260 | { 2116, 5, 1, 4, 753, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2116 = VABDuv8i8 |
| 8261 | { 2115, 5, 1, 4, 754, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2115 = VABDuv8i16 |
| 8262 | { 2114, 5, 1, 4, 754, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2114 = VABDuv4i32 |
| 8263 | { 2113, 5, 1, 4, 753, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2113 = VABDuv4i16 |
| 8264 | { 2112, 5, 1, 4, 753, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2112 = VABDuv2i32 |
| 8265 | { 2111, 5, 1, 4, 754, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2111 = VABDuv16i8 |
| 8266 | { 2110, 5, 1, 4, 753, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2110 = VABDsv8i8 |
| 8267 | { 2109, 5, 1, 4, 754, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2109 = VABDsv8i16 |
| 8268 | { 2108, 5, 1, 4, 754, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2108 = VABDsv4i32 |
| 8269 | { 2107, 5, 1, 4, 753, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2107 = VABDsv4i16 |
| 8270 | { 2106, 5, 1, 4, 753, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2106 = VABDsv2i32 |
| 8271 | { 2105, 5, 1, 4, 754, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2105 = VABDsv16i8 |
| 8272 | { 2104, 5, 1, 4, 735, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2104 = VABDhq |
| 8273 | { 2103, 5, 1, 4, 734, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2103 = VABDhd |
| 8274 | { 2102, 5, 1, 4, 735, 0, 0, ARMImpOpBase + 0, 1673, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2102 = VABDfq |
| 8275 | { 2101, 5, 1, 4, 734, 0, 0, ARMImpOpBase + 0, 1668, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2101 = VABDfd |
| 8276 | { 2100, 5, 1, 4, 755, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2100 = VABDLuv8i16 |
| 8277 | { 2099, 5, 1, 4, 755, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2099 = VABDLuv4i32 |
| 8278 | { 2098, 5, 1, 4, 524, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2098 = VABDLuv2i64 |
| 8279 | { 2097, 5, 1, 4, 755, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2097 = VABDLsv8i16 |
| 8280 | { 2096, 5, 1, 4, 755, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2096 = VABDLsv4i32 |
| 8281 | { 2095, 5, 1, 4, 524, 0, 0, ARMImpOpBase + 0, 1663, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2095 = VABDLsv2i64 |
| 8282 | { 2094, 6, 1, 4, 752, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2094 = VABAuv8i8 |
| 8283 | { 2093, 6, 1, 4, 481, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2093 = VABAuv8i16 |
| 8284 | { 2092, 6, 1, 4, 481, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2092 = VABAuv4i32 |
| 8285 | { 2091, 6, 1, 4, 752, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2091 = VABAuv4i16 |
| 8286 | { 2090, 6, 1, 4, 752, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2090 = VABAuv2i32 |
| 8287 | { 2089, 6, 1, 4, 481, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2089 = VABAuv16i8 |
| 8288 | { 2088, 6, 1, 4, 752, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2088 = VABAsv8i8 |
| 8289 | { 2087, 6, 1, 4, 481, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2087 = VABAsv8i16 |
| 8290 | { 2086, 6, 1, 4, 481, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2086 = VABAsv4i32 |
| 8291 | { 2085, 6, 1, 4, 752, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2085 = VABAsv4i16 |
| 8292 | { 2084, 6, 1, 4, 752, 0, 0, ARMImpOpBase + 0, 1657, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2084 = VABAsv2i32 |
| 8293 | { 2083, 6, 1, 4, 481, 0, 0, ARMImpOpBase + 0, 1651, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2083 = VABAsv16i8 |
| 8294 | { 2082, 6, 1, 4, 480, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2082 = VABALuv8i16 |
| 8295 | { 2081, 6, 1, 4, 480, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2081 = VABALuv4i32 |
| 8296 | { 2080, 6, 1, 4, 480, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2080 = VABALuv2i64 |
| 8297 | { 2079, 6, 1, 4, 480, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2079 = VABALsv8i16 |
| 8298 | { 2078, 6, 1, 4, 480, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2078 = VABALsv4i32 |
| 8299 | { 2077, 6, 1, 4, 480, 0, 0, ARMImpOpBase + 0, 1645, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2077 = VABALsv2i64 |
| 8300 | { 2076, 5, 1, 4, 897, 0, 0, ARMImpOpBase + 0, 1632, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2076 = UXTH |
| 8301 | { 2075, 5, 1, 4, 352, 0, 0, ARMImpOpBase + 0, 1632, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2075 = UXTB16 |
| 8302 | { 2074, 5, 1, 4, 897, 0, 0, ARMImpOpBase + 0, 1632, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2074 = UXTB |
| 8303 | { 2073, 6, 1, 4, 900, 0, 0, ARMImpOpBase + 0, 1626, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2073 = UXTAH |
| 8304 | { 2072, 6, 1, 4, 367, 0, 0, ARMImpOpBase + 0, 1626, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2072 = UXTAB16 |
| 8305 | { 2071, 6, 1, 4, 900, 0, 0, ARMImpOpBase + 0, 1626, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2071 = UXTAB |
| 8306 | { 2070, 5, 1, 4, 885, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #2070 = USUB8 |
| 8307 | { 2069, 5, 1, 4, 885, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #2069 = USUB16 |
| 8308 | { 2068, 5, 1, 4, 364, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #2068 = USAX |
| 8309 | { 2067, 5, 1, 4, 893, 0, 0, ARMImpOpBase + 0, 1565, 0|(1ULL<<MCID::Predicable), 0x680ULL }, // Inst #2067 = USAT16 |
| 8310 | { 2066, 6, 1, 4, 893, 0, 0, ARMImpOpBase + 0, 1559, 0|(1ULL<<MCID::Predicable), 0x680ULL }, // Inst #2066 = USAT |
| 8311 | { 2065, 6, 1, 4, 371, 0, 0, ARMImpOpBase + 0, 1002, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #2065 = USADA8 |
| 8312 | { 2064, 5, 1, 4, 370, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #2064 = USAD8 |
| 8313 | { 2063, 5, 1, 4, 889, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2063 = UQSUB8 |
| 8314 | { 2062, 5, 1, 4, 889, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2062 = UQSUB16 |
| 8315 | { 2061, 5, 1, 4, 891, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2061 = UQSAX |
| 8316 | { 2060, 5, 1, 4, 891, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2060 = UQASX |
| 8317 | { 2059, 5, 1, 4, 889, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2059 = UQADD8 |
| 8318 | { 2058, 5, 1, 4, 889, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2058 = UQADD16 |
| 8319 | { 2057, 7, 2, 4, 339, 0, 0, ARMImpOpBase + 0, 1552, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // Inst #2057 = UMULL |
| 8320 | { 2056, 9, 2, 4, 340, 0, 0, ARMImpOpBase + 0, 1535, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // Inst #2056 = UMLAL |
| 8321 | { 2055, 8, 2, 4, 340, 0, 0, ARMImpOpBase + 0, 1637, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #2055 = UMAAL |
| 8322 | { 2054, 5, 1, 4, 887, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2054 = UHSUB8 |
| 8323 | { 2053, 5, 1, 4, 887, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2053 = UHSUB16 |
| 8324 | { 2052, 5, 1, 4, 366, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2052 = UHSAX |
| 8325 | { 2051, 5, 1, 4, 366, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2051 = UHASX |
| 8326 | { 2050, 5, 1, 4, 887, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2050 = UHADD8 |
| 8327 | { 2049, 5, 1, 4, 887, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2049 = UHADD16 |
| 8328 | { 2048, 5, 1, 4, 385, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #2048 = UDIV |
| 8329 | { 2047, 1, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #2047 = UDF |
| 8330 | { 2046, 6, 1, 4, 895, 0, 0, ARMImpOpBase + 0, 1523, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL }, // Inst #2046 = UBFX |
| 8331 | { 2045, 5, 1, 4, 364, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #2045 = UASX |
| 8332 | { 2044, 5, 1, 4, 885, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #2044 = UADD8 |
| 8333 | { 2043, 5, 1, 4, 885, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #2043 = UADD16 |
| 8334 | { 2042, 6, 0, 4, 727, 0, 1, ARMImpOpBase + 0, 849, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL }, // Inst #2042 = TSTrsr |
| 8335 | { 2041, 5, 0, 4, 726, 0, 1, ARMImpOpBase + 0, 844, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL }, // Inst #2041 = TSTrsi |
| 8336 | { 2040, 4, 0, 4, 725, 0, 1, ARMImpOpBase + 0, 840, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL }, // Inst #2040 = TSTrr |
| 8337 | { 2039, 4, 0, 4, 724, 0, 1, ARMImpOpBase + 0, 243, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #2039 = TSTri |
| 8338 | { 2038, 1, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #2038 = TSB |
| 8339 | { 2037, 0, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #2037 = TRAPNaCl |
| 8340 | { 2036, 0, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #2036 = TRAP |
| 8341 | { 2035, 6, 0, 4, 95, 0, 1, ARMImpOpBase + 0, 849, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL }, // Inst #2035 = TEQrsr |
| 8342 | { 2034, 5, 0, 4, 94, 0, 1, ARMImpOpBase + 0, 844, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL }, // Inst #2034 = TEQrsi |
| 8343 | { 2033, 4, 0, 4, 93, 0, 1, ARMImpOpBase + 0, 840, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL }, // Inst #2033 = TEQrr |
| 8344 | { 2032, 4, 0, 4, 92, 0, 1, ARMImpOpBase + 0, 243, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #2032 = TEQri |
| 8345 | { 2031, 5, 1, 4, 897, 0, 0, ARMImpOpBase + 0, 1632, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2031 = SXTH |
| 8346 | { 2030, 5, 1, 4, 352, 0, 0, ARMImpOpBase + 0, 1632, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2030 = SXTB16 |
| 8347 | { 2029, 5, 1, 4, 897, 0, 0, ARMImpOpBase + 0, 1632, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2029 = SXTB |
| 8348 | { 2028, 6, 1, 4, 900, 0, 0, ARMImpOpBase + 0, 1626, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2028 = SXTAH |
| 8349 | { 2027, 6, 1, 4, 367, 0, 0, ARMImpOpBase + 0, 1626, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2027 = SXTAB16 |
| 8350 | { 2026, 6, 1, 4, 900, 0, 0, ARMImpOpBase + 0, 1626, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2026 = SXTAB |
| 8351 | { 2025, 5, 1, 4, 844, 0, 0, ARMImpOpBase + 0, 1621, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #2025 = SWPB |
| 8352 | { 2024, 5, 1, 4, 844, 0, 0, ARMImpOpBase + 0, 1621, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #2024 = SWP |
| 8353 | { 2023, 3, 0, 4, 845, 1, 0, ARMImpOpBase + 54, 861, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #2023 = SVC |
| 8354 | { 2022, 8, 1, 4, 45, 0, 0, ARMImpOpBase + 0, 617, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #2022 = SUBrsr |
| 8355 | { 2021, 7, 1, 4, 3, 0, 0, ARMImpOpBase + 0, 602, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #2021 = SUBrsi |
| 8356 | { 2020, 6, 1, 4, 2, 0, 0, ARMImpOpBase + 0, 596, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #2020 = SUBrr |
| 8357 | { 2019, 6, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 181, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #2019 = SUBri |
| 8358 | { 2018, 6, 0, 4, 428, 0, 0, ARMImpOpBase + 0, 963, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x380ULL }, // Inst #2018 = STRrs |
| 8359 | { 2017, 5, 0, 4, 426, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x392ULL }, // Inst #2017 = STRi12 |
| 8360 | { 2016, 7, 1, 4, 948, 0, 0, ARMImpOpBase + 0, 1587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL }, // Inst #2016 = STR_PRE_REG |
| 8361 | { 2015, 6, 1, 4, 940, 0, 0, ARMImpOpBase + 0, 1594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL }, // Inst #2015 = STR_PRE_IMM |
| 8362 | { 2014, 7, 1, 4, 439, 0, 0, ARMImpOpBase + 0, 1587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #2014 = STR_POST_REG |
| 8363 | { 2013, 7, 1, 4, 440, 0, 0, ARMImpOpBase + 0, 1587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #2013 = STR_POST_IMM |
| 8364 | { 2012, 7, 1, 4, 439, 0, 0, ARMImpOpBase + 0, 1580, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #2012 = STRT_POST_REG |
| 8365 | { 2011, 7, 1, 4, 951, 0, 0, ARMImpOpBase + 0, 1580, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #2011 = STRT_POST_IMM |
| 8366 | { 2010, 7, 1, 4, 944, 0, 0, ARMImpOpBase + 0, 1614, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a3ULL }, // Inst #2010 = STRH_PRE |
| 8367 | { 2009, 7, 1, 4, 437, 0, 0, ARMImpOpBase + 0, 1614, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x4c3ULL }, // Inst #2009 = STRH_POST |
| 8368 | { 2008, 7, 1, 4, 437, 0, 0, ARMImpOpBase + 0, 1580, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4c3ULL }, // Inst #2008 = STRHTr |
| 8369 | { 2007, 6, 1, 4, 437, 0, 0, ARMImpOpBase + 0, 1608, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4c3ULL }, // Inst #2007 = STRHTi |
| 8370 | { 2006, 6, 0, 4, 427, 0, 0, ARMImpOpBase + 0, 943, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x483ULL }, // Inst #2006 = STRH |
| 8371 | { 2005, 5, 1, 4, 430, 0, 0, ARMImpOpBase + 0, 1570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #2005 = STREXH |
| 8372 | { 2004, 5, 1, 4, 430, 0, 0, ARMImpOpBase + 0, 1575, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x580ULL }, // Inst #2004 = STREXD |
| 8373 | { 2003, 5, 1, 4, 430, 0, 0, ARMImpOpBase + 0, 1570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #2003 = STREXB |
| 8374 | { 2002, 5, 1, 4, 430, 0, 0, ARMImpOpBase + 0, 1570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #2002 = STREX |
| 8375 | { 2001, 8, 1, 4, 950, 0, 0, ARMImpOpBase + 0, 1600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4a3ULL }, // Inst #2001 = STRD_PRE |
| 8376 | { 2000, 8, 1, 4, 450, 0, 0, ARMImpOpBase + 0, 1600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4c3ULL }, // Inst #2000 = STRD_POST |
| 8377 | { 1999, 7, 0, 4, 447, 0, 0, ARMImpOpBase + 0, 928, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x483ULL }, // Inst #1999 = STRD |
| 8378 | { 1998, 6, 0, 4, 429, 0, 0, ARMImpOpBase + 0, 922, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x380ULL }, // Inst #1998 = STRBrs |
| 8379 | { 1997, 5, 0, 4, 938, 0, 0, ARMImpOpBase + 0, 917, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x392ULL }, // Inst #1997 = STRBi12 |
| 8380 | { 1996, 7, 1, 4, 949, 0, 0, ARMImpOpBase + 0, 1587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL }, // Inst #1996 = STRB_PRE_REG |
| 8381 | { 1995, 6, 1, 4, 941, 0, 0, ARMImpOpBase + 0, 1594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL }, // Inst #1995 = STRB_PRE_IMM |
| 8382 | { 1994, 7, 1, 4, 955, 0, 0, ARMImpOpBase + 0, 1587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #1994 = STRB_POST_REG |
| 8383 | { 1993, 7, 1, 4, 438, 0, 0, ARMImpOpBase + 0, 1587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #1993 = STRB_POST_IMM |
| 8384 | { 1992, 7, 1, 4, 955, 0, 0, ARMImpOpBase + 0, 1580, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x3c2ULL }, // Inst #1992 = STRBT_POST_REG |
| 8385 | { 1991, 7, 1, 4, 952, 0, 0, ARMImpOpBase + 0, 1580, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x3c2ULL }, // Inst #1991 = STRBT_POST_IMM |
| 8386 | { 1990, 5, 1, 4, 452, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #1990 = STMIB_UPD |
| 8387 | { 1989, 4, 0, 4, 451, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #1989 = STMIB |
| 8388 | { 1988, 5, 1, 4, 452, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #1988 = STMIA_UPD |
| 8389 | { 1987, 4, 0, 4, 451, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #1987 = STMIA |
| 8390 | { 1986, 5, 1, 4, 452, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #1986 = STMDB_UPD |
| 8391 | { 1985, 4, 0, 4, 451, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #1985 = STMDB |
| 8392 | { 1984, 5, 1, 4, 452, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #1984 = STMDA_UPD |
| 8393 | { 1983, 4, 0, 4, 451, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #1983 = STMDA |
| 8394 | { 1982, 4, 0, 4, 732, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL }, // Inst #1982 = STLH |
| 8395 | { 1981, 5, 1, 4, 732, 0, 0, ARMImpOpBase + 0, 1570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #1981 = STLEXH |
| 8396 | { 1980, 5, 1, 4, 732, 0, 0, ARMImpOpBase + 0, 1575, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x580ULL }, // Inst #1980 = STLEXD |
| 8397 | { 1979, 5, 1, 4, 732, 0, 0, ARMImpOpBase + 0, 1570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #1979 = STLEXB |
| 8398 | { 1978, 5, 1, 4, 732, 0, 0, ARMImpOpBase + 0, 1570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #1978 = STLEX |
| 8399 | { 1977, 4, 0, 4, 732, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL }, // Inst #1977 = STLB |
| 8400 | { 1976, 4, 0, 4, 732, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL }, // Inst #1976 = STL |
| 8401 | { 1975, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #1975 = STC_PRE |
| 8402 | { 1974, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #1974 = STC_POST |
| 8403 | { 1973, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 898, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1973 = STC_OPTION |
| 8404 | { 1972, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #1972 = STC_OFFSET |
| 8405 | { 1971, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #1971 = STCL_PRE |
| 8406 | { 1970, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #1970 = STCL_POST |
| 8407 | { 1969, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 898, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1969 = STCL_OPTION |
| 8408 | { 1968, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #1968 = STCL_OFFSET |
| 8409 | { 1967, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 884, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #1967 = STC2_PRE |
| 8410 | { 1966, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 884, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #1966 = STC2_POST |
| 8411 | { 1965, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 888, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1965 = STC2_OPTION |
| 8412 | { 1964, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 884, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #1964 = STC2_OFFSET |
| 8413 | { 1963, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 884, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #1963 = STC2L_PRE |
| 8414 | { 1962, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 884, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #1962 = STC2L_POST |
| 8415 | { 1961, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 888, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1961 = STC2L_OPTION |
| 8416 | { 1960, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 884, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #1960 = STC2L_OFFSET |
| 8417 | { 1959, 5, 1, 4, 885, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1959 = SSUB8 |
| 8418 | { 1958, 5, 1, 4, 885, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1958 = SSUB16 |
| 8419 | { 1957, 5, 1, 4, 364, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1957 = SSAX |
| 8420 | { 1956, 5, 1, 4, 893, 0, 0, ARMImpOpBase + 0, 1565, 0|(1ULL<<MCID::Predicable), 0x680ULL }, // Inst #1956 = SSAT16 |
| 8421 | { 1955, 6, 1, 4, 893, 0, 0, ARMImpOpBase + 0, 1559, 0|(1ULL<<MCID::Predicable), 0x680ULL }, // Inst #1955 = SSAT |
| 8422 | { 1954, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1954 = SRSIB_UPD |
| 8423 | { 1953, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1953 = SRSIB |
| 8424 | { 1952, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1952 = SRSIA_UPD |
| 8425 | { 1951, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1951 = SRSIA |
| 8426 | { 1950, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1950 = SRSDB_UPD |
| 8427 | { 1949, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1949 = SRSDB |
| 8428 | { 1948, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1948 = SRSDA_UPD |
| 8429 | { 1947, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1947 = SRSDA |
| 8430 | { 1946, 5, 1, 4, 372, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1946 = SMUSDX |
| 8431 | { 1945, 5, 1, 4, 372, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1945 = SMUSD |
| 8432 | { 1944, 5, 1, 4, 345, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1944 = SMULWT |
| 8433 | { 1943, 5, 1, 4, 345, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1943 = SMULWB |
| 8434 | { 1942, 5, 1, 4, 345, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1942 = SMULTT |
| 8435 | { 1941, 5, 1, 4, 345, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1941 = SMULTB |
| 8436 | { 1940, 7, 2, 4, 382, 0, 0, ARMImpOpBase + 0, 1552, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // Inst #1940 = SMULL |
| 8437 | { 1939, 5, 1, 4, 345, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1939 = SMULBT |
| 8438 | { 1938, 5, 1, 4, 345, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1938 = SMULBB |
| 8439 | { 1937, 5, 1, 4, 344, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1937 = SMUADX |
| 8440 | { 1936, 5, 1, 4, 344, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1936 = SMUAD |
| 8441 | { 1935, 5, 1, 4, 336, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1935 = SMMULR |
| 8442 | { 1934, 5, 1, 4, 336, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1934 = SMMUL |
| 8443 | { 1933, 6, 1, 4, 337, 0, 0, ARMImpOpBase + 0, 1002, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1933 = SMMLSR |
| 8444 | { 1932, 6, 1, 4, 337, 0, 0, ARMImpOpBase + 0, 1002, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1932 = SMMLS |
| 8445 | { 1931, 6, 1, 4, 337, 0, 0, ARMImpOpBase + 0, 1002, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1931 = SMMLAR |
| 8446 | { 1930, 6, 1, 4, 337, 0, 0, ARMImpOpBase + 0, 1002, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1930 = SMMLA |
| 8447 | { 1929, 8, 2, 4, 343, 0, 0, ARMImpOpBase + 0, 1544, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1929 = SMLSLDX |
| 8448 | { 1928, 8, 2, 4, 342, 0, 0, ARMImpOpBase + 0, 1544, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1928 = SMLSLD |
| 8449 | { 1927, 6, 1, 4, 378, 0, 0, ARMImpOpBase + 0, 1529, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1927 = SMLSDX |
| 8450 | { 1926, 6, 1, 4, 378, 0, 0, ARMImpOpBase + 0, 1529, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1926 = SMLSD |
| 8451 | { 1925, 6, 1, 4, 346, 0, 0, ARMImpOpBase + 0, 1529, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1925 = SMLAWT |
| 8452 | { 1924, 6, 1, 4, 346, 0, 0, ARMImpOpBase + 0, 1529, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1924 = SMLAWB |
| 8453 | { 1923, 6, 1, 4, 346, 0, 0, ARMImpOpBase + 0, 1529, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1923 = SMLATT |
| 8454 | { 1922, 6, 1, 4, 346, 0, 0, ARMImpOpBase + 0, 1529, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1922 = SMLATB |
| 8455 | { 1921, 8, 2, 4, 340, 0, 0, ARMImpOpBase + 0, 1544, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1921 = SMLALTT |
| 8456 | { 1920, 8, 2, 4, 340, 0, 0, ARMImpOpBase + 0, 1544, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1920 = SMLALTB |
| 8457 | { 1919, 8, 2, 4, 343, 0, 0, ARMImpOpBase + 0, 1544, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1919 = SMLALDX |
| 8458 | { 1918, 8, 2, 4, 342, 0, 0, ARMImpOpBase + 0, 1544, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1918 = SMLALD |
| 8459 | { 1917, 8, 2, 4, 340, 0, 0, ARMImpOpBase + 0, 1544, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1917 = SMLALBT |
| 8460 | { 1916, 8, 2, 4, 340, 0, 0, ARMImpOpBase + 0, 1544, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1916 = SMLALBB |
| 8461 | { 1915, 9, 2, 4, 340, 0, 0, ARMImpOpBase + 0, 1535, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // Inst #1915 = SMLAL |
| 8462 | { 1914, 6, 1, 4, 341, 0, 0, ARMImpOpBase + 0, 1529, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1914 = SMLADX |
| 8463 | { 1913, 6, 1, 4, 341, 0, 0, ARMImpOpBase + 0, 1529, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1913 = SMLAD |
| 8464 | { 1912, 6, 1, 4, 346, 0, 0, ARMImpOpBase + 0, 1529, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1912 = SMLABT |
| 8465 | { 1911, 6, 1, 4, 346, 0, 0, ARMImpOpBase + 0, 1529, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1911 = SMLABB |
| 8466 | { 1910, 3, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1910 = SMC |
| 8467 | { 1909, 5, 1, 4, 887, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1909 = SHSUB8 |
| 8468 | { 1908, 5, 1, 4, 887, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1908 = SHSUB16 |
| 8469 | { 1907, 5, 1, 4, 366, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1907 = SHSAX |
| 8470 | { 1906, 5, 1, 4, 366, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1906 = SHASX |
| 8471 | { 1905, 5, 1, 4, 887, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1905 = SHADD8 |
| 8472 | { 1904, 5, 1, 4, 887, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1904 = SHADD16 |
| 8473 | { 1903, 4, 1, 4, 1016, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #1903 = SHA256SU1 |
| 8474 | { 1902, 3, 1, 4, 1015, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #1902 = SHA256SU0 |
| 8475 | { 1901, 4, 1, 4, 1016, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #1901 = SHA256H2 |
| 8476 | { 1900, 4, 1, 4, 1016, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #1900 = SHA256H |
| 8477 | { 1899, 3, 1, 4, 1013, 0, 0, ARMImpOpBase + 0, 625, 0, 0x11000ULL }, // Inst #1899 = SHA1SU1 |
| 8478 | { 1898, 4, 1, 4, 1012, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #1898 = SHA1SU0 |
| 8479 | { 1897, 4, 1, 4, 1014, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #1897 = SHA1P |
| 8480 | { 1896, 4, 1, 4, 1014, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #1896 = SHA1M |
| 8481 | { 1895, 2, 1, 4, 1013, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #1895 = SHA1H |
| 8482 | { 1894, 4, 1, 4, 1014, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #1894 = SHA1C |
| 8483 | { 1893, 1, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #1893 = SETPAN |
| 8484 | { 1892, 1, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #1892 = SETEND |
| 8485 | { 1891, 5, 1, 4, 334, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1891 = SEL |
| 8486 | { 1890, 5, 1, 4, 385, 0, 0, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1890 = SDIV |
| 8487 | { 1889, 6, 1, 4, 895, 0, 0, ARMImpOpBase + 0, 1523, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL }, // Inst #1889 = SBFX |
| 8488 | { 1888, 8, 1, 4, 710, 1, 1, ARMImpOpBase + 63, 609, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL }, // Inst #1888 = SBCrsr |
| 8489 | { 1887, 7, 1, 4, 704, 1, 1, ARMImpOpBase + 63, 602, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL }, // Inst #1887 = SBCrsi |
| 8490 | { 1886, 6, 1, 4, 701, 1, 1, ARMImpOpBase + 63, 596, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // Inst #1886 = SBCrr |
| 8491 | { 1885, 6, 1, 4, 694, 1, 1, ARMImpOpBase + 63, 181, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // Inst #1885 = SBCri |
| 8492 | { 1884, 0, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #1884 = SB |
| 8493 | { 1883, 5, 1, 4, 364, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1883 = SASX |
| 8494 | { 1882, 5, 1, 4, 885, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1882 = SADD8 |
| 8495 | { 1881, 5, 1, 4, 885, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1881 = SADD16 |
| 8496 | { 1880, 8, 1, 4, 710, 1, 1, ARMImpOpBase + 63, 617, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL }, // Inst #1880 = RSCrsr |
| 8497 | { 1879, 7, 1, 4, 704, 1, 1, ARMImpOpBase + 63, 602, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL }, // Inst #1879 = RSCrsi |
| 8498 | { 1878, 6, 1, 4, 701, 1, 1, ARMImpOpBase + 63, 596, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL }, // Inst #1878 = RSCrr |
| 8499 | { 1877, 6, 1, 4, 694, 1, 1, ARMImpOpBase + 63, 181, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // Inst #1877 = RSCri |
| 8500 | { 1876, 8, 1, 4, 710, 0, 0, ARMImpOpBase + 0, 617, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #1876 = RSBrsr |
| 8501 | { 1875, 7, 1, 4, 704, 0, 0, ARMImpOpBase + 0, 602, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #1875 = RSBrsi |
| 8502 | { 1874, 6, 1, 4, 701, 0, 0, ARMImpOpBase + 0, 596, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL }, // Inst #1874 = RSBrr |
| 8503 | { 1873, 6, 1, 4, 694, 0, 0, ARMImpOpBase + 0, 181, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #1873 = RSBri |
| 8504 | { 1872, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1872 = RFEIB_UPD |
| 8505 | { 1871, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1871 = RFEIB |
| 8506 | { 1870, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1870 = RFEIA_UPD |
| 8507 | { 1869, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1869 = RFEIA |
| 8508 | { 1868, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1868 = RFEDB_UPD |
| 8509 | { 1867, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1867 = RFEDB |
| 8510 | { 1866, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1866 = RFEDA_UPD |
| 8511 | { 1865, 1, 0, 4, 730, 0, 0, ARMImpOpBase + 0, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1865 = RFEDA |
| 8512 | { 1864, 4, 1, 4, 722, 0, 0, ARMImpOpBase + 0, 840, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1864 = REVSH |
| 8513 | { 1863, 4, 1, 4, 722, 0, 0, ARMImpOpBase + 0, 840, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1863 = REV16 |
| 8514 | { 1862, 4, 1, 4, 722, 0, 0, ARMImpOpBase + 0, 840, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1862 = REV |
| 8515 | { 1861, 4, 1, 4, 722, 0, 0, ARMImpOpBase + 0, 840, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1861 = RBIT |
| 8516 | { 1860, 5, 1, 4, 889, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1860 = QSUB8 |
| 8517 | { 1859, 5, 1, 4, 889, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1859 = QSUB16 |
| 8518 | { 1858, 5, 1, 4, 894, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1858 = QSUB |
| 8519 | { 1857, 5, 1, 4, 891, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1857 = QSAX |
| 8520 | { 1856, 5, 1, 4, 361, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1856 = QDSUB |
| 8521 | { 1855, 5, 1, 4, 361, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1855 = QDADD |
| 8522 | { 1854, 5, 1, 4, 891, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1854 = QASX |
| 8523 | { 1853, 5, 1, 4, 889, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1853 = QADD8 |
| 8524 | { 1852, 5, 1, 4, 889, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1852 = QADD16 |
| 8525 | { 1851, 5, 1, 4, 894, 0, 0, ARMImpOpBase + 0, 1518, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1851 = QADD |
| 8526 | { 1850, 3, 0, 4, 935, 0, 0, ARMImpOpBase + 0, 1515, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL }, // Inst #1850 = PLIrs |
| 8527 | { 1849, 2, 0, 4, 935, 0, 0, ARMImpOpBase + 0, 1513, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd12ULL }, // Inst #1849 = PLIi12 |
| 8528 | { 1848, 3, 0, 4, 936, 0, 0, ARMImpOpBase + 0, 1515, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL }, // Inst #1848 = PLDrs |
| 8529 | { 1847, 2, 0, 4, 935, 0, 0, ARMImpOpBase + 0, 1513, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd12ULL }, // Inst #1847 = PLDi12 |
| 8530 | { 1846, 3, 0, 4, 936, 0, 0, ARMImpOpBase + 0, 1515, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL }, // Inst #1846 = PLDWrs |
| 8531 | { 1845, 2, 0, 4, 935, 0, 0, ARMImpOpBase + 0, 1513, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd12ULL }, // Inst #1845 = PLDWi12 |
| 8532 | { 1844, 6, 1, 4, 73, 0, 0, ARMImpOpBase + 0, 1507, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1844 = PKHTB |
| 8533 | { 1843, 6, 1, 4, 39, 0, 0, ARMImpOpBase + 0, 1507, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1843 = PKHBT |
| 8534 | { 1842, 8, 1, 4, 324, 0, 0, ARMImpOpBase + 0, 617, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #1842 = ORRrsr |
| 8535 | { 1841, 7, 1, 4, 323, 0, 0, ARMImpOpBase + 0, 602, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #1841 = ORRrsi |
| 8536 | { 1840, 6, 1, 4, 322, 0, 0, ARMImpOpBase + 0, 596, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #1840 = ORRrr |
| 8537 | { 1839, 6, 1, 4, 321, 0, 0, ARMImpOpBase + 0, 181, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #1839 = ORRri |
| 8538 | { 1838, 3, 1, 4, 997, 0, 0, ARMImpOpBase + 0, 1504, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1838 = NEON_VMINNMNQh |
| 8539 | { 1837, 3, 1, 4, 997, 0, 0, ARMImpOpBase + 0, 1504, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1837 = NEON_VMINNMNQf |
| 8540 | { 1836, 3, 1, 4, 997, 0, 0, ARMImpOpBase + 0, 1501, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1836 = NEON_VMINNMNDh |
| 8541 | { 1835, 3, 1, 4, 997, 0, 0, ARMImpOpBase + 0, 1501, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1835 = NEON_VMINNMNDf |
| 8542 | { 1834, 3, 1, 4, 997, 0, 0, ARMImpOpBase + 0, 1504, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1834 = NEON_VMAXNMNQh |
| 8543 | { 1833, 3, 1, 4, 997, 0, 0, ARMImpOpBase + 0, 1504, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1833 = NEON_VMAXNMNQf |
| 8544 | { 1832, 3, 1, 4, 997, 0, 0, ARMImpOpBase + 0, 1501, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1832 = NEON_VMAXNMNDh |
| 8545 | { 1831, 3, 1, 4, 997, 0, 0, ARMImpOpBase + 0, 1501, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1831 = NEON_VMAXNMNDf |
| 8546 | { 1830, 7, 1, 4, 327, 0, 0, ARMImpOpBase + 0, 1494, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2281ULL }, // Inst #1830 = MVNsr |
| 8547 | { 1829, 6, 1, 4, 713, 0, 0, ARMImpOpBase + 0, 1023, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x3501ULL }, // Inst #1829 = MVNsi |
| 8548 | { 1828, 5, 1, 4, 329, 0, 0, ARMImpOpBase + 0, 329, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL }, // Inst #1828 = MVNr |
| 8549 | { 1827, 5, 1, 4, 712, 0, 0, ARMImpOpBase + 0, 1013, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL }, // Inst #1827 = MVNi |
| 8550 | { 1826, 3, 1, 4, 1286, 0, 0, ARMImpOpBase + 0, 514, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #1826 = MVE_WLSTP_8 |
| 8551 | { 1825, 3, 1, 4, 1286, 0, 0, ARMImpOpBase + 0, 514, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #1825 = MVE_WLSTP_64 |
| 8552 | { 1824, 3, 1, 4, 1286, 0, 0, ARMImpOpBase + 0, 514, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #1824 = MVE_WLSTP_32 |
| 8553 | { 1823, 3, 1, 4, 1286, 0, 0, ARMImpOpBase + 0, 514, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #1823 = MVE_WLSTP_16 |
| 8554 | { 1822, 7, 1, 4, 1171, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1822 = MVE_VSUBi8 |
| 8555 | { 1821, 7, 1, 4, 1171, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1821 = MVE_VSUBi32 |
| 8556 | { 1820, 7, 1, 4, 1171, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1820 = MVE_VSUBi16 |
| 8557 | { 1819, 7, 1, 4, 1202, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1819 = MVE_VSUBf32 |
| 8558 | { 1818, 7, 1, 4, 1202, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1818 = MVE_VSUBf16 |
| 8559 | { 1817, 7, 1, 4, 1302, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1817 = MVE_VSUB_qr_i8 |
| 8560 | { 1816, 7, 1, 4, 1302, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1816 = MVE_VSUB_qr_i32 |
| 8561 | { 1815, 7, 1, 4, 1302, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1815 = MVE_VSUB_qr_i16 |
| 8562 | { 1814, 7, 1, 4, 1203, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1814 = MVE_VSUB_qr_f32 |
| 8563 | { 1813, 7, 1, 4, 1203, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1813 = MVE_VSUB_qr_f16 |
| 8564 | { 1812, 7, 1, 4, 1122, 0, 0, ARMImpOpBase + 0, 1311, 0|(1ULL<<MCID::MayStore), 0x2140cb5ULL }, // Inst #1812 = MVE_VSTRWU32_pre |
| 8565 | { 1811, 7, 1, 4, 1122, 0, 0, ARMImpOpBase + 0, 1311, 0|(1ULL<<MCID::MayStore), 0x2140cd5ULL }, // Inst #1811 = MVE_VSTRWU32_post |
| 8566 | { 1810, 6, 0, 4, 1121, 0, 0, ARMImpOpBase + 0, 1305, 0|(1ULL<<MCID::MayStore), 0x2140c95ULL }, // Inst #1810 = MVE_VSTRWU32 |
| 8567 | { 1809, 6, 0, 4, 1123, 0, 0, ARMImpOpBase + 0, 1475, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1809 = MVE_VSTRW32_rq_u |
| 8568 | { 1808, 6, 0, 4, 1123, 0, 0, ARMImpOpBase + 0, 1475, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1808 = MVE_VSTRW32_rq |
| 8569 | { 1807, 7, 1, 4, 1124, 0, 0, ARMImpOpBase + 0, 1487, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1807 = MVE_VSTRW32_qi_pre |
| 8570 | { 1806, 6, 0, 4, 1267, 0, 0, ARMImpOpBase + 0, 1481, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1806 = MVE_VSTRW32_qi |
| 8571 | { 1805, 7, 1, 4, 1122, 0, 0, ARMImpOpBase + 0, 1311, 0|(1ULL<<MCID::MayStore), 0x1140cb6ULL }, // Inst #1805 = MVE_VSTRHU16_pre |
| 8572 | { 1804, 7, 1, 4, 1122, 0, 0, ARMImpOpBase + 0, 1311, 0|(1ULL<<MCID::MayStore), 0x1140cd6ULL }, // Inst #1804 = MVE_VSTRHU16_post |
| 8573 | { 1803, 6, 0, 4, 1121, 0, 0, ARMImpOpBase + 0, 1305, 0|(1ULL<<MCID::MayStore), 0x1140c96ULL }, // Inst #1803 = MVE_VSTRHU16 |
| 8574 | { 1802, 6, 0, 4, 1123, 0, 0, ARMImpOpBase + 0, 1475, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1802 = MVE_VSTRH32_rq_u |
| 8575 | { 1801, 6, 0, 4, 1123, 0, 0, ARMImpOpBase + 0, 1475, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1801 = MVE_VSTRH32_rq |
| 8576 | { 1800, 7, 1, 4, 1122, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayStore), 0x2140cb6ULL }, // Inst #1800 = MVE_VSTRH32_pre |
| 8577 | { 1799, 7, 1, 4, 1122, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayStore), 0x2140cd6ULL }, // Inst #1799 = MVE_VSTRH32_post |
| 8578 | { 1798, 6, 0, 4, 1121, 0, 0, ARMImpOpBase + 0, 1286, 0|(1ULL<<MCID::MayStore), 0x2140c96ULL }, // Inst #1798 = MVE_VSTRH32 |
| 8579 | { 1797, 6, 0, 4, 1123, 0, 0, ARMImpOpBase + 0, 1475, 0|(1ULL<<MCID::MayStore), 0x1140c80ULL }, // Inst #1797 = MVE_VSTRH16_rq_u |
| 8580 | { 1796, 6, 0, 4, 1123, 0, 0, ARMImpOpBase + 0, 1475, 0|(1ULL<<MCID::MayStore), 0x1140c80ULL }, // Inst #1796 = MVE_VSTRH16_rq |
| 8581 | { 1795, 6, 0, 4, 1123, 0, 0, ARMImpOpBase + 0, 1475, 0|(1ULL<<MCID::MayStore), 0x3140c80ULL }, // Inst #1795 = MVE_VSTRD64_rq_u |
| 8582 | { 1794, 6, 0, 4, 1123, 0, 0, ARMImpOpBase + 0, 1475, 0|(1ULL<<MCID::MayStore), 0x3140c80ULL }, // Inst #1794 = MVE_VSTRD64_rq |
| 8583 | { 1793, 7, 1, 4, 1124, 0, 0, ARMImpOpBase + 0, 1487, 0|(1ULL<<MCID::MayStore), 0x3140c80ULL }, // Inst #1793 = MVE_VSTRD64_qi_pre |
| 8584 | { 1792, 6, 0, 4, 1267, 0, 0, ARMImpOpBase + 0, 1481, 0|(1ULL<<MCID::MayStore), 0x3140c80ULL }, // Inst #1792 = MVE_VSTRD64_qi |
| 8585 | { 1791, 7, 1, 4, 1122, 0, 0, ARMImpOpBase + 0, 1311, 0|(1ULL<<MCID::MayStore), 0x140cb7ULL }, // Inst #1791 = MVE_VSTRBU8_pre |
| 8586 | { 1790, 7, 1, 4, 1122, 0, 0, ARMImpOpBase + 0, 1311, 0|(1ULL<<MCID::MayStore), 0x140cd7ULL }, // Inst #1790 = MVE_VSTRBU8_post |
| 8587 | { 1789, 6, 0, 4, 1121, 0, 0, ARMImpOpBase + 0, 1305, 0|(1ULL<<MCID::MayStore), 0x140c97ULL }, // Inst #1789 = MVE_VSTRBU8 |
| 8588 | { 1788, 6, 0, 4, 1123, 0, 0, ARMImpOpBase + 0, 1475, 0|(1ULL<<MCID::MayStore), 0x140c80ULL }, // Inst #1788 = MVE_VSTRB8_rq |
| 8589 | { 1787, 6, 0, 4, 1123, 0, 0, ARMImpOpBase + 0, 1475, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1787 = MVE_VSTRB32_rq |
| 8590 | { 1786, 7, 1, 4, 1122, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayStore), 0x2140cb7ULL }, // Inst #1786 = MVE_VSTRB32_pre |
| 8591 | { 1785, 7, 1, 4, 1122, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayStore), 0x2140cd7ULL }, // Inst #1785 = MVE_VSTRB32_post |
| 8592 | { 1784, 6, 0, 4, 1121, 0, 0, ARMImpOpBase + 0, 1286, 0|(1ULL<<MCID::MayStore), 0x2140c97ULL }, // Inst #1784 = MVE_VSTRB32 |
| 8593 | { 1783, 6, 0, 4, 1123, 0, 0, ARMImpOpBase + 0, 1475, 0|(1ULL<<MCID::MayStore), 0x1140c80ULL }, // Inst #1783 = MVE_VSTRB16_rq |
| 8594 | { 1782, 7, 1, 4, 1122, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayStore), 0x1140cb7ULL }, // Inst #1782 = MVE_VSTRB16_pre |
| 8595 | { 1781, 7, 1, 4, 1122, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayStore), 0x1140cd7ULL }, // Inst #1781 = MVE_VSTRB16_post |
| 8596 | { 1780, 6, 0, 4, 1121, 0, 0, ARMImpOpBase + 0, 1286, 0|(1ULL<<MCID::MayStore), 0x1140c97ULL }, // Inst #1780 = MVE_VSTRB16 |
| 8597 | { 1779, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1472, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1779 = MVE_VST43_8_wb |
| 8598 | { 1778, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1470, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1778 = MVE_VST43_8 |
| 8599 | { 1777, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1472, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1777 = MVE_VST43_32_wb |
| 8600 | { 1776, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1470, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1776 = MVE_VST43_32 |
| 8601 | { 1775, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1472, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1775 = MVE_VST43_16_wb |
| 8602 | { 1774, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1470, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1774 = MVE_VST43_16 |
| 8603 | { 1773, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1472, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1773 = MVE_VST42_8_wb |
| 8604 | { 1772, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1470, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1772 = MVE_VST42_8 |
| 8605 | { 1771, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1472, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1771 = MVE_VST42_32_wb |
| 8606 | { 1770, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1470, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1770 = MVE_VST42_32 |
| 8607 | { 1769, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1472, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1769 = MVE_VST42_16_wb |
| 8608 | { 1768, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1470, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1768 = MVE_VST42_16 |
| 8609 | { 1767, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1472, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1767 = MVE_VST41_8_wb |
| 8610 | { 1766, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1470, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1766 = MVE_VST41_8 |
| 8611 | { 1765, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1472, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1765 = MVE_VST41_32_wb |
| 8612 | { 1764, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1470, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1764 = MVE_VST41_32 |
| 8613 | { 1763, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1472, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1763 = MVE_VST41_16_wb |
| 8614 | { 1762, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1470, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1762 = MVE_VST41_16 |
| 8615 | { 1761, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1472, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1761 = MVE_VST40_8_wb |
| 8616 | { 1760, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1470, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1760 = MVE_VST40_8 |
| 8617 | { 1759, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1472, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1759 = MVE_VST40_32_wb |
| 8618 | { 1758, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1470, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1758 = MVE_VST40_32 |
| 8619 | { 1757, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1472, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1757 = MVE_VST40_16_wb |
| 8620 | { 1756, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1470, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1756 = MVE_VST40_16 |
| 8621 | { 1755, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1467, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1755 = MVE_VST21_8_wb |
| 8622 | { 1754, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1465, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1754 = MVE_VST21_8 |
| 8623 | { 1753, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1467, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1753 = MVE_VST21_32_wb |
| 8624 | { 1752, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1465, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1752 = MVE_VST21_32 |
| 8625 | { 1751, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1467, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1751 = MVE_VST21_16_wb |
| 8626 | { 1750, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1465, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1750 = MVE_VST21_16 |
| 8627 | { 1749, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1467, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1749 = MVE_VST20_8_wb |
| 8628 | { 1748, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1465, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1748 = MVE_VST20_8 |
| 8629 | { 1747, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1467, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1747 = MVE_VST20_32_wb |
| 8630 | { 1746, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1465, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1746 = MVE_VST20_32 |
| 8631 | { 1745, 3, 1, 4, 1125, 0, 0, ARMImpOpBase + 0, 1467, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1745 = MVE_VST20_16_wb |
| 8632 | { 1744, 2, 0, 4, 1266, 0, 0, ARMImpOpBase + 0, 1465, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1744 = MVE_VST20_16 |
| 8633 | { 1743, 7, 1, 4, 1170, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x140c80ULL }, // Inst #1743 = MVE_VSRIimm8 |
| 8634 | { 1742, 7, 1, 4, 1170, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2140c80ULL }, // Inst #1742 = MVE_VSRIimm32 |
| 8635 | { 1741, 7, 1, 4, 1170, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1140c80ULL }, // Inst #1741 = MVE_VSRIimm16 |
| 8636 | { 1740, 7, 1, 4, 1169, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x140c80ULL }, // Inst #1740 = MVE_VSLIimm8 |
| 8637 | { 1739, 7, 1, 4, 1169, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2140c80ULL }, // Inst #1739 = MVE_VSLIimm32 |
| 8638 | { 1738, 7, 1, 4, 1169, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1140c80ULL }, // Inst #1738 = MVE_VSLIimm16 |
| 8639 | { 1737, 7, 1, 4, 1163, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x140c80ULL }, // Inst #1737 = MVE_VSHR_immu8 |
| 8640 | { 1736, 7, 1, 4, 1163, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2140c80ULL }, // Inst #1736 = MVE_VSHR_immu32 |
| 8641 | { 1735, 7, 1, 4, 1163, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1140c80ULL }, // Inst #1735 = MVE_VSHR_immu16 |
| 8642 | { 1734, 7, 1, 4, 1163, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x140c80ULL }, // Inst #1734 = MVE_VSHR_imms8 |
| 8643 | { 1733, 7, 1, 4, 1163, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2140c80ULL }, // Inst #1733 = MVE_VSHR_imms32 |
| 8644 | { 1732, 7, 1, 4, 1163, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1140c80ULL }, // Inst #1732 = MVE_VSHR_imms16 |
| 8645 | { 1731, 7, 1, 4, 1304, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1731 = MVE_VSHRNi32th |
| 8646 | { 1730, 7, 1, 4, 1304, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1730 = MVE_VSHRNi32bh |
| 8647 | { 1729, 7, 1, 4, 1304, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1729 = MVE_VSHRNi16th |
| 8648 | { 1728, 7, 1, 4, 1304, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1728 = MVE_VSHRNi16bh |
| 8649 | { 1727, 6, 1, 4, 1301, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x140c80ULL }, // Inst #1727 = MVE_VSHL_qru8 |
| 8650 | { 1726, 6, 1, 4, 1301, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x2140c80ULL }, // Inst #1726 = MVE_VSHL_qru32 |
| 8651 | { 1725, 6, 1, 4, 1301, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x1140c80ULL }, // Inst #1725 = MVE_VSHL_qru16 |
| 8652 | { 1724, 6, 1, 4, 1301, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x140c80ULL }, // Inst #1724 = MVE_VSHL_qrs8 |
| 8653 | { 1723, 6, 1, 4, 1301, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x2140c80ULL }, // Inst #1723 = MVE_VSHL_qrs32 |
| 8654 | { 1722, 6, 1, 4, 1301, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x1140c80ULL }, // Inst #1722 = MVE_VSHL_qrs16 |
| 8655 | { 1721, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x140c80ULL }, // Inst #1721 = MVE_VSHL_immi8 |
| 8656 | { 1720, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2140c80ULL }, // Inst #1720 = MVE_VSHL_immi32 |
| 8657 | { 1719, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1140c80ULL }, // Inst #1719 = MVE_VSHL_immi16 |
| 8658 | { 1718, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1718 = MVE_VSHL_by_vecu8 |
| 8659 | { 1717, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1717 = MVE_VSHL_by_vecu32 |
| 8660 | { 1716, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1716 = MVE_VSHL_by_vecu16 |
| 8661 | { 1715, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1715 = MVE_VSHL_by_vecs8 |
| 8662 | { 1714, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1714 = MVE_VSHL_by_vecs32 |
| 8663 | { 1713, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1713 = MVE_VSHL_by_vecs16 |
| 8664 | { 1712, 6, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1840c80ULL }, // Inst #1712 = MVE_VSHLL_lwu8th |
| 8665 | { 1711, 6, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1840c80ULL }, // Inst #1711 = MVE_VSHLL_lwu8bh |
| 8666 | { 1710, 6, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2840c80ULL }, // Inst #1710 = MVE_VSHLL_lwu16th |
| 8667 | { 1709, 6, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2840c80ULL }, // Inst #1709 = MVE_VSHLL_lwu16bh |
| 8668 | { 1708, 6, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1840c80ULL }, // Inst #1708 = MVE_VSHLL_lws8th |
| 8669 | { 1707, 6, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1840c80ULL }, // Inst #1707 = MVE_VSHLL_lws8bh |
| 8670 | { 1706, 6, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2840c80ULL }, // Inst #1706 = MVE_VSHLL_lws16th |
| 8671 | { 1705, 6, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2840c80ULL }, // Inst #1705 = MVE_VSHLL_lws16bh |
| 8672 | { 1704, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1840c80ULL }, // Inst #1704 = MVE_VSHLL_immu8th |
| 8673 | { 1703, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1840c80ULL }, // Inst #1703 = MVE_VSHLL_immu8bh |
| 8674 | { 1702, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2840c80ULL }, // Inst #1702 = MVE_VSHLL_immu16th |
| 8675 | { 1701, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2840c80ULL }, // Inst #1701 = MVE_VSHLL_immu16bh |
| 8676 | { 1700, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1840c80ULL }, // Inst #1700 = MVE_VSHLL_imms8th |
| 8677 | { 1699, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1840c80ULL }, // Inst #1699 = MVE_VSHLL_imms8bh |
| 8678 | { 1698, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2840c80ULL }, // Inst #1698 = MVE_VSHLL_imms16th |
| 8679 | { 1697, 7, 1, 4, 1303, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2840c80ULL }, // Inst #1697 = MVE_VSHLL_imms16bh |
| 8680 | { 1696, 8, 2, 4, 1159, 0, 0, ARMImpOpBase + 0, 1457, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // Inst #1696 = MVE_VSHLC |
| 8681 | { 1695, 8, 2, 4, 1168, 0, 0, ARMImpOpBase + 0, 1133, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // Inst #1695 = MVE_VSBCI |
| 8682 | { 1694, 9, 2, 4, 1168, 0, 0, ARMImpOpBase + 0, 1124, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // Inst #1694 = MVE_VSBC |
| 8683 | { 1693, 7, 1, 4, 1164, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x140c80ULL }, // Inst #1693 = MVE_VRSHR_immu8 |
| 8684 | { 1692, 7, 1, 4, 1164, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2140c80ULL }, // Inst #1692 = MVE_VRSHR_immu32 |
| 8685 | { 1691, 7, 1, 4, 1164, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1140c80ULL }, // Inst #1691 = MVE_VRSHR_immu16 |
| 8686 | { 1690, 7, 1, 4, 1164, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x140c80ULL }, // Inst #1690 = MVE_VRSHR_imms8 |
| 8687 | { 1689, 7, 1, 4, 1164, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2140c80ULL }, // Inst #1689 = MVE_VRSHR_imms32 |
| 8688 | { 1688, 7, 1, 4, 1164, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1140c80ULL }, // Inst #1688 = MVE_VRSHR_imms16 |
| 8689 | { 1687, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1687 = MVE_VRSHRNi32th |
| 8690 | { 1686, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1686 = MVE_VRSHRNi32bh |
| 8691 | { 1685, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1685 = MVE_VRSHRNi16th |
| 8692 | { 1684, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1684 = MVE_VRSHRNi16bh |
| 8693 | { 1683, 6, 1, 4, 1308, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x140c80ULL }, // Inst #1683 = MVE_VRSHL_qru8 |
| 8694 | { 1682, 6, 1, 4, 1308, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x2140c80ULL }, // Inst #1682 = MVE_VRSHL_qru32 |
| 8695 | { 1681, 6, 1, 4, 1308, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x1140c80ULL }, // Inst #1681 = MVE_VRSHL_qru16 |
| 8696 | { 1680, 6, 1, 4, 1308, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x140c80ULL }, // Inst #1680 = MVE_VRSHL_qrs8 |
| 8697 | { 1679, 6, 1, 4, 1308, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x2140c80ULL }, // Inst #1679 = MVE_VRSHL_qrs32 |
| 8698 | { 1678, 6, 1, 4, 1308, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x1140c80ULL }, // Inst #1678 = MVE_VRSHL_qrs16 |
| 8699 | { 1677, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1677 = MVE_VRSHL_by_vecu8 |
| 8700 | { 1676, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1676 = MVE_VRSHL_by_vecu32 |
| 8701 | { 1675, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1675 = MVE_VRSHL_by_vecu16 |
| 8702 | { 1674, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1674 = MVE_VRSHL_by_vecs8 |
| 8703 | { 1673, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1673 = MVE_VRSHL_by_vecs32 |
| 8704 | { 1672, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1672 = MVE_VRSHL_by_vecs16 |
| 8705 | { 1671, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1671 = MVE_VRMULHu8 |
| 8706 | { 1670, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1670 = MVE_VRMULHu32 |
| 8707 | { 1669, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1669 = MVE_VRMULHu16 |
| 8708 | { 1668, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1668 = MVE_VRMULHs8 |
| 8709 | { 1667, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1667 = MVE_VRMULHs32 |
| 8710 | { 1666, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1666 = MVE_VRMULHs16 |
| 8711 | { 1665, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x2440c80ULL }, // Inst #1665 = MVE_VRMLSLDAVHxs32 |
| 8712 | { 1664, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x2540c80ULL }, // Inst #1664 = MVE_VRMLSLDAVHs32 |
| 8713 | { 1663, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x2440c80ULL }, // Inst #1663 = MVE_VRMLSLDAVHaxs32 |
| 8714 | { 1662, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x2540c80ULL }, // Inst #1662 = MVE_VRMLSLDAVHas32 |
| 8715 | { 1661, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x2440c80ULL }, // Inst #1661 = MVE_VRMLALDAVHxs32 |
| 8716 | { 1660, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x2540c80ULL }, // Inst #1660 = MVE_VRMLALDAVHu32 |
| 8717 | { 1659, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x2540c80ULL }, // Inst #1659 = MVE_VRMLALDAVHs32 |
| 8718 | { 1658, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x2440c80ULL }, // Inst #1658 = MVE_VRMLALDAVHaxs32 |
| 8719 | { 1657, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x2540c80ULL }, // Inst #1657 = MVE_VRMLALDAVHau32 |
| 8720 | { 1656, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x2540c80ULL }, // Inst #1656 = MVE_VRMLALDAVHas32 |
| 8721 | { 1655, 6, 1, 4, 1201, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1655 = MVE_VRINTf32Z |
| 8722 | { 1654, 6, 1, 4, 1201, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1654 = MVE_VRINTf32X |
| 8723 | { 1653, 6, 1, 4, 1201, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1653 = MVE_VRINTf32P |
| 8724 | { 1652, 6, 1, 4, 1201, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1652 = MVE_VRINTf32N |
| 8725 | { 1651, 6, 1, 4, 1201, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1651 = MVE_VRINTf32M |
| 8726 | { 1650, 6, 1, 4, 1201, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1650 = MVE_VRINTf32A |
| 8727 | { 1649, 6, 1, 4, 1201, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1649 = MVE_VRINTf16Z |
| 8728 | { 1648, 6, 1, 4, 1201, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1648 = MVE_VRINTf16X |
| 8729 | { 1647, 6, 1, 4, 1201, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1647 = MVE_VRINTf16P |
| 8730 | { 1646, 6, 1, 4, 1201, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1646 = MVE_VRINTf16N |
| 8731 | { 1645, 6, 1, 4, 1201, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1645 = MVE_VRINTf16M |
| 8732 | { 1644, 6, 1, 4, 1201, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1644 = MVE_VRINTf16A |
| 8733 | { 1643, 7, 1, 4, 1167, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1643 = MVE_VRHADDu8 |
| 8734 | { 1642, 7, 1, 4, 1167, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1642 = MVE_VRHADDu32 |
| 8735 | { 1641, 7, 1, 4, 1167, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1641 = MVE_VRHADDu16 |
| 8736 | { 1640, 7, 1, 4, 1167, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1640 = MVE_VRHADDs8 |
| 8737 | { 1639, 7, 1, 4, 1167, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1639 = MVE_VRHADDs32 |
| 8738 | { 1638, 7, 1, 4, 1167, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1638 = MVE_VRHADDs16 |
| 8739 | { 1637, 6, 1, 4, 1166, 0, 0, ARMImpOpBase + 0, 1451, 0, 0x3040c80ULL }, // Inst #1637 = MVE_VREV64_8 |
| 8740 | { 1636, 6, 1, 4, 1166, 0, 0, ARMImpOpBase + 0, 1451, 0, 0x3040c80ULL }, // Inst #1636 = MVE_VREV64_32 |
| 8741 | { 1635, 6, 1, 4, 1166, 0, 0, ARMImpOpBase + 0, 1451, 0, 0x3040c80ULL }, // Inst #1635 = MVE_VREV64_16 |
| 8742 | { 1634, 6, 1, 4, 1166, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2040c80ULL }, // Inst #1634 = MVE_VREV32_8 |
| 8743 | { 1633, 6, 1, 4, 1166, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2040c80ULL }, // Inst #1633 = MVE_VREV32_16 |
| 8744 | { 1632, 6, 1, 4, 1166, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1040c80ULL }, // Inst #1632 = MVE_VREV16_8 |
| 8745 | { 1631, 7, 1, 4, 1165, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1631 = MVE_VQSUBu8 |
| 8746 | { 1630, 7, 1, 4, 1165, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1630 = MVE_VQSUBu32 |
| 8747 | { 1629, 7, 1, 4, 1165, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1629 = MVE_VQSUBu16 |
| 8748 | { 1628, 7, 1, 4, 1165, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1628 = MVE_VQSUBs8 |
| 8749 | { 1627, 7, 1, 4, 1165, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1627 = MVE_VQSUBs32 |
| 8750 | { 1626, 7, 1, 4, 1165, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1626 = MVE_VQSUBs16 |
| 8751 | { 1625, 7, 1, 4, 1300, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1625 = MVE_VQSUB_qr_u8 |
| 8752 | { 1624, 7, 1, 4, 1300, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1624 = MVE_VQSUB_qr_u32 |
| 8753 | { 1623, 7, 1, 4, 1300, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1623 = MVE_VQSUB_qr_u16 |
| 8754 | { 1622, 7, 1, 4, 1300, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1622 = MVE_VQSUB_qr_s8 |
| 8755 | { 1621, 7, 1, 4, 1300, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1621 = MVE_VQSUB_qr_s32 |
| 8756 | { 1620, 7, 1, 4, 1300, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1620 = MVE_VQSUB_qr_s16 |
| 8757 | { 1619, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1619 = MVE_VQSHRUNs32th |
| 8758 | { 1618, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1618 = MVE_VQSHRUNs32bh |
| 8759 | { 1617, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1617 = MVE_VQSHRUNs16th |
| 8760 | { 1616, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1616 = MVE_VQSHRUNs16bh |
| 8761 | { 1615, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1615 = MVE_VQSHRNthu32 |
| 8762 | { 1614, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1614 = MVE_VQSHRNthu16 |
| 8763 | { 1613, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1613 = MVE_VQSHRNths32 |
| 8764 | { 1612, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1612 = MVE_VQSHRNths16 |
| 8765 | { 1611, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1611 = MVE_VQSHRNbhu32 |
| 8766 | { 1610, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1610 = MVE_VQSHRNbhu16 |
| 8767 | { 1609, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1609 = MVE_VQSHRNbhs32 |
| 8768 | { 1608, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1608 = MVE_VQSHRNbhs16 |
| 8769 | { 1607, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x140c80ULL }, // Inst #1607 = MVE_VQSHLimmu8 |
| 8770 | { 1606, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2140c80ULL }, // Inst #1606 = MVE_VQSHLimmu32 |
| 8771 | { 1605, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1140c80ULL }, // Inst #1605 = MVE_VQSHLimmu16 |
| 8772 | { 1604, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x140c80ULL }, // Inst #1604 = MVE_VQSHLimms8 |
| 8773 | { 1603, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2140c80ULL }, // Inst #1603 = MVE_VQSHLimms32 |
| 8774 | { 1602, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1140c80ULL }, // Inst #1602 = MVE_VQSHLimms16 |
| 8775 | { 1601, 6, 1, 4, 1308, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x140c80ULL }, // Inst #1601 = MVE_VQSHL_qru8 |
| 8776 | { 1600, 6, 1, 4, 1308, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x2140c80ULL }, // Inst #1600 = MVE_VQSHL_qru32 |
| 8777 | { 1599, 6, 1, 4, 1308, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x1140c80ULL }, // Inst #1599 = MVE_VQSHL_qru16 |
| 8778 | { 1598, 6, 1, 4, 1308, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x140c80ULL }, // Inst #1598 = MVE_VQSHL_qrs8 |
| 8779 | { 1597, 6, 1, 4, 1308, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x2140c80ULL }, // Inst #1597 = MVE_VQSHL_qrs32 |
| 8780 | { 1596, 6, 1, 4, 1308, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x1140c80ULL }, // Inst #1596 = MVE_VQSHL_qrs16 |
| 8781 | { 1595, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1595 = MVE_VQSHL_by_vecu8 |
| 8782 | { 1594, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1594 = MVE_VQSHL_by_vecu32 |
| 8783 | { 1593, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1593 = MVE_VQSHL_by_vecu16 |
| 8784 | { 1592, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1592 = MVE_VQSHL_by_vecs8 |
| 8785 | { 1591, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1591 = MVE_VQSHL_by_vecs32 |
| 8786 | { 1590, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1590 = MVE_VQSHL_by_vecs16 |
| 8787 | { 1589, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x140c80ULL }, // Inst #1589 = MVE_VQSHLU_imms8 |
| 8788 | { 1588, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2140c80ULL }, // Inst #1588 = MVE_VQSHLU_imms32 |
| 8789 | { 1587, 7, 1, 4, 1160, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1140c80ULL }, // Inst #1587 = MVE_VQSHLU_imms16 |
| 8790 | { 1586, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1586 = MVE_VQRSHRUNs32th |
| 8791 | { 1585, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1585 = MVE_VQRSHRUNs32bh |
| 8792 | { 1584, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1584 = MVE_VQRSHRUNs16th |
| 8793 | { 1583, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1583 = MVE_VQRSHRUNs16bh |
| 8794 | { 1582, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1582 = MVE_VQRSHRNthu32 |
| 8795 | { 1581, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1581 = MVE_VQRSHRNthu16 |
| 8796 | { 1580, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1580 = MVE_VQRSHRNths32 |
| 8797 | { 1579, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1579 = MVE_VQRSHRNths16 |
| 8798 | { 1578, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1578 = MVE_VQRSHRNbhu32 |
| 8799 | { 1577, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1577 = MVE_VQRSHRNbhu16 |
| 8800 | { 1576, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x2340c80ULL }, // Inst #1576 = MVE_VQRSHRNbhs32 |
| 8801 | { 1575, 7, 1, 4, 1162, 0, 0, ARMImpOpBase + 0, 1444, 0, 0x1340c80ULL }, // Inst #1575 = MVE_VQRSHRNbhs16 |
| 8802 | { 1574, 6, 1, 4, 1307, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x140c80ULL }, // Inst #1574 = MVE_VQRSHL_qru8 |
| 8803 | { 1573, 6, 1, 4, 1307, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x2140c80ULL }, // Inst #1573 = MVE_VQRSHL_qru32 |
| 8804 | { 1572, 6, 1, 4, 1307, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x1140c80ULL }, // Inst #1572 = MVE_VQRSHL_qru16 |
| 8805 | { 1571, 6, 1, 4, 1307, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x140c80ULL }, // Inst #1571 = MVE_VQRSHL_qrs8 |
| 8806 | { 1570, 6, 1, 4, 1307, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x2140c80ULL }, // Inst #1570 = MVE_VQRSHL_qrs32 |
| 8807 | { 1569, 6, 1, 4, 1307, 0, 0, ARMImpOpBase + 0, 1438, 0, 0x1140c80ULL }, // Inst #1569 = MVE_VQRSHL_qrs16 |
| 8808 | { 1568, 7, 1, 4, 1161, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1568 = MVE_VQRSHL_by_vecu8 |
| 8809 | { 1567, 7, 1, 4, 1161, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1567 = MVE_VQRSHL_by_vecu32 |
| 8810 | { 1566, 7, 1, 4, 1161, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1566 = MVE_VQRSHL_by_vecu16 |
| 8811 | { 1565, 7, 1, 4, 1161, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1565 = MVE_VQRSHL_by_vecs8 |
| 8812 | { 1564, 7, 1, 4, 1161, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1564 = MVE_VQRSHL_by_vecs32 |
| 8813 | { 1563, 7, 1, 4, 1161, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1563 = MVE_VQRSHL_by_vecs16 |
| 8814 | { 1562, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1562 = MVE_VQRDMULHi8 |
| 8815 | { 1561, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1561 = MVE_VQRDMULHi32 |
| 8816 | { 1560, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1560 = MVE_VQRDMULHi16 |
| 8817 | { 1559, 7, 1, 4, 1313, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1559 = MVE_VQRDMULH_qr_s8 |
| 8818 | { 1558, 7, 1, 4, 1313, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1558 = MVE_VQRDMULH_qr_s32 |
| 8819 | { 1557, 7, 1, 4, 1313, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1557 = MVE_VQRDMULH_qr_s16 |
| 8820 | { 1556, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x40c80ULL }, // Inst #1556 = MVE_VQRDMLSDHs8 |
| 8821 | { 1555, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1424, 0, 0x2040c80ULL }, // Inst #1555 = MVE_VQRDMLSDHs32 |
| 8822 | { 1554, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x1040c80ULL }, // Inst #1554 = MVE_VQRDMLSDHs16 |
| 8823 | { 1553, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x40c80ULL }, // Inst #1553 = MVE_VQRDMLSDHXs8 |
| 8824 | { 1552, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1424, 0, 0x2040c80ULL }, // Inst #1552 = MVE_VQRDMLSDHXs32 |
| 8825 | { 1551, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x1040c80ULL }, // Inst #1551 = MVE_VQRDMLSDHXs16 |
| 8826 | { 1550, 7, 1, 4, 1315, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x40c80ULL }, // Inst #1550 = MVE_VQRDMLASH_qrs8 |
| 8827 | { 1549, 7, 1, 4, 1315, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x2040c80ULL }, // Inst #1549 = MVE_VQRDMLASH_qrs32 |
| 8828 | { 1548, 7, 1, 4, 1315, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x1040c80ULL }, // Inst #1548 = MVE_VQRDMLASH_qrs16 |
| 8829 | { 1547, 7, 1, 4, 1315, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x40c80ULL }, // Inst #1547 = MVE_VQRDMLAH_qrs8 |
| 8830 | { 1546, 7, 1, 4, 1315, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x2040c80ULL }, // Inst #1546 = MVE_VQRDMLAH_qrs32 |
| 8831 | { 1545, 7, 1, 4, 1315, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x1040c80ULL }, // Inst #1545 = MVE_VQRDMLAH_qrs16 |
| 8832 | { 1544, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x40c80ULL }, // Inst #1544 = MVE_VQRDMLADHs8 |
| 8833 | { 1543, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1424, 0, 0x2040c80ULL }, // Inst #1543 = MVE_VQRDMLADHs32 |
| 8834 | { 1542, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x1040c80ULL }, // Inst #1542 = MVE_VQRDMLADHs16 |
| 8835 | { 1541, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x40c80ULL }, // Inst #1541 = MVE_VQRDMLADHXs8 |
| 8836 | { 1540, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1424, 0, 0x2040c80ULL }, // Inst #1540 = MVE_VQRDMLADHXs32 |
| 8837 | { 1539, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x1040c80ULL }, // Inst #1539 = MVE_VQRDMLADHXs16 |
| 8838 | { 1538, 6, 1, 4, 1158, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x140c80ULL }, // Inst #1538 = MVE_VQNEGs8 |
| 8839 | { 1537, 6, 1, 4, 1158, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1537 = MVE_VQNEGs32 |
| 8840 | { 1536, 6, 1, 4, 1158, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1536 = MVE_VQNEGs16 |
| 8841 | { 1535, 6, 1, 4, 1157, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x2340c80ULL }, // Inst #1535 = MVE_VQMOVUNs32th |
| 8842 | { 1534, 6, 1, 4, 1157, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x2340c80ULL }, // Inst #1534 = MVE_VQMOVUNs32bh |
| 8843 | { 1533, 6, 1, 4, 1157, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x1340c80ULL }, // Inst #1533 = MVE_VQMOVUNs16th |
| 8844 | { 1532, 6, 1, 4, 1157, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x1340c80ULL }, // Inst #1532 = MVE_VQMOVUNs16bh |
| 8845 | { 1531, 6, 1, 4, 1157, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x2340c80ULL }, // Inst #1531 = MVE_VQMOVNu32th |
| 8846 | { 1530, 6, 1, 4, 1157, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x2340c80ULL }, // Inst #1530 = MVE_VQMOVNu32bh |
| 8847 | { 1529, 6, 1, 4, 1157, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x1340c80ULL }, // Inst #1529 = MVE_VQMOVNu16th |
| 8848 | { 1528, 6, 1, 4, 1157, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x1340c80ULL }, // Inst #1528 = MVE_VQMOVNu16bh |
| 8849 | { 1527, 6, 1, 4, 1157, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x2340c80ULL }, // Inst #1527 = MVE_VQMOVNs32th |
| 8850 | { 1526, 6, 1, 4, 1157, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x2340c80ULL }, // Inst #1526 = MVE_VQMOVNs32bh |
| 8851 | { 1525, 6, 1, 4, 1157, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x1340c80ULL }, // Inst #1525 = MVE_VQMOVNs16th |
| 8852 | { 1524, 6, 1, 4, 1157, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x1340c80ULL }, // Inst #1524 = MVE_VQMOVNs16bh |
| 8853 | { 1523, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1398, 0, 0x2940c80ULL }, // Inst #1523 = MVE_VQDMULLs32th |
| 8854 | { 1522, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1398, 0, 0x2940c80ULL }, // Inst #1522 = MVE_VQDMULLs32bh |
| 8855 | { 1521, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1940c80ULL }, // Inst #1521 = MVE_VQDMULLs16th |
| 8856 | { 1520, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1940c80ULL }, // Inst #1520 = MVE_VQDMULLs16bh |
| 8857 | { 1519, 7, 1, 4, 1197, 0, 0, ARMImpOpBase + 0, 1431, 0, 0x2940c80ULL }, // Inst #1519 = MVE_VQDMULL_qr_s32th |
| 8858 | { 1518, 7, 1, 4, 1197, 0, 0, ARMImpOpBase + 0, 1431, 0, 0x2940c80ULL }, // Inst #1518 = MVE_VQDMULL_qr_s32bh |
| 8859 | { 1517, 7, 1, 4, 1197, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1940c80ULL }, // Inst #1517 = MVE_VQDMULL_qr_s16th |
| 8860 | { 1516, 7, 1, 4, 1197, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1940c80ULL }, // Inst #1516 = MVE_VQDMULL_qr_s16bh |
| 8861 | { 1515, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1515 = MVE_VQDMULHi8 |
| 8862 | { 1514, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1514 = MVE_VQDMULHi32 |
| 8863 | { 1513, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1513 = MVE_VQDMULHi16 |
| 8864 | { 1512, 7, 1, 4, 1313, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1512 = MVE_VQDMULH_qr_s8 |
| 8865 | { 1511, 7, 1, 4, 1313, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1511 = MVE_VQDMULH_qr_s32 |
| 8866 | { 1510, 7, 1, 4, 1313, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1510 = MVE_VQDMULH_qr_s16 |
| 8867 | { 1509, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x40c80ULL }, // Inst #1509 = MVE_VQDMLSDHs8 |
| 8868 | { 1508, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1424, 0, 0x2040c80ULL }, // Inst #1508 = MVE_VQDMLSDHs32 |
| 8869 | { 1507, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x1040c80ULL }, // Inst #1507 = MVE_VQDMLSDHs16 |
| 8870 | { 1506, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x40c80ULL }, // Inst #1506 = MVE_VQDMLSDHXs8 |
| 8871 | { 1505, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1424, 0, 0x2040c80ULL }, // Inst #1505 = MVE_VQDMLSDHXs32 |
| 8872 | { 1504, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x1040c80ULL }, // Inst #1504 = MVE_VQDMLSDHXs16 |
| 8873 | { 1503, 7, 1, 4, 1315, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x40c80ULL }, // Inst #1503 = MVE_VQDMLASH_qrs8 |
| 8874 | { 1502, 7, 1, 4, 1315, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x2040c80ULL }, // Inst #1502 = MVE_VQDMLASH_qrs32 |
| 8875 | { 1501, 7, 1, 4, 1315, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x1040c80ULL }, // Inst #1501 = MVE_VQDMLASH_qrs16 |
| 8876 | { 1500, 7, 1, 4, 1315, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x40c80ULL }, // Inst #1500 = MVE_VQDMLAH_qrs8 |
| 8877 | { 1499, 7, 1, 4, 1315, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x2040c80ULL }, // Inst #1499 = MVE_VQDMLAH_qrs32 |
| 8878 | { 1498, 7, 1, 4, 1315, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x1040c80ULL }, // Inst #1498 = MVE_VQDMLAH_qrs16 |
| 8879 | { 1497, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x40c80ULL }, // Inst #1497 = MVE_VQDMLADHs8 |
| 8880 | { 1496, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1424, 0, 0x2040c80ULL }, // Inst #1496 = MVE_VQDMLADHs32 |
| 8881 | { 1495, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x1040c80ULL }, // Inst #1495 = MVE_VQDMLADHs16 |
| 8882 | { 1494, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x40c80ULL }, // Inst #1494 = MVE_VQDMLADHXs8 |
| 8883 | { 1493, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1424, 0, 0x2040c80ULL }, // Inst #1493 = MVE_VQDMLADHXs32 |
| 8884 | { 1492, 7, 1, 4, 1316, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x1040c80ULL }, // Inst #1492 = MVE_VQDMLADHXs16 |
| 8885 | { 1491, 7, 1, 4, 1156, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1491 = MVE_VQADDu8 |
| 8886 | { 1490, 7, 1, 4, 1156, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1490 = MVE_VQADDu32 |
| 8887 | { 1489, 7, 1, 4, 1156, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1489 = MVE_VQADDu16 |
| 8888 | { 1488, 7, 1, 4, 1156, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1488 = MVE_VQADDs8 |
| 8889 | { 1487, 7, 1, 4, 1156, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1487 = MVE_VQADDs32 |
| 8890 | { 1486, 7, 1, 4, 1156, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1486 = MVE_VQADDs16 |
| 8891 | { 1485, 7, 1, 4, 1299, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1485 = MVE_VQADD_qr_u8 |
| 8892 | { 1484, 7, 1, 4, 1299, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1484 = MVE_VQADD_qr_u32 |
| 8893 | { 1483, 7, 1, 4, 1299, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1483 = MVE_VQADD_qr_u16 |
| 8894 | { 1482, 7, 1, 4, 1299, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1482 = MVE_VQADD_qr_s8 |
| 8895 | { 1481, 7, 1, 4, 1299, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1481 = MVE_VQADD_qr_s32 |
| 8896 | { 1480, 7, 1, 4, 1299, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1480 = MVE_VQADD_qr_s16 |
| 8897 | { 1479, 6, 1, 4, 1155, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x140c80ULL }, // Inst #1479 = MVE_VQABSs8 |
| 8898 | { 1478, 6, 1, 4, 1155, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1478 = MVE_VQABSs32 |
| 8899 | { 1477, 6, 1, 4, 1155, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1477 = MVE_VQABSs16 |
| 8900 | { 1476, 4, 0, 4, 1323, 0, 1, ARMImpOpBase + 69, 1420, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1476 = MVE_VPTv8u16r |
| 8901 | { 1475, 4, 0, 4, 1181, 0, 1, ARMImpOpBase + 69, 1416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1475 = MVE_VPTv8u16 |
| 8902 | { 1474, 4, 0, 4, 1323, 0, 1, ARMImpOpBase + 69, 1420, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1474 = MVE_VPTv8s16r |
| 8903 | { 1473, 4, 0, 4, 1181, 0, 1, ARMImpOpBase + 69, 1416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1473 = MVE_VPTv8s16 |
| 8904 | { 1472, 4, 0, 4, 1323, 0, 1, ARMImpOpBase + 69, 1420, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1472 = MVE_VPTv8i16r |
| 8905 | { 1471, 4, 0, 4, 1181, 0, 1, ARMImpOpBase + 69, 1416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1471 = MVE_VPTv8i16 |
| 8906 | { 1470, 4, 0, 4, 1322, 0, 1, ARMImpOpBase + 69, 1420, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1470 = MVE_VPTv8f16r |
| 8907 | { 1469, 4, 0, 4, 1182, 0, 1, ARMImpOpBase + 69, 1416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1469 = MVE_VPTv8f16 |
| 8908 | { 1468, 4, 0, 4, 1323, 0, 1, ARMImpOpBase + 69, 1420, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1468 = MVE_VPTv4u32r |
| 8909 | { 1467, 4, 0, 4, 1181, 0, 1, ARMImpOpBase + 69, 1416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1467 = MVE_VPTv4u32 |
| 8910 | { 1466, 4, 0, 4, 1323, 0, 1, ARMImpOpBase + 69, 1420, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1466 = MVE_VPTv4s32r |
| 8911 | { 1465, 4, 0, 4, 1181, 0, 1, ARMImpOpBase + 69, 1416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1465 = MVE_VPTv4s32 |
| 8912 | { 1464, 4, 0, 4, 1323, 0, 1, ARMImpOpBase + 69, 1420, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1464 = MVE_VPTv4i32r |
| 8913 | { 1463, 4, 0, 4, 1181, 0, 1, ARMImpOpBase + 69, 1416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1463 = MVE_VPTv4i32 |
| 8914 | { 1462, 4, 0, 4, 1322, 0, 1, ARMImpOpBase + 69, 1420, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1462 = MVE_VPTv4f32r |
| 8915 | { 1461, 4, 0, 4, 1182, 0, 1, ARMImpOpBase + 69, 1416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1461 = MVE_VPTv4f32 |
| 8916 | { 1460, 4, 0, 4, 1323, 0, 1, ARMImpOpBase + 69, 1420, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1460 = MVE_VPTv16u8r |
| 8917 | { 1459, 4, 0, 4, 1181, 0, 1, ARMImpOpBase + 69, 1416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1459 = MVE_VPTv16u8 |
| 8918 | { 1458, 4, 0, 4, 1323, 0, 1, ARMImpOpBase + 69, 1420, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1458 = MVE_VPTv16s8r |
| 8919 | { 1457, 4, 0, 4, 1181, 0, 1, ARMImpOpBase + 69, 1416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1457 = MVE_VPTv16s8 |
| 8920 | { 1456, 4, 0, 4, 1323, 0, 1, ARMImpOpBase + 69, 1420, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1456 = MVE_VPTv16i8r |
| 8921 | { 1455, 4, 0, 4, 1181, 0, 1, ARMImpOpBase + 69, 1416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1455 = MVE_VPTv16i8 |
| 8922 | { 1454, 1, 0, 4, 1207, 1, 0, ARMImpOpBase + 69, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1454 = MVE_VPST |
| 8923 | { 1453, 6, 1, 4, 1153, 0, 0, ARMImpOpBase + 0, 1410, 0, 0x40c80ULL }, // Inst #1453 = MVE_VPSEL |
| 8924 | { 1452, 5, 1, 4, 1206, 0, 0, ARMImpOpBase + 0, 1405, 0, 0x40c80ULL }, // Inst #1452 = MVE_VPNOT |
| 8925 | { 1451, 6, 1, 4, 1152, 0, 0, ARMImpOpBase + 0, 1173, 0, 0x2140c80ULL }, // Inst #1451 = MVE_VORRimmi32 |
| 8926 | { 1450, 6, 1, 4, 1152, 0, 0, ARMImpOpBase + 0, 1173, 0, 0x1140c80ULL }, // Inst #1450 = MVE_VORRimmi16 |
| 8927 | { 1449, 7, 1, 4, 1152, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1449 = MVE_VORR |
| 8928 | { 1448, 7, 1, 4, 1151, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1448 = MVE_VORN |
| 8929 | { 1447, 6, 1, 4, 1150, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x140c80ULL }, // Inst #1447 = MVE_VNEGs8 |
| 8930 | { 1446, 6, 1, 4, 1150, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1446 = MVE_VNEGs32 |
| 8931 | { 1445, 6, 1, 4, 1150, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1445 = MVE_VNEGs16 |
| 8932 | { 1444, 6, 1, 4, 1200, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1444 = MVE_VNEGf32 |
| 8933 | { 1443, 6, 1, 4, 1200, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1443 = MVE_VNEGf16 |
| 8934 | { 1442, 6, 1, 4, 1149, 0, 0, ARMImpOpBase + 0, 1392, 0|(1ULL<<MCID::Rematerializable), 0x2140c80ULL }, // Inst #1442 = MVE_VMVNimmi32 |
| 8935 | { 1441, 6, 1, 4, 1149, 0, 0, ARMImpOpBase + 0, 1392, 0|(1ULL<<MCID::Rematerializable), 0x1140c80ULL }, // Inst #1441 = MVE_VMVNimmi16 |
| 8936 | { 1440, 6, 1, 4, 1149, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x140c80ULL }, // Inst #1440 = MVE_VMVN |
| 8937 | { 1439, 7, 1, 4, 1319, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1439 = MVE_VMULi8 |
| 8938 | { 1438, 7, 1, 4, 1319, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1438 = MVE_VMULi32 |
| 8939 | { 1437, 7, 1, 4, 1319, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1437 = MVE_VMULi16 |
| 8940 | { 1436, 7, 1, 4, 1194, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1436 = MVE_VMULf32 |
| 8941 | { 1435, 7, 1, 4, 1194, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1435 = MVE_VMULf16 |
| 8942 | { 1434, 7, 1, 4, 1312, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1434 = MVE_VMUL_qr_i8 |
| 8943 | { 1433, 7, 1, 4, 1312, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1433 = MVE_VMUL_qr_i32 |
| 8944 | { 1432, 7, 1, 4, 1312, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1432 = MVE_VMUL_qr_i16 |
| 8945 | { 1431, 7, 1, 4, 1320, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1431 = MVE_VMUL_qr_f32 |
| 8946 | { 1430, 7, 1, 4, 1320, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1430 = MVE_VMUL_qr_f16 |
| 8947 | { 1429, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1940c80ULL }, // Inst #1429 = MVE_VMULLTu8 |
| 8948 | { 1428, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1398, 0, 0x3940c80ULL }, // Inst #1428 = MVE_VMULLTu32 |
| 8949 | { 1427, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2940c80ULL }, // Inst #1427 = MVE_VMULLTu16 |
| 8950 | { 1426, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1940c80ULL }, // Inst #1426 = MVE_VMULLTs8 |
| 8951 | { 1425, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1398, 0, 0x3940c80ULL }, // Inst #1425 = MVE_VMULLTs32 |
| 8952 | { 1424, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2940c80ULL }, // Inst #1424 = MVE_VMULLTs16 |
| 8953 | { 1423, 7, 1, 4, 1148, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1940c80ULL }, // Inst #1423 = MVE_VMULLTp8 |
| 8954 | { 1422, 7, 1, 4, 1148, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2940c80ULL }, // Inst #1422 = MVE_VMULLTp16 |
| 8955 | { 1421, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1940c80ULL }, // Inst #1421 = MVE_VMULLBu8 |
| 8956 | { 1420, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1398, 0, 0x3940c80ULL }, // Inst #1420 = MVE_VMULLBu32 |
| 8957 | { 1419, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2940c80ULL }, // Inst #1419 = MVE_VMULLBu16 |
| 8958 | { 1418, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1940c80ULL }, // Inst #1418 = MVE_VMULLBs8 |
| 8959 | { 1417, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1398, 0, 0x3940c80ULL }, // Inst #1417 = MVE_VMULLBs32 |
| 8960 | { 1416, 7, 1, 4, 1196, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2940c80ULL }, // Inst #1416 = MVE_VMULLBs16 |
| 8961 | { 1415, 7, 1, 4, 1148, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1940c80ULL }, // Inst #1415 = MVE_VMULLBp8 |
| 8962 | { 1414, 7, 1, 4, 1148, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2940c80ULL }, // Inst #1414 = MVE_VMULLBp16 |
| 8963 | { 1413, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1413 = MVE_VMULHu8 |
| 8964 | { 1412, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1412 = MVE_VMULHu32 |
| 8965 | { 1411, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1411 = MVE_VMULHu16 |
| 8966 | { 1410, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1410 = MVE_VMULHs8 |
| 8967 | { 1409, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1409 = MVE_VMULHs32 |
| 8968 | { 1408, 7, 1, 4, 1195, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1408 = MVE_VMULHs16 |
| 8969 | { 1407, 6, 1, 4, 1193, 0, 0, ARMImpOpBase + 0, 1392, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x140c80ULL }, // Inst #1407 = MVE_VMOVimmi8 |
| 8970 | { 1406, 6, 1, 4, 1193, 0, 0, ARMImpOpBase + 0, 1392, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3140c80ULL }, // Inst #1406 = MVE_VMOVimmi64 |
| 8971 | { 1405, 6, 1, 4, 1193, 0, 0, ARMImpOpBase + 0, 1392, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2140c80ULL }, // Inst #1405 = MVE_VMOVimmi32 |
| 8972 | { 1404, 6, 1, 4, 1193, 0, 0, ARMImpOpBase + 0, 1392, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1140c80ULL }, // Inst #1404 = MVE_VMOVimmi16 |
| 8973 | { 1403, 6, 1, 4, 1193, 0, 0, ARMImpOpBase + 0, 1392, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2140c80ULL }, // Inst #1403 = MVE_VMOVimmf32 |
| 8974 | { 1402, 6, 1, 4, 1204, 0, 0, ARMImpOpBase + 0, 1386, 0|(1ULL<<MCID::Predicable), 0x40c80ULL }, // Inst #1402 = MVE_VMOV_to_lane_8 |
| 8975 | { 1401, 6, 1, 4, 1204, 0, 0, ARMImpOpBase + 0, 1386, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::InsertSubreg), 0x2040c80ULL }, // Inst #1401 = MVE_VMOV_to_lane_32 |
| 8976 | { 1400, 6, 1, 4, 1204, 0, 0, ARMImpOpBase + 0, 1386, 0|(1ULL<<MCID::Predicable), 0x1040c80ULL }, // Inst #1400 = MVE_VMOV_to_lane_16 |
| 8977 | { 1399, 7, 2, 4, 1192, 0, 0, ARMImpOpBase + 0, 1379, 0|(1ULL<<MCID::Predicable), 0x2040c80ULL }, // Inst #1399 = MVE_VMOV_rr_q |
| 8978 | { 1398, 8, 1, 4, 1294, 0, 0, ARMImpOpBase + 0, 1371, 0|(1ULL<<MCID::Predicable), 0x2040c80ULL }, // Inst #1398 = MVE_VMOV_q_rr |
| 8979 | { 1397, 5, 1, 4, 1191, 0, 0, ARMImpOpBase + 0, 1366, 0|(1ULL<<MCID::Predicable), 0x40c80ULL }, // Inst #1397 = MVE_VMOV_from_lane_u8 |
| 8980 | { 1396, 5, 1, 4, 1191, 0, 0, ARMImpOpBase + 0, 1366, 0|(1ULL<<MCID::Predicable), 0x1040c80ULL }, // Inst #1396 = MVE_VMOV_from_lane_u16 |
| 8981 | { 1395, 5, 1, 4, 1191, 0, 0, ARMImpOpBase + 0, 1366, 0|(1ULL<<MCID::Predicable), 0x40c80ULL }, // Inst #1395 = MVE_VMOV_from_lane_s8 |
| 8982 | { 1394, 5, 1, 4, 1191, 0, 0, ARMImpOpBase + 0, 1366, 0|(1ULL<<MCID::Predicable), 0x1040c80ULL }, // Inst #1394 = MVE_VMOV_from_lane_s16 |
| 8983 | { 1393, 5, 1, 4, 1191, 0, 0, ARMImpOpBase + 0, 1366, 0|(1ULL<<MCID::Predicable), 0x2040c80ULL }, // Inst #1393 = MVE_VMOV_from_lane_32 |
| 8984 | { 1392, 6, 1, 4, 1146, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x2340c80ULL }, // Inst #1392 = MVE_VMOVNi32th |
| 8985 | { 1391, 6, 1, 4, 1146, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x2340c80ULL }, // Inst #1391 = MVE_VMOVNi32bh |
| 8986 | { 1390, 6, 1, 4, 1146, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x1340c80ULL }, // Inst #1390 = MVE_VMOVNi16th |
| 8987 | { 1389, 6, 1, 4, 1146, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x1340c80ULL }, // Inst #1389 = MVE_VMOVNi16bh |
| 8988 | { 1388, 6, 1, 4, 1147, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1840c80ULL }, // Inst #1388 = MVE_VMOVLu8th |
| 8989 | { 1387, 6, 1, 4, 1147, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1840c80ULL }, // Inst #1387 = MVE_VMOVLu8bh |
| 8990 | { 1386, 6, 1, 4, 1147, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2840c80ULL }, // Inst #1386 = MVE_VMOVLu16th |
| 8991 | { 1385, 6, 1, 4, 1147, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2840c80ULL }, // Inst #1385 = MVE_VMOVLu16bh |
| 8992 | { 1384, 6, 1, 4, 1147, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1840c80ULL }, // Inst #1384 = MVE_VMOVLs8th |
| 8993 | { 1383, 6, 1, 4, 1147, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1840c80ULL }, // Inst #1383 = MVE_VMOVLs8bh |
| 8994 | { 1382, 6, 1, 4, 1147, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2840c80ULL }, // Inst #1382 = MVE_VMOVLs16th |
| 8995 | { 1381, 6, 1, 4, 1147, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2840c80ULL }, // Inst #1381 = MVE_VMOVLs16bh |
| 8996 | { 1380, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x2440c80ULL }, // Inst #1380 = MVE_VMLSLDAVxs32 |
| 8997 | { 1379, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x1440c80ULL }, // Inst #1379 = MVE_VMLSLDAVxs16 |
| 8998 | { 1378, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x2540c80ULL }, // Inst #1378 = MVE_VMLSLDAVs32 |
| 8999 | { 1377, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x1540c80ULL }, // Inst #1377 = MVE_VMLSLDAVs16 |
| 9000 | { 1376, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x2440c80ULL }, // Inst #1376 = MVE_VMLSLDAVaxs32 |
| 9001 | { 1375, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x1440c80ULL }, // Inst #1375 = MVE_VMLSLDAVaxs16 |
| 9002 | { 1374, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x2540c80ULL }, // Inst #1374 = MVE_VMLSLDAVas32 |
| 9003 | { 1373, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x1540c80ULL }, // Inst #1373 = MVE_VMLSLDAVas16 |
| 9004 | { 1372, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x440c80ULL }, // Inst #1372 = MVE_VMLSDAVxs8 |
| 9005 | { 1371, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x2440c80ULL }, // Inst #1371 = MVE_VMLSDAVxs32 |
| 9006 | { 1370, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x1440c80ULL }, // Inst #1370 = MVE_VMLSDAVxs16 |
| 9007 | { 1369, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x540c80ULL }, // Inst #1369 = MVE_VMLSDAVs8 |
| 9008 | { 1368, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x2540c80ULL }, // Inst #1368 = MVE_VMLSDAVs32 |
| 9009 | { 1367, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x1540c80ULL }, // Inst #1367 = MVE_VMLSDAVs16 |
| 9010 | { 1366, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x440c80ULL }, // Inst #1366 = MVE_VMLSDAVaxs8 |
| 9011 | { 1365, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x2440c80ULL }, // Inst #1365 = MVE_VMLSDAVaxs32 |
| 9012 | { 1364, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x1440c80ULL }, // Inst #1364 = MVE_VMLSDAVaxs16 |
| 9013 | { 1363, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x540c80ULL }, // Inst #1363 = MVE_VMLSDAVas8 |
| 9014 | { 1362, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x2540c80ULL }, // Inst #1362 = MVE_VMLSDAVas32 |
| 9015 | { 1361, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x1540c80ULL }, // Inst #1361 = MVE_VMLSDAVas16 |
| 9016 | { 1360, 7, 1, 4, 1314, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x140c80ULL }, // Inst #1360 = MVE_VMLA_qr_i8 |
| 9017 | { 1359, 7, 1, 4, 1314, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x2140c80ULL }, // Inst #1359 = MVE_VMLA_qr_i32 |
| 9018 | { 1358, 7, 1, 4, 1314, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x1140c80ULL }, // Inst #1358 = MVE_VMLA_qr_i16 |
| 9019 | { 1357, 7, 1, 4, 1314, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x140c80ULL }, // Inst #1357 = MVE_VMLAS_qr_i8 |
| 9020 | { 1356, 7, 1, 4, 1314, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x2140c80ULL }, // Inst #1356 = MVE_VMLAS_qr_i32 |
| 9021 | { 1355, 7, 1, 4, 1314, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x1140c80ULL }, // Inst #1355 = MVE_VMLAS_qr_i16 |
| 9022 | { 1354, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x2440c80ULL }, // Inst #1354 = MVE_VMLALDAVxs32 |
| 9023 | { 1353, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x1440c80ULL }, // Inst #1353 = MVE_VMLALDAVxs16 |
| 9024 | { 1352, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x2540c80ULL }, // Inst #1352 = MVE_VMLALDAVu32 |
| 9025 | { 1351, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x1540c80ULL }, // Inst #1351 = MVE_VMLALDAVu16 |
| 9026 | { 1350, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x2540c80ULL }, // Inst #1350 = MVE_VMLALDAVs32 |
| 9027 | { 1349, 7, 2, 4, 1199, 0, 0, ARMImpOpBase + 0, 1359, 0, 0x1540c80ULL }, // Inst #1349 = MVE_VMLALDAVs16 |
| 9028 | { 1348, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x2440c80ULL }, // Inst #1348 = MVE_VMLALDAVaxs32 |
| 9029 | { 1347, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x1440c80ULL }, // Inst #1347 = MVE_VMLALDAVaxs16 |
| 9030 | { 1346, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x2540c80ULL }, // Inst #1346 = MVE_VMLALDAVau32 |
| 9031 | { 1345, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x1540c80ULL }, // Inst #1345 = MVE_VMLALDAVau16 |
| 9032 | { 1344, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x2540c80ULL }, // Inst #1344 = MVE_VMLALDAVas32 |
| 9033 | { 1343, 9, 2, 4, 1317, 0, 0, ARMImpOpBase + 0, 1350, 0, 0x1540c80ULL }, // Inst #1343 = MVE_VMLALDAVas16 |
| 9034 | { 1342, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x440c80ULL }, // Inst #1342 = MVE_VMLADAVxs8 |
| 9035 | { 1341, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x2440c80ULL }, // Inst #1341 = MVE_VMLADAVxs32 |
| 9036 | { 1340, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x1440c80ULL }, // Inst #1340 = MVE_VMLADAVxs16 |
| 9037 | { 1339, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x540c80ULL }, // Inst #1339 = MVE_VMLADAVu8 |
| 9038 | { 1338, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x2540c80ULL }, // Inst #1338 = MVE_VMLADAVu32 |
| 9039 | { 1337, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x1540c80ULL }, // Inst #1337 = MVE_VMLADAVu16 |
| 9040 | { 1336, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x540c80ULL }, // Inst #1336 = MVE_VMLADAVs8 |
| 9041 | { 1335, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x2540c80ULL }, // Inst #1335 = MVE_VMLADAVs32 |
| 9042 | { 1334, 6, 1, 4, 1198, 0, 0, ARMImpOpBase + 0, 1344, 0, 0x1540c80ULL }, // Inst #1334 = MVE_VMLADAVs16 |
| 9043 | { 1333, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x440c80ULL }, // Inst #1333 = MVE_VMLADAVaxs8 |
| 9044 | { 1332, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x2440c80ULL }, // Inst #1332 = MVE_VMLADAVaxs32 |
| 9045 | { 1331, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x1440c80ULL }, // Inst #1331 = MVE_VMLADAVaxs16 |
| 9046 | { 1330, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x540c80ULL }, // Inst #1330 = MVE_VMLADAVau8 |
| 9047 | { 1329, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x2540c80ULL }, // Inst #1329 = MVE_VMLADAVau32 |
| 9048 | { 1328, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x1540c80ULL }, // Inst #1328 = MVE_VMLADAVau16 |
| 9049 | { 1327, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x540c80ULL }, // Inst #1327 = MVE_VMLADAVas8 |
| 9050 | { 1326, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x2540c80ULL }, // Inst #1326 = MVE_VMLADAVas32 |
| 9051 | { 1325, 7, 1, 4, 1318, 0, 0, ARMImpOpBase + 0, 1337, 0, 0x1540c80ULL }, // Inst #1325 = MVE_VMLADAVas16 |
| 9052 | { 1324, 7, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1324 = MVE_VMINu8 |
| 9053 | { 1323, 7, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1323 = MVE_VMINu32 |
| 9054 | { 1322, 7, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1322 = MVE_VMINu16 |
| 9055 | { 1321, 7, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1321 = MVE_VMINs8 |
| 9056 | { 1320, 7, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1320 = MVE_VMINs32 |
| 9057 | { 1319, 7, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1319 = MVE_VMINs16 |
| 9058 | { 1318, 6, 1, 4, 1143, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x440c80ULL }, // Inst #1318 = MVE_VMINVu8 |
| 9059 | { 1317, 6, 1, 4, 1145, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x2440c80ULL }, // Inst #1317 = MVE_VMINVu32 |
| 9060 | { 1316, 6, 1, 4, 1144, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x1440c80ULL }, // Inst #1316 = MVE_VMINVu16 |
| 9061 | { 1315, 6, 1, 4, 1143, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x440c80ULL }, // Inst #1315 = MVE_VMINVs8 |
| 9062 | { 1314, 6, 1, 4, 1145, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x2440c80ULL }, // Inst #1314 = MVE_VMINVs32 |
| 9063 | { 1313, 6, 1, 4, 1144, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x1440c80ULL }, // Inst #1313 = MVE_VMINVs16 |
| 9064 | { 1312, 7, 1, 4, 1309, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1312 = MVE_VMINNMf32 |
| 9065 | { 1311, 7, 1, 4, 1309, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1311 = MVE_VMINNMf16 |
| 9066 | { 1310, 6, 1, 4, 1190, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x2440c80ULL }, // Inst #1310 = MVE_VMINNMVf32 |
| 9067 | { 1309, 6, 1, 4, 1190, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x1440c80ULL }, // Inst #1309 = MVE_VMINNMVf16 |
| 9068 | { 1308, 6, 1, 4, 1309, 0, 0, ARMImpOpBase + 0, 1222, 0|(1ULL<<MCID::Commutable), 0x2140c80ULL }, // Inst #1308 = MVE_VMINNMAf32 |
| 9069 | { 1307, 6, 1, 4, 1309, 0, 0, ARMImpOpBase + 0, 1222, 0|(1ULL<<MCID::Commutable), 0x1140c80ULL }, // Inst #1307 = MVE_VMINNMAf16 |
| 9070 | { 1306, 6, 1, 4, 1190, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x2440c80ULL }, // Inst #1306 = MVE_VMINNMAVf32 |
| 9071 | { 1305, 6, 1, 4, 1190, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x1440c80ULL }, // Inst #1305 = MVE_VMINNMAVf16 |
| 9072 | { 1304, 6, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x140c80ULL }, // Inst #1304 = MVE_VMINAs8 |
| 9073 | { 1303, 6, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x2140c80ULL }, // Inst #1303 = MVE_VMINAs32 |
| 9074 | { 1302, 6, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x1140c80ULL }, // Inst #1302 = MVE_VMINAs16 |
| 9075 | { 1301, 6, 1, 4, 1143, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x440c80ULL }, // Inst #1301 = MVE_VMINAVs8 |
| 9076 | { 1300, 6, 1, 4, 1145, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x2440c80ULL }, // Inst #1300 = MVE_VMINAVs32 |
| 9077 | { 1299, 6, 1, 4, 1144, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x1440c80ULL }, // Inst #1299 = MVE_VMINAVs16 |
| 9078 | { 1298, 7, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1298 = MVE_VMAXu8 |
| 9079 | { 1297, 7, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1297 = MVE_VMAXu32 |
| 9080 | { 1296, 7, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1296 = MVE_VMAXu16 |
| 9081 | { 1295, 7, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1295 = MVE_VMAXs8 |
| 9082 | { 1294, 7, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1294 = MVE_VMAXs32 |
| 9083 | { 1293, 7, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1293 = MVE_VMAXs16 |
| 9084 | { 1292, 6, 1, 4, 1143, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x440c80ULL }, // Inst #1292 = MVE_VMAXVu8 |
| 9085 | { 1291, 6, 1, 4, 1145, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x2440c80ULL }, // Inst #1291 = MVE_VMAXVu32 |
| 9086 | { 1290, 6, 1, 4, 1144, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x1440c80ULL }, // Inst #1290 = MVE_VMAXVu16 |
| 9087 | { 1289, 6, 1, 4, 1143, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x440c80ULL }, // Inst #1289 = MVE_VMAXVs8 |
| 9088 | { 1288, 6, 1, 4, 1145, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x2440c80ULL }, // Inst #1288 = MVE_VMAXVs32 |
| 9089 | { 1287, 6, 1, 4, 1144, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x1440c80ULL }, // Inst #1287 = MVE_VMAXVs16 |
| 9090 | { 1286, 7, 1, 4, 1309, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1286 = MVE_VMAXNMf32 |
| 9091 | { 1285, 7, 1, 4, 1309, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1285 = MVE_VMAXNMf16 |
| 9092 | { 1284, 6, 1, 4, 1190, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x2440c80ULL }, // Inst #1284 = MVE_VMAXNMVf32 |
| 9093 | { 1283, 6, 1, 4, 1190, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x1440c80ULL }, // Inst #1283 = MVE_VMAXNMVf16 |
| 9094 | { 1282, 6, 1, 4, 1309, 0, 0, ARMImpOpBase + 0, 1222, 0|(1ULL<<MCID::Commutable), 0x2140c80ULL }, // Inst #1282 = MVE_VMAXNMAf32 |
| 9095 | { 1281, 6, 1, 4, 1309, 0, 0, ARMImpOpBase + 0, 1222, 0|(1ULL<<MCID::Commutable), 0x1140c80ULL }, // Inst #1281 = MVE_VMAXNMAf16 |
| 9096 | { 1280, 6, 1, 4, 1190, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x2440c80ULL }, // Inst #1280 = MVE_VMAXNMAVf32 |
| 9097 | { 1279, 6, 1, 4, 1190, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x1440c80ULL }, // Inst #1279 = MVE_VMAXNMAVf16 |
| 9098 | { 1278, 6, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x140c80ULL }, // Inst #1278 = MVE_VMAXAs8 |
| 9099 | { 1277, 6, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x2140c80ULL }, // Inst #1277 = MVE_VMAXAs32 |
| 9100 | { 1276, 6, 1, 4, 1142, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x1140c80ULL }, // Inst #1276 = MVE_VMAXAs16 |
| 9101 | { 1275, 6, 1, 4, 1143, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x440c80ULL }, // Inst #1275 = MVE_VMAXAVs8 |
| 9102 | { 1274, 6, 1, 4, 1145, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x2440c80ULL }, // Inst #1274 = MVE_VMAXAVs32 |
| 9103 | { 1273, 6, 1, 4, 1144, 0, 0, ARMImpOpBase + 0, 1331, 0, 0x1440c80ULL }, // Inst #1273 = MVE_VMAXAVs16 |
| 9104 | { 1272, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1272 = MVE_VLDRWU32_rq_u |
| 9105 | { 1271, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1271 = MVE_VLDRWU32_rq |
| 9106 | { 1270, 7, 2, 4, 1118, 0, 0, ARMImpOpBase + 0, 1324, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1270 = MVE_VLDRWU32_qi_pre |
| 9107 | { 1269, 6, 1, 4, 1117, 0, 0, ARMImpOpBase + 0, 1318, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1269 = MVE_VLDRWU32_qi |
| 9108 | { 1268, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1311, 0|(1ULL<<MCID::MayLoad), 0x2140cb5ULL }, // Inst #1268 = MVE_VLDRWU32_pre |
| 9109 | { 1267, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1311, 0|(1ULL<<MCID::MayLoad), 0x2140cd5ULL }, // Inst #1267 = MVE_VLDRWU32_post |
| 9110 | { 1266, 6, 1, 4, 1114, 0, 0, ARMImpOpBase + 0, 1305, 0|(1ULL<<MCID::MayLoad), 0x2140c95ULL }, // Inst #1266 = MVE_VLDRWU32 |
| 9111 | { 1265, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1265 = MVE_VLDRHU32_rq_u |
| 9112 | { 1264, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1264 = MVE_VLDRHU32_rq |
| 9113 | { 1263, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayLoad), 0x2140cb6ULL }, // Inst #1263 = MVE_VLDRHU32_pre |
| 9114 | { 1262, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayLoad), 0x2140cd6ULL }, // Inst #1262 = MVE_VLDRHU32_post |
| 9115 | { 1261, 6, 1, 4, 1114, 0, 0, ARMImpOpBase + 0, 1286, 0|(1ULL<<MCID::MayLoad), 0x2140c96ULL }, // Inst #1261 = MVE_VLDRHU32 |
| 9116 | { 1260, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1260 = MVE_VLDRHU16_rq_u |
| 9117 | { 1259, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1259 = MVE_VLDRHU16_rq |
| 9118 | { 1258, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1311, 0|(1ULL<<MCID::MayLoad), 0x1140cb6ULL }, // Inst #1258 = MVE_VLDRHU16_pre |
| 9119 | { 1257, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1311, 0|(1ULL<<MCID::MayLoad), 0x1140cd6ULL }, // Inst #1257 = MVE_VLDRHU16_post |
| 9120 | { 1256, 6, 1, 4, 1114, 0, 0, ARMImpOpBase + 0, 1305, 0|(1ULL<<MCID::MayLoad), 0x1140c96ULL }, // Inst #1256 = MVE_VLDRHU16 |
| 9121 | { 1255, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1255 = MVE_VLDRHS32_rq_u |
| 9122 | { 1254, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1254 = MVE_VLDRHS32_rq |
| 9123 | { 1253, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayLoad), 0x2140cb6ULL }, // Inst #1253 = MVE_VLDRHS32_pre |
| 9124 | { 1252, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayLoad), 0x2140cd6ULL }, // Inst #1252 = MVE_VLDRHS32_post |
| 9125 | { 1251, 6, 1, 4, 1114, 0, 0, ARMImpOpBase + 0, 1286, 0|(1ULL<<MCID::MayLoad), 0x2140c96ULL }, // Inst #1251 = MVE_VLDRHS32 |
| 9126 | { 1250, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x3140c80ULL }, // Inst #1250 = MVE_VLDRDU64_rq_u |
| 9127 | { 1249, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x3140c80ULL }, // Inst #1249 = MVE_VLDRDU64_rq |
| 9128 | { 1248, 7, 2, 4, 1118, 0, 0, ARMImpOpBase + 0, 1324, 0|(1ULL<<MCID::MayLoad), 0x3140c80ULL }, // Inst #1248 = MVE_VLDRDU64_qi_pre |
| 9129 | { 1247, 6, 1, 4, 1117, 0, 0, ARMImpOpBase + 0, 1318, 0|(1ULL<<MCID::MayLoad), 0x3140c80ULL }, // Inst #1247 = MVE_VLDRDU64_qi |
| 9130 | { 1246, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1246 = MVE_VLDRBU8_rq |
| 9131 | { 1245, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1311, 0|(1ULL<<MCID::MayLoad), 0x140cb7ULL }, // Inst #1245 = MVE_VLDRBU8_pre |
| 9132 | { 1244, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1311, 0|(1ULL<<MCID::MayLoad), 0x140cd7ULL }, // Inst #1244 = MVE_VLDRBU8_post |
| 9133 | { 1243, 6, 1, 4, 1114, 0, 0, ARMImpOpBase + 0, 1305, 0|(1ULL<<MCID::MayLoad), 0x140c97ULL }, // Inst #1243 = MVE_VLDRBU8 |
| 9134 | { 1242, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1242 = MVE_VLDRBU32_rq |
| 9135 | { 1241, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayLoad), 0x2140cb7ULL }, // Inst #1241 = MVE_VLDRBU32_pre |
| 9136 | { 1240, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayLoad), 0x2140cd7ULL }, // Inst #1240 = MVE_VLDRBU32_post |
| 9137 | { 1239, 6, 1, 4, 1114, 0, 0, ARMImpOpBase + 0, 1286, 0|(1ULL<<MCID::MayLoad), 0x2140c97ULL }, // Inst #1239 = MVE_VLDRBU32 |
| 9138 | { 1238, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1238 = MVE_VLDRBU16_rq |
| 9139 | { 1237, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayLoad), 0x1140cb7ULL }, // Inst #1237 = MVE_VLDRBU16_pre |
| 9140 | { 1236, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayLoad), 0x1140cd7ULL }, // Inst #1236 = MVE_VLDRBU16_post |
| 9141 | { 1235, 6, 1, 4, 1114, 0, 0, ARMImpOpBase + 0, 1286, 0|(1ULL<<MCID::MayLoad), 0x1140c97ULL }, // Inst #1235 = MVE_VLDRBU16 |
| 9142 | { 1234, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1234 = MVE_VLDRBS32_rq |
| 9143 | { 1233, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayLoad), 0x2140cb7ULL }, // Inst #1233 = MVE_VLDRBS32_pre |
| 9144 | { 1232, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayLoad), 0x2140cd7ULL }, // Inst #1232 = MVE_VLDRBS32_post |
| 9145 | { 1231, 6, 1, 4, 1114, 0, 0, ARMImpOpBase + 0, 1286, 0|(1ULL<<MCID::MayLoad), 0x2140c97ULL }, // Inst #1231 = MVE_VLDRBS32 |
| 9146 | { 1230, 6, 1, 4, 1116, 0, 0, ARMImpOpBase + 0, 1299, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1230 = MVE_VLDRBS16_rq |
| 9147 | { 1229, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayLoad), 0x1140cb7ULL }, // Inst #1229 = MVE_VLDRBS16_pre |
| 9148 | { 1228, 7, 2, 4, 1115, 0, 0, ARMImpOpBase + 0, 1292, 0|(1ULL<<MCID::MayLoad), 0x1140cd7ULL }, // Inst #1228 = MVE_VLDRBS16_post |
| 9149 | { 1227, 6, 1, 4, 1114, 0, 0, ARMImpOpBase + 0, 1286, 0|(1ULL<<MCID::MayLoad), 0x1140c97ULL }, // Inst #1227 = MVE_VLDRBS16 |
| 9150 | { 1226, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1282, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1226 = MVE_VLD43_8_wb |
| 9151 | { 1225, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1279, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1225 = MVE_VLD43_8 |
| 9152 | { 1224, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1282, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1224 = MVE_VLD43_32_wb |
| 9153 | { 1223, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1279, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1223 = MVE_VLD43_32 |
| 9154 | { 1222, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1282, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1222 = MVE_VLD43_16_wb |
| 9155 | { 1221, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1279, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1221 = MVE_VLD43_16 |
| 9156 | { 1220, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1282, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1220 = MVE_VLD42_8_wb |
| 9157 | { 1219, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1279, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1219 = MVE_VLD42_8 |
| 9158 | { 1218, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1282, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1218 = MVE_VLD42_32_wb |
| 9159 | { 1217, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1279, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1217 = MVE_VLD42_32 |
| 9160 | { 1216, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1282, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1216 = MVE_VLD42_16_wb |
| 9161 | { 1215, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1279, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1215 = MVE_VLD42_16 |
| 9162 | { 1214, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1282, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1214 = MVE_VLD41_8_wb |
| 9163 | { 1213, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1279, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1213 = MVE_VLD41_8 |
| 9164 | { 1212, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1282, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1212 = MVE_VLD41_32_wb |
| 9165 | { 1211, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1279, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1211 = MVE_VLD41_32 |
| 9166 | { 1210, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1282, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1210 = MVE_VLD41_16_wb |
| 9167 | { 1209, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1279, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1209 = MVE_VLD41_16 |
| 9168 | { 1208, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1282, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1208 = MVE_VLD40_8_wb |
| 9169 | { 1207, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1279, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1207 = MVE_VLD40_8 |
| 9170 | { 1206, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1282, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1206 = MVE_VLD40_32_wb |
| 9171 | { 1205, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1279, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1205 = MVE_VLD40_32 |
| 9172 | { 1204, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1282, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1204 = MVE_VLD40_16_wb |
| 9173 | { 1203, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1279, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1203 = MVE_VLD40_16 |
| 9174 | { 1202, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1275, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1202 = MVE_VLD21_8_wb |
| 9175 | { 1201, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1272, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1201 = MVE_VLD21_8 |
| 9176 | { 1200, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1275, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1200 = MVE_VLD21_32_wb |
| 9177 | { 1199, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1272, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1199 = MVE_VLD21_32 |
| 9178 | { 1198, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1275, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1198 = MVE_VLD21_16_wb |
| 9179 | { 1197, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1272, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1197 = MVE_VLD21_16 |
| 9180 | { 1196, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1275, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1196 = MVE_VLD20_8_wb |
| 9181 | { 1195, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1272, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1195 = MVE_VLD20_8 |
| 9182 | { 1194, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1275, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1194 = MVE_VLD20_32_wb |
| 9183 | { 1193, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1272, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1193 = MVE_VLD20_32 |
| 9184 | { 1192, 4, 2, 4, 1120, 0, 0, ARMImpOpBase + 0, 1275, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1192 = MVE_VLD20_16_wb |
| 9185 | { 1191, 3, 1, 4, 1119, 0, 0, ARMImpOpBase + 0, 1272, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1191 = MVE_VLD20_16 |
| 9186 | { 1190, 9, 2, 4, 1305, 0, 0, ARMImpOpBase + 0, 1249, 0, 0x140c80ULL }, // Inst #1190 = MVE_VIWDUPu8 |
| 9187 | { 1189, 9, 2, 4, 1305, 0, 0, ARMImpOpBase + 0, 1249, 0, 0x2140c80ULL }, // Inst #1189 = MVE_VIWDUPu32 |
| 9188 | { 1188, 9, 2, 4, 1305, 0, 0, ARMImpOpBase + 0, 1249, 0, 0x1140c80ULL }, // Inst #1188 = MVE_VIWDUPu16 |
| 9189 | { 1187, 8, 2, 4, 1306, 0, 0, ARMImpOpBase + 0, 1235, 0, 0x140c80ULL }, // Inst #1187 = MVE_VIDUPu8 |
| 9190 | { 1186, 8, 2, 4, 1306, 0, 0, ARMImpOpBase + 0, 1235, 0, 0x2140c80ULL }, // Inst #1186 = MVE_VIDUPu32 |
| 9191 | { 1185, 8, 2, 4, 1306, 0, 0, ARMImpOpBase + 0, 1235, 0, 0x1140c80ULL }, // Inst #1185 = MVE_VIDUPu16 |
| 9192 | { 1184, 7, 1, 4, 1141, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1184 = MVE_VHSUBu8 |
| 9193 | { 1183, 7, 1, 4, 1141, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1183 = MVE_VHSUBu32 |
| 9194 | { 1182, 7, 1, 4, 1141, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1182 = MVE_VHSUBu16 |
| 9195 | { 1181, 7, 1, 4, 1141, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1181 = MVE_VHSUBs8 |
| 9196 | { 1180, 7, 1, 4, 1141, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1180 = MVE_VHSUBs32 |
| 9197 | { 1179, 7, 1, 4, 1141, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1179 = MVE_VHSUBs16 |
| 9198 | { 1178, 7, 1, 4, 1298, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1178 = MVE_VHSUB_qr_u8 |
| 9199 | { 1177, 7, 1, 4, 1298, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1177 = MVE_VHSUB_qr_u32 |
| 9200 | { 1176, 7, 1, 4, 1298, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1176 = MVE_VHSUB_qr_u16 |
| 9201 | { 1175, 7, 1, 4, 1298, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1175 = MVE_VHSUB_qr_s8 |
| 9202 | { 1174, 7, 1, 4, 1298, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1174 = MVE_VHSUB_qr_s32 |
| 9203 | { 1173, 7, 1, 4, 1298, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1173 = MVE_VHSUB_qr_s16 |
| 9204 | { 1172, 8, 1, 4, 1140, 0, 0, ARMImpOpBase + 0, 1179, 0, 0x40c80ULL }, // Inst #1172 = MVE_VHCADDs8 |
| 9205 | { 1171, 8, 1, 4, 1140, 0, 0, ARMImpOpBase + 0, 1187, 0, 0x2040c80ULL }, // Inst #1171 = MVE_VHCADDs32 |
| 9206 | { 1170, 8, 1, 4, 1140, 0, 0, ARMImpOpBase + 0, 1179, 0, 0x1040c80ULL }, // Inst #1170 = MVE_VHCADDs16 |
| 9207 | { 1169, 7, 1, 4, 1139, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1169 = MVE_VHADDu8 |
| 9208 | { 1168, 7, 1, 4, 1139, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1168 = MVE_VHADDu32 |
| 9209 | { 1167, 7, 1, 4, 1139, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1167 = MVE_VHADDu16 |
| 9210 | { 1166, 7, 1, 4, 1139, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1166 = MVE_VHADDs8 |
| 9211 | { 1165, 7, 1, 4, 1139, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1165 = MVE_VHADDs32 |
| 9212 | { 1164, 7, 1, 4, 1139, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1164 = MVE_VHADDs16 |
| 9213 | { 1163, 7, 1, 4, 1297, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1163 = MVE_VHADD_qr_u8 |
| 9214 | { 1162, 7, 1, 4, 1297, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1162 = MVE_VHADD_qr_u32 |
| 9215 | { 1161, 7, 1, 4, 1297, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1161 = MVE_VHADD_qr_u16 |
| 9216 | { 1160, 7, 1, 4, 1297, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1160 = MVE_VHADD_qr_s8 |
| 9217 | { 1159, 7, 1, 4, 1297, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1159 = MVE_VHADD_qr_s32 |
| 9218 | { 1158, 7, 1, 4, 1297, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1158 = MVE_VHADD_qr_s16 |
| 9219 | { 1157, 7, 1, 4, 1189, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x2140c80ULL }, // Inst #1157 = MVE_VFMSf32 |
| 9220 | { 1156, 7, 1, 4, 1189, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x1140c80ULL }, // Inst #1156 = MVE_VFMSf16 |
| 9221 | { 1155, 7, 1, 4, 1189, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x2140c80ULL }, // Inst #1155 = MVE_VFMAf32 |
| 9222 | { 1154, 7, 1, 4, 1189, 0, 0, ARMImpOpBase + 0, 1265, 0, 0x1140c80ULL }, // Inst #1154 = MVE_VFMAf16 |
| 9223 | { 1153, 7, 1, 4, 1321, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x2140c80ULL }, // Inst #1153 = MVE_VFMA_qr_f32 |
| 9224 | { 1152, 7, 1, 4, 1321, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x1140c80ULL }, // Inst #1152 = MVE_VFMA_qr_f16 |
| 9225 | { 1151, 7, 1, 4, 1321, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x2140c80ULL }, // Inst #1151 = MVE_VFMA_qr_Sf32 |
| 9226 | { 1150, 7, 1, 4, 1321, 0, 0, ARMImpOpBase + 0, 1258, 0, 0x1140c80ULL }, // Inst #1150 = MVE_VFMA_qr_Sf16 |
| 9227 | { 1149, 7, 1, 4, 1138, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1149 = MVE_VEOR |
| 9228 | { 1148, 9, 2, 4, 1305, 0, 0, ARMImpOpBase + 0, 1249, 0, 0x140c80ULL }, // Inst #1148 = MVE_VDWDUPu8 |
| 9229 | { 1147, 9, 2, 4, 1305, 0, 0, ARMImpOpBase + 0, 1249, 0, 0x2140c80ULL }, // Inst #1147 = MVE_VDWDUPu32 |
| 9230 | { 1146, 9, 2, 4, 1305, 0, 0, ARMImpOpBase + 0, 1249, 0, 0x1140c80ULL }, // Inst #1146 = MVE_VDWDUPu16 |
| 9231 | { 1145, 6, 1, 4, 1137, 0, 0, ARMImpOpBase + 0, 1243, 0, 0x140c80ULL }, // Inst #1145 = MVE_VDUP8 |
| 9232 | { 1144, 6, 1, 4, 1137, 0, 0, ARMImpOpBase + 0, 1243, 0, 0x2140c80ULL }, // Inst #1144 = MVE_VDUP32 |
| 9233 | { 1143, 6, 1, 4, 1137, 0, 0, ARMImpOpBase + 0, 1243, 0, 0x1140c80ULL }, // Inst #1143 = MVE_VDUP16 |
| 9234 | { 1142, 8, 2, 4, 1306, 0, 0, ARMImpOpBase + 0, 1235, 0, 0x140c80ULL }, // Inst #1142 = MVE_VDDUPu8 |
| 9235 | { 1141, 8, 2, 4, 1306, 0, 0, ARMImpOpBase + 0, 1235, 0, 0x2140c80ULL }, // Inst #1141 = MVE_VDDUPu32 |
| 9236 | { 1140, 8, 2, 4, 1306, 0, 0, ARMImpOpBase + 0, 1235, 0, 0x1140c80ULL }, // Inst #1140 = MVE_VDDUPu16 |
| 9237 | { 1139, 6, 1, 4, 1186, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1139 = MVE_VCVTu32f32z |
| 9238 | { 1138, 6, 1, 4, 1186, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1138 = MVE_VCVTu32f32p |
| 9239 | { 1137, 6, 1, 4, 1186, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1137 = MVE_VCVTu32f32n |
| 9240 | { 1136, 6, 1, 4, 1186, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1136 = MVE_VCVTu32f32m |
| 9241 | { 1135, 6, 1, 4, 1186, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1135 = MVE_VCVTu32f32a |
| 9242 | { 1134, 7, 1, 4, 1186, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2140c80ULL }, // Inst #1134 = MVE_VCVTu32f32_fix |
| 9243 | { 1133, 6, 1, 4, 1185, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1133 = MVE_VCVTu16f16z |
| 9244 | { 1132, 6, 1, 4, 1185, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1132 = MVE_VCVTu16f16p |
| 9245 | { 1131, 6, 1, 4, 1185, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1131 = MVE_VCVTu16f16n |
| 9246 | { 1130, 6, 1, 4, 1185, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1130 = MVE_VCVTu16f16m |
| 9247 | { 1129, 6, 1, 4, 1185, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1129 = MVE_VCVTu16f16a |
| 9248 | { 1128, 7, 1, 4, 1185, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1140c80ULL }, // Inst #1128 = MVE_VCVTu16f16_fix |
| 9249 | { 1127, 6, 1, 4, 1186, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1127 = MVE_VCVTs32f32z |
| 9250 | { 1126, 6, 1, 4, 1186, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1126 = MVE_VCVTs32f32p |
| 9251 | { 1125, 6, 1, 4, 1186, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1125 = MVE_VCVTs32f32n |
| 9252 | { 1124, 6, 1, 4, 1186, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1124 = MVE_VCVTs32f32m |
| 9253 | { 1123, 6, 1, 4, 1186, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1123 = MVE_VCVTs32f32a |
| 9254 | { 1122, 7, 1, 4, 1186, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2140c80ULL }, // Inst #1122 = MVE_VCVTs32f32_fix |
| 9255 | { 1121, 6, 1, 4, 1185, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1121 = MVE_VCVTs16f16z |
| 9256 | { 1120, 6, 1, 4, 1185, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1120 = MVE_VCVTs16f16p |
| 9257 | { 1119, 6, 1, 4, 1185, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1119 = MVE_VCVTs16f16n |
| 9258 | { 1118, 6, 1, 4, 1185, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1118 = MVE_VCVTs16f16m |
| 9259 | { 1117, 6, 1, 4, 1185, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1117 = MVE_VCVTs16f16a |
| 9260 | { 1116, 7, 1, 4, 1185, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1140c80ULL }, // Inst #1116 = MVE_VCVTs16f16_fix |
| 9261 | { 1115, 6, 1, 4, 1184, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1115 = MVE_VCVTf32u32n |
| 9262 | { 1114, 7, 1, 4, 1184, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2140c80ULL }, // Inst #1114 = MVE_VCVTf32u32_fix |
| 9263 | { 1113, 6, 1, 4, 1184, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1113 = MVE_VCVTf32s32n |
| 9264 | { 1112, 7, 1, 4, 1184, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x2140c80ULL }, // Inst #1112 = MVE_VCVTf32s32_fix |
| 9265 | { 1111, 6, 1, 4, 1188, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2240c80ULL }, // Inst #1111 = MVE_VCVTf32f16th |
| 9266 | { 1110, 6, 1, 4, 1188, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2240c80ULL }, // Inst #1110 = MVE_VCVTf32f16bh |
| 9267 | { 1109, 6, 1, 4, 1183, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1109 = MVE_VCVTf16u16n |
| 9268 | { 1108, 7, 1, 4, 1183, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1140c80ULL }, // Inst #1108 = MVE_VCVTf16u16_fix |
| 9269 | { 1107, 6, 1, 4, 1183, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1107 = MVE_VCVTf16s16n |
| 9270 | { 1106, 7, 1, 4, 1183, 0, 0, ARMImpOpBase + 0, 1228, 0, 0x1140c80ULL }, // Inst #1106 = MVE_VCVTf16s16_fix |
| 9271 | { 1105, 6, 1, 4, 1187, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x2240c80ULL }, // Inst #1105 = MVE_VCVTf16f32th |
| 9272 | { 1104, 6, 1, 4, 1187, 0, 0, ARMImpOpBase + 0, 1222, 0, 0x2240c80ULL }, // Inst #1104 = MVE_VCVTf16f32bh |
| 9273 | { 1103, 5, 1, 4, 1205, 0, 0, ARMImpOpBase + 0, 1217, 0|(1ULL<<MCID::Rematerializable), 0x140c80ULL }, // Inst #1103 = MVE_VCTP8 |
| 9274 | { 1102, 5, 1, 4, 1205, 0, 0, ARMImpOpBase + 0, 1217, 0|(1ULL<<MCID::Rematerializable), 0x3140c80ULL }, // Inst #1102 = MVE_VCTP64 |
| 9275 | { 1101, 5, 1, 4, 1205, 0, 0, ARMImpOpBase + 0, 1217, 0|(1ULL<<MCID::Rematerializable), 0x2140c80ULL }, // Inst #1101 = MVE_VCTP32 |
| 9276 | { 1100, 5, 1, 4, 1205, 0, 0, ARMImpOpBase + 0, 1217, 0|(1ULL<<MCID::Rematerializable), 0x1140c80ULL }, // Inst #1100 = MVE_VCTP16 |
| 9277 | { 1099, 8, 1, 4, 1180, 0, 0, ARMImpOpBase + 0, 1187, 0, 0x2040c80ULL }, // Inst #1099 = MVE_VCMULf32 |
| 9278 | { 1098, 8, 1, 4, 1180, 0, 0, ARMImpOpBase + 0, 1179, 0, 0x1040c80ULL }, // Inst #1098 = MVE_VCMULf16 |
| 9279 | { 1097, 7, 1, 4, 1324, 0, 0, ARMImpOpBase + 0, 1210, 0, 0x140c80ULL }, // Inst #1097 = MVE_VCMPu8r |
| 9280 | { 1096, 7, 1, 4, 1181, 0, 0, ARMImpOpBase + 0, 1203, 0, 0x140c80ULL }, // Inst #1096 = MVE_VCMPu8 |
| 9281 | { 1095, 7, 1, 4, 1324, 0, 0, ARMImpOpBase + 0, 1210, 0, 0x2140c80ULL }, // Inst #1095 = MVE_VCMPu32r |
| 9282 | { 1094, 7, 1, 4, 1181, 0, 0, ARMImpOpBase + 0, 1203, 0, 0x2140c80ULL }, // Inst #1094 = MVE_VCMPu32 |
| 9283 | { 1093, 7, 1, 4, 1324, 0, 0, ARMImpOpBase + 0, 1210, 0, 0x1140c80ULL }, // Inst #1093 = MVE_VCMPu16r |
| 9284 | { 1092, 7, 1, 4, 1181, 0, 0, ARMImpOpBase + 0, 1203, 0, 0x1140c80ULL }, // Inst #1092 = MVE_VCMPu16 |
| 9285 | { 1091, 7, 1, 4, 1324, 0, 0, ARMImpOpBase + 0, 1210, 0, 0x140c80ULL }, // Inst #1091 = MVE_VCMPs8r |
| 9286 | { 1090, 7, 1, 4, 1181, 0, 0, ARMImpOpBase + 0, 1203, 0, 0x140c80ULL }, // Inst #1090 = MVE_VCMPs8 |
| 9287 | { 1089, 7, 1, 4, 1324, 0, 0, ARMImpOpBase + 0, 1210, 0, 0x2140c80ULL }, // Inst #1089 = MVE_VCMPs32r |
| 9288 | { 1088, 7, 1, 4, 1181, 0, 0, ARMImpOpBase + 0, 1203, 0, 0x2140c80ULL }, // Inst #1088 = MVE_VCMPs32 |
| 9289 | { 1087, 7, 1, 4, 1324, 0, 0, ARMImpOpBase + 0, 1210, 0, 0x1140c80ULL }, // Inst #1087 = MVE_VCMPs16r |
| 9290 | { 1086, 7, 1, 4, 1181, 0, 0, ARMImpOpBase + 0, 1203, 0, 0x1140c80ULL }, // Inst #1086 = MVE_VCMPs16 |
| 9291 | { 1085, 7, 1, 4, 1324, 0, 0, ARMImpOpBase + 0, 1210, 0, 0x140c80ULL }, // Inst #1085 = MVE_VCMPi8r |
| 9292 | { 1084, 7, 1, 4, 1181, 0, 0, ARMImpOpBase + 0, 1203, 0, 0x140c80ULL }, // Inst #1084 = MVE_VCMPi8 |
| 9293 | { 1083, 7, 1, 4, 1324, 0, 0, ARMImpOpBase + 0, 1210, 0, 0x2140c80ULL }, // Inst #1083 = MVE_VCMPi32r |
| 9294 | { 1082, 7, 1, 4, 1181, 0, 0, ARMImpOpBase + 0, 1203, 0, 0x2140c80ULL }, // Inst #1082 = MVE_VCMPi32 |
| 9295 | { 1081, 7, 1, 4, 1324, 0, 0, ARMImpOpBase + 0, 1210, 0, 0x1140c80ULL }, // Inst #1081 = MVE_VCMPi16r |
| 9296 | { 1080, 7, 1, 4, 1181, 0, 0, ARMImpOpBase + 0, 1203, 0, 0x1140c80ULL }, // Inst #1080 = MVE_VCMPi16 |
| 9297 | { 1079, 7, 1, 4, 1325, 0, 0, ARMImpOpBase + 0, 1210, 0, 0x2140c80ULL }, // Inst #1079 = MVE_VCMPf32r |
| 9298 | { 1078, 7, 1, 4, 1182, 0, 0, ARMImpOpBase + 0, 1203, 0, 0x2140c80ULL }, // Inst #1078 = MVE_VCMPf32 |
| 9299 | { 1077, 7, 1, 4, 1325, 0, 0, ARMImpOpBase + 0, 1210, 0, 0x1140c80ULL }, // Inst #1077 = MVE_VCMPf16r |
| 9300 | { 1076, 7, 1, 4, 1182, 0, 0, ARMImpOpBase + 0, 1203, 0, 0x1140c80ULL }, // Inst #1076 = MVE_VCMPf16 |
| 9301 | { 1075, 8, 1, 4, 1179, 0, 0, ARMImpOpBase + 0, 1195, 0, 0x2040c80ULL }, // Inst #1075 = MVE_VCMLAf32 |
| 9302 | { 1074, 8, 1, 4, 1179, 0, 0, ARMImpOpBase + 0, 1195, 0, 0x1040c80ULL }, // Inst #1074 = MVE_VCMLAf16 |
| 9303 | { 1073, 6, 1, 4, 1136, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x140c80ULL }, // Inst #1073 = MVE_VCLZs8 |
| 9304 | { 1072, 6, 1, 4, 1136, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1072 = MVE_VCLZs32 |
| 9305 | { 1071, 6, 1, 4, 1136, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1071 = MVE_VCLZs16 |
| 9306 | { 1070, 6, 1, 4, 1135, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x140c80ULL }, // Inst #1070 = MVE_VCLSs8 |
| 9307 | { 1069, 6, 1, 4, 1135, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1069 = MVE_VCLSs32 |
| 9308 | { 1068, 6, 1, 4, 1135, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1068 = MVE_VCLSs16 |
| 9309 | { 1067, 8, 1, 4, 1134, 0, 0, ARMImpOpBase + 0, 1179, 0, 0x40c80ULL }, // Inst #1067 = MVE_VCADDi8 |
| 9310 | { 1066, 8, 1, 4, 1134, 0, 0, ARMImpOpBase + 0, 1187, 0, 0x2040c80ULL }, // Inst #1066 = MVE_VCADDi32 |
| 9311 | { 1065, 8, 1, 4, 1134, 0, 0, ARMImpOpBase + 0, 1179, 0, 0x1040c80ULL }, // Inst #1065 = MVE_VCADDi16 |
| 9312 | { 1064, 8, 1, 4, 1178, 0, 0, ARMImpOpBase + 0, 1187, 0, 0x2040c80ULL }, // Inst #1064 = MVE_VCADDf32 |
| 9313 | { 1063, 8, 1, 4, 1178, 0, 0, ARMImpOpBase + 0, 1179, 0, 0x1040c80ULL }, // Inst #1063 = MVE_VCADDf16 |
| 9314 | { 1062, 7, 1, 4, 1133, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1062 = MVE_VBRSR8 |
| 9315 | { 1061, 7, 1, 4, 1133, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1061 = MVE_VBRSR32 |
| 9316 | { 1060, 7, 1, 4, 1133, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1060 = MVE_VBRSR16 |
| 9317 | { 1059, 6, 1, 4, 1132, 0, 0, ARMImpOpBase + 0, 1173, 0, 0x2140c80ULL }, // Inst #1059 = MVE_VBICimmi32 |
| 9318 | { 1058, 6, 1, 4, 1132, 0, 0, ARMImpOpBase + 0, 1173, 0, 0x1140c80ULL }, // Inst #1058 = MVE_VBICimmi16 |
| 9319 | { 1057, 7, 1, 4, 1132, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1057 = MVE_VBIC |
| 9320 | { 1056, 7, 1, 4, 1131, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1056 = MVE_VAND |
| 9321 | { 1055, 7, 1, 4, 1130, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1055 = MVE_VADDi8 |
| 9322 | { 1054, 7, 1, 4, 1130, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1054 = MVE_VADDi32 |
| 9323 | { 1053, 7, 1, 4, 1130, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1053 = MVE_VADDi16 |
| 9324 | { 1052, 7, 1, 4, 1174, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1052 = MVE_VADDf32 |
| 9325 | { 1051, 7, 1, 4, 1174, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1051 = MVE_VADDf16 |
| 9326 | { 1050, 7, 1, 4, 1296, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x140c80ULL }, // Inst #1050 = MVE_VADD_qr_i8 |
| 9327 | { 1049, 7, 1, 4, 1296, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1049 = MVE_VADD_qr_i32 |
| 9328 | { 1048, 7, 1, 4, 1296, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1048 = MVE_VADD_qr_i16 |
| 9329 | { 1047, 7, 1, 4, 1175, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x2140c80ULL }, // Inst #1047 = MVE_VADD_qr_f32 |
| 9330 | { 1046, 7, 1, 4, 1175, 0, 0, ARMImpOpBase + 0, 1166, 0, 0x1140c80ULL }, // Inst #1046 = MVE_VADD_qr_f16 |
| 9331 | { 1045, 5, 1, 4, 1177, 0, 0, ARMImpOpBase + 0, 1161, 0, 0x540c80ULL }, // Inst #1045 = MVE_VADDVu8no_acc |
| 9332 | { 1044, 6, 1, 4, 1311, 0, 0, ARMImpOpBase + 0, 1155, 0, 0x540c80ULL }, // Inst #1044 = MVE_VADDVu8acc |
| 9333 | { 1043, 5, 1, 4, 1177, 0, 0, ARMImpOpBase + 0, 1161, 0, 0x2540c80ULL }, // Inst #1043 = MVE_VADDVu32no_acc |
| 9334 | { 1042, 6, 1, 4, 1311, 0, 0, ARMImpOpBase + 0, 1155, 0, 0x2540c80ULL }, // Inst #1042 = MVE_VADDVu32acc |
| 9335 | { 1041, 5, 1, 4, 1177, 0, 0, ARMImpOpBase + 0, 1161, 0, 0x1540c80ULL }, // Inst #1041 = MVE_VADDVu16no_acc |
| 9336 | { 1040, 6, 1, 4, 1311, 0, 0, ARMImpOpBase + 0, 1155, 0, 0x1540c80ULL }, // Inst #1040 = MVE_VADDVu16acc |
| 9337 | { 1039, 5, 1, 4, 1177, 0, 0, ARMImpOpBase + 0, 1161, 0, 0x540c80ULL }, // Inst #1039 = MVE_VADDVs8no_acc |
| 9338 | { 1038, 6, 1, 4, 1311, 0, 0, ARMImpOpBase + 0, 1155, 0, 0x540c80ULL }, // Inst #1038 = MVE_VADDVs8acc |
| 9339 | { 1037, 5, 1, 4, 1177, 0, 0, ARMImpOpBase + 0, 1161, 0, 0x2540c80ULL }, // Inst #1037 = MVE_VADDVs32no_acc |
| 9340 | { 1036, 6, 1, 4, 1311, 0, 0, ARMImpOpBase + 0, 1155, 0, 0x2540c80ULL }, // Inst #1036 = MVE_VADDVs32acc |
| 9341 | { 1035, 5, 1, 4, 1177, 0, 0, ARMImpOpBase + 0, 1161, 0, 0x1540c80ULL }, // Inst #1035 = MVE_VADDVs16no_acc |
| 9342 | { 1034, 6, 1, 4, 1311, 0, 0, ARMImpOpBase + 0, 1155, 0, 0x1540c80ULL }, // Inst #1034 = MVE_VADDVs16acc |
| 9343 | { 1033, 6, 2, 4, 1176, 0, 0, ARMImpOpBase + 0, 1149, 0, 0x2440c80ULL }, // Inst #1033 = MVE_VADDLVu32no_acc |
| 9344 | { 1032, 8, 2, 4, 1310, 0, 0, ARMImpOpBase + 0, 1141, 0, 0x2440c80ULL }, // Inst #1032 = MVE_VADDLVu32acc |
| 9345 | { 1031, 6, 2, 4, 1176, 0, 0, ARMImpOpBase + 0, 1149, 0, 0x2440c80ULL }, // Inst #1031 = MVE_VADDLVs32no_acc |
| 9346 | { 1030, 8, 2, 4, 1310, 0, 0, ARMImpOpBase + 0, 1141, 0, 0x2440c80ULL }, // Inst #1030 = MVE_VADDLVs32acc |
| 9347 | { 1029, 8, 2, 4, 1129, 0, 0, ARMImpOpBase + 0, 1133, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // Inst #1029 = MVE_VADCI |
| 9348 | { 1028, 9, 2, 4, 1295, 0, 0, ARMImpOpBase + 0, 1124, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // Inst #1028 = MVE_VADC |
| 9349 | { 1027, 6, 1, 4, 1128, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x140c80ULL }, // Inst #1027 = MVE_VABSs8 |
| 9350 | { 1026, 6, 1, 4, 1128, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1026 = MVE_VABSs32 |
| 9351 | { 1025, 6, 1, 4, 1128, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1025 = MVE_VABSs16 |
| 9352 | { 1024, 6, 1, 4, 1173, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x2140c80ULL }, // Inst #1024 = MVE_VABSf32 |
| 9353 | { 1023, 6, 1, 4, 1173, 0, 0, ARMImpOpBase + 0, 1118, 0, 0x1140c80ULL }, // Inst #1023 = MVE_VABSf16 |
| 9354 | { 1022, 7, 1, 4, 1127, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1022 = MVE_VABDu8 |
| 9355 | { 1021, 7, 1, 4, 1127, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1021 = MVE_VABDu32 |
| 9356 | { 1020, 7, 1, 4, 1127, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1020 = MVE_VABDu16 |
| 9357 | { 1019, 7, 1, 4, 1127, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x140c80ULL }, // Inst #1019 = MVE_VABDs8 |
| 9358 | { 1018, 7, 1, 4, 1127, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1018 = MVE_VABDs32 |
| 9359 | { 1017, 7, 1, 4, 1127, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1017 = MVE_VABDs16 |
| 9360 | { 1016, 7, 1, 4, 1172, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x2140c80ULL }, // Inst #1016 = MVE_VABDf32 |
| 9361 | { 1015, 7, 1, 4, 1172, 0, 0, ARMImpOpBase + 0, 1111, 0, 0x1140c80ULL }, // Inst #1015 = MVE_VABDf16 |
| 9362 | { 1014, 7, 1, 4, 1126, 0, 0, ARMImpOpBase + 0, 1104, 0, 0x440c80ULL }, // Inst #1014 = MVE_VABAVu8 |
| 9363 | { 1013, 7, 1, 4, 1126, 0, 0, ARMImpOpBase + 0, 1104, 0, 0x2440c80ULL }, // Inst #1013 = MVE_VABAVu32 |
| 9364 | { 1012, 7, 1, 4, 1126, 0, 0, ARMImpOpBase + 0, 1104, 0, 0x1440c80ULL }, // Inst #1012 = MVE_VABAVu16 |
| 9365 | { 1011, 7, 1, 4, 1126, 0, 0, ARMImpOpBase + 0, 1104, 0, 0x440c80ULL }, // Inst #1011 = MVE_VABAVs8 |
| 9366 | { 1010, 7, 1, 4, 1126, 0, 0, ARMImpOpBase + 0, 1104, 0, 0x2440c80ULL }, // Inst #1010 = MVE_VABAVs32 |
| 9367 | { 1009, 7, 1, 4, 1126, 0, 0, ARMImpOpBase + 0, 1104, 0, 0x1440c80ULL }, // Inst #1009 = MVE_VABAVs16 |
| 9368 | { 1008, 7, 2, 4, 1282, 0, 0, ARMImpOpBase + 0, 1077, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1008 = MVE_URSHRL |
| 9369 | { 1007, 5, 1, 4, 1103, 0, 0, ARMImpOpBase + 0, 467, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1007 = MVE_URSHR |
| 9370 | { 1006, 7, 2, 4, 1282, 0, 0, ARMImpOpBase + 0, 1077, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1006 = MVE_UQSHLL |
| 9371 | { 1005, 5, 1, 4, 1103, 0, 0, ARMImpOpBase + 0, 467, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1005 = MVE_UQSHL |
| 9372 | { 1004, 8, 2, 4, 1104, 0, 0, ARMImpOpBase + 0, 1096, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1004 = MVE_UQRSHLL |
| 9373 | { 1003, 5, 1, 4, 1283, 0, 0, ARMImpOpBase + 0, 1091, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1003 = MVE_UQRSHL |
| 9374 | { 1002, 7, 2, 4, 1282, 0, 0, ARMImpOpBase + 0, 1077, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1002 = MVE_SRSHRL |
| 9375 | { 1001, 5, 1, 4, 1103, 0, 0, ARMImpOpBase + 0, 467, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1001 = MVE_SRSHR |
| 9376 | { 1000, 7, 2, 4, 1282, 0, 0, ARMImpOpBase + 0, 1077, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1000 = MVE_SQSHLL |
| 9377 | { 999, 5, 1, 4, 1103, 0, 0, ARMImpOpBase + 0, 467, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #999 = MVE_SQSHL |
| 9378 | { 998, 8, 2, 4, 1104, 0, 0, ARMImpOpBase + 0, 1096, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #998 = MVE_SQRSHRL |
| 9379 | { 997, 5, 1, 4, 1283, 0, 0, ARMImpOpBase + 0, 1091, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #997 = MVE_SQRSHR |
| 9380 | { 996, 7, 2, 4, 1282, 0, 0, ARMImpOpBase + 0, 1077, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #996 = MVE_LSRL |
| 9381 | { 995, 7, 2, 4, 1104, 0, 0, ARMImpOpBase + 0, 1084, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #995 = MVE_LSLLr |
| 9382 | { 994, 7, 2, 4, 1282, 0, 0, ARMImpOpBase + 0, 1077, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #994 = MVE_LSLLi |
| 9383 | { 993, 3, 1, 4, 1288, 0, 0, ARMImpOpBase + 0, 458, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #993 = MVE_LETP |
| 9384 | { 992, 2, 0, 4, 1285, 0, 0, ARMImpOpBase + 0, 543, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #992 = MVE_LCTP |
| 9385 | { 991, 2, 1, 4, 1286, 0, 0, ARMImpOpBase + 0, 437, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #991 = MVE_DLSTP_8 |
| 9386 | { 990, 2, 1, 4, 1286, 0, 0, ARMImpOpBase + 0, 437, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #990 = MVE_DLSTP_64 |
| 9387 | { 989, 2, 1, 4, 1286, 0, 0, ARMImpOpBase + 0, 437, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #989 = MVE_DLSTP_32 |
| 9388 | { 988, 2, 1, 4, 1286, 0, 0, ARMImpOpBase + 0, 437, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #988 = MVE_DLSTP_16 |
| 9389 | { 987, 7, 2, 4, 1104, 0, 0, ARMImpOpBase + 0, 1084, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #987 = MVE_ASRLr |
| 9390 | { 986, 7, 2, 4, 1282, 0, 0, ARMImpOpBase + 0, 1077, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #986 = MVE_ASRLi |
| 9391 | { 985, 6, 1, 4, 336, 0, 0, ARMImpOpBase + 0, 187, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // Inst #985 = MUL |
| 9392 | { 984, 4, 0, 4, 729, 0, 1, ARMImpOpBase + 0, 1073, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #984 = MSRi |
| 9393 | { 983, 4, 0, 4, 729, 0, 0, ARMImpOpBase + 0, 1069, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #983 = MSRbanked |
| 9394 | { 982, 4, 0, 4, 729, 0, 1, ARMImpOpBase + 0, 1065, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #982 = MSR |
| 9395 | { 981, 3, 1, 4, 728, 0, 0, ARMImpOpBase + 0, 1062, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #981 = MRSsys |
| 9396 | { 980, 4, 1, 4, 728, 0, 0, ARMImpOpBase + 0, 442, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #980 = MRSbanked |
| 9397 | { 979, 3, 1, 4, 728, 0, 0, ARMImpOpBase + 0, 1062, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #979 = MRS |
| 9398 | { 978, 5, 2, 4, 850, 0, 0, ARMImpOpBase + 0, 1057, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #978 = MRRC2 |
| 9399 | { 977, 7, 2, 4, 850, 0, 0, ARMImpOpBase + 0, 1050, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #977 = MRRC |
| 9400 | { 976, 6, 1, 4, 850, 0, 0, ARMImpOpBase + 0, 1044, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #976 = MRC2 |
| 9401 | { 975, 8, 1, 4, 850, 0, 0, ARMImpOpBase + 0, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #975 = MRC |
| 9402 | { 974, 7, 1, 4, 690, 0, 0, ARMImpOpBase + 0, 1029, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2281ULL }, // Inst #974 = MOVsr |
| 9403 | { 973, 6, 1, 4, 326, 0, 0, ARMImpOpBase + 0, 1023, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x3501ULL }, // Inst #973 = MOVsi |
| 9404 | { 972, 5, 1, 4, 868, 0, 0, ARMImpOpBase + 0, 1018, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL }, // Inst #972 = MOVr_TC |
| 9405 | { 971, 5, 1, 4, 868, 0, 0, ARMImpOpBase + 0, 329, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL }, // Inst #971 = MOVr |
| 9406 | { 970, 4, 1, 4, 867, 0, 0, ARMImpOpBase + 0, 243, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL }, // Inst #970 = MOVi16 |
| 9407 | { 969, 5, 1, 4, 867, 0, 0, ARMImpOpBase + 0, 1013, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL }, // Inst #969 = MOVi |
| 9408 | { 968, 5, 1, 4, 693, 0, 0, ARMImpOpBase + 0, 1008, 0|(1ULL<<MCID::Predicable), 0x2201ULL }, // Inst #968 = MOVTi16 |
| 9409 | { 967, 2, 0, 4, 883, 0, 0, ARMImpOpBase + 0, 543, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL }, // Inst #967 = MOVPCLR |
| 9410 | { 966, 6, 1, 4, 337, 0, 0, ARMImpOpBase + 0, 1002, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #966 = MLS |
| 9411 | { 965, 7, 1, 4, 337, 0, 0, ARMImpOpBase + 0, 995, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // Inst #965 = MLA |
| 9412 | { 964, 5, 0, 4, 850, 0, 0, ARMImpOpBase + 0, 990, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #964 = MCRR2 |
| 9413 | { 963, 7, 0, 4, 850, 0, 0, ARMImpOpBase + 0, 983, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #963 = MCRR |
| 9414 | { 962, 6, 0, 4, 850, 0, 0, ARMImpOpBase + 0, 977, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #962 = MCR2 |
| 9415 | { 961, 8, 0, 4, 850, 0, 0, ARMImpOpBase + 0, 969, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #961 = MCR |
| 9416 | { 960, 6, 1, 4, 348, 0, 0, ARMImpOpBase + 0, 963, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL }, // Inst #960 = LDRrs |
| 9417 | { 959, 5, 1, 4, 386, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x312ULL }, // Inst #959 = LDRi12 |
| 9418 | { 958, 5, 1, 4, 398, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x312ULL }, // Inst #958 = LDRcp |
| 9419 | { 957, 7, 2, 4, 913, 0, 0, ARMImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL }, // Inst #957 = LDR_PRE_REG |
| 9420 | { 956, 6, 2, 4, 909, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL }, // Inst #956 = LDR_PRE_IMM |
| 9421 | { 955, 7, 2, 4, 932, 0, 0, ARMImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #955 = LDR_POST_REG |
| 9422 | { 954, 7, 2, 4, 406, 0, 0, ARMImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #954 = LDR_POST_IMM |
| 9423 | { 953, 7, 2, 4, 405, 0, 0, ARMImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #953 = LDRT_POST_REG |
| 9424 | { 952, 7, 2, 4, 924, 0, 0, ARMImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #952 = LDRT_POST_IMM |
| 9425 | { 951, 7, 2, 4, 916, 0, 0, ARMImpOpBase + 0, 956, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL }, // Inst #951 = LDRSH_PRE |
| 9426 | { 950, 7, 2, 4, 931, 0, 0, ARMImpOpBase + 0, 956, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #950 = LDRSH_POST |
| 9427 | { 949, 7, 2, 4, 351, 0, 0, ARMImpOpBase + 0, 949, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #949 = LDRSHTr |
| 9428 | { 948, 6, 2, 4, 927, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #948 = LDRSHTi |
| 9429 | { 947, 6, 1, 4, 349, 0, 0, ARMImpOpBase + 0, 943, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL }, // Inst #947 = LDRSH |
| 9430 | { 946, 7, 2, 4, 916, 0, 0, ARMImpOpBase + 0, 956, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL }, // Inst #946 = LDRSB_PRE |
| 9431 | { 945, 7, 2, 4, 931, 0, 0, ARMImpOpBase + 0, 956, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #945 = LDRSB_POST |
| 9432 | { 944, 7, 2, 4, 351, 0, 0, ARMImpOpBase + 0, 949, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #944 = LDRSBTr |
| 9433 | { 943, 6, 2, 4, 927, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #943 = LDRSBTi |
| 9434 | { 942, 6, 1, 4, 349, 0, 0, ARMImpOpBase + 0, 943, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL }, // Inst #942 = LDRSB |
| 9435 | { 941, 7, 2, 4, 915, 0, 0, ARMImpOpBase + 0, 956, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL }, // Inst #941 = LDRH_PRE |
| 9436 | { 940, 7, 2, 4, 930, 0, 0, ARMImpOpBase + 0, 956, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #940 = LDRH_POST |
| 9437 | { 939, 7, 2, 4, 407, 0, 0, ARMImpOpBase + 0, 949, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #939 = LDRHTr |
| 9438 | { 938, 6, 2, 4, 926, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #938 = LDRHTi |
| 9439 | { 937, 6, 1, 4, 397, 0, 0, ARMImpOpBase + 0, 943, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL }, // Inst #937 = LDRH |
| 9440 | { 936, 4, 1, 4, 849, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #936 = LDREXH |
| 9441 | { 935, 4, 1, 4, 849, 0, 0, ARMImpOpBase + 0, 880, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x580ULL }, // Inst #935 = LDREXD |
| 9442 | { 934, 4, 1, 4, 849, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #934 = LDREXB |
| 9443 | { 933, 4, 1, 4, 849, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #933 = LDREX |
| 9444 | { 932, 8, 3, 4, 922, 0, 0, ARMImpOpBase + 0, 935, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x423ULL }, // Inst #932 = LDRD_PRE |
| 9445 | { 931, 8, 3, 4, 419, 0, 0, ARMImpOpBase + 0, 935, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x443ULL }, // Inst #931 = LDRD_POST |
| 9446 | { 930, 7, 2, 4, 418, 0, 0, ARMImpOpBase + 0, 928, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x403ULL }, // Inst #930 = LDRD |
| 9447 | { 929, 6, 1, 4, 388, 0, 0, ARMImpOpBase + 0, 922, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL }, // Inst #929 = LDRBrs |
| 9448 | { 928, 5, 1, 4, 387, 0, 0, ARMImpOpBase + 0, 917, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x312ULL }, // Inst #928 = LDRBi12 |
| 9449 | { 927, 7, 2, 4, 914, 0, 0, ARMImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL }, // Inst #927 = LDRB_PRE_REG |
| 9450 | { 926, 6, 2, 4, 910, 0, 0, ARMImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL }, // Inst #926 = LDRB_PRE_IMM |
| 9451 | { 925, 7, 2, 4, 933, 0, 0, ARMImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #925 = LDRB_POST_REG |
| 9452 | { 924, 7, 2, 4, 404, 0, 0, ARMImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #924 = LDRB_POST_IMM |
| 9453 | { 923, 7, 2, 4, 403, 0, 0, ARMImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #923 = LDRBT_POST_REG |
| 9454 | { 922, 7, 2, 4, 925, 0, 0, ARMImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #922 = LDRBT_POST_IMM |
| 9455 | { 921, 5, 1, 4, 422, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL }, // Inst #921 = LDMIB_UPD |
| 9456 | { 920, 4, 0, 4, 421, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL }, // Inst #920 = LDMIB |
| 9457 | { 919, 5, 1, 4, 422, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL }, // Inst #919 = LDMIA_UPD |
| 9458 | { 918, 4, 0, 4, 421, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL }, // Inst #918 = LDMIA |
| 9459 | { 917, 5, 1, 4, 422, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL }, // Inst #917 = LDMDB_UPD |
| 9460 | { 916, 4, 0, 4, 421, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL }, // Inst #916 = LDMDB |
| 9461 | { 915, 5, 1, 4, 422, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL }, // Inst #915 = LDMDA_UPD |
| 9462 | { 914, 4, 0, 4, 421, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL }, // Inst #914 = LDMDA |
| 9463 | { 913, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #913 = LDC_PRE |
| 9464 | { 912, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #912 = LDC_POST |
| 9465 | { 911, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 898, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #911 = LDC_OPTION |
| 9466 | { 910, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #910 = LDC_OFFSET |
| 9467 | { 909, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #909 = LDCL_PRE |
| 9468 | { 908, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #908 = LDCL_POST |
| 9469 | { 907, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 898, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #907 = LDCL_OPTION |
| 9470 | { 906, 6, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #906 = LDCL_OFFSET |
| 9471 | { 905, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 884, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #905 = LDC2_PRE |
| 9472 | { 904, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 884, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #904 = LDC2_POST |
| 9473 | { 903, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 888, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #903 = LDC2_OPTION |
| 9474 | { 902, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 884, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #902 = LDC2_OFFSET |
| 9475 | { 901, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 884, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #901 = LDC2L_PRE |
| 9476 | { 900, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 884, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #900 = LDC2L_POST |
| 9477 | { 899, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 888, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #899 = LDC2L_OPTION |
| 9478 | { 898, 4, 0, 4, 847, 0, 0, ARMImpOpBase + 0, 884, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #898 = LDC2L_OFFSET |
| 9479 | { 897, 4, 1, 4, 688, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL }, // Inst #897 = LDAH |
| 9480 | { 896, 4, 1, 4, 688, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #896 = LDAEXH |
| 9481 | { 895, 4, 1, 4, 688, 0, 0, ARMImpOpBase + 0, 880, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x580ULL }, // Inst #895 = LDAEXD |
| 9482 | { 894, 4, 1, 4, 688, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #894 = LDAEXB |
| 9483 | { 893, 4, 1, 4, 688, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #893 = LDAEX |
| 9484 | { 892, 4, 1, 4, 688, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL }, // Inst #892 = LDAB |
| 9485 | { 891, 4, 1, 4, 688, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL }, // Inst #891 = LDA |
| 9486 | { 890, 1, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #890 = ISB |
| 9487 | { 889, 1, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #889 = HVC |
| 9488 | { 888, 1, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #888 = HLT |
| 9489 | { 887, 3, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #887 = HINT |
| 9490 | { 886, 5, 1, 4, 851, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL }, // Inst #886 = FSTMXIA_UPD |
| 9491 | { 885, 4, 0, 4, 851, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b04ULL }, // Inst #885 = FSTMXIA |
| 9492 | { 884, 5, 1, 4, 851, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL }, // Inst #884 = FSTMXDB_UPD |
| 9493 | { 883, 2, 0, 4, 588, 1, 1, ARMImpOpBase + 67, 543, 0|(1ULL<<MCID::Predicable), 0x8c00ULL }, // Inst #883 = FMSTAT |
| 9494 | { 882, 5, 1, 4, 851, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL }, // Inst #882 = FLDMXIA_UPD |
| 9495 | { 881, 4, 0, 4, 851, 0, 0, ARMImpOpBase + 0, 876, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b04ULL }, // Inst #881 = FLDMXIA |
| 9496 | { 880, 5, 1, 4, 851, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL }, // Inst #880 = FLDMXDB_UPD |
| 9497 | { 879, 4, 1, 4, 967, 0, 0, ARMImpOpBase + 0, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x8c00ULL }, // Inst #879 = FCONSTS |
| 9498 | { 878, 4, 1, 4, 966, 0, 0, ARMImpOpBase + 0, 868, 0|(1ULL<<MCID::Rematerializable), 0x8c00ULL }, // Inst #878 = FCONSTH |
| 9499 | { 877, 4, 1, 4, 965, 0, 0, ARMImpOpBase + 0, 864, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x8c00ULL }, // Inst #877 = FCONSTD |
| 9500 | { 876, 2, 0, 4, 1219, 0, 1, ARMImpOpBase + 66, 543, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #876 = ERET |
| 9501 | { 875, 8, 1, 4, 324, 0, 0, ARMImpOpBase + 0, 617, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #875 = EORrsr |
| 9502 | { 874, 7, 1, 4, 323, 0, 0, ARMImpOpBase + 0, 602, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #874 = EORrsi |
| 9503 | { 873, 6, 1, 4, 322, 0, 0, ARMImpOpBase + 0, 596, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #873 = EORrr |
| 9504 | { 872, 6, 1, 4, 321, 0, 0, ARMImpOpBase + 0, 181, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #872 = EORri |
| 9505 | { 871, 1, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #871 = DSB |
| 9506 | { 870, 1, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #870 = DMB |
| 9507 | { 869, 3, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #869 = DBG |
| 9508 | { 868, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 858, 0, 0xd00ULL }, // Inst #868 = CRC32W |
| 9509 | { 867, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 858, 0, 0xd00ULL }, // Inst #867 = CRC32H |
| 9510 | { 866, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 858, 0, 0xd00ULL }, // Inst #866 = CRC32CW |
| 9511 | { 865, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 858, 0, 0xd00ULL }, // Inst #865 = CRC32CH |
| 9512 | { 864, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 858, 0, 0xd00ULL }, // Inst #864 = CRC32CB |
| 9513 | { 863, 3, 1, 4, 702, 0, 0, ARMImpOpBase + 0, 858, 0, 0xd00ULL }, // Inst #863 = CRC32B |
| 9514 | { 862, 3, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 855, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #862 = CPS3p |
| 9515 | { 861, 2, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #861 = CPS2p |
| 9516 | { 860, 1, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #860 = CPS1p |
| 9517 | { 859, 6, 0, 4, 720, 0, 1, ARMImpOpBase + 0, 849, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL }, // Inst #859 = CMPrsr |
| 9518 | { 858, 5, 0, 4, 719, 0, 1, ARMImpOpBase + 0, 844, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL }, // Inst #858 = CMPrsi |
| 9519 | { 857, 4, 0, 4, 718, 0, 1, ARMImpOpBase + 0, 840, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #857 = CMPrr |
| 9520 | { 856, 4, 0, 4, 717, 0, 1, ARMImpOpBase + 0, 243, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #856 = CMPri |
| 9521 | { 855, 6, 0, 4, 720, 0, 1, ARMImpOpBase + 0, 849, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL }, // Inst #855 = CMNzrsr |
| 9522 | { 854, 5, 0, 4, 719, 0, 1, ARMImpOpBase + 0, 844, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL }, // Inst #854 = CMNzrsi |
| 9523 | { 853, 4, 0, 4, 718, 0, 1, ARMImpOpBase + 0, 840, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL }, // Inst #853 = CMNzrr |
| 9524 | { 852, 4, 0, 4, 717, 0, 1, ARMImpOpBase + 0, 243, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #852 = CMNri |
| 9525 | { 851, 4, 1, 4, 695, 0, 0, ARMImpOpBase + 0, 840, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #851 = CLZ |
| 9526 | { 850, 0, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #850 = CLREX |
| 9527 | { 849, 6, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 834, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #849 = CDP2 |
| 9528 | { 848, 8, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 826, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #848 = CDP |
| 9529 | { 847, 9, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 817, 0, 0xc80ULL }, // Inst #847 = CDE_VCX3_vec |
| 9530 | { 846, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 812, 0, 0xc80ULL }, // Inst #846 = CDE_VCX3_fpsp |
| 9531 | { 845, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 807, 0, 0xc80ULL }, // Inst #845 = CDE_VCX3_fpdp |
| 9532 | { 844, 9, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 798, 0, 0xc80ULL }, // Inst #844 = CDE_VCX3A_vec |
| 9533 | { 843, 6, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 792, 0, 0xc80ULL }, // Inst #843 = CDE_VCX3A_fpsp |
| 9534 | { 842, 6, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 786, 0, 0xc80ULL }, // Inst #842 = CDE_VCX3A_fpdp |
| 9535 | { 841, 8, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 778, 0, 0xc80ULL }, // Inst #841 = CDE_VCX2_vec |
| 9536 | { 840, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 774, 0, 0xc80ULL }, // Inst #840 = CDE_VCX2_fpsp |
| 9537 | { 839, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 770, 0, 0xc80ULL }, // Inst #839 = CDE_VCX2_fpdp |
| 9538 | { 838, 8, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 762, 0, 0xc80ULL }, // Inst #838 = CDE_VCX2A_vec |
| 9539 | { 837, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 757, 0, 0xc80ULL }, // Inst #837 = CDE_VCX2A_fpsp |
| 9540 | { 836, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 752, 0, 0xc80ULL }, // Inst #836 = CDE_VCX2A_fpdp |
| 9541 | { 835, 7, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 745, 0, 0xc80ULL }, // Inst #835 = CDE_VCX1_vec |
| 9542 | { 834, 3, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 742, 0, 0xc80ULL }, // Inst #834 = CDE_VCX1_fpsp |
| 9543 | { 833, 3, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 739, 0, 0xc80ULL }, // Inst #833 = CDE_VCX1_fpdp |
| 9544 | { 832, 7, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 732, 0, 0xc80ULL }, // Inst #832 = CDE_VCX1A_vec |
| 9545 | { 831, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 728, 0, 0xc80ULL }, // Inst #831 = CDE_VCX1A_fpsp |
| 9546 | { 830, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 724, 0, 0xc80ULL }, // Inst #830 = CDE_VCX1A_fpdp |
| 9547 | { 829, 8, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 716, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #829 = CDE_CX3DA |
| 9548 | { 828, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 711, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #828 = CDE_CX3D |
| 9549 | { 827, 8, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 703, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #827 = CDE_CX3A |
| 9550 | { 826, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 698, 0, 0xc80ULL }, // Inst #826 = CDE_CX3 |
| 9551 | { 825, 7, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 691, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #825 = CDE_CX2DA |
| 9552 | { 824, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 687, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #824 = CDE_CX2D |
| 9553 | { 823, 7, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 680, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #823 = CDE_CX2A |
| 9554 | { 822, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 676, 0, 0xc80ULL }, // Inst #822 = CDE_CX2 |
| 9555 | { 821, 6, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 670, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #821 = CDE_CX1DA |
| 9556 | { 820, 3, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 667, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #820 = CDE_CX1D |
| 9557 | { 819, 6, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 661, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #819 = CDE_CX1A |
| 9558 | { 818, 3, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 658, 0, 0xc80ULL }, // Inst #818 = CDE_CX1 |
| 9559 | { 817, 3, 0, 4, 854, 0, 0, ARMImpOpBase + 0, 548, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #817 = Bcc |
| 9560 | { 816, 3, 0, 4, 854, 0, 0, ARMImpOpBase + 0, 538, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // Inst #816 = BX_pred |
| 9561 | { 815, 2, 0, 4, 854, 0, 0, ARMImpOpBase + 0, 543, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL }, // Inst #815 = BX_RET |
| 9562 | { 814, 3, 0, 4, 855, 0, 0, ARMImpOpBase + 0, 538, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #814 = BXJ |
| 9563 | { 813, 1, 0, 4, 854, 0, 0, ARMImpOpBase + 0, 295, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x180ULL }, // Inst #813 = BX |
| 9564 | { 812, 3, 0, 4, 857, 1, 1, ARMImpOpBase + 3, 548, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x100ULL }, // Inst #812 = BL_pred |
| 9565 | { 811, 1, 0, 4, 858, 0, 0, ARMImpOpBase + 0, 193, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // Inst #811 = BLXi |
| 9566 | { 810, 3, 0, 4, 860, 1, 1, ARMImpOpBase + 3, 538, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x180ULL }, // Inst #810 = BLX_pred |
| 9567 | { 809, 1, 0, 4, 860, 1, 1, ARMImpOpBase + 3, 295, 0|(1ULL<<MCID::Call), 0x180ULL }, // Inst #809 = BLX |
| 9568 | { 808, 1, 0, 4, 857, 1, 1, ARMImpOpBase + 3, 193, 0|(1ULL<<MCID::Call), 0x100ULL }, // Inst #808 = BL |
| 9569 | { 807, 1, 0, 4, 844, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #807 = BKPT |
| 9570 | { 806, 8, 1, 4, 324, 0, 0, ARMImpOpBase + 0, 617, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #806 = BICrsr |
| 9571 | { 805, 7, 1, 4, 323, 0, 0, ARMImpOpBase + 0, 602, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #805 = BICrsi |
| 9572 | { 804, 6, 1, 4, 322, 0, 0, ARMImpOpBase + 0, 596, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #804 = BICrr |
| 9573 | { 803, 6, 1, 4, 321, 0, 0, ARMImpOpBase + 0, 181, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #803 = BICri |
| 9574 | { 802, 6, 1, 4, 335, 0, 0, ARMImpOpBase + 0, 652, 0|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #802 = BFI |
| 9575 | { 801, 5, 1, 4, 335, 0, 0, ARMImpOpBase + 0, 267, 0|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #801 = BFC |
| 9576 | { 800, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 411, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #800 = BF16_VCVTT |
| 9577 | { 799, 5, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 411, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #799 = BF16_VCVTB |
| 9578 | { 798, 4, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 648, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #798 = BF16_VCVT |
| 9579 | { 797, 4, 1, 4, 50, 0, 0, ARMImpOpBase + 0, 644, 0, 0x11280ULL }, // Inst #797 = BF16VDOTS_VDOTQ |
| 9580 | { 796, 4, 1, 4, 50, 0, 0, ARMImpOpBase + 0, 640, 0, 0x11280ULL }, // Inst #796 = BF16VDOTS_VDOTD |
| 9581 | { 795, 5, 1, 4, 50, 0, 0, ARMImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #795 = BF16VDOTI_VDOTQ |
| 9582 | { 794, 5, 1, 4, 50, 0, 0, ARMImpOpBase + 0, 630, 0, 0x11280ULL }, // Inst #794 = BF16VDOTI_VDOTD |
| 9583 | { 793, 8, 1, 4, 324, 0, 0, ARMImpOpBase + 0, 617, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #793 = ANDrsr |
| 9584 | { 792, 7, 1, 4, 323, 0, 0, ARMImpOpBase + 0, 602, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #792 = ANDrsi |
| 9585 | { 791, 6, 1, 4, 322, 0, 0, ARMImpOpBase + 0, 596, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #791 = ANDrr |
| 9586 | { 790, 6, 1, 4, 321, 0, 0, ARMImpOpBase + 0, 181, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #790 = ANDri |
| 9587 | { 789, 2, 1, 4, 1011, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #789 = AESMC |
| 9588 | { 788, 2, 1, 4, 1011, 0, 0, ARMImpOpBase + 0, 628, 0, 0x11000ULL }, // Inst #788 = AESIMC |
| 9589 | { 787, 3, 1, 4, 1011, 0, 0, ARMImpOpBase + 0, 625, 0|(1ULL<<MCID::Commutable), 0x11000ULL }, // Inst #787 = AESE |
| 9590 | { 786, 3, 1, 4, 1011, 0, 0, ARMImpOpBase + 0, 625, 0|(1ULL<<MCID::Commutable), 0x11000ULL }, // Inst #786 = AESD |
| 9591 | { 785, 4, 1, 4, 711, 0, 0, ARMImpOpBase + 0, 243, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xd01ULL }, // Inst #785 = ADR |
| 9592 | { 784, 8, 1, 4, 710, 0, 0, ARMImpOpBase + 0, 617, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #784 = ADDrsr |
| 9593 | { 783, 7, 1, 4, 704, 0, 0, ARMImpOpBase + 0, 602, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #783 = ADDrsi |
| 9594 | { 782, 6, 1, 4, 701, 0, 0, ARMImpOpBase + 0, 596, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #782 = ADDrr |
| 9595 | { 781, 6, 1, 4, 694, 0, 0, ARMImpOpBase + 0, 181, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #781 = ADDri |
| 9596 | { 780, 8, 1, 4, 710, 1, 1, ARMImpOpBase + 63, 609, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL }, // Inst #780 = ADCrsr |
| 9597 | { 779, 7, 1, 4, 704, 1, 1, ARMImpOpBase + 63, 602, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL }, // Inst #779 = ADCrsi |
| 9598 | { 778, 6, 1, 4, 701, 1, 1, ARMImpOpBase + 63, 596, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // Inst #778 = ADCrr |
| 9599 | { 777, 6, 1, 4, 694, 1, 1, ARMImpOpBase + 63, 181, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // Inst #777 = ADCri |
| 9600 | { 776, 0, 0, 4, 859, 1, 4, ARMImpOpBase + 55, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #776 = tTPsoft |
| 9601 | { 775, 4, 0, 2, 5, 0, 0, ARMImpOpBase + 0, 592, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #775 = tTBH_JT |
| 9602 | { 774, 4, 0, 2, 5, 0, 0, ARMImpOpBase + 0, 592, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #774 = tTBB_JT |
| 9603 | { 773, 1, 0, 4, 854, 1, 0, ARMImpOpBase + 54, 370, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #773 = tTAILJMPr |
| 9604 | { 772, 3, 0, 4, 854, 1, 0, ARMImpOpBase + 54, 548, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #772 = tTAILJMPdND |
| 9605 | { 771, 3, 0, 4, 854, 1, 0, ARMImpOpBase + 54, 548, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #771 = tTAILJMPd |
| 9606 | { 770, 3, 1, 2, 41, 0, 1, ARMImpOpBase + 0, 521, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #770 = tSUBSrr |
| 9607 | { 769, 3, 1, 2, 42, 0, 1, ARMImpOpBase + 0, 524, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #769 = tSUBSi8 |
| 9608 | { 768, 3, 1, 2, 42, 0, 1, ARMImpOpBase + 0, 524, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #768 = tSUBSi3 |
| 9609 | { 767, 3, 1, 2, 41, 1, 1, ARMImpOpBase + 63, 521, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #767 = tSBCS |
| 9610 | { 766, 2, 1, 2, 41, 0, 1, ARMImpOpBase + 0, 590, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #766 = tRSBS |
| 9611 | { 765, 3, 0, 2, 424, 0, 0, ARMImpOpBase + 0, 587, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #765 = tPOP_RET |
| 9612 | { 764, 2, 1, 16, 872, 0, 1, ARMImpOpBase + 0, 446, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #764 = tMOVi32imm |
| 9613 | { 763, 5, 1, 0, 872, 0, 0, ARMImpOpBase + 0, 582, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #763 = tMOVCCr_pseudo |
| 9614 | { 762, 3, 1, 2, 1245, 0, 1, ARMImpOpBase + 0, 524, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #762 = tLSLSri |
| 9615 | { 761, 4, 1, 2, 42, 0, 0, ARMImpOpBase + 0, 578, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #761 = tLEApcrelJT |
| 9616 | { 760, 4, 1, 2, 42, 0, 0, ARMImpOpBase + 0, 578, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #760 = tLEApcrel |
| 9617 | { 759, 3, 1, 0, 394, 0, 0, ARMImpOpBase + 0, 575, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #759 = tLDRpci_pic |
| 9618 | { 758, 5, 2, 4, 905, 0, 0, ARMImpOpBase + 0, 570, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #758 = tLDR_postidx |
| 9619 | { 757, 2, 1, 0, 1024, 0, 0, ARMImpOpBase + 0, 541, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #757 = tLDRLIT_ga_pcrel |
| 9620 | { 756, 2, 1, 0, 1023, 0, 0, ARMImpOpBase + 0, 541, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #756 = tLDRLIT_ga_abs |
| 9621 | { 755, 4, 0, 4, 1021, 0, 0, ARMImpOpBase + 0, 566, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #755 = tLDRConstPool |
| 9622 | { 754, 5, 1, 2, 1018, 0, 0, ARMImpOpBase + 0, 561, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #754 = tLDMIA_UPD |
| 9623 | { 753, 5, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 551, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #753 = tCMP_SWAP_8 |
| 9624 | { 752, 5, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 556, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #752 = tCMP_SWAP_32 |
| 9625 | { 751, 5, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 551, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #751 = tCMP_SWAP_16 |
| 9626 | { 750, 3, 0, 4, 856, 0, 1, ARMImpOpBase + 65, 548, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #750 = tBfar |
| 9627 | { 749, 3, 0, 2, 854, 0, 0, ARMImpOpBase + 0, 545, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #749 = tBX_RET_vararg |
| 9628 | { 748, 2, 0, 2, 854, 0, 0, ARMImpOpBase + 0, 543, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #748 = tBX_RET |
| 9629 | { 747, 1, 0, 4, 854, 1, 1, ARMImpOpBase + 3, 207, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #747 = tBX_CALL |
| 9630 | { 746, 0, 0, 2, 854, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #746 = tBXNS_RET |
| 9631 | { 745, 2, 0, 2, 862, 0, 0, ARMImpOpBase + 0, 541, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #745 = tBR_JTr |
| 9632 | { 744, 3, 0, 2, 863, 0, 0, ARMImpOpBase + 0, 538, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #744 = tBRIND |
| 9633 | { 743, 4, 0, 4, 5, 1, 1, ARMImpOpBase + 3, 534, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #743 = tBL_PUSHLR |
| 9634 | { 742, 3, 0, 2, 860, 1, 1, ARMImpOpBase + 3, 531, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #742 = tBLXr_noip |
| 9635 | { 741, 1, 0, 0, 5, 1, 1, ARMImpOpBase + 3, 530, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #741 = tBLXNS_CALL |
| 9636 | { 740, 2, 0, 0, 1040, 1, 1, ARMImpOpBase + 1, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #740 = tADJCALLSTACKUP |
| 9637 | { 739, 2, 0, 0, 1040, 1, 1, ARMImpOpBase + 1, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #739 = tADJCALLSTACKDOWN |
| 9638 | { 738, 3, 1, 0, 866, 0, 1, ARMImpOpBase + 0, 527, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #738 = tADDframe |
| 9639 | { 737, 3, 1, 2, 41, 0, 1, ARMImpOpBase + 0, 521, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #737 = tADDSrr |
| 9640 | { 736, 3, 1, 2, 42, 0, 1, ARMImpOpBase + 0, 524, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #736 = tADDSi8 |
| 9641 | { 735, 3, 1, 2, 42, 0, 1, ARMImpOpBase + 0, 524, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #735 = tADDSi3 |
| 9642 | { 734, 3, 1, 2, 41, 1, 1, ARMImpOpBase + 63, 521, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #734 = tADCS |
| 9643 | { 733, 4, 1, 8, 5, 0, 1, ARMImpOpBase + 0, 517, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #733 = t2WhileLoopStartTP |
| 9644 | { 732, 3, 1, 8, 5, 0, 1, ARMImpOpBase + 0, 514, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #732 = t2WhileLoopStartLR |
| 9645 | { 731, 2, 0, 4, 5, 0, 1, ARMImpOpBase + 0, 205, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #731 = t2WhileLoopStart |
| 9646 | { 730, 2, 1, 4, 32, 0, 0, ARMImpOpBase + 0, 437, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #730 = t2WhileLoopSetup |
| 9647 | { 729, 4, 0, 4, 1235, 0, 0, ARMImpOpBase + 0, 230, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #729 = t2TBH_JT |
| 9648 | { 728, 4, 0, 4, 1235, 0, 0, ARMImpOpBase + 0, 230, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #728 = t2TBB_JT |
| 9649 | { 727, 0, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #727 = t2SpeculationBarrierSBEndBB |
| 9650 | { 726, 0, 0, 8, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #726 = t2SpeculationBarrierISBDSBEndBB |
| 9651 | { 725, 6, 1, 4, 1238, 0, 1, ARMImpOpBase + 0, 428, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #725 = t2SUBSrs |
| 9652 | { 724, 5, 1, 4, 1271, 0, 1, ARMImpOpBase + 0, 423, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #724 = t2SUBSrr |
| 9653 | { 723, 5, 1, 4, 1112, 0, 1, ARMImpOpBase + 0, 418, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #723 = t2SUBSri |
| 9654 | { 722, 6, 1, 4, 444, 0, 0, ARMImpOpBase + 0, 508, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #722 = t2STR_preidx |
| 9655 | { 721, 5, 0, 4, 943, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #721 = t2STR_PRE_imm |
| 9656 | { 720, 5, 0, 4, 953, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #720 = t2STR_POST_imm |
| 9657 | { 719, 6, 1, 4, 444, 0, 0, ARMImpOpBase + 0, 508, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #719 = t2STRH_preidx |
| 9658 | { 718, 5, 0, 4, 943, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #718 = t2STRH_PRE_imm |
| 9659 | { 717, 5, 0, 4, 441, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #717 = t2STRH_POST_imm |
| 9660 | { 716, 5, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #716 = t2STRH_OFFSET_imm |
| 9661 | { 715, 6, 1, 4, 444, 0, 0, ARMImpOpBase + 0, 508, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #715 = t2STRB_preidx |
| 9662 | { 714, 5, 0, 4, 943, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #714 = t2STRB_PRE_imm |
| 9663 | { 713, 5, 0, 4, 953, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #713 = t2STRB_POST_imm |
| 9664 | { 712, 5, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #712 = t2STRB_OFFSET_imm |
| 9665 | { 711, 6, 1, 4, 1268, 0, 1, ARMImpOpBase + 0, 502, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #711 = t2RSBSrs |
| 9666 | { 710, 5, 1, 4, 1072, 0, 1, ARMImpOpBase + 0, 497, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #710 = t2RSBSri |
| 9667 | { 709, 5, 1, 4, 697, 0, 0, ARMImpOpBase + 0, 467, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #709 = t2MVNCCi |
| 9668 | { 708, 6, 0, 4, 691, 0, 0, ARMImpOpBase + 0, 487, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #708 = t2MOVsr |
| 9669 | { 707, 5, 0, 4, 714, 0, 0, ARMImpOpBase + 0, 482, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #707 = t2MOVsi |
| 9670 | { 706, 2, 1, 8, 355, 0, 0, ARMImpOpBase + 0, 446, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #706 = t2MOVi32imm |
| 9671 | { 705, 3, 1, 4, 357, 0, 0, ARMImpOpBase + 0, 448, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #705 = t2MOVi16_ga_pcrel |
| 9672 | { 704, 2, 1, 0, 356, 0, 0, ARMImpOpBase + 0, 446, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #704 = t2MOV_ga_pcrel |
| 9673 | { 703, 4, 1, 4, 879, 0, 0, ARMImpOpBase + 0, 493, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #703 = t2MOVTi16_ga_pcrel |
| 9674 | { 702, 6, 0, 4, 1098, 0, 0, ARMImpOpBase + 0, 487, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #702 = t2MOVSsr |
| 9675 | { 701, 5, 0, 4, 1097, 0, 0, ARMImpOpBase + 0, 482, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #701 = t2MOVSsi |
| 9676 | { 700, 6, 1, 4, 877, 0, 0, ARMImpOpBase + 0, 461, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #700 = t2MOVCCror |
| 9677 | { 699, 5, 1, 4, 878, 0, 0, ARMImpOpBase + 0, 477, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Select)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #699 = t2MOVCCr |
| 9678 | { 698, 6, 1, 4, 877, 0, 0, ARMImpOpBase + 0, 461, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #698 = t2MOVCClsr |
| 9679 | { 697, 6, 1, 4, 877, 0, 0, ARMImpOpBase + 0, 461, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #697 = t2MOVCClsl |
| 9680 | { 696, 5, 1, 8, 354, 0, 0, ARMImpOpBase + 0, 472, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #696 = t2MOVCCi32imm |
| 9681 | { 695, 5, 1, 4, 682, 0, 0, ARMImpOpBase + 0, 467, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #695 = t2MOVCCi16 |
| 9682 | { 694, 5, 1, 4, 682, 0, 0, ARMImpOpBase + 0, 467, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #694 = t2MOVCCi |
| 9683 | { 693, 6, 1, 4, 877, 0, 0, ARMImpOpBase + 0, 461, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #693 = t2MOVCCasr |
| 9684 | { 692, 3, 1, 8, 5, 0, 1, ARMImpOpBase + 0, 458, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #692 = t2LoopEndDec |
| 9685 | { 691, 2, 0, 8, 5, 0, 1, ARMImpOpBase + 0, 205, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #691 = t2LoopEnd |
| 9686 | { 690, 3, 1, 4, 1113, 0, 0, ARMImpOpBase + 0, 455, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #690 = t2LoopDec |
| 9687 | { 689, 4, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 451, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #689 = t2LEApcrelJT |
| 9688 | { 688, 4, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 451, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #688 = t2LEApcrel |
| 9689 | { 687, 4, 0, 4, 908, 0, 0, ARMImpOpBase + 0, 243, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #687 = t2LDRpcrel |
| 9690 | { 686, 3, 1, 0, 389, 0, 0, ARMImpOpBase + 0, 448, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #686 = t2LDRpci_pic |
| 9691 | { 685, 5, 0, 4, 917, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #685 = t2LDR_PRE_imm |
| 9692 | { 684, 5, 0, 4, 409, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #684 = t2LDR_POST_imm |
| 9693 | { 683, 4, 0, 4, 399, 0, 0, ARMImpOpBase + 0, 442, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #683 = t2LDRSHpcrel |
| 9694 | { 682, 5, 0, 4, 918, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #682 = t2LDRSH_PRE_imm |
| 9695 | { 681, 5, 0, 4, 414, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #681 = t2LDRSH_POST_imm |
| 9696 | { 680, 5, 0, 4, 1020, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #680 = t2LDRSH_OFFSET_imm |
| 9697 | { 679, 4, 0, 4, 399, 0, 0, ARMImpOpBase + 0, 442, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #679 = t2LDRSBpcrel |
| 9698 | { 678, 5, 0, 4, 918, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #678 = t2LDRSB_PRE_imm |
| 9699 | { 677, 5, 0, 4, 414, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #677 = t2LDRSB_POST_imm |
| 9700 | { 676, 5, 0, 4, 1020, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #676 = t2LDRSB_OFFSET_imm |
| 9701 | { 675, 2, 1, 0, 1022, 0, 0, ARMImpOpBase + 0, 446, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #675 = t2LDRLIT_ga_pcrel |
| 9702 | { 674, 4, 0, 4, 1222, 0, 0, ARMImpOpBase + 0, 442, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #674 = t2LDRHpcrel |
| 9703 | { 673, 5, 0, 4, 1226, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #673 = t2LDRH_PRE_imm |
| 9704 | { 672, 5, 0, 4, 1225, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #672 = t2LDRH_POST_imm |
| 9705 | { 671, 5, 0, 4, 1020, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #671 = t2LDRH_OFFSET_imm |
| 9706 | { 670, 4, 0, 4, 1021, 0, 0, ARMImpOpBase + 0, 243, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #670 = t2LDRConstPool |
| 9707 | { 669, 4, 0, 4, 1222, 0, 0, ARMImpOpBase + 0, 442, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #669 = t2LDRBpcrel |
| 9708 | { 668, 5, 0, 4, 911, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #668 = t2LDRB_PRE_imm |
| 9709 | { 667, 5, 0, 4, 928, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #667 = t2LDRB_POST_imm |
| 9710 | { 666, 5, 0, 4, 1020, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #666 = t2LDRB_OFFSET_imm |
| 9711 | { 665, 5, 1, 4, 1017, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #665 = t2LDMIA_RET |
| 9712 | { 664, 3, 1, 4, 32, 0, 0, ARMImpOpBase + 0, 439, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #664 = t2DoLoopStartTP |
| 9713 | { 663, 2, 1, 4, 32, 0, 0, ARMImpOpBase + 0, 437, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #663 = t2DoLoopStart |
| 9714 | { 662, 3, 0, 0, 6, 0, 0, ARMImpOpBase + 0, 434, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #662 = t2CALL_BTI |
| 9715 | { 661, 3, 0, 4, 863, 0, 0, ARMImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #661 = t2BR_JT |
| 9716 | { 660, 1, 0, 0, 1284, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #660 = t2BF_LabelPseudo |
| 9717 | { 659, 6, 1, 4, 705, 0, 1, ARMImpOpBase + 0, 428, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #659 = t2ADDSrs |
| 9718 | { 658, 5, 1, 4, 1270, 0, 1, ARMImpOpBase + 0, 423, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #658 = t2ADDSrr |
| 9719 | { 657, 5, 1, 4, 1111, 0, 1, ARMImpOpBase + 0, 418, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #657 = t2ADDSri |
| 9720 | { 656, 2, 1, 0, 684, 0, 1, ARMImpOpBase + 0, 416, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #656 = t2ABS |
| 9721 | { 655, 1, 0, 0, 852, 0, 1, ARMImpOpBase + 0, 207, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #655 = WIN__DBZCHK |
| 9722 | { 654, 0, 0, 0, 852, 1, 2, ARMImpOpBase + 60, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #654 = WIN__CHKSTK |
| 9723 | { 653, 6, 0, 4, 839, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #653 = VST4qWB_register_Asm_8 |
| 9724 | { 652, 6, 0, 4, 839, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #652 = VST4qWB_register_Asm_32 |
| 9725 | { 651, 6, 0, 4, 839, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #651 = VST4qWB_register_Asm_16 |
| 9726 | { 650, 5, 0, 4, 839, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #650 = VST4qWB_fixed_Asm_8 |
| 9727 | { 649, 5, 0, 4, 839, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #649 = VST4qWB_fixed_Asm_32 |
| 9728 | { 648, 5, 0, 4, 839, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #648 = VST4qWB_fixed_Asm_16 |
| 9729 | { 647, 5, 0, 4, 831, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #647 = VST4qAsm_8 |
| 9730 | { 646, 5, 0, 4, 831, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #646 = VST4qAsm_32 |
| 9731 | { 645, 5, 0, 4, 831, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #645 = VST4qAsm_16 |
| 9732 | { 644, 6, 0, 4, 839, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #644 = VST4dWB_register_Asm_8 |
| 9733 | { 643, 6, 0, 4, 839, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #643 = VST4dWB_register_Asm_32 |
| 9734 | { 642, 6, 0, 4, 839, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #642 = VST4dWB_register_Asm_16 |
| 9735 | { 641, 5, 0, 4, 839, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #641 = VST4dWB_fixed_Asm_8 |
| 9736 | { 640, 5, 0, 4, 839, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #640 = VST4dWB_fixed_Asm_32 |
| 9737 | { 639, 5, 0, 4, 839, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #639 = VST4dWB_fixed_Asm_16 |
| 9738 | { 638, 5, 0, 4, 831, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #638 = VST4dAsm_8 |
| 9739 | { 637, 5, 0, 4, 831, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #637 = VST4dAsm_32 |
| 9740 | { 636, 5, 0, 4, 831, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #636 = VST4dAsm_16 |
| 9741 | { 635, 7, 0, 4, 843, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #635 = VST4LNqWB_register_Asm_32 |
| 9742 | { 634, 7, 0, 4, 843, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #634 = VST4LNqWB_register_Asm_16 |
| 9743 | { 633, 6, 0, 4, 843, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #633 = VST4LNqWB_fixed_Asm_32 |
| 9744 | { 632, 6, 0, 4, 843, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #632 = VST4LNqWB_fixed_Asm_16 |
| 9745 | { 631, 6, 0, 4, 837, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #631 = VST4LNqAsm_32 |
| 9746 | { 630, 6, 0, 4, 837, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #630 = VST4LNqAsm_16 |
| 9747 | { 629, 7, 0, 4, 841, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #629 = VST4LNdWB_register_Asm_8 |
| 9748 | { 628, 7, 0, 4, 841, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #628 = VST4LNdWB_register_Asm_32 |
| 9749 | { 627, 7, 0, 4, 841, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #627 = VST4LNdWB_register_Asm_16 |
| 9750 | { 626, 6, 0, 4, 841, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #626 = VST4LNdWB_fixed_Asm_8 |
| 9751 | { 625, 6, 0, 4, 841, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #625 = VST4LNdWB_fixed_Asm_32 |
| 9752 | { 624, 6, 0, 4, 841, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #624 = VST4LNdWB_fixed_Asm_16 |
| 9753 | { 623, 6, 0, 4, 834, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #623 = VST4LNdAsm_8 |
| 9754 | { 622, 6, 0, 4, 834, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #622 = VST4LNdAsm_32 |
| 9755 | { 621, 6, 0, 4, 834, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #621 = VST4LNdAsm_16 |
| 9756 | { 620, 6, 0, 4, 825, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #620 = VST3qWB_register_Asm_8 |
| 9757 | { 619, 6, 0, 4, 825, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #619 = VST3qWB_register_Asm_32 |
| 9758 | { 618, 6, 0, 4, 825, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #618 = VST3qWB_register_Asm_16 |
| 9759 | { 617, 5, 0, 4, 825, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #617 = VST3qWB_fixed_Asm_8 |
| 9760 | { 616, 5, 0, 4, 825, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #616 = VST3qWB_fixed_Asm_32 |
| 9761 | { 615, 5, 0, 4, 825, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #615 = VST3qWB_fixed_Asm_16 |
| 9762 | { 614, 5, 0, 4, 818, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #614 = VST3qAsm_8 |
| 9763 | { 613, 5, 0, 4, 818, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #613 = VST3qAsm_32 |
| 9764 | { 612, 5, 0, 4, 818, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #612 = VST3qAsm_16 |
| 9765 | { 611, 6, 0, 4, 825, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #611 = VST3dWB_register_Asm_8 |
| 9766 | { 610, 6, 0, 4, 825, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #610 = VST3dWB_register_Asm_32 |
| 9767 | { 609, 6, 0, 4, 825, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #609 = VST3dWB_register_Asm_16 |
| 9768 | { 608, 5, 0, 4, 825, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #608 = VST3dWB_fixed_Asm_8 |
| 9769 | { 607, 5, 0, 4, 825, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #607 = VST3dWB_fixed_Asm_32 |
| 9770 | { 606, 5, 0, 4, 825, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #606 = VST3dWB_fixed_Asm_16 |
| 9771 | { 605, 5, 0, 4, 818, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #605 = VST3dAsm_8 |
| 9772 | { 604, 5, 0, 4, 818, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #604 = VST3dAsm_32 |
| 9773 | { 603, 5, 0, 4, 818, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #603 = VST3dAsm_16 |
| 9774 | { 602, 7, 0, 4, 829, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #602 = VST3LNqWB_register_Asm_32 |
| 9775 | { 601, 7, 0, 4, 829, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #601 = VST3LNqWB_register_Asm_16 |
| 9776 | { 600, 6, 0, 4, 829, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #600 = VST3LNqWB_fixed_Asm_32 |
| 9777 | { 599, 6, 0, 4, 829, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #599 = VST3LNqWB_fixed_Asm_16 |
| 9778 | { 598, 6, 0, 4, 823, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #598 = VST3LNqAsm_32 |
| 9779 | { 597, 6, 0, 4, 823, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #597 = VST3LNqAsm_16 |
| 9780 | { 596, 7, 0, 4, 827, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #596 = VST3LNdWB_register_Asm_8 |
| 9781 | { 595, 7, 0, 4, 827, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #595 = VST3LNdWB_register_Asm_32 |
| 9782 | { 594, 7, 0, 4, 827, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #594 = VST3LNdWB_register_Asm_16 |
| 9783 | { 593, 6, 0, 4, 827, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #593 = VST3LNdWB_fixed_Asm_8 |
| 9784 | { 592, 6, 0, 4, 827, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #592 = VST3LNdWB_fixed_Asm_32 |
| 9785 | { 591, 6, 0, 4, 827, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #591 = VST3LNdWB_fixed_Asm_16 |
| 9786 | { 590, 6, 0, 4, 821, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #590 = VST3LNdAsm_8 |
| 9787 | { 589, 6, 0, 4, 821, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #589 = VST3LNdAsm_32 |
| 9788 | { 588, 6, 0, 4, 821, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #588 = VST3LNdAsm_16 |
| 9789 | { 587, 7, 0, 4, 816, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #587 = VST2LNqWB_register_Asm_32 |
| 9790 | { 586, 7, 0, 4, 816, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #586 = VST2LNqWB_register_Asm_16 |
| 9791 | { 585, 6, 0, 4, 816, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #585 = VST2LNqWB_fixed_Asm_32 |
| 9792 | { 584, 6, 0, 4, 816, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #584 = VST2LNqWB_fixed_Asm_16 |
| 9793 | { 583, 6, 0, 4, 812, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #583 = VST2LNqAsm_32 |
| 9794 | { 582, 6, 0, 4, 812, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #582 = VST2LNqAsm_16 |
| 9795 | { 581, 7, 0, 4, 814, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #581 = VST2LNdWB_register_Asm_8 |
| 9796 | { 580, 7, 0, 4, 814, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #580 = VST2LNdWB_register_Asm_32 |
| 9797 | { 579, 7, 0, 4, 814, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #579 = VST2LNdWB_register_Asm_16 |
| 9798 | { 578, 6, 0, 4, 814, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #578 = VST2LNdWB_fixed_Asm_8 |
| 9799 | { 577, 6, 0, 4, 814, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #577 = VST2LNdWB_fixed_Asm_32 |
| 9800 | { 576, 6, 0, 4, 814, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #576 = VST2LNdWB_fixed_Asm_16 |
| 9801 | { 575, 6, 0, 4, 809, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #575 = VST2LNdAsm_8 |
| 9802 | { 574, 6, 0, 4, 809, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #574 = VST2LNdAsm_32 |
| 9803 | { 573, 6, 0, 4, 809, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #573 = VST2LNdAsm_16 |
| 9804 | { 572, 7, 0, 4, 806, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #572 = VST1LNdWB_register_Asm_8 |
| 9805 | { 571, 7, 0, 4, 806, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #571 = VST1LNdWB_register_Asm_32 |
| 9806 | { 570, 7, 0, 4, 806, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #570 = VST1LNdWB_register_Asm_16 |
| 9807 | { 569, 6, 0, 4, 806, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #569 = VST1LNdWB_fixed_Asm_8 |
| 9808 | { 568, 6, 0, 4, 806, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #568 = VST1LNdWB_fixed_Asm_32 |
| 9809 | { 567, 6, 0, 4, 806, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #567 = VST1LNdWB_fixed_Asm_16 |
| 9810 | { 566, 6, 0, 4, 803, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #566 = VST1LNdAsm_8 |
| 9811 | { 565, 6, 0, 4, 803, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #565 = VST1LNdAsm_32 |
| 9812 | { 564, 6, 0, 4, 803, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #564 = VST1LNdAsm_16 |
| 9813 | { 563, 5, 1, 0, 570, 0, 0, ARMImpOpBase + 0, 411, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #563 = VMOVScc |
| 9814 | { 562, 1, 1, 4, 1001, 0, 0, ARMImpOpBase + 0, 410, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #562 = VMOVQ0 |
| 9815 | { 561, 5, 1, 0, 968, 0, 0, ARMImpOpBase + 0, 405, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #561 = VMOVHcc |
| 9816 | { 560, 5, 1, 0, 569, 0, 0, ARMImpOpBase + 0, 400, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #560 = VMOVDcc |
| 9817 | { 559, 1, 1, 4, 1057, 0, 0, ARMImpOpBase + 0, 399, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #559 = VMOVD0 |
| 9818 | { 558, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #558 = VLD4qWB_register_Asm_8 |
| 9819 | { 557, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #557 = VLD4qWB_register_Asm_32 |
| 9820 | { 556, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #556 = VLD4qWB_register_Asm_16 |
| 9821 | { 555, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #555 = VLD4qWB_fixed_Asm_8 |
| 9822 | { 554, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #554 = VLD4qWB_fixed_Asm_32 |
| 9823 | { 553, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #553 = VLD4qWB_fixed_Asm_16 |
| 9824 | { 552, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #552 = VLD4qAsm_8 |
| 9825 | { 551, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #551 = VLD4qAsm_32 |
| 9826 | { 550, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #550 = VLD4qAsm_16 |
| 9827 | { 549, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #549 = VLD4dWB_register_Asm_8 |
| 9828 | { 548, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #548 = VLD4dWB_register_Asm_32 |
| 9829 | { 547, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #547 = VLD4dWB_register_Asm_16 |
| 9830 | { 546, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #546 = VLD4dWB_fixed_Asm_8 |
| 9831 | { 545, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #545 = VLD4dWB_fixed_Asm_32 |
| 9832 | { 544, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #544 = VLD4dWB_fixed_Asm_16 |
| 9833 | { 543, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #543 = VLD4dAsm_8 |
| 9834 | { 542, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #542 = VLD4dAsm_32 |
| 9835 | { 541, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #541 = VLD4dAsm_16 |
| 9836 | { 540, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #540 = VLD4LNqWB_register_Asm_32 |
| 9837 | { 539, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #539 = VLD4LNqWB_register_Asm_16 |
| 9838 | { 538, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #538 = VLD4LNqWB_fixed_Asm_32 |
| 9839 | { 537, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #537 = VLD4LNqWB_fixed_Asm_16 |
| 9840 | { 536, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #536 = VLD4LNqAsm_32 |
| 9841 | { 535, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #535 = VLD4LNqAsm_16 |
| 9842 | { 534, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #534 = VLD4LNdWB_register_Asm_8 |
| 9843 | { 533, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #533 = VLD4LNdWB_register_Asm_32 |
| 9844 | { 532, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #532 = VLD4LNdWB_register_Asm_16 |
| 9845 | { 531, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #531 = VLD4LNdWB_fixed_Asm_8 |
| 9846 | { 530, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #530 = VLD4LNdWB_fixed_Asm_32 |
| 9847 | { 529, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #529 = VLD4LNdWB_fixed_Asm_16 |
| 9848 | { 528, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #528 = VLD4LNdAsm_8 |
| 9849 | { 527, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #527 = VLD4LNdAsm_32 |
| 9850 | { 526, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #526 = VLD4LNdAsm_16 |
| 9851 | { 525, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #525 = VLD4DUPqWB_register_Asm_8 |
| 9852 | { 524, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #524 = VLD4DUPqWB_register_Asm_32 |
| 9853 | { 523, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #523 = VLD4DUPqWB_register_Asm_16 |
| 9854 | { 522, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #522 = VLD4DUPqWB_fixed_Asm_8 |
| 9855 | { 521, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #521 = VLD4DUPqWB_fixed_Asm_32 |
| 9856 | { 520, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #520 = VLD4DUPqWB_fixed_Asm_16 |
| 9857 | { 519, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #519 = VLD4DUPqAsm_8 |
| 9858 | { 518, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #518 = VLD4DUPqAsm_32 |
| 9859 | { 517, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #517 = VLD4DUPqAsm_16 |
| 9860 | { 516, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #516 = VLD4DUPdWB_register_Asm_8 |
| 9861 | { 515, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #515 = VLD4DUPdWB_register_Asm_32 |
| 9862 | { 514, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #514 = VLD4DUPdWB_register_Asm_16 |
| 9863 | { 513, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #513 = VLD4DUPdWB_fixed_Asm_8 |
| 9864 | { 512, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #512 = VLD4DUPdWB_fixed_Asm_32 |
| 9865 | { 511, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #511 = VLD4DUPdWB_fixed_Asm_16 |
| 9866 | { 510, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #510 = VLD4DUPdAsm_8 |
| 9867 | { 509, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #509 = VLD4DUPdAsm_32 |
| 9868 | { 508, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #508 = VLD4DUPdAsm_16 |
| 9869 | { 507, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #507 = VLD3qWB_register_Asm_8 |
| 9870 | { 506, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #506 = VLD3qWB_register_Asm_32 |
| 9871 | { 505, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #505 = VLD3qWB_register_Asm_16 |
| 9872 | { 504, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #504 = VLD3qWB_fixed_Asm_8 |
| 9873 | { 503, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #503 = VLD3qWB_fixed_Asm_32 |
| 9874 | { 502, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #502 = VLD3qWB_fixed_Asm_16 |
| 9875 | { 501, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #501 = VLD3qAsm_8 |
| 9876 | { 500, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #500 = VLD3qAsm_32 |
| 9877 | { 499, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #499 = VLD3qAsm_16 |
| 9878 | { 498, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #498 = VLD3dWB_register_Asm_8 |
| 9879 | { 497, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #497 = VLD3dWB_register_Asm_32 |
| 9880 | { 496, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #496 = VLD3dWB_register_Asm_16 |
| 9881 | { 495, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #495 = VLD3dWB_fixed_Asm_8 |
| 9882 | { 494, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #494 = VLD3dWB_fixed_Asm_32 |
| 9883 | { 493, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #493 = VLD3dWB_fixed_Asm_16 |
| 9884 | { 492, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #492 = VLD3dAsm_8 |
| 9885 | { 491, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #491 = VLD3dAsm_32 |
| 9886 | { 490, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #490 = VLD3dAsm_16 |
| 9887 | { 489, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #489 = VLD3LNqWB_register_Asm_32 |
| 9888 | { 488, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #488 = VLD3LNqWB_register_Asm_16 |
| 9889 | { 487, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #487 = VLD3LNqWB_fixed_Asm_32 |
| 9890 | { 486, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #486 = VLD3LNqWB_fixed_Asm_16 |
| 9891 | { 485, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #485 = VLD3LNqAsm_32 |
| 9892 | { 484, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #484 = VLD3LNqAsm_16 |
| 9893 | { 483, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #483 = VLD3LNdWB_register_Asm_8 |
| 9894 | { 482, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #482 = VLD3LNdWB_register_Asm_32 |
| 9895 | { 481, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #481 = VLD3LNdWB_register_Asm_16 |
| 9896 | { 480, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #480 = VLD3LNdWB_fixed_Asm_8 |
| 9897 | { 479, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #479 = VLD3LNdWB_fixed_Asm_32 |
| 9898 | { 478, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #478 = VLD3LNdWB_fixed_Asm_16 |
| 9899 | { 477, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #477 = VLD3LNdAsm_8 |
| 9900 | { 476, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #476 = VLD3LNdAsm_32 |
| 9901 | { 475, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #475 = VLD3LNdAsm_16 |
| 9902 | { 474, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #474 = VLD3DUPqWB_register_Asm_8 |
| 9903 | { 473, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #473 = VLD3DUPqWB_register_Asm_32 |
| 9904 | { 472, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #472 = VLD3DUPqWB_register_Asm_16 |
| 9905 | { 471, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #471 = VLD3DUPqWB_fixed_Asm_8 |
| 9906 | { 470, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #470 = VLD3DUPqWB_fixed_Asm_32 |
| 9907 | { 469, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #469 = VLD3DUPqWB_fixed_Asm_16 |
| 9908 | { 468, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #468 = VLD3DUPqAsm_8 |
| 9909 | { 467, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #467 = VLD3DUPqAsm_32 |
| 9910 | { 466, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #466 = VLD3DUPqAsm_16 |
| 9911 | { 465, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #465 = VLD3DUPdWB_register_Asm_8 |
| 9912 | { 464, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #464 = VLD3DUPdWB_register_Asm_32 |
| 9913 | { 463, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #463 = VLD3DUPdWB_register_Asm_16 |
| 9914 | { 462, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #462 = VLD3DUPdWB_fixed_Asm_8 |
| 9915 | { 461, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #461 = VLD3DUPdWB_fixed_Asm_32 |
| 9916 | { 460, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #460 = VLD3DUPdWB_fixed_Asm_16 |
| 9917 | { 459, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #459 = VLD3DUPdAsm_8 |
| 9918 | { 458, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #458 = VLD3DUPdAsm_32 |
| 9919 | { 457, 5, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #457 = VLD3DUPdAsm_16 |
| 9920 | { 456, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #456 = VLD2LNqWB_register_Asm_32 |
| 9921 | { 455, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #455 = VLD2LNqWB_register_Asm_16 |
| 9922 | { 454, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #454 = VLD2LNqWB_fixed_Asm_32 |
| 9923 | { 453, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #453 = VLD2LNqWB_fixed_Asm_16 |
| 9924 | { 452, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #452 = VLD2LNqAsm_32 |
| 9925 | { 451, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #451 = VLD2LNqAsm_16 |
| 9926 | { 450, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #450 = VLD2LNdWB_register_Asm_8 |
| 9927 | { 449, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #449 = VLD2LNdWB_register_Asm_32 |
| 9928 | { 448, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #448 = VLD2LNdWB_register_Asm_16 |
| 9929 | { 447, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #447 = VLD2LNdWB_fixed_Asm_8 |
| 9930 | { 446, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #446 = VLD2LNdWB_fixed_Asm_32 |
| 9931 | { 445, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #445 = VLD2LNdWB_fixed_Asm_16 |
| 9932 | { 444, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #444 = VLD2LNdAsm_8 |
| 9933 | { 443, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #443 = VLD2LNdAsm_32 |
| 9934 | { 442, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #442 = VLD2LNdAsm_16 |
| 9935 | { 441, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #441 = VLD1LNdWB_register_Asm_8 |
| 9936 | { 440, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #440 = VLD1LNdWB_register_Asm_32 |
| 9937 | { 439, 7, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #439 = VLD1LNdWB_register_Asm_16 |
| 9938 | { 438, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #438 = VLD1LNdWB_fixed_Asm_8 |
| 9939 | { 437, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #437 = VLD1LNdWB_fixed_Asm_32 |
| 9940 | { 436, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #436 = VLD1LNdWB_fixed_Asm_16 |
| 9941 | { 435, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #435 = VLD1LNdAsm_8 |
| 9942 | { 434, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #434 = VLD1LNdAsm_32 |
| 9943 | { 433, 6, 0, 4, 1046, 0, 0, ARMImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #433 = VLD1LNdAsm_16 |
| 9944 | { 432, 7, 2, 4, 338, 0, 0, ARMImpOpBase + 0, 343, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // Inst #432 = UMULLv5 |
| 9945 | { 431, 9, 2, 4, 340, 0, 0, ARMImpOpBase + 0, 334, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // Inst #431 = UMLALv5 |
| 9946 | { 430, 0, 0, 4, 859, 1, 4, ARMImpOpBase + 55, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #430 = TPsoft |
| 9947 | { 429, 2, 0, 0, 854, 1, 0, ARMImpOpBase + 54, 373, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #429 = TCRETURNrinotr12 |
| 9948 | { 428, 2, 0, 0, 854, 1, 0, ARMImpOpBase + 54, 371, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #428 = TCRETURNri |
| 9949 | { 427, 2, 0, 0, 854, 1, 0, ARMImpOpBase + 54, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #427 = TCRETURNdi |
| 9950 | { 426, 1, 0, 4, 854, 1, 0, ARMImpOpBase + 54, 295, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #426 = TAILJMPr4 |
| 9951 | { 425, 1, 0, 4, 854, 1, 0, ARMImpOpBase + 54, 370, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #425 = TAILJMPr |
| 9952 | { 424, 1, 0, 4, 854, 1, 0, ARMImpOpBase + 54, 193, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #424 = TAILJMPd |
| 9953 | { 423, 0, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #423 = SpeculationBarrierSBEndBB |
| 9954 | { 422, 0, 0, 8, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #422 = SpeculationBarrierISBDSBEndBB |
| 9955 | { 421, 7, 1, 4, 4, 0, 1, ARMImpOpBase + 0, 170, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #421 = SUBSrsr |
| 9956 | { 420, 6, 1, 4, 3, 0, 1, ARMImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #420 = SUBSrsi |
| 9957 | { 419, 5, 1, 4, 2, 0, 1, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #419 = SUBSrr |
| 9958 | { 418, 5, 1, 4, 1, 0, 1, ARMImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #418 = SUBSri |
| 9959 | { 417, 3, 0, 4, 853, 0, 0, ARMImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #417 = SUBS_PC_LR |
| 9960 | { 416, 7, 1, 4, 942, 0, 0, ARMImpOpBase + 0, 353, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #416 = STRr_preidx |
| 9961 | { 415, 7, 1, 4, 942, 0, 0, ARMImpOpBase + 0, 353, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #415 = STRi_preidx |
| 9962 | { 414, 4, 0, 4, 956, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #414 = STRT_POST |
| 9963 | { 413, 7, 1, 4, 942, 0, 0, ARMImpOpBase + 0, 360, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #413 = STRH_preidx |
| 9964 | { 412, 7, 1, 4, 942, 0, 0, ARMImpOpBase + 0, 353, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #412 = STRBr_preidx |
| 9965 | { 411, 7, 1, 4, 942, 0, 0, ARMImpOpBase + 0, 353, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #411 = STRBi_preidx |
| 9966 | { 410, 4, 0, 4, 956, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #410 = STRBT_POST |
| 9967 | { 409, 4, 0, 64, 30, 0, 0, ARMImpOpBase + 0, 251, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x3ULL }, // Inst #409 = STOREDUAL |
| 9968 | { 408, 3, 1, 0, 844, 0, 0, ARMImpOpBase + 0, 350, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #408 = SPACE |
| 9969 | { 407, 7, 2, 4, 338, 0, 0, ARMImpOpBase + 0, 343, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // Inst #407 = SMULLv5 |
| 9970 | { 406, 9, 2, 4, 340, 0, 0, ARMImpOpBase + 0, 334, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // Inst #406 = SMLALv5 |
| 9971 | { 405, 2, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #405 = SEH_StackAlloc |
| 9972 | { 404, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #404 = SEH_SaveSP |
| 9973 | { 403, 2, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #403 = SEH_SaveRegs_Ret |
| 9974 | { 402, 2, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #402 = SEH_SaveRegs |
| 9975 | { 401, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #401 = SEH_SaveLR |
| 9976 | { 400, 2, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #400 = SEH_SaveFRegs |
| 9977 | { 399, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #399 = SEH_PrologEnd |
| 9978 | { 398, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #398 = SEH_Nop_Ret |
| 9979 | { 397, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #397 = SEH_Nop |
| 9980 | { 396, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #396 = SEH_EpilogStart |
| 9981 | { 395, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #395 = SEH_EpilogEnd |
| 9982 | { 394, 7, 1, 4, 4, 0, 1, ARMImpOpBase + 0, 170, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #394 = RSBSrsr |
| 9983 | { 393, 6, 1, 4, 3, 0, 1, ARMImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #393 = RSBSrsi |
| 9984 | { 392, 5, 1, 4, 694, 0, 1, ARMImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #392 = RSBSri |
| 9985 | { 391, 5, 0, 4, 721, 0, 0, ARMImpOpBase + 0, 329, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #391 = RRXi |
| 9986 | { 390, 2, 1, 0, 723, 1, 0, ARMImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo), 0x2000ULL }, // Inst #390 = RRX |
| 9987 | { 389, 6, 0, 4, 716, 0, 0, ARMImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #389 = RORr |
| 9988 | { 388, 6, 0, 4, 715, 0, 0, ARMImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #388 = RORi |
| 9989 | { 387, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 328, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #387 = PseudoARMInitUndefSPR |
| 9990 | { 386, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 327, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #386 = PseudoARMInitUndefMQPR |
| 9991 | { 385, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 295, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #385 = PseudoARMInitUndefGPR |
| 9992 | { 384, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 326, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #384 = PseudoARMInitUndefDPR_VFP2 |
| 9993 | { 383, 5, 0, 4, 938, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #383 = PICSTRH |
| 9994 | { 382, 5, 0, 4, 938, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #382 = PICSTRB |
| 9995 | { 381, 5, 0, 4, 426, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #381 = PICSTR |
| 9996 | { 380, 5, 1, 4, 904, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #380 = PICLDRSH |
| 9997 | { 379, 5, 1, 4, 904, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #379 = PICLDRSB |
| 9998 | { 378, 5, 1, 4, 903, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #378 = PICLDRH |
| 9999 | { 377, 5, 1, 4, 903, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #377 = PICLDRB |
| 10000 | { 376, 5, 1, 4, 347, 0, 0, ARMImpOpBase + 0, 321, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #376 = PICLDR |
| 10001 | { 375, 5, 1, 4, 23, 0, 0, ARMImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #375 = PICADD |
| 10002 | { 374, 5, 1, 4, 869, 0, 0, ARMImpOpBase + 0, 267, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #374 = MVNCCi |
| 10003 | { 373, 3, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #373 = MVE_MEMSETLOOPINST |
| 10004 | { 372, 3, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 315, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #372 = MVE_MEMCPYLOOPINST |
| 10005 | { 371, 6, 1, 4, 336, 0, 0, ARMImpOpBase + 0, 309, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // Inst #371 = MULv5 |
| 10006 | { 370, 2, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 307, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #370 = MQQQQPRStore |
| 10007 | { 369, 2, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 307, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #369 = MQQQQPRLoad |
| 10008 | { 368, 2, 0, 4, 0, 0, 0, ARMImpOpBase + 0, 305, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #368 = MQQPRStore |
| 10009 | { 367, 2, 1, 4, 0, 0, 0, ARMImpOpBase + 0, 305, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #367 = MQQPRLoad |
| 10010 | { 366, 2, 1, 8, 1154, 0, 0, ARMImpOpBase + 0, 303, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveReg), 0x40000ULL }, // Inst #366 = MQPRCopy |
| 10011 | { 365, 2, 1, 0, 325, 0, 1, ARMImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo), 0x2000ULL }, // Inst #365 = MOVsrl_glue |
| 10012 | { 364, 2, 1, 0, 325, 0, 1, ARMImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo), 0x2000ULL }, // Inst #364 = MOVsra_glue |
| 10013 | { 363, 2, 1, 8, 331, 0, 0, ARMImpOpBase + 0, 218, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #363 = MOVi32imm |
| 10014 | { 362, 3, 1, 4, 867, 0, 0, ARMImpOpBase + 0, 300, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #362 = MOVi16_ga_pcrel |
| 10015 | { 361, 2, 1, 0, 333, 0, 0, ARMImpOpBase + 0, 218, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #361 = MOV_ga_pcrel_ldr |
| 10016 | { 360, 2, 1, 0, 332, 0, 0, ARMImpOpBase + 0, 218, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #360 = MOV_ga_pcrel |
| 10017 | { 359, 4, 1, 4, 693, 0, 0, ARMImpOpBase + 0, 296, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #359 = MOVTi16_ga_pcrel |
| 10018 | { 358, 1, 0, 4, 883, 0, 0, ARMImpOpBase + 0, 295, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #358 = MOVPCRX |
| 10019 | { 357, 7, 1, 4, 328, 0, 0, ARMImpOpBase + 0, 288, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #357 = MOVCCsr |
| 10020 | { 356, 6, 1, 4, 874, 0, 0, ARMImpOpBase + 0, 282, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #356 = MOVCCsi |
| 10021 | { 355, 5, 1, 4, 871, 0, 0, ARMImpOpBase + 0, 277, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Select)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #355 = MOVCCr |
| 10022 | { 354, 5, 1, 8, 330, 0, 0, ARMImpOpBase + 0, 272, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #354 = MOVCCi32imm |
| 10023 | { 353, 5, 1, 4, 867, 0, 0, ARMImpOpBase + 0, 267, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #353 = MOVCCi16 |
| 10024 | { 352, 5, 1, 4, 869, 0, 0, ARMImpOpBase + 0, 267, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #352 = MOVCCi |
| 10025 | { 351, 7, 1, 4, 337, 0, 0, ARMImpOpBase + 0, 260, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // Inst #351 = MLAv5 |
| 10026 | { 350, 5, 2, 0, 1043, 0, 0, ARMImpOpBase + 0, 255, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #350 = MEMCPY |
| 10027 | { 349, 6, 0, 4, 716, 0, 0, ARMImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #349 = LSRr |
| 10028 | { 348, 6, 0, 4, 876, 0, 0, ARMImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #348 = LSRi |
| 10029 | { 347, 6, 0, 4, 716, 0, 0, ARMImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #347 = LSLr |
| 10030 | { 346, 6, 0, 4, 876, 0, 0, ARMImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #346 = LSLi |
| 10031 | { 345, 4, 1, 64, 11, 0, 0, ARMImpOpBase + 0, 251, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x3ULL }, // Inst #345 = LOADDUAL |
| 10032 | { 344, 4, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 247, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #344 = LEApcrelJT |
| 10033 | { 343, 4, 1, 4, 1, 0, 0, ARMImpOpBase + 0, 247, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #343 = LEApcrel |
| 10034 | { 342, 4, 1, 4, 934, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #342 = LDRT_POST |
| 10035 | { 341, 4, 1, 4, 350, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #341 = LDRSHTii |
| 10036 | { 340, 4, 1, 4, 350, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #340 = LDRSBTii |
| 10037 | { 339, 2, 1, 0, 456, 0, 0, ARMImpOpBase + 0, 218, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #339 = LDRLIT_ga_pcrel_ldr |
| 10038 | { 338, 2, 1, 0, 455, 0, 0, ARMImpOpBase + 0, 218, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #338 = LDRLIT_ga_pcrel |
| 10039 | { 337, 2, 1, 0, 454, 0, 0, ARMImpOpBase + 0, 218, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #337 = LDRLIT_ga_abs |
| 10040 | { 336, 4, 1, 4, 408, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #336 = LDRHTii |
| 10041 | { 335, 4, 1, 4, 902, 0, 0, ARMImpOpBase + 0, 243, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #335 = LDRConstPool |
| 10042 | { 334, 4, 1, 4, 689, 0, 0, ARMImpOpBase + 0, 239, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #334 = LDRBT_POST |
| 10043 | { 333, 5, 1, 4, 423, 0, 0, ARMImpOpBase + 0, 234, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = LDMIA_RET |
| 10044 | { 332, 3, 0, 0, 1042, 0, 0, ARMImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #332 = JUMPTABLE_TBH |
| 10045 | { 331, 3, 0, 0, 1042, 0, 0, ARMImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #331 = JUMPTABLE_TBB |
| 10046 | { 330, 3, 0, 0, 1042, 0, 0, ARMImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #330 = JUMPTABLE_INSTS |
| 10047 | { 329, 3, 0, 0, 1042, 0, 0, ARMImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #329 = JUMPTABLE_ADDRS |
| 10048 | { 328, 0, 0, 0, 1040, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #328 = Int_eh_sjlj_setup_dispatch |
| 10049 | { 327, 2, 0, 20, 1040, 0, 15, ARMImpOpBase + 39, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #327 = Int_eh_sjlj_setjmp_nofp |
| 10050 | { 326, 2, 0, 20, 1040, 0, 31, ARMImpOpBase + 8, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #326 = Int_eh_sjlj_setjmp |
| 10051 | { 325, 2, 0, 16, 1040, 0, 3, ARMImpOpBase + 5, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #325 = Int_eh_sjlj_longjmp |
| 10052 | { 324, 0, 0, 0, 1040, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #324 = Int_eh_sjlj_dispatchsetup |
| 10053 | { 323, 2, 0, 4, 458, 0, 0, ARMImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #323 = ITasm |
| 10054 | { 322, 4, 0, 0, 1062, 0, 1, ARMImpOpBase + 0, 230, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #322 = COPY_STRUCT_BYVAL_I32 |
| 10055 | { 321, 3, 0, 0, 844, 0, 0, ARMImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #321 = CONSTPOOL_ENTRY |
| 10056 | { 320, 5, 2, 0, 1041, 0, 0, ARMImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #320 = CMP_SWAP_8 |
| 10057 | { 319, 5, 2, 0, 1041, 0, 0, ARMImpOpBase + 0, 225, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #319 = CMP_SWAP_64 |
| 10058 | { 318, 5, 2, 0, 1041, 0, 0, ARMImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #318 = CMP_SWAP_32 |
| 10059 | { 317, 5, 2, 0, 1041, 0, 0, ARMImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #317 = CMP_SWAP_16 |
| 10060 | { 316, 1, 0, 8, 854, 1, 1, ARMImpOpBase + 3, 207, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #316 = BX_CALL |
| 10061 | { 315, 2, 0, 4, 863, 0, 0, ARMImpOpBase + 0, 218, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #315 = BR_JTr |
| 10062 | { 314, 4, 0, 4, 865, 0, 0, ARMImpOpBase + 0, 214, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #314 = BR_JTm_rs |
| 10063 | { 313, 3, 0, 4, 865, 0, 0, ARMImpOpBase + 0, 211, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #313 = BR_JTm_i12 |
| 10064 | { 312, 3, 0, 4, 862, 0, 0, ARMImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #312 = BR_JTadd |
| 10065 | { 311, 1, 0, 8, 870, 1, 1, ARMImpOpBase + 3, 207, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #311 = BMOVPCRX_CALL |
| 10066 | { 310, 1, 0, 8, 870, 1, 1, ARMImpOpBase + 3, 193, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #310 = BMOVPCB_CALL |
| 10067 | { 309, 2, 0, 4, 5, 1, 1, ARMImpOpBase + 3, 205, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #309 = BL_PUSHLR |
| 10068 | { 308, 1, 0, 4, 860, 1, 1, ARMImpOpBase + 3, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #308 = BLX_pred_noip |
| 10069 | { 307, 1, 0, 4, 860, 1, 1, ARMImpOpBase + 3, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #307 = BLX_noip |
| 10070 | { 306, 6, 0, 0, 861, 0, 1, ARMImpOpBase + 0, 198, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #306 = BCCi64 |
| 10071 | { 305, 4, 0, 0, 861, 0, 1, ARMImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #305 = BCCZi64 |
| 10072 | { 304, 1, 0, 4, 854, 0, 0, ARMImpOpBase + 0, 193, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #304 = B |
| 10073 | { 303, 6, 0, 4, 716, 0, 0, ARMImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #303 = ASRr |
| 10074 | { 302, 6, 0, 4, 715, 0, 0, ARMImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #302 = ASRi |
| 10075 | { 301, 4, 0, 0, 1040, 1, 1, ARMImpOpBase + 1, 177, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #301 = ADJCALLSTACKUP |
| 10076 | { 300, 4, 0, 0, 1040, 1, 1, ARMImpOpBase + 1, 177, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #300 = ADJCALLSTACKDOWN |
| 10077 | { 299, 7, 1, 4, 709, 0, 1, ARMImpOpBase + 0, 170, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #299 = ADDSrsr |
| 10078 | { 298, 6, 1, 4, 704, 0, 1, ARMImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #298 = ADDSrsi |
| 10079 | { 297, 5, 1, 4, 701, 0, 1, ARMImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #297 = ADDSrr |
| 10080 | { 296, 5, 1, 4, 694, 0, 1, ARMImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #296 = ADDSri |
| 10081 | { 295, 2, 1, 8, 680, 0, 1, ARMImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #295 = ABS |
| 10082 | { 294, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_UBFX |
| 10083 | { 293, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_SBFX |
| 10084 | { 292, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMIN |
| 10085 | { 291, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_UMAX |
| 10086 | { 290, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMIN |
| 10087 | { 289, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #289 = G_VECREDUCE_SMAX |
| 10088 | { 288, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #288 = G_VECREDUCE_XOR |
| 10089 | { 287, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #287 = G_VECREDUCE_OR |
| 10090 | { 286, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #286 = G_VECREDUCE_AND |
| 10091 | { 285, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #285 = G_VECREDUCE_MUL |
| 10092 | { 284, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #284 = G_VECREDUCE_ADD |
| 10093 | { 283, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMINIMUM |
| 10094 | { 282, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMAXIMUM |
| 10095 | { 281, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMIN |
| 10096 | { 280, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMAX |
| 10097 | { 279, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #279 = G_VECREDUCE_FMUL |
| 10098 | { 278, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #278 = G_VECREDUCE_FADD |
| 10099 | { 277, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FMUL |
| 10100 | { 276, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #276 = G_VECREDUCE_SEQ_FADD |
| 10101 | { 275, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_UBSANTRAP |
| 10102 | { 274, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_DEBUGTRAP |
| 10103 | { 273, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = G_TRAP |
| 10104 | { 272, 3, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #272 = G_BZERO |
| 10105 | { 271, 4, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #271 = G_MEMSET |
| 10106 | { 270, 4, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #270 = G_MEMMOVE |
| 10107 | { 269, 3, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #269 = G_MEMCPY_INLINE |
| 10108 | { 268, 4, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #268 = G_MEMCPY |
| 10109 | { 267, 2, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_WRITE_REGISTER |
| 10110 | { 266, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #266 = G_READ_REGISTER |
| 10111 | { 265, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #265 = G_STRICT_FLDEXP |
| 10112 | { 264, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #264 = G_STRICT_FSQRT |
| 10113 | { 263, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #263 = G_STRICT_FMA |
| 10114 | { 262, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #262 = G_STRICT_FREM |
| 10115 | { 261, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #261 = G_STRICT_FDIV |
| 10116 | { 260, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #260 = G_STRICT_FMUL |
| 10117 | { 259, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #259 = G_STRICT_FSUB |
| 10118 | { 258, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #258 = G_STRICT_FADD |
| 10119 | { 257, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #257 = G_STACKRESTORE |
| 10120 | { 256, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #256 = G_STACKSAVE |
| 10121 | { 255, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #255 = G_DYN_STACKALLOC |
| 10122 | { 254, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_JUMP_TABLE |
| 10123 | { 253, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_BLOCK_ADDR |
| 10124 | { 252, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_ADDRSPACE_CAST |
| 10125 | { 251, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FNEARBYINT |
| 10126 | { 250, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_FRINT |
| 10127 | { 249, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_FFLOOR |
| 10128 | { 248, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_FSQRT |
| 10129 | { 247, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_FTANH |
| 10130 | { 246, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_FSINH |
| 10131 | { 245, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_FCOSH |
| 10132 | { 244, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_FATAN |
| 10133 | { 243, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_FASIN |
| 10134 | { 242, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_FACOS |
| 10135 | { 241, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_FTAN |
| 10136 | { 240, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_FSIN |
| 10137 | { 239, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_FCOS |
| 10138 | { 238, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_FCEIL |
| 10139 | { 237, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_BITREVERSE |
| 10140 | { 236, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_BSWAP |
| 10141 | { 235, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_CTPOP |
| 10142 | { 234, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #234 = G_CTLZ_ZERO_UNDEF |
| 10143 | { 233, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #233 = G_CTLZ |
| 10144 | { 232, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_CTTZ_ZERO_UNDEF |
| 10145 | { 231, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_CTTZ |
| 10146 | { 230, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_VECTOR_COMPRESS |
| 10147 | { 229, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #229 = G_SPLAT_VECTOR |
| 10148 | { 228, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #228 = G_SHUFFLE_VECTOR |
| 10149 | { 227, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #227 = G_EXTRACT_VECTOR_ELT |
| 10150 | { 226, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #226 = G_INSERT_VECTOR_ELT |
| 10151 | { 225, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_EXTRACT_SUBVECTOR |
| 10152 | { 224, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_INSERT_SUBVECTOR |
| 10153 | { 223, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #223 = G_VSCALE |
| 10154 | { 222, 3, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #222 = G_BRJT |
| 10155 | { 221, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #221 = G_BR |
| 10156 | { 220, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #220 = G_LLROUND |
| 10157 | { 219, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #219 = G_LROUND |
| 10158 | { 218, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #218 = G_ABS |
| 10159 | { 217, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_UMAX |
| 10160 | { 216, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_UMIN |
| 10161 | { 215, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_SMAX |
| 10162 | { 214, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #214 = G_SMIN |
| 10163 | { 213, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #213 = G_PTRMASK |
| 10164 | { 212, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #212 = G_PTR_ADD |
| 10165 | { 211, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #211 = G_RESET_FPMODE |
| 10166 | { 210, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #210 = G_SET_FPMODE |
| 10167 | { 209, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #209 = G_GET_FPMODE |
| 10168 | { 208, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #208 = G_RESET_FPENV |
| 10169 | { 207, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #207 = G_SET_FPENV |
| 10170 | { 206, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #206 = G_GET_FPENV |
| 10171 | { 205, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #205 = G_FMAXIMUM |
| 10172 | { 204, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #204 = G_FMINIMUM |
| 10173 | { 203, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #203 = G_FMAXNUM_IEEE |
| 10174 | { 202, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #202 = G_FMINNUM_IEEE |
| 10175 | { 201, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #201 = G_FMAXNUM |
| 10176 | { 200, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #200 = G_FMINNUM |
| 10177 | { 199, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_FCANONICALIZE |
| 10178 | { 198, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_IS_FPCLASS |
| 10179 | { 197, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FCOPYSIGN |
| 10180 | { 196, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FABS |
| 10181 | { 195, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_UITOFP |
| 10182 | { 194, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_SITOFP |
| 10183 | { 193, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FPTOUI |
| 10184 | { 192, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FPTOSI |
| 10185 | { 191, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FPTRUNC |
| 10186 | { 190, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FPEXT |
| 10187 | { 189, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FNEG |
| 10188 | { 188, 3, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FFREXP |
| 10189 | { 187, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FLDEXP |
| 10190 | { 186, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FLOG10 |
| 10191 | { 185, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FLOG2 |
| 10192 | { 184, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FLOG |
| 10193 | { 183, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FEXP10 |
| 10194 | { 182, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #182 = G_FEXP2 |
| 10195 | { 181, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FEXP |
| 10196 | { 180, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #180 = G_FPOWI |
| 10197 | { 179, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_FPOW |
| 10198 | { 178, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_FREM |
| 10199 | { 177, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_FDIV |
| 10200 | { 176, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_FMAD |
| 10201 | { 175, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #175 = G_FMA |
| 10202 | { 174, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #174 = G_FMUL |
| 10203 | { 173, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #173 = G_FSUB |
| 10204 | { 172, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #172 = G_FADD |
| 10205 | { 171, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_UDIVFIXSAT |
| 10206 | { 170, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_SDIVFIXSAT |
| 10207 | { 169, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_UDIVFIX |
| 10208 | { 168, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_SDIVFIX |
| 10209 | { 167, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_UMULFIXSAT |
| 10210 | { 166, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_SMULFIXSAT |
| 10211 | { 165, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_UMULFIX |
| 10212 | { 164, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #164 = G_SMULFIX |
| 10213 | { 163, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #163 = G_SSHLSAT |
| 10214 | { 162, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #162 = G_USHLSAT |
| 10215 | { 161, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SSUBSAT |
| 10216 | { 160, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_USUBSAT |
| 10217 | { 159, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #159 = G_SADDSAT |
| 10218 | { 158, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_UADDSAT |
| 10219 | { 157, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #157 = G_SMULH |
| 10220 | { 156, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #156 = G_UMULH |
| 10221 | { 155, 4, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #155 = G_SMULO |
| 10222 | { 154, 4, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_UMULO |
| 10223 | { 153, 5, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SSUBE |
| 10224 | { 152, 4, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_SSUBO |
| 10225 | { 151, 5, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_SADDE |
| 10226 | { 150, 4, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #150 = G_SADDO |
| 10227 | { 149, 5, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_USUBE |
| 10228 | { 148, 4, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_USUBO |
| 10229 | { 147, 5, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_UADDE |
| 10230 | { 146, 4, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #146 = G_UADDO |
| 10231 | { 145, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_SELECT |
| 10232 | { 144, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_UCMP |
| 10233 | { 143, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_SCMP |
| 10234 | { 142, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_FCMP |
| 10235 | { 141, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ICMP |
| 10236 | { 140, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_ROTL |
| 10237 | { 139, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_ROTR |
| 10238 | { 138, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #138 = G_FSHR |
| 10239 | { 137, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #137 = G_FSHL |
| 10240 | { 136, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_ASHR |
| 10241 | { 135, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_LSHR |
| 10242 | { 134, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_SHL |
| 10243 | { 133, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ZEXT |
| 10244 | { 132, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #132 = G_SEXT_INREG |
| 10245 | { 131, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #131 = G_SEXT |
| 10246 | { 130, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #130 = G_VAARG |
| 10247 | { 129, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #129 = G_VASTART |
| 10248 | { 128, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #128 = G_FCONSTANT |
| 10249 | { 127, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #127 = G_CONSTANT |
| 10250 | { 126, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #126 = G_TRUNC |
| 10251 | { 125, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #125 = G_ANYEXT |
| 10252 | { 124, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 10253 | { 123, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #123 = G_INTRINSIC_CONVERGENT |
| 10254 | { 122, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #122 = G_INTRINSIC_W_SIDE_EFFECTS |
| 10255 | { 121, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #121 = G_INTRINSIC |
| 10256 | { 120, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #120 = G_INVOKE_REGION_START |
| 10257 | { 119, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #119 = G_BRINDIRECT |
| 10258 | { 118, 2, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #118 = G_BRCOND |
| 10259 | { 117, 4, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #117 = G_PREFETCH |
| 10260 | { 116, 2, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #116 = G_FENCE |
| 10261 | { 115, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UDEC_WRAP |
| 10262 | { 114, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_UINC_WRAP |
| 10263 | { 113, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMIN |
| 10264 | { 112, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FMAX |
| 10265 | { 111, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FSUB |
| 10266 | { 110, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_FADD |
| 10267 | { 109, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMIN |
| 10268 | { 108, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_UMAX |
| 10269 | { 107, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MIN |
| 10270 | { 106, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_MAX |
| 10271 | { 105, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_XOR |
| 10272 | { 104, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_OR |
| 10273 | { 103, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_NAND |
| 10274 | { 102, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMICRMW_AND |
| 10275 | { 101, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMICRMW_SUB |
| 10276 | { 100, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_ATOMICRMW_ADD |
| 10277 | { 99, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_ATOMICRMW_XCHG |
| 10278 | { 98, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG |
| 10279 | { 97, 5, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #97 = G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 10280 | { 96, 5, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #96 = G_INDEXED_STORE |
| 10281 | { 95, 2, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #95 = G_STORE |
| 10282 | { 94, 5, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_INDEXED_ZEXTLOAD |
| 10283 | { 93, 5, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_INDEXED_SEXTLOAD |
| 10284 | { 92, 5, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #92 = G_INDEXED_LOAD |
| 10285 | { 91, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #91 = G_ZEXTLOAD |
| 10286 | { 90, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #90 = G_SEXTLOAD |
| 10287 | { 89, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #89 = G_LOAD |
| 10288 | { 88, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #88 = G_READSTEADYCOUNTER |
| 10289 | { 87, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #87 = G_READCYCLECOUNTER |
| 10290 | { 86, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_ROUNDEVEN |
| 10291 | { 85, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_LLRINT |
| 10292 | { 84, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_INTRINSIC_LRINT |
| 10293 | { 83, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_INTRINSIC_ROUND |
| 10294 | { 82, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_INTRINSIC_TRUNC |
| 10295 | { 81, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_INTRINSIC_FPTRUNC_ROUND |
| 10296 | { 80, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_CONSTANT_FOLD_BARRIER |
| 10297 | { 79, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #79 = G_FREEZE |
| 10298 | { 78, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #78 = G_BITCAST |
| 10299 | { 77, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #77 = G_INTTOPTR |
| 10300 | { 76, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #76 = G_PTRTOINT |
| 10301 | { 75, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #75 = G_CONCAT_VECTORS |
| 10302 | { 74, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR_TRUNC |
| 10303 | { 73, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #73 = G_BUILD_VECTOR |
| 10304 | { 72, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #72 = G_MERGE_VALUES |
| 10305 | { 71, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_INSERT |
| 10306 | { 70, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #70 = G_UNMERGE_VALUES |
| 10307 | { 69, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_EXTRACT |
| 10308 | { 68, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #68 = G_CONSTANT_POOL |
| 10309 | { 67, 5, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_PTRAUTH_GLOBAL_VALUE |
| 10310 | { 66, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #66 = G_GLOBAL_VALUE |
| 10311 | { 65, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #65 = G_FRAME_INDEX |
| 10312 | { 64, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #64 = G_PHI |
| 10313 | { 63, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #63 = G_IMPLICIT_DEF |
| 10314 | { 62, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_XOR |
| 10315 | { 61, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #61 = G_OR |
| 10316 | { 60, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #60 = G_AND |
| 10317 | { 59, 4, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UDIVREM |
| 10318 | { 58, 4, 2, 0, 0, 0, 0, ARMImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SDIVREM |
| 10319 | { 57, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UREM |
| 10320 | { 56, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SREM |
| 10321 | { 55, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #55 = G_UDIV |
| 10322 | { 54, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SDIV |
| 10323 | { 53, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_MUL |
| 10324 | { 52, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_SUB |
| 10325 | { 51, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #51 = G_ADD |
| 10326 | { 50, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_ALIGN |
| 10327 | { 49, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #49 = G_ASSERT_ZEXT |
| 10328 | { 48, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #48 = G_ASSERT_SEXT |
| 10329 | { 47, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_GLUE |
| 10330 | { 46, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_LOOP |
| 10331 | { 45, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ANCHOR |
| 10332 | { 44, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #44 = CONVERGENCECTRL_ENTRY |
| 10333 | { 43, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #43 = JUMP_TABLE_DEBUG_INFO |
| 10334 | { 42, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = MEMBARRIER |
| 10335 | { 41, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL |
| 10336 | { 40, 3, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL |
| 10337 | { 39, 2, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL |
| 10338 | { 38, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL |
| 10339 | { 37, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT |
| 10340 | { 36, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_RET |
| 10341 | { 35, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER |
| 10342 | { 34, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = PATCHABLE_OP |
| 10343 | { 33, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #33 = FAULTING_OP |
| 10344 | { 32, 2, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE |
| 10345 | { 31, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = STATEPOINT |
| 10346 | { 30, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG |
| 10347 | { 29, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP |
| 10348 | { 28, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD |
| 10349 | { 27, 6, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = PATCHPOINT |
| 10350 | { 26, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = FENTRY_CALL |
| 10351 | { 25, 2, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #25 = STACKMAP |
| 10352 | { 24, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #24 = ARITH_FENCE |
| 10353 | { 23, 4, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #23 = PSEUDO_PROBE |
| 10354 | { 22, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_END |
| 10355 | { 21, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #21 = LIFETIME_START |
| 10356 | { 20, 0, 0, 0, 1221, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #20 = BUNDLE |
| 10357 | { 19, 2, 1, 0, 681, 0, 0, ARMImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = COPY |
| 10358 | { 18, 2, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #18 = REG_SEQUENCE |
| 10359 | { 17, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #17 = DBG_LABEL |
| 10360 | { 16, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_PHI |
| 10361 | { 15, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_INSTR_REF |
| 10362 | { 14, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST |
| 10363 | { 13, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #13 = DBG_VALUE |
| 10364 | { 12, 3, 1, 0, 1061, 0, 0, ARMImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS |
| 10365 | { 11, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = SUBREG_TO_REG |
| 10366 | { 10, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF |
| 10367 | { 9, 4, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG |
| 10368 | { 8, 3, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG |
| 10369 | { 7, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL |
| 10370 | { 6, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL |
| 10371 | { 5, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL |
| 10372 | { 4, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL |
| 10373 | { 3, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION |
| 10374 | { 2, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR |
| 10375 | { 1, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM |
| 10376 | { 0, 1, 1, 0, 0, 0, 0, ARMImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI |
| 10377 | }, { |
| 10378 | /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10379 | /* 1 */ |
| 10380 | /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10381 | /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10382 | /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10383 | /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10384 | /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10385 | /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10386 | /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, |
| 10387 | /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10388 | /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10389 | /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10390 | /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10391 | /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10392 | /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10393 | /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10394 | /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10395 | /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10396 | /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10397 | /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10398 | /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10399 | /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10400 | /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10401 | /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10402 | /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10403 | /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10404 | /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10405 | /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10406 | /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10407 | /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10408 | /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10409 | /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10410 | /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10411 | /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10412 | /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10413 | /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10414 | /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10415 | /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10416 | /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10417 | /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10418 | /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10419 | /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 10420 | /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 10421 | /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10422 | /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10423 | /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10424 | /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10425 | /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10426 | /* 152 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10427 | /* 154 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10428 | /* 159 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10429 | /* 164 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10430 | /* 170 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10431 | /* 177 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10432 | /* 181 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10433 | /* 187 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10434 | /* 193 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10435 | /* 194 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10436 | /* 198 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10437 | /* 204 */ { ARM::GPRnoipRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10438 | /* 205 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10439 | /* 207 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10440 | /* 208 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10441 | /* 211 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10442 | /* 214 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10443 | /* 218 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10444 | /* 220 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10445 | /* 225 */ { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10446 | /* 230 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10447 | /* 234 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10448 | /* 239 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10449 | /* 243 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10450 | /* 247 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10451 | /* 251 */ { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10452 | /* 255 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10453 | /* 260 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10454 | /* 267 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10455 | /* 272 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10456 | /* 277 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10457 | /* 282 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10458 | /* 288 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10459 | /* 295 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10460 | /* 296 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10461 | /* 300 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10462 | /* 303 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10463 | /* 305 */ { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10464 | /* 307 */ { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10465 | /* 309 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10466 | /* 315 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10467 | /* 318 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10468 | /* 321 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10469 | /* 326 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10470 | /* 327 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10471 | /* 328 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10472 | /* 329 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10473 | /* 334 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10474 | /* 343 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10475 | /* 350 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10476 | /* 353 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10477 | /* 360 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10478 | /* 367 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10479 | /* 370 */ { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10480 | /* 371 */ { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10481 | /* 373 */ { ARM::tcGPRnotr12RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10482 | /* 375 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10483 | /* 381 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10484 | /* 388 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10485 | /* 393 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10486 | /* 399 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10487 | /* 400 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10488 | /* 405 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10489 | /* 410 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10490 | /* 411 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10491 | /* 416 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10492 | /* 418 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10493 | /* 423 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10494 | /* 428 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10495 | /* 434 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10496 | /* 437 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10497 | /* 439 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10498 | /* 442 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10499 | /* 446 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10500 | /* 448 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10501 | /* 451 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10502 | /* 455 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10503 | /* 458 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10504 | /* 461 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10505 | /* 467 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10506 | /* 472 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10507 | /* 477 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10508 | /* 482 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10509 | /* 487 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10510 | /* 493 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10511 | /* 497 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10512 | /* 502 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10513 | /* 508 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10514 | /* 514 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10515 | /* 517 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10516 | /* 521 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10517 | /* 524 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10518 | /* 527 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10519 | /* 530 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10520 | /* 531 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnoipRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10521 | /* 534 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10522 | /* 538 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10523 | /* 541 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10524 | /* 543 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10525 | /* 545 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10526 | /* 548 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10527 | /* 551 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10528 | /* 556 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10529 | /* 561 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10530 | /* 566 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10531 | /* 570 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10532 | /* 575 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10533 | /* 578 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10534 | /* 582 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10535 | /* 587 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10536 | /* 590 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10537 | /* 592 */ { ARM::tGPRwithpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10538 | /* 596 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10539 | /* 602 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10540 | /* 609 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10541 | /* 617 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10542 | /* 625 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10543 | /* 628 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10544 | /* 630 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10545 | /* 635 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10546 | /* 640 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10547 | /* 644 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10548 | /* 648 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10549 | /* 652 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10550 | /* 658 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10551 | /* 661 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10552 | /* 667 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10553 | /* 670 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10554 | /* 676 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10555 | /* 680 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10556 | /* 687 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10557 | /* 691 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10558 | /* 698 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10559 | /* 703 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10560 | /* 711 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10561 | /* 716 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10562 | /* 724 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10563 | /* 728 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10564 | /* 732 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10565 | /* 739 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10566 | /* 742 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10567 | /* 745 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10568 | /* 752 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10569 | /* 757 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10570 | /* 762 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10571 | /* 770 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10572 | /* 774 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10573 | /* 778 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10574 | /* 786 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10575 | /* 792 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10576 | /* 798 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10577 | /* 807 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10578 | /* 812 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10579 | /* 817 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10580 | /* 826 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10581 | /* 834 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10582 | /* 840 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10583 | /* 844 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10584 | /* 849 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10585 | /* 855 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10586 | /* 858 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10587 | /* 861 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10588 | /* 864 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10589 | /* 868 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10590 | /* 872 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10591 | /* 876 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10592 | /* 880 */ { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10593 | /* 884 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10594 | /* 888 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10595 | /* 892 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10596 | /* 898 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10597 | /* 904 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10598 | /* 911 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10599 | /* 917 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10600 | /* 922 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10601 | /* 928 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10602 | /* 935 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(2) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10603 | /* 943 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10604 | /* 949 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10605 | /* 956 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10606 | /* 963 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10607 | /* 969 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10608 | /* 977 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10609 | /* 983 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10610 | /* 990 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10611 | /* 995 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10612 | /* 1002 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10613 | /* 1008 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10614 | /* 1013 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10615 | /* 1018 */ { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10616 | /* 1023 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10617 | /* 1029 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10618 | /* 1036 */ { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10619 | /* 1044 */ { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10620 | /* 1050 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10621 | /* 1057 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10622 | /* 1062 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10623 | /* 1065 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10624 | /* 1069 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10625 | /* 1073 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10626 | /* 1077 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10627 | /* 1084 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10628 | /* 1091 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10629 | /* 1096 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10630 | /* 1104 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10631 | /* 1111 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10632 | /* 1118 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10633 | /* 1124 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10634 | /* 1133 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10635 | /* 1141 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10636 | /* 1149 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10637 | /* 1155 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10638 | /* 1161 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10639 | /* 1166 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10640 | /* 1173 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10641 | /* 1179 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10642 | /* 1187 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10643 | /* 1195 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10644 | /* 1203 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10645 | /* 1210 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10646 | /* 1217 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10647 | /* 1222 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10648 | /* 1228 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10649 | /* 1235 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10650 | /* 1243 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10651 | /* 1249 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10652 | /* 1258 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10653 | /* 1265 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10654 | /* 1272 */ { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10655 | /* 1275 */ { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, |
| 10656 | /* 1279 */ { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10657 | /* 1282 */ { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, |
| 10658 | /* 1286 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10659 | /* 1292 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10660 | /* 1299 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10661 | /* 1305 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10662 | /* 1311 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10663 | /* 1318 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10664 | /* 1324 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10665 | /* 1331 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10666 | /* 1337 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10667 | /* 1344 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10668 | /* 1350 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10669 | /* 1359 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10670 | /* 1366 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10671 | /* 1371 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10672 | /* 1379 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10673 | /* 1386 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10674 | /* 1392 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10675 | /* 1398 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10676 | /* 1405 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10677 | /* 1410 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10678 | /* 1416 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10679 | /* 1420 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10680 | /* 1424 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10681 | /* 1431 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10682 | /* 1438 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10683 | /* 1444 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10684 | /* 1451 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10685 | /* 1457 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10686 | /* 1465 */ { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10687 | /* 1467 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, |
| 10688 | /* 1470 */ { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10689 | /* 1472 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, |
| 10690 | /* 1475 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10691 | /* 1481 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10692 | /* 1487 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10693 | /* 1494 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10694 | /* 1501 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10695 | /* 1504 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10696 | /* 1507 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10697 | /* 1513 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10698 | /* 1515 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10699 | /* 1518 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10700 | /* 1523 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10701 | /* 1529 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10702 | /* 1535 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10703 | /* 1544 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10704 | /* 1552 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10705 | /* 1559 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10706 | /* 1565 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10707 | /* 1570 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10708 | /* 1575 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10709 | /* 1580 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10710 | /* 1587 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10711 | /* 1594 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10712 | /* 1600 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10713 | /* 1608 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10714 | /* 1614 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10715 | /* 1621 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10716 | /* 1626 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10717 | /* 1632 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10718 | /* 1637 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10719 | /* 1645 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10720 | /* 1651 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10721 | /* 1657 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10722 | /* 1663 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10723 | /* 1668 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10724 | /* 1673 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10725 | /* 1678 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10726 | /* 1682 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10727 | /* 1686 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10728 | /* 1690 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10729 | /* 1694 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10730 | /* 1699 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10731 | /* 1704 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10732 | /* 1709 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10733 | /* 1714 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10734 | /* 1719 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10735 | /* 1724 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10736 | /* 1729 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10737 | /* 1735 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10738 | /* 1741 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10739 | /* 1745 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10740 | /* 1749 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10741 | /* 1754 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10742 | /* 1760 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10743 | /* 1766 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10744 | /* 1771 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10745 | /* 1777 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10746 | /* 1783 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10747 | /* 1786 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10748 | /* 1789 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10749 | /* 1792 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10750 | /* 1794 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10751 | /* 1796 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10752 | /* 1798 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10753 | /* 1800 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10754 | /* 1805 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10755 | /* 1809 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10756 | /* 1813 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10757 | /* 1818 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10758 | /* 1823 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10759 | /* 1827 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10760 | /* 1831 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10761 | /* 1835 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10762 | /* 1840 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10763 | /* 1846 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10764 | /* 1852 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10765 | /* 1858 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10766 | /* 1861 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10767 | /* 1865 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10768 | /* 1868 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10769 | /* 1872 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10770 | /* 1878 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10771 | /* 1881 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10772 | /* 1884 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10773 | /* 1889 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10774 | /* 1892 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10775 | /* 1898 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10776 | /* 1905 */ { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10777 | /* 1910 */ { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10778 | /* 1916 */ { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10779 | /* 1923 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10780 | /* 1930 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10781 | /* 1939 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10782 | /* 1946 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10783 | /* 1955 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10784 | /* 1960 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10785 | /* 1966 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10786 | /* 1973 */ { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10787 | /* 1979 */ { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10788 | /* 1987 */ { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10789 | /* 1992 */ { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10790 | /* 1998 */ { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10791 | /* 2005 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10792 | /* 2011 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10793 | /* 2018 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10794 | /* 2026 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10795 | /* 2035 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10796 | /* 2046 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10797 | /* 2053 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10798 | /* 2062 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10799 | /* 2069 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10800 | /* 2076 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10801 | /* 2085 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10802 | /* 2096 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10803 | /* 2109 */ { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10804 | /* 2116 */ { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10805 | /* 2125 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10806 | /* 2133 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(4) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10807 | /* 2143 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10808 | /* 2156 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(4) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10809 | /* 2171 */ { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10810 | /* 2175 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10811 | /* 2180 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10812 | /* 2185 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10813 | /* 2189 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10814 | /* 2194 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10815 | /* 2199 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10816 | /* 2205 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10817 | /* 2209 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10818 | /* 2216 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10819 | /* 2223 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10820 | /* 2230 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10821 | /* 2237 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10822 | /* 2244 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10823 | /* 2251 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10824 | /* 2256 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10825 | /* 2260 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10826 | /* 2264 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10827 | /* 2269 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10828 | /* 2275 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10829 | /* 2279 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10830 | /* 2283 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10831 | /* 2289 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10832 | /* 2293 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10833 | /* 2297 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10834 | /* 2301 */ { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10835 | /* 2305 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10836 | /* 2309 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10837 | /* 2315 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10838 | /* 2321 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10839 | /* 2327 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10840 | /* 2333 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10841 | /* 2339 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10842 | /* 2345 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10843 | /* 2350 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10844 | /* 2355 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10845 | /* 2360 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10846 | /* 2365 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10847 | /* 2367 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10848 | /* 2373 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10849 | /* 2379 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10850 | /* 2385 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10851 | /* 2390 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10852 | /* 2395 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10853 | /* 2399 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10854 | /* 2405 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10855 | /* 2411 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10856 | /* 2417 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10857 | /* 2425 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10858 | /* 2431 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10859 | /* 2439 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10860 | /* 2444 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10861 | /* 2449 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10862 | /* 2455 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10863 | /* 2462 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10864 | /* 2468 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10865 | /* 2475 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10866 | /* 2480 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10867 | /* 2485 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10868 | /* 2492 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10869 | /* 2498 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10870 | /* 2505 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10871 | /* 2512 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10872 | /* 2521 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10873 | /* 2527 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10874 | /* 2535 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10875 | /* 2542 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10876 | /* 2550 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10877 | /* 2560 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10878 | /* 2566 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10879 | /* 2574 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10880 | /* 2581 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10881 | /* 2590 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10882 | /* 2599 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10883 | /* 2610 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10884 | /* 2618 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10885 | /* 2628 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10886 | /* 2634 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10887 | /* 2640 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10888 | /* 2646 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10889 | /* 2651 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10890 | /* 2656 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10891 | /* 2662 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10892 | /* 2668 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10893 | /* 2672 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10894 | /* 2678 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10895 | /* 2684 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10896 | /* 2691 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10897 | /* 2697 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10898 | /* 2702 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10899 | /* 2708 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10900 | /* 2715 */ { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10901 | /* 2721 */ { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10902 | /* 2726 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10903 | /* 2730 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10904 | /* 2735 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10905 | /* 2741 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10906 | /* 2745 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10907 | /* 2749 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10908 | /* 2753 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10909 | /* 2758 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10910 | /* 2762 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10911 | /* 2766 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10912 | /* 2771 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10913 | /* 2775 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10914 | /* 2779 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10915 | /* 2784 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10916 | /* 2789 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10917 | /* 2793 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10918 | /* 2799 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10919 | /* 2806 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10920 | /* 2812 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10921 | /* 2817 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10922 | /* 2821 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10923 | /* 2827 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10924 | /* 2834 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10925 | /* 2840 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10926 | /* 2845 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10927 | /* 2850 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10928 | /* 2857 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10929 | /* 2861 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10930 | /* 2866 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10931 | /* 2871 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10932 | /* 2877 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10933 | /* 2882 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10934 | /* 2888 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10935 | /* 2892 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10936 | /* 2897 */ { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10937 | /* 2900 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10938 | /* 2906 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10939 | /* 2914 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10940 | /* 2920 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10941 | /* 2925 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10942 | /* 2930 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10943 | /* 2936 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10944 | /* 2942 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10945 | /* 2948 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10946 | /* 2955 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10947 | /* 2961 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10948 | /* 2967 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10949 | /* 2971 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10950 | /* 2975 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10951 | /* 2981 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10952 | /* 2987 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10953 | /* 2993 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10954 | /* 2998 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10955 | /* 3003 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10956 | /* 3009 */ { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10957 | /* 3014 */ { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10958 | /* 3019 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10959 | /* 3023 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10960 | /* 3026 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10961 | /* 3029 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10962 | /* 3031 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10963 | /* 3035 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10964 | /* 3039 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10965 | /* 3044 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10966 | /* 3049 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10967 | /* 3053 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10968 | /* 3058 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10969 | /* 3063 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10970 | /* 3069 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10971 | /* 3074 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10972 | }, { |
| 10973 | /* 0 */ |
| 10974 | /* 0 */ ARM::CPSR, |
| 10975 | /* 1 */ ARM::SP, ARM::SP, |
| 10976 | /* 3 */ ARM::SP, ARM::LR, |
| 10977 | /* 5 */ ARM::R7, ARM::LR, ARM::SP, |
| 10978 | /* 8 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, |
| 10979 | /* 39 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, |
| 10980 | /* 54 */ ARM::SP, |
| 10981 | /* 55 */ ARM::SP, ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, |
| 10982 | /* 60 */ ARM::R4, ARM::R4, ARM::SP, |
| 10983 | /* 63 */ ARM::CPSR, ARM::CPSR, |
| 10984 | /* 65 */ ARM::LR, |
| 10985 | /* 66 */ ARM::PC, |
| 10986 | /* 67 */ ARM::FPSCR_NZCV, ARM::CPSR, |
| 10987 | /* 69 */ ARM::VPR, |
| 10988 | /* 70 */ ARM::FPSCR_NZCV, |
| 10989 | /* 71 */ ARM::FPSCR, |
| 10990 | /* 72 */ ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, |
| 10991 | /* 91 */ ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, |
| 10992 | /* 126 */ ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, |
| 10993 | /* 148 */ ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, |
| 10994 | /* 186 */ ARM::R12, ARM::LR, ARM::SP, |
| 10995 | /* 189 */ ARM::ITSTATE, |
| 10996 | /* 190 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, |
| 10997 | /* 217 */ ARM::LR, ARM::SP, ARM::R12, |
| 10998 | /* 220 */ ARM::R11, ARM::LR, ARM::SP, |
| 10999 | /* 223 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::CPSR, |
| 11000 | } |
| 11001 | }; |
| 11002 | |
| 11003 | |
| 11004 | #ifdef __GNUC__ |
| 11005 | #pragma GCC diagnostic push |
| 11006 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 11007 | #endif |
| 11008 | extern const char ARMInstrNameData[] = { |
| 11009 | /* 0 */ "G_FLOG10\0" |
| 11010 | /* 9 */ "G_FEXP10\0" |
| 11011 | /* 18 */ "VMOVD0\0" |
| 11012 | /* 25 */ "VMSR_P0\0" |
| 11013 | /* 33 */ "VMRS_P0\0" |
| 11014 | /* 41 */ "VMOVQ0\0" |
| 11015 | /* 48 */ "VMRS_MVFR0\0" |
| 11016 | /* 59 */ "SHA1SU0\0" |
| 11017 | /* 67 */ "SHA256SU0\0" |
| 11018 | /* 77 */ "t__brkdiv0\0" |
| 11019 | /* 88 */ "VTBL1\0" |
| 11020 | /* 94 */ "VMRS_MVFR1\0" |
| 11021 | /* 105 */ "t2DCPS1\0" |
| 11022 | /* 113 */ "SHA1SU1\0" |
| 11023 | /* 121 */ "SHA256SU1\0" |
| 11024 | /* 131 */ "VTBX1\0" |
| 11025 | /* 137 */ "CDE_CX1\0" |
| 11026 | /* 145 */ "t2LDRBi12\0" |
| 11027 | /* 155 */ "t2STRBi12\0" |
| 11028 | /* 165 */ "t2LDRSBi12\0" |
| 11029 | /* 176 */ "t2PLDi12\0" |
| 11030 | /* 185 */ "t2LDRHi12\0" |
| 11031 | /* 195 */ "t2STRHi12\0" |
| 11032 | /* 205 */ "t2LDRSHi12\0" |
| 11033 | /* 216 */ "t2PLIi12\0" |
| 11034 | /* 225 */ "t2LDRi12\0" |
| 11035 | /* 234 */ "t2STRi12\0" |
| 11036 | /* 243 */ "t2PLDWi12\0" |
| 11037 | /* 253 */ "BR_JTm_i12\0" |
| 11038 | /* 264 */ "t2SUBri12\0" |
| 11039 | /* 274 */ "t2ADDri12\0" |
| 11040 | /* 284 */ "t2SUBspImm12\0" |
| 11041 | /* 297 */ "t2ADDspImm12\0" |
| 11042 | /* 310 */ "TCRETURNrinotr12\0" |
| 11043 | /* 327 */ "MVE_VSTRB32\0" |
| 11044 | /* 339 */ "MVE_VSTRH32\0" |
| 11045 | /* 351 */ "COPY_STRUCT_BYVAL_I32\0" |
| 11046 | /* 373 */ "MVE_VCTP32\0" |
| 11047 | /* 384 */ "MVE_VDUP32\0" |
| 11048 | /* 395 */ "MVE_VBRSR32\0" |
| 11049 | /* 407 */ "MVE_VLDRBS32\0" |
| 11050 | /* 420 */ "MVE_VLDRHS32\0" |
| 11051 | /* 433 */ "MVE_VLDRBU32\0" |
| 11052 | /* 446 */ "MVE_VLDRHU32\0" |
| 11053 | /* 459 */ "MVE_VLDRWU32\0" |
| 11054 | /* 472 */ "MVE_VSTRWU32\0" |
| 11055 | /* 485 */ "MVE_VLD20_32\0" |
| 11056 | /* 498 */ "MVE_VST20_32\0" |
| 11057 | /* 511 */ "MVE_VLD40_32\0" |
| 11058 | /* 524 */ "MVE_VST40_32\0" |
| 11059 | /* 537 */ "MVE_VLD21_32\0" |
| 11060 | /* 550 */ "MVE_VST21_32\0" |
| 11061 | /* 563 */ "MVE_VLD41_32\0" |
| 11062 | /* 576 */ "MVE_VST41_32\0" |
| 11063 | /* 589 */ "MVE_VLD42_32\0" |
| 11064 | /* 602 */ "MVE_VST42_32\0" |
| 11065 | /* 615 */ "MVE_VLD43_32\0" |
| 11066 | /* 628 */ "MVE_VST43_32\0" |
| 11067 | /* 641 */ "MVE_VREV64_32\0" |
| 11068 | /* 655 */ "tCMP_SWAP_32\0" |
| 11069 | /* 668 */ "MVE_DLSTP_32\0" |
| 11070 | /* 681 */ "MVE_WLSTP_32\0" |
| 11071 | /* 694 */ "MVE_VMOV_from_lane_32\0" |
| 11072 | /* 716 */ "MVE_VMOV_to_lane_32\0" |
| 11073 | /* 736 */ "VLD3dWB_fixed_Asm_32\0" |
| 11074 | /* 757 */ "VST3dWB_fixed_Asm_32\0" |
| 11075 | /* 778 */ "VLD4dWB_fixed_Asm_32\0" |
| 11076 | /* 799 */ "VST4dWB_fixed_Asm_32\0" |
| 11077 | /* 820 */ "VLD1LNdWB_fixed_Asm_32\0" |
| 11078 | /* 843 */ "VST1LNdWB_fixed_Asm_32\0" |
| 11079 | /* 866 */ "VLD2LNdWB_fixed_Asm_32\0" |
| 11080 | /* 889 */ "VST2LNdWB_fixed_Asm_32\0" |
| 11081 | /* 912 */ "VLD3LNdWB_fixed_Asm_32\0" |
| 11082 | /* 935 */ "VST3LNdWB_fixed_Asm_32\0" |
| 11083 | /* 958 */ "VLD4LNdWB_fixed_Asm_32\0" |
| 11084 | /* 981 */ "VST4LNdWB_fixed_Asm_32\0" |
| 11085 | /* 1004 */ "VLD3DUPdWB_fixed_Asm_32\0" |
| 11086 | /* 1028 */ "VLD4DUPdWB_fixed_Asm_32\0" |
| 11087 | /* 1052 */ "VLD3qWB_fixed_Asm_32\0" |
| 11088 | /* 1073 */ "VST3qWB_fixed_Asm_32\0" |
| 11089 | /* 1094 */ "VLD4qWB_fixed_Asm_32\0" |
| 11090 | /* 1115 */ "VST4qWB_fixed_Asm_32\0" |
| 11091 | /* 1136 */ "VLD2LNqWB_fixed_Asm_32\0" |
| 11092 | /* 1159 */ "VST2LNqWB_fixed_Asm_32\0" |
| 11093 | /* 1182 */ "VLD3LNqWB_fixed_Asm_32\0" |
| 11094 | /* 1205 */ "VST3LNqWB_fixed_Asm_32\0" |
| 11095 | /* 1228 */ "VLD4LNqWB_fixed_Asm_32\0" |
| 11096 | /* 1251 */ "VST4LNqWB_fixed_Asm_32\0" |
| 11097 | /* 1274 */ "VLD3DUPqWB_fixed_Asm_32\0" |
| 11098 | /* 1298 */ "VLD4DUPqWB_fixed_Asm_32\0" |
| 11099 | /* 1322 */ "VLD3dWB_register_Asm_32\0" |
| 11100 | /* 1346 */ "VST3dWB_register_Asm_32\0" |
| 11101 | /* 1370 */ "VLD4dWB_register_Asm_32\0" |
| 11102 | /* 1394 */ "VST4dWB_register_Asm_32\0" |
| 11103 | /* 1418 */ "VLD1LNdWB_register_Asm_32\0" |
| 11104 | /* 1444 */ "VST1LNdWB_register_Asm_32\0" |
| 11105 | /* 1470 */ "VLD2LNdWB_register_Asm_32\0" |
| 11106 | /* 1496 */ "VST2LNdWB_register_Asm_32\0" |
| 11107 | /* 1522 */ "VLD3LNdWB_register_Asm_32\0" |
| 11108 | /* 1548 */ "VST3LNdWB_register_Asm_32\0" |
| 11109 | /* 1574 */ "VLD4LNdWB_register_Asm_32\0" |
| 11110 | /* 1600 */ "VST4LNdWB_register_Asm_32\0" |
| 11111 | /* 1626 */ "VLD3DUPdWB_register_Asm_32\0" |
| 11112 | /* 1653 */ "VLD4DUPdWB_register_Asm_32\0" |
| 11113 | /* 1680 */ "VLD3qWB_register_Asm_32\0" |
| 11114 | /* 1704 */ "VST3qWB_register_Asm_32\0" |
| 11115 | /* 1728 */ "VLD4qWB_register_Asm_32\0" |
| 11116 | /* 1752 */ "VST4qWB_register_Asm_32\0" |
| 11117 | /* 1776 */ "VLD2LNqWB_register_Asm_32\0" |
| 11118 | /* 1802 */ "VST2LNqWB_register_Asm_32\0" |
| 11119 | /* 1828 */ "VLD3LNqWB_register_Asm_32\0" |
| 11120 | /* 1854 */ "VST3LNqWB_register_Asm_32\0" |
| 11121 | /* 1880 */ "VLD4LNqWB_register_Asm_32\0" |
| 11122 | /* 1906 */ "VST4LNqWB_register_Asm_32\0" |
| 11123 | /* 1932 */ "VLD3DUPqWB_register_Asm_32\0" |
| 11124 | /* 1959 */ "VLD4DUPqWB_register_Asm_32\0" |
| 11125 | /* 1986 */ "VLD3dAsm_32\0" |
| 11126 | /* 1998 */ "VST3dAsm_32\0" |
| 11127 | /* 2010 */ "VLD4dAsm_32\0" |
| 11128 | /* 2022 */ "VST4dAsm_32\0" |
| 11129 | /* 2034 */ "VLD1LNdAsm_32\0" |
| 11130 | /* 2048 */ "VST1LNdAsm_32\0" |
| 11131 | /* 2062 */ "VLD2LNdAsm_32\0" |
| 11132 | /* 2076 */ "VST2LNdAsm_32\0" |
| 11133 | /* 2090 */ "VLD3LNdAsm_32\0" |
| 11134 | /* 2104 */ "VST3LNdAsm_32\0" |
| 11135 | /* 2118 */ "VLD4LNdAsm_32\0" |
| 11136 | /* 2132 */ "VST4LNdAsm_32\0" |
| 11137 | /* 2146 */ "VLD3DUPdAsm_32\0" |
| 11138 | /* 2161 */ "VLD4DUPdAsm_32\0" |
| 11139 | /* 2176 */ "VLD3qAsm_32\0" |
| 11140 | /* 2188 */ "VST3qAsm_32\0" |
| 11141 | /* 2200 */ "VLD4qAsm_32\0" |
| 11142 | /* 2212 */ "VST4qAsm_32\0" |
| 11143 | /* 2224 */ "VLD2LNqAsm_32\0" |
| 11144 | /* 2238 */ "VST2LNqAsm_32\0" |
| 11145 | /* 2252 */ "VLD3LNqAsm_32\0" |
| 11146 | /* 2266 */ "VST3LNqAsm_32\0" |
| 11147 | /* 2280 */ "VLD4LNqAsm_32\0" |
| 11148 | /* 2294 */ "VST4LNqAsm_32\0" |
| 11149 | /* 2308 */ "VLD3DUPqAsm_32\0" |
| 11150 | /* 2323 */ "VLD4DUPqAsm_32\0" |
| 11151 | /* 2338 */ "VLD2b32\0" |
| 11152 | /* 2346 */ "VST2b32\0" |
| 11153 | /* 2354 */ "VLD1d32\0" |
| 11154 | /* 2362 */ "VST1d32\0" |
| 11155 | /* 2370 */ "VLD2d32\0" |
| 11156 | /* 2378 */ "VST2d32\0" |
| 11157 | /* 2386 */ "VLD3d32\0" |
| 11158 | /* 2394 */ "VST3d32\0" |
| 11159 | /* 2402 */ "VREV64d32\0" |
| 11160 | /* 2412 */ "VLD4d32\0" |
| 11161 | /* 2420 */ "VST4d32\0" |
| 11162 | /* 2428 */ "VLD1LNd32\0" |
| 11163 | /* 2438 */ "VST1LNd32\0" |
| 11164 | /* 2448 */ "VLD2LNd32\0" |
| 11165 | /* 2458 */ "VST2LNd32\0" |
| 11166 | /* 2468 */ "VLD3LNd32\0" |
| 11167 | /* 2478 */ "VST3LNd32\0" |
| 11168 | /* 2488 */ "VLD4LNd32\0" |
| 11169 | /* 2498 */ "VST4LNd32\0" |
| 11170 | /* 2508 */ "VTRNd32\0" |
| 11171 | /* 2516 */ "VLD1DUPd32\0" |
| 11172 | /* 2527 */ "VLD2DUPd32\0" |
| 11173 | /* 2538 */ "VLD3DUPd32\0" |
| 11174 | /* 2549 */ "VLD4DUPd32\0" |
| 11175 | /* 2560 */ "VEXTd32\0" |
| 11176 | /* 2568 */ "VCMLAv2f32\0" |
| 11177 | /* 2579 */ "VCADDv2f32\0" |
| 11178 | /* 2590 */ "VMOVv2f32\0" |
| 11179 | /* 2600 */ "VCGEzv2f32\0" |
| 11180 | /* 2611 */ "VCLEzv2f32\0" |
| 11181 | /* 2622 */ "VCEQzv2f32\0" |
| 11182 | /* 2633 */ "VCGTzv2f32\0" |
| 11183 | /* 2644 */ "VCLTzv2f32\0" |
| 11184 | /* 2655 */ "VCMLAv4f32\0" |
| 11185 | /* 2666 */ "VCADDv4f32\0" |
| 11186 | /* 2677 */ "MVE_VPTv4f32\0" |
| 11187 | /* 2690 */ "VMOVv4f32\0" |
| 11188 | /* 2700 */ "VCGEzv4f32\0" |
| 11189 | /* 2711 */ "VCLEzv4f32\0" |
| 11190 | /* 2722 */ "VCEQzv4f32\0" |
| 11191 | /* 2733 */ "VCGTzv4f32\0" |
| 11192 | /* 2744 */ "VCLTzv4f32\0" |
| 11193 | /* 2755 */ "MVE_VCMLAf32\0" |
| 11194 | /* 2768 */ "MVE_VFMAf32\0" |
| 11195 | /* 2780 */ "MVE_VMINNMAf32\0" |
| 11196 | /* 2795 */ "MVE_VMAXNMAf32\0" |
| 11197 | /* 2810 */ "MVE_VSUBf32\0" |
| 11198 | /* 2822 */ "MVE_VABDf32\0" |
| 11199 | /* 2834 */ "MVE_VCADDf32\0" |
| 11200 | /* 2847 */ "MVE_VADDf32\0" |
| 11201 | /* 2859 */ "MVE_VNEGf32\0" |
| 11202 | /* 2871 */ "MVE_VCMULf32\0" |
| 11203 | /* 2884 */ "MVE_VMULf32\0" |
| 11204 | /* 2896 */ "MVE_VMINNMf32\0" |
| 11205 | /* 2910 */ "MVE_VMAXNMf32\0" |
| 11206 | /* 2924 */ "MVE_VCMPf32\0" |
| 11207 | /* 2936 */ "MVE_VABSf32\0" |
| 11208 | /* 2948 */ "MVE_VFMSf32\0" |
| 11209 | /* 2960 */ "MVE_VFMA_qr_Sf32\0" |
| 11210 | /* 2977 */ "MVE_VMINNMAVf32\0" |
| 11211 | /* 2993 */ "MVE_VMAXNMAVf32\0" |
| 11212 | /* 3009 */ "MVE_VMINNMVf32\0" |
| 11213 | /* 3024 */ "MVE_VMAXNMVf32\0" |
| 11214 | /* 3039 */ "MVE_VFMA_qr_f32\0" |
| 11215 | /* 3055 */ "MVE_VSUB_qr_f32\0" |
| 11216 | /* 3071 */ "MVE_VADD_qr_f32\0" |
| 11217 | /* 3087 */ "MVE_VMUL_qr_f32\0" |
| 11218 | /* 3103 */ "MVE_VMOVimmf32\0" |
| 11219 | /* 3118 */ "VMLAv2i32\0" |
| 11220 | /* 3128 */ "VSUBv2i32\0" |
| 11221 | /* 3138 */ "VADDv2i32\0" |
| 11222 | /* 3148 */ "VQNEGv2i32\0" |
| 11223 | /* 3159 */ "VQRDMLAHv2i32\0" |
| 11224 | /* 3173 */ "VQDMULHv2i32\0" |
| 11225 | /* 3186 */ "VQRDMULHv2i32\0" |
| 11226 | /* 3200 */ "VQRDMLSHv2i32\0" |
| 11227 | /* 3214 */ "VSLIv2i32\0" |
| 11228 | /* 3224 */ "VSRIv2i32\0" |
| 11229 | /* 3234 */ "VMULv2i32\0" |
| 11230 | /* 3244 */ "VRSUBHNv2i32\0" |
| 11231 | /* 3257 */ "VSUBHNv2i32\0" |
| 11232 | /* 3269 */ "VRADDHNv2i32\0" |
| 11233 | /* 3282 */ "VADDHNv2i32\0" |
| 11234 | /* 3294 */ "VRSHRNv2i32\0" |
| 11235 | /* 3306 */ "VSHRNv2i32\0" |
| 11236 | /* 3317 */ "VQSHRUNv2i32\0" |
| 11237 | /* 3330 */ "VQRSHRUNv2i32\0" |
| 11238 | /* 3344 */ "VMVNv2i32\0" |
| 11239 | /* 3354 */ "VMOVNv2i32\0" |
| 11240 | /* 3365 */ "VCEQv2i32\0" |
| 11241 | /* 3375 */ "VQABSv2i32\0" |
| 11242 | /* 3386 */ "VABSv2i32\0" |
| 11243 | /* 3396 */ "VCLSv2i32\0" |
| 11244 | /* 3406 */ "VMLSv2i32\0" |
| 11245 | /* 3416 */ "VTSTv2i32\0" |
| 11246 | /* 3426 */ "VMOVv2i32\0" |
| 11247 | /* 3436 */ "VCLZv2i32\0" |
| 11248 | /* 3446 */ "VBICiv2i32\0" |
| 11249 | /* 3457 */ "VSHLiv2i32\0" |
| 11250 | /* 3468 */ "VORRiv2i32\0" |
| 11251 | /* 3479 */ "VQSHLsiv2i32\0" |
| 11252 | /* 3492 */ "VQSHLuiv2i32\0" |
| 11253 | /* 3505 */ "VMLAslv2i32\0" |
| 11254 | /* 3517 */ "VQRDMLAHslv2i32\0" |
| 11255 | /* 3533 */ "VQDMULHslv2i32\0" |
| 11256 | /* 3548 */ "VQRDMULHslv2i32\0" |
| 11257 | /* 3564 */ "VQRDMLSHslv2i32\0" |
| 11258 | /* 3580 */ "VQDMLALslv2i32\0" |
| 11259 | /* 3595 */ "VQDMULLslv2i32\0" |
| 11260 | /* 3610 */ "VQDMLSLslv2i32\0" |
| 11261 | /* 3625 */ "VMULslv2i32\0" |
| 11262 | /* 3637 */ "VMLSslv2i32\0" |
| 11263 | /* 3649 */ "VABAsv2i32\0" |
| 11264 | /* 3660 */ "VRSRAsv2i32\0" |
| 11265 | /* 3672 */ "VSRAsv2i32\0" |
| 11266 | /* 3683 */ "VHSUBsv2i32\0" |
| 11267 | /* 3695 */ "VQSUBsv2i32\0" |
| 11268 | /* 3707 */ "VABDsv2i32\0" |
| 11269 | /* 3718 */ "VRHADDsv2i32\0" |
| 11270 | /* 3731 */ "VHADDsv2i32\0" |
| 11271 | /* 3743 */ "VQADDsv2i32\0" |
| 11272 | /* 3755 */ "VCGEsv2i32\0" |
| 11273 | /* 3766 */ "VPADALsv2i32\0" |
| 11274 | /* 3779 */ "VPADDLsv2i32\0" |
| 11275 | /* 3792 */ "VQSHLsv2i32\0" |
| 11276 | /* 3804 */ "VQRSHLsv2i32\0" |
| 11277 | /* 3817 */ "VRSHLsv2i32\0" |
| 11278 | /* 3829 */ "VSHLsv2i32\0" |
| 11279 | /* 3840 */ "VMINsv2i32\0" |
| 11280 | /* 3851 */ "VQSHRNsv2i32\0" |
| 11281 | /* 3864 */ "VQRSHRNsv2i32\0" |
| 11282 | /* 3878 */ "VQMOVNsv2i32\0" |
| 11283 | /* 3891 */ "VRSHRsv2i32\0" |
| 11284 | /* 3903 */ "VSHRsv2i32\0" |
| 11285 | /* 3914 */ "VCGTsv2i32\0" |
| 11286 | /* 3925 */ "VMAXsv2i32\0" |
| 11287 | /* 3936 */ "VMLALslsv2i32\0" |
| 11288 | /* 3950 */ "VMULLslsv2i32\0" |
| 11289 | /* 3964 */ "VMLSLslsv2i32\0" |
| 11290 | /* 3978 */ "VABAuv2i32\0" |
| 11291 | /* 3989 */ "VRSRAuv2i32\0" |
| 11292 | /* 4001 */ "VSRAuv2i32\0" |
| 11293 | /* 4012 */ "VHSUBuv2i32\0" |
| 11294 | /* 4024 */ "VQSUBuv2i32\0" |
| 11295 | /* 4036 */ "VABDuv2i32\0" |
| 11296 | /* 4047 */ "VRHADDuv2i32\0" |
| 11297 | /* 4060 */ "VHADDuv2i32\0" |
| 11298 | /* 4072 */ "VQADDuv2i32\0" |
| 11299 | /* 4084 */ "VCGEuv2i32\0" |
| 11300 | /* 4095 */ "VPADALuv2i32\0" |
| 11301 | /* 4108 */ "VPADDLuv2i32\0" |
| 11302 | /* 4121 */ "VQSHLuv2i32\0" |
| 11303 | /* 4133 */ "VQRSHLuv2i32\0" |
| 11304 | /* 4146 */ "VRSHLuv2i32\0" |
| 11305 | /* 4158 */ "VSHLuv2i32\0" |
| 11306 | /* 4169 */ "VMINuv2i32\0" |
| 11307 | /* 4180 */ "VQSHRNuv2i32\0" |
| 11308 | /* 4193 */ "VQRSHRNuv2i32\0" |
| 11309 | /* 4207 */ "VQMOVNuv2i32\0" |
| 11310 | /* 4220 */ "VRSHRuv2i32\0" |
| 11311 | /* 4232 */ "VSHRuv2i32\0" |
| 11312 | /* 4243 */ "VCGTuv2i32\0" |
| 11313 | /* 4254 */ "VMAXuv2i32\0" |
| 11314 | /* 4265 */ "VMLALsluv2i32\0" |
| 11315 | /* 4279 */ "VMULLsluv2i32\0" |
| 11316 | /* 4293 */ "VMLSLsluv2i32\0" |
| 11317 | /* 4307 */ "VQSHLsuv2i32\0" |
| 11318 | /* 4320 */ "VQMOVNsuv2i32\0" |
| 11319 | /* 4334 */ "VCGEzv2i32\0" |
| 11320 | /* 4345 */ "VCLEzv2i32\0" |
| 11321 | /* 4356 */ "VCEQzv2i32\0" |
| 11322 | /* 4367 */ "VCGTzv2i32\0" |
| 11323 | /* 4378 */ "VCLTzv2i32\0" |
| 11324 | /* 4389 */ "VMLAv4i32\0" |
| 11325 | /* 4399 */ "VSUBv4i32\0" |
| 11326 | /* 4409 */ "VADDv4i32\0" |
| 11327 | /* 4419 */ "VQNEGv4i32\0" |
| 11328 | /* 4430 */ "VQRDMLAHv4i32\0" |
| 11329 | /* 4444 */ "VQDMULHv4i32\0" |
| 11330 | /* 4457 */ "VQRDMULHv4i32\0" |
| 11331 | /* 4471 */ "VQRDMLSHv4i32\0" |
| 11332 | /* 4485 */ "VSLIv4i32\0" |
| 11333 | /* 4495 */ "VSRIv4i32\0" |
| 11334 | /* 4505 */ "VQDMLALv4i32\0" |
| 11335 | /* 4518 */ "VQDMULLv4i32\0" |
| 11336 | /* 4531 */ "VQDMLSLv4i32\0" |
| 11337 | /* 4544 */ "VMULv4i32\0" |
| 11338 | /* 4554 */ "VMVNv4i32\0" |
| 11339 | /* 4564 */ "VCEQv4i32\0" |
| 11340 | /* 4574 */ "VQABSv4i32\0" |
| 11341 | /* 4585 */ "VABSv4i32\0" |
| 11342 | /* 4595 */ "VCLSv4i32\0" |
| 11343 | /* 4605 */ "VMLSv4i32\0" |
| 11344 | /* 4615 */ "MVE_VPTv4i32\0" |
| 11345 | /* 4628 */ "VTSTv4i32\0" |
| 11346 | /* 4638 */ "VMOVv4i32\0" |
| 11347 | /* 4648 */ "VCLZv4i32\0" |
| 11348 | /* 4658 */ "VBICiv4i32\0" |
| 11349 | /* 4669 */ "VSHLiv4i32\0" |
| 11350 | /* 4680 */ "VORRiv4i32\0" |
| 11351 | /* 4691 */ "VQSHLsiv4i32\0" |
| 11352 | /* 4704 */ "VQSHLuiv4i32\0" |
| 11353 | /* 4717 */ "VMLAslv4i32\0" |
| 11354 | /* 4729 */ "VQRDMLAHslv4i32\0" |
| 11355 | /* 4745 */ "VQDMULHslv4i32\0" |
| 11356 | /* 4760 */ "VQRDMULHslv4i32\0" |
| 11357 | /* 4776 */ "VQRDMLSHslv4i32\0" |
| 11358 | /* 4792 */ "VMULslv4i32\0" |
| 11359 | /* 4804 */ "VMLSslv4i32\0" |
| 11360 | /* 4816 */ "VABAsv4i32\0" |
| 11361 | /* 4827 */ "VRSRAsv4i32\0" |
| 11362 | /* 4839 */ "VSRAsv4i32\0" |
| 11363 | /* 4850 */ "VHSUBsv4i32\0" |
| 11364 | /* 4862 */ "VQSUBsv4i32\0" |
| 11365 | /* 4874 */ "VABDsv4i32\0" |
| 11366 | /* 4885 */ "VRHADDsv4i32\0" |
| 11367 | /* 4898 */ "VHADDsv4i32\0" |
| 11368 | /* 4910 */ "VQADDsv4i32\0" |
| 11369 | /* 4922 */ "VCGEsv4i32\0" |
| 11370 | /* 4933 */ "VABALsv4i32\0" |
| 11371 | /* 4945 */ "VPADALsv4i32\0" |
| 11372 | /* 4958 */ "VMLALsv4i32\0" |
| 11373 | /* 4970 */ "VSUBLsv4i32\0" |
| 11374 | /* 4982 */ "VABDLsv4i32\0" |
| 11375 | /* 4994 */ "VPADDLsv4i32\0" |
| 11376 | /* 5007 */ "VADDLsv4i32\0" |
| 11377 | /* 5019 */ "VQSHLsv4i32\0" |
| 11378 | /* 5031 */ "VQRSHLsv4i32\0" |
| 11379 | /* 5044 */ "VRSHLsv4i32\0" |
| 11380 | /* 5056 */ "VSHLsv4i32\0" |
| 11381 | /* 5067 */ "VSHLLsv4i32\0" |
| 11382 | /* 5079 */ "VMULLsv4i32\0" |
| 11383 | /* 5091 */ "VMLSLsv4i32\0" |
| 11384 | /* 5103 */ "VMOVLsv4i32\0" |
| 11385 | /* 5115 */ "VMINsv4i32\0" |
| 11386 | /* 5126 */ "VRSHRsv4i32\0" |
| 11387 | /* 5138 */ "VSHRsv4i32\0" |
| 11388 | /* 5149 */ "VCGTsv4i32\0" |
| 11389 | /* 5160 */ "VSUBWsv4i32\0" |
| 11390 | /* 5172 */ "VADDWsv4i32\0" |
| 11391 | /* 5184 */ "VMAXsv4i32\0" |
| 11392 | /* 5195 */ "VABAuv4i32\0" |
| 11393 | /* 5206 */ "VRSRAuv4i32\0" |
| 11394 | /* 5218 */ "VSRAuv4i32\0" |
| 11395 | /* 5229 */ "VHSUBuv4i32\0" |
| 11396 | /* 5241 */ "VQSUBuv4i32\0" |
| 11397 | /* 5253 */ "VABDuv4i32\0" |
| 11398 | /* 5264 */ "VRHADDuv4i32\0" |
| 11399 | /* 5277 */ "VHADDuv4i32\0" |
| 11400 | /* 5289 */ "VQADDuv4i32\0" |
| 11401 | /* 5301 */ "VCGEuv4i32\0" |
| 11402 | /* 5312 */ "VABALuv4i32\0" |
| 11403 | /* 5324 */ "VPADALuv4i32\0" |
| 11404 | /* 5337 */ "VMLALuv4i32\0" |
| 11405 | /* 5349 */ "VSUBLuv4i32\0" |
| 11406 | /* 5361 */ "VABDLuv4i32\0" |
| 11407 | /* 5373 */ "VPADDLuv4i32\0" |
| 11408 | /* 5386 */ "VADDLuv4i32\0" |
| 11409 | /* 5398 */ "VQSHLuv4i32\0" |
| 11410 | /* 5410 */ "VQRSHLuv4i32\0" |
| 11411 | /* 5423 */ "VRSHLuv4i32\0" |
| 11412 | /* 5435 */ "VSHLuv4i32\0" |
| 11413 | /* 5446 */ "VSHLLuv4i32\0" |
| 11414 | /* 5458 */ "VMULLuv4i32\0" |
| 11415 | /* 5470 */ "VMLSLuv4i32\0" |
| 11416 | /* 5482 */ "VMOVLuv4i32\0" |
| 11417 | /* 5494 */ "VMINuv4i32\0" |
| 11418 | /* 5505 */ "VRSHRuv4i32\0" |
| 11419 | /* 5517 */ "VSHRuv4i32\0" |
| 11420 | /* 5528 */ "VCGTuv4i32\0" |
| 11421 | /* 5539 */ "VSUBWuv4i32\0" |
| 11422 | /* 5551 */ "VADDWuv4i32\0" |
| 11423 | /* 5563 */ "VMAXuv4i32\0" |
| 11424 | /* 5574 */ "VQSHLsuv4i32\0" |
| 11425 | /* 5587 */ "VCGEzv4i32\0" |
| 11426 | /* 5598 */ "VCLEzv4i32\0" |
| 11427 | /* 5609 */ "VCEQzv4i32\0" |
| 11428 | /* 5620 */ "VCGTzv4i32\0" |
| 11429 | /* 5631 */ "VCLTzv4i32\0" |
| 11430 | /* 5642 */ "MVE_VSUBi32\0" |
| 11431 | /* 5654 */ "MVE_VCADDi32\0" |
| 11432 | /* 5667 */ "VPADDi32\0" |
| 11433 | /* 5676 */ "MVE_VADDi32\0" |
| 11434 | /* 5688 */ "MVE_VQDMULHi32\0" |
| 11435 | /* 5703 */ "MVE_VQRDMULHi32\0" |
| 11436 | /* 5719 */ "VSHLLi32\0" |
| 11437 | /* 5728 */ "MVE_VMULi32\0" |
| 11438 | /* 5740 */ "VGETLNi32\0" |
| 11439 | /* 5750 */ "VSETLNi32\0" |
| 11440 | /* 5760 */ "MVE_VCMPi32\0" |
| 11441 | /* 5772 */ "MVE_VMLA_qr_i32\0" |
| 11442 | /* 5788 */ "MVE_VSUB_qr_i32\0" |
| 11443 | /* 5804 */ "MVE_VADD_qr_i32\0" |
| 11444 | /* 5820 */ "MVE_VMUL_qr_i32\0" |
| 11445 | /* 5836 */ "MVE_VMLAS_qr_i32\0" |
| 11446 | /* 5853 */ "MVE_VBICimmi32\0" |
| 11447 | /* 5868 */ "MVE_VMVNimmi32\0" |
| 11448 | /* 5883 */ "MVE_VORRimmi32\0" |
| 11449 | /* 5898 */ "MVE_VMOVimmi32\0" |
| 11450 | /* 5913 */ "MVE_VSHL_immi32\0" |
| 11451 | /* 5929 */ "MVE_VSLIimm32\0" |
| 11452 | /* 5943 */ "MVE_VSRIimm32\0" |
| 11453 | /* 5957 */ "VLD1q32\0" |
| 11454 | /* 5965 */ "VST1q32\0" |
| 11455 | /* 5973 */ "VLD2q32\0" |
| 11456 | /* 5981 */ "VST2q32\0" |
| 11457 | /* 5989 */ "VLD3q32\0" |
| 11458 | /* 5997 */ "VST3q32\0" |
| 11459 | /* 6005 */ "VREV64q32\0" |
| 11460 | /* 6015 */ "VLD4q32\0" |
| 11461 | /* 6023 */ "VST4q32\0" |
| 11462 | /* 6031 */ "VLD2LNq32\0" |
| 11463 | /* 6041 */ "VST2LNq32\0" |
| 11464 | /* 6051 */ "VLD3LNq32\0" |
| 11465 | /* 6061 */ "VST3LNq32\0" |
| 11466 | /* 6071 */ "VLD4LNq32\0" |
| 11467 | /* 6081 */ "VST4LNq32\0" |
| 11468 | /* 6091 */ "VTRNq32\0" |
| 11469 | /* 6099 */ "VZIPq32\0" |
| 11470 | /* 6107 */ "VLD1DUPq32\0" |
| 11471 | /* 6118 */ "VLD3DUPq32\0" |
| 11472 | /* 6129 */ "VLD4DUPq32\0" |
| 11473 | /* 6140 */ "VUZPq32\0" |
| 11474 | /* 6148 */ "VEXTq32\0" |
| 11475 | /* 6156 */ "MVE_VPTv4s32\0" |
| 11476 | /* 6169 */ "MVE_VMINAs32\0" |
| 11477 | /* 6182 */ "MVE_VMAXAs32\0" |
| 11478 | /* 6195 */ "MVE_VMULLBs32\0" |
| 11479 | /* 6209 */ "MVE_VHSUBs32\0" |
| 11480 | /* 6222 */ "MVE_VQSUBs32\0" |
| 11481 | /* 6235 */ "MVE_VABDs32\0" |
| 11482 | /* 6247 */ "MVE_VHCADDs32\0" |
| 11483 | /* 6261 */ "MVE_VRHADDs32\0" |
| 11484 | /* 6275 */ "MVE_VHADDs32\0" |
| 11485 | /* 6288 */ "MVE_VQADDs32\0" |
| 11486 | /* 6301 */ "MVE_VQNEGs32\0" |
| 11487 | /* 6314 */ "MVE_VNEGs32\0" |
| 11488 | /* 6326 */ "MVE_VQDMLADHs32\0" |
| 11489 | /* 6342 */ "MVE_VQRDMLADHs32\0" |
| 11490 | /* 6359 */ "MVE_VQDMLSDHs32\0" |
| 11491 | /* 6375 */ "MVE_VQRDMLSDHs32\0" |
| 11492 | /* 6392 */ "MVE_VRMULHs32\0" |
| 11493 | /* 6406 */ "MVE_VMULHs32\0" |
| 11494 | /* 6419 */ "MVE_VRMLALDAVHs32\0" |
| 11495 | /* 6437 */ "MVE_VRMLSLDAVHs32\0" |
| 11496 | /* 6455 */ "VPMINs32\0" |
| 11497 | /* 6464 */ "MVE_VMINs32\0" |
| 11498 | /* 6476 */ "MVE_VCMPs32\0" |
| 11499 | /* 6488 */ "MVE_VQABSs32\0" |
| 11500 | /* 6501 */ "MVE_VABSs32\0" |
| 11501 | /* 6513 */ "MVE_VCLSs32\0" |
| 11502 | /* 6525 */ "MVE_VMULLTs32\0" |
| 11503 | /* 6539 */ "MVE_VABAVs32\0" |
| 11504 | /* 6552 */ "MVE_VMLADAVs32\0" |
| 11505 | /* 6567 */ "MVE_VMLALDAVs32\0" |
| 11506 | /* 6583 */ "MVE_VMLSLDAVs32\0" |
| 11507 | /* 6599 */ "MVE_VMLSDAVs32\0" |
| 11508 | /* 6614 */ "MVE_VMINAVs32\0" |
| 11509 | /* 6628 */ "MVE_VMAXAVs32\0" |
| 11510 | /* 6642 */ "MVE_VMINVs32\0" |
| 11511 | /* 6655 */ "MVE_VMAXVs32\0" |
| 11512 | /* 6668 */ "VPMAXs32\0" |
| 11513 | /* 6677 */ "MVE_VMAXs32\0" |
| 11514 | /* 6689 */ "MVE_VQDMLADHXs32\0" |
| 11515 | /* 6706 */ "MVE_VQRDMLADHXs32\0" |
| 11516 | /* 6724 */ "MVE_VQDMLSDHXs32\0" |
| 11517 | /* 6741 */ "MVE_VQRDMLSDHXs32\0" |
| 11518 | /* 6759 */ "MVE_VCLZs32\0" |
| 11519 | /* 6771 */ "MVE_VHSUB_qr_s32\0" |
| 11520 | /* 6788 */ "MVE_VQSUB_qr_s32\0" |
| 11521 | /* 6805 */ "MVE_VHADD_qr_s32\0" |
| 11522 | /* 6822 */ "MVE_VQADD_qr_s32\0" |
| 11523 | /* 6839 */ "MVE_VQDMULH_qr_s32\0" |
| 11524 | /* 6858 */ "MVE_VQRDMULH_qr_s32\0" |
| 11525 | /* 6878 */ "MVE_VRMLALDAVHas32\0" |
| 11526 | /* 6897 */ "MVE_VRMLSLDAVHas32\0" |
| 11527 | /* 6916 */ "MVE_VMLADAVas32\0" |
| 11528 | /* 6932 */ "MVE_VMLALDAVas32\0" |
| 11529 | /* 6949 */ "MVE_VMLSLDAVas32\0" |
| 11530 | /* 6966 */ "MVE_VMLSDAVas32\0" |
| 11531 | /* 6982 */ "MVE_VQSHL_by_vecs32\0" |
| 11532 | /* 7002 */ "MVE_VQRSHL_by_vecs32\0" |
| 11533 | /* 7023 */ "MVE_VRSHL_by_vecs32\0" |
| 11534 | /* 7043 */ "MVE_VSHL_by_vecs32\0" |
| 11535 | /* 7062 */ "MVE_VQSHRNbhs32\0" |
| 11536 | /* 7078 */ "MVE_VQRSHRNbhs32\0" |
| 11537 | /* 7095 */ "MVE_VQSHRNths32\0" |
| 11538 | /* 7111 */ "MVE_VQRSHRNths32\0" |
| 11539 | /* 7128 */ "MVE_VQSHLimms32\0" |
| 11540 | /* 7144 */ "MVE_VRSHR_imms32\0" |
| 11541 | /* 7161 */ "MVE_VSHR_imms32\0" |
| 11542 | /* 7177 */ "MVE_VQSHLU_imms32\0" |
| 11543 | /* 7195 */ "MVE_VQDMLAH_qrs32\0" |
| 11544 | /* 7213 */ "MVE_VQRDMLAH_qrs32\0" |
| 11545 | /* 7232 */ "MVE_VQDMLASH_qrs32\0" |
| 11546 | /* 7251 */ "MVE_VQRDMLASH_qrs32\0" |
| 11547 | /* 7271 */ "MVE_VQSHL_qrs32\0" |
| 11548 | /* 7287 */ "MVE_VQRSHL_qrs32\0" |
| 11549 | /* 7304 */ "MVE_VRSHL_qrs32\0" |
| 11550 | /* 7320 */ "MVE_VSHL_qrs32\0" |
| 11551 | /* 7335 */ "MVE_VRMLALDAVHxs32\0" |
| 11552 | /* 7354 */ "MVE_VRMLSLDAVHxs32\0" |
| 11553 | /* 7373 */ "MVE_VMLADAVxs32\0" |
| 11554 | /* 7389 */ "MVE_VMLALDAVxs32\0" |
| 11555 | /* 7406 */ "MVE_VMLSLDAVxs32\0" |
| 11556 | /* 7423 */ "MVE_VMLSDAVxs32\0" |
| 11557 | /* 7439 */ "MVE_VRMLALDAVHaxs32\0" |
| 11558 | /* 7459 */ "MVE_VRMLSLDAVHaxs32\0" |
| 11559 | /* 7479 */ "MVE_VMLADAVaxs32\0" |
| 11560 | /* 7496 */ "MVE_VMLALDAVaxs32\0" |
| 11561 | /* 7514 */ "MVE_VMLSLDAVaxs32\0" |
| 11562 | /* 7532 */ "MVE_VMLSDAVaxs32\0" |
| 11563 | /* 7549 */ "MVE_VPTv4u32\0" |
| 11564 | /* 7562 */ "MVE_VMULLBu32\0" |
| 11565 | /* 7576 */ "MVE_VHSUBu32\0" |
| 11566 | /* 7589 */ "MVE_VQSUBu32\0" |
| 11567 | /* 7602 */ "MVE_VABDu32\0" |
| 11568 | /* 7614 */ "MVE_VRHADDu32\0" |
| 11569 | /* 7628 */ "MVE_VHADDu32\0" |
| 11570 | /* 7641 */ "MVE_VQADDu32\0" |
| 11571 | /* 7654 */ "MVE_VRMULHu32\0" |
| 11572 | /* 7668 */ "MVE_VMULHu32\0" |
| 11573 | /* 7681 */ "MVE_VRMLALDAVHu32\0" |
| 11574 | /* 7699 */ "VPMINu32\0" |
| 11575 | /* 7708 */ "MVE_VMINu32\0" |
| 11576 | /* 7720 */ "MVE_VCMPu32\0" |
| 11577 | /* 7732 */ "MVE_VDDUPu32\0" |
| 11578 | /* 7745 */ "MVE_VIDUPu32\0" |
| 11579 | /* 7758 */ "MVE_VDWDUPu32\0" |
| 11580 | /* 7772 */ "MVE_VIWDUPu32\0" |
| 11581 | /* 7786 */ "MVE_VMULLTu32\0" |
| 11582 | /* 7800 */ "MVE_VABAVu32\0" |
| 11583 | /* 7813 */ "MVE_VMLADAVu32\0" |
| 11584 | /* 7828 */ "MVE_VMLALDAVu32\0" |
| 11585 | /* 7844 */ "MVE_VMINVu32\0" |
| 11586 | /* 7857 */ "MVE_VMAXVu32\0" |
| 11587 | /* 7870 */ "VPMAXu32\0" |
| 11588 | /* 7879 */ "MVE_VMAXu32\0" |
| 11589 | /* 7891 */ "MVE_VHSUB_qr_u32\0" |
| 11590 | /* 7908 */ "MVE_VQSUB_qr_u32\0" |
| 11591 | /* 7925 */ "MVE_VHADD_qr_u32\0" |
| 11592 | /* 7942 */ "MVE_VQADD_qr_u32\0" |
| 11593 | /* 7959 */ "MVE_VRMLALDAVHau32\0" |
| 11594 | /* 7978 */ "MVE_VMLADAVau32\0" |
| 11595 | /* 7994 */ "MVE_VMLALDAVau32\0" |
| 11596 | /* 8011 */ "MVE_VQSHL_by_vecu32\0" |
| 11597 | /* 8031 */ "MVE_VQRSHL_by_vecu32\0" |
| 11598 | /* 8052 */ "MVE_VRSHL_by_vecu32\0" |
| 11599 | /* 8072 */ "MVE_VSHL_by_vecu32\0" |
| 11600 | /* 8091 */ "MVE_VQSHRNbhu32\0" |
| 11601 | /* 8107 */ "MVE_VQRSHRNbhu32\0" |
| 11602 | /* 8124 */ "MVE_VQSHRNthu32\0" |
| 11603 | /* 8140 */ "MVE_VQRSHRNthu32\0" |
| 11604 | /* 8157 */ "MVE_VQSHLimmu32\0" |
| 11605 | /* 8173 */ "MVE_VRSHR_immu32\0" |
| 11606 | /* 8190 */ "MVE_VSHR_immu32\0" |
| 11607 | /* 8206 */ "MVE_VQSHL_qru32\0" |
| 11608 | /* 8222 */ "MVE_VQRSHL_qru32\0" |
| 11609 | /* 8239 */ "MVE_VRSHL_qru32\0" |
| 11610 | /* 8255 */ "MVE_VSHL_qru32\0" |
| 11611 | /* 8270 */ "t2MRC2\0" |
| 11612 | /* 8277 */ "t2MRRC2\0" |
| 11613 | /* 8285 */ "G_FLOG2\0" |
| 11614 | /* 8293 */ "SHA256H2\0" |
| 11615 | /* 8302 */ "VTBL2\0" |
| 11616 | /* 8308 */ "t2CDP2\0" |
| 11617 | /* 8315 */ "PseudoARMInitUndefDPR_VFP2\0" |
| 11618 | /* 8342 */ "G_FEXP2\0" |
| 11619 | /* 8350 */ "t2MCR2\0" |
| 11620 | /* 8357 */ "VMRS_MVFR2\0" |
| 11621 | /* 8368 */ "t2MCRR2\0" |
| 11622 | /* 8376 */ "t2DCPS2\0" |
| 11623 | /* 8384 */ "VMSR_FPINST2\0" |
| 11624 | /* 8397 */ "VMRS_FPINST2\0" |
| 11625 | /* 8410 */ "VLLDM_T2\0" |
| 11626 | /* 8419 */ "VLSTM_T2\0" |
| 11627 | /* 8428 */ "VTBX2\0" |
| 11628 | /* 8434 */ "CDE_CX2\0" |
| 11629 | /* 8442 */ "VLD2DUPd32x2\0" |
| 11630 | /* 8455 */ "VLD2DUPd16x2\0" |
| 11631 | /* 8468 */ "VLD2DUPd8x2\0" |
| 11632 | /* 8480 */ "VTBL3\0" |
| 11633 | /* 8486 */ "t2DCPS3\0" |
| 11634 | /* 8494 */ "VTBX3\0" |
| 11635 | /* 8500 */ "CDE_CX3\0" |
| 11636 | /* 8508 */ "tSUBi3\0" |
| 11637 | /* 8515 */ "tADDi3\0" |
| 11638 | /* 8522 */ "tSUBSi3\0" |
| 11639 | /* 8530 */ "tADDSi3\0" |
| 11640 | /* 8538 */ "MVE_VCTP64\0" |
| 11641 | /* 8549 */ "CMP_SWAP_64\0" |
| 11642 | /* 8561 */ "MVE_DLSTP_64\0" |
| 11643 | /* 8574 */ "MVE_WLSTP_64\0" |
| 11644 | /* 8587 */ "VLD1d64\0" |
| 11645 | /* 8595 */ "VST1d64\0" |
| 11646 | /* 8603 */ "VSUBv1i64\0" |
| 11647 | /* 8613 */ "VADDv1i64\0" |
| 11648 | /* 8623 */ "VSLIv1i64\0" |
| 11649 | /* 8633 */ "VSRIv1i64\0" |
| 11650 | /* 8643 */ "VMOVv1i64\0" |
| 11651 | /* 8653 */ "VSHLiv1i64\0" |
| 11652 | /* 8664 */ "VQSHLsiv1i64\0" |
| 11653 | /* 8677 */ "VQSHLuiv1i64\0" |
| 11654 | /* 8690 */ "VRSRAsv1i64\0" |
| 11655 | /* 8702 */ "VSRAsv1i64\0" |
| 11656 | /* 8713 */ "VQSUBsv1i64\0" |
| 11657 | /* 8725 */ "VQADDsv1i64\0" |
| 11658 | /* 8737 */ "VQSHLsv1i64\0" |
| 11659 | /* 8749 */ "VQRSHLsv1i64\0" |
| 11660 | /* 8762 */ "VRSHLsv1i64\0" |
| 11661 | /* 8774 */ "VSHLsv1i64\0" |
| 11662 | /* 8785 */ "VRSHRsv1i64\0" |
| 11663 | /* 8797 */ "VSHRsv1i64\0" |
| 11664 | /* 8808 */ "VRSRAuv1i64\0" |
| 11665 | /* 8820 */ "VSRAuv1i64\0" |
| 11666 | /* 8831 */ "VQSUBuv1i64\0" |
| 11667 | /* 8843 */ "VQADDuv1i64\0" |
| 11668 | /* 8855 */ "VQSHLuv1i64\0" |
| 11669 | /* 8867 */ "VQRSHLuv1i64\0" |
| 11670 | /* 8880 */ "VRSHLuv1i64\0" |
| 11671 | /* 8892 */ "VSHLuv1i64\0" |
| 11672 | /* 8903 */ "VRSHRuv1i64\0" |
| 11673 | /* 8915 */ "VSHRuv1i64\0" |
| 11674 | /* 8926 */ "VQSHLsuv1i64\0" |
| 11675 | /* 8939 */ "VSUBv2i64\0" |
| 11676 | /* 8949 */ "VADDv2i64\0" |
| 11677 | /* 8959 */ "VSLIv2i64\0" |
| 11678 | /* 8969 */ "VSRIv2i64\0" |
| 11679 | /* 8979 */ "VQDMLALv2i64\0" |
| 11680 | /* 8992 */ "VQDMULLv2i64\0" |
| 11681 | /* 9005 */ "VQDMLSLv2i64\0" |
| 11682 | /* 9018 */ "VMOVv2i64\0" |
| 11683 | /* 9028 */ "VSHLiv2i64\0" |
| 11684 | /* 9039 */ "VQSHLsiv2i64\0" |
| 11685 | /* 9052 */ "VQSHLuiv2i64\0" |
| 11686 | /* 9065 */ "VRSRAsv2i64\0" |
| 11687 | /* 9077 */ "VSRAsv2i64\0" |
| 11688 | /* 9088 */ "VQSUBsv2i64\0" |
| 11689 | /* 9100 */ "VQADDsv2i64\0" |
| 11690 | /* 9112 */ "VABALsv2i64\0" |
| 11691 | /* 9124 */ "VMLALsv2i64\0" |
| 11692 | /* 9136 */ "VSUBLsv2i64\0" |
| 11693 | /* 9148 */ "VABDLsv2i64\0" |
| 11694 | /* 9160 */ "VADDLsv2i64\0" |
| 11695 | /* 9172 */ "VQSHLsv2i64\0" |
| 11696 | /* 9184 */ "VQRSHLsv2i64\0" |
| 11697 | /* 9197 */ "VRSHLsv2i64\0" |
| 11698 | /* 9209 */ "VSHLsv2i64\0" |
| 11699 | /* 9220 */ "VSHLLsv2i64\0" |
| 11700 | /* 9232 */ "VMULLsv2i64\0" |
| 11701 | /* 9244 */ "VMLSLsv2i64\0" |
| 11702 | /* 9256 */ "VMOVLsv2i64\0" |
| 11703 | /* 9268 */ "VRSHRsv2i64\0" |
| 11704 | /* 9280 */ "VSHRsv2i64\0" |
| 11705 | /* 9291 */ "VSUBWsv2i64\0" |
| 11706 | /* 9303 */ "VADDWsv2i64\0" |
| 11707 | /* 9315 */ "VRSRAuv2i64\0" |
| 11708 | /* 9327 */ "VSRAuv2i64\0" |
| 11709 | /* 9338 */ "VQSUBuv2i64\0" |
| 11710 | /* 9350 */ "VQADDuv2i64\0" |
| 11711 | /* 9362 */ "VABALuv2i64\0" |
| 11712 | /* 9374 */ "VMLALuv2i64\0" |
| 11713 | /* 9386 */ "VSUBLuv2i64\0" |
| 11714 | /* 9398 */ "VABDLuv2i64\0" |
| 11715 | /* 9410 */ "VADDLuv2i64\0" |
| 11716 | /* 9422 */ "VQSHLuv2i64\0" |
| 11717 | /* 9434 */ "VQRSHLuv2i64\0" |
| 11718 | /* 9447 */ "VRSHLuv2i64\0" |
| 11719 | /* 9459 */ "VSHLuv2i64\0" |
| 11720 | /* 9470 */ "VSHLLuv2i64\0" |
| 11721 | /* 9482 */ "VMULLuv2i64\0" |
| 11722 | /* 9494 */ "VMLSLuv2i64\0" |
| 11723 | /* 9506 */ "VMOVLuv2i64\0" |
| 11724 | /* 9518 */ "VRSHRuv2i64\0" |
| 11725 | /* 9530 */ "VSHRuv2i64\0" |
| 11726 | /* 9541 */ "VSUBWuv2i64\0" |
| 11727 | /* 9553 */ "VADDWuv2i64\0" |
| 11728 | /* 9565 */ "VQSHLsuv2i64\0" |
| 11729 | /* 9578 */ "BCCi64\0" |
| 11730 | /* 9585 */ "BCCZi64\0" |
| 11731 | /* 9593 */ "MVE_VMOVimmi64\0" |
| 11732 | /* 9608 */ "VMULLp64\0" |
| 11733 | /* 9617 */ "VLD1q64\0" |
| 11734 | /* 9625 */ "VST1q64\0" |
| 11735 | /* 9633 */ "VEXTq64\0" |
| 11736 | /* 9641 */ "VTBL4\0" |
| 11737 | /* 9647 */ "VTBX4\0" |
| 11738 | /* 9653 */ "TAILJMPr4\0" |
| 11739 | /* 9663 */ "MLAv5\0" |
| 11740 | /* 9669 */ "SMLALv5\0" |
| 11741 | /* 9677 */ "UMLALv5\0" |
| 11742 | /* 9685 */ "SMULLv5\0" |
| 11743 | /* 9693 */ "UMULLv5\0" |
| 11744 | /* 9701 */ "MULv5\0" |
| 11745 | /* 9707 */ "t2SXTAB16\0" |
| 11746 | /* 9717 */ "t2UXTAB16\0" |
| 11747 | /* 9727 */ "MVE_VSTRB16\0" |
| 11748 | /* 9739 */ "t2SXTB16\0" |
| 11749 | /* 9748 */ "t2UXTB16\0" |
| 11750 | /* 9757 */ "t2SHSUB16\0" |
| 11751 | /* 9767 */ "t2UHSUB16\0" |
| 11752 | /* 9777 */ "t2QSUB16\0" |
| 11753 | /* 9786 */ "t2UQSUB16\0" |
| 11754 | /* 9796 */ "t2SSUB16\0" |
| 11755 | /* 9805 */ "t2USUB16\0" |
| 11756 | /* 9814 */ "t2SHADD16\0" |
| 11757 | /* 9824 */ "t2UHADD16\0" |
| 11758 | /* 9834 */ "t2QADD16\0" |
| 11759 | /* 9843 */ "t2UQADD16\0" |
| 11760 | /* 9853 */ "t2SADD16\0" |
| 11761 | /* 9862 */ "t2UADD16\0" |
| 11762 | /* 9871 */ "MVE_VCTP16\0" |
| 11763 | /* 9882 */ "MVE_VDUP16\0" |
| 11764 | /* 9893 */ "MVE_VBRSR16\0" |
| 11765 | /* 9905 */ "MVE_VLDRBS16\0" |
| 11766 | /* 9918 */ "t2SSAT16\0" |
| 11767 | /* 9927 */ "t2USAT16\0" |
| 11768 | /* 9936 */ "MVE_VLDRBU16\0" |
| 11769 | /* 9949 */ "MVE_VLDRHU16\0" |
| 11770 | /* 9962 */ "MVE_VSTRHU16\0" |
| 11771 | /* 9975 */ "t2REV16\0" |
| 11772 | /* 9983 */ "tREV16\0" |
| 11773 | /* 9990 */ "MVE_VLD20_16\0" |
| 11774 | /* 10003 */ "MVE_VST20_16\0" |
| 11775 | /* 10016 */ "MVE_VLD40_16\0" |
| 11776 | /* 10029 */ "MVE_VST40_16\0" |
| 11777 | /* 10042 */ "MVE_VLD21_16\0" |
| 11778 | /* 10055 */ "MVE_VST21_16\0" |
| 11779 | /* 10068 */ "MVE_VLD41_16\0" |
| 11780 | /* 10081 */ "MVE_VST41_16\0" |
| 11781 | /* 10094 */ "MVE_VREV32_16\0" |
| 11782 | /* 10108 */ "MVE_VLD42_16\0" |
| 11783 | /* 10121 */ "MVE_VST42_16\0" |
| 11784 | /* 10134 */ "MVE_VLD43_16\0" |
| 11785 | /* 10147 */ "MVE_VST43_16\0" |
| 11786 | /* 10160 */ "MVE_VREV64_16\0" |
| 11787 | /* 10174 */ "tCMP_SWAP_16\0" |
| 11788 | /* 10187 */ "MVE_DLSTP_16\0" |
| 11789 | /* 10200 */ "MVE_WLSTP_16\0" |
| 11790 | /* 10213 */ "MVE_VMOV_to_lane_16\0" |
| 11791 | /* 10233 */ "VLD3dWB_fixed_Asm_16\0" |
| 11792 | /* 10254 */ "VST3dWB_fixed_Asm_16\0" |
| 11793 | /* 10275 */ "VLD4dWB_fixed_Asm_16\0" |
| 11794 | /* 10296 */ "VST4dWB_fixed_Asm_16\0" |
| 11795 | /* 10317 */ "VLD1LNdWB_fixed_Asm_16\0" |
| 11796 | /* 10340 */ "VST1LNdWB_fixed_Asm_16\0" |
| 11797 | /* 10363 */ "VLD2LNdWB_fixed_Asm_16\0" |
| 11798 | /* 10386 */ "VST2LNdWB_fixed_Asm_16\0" |
| 11799 | /* 10409 */ "VLD3LNdWB_fixed_Asm_16\0" |
| 11800 | /* 10432 */ "VST3LNdWB_fixed_Asm_16\0" |
| 11801 | /* 10455 */ "VLD4LNdWB_fixed_Asm_16\0" |
| 11802 | /* 10478 */ "VST4LNdWB_fixed_Asm_16\0" |
| 11803 | /* 10501 */ "VLD3DUPdWB_fixed_Asm_16\0" |
| 11804 | /* 10525 */ "VLD4DUPdWB_fixed_Asm_16\0" |
| 11805 | /* 10549 */ "VLD3qWB_fixed_Asm_16\0" |
| 11806 | /* 10570 */ "VST3qWB_fixed_Asm_16\0" |
| 11807 | /* 10591 */ "VLD4qWB_fixed_Asm_16\0" |
| 11808 | /* 10612 */ "VST4qWB_fixed_Asm_16\0" |
| 11809 | /* 10633 */ "VLD2LNqWB_fixed_Asm_16\0" |
| 11810 | /* 10656 */ "VST2LNqWB_fixed_Asm_16\0" |
| 11811 | /* 10679 */ "VLD3LNqWB_fixed_Asm_16\0" |
| 11812 | /* 10702 */ "VST3LNqWB_fixed_Asm_16\0" |
| 11813 | /* 10725 */ "VLD4LNqWB_fixed_Asm_16\0" |
| 11814 | /* 10748 */ "VST4LNqWB_fixed_Asm_16\0" |
| 11815 | /* 10771 */ "VLD3DUPqWB_fixed_Asm_16\0" |
| 11816 | /* 10795 */ "VLD4DUPqWB_fixed_Asm_16\0" |
| 11817 | /* 10819 */ "VLD3dWB_register_Asm_16\0" |
| 11818 | /* 10843 */ "VST3dWB_register_Asm_16\0" |
| 11819 | /* 10867 */ "VLD4dWB_register_Asm_16\0" |
| 11820 | /* 10891 */ "VST4dWB_register_Asm_16\0" |
| 11821 | /* 10915 */ "VLD1LNdWB_register_Asm_16\0" |
| 11822 | /* 10941 */ "VST1LNdWB_register_Asm_16\0" |
| 11823 | /* 10967 */ "VLD2LNdWB_register_Asm_16\0" |
| 11824 | /* 10993 */ "VST2LNdWB_register_Asm_16\0" |
| 11825 | /* 11019 */ "VLD3LNdWB_register_Asm_16\0" |
| 11826 | /* 11045 */ "VST3LNdWB_register_Asm_16\0" |
| 11827 | /* 11071 */ "VLD4LNdWB_register_Asm_16\0" |
| 11828 | /* 11097 */ "VST4LNdWB_register_Asm_16\0" |
| 11829 | /* 11123 */ "VLD3DUPdWB_register_Asm_16\0" |
| 11830 | /* 11150 */ "VLD4DUPdWB_register_Asm_16\0" |
| 11831 | /* 11177 */ "VLD3qWB_register_Asm_16\0" |
| 11832 | /* 11201 */ "VST3qWB_register_Asm_16\0" |
| 11833 | /* 11225 */ "VLD4qWB_register_Asm_16\0" |
| 11834 | /* 11249 */ "VST4qWB_register_Asm_16\0" |
| 11835 | /* 11273 */ "VLD2LNqWB_register_Asm_16\0" |
| 11836 | /* 11299 */ "VST2LNqWB_register_Asm_16\0" |
| 11837 | /* 11325 */ "VLD3LNqWB_register_Asm_16\0" |
| 11838 | /* 11351 */ "VST3LNqWB_register_Asm_16\0" |
| 11839 | /* 11377 */ "VLD4LNqWB_register_Asm_16\0" |
| 11840 | /* 11403 */ "VST4LNqWB_register_Asm_16\0" |
| 11841 | /* 11429 */ "VLD3DUPqWB_register_Asm_16\0" |
| 11842 | /* 11456 */ "VLD4DUPqWB_register_Asm_16\0" |
| 11843 | /* 11483 */ "VLD3dAsm_16\0" |
| 11844 | /* 11495 */ "VST3dAsm_16\0" |
| 11845 | /* 11507 */ "VLD4dAsm_16\0" |
| 11846 | /* 11519 */ "VST4dAsm_16\0" |
| 11847 | /* 11531 */ "VLD1LNdAsm_16\0" |
| 11848 | /* 11545 */ "VST1LNdAsm_16\0" |
| 11849 | /* 11559 */ "VLD2LNdAsm_16\0" |
| 11850 | /* 11573 */ "VST2LNdAsm_16\0" |
| 11851 | /* 11587 */ "VLD3LNdAsm_16\0" |
| 11852 | /* 11601 */ "VST3LNdAsm_16\0" |
| 11853 | /* 11615 */ "VLD4LNdAsm_16\0" |
| 11854 | /* 11629 */ "VST4LNdAsm_16\0" |
| 11855 | /* 11643 */ "VLD3DUPdAsm_16\0" |
| 11856 | /* 11658 */ "VLD4DUPdAsm_16\0" |
| 11857 | /* 11673 */ "VLD3qAsm_16\0" |
| 11858 | /* 11685 */ "VST3qAsm_16\0" |
| 11859 | /* 11697 */ "VLD4qAsm_16\0" |
| 11860 | /* 11709 */ "VST4qAsm_16\0" |
| 11861 | /* 11721 */ "VLD2LNqAsm_16\0" |
| 11862 | /* 11735 */ "VST2LNqAsm_16\0" |
| 11863 | /* 11749 */ "VLD3LNqAsm_16\0" |
| 11864 | /* 11763 */ "VST3LNqAsm_16\0" |
| 11865 | /* 11777 */ "VLD4LNqAsm_16\0" |
| 11866 | /* 11791 */ "VST4LNqAsm_16\0" |
| 11867 | /* 11805 */ "VLD3DUPqAsm_16\0" |
| 11868 | /* 11820 */ "VLD4DUPqAsm_16\0" |
| 11869 | /* 11835 */ "VLD2b16\0" |
| 11870 | /* 11843 */ "VST2b16\0" |
| 11871 | /* 11851 */ "VLD1d16\0" |
| 11872 | /* 11859 */ "VST1d16\0" |
| 11873 | /* 11867 */ "VREV32d16\0" |
| 11874 | /* 11877 */ "VLD2d16\0" |
| 11875 | /* 11885 */ "VST2d16\0" |
| 11876 | /* 11893 */ "VLD3d16\0" |
| 11877 | /* 11901 */ "VST3d16\0" |
| 11878 | /* 11909 */ "VREV64d16\0" |
| 11879 | /* 11919 */ "VLD4d16\0" |
| 11880 | /* 11927 */ "VST4d16\0" |
| 11881 | /* 11935 */ "VLD1LNd16\0" |
| 11882 | /* 11945 */ "VST1LNd16\0" |
| 11883 | /* 11955 */ "VLD2LNd16\0" |
| 11884 | /* 11965 */ "VST2LNd16\0" |
| 11885 | /* 11975 */ "VLD3LNd16\0" |
| 11886 | /* 11985 */ "VST3LNd16\0" |
| 11887 | /* 11995 */ "VLD4LNd16\0" |
| 11888 | /* 12005 */ "VST4LNd16\0" |
| 11889 | /* 12015 */ "VTRNd16\0" |
| 11890 | /* 12023 */ "VZIPd16\0" |
| 11891 | /* 12031 */ "VLD1DUPd16\0" |
| 11892 | /* 12042 */ "VLD2DUPd16\0" |
| 11893 | /* 12053 */ "VLD3DUPd16\0" |
| 11894 | /* 12064 */ "VLD4DUPd16\0" |
| 11895 | /* 12075 */ "VUZPd16\0" |
| 11896 | /* 12083 */ "VEXTd16\0" |
| 11897 | /* 12091 */ "VCMLAv4f16\0" |
| 11898 | /* 12102 */ "VCADDv4f16\0" |
| 11899 | /* 12113 */ "VCGEzv4f16\0" |
| 11900 | /* 12124 */ "VCLEzv4f16\0" |
| 11901 | /* 12135 */ "VCEQzv4f16\0" |
| 11902 | /* 12146 */ "VCGTzv4f16\0" |
| 11903 | /* 12157 */ "VCLTzv4f16\0" |
| 11904 | /* 12168 */ "VCMLAv8f16\0" |
| 11905 | /* 12179 */ "VCADDv8f16\0" |
| 11906 | /* 12190 */ "MVE_VPTv8f16\0" |
| 11907 | /* 12203 */ "VCGEzv8f16\0" |
| 11908 | /* 12214 */ "VCLEzv8f16\0" |
| 11909 | /* 12225 */ "VCEQzv8f16\0" |
| 11910 | /* 12236 */ "VCGTzv8f16\0" |
| 11911 | /* 12247 */ "VCLTzv8f16\0" |
| 11912 | /* 12258 */ "MVE_VCMLAf16\0" |
| 11913 | /* 12271 */ "MVE_VFMAf16\0" |
| 11914 | /* 12283 */ "MVE_VMINNMAf16\0" |
| 11915 | /* 12298 */ "MVE_VMAXNMAf16\0" |
| 11916 | /* 12313 */ "MVE_VSUBf16\0" |
| 11917 | /* 12325 */ "MVE_VABDf16\0" |
| 11918 | /* 12337 */ "MVE_VCADDf16\0" |
| 11919 | /* 12350 */ "MVE_VADDf16\0" |
| 11920 | /* 12362 */ "MVE_VNEGf16\0" |
| 11921 | /* 12374 */ "MVE_VCMULf16\0" |
| 11922 | /* 12387 */ "MVE_VMULf16\0" |
| 11923 | /* 12399 */ "MVE_VMINNMf16\0" |
| 11924 | /* 12413 */ "MVE_VMAXNMf16\0" |
| 11925 | /* 12427 */ "MVE_VCMPf16\0" |
| 11926 | /* 12439 */ "MVE_VABSf16\0" |
| 11927 | /* 12451 */ "MVE_VFMSf16\0" |
| 11928 | /* 12463 */ "MVE_VFMA_qr_Sf16\0" |
| 11929 | /* 12480 */ "MVE_VMINNMAVf16\0" |
| 11930 | /* 12496 */ "MVE_VMAXNMAVf16\0" |
| 11931 | /* 12512 */ "MVE_VMINNMVf16\0" |
| 11932 | /* 12527 */ "MVE_VMAXNMVf16\0" |
| 11933 | /* 12542 */ "MVE_VFMA_qr_f16\0" |
| 11934 | /* 12558 */ "MVE_VSUB_qr_f16\0" |
| 11935 | /* 12574 */ "MVE_VADD_qr_f16\0" |
| 11936 | /* 12590 */ "MVE_VMUL_qr_f16\0" |
| 11937 | /* 12606 */ "VMLAv4i16\0" |
| 11938 | /* 12616 */ "VSUBv4i16\0" |
| 11939 | /* 12626 */ "VADDv4i16\0" |
| 11940 | /* 12636 */ "VQNEGv4i16\0" |
| 11941 | /* 12647 */ "VQRDMLAHv4i16\0" |
| 11942 | /* 12661 */ "VQDMULHv4i16\0" |
| 11943 | /* 12674 */ "VQRDMULHv4i16\0" |
| 11944 | /* 12688 */ "VQRDMLSHv4i16\0" |
| 11945 | /* 12702 */ "VSLIv4i16\0" |
| 11946 | /* 12712 */ "VSRIv4i16\0" |
| 11947 | /* 12722 */ "VMULv4i16\0" |
| 11948 | /* 12732 */ "VRSUBHNv4i16\0" |
| 11949 | /* 12745 */ "VSUBHNv4i16\0" |
| 11950 | /* 12757 */ "VRADDHNv4i16\0" |
| 11951 | /* 12770 */ "VADDHNv4i16\0" |
| 11952 | /* 12782 */ "VRSHRNv4i16\0" |
| 11953 | /* 12794 */ "VSHRNv4i16\0" |
| 11954 | /* 12805 */ "VQSHRUNv4i16\0" |
| 11955 | /* 12818 */ "VQRSHRUNv4i16\0" |
| 11956 | /* 12832 */ "VMVNv4i16\0" |
| 11957 | /* 12842 */ "VMOVNv4i16\0" |
| 11958 | /* 12853 */ "VCEQv4i16\0" |
| 11959 | /* 12863 */ "VQABSv4i16\0" |
| 11960 | /* 12874 */ "VABSv4i16\0" |
| 11961 | /* 12884 */ "VCLSv4i16\0" |
| 11962 | /* 12894 */ "VMLSv4i16\0" |
| 11963 | /* 12904 */ "VTSTv4i16\0" |
| 11964 | /* 12914 */ "VMOVv4i16\0" |
| 11965 | /* 12924 */ "VCLZv4i16\0" |
| 11966 | /* 12934 */ "VBICiv4i16\0" |
| 11967 | /* 12945 */ "VSHLiv4i16\0" |
| 11968 | /* 12956 */ "VORRiv4i16\0" |
| 11969 | /* 12967 */ "VQSHLsiv4i16\0" |
| 11970 | /* 12980 */ "VQSHLuiv4i16\0" |
| 11971 | /* 12993 */ "VMLAslv4i16\0" |
| 11972 | /* 13005 */ "VQRDMLAHslv4i16\0" |
| 11973 | /* 13021 */ "VQDMULHslv4i16\0" |
| 11974 | /* 13036 */ "VQRDMULHslv4i16\0" |
| 11975 | /* 13052 */ "VQRDMLSHslv4i16\0" |
| 11976 | /* 13068 */ "VQDMLALslv4i16\0" |
| 11977 | /* 13083 */ "VQDMULLslv4i16\0" |
| 11978 | /* 13098 */ "VQDMLSLslv4i16\0" |
| 11979 | /* 13113 */ "VMULslv4i16\0" |
| 11980 | /* 13125 */ "VMLSslv4i16\0" |
| 11981 | /* 13137 */ "VABAsv4i16\0" |
| 11982 | /* 13148 */ "VRSRAsv4i16\0" |
| 11983 | /* 13160 */ "VSRAsv4i16\0" |
| 11984 | /* 13171 */ "VHSUBsv4i16\0" |
| 11985 | /* 13183 */ "VQSUBsv4i16\0" |
| 11986 | /* 13195 */ "VABDsv4i16\0" |
| 11987 | /* 13206 */ "VRHADDsv4i16\0" |
| 11988 | /* 13219 */ "VHADDsv4i16\0" |
| 11989 | /* 13231 */ "VQADDsv4i16\0" |
| 11990 | /* 13243 */ "VCGEsv4i16\0" |
| 11991 | /* 13254 */ "VPADALsv4i16\0" |
| 11992 | /* 13267 */ "VPADDLsv4i16\0" |
| 11993 | /* 13280 */ "VQSHLsv4i16\0" |
| 11994 | /* 13292 */ "VQRSHLsv4i16\0" |
| 11995 | /* 13305 */ "VRSHLsv4i16\0" |
| 11996 | /* 13317 */ "VSHLsv4i16\0" |
| 11997 | /* 13328 */ "VMINsv4i16\0" |
| 11998 | /* 13339 */ "VQSHRNsv4i16\0" |
| 11999 | /* 13352 */ "VQRSHRNsv4i16\0" |
| 12000 | /* 13366 */ "VQMOVNsv4i16\0" |
| 12001 | /* 13379 */ "VRSHRsv4i16\0" |
| 12002 | /* 13391 */ "VSHRsv4i16\0" |
| 12003 | /* 13402 */ "VCGTsv4i16\0" |
| 12004 | /* 13413 */ "VMAXsv4i16\0" |
| 12005 | /* 13424 */ "VMLALslsv4i16\0" |
| 12006 | /* 13438 */ "VMULLslsv4i16\0" |
| 12007 | /* 13452 */ "VMLSLslsv4i16\0" |
| 12008 | /* 13466 */ "VABAuv4i16\0" |
| 12009 | /* 13477 */ "VRSRAuv4i16\0" |
| 12010 | /* 13489 */ "VSRAuv4i16\0" |
| 12011 | /* 13500 */ "VHSUBuv4i16\0" |
| 12012 | /* 13512 */ "VQSUBuv4i16\0" |
| 12013 | /* 13524 */ "VABDuv4i16\0" |
| 12014 | /* 13535 */ "VRHADDuv4i16\0" |
| 12015 | /* 13548 */ "VHADDuv4i16\0" |
| 12016 | /* 13560 */ "VQADDuv4i16\0" |
| 12017 | /* 13572 */ "VCGEuv4i16\0" |
| 12018 | /* 13583 */ "VPADALuv4i16\0" |
| 12019 | /* 13596 */ "VPADDLuv4i16\0" |
| 12020 | /* 13609 */ "VQSHLuv4i16\0" |
| 12021 | /* 13621 */ "VQRSHLuv4i16\0" |
| 12022 | /* 13634 */ "VRSHLuv4i16\0" |
| 12023 | /* 13646 */ "VSHLuv4i16\0" |
| 12024 | /* 13657 */ "VMINuv4i16\0" |
| 12025 | /* 13668 */ "VQSHRNuv4i16\0" |
| 12026 | /* 13681 */ "VQRSHRNuv4i16\0" |
| 12027 | /* 13695 */ "VQMOVNuv4i16\0" |
| 12028 | /* 13708 */ "VRSHRuv4i16\0" |
| 12029 | /* 13720 */ "VSHRuv4i16\0" |
| 12030 | /* 13731 */ "VCGTuv4i16\0" |
| 12031 | /* 13742 */ "VMAXuv4i16\0" |
| 12032 | /* 13753 */ "VMLALsluv4i16\0" |
| 12033 | /* 13767 */ "VMULLsluv4i16\0" |
| 12034 | /* 13781 */ "VMLSLsluv4i16\0" |
| 12035 | /* 13795 */ "VQSHLsuv4i16\0" |
| 12036 | /* 13808 */ "VQMOVNsuv4i16\0" |
| 12037 | /* 13822 */ "VCGEzv4i16\0" |
| 12038 | /* 13833 */ "VCLEzv4i16\0" |
| 12039 | /* 13844 */ "VCEQzv4i16\0" |
| 12040 | /* 13855 */ "VCGTzv4i16\0" |
| 12041 | /* 13866 */ "VCLTzv4i16\0" |
| 12042 | /* 13877 */ "VMLAv8i16\0" |
| 12043 | /* 13887 */ "VSUBv8i16\0" |
| 12044 | /* 13897 */ "VADDv8i16\0" |
| 12045 | /* 13907 */ "VQNEGv8i16\0" |
| 12046 | /* 13918 */ "VQRDMLAHv8i16\0" |
| 12047 | /* 13932 */ "VQDMULHv8i16\0" |
| 12048 | /* 13945 */ "VQRDMULHv8i16\0" |
| 12049 | /* 13959 */ "VQRDMLSHv8i16\0" |
| 12050 | /* 13973 */ "VSLIv8i16\0" |
| 12051 | /* 13983 */ "VSRIv8i16\0" |
| 12052 | /* 13993 */ "VMULv8i16\0" |
| 12053 | /* 14003 */ "VMVNv8i16\0" |
| 12054 | /* 14013 */ "VCEQv8i16\0" |
| 12055 | /* 14023 */ "VQABSv8i16\0" |
| 12056 | /* 14034 */ "VABSv8i16\0" |
| 12057 | /* 14044 */ "VCLSv8i16\0" |
| 12058 | /* 14054 */ "VMLSv8i16\0" |
| 12059 | /* 14064 */ "MVE_VPTv8i16\0" |
| 12060 | /* 14077 */ "VTSTv8i16\0" |
| 12061 | /* 14087 */ "VMOVv8i16\0" |
| 12062 | /* 14097 */ "VCLZv8i16\0" |
| 12063 | /* 14107 */ "VBICiv8i16\0" |
| 12064 | /* 14118 */ "VSHLiv8i16\0" |
| 12065 | /* 14129 */ "VORRiv8i16\0" |
| 12066 | /* 14140 */ "VQSHLsiv8i16\0" |
| 12067 | /* 14153 */ "VQSHLuiv8i16\0" |
| 12068 | /* 14166 */ "VMLAslv8i16\0" |
| 12069 | /* 14178 */ "VQRDMLAHslv8i16\0" |
| 12070 | /* 14194 */ "VQDMULHslv8i16\0" |
| 12071 | /* 14209 */ "VQRDMULHslv8i16\0" |
| 12072 | /* 14225 */ "VQRDMLSHslv8i16\0" |
| 12073 | /* 14241 */ "VMULslv8i16\0" |
| 12074 | /* 14253 */ "VMLSslv8i16\0" |
| 12075 | /* 14265 */ "VABAsv8i16\0" |
| 12076 | /* 14276 */ "VRSRAsv8i16\0" |
| 12077 | /* 14288 */ "VSRAsv8i16\0" |
| 12078 | /* 14299 */ "VHSUBsv8i16\0" |
| 12079 | /* 14311 */ "VQSUBsv8i16\0" |
| 12080 | /* 14323 */ "VABDsv8i16\0" |
| 12081 | /* 14334 */ "VRHADDsv8i16\0" |
| 12082 | /* 14347 */ "VHADDsv8i16\0" |
| 12083 | /* 14359 */ "VQADDsv8i16\0" |
| 12084 | /* 14371 */ "VCGEsv8i16\0" |
| 12085 | /* 14382 */ "VABALsv8i16\0" |
| 12086 | /* 14394 */ "VPADALsv8i16\0" |
| 12087 | /* 14407 */ "VMLALsv8i16\0" |
| 12088 | /* 14419 */ "VSUBLsv8i16\0" |
| 12089 | /* 14431 */ "VABDLsv8i16\0" |
| 12090 | /* 14443 */ "VPADDLsv8i16\0" |
| 12091 | /* 14456 */ "VADDLsv8i16\0" |
| 12092 | /* 14468 */ "VQSHLsv8i16\0" |
| 12093 | /* 14480 */ "VQRSHLsv8i16\0" |
| 12094 | /* 14493 */ "VRSHLsv8i16\0" |
| 12095 | /* 14505 */ "VSHLsv8i16\0" |
| 12096 | /* 14516 */ "VSHLLsv8i16\0" |
| 12097 | /* 14528 */ "VMULLsv8i16\0" |
| 12098 | /* 14540 */ "VMLSLsv8i16\0" |
| 12099 | /* 14552 */ "VMOVLsv8i16\0" |
| 12100 | /* 14564 */ "VMINsv8i16\0" |
| 12101 | /* 14575 */ "VRSHRsv8i16\0" |
| 12102 | /* 14587 */ "VSHRsv8i16\0" |
| 12103 | /* 14598 */ "VCGTsv8i16\0" |
| 12104 | /* 14609 */ "VSUBWsv8i16\0" |
| 12105 | /* 14621 */ "VADDWsv8i16\0" |
| 12106 | /* 14633 */ "VMAXsv8i16\0" |
| 12107 | /* 14644 */ "VABAuv8i16\0" |
| 12108 | /* 14655 */ "VRSRAuv8i16\0" |
| 12109 | /* 14667 */ "VSRAuv8i16\0" |
| 12110 | /* 14678 */ "VHSUBuv8i16\0" |
| 12111 | /* 14690 */ "VQSUBuv8i16\0" |
| 12112 | /* 14702 */ "VABDuv8i16\0" |
| 12113 | /* 14713 */ "VRHADDuv8i16\0" |
| 12114 | /* 14726 */ "VHADDuv8i16\0" |
| 12115 | /* 14738 */ "VQADDuv8i16\0" |
| 12116 | /* 14750 */ "VCGEuv8i16\0" |
| 12117 | /* 14761 */ "VABALuv8i16\0" |
| 12118 | /* 14773 */ "VPADALuv8i16\0" |
| 12119 | /* 14786 */ "VMLALuv8i16\0" |
| 12120 | /* 14798 */ "VSUBLuv8i16\0" |
| 12121 | /* 14810 */ "VABDLuv8i16\0" |
| 12122 | /* 14822 */ "VPADDLuv8i16\0" |
| 12123 | /* 14835 */ "VADDLuv8i16\0" |
| 12124 | /* 14847 */ "VQSHLuv8i16\0" |
| 12125 | /* 14859 */ "VQRSHLuv8i16\0" |
| 12126 | /* 14872 */ "VRSHLuv8i16\0" |
| 12127 | /* 14884 */ "VSHLuv8i16\0" |
| 12128 | /* 14895 */ "VSHLLuv8i16\0" |
| 12129 | /* 14907 */ "VMULLuv8i16\0" |
| 12130 | /* 14919 */ "VMLSLuv8i16\0" |
| 12131 | /* 14931 */ "VMOVLuv8i16\0" |
| 12132 | /* 14943 */ "VMINuv8i16\0" |
| 12133 | /* 14954 */ "VRSHRuv8i16\0" |
| 12134 | /* 14966 */ "VSHRuv8i16\0" |
| 12135 | /* 14977 */ "VCGTuv8i16\0" |
| 12136 | /* 14988 */ "VSUBWuv8i16\0" |
| 12137 | /* 15000 */ "VADDWuv8i16\0" |
| 12138 | /* 15012 */ "VMAXuv8i16\0" |
| 12139 | /* 15023 */ "VQSHLsuv8i16\0" |
| 12140 | /* 15036 */ "VCGEzv8i16\0" |
| 12141 | /* 15047 */ "VCLEzv8i16\0" |
| 12142 | /* 15058 */ "VCEQzv8i16\0" |
| 12143 | /* 15069 */ "VCGTzv8i16\0" |
| 12144 | /* 15080 */ "VCLTzv8i16\0" |
| 12145 | /* 15091 */ "MVE_VSUBi16\0" |
| 12146 | /* 15103 */ "t2MOVCCi16\0" |
| 12147 | /* 15114 */ "MVE_VCADDi16\0" |
| 12148 | /* 15127 */ "VPADDi16\0" |
| 12149 | /* 15136 */ "MVE_VADDi16\0" |
| 12150 | /* 15148 */ "MVE_VQDMULHi16\0" |
| 12151 | /* 15163 */ "MVE_VQRDMULHi16\0" |
| 12152 | /* 15179 */ "VSHLLi16\0" |
| 12153 | /* 15188 */ "MVE_VMULi16\0" |
| 12154 | /* 15200 */ "VSETLNi16\0" |
| 12155 | /* 15210 */ "MVE_VCMPi16\0" |
| 12156 | /* 15222 */ "t2MOVTi16\0" |
| 12157 | /* 15232 */ "t2MOVi16\0" |
| 12158 | /* 15241 */ "MVE_VMLA_qr_i16\0" |
| 12159 | /* 15257 */ "MVE_VSUB_qr_i16\0" |
| 12160 | /* 15273 */ "MVE_VADD_qr_i16\0" |
| 12161 | /* 15289 */ "MVE_VMUL_qr_i16\0" |
| 12162 | /* 15305 */ "MVE_VMLAS_qr_i16\0" |
| 12163 | /* 15322 */ "MVE_VBICimmi16\0" |
| 12164 | /* 15337 */ "MVE_VMVNimmi16\0" |
| 12165 | /* 15352 */ "MVE_VORRimmi16\0" |
| 12166 | /* 15367 */ "MVE_VMOVimmi16\0" |
| 12167 | /* 15382 */ "MVE_VSHL_immi16\0" |
| 12168 | /* 15398 */ "MVE_VSLIimm16\0" |
| 12169 | /* 15412 */ "MVE_VSRIimm16\0" |
| 12170 | /* 15426 */ "MVE_VMULLBp16\0" |
| 12171 | /* 15440 */ "MVE_VMULLTp16\0" |
| 12172 | /* 15454 */ "VLD1q16\0" |
| 12173 | /* 15462 */ "VST1q16\0" |
| 12174 | /* 15470 */ "VREV32q16\0" |
| 12175 | /* 15480 */ "VLD2q16\0" |
| 12176 | /* 15488 */ "VST2q16\0" |
| 12177 | /* 15496 */ "VLD3q16\0" |
| 12178 | /* 15504 */ "VST3q16\0" |
| 12179 | /* 15512 */ "VREV64q16\0" |
| 12180 | /* 15522 */ "VLD4q16\0" |
| 12181 | /* 15530 */ "VST4q16\0" |
| 12182 | /* 15538 */ "VLD2LNq16\0" |
| 12183 | /* 15548 */ "VST2LNq16\0" |
| 12184 | /* 15558 */ "VLD3LNq16\0" |
| 12185 | /* 15568 */ "VST3LNq16\0" |
| 12186 | /* 15578 */ "VLD4LNq16\0" |
| 12187 | /* 15588 */ "VST4LNq16\0" |
| 12188 | /* 15598 */ "VTRNq16\0" |
| 12189 | /* 15606 */ "VZIPq16\0" |
| 12190 | /* 15614 */ "VLD1DUPq16\0" |
| 12191 | /* 15625 */ "VLD3DUPq16\0" |
| 12192 | /* 15636 */ "VLD4DUPq16\0" |
| 12193 | /* 15647 */ "VUZPq16\0" |
| 12194 | /* 15655 */ "VEXTq16\0" |
| 12195 | /* 15663 */ "MVE_VPTv8s16\0" |
| 12196 | /* 15676 */ "MVE_VMINAs16\0" |
| 12197 | /* 15689 */ "MVE_VMAXAs16\0" |
| 12198 | /* 15702 */ "MVE_VMULLBs16\0" |
| 12199 | /* 15716 */ "MVE_VHSUBs16\0" |
| 12200 | /* 15729 */ "MVE_VQSUBs16\0" |
| 12201 | /* 15742 */ "MVE_VABDs16\0" |
| 12202 | /* 15754 */ "MVE_VHCADDs16\0" |
| 12203 | /* 15768 */ "MVE_VRHADDs16\0" |
| 12204 | /* 15782 */ "MVE_VHADDs16\0" |
| 12205 | /* 15795 */ "MVE_VQADDs16\0" |
| 12206 | /* 15808 */ "MVE_VQNEGs16\0" |
| 12207 | /* 15821 */ "MVE_VNEGs16\0" |
| 12208 | /* 15833 */ "MVE_VQDMLADHs16\0" |
| 12209 | /* 15849 */ "MVE_VQRDMLADHs16\0" |
| 12210 | /* 15866 */ "MVE_VQDMLSDHs16\0" |
| 12211 | /* 15882 */ "MVE_VQRDMLSDHs16\0" |
| 12212 | /* 15899 */ "MVE_VRMULHs16\0" |
| 12213 | /* 15913 */ "MVE_VMULHs16\0" |
| 12214 | /* 15926 */ "VPMINs16\0" |
| 12215 | /* 15935 */ "MVE_VMINs16\0" |
| 12216 | /* 15947 */ "VGETLNs16\0" |
| 12217 | /* 15957 */ "MVE_VCMPs16\0" |
| 12218 | /* 15969 */ "MVE_VQABSs16\0" |
| 12219 | /* 15982 */ "MVE_VABSs16\0" |
| 12220 | /* 15994 */ "MVE_VCLSs16\0" |
| 12221 | /* 16006 */ "MVE_VMULLTs16\0" |
| 12222 | /* 16020 */ "MVE_VABAVs16\0" |
| 12223 | /* 16033 */ "MVE_VMLADAVs16\0" |
| 12224 | /* 16048 */ "MVE_VMLALDAVs16\0" |
| 12225 | /* 16064 */ "MVE_VMLSLDAVs16\0" |
| 12226 | /* 16080 */ "MVE_VMLSDAVs16\0" |
| 12227 | /* 16095 */ "MVE_VMINAVs16\0" |
| 12228 | /* 16109 */ "MVE_VMAXAVs16\0" |
| 12229 | /* 16123 */ "MVE_VMINVs16\0" |
| 12230 | /* 16136 */ "MVE_VMAXVs16\0" |
| 12231 | /* 16149 */ "VPMAXs16\0" |
| 12232 | /* 16158 */ "MVE_VMAXs16\0" |
| 12233 | /* 16170 */ "MVE_VQDMLADHXs16\0" |
| 12234 | /* 16187 */ "MVE_VQRDMLADHXs16\0" |
| 12235 | /* 16205 */ "MVE_VQDMLSDHXs16\0" |
| 12236 | /* 16222 */ "MVE_VQRDMLSDHXs16\0" |
| 12237 | /* 16240 */ "MVE_VCLZs16\0" |
| 12238 | /* 16252 */ "MVE_VMOV_from_lane_s16\0" |
| 12239 | /* 16275 */ "MVE_VHSUB_qr_s16\0" |
| 12240 | /* 16292 */ "MVE_VQSUB_qr_s16\0" |
| 12241 | /* 16309 */ "MVE_VHADD_qr_s16\0" |
| 12242 | /* 16326 */ "MVE_VQADD_qr_s16\0" |
| 12243 | /* 16343 */ "MVE_VQDMULH_qr_s16\0" |
| 12244 | /* 16362 */ "MVE_VQRDMULH_qr_s16\0" |
| 12245 | /* 16382 */ "MVE_VMLADAVas16\0" |
| 12246 | /* 16398 */ "MVE_VMLALDAVas16\0" |
| 12247 | /* 16415 */ "MVE_VMLSLDAVas16\0" |
| 12248 | /* 16432 */ "MVE_VMLSDAVas16\0" |
| 12249 | /* 16448 */ "MVE_VQSHL_by_vecs16\0" |
| 12250 | /* 16468 */ "MVE_VQRSHL_by_vecs16\0" |
| 12251 | /* 16489 */ "MVE_VRSHL_by_vecs16\0" |
| 12252 | /* 16509 */ "MVE_VSHL_by_vecs16\0" |
| 12253 | /* 16528 */ "MVE_VQSHRNbhs16\0" |
| 12254 | /* 16544 */ "MVE_VQRSHRNbhs16\0" |
| 12255 | /* 16561 */ "MVE_VQSHRNths16\0" |
| 12256 | /* 16577 */ "MVE_VQRSHRNths16\0" |
| 12257 | /* 16594 */ "MVE_VQSHLimms16\0" |
| 12258 | /* 16610 */ "MVE_VRSHR_imms16\0" |
| 12259 | /* 16627 */ "MVE_VSHR_imms16\0" |
| 12260 | /* 16643 */ "MVE_VQSHLU_imms16\0" |
| 12261 | /* 16661 */ "MVE_VQDMLAH_qrs16\0" |
| 12262 | /* 16679 */ "MVE_VQRDMLAH_qrs16\0" |
| 12263 | /* 16698 */ "MVE_VQDMLASH_qrs16\0" |
| 12264 | /* 16717 */ "MVE_VQRDMLASH_qrs16\0" |
| 12265 | /* 16737 */ "MVE_VQSHL_qrs16\0" |
| 12266 | /* 16753 */ "MVE_VQRSHL_qrs16\0" |
| 12267 | /* 16770 */ "MVE_VRSHL_qrs16\0" |
| 12268 | /* 16786 */ "MVE_VSHL_qrs16\0" |
| 12269 | /* 16801 */ "MVE_VMLADAVxs16\0" |
| 12270 | /* 16817 */ "MVE_VMLALDAVxs16\0" |
| 12271 | /* 16834 */ "MVE_VMLSLDAVxs16\0" |
| 12272 | /* 16851 */ "MVE_VMLSDAVxs16\0" |
| 12273 | /* 16867 */ "MVE_VMLADAVaxs16\0" |
| 12274 | /* 16884 */ "MVE_VMLALDAVaxs16\0" |
| 12275 | /* 16902 */ "MVE_VMLSLDAVaxs16\0" |
| 12276 | /* 16920 */ "MVE_VMLSDAVaxs16\0" |
| 12277 | /* 16937 */ "MVE_VPTv8u16\0" |
| 12278 | /* 16950 */ "MVE_VMULLBu16\0" |
| 12279 | /* 16964 */ "MVE_VHSUBu16\0" |
| 12280 | /* 16977 */ "MVE_VQSUBu16\0" |
| 12281 | /* 16990 */ "MVE_VABDu16\0" |
| 12282 | /* 17002 */ "MVE_VRHADDu16\0" |
| 12283 | /* 17016 */ "MVE_VHADDu16\0" |
| 12284 | /* 17029 */ "MVE_VQADDu16\0" |
| 12285 | /* 17042 */ "MVE_VRMULHu16\0" |
| 12286 | /* 17056 */ "MVE_VMULHu16\0" |
| 12287 | /* 17069 */ "VPMINu16\0" |
| 12288 | /* 17078 */ "MVE_VMINu16\0" |
| 12289 | /* 17090 */ "VGETLNu16\0" |
| 12290 | /* 17100 */ "MVE_VCMPu16\0" |
| 12291 | /* 17112 */ "MVE_VDDUPu16\0" |
| 12292 | /* 17125 */ "MVE_VIDUPu16\0" |
| 12293 | /* 17138 */ "MVE_VDWDUPu16\0" |
| 12294 | /* 17152 */ "MVE_VIWDUPu16\0" |
| 12295 | /* 17166 */ "MVE_VMULLTu16\0" |
| 12296 | /* 17180 */ "MVE_VABAVu16\0" |
| 12297 | /* 17193 */ "MVE_VMLADAVu16\0" |
| 12298 | /* 17208 */ "MVE_VMLALDAVu16\0" |
| 12299 | /* 17224 */ "MVE_VMINVu16\0" |
| 12300 | /* 17237 */ "MVE_VMAXVu16\0" |
| 12301 | /* 17250 */ "VPMAXu16\0" |
| 12302 | /* 17259 */ "MVE_VMAXu16\0" |
| 12303 | /* 17271 */ "MVE_VMOV_from_lane_u16\0" |
| 12304 | /* 17294 */ "MVE_VHSUB_qr_u16\0" |
| 12305 | /* 17311 */ "MVE_VQSUB_qr_u16\0" |
| 12306 | /* 17328 */ "MVE_VHADD_qr_u16\0" |
| 12307 | /* 17345 */ "MVE_VQADD_qr_u16\0" |
| 12308 | /* 17362 */ "MVE_VMLADAVau16\0" |
| 12309 | /* 17378 */ "MVE_VMLALDAVau16\0" |
| 12310 | /* 17395 */ "MVE_VQSHL_by_vecu16\0" |
| 12311 | /* 17415 */ "MVE_VQRSHL_by_vecu16\0" |
| 12312 | /* 17436 */ "MVE_VRSHL_by_vecu16\0" |
| 12313 | /* 17456 */ "MVE_VSHL_by_vecu16\0" |
| 12314 | /* 17475 */ "MVE_VQSHRNbhu16\0" |
| 12315 | /* 17491 */ "MVE_VQRSHRNbhu16\0" |
| 12316 | /* 17508 */ "MVE_VQSHRNthu16\0" |
| 12317 | /* 17524 */ "MVE_VQRSHRNthu16\0" |
| 12318 | /* 17541 */ "MVE_VQSHLimmu16\0" |
| 12319 | /* 17557 */ "MVE_VRSHR_immu16\0" |
| 12320 | /* 17574 */ "MVE_VSHR_immu16\0" |
| 12321 | /* 17590 */ "MVE_VQSHL_qru16\0" |
| 12322 | /* 17606 */ "MVE_VQRSHL_qru16\0" |
| 12323 | /* 17623 */ "MVE_VRSHL_qru16\0" |
| 12324 | /* 17639 */ "MVE_VSHL_qru16\0" |
| 12325 | /* 17654 */ "t2USADA8\0" |
| 12326 | /* 17663 */ "t2SHSUB8\0" |
| 12327 | /* 17672 */ "t2UHSUB8\0" |
| 12328 | /* 17681 */ "t2QSUB8\0" |
| 12329 | /* 17689 */ "t2UQSUB8\0" |
| 12330 | /* 17698 */ "t2SSUB8\0" |
| 12331 | /* 17706 */ "t2USUB8\0" |
| 12332 | /* 17714 */ "t2USAD8\0" |
| 12333 | /* 17722 */ "t2SHADD8\0" |
| 12334 | /* 17731 */ "t2UHADD8\0" |
| 12335 | /* 17740 */ "t2QADD8\0" |
| 12336 | /* 17748 */ "t2UQADD8\0" |
| 12337 | /* 17757 */ "t2SADD8\0" |
| 12338 | /* 17765 */ "t2UADD8\0" |
| 12339 | /* 17773 */ "MVE_VCTP8\0" |
| 12340 | /* 17783 */ "MVE_VDUP8\0" |
| 12341 | /* 17793 */ "MVE_VBRSR8\0" |
| 12342 | /* 17804 */ "MVE_VLDRBU8\0" |
| 12343 | /* 17816 */ "MVE_VSTRBU8\0" |
| 12344 | /* 17828 */ "MVE_VLD20_8\0" |
| 12345 | /* 17840 */ "MVE_VST20_8\0" |
| 12346 | /* 17852 */ "MVE_VLD40_8\0" |
| 12347 | /* 17864 */ "MVE_VST40_8\0" |
| 12348 | /* 17876 */ "MVE_VLD21_8\0" |
| 12349 | /* 17888 */ "MVE_VST21_8\0" |
| 12350 | /* 17900 */ "MVE_VLD41_8\0" |
| 12351 | /* 17912 */ "MVE_VST41_8\0" |
| 12352 | /* 17924 */ "MVE_VREV32_8\0" |
| 12353 | /* 17937 */ "MVE_VLD42_8\0" |
| 12354 | /* 17949 */ "MVE_VST42_8\0" |
| 12355 | /* 17961 */ "MVE_VLD43_8\0" |
| 12356 | /* 17973 */ "MVE_VST43_8\0" |
| 12357 | /* 17985 */ "MVE_VREV64_8\0" |
| 12358 | /* 17998 */ "MVE_VREV16_8\0" |
| 12359 | /* 18011 */ "tCMP_SWAP_8\0" |
| 12360 | /* 18023 */ "MVE_DLSTP_8\0" |
| 12361 | /* 18035 */ "MVE_WLSTP_8\0" |
| 12362 | /* 18047 */ "MVE_VMOV_to_lane_8\0" |
| 12363 | /* 18066 */ "VLD3dWB_fixed_Asm_8\0" |
| 12364 | /* 18086 */ "VST3dWB_fixed_Asm_8\0" |
| 12365 | /* 18106 */ "VLD4dWB_fixed_Asm_8\0" |
| 12366 | /* 18126 */ "VST4dWB_fixed_Asm_8\0" |
| 12367 | /* 18146 */ "VLD1LNdWB_fixed_Asm_8\0" |
| 12368 | /* 18168 */ "VST1LNdWB_fixed_Asm_8\0" |
| 12369 | /* 18190 */ "VLD2LNdWB_fixed_Asm_8\0" |
| 12370 | /* 18212 */ "VST2LNdWB_fixed_Asm_8\0" |
| 12371 | /* 18234 */ "VLD3LNdWB_fixed_Asm_8\0" |
| 12372 | /* 18256 */ "VST3LNdWB_fixed_Asm_8\0" |
| 12373 | /* 18278 */ "VLD4LNdWB_fixed_Asm_8\0" |
| 12374 | /* 18300 */ "VST4LNdWB_fixed_Asm_8\0" |
| 12375 | /* 18322 */ "VLD3DUPdWB_fixed_Asm_8\0" |
| 12376 | /* 18345 */ "VLD4DUPdWB_fixed_Asm_8\0" |
| 12377 | /* 18368 */ "VLD3qWB_fixed_Asm_8\0" |
| 12378 | /* 18388 */ "VST3qWB_fixed_Asm_8\0" |
| 12379 | /* 18408 */ "VLD4qWB_fixed_Asm_8\0" |
| 12380 | /* 18428 */ "VST4qWB_fixed_Asm_8\0" |
| 12381 | /* 18448 */ "VLD3DUPqWB_fixed_Asm_8\0" |
| 12382 | /* 18471 */ "VLD4DUPqWB_fixed_Asm_8\0" |
| 12383 | /* 18494 */ "VLD3dWB_register_Asm_8\0" |
| 12384 | /* 18517 */ "VST3dWB_register_Asm_8\0" |
| 12385 | /* 18540 */ "VLD4dWB_register_Asm_8\0" |
| 12386 | /* 18563 */ "VST4dWB_register_Asm_8\0" |
| 12387 | /* 18586 */ "VLD1LNdWB_register_Asm_8\0" |
| 12388 | /* 18611 */ "VST1LNdWB_register_Asm_8\0" |
| 12389 | /* 18636 */ "VLD2LNdWB_register_Asm_8\0" |
| 12390 | /* 18661 */ "VST2LNdWB_register_Asm_8\0" |
| 12391 | /* 18686 */ "VLD3LNdWB_register_Asm_8\0" |
| 12392 | /* 18711 */ "VST3LNdWB_register_Asm_8\0" |
| 12393 | /* 18736 */ "VLD4LNdWB_register_Asm_8\0" |
| 12394 | /* 18761 */ "VST4LNdWB_register_Asm_8\0" |
| 12395 | /* 18786 */ "VLD3DUPdWB_register_Asm_8\0" |
| 12396 | /* 18812 */ "VLD4DUPdWB_register_Asm_8\0" |
| 12397 | /* 18838 */ "VLD3qWB_register_Asm_8\0" |
| 12398 | /* 18861 */ "VST3qWB_register_Asm_8\0" |
| 12399 | /* 18884 */ "VLD4qWB_register_Asm_8\0" |
| 12400 | /* 18907 */ "VST4qWB_register_Asm_8\0" |
| 12401 | /* 18930 */ "VLD3DUPqWB_register_Asm_8\0" |
| 12402 | /* 18956 */ "VLD4DUPqWB_register_Asm_8\0" |
| 12403 | /* 18982 */ "VLD3dAsm_8\0" |
| 12404 | /* 18993 */ "VST3dAsm_8\0" |
| 12405 | /* 19004 */ "VLD4dAsm_8\0" |
| 12406 | /* 19015 */ "VST4dAsm_8\0" |
| 12407 | /* 19026 */ "VLD1LNdAsm_8\0" |
| 12408 | /* 19039 */ "VST1LNdAsm_8\0" |
| 12409 | /* 19052 */ "VLD2LNdAsm_8\0" |
| 12410 | /* 19065 */ "VST2LNdAsm_8\0" |
| 12411 | /* 19078 */ "VLD3LNdAsm_8\0" |
| 12412 | /* 19091 */ "VST3LNdAsm_8\0" |
| 12413 | /* 19104 */ "VLD4LNdAsm_8\0" |
| 12414 | /* 19117 */ "VST4LNdAsm_8\0" |
| 12415 | /* 19130 */ "VLD3DUPdAsm_8\0" |
| 12416 | /* 19144 */ "VLD4DUPdAsm_8\0" |
| 12417 | /* 19158 */ "VLD3qAsm_8\0" |
| 12418 | /* 19169 */ "VST3qAsm_8\0" |
| 12419 | /* 19180 */ "VLD4qAsm_8\0" |
| 12420 | /* 19191 */ "VST4qAsm_8\0" |
| 12421 | /* 19202 */ "VLD3DUPqAsm_8\0" |
| 12422 | /* 19216 */ "VLD4DUPqAsm_8\0" |
| 12423 | /* 19230 */ "VLD2b8\0" |
| 12424 | /* 19237 */ "VST2b8\0" |
| 12425 | /* 19244 */ "VLD1d8\0" |
| 12426 | /* 19251 */ "VST1d8\0" |
| 12427 | /* 19258 */ "VREV32d8\0" |
| 12428 | /* 19267 */ "VLD2d8\0" |
| 12429 | /* 19274 */ "VST2d8\0" |
| 12430 | /* 19281 */ "VLD3d8\0" |
| 12431 | /* 19288 */ "VST3d8\0" |
| 12432 | /* 19295 */ "VREV64d8\0" |
| 12433 | /* 19304 */ "VLD4d8\0" |
| 12434 | /* 19311 */ "VST4d8\0" |
| 12435 | /* 19318 */ "VREV16d8\0" |
| 12436 | /* 19327 */ "VLD1LNd8\0" |
| 12437 | /* 19336 */ "VST1LNd8\0" |
| 12438 | /* 19345 */ "VLD2LNd8\0" |
| 12439 | /* 19354 */ "VST2LNd8\0" |
| 12440 | /* 19363 */ "VLD3LNd8\0" |
| 12441 | /* 19372 */ "VST3LNd8\0" |
| 12442 | /* 19381 */ "VLD4LNd8\0" |
| 12443 | /* 19390 */ "VST4LNd8\0" |
| 12444 | /* 19399 */ "VTRNd8\0" |
| 12445 | /* 19406 */ "VZIPd8\0" |
| 12446 | /* 19413 */ "VLD1DUPd8\0" |
| 12447 | /* 19423 */ "VLD2DUPd8\0" |
| 12448 | /* 19433 */ "VLD3DUPd8\0" |
| 12449 | /* 19443 */ "VLD4DUPd8\0" |
| 12450 | /* 19453 */ "VUZPd8\0" |
| 12451 | /* 19460 */ "VEXTd8\0" |
| 12452 | /* 19467 */ "VMLAv16i8\0" |
| 12453 | /* 19477 */ "VSUBv16i8\0" |
| 12454 | /* 19487 */ "VADDv16i8\0" |
| 12455 | /* 19497 */ "VQNEGv16i8\0" |
| 12456 | /* 19508 */ "VSLIv16i8\0" |
| 12457 | /* 19518 */ "VSRIv16i8\0" |
| 12458 | /* 19528 */ "VMULv16i8\0" |
| 12459 | /* 19538 */ "VCEQv16i8\0" |
| 12460 | /* 19548 */ "VQABSv16i8\0" |
| 12461 | /* 19559 */ "VABSv16i8\0" |
| 12462 | /* 19569 */ "VCLSv16i8\0" |
| 12463 | /* 19579 */ "VMLSv16i8\0" |
| 12464 | /* 19589 */ "MVE_VPTv16i8\0" |
| 12465 | /* 19602 */ "VTSTv16i8\0" |
| 12466 | /* 19612 */ "VMOVv16i8\0" |
| 12467 | /* 19622 */ "VCLZv16i8\0" |
| 12468 | /* 19632 */ "VSHLiv16i8\0" |
| 12469 | /* 19643 */ "VQSHLsiv16i8\0" |
| 12470 | /* 19656 */ "VQSHLuiv16i8\0" |
| 12471 | /* 19669 */ "VABAsv16i8\0" |
| 12472 | /* 19680 */ "VRSRAsv16i8\0" |
| 12473 | /* 19692 */ "VSRAsv16i8\0" |
| 12474 | /* 19703 */ "VHSUBsv16i8\0" |
| 12475 | /* 19715 */ "VQSUBsv16i8\0" |
| 12476 | /* 19727 */ "VABDsv16i8\0" |
| 12477 | /* 19738 */ "VRHADDsv16i8\0" |
| 12478 | /* 19751 */ "VHADDsv16i8\0" |
| 12479 | /* 19763 */ "VQADDsv16i8\0" |
| 12480 | /* 19775 */ "VCGEsv16i8\0" |
| 12481 | /* 19786 */ "VPADALsv16i8\0" |
| 12482 | /* 19799 */ "VPADDLsv16i8\0" |
| 12483 | /* 19812 */ "VQSHLsv16i8\0" |
| 12484 | /* 19824 */ "VQRSHLsv16i8\0" |
| 12485 | /* 19837 */ "VRSHLsv16i8\0" |
| 12486 | /* 19849 */ "VSHLsv16i8\0" |
| 12487 | /* 19860 */ "VMINsv16i8\0" |
| 12488 | /* 19871 */ "VRSHRsv16i8\0" |
| 12489 | /* 19883 */ "VSHRsv16i8\0" |
| 12490 | /* 19894 */ "VCGTsv16i8\0" |
| 12491 | /* 19905 */ "VMAXsv16i8\0" |
| 12492 | /* 19916 */ "VABAuv16i8\0" |
| 12493 | /* 19927 */ "VRSRAuv16i8\0" |
| 12494 | /* 19939 */ "VSRAuv16i8\0" |
| 12495 | /* 19950 */ "VHSUBuv16i8\0" |
| 12496 | /* 19962 */ "VQSUBuv16i8\0" |
| 12497 | /* 19974 */ "VABDuv16i8\0" |
| 12498 | /* 19985 */ "VRHADDuv16i8\0" |
| 12499 | /* 19998 */ "VHADDuv16i8\0" |
| 12500 | /* 20010 */ "VQADDuv16i8\0" |
| 12501 | /* 20022 */ "VCGEuv16i8\0" |
| 12502 | /* 20033 */ "VPADALuv16i8\0" |
| 12503 | /* 20046 */ "VPADDLuv16i8\0" |
| 12504 | /* 20059 */ "VQSHLuv16i8\0" |
| 12505 | /* 20071 */ "VQRSHLuv16i8\0" |
| 12506 | /* 20084 */ "VRSHLuv16i8\0" |
| 12507 | /* 20096 */ "VSHLuv16i8\0" |
| 12508 | /* 20107 */ "VMINuv16i8\0" |
| 12509 | /* 20118 */ "VRSHRuv16i8\0" |
| 12510 | /* 20130 */ "VSHRuv16i8\0" |
| 12511 | /* 20141 */ "VCGTuv16i8\0" |
| 12512 | /* 20152 */ "VMAXuv16i8\0" |
| 12513 | /* 20163 */ "VQSHLsuv16i8\0" |
| 12514 | /* 20176 */ "VCGEzv16i8\0" |
| 12515 | /* 20187 */ "VCLEzv16i8\0" |
| 12516 | /* 20198 */ "VCEQzv16i8\0" |
| 12517 | /* 20209 */ "VCGTzv16i8\0" |
| 12518 | /* 20220 */ "VCLTzv16i8\0" |
| 12519 | /* 20231 */ "VMLAv8i8\0" |
| 12520 | /* 20240 */ "VSUBv8i8\0" |
| 12521 | /* 20249 */ "VADDv8i8\0" |
| 12522 | /* 20258 */ "VQNEGv8i8\0" |
| 12523 | /* 20268 */ "VSLIv8i8\0" |
| 12524 | /* 20277 */ "VSRIv8i8\0" |
| 12525 | /* 20286 */ "VMULv8i8\0" |
| 12526 | /* 20295 */ "VRSUBHNv8i8\0" |
| 12527 | /* 20307 */ "VSUBHNv8i8\0" |
| 12528 | /* 20318 */ "VRADDHNv8i8\0" |
| 12529 | /* 20330 */ "VADDHNv8i8\0" |
| 12530 | /* 20341 */ "VRSHRNv8i8\0" |
| 12531 | /* 20352 */ "VSHRNv8i8\0" |
| 12532 | /* 20362 */ "VQSHRUNv8i8\0" |
| 12533 | /* 20374 */ "VQRSHRUNv8i8\0" |
| 12534 | /* 20387 */ "VMOVNv8i8\0" |
| 12535 | /* 20397 */ "VCEQv8i8\0" |
| 12536 | /* 20406 */ "VQABSv8i8\0" |
| 12537 | /* 20416 */ "VABSv8i8\0" |
| 12538 | /* 20425 */ "VCLSv8i8\0" |
| 12539 | /* 20434 */ "VMLSv8i8\0" |
| 12540 | /* 20443 */ "VTSTv8i8\0" |
| 12541 | /* 20452 */ "VMOVv8i8\0" |
| 12542 | /* 20461 */ "VCLZv8i8\0" |
| 12543 | /* 20470 */ "VSHLiv8i8\0" |
| 12544 | /* 20480 */ "VQSHLsiv8i8\0" |
| 12545 | /* 20492 */ "VQSHLuiv8i8\0" |
| 12546 | /* 20504 */ "VABAsv8i8\0" |
| 12547 | /* 20514 */ "VRSRAsv8i8\0" |
| 12548 | /* 20525 */ "VSRAsv8i8\0" |
| 12549 | /* 20535 */ "VHSUBsv8i8\0" |
| 12550 | /* 20546 */ "VQSUBsv8i8\0" |
| 12551 | /* 20557 */ "VABDsv8i8\0" |
| 12552 | /* 20567 */ "VRHADDsv8i8\0" |
| 12553 | /* 20579 */ "VHADDsv8i8\0" |
| 12554 | /* 20590 */ "VQADDsv8i8\0" |
| 12555 | /* 20601 */ "VCGEsv8i8\0" |
| 12556 | /* 20611 */ "VPADALsv8i8\0" |
| 12557 | /* 20623 */ "VPADDLsv8i8\0" |
| 12558 | /* 20635 */ "VQSHLsv8i8\0" |
| 12559 | /* 20646 */ "VQRSHLsv8i8\0" |
| 12560 | /* 20658 */ "VRSHLsv8i8\0" |
| 12561 | /* 20669 */ "VSHLsv8i8\0" |
| 12562 | /* 20679 */ "VMINsv8i8\0" |
| 12563 | /* 20689 */ "VQSHRNsv8i8\0" |
| 12564 | /* 20701 */ "VQRSHRNsv8i8\0" |
| 12565 | /* 20714 */ "VQMOVNsv8i8\0" |
| 12566 | /* 20726 */ "VRSHRsv8i8\0" |
| 12567 | /* 20737 */ "VSHRsv8i8\0" |
| 12568 | /* 20747 */ "VCGTsv8i8\0" |
| 12569 | /* 20757 */ "VMAXsv8i8\0" |
| 12570 | /* 20767 */ "VABAuv8i8\0" |
| 12571 | /* 20777 */ "VRSRAuv8i8\0" |
| 12572 | /* 20788 */ "VSRAuv8i8\0" |
| 12573 | /* 20798 */ "VHSUBuv8i8\0" |
| 12574 | /* 20809 */ "VQSUBuv8i8\0" |
| 12575 | /* 20820 */ "VABDuv8i8\0" |
| 12576 | /* 20830 */ "VRHADDuv8i8\0" |
| 12577 | /* 20842 */ "VHADDuv8i8\0" |
| 12578 | /* 20853 */ "VQADDuv8i8\0" |
| 12579 | /* 20864 */ "VCGEuv8i8\0" |
| 12580 | /* 20874 */ "VPADALuv8i8\0" |
| 12581 | /* 20886 */ "VPADDLuv8i8\0" |
| 12582 | /* 20898 */ "VQSHLuv8i8\0" |
| 12583 | /* 20909 */ "VQRSHLuv8i8\0" |
| 12584 | /* 20921 */ "VRSHLuv8i8\0" |
| 12585 | /* 20932 */ "VSHLuv8i8\0" |
| 12586 | /* 20942 */ "VMINuv8i8\0" |
| 12587 | /* 20952 */ "VQSHRNuv8i8\0" |
| 12588 | /* 20964 */ "VQRSHRNuv8i8\0" |
| 12589 | /* 20977 */ "VQMOVNuv8i8\0" |
| 12590 | /* 20989 */ "VRSHRuv8i8\0" |
| 12591 | /* 21000 */ "VSHRuv8i8\0" |
| 12592 | /* 21010 */ "VCGTuv8i8\0" |
| 12593 | /* 21020 */ "VMAXuv8i8\0" |
| 12594 | /* 21030 */ "VQSHLsuv8i8\0" |
| 12595 | /* 21042 */ "VQMOVNsuv8i8\0" |
| 12596 | /* 21055 */ "VCGEzv8i8\0" |
| 12597 | /* 21065 */ "VCLEzv8i8\0" |
| 12598 | /* 21075 */ "VCEQzv8i8\0" |
| 12599 | /* 21085 */ "VCGTzv8i8\0" |
| 12600 | /* 21095 */ "VCLTzv8i8\0" |
| 12601 | /* 21105 */ "t2LDRBi8\0" |
| 12602 | /* 21114 */ "t2STRBi8\0" |
| 12603 | /* 21123 */ "t2LDRSBi8\0" |
| 12604 | /* 21133 */ "MVE_VSUBi8\0" |
| 12605 | /* 21144 */ "tSUBi8\0" |
| 12606 | /* 21151 */ "MVE_VCADDi8\0" |
| 12607 | /* 21163 */ "VPADDi8\0" |
| 12608 | /* 21171 */ "MVE_VADDi8\0" |
| 12609 | /* 21182 */ "tADDi8\0" |
| 12610 | /* 21189 */ "t2PLDi8\0" |
| 12611 | /* 21197 */ "t2LDRDi8\0" |
| 12612 | /* 21206 */ "t2STRDi8\0" |
| 12613 | /* 21215 */ "MVE_VQDMULHi8\0" |
| 12614 | /* 21229 */ "MVE_VQRDMULHi8\0" |
| 12615 | /* 21244 */ "t2LDRHi8\0" |
| 12616 | /* 21253 */ "t2STRHi8\0" |
| 12617 | /* 21262 */ "t2LDRSHi8\0" |
| 12618 | /* 21272 */ "t2PLIi8\0" |
| 12619 | /* 21280 */ "VSHLLi8\0" |
| 12620 | /* 21288 */ "MVE_VMULi8\0" |
| 12621 | /* 21299 */ "VSETLNi8\0" |
| 12622 | /* 21308 */ "MVE_VCMPi8\0" |
| 12623 | /* 21319 */ "tCMPi8\0" |
| 12624 | /* 21326 */ "t2LDRi8\0" |
| 12625 | /* 21334 */ "t2STRi8\0" |
| 12626 | /* 21342 */ "tSUBSi8\0" |
| 12627 | /* 21350 */ "tADDSi8\0" |
| 12628 | /* 21358 */ "tMOVi8\0" |
| 12629 | /* 21365 */ "t2PLDWi8\0" |
| 12630 | /* 21374 */ "MVE_VMLA_qr_i8\0" |
| 12631 | /* 21389 */ "MVE_VSUB_qr_i8\0" |
| 12632 | /* 21404 */ "MVE_VADD_qr_i8\0" |
| 12633 | /* 21419 */ "MVE_VMUL_qr_i8\0" |
| 12634 | /* 21434 */ "MVE_VMLAS_qr_i8\0" |
| 12635 | /* 21450 */ "MVE_VMOVimmi8\0" |
| 12636 | /* 21464 */ "MVE_VSHL_immi8\0" |
| 12637 | /* 21479 */ "MVE_VSLIimm8\0" |
| 12638 | /* 21492 */ "MVE_VSRIimm8\0" |
| 12639 | /* 21505 */ "MVE_VMULLBp8\0" |
| 12640 | /* 21518 */ "VMULLp8\0" |
| 12641 | /* 21526 */ "MVE_VMULLTp8\0" |
| 12642 | /* 21539 */ "VLD1q8\0" |
| 12643 | /* 21546 */ "VST1q8\0" |
| 12644 | /* 21553 */ "VREV32q8\0" |
| 12645 | /* 21562 */ "VLD2q8\0" |
| 12646 | /* 21569 */ "VST2q8\0" |
| 12647 | /* 21576 */ "VLD3q8\0" |
| 12648 | /* 21583 */ "VST3q8\0" |
| 12649 | /* 21590 */ "VREV64q8\0" |
| 12650 | /* 21599 */ "VLD4q8\0" |
| 12651 | /* 21606 */ "VST4q8\0" |
| 12652 | /* 21613 */ "VREV16q8\0" |
| 12653 | /* 21622 */ "VTRNq8\0" |
| 12654 | /* 21629 */ "VZIPq8\0" |
| 12655 | /* 21636 */ "VLD1DUPq8\0" |
| 12656 | /* 21646 */ "VLD3DUPq8\0" |
| 12657 | /* 21656 */ "VLD4DUPq8\0" |
| 12658 | /* 21666 */ "VUZPq8\0" |
| 12659 | /* 21673 */ "VEXTq8\0" |
| 12660 | /* 21680 */ "MVE_VPTv16s8\0" |
| 12661 | /* 21693 */ "MVE_VMINAs8\0" |
| 12662 | /* 21705 */ "MVE_VMAXAs8\0" |
| 12663 | /* 21717 */ "MVE_VMULLBs8\0" |
| 12664 | /* 21730 */ "MVE_VHSUBs8\0" |
| 12665 | /* 21742 */ "MVE_VQSUBs8\0" |
| 12666 | /* 21754 */ "MVE_VABDs8\0" |
| 12667 | /* 21765 */ "MVE_VHCADDs8\0" |
| 12668 | /* 21778 */ "MVE_VRHADDs8\0" |
| 12669 | /* 21791 */ "MVE_VHADDs8\0" |
| 12670 | /* 21803 */ "MVE_VQADDs8\0" |
| 12671 | /* 21815 */ "MVE_VQNEGs8\0" |
| 12672 | /* 21827 */ "MVE_VNEGs8\0" |
| 12673 | /* 21838 */ "MVE_VQDMLADHs8\0" |
| 12674 | /* 21853 */ "MVE_VQRDMLADHs8\0" |
| 12675 | /* 21869 */ "MVE_VQDMLSDHs8\0" |
| 12676 | /* 21884 */ "MVE_VQRDMLSDHs8\0" |
| 12677 | /* 21900 */ "MVE_VRMULHs8\0" |
| 12678 | /* 21913 */ "MVE_VMULHs8\0" |
| 12679 | /* 21925 */ "VPMINs8\0" |
| 12680 | /* 21933 */ "MVE_VMINs8\0" |
| 12681 | /* 21944 */ "VGETLNs8\0" |
| 12682 | /* 21953 */ "MVE_VCMPs8\0" |
| 12683 | /* 21964 */ "MVE_VQABSs8\0" |
| 12684 | /* 21976 */ "MVE_VABSs8\0" |
| 12685 | /* 21987 */ "MVE_VCLSs8\0" |
| 12686 | /* 21998 */ "MVE_VMULLTs8\0" |
| 12687 | /* 22011 */ "MVE_VABAVs8\0" |
| 12688 | /* 22023 */ "MVE_VMLADAVs8\0" |
| 12689 | /* 22037 */ "MVE_VMLSDAVs8\0" |
| 12690 | /* 22051 */ "MVE_VMINAVs8\0" |
| 12691 | /* 22064 */ "MVE_VMAXAVs8\0" |
| 12692 | /* 22077 */ "MVE_VMINVs8\0" |
| 12693 | /* 22089 */ "MVE_VMAXVs8\0" |
| 12694 | /* 22101 */ "VPMAXs8\0" |
| 12695 | /* 22109 */ "MVE_VMAXs8\0" |
| 12696 | /* 22120 */ "MVE_VQDMLADHXs8\0" |
| 12697 | /* 22136 */ "MVE_VQRDMLADHXs8\0" |
| 12698 | /* 22153 */ "MVE_VQDMLSDHXs8\0" |
| 12699 | /* 22169 */ "MVE_VQRDMLSDHXs8\0" |
| 12700 | /* 22186 */ "MVE_VCLZs8\0" |
| 12701 | /* 22197 */ "MVE_VMOV_from_lane_s8\0" |
| 12702 | /* 22219 */ "MVE_VHSUB_qr_s8\0" |
| 12703 | /* 22235 */ "MVE_VQSUB_qr_s8\0" |
| 12704 | /* 22251 */ "MVE_VHADD_qr_s8\0" |
| 12705 | /* 22267 */ "MVE_VQADD_qr_s8\0" |
| 12706 | /* 22283 */ "MVE_VQDMULH_qr_s8\0" |
| 12707 | /* 22301 */ "MVE_VQRDMULH_qr_s8\0" |
| 12708 | /* 22320 */ "MVE_VMLADAVas8\0" |
| 12709 | /* 22335 */ "MVE_VMLSDAVas8\0" |
| 12710 | /* 22350 */ "MVE_VQSHL_by_vecs8\0" |
| 12711 | /* 22369 */ "MVE_VQRSHL_by_vecs8\0" |
| 12712 | /* 22389 */ "MVE_VRSHL_by_vecs8\0" |
| 12713 | /* 22408 */ "MVE_VSHL_by_vecs8\0" |
| 12714 | /* 22426 */ "MVE_VQSHLimms8\0" |
| 12715 | /* 22441 */ "MVE_VRSHR_imms8\0" |
| 12716 | /* 22457 */ "MVE_VSHR_imms8\0" |
| 12717 | /* 22472 */ "MVE_VQSHLU_imms8\0" |
| 12718 | /* 22489 */ "MVE_VQDMLAH_qrs8\0" |
| 12719 | /* 22506 */ "MVE_VQRDMLAH_qrs8\0" |
| 12720 | /* 22524 */ "MVE_VQDMLASH_qrs8\0" |
| 12721 | /* 22542 */ "MVE_VQRDMLASH_qrs8\0" |
| 12722 | /* 22561 */ "MVE_VQSHL_qrs8\0" |
| 12723 | /* 22576 */ "MVE_VQRSHL_qrs8\0" |
| 12724 | /* 22592 */ "MVE_VRSHL_qrs8\0" |
| 12725 | /* 22607 */ "MVE_VSHL_qrs8\0" |
| 12726 | /* 22621 */ "MVE_VMLADAVxs8\0" |
| 12727 | /* 22636 */ "MVE_VMLSDAVxs8\0" |
| 12728 | /* 22651 */ "MVE_VMLADAVaxs8\0" |
| 12729 | /* 22667 */ "MVE_VMLSDAVaxs8\0" |
| 12730 | /* 22683 */ "MVE_VPTv16u8\0" |
| 12731 | /* 22696 */ "MVE_VMULLBu8\0" |
| 12732 | /* 22709 */ "MVE_VHSUBu8\0" |
| 12733 | /* 22721 */ "MVE_VQSUBu8\0" |
| 12734 | /* 22733 */ "MVE_VABDu8\0" |
| 12735 | /* 22744 */ "MVE_VRHADDu8\0" |
| 12736 | /* 22757 */ "MVE_VHADDu8\0" |
| 12737 | /* 22769 */ "MVE_VQADDu8\0" |
| 12738 | /* 22781 */ "MVE_VRMULHu8\0" |
| 12739 | /* 22794 */ "MVE_VMULHu8\0" |
| 12740 | /* 22806 */ "VPMINu8\0" |
| 12741 | /* 22814 */ "MVE_VMINu8\0" |
| 12742 | /* 22825 */ "VGETLNu8\0" |
| 12743 | /* 22834 */ "MVE_VCMPu8\0" |
| 12744 | /* 22845 */ "MVE_VDDUPu8\0" |
| 12745 | /* 22857 */ "MVE_VIDUPu8\0" |
| 12746 | /* 22869 */ "MVE_VDWDUPu8\0" |
| 12747 | /* 22882 */ "MVE_VIWDUPu8\0" |
| 12748 | /* 22895 */ "MVE_VMULLTu8\0" |
| 12749 | /* 22908 */ "MVE_VABAVu8\0" |
| 12750 | /* 22920 */ "MVE_VMLADAVu8\0" |
| 12751 | /* 22934 */ "MVE_VMINVu8\0" |
| 12752 | /* 22946 */ "MVE_VMAXVu8\0" |
| 12753 | /* 22958 */ "VPMAXu8\0" |
| 12754 | /* 22966 */ "MVE_VMAXu8\0" |
| 12755 | /* 22977 */ "MVE_VMOV_from_lane_u8\0" |
| 12756 | /* 22999 */ "MVE_VHSUB_qr_u8\0" |
| 12757 | /* 23015 */ "MVE_VQSUB_qr_u8\0" |
| 12758 | /* 23031 */ "MVE_VHADD_qr_u8\0" |
| 12759 | /* 23047 */ "MVE_VQADD_qr_u8\0" |
| 12760 | /* 23063 */ "MVE_VMLADAVau8\0" |
| 12761 | /* 23078 */ "MVE_VQSHL_by_vecu8\0" |
| 12762 | /* 23097 */ "MVE_VQRSHL_by_vecu8\0" |
| 12763 | /* 23117 */ "MVE_VRSHL_by_vecu8\0" |
| 12764 | /* 23136 */ "MVE_VSHL_by_vecu8\0" |
| 12765 | /* 23154 */ "MVE_VQSHLimmu8\0" |
| 12766 | /* 23169 */ "MVE_VRSHR_immu8\0" |
| 12767 | /* 23185 */ "MVE_VSHR_immu8\0" |
| 12768 | /* 23200 */ "MVE_VQSHL_qru8\0" |
| 12769 | /* 23215 */ "MVE_VQRSHL_qru8\0" |
| 12770 | /* 23231 */ "MVE_VRSHL_qru8\0" |
| 12771 | /* 23246 */ "MVE_VSHL_qru8\0" |
| 12772 | /* 23260 */ "CDE_CX1A\0" |
| 12773 | /* 23269 */ "MVE_VRINTf32A\0" |
| 12774 | /* 23283 */ "CDE_CX2A\0" |
| 12775 | /* 23292 */ "CDE_CX3A\0" |
| 12776 | /* 23301 */ "MVE_VRINTf16A\0" |
| 12777 | /* 23315 */ "CDE_CX1DA\0" |
| 12778 | /* 23325 */ "CDE_CX2DA\0" |
| 12779 | /* 23335 */ "CDE_CX3DA\0" |
| 12780 | /* 23345 */ "RFEDA\0" |
| 12781 | /* 23351 */ "t2LDA\0" |
| 12782 | /* 23357 */ "sysLDMDA\0" |
| 12783 | /* 23366 */ "sysSTMDA\0" |
| 12784 | /* 23375 */ "SRSDA\0" |
| 12785 | /* 23381 */ "VLDMDIA\0" |
| 12786 | /* 23389 */ "VSTMDIA\0" |
| 12787 | /* 23397 */ "t2RFEIA\0" |
| 12788 | /* 23405 */ "t2LDMIA\0" |
| 12789 | /* 23413 */ "sysLDMIA\0" |
| 12790 | /* 23422 */ "tLDMIA\0" |
| 12791 | /* 23429 */ "t2STMIA\0" |
| 12792 | /* 23437 */ "sysSTMIA\0" |
| 12793 | /* 23446 */ "VLDMQIA\0" |
| 12794 | /* 23454 */ "VSTMQIA\0" |
| 12795 | /* 23462 */ "VLDMSIA\0" |
| 12796 | /* 23470 */ "VSTMSIA\0" |
| 12797 | /* 23478 */ "t2SRSIA\0" |
| 12798 | /* 23486 */ "FLDMXIA\0" |
| 12799 | /* 23494 */ "FSTMXIA\0" |
| 12800 | /* 23502 */ "t2MLA\0" |
| 12801 | /* 23508 */ "t2SMMLA\0" |
| 12802 | /* 23516 */ "VUSMMLA\0" |
| 12803 | /* 23524 */ "VSMMLA\0" |
| 12804 | /* 23531 */ "VUMMLA\0" |
| 12805 | /* 23538 */ "VMMLA\0" |
| 12806 | /* 23544 */ "G_FMA\0" |
| 12807 | /* 23550 */ "G_STRICT_FMA\0" |
| 12808 | /* 23563 */ "t2TTA\0" |
| 12809 | /* 23569 */ "t2CRC32B\0" |
| 12810 | /* 23578 */ "t2B\0" |
| 12811 | /* 23582 */ "t2LDAB\0" |
| 12812 | /* 23589 */ "t2SXTAB\0" |
| 12813 | /* 23597 */ "t2UXTAB\0" |
| 12814 | /* 23605 */ "t2SMLABB\0" |
| 12815 | /* 23614 */ "t2SMLALBB\0" |
| 12816 | /* 23624 */ "t2SMULBB\0" |
| 12817 | /* 23633 */ "t2TBB\0" |
| 12818 | /* 23639 */ "JUMPTABLE_TBB\0" |
| 12819 | /* 23653 */ "t2SpeculationBarrierISBDSBEndBB\0" |
| 12820 | /* 23685 */ "t2SpeculationBarrierSBEndBB\0" |
| 12821 | /* 23713 */ "t2CRC32CB\0" |
| 12822 | /* 23723 */ "t2RFEDB\0" |
| 12823 | /* 23731 */ "t2LDMDB\0" |
| 12824 | /* 23739 */ "sysLDMDB\0" |
| 12825 | /* 23748 */ "t2STMDB\0" |
| 12826 | /* 23756 */ "sysSTMDB\0" |
| 12827 | /* 23765 */ "t2SRSDB\0" |
| 12828 | /* 23773 */ "RFEIB\0" |
| 12829 | /* 23779 */ "sysLDMIB\0" |
| 12830 | /* 23788 */ "sysSTMIB\0" |
| 12831 | /* 23797 */ "SRSIB\0" |
| 12832 | /* 23803 */ "t2STLB\0" |
| 12833 | /* 23810 */ "t2DMB\0" |
| 12834 | /* 23816 */ "SWPB\0" |
| 12835 | /* 23821 */ "PICLDRB\0" |
| 12836 | /* 23829 */ "PICSTRB\0" |
| 12837 | /* 23837 */ "t2SB\0" |
| 12838 | /* 23842 */ "t2DSB\0" |
| 12839 | /* 23848 */ "t2ISB\0" |
| 12840 | /* 23854 */ "PICLDRSB\0" |
| 12841 | /* 23863 */ "tLDRSB\0" |
| 12842 | /* 23870 */ "tRSB\0" |
| 12843 | /* 23875 */ "t2TSB\0" |
| 12844 | /* 23881 */ "t2SMLATB\0" |
| 12845 | /* 23890 */ "t2PKHTB\0" |
| 12846 | /* 23898 */ "t2SMLALTB\0" |
| 12847 | /* 23908 */ "t2SMULTB\0" |
| 12848 | /* 23917 */ "BF16_VCVTB\0" |
| 12849 | /* 23928 */ "t2SXTB\0" |
| 12850 | /* 23935 */ "tSXTB\0" |
| 12851 | /* 23941 */ "t2UXTB\0" |
| 12852 | /* 23948 */ "tUXTB\0" |
| 12853 | /* 23954 */ "t2QDSUB\0" |
| 12854 | /* 23962 */ "G_FSUB\0" |
| 12855 | /* 23969 */ "G_STRICT_FSUB\0" |
| 12856 | /* 23983 */ "G_ATOMICRMW_FSUB\0" |
| 12857 | /* 24000 */ "t2QSUB\0" |
| 12858 | /* 24007 */ "G_SUB\0" |
| 12859 | /* 24013 */ "G_ATOMICRMW_SUB\0" |
| 12860 | /* 24029 */ "t2SMLAWB\0" |
| 12861 | /* 24038 */ "t2SMULWB\0" |
| 12862 | /* 24047 */ "t2LDAEXB\0" |
| 12863 | /* 24056 */ "t2STLEXB\0" |
| 12864 | /* 24065 */ "t2LDREXB\0" |
| 12865 | /* 24074 */ "t2STREXB\0" |
| 12866 | /* 24083 */ "tB\0" |
| 12867 | /* 24086 */ "SHA1C\0" |
| 12868 | /* 24092 */ "t2PAC\0" |
| 12869 | /* 24098 */ "MVE_VSBC\0" |
| 12870 | /* 24107 */ "tSBC\0" |
| 12871 | /* 24112 */ "MVE_VADC\0" |
| 12872 | /* 24121 */ "tADC\0" |
| 12873 | /* 24126 */ "t2BFC\0" |
| 12874 | /* 24132 */ "MVE_VBIC\0" |
| 12875 | /* 24141 */ "tBIC\0" |
| 12876 | /* 24146 */ "G_INTRINSIC\0" |
| 12877 | /* 24158 */ "MVE_VSHLC\0" |
| 12878 | /* 24168 */ "AESIMC\0" |
| 12879 | /* 24175 */ "t2SMC\0" |
| 12880 | /* 24181 */ "AESMC\0" |
| 12881 | /* 24187 */ "t2CSINC\0" |
| 12882 | /* 24195 */ "G_FPTRUNC\0" |
| 12883 | /* 24205 */ "G_INTRINSIC_TRUNC\0" |
| 12884 | /* 24223 */ "G_TRUNC\0" |
| 12885 | /* 24231 */ "G_BUILD_VECTOR_TRUNC\0" |
| 12886 | /* 24252 */ "G_DYN_STACKALLOC\0" |
| 12887 | /* 24269 */ "VMSR_FPSCR_NZCVQC\0" |
| 12888 | /* 24287 */ "VMRS_FPSCR_NZCVQC\0" |
| 12889 | /* 24305 */ "t2MRC\0" |
| 12890 | /* 24311 */ "t2MRRC\0" |
| 12891 | /* 24318 */ "MOVr_TC\0" |
| 12892 | /* 24326 */ "t2HVC\0" |
| 12893 | /* 24332 */ "tSVC\0" |
| 12894 | /* 24337 */ "VMSR_FPEXC\0" |
| 12895 | /* 24348 */ "VMRS_FPEXC\0" |
| 12896 | /* 24359 */ "CDE_CX1D\0" |
| 12897 | /* 24368 */ "CDE_CX2D\0" |
| 12898 | /* 24377 */ "CDE_CX3D\0" |
| 12899 | /* 24386 */ "VNMLAD\0" |
| 12900 | /* 24393 */ "t2SMLAD\0" |
| 12901 | /* 24401 */ "VMLAD\0" |
| 12902 | /* 24407 */ "VFMAD\0" |
| 12903 | /* 24413 */ "G_FMAD\0" |
| 12904 | /* 24420 */ "VFNMAD\0" |
| 12905 | /* 24427 */ "G_INDEXED_SEXTLOAD\0" |
| 12906 | /* 24446 */ "G_SEXTLOAD\0" |
| 12907 | /* 24457 */ "G_INDEXED_ZEXTLOAD\0" |
| 12908 | /* 24476 */ "G_ZEXTLOAD\0" |
| 12909 | /* 24487 */ "G_INDEXED_LOAD\0" |
| 12910 | /* 24502 */ "G_LOAD\0" |
| 12911 | /* 24509 */ "VRINTAD\0" |
| 12912 | /* 24517 */ "t2SMUAD\0" |
| 12913 | /* 24525 */ "VSUBD\0" |
| 12914 | /* 24531 */ "tPICADD\0" |
| 12915 | /* 24539 */ "t2QDADD\0" |
| 12916 | /* 24547 */ "G_VECREDUCE_FADD\0" |
| 12917 | /* 24564 */ "G_FADD\0" |
| 12918 | /* 24571 */ "G_VECREDUCE_SEQ_FADD\0" |
| 12919 | /* 24592 */ "G_STRICT_FADD\0" |
| 12920 | /* 24606 */ "G_ATOMICRMW_FADD\0" |
| 12921 | /* 24623 */ "t2QADD\0" |
| 12922 | /* 24630 */ "G_VECREDUCE_ADD\0" |
| 12923 | /* 24646 */ "G_ADD\0" |
| 12924 | /* 24652 */ "G_PTR_ADD\0" |
| 12925 | /* 24662 */ "G_ATOMICRMW_ADD\0" |
| 12926 | /* 24678 */ "VADDD\0" |
| 12927 | /* 24684 */ "VSELGED\0" |
| 12928 | /* 24692 */ "VCMPED\0" |
| 12929 | /* 24699 */ "VNEGD\0" |
| 12930 | /* 24705 */ "VCVTBHD\0" |
| 12931 | /* 24713 */ "VTOSHD\0" |
| 12932 | /* 24720 */ "VCVTTHD\0" |
| 12933 | /* 24728 */ "VTOUHD\0" |
| 12934 | /* 24735 */ "VMSR_FPSID\0" |
| 12935 | /* 24746 */ "VMRS_FPSID\0" |
| 12936 | /* 24757 */ "t2SMLALD\0" |
| 12937 | /* 24766 */ "VFMALD\0" |
| 12938 | /* 24773 */ "t2SMLSLD\0" |
| 12939 | /* 24782 */ "VFMSLD\0" |
| 12940 | /* 24789 */ "VTOSLD\0" |
| 12941 | /* 24796 */ "VNMULD\0" |
| 12942 | /* 24803 */ "VMULD\0" |
| 12943 | /* 24809 */ "VTOULD\0" |
| 12944 | /* 24816 */ "VFP_VMINNMD\0" |
| 12945 | /* 24828 */ "VFP_VMAXNMD\0" |
| 12946 | /* 24840 */ "VSCCLRMD\0" |
| 12947 | /* 24849 */ "VRINTMD\0" |
| 12948 | /* 24857 */ "G_ATOMICRMW_NAND\0" |
| 12949 | /* 24874 */ "MVE_VAND\0" |
| 12950 | /* 24883 */ "G_VECREDUCE_AND\0" |
| 12951 | /* 24899 */ "G_AND\0" |
| 12952 | /* 24905 */ "G_ATOMICRMW_AND\0" |
| 12953 | /* 24921 */ "tAND\0" |
| 12954 | /* 24926 */ "tSETEND\0" |
| 12955 | /* 24934 */ "LIFETIME_END\0" |
| 12956 | /* 24947 */ "tBRIND\0" |
| 12957 | /* 24954 */ "G_BRCOND\0" |
| 12958 | /* 24963 */ "VRINTND\0" |
| 12959 | /* 24971 */ "G_LLROUND\0" |
| 12960 | /* 24981 */ "G_LROUND\0" |
| 12961 | /* 24990 */ "G_INTRINSIC_ROUND\0" |
| 12962 | /* 25008 */ "G_INTRINSIC_FPTRUNC_ROUND\0" |
| 12963 | /* 25034 */ "tTAILJMPdND\0" |
| 12964 | /* 25046 */ "VSHTOD\0" |
| 12965 | /* 25053 */ "VUHTOD\0" |
| 12966 | /* 25060 */ "VSITOD\0" |
| 12967 | /* 25067 */ "VUITOD\0" |
| 12968 | /* 25074 */ "VSLTOD\0" |
| 12969 | /* 25081 */ "VULTOD\0" |
| 12970 | /* 25088 */ "VCMPD\0" |
| 12971 | /* 25094 */ "VRINTPD\0" |
| 12972 | /* 25102 */ "VLD3d32_UPD\0" |
| 12973 | /* 25114 */ "VST3d32_UPD\0" |
| 12974 | /* 25126 */ "VLD4d32_UPD\0" |
| 12975 | /* 25138 */ "VST4d32_UPD\0" |
| 12976 | /* 25150 */ "VLD1LNd32_UPD\0" |
| 12977 | /* 25164 */ "VST1LNd32_UPD\0" |
| 12978 | /* 25178 */ "VLD2LNd32_UPD\0" |
| 12979 | /* 25192 */ "VST2LNd32_UPD\0" |
| 12980 | /* 25206 */ "VLD3LNd32_UPD\0" |
| 12981 | /* 25220 */ "VST3LNd32_UPD\0" |
| 12982 | /* 25234 */ "VLD4LNd32_UPD\0" |
| 12983 | /* 25248 */ "VST4LNd32_UPD\0" |
| 12984 | /* 25262 */ "VLD3DUPd32_UPD\0" |
| 12985 | /* 25277 */ "VLD4DUPd32_UPD\0" |
| 12986 | /* 25292 */ "VLD3q32_UPD\0" |
| 12987 | /* 25304 */ "VST3q32_UPD\0" |
| 12988 | /* 25316 */ "VLD4q32_UPD\0" |
| 12989 | /* 25328 */ "VST4q32_UPD\0" |
| 12990 | /* 25340 */ "VLD2LNq32_UPD\0" |
| 12991 | /* 25354 */ "VST2LNq32_UPD\0" |
| 12992 | /* 25368 */ "VLD3LNq32_UPD\0" |
| 12993 | /* 25382 */ "VST3LNq32_UPD\0" |
| 12994 | /* 25396 */ "VLD4LNq32_UPD\0" |
| 12995 | /* 25410 */ "VST4LNq32_UPD\0" |
| 12996 | /* 25424 */ "VLD3DUPq32_UPD\0" |
| 12997 | /* 25439 */ "VLD4DUPq32_UPD\0" |
| 12998 | /* 25454 */ "VLD3d16_UPD\0" |
| 12999 | /* 25466 */ "VST3d16_UPD\0" |
| 13000 | /* 25478 */ "VLD4d16_UPD\0" |
| 13001 | /* 25490 */ "VST4d16_UPD\0" |
| 13002 | /* 25502 */ "VLD1LNd16_UPD\0" |
| 13003 | /* 25516 */ "VST1LNd16_UPD\0" |
| 13004 | /* 25530 */ "VLD2LNd16_UPD\0" |
| 13005 | /* 25544 */ "VST2LNd16_UPD\0" |
| 13006 | /* 25558 */ "VLD3LNd16_UPD\0" |
| 13007 | /* 25572 */ "VST3LNd16_UPD\0" |
| 13008 | /* 25586 */ "VLD4LNd16_UPD\0" |
| 13009 | /* 25600 */ "VST4LNd16_UPD\0" |
| 13010 | /* 25614 */ "VLD3DUPd16_UPD\0" |
| 13011 | /* 25629 */ "VLD4DUPd16_UPD\0" |
| 13012 | /* 25644 */ "VLD3q16_UPD\0" |
| 13013 | /* 25656 */ "VST3q16_UPD\0" |
| 13014 | /* 25668 */ "VLD4q16_UPD\0" |
| 13015 | /* 25680 */ "VST4q16_UPD\0" |
| 13016 | /* 25692 */ "VLD2LNq16_UPD\0" |
| 13017 | /* 25706 */ "VST2LNq16_UPD\0" |
| 13018 | /* 25720 */ "VLD3LNq16_UPD\0" |
| 13019 | /* 25734 */ "VST3LNq16_UPD\0" |
| 13020 | /* 25748 */ "VLD4LNq16_UPD\0" |
| 13021 | /* 25762 */ "VST4LNq16_UPD\0" |
| 13022 | /* 25776 */ "VLD3DUPq16_UPD\0" |
| 13023 | /* 25791 */ "VLD4DUPq16_UPD\0" |
| 13024 | /* 25806 */ "VLD3d8_UPD\0" |
| 13025 | /* 25817 */ "VST3d8_UPD\0" |
| 13026 | /* 25828 */ "VLD4d8_UPD\0" |
| 13027 | /* 25839 */ "VST4d8_UPD\0" |
| 13028 | /* 25850 */ "VLD1LNd8_UPD\0" |
| 13029 | /* 25863 */ "VST1LNd8_UPD\0" |
| 13030 | /* 25876 */ "VLD2LNd8_UPD\0" |
| 13031 | /* 25889 */ "VST2LNd8_UPD\0" |
| 13032 | /* 25902 */ "VLD3LNd8_UPD\0" |
| 13033 | /* 25915 */ "VST3LNd8_UPD\0" |
| 13034 | /* 25928 */ "VLD4LNd8_UPD\0" |
| 13035 | /* 25941 */ "VST4LNd8_UPD\0" |
| 13036 | /* 25954 */ "VLD3DUPd8_UPD\0" |
| 13037 | /* 25968 */ "VLD4DUPd8_UPD\0" |
| 13038 | /* 25982 */ "VLD3q8_UPD\0" |
| 13039 | /* 25993 */ "VST3q8_UPD\0" |
| 13040 | /* 26004 */ "VLD4q8_UPD\0" |
| 13041 | /* 26015 */ "VST4q8_UPD\0" |
| 13042 | /* 26026 */ "VLD3DUPq8_UPD\0" |
| 13043 | /* 26040 */ "VLD4DUPq8_UPD\0" |
| 13044 | /* 26054 */ "RFEDA_UPD\0" |
| 13045 | /* 26064 */ "sysLDMDA_UPD\0" |
| 13046 | /* 26077 */ "sysSTMDA_UPD\0" |
| 13047 | /* 26090 */ "SRSDA_UPD\0" |
| 13048 | /* 26100 */ "VLDMDIA_UPD\0" |
| 13049 | /* 26112 */ "VSTMDIA_UPD\0" |
| 13050 | /* 26124 */ "RFEIA_UPD\0" |
| 13051 | /* 26134 */ "t2LDMIA_UPD\0" |
| 13052 | /* 26146 */ "sysLDMIA_UPD\0" |
| 13053 | /* 26159 */ "tLDMIA_UPD\0" |
| 13054 | /* 26170 */ "t2STMIA_UPD\0" |
| 13055 | /* 26182 */ "sysSTMIA_UPD\0" |
| 13056 | /* 26195 */ "tSTMIA_UPD\0" |
| 13057 | /* 26206 */ "VLDMSIA_UPD\0" |
| 13058 | /* 26218 */ "VSTMSIA_UPD\0" |
| 13059 | /* 26230 */ "t2SRSIA_UPD\0" |
| 13060 | /* 26242 */ "FLDMXIA_UPD\0" |
| 13061 | /* 26254 */ "FSTMXIA_UPD\0" |
| 13062 | /* 26266 */ "VLDMDDB_UPD\0" |
| 13063 | /* 26278 */ "VSTMDDB_UPD\0" |
| 13064 | /* 26290 */ "RFEDB_UPD\0" |
| 13065 | /* 26300 */ "t2LDMDB_UPD\0" |
| 13066 | /* 26312 */ "sysLDMDB_UPD\0" |
| 13067 | /* 26325 */ "t2STMDB_UPD\0" |
| 13068 | /* 26337 */ "sysSTMDB_UPD\0" |
| 13069 | /* 26350 */ "VLDMSDB_UPD\0" |
| 13070 | /* 26362 */ "VSTMSDB_UPD\0" |
| 13071 | /* 26374 */ "t2SRSDB_UPD\0" |
| 13072 | /* 26386 */ "FLDMXDB_UPD\0" |
| 13073 | /* 26398 */ "FSTMXDB_UPD\0" |
| 13074 | /* 26410 */ "RFEIB_UPD\0" |
| 13075 | /* 26420 */ "sysLDMIB_UPD\0" |
| 13076 | /* 26433 */ "sysSTMIB_UPD\0" |
| 13077 | /* 26446 */ "SRSIB_UPD\0" |
| 13078 | /* 26456 */ "VLD3d32Pseudo_UPD\0" |
| 13079 | /* 26474 */ "VST3d32Pseudo_UPD\0" |
| 13080 | /* 26492 */ "VLD4d32Pseudo_UPD\0" |
| 13081 | /* 26510 */ "VST4d32Pseudo_UPD\0" |
| 13082 | /* 26528 */ "VLD2LNd32Pseudo_UPD\0" |
| 13083 | /* 26548 */ "VST2LNd32Pseudo_UPD\0" |
| 13084 | /* 26568 */ "VLD3LNd32Pseudo_UPD\0" |
| 13085 | /* 26588 */ "VST3LNd32Pseudo_UPD\0" |
| 13086 | /* 26608 */ "VLD4LNd32Pseudo_UPD\0" |
| 13087 | /* 26628 */ "VST4LNd32Pseudo_UPD\0" |
| 13088 | /* 26648 */ "VLD3DUPd32Pseudo_UPD\0" |
| 13089 | /* 26669 */ "VLD4DUPd32Pseudo_UPD\0" |
| 13090 | /* 26690 */ "VLD3q32Pseudo_UPD\0" |
| 13091 | /* 26708 */ "VST3q32Pseudo_UPD\0" |
| 13092 | /* 26726 */ "VLD4q32Pseudo_UPD\0" |
| 13093 | /* 26744 */ "VST4q32Pseudo_UPD\0" |
| 13094 | /* 26762 */ "VLD1LNq32Pseudo_UPD\0" |
| 13095 | /* 26782 */ "VST1LNq32Pseudo_UPD\0" |
| 13096 | /* 26802 */ "VLD2LNq32Pseudo_UPD\0" |
| 13097 | /* 26822 */ "VST2LNq32Pseudo_UPD\0" |
| 13098 | /* 26842 */ "VLD3LNq32Pseudo_UPD\0" |
| 13099 | /* 26862 */ "VST3LNq32Pseudo_UPD\0" |
| 13100 | /* 26882 */ "VLD4LNq32Pseudo_UPD\0" |
| 13101 | /* 26902 */ "VST4LNq32Pseudo_UPD\0" |
| 13102 | /* 26922 */ "VLD3d16Pseudo_UPD\0" |
| 13103 | /* 26940 */ "VST3d16Pseudo_UPD\0" |
| 13104 | /* 26958 */ "VLD4d16Pseudo_UPD\0" |
| 13105 | /* 26976 */ "VST4d16Pseudo_UPD\0" |
| 13106 | /* 26994 */ "VLD2LNd16Pseudo_UPD\0" |
| 13107 | /* 27014 */ "VST2LNd16Pseudo_UPD\0" |
| 13108 | /* 27034 */ "VLD3LNd16Pseudo_UPD\0" |
| 13109 | /* 27054 */ "VST3LNd16Pseudo_UPD\0" |
| 13110 | /* 27074 */ "VLD4LNd16Pseudo_UPD\0" |
| 13111 | /* 27094 */ "VST4LNd16Pseudo_UPD\0" |
| 13112 | /* 27114 */ "VLD3DUPd16Pseudo_UPD\0" |
| 13113 | /* 27135 */ "VLD4DUPd16Pseudo_UPD\0" |
| 13114 | /* 27156 */ "VLD3q16Pseudo_UPD\0" |
| 13115 | /* 27174 */ "VST3q16Pseudo_UPD\0" |
| 13116 | /* 27192 */ "VLD4q16Pseudo_UPD\0" |
| 13117 | /* 27210 */ "VST4q16Pseudo_UPD\0" |
| 13118 | /* 27228 */ "VLD1LNq16Pseudo_UPD\0" |
| 13119 | /* 27248 */ "VST1LNq16Pseudo_UPD\0" |
| 13120 | /* 27268 */ "VLD2LNq16Pseudo_UPD\0" |
| 13121 | /* 27288 */ "VST2LNq16Pseudo_UPD\0" |
| 13122 | /* 27308 */ "VLD3LNq16Pseudo_UPD\0" |
| 13123 | /* 27328 */ "VST3LNq16Pseudo_UPD\0" |
| 13124 | /* 27348 */ "VLD4LNq16Pseudo_UPD\0" |
| 13125 | /* 27368 */ "VST4LNq16Pseudo_UPD\0" |
| 13126 | /* 27388 */ "VLD3d8Pseudo_UPD\0" |
| 13127 | /* 27405 */ "VST3d8Pseudo_UPD\0" |
| 13128 | /* 27422 */ "VLD4d8Pseudo_UPD\0" |
| 13129 | /* 27439 */ "VST4d8Pseudo_UPD\0" |
| 13130 | /* 27456 */ "VLD2LNd8Pseudo_UPD\0" |
| 13131 | /* 27475 */ "VST2LNd8Pseudo_UPD\0" |
| 13132 | /* 27494 */ "VLD3LNd8Pseudo_UPD\0" |
| 13133 | /* 27513 */ "VST3LNd8Pseudo_UPD\0" |
| 13134 | /* 27532 */ "VLD4LNd8Pseudo_UPD\0" |
| 13135 | /* 27551 */ "VST4LNd8Pseudo_UPD\0" |
| 13136 | /* 27570 */ "VLD3DUPd8Pseudo_UPD\0" |
| 13137 | /* 27590 */ "VLD4DUPd8Pseudo_UPD\0" |
| 13138 | /* 27610 */ "VLD3q8Pseudo_UPD\0" |
| 13139 | /* 27627 */ "VST3q8Pseudo_UPD\0" |
| 13140 | /* 27644 */ "VLD4q8Pseudo_UPD\0" |
| 13141 | /* 27661 */ "VST4q8Pseudo_UPD\0" |
| 13142 | /* 27678 */ "VLD1LNq8Pseudo_UPD\0" |
| 13143 | /* 27697 */ "VST1LNq8Pseudo_UPD\0" |
| 13144 | /* 27716 */ "VLD1q32HighQPseudo_UPD\0" |
| 13145 | /* 27739 */ "VST1q32HighQPseudo_UPD\0" |
| 13146 | /* 27762 */ "VLD1q64HighQPseudo_UPD\0" |
| 13147 | /* 27785 */ "VST1q64HighQPseudo_UPD\0" |
| 13148 | /* 27808 */ "VLD1q16HighQPseudo_UPD\0" |
| 13149 | /* 27831 */ "VST1q16HighQPseudo_UPD\0" |
| 13150 | /* 27854 */ "VLD1q8HighQPseudo_UPD\0" |
| 13151 | /* 27876 */ "VST1q8HighQPseudo_UPD\0" |
| 13152 | /* 27898 */ "VLD1q32LowQPseudo_UPD\0" |
| 13153 | /* 27920 */ "VST1q32LowQPseudo_UPD\0" |
| 13154 | /* 27942 */ "VLD1q64LowQPseudo_UPD\0" |
| 13155 | /* 27964 */ "VST1q64LowQPseudo_UPD\0" |
| 13156 | /* 27986 */ "VLD1q16LowQPseudo_UPD\0" |
| 13157 | /* 28008 */ "VST1q16LowQPseudo_UPD\0" |
| 13158 | /* 28030 */ "VLD1q8LowQPseudo_UPD\0" |
| 13159 | /* 28051 */ "VST1q8LowQPseudo_UPD\0" |
| 13160 | /* 28072 */ "VLD1q32HighTPseudo_UPD\0" |
| 13161 | /* 28095 */ "VST1q32HighTPseudo_UPD\0" |
| 13162 | /* 28118 */ "VLD1q64HighTPseudo_UPD\0" |
| 13163 | /* 28141 */ "VST1q64HighTPseudo_UPD\0" |
| 13164 | /* 28164 */ "VLD1q16HighTPseudo_UPD\0" |
| 13165 | /* 28187 */ "VST1q16HighTPseudo_UPD\0" |
| 13166 | /* 28210 */ "VLD1q8HighTPseudo_UPD\0" |
| 13167 | /* 28232 */ "VST1q8HighTPseudo_UPD\0" |
| 13168 | /* 28254 */ "VLD1q32LowTPseudo_UPD\0" |
| 13169 | /* 28276 */ "VST1q32LowTPseudo_UPD\0" |
| 13170 | /* 28298 */ "VLD1q64LowTPseudo_UPD\0" |
| 13171 | /* 28320 */ "VST1q64LowTPseudo_UPD\0" |
| 13172 | /* 28342 */ "VLD1q16LowTPseudo_UPD\0" |
| 13173 | /* 28364 */ "VST1q16LowTPseudo_UPD\0" |
| 13174 | /* 28386 */ "VLD1q8LowTPseudo_UPD\0" |
| 13175 | /* 28407 */ "VST1q8LowTPseudo_UPD\0" |
| 13176 | /* 28428 */ "VLD3DUPq32OddPseudo_UPD\0" |
| 13177 | /* 28452 */ "VLD4DUPq32OddPseudo_UPD\0" |
| 13178 | /* 28476 */ "VLD3DUPq16OddPseudo_UPD\0" |
| 13179 | /* 28500 */ "VLD4DUPq16OddPseudo_UPD\0" |
| 13180 | /* 28524 */ "VLD3DUPq8OddPseudo_UPD\0" |
| 13181 | /* 28547 */ "VLD4DUPq8OddPseudo_UPD\0" |
| 13182 | /* 28570 */ "VLD3q32oddPseudo_UPD\0" |
| 13183 | /* 28591 */ "VST3q32oddPseudo_UPD\0" |
| 13184 | /* 28612 */ "VLD4q32oddPseudo_UPD\0" |
| 13185 | /* 28633 */ "VST4q32oddPseudo_UPD\0" |
| 13186 | /* 28654 */ "VLD3q16oddPseudo_UPD\0" |
| 13187 | /* 28675 */ "VST3q16oddPseudo_UPD\0" |
| 13188 | /* 28696 */ "VLD4q16oddPseudo_UPD\0" |
| 13189 | /* 28717 */ "VST4q16oddPseudo_UPD\0" |
| 13190 | /* 28738 */ "VLD3q8oddPseudo_UPD\0" |
| 13191 | /* 28758 */ "VST3q8oddPseudo_UPD\0" |
| 13192 | /* 28778 */ "VLD4q8oddPseudo_UPD\0" |
| 13193 | /* 28798 */ "VST4q8oddPseudo_UPD\0" |
| 13194 | /* 28818 */ "VSELEQD\0" |
| 13195 | /* 28826 */ "LOAD_STACK_GUARD\0" |
| 13196 | /* 28843 */ "VLDRD\0" |
| 13197 | /* 28849 */ "VTOSIRD\0" |
| 13198 | /* 28857 */ "VTOUIRD\0" |
| 13199 | /* 28865 */ "VMOVRRD\0" |
| 13200 | /* 28873 */ "VRINTRD\0" |
| 13201 | /* 28881 */ "VSTRD\0" |
| 13202 | /* 28887 */ "VCVTASD\0" |
| 13203 | /* 28895 */ "VABSD\0" |
| 13204 | /* 28901 */ "AESD\0" |
| 13205 | /* 28906 */ "VNMLSD\0" |
| 13206 | /* 28913 */ "t2SMLSD\0" |
| 13207 | /* 28921 */ "VMLSD\0" |
| 13208 | /* 28927 */ "VFMSD\0" |
| 13209 | /* 28933 */ "VFNMSD\0" |
| 13210 | /* 28940 */ "VCVTMSD\0" |
| 13211 | /* 28948 */ "VCVTNSD\0" |
| 13212 | /* 28956 */ "VCVTPSD\0" |
| 13213 | /* 28964 */ "VCVTSD\0" |
| 13214 | /* 28971 */ "t2SMUSD\0" |
| 13215 | /* 28979 */ "VSELVSD\0" |
| 13216 | /* 28987 */ "VSELGTD\0" |
| 13217 | /* 28995 */ "VUSDOTD\0" |
| 13218 | /* 29003 */ "VSDOTD\0" |
| 13219 | /* 29010 */ "VUDOTD\0" |
| 13220 | /* 29017 */ "BF16VDOTI_VDOTD\0" |
| 13221 | /* 29033 */ "BF16VDOTS_VDOTD\0" |
| 13222 | /* 29049 */ "VSQRTD\0" |
| 13223 | /* 29056 */ "FCONSTD\0" |
| 13224 | /* 29064 */ "VCVTAUD\0" |
| 13225 | /* 29072 */ "VCVTMUD\0" |
| 13226 | /* 29080 */ "VCVTNUD\0" |
| 13227 | /* 29088 */ "VCVTPUD\0" |
| 13228 | /* 29096 */ "VDIVD\0" |
| 13229 | /* 29102 */ "VMOVD\0" |
| 13230 | /* 29108 */ "t2LDAEXD\0" |
| 13231 | /* 29117 */ "t2STLEXD\0" |
| 13232 | /* 29126 */ "t2LDREXD\0" |
| 13233 | /* 29135 */ "t2STREXD\0" |
| 13234 | /* 29144 */ "VRINTXD\0" |
| 13235 | /* 29152 */ "VCMPEZD\0" |
| 13236 | /* 29160 */ "VTOSIZD\0" |
| 13237 | /* 29168 */ "VTOUIZD\0" |
| 13238 | /* 29176 */ "VCMPZD\0" |
| 13239 | /* 29183 */ "VRINTZD\0" |
| 13240 | /* 29191 */ "PSEUDO_PROBE\0" |
| 13241 | /* 29204 */ "G_SSUBE\0" |
| 13242 | /* 29212 */ "G_USUBE\0" |
| 13243 | /* 29220 */ "SPACE\0" |
| 13244 | /* 29226 */ "G_FENCE\0" |
| 13245 | /* 29234 */ "ARITH_FENCE\0" |
| 13246 | /* 29246 */ "REG_SEQUENCE\0" |
| 13247 | /* 29259 */ "G_SADDE\0" |
| 13248 | /* 29267 */ "G_UADDE\0" |
| 13249 | /* 29275 */ "G_GET_FPMODE\0" |
| 13250 | /* 29288 */ "G_RESET_FPMODE\0" |
| 13251 | /* 29303 */ "G_SET_FPMODE\0" |
| 13252 | /* 29316 */ "G_FMINNUM_IEEE\0" |
| 13253 | /* 29331 */ "G_FMAXNUM_IEEE\0" |
| 13254 | /* 29346 */ "t2LE\0" |
| 13255 | /* 29351 */ "G_VSCALE\0" |
| 13256 | /* 29360 */ "G_JUMP_TABLE\0" |
| 13257 | /* 29373 */ "BUNDLE\0" |
| 13258 | /* 29380 */ "G_MEMCPY_INLINE\0" |
| 13259 | /* 29396 */ "LOCAL_ESCAPE\0" |
| 13260 | /* 29409 */ "G_STACKRESTORE\0" |
| 13261 | /* 29424 */ "G_INDEXED_STORE\0" |
| 13262 | /* 29440 */ "G_STORE\0" |
| 13263 | /* 29448 */ "t2LDC2_PRE\0" |
| 13264 | /* 29459 */ "t2STC2_PRE\0" |
| 13265 | /* 29470 */ "t2LDRB_PRE\0" |
| 13266 | /* 29481 */ "t2STRB_PRE\0" |
| 13267 | /* 29492 */ "t2LDRSB_PRE\0" |
| 13268 | /* 29504 */ "t2LDC_PRE\0" |
| 13269 | /* 29514 */ "t2STC_PRE\0" |
| 13270 | /* 29524 */ "t2LDRD_PRE\0" |
| 13271 | /* 29535 */ "t2STRD_PRE\0" |
| 13272 | /* 29546 */ "t2LDRH_PRE\0" |
| 13273 | /* 29557 */ "t2STRH_PRE\0" |
| 13274 | /* 29568 */ "t2LDRSH_PRE\0" |
| 13275 | /* 29580 */ "t2LDC2L_PRE\0" |
| 13276 | /* 29592 */ "t2STC2L_PRE\0" |
| 13277 | /* 29604 */ "t2LDCL_PRE\0" |
| 13278 | /* 29615 */ "t2STCL_PRE\0" |
| 13279 | /* 29626 */ "t2LDR_PRE\0" |
| 13280 | /* 29636 */ "t2STR_PRE\0" |
| 13281 | /* 29646 */ "AESE\0" |
| 13282 | /* 29651 */ "G_BITREVERSE\0" |
| 13283 | /* 29664 */ "DBG_VALUE\0" |
| 13284 | /* 29674 */ "G_GLOBAL_VALUE\0" |
| 13285 | /* 29689 */ "G_PTRAUTH_GLOBAL_VALUE\0" |
| 13286 | /* 29712 */ "CONVERGENCECTRL_GLUE\0" |
| 13287 | /* 29733 */ "G_STACKSAVE\0" |
| 13288 | /* 29745 */ "G_MEMMOVE\0" |
| 13289 | /* 29755 */ "G_FREEZE\0" |
| 13290 | /* 29764 */ "G_FCANONICALIZE\0" |
| 13291 | /* 29780 */ "t2UDF\0" |
| 13292 | /* 29786 */ "tUDF\0" |
| 13293 | /* 29791 */ "G_CTLZ_ZERO_UNDEF\0" |
| 13294 | /* 29809 */ "G_CTTZ_ZERO_UNDEF\0" |
| 13295 | /* 29827 */ "G_IMPLICIT_DEF\0" |
| 13296 | /* 29842 */ "DBG_INSTR_REF\0" |
| 13297 | /* 29856 */ "t2DBG\0" |
| 13298 | /* 29862 */ "t2PACG\0" |
| 13299 | /* 29869 */ "G_FNEG\0" |
| 13300 | /* 29876 */ "t2CSNEG\0" |
| 13301 | /* 29884 */ "EXTRACT_SUBREG\0" |
| 13302 | /* 29899 */ "INSERT_SUBREG\0" |
| 13303 | /* 29913 */ "G_SEXT_INREG\0" |
| 13304 | /* 29926 */ "LDRB_PRE_REG\0" |
| 13305 | /* 29939 */ "STRB_PRE_REG\0" |
| 13306 | /* 29952 */ "LDR_PRE_REG\0" |
| 13307 | /* 29964 */ "STR_PRE_REG\0" |
| 13308 | /* 29976 */ "SUBREG_TO_REG\0" |
| 13309 | /* 29990 */ "LDRB_POST_REG\0" |
| 13310 | /* 30004 */ "STRB_POST_REG\0" |
| 13311 | /* 30018 */ "LDR_POST_REG\0" |
| 13312 | /* 30031 */ "STR_POST_REG\0" |
| 13313 | /* 30044 */ "LDRBT_POST_REG\0" |
| 13314 | /* 30059 */ "STRBT_POST_REG\0" |
| 13315 | /* 30074 */ "LDRT_POST_REG\0" |
| 13316 | /* 30088 */ "STRT_POST_REG\0" |
| 13317 | /* 30102 */ "G_ATOMIC_CMPXCHG\0" |
| 13318 | /* 30119 */ "G_ATOMICRMW_XCHG\0" |
| 13319 | /* 30136 */ "G_FLOG\0" |
| 13320 | /* 30143 */ "G_VAARG\0" |
| 13321 | /* 30151 */ "PREALLOCATED_ARG\0" |
| 13322 | /* 30168 */ "t2SG\0" |
| 13323 | /* 30173 */ "t2AUTG\0" |
| 13324 | /* 30180 */ "SHA1H\0" |
| 13325 | /* 30186 */ "t2CRC32H\0" |
| 13326 | /* 30195 */ "SHA256H\0" |
| 13327 | /* 30203 */ "t2LDAH\0" |
| 13328 | /* 30210 */ "VNMLAH\0" |
| 13329 | /* 30217 */ "VMLAH\0" |
| 13330 | /* 30223 */ "VFMAH\0" |
| 13331 | /* 30229 */ "VFNMAH\0" |
| 13332 | /* 30236 */ "VRINTAH\0" |
| 13333 | /* 30244 */ "t2SXTAH\0" |
| 13334 | /* 30252 */ "t2UXTAH\0" |
| 13335 | /* 30260 */ "t2TBH\0" |
| 13336 | /* 30266 */ "JUMPTABLE_TBH\0" |
| 13337 | /* 30280 */ "VSUBH\0" |
| 13338 | /* 30286 */ "t2CRC32CH\0" |
| 13339 | /* 30296 */ "G_PREFETCH\0" |
| 13340 | /* 30307 */ "VCVTBDH\0" |
| 13341 | /* 30315 */ "VADDH\0" |
| 13342 | /* 30321 */ "VCVTTDH\0" |
| 13343 | /* 30329 */ "VSELGEH\0" |
| 13344 | /* 30337 */ "VCMPEH\0" |
| 13345 | /* 30344 */ "VNEGH\0" |
| 13346 | /* 30350 */ "VTOSHH\0" |
| 13347 | /* 30357 */ "VTOUHH\0" |
| 13348 | /* 30364 */ "VTOSLH\0" |
| 13349 | /* 30371 */ "t2STLH\0" |
| 13350 | /* 30378 */ "VNMULH\0" |
| 13351 | /* 30385 */ "G_SMULH\0" |
| 13352 | /* 30393 */ "G_UMULH\0" |
| 13353 | /* 30401 */ "VMULH\0" |
| 13354 | /* 30407 */ "VTOULH\0" |
| 13355 | /* 30414 */ "VFP_VMINNMH\0" |
| 13356 | /* 30426 */ "VFP_VMAXNMH\0" |
| 13357 | /* 30438 */ "VRINTMH\0" |
| 13358 | /* 30446 */ "G_FTANH\0" |
| 13359 | /* 30454 */ "G_FSINH\0" |
| 13360 | /* 30462 */ "VRINTNH\0" |
| 13361 | /* 30470 */ "VSHTOH\0" |
| 13362 | /* 30477 */ "VUHTOH\0" |
| 13363 | /* 30484 */ "VSITOH\0" |
| 13364 | /* 30491 */ "VUITOH\0" |
| 13365 | /* 30498 */ "VSLTOH\0" |
| 13366 | /* 30505 */ "VULTOH\0" |
| 13367 | /* 30512 */ "VCMPH\0" |
| 13368 | /* 30518 */ "VRINTPH\0" |
| 13369 | /* 30526 */ "VSELEQH\0" |
| 13370 | /* 30534 */ "PICLDRH\0" |
| 13371 | /* 30542 */ "VLDRH\0" |
| 13372 | /* 30548 */ "VTOSIRH\0" |
| 13373 | /* 30556 */ "VTOUIRH\0" |
| 13374 | /* 30564 */ "VRINTRH\0" |
| 13375 | /* 30572 */ "PICSTRH\0" |
| 13376 | /* 30580 */ "VSTRH\0" |
| 13377 | /* 30586 */ "VMOVRH\0" |
| 13378 | /* 30593 */ "VCVTASH\0" |
| 13379 | /* 30601 */ "VABSH\0" |
| 13380 | /* 30607 */ "VCVTBSH\0" |
| 13381 | /* 30615 */ "VNMLSH\0" |
| 13382 | /* 30622 */ "VMLSH\0" |
| 13383 | /* 30628 */ "VFMSH\0" |
| 13384 | /* 30634 */ "VFNMSH\0" |
| 13385 | /* 30641 */ "VCVTMSH\0" |
| 13386 | /* 30649 */ "VINSH\0" |
| 13387 | /* 30655 */ "VCVTNSH\0" |
| 13388 | /* 30663 */ "G_FCOSH\0" |
| 13389 | /* 30671 */ "VCVTPSH\0" |
| 13390 | /* 30679 */ "PICLDRSH\0" |
| 13391 | /* 30688 */ "tLDRSH\0" |
| 13392 | /* 30695 */ "VCVTTSH\0" |
| 13393 | /* 30703 */ "tPUSH\0" |
| 13394 | /* 30709 */ "t2REVSH\0" |
| 13395 | /* 30717 */ "tREVSH\0" |
| 13396 | /* 30724 */ "VSELVSH\0" |
| 13397 | /* 30732 */ "VSELGTH\0" |
| 13398 | /* 30740 */ "VSQRTH\0" |
| 13399 | /* 30747 */ "FCONSTH\0" |
| 13400 | /* 30755 */ "t2SXTH\0" |
| 13401 | /* 30762 */ "tSXTH\0" |
| 13402 | /* 30768 */ "t2UXTH\0" |
| 13403 | /* 30775 */ "tUXTH\0" |
| 13404 | /* 30781 */ "VCVTAUH\0" |
| 13405 | /* 30789 */ "VCVTMUH\0" |
| 13406 | /* 30797 */ "VCVTNUH\0" |
| 13407 | /* 30805 */ "VCVTPUH\0" |
| 13408 | /* 30813 */ "VDIVH\0" |
| 13409 | /* 30819 */ "VMOVH\0" |
| 13410 | /* 30825 */ "t2LDAEXH\0" |
| 13411 | /* 30834 */ "t2STLEXH\0" |
| 13412 | /* 30843 */ "t2LDREXH\0" |
| 13413 | /* 30852 */ "t2STREXH\0" |
| 13414 | /* 30861 */ "VRINTXH\0" |
| 13415 | /* 30869 */ "VCMPEZH\0" |
| 13416 | /* 30877 */ "VTOSIZH\0" |
| 13417 | /* 30885 */ "VTOUIZH\0" |
| 13418 | /* 30893 */ "VCMPZH\0" |
| 13419 | /* 30900 */ "VRINTZH\0" |
| 13420 | /* 30908 */ "MVE_VSBCI\0" |
| 13421 | /* 30918 */ "MVE_VADCI\0" |
| 13422 | /* 30928 */ "VFMALDI\0" |
| 13423 | /* 30936 */ "VFMSLDI\0" |
| 13424 | /* 30944 */ "VUSDOTDI\0" |
| 13425 | /* 30953 */ "VSDOTDI\0" |
| 13426 | /* 30961 */ "VSUDOTDI\0" |
| 13427 | /* 30970 */ "VUDOTDI\0" |
| 13428 | /* 30978 */ "t2BFI\0" |
| 13429 | /* 30984 */ "DBG_PHI\0" |
| 13430 | /* 30992 */ "VBF16MALBQI\0" |
| 13431 | /* 31004 */ "VFMALQI\0" |
| 13432 | /* 31012 */ "VFMSLQI\0" |
| 13433 | /* 31020 */ "VBF16MALTQI\0" |
| 13434 | /* 31032 */ "VUSDOTQI\0" |
| 13435 | /* 31041 */ "VSDOTQI\0" |
| 13436 | /* 31049 */ "VSUDOTQI\0" |
| 13437 | /* 31058 */ "VUDOTQI\0" |
| 13438 | /* 31066 */ "G_FPTOSI\0" |
| 13439 | /* 31075 */ "t2BTI\0" |
| 13440 | /* 31081 */ "t2PACBTI\0" |
| 13441 | /* 31090 */ "t2CALL_BTI\0" |
| 13442 | /* 31101 */ "G_FPTOUI\0" |
| 13443 | /* 31110 */ "G_FPOWI\0" |
| 13444 | /* 31118 */ "t2BXJ\0" |
| 13445 | /* 31124 */ "WIN__DBZCHK\0" |
| 13446 | /* 31136 */ "G_PTRMASK\0" |
| 13447 | /* 31146 */ "WIN__CHKSTK\0" |
| 13448 | /* 31158 */ "t2UMAAL\0" |
| 13449 | /* 31166 */ "t2SMLAL\0" |
| 13450 | /* 31174 */ "t2UMLAL\0" |
| 13451 | /* 31182 */ "LOADDUAL\0" |
| 13452 | /* 31191 */ "STOREDUAL\0" |
| 13453 | /* 31201 */ "tBL\0" |
| 13454 | /* 31205 */ "GC_LABEL\0" |
| 13455 | /* 31214 */ "DBG_LABEL\0" |
| 13456 | /* 31224 */ "EH_LABEL\0" |
| 13457 | /* 31233 */ "ANNOTATION_LABEL\0" |
| 13458 | /* 31250 */ "ICALL_BRANCH_FUNNEL\0" |
| 13459 | /* 31270 */ "t2SEL\0" |
| 13460 | /* 31276 */ "t2CSEL\0" |
| 13461 | /* 31283 */ "MVE_VPSEL\0" |
| 13462 | /* 31293 */ "G_FSHL\0" |
| 13463 | /* 31300 */ "MVE_SQSHL\0" |
| 13464 | /* 31310 */ "MVE_UQSHL\0" |
| 13465 | /* 31320 */ "MVE_UQRSHL\0" |
| 13466 | /* 31331 */ "G_SHL\0" |
| 13467 | /* 31337 */ "G_FCEIL\0" |
| 13468 | /* 31345 */ "BMOVPCB_CALL\0" |
| 13469 | /* 31358 */ "PATCHABLE_TAIL_CALL\0" |
| 13470 | /* 31378 */ "tBLXNS_CALL\0" |
| 13471 | /* 31390 */ "PATCHABLE_TYPED_EVENT_CALL\0" |
| 13472 | /* 31417 */ "PATCHABLE_EVENT_CALL\0" |
| 13473 | /* 31438 */ "tBX_CALL\0" |
| 13474 | /* 31447 */ "BMOVPCRX_CALL\0" |
| 13475 | /* 31461 */ "FENTRY_CALL\0" |
| 13476 | /* 31473 */ "MVE_SQSHLL\0" |
| 13477 | /* 31484 */ "MVE_UQSHLL\0" |
| 13478 | /* 31495 */ "MVE_UQRSHLL\0" |
| 13479 | /* 31507 */ "KILL\0" |
| 13480 | /* 31512 */ "t2SMULL\0" |
| 13481 | /* 31520 */ "t2UMULL\0" |
| 13482 | /* 31528 */ "G_CONSTANT_POOL\0" |
| 13483 | /* 31544 */ "MVE_SQRSHRL\0" |
| 13484 | /* 31556 */ "MVE_SRSHRL\0" |
| 13485 | /* 31567 */ "MVE_URSHRL\0" |
| 13486 | /* 31578 */ "MVE_LSRL\0" |
| 13487 | /* 31587 */ "G_ROTL\0" |
| 13488 | /* 31594 */ "t2STL\0" |
| 13489 | /* 31600 */ "t2MUL\0" |
| 13490 | /* 31606 */ "G_VECREDUCE_FMUL\0" |
| 13491 | /* 31623 */ "G_FMUL\0" |
| 13492 | /* 31630 */ "G_VECREDUCE_SEQ_FMUL\0" |
| 13493 | /* 31651 */ "G_STRICT_FMUL\0" |
| 13494 | /* 31665 */ "t2SMMUL\0" |
| 13495 | /* 31673 */ "G_VECREDUCE_MUL\0" |
| 13496 | /* 31689 */ "G_MUL\0" |
| 13497 | /* 31695 */ "tMUL\0" |
| 13498 | /* 31700 */ "SHA1M\0" |
| 13499 | /* 31706 */ "MVE_VRINTf32M\0" |
| 13500 | /* 31720 */ "MVE_VRINTf16M\0" |
| 13501 | /* 31734 */ "VLLDM\0" |
| 13502 | /* 31740 */ "G_FREM\0" |
| 13503 | /* 31747 */ "G_STRICT_FREM\0" |
| 13504 | /* 31761 */ "G_SREM\0" |
| 13505 | /* 31768 */ "G_UREM\0" |
| 13506 | /* 31775 */ "G_SDIVREM\0" |
| 13507 | /* 31785 */ "G_UDIVREM\0" |
| 13508 | /* 31795 */ "LDRB_PRE_IMM\0" |
| 13509 | /* 31808 */ "STRB_PRE_IMM\0" |
| 13510 | /* 31821 */ "LDR_PRE_IMM\0" |
| 13511 | /* 31833 */ "STR_PRE_IMM\0" |
| 13512 | /* 31845 */ "LDRB_POST_IMM\0" |
| 13513 | /* 31859 */ "STRB_POST_IMM\0" |
| 13514 | /* 31873 */ "LDR_POST_IMM\0" |
| 13515 | /* 31886 */ "STR_POST_IMM\0" |
| 13516 | /* 31899 */ "LDRBT_POST_IMM\0" |
| 13517 | /* 31914 */ "STRBT_POST_IMM\0" |
| 13518 | /* 31929 */ "LDRT_POST_IMM\0" |
| 13519 | /* 31943 */ "STRT_POST_IMM\0" |
| 13520 | /* 31957 */ "t2CLRM\0" |
| 13521 | /* 31964 */ "INLINEASM\0" |
| 13522 | /* 31974 */ "VLSTM\0" |
| 13523 | /* 31980 */ "G_VECREDUCE_FMINIMUM\0" |
| 13524 | /* 32001 */ "G_FMINIMUM\0" |
| 13525 | /* 32012 */ "G_VECREDUCE_FMAXIMUM\0" |
| 13526 | /* 32033 */ "G_FMAXIMUM\0" |
| 13527 | /* 32044 */ "G_FMINNUM\0" |
| 13528 | /* 32054 */ "G_FMAXNUM\0" |
| 13529 | /* 32064 */ "t2MSR_M\0" |
| 13530 | /* 32072 */ "t2MRS_M\0" |
| 13531 | /* 32080 */ "MVE_VRINTf32N\0" |
| 13532 | /* 32094 */ "MVE_VRINTf16N\0" |
| 13533 | /* 32108 */ "t2SETPAN\0" |
| 13534 | /* 32117 */ "G_FATAN\0" |
| 13535 | /* 32125 */ "G_FTAN\0" |
| 13536 | /* 32132 */ "G_INTRINSIC_ROUNDEVEN\0" |
| 13537 | /* 32154 */ "G_ASSERT_ALIGN\0" |
| 13538 | /* 32169 */ "G_FCOPYSIGN\0" |
| 13539 | /* 32181 */ "G_VECREDUCE_FMIN\0" |
| 13540 | /* 32198 */ "G_ATOMICRMW_FMIN\0" |
| 13541 | /* 32215 */ "G_VECREDUCE_SMIN\0" |
| 13542 | /* 32232 */ "G_SMIN\0" |
| 13543 | /* 32239 */ "G_VECREDUCE_UMIN\0" |
| 13544 | /* 32256 */ "G_UMIN\0" |
| 13545 | /* 32263 */ "G_ATOMICRMW_UMIN\0" |
| 13546 | /* 32280 */ "G_ATOMICRMW_MIN\0" |
| 13547 | /* 32296 */ "G_FASIN\0" |
| 13548 | /* 32304 */ "G_FSIN\0" |
| 13549 | /* 32311 */ "CFI_INSTRUCTION\0" |
| 13550 | /* 32327 */ "t2LDC2_OPTION\0" |
| 13551 | /* 32341 */ "t2STC2_OPTION\0" |
| 13552 | /* 32355 */ "t2LDC_OPTION\0" |
| 13553 | /* 32368 */ "t2STC_OPTION\0" |
| 13554 | /* 32381 */ "t2LDC2L_OPTION\0" |
| 13555 | /* 32396 */ "t2STC2L_OPTION\0" |
| 13556 | /* 32411 */ "t2LDCL_OPTION\0" |
| 13557 | /* 32425 */ "t2STCL_OPTION\0" |
| 13558 | /* 32439 */ "MVE_VORN\0" |
| 13559 | /* 32448 */ "MVE_VMVN\0" |
| 13560 | /* 32457 */ "tMVN\0" |
| 13561 | /* 32462 */ "tADJCALLSTACKDOWN\0" |
| 13562 | /* 32480 */ "G_SSUBO\0" |
| 13563 | /* 32488 */ "G_USUBO\0" |
| 13564 | /* 32496 */ "G_SADDO\0" |
| 13565 | /* 32504 */ "G_UADDO\0" |
| 13566 | /* 32512 */ "JUMP_TABLE_DEBUG_INFO\0" |
| 13567 | /* 32534 */ "G_SMULO\0" |
| 13568 | /* 32542 */ "G_UMULO\0" |
| 13569 | /* 32550 */ "G_BZERO\0" |
| 13570 | /* 32558 */ "SHA1P\0" |
| 13571 | /* 32564 */ "MVE_VRINTf32P\0" |
| 13572 | /* 32578 */ "MVE_VRINTf16P\0" |
| 13573 | /* 32592 */ "STACKMAP\0" |
| 13574 | /* 32601 */ "G_DEBUGTRAP\0" |
| 13575 | /* 32613 */ "G_UBSANTRAP\0" |
| 13576 | /* 32625 */ "G_TRAP\0" |
| 13577 | /* 32632 */ "tTRAP\0" |
| 13578 | /* 32638 */ "G_ATOMICRMW_UDEC_WRAP\0" |
| 13579 | /* 32660 */ "G_ATOMICRMW_UINC_WRAP\0" |
| 13580 | /* 32682 */ "G_BSWAP\0" |
| 13581 | /* 32690 */ "t2CDP\0" |
| 13582 | /* 32696 */ "G_SITOFP\0" |
| 13583 | /* 32705 */ "G_UITOFP\0" |
| 13584 | /* 32714 */ "G_FCMP\0" |
| 13585 | /* 32721 */ "G_ICMP\0" |
| 13586 | /* 32728 */ "G_SCMP\0" |
| 13587 | /* 32735 */ "G_UCMP\0" |
| 13588 | /* 32742 */ "CONVERGENCECTRL_LOOP\0" |
| 13589 | /* 32763 */ "G_CTPOP\0" |
| 13590 | /* 32771 */ "tPOP\0" |
| 13591 | /* 32776 */ "PATCHABLE_OP\0" |
| 13592 | /* 32789 */ "FAULTING_OP\0" |
| 13593 | /* 32801 */ "SEH_SaveSP\0" |
| 13594 | /* 32812 */ "tADDrSP\0" |
| 13595 | /* 32820 */ "MVE_LCTP\0" |
| 13596 | /* 32829 */ "MVE_LETP\0" |
| 13597 | /* 32838 */ "t2WhileLoopStartTP\0" |
| 13598 | /* 32857 */ "t2DoLoopStartTP\0" |
| 13599 | /* 32873 */ "tADJCALLSTACKUP\0" |
| 13600 | /* 32889 */ "PREALLOCATED_SETUP\0" |
| 13601 | /* 32908 */ "SWP\0" |
| 13602 | /* 32912 */ "G_FLDEXP\0" |
| 13603 | /* 32921 */ "G_STRICT_FLDEXP\0" |
| 13604 | /* 32937 */ "G_FEXP\0" |
| 13605 | /* 32944 */ "G_FFREXP\0" |
| 13606 | /* 32953 */ "VLD1d32Q\0" |
| 13607 | /* 32962 */ "VST1d32Q\0" |
| 13608 | /* 32971 */ "VLD1d64Q\0" |
| 13609 | /* 32980 */ "VST1d64Q\0" |
| 13610 | /* 32989 */ "VLD1d16Q\0" |
| 13611 | /* 32998 */ "VST1d16Q\0" |
| 13612 | /* 33007 */ "VLD1d8Q\0" |
| 13613 | /* 33015 */ "VST1d8Q\0" |
| 13614 | /* 33023 */ "VBF16MALBQ\0" |
| 13615 | /* 33034 */ "VFMALQ\0" |
| 13616 | /* 33041 */ "VFMSLQ\0" |
| 13617 | /* 33048 */ "VBF16MALTQ\0" |
| 13618 | /* 33059 */ "VUSDOTQ\0" |
| 13619 | /* 33067 */ "VSDOTQ\0" |
| 13620 | /* 33074 */ "VUDOTQ\0" |
| 13621 | /* 33081 */ "BF16VDOTI_VDOTQ\0" |
| 13622 | /* 33097 */ "BF16VDOTS_VDOTQ\0" |
| 13623 | /* 33113 */ "t2SMMLAR\0" |
| 13624 | /* 33122 */ "t2MSR_AR\0" |
| 13625 | /* 33131 */ "t2MRS_AR\0" |
| 13626 | /* 33140 */ "t2MRSsys_AR\0" |
| 13627 | /* 33152 */ "G_BR\0" |
| 13628 | /* 33157 */ "INLINEASM_BR\0" |
| 13629 | /* 33170 */ "t2MCR\0" |
| 13630 | /* 33176 */ "t2ADR\0" |
| 13631 | /* 33182 */ "tADR\0" |
| 13632 | /* 33187 */ "G_BLOCK_ADDR\0" |
| 13633 | /* 33200 */ "PICLDR\0" |
| 13634 | /* 33207 */ "MEMBARRIER\0" |
| 13635 | /* 33218 */ "G_CONSTANT_FOLD_BARRIER\0" |
| 13636 | /* 33242 */ "PATCHABLE_FUNCTION_ENTER\0" |
| 13637 | /* 33267 */ "G_READCYCLECOUNTER\0" |
| 13638 | /* 33286 */ "G_READSTEADYCOUNTER\0" |
| 13639 | /* 33306 */ "G_READ_REGISTER\0" |
| 13640 | /* 33322 */ "G_WRITE_REGISTER\0" |
| 13641 | /* 33339 */ "G_ASHR\0" |
| 13642 | /* 33346 */ "G_FSHR\0" |
| 13643 | /* 33353 */ "G_LSHR\0" |
| 13644 | /* 33360 */ "MVE_SQRSHR\0" |
| 13645 | /* 33371 */ "MVE_SRSHR\0" |
| 13646 | /* 33381 */ "MVE_URSHR\0" |
| 13647 | /* 33391 */ "VMOVHR\0" |
| 13648 | /* 33398 */ "MOVPCLR\0" |
| 13649 | /* 33406 */ "tBL_PUSHLR\0" |
| 13650 | /* 33417 */ "t2SMMULR\0" |
| 13651 | /* 33426 */ "t2SUBS_PC_LR\0" |
| 13652 | /* 33439 */ "SEH_SaveLR\0" |
| 13653 | /* 33450 */ "t2WhileLoopStartLR\0" |
| 13654 | /* 33469 */ "MVE_VEOR\0" |
| 13655 | /* 33478 */ "tEOR\0" |
| 13656 | /* 33483 */ "CONVERGENCECTRL_ANCHOR\0" |
| 13657 | /* 33506 */ "G_FFLOOR\0" |
| 13658 | /* 33515 */ "tROR\0" |
| 13659 | /* 33520 */ "G_EXTRACT_SUBVECTOR\0" |
| 13660 | /* 33540 */ "G_INSERT_SUBVECTOR\0" |
| 13661 | /* 33559 */ "G_BUILD_VECTOR\0" |
| 13662 | /* 33574 */ "G_SHUFFLE_VECTOR\0" |
| 13663 | /* 33591 */ "G_SPLAT_VECTOR\0" |
| 13664 | /* 33606 */ "G_VECREDUCE_XOR\0" |
| 13665 | /* 33622 */ "G_XOR\0" |
| 13666 | /* 33628 */ "G_ATOMICRMW_XOR\0" |
| 13667 | /* 33644 */ "G_VECREDUCE_OR\0" |
| 13668 | /* 33659 */ "G_OR\0" |
| 13669 | /* 33664 */ "G_ATOMICRMW_OR\0" |
| 13670 | /* 33679 */ "PseudoARMInitUndefGPR\0" |
| 13671 | /* 33701 */ "PseudoARMInitUndefMQPR\0" |
| 13672 | /* 33724 */ "PseudoARMInitUndefSPR\0" |
| 13673 | /* 33746 */ "VMSR_VPR\0" |
| 13674 | /* 33755 */ "VMRS_VPR\0" |
| 13675 | /* 33764 */ "t2MCRR\0" |
| 13676 | /* 33771 */ "VMOVDRR\0" |
| 13677 | /* 33779 */ "MVE_VORR\0" |
| 13678 | /* 33788 */ "tORR\0" |
| 13679 | /* 33793 */ "VMOVSRR\0" |
| 13680 | /* 33801 */ "t2SMMLSR\0" |
| 13681 | /* 33810 */ "VMSR\0" |
| 13682 | /* 33815 */ "VMOVSR\0" |
| 13683 | /* 33822 */ "G_ROTR\0" |
| 13684 | /* 33829 */ "G_INTTOPTR\0" |
| 13685 | /* 33840 */ "PICSTR\0" |
| 13686 | /* 33847 */ "VNMLAS\0" |
| 13687 | /* 33854 */ "VMLAS\0" |
| 13688 | /* 33860 */ "VFMAS\0" |
| 13689 | /* 33866 */ "VFNMAS\0" |
| 13690 | /* 33873 */ "VRINTAS\0" |
| 13691 | /* 33881 */ "t2ABS\0" |
| 13692 | /* 33887 */ "G_FABS\0" |
| 13693 | /* 33894 */ "G_ABS\0" |
| 13694 | /* 33900 */ "tRSBS\0" |
| 13695 | /* 33906 */ "VSUBS\0" |
| 13696 | /* 33912 */ "tSBCS\0" |
| 13697 | /* 33918 */ "tADCS\0" |
| 13698 | /* 33924 */ "VADDS\0" |
| 13699 | /* 33930 */ "VCVTDS\0" |
| 13700 | /* 33937 */ "VSELGES\0" |
| 13701 | /* 33945 */ "VCMPES\0" |
| 13702 | /* 33952 */ "G_UNMERGE_VALUES\0" |
| 13703 | /* 33969 */ "G_MERGE_VALUES\0" |
| 13704 | /* 33984 */ "VNEGS\0" |
| 13705 | /* 33990 */ "VCVTBHS\0" |
| 13706 | /* 33998 */ "VTOSHS\0" |
| 13707 | /* 34005 */ "VCVTTHS\0" |
| 13708 | /* 34013 */ "VTOUHS\0" |
| 13709 | /* 34020 */ "t2DLS\0" |
| 13710 | /* 34026 */ "t2MLS\0" |
| 13711 | /* 34032 */ "t2SMMLS\0" |
| 13712 | /* 34040 */ "VTOSLS\0" |
| 13713 | /* 34047 */ "VNMULS\0" |
| 13714 | /* 34054 */ "VMULS\0" |
| 13715 | /* 34060 */ "VTOULS\0" |
| 13716 | /* 34067 */ "t2WLS\0" |
| 13717 | /* 34073 */ "VFP_VMINNMS\0" |
| 13718 | /* 34085 */ "VFP_VMAXNMS\0" |
| 13719 | /* 34097 */ "VSCCLRMS\0" |
| 13720 | /* 34106 */ "VRINTMS\0" |
| 13721 | /* 34114 */ "VRINTNS\0" |
| 13722 | /* 34122 */ "VMSR_FPCXTNS\0" |
| 13723 | /* 34135 */ "VMRS_FPCXTNS\0" |
| 13724 | /* 34148 */ "tBXNS\0" |
| 13725 | /* 34154 */ "G_FACOS\0" |
| 13726 | /* 34162 */ "G_FCOS\0" |
| 13727 | /* 34169 */ "VSHTOS\0" |
| 13728 | /* 34176 */ "VUHTOS\0" |
| 13729 | /* 34183 */ "VSITOS\0" |
| 13730 | /* 34190 */ "VUITOS\0" |
| 13731 | /* 34197 */ "VSLTOS\0" |
| 13732 | /* 34204 */ "VULTOS\0" |
| 13733 | /* 34211 */ "tCPS\0" |
| 13734 | /* 34216 */ "VCMPS\0" |
| 13735 | /* 34222 */ "VRINTPS\0" |
| 13736 | /* 34230 */ "VSELEQS\0" |
| 13737 | /* 34238 */ "JUMPTABLE_ADDRS\0" |
| 13738 | /* 34254 */ "VLDRS\0" |
| 13739 | /* 34260 */ "VTOSIRS\0" |
| 13740 | /* 34268 */ "VTOUIRS\0" |
| 13741 | /* 34276 */ "VMRS\0" |
| 13742 | /* 34281 */ "G_CONCAT_VECTORS\0" |
| 13743 | /* 34298 */ "VMOVRRS\0" |
| 13744 | /* 34306 */ "VRINTRS\0" |
| 13745 | /* 34314 */ "VSTRS\0" |
| 13746 | /* 34320 */ "VMOVRS\0" |
| 13747 | /* 34327 */ "COPY_TO_REGCLASS\0" |
| 13748 | /* 34344 */ "G_IS_FPCLASS\0" |
| 13749 | /* 34357 */ "VCVTASS\0" |
| 13750 | /* 34365 */ "VABSS\0" |
| 13751 | /* 34371 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" |
| 13752 | /* 34401 */ "G_VECTOR_COMPRESS\0" |
| 13753 | /* 34419 */ "VNMLSS\0" |
| 13754 | /* 34426 */ "VMLSS\0" |
| 13755 | /* 34432 */ "VFMSS\0" |
| 13756 | /* 34438 */ "VFNMSS\0" |
| 13757 | /* 34445 */ "VCVTMSS\0" |
| 13758 | /* 34453 */ "VCVTNSS\0" |
| 13759 | /* 34461 */ "VCVTPSS\0" |
| 13760 | /* 34469 */ "VSELVSS\0" |
| 13761 | /* 34477 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" |
| 13762 | /* 34504 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0" |
| 13763 | /* 34542 */ "VSELGTS\0" |
| 13764 | /* 34550 */ "VSQRTS\0" |
| 13765 | /* 34557 */ "JUMPTABLE_INSTS\0" |
| 13766 | /* 34573 */ "FCONSTS\0" |
| 13767 | /* 34581 */ "VMSR_FPCXTS\0" |
| 13768 | /* 34593 */ "VMRS_FPCXTS\0" |
| 13769 | /* 34605 */ "VCVTAUS\0" |
| 13770 | /* 34613 */ "VCVTMUS\0" |
| 13771 | /* 34621 */ "VCVTNUS\0" |
| 13772 | /* 34629 */ "VCVTPUS\0" |
| 13773 | /* 34637 */ "VDIVS\0" |
| 13774 | /* 34643 */ "VMOVS\0" |
| 13775 | /* 34649 */ "VRINTXS\0" |
| 13776 | /* 34657 */ "VCMPEZS\0" |
| 13777 | /* 34665 */ "VTOSIZS\0" |
| 13778 | /* 34673 */ "VTOUIZS\0" |
| 13779 | /* 34681 */ "VCMPZS\0" |
| 13780 | /* 34688 */ "VRINTZS\0" |
| 13781 | /* 34696 */ "VLD1d32T\0" |
| 13782 | /* 34705 */ "VST1d32T\0" |
| 13783 | /* 34714 */ "VLD1d64T\0" |
| 13784 | /* 34723 */ "VST1d64T\0" |
| 13785 | /* 34732 */ "VLD1d16T\0" |
| 13786 | /* 34741 */ "VST1d16T\0" |
| 13787 | /* 34750 */ "VLD1d8T\0" |
| 13788 | /* 34758 */ "VST1d8T\0" |
| 13789 | /* 34766 */ "G_SSUBSAT\0" |
| 13790 | /* 34776 */ "G_USUBSAT\0" |
| 13791 | /* 34786 */ "G_SADDSAT\0" |
| 13792 | /* 34796 */ "G_UADDSAT\0" |
| 13793 | /* 34806 */ "G_SSHLSAT\0" |
| 13794 | /* 34816 */ "G_USHLSAT\0" |
| 13795 | /* 34826 */ "t2SSAT\0" |
| 13796 | /* 34833 */ "t2USAT\0" |
| 13797 | /* 34840 */ "G_SMULFIXSAT\0" |
| 13798 | /* 34853 */ "G_UMULFIXSAT\0" |
| 13799 | /* 34866 */ "G_SDIVFIXSAT\0" |
| 13800 | /* 34879 */ "G_UDIVFIXSAT\0" |
| 13801 | /* 34892 */ "FMSTAT\0" |
| 13802 | /* 34899 */ "t2TTAT\0" |
| 13803 | /* 34906 */ "t2SMLABT\0" |
| 13804 | /* 34915 */ "t2PKHBT\0" |
| 13805 | /* 34923 */ "t2SMLALBT\0" |
| 13806 | /* 34933 */ "t2SMULBT\0" |
| 13807 | /* 34942 */ "t2LDRBT\0" |
| 13808 | /* 34950 */ "t2STRBT\0" |
| 13809 | /* 34958 */ "t2LDRSBT\0" |
| 13810 | /* 34967 */ "G_EXTRACT\0" |
| 13811 | /* 34977 */ "G_SELECT\0" |
| 13812 | /* 34986 */ "G_BRINDIRECT\0" |
| 13813 | /* 34999 */ "ERET\0" |
| 13814 | /* 35004 */ "t2LDMIA_RET\0" |
| 13815 | /* 35016 */ "PATCHABLE_RET\0" |
| 13816 | /* 35030 */ "tPOP_RET\0" |
| 13817 | /* 35039 */ "tBXNS_RET\0" |
| 13818 | /* 35049 */ "tBX_RET\0" |
| 13819 | /* 35057 */ "t2LDC2_OFFSET\0" |
| 13820 | /* 35071 */ "t2STC2_OFFSET\0" |
| 13821 | /* 35085 */ "t2LDC_OFFSET\0" |
| 13822 | /* 35098 */ "t2STC_OFFSET\0" |
| 13823 | /* 35111 */ "t2LDC2L_OFFSET\0" |
| 13824 | /* 35126 */ "t2STC2L_OFFSET\0" |
| 13825 | /* 35141 */ "t2LDCL_OFFSET\0" |
| 13826 | /* 35155 */ "t2STCL_OFFSET\0" |
| 13827 | /* 35169 */ "G_MEMSET\0" |
| 13828 | /* 35178 */ "t2LDRHT\0" |
| 13829 | /* 35186 */ "t2STRHT\0" |
| 13830 | /* 35194 */ "t2LDRSHT\0" |
| 13831 | /* 35203 */ "t2IT\0" |
| 13832 | /* 35208 */ "t2RBIT\0" |
| 13833 | /* 35215 */ "PATCHABLE_FUNCTION_EXIT\0" |
| 13834 | /* 35239 */ "G_BRJT\0" |
| 13835 | /* 35246 */ "t2TBB_JT\0" |
| 13836 | /* 35255 */ "tTBB_JT\0" |
| 13837 | /* 35263 */ "t2TBH_JT\0" |
| 13838 | /* 35272 */ "tTBH_JT\0" |
| 13839 | /* 35280 */ "t2BR_JT\0" |
| 13840 | /* 35288 */ "t2LEApcrelJT\0" |
| 13841 | /* 35301 */ "tLEApcrelJT\0" |
| 13842 | /* 35313 */ "G_EXTRACT_VECTOR_ELT\0" |
| 13843 | /* 35334 */ "G_INSERT_VECTOR_ELT\0" |
| 13844 | /* 35354 */ "tHLT\0" |
| 13845 | /* 35359 */ "G_FCONSTANT\0" |
| 13846 | /* 35371 */ "G_CONSTANT\0" |
| 13847 | /* 35382 */ "G_INTRINSIC_CONVERGENT\0" |
| 13848 | /* 35405 */ "t2HINT\0" |
| 13849 | /* 35412 */ "tHINT\0" |
| 13850 | /* 35418 */ "STATEPOINT\0" |
| 13851 | /* 35429 */ "PATCHPOINT\0" |
| 13852 | /* 35440 */ "G_PTRTOINT\0" |
| 13853 | /* 35451 */ "G_FRINT\0" |
| 13854 | /* 35459 */ "G_INTRINSIC_LLRINT\0" |
| 13855 | /* 35478 */ "G_INTRINSIC_LRINT\0" |
| 13856 | /* 35496 */ "G_FNEARBYINT\0" |
| 13857 | /* 35509 */ "MVE_VPNOT\0" |
| 13858 | /* 35519 */ "tBKPT\0" |
| 13859 | /* 35525 */ "G_VASTART\0" |
| 13860 | /* 35535 */ "LIFETIME_START\0" |
| 13861 | /* 35550 */ "G_INVOKE_REGION_START\0" |
| 13862 | /* 35572 */ "t2LDRT\0" |
| 13863 | /* 35579 */ "G_INSERT\0" |
| 13864 | /* 35588 */ "G_FSQRT\0" |
| 13865 | /* 35596 */ "G_STRICT_FSQRT\0" |
| 13866 | /* 35611 */ "t2STRT\0" |
| 13867 | /* 35618 */ "G_BITCAST\0" |
| 13868 | /* 35628 */ "G_ADDRSPACE_CAST\0" |
| 13869 | /* 35645 */ "DBG_VALUE_LIST\0" |
| 13870 | /* 35660 */ "VMSR_FPINST\0" |
| 13871 | /* 35672 */ "VMRS_FPINST\0" |
| 13872 | /* 35684 */ "MVE_MEMSETLOOPINST\0" |
| 13873 | /* 35703 */ "MVE_MEMCPYLOOPINST\0" |
| 13874 | /* 35722 */ "t2LDC2_POST\0" |
| 13875 | /* 35734 */ "t2STC2_POST\0" |
| 13876 | /* 35746 */ "t2LDRB_POST\0" |
| 13877 | /* 35758 */ "t2STRB_POST\0" |
| 13878 | /* 35770 */ "t2LDRSB_POST\0" |
| 13879 | /* 35783 */ "t2LDC_POST\0" |
| 13880 | /* 35794 */ "t2STC_POST\0" |
| 13881 | /* 35805 */ "t2LDRD_POST\0" |
| 13882 | /* 35817 */ "t2STRD_POST\0" |
| 13883 | /* 35829 */ "t2LDRH_POST\0" |
| 13884 | /* 35841 */ "t2STRH_POST\0" |
| 13885 | /* 35853 */ "t2LDRSH_POST\0" |
| 13886 | /* 35866 */ "t2LDC2L_POST\0" |
| 13887 | /* 35879 */ "t2STC2L_POST\0" |
| 13888 | /* 35892 */ "t2LDCL_POST\0" |
| 13889 | /* 35904 */ "t2STCL_POST\0" |
| 13890 | /* 35916 */ "t2LDR_POST\0" |
| 13891 | /* 35927 */ "t2STR_POST\0" |
| 13892 | /* 35938 */ "LDRBT_POST\0" |
| 13893 | /* 35949 */ "STRBT_POST\0" |
| 13894 | /* 35960 */ "LDRT_POST\0" |
| 13895 | /* 35970 */ "STRT_POST\0" |
| 13896 | /* 35980 */ "MVE_VPST\0" |
| 13897 | /* 35989 */ "tTST\0" |
| 13898 | /* 35994 */ "t2TT\0" |
| 13899 | /* 35999 */ "t2SMLATT\0" |
| 13900 | /* 36008 */ "t2SMLALTT\0" |
| 13901 | /* 36018 */ "t2SMULTT\0" |
| 13902 | /* 36027 */ "t2TTT\0" |
| 13903 | /* 36033 */ "BF16_VCVTT\0" |
| 13904 | /* 36044 */ "t2AUT\0" |
| 13905 | /* 36050 */ "t2BXAUT\0" |
| 13906 | /* 36058 */ "VJCVT\0" |
| 13907 | /* 36064 */ "BF16_VCVT\0" |
| 13908 | /* 36074 */ "t2SMLAWT\0" |
| 13909 | /* 36083 */ "t2SMULWT\0" |
| 13910 | /* 36092 */ "G_FPEXT\0" |
| 13911 | /* 36100 */ "G_SEXT\0" |
| 13912 | /* 36107 */ "G_ASSERT_SEXT\0" |
| 13913 | /* 36121 */ "G_ANYEXT\0" |
| 13914 | /* 36130 */ "G_ZEXT\0" |
| 13915 | /* 36137 */ "G_ASSERT_ZEXT\0" |
| 13916 | /* 36151 */ "t2REV\0" |
| 13917 | /* 36157 */ "tREV\0" |
| 13918 | /* 36162 */ "G_FDIV\0" |
| 13919 | /* 36169 */ "G_STRICT_FDIV\0" |
| 13920 | /* 36183 */ "t2SDIV\0" |
| 13921 | /* 36190 */ "G_SDIV\0" |
| 13922 | /* 36197 */ "t2UDIV\0" |
| 13923 | /* 36204 */ "G_UDIV\0" |
| 13924 | /* 36211 */ "G_GET_FPENV\0" |
| 13925 | /* 36223 */ "G_RESET_FPENV\0" |
| 13926 | /* 36237 */ "G_SET_FPENV\0" |
| 13927 | /* 36249 */ "t2CSINV\0" |
| 13928 | /* 36257 */ "t2CRC32W\0" |
| 13929 | /* 36266 */ "t2RFEIAW\0" |
| 13930 | /* 36275 */ "t2RFEDBW\0" |
| 13931 | /* 36284 */ "t2CRC32CW\0" |
| 13932 | /* 36294 */ "G_FPOW\0" |
| 13933 | /* 36301 */ "MVE_VRINTf32X\0" |
| 13934 | /* 36315 */ "MVE_VRINTf16X\0" |
| 13935 | /* 36329 */ "G_VECREDUCE_FMAX\0" |
| 13936 | /* 36346 */ "G_ATOMICRMW_FMAX\0" |
| 13937 | /* 36363 */ "G_VECREDUCE_SMAX\0" |
| 13938 | /* 36380 */ "G_SMAX\0" |
| 13939 | /* 36387 */ "G_VECREDUCE_UMAX\0" |
| 13940 | /* 36404 */ "G_UMAX\0" |
| 13941 | /* 36411 */ "G_ATOMICRMW_UMAX\0" |
| 13942 | /* 36428 */ "G_ATOMICRMW_MAX\0" |
| 13943 | /* 36444 */ "t2SHSAX\0" |
| 13944 | /* 36452 */ "t2UHSAX\0" |
| 13945 | /* 36460 */ "t2QSAX\0" |
| 13946 | /* 36467 */ "t2UQSAX\0" |
| 13947 | /* 36475 */ "t2SSAX\0" |
| 13948 | /* 36482 */ "t2USAX\0" |
| 13949 | /* 36489 */ "tBX\0" |
| 13950 | /* 36493 */ "t2SMLADX\0" |
| 13951 | /* 36502 */ "t2SMUADX\0" |
| 13952 | /* 36511 */ "t2SMLALDX\0" |
| 13953 | /* 36521 */ "t2SMLSLDX\0" |
| 13954 | /* 36531 */ "t2SMLSDX\0" |
| 13955 | /* 36540 */ "t2SMUSDX\0" |
| 13956 | /* 36549 */ "t2LDAEX\0" |
| 13957 | /* 36557 */ "G_FRAME_INDEX\0" |
| 13958 | /* 36571 */ "t2STLEX\0" |
| 13959 | /* 36579 */ "t2LDREX\0" |
| 13960 | /* 36587 */ "t2CLREX\0" |
| 13961 | /* 36595 */ "t2STREX\0" |
| 13962 | /* 36603 */ "t2SBFX\0" |
| 13963 | /* 36610 */ "G_SBFX\0" |
| 13964 | /* 36617 */ "t2UBFX\0" |
| 13965 | /* 36624 */ "G_UBFX\0" |
| 13966 | /* 36631 */ "G_SMULFIX\0" |
| 13967 | /* 36641 */ "G_UMULFIX\0" |
| 13968 | /* 36651 */ "G_SDIVFIX\0" |
| 13969 | /* 36661 */ "G_UDIVFIX\0" |
| 13970 | /* 36671 */ "BLX\0" |
| 13971 | /* 36675 */ "MOVPCRX\0" |
| 13972 | /* 36683 */ "t2RRX\0" |
| 13973 | /* 36689 */ "t2SHASX\0" |
| 13974 | /* 36697 */ "t2UHASX\0" |
| 13975 | /* 36705 */ "t2QASX\0" |
| 13976 | /* 36712 */ "t2UQASX\0" |
| 13977 | /* 36720 */ "t2SASX\0" |
| 13978 | /* 36727 */ "t2UASX\0" |
| 13979 | /* 36734 */ "G_MEMCPY\0" |
| 13980 | /* 36743 */ "COPY\0" |
| 13981 | /* 36748 */ "CONSTPOOL_ENTRY\0" |
| 13982 | /* 36764 */ "CONVERGENCECTRL_ENTRY\0" |
| 13983 | /* 36786 */ "MVE_VRINTf32Z\0" |
| 13984 | /* 36800 */ "MVE_VRINTf16Z\0" |
| 13985 | /* 36814 */ "tCBZ\0" |
| 13986 | /* 36819 */ "t2CLZ\0" |
| 13987 | /* 36825 */ "G_CTLZ\0" |
| 13988 | /* 36832 */ "tCBNZ\0" |
| 13989 | /* 36838 */ "G_CTTZ\0" |
| 13990 | /* 36845 */ "MVE_VCVTs32f32a\0" |
| 13991 | /* 36861 */ "MVE_VCVTu32f32a\0" |
| 13992 | /* 36877 */ "MVE_VCVTs16f16a\0" |
| 13993 | /* 36893 */ "MVE_VCVTu16f16a\0" |
| 13994 | /* 36909 */ "MVE_VLD20_32_wb\0" |
| 13995 | /* 36925 */ "MVE_VST20_32_wb\0" |
| 13996 | /* 36941 */ "MVE_VLD40_32_wb\0" |
| 13997 | /* 36957 */ "MVE_VST40_32_wb\0" |
| 13998 | /* 36973 */ "MVE_VLD21_32_wb\0" |
| 13999 | /* 36989 */ "MVE_VST21_32_wb\0" |
| 14000 | /* 37005 */ "MVE_VLD41_32_wb\0" |
| 14001 | /* 37021 */ "MVE_VST41_32_wb\0" |
| 14002 | /* 37037 */ "MVE_VLD42_32_wb\0" |
| 14003 | /* 37053 */ "MVE_VST42_32_wb\0" |
| 14004 | /* 37069 */ "MVE_VLD43_32_wb\0" |
| 14005 | /* 37085 */ "MVE_VST43_32_wb\0" |
| 14006 | /* 37101 */ "MVE_VLD20_16_wb\0" |
| 14007 | /* 37117 */ "MVE_VST20_16_wb\0" |
| 14008 | /* 37133 */ "MVE_VLD40_16_wb\0" |
| 14009 | /* 37149 */ "MVE_VST40_16_wb\0" |
| 14010 | /* 37165 */ "MVE_VLD21_16_wb\0" |
| 14011 | /* 37181 */ "MVE_VST21_16_wb\0" |
| 14012 | /* 37197 */ "MVE_VLD41_16_wb\0" |
| 14013 | /* 37213 */ "MVE_VST41_16_wb\0" |
| 14014 | /* 37229 */ "MVE_VLD42_16_wb\0" |
| 14015 | /* 37245 */ "MVE_VST42_16_wb\0" |
| 14016 | /* 37261 */ "MVE_VLD43_16_wb\0" |
| 14017 | /* 37277 */ "MVE_VST43_16_wb\0" |
| 14018 | /* 37293 */ "MVE_VLD20_8_wb\0" |
| 14019 | /* 37308 */ "MVE_VST20_8_wb\0" |
| 14020 | /* 37323 */ "MVE_VLD40_8_wb\0" |
| 14021 | /* 37338 */ "MVE_VST40_8_wb\0" |
| 14022 | /* 37353 */ "MVE_VLD21_8_wb\0" |
| 14023 | /* 37368 */ "MVE_VST21_8_wb\0" |
| 14024 | /* 37383 */ "MVE_VLD41_8_wb\0" |
| 14025 | /* 37398 */ "MVE_VST41_8_wb\0" |
| 14026 | /* 37413 */ "MVE_VLD42_8_wb\0" |
| 14027 | /* 37428 */ "MVE_VST42_8_wb\0" |
| 14028 | /* 37443 */ "MVE_VLD43_8_wb\0" |
| 14029 | /* 37458 */ "MVE_VST43_8_wb\0" |
| 14030 | /* 37473 */ "t2Bcc\0" |
| 14031 | /* 37479 */ "tBcc\0" |
| 14032 | /* 37484 */ "VMOVDcc\0" |
| 14033 | /* 37492 */ "VMOVHcc\0" |
| 14034 | /* 37500 */ "VMOVScc\0" |
| 14035 | /* 37508 */ "MVE_VADDVs32acc\0" |
| 14036 | /* 37524 */ "MVE_VADDLVs32acc\0" |
| 14037 | /* 37541 */ "MVE_VADDVu32acc\0" |
| 14038 | /* 37557 */ "MVE_VADDLVu32acc\0" |
| 14039 | /* 37574 */ "MVE_VADDVs16acc\0" |
| 14040 | /* 37590 */ "MVE_VADDVu16acc\0" |
| 14041 | /* 37606 */ "MVE_VADDVs8acc\0" |
| 14042 | /* 37621 */ "MVE_VADDVu8acc\0" |
| 14043 | /* 37636 */ "MVE_VADDVs32no_acc\0" |
| 14044 | /* 37655 */ "MVE_VADDLVs32no_acc\0" |
| 14045 | /* 37675 */ "MVE_VADDVu32no_acc\0" |
| 14046 | /* 37694 */ "MVE_VADDLVu32no_acc\0" |
| 14047 | /* 37714 */ "MVE_VADDVs16no_acc\0" |
| 14048 | /* 37733 */ "MVE_VADDVu16no_acc\0" |
| 14049 | /* 37752 */ "MVE_VADDVs8no_acc\0" |
| 14050 | /* 37770 */ "MVE_VADDVu8no_acc\0" |
| 14051 | /* 37788 */ "t2LoopEndDec\0" |
| 14052 | /* 37801 */ "t2LoopDec\0" |
| 14053 | /* 37811 */ "CDE_VCX1_vec\0" |
| 14054 | /* 37824 */ "CDE_VCX2_vec\0" |
| 14055 | /* 37837 */ "CDE_VCX3_vec\0" |
| 14056 | /* 37850 */ "CDE_VCX1A_vec\0" |
| 14057 | /* 37864 */ "CDE_VCX2A_vec\0" |
| 14058 | /* 37878 */ "CDE_VCX3A_vec\0" |
| 14059 | /* 37892 */ "t2BFic\0" |
| 14060 | /* 37899 */ "t2LDRpci_pic\0" |
| 14061 | /* 37912 */ "tLDRpci_pic\0" |
| 14062 | /* 37924 */ "SEH_StackAlloc\0" |
| 14063 | /* 37939 */ "VDUPLN32d\0" |
| 14064 | /* 37949 */ "VDUP32d\0" |
| 14065 | /* 37957 */ "VNEGs32d\0" |
| 14066 | /* 37966 */ "VDUPLN16d\0" |
| 14067 | /* 37976 */ "VDUP16d\0" |
| 14068 | /* 37984 */ "VNEGs16d\0" |
| 14069 | /* 37993 */ "VDUPLN8d\0" |
| 14070 | /* 38002 */ "VDUP8d\0" |
| 14071 | /* 38009 */ "VNEGs8d\0" |
| 14072 | /* 38017 */ "VBICd\0" |
| 14073 | /* 38023 */ "VANDd\0" |
| 14074 | /* 38029 */ "VRECPEd\0" |
| 14075 | /* 38037 */ "VRSQRTEd\0" |
| 14076 | /* 38046 */ "VBIFd\0" |
| 14077 | /* 38052 */ "VBSLd\0" |
| 14078 | /* 38058 */ "VORNd\0" |
| 14079 | /* 38064 */ "VMVNd\0" |
| 14080 | /* 38070 */ "tTAILJMPd\0" |
| 14081 | /* 38080 */ "VBSPd\0" |
| 14082 | /* 38086 */ "VSWPd\0" |
| 14083 | /* 38092 */ "VEORd\0" |
| 14084 | /* 38098 */ "VORRd\0" |
| 14085 | /* 38104 */ "VBITd\0" |
| 14086 | /* 38110 */ "VCNTd\0" |
| 14087 | /* 38116 */ "MQQPRLoad\0" |
| 14088 | /* 38126 */ "MQQQQPRLoad\0" |
| 14089 | /* 38138 */ "BR_JTadd\0" |
| 14090 | /* 38147 */ "t2MSRbanked\0" |
| 14091 | /* 38159 */ "t2MRSbanked\0" |
| 14092 | /* 38171 */ "BL_pred\0" |
| 14093 | /* 38179 */ "BX_pred\0" |
| 14094 | /* 38187 */ "BLX_pred\0" |
| 14095 | /* 38196 */ "VCMLAv2f32_indexed\0" |
| 14096 | /* 38215 */ "VCMLAv4f32_indexed\0" |
| 14097 | /* 38234 */ "VCMLAv4f16_indexed\0" |
| 14098 | /* 38253 */ "VCMLAv8f16_indexed\0" |
| 14099 | /* 38272 */ "VLD2q32PseudoWB_fixed\0" |
| 14100 | /* 38294 */ "VST2q32PseudoWB_fixed\0" |
| 14101 | /* 38316 */ "VLD2q16PseudoWB_fixed\0" |
| 14102 | /* 38338 */ "VST2q16PseudoWB_fixed\0" |
| 14103 | /* 38360 */ "VLD2q8PseudoWB_fixed\0" |
| 14104 | /* 38381 */ "VST2q8PseudoWB_fixed\0" |
| 14105 | /* 38402 */ "VLD1d32QPseudoWB_fixed\0" |
| 14106 | /* 38425 */ "VST1d32QPseudoWB_fixed\0" |
| 14107 | /* 38448 */ "VLD1d64QPseudoWB_fixed\0" |
| 14108 | /* 38471 */ "VST1d64QPseudoWB_fixed\0" |
| 14109 | /* 38494 */ "VLD1d16QPseudoWB_fixed\0" |
| 14110 | /* 38517 */ "VST1d16QPseudoWB_fixed\0" |
| 14111 | /* 38540 */ "VLD1d8QPseudoWB_fixed\0" |
| 14112 | /* 38562 */ "VST1d8QPseudoWB_fixed\0" |
| 14113 | /* 38584 */ "VLD1d32TPseudoWB_fixed\0" |
| 14114 | /* 38607 */ "VST1d32TPseudoWB_fixed\0" |
| 14115 | /* 38630 */ "VLD1d64TPseudoWB_fixed\0" |
| 14116 | /* 38653 */ "VST1d64TPseudoWB_fixed\0" |
| 14117 | /* 38676 */ "VLD1d16TPseudoWB_fixed\0" |
| 14118 | /* 38699 */ "VST1d16TPseudoWB_fixed\0" |
| 14119 | /* 38722 */ "VLD1d8TPseudoWB_fixed\0" |
| 14120 | /* 38744 */ "VST1d8TPseudoWB_fixed\0" |
| 14121 | /* 38766 */ "VLD2DUPq32OddPseudoWB_fixed\0" |
| 14122 | /* 38794 */ "VLD2DUPq16OddPseudoWB_fixed\0" |
| 14123 | /* 38822 */ "VLD2DUPq8OddPseudoWB_fixed\0" |
| 14124 | /* 38849 */ "VLD2b32wb_fixed\0" |
| 14125 | /* 38865 */ "VST2b32wb_fixed\0" |
| 14126 | /* 38881 */ "VLD1d32wb_fixed\0" |
| 14127 | /* 38897 */ "VST1d32wb_fixed\0" |
| 14128 | /* 38913 */ "VLD2d32wb_fixed\0" |
| 14129 | /* 38929 */ "VST2d32wb_fixed\0" |
| 14130 | /* 38945 */ "VLD1DUPd32wb_fixed\0" |
| 14131 | /* 38964 */ "VLD2DUPd32wb_fixed\0" |
| 14132 | /* 38983 */ "VLD1q32wb_fixed\0" |
| 14133 | /* 38999 */ "VST1q32wb_fixed\0" |
| 14134 | /* 39015 */ "VLD2q32wb_fixed\0" |
| 14135 | /* 39031 */ "VST2q32wb_fixed\0" |
| 14136 | /* 39047 */ "VLD1DUPq32wb_fixed\0" |
| 14137 | /* 39066 */ "VLD2DUPd32x2wb_fixed\0" |
| 14138 | /* 39087 */ "VLD2DUPd16x2wb_fixed\0" |
| 14139 | /* 39108 */ "VLD2DUPd8x2wb_fixed\0" |
| 14140 | /* 39128 */ "VLD1d64wb_fixed\0" |
| 14141 | /* 39144 */ "VST1d64wb_fixed\0" |
| 14142 | /* 39160 */ "VLD1q64wb_fixed\0" |
| 14143 | /* 39176 */ "VST1q64wb_fixed\0" |
| 14144 | /* 39192 */ "VLD2b16wb_fixed\0" |
| 14145 | /* 39208 */ "VST2b16wb_fixed\0" |
| 14146 | /* 39224 */ "VLD1d16wb_fixed\0" |
| 14147 | /* 39240 */ "VST1d16wb_fixed\0" |
| 14148 | /* 39256 */ "VLD2d16wb_fixed\0" |
| 14149 | /* 39272 */ "VST2d16wb_fixed\0" |
| 14150 | /* 39288 */ "VLD1DUPd16wb_fixed\0" |
| 14151 | /* 39307 */ "VLD2DUPd16wb_fixed\0" |
| 14152 | /* 39326 */ "VLD1q16wb_fixed\0" |
| 14153 | /* 39342 */ "VST1q16wb_fixed\0" |
| 14154 | /* 39358 */ "VLD2q16wb_fixed\0" |
| 14155 | /* 39374 */ "VST2q16wb_fixed\0" |
| 14156 | /* 39390 */ "VLD1DUPq16wb_fixed\0" |
| 14157 | /* 39409 */ "VLD2b8wb_fixed\0" |
| 14158 | /* 39424 */ "VST2b8wb_fixed\0" |
| 14159 | /* 39439 */ "VLD1d8wb_fixed\0" |
| 14160 | /* 39454 */ "VST1d8wb_fixed\0" |
| 14161 | /* 39469 */ "VLD2d8wb_fixed\0" |
| 14162 | /* 39484 */ "VST2d8wb_fixed\0" |
| 14163 | /* 39499 */ "VLD1DUPd8wb_fixed\0" |
| 14164 | /* 39517 */ "VLD2DUPd8wb_fixed\0" |
| 14165 | /* 39535 */ "VLD1q8wb_fixed\0" |
| 14166 | /* 39550 */ "VST1q8wb_fixed\0" |
| 14167 | /* 39565 */ "VLD2q8wb_fixed\0" |
| 14168 | /* 39580 */ "VST2q8wb_fixed\0" |
| 14169 | /* 39595 */ "VLD1DUPq8wb_fixed\0" |
| 14170 | /* 39613 */ "VLD1d32Qwb_fixed\0" |
| 14171 | /* 39630 */ "VST1d32Qwb_fixed\0" |
| 14172 | /* 39647 */ "VLD1d64Qwb_fixed\0" |
| 14173 | /* 39664 */ "VST1d64Qwb_fixed\0" |
| 14174 | /* 39681 */ "VLD1d16Qwb_fixed\0" |
| 14175 | /* 39698 */ "VST1d16Qwb_fixed\0" |
| 14176 | /* 39715 */ "VLD1d8Qwb_fixed\0" |
| 14177 | /* 39731 */ "VST1d8Qwb_fixed\0" |
| 14178 | /* 39747 */ "VLD1d32Twb_fixed\0" |
| 14179 | /* 39764 */ "VST1d32Twb_fixed\0" |
| 14180 | /* 39781 */ "VLD1d64Twb_fixed\0" |
| 14181 | /* 39798 */ "VST1d64Twb_fixed\0" |
| 14182 | /* 39815 */ "VLD1d16Twb_fixed\0" |
| 14183 | /* 39832 */ "VST1d16Twb_fixed\0" |
| 14184 | /* 39849 */ "VLD1d8Twb_fixed\0" |
| 14185 | /* 39865 */ "VST1d8Twb_fixed\0" |
| 14186 | /* 39881 */ "VCVTs2fd\0" |
| 14187 | /* 39890 */ "VCVTxs2fd\0" |
| 14188 | /* 39900 */ "VCVTu2fd\0" |
| 14189 | /* 39909 */ "VCVTxu2fd\0" |
| 14190 | /* 39919 */ "VMLAfd\0" |
| 14191 | /* 39926 */ "VFMAfd\0" |
| 14192 | /* 39933 */ "VSUBfd\0" |
| 14193 | /* 39940 */ "VABDfd\0" |
| 14194 | /* 39947 */ "VADDfd\0" |
| 14195 | /* 39954 */ "VACGEfd\0" |
| 14196 | /* 39962 */ "VCGEfd\0" |
| 14197 | /* 39969 */ "VRECPEfd\0" |
| 14198 | /* 39978 */ "VRSQRTEfd\0" |
| 14199 | /* 39988 */ "VNEGfd\0" |
| 14200 | /* 39995 */ "VMULfd\0" |
| 14201 | /* 40002 */ "VMINfd\0" |
| 14202 | /* 40009 */ "VCEQfd\0" |
| 14203 | /* 40016 */ "VABSfd\0" |
| 14204 | /* 40023 */ "VMLSfd\0" |
| 14205 | /* 40030 */ "VFMSfd\0" |
| 14206 | /* 40037 */ "VRECPSfd\0" |
| 14207 | /* 40046 */ "VRSQRTSfd\0" |
| 14208 | /* 40056 */ "VACGTfd\0" |
| 14209 | /* 40064 */ "VCGTfd\0" |
| 14210 | /* 40071 */ "VMAXfd\0" |
| 14211 | /* 40078 */ "VMLAslfd\0" |
| 14212 | /* 40087 */ "VMULslfd\0" |
| 14213 | /* 40096 */ "VMLSslfd\0" |
| 14214 | /* 40105 */ "VCVTs2hd\0" |
| 14215 | /* 40114 */ "VCVTxs2hd\0" |
| 14216 | /* 40124 */ "VCVTu2hd\0" |
| 14217 | /* 40133 */ "VCVTxu2hd\0" |
| 14218 | /* 40143 */ "VMLAhd\0" |
| 14219 | /* 40150 */ "VFMAhd\0" |
| 14220 | /* 40157 */ "VSUBhd\0" |
| 14221 | /* 40164 */ "VABDhd\0" |
| 14222 | /* 40171 */ "VADDhd\0" |
| 14223 | /* 40178 */ "VACGEhd\0" |
| 14224 | /* 40186 */ "VCGEhd\0" |
| 14225 | /* 40193 */ "VRECPEhd\0" |
| 14226 | /* 40202 */ "VRSQRTEhd\0" |
| 14227 | /* 40212 */ "VNEGhd\0" |
| 14228 | /* 40219 */ "VMULhd\0" |
| 14229 | /* 40226 */ "VMINhd\0" |
| 14230 | /* 40233 */ "VCEQhd\0" |
| 14231 | /* 40240 */ "VABShd\0" |
| 14232 | /* 40247 */ "VMLShd\0" |
| 14233 | /* 40254 */ "VFMShd\0" |
| 14234 | /* 40261 */ "VRECPShd\0" |
| 14235 | /* 40270 */ "VRSQRTShd\0" |
| 14236 | /* 40280 */ "VACGThd\0" |
| 14237 | /* 40288 */ "VCGThd\0" |
| 14238 | /* 40295 */ "VMAXhd\0" |
| 14239 | /* 40302 */ "VMLAslhd\0" |
| 14240 | /* 40311 */ "VMULslhd\0" |
| 14241 | /* 40320 */ "VMLSslhd\0" |
| 14242 | /* 40329 */ "SEH_EpilogEnd\0" |
| 14243 | /* 40343 */ "SEH_PrologEnd\0" |
| 14244 | /* 40357 */ "t2LoopEnd\0" |
| 14245 | /* 40367 */ "VMULpd\0" |
| 14246 | /* 40374 */ "VCVTf2sd\0" |
| 14247 | /* 40383 */ "VCVTh2sd\0" |
| 14248 | /* 40392 */ "VCVTf2xsd\0" |
| 14249 | /* 40402 */ "VCVTh2xsd\0" |
| 14250 | /* 40412 */ "VCVTf2ud\0" |
| 14251 | /* 40421 */ "VCVTh2ud\0" |
| 14252 | /* 40430 */ "VCVTf2xud\0" |
| 14253 | /* 40440 */ "VCVTh2xud\0" |
| 14254 | /* 40450 */ "tADDframe\0" |
| 14255 | /* 40460 */ "MQQPRStore\0" |
| 14256 | /* 40471 */ "MQQQQPRStore\0" |
| 14257 | /* 40484 */ "VLDR_P0_pre\0" |
| 14258 | /* 40496 */ "VSTR_P0_pre\0" |
| 14259 | /* 40508 */ "MVE_VSTRB32_pre\0" |
| 14260 | /* 40524 */ "MVE_VSTRH32_pre\0" |
| 14261 | /* 40540 */ "MVE_VLDRBS32_pre\0" |
| 14262 | /* 40557 */ "MVE_VLDRHS32_pre\0" |
| 14263 | /* 40574 */ "MVE_VLDRBU32_pre\0" |
| 14264 | /* 40591 */ "MVE_VLDRHU32_pre\0" |
| 14265 | /* 40608 */ "MVE_VLDRWU32_pre\0" |
| 14266 | /* 40625 */ "MVE_VSTRWU32_pre\0" |
| 14267 | /* 40642 */ "MVE_VSTRB16_pre\0" |
| 14268 | /* 40658 */ "MVE_VLDRBS16_pre\0" |
| 14269 | /* 40675 */ "MVE_VLDRBU16_pre\0" |
| 14270 | /* 40692 */ "MVE_VLDRHU16_pre\0" |
| 14271 | /* 40709 */ "MVE_VSTRHU16_pre\0" |
| 14272 | /* 40726 */ "MVE_VLDRBU8_pre\0" |
| 14273 | /* 40742 */ "MVE_VSTRBU8_pre\0" |
| 14274 | /* 40758 */ "VLDR_FPSCR_NZCVQC_pre\0" |
| 14275 | /* 40780 */ "VSTR_FPSCR_NZCVQC_pre\0" |
| 14276 | /* 40802 */ "VLDR_FPSCR_pre\0" |
| 14277 | /* 40817 */ "VSTR_FPSCR_pre\0" |
| 14278 | /* 40832 */ "VLDR_VPR_pre\0" |
| 14279 | /* 40845 */ "VSTR_VPR_pre\0" |
| 14280 | /* 40858 */ "VLDR_FPCXTNS_pre\0" |
| 14281 | /* 40875 */ "VSTR_FPCXTNS_pre\0" |
| 14282 | /* 40892 */ "VLDR_FPCXTS_pre\0" |
| 14283 | /* 40908 */ "VSTR_FPCXTS_pre\0" |
| 14284 | /* 40924 */ "MVE_VLDRWU32_qi_pre\0" |
| 14285 | /* 40944 */ "MVE_VSTRW32_qi_pre\0" |
| 14286 | /* 40963 */ "MVE_VSTRD64_qi_pre\0" |
| 14287 | /* 40982 */ "MVE_VLDRDU64_qi_pre\0" |
| 14288 | /* 41002 */ "t2LEUpdate\0" |
| 14289 | /* 41013 */ "t2MOVsra_glue\0" |
| 14290 | /* 41027 */ "t2MOVsrl_glue\0" |
| 14291 | /* 41041 */ "VCVTh2f\0" |
| 14292 | /* 41049 */ "VPADDf\0" |
| 14293 | /* 41056 */ "VRINTANDf\0" |
| 14294 | /* 41066 */ "NEON_VMINNMNDf\0" |
| 14295 | /* 41081 */ "NEON_VMAXNMNDf\0" |
| 14296 | /* 41096 */ "VRINTMNDf\0" |
| 14297 | /* 41106 */ "VRINTNNDf\0" |
| 14298 | /* 41116 */ "VRINTPNDf\0" |
| 14299 | /* 41126 */ "VRINTXNDf\0" |
| 14300 | /* 41136 */ "VRINTZNDf\0" |
| 14301 | /* 41146 */ "VCVTANSDf\0" |
| 14302 | /* 41156 */ "VCVTMNSDf\0" |
| 14303 | /* 41166 */ "VCVTNNSDf\0" |
| 14304 | /* 41176 */ "VCVTPNSDf\0" |
| 14305 | /* 41186 */ "VCVTANUDf\0" |
| 14306 | /* 41196 */ "VCVTMNUDf\0" |
| 14307 | /* 41206 */ "VCVTNNUDf\0" |
| 14308 | /* 41216 */ "VCVTPNUDf\0" |
| 14309 | /* 41226 */ "VPMINf\0" |
| 14310 | /* 41233 */ "VRINTANQf\0" |
| 14311 | /* 41243 */ "NEON_VMINNMNQf\0" |
| 14312 | /* 41258 */ "NEON_VMAXNMNQf\0" |
| 14313 | /* 41273 */ "VRINTMNQf\0" |
| 14314 | /* 41283 */ "VRINTNNQf\0" |
| 14315 | /* 41293 */ "VRINTPNQf\0" |
| 14316 | /* 41303 */ "VRINTXNQf\0" |
| 14317 | /* 41313 */ "VRINTZNQf\0" |
| 14318 | /* 41323 */ "VCVTANSQf\0" |
| 14319 | /* 41333 */ "VCVTMNSQf\0" |
| 14320 | /* 41343 */ "VCVTNNSQf\0" |
| 14321 | /* 41353 */ "VCVTPNSQf\0" |
| 14322 | /* 41363 */ "VCVTANUQf\0" |
| 14323 | /* 41373 */ "VCVTMNUQf\0" |
| 14324 | /* 41383 */ "VCVTNNUQf\0" |
| 14325 | /* 41393 */ "VCVTPNUQf\0" |
| 14326 | /* 41403 */ "VPMAXf\0" |
| 14327 | /* 41410 */ "VLDR_P0_off\0" |
| 14328 | /* 41422 */ "VSTR_P0_off\0" |
| 14329 | /* 41434 */ "VLDR_FPSCR_NZCVQC_off\0" |
| 14330 | /* 41456 */ "VSTR_FPSCR_NZCVQC_off\0" |
| 14331 | /* 41478 */ "VLDR_FPSCR_off\0" |
| 14332 | /* 41493 */ "VSTR_FPSCR_off\0" |
| 14333 | /* 41508 */ "VLDR_VPR_off\0" |
| 14334 | /* 41521 */ "VSTR_VPR_off\0" |
| 14335 | /* 41534 */ "VLDR_FPCXTNS_off\0" |
| 14336 | /* 41551 */ "VSTR_FPCXTNS_off\0" |
| 14337 | /* 41568 */ "VLDR_FPCXTS_off\0" |
| 14338 | /* 41584 */ "VSTR_FPCXTS_off\0" |
| 14339 | /* 41600 */ "tBX_RET_vararg\0" |
| 14340 | /* 41615 */ "VCVTf2h\0" |
| 14341 | /* 41623 */ "VPADDh\0" |
| 14342 | /* 41630 */ "VRINTANDh\0" |
| 14343 | /* 41640 */ "NEON_VMINNMNDh\0" |
| 14344 | /* 41655 */ "NEON_VMAXNMNDh\0" |
| 14345 | /* 41670 */ "VRINTMNDh\0" |
| 14346 | /* 41680 */ "VRINTNNDh\0" |
| 14347 | /* 41690 */ "VRINTPNDh\0" |
| 14348 | /* 41700 */ "VRINTXNDh\0" |
| 14349 | /* 41710 */ "VRINTZNDh\0" |
| 14350 | /* 41720 */ "VCVTANSDh\0" |
| 14351 | /* 41730 */ "VCVTMNSDh\0" |
| 14352 | /* 41740 */ "VCVTNNSDh\0" |
| 14353 | /* 41750 */ "VCVTPNSDh\0" |
| 14354 | /* 41760 */ "VCVTANUDh\0" |
| 14355 | /* 41770 */ "VCVTMNUDh\0" |
| 14356 | /* 41780 */ "VCVTNNUDh\0" |
| 14357 | /* 41790 */ "VCVTPNUDh\0" |
| 14358 | /* 41800 */ "VPMINh\0" |
| 14359 | /* 41807 */ "VRINTANQh\0" |
| 14360 | /* 41817 */ "NEON_VMINNMNQh\0" |
| 14361 | /* 41832 */ "NEON_VMAXNMNQh\0" |
| 14362 | /* 41847 */ "VRINTMNQh\0" |
| 14363 | /* 41857 */ "VRINTNNQh\0" |
| 14364 | /* 41867 */ "VRINTPNQh\0" |
| 14365 | /* 41877 */ "VRINTXNQh\0" |
| 14366 | /* 41887 */ "VRINTZNQh\0" |
| 14367 | /* 41897 */ "VCVTANSQh\0" |
| 14368 | /* 41907 */ "VCVTMNSQh\0" |
| 14369 | /* 41917 */ "VCVTNNSQh\0" |
| 14370 | /* 41927 */ "VCVTPNSQh\0" |
| 14371 | /* 41937 */ "VCVTANUQh\0" |
| 14372 | /* 41947 */ "VCVTMNUQh\0" |
| 14373 | /* 41957 */ "VCVTNNUQh\0" |
| 14374 | /* 41967 */ "VCVTPNUQh\0" |
| 14375 | /* 41977 */ "VPMAXh\0" |
| 14376 | /* 41984 */ "MVE_VCVTf16f32bh\0" |
| 14377 | /* 42001 */ "MVE_VRSHRNi32bh\0" |
| 14378 | /* 42017 */ "MVE_VSHRNi32bh\0" |
| 14379 | /* 42032 */ "MVE_VMOVNi32bh\0" |
| 14380 | /* 42047 */ "MVE_VQDMULLs32bh\0" |
| 14381 | /* 42064 */ "MVE_VQSHRUNs32bh\0" |
| 14382 | /* 42081 */ "MVE_VQRSHRUNs32bh\0" |
| 14383 | /* 42099 */ "MVE_VQMOVUNs32bh\0" |
| 14384 | /* 42116 */ "MVE_VQMOVNs32bh\0" |
| 14385 | /* 42132 */ "MVE_VQDMULL_qr_s32bh\0" |
| 14386 | /* 42153 */ "MVE_VQMOVNu32bh\0" |
| 14387 | /* 42169 */ "MVE_VCVTf32f16bh\0" |
| 14388 | /* 42186 */ "MVE_VRSHRNi16bh\0" |
| 14389 | /* 42202 */ "MVE_VSHRNi16bh\0" |
| 14390 | /* 42217 */ "MVE_VMOVNi16bh\0" |
| 14391 | /* 42232 */ "MVE_VQDMULLs16bh\0" |
| 14392 | /* 42249 */ "MVE_VMOVLs16bh\0" |
| 14393 | /* 42264 */ "MVE_VQSHRUNs16bh\0" |
| 14394 | /* 42281 */ "MVE_VQRSHRUNs16bh\0" |
| 14395 | /* 42299 */ "MVE_VQMOVUNs16bh\0" |
| 14396 | /* 42316 */ "MVE_VQMOVNs16bh\0" |
| 14397 | /* 42332 */ "MVE_VQDMULL_qr_s16bh\0" |
| 14398 | /* 42353 */ "MVE_VSHLL_imms16bh\0" |
| 14399 | /* 42372 */ "MVE_VSHLL_lws16bh\0" |
| 14400 | /* 42390 */ "MVE_VMOVLu16bh\0" |
| 14401 | /* 42405 */ "MVE_VQMOVNu16bh\0" |
| 14402 | /* 42421 */ "MVE_VSHLL_immu16bh\0" |
| 14403 | /* 42440 */ "MVE_VSHLL_lwu16bh\0" |
| 14404 | /* 42458 */ "MVE_VMOVLs8bh\0" |
| 14405 | /* 42472 */ "MVE_VSHLL_imms8bh\0" |
| 14406 | /* 42490 */ "MVE_VSHLL_lws8bh\0" |
| 14407 | /* 42507 */ "MVE_VMOVLu8bh\0" |
| 14408 | /* 42521 */ "MVE_VSHLL_immu8bh\0" |
| 14409 | /* 42539 */ "MVE_VSHLL_lwu8bh\0" |
| 14410 | /* 42556 */ "Int_eh_sjlj_setup_dispatch\0" |
| 14411 | /* 42583 */ "MVE_VCVTf16f32th\0" |
| 14412 | /* 42600 */ "MVE_VRSHRNi32th\0" |
| 14413 | /* 42616 */ "MVE_VSHRNi32th\0" |
| 14414 | /* 42631 */ "MVE_VMOVNi32th\0" |
| 14415 | /* 42646 */ "MVE_VQDMULLs32th\0" |
| 14416 | /* 42663 */ "MVE_VQSHRUNs32th\0" |
| 14417 | /* 42680 */ "MVE_VQRSHRUNs32th\0" |
| 14418 | /* 42698 */ "MVE_VQMOVUNs32th\0" |
| 14419 | /* 42715 */ "MVE_VQMOVNs32th\0" |
| 14420 | /* 42731 */ "MVE_VQDMULL_qr_s32th\0" |
| 14421 | /* 42752 */ "MVE_VQMOVNu32th\0" |
| 14422 | /* 42768 */ "MVE_VCVTf32f16th\0" |
| 14423 | /* 42785 */ "MVE_VRSHRNi16th\0" |
| 14424 | /* 42801 */ "MVE_VSHRNi16th\0" |
| 14425 | /* 42816 */ "MVE_VMOVNi16th\0" |
| 14426 | /* 42831 */ "MVE_VQDMULLs16th\0" |
| 14427 | /* 42848 */ "MVE_VMOVLs16th\0" |
| 14428 | /* 42863 */ "MVE_VQSHRUNs16th\0" |
| 14429 | /* 42880 */ "MVE_VQRSHRUNs16th\0" |
| 14430 | /* 42898 */ "MVE_VQMOVUNs16th\0" |
| 14431 | /* 42915 */ "MVE_VQMOVNs16th\0" |
| 14432 | /* 42931 */ "MVE_VQDMULL_qr_s16th\0" |
| 14433 | /* 42952 */ "MVE_VSHLL_imms16th\0" |
| 14434 | /* 42971 */ "MVE_VSHLL_lws16th\0" |
| 14435 | /* 42989 */ "MVE_VMOVLu16th\0" |
| 14436 | /* 43004 */ "MVE_VQMOVNu16th\0" |
| 14437 | /* 43020 */ "MVE_VSHLL_immu16th\0" |
| 14438 | /* 43039 */ "MVE_VSHLL_lwu16th\0" |
| 14439 | /* 43057 */ "MVE_VMOVLs8th\0" |
| 14440 | /* 43071 */ "MVE_VSHLL_imms8th\0" |
| 14441 | /* 43089 */ "MVE_VSHLL_lws8th\0" |
| 14442 | /* 43106 */ "MVE_VMOVLu8th\0" |
| 14443 | /* 43120 */ "MVE_VSHLL_immu8th\0" |
| 14444 | /* 43138 */ "MVE_VSHLL_lwu8th\0" |
| 14445 | /* 43155 */ "tLDRBi\0" |
| 14446 | /* 43162 */ "tSTRBi\0" |
| 14447 | /* 43169 */ "t2MVNCCi\0" |
| 14448 | /* 43178 */ "t2MOVCCi\0" |
| 14449 | /* 43187 */ "t2BFi\0" |
| 14450 | /* 43193 */ "tLDRHi\0" |
| 14451 | /* 43200 */ "tSTRHi\0" |
| 14452 | /* 43207 */ "t2BFLi\0" |
| 14453 | /* 43214 */ "MVE_LSLLi\0" |
| 14454 | /* 43224 */ "MVE_ASRLi\0" |
| 14455 | /* 43234 */ "LSLi\0" |
| 14456 | /* 43239 */ "t2MVNi\0" |
| 14457 | /* 43246 */ "tADDrSPi\0" |
| 14458 | /* 43255 */ "tLDRi\0" |
| 14459 | /* 43261 */ "RORi\0" |
| 14460 | /* 43266 */ "ASRi\0" |
| 14461 | /* 43271 */ "LSRi\0" |
| 14462 | /* 43276 */ "MSRi\0" |
| 14463 | /* 43281 */ "tSTRi\0" |
| 14464 | /* 43287 */ "LDRSBTi\0" |
| 14465 | /* 43295 */ "LDRHTi\0" |
| 14466 | /* 43302 */ "STRHTi\0" |
| 14467 | /* 43309 */ "LDRSHTi\0" |
| 14468 | /* 43317 */ "t2MOVi\0" |
| 14469 | /* 43324 */ "tBLXi\0" |
| 14470 | /* 43330 */ "RRXi\0" |
| 14471 | /* 43335 */ "t2LDRBpci\0" |
| 14472 | /* 43345 */ "t2LDRSBpci\0" |
| 14473 | /* 43356 */ "t2PLDpci\0" |
| 14474 | /* 43365 */ "t2LDRHpci\0" |
| 14475 | /* 43375 */ "t2LDRSHpci\0" |
| 14476 | /* 43386 */ "t2PLIpci\0" |
| 14477 | /* 43395 */ "t2LDRpci\0" |
| 14478 | /* 43404 */ "tLDRpci\0" |
| 14479 | /* 43412 */ "TCRETURNdi\0" |
| 14480 | /* 43423 */ "LDRSBTii\0" |
| 14481 | /* 43432 */ "LDRHTii\0" |
| 14482 | /* 43440 */ "LDRSHTii\0" |
| 14483 | /* 43449 */ "tSUBspi\0" |
| 14484 | /* 43457 */ "tADDspi\0" |
| 14485 | /* 43465 */ "tLDRspi\0" |
| 14486 | /* 43473 */ "tSTRspi\0" |
| 14487 | /* 43481 */ "MVE_VLDRWU32_qi\0" |
| 14488 | /* 43497 */ "MVE_VSTRW32_qi\0" |
| 14489 | /* 43512 */ "MVE_VSTRD64_qi\0" |
| 14490 | /* 43527 */ "MVE_VLDRDU64_qi\0" |
| 14491 | /* 43543 */ "t2RSBri\0" |
| 14492 | /* 43551 */ "t2SUBri\0" |
| 14493 | /* 43559 */ "t2SBCri\0" |
| 14494 | /* 43567 */ "t2ADCri\0" |
| 14495 | /* 43575 */ "t2BICri\0" |
| 14496 | /* 43583 */ "RSCri\0" |
| 14497 | /* 43589 */ "t2ADDri\0" |
| 14498 | /* 43597 */ "t2ANDri\0" |
| 14499 | /* 43605 */ "t2LSLri\0" |
| 14500 | /* 43613 */ "tLSLri\0" |
| 14501 | /* 43620 */ "t2CMNri\0" |
| 14502 | /* 43628 */ "t2ORNri\0" |
| 14503 | /* 43636 */ "TCRETURNri\0" |
| 14504 | /* 43647 */ "t2CMPri\0" |
| 14505 | /* 43655 */ "t2TEQri\0" |
| 14506 | /* 43663 */ "t2EORri\0" |
| 14507 | /* 43671 */ "t2RORri\0" |
| 14508 | /* 43679 */ "t2ORRri\0" |
| 14509 | /* 43687 */ "t2ASRri\0" |
| 14510 | /* 43695 */ "tASRri\0" |
| 14511 | /* 43702 */ "t2LSRri\0" |
| 14512 | /* 43710 */ "tLSRri\0" |
| 14513 | /* 43717 */ "t2RSBSri\0" |
| 14514 | /* 43726 */ "t2SUBSri\0" |
| 14515 | /* 43735 */ "t2ADDSri\0" |
| 14516 | /* 43744 */ "tLSLSri\0" |
| 14517 | /* 43752 */ "t2TSTri\0" |
| 14518 | /* 43760 */ "MOVCCsi\0" |
| 14519 | /* 43768 */ "MVNsi\0" |
| 14520 | /* 43774 */ "t2MOVSsi\0" |
| 14521 | /* 43783 */ "t2MOVsi\0" |
| 14522 | /* 43791 */ "RSBrsi\0" |
| 14523 | /* 43798 */ "SUBrsi\0" |
| 14524 | /* 43805 */ "SBCrsi\0" |
| 14525 | /* 43812 */ "ADCrsi\0" |
| 14526 | /* 43819 */ "BICrsi\0" |
| 14527 | /* 43826 */ "RSCrsi\0" |
| 14528 | /* 43833 */ "ADDrsi\0" |
| 14529 | /* 43840 */ "ANDrsi\0" |
| 14530 | /* 43847 */ "CMPrsi\0" |
| 14531 | /* 43854 */ "TEQrsi\0" |
| 14532 | /* 43861 */ "EORrsi\0" |
| 14533 | /* 43868 */ "ORRrsi\0" |
| 14534 | /* 43875 */ "RSBSrsi\0" |
| 14535 | /* 43883 */ "SUBSrsi\0" |
| 14536 | /* 43891 */ "ADDSrsi\0" |
| 14537 | /* 43899 */ "TSTrsi\0" |
| 14538 | /* 43906 */ "CMNzrsi\0" |
| 14539 | /* 43914 */ "TRAPNaCl\0" |
| 14540 | /* 43923 */ "t2LEApcrel\0" |
| 14541 | /* 43934 */ "tLEApcrel\0" |
| 14542 | /* 43944 */ "t2LDRBpcrel\0" |
| 14543 | /* 43956 */ "t2LDRSBpcrel\0" |
| 14544 | /* 43969 */ "t2LDRHpcrel\0" |
| 14545 | /* 43981 */ "t2LDRSHpcrel\0" |
| 14546 | /* 43994 */ "t2LDRpcrel\0" |
| 14547 | /* 44005 */ "t2MOVTi16_ga_pcrel\0" |
| 14548 | /* 44024 */ "t2MOVi16_ga_pcrel\0" |
| 14549 | /* 44042 */ "t2LDRLIT_ga_pcrel\0" |
| 14550 | /* 44060 */ "tLDRLIT_ga_pcrel\0" |
| 14551 | /* 44077 */ "t2MOV_ga_pcrel\0" |
| 14552 | /* 44092 */ "t2LDRConstPool\0" |
| 14553 | /* 44107 */ "tLDRConstPool\0" |
| 14554 | /* 44121 */ "t2MOVCClsl\0" |
| 14555 | /* 44132 */ "MVE_VCVTs32f32m\0" |
| 14556 | /* 44148 */ "MVE_VCVTu32f32m\0" |
| 14557 | /* 44164 */ "MVE_VCVTs16f16m\0" |
| 14558 | /* 44180 */ "MVE_VCVTu16f16m\0" |
| 14559 | /* 44196 */ "t2SUBspImm\0" |
| 14560 | /* 44207 */ "t2ADDspImm\0" |
| 14561 | /* 44218 */ "t2MOVCCi32imm\0" |
| 14562 | /* 44232 */ "t2MOVi32imm\0" |
| 14563 | /* 44244 */ "tMOVi32imm\0" |
| 14564 | /* 44255 */ "t2LDRB_PRE_imm\0" |
| 14565 | /* 44270 */ "t2STRB_PRE_imm\0" |
| 14566 | /* 44285 */ "t2LDRSB_PRE_imm\0" |
| 14567 | /* 44301 */ "t2LDRH_PRE_imm\0" |
| 14568 | /* 44316 */ "t2STRH_PRE_imm\0" |
| 14569 | /* 44331 */ "t2LDRSH_PRE_imm\0" |
| 14570 | /* 44347 */ "t2LDR_PRE_imm\0" |
| 14571 | /* 44361 */ "t2STR_PRE_imm\0" |
| 14572 | /* 44375 */ "t2LDRB_OFFSET_imm\0" |
| 14573 | /* 44393 */ "t2STRB_OFFSET_imm\0" |
| 14574 | /* 44411 */ "t2LDRSB_OFFSET_imm\0" |
| 14575 | /* 44430 */ "t2LDRH_OFFSET_imm\0" |
| 14576 | /* 44448 */ "t2STRH_OFFSET_imm\0" |
| 14577 | /* 44466 */ "t2LDRSH_OFFSET_imm\0" |
| 14578 | /* 44485 */ "t2LDRB_POST_imm\0" |
| 14579 | /* 44501 */ "t2STRB_POST_imm\0" |
| 14580 | /* 44517 */ "t2LDRSB_POST_imm\0" |
| 14581 | /* 44534 */ "t2LDRH_POST_imm\0" |
| 14582 | /* 44550 */ "t2STRH_POST_imm\0" |
| 14583 | /* 44566 */ "t2LDRSH_POST_imm\0" |
| 14584 | /* 44583 */ "t2LDR_POST_imm\0" |
| 14585 | /* 44598 */ "t2STR_POST_imm\0" |
| 14586 | /* 44613 */ "ITasm\0" |
| 14587 | /* 44619 */ "MVE_VCVTs32f32n\0" |
| 14588 | /* 44635 */ "MVE_VCVTu32f32n\0" |
| 14589 | /* 44651 */ "MVE_VCVTf32s32n\0" |
| 14590 | /* 44667 */ "MVE_VCVTf32u32n\0" |
| 14591 | /* 44683 */ "MVE_VCVTs16f16n\0" |
| 14592 | /* 44699 */ "MVE_VCVTu16f16n\0" |
| 14593 | /* 44715 */ "MVE_VCVTf16s16n\0" |
| 14594 | /* 44731 */ "MVE_VCVTf16u16n\0" |
| 14595 | /* 44747 */ "VLD3d32Pseudo\0" |
| 14596 | /* 44761 */ "VST3d32Pseudo\0" |
| 14597 | /* 44775 */ "VLD4d32Pseudo\0" |
| 14598 | /* 44789 */ "VST4d32Pseudo\0" |
| 14599 | /* 44803 */ "VLD2LNd32Pseudo\0" |
| 14600 | /* 44819 */ "VST2LNd32Pseudo\0" |
| 14601 | /* 44835 */ "VLD3LNd32Pseudo\0" |
| 14602 | /* 44851 */ "VST3LNd32Pseudo\0" |
| 14603 | /* 44867 */ "VLD4LNd32Pseudo\0" |
| 14604 | /* 44883 */ "VST4LNd32Pseudo\0" |
| 14605 | /* 44899 */ "VLD3DUPd32Pseudo\0" |
| 14606 | /* 44916 */ "VLD4DUPd32Pseudo\0" |
| 14607 | /* 44933 */ "VLD2q32Pseudo\0" |
| 14608 | /* 44947 */ "VST2q32Pseudo\0" |
| 14609 | /* 44961 */ "VLD1LNq32Pseudo\0" |
| 14610 | /* 44977 */ "VST1LNq32Pseudo\0" |
| 14611 | /* 44993 */ "VLD2LNq32Pseudo\0" |
| 14612 | /* 45009 */ "VST2LNq32Pseudo\0" |
| 14613 | /* 45025 */ "VLD3LNq32Pseudo\0" |
| 14614 | /* 45041 */ "VST3LNq32Pseudo\0" |
| 14615 | /* 45057 */ "VLD4LNq32Pseudo\0" |
| 14616 | /* 45073 */ "VST4LNq32Pseudo\0" |
| 14617 | /* 45089 */ "VTBL3Pseudo\0" |
| 14618 | /* 45101 */ "VTBX3Pseudo\0" |
| 14619 | /* 45113 */ "VTBL4Pseudo\0" |
| 14620 | /* 45125 */ "VTBX4Pseudo\0" |
| 14621 | /* 45137 */ "VLD3d16Pseudo\0" |
| 14622 | /* 45151 */ "VST3d16Pseudo\0" |
| 14623 | /* 45165 */ "VLD4d16Pseudo\0" |
| 14624 | /* 45179 */ "VST4d16Pseudo\0" |
| 14625 | /* 45193 */ "VLD2LNd16Pseudo\0" |
| 14626 | /* 45209 */ "VST2LNd16Pseudo\0" |
| 14627 | /* 45225 */ "VLD3LNd16Pseudo\0" |
| 14628 | /* 45241 */ "VST3LNd16Pseudo\0" |
| 14629 | /* 45257 */ "VLD4LNd16Pseudo\0" |
| 14630 | /* 45273 */ "VST4LNd16Pseudo\0" |
| 14631 | /* 45289 */ "VLD3DUPd16Pseudo\0" |
| 14632 | /* 45306 */ "VLD4DUPd16Pseudo\0" |
| 14633 | /* 45323 */ "VLD2q16Pseudo\0" |
| 14634 | /* 45337 */ "VST2q16Pseudo\0" |
| 14635 | /* 45351 */ "VLD1LNq16Pseudo\0" |
| 14636 | /* 45367 */ "VST1LNq16Pseudo\0" |
| 14637 | /* 45383 */ "VLD2LNq16Pseudo\0" |
| 14638 | /* 45399 */ "VST2LNq16Pseudo\0" |
| 14639 | /* 45415 */ "VLD3LNq16Pseudo\0" |
| 14640 | /* 45431 */ "VST3LNq16Pseudo\0" |
| 14641 | /* 45447 */ "VLD4LNq16Pseudo\0" |
| 14642 | /* 45463 */ "VST4LNq16Pseudo\0" |
| 14643 | /* 45479 */ "VLD3d8Pseudo\0" |
| 14644 | /* 45492 */ "VST3d8Pseudo\0" |
| 14645 | /* 45505 */ "VLD4d8Pseudo\0" |
| 14646 | /* 45518 */ "VST4d8Pseudo\0" |
| 14647 | /* 45531 */ "VLD2LNd8Pseudo\0" |
| 14648 | /* 45546 */ "VST2LNd8Pseudo\0" |
| 14649 | /* 45561 */ "VLD3LNd8Pseudo\0" |
| 14650 | /* 45576 */ "VST3LNd8Pseudo\0" |
| 14651 | /* 45591 */ "VLD4LNd8Pseudo\0" |
| 14652 | /* 45606 */ "VST4LNd8Pseudo\0" |
| 14653 | /* 45621 */ "VLD3DUPd8Pseudo\0" |
| 14654 | /* 45637 */ "VLD4DUPd8Pseudo\0" |
| 14655 | /* 45653 */ "VLD2q8Pseudo\0" |
| 14656 | /* 45666 */ "VST2q8Pseudo\0" |
| 14657 | /* 45679 */ "VLD1LNq8Pseudo\0" |
| 14658 | /* 45694 */ "VST1LNq8Pseudo\0" |
| 14659 | /* 45709 */ "VLD1d32QPseudo\0" |
| 14660 | /* 45724 */ "VST1d32QPseudo\0" |
| 14661 | /* 45739 */ "VLD1d64QPseudo\0" |
| 14662 | /* 45754 */ "VST1d64QPseudo\0" |
| 14663 | /* 45769 */ "VLD1d16QPseudo\0" |
| 14664 | /* 45784 */ "VST1d16QPseudo\0" |
| 14665 | /* 45799 */ "VLD1d8QPseudo\0" |
| 14666 | /* 45813 */ "VST1d8QPseudo\0" |
| 14667 | /* 45827 */ "VLD1q32HighQPseudo\0" |
| 14668 | /* 45846 */ "VST1q32HighQPseudo\0" |
| 14669 | /* 45865 */ "VLD1q64HighQPseudo\0" |
| 14670 | /* 45884 */ "VST1q64HighQPseudo\0" |
| 14671 | /* 45903 */ "VLD1q16HighQPseudo\0" |
| 14672 | /* 45922 */ "VST1q16HighQPseudo\0" |
| 14673 | /* 45941 */ "VLD1q8HighQPseudo\0" |
| 14674 | /* 45959 */ "VST1q8HighQPseudo\0" |
| 14675 | /* 45977 */ "VLD1d32TPseudo\0" |
| 14676 | /* 45992 */ "VST1d32TPseudo\0" |
| 14677 | /* 46007 */ "VLD1d64TPseudo\0" |
| 14678 | /* 46022 */ "VST1d64TPseudo\0" |
| 14679 | /* 46037 */ "VLD1d16TPseudo\0" |
| 14680 | /* 46052 */ "VST1d16TPseudo\0" |
| 14681 | /* 46067 */ "VLD1d8TPseudo\0" |
| 14682 | /* 46081 */ "VST1d8TPseudo\0" |
| 14683 | /* 46095 */ "VLD1q32HighTPseudo\0" |
| 14684 | /* 46114 */ "VST1q32HighTPseudo\0" |
| 14685 | /* 46133 */ "VLD1q64HighTPseudo\0" |
| 14686 | /* 46152 */ "VST1q64HighTPseudo\0" |
| 14687 | /* 46171 */ "VLD1q16HighTPseudo\0" |
| 14688 | /* 46190 */ "VST1q16HighTPseudo\0" |
| 14689 | /* 46209 */ "VLD1q8HighTPseudo\0" |
| 14690 | /* 46227 */ "VST1q8HighTPseudo\0" |
| 14691 | /* 46245 */ "VLD2DUPq32OddPseudo\0" |
| 14692 | /* 46265 */ "VLD3DUPq32OddPseudo\0" |
| 14693 | /* 46285 */ "VLD4DUPq32OddPseudo\0" |
| 14694 | /* 46305 */ "VLD2DUPq16OddPseudo\0" |
| 14695 | /* 46325 */ "VLD3DUPq16OddPseudo\0" |
| 14696 | /* 46345 */ "VLD4DUPq16OddPseudo\0" |
| 14697 | /* 46365 */ "VLD2DUPq8OddPseudo\0" |
| 14698 | /* 46384 */ "VLD3DUPq8OddPseudo\0" |
| 14699 | /* 46403 */ "VLD4DUPq8OddPseudo\0" |
| 14700 | /* 46422 */ "VLD3q32oddPseudo\0" |
| 14701 | /* 46439 */ "VST3q32oddPseudo\0" |
| 14702 | /* 46456 */ "VLD4q32oddPseudo\0" |
| 14703 | /* 46473 */ "VST4q32oddPseudo\0" |
| 14704 | /* 46490 */ "VLD3q16oddPseudo\0" |
| 14705 | /* 46507 */ "VST3q16oddPseudo\0" |
| 14706 | /* 46524 */ "VLD4q16oddPseudo\0" |
| 14707 | /* 46541 */ "VST4q16oddPseudo\0" |
| 14708 | /* 46558 */ "VLD3q8oddPseudo\0" |
| 14709 | /* 46574 */ "VST3q8oddPseudo\0" |
| 14710 | /* 46590 */ "VLD4q8oddPseudo\0" |
| 14711 | /* 46606 */ "VST4q8oddPseudo\0" |
| 14712 | /* 46622 */ "t2BF_LabelPseudo\0" |
| 14713 | /* 46639 */ "VLD2DUPq32EvenPseudo\0" |
| 14714 | /* 46660 */ "VLD3DUPq32EvenPseudo\0" |
| 14715 | /* 46681 */ "VLD4DUPq32EvenPseudo\0" |
| 14716 | /* 46702 */ "VLD2DUPq16EvenPseudo\0" |
| 14717 | /* 46723 */ "VLD3DUPq16EvenPseudo\0" |
| 14718 | /* 46744 */ "VLD4DUPq16EvenPseudo\0" |
| 14719 | /* 46765 */ "VLD2DUPq8EvenPseudo\0" |
| 14720 | /* 46785 */ "VLD3DUPq8EvenPseudo\0" |
| 14721 | /* 46805 */ "VLD4DUPq8EvenPseudo\0" |
| 14722 | /* 46825 */ "tMOVCCr_pseudo\0" |
| 14723 | /* 46840 */ "t2CPS1p\0" |
| 14724 | /* 46848 */ "MVE_VCVTs32f32p\0" |
| 14725 | /* 46864 */ "MVE_VCVTu32f32p\0" |
| 14726 | /* 46880 */ "t2CPS2p\0" |
| 14727 | /* 46888 */ "t2CPS3p\0" |
| 14728 | /* 46896 */ "MVE_VCVTs16f16p\0" |
| 14729 | /* 46912 */ "MVE_VCVTu16f16p\0" |
| 14730 | /* 46928 */ "LDRcp\0" |
| 14731 | /* 46934 */ "CDE_VCX1_fpdp\0" |
| 14732 | /* 46948 */ "CDE_VCX2_fpdp\0" |
| 14733 | /* 46962 */ "CDE_VCX3_fpdp\0" |
| 14734 | /* 46976 */ "CDE_VCX1A_fpdp\0" |
| 14735 | /* 46991 */ "CDE_VCX2A_fpdp\0" |
| 14736 | /* 47006 */ "CDE_VCX3A_fpdp\0" |
| 14737 | /* 47021 */ "t2Int_eh_sjlj_setjmp_nofp\0" |
| 14738 | /* 47047 */ "BLX_noip\0" |
| 14739 | /* 47056 */ "BLX_pred_noip\0" |
| 14740 | /* 47070 */ "tBLXr_noip\0" |
| 14741 | /* 47081 */ "tInt_WIN_eh_sjlj_longjmp\0" |
| 14742 | /* 47106 */ "tInt_eh_sjlj_longjmp\0" |
| 14743 | /* 47127 */ "t2Int_eh_sjlj_setjmp\0" |
| 14744 | /* 47148 */ "tInt_eh_sjlj_setjmp\0" |
| 14745 | /* 47168 */ "SEH_Nop\0" |
| 14746 | /* 47176 */ "CDE_VCX1_fpsp\0" |
| 14747 | /* 47190 */ "CDE_VCX2_fpsp\0" |
| 14748 | /* 47204 */ "CDE_VCX3_fpsp\0" |
| 14749 | /* 47218 */ "CDE_VCX1A_fpsp\0" |
| 14750 | /* 47233 */ "CDE_VCX2A_fpsp\0" |
| 14751 | /* 47248 */ "CDE_VCX3A_fpsp\0" |
| 14752 | /* 47263 */ "t2WhileLoopSetup\0" |
| 14753 | /* 47280 */ "Int_eh_sjlj_dispatchsetup\0" |
| 14754 | /* 47306 */ "VDUPLN32q\0" |
| 14755 | /* 47316 */ "VDUP32q\0" |
| 14756 | /* 47324 */ "VNEGf32q\0" |
| 14757 | /* 47333 */ "VNEGs32q\0" |
| 14758 | /* 47342 */ "VDUPLN16q\0" |
| 14759 | /* 47352 */ "VDUP16q\0" |
| 14760 | /* 47360 */ "VNEGs16q\0" |
| 14761 | /* 47369 */ "VDUPLN8q\0" |
| 14762 | /* 47378 */ "VDUP8q\0" |
| 14763 | /* 47385 */ "VNEGs8q\0" |
| 14764 | /* 47393 */ "VBICq\0" |
| 14765 | /* 47399 */ "VANDq\0" |
| 14766 | /* 47405 */ "VRECPEq\0" |
| 14767 | /* 47413 */ "VRSQRTEq\0" |
| 14768 | /* 47422 */ "VBIFq\0" |
| 14769 | /* 47428 */ "VBSLq\0" |
| 14770 | /* 47434 */ "VORNq\0" |
| 14771 | /* 47440 */ "VMVNq\0" |
| 14772 | /* 47446 */ "VBSPq\0" |
| 14773 | /* 47452 */ "VSWPq\0" |
| 14774 | /* 47458 */ "VEORq\0" |
| 14775 | /* 47464 */ "VORRq\0" |
| 14776 | /* 47470 */ "VBITq\0" |
| 14777 | /* 47476 */ "VCNTq\0" |
| 14778 | /* 47482 */ "MVE_VMOV_rr_q\0" |
| 14779 | /* 47496 */ "VCVTs2fq\0" |
| 14780 | /* 47505 */ "VCVTxs2fq\0" |
| 14781 | /* 47515 */ "VCVTu2fq\0" |
| 14782 | /* 47524 */ "VCVTxu2fq\0" |
| 14783 | /* 47534 */ "VMLAfq\0" |
| 14784 | /* 47541 */ "VFMAfq\0" |
| 14785 | /* 47548 */ "VSUBfq\0" |
| 14786 | /* 47555 */ "VABDfq\0" |
| 14787 | /* 47562 */ "VADDfq\0" |
| 14788 | /* 47569 */ "VACGEfq\0" |
| 14789 | /* 47577 */ "VCGEfq\0" |
| 14790 | /* 47584 */ "VRECPEfq\0" |
| 14791 | /* 47593 */ "VRSQRTEfq\0" |
| 14792 | /* 47603 */ "VMULfq\0" |
| 14793 | /* 47610 */ "VMINfq\0" |
| 14794 | /* 47617 */ "VCEQfq\0" |
| 14795 | /* 47624 */ "VABSfq\0" |
| 14796 | /* 47631 */ "VMLSfq\0" |
| 14797 | /* 47638 */ "VFMSfq\0" |
| 14798 | /* 47645 */ "VRECPSfq\0" |
| 14799 | /* 47654 */ "VRSQRTSfq\0" |
| 14800 | /* 47664 */ "VACGTfq\0" |
| 14801 | /* 47672 */ "VCGTfq\0" |
| 14802 | /* 47679 */ "VMAXfq\0" |
| 14803 | /* 47686 */ "VMLAslfq\0" |
| 14804 | /* 47695 */ "VMULslfq\0" |
| 14805 | /* 47704 */ "VMLSslfq\0" |
| 14806 | /* 47713 */ "VCVTs2hq\0" |
| 14807 | /* 47722 */ "VCVTxs2hq\0" |
| 14808 | /* 47732 */ "VCVTu2hq\0" |
| 14809 | /* 47741 */ "VCVTxu2hq\0" |
| 14810 | /* 47751 */ "VMLAhq\0" |
| 14811 | /* 47758 */ "VFMAhq\0" |
| 14812 | /* 47765 */ "VSUBhq\0" |
| 14813 | /* 47772 */ "VABDhq\0" |
| 14814 | /* 47779 */ "VADDhq\0" |
| 14815 | /* 47786 */ "VACGEhq\0" |
| 14816 | /* 47794 */ "VCGEhq\0" |
| 14817 | /* 47801 */ "VRECPEhq\0" |
| 14818 | /* 47810 */ "VRSQRTEhq\0" |
| 14819 | /* 47820 */ "VNEGhq\0" |
| 14820 | /* 47827 */ "VMULhq\0" |
| 14821 | /* 47834 */ "VMINhq\0" |
| 14822 | /* 47841 */ "VCEQhq\0" |
| 14823 | /* 47848 */ "VABShq\0" |
| 14824 | /* 47855 */ "VMLShq\0" |
| 14825 | /* 47862 */ "VFMShq\0" |
| 14826 | /* 47869 */ "VRECPShq\0" |
| 14827 | /* 47878 */ "VRSQRTShq\0" |
| 14828 | /* 47888 */ "VACGThq\0" |
| 14829 | /* 47896 */ "VCGThq\0" |
| 14830 | /* 47903 */ "VMAXhq\0" |
| 14831 | /* 47910 */ "VMLAslhq\0" |
| 14832 | /* 47919 */ "VMULslhq\0" |
| 14833 | /* 47928 */ "VMLSslhq\0" |
| 14834 | /* 47937 */ "VMULpq\0" |
| 14835 | /* 47944 */ "MVE_VSTRB32_rq\0" |
| 14836 | /* 47959 */ "MVE_VSTRH32_rq\0" |
| 14837 | /* 47974 */ "MVE_VLDRBS32_rq\0" |
| 14838 | /* 47990 */ "MVE_VLDRHS32_rq\0" |
| 14839 | /* 48006 */ "MVE_VLDRBU32_rq\0" |
| 14840 | /* 48022 */ "MVE_VLDRHU32_rq\0" |
| 14841 | /* 48038 */ "MVE_VLDRWU32_rq\0" |
| 14842 | /* 48054 */ "MVE_VSTRW32_rq\0" |
| 14843 | /* 48069 */ "MVE_VSTRD64_rq\0" |
| 14844 | /* 48084 */ "MVE_VLDRDU64_rq\0" |
| 14845 | /* 48100 */ "MVE_VSTRB16_rq\0" |
| 14846 | /* 48115 */ "MVE_VSTRH16_rq\0" |
| 14847 | /* 48130 */ "MVE_VLDRBS16_rq\0" |
| 14848 | /* 48146 */ "MVE_VLDRBU16_rq\0" |
| 14849 | /* 48162 */ "MVE_VLDRHU16_rq\0" |
| 14850 | /* 48178 */ "MVE_VSTRB8_rq\0" |
| 14851 | /* 48192 */ "MVE_VLDRBU8_rq\0" |
| 14852 | /* 48207 */ "VCVTf2sq\0" |
| 14853 | /* 48216 */ "VCVTh2sq\0" |
| 14854 | /* 48225 */ "VCVTf2xsq\0" |
| 14855 | /* 48235 */ "VCVTh2xsq\0" |
| 14856 | /* 48245 */ "VCVTf2uq\0" |
| 14857 | /* 48254 */ "VCVTh2uq\0" |
| 14858 | /* 48263 */ "VCVTf2xuq\0" |
| 14859 | /* 48273 */ "VCVTh2xuq\0" |
| 14860 | /* 48283 */ "MVE_VPTv4f32r\0" |
| 14861 | /* 48297 */ "MVE_VCMPf32r\0" |
| 14862 | /* 48310 */ "MVE_VPTv4i32r\0" |
| 14863 | /* 48324 */ "MVE_VCMPi32r\0" |
| 14864 | /* 48337 */ "MVE_VPTv4s32r\0" |
| 14865 | /* 48351 */ "MVE_VCMPs32r\0" |
| 14866 | /* 48364 */ "MVE_VPTv4u32r\0" |
| 14867 | /* 48378 */ "MVE_VCMPu32r\0" |
| 14868 | /* 48391 */ "MVE_VPTv8f16r\0" |
| 14869 | /* 48405 */ "MVE_VCMPf16r\0" |
| 14870 | /* 48418 */ "MVE_VPTv8i16r\0" |
| 14871 | /* 48432 */ "MVE_VCMPi16r\0" |
| 14872 | /* 48445 */ "MVE_VPTv8s16r\0" |
| 14873 | /* 48459 */ "MVE_VCMPs16r\0" |
| 14874 | /* 48472 */ "MVE_VPTv8u16r\0" |
| 14875 | /* 48486 */ "MVE_VCMPu16r\0" |
| 14876 | /* 48499 */ "MVE_VPTv16i8r\0" |
| 14877 | /* 48513 */ "MVE_VCMPi8r\0" |
| 14878 | /* 48525 */ "MVE_VPTv16s8r\0" |
| 14879 | /* 48539 */ "MVE_VCMPs8r\0" |
| 14880 | /* 48551 */ "MVE_VPTv16u8r\0" |
| 14881 | /* 48565 */ "MVE_VCMPu8r\0" |
| 14882 | /* 48577 */ "tLDRBr\0" |
| 14883 | /* 48584 */ "tSTRBr\0" |
| 14884 | /* 48591 */ "t2MOVCCr\0" |
| 14885 | /* 48600 */ "t2BFr\0" |
| 14886 | /* 48606 */ "tLDRHr\0" |
| 14887 | /* 48613 */ "tSTRHr\0" |
| 14888 | /* 48620 */ "t2BFLr\0" |
| 14889 | /* 48627 */ "MVE_LSLLr\0" |
| 14890 | /* 48637 */ "MVE_ASRLr\0" |
| 14891 | /* 48647 */ "LSLr\0" |
| 14892 | /* 48652 */ "t2MVNr\0" |
| 14893 | /* 48659 */ "tCMPr\0" |
| 14894 | /* 48665 */ "tTAILJMPr\0" |
| 14895 | /* 48675 */ "tLDRr\0" |
| 14896 | /* 48681 */ "RORr\0" |
| 14897 | /* 48686 */ "ASRr\0" |
| 14898 | /* 48691 */ "LSRr\0" |
| 14899 | /* 48696 */ "tSTRr\0" |
| 14900 | /* 48702 */ "tBLXNSr\0" |
| 14901 | /* 48710 */ "tMOVSr\0" |
| 14902 | /* 48717 */ "LDRSBTr\0" |
| 14903 | /* 48725 */ "LDRHTr\0" |
| 14904 | /* 48732 */ "STRHTr\0" |
| 14905 | /* 48739 */ "LDRSHTr\0" |
| 14906 | /* 48747 */ "tBR_JTr\0" |
| 14907 | /* 48755 */ "t2MOVr\0" |
| 14908 | /* 48762 */ "tMOVr\0" |
| 14909 | /* 48768 */ "tBLXr\0" |
| 14910 | /* 48774 */ "tBfar\0" |
| 14911 | /* 48780 */ "LDRLIT_ga_pcrel_ldr\0" |
| 14912 | /* 48800 */ "MOV_ga_pcrel_ldr\0" |
| 14913 | /* 48817 */ "VLD2q32PseudoWB_register\0" |
| 14914 | /* 48842 */ "VST2q32PseudoWB_register\0" |
| 14915 | /* 48867 */ "VLD2q16PseudoWB_register\0" |
| 14916 | /* 48892 */ "VST2q16PseudoWB_register\0" |
| 14917 | /* 48917 */ "VLD2q8PseudoWB_register\0" |
| 14918 | /* 48941 */ "VST2q8PseudoWB_register\0" |
| 14919 | /* 48965 */ "VLD1d32QPseudoWB_register\0" |
| 14920 | /* 48991 */ "VST1d32QPseudoWB_register\0" |
| 14921 | /* 49017 */ "VLD1d64QPseudoWB_register\0" |
| 14922 | /* 49043 */ "VST1d64QPseudoWB_register\0" |
| 14923 | /* 49069 */ "VLD1d16QPseudoWB_register\0" |
| 14924 | /* 49095 */ "VST1d16QPseudoWB_register\0" |
| 14925 | /* 49121 */ "VLD1d8QPseudoWB_register\0" |
| 14926 | /* 49146 */ "VST1d8QPseudoWB_register\0" |
| 14927 | /* 49171 */ "VLD1d32TPseudoWB_register\0" |
| 14928 | /* 49197 */ "VST1d32TPseudoWB_register\0" |
| 14929 | /* 49223 */ "VLD1d64TPseudoWB_register\0" |
| 14930 | /* 49249 */ "VST1d64TPseudoWB_register\0" |
| 14931 | /* 49275 */ "VLD1d16TPseudoWB_register\0" |
| 14932 | /* 49301 */ "VST1d16TPseudoWB_register\0" |
| 14933 | /* 49327 */ "VLD1d8TPseudoWB_register\0" |
| 14934 | /* 49352 */ "VST1d8TPseudoWB_register\0" |
| 14935 | /* 49377 */ "VLD2DUPq32OddPseudoWB_register\0" |
| 14936 | /* 49408 */ "VLD2DUPq16OddPseudoWB_register\0" |
| 14937 | /* 49439 */ "VLD2DUPq8OddPseudoWB_register\0" |
| 14938 | /* 49469 */ "VLD2b32wb_register\0" |
| 14939 | /* 49488 */ "VST2b32wb_register\0" |
| 14940 | /* 49507 */ "VLD1d32wb_register\0" |
| 14941 | /* 49526 */ "VST1d32wb_register\0" |
| 14942 | /* 49545 */ "VLD2d32wb_register\0" |
| 14943 | /* 49564 */ "VST2d32wb_register\0" |
| 14944 | /* 49583 */ "VLD1DUPd32wb_register\0" |
| 14945 | /* 49605 */ "VLD2DUPd32wb_register\0" |
| 14946 | /* 49627 */ "VLD1q32wb_register\0" |
| 14947 | /* 49646 */ "VST1q32wb_register\0" |
| 14948 | /* 49665 */ "VLD2q32wb_register\0" |
| 14949 | /* 49684 */ "VST2q32wb_register\0" |
| 14950 | /* 49703 */ "VLD1DUPq32wb_register\0" |
| 14951 | /* 49725 */ "VLD2DUPd32x2wb_register\0" |
| 14952 | /* 49749 */ "VLD2DUPd16x2wb_register\0" |
| 14953 | /* 49773 */ "VLD2DUPd8x2wb_register\0" |
| 14954 | /* 49796 */ "VLD1d64wb_register\0" |
| 14955 | /* 49815 */ "VST1d64wb_register\0" |
| 14956 | /* 49834 */ "VLD1q64wb_register\0" |
| 14957 | /* 49853 */ "VST1q64wb_register\0" |
| 14958 | /* 49872 */ "VLD2b16wb_register\0" |
| 14959 | /* 49891 */ "VST2b16wb_register\0" |
| 14960 | /* 49910 */ "VLD1d16wb_register\0" |
| 14961 | /* 49929 */ "VST1d16wb_register\0" |
| 14962 | /* 49948 */ "VLD2d16wb_register\0" |
| 14963 | /* 49967 */ "VST2d16wb_register\0" |
| 14964 | /* 49986 */ "VLD1DUPd16wb_register\0" |
| 14965 | /* 50008 */ "VLD2DUPd16wb_register\0" |
| 14966 | /* 50030 */ "VLD1q16wb_register\0" |
| 14967 | /* 50049 */ "VST1q16wb_register\0" |
| 14968 | /* 50068 */ "VLD2q16wb_register\0" |
| 14969 | /* 50087 */ "VST2q16wb_register\0" |
| 14970 | /* 50106 */ "VLD1DUPq16wb_register\0" |
| 14971 | /* 50128 */ "VLD2b8wb_register\0" |
| 14972 | /* 50146 */ "VST2b8wb_register\0" |
| 14973 | /* 50164 */ "VLD1d8wb_register\0" |
| 14974 | /* 50182 */ "VST1d8wb_register\0" |
| 14975 | /* 50200 */ "VLD2d8wb_register\0" |
| 14976 | /* 50218 */ "VST2d8wb_register\0" |
| 14977 | /* 50236 */ "VLD1DUPd8wb_register\0" |
| 14978 | /* 50257 */ "VLD2DUPd8wb_register\0" |
| 14979 | /* 50278 */ "VLD1q8wb_register\0" |
| 14980 | /* 50296 */ "VST1q8wb_register\0" |
| 14981 | /* 50314 */ "VLD2q8wb_register\0" |
| 14982 | /* 50332 */ "VST2q8wb_register\0" |
| 14983 | /* 50350 */ "VLD1DUPq8wb_register\0" |
| 14984 | /* 50371 */ "VLD1d32Qwb_register\0" |
| 14985 | /* 50391 */ "VST1d32Qwb_register\0" |
| 14986 | /* 50411 */ "VLD1d64Qwb_register\0" |
| 14987 | /* 50431 */ "VST1d64Qwb_register\0" |
| 14988 | /* 50451 */ "VLD1d16Qwb_register\0" |
| 14989 | /* 50471 */ "VST1d16Qwb_register\0" |
| 14990 | /* 50491 */ "VLD1d8Qwb_register\0" |
| 14991 | /* 50510 */ "VST1d8Qwb_register\0" |
| 14992 | /* 50529 */ "VLD1d32Twb_register\0" |
| 14993 | /* 50549 */ "VST1d32Twb_register\0" |
| 14994 | /* 50569 */ "VLD1d64Twb_register\0" |
| 14995 | /* 50589 */ "VST1d64Twb_register\0" |
| 14996 | /* 50609 */ "VLD1d16Twb_register\0" |
| 14997 | /* 50629 */ "VST1d16Twb_register\0" |
| 14998 | /* 50649 */ "VLD1d8Twb_register\0" |
| 14999 | /* 50668 */ "VST1d8Twb_register\0" |
| 15000 | /* 50687 */ "tCMPhir\0" |
| 15001 | /* 50695 */ "t2MOVCCror\0" |
| 15002 | /* 50706 */ "tADDspr\0" |
| 15003 | /* 50714 */ "t2RSBrr\0" |
| 15004 | /* 50722 */ "t2SUBrr\0" |
| 15005 | /* 50730 */ "tSUBrr\0" |
| 15006 | /* 50737 */ "t2SBCrr\0" |
| 15007 | /* 50745 */ "t2ADCrr\0" |
| 15008 | /* 50753 */ "t2BICrr\0" |
| 15009 | /* 50761 */ "RSCrr\0" |
| 15010 | /* 50767 */ "t2ADDrr\0" |
| 15011 | /* 50775 */ "tADDrr\0" |
| 15012 | /* 50782 */ "t2ANDrr\0" |
| 15013 | /* 50790 */ "t2LSLrr\0" |
| 15014 | /* 50798 */ "tLSLrr\0" |
| 15015 | /* 50805 */ "t2ORNrr\0" |
| 15016 | /* 50813 */ "t2CMPrr\0" |
| 15017 | /* 50821 */ "t2TEQrr\0" |
| 15018 | /* 50829 */ "t2EORrr\0" |
| 15019 | /* 50837 */ "t2RORrr\0" |
| 15020 | /* 50845 */ "t2ORRrr\0" |
| 15021 | /* 50853 */ "t2ASRrr\0" |
| 15022 | /* 50861 */ "tASRrr\0" |
| 15023 | /* 50868 */ "t2LSRrr\0" |
| 15024 | /* 50876 */ "tLSRrr\0" |
| 15025 | /* 50883 */ "t2SUBSrr\0" |
| 15026 | /* 50892 */ "tSUBSrr\0" |
| 15027 | /* 50900 */ "t2ADDSrr\0" |
| 15028 | /* 50909 */ "tADDSrr\0" |
| 15029 | /* 50917 */ "t2TSTrr\0" |
| 15030 | /* 50925 */ "MVE_VMOV_q_rr\0" |
| 15031 | /* 50939 */ "tADDhirr\0" |
| 15032 | /* 50948 */ "t2CMNzrr\0" |
| 15033 | /* 50957 */ "MOVCCsr\0" |
| 15034 | /* 50965 */ "MVNsr\0" |
| 15035 | /* 50971 */ "t2MOVSsr\0" |
| 15036 | /* 50980 */ "t2MOVsr\0" |
| 15037 | /* 50988 */ "t2MOVCCasr\0" |
| 15038 | /* 50999 */ "t2MOVCClsr\0" |
| 15039 | /* 51010 */ "RSBrsr\0" |
| 15040 | /* 51017 */ "SUBrsr\0" |
| 15041 | /* 51024 */ "SBCrsr\0" |
| 15042 | /* 51031 */ "ADCrsr\0" |
| 15043 | /* 51038 */ "BICrsr\0" |
| 15044 | /* 51045 */ "RSCrsr\0" |
| 15045 | /* 51052 */ "ADDrsr\0" |
| 15046 | /* 51059 */ "ANDrsr\0" |
| 15047 | /* 51066 */ "CMPrsr\0" |
| 15048 | /* 51073 */ "TEQrsr\0" |
| 15049 | /* 51080 */ "EORrsr\0" |
| 15050 | /* 51087 */ "ORRrsr\0" |
| 15051 | /* 51094 */ "RSBSrsr\0" |
| 15052 | /* 51102 */ "SUBSrsr\0" |
| 15053 | /* 51110 */ "ADDSrsr\0" |
| 15054 | /* 51118 */ "TSTrsr\0" |
| 15055 | /* 51125 */ "CMNzrsr\0" |
| 15056 | /* 51133 */ "t2LDRBs\0" |
| 15057 | /* 51141 */ "t2STRBs\0" |
| 15058 | /* 51149 */ "t2LDRSBs\0" |
| 15059 | /* 51158 */ "t2PLDs\0" |
| 15060 | /* 51165 */ "t2LDRHs\0" |
| 15061 | /* 51173 */ "t2STRHs\0" |
| 15062 | /* 51181 */ "t2LDRSHs\0" |
| 15063 | /* 51190 */ "t2PLIs\0" |
| 15064 | /* 51197 */ "t2MVNs\0" |
| 15065 | /* 51204 */ "t2LDRs\0" |
| 15066 | /* 51211 */ "t2STRs\0" |
| 15067 | /* 51218 */ "t2PLDWs\0" |
| 15068 | /* 51226 */ "tLDRLIT_ga_abs\0" |
| 15069 | /* 51241 */ "SEH_SaveFRegs\0" |
| 15070 | /* 51255 */ "SEH_SaveRegs\0" |
| 15071 | /* 51268 */ "LDRBrs\0" |
| 15072 | /* 51275 */ "STRBrs\0" |
| 15073 | /* 51282 */ "t2RSBrs\0" |
| 15074 | /* 51290 */ "t2SUBrs\0" |
| 15075 | /* 51298 */ "t2SBCrs\0" |
| 15076 | /* 51306 */ "t2ADCrs\0" |
| 15077 | /* 51314 */ "t2BICrs\0" |
| 15078 | /* 51322 */ "t2ADDrs\0" |
| 15079 | /* 51330 */ "PLDrs\0" |
| 15080 | /* 51336 */ "t2ANDrs\0" |
| 15081 | /* 51344 */ "PLIrs\0" |
| 15082 | /* 51350 */ "t2ORNrs\0" |
| 15083 | /* 51358 */ "t2CMPrs\0" |
| 15084 | /* 51366 */ "t2TEQrs\0" |
| 15085 | /* 51374 */ "LDRrs\0" |
| 15086 | /* 51380 */ "t2EORrs\0" |
| 15087 | /* 51388 */ "t2ORRrs\0" |
| 15088 | /* 51396 */ "STRrs\0" |
| 15089 | /* 51402 */ "t2RSBSrs\0" |
| 15090 | /* 51411 */ "t2SUBSrs\0" |
| 15091 | /* 51420 */ "t2ADDSrs\0" |
| 15092 | /* 51429 */ "t2TSTrs\0" |
| 15093 | /* 51437 */ "PLDWrs\0" |
| 15094 | /* 51444 */ "BR_JTm_rs\0" |
| 15095 | /* 51454 */ "t2CMNzrs\0" |
| 15096 | /* 51463 */ "MRSsys\0" |
| 15097 | /* 51470 */ "SEH_Nop_Ret\0" |
| 15098 | /* 51482 */ "SEH_SaveRegs_Ret\0" |
| 15099 | /* 51499 */ "tTPsoft\0" |
| 15100 | /* 51507 */ "SEH_EpilogStart\0" |
| 15101 | /* 51523 */ "t2WhileLoopStart\0" |
| 15102 | /* 51540 */ "t2DoLoopStart\0" |
| 15103 | /* 51554 */ "VLDR_P0_post\0" |
| 15104 | /* 51567 */ "VSTR_P0_post\0" |
| 15105 | /* 51580 */ "MVE_VSTRB32_post\0" |
| 15106 | /* 51597 */ "MVE_VSTRH32_post\0" |
| 15107 | /* 51614 */ "MVE_VLDRBS32_post\0" |
| 15108 | /* 51632 */ "MVE_VLDRHS32_post\0" |
| 15109 | /* 51650 */ "MVE_VLDRBU32_post\0" |
| 15110 | /* 51668 */ "MVE_VLDRHU32_post\0" |
| 15111 | /* 51686 */ "MVE_VLDRWU32_post\0" |
| 15112 | /* 51704 */ "MVE_VSTRWU32_post\0" |
| 15113 | /* 51722 */ "MVE_VSTRB16_post\0" |
| 15114 | /* 51739 */ "MVE_VLDRBS16_post\0" |
| 15115 | /* 51757 */ "MVE_VLDRBU16_post\0" |
| 15116 | /* 51775 */ "MVE_VLDRHU16_post\0" |
| 15117 | /* 51793 */ "MVE_VSTRHU16_post\0" |
| 15118 | /* 51811 */ "MVE_VLDRBU8_post\0" |
| 15119 | /* 51828 */ "MVE_VSTRBU8_post\0" |
| 15120 | /* 51845 */ "VLDR_FPSCR_NZCVQC_post\0" |
| 15121 | /* 51868 */ "VSTR_FPSCR_NZCVQC_post\0" |
| 15122 | /* 51891 */ "VLDR_FPSCR_post\0" |
| 15123 | /* 51907 */ "VSTR_FPSCR_post\0" |
| 15124 | /* 51923 */ "VLDR_VPR_post\0" |
| 15125 | /* 51937 */ "VSTR_VPR_post\0" |
| 15126 | /* 51951 */ "VLDR_FPCXTNS_post\0" |
| 15127 | /* 51969 */ "VSTR_FPCXTNS_post\0" |
| 15128 | /* 51987 */ "VLDR_FPCXTS_post\0" |
| 15129 | /* 52004 */ "VSTR_FPCXTS_post\0" |
| 15130 | /* 52021 */ "MVE_VSTRH32_rq_u\0" |
| 15131 | /* 52038 */ "MVE_VLDRHS32_rq_u\0" |
| 15132 | /* 52056 */ "MVE_VLDRHU32_rq_u\0" |
| 15133 | /* 52074 */ "MVE_VLDRWU32_rq_u\0" |
| 15134 | /* 52092 */ "MVE_VSTRW32_rq_u\0" |
| 15135 | /* 52109 */ "MVE_VSTRD64_rq_u\0" |
| 15136 | /* 52126 */ "MVE_VLDRDU64_rq_u\0" |
| 15137 | /* 52144 */ "MVE_VSTRH16_rq_u\0" |
| 15138 | /* 52161 */ "MVE_VLDRHU16_rq_u\0" |
| 15139 | /* 52179 */ "t2STRB_preidx\0" |
| 15140 | /* 52193 */ "t2STRH_preidx\0" |
| 15141 | /* 52207 */ "t2STR_preidx\0" |
| 15142 | /* 52220 */ "STRBi_preidx\0" |
| 15143 | /* 52233 */ "STRi_preidx\0" |
| 15144 | /* 52245 */ "STRBr_preidx\0" |
| 15145 | /* 52258 */ "STRr_preidx\0" |
| 15146 | /* 52270 */ "tLDR_postidx\0" |
| 15147 | /* 52283 */ "MVE_VCVTs32f32_fix\0" |
| 15148 | /* 52302 */ "MVE_VCVTu32f32_fix\0" |
| 15149 | /* 52321 */ "MVE_VCVTf32s32_fix\0" |
| 15150 | /* 52340 */ "MVE_VCVTf32u32_fix\0" |
| 15151 | /* 52359 */ "MVE_VCVTs16f16_fix\0" |
| 15152 | /* 52378 */ "MVE_VCVTu16f16_fix\0" |
| 15153 | /* 52397 */ "MVE_VCVTf16s16_fix\0" |
| 15154 | /* 52416 */ "MVE_VCVTf16u16_fix\0" |
| 15155 | /* 52435 */ "MQPRCopy\0" |
| 15156 | /* 52444 */ "MVE_VCVTs32f32z\0" |
| 15157 | /* 52460 */ "MVE_VCVTu32f32z\0" |
| 15158 | /* 52476 */ "MVE_VCVTs16f16z\0" |
| 15159 | /* 52492 */ "MVE_VCVTu16f16z\0" |
| 15160 | /* 52508 */ "tCMNz\0" |
| 15161 | }; |
| 15162 | #ifdef __GNUC__ |
| 15163 | #pragma GCC diagnostic pop |
| 15164 | #endif |
| 15165 | |
| 15166 | extern const unsigned ARMInstrNameIndices[] = { |
| 15167 | 30988U, 31964U, 33157U, 32311U, 31224U, 31205U, 31233U, 31507U, |
| 15168 | 29884U, 29899U, 29829U, 29976U, 34327U, 29664U, 35645U, 29842U, |
| 15169 | 30984U, 31214U, 29246U, 36743U, 29373U, 35535U, 24934U, 29191U, |
| 15170 | 29234U, 32592U, 31461U, 35429U, 28826U, 32889U, 30151U, 35418U, |
| 15171 | 29396U, 32789U, 32776U, 33242U, 35016U, 35215U, 31358U, 31417U, |
| 15172 | 31390U, 31250U, 33207U, 32512U, 36764U, 33483U, 32742U, 29712U, |
| 15173 | 36107U, 36137U, 32154U, 24646U, 24007U, 31689U, 36190U, 36204U, |
| 15174 | 31761U, 31768U, 31775U, 31785U, 24899U, 33659U, 33622U, 29827U, |
| 15175 | 30986U, 36557U, 29674U, 29689U, 31528U, 34967U, 33952U, 35579U, |
| 15176 | 33969U, 33559U, 24231U, 34281U, 35440U, 33829U, 35618U, 29755U, |
| 15177 | 33218U, 25008U, 24205U, 24990U, 35478U, 35459U, 32132U, 33267U, |
| 15178 | 33286U, 24502U, 24446U, 24476U, 24487U, 24427U, 24457U, 29440U, |
| 15179 | 29424U, 34371U, 30102U, 30119U, 24662U, 24013U, 24905U, 24857U, |
| 15180 | 33664U, 33628U, 36428U, 32280U, 36411U, 32263U, 24606U, 23983U, |
| 15181 | 36346U, 32198U, 32660U, 32638U, 29226U, 30296U, 24954U, 34986U, |
| 15182 | 35550U, 24146U, 34477U, 35382U, 34504U, 36121U, 24223U, 35371U, |
| 15183 | 35359U, 35525U, 30143U, 36100U, 29913U, 36130U, 31331U, 33353U, |
| 15184 | 33339U, 31293U, 33346U, 33822U, 31587U, 32721U, 32714U, 32728U, |
| 15185 | 32735U, 34977U, 32504U, 29267U, 32488U, 29212U, 32496U, 29259U, |
| 15186 | 32480U, 29204U, 32542U, 32534U, 30393U, 30385U, 34796U, 34786U, |
| 15187 | 34776U, 34766U, 34816U, 34806U, 36631U, 36641U, 34840U, 34853U, |
| 15188 | 36651U, 36661U, 34866U, 34879U, 24564U, 23962U, 31623U, 23544U, |
| 15189 | 24413U, 36162U, 31740U, 36294U, 31110U, 32937U, 8342U, 9U, |
| 15190 | 30136U, 8285U, 0U, 32912U, 32944U, 29869U, 36092U, 24195U, |
| 15191 | 31066U, 31101U, 32696U, 32705U, 33887U, 32169U, 34344U, 29764U, |
| 15192 | 32044U, 32054U, 29316U, 29331U, 32001U, 32033U, 36211U, 36237U, |
| 15193 | 36223U, 29275U, 29303U, 29288U, 24652U, 31136U, 32232U, 36380U, |
| 15194 | 32256U, 36404U, 33894U, 24981U, 24971U, 33152U, 35239U, 29351U, |
| 15195 | 33540U, 33520U, 35334U, 35313U, 33574U, 33591U, 34401U, 36838U, |
| 15196 | 29809U, 36825U, 29791U, 32763U, 32682U, 29651U, 31337U, 34162U, |
| 15197 | 32304U, 32125U, 34154U, 32296U, 32117U, 30663U, 30454U, 30446U, |
| 15198 | 35588U, 33506U, 35451U, 35496U, 35628U, 33187U, 29360U, 24252U, |
| 15199 | 29733U, 29409U, 24592U, 23969U, 31651U, 36169U, 31747U, 23550U, |
| 15200 | 35596U, 32921U, 33306U, 33322U, 36734U, 29380U, 29745U, 35169U, |
| 15201 | 32550U, 32625U, 32601U, 32613U, 24571U, 31630U, 24547U, 31606U, |
| 15202 | 36329U, 32181U, 32012U, 31980U, 24630U, 31673U, 24883U, 33644U, |
| 15203 | 33606U, 36363U, 32215U, 36387U, 32239U, 36610U, 36624U, 33883U, |
| 15204 | 43737U, 50902U, 43891U, 51110U, 32463U, 32874U, 43266U, 48686U, |
| 15205 | 23576U, 9585U, 9578U, 47047U, 47056U, 33407U, 31345U, 31447U, |
| 15206 | 38138U, 253U, 51444U, 48748U, 31439U, 10175U, 656U, 8549U, |
| 15207 | 18012U, 36748U, 351U, 44613U, 47280U, 47107U, 47129U, 47023U, |
| 15208 | 42556U, 34238U, 34557U, 23639U, 30266U, 35006U, 35938U, 44094U, |
| 15209 | 43432U, 51227U, 44044U, 48780U, 43423U, 43440U, 35960U, 43925U, |
| 15210 | 35290U, 31182U, 43234U, 48647U, 43271U, 48691U, 36736U, 9663U, |
| 15211 | 43180U, 15105U, 44220U, 48593U, 43760U, 50957U, 36675U, 44007U, |
| 15212 | 44079U, 48800U, 44026U, 44234U, 41015U, 41029U, 52435U, 38116U, |
| 15213 | 40460U, 38126U, 40471U, 9701U, 35703U, 35684U, 43171U, 24532U, |
| 15214 | 33200U, 23821U, 30534U, 23854U, 30679U, 33840U, 23829U, 30572U, |
| 15215 | 8315U, 33679U, 33701U, 33724U, 43261U, 48681U, 36685U, 43330U, |
| 15216 | 43719U, 43875U, 51094U, 40329U, 51507U, 47168U, 51470U, 40343U, |
| 15217 | 51241U, 33439U, 51255U, 51482U, 32801U, 37924U, 9669U, 9685U, |
| 15218 | 29220U, 31191U, 35949U, 52220U, 52245U, 52195U, 35970U, 52233U, |
| 15219 | 52258U, 33428U, 43728U, 50885U, 43883U, 51102U, 23655U, 23687U, |
| 15220 | 38071U, 48666U, 9653U, 43412U, 43636U, 310U, 51500U, 9677U, |
| 15221 | 9693U, 11531U, 2034U, 19026U, 10317U, 820U, 18146U, 10915U, |
| 15222 | 1418U, 18586U, 11559U, 2062U, 19052U, 10363U, 866U, 18190U, |
| 15223 | 10967U, 1470U, 18636U, 11721U, 2224U, 10633U, 1136U, 11273U, |
| 15224 | 1776U, 11643U, 2146U, 19130U, 10501U, 1004U, 18322U, 11123U, |
| 15225 | 1626U, 18786U, 11805U, 2308U, 19202U, 10771U, 1274U, 18448U, |
| 15226 | 11429U, 1932U, 18930U, 11587U, 2090U, 19078U, 10409U, 912U, |
| 15227 | 18234U, 11019U, 1522U, 18686U, 11749U, 2252U, 10679U, 1182U, |
| 15228 | 11325U, 1828U, 11483U, 1986U, 18982U, 10233U, 736U, 18066U, |
| 15229 | 10819U, 1322U, 18494U, 11673U, 2176U, 19158U, 10549U, 1052U, |
| 15230 | 18368U, 11177U, 1680U, 18838U, 11658U, 2161U, 19144U, 10525U, |
| 15231 | 1028U, 18345U, 11150U, 1653U, 18812U, 11820U, 2323U, 19216U, |
| 15232 | 10795U, 1298U, 18471U, 11456U, 1959U, 18956U, 11615U, 2118U, |
| 15233 | 19104U, 10455U, 958U, 18278U, 11071U, 1574U, 18736U, 11777U, |
| 15234 | 2280U, 10725U, 1228U, 11377U, 1880U, 11507U, 2010U, 19004U, |
| 15235 | 10275U, 778U, 18106U, 10867U, 1370U, 18540U, 11697U, 2200U, |
| 15236 | 19180U, 10591U, 1094U, 18408U, 11225U, 1728U, 18884U, 18U, |
| 15237 | 37484U, 37492U, 41U, 37500U, 11545U, 2048U, 19039U, 10340U, |
| 15238 | 843U, 18168U, 10941U, 1444U, 18611U, 11573U, 2076U, 19065U, |
| 15239 | 10386U, 889U, 18212U, 10993U, 1496U, 18661U, 11735U, 2238U, |
| 15240 | 10656U, 1159U, 11299U, 1802U, 11601U, 2104U, 19091U, 10432U, |
| 15241 | 935U, 18256U, 11045U, 1548U, 18711U, 11763U, 2266U, 10702U, |
| 15242 | 1205U, 11351U, 1854U, 11495U, 1998U, 18993U, 10254U, 757U, |
| 15243 | 18086U, 10843U, 1346U, 18517U, 11685U, 2188U, 19169U, 10570U, |
| 15244 | 1073U, 18388U, 11201U, 1704U, 18861U, 11629U, 2132U, 19117U, |
| 15245 | 10478U, 981U, 18300U, 11097U, 1600U, 18761U, 11791U, 2294U, |
| 15246 | 10748U, 1251U, 11403U, 1906U, 11519U, 2022U, 19015U, 10296U, |
| 15247 | 799U, 18126U, 10891U, 1394U, 18563U, 11709U, 2212U, 19191U, |
| 15248 | 10612U, 1115U, 18428U, 11249U, 1752U, 18907U, 31146U, 31124U, |
| 15249 | 33881U, 43735U, 50900U, 51420U, 46622U, 35280U, 31090U, 51540U, |
| 15250 | 32857U, 35004U, 44375U, 44485U, 44255U, 43944U, 44092U, 44430U, |
| 15251 | 44534U, 44301U, 43969U, 44042U, 44411U, 44517U, 44285U, 43956U, |
| 15252 | 44466U, 44566U, 44331U, 43981U, 44583U, 44347U, 37899U, 43994U, |
| 15253 | 43923U, 35288U, 37801U, 40357U, 37788U, 50988U, 43178U, 15103U, |
| 15254 | 44218U, 44121U, 50999U, 48591U, 50695U, 43774U, 50971U, 44005U, |
| 15255 | 44077U, 44024U, 44232U, 43783U, 50980U, 43169U, 43717U, 51402U, |
| 15256 | 44393U, 44501U, 44270U, 52179U, 44448U, 44550U, 44316U, 52193U, |
| 15257 | 44598U, 44361U, 52207U, 43726U, 50883U, 51411U, 23653U, 23685U, |
| 15258 | 35246U, 35263U, 47263U, 51523U, 33450U, 32838U, 33918U, 8530U, |
| 15259 | 21350U, 50909U, 40450U, 32462U, 32873U, 31378U, 47070U, 33406U, |
| 15260 | 24947U, 48747U, 35039U, 31438U, 35049U, 41600U, 48774U, 10174U, |
| 15261 | 655U, 18011U, 26159U, 44107U, 51226U, 44060U, 52270U, 37912U, |
| 15262 | 43934U, 35301U, 43744U, 46825U, 44244U, 35030U, 33900U, 33912U, |
| 15263 | 8522U, 21342U, 50892U, 38070U, 25034U, 48665U, 35255U, 35272U, |
| 15264 | 51499U, 43569U, 50747U, 43812U, 51031U, 43591U, 50769U, 43833U, |
| 15265 | 51052U, 33178U, 28901U, 29646U, 24168U, 24181U, 43599U, 50784U, |
| 15266 | 43840U, 51059U, 29017U, 33081U, 29033U, 33097U, 36064U, 23917U, |
| 15267 | 36033U, 24128U, 30980U, 43577U, 50755U, 43819U, 51038U, 35520U, |
| 15268 | 31202U, 36671U, 38187U, 43325U, 38171U, 36490U, 31120U, 35050U, |
| 15269 | 38179U, 37475U, 137U, 23260U, 24359U, 23315U, 8434U, 23283U, |
| 15270 | 24368U, 23325U, 8500U, 23292U, 24377U, 23335U, 46976U, 47218U, |
| 15271 | 37850U, 46934U, 47176U, 37811U, 46991U, 47233U, 37864U, 46948U, |
| 15272 | 47190U, 37824U, 47006U, 47248U, 37878U, 46962U, 47204U, 37837U, |
| 15273 | 32692U, 8310U, 36589U, 36821U, 43622U, 50950U, 43906U, 51125U, |
| 15274 | 43649U, 50815U, 43847U, 51066U, 46842U, 46882U, 46890U, 23571U, |
| 15275 | 23715U, 30288U, 36286U, 30188U, 36259U, 29858U, 23812U, 23844U, |
| 15276 | 43665U, 50831U, 43861U, 51080U, 34999U, 29056U, 30747U, 34573U, |
| 15277 | 26386U, 23486U, 26242U, 34892U, 26398U, 23494U, 26254U, 35407U, |
| 15278 | 35355U, 24328U, 23850U, 23353U, 23584U, 36551U, 24049U, 29110U, |
| 15279 | 30827U, 30205U, 35113U, 32383U, 35868U, 29582U, 35059U, 32329U, |
| 15280 | 35724U, 29450U, 35143U, 32413U, 35894U, 29606U, 35087U, 32357U, |
| 15281 | 35785U, 29506U, 23360U, 26067U, 23733U, 26302U, 23407U, 26136U, |
| 15282 | 23782U, 26423U, 31899U, 30044U, 31845U, 29990U, 31795U, 29926U, |
| 15283 | 147U, 51268U, 28844U, 35807U, 29526U, 36581U, 24067U, 29128U, |
| 15284 | 30845U, 30537U, 43295U, 48725U, 35831U, 29548U, 23857U, 43287U, |
| 15285 | 48717U, 35772U, 29494U, 30682U, 43309U, 48739U, 35855U, 29570U, |
| 15286 | 31929U, 30074U, 31873U, 30018U, 31821U, 29952U, 46928U, 227U, |
| 15287 | 51374U, 33172U, 8352U, 33766U, 8370U, 23504U, 34028U, 33398U, |
| 15288 | 15224U, 43319U, 15234U, 48757U, 24318U, 43785U, 50982U, 24307U, |
| 15289 | 8272U, 24313U, 8279U, 34277U, 38161U, 51463U, 33811U, 38149U, |
| 15290 | 43276U, 31602U, 43224U, 48637U, 10187U, 668U, 8561U, 18023U, |
| 15291 | 32820U, 32829U, 43214U, 48627U, 31578U, 33360U, 31544U, 31300U, |
| 15292 | 31473U, 33371U, 31556U, 31320U, 31495U, 31310U, 31484U, 33381U, |
| 15293 | 31567U, 16020U, 6539U, 22011U, 17180U, 7800U, 22908U, 12325U, |
| 15294 | 2822U, 15742U, 6235U, 21754U, 16990U, 7602U, 22733U, 12439U, |
| 15295 | 2936U, 15982U, 6501U, 21976U, 24112U, 30918U, 37524U, 37655U, |
| 15296 | 37557U, 37694U, 37574U, 37714U, 37508U, 37636U, 37606U, 37752U, |
| 15297 | 37590U, 37733U, 37541U, 37675U, 37621U, 37770U, 12574U, 3071U, |
| 15298 | 15273U, 5804U, 21404U, 12350U, 2847U, 15136U, 5676U, 21171U, |
| 15299 | 24874U, 24132U, 15322U, 5853U, 9893U, 395U, 17793U, 12337U, |
| 15300 | 2834U, 15114U, 5654U, 21151U, 15994U, 6513U, 21987U, 16240U, |
| 15301 | 6759U, 22186U, 12258U, 2755U, 12427U, 48405U, 2924U, 48297U, |
| 15302 | 15210U, 48432U, 5760U, 48324U, 21308U, 48513U, 15957U, 48459U, |
| 15303 | 6476U, 48351U, 21953U, 48539U, 17100U, 48486U, 7720U, 48378U, |
| 15304 | 22834U, 48565U, 12374U, 2871U, 9871U, 373U, 8538U, 17773U, |
| 15305 | 41984U, 42583U, 52397U, 44715U, 52416U, 44731U, 42169U, 42768U, |
| 15306 | 52321U, 44651U, 52340U, 44667U, 52359U, 36877U, 44164U, 44683U, |
| 15307 | 46896U, 52476U, 52283U, 36845U, 44132U, 44619U, 46848U, 52444U, |
| 15308 | 52378U, 36893U, 44180U, 44699U, 46912U, 52492U, 52302U, 36861U, |
| 15309 | 44148U, 44635U, 46864U, 52460U, 17112U, 7732U, 22845U, 9882U, |
| 15310 | 384U, 17783U, 17138U, 7758U, 22869U, 33469U, 12463U, 2960U, |
| 15311 | 12542U, 3039U, 12271U, 2768U, 12451U, 2948U, 16309U, 6805U, |
| 15312 | 22251U, 17328U, 7925U, 23031U, 15782U, 6275U, 21791U, 17016U, |
| 15313 | 7628U, 22757U, 15754U, 6247U, 21765U, 16275U, 6771U, 22219U, |
| 15314 | 17294U, 7891U, 22999U, 15716U, 6209U, 21730U, 16964U, 7576U, |
| 15315 | 22709U, 17125U, 7745U, 22857U, 17152U, 7772U, 22882U, 9990U, |
| 15316 | 37101U, 485U, 36909U, 17828U, 37293U, 10042U, 37165U, 537U, |
| 15317 | 36973U, 17876U, 37353U, 10016U, 37133U, 511U, 36941U, 17852U, |
| 15318 | 37323U, 10068U, 37197U, 563U, 37005U, 17900U, 37383U, 10108U, |
| 15319 | 37229U, 589U, 37037U, 17937U, 37413U, 10134U, 37261U, 615U, |
| 15320 | 37069U, 17961U, 37443U, 9905U, 51739U, 40658U, 48130U, 407U, |
| 15321 | 51614U, 40540U, 47974U, 9936U, 51757U, 40675U, 48146U, 433U, |
| 15322 | 51650U, 40574U, 48006U, 17804U, 51811U, 40726U, 48192U, 43527U, |
| 15323 | 40982U, 48084U, 52126U, 420U, 51632U, 40557U, 47990U, 52038U, |
| 15324 | 9949U, 51775U, 40692U, 48162U, 52161U, 446U, 51668U, 40591U, |
| 15325 | 48022U, 52056U, 459U, 51686U, 40608U, 43481U, 40924U, 48038U, |
| 15326 | 52074U, 16109U, 6628U, 22064U, 15689U, 6182U, 21705U, 12496U, |
| 15327 | 2993U, 12298U, 2795U, 12527U, 3024U, 12413U, 2910U, 16136U, |
| 15328 | 6655U, 22089U, 17237U, 7857U, 22946U, 16158U, 6677U, 22109U, |
| 15329 | 17259U, 7879U, 22966U, 16095U, 6614U, 22051U, 15676U, 6169U, |
| 15330 | 21693U, 12480U, 2977U, 12283U, 2780U, 12512U, 3009U, 12399U, |
| 15331 | 2896U, 16123U, 6642U, 22077U, 17224U, 7844U, 22934U, 15935U, |
| 15332 | 6464U, 21933U, 17078U, 7708U, 22814U, 16382U, 6916U, 22320U, |
| 15333 | 17362U, 7978U, 23063U, 16867U, 7479U, 22651U, 16033U, 6552U, |
| 15334 | 22023U, 17193U, 7813U, 22920U, 16801U, 7373U, 22621U, 16398U, |
| 15335 | 6932U, 17378U, 7994U, 16884U, 7496U, 16048U, 6567U, 17208U, |
| 15336 | 7828U, 16817U, 7389U, 15305U, 5836U, 21434U, 15241U, 5772U, |
| 15337 | 21374U, 16432U, 6966U, 22335U, 16920U, 7532U, 22667U, 16080U, |
| 15338 | 6599U, 22037U, 16851U, 7423U, 22636U, 16415U, 6949U, 16902U, |
| 15339 | 7514U, 16064U, 6583U, 16834U, 7406U, 42249U, 42848U, 42458U, |
| 15340 | 43057U, 42390U, 42989U, 42507U, 43106U, 42217U, 42816U, 42032U, |
| 15341 | 42631U, 694U, 16252U, 22197U, 17271U, 22977U, 50925U, 47482U, |
| 15342 | 10213U, 716U, 18047U, 3103U, 15367U, 5898U, 9593U, 21450U, |
| 15343 | 15913U, 6406U, 21913U, 17056U, 7668U, 22794U, 15426U, 21505U, |
| 15344 | 15702U, 6195U, 21717U, 16950U, 7562U, 22696U, 15440U, 21526U, |
| 15345 | 16006U, 6525U, 21998U, 17166U, 7786U, 22895U, 12590U, 3087U, |
| 15346 | 15289U, 5820U, 21419U, 12387U, 2884U, 15188U, 5728U, 21288U, |
| 15347 | 32448U, 15337U, 5868U, 12362U, 2859U, 15821U, 6314U, 21827U, |
| 15348 | 32439U, 33779U, 15352U, 5883U, 35509U, 31283U, 35980U, 19589U, |
| 15349 | 48499U, 21680U, 48525U, 22683U, 48551U, 2677U, 48283U, 4615U, |
| 15350 | 48310U, 6156U, 48337U, 7549U, 48364U, 12190U, 48391U, 14064U, |
| 15351 | 48418U, 15663U, 48445U, 16937U, 48472U, 15969U, 6488U, 21964U, |
| 15352 | 16326U, 6822U, 22267U, 17345U, 7942U, 23047U, 15795U, 6288U, |
| 15353 | 21803U, 17029U, 7641U, 22769U, 16170U, 6689U, 22120U, 15833U, |
| 15354 | 6326U, 21838U, 16661U, 7195U, 22489U, 16698U, 7232U, 22524U, |
| 15355 | 16205U, 6724U, 22153U, 15866U, 6359U, 21869U, 16343U, 6839U, |
| 15356 | 22283U, 15148U, 5688U, 21215U, 42332U, 42931U, 42132U, 42731U, |
| 15357 | 42232U, 42831U, 42047U, 42646U, 42316U, 42915U, 42116U, 42715U, |
| 15358 | 42405U, 43004U, 42153U, 42752U, 42299U, 42898U, 42099U, 42698U, |
| 15359 | 15808U, 6301U, 21815U, 16187U, 6706U, 22136U, 15849U, 6342U, |
| 15360 | 21853U, 16679U, 7213U, 22506U, 16717U, 7251U, 22542U, 16222U, |
| 15361 | 6741U, 22169U, 15882U, 6375U, 21884U, 16362U, 6858U, 22301U, |
| 15362 | 15163U, 5703U, 21229U, 16468U, 7002U, 22369U, 17415U, 8031U, |
| 15363 | 23097U, 16753U, 7287U, 22576U, 17606U, 8222U, 23215U, 16544U, |
| 15364 | 7078U, 17491U, 8107U, 16577U, 7111U, 17524U, 8140U, 42281U, |
| 15365 | 42880U, 42081U, 42680U, 16643U, 7177U, 22472U, 16448U, 6982U, |
| 15366 | 22350U, 17395U, 8011U, 23078U, 16737U, 7271U, 22561U, 17590U, |
| 15367 | 8206U, 23200U, 16594U, 7128U, 22426U, 17541U, 8157U, 23154U, |
| 15368 | 16528U, 7062U, 17475U, 8091U, 16561U, 7095U, 17508U, 8124U, |
| 15369 | 42264U, 42863U, 42064U, 42663U, 16292U, 6788U, 22235U, 17311U, |
| 15370 | 7908U, 23015U, 15729U, 6222U, 21742U, 16977U, 7589U, 22721U, |
| 15371 | 17998U, 10094U, 17924U, 10160U, 641U, 17985U, 15768U, 6261U, |
| 15372 | 21778U, 17002U, 7614U, 22744U, 23301U, 31720U, 32094U, 32578U, |
| 15373 | 36315U, 36800U, 23269U, 31706U, 32080U, 32564U, 36301U, 36786U, |
| 15374 | 6878U, 7959U, 7439U, 6419U, 7681U, 7335U, 6897U, 7459U, |
| 15375 | 6437U, 7354U, 15899U, 6392U, 21900U, 17042U, 7654U, 22781U, |
| 15376 | 16489U, 7023U, 22389U, 17436U, 8052U, 23117U, 16770U, 7304U, |
| 15377 | 22592U, 17623U, 8239U, 23231U, 42186U, 42785U, 42001U, 42600U, |
| 15378 | 16610U, 7144U, 22441U, 17557U, 8173U, 23169U, 24098U, 30908U, |
| 15379 | 24158U, 42353U, 42952U, 42472U, 43071U, 42421U, 43020U, 42521U, |
| 15380 | 43120U, 42372U, 42971U, 42490U, 43089U, 42440U, 43039U, 42539U, |
| 15381 | 43138U, 16509U, 7043U, 22408U, 17456U, 8072U, 23136U, 15382U, |
| 15382 | 5913U, 21464U, 16786U, 7320U, 22607U, 17639U, 8255U, 23246U, |
| 15383 | 42202U, 42801U, 42017U, 42616U, 16627U, 7161U, 22457U, 17574U, |
| 15384 | 8190U, 23185U, 15398U, 5929U, 21479U, 15412U, 5943U, 21492U, |
| 15385 | 10003U, 37117U, 498U, 36925U, 17840U, 37308U, 10055U, 37181U, |
| 15386 | 550U, 36989U, 17888U, 37368U, 10029U, 37149U, 524U, 36957U, |
| 15387 | 17864U, 37338U, 10081U, 37213U, 576U, 37021U, 17912U, 37398U, |
| 15388 | 10121U, 37245U, 602U, 37053U, 17949U, 37428U, 10147U, 37277U, |
| 15389 | 628U, 37085U, 17973U, 37458U, 9727U, 51722U, 40642U, 48100U, |
| 15390 | 327U, 51580U, 40508U, 47944U, 48178U, 17816U, 51828U, 40742U, |
| 15391 | 43512U, 40963U, 48069U, 52109U, 48115U, 52144U, 339U, 51597U, |
| 15392 | 40524U, 47959U, 52021U, 9962U, 51793U, 40709U, 43497U, 40944U, |
| 15393 | 48054U, 52092U, 472U, 51704U, 40625U, 12558U, 3055U, 15257U, |
| 15394 | 5788U, 21389U, 12313U, 2810U, 15091U, 5642U, 21133U, 10200U, |
| 15395 | 681U, 8574U, 18035U, 43241U, 48654U, 43768U, 50965U, 41081U, |
| 15396 | 41655U, 41258U, 41832U, 41066U, 41640U, 41243U, 41817U, 43681U, |
| 15397 | 50847U, 43868U, 51087U, 34917U, 23892U, 245U, 51437U, 178U, |
| 15398 | 51330U, 218U, 51344U, 24625U, 9836U, 17742U, 36707U, 24541U, |
| 15399 | 23956U, 36462U, 24002U, 9779U, 17683U, 35210U, 36153U, 9977U, |
| 15400 | 30711U, 23345U, 26054U, 23725U, 26290U, 23399U, 26124U, 23773U, |
| 15401 | 26410U, 43545U, 50716U, 43791U, 51010U, 43583U, 50761U, 43826U, |
| 15402 | 51045U, 9855U, 17759U, 36722U, 23839U, 43561U, 50739U, 43805U, |
| 15403 | 51024U, 36605U, 36185U, 31272U, 24927U, 32110U, 24086U, 30180U, |
| 15404 | 31700U, 32558U, 59U, 113U, 30195U, 8293U, 67U, 121U, |
| 15405 | 9816U, 17724U, 36691U, 36446U, 9759U, 17665U, 24177U, 23607U, |
| 15406 | 34908U, 24395U, 36495U, 31168U, 23616U, 34925U, 24759U, 36513U, |
| 15407 | 23900U, 36010U, 23883U, 36001U, 24031U, 36076U, 28915U, 36533U, |
| 15408 | 24775U, 36523U, 23510U, 33115U, 34034U, 33803U, 31667U, 33419U, |
| 15409 | 24519U, 36504U, 23626U, 34935U, 31514U, 23910U, 36020U, 24040U, |
| 15410 | 36085U, 28973U, 36542U, 23375U, 26090U, 23767U, 26376U, 23480U, |
| 15411 | 26232U, 23797U, 26446U, 34828U, 9920U, 36477U, 9798U, 17700U, |
| 15412 | 35128U, 32398U, 35881U, 29594U, 35073U, 32343U, 35736U, 29461U, |
| 15413 | 35157U, 32427U, 35906U, 29617U, 35100U, 32370U, 35796U, 29516U, |
| 15414 | 31596U, 23805U, 36573U, 24058U, 29119U, 30836U, 30373U, 23369U, |
| 15415 | 26080U, 23750U, 26327U, 23431U, 26172U, 23791U, 26436U, 31914U, |
| 15416 | 30059U, 31859U, 30004U, 31808U, 29939U, 157U, 51275U, 28882U, |
| 15417 | 35819U, 29537U, 36597U, 24076U, 29137U, 30854U, 30575U, 43302U, |
| 15418 | 48732U, 35843U, 29559U, 31943U, 30088U, 31886U, 30031U, 31833U, |
| 15419 | 29964U, 236U, 51396U, 43553U, 50724U, 43798U, 51017U, 24333U, |
| 15420 | 32908U, 23816U, 23591U, 9709U, 30246U, 23930U, 9741U, 30757U, |
| 15421 | 43657U, 50823U, 43854U, 51073U, 32608U, 43914U, 23877U, 43754U, |
| 15422 | 50919U, 43899U, 51118U, 9864U, 17767U, 36729U, 36619U, 29782U, |
| 15423 | 36199U, 9826U, 17733U, 36699U, 36454U, 9769U, 17674U, 31160U, |
| 15424 | 31176U, 31522U, 9845U, 17750U, 36714U, 36469U, 9788U, 17691U, |
| 15425 | 17716U, 17656U, 34835U, 9929U, 36484U, 9807U, 17708U, 23599U, |
| 15426 | 9719U, 30254U, 23943U, 9750U, 30770U, 9112U, 4933U, 14382U, |
| 15427 | 9362U, 5312U, 14761U, 19669U, 3649U, 13137U, 4816U, 14265U, |
| 15428 | 20504U, 19916U, 3978U, 13466U, 5195U, 14644U, 20767U, 9148U, |
| 15429 | 4982U, 14431U, 9398U, 5361U, 14810U, 39940U, 47555U, 40164U, |
| 15430 | 47772U, 19727U, 3707U, 13195U, 4874U, 14323U, 20557U, 19974U, |
| 15431 | 4036U, 13524U, 5253U, 14702U, 20820U, 28895U, 30601U, 34365U, |
| 15432 | 40016U, 47624U, 40240U, 47848U, 19559U, 3386U, 12874U, 4585U, |
| 15433 | 14034U, 20416U, 39954U, 47569U, 40178U, 47786U, 40056U, 47664U, |
| 15434 | 40280U, 47888U, 24678U, 30315U, 3282U, 12770U, 20330U, 9160U, |
| 15435 | 5007U, 14456U, 9410U, 5386U, 14835U, 33924U, 9303U, 5172U, |
| 15436 | 14621U, 9553U, 5551U, 15000U, 39947U, 47562U, 40171U, 47779U, |
| 15437 | 19487U, 8613U, 3138U, 8949U, 12626U, 4409U, 13897U, 20249U, |
| 15438 | 38023U, 47399U, 33023U, 30992U, 33048U, 31020U, 38017U, 3446U, |
| 15439 | 12934U, 4658U, 14107U, 47393U, 38046U, 47422U, 38104U, 47470U, |
| 15440 | 38052U, 47428U, 38080U, 47446U, 2579U, 12102U, 2666U, 12179U, |
| 15441 | 40009U, 47617U, 40233U, 47841U, 19538U, 3365U, 12853U, 4564U, |
| 15442 | 14013U, 20397U, 20198U, 2622U, 4356U, 12135U, 2722U, 13844U, |
| 15443 | 5609U, 12225U, 15058U, 21075U, 39962U, 47577U, 40186U, 47794U, |
| 15444 | 19775U, 3755U, 13243U, 4922U, 14371U, 20601U, 20022U, 4084U, |
| 15445 | 13572U, 5301U, 14750U, 20864U, 20176U, 2600U, 4334U, 12113U, |
| 15446 | 2700U, 13822U, 5587U, 12203U, 15036U, 21055U, 40064U, 47672U, |
| 15447 | 40288U, 47896U, 19894U, 3914U, 13402U, 5149U, 14598U, 20747U, |
| 15448 | 20141U, 4243U, 13731U, 5528U, 14977U, 21010U, 20209U, 2633U, |
| 15449 | 4367U, 12146U, 2733U, 13855U, 5620U, 12236U, 15069U, 21085U, |
| 15450 | 20187U, 2611U, 4345U, 12124U, 2711U, 13833U, 5598U, 12214U, |
| 15451 | 15047U, 21065U, 19569U, 3396U, 12884U, 4595U, 14044U, 20425U, |
| 15452 | 20220U, 2644U, 4378U, 12157U, 2744U, 13866U, 5631U, 12247U, |
| 15453 | 15080U, 21095U, 19622U, 3436U, 12924U, 4648U, 14097U, 20461U, |
| 15454 | 2568U, 38196U, 12091U, 38234U, 2655U, 38215U, 12168U, 38253U, |
| 15455 | 25088U, 24692U, 30337U, 33945U, 29152U, 30869U, 34657U, 30512U, |
| 15456 | 34216U, 29176U, 30893U, 34681U, 38110U, 47476U, 41146U, 41720U, |
| 15457 | 41323U, 41897U, 41186U, 41760U, 41363U, 41937U, 28887U, 30593U, |
| 15458 | 34357U, 29064U, 30781U, 34605U, 30307U, 24705U, 33990U, 30607U, |
| 15459 | 33930U, 41156U, 41730U, 41333U, 41907U, 41196U, 41770U, 41373U, |
| 15460 | 41947U, 28940U, 30641U, 34445U, 29072U, 30789U, 34613U, 41166U, |
| 15461 | 41740U, 41343U, 41917U, 41206U, 41780U, 41383U, 41957U, 28948U, |
| 15462 | 30655U, 34453U, 29080U, 30797U, 34621U, 41176U, 41750U, 41353U, |
| 15463 | 41927U, 41216U, 41790U, 41393U, 41967U, 28956U, 30671U, 34461U, |
| 15464 | 29088U, 30805U, 34629U, 28964U, 30321U, 24720U, 34005U, 30695U, |
| 15465 | 41615U, 40374U, 48207U, 40412U, 48245U, 40392U, 48225U, 40430U, |
| 15466 | 48263U, 41041U, 40383U, 48216U, 40421U, 48254U, 40402U, 48235U, |
| 15467 | 40440U, 48273U, 39881U, 47496U, 40105U, 47713U, 39900U, 47515U, |
| 15468 | 40124U, 47732U, 39890U, 47505U, 40114U, 47722U, 39909U, 47524U, |
| 15469 | 40133U, 47741U, 29096U, 30813U, 34637U, 37976U, 47352U, 37949U, |
| 15470 | 47316U, 38002U, 47378U, 37966U, 47342U, 37939U, 47306U, 37993U, |
| 15471 | 47369U, 38092U, 47458U, 12083U, 2560U, 19460U, 15655U, 6148U, |
| 15472 | 9633U, 21673U, 24407U, 30223U, 24766U, 30928U, 33034U, 31004U, |
| 15473 | 33860U, 39926U, 47541U, 40150U, 47758U, 28927U, 30628U, 24782U, |
| 15474 | 30936U, 33041U, 31012U, 34432U, 40030U, 47638U, 40254U, 47862U, |
| 15475 | 24420U, 30229U, 33866U, 28933U, 30634U, 34438U, 24828U, 30426U, |
| 15476 | 34085U, 24816U, 30414U, 34073U, 5740U, 15947U, 21944U, 17090U, |
| 15477 | 22825U, 19751U, 3731U, 13219U, 4898U, 14347U, 20579U, 19998U, |
| 15478 | 4060U, 13548U, 5277U, 14726U, 20842U, 19703U, 3683U, 13171U, |
| 15479 | 4850U, 14299U, 20535U, 19950U, 4012U, 13500U, 5229U, 14678U, |
| 15480 | 20798U, 30649U, 36058U, 12031U, 39288U, 49986U, 2516U, 38945U, |
| 15481 | 49583U, 19413U, 39499U, 50236U, 15614U, 39390U, 50106U, 6107U, |
| 15482 | 39047U, 49703U, 21636U, 39595U, 50350U, 11935U, 25502U, 2428U, |
| 15483 | 25150U, 19327U, 25850U, 45351U, 27228U, 44961U, 26762U, 45679U, |
| 15484 | 27678U, 11851U, 32989U, 45769U, 38494U, 49069U, 39681U, 50451U, |
| 15485 | 34732U, 46037U, 38676U, 49275U, 39815U, 50609U, 39224U, 49910U, |
| 15486 | 2354U, 32953U, 45709U, 38402U, 48965U, 39613U, 50371U, 34696U, |
| 15487 | 45977U, 38584U, 49171U, 39747U, 50529U, 38881U, 49507U, 8587U, |
| 15488 | 32971U, 45739U, 38448U, 49017U, 39647U, 50411U, 34714U, 46007U, |
| 15489 | 38630U, 49223U, 39781U, 50569U, 39128U, 49796U, 19244U, 33007U, |
| 15490 | 45799U, 38540U, 49121U, 39715U, 50491U, 34750U, 46067U, 38722U, |
| 15491 | 49327U, 39849U, 50649U, 39439U, 50164U, 15454U, 45903U, 27808U, |
| 15492 | 46171U, 28164U, 27986U, 28342U, 39326U, 50030U, 5957U, 45827U, |
| 15493 | 27716U, 46095U, 28072U, 27898U, 28254U, 38983U, 49627U, 9617U, |
| 15494 | 45865U, 27762U, 46133U, 28118U, 27942U, 28298U, 39160U, 49834U, |
| 15495 | 21539U, 45941U, 27854U, 46209U, 28210U, 28030U, 28386U, 39535U, |
| 15496 | 50278U, 12042U, 39307U, 50008U, 8455U, 39087U, 49749U, 2527U, |
| 15497 | 38964U, 49605U, 8442U, 39066U, 49725U, 19423U, 39517U, 50257U, |
| 15498 | 8468U, 39108U, 49773U, 46702U, 46305U, 38794U, 49408U, 46639U, |
| 15499 | 46245U, 38766U, 49377U, 46765U, 46365U, 38822U, 49439U, 11955U, |
| 15500 | 45193U, 26994U, 25530U, 2448U, 44803U, 26528U, 25178U, 19345U, |
| 15501 | 45531U, 27456U, 25876U, 15538U, 45383U, 27268U, 25692U, 6031U, |
| 15502 | 44993U, 26802U, 25340U, 11835U, 39192U, 49872U, 2338U, 38849U, |
| 15503 | 49469U, 19230U, 39409U, 50128U, 11877U, 39256U, 49948U, 2370U, |
| 15504 | 38913U, 49545U, 19267U, 39469U, 50200U, 15480U, 45323U, 38316U, |
| 15505 | 48867U, 39358U, 50068U, 5973U, 44933U, 38272U, 48817U, 39015U, |
| 15506 | 49665U, 21562U, 45653U, 38360U, 48917U, 39565U, 50314U, 12053U, |
| 15507 | 45289U, 27114U, 25614U, 2538U, 44899U, 26648U, 25262U, 19433U, |
| 15508 | 45621U, 27570U, 25954U, 15625U, 46723U, 46325U, 28476U, 25776U, |
| 15509 | 6118U, 46660U, 46265U, 28428U, 25424U, 21646U, 46785U, 46384U, |
| 15510 | 28524U, 26026U, 11975U, 45225U, 27034U, 25558U, 2468U, 44835U, |
| 15511 | 26568U, 25206U, 19363U, 45561U, 27494U, 25902U, 15558U, 45415U, |
| 15512 | 27308U, 25720U, 6051U, 45025U, 26842U, 25368U, 11893U, 45137U, |
| 15513 | 26922U, 25454U, 2386U, 44747U, 26456U, 25102U, 19281U, 45479U, |
| 15514 | 27388U, 25806U, 15496U, 27156U, 25644U, 46490U, 28654U, 5989U, |
| 15515 | 26690U, 25292U, 46422U, 28570U, 21576U, 27610U, 25982U, 46558U, |
| 15516 | 28738U, 12064U, 45306U, 27135U, 25629U, 2549U, 44916U, 26669U, |
| 15517 | 25277U, 19443U, 45637U, 27590U, 25968U, 15636U, 46744U, 46345U, |
| 15518 | 28500U, 25791U, 6129U, 46681U, 46285U, 28452U, 25439U, 21656U, |
| 15519 | 46805U, 46403U, 28547U, 26040U, 11995U, 45257U, 27074U, 25586U, |
| 15520 | 2488U, 44867U, 26608U, 25234U, 19381U, 45591U, 27532U, 25928U, |
| 15521 | 15578U, 45447U, 27348U, 25748U, 6071U, 45057U, 26882U, 25396U, |
| 15522 | 11919U, 45165U, 26958U, 25478U, 2412U, 44775U, 26492U, 25126U, |
| 15523 | 19304U, 45505U, 27422U, 25828U, 15522U, 27192U, 25668U, 46524U, |
| 15524 | 28696U, 6015U, 26726U, 25316U, 46456U, 28612U, 21599U, 27644U, |
| 15525 | 26004U, 46590U, 28778U, 26266U, 23381U, 26100U, 23446U, 26350U, |
| 15526 | 23462U, 26206U, 28843U, 30542U, 34254U, 41534U, 51951U, 40858U, |
| 15527 | 41568U, 51987U, 40892U, 41434U, 51845U, 40758U, 41478U, 51891U, |
| 15528 | 40802U, 41410U, 51554U, 40484U, 41508U, 51923U, 40832U, 31734U, |
| 15529 | 8410U, 31974U, 8419U, 40071U, 47679U, 40295U, 47903U, 19905U, |
| 15530 | 3925U, 13413U, 5184U, 14633U, 20757U, 20152U, 4254U, 13742U, |
| 15531 | 5563U, 15012U, 21020U, 40002U, 47610U, 40226U, 47834U, 19860U, |
| 15532 | 3840U, 13328U, 5115U, 14564U, 20679U, 20107U, 4169U, 13657U, |
| 15533 | 5494U, 14943U, 20942U, 24401U, 30217U, 3936U, 13424U, 4265U, |
| 15534 | 13753U, 9124U, 4958U, 14407U, 9374U, 5337U, 14786U, 33854U, |
| 15535 | 39919U, 47534U, 40143U, 47751U, 40078U, 47686U, 40302U, 47910U, |
| 15536 | 3505U, 12993U, 4717U, 14166U, 19467U, 3118U, 12606U, 4389U, |
| 15537 | 13877U, 20231U, 28921U, 30622U, 3964U, 13452U, 4293U, 13781U, |
| 15538 | 9244U, 5091U, 14540U, 9494U, 5470U, 14919U, 34426U, 40023U, |
| 15539 | 47631U, 40247U, 47855U, 40096U, 47704U, 40320U, 47928U, 3637U, |
| 15540 | 13125U, 4804U, 14253U, 19579U, 3406U, 12894U, 4605U, 14054U, |
| 15541 | 20434U, 23538U, 29102U, 33771U, 30819U, 33391U, 9256U, 5103U, |
| 15542 | 14552U, 9506U, 5482U, 14931U, 3354U, 12842U, 20387U, 30586U, |
| 15543 | 28865U, 34298U, 34320U, 34643U, 33815U, 33793U, 19612U, 8643U, |
| 15544 | 2590U, 3426U, 9018U, 2690U, 12914U, 4638U, 14087U, 20452U, |
| 15545 | 34276U, 34135U, 34593U, 24348U, 35672U, 8397U, 24287U, 24746U, |
| 15546 | 48U, 94U, 8357U, 33U, 33755U, 33810U, 34122U, 34581U, |
| 15547 | 24337U, 35660U, 8384U, 24269U, 24735U, 25U, 33746U, 24803U, |
| 15548 | 30401U, 9608U, 21518U, 3950U, 13438U, 4279U, 13767U, 9232U, |
| 15549 | 5079U, 14528U, 9482U, 5458U, 14907U, 34054U, 39995U, 47603U, |
| 15550 | 40219U, 47827U, 40367U, 47937U, 40087U, 47695U, 40311U, 47919U, |
| 15551 | 3625U, 13113U, 4792U, 14241U, 19528U, 3234U, 12722U, 4544U, |
| 15552 | 13993U, 20286U, 38064U, 47440U, 3344U, 12832U, 4554U, 14003U, |
| 15553 | 24699U, 30344U, 33984U, 47324U, 39988U, 40212U, 47820U, 37984U, |
| 15554 | 47360U, 37957U, 47333U, 38009U, 47385U, 24386U, 30210U, 33847U, |
| 15555 | 28906U, 30615U, 34419U, 24796U, 30378U, 34047U, 38058U, 47434U, |
| 15556 | 38098U, 3468U, 12956U, 4680U, 14129U, 47464U, 19786U, 3766U, |
| 15557 | 13254U, 4945U, 14394U, 20611U, 20033U, 4095U, 13583U, 5324U, |
| 15558 | 14773U, 20874U, 19799U, 3779U, 13267U, 4994U, 14443U, 20623U, |
| 15559 | 20046U, 4108U, 13596U, 5373U, 14822U, 20886U, 41049U, 41623U, |
| 15560 | 15127U, 5667U, 21163U, 41403U, 41977U, 16149U, 6668U, 22101U, |
| 15561 | 17250U, 7870U, 22958U, 41226U, 41800U, 15926U, 6455U, 21925U, |
| 15562 | 17069U, 7699U, 22806U, 19548U, 3375U, 12863U, 4574U, 14023U, |
| 15563 | 20406U, 19763U, 8725U, 3743U, 9100U, 13231U, 4910U, 14359U, |
| 15564 | 20590U, 20010U, 8843U, 4072U, 9350U, 13560U, 5289U, 14738U, |
| 15565 | 20853U, 3580U, 13068U, 8979U, 4505U, 3610U, 13098U, 9005U, |
| 15566 | 4531U, 3533U, 13021U, 4745U, 14194U, 3173U, 12661U, 4444U, |
| 15567 | 13932U, 3595U, 13083U, 8992U, 4518U, 4320U, 13808U, 21042U, |
| 15568 | 3878U, 13366U, 20714U, 4207U, 13695U, 20977U, 19497U, 3148U, |
| 15569 | 12636U, 4419U, 13907U, 20258U, 3517U, 13005U, 4729U, 14178U, |
| 15570 | 3159U, 12647U, 4430U, 13918U, 3564U, 13052U, 4776U, 14225U, |
| 15571 | 3200U, 12688U, 4471U, 13959U, 3548U, 13036U, 4760U, 14209U, |
| 15572 | 3186U, 12674U, 4457U, 13945U, 19824U, 8749U, 3804U, 9184U, |
| 15573 | 13292U, 5031U, 14480U, 20646U, 20071U, 8867U, 4133U, 9434U, |
| 15574 | 13621U, 5410U, 14859U, 20909U, 3864U, 13352U, 20701U, 4193U, |
| 15575 | 13681U, 20964U, 3330U, 12818U, 20374U, 19643U, 8664U, 3479U, |
| 15576 | 9039U, 12967U, 4691U, 14140U, 20480U, 20163U, 8926U, 4307U, |
| 15577 | 9565U, 13795U, 5574U, 15023U, 21030U, 19812U, 8737U, 3792U, |
| 15578 | 9172U, 13280U, 5019U, 14468U, 20635U, 19656U, 8677U, 3492U, |
| 15579 | 9052U, 12980U, 4704U, 14153U, 20492U, 20059U, 8855U, 4121U, |
| 15580 | 9422U, 13609U, 5398U, 14847U, 20898U, 3851U, 13339U, 20689U, |
| 15581 | 4180U, 13668U, 20952U, 3317U, 12805U, 20362U, 19715U, 8713U, |
| 15582 | 3695U, 9088U, 13183U, 4862U, 14311U, 20546U, 19962U, 8831U, |
| 15583 | 4024U, 9338U, 13512U, 5241U, 14690U, 20809U, 3269U, 12757U, |
| 15584 | 20318U, 38029U, 39969U, 47584U, 40193U, 47801U, 47405U, 40037U, |
| 15585 | 47645U, 40261U, 47869U, 19318U, 21613U, 11867U, 19258U, 15470U, |
| 15586 | 21553U, 11909U, 2402U, 19295U, 15512U, 6005U, 21590U, 19738U, |
| 15587 | 3718U, 13206U, 4885U, 14334U, 20567U, 19985U, 4047U, 13535U, |
| 15588 | 5264U, 14713U, 20830U, 24509U, 30236U, 41056U, 41630U, 41233U, |
| 15589 | 41807U, 33873U, 24849U, 30438U, 41096U, 41670U, 41273U, 41847U, |
| 15590 | 34106U, 24963U, 30462U, 41106U, 41680U, 41283U, 41857U, 34114U, |
| 15591 | 25094U, 30518U, 41116U, 41690U, 41293U, 41867U, 34222U, 28873U, |
| 15592 | 30564U, 34306U, 29144U, 30861U, 41126U, 41700U, 41303U, 41877U, |
| 15593 | 34649U, 29183U, 30900U, 41136U, 41710U, 41313U, 41887U, 34688U, |
| 15594 | 19837U, 8762U, 3817U, 9197U, 13305U, 5044U, 14493U, 20658U, |
| 15595 | 20084U, 8880U, 4146U, 9447U, 13634U, 5423U, 14872U, 20921U, |
| 15596 | 3294U, 12782U, 20341U, 19871U, 8785U, 3891U, 9268U, 13379U, |
| 15597 | 5126U, 14575U, 20726U, 20118U, 8903U, 4220U, 9518U, 13708U, |
| 15598 | 5505U, 14954U, 20989U, 38037U, 39978U, 47593U, 40202U, 47810U, |
| 15599 | 47413U, 40046U, 47654U, 40270U, 47878U, 19680U, 8690U, 3660U, |
| 15600 | 9065U, 13148U, 4827U, 14276U, 20514U, 19927U, 8808U, 3989U, |
| 15601 | 9315U, 13477U, 5206U, 14655U, 20777U, 3244U, 12732U, 20295U, |
| 15602 | 24840U, 34097U, 29003U, 30953U, 33067U, 31041U, 28818U, 30526U, |
| 15603 | 34230U, 24684U, 30329U, 33937U, 28987U, 30732U, 34542U, 28979U, |
| 15604 | 30724U, 34469U, 15200U, 5750U, 21299U, 15179U, 5719U, 21280U, |
| 15605 | 9220U, 5067U, 14516U, 9470U, 5446U, 14895U, 19632U, 8653U, |
| 15606 | 3457U, 9028U, 12945U, 4669U, 14118U, 20470U, 19849U, 8774U, |
| 15607 | 3829U, 9209U, 13317U, 5056U, 14505U, 20669U, 20096U, 8892U, |
| 15608 | 4158U, 9459U, 13646U, 5435U, 14884U, 20932U, 3306U, 12794U, |
| 15609 | 20352U, 19883U, 8797U, 3903U, 9280U, 13391U, 5138U, 14587U, |
| 15610 | 20737U, 20130U, 8915U, 4232U, 9530U, 13720U, 5517U, 14966U, |
| 15611 | 21000U, 25046U, 30470U, 34169U, 25060U, 30484U, 34183U, 19508U, |
| 15612 | 8623U, 3214U, 8959U, 12702U, 4485U, 13973U, 20268U, 25074U, |
| 15613 | 30498U, 34197U, 23524U, 29049U, 30740U, 34550U, 19692U, 8702U, |
| 15614 | 3672U, 9077U, 13160U, 4839U, 14288U, 20525U, 19939U, 8820U, |
| 15615 | 4001U, 9327U, 13489U, 5218U, 14667U, 20788U, 19518U, 8633U, |
| 15616 | 3224U, 8969U, 12712U, 4495U, 13983U, 20277U, 11945U, 25516U, |
| 15617 | 2438U, 25164U, 19336U, 25863U, 45367U, 27248U, 44977U, 26782U, |
| 15618 | 45694U, 27697U, 11859U, 32998U, 45784U, 38517U, 49095U, 39698U, |
| 15619 | 50471U, 34741U, 46052U, 38699U, 49301U, 39832U, 50629U, 39240U, |
| 15620 | 49929U, 2362U, 32962U, 45724U, 38425U, 48991U, 39630U, 50391U, |
| 15621 | 34705U, 45992U, 38607U, 49197U, 39764U, 50549U, 38897U, 49526U, |
| 15622 | 8595U, 32980U, 45754U, 38471U, 49043U, 39664U, 50431U, 34723U, |
| 15623 | 46022U, 38653U, 49249U, 39798U, 50589U, 39144U, 49815U, 19251U, |
| 15624 | 33015U, 45813U, 38562U, 49146U, 39731U, 50510U, 34758U, 46081U, |
| 15625 | 38744U, 49352U, 39865U, 50668U, 39454U, 50182U, 15462U, 45922U, |
| 15626 | 27831U, 46190U, 28187U, 28008U, 28364U, 39342U, 50049U, 5965U, |
| 15627 | 45846U, 27739U, 46114U, 28095U, 27920U, 28276U, 38999U, 49646U, |
| 15628 | 9625U, 45884U, 27785U, 46152U, 28141U, 27964U, 28320U, 39176U, |
| 15629 | 49853U, 21546U, 45959U, 27876U, 46227U, 28232U, 28051U, 28407U, |
| 15630 | 39550U, 50296U, 11965U, 45209U, 27014U, 25544U, 2458U, 44819U, |
| 15631 | 26548U, 25192U, 19354U, 45546U, 27475U, 25889U, 15548U, 45399U, |
| 15632 | 27288U, 25706U, 6041U, 45009U, 26822U, 25354U, 11843U, 39208U, |
| 15633 | 49891U, 2346U, 38865U, 49488U, 19237U, 39424U, 50146U, 11885U, |
| 15634 | 39272U, 49967U, 2378U, 38929U, 49564U, 19274U, 39484U, 50218U, |
| 15635 | 15488U, 45337U, 38338U, 48892U, 39374U, 50087U, 5981U, 44947U, |
| 15636 | 38294U, 48842U, 39031U, 49684U, 21569U, 45666U, 38381U, 48941U, |
| 15637 | 39580U, 50332U, 11985U, 45241U, 27054U, 25572U, 2478U, 44851U, |
| 15638 | 26588U, 25220U, 19372U, 45576U, 27513U, 25915U, 15568U, 45431U, |
| 15639 | 27328U, 25734U, 6061U, 45041U, 26862U, 25382U, 11901U, 45151U, |
| 15640 | 26940U, 25466U, 2394U, 44761U, 26474U, 25114U, 19288U, 45492U, |
| 15641 | 27405U, 25817U, 15504U, 27174U, 25656U, 46507U, 28675U, 5997U, |
| 15642 | 26708U, 25304U, 46439U, 28591U, 21583U, 27627U, 25993U, 46574U, |
| 15643 | 28758U, 12005U, 45273U, 27094U, 25600U, 2498U, 44883U, 26628U, |
| 15644 | 25248U, 19390U, 45606U, 27551U, 25941U, 15588U, 45463U, 27368U, |
| 15645 | 25762U, 6081U, 45073U, 26902U, 25410U, 11927U, 45179U, 26976U, |
| 15646 | 25490U, 2420U, 44789U, 26510U, 25138U, 19311U, 45518U, 27439U, |
| 15647 | 25839U, 15530U, 27210U, 25680U, 46541U, 28717U, 6023U, 26744U, |
| 15648 | 25328U, 46473U, 28633U, 21606U, 27661U, 26015U, 46606U, 28798U, |
| 15649 | 26278U, 23389U, 26112U, 23454U, 26362U, 23470U, 26218U, 28881U, |
| 15650 | 30580U, 34314U, 41551U, 51969U, 40875U, 41584U, 52004U, 40908U, |
| 15651 | 41456U, 51868U, 40780U, 41493U, 51907U, 40817U, 41422U, 51567U, |
| 15652 | 40496U, 41521U, 51937U, 40845U, 24525U, 30280U, 3257U, 12745U, |
| 15653 | 20307U, 9136U, 4970U, 14419U, 9386U, 5349U, 14798U, 33906U, |
| 15654 | 9291U, 5160U, 14609U, 9541U, 5539U, 14988U, 39933U, 47548U, |
| 15655 | 40157U, 47765U, 19477U, 8603U, 3128U, 8939U, 12616U, 4399U, |
| 15656 | 13887U, 20240U, 30961U, 31049U, 38086U, 47452U, 88U, 8302U, |
| 15657 | 8480U, 45089U, 9641U, 45113U, 131U, 8428U, 8494U, 45101U, |
| 15658 | 9647U, 45125U, 24713U, 30350U, 33998U, 28849U, 30548U, 34260U, |
| 15659 | 29160U, 30877U, 34665U, 24789U, 30364U, 34040U, 24728U, 30357U, |
| 15660 | 34013U, 28857U, 30556U, 34268U, 29168U, 30885U, 34673U, 24809U, |
| 15661 | 30407U, 34060U, 12015U, 2508U, 19399U, 15598U, 6091U, 21622U, |
| 15662 | 19602U, 3416U, 12904U, 4628U, 14077U, 20443U, 29010U, 30970U, |
| 15663 | 33074U, 31058U, 25053U, 30477U, 34176U, 25067U, 30491U, 34190U, |
| 15664 | 25081U, 30505U, 34204U, 23531U, 28995U, 30944U, 33059U, 31032U, |
| 15665 | 23516U, 12075U, 19453U, 15647U, 6140U, 21666U, 12023U, 19406U, |
| 15666 | 15606U, 6099U, 21629U, 23357U, 26064U, 23739U, 26312U, 23413U, |
| 15667 | 26146U, 23779U, 26420U, 23366U, 26077U, 23756U, 26337U, 23437U, |
| 15668 | 26182U, 23788U, 26433U, 43567U, 50745U, 51306U, 43589U, 274U, |
| 15669 | 50767U, 51322U, 44207U, 297U, 33176U, 43597U, 50782U, 51336U, |
| 15670 | 43687U, 50853U, 36044U, 30173U, 23578U, 24126U, 30978U, 43207U, |
| 15671 | 48620U, 43187U, 37892U, 48600U, 43575U, 50753U, 51314U, 31075U, |
| 15672 | 36050U, 31118U, 37473U, 32690U, 8308U, 36587U, 31957U, 36819U, |
| 15673 | 43620U, 50948U, 51454U, 43647U, 50813U, 51358U, 46840U, 46880U, |
| 15674 | 46888U, 23569U, 23713U, 30286U, 36284U, 30186U, 36257U, 31276U, |
| 15675 | 24187U, 36249U, 29876U, 29856U, 105U, 8376U, 8486U, 34020U, |
| 15676 | 23810U, 23842U, 43663U, 50829U, 51380U, 35405U, 24326U, 23848U, |
| 15677 | 35203U, 47127U, 47021U, 23351U, 23582U, 36549U, 24047U, 29108U, |
| 15678 | 30825U, 30203U, 35111U, 32381U, 35866U, 29580U, 35057U, 32327U, |
| 15679 | 35722U, 29448U, 35141U, 32411U, 35892U, 29604U, 35085U, 32355U, |
| 15680 | 35783U, 29504U, 23731U, 26300U, 23405U, 26134U, 34942U, 35746U, |
| 15681 | 29470U, 145U, 21105U, 43335U, 51133U, 35805U, 29524U, 21197U, |
| 15682 | 36579U, 24065U, 29126U, 30843U, 35178U, 35829U, 29546U, 185U, |
| 15683 | 21244U, 43365U, 51165U, 34958U, 35770U, 29492U, 165U, 21123U, |
| 15684 | 43345U, 51149U, 35194U, 35853U, 29568U, 205U, 21262U, 43375U, |
| 15685 | 51181U, 35572U, 35916U, 29626U, 225U, 21326U, 43395U, 51204U, |
| 15686 | 29346U, 41002U, 43605U, 50790U, 43702U, 50868U, 33170U, 8350U, |
| 15687 | 33764U, 8368U, 23502U, 34026U, 15222U, 43317U, 15232U, 48755U, |
| 15688 | 41013U, 41027U, 24305U, 8270U, 24311U, 8277U, 33131U, 32072U, |
| 15689 | 38159U, 33140U, 33122U, 32064U, 38147U, 31600U, 43239U, 48652U, |
| 15690 | 51197U, 43628U, 50805U, 51350U, 43679U, 50845U, 51388U, 24092U, |
| 15691 | 31081U, 29862U, 34915U, 23890U, 243U, 21365U, 51218U, 176U, |
| 15692 | 21189U, 43356U, 51158U, 216U, 21272U, 43386U, 51190U, 24623U, |
| 15693 | 9834U, 17740U, 36705U, 24539U, 23954U, 36460U, 24000U, 9777U, |
| 15694 | 17681U, 35208U, 36151U, 9975U, 30709U, 23723U, 36275U, 23397U, |
| 15695 | 36266U, 43671U, 50837U, 36683U, 43543U, 50714U, 51282U, 9853U, |
| 15696 | 17757U, 36720U, 23837U, 43559U, 50737U, 51298U, 36603U, 36183U, |
| 15697 | 31270U, 32108U, 30168U, 9814U, 17722U, 36689U, 36444U, 9757U, |
| 15698 | 17663U, 24175U, 23605U, 34906U, 24393U, 36493U, 31166U, 23614U, |
| 15699 | 34923U, 24757U, 36511U, 23898U, 36008U, 23881U, 35999U, 24029U, |
| 15700 | 36074U, 28913U, 36531U, 24773U, 36521U, 23508U, 33113U, 34032U, |
| 15701 | 33801U, 31665U, 33417U, 24517U, 36502U, 23624U, 34933U, 31512U, |
| 15702 | 23908U, 36018U, 24038U, 36083U, 28971U, 36540U, 23765U, 26374U, |
| 15703 | 23478U, 26230U, 34826U, 9918U, 36475U, 9796U, 17698U, 35126U, |
| 15704 | 32396U, 35879U, 29592U, 35071U, 32341U, 35734U, 29459U, 35155U, |
| 15705 | 32425U, 35904U, 29615U, 35098U, 32368U, 35794U, 29514U, 31594U, |
| 15706 | 23803U, 36571U, 24056U, 29117U, 30834U, 30371U, 23748U, 26325U, |
| 15707 | 23429U, 26170U, 34950U, 35758U, 29481U, 155U, 21114U, 51141U, |
| 15708 | 35817U, 29535U, 21206U, 36595U, 24074U, 29135U, 30852U, 35186U, |
| 15709 | 35841U, 29557U, 195U, 21253U, 51173U, 35611U, 35927U, 29636U, |
| 15710 | 234U, 21334U, 51211U, 33426U, 43551U, 264U, 50722U, 51290U, |
| 15711 | 44196U, 284U, 23589U, 9707U, 30244U, 23928U, 9739U, 30755U, |
| 15712 | 23633U, 30260U, 43655U, 50821U, 51366U, 23875U, 43752U, 50917U, |
| 15713 | 51429U, 35994U, 23563U, 34899U, 36027U, 9862U, 17765U, 36727U, |
| 15714 | 36617U, 29780U, 36197U, 9824U, 17731U, 36697U, 36452U, 9767U, |
| 15715 | 17672U, 31158U, 31174U, 31520U, 9843U, 17748U, 36712U, 36467U, |
| 15716 | 9786U, 17689U, 17714U, 17654U, 34833U, 9927U, 36482U, 9805U, |
| 15717 | 17706U, 23597U, 9717U, 30252U, 23941U, 9748U, 30768U, 34067U, |
| 15718 | 24121U, 50939U, 8515U, 21182U, 32812U, 43246U, 50775U, 43457U, |
| 15719 | 50706U, 33182U, 24921U, 43695U, 50861U, 24083U, 24141U, 35519U, |
| 15720 | 31201U, 48702U, 43324U, 48768U, 36489U, 34148U, 37479U, 36832U, |
| 15721 | 36814U, 52508U, 50687U, 21319U, 48659U, 34211U, 33478U, 35412U, |
| 15722 | 35354U, 47081U, 47106U, 47148U, 23422U, 43155U, 48577U, 43193U, |
| 15723 | 48606U, 23863U, 30688U, 43255U, 43404U, 48675U, 43465U, 43613U, |
| 15724 | 50798U, 43710U, 50876U, 48710U, 21358U, 48762U, 31695U, 32457U, |
| 15725 | 33788U, 24531U, 32771U, 30703U, 36157U, 9983U, 30717U, 33515U, |
| 15726 | 23870U, 24107U, 24926U, 26195U, 43162U, 48584U, 43200U, 48613U, |
| 15727 | 43281U, 48696U, 43473U, 8508U, 21144U, 50730U, 43449U, 24332U, |
| 15728 | 23935U, 30762U, 32632U, 35989U, 29786U, 23948U, 30775U, 77U, |
| 15729 | }; |
| 15730 | |
| 15731 | extern const uint8_t ARMInstrDeprecationFeatures[] = { |
| 15732 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15733 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15734 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15735 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15736 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15737 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15738 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15739 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15740 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15741 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15742 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15743 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15744 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15745 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15746 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15747 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15748 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15749 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15750 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15751 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15752 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15753 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15754 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15755 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15756 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15757 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15758 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15759 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15760 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15761 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15762 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15763 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15764 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15765 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15766 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15767 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15768 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15769 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15770 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15771 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15772 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15773 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15774 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15775 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15776 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15777 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15778 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15779 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15780 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15781 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15782 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15783 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15784 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15785 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15786 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15787 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15788 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15789 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15790 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15791 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15792 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15793 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15794 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15795 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15796 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15797 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15798 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15799 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15800 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15801 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15802 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15803 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15804 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15805 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15806 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15807 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15808 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15809 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15810 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15811 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15812 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15813 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15814 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15815 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15816 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15817 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15818 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15819 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15820 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15821 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15822 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15823 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15824 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15825 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15826 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15827 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15828 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15829 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15830 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15831 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15832 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15833 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15834 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15835 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15836 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15837 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15838 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15839 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15840 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15841 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15842 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15843 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15844 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15845 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15846 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15847 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15848 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15849 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15850 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15851 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15852 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15853 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15854 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15855 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15856 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15857 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15858 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15859 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15860 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15861 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15862 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15863 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15864 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15865 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15866 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15867 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15868 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15869 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15870 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15871 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15872 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15873 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15874 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15875 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15876 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15877 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15878 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15879 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15880 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15881 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15882 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15883 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15884 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15885 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15886 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15887 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15888 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15889 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15890 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15891 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15892 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15893 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15894 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15895 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15896 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15897 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15898 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15899 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15900 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15901 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15902 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15903 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15904 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15905 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15906 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15907 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15908 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15909 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15910 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15911 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15912 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15913 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15914 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15915 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15916 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15917 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15918 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15919 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15920 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15921 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15922 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15923 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15924 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15925 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15926 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15927 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15928 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15929 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15930 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15931 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15932 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15933 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15934 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15935 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15936 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15937 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15938 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15939 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15940 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15941 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15942 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15943 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15944 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15945 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15946 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15947 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15948 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15949 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15950 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15951 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15952 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15953 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15954 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15955 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15956 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15957 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15958 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15959 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15960 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15961 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15962 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15963 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15964 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15965 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15966 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15967 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15968 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), ARM::HasV8Ops, uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15969 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15970 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15971 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15972 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15973 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15974 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15975 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15976 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15977 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15978 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15979 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15980 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15981 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15982 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15983 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15984 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15985 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15986 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15987 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15988 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15989 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15990 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15991 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15992 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15993 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15994 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15995 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15996 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15997 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15998 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15999 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16000 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16001 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16002 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16003 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16004 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16005 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16006 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16007 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16008 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16009 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16010 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16011 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16012 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16013 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16014 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16015 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16016 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16017 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16018 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16019 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16020 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16021 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16022 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16023 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16024 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16025 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16026 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16027 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16028 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16029 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16030 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16031 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16032 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16033 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16034 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16035 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16036 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16037 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16038 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16039 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16040 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16041 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16042 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16043 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16044 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16045 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16046 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16047 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16048 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16049 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16050 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16051 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16052 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16053 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16054 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16055 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16056 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16057 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16058 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16059 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16060 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16061 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16062 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16063 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16064 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16065 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16066 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16067 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16068 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16069 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16070 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16071 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16072 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16073 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16074 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16075 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16076 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16077 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16078 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16079 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16080 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16081 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16082 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16083 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16084 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16085 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16086 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16087 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16088 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16089 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16090 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16091 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16092 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16093 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16094 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16095 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16096 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16097 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16098 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16099 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16100 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16101 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16102 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16103 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16104 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16105 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16106 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16107 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16108 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16109 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16110 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16111 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16112 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16113 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16114 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16115 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16116 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16117 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16118 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16119 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16120 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16121 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16122 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16123 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16124 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16125 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16126 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16127 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16128 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16129 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16130 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16131 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16132 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16133 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16134 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16135 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16136 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16137 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16138 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16139 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16140 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16141 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16142 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16143 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16144 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16145 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16146 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16147 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16148 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16149 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16150 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16151 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16152 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16153 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16154 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16155 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16156 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16157 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16158 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16159 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16160 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16161 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16162 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16163 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16164 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16165 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16166 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16167 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16168 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16169 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16170 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16171 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16172 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16173 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16174 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16175 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16176 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16177 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16178 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16179 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16180 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16181 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16182 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16183 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16184 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16185 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16186 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16187 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16188 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16189 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16190 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16191 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16192 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16193 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16194 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16195 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16196 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16197 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16198 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16199 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16200 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16201 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16202 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16203 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16204 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16205 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16206 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16207 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16208 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16209 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16210 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16211 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16212 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16213 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16214 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16215 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16216 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16217 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16218 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16219 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16220 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16221 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16222 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16223 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16224 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16225 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16226 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16227 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16228 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16229 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16230 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16231 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16232 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16233 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16234 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16235 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16236 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16237 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16238 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16239 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16240 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16241 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16242 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16243 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16244 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16245 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16246 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16247 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16248 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16249 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16250 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16251 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16252 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16253 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16254 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16255 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16256 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16257 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16258 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16259 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16260 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16261 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16262 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16263 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16264 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16265 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16266 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16267 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16268 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16269 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16270 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16271 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16272 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16273 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16274 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16275 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16276 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16277 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16278 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16279 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16280 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16281 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16282 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16283 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16284 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16285 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16286 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16287 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16288 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16289 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16290 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16291 | uint8_t(-1), uint8_t(-1), ARM::HasV8Ops, uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16292 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16293 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16294 | }; |
| 16295 | |
| 16296 | extern const MCInstrInfo::ComplexDeprecationPredicate ARMInstrComplexDeprecationInfos[] = { |
| 16297 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16298 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16299 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16300 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16301 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16302 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16303 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16304 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16305 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16306 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16307 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16308 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16309 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16310 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16311 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16312 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16313 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16314 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16315 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16316 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16317 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16318 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16319 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16320 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16321 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16322 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16323 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16324 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16325 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16326 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16327 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16328 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16329 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16330 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16331 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16332 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16333 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16334 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16335 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16336 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16337 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16338 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16339 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16340 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16341 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16342 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16343 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16344 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16345 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16346 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16347 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16348 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16349 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16350 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16351 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16352 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16353 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16354 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16355 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16356 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16357 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16358 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16359 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16360 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16361 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16362 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16363 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16364 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16365 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16366 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16367 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16368 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16369 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16370 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16371 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16372 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16373 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16374 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16375 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16376 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16377 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16378 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16379 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16380 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16381 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16382 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16383 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16384 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16385 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16386 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16387 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16388 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16389 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16390 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16391 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16392 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16393 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16394 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16395 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16396 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16397 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16398 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16399 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16400 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16401 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16402 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16403 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16404 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16405 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16406 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16407 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16408 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16409 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16410 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16411 | nullptr, nullptr, &getARMLoadDeprecationInfo, &getARMLoadDeprecationInfo, &getARMLoadDeprecationInfo, &getARMLoadDeprecationInfo, &getARMLoadDeprecationInfo, &getARMLoadDeprecationInfo, |
| 16412 | &getARMLoadDeprecationInfo, &getARMLoadDeprecationInfo, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16413 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16414 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16415 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16416 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16417 | nullptr, &getMCRDeprecationInfo, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16418 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, &getMRCDeprecationInfo, |
| 16419 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16420 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16421 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16422 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16423 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16424 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16425 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16426 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16427 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16428 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16429 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16430 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16431 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16432 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16433 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16434 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16435 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16436 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16437 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16438 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16439 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16440 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16441 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16442 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16443 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16444 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16445 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16446 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16447 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16448 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16449 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16450 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16451 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16452 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16453 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16454 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16455 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16456 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16457 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16458 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16459 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16460 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16461 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16462 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16463 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16464 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16465 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16466 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16467 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16468 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16469 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16470 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16471 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16472 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16473 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16474 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16475 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16476 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16477 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16478 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16479 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16480 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16481 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16482 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16483 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16484 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16485 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16486 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16487 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16488 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16489 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16490 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16491 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16492 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16493 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16494 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16495 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16496 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16497 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16498 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16499 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16500 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16501 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16502 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16503 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16504 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16505 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16506 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16507 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16508 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16509 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16510 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16511 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16512 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16513 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16514 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16515 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16516 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16517 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16518 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16519 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16520 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16521 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16522 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16523 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16524 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16525 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16526 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16527 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16528 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16529 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16530 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16531 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16532 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16533 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16534 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16535 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16536 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16537 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16538 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16539 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16540 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16541 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16542 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16543 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16544 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, &getARMStoreDeprecationInfo, |
| 16545 | &getARMStoreDeprecationInfo, &getARMStoreDeprecationInfo, &getARMStoreDeprecationInfo, &getARMStoreDeprecationInfo, &getARMStoreDeprecationInfo, &getARMStoreDeprecationInfo, &getARMStoreDeprecationInfo, nullptr, |
| 16546 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16547 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16548 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16549 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16550 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16551 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16552 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16553 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16554 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16555 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16556 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16557 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16558 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16559 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16560 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16561 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16562 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16563 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16564 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16565 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16566 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16567 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16568 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16569 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16570 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16571 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16572 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16573 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16574 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16575 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16576 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16577 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16578 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16579 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16580 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16581 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16582 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16583 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16584 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16585 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16586 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16587 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16588 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16589 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16590 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16591 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16592 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16593 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16594 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16595 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16596 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16597 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16598 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16599 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16600 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16601 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16602 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16603 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16604 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16605 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16606 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16607 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16608 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16609 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16610 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16611 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16612 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16613 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16614 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16615 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16616 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16617 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16618 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16619 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16620 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16621 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16622 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16623 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16624 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16625 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16626 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16627 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16628 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16629 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16630 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16631 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16632 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16633 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16634 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16635 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16636 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16637 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16638 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16639 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16640 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16641 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16642 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16643 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16644 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16645 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16646 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16647 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16648 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16649 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16650 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16651 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16652 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16653 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16654 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16655 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16656 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16657 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16658 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16659 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16660 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16661 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16662 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16663 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16664 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16665 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16666 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16667 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16668 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16669 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16670 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16671 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16672 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16673 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16674 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16675 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16676 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16677 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16678 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16679 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16680 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16681 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16682 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16683 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16684 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16685 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16686 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16687 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16688 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16689 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16690 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16691 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16692 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16693 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16694 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16695 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16696 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16697 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16698 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16699 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16700 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16701 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16702 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16703 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16704 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16705 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16706 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16707 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16708 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16709 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16710 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16711 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16712 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16713 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16714 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16715 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16716 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16717 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16718 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16719 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16720 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16721 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16722 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16723 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16724 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16725 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16726 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16727 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16728 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16729 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16730 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16731 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16732 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16733 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16734 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16735 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16736 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16737 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16738 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16739 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16740 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16741 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16742 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16743 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16744 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16745 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16746 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16747 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16748 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16749 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16750 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16751 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16752 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16753 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16754 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16755 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16756 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16757 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16758 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16759 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16760 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16761 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16762 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16763 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16764 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16765 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16766 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16767 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16768 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16769 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16770 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16771 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16772 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16773 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16774 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16775 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16776 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16777 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16778 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16779 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16780 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16781 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16782 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16783 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16784 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16785 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16786 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16787 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16788 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16789 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16790 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16791 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16792 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16793 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16794 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16795 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16796 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16797 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16798 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16799 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16800 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16801 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16802 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16803 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16804 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16805 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16806 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16807 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16808 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16809 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16810 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16811 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16812 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16813 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16814 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16815 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16816 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, &getMCRDeprecationInfo, nullptr, |
| 16817 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16818 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16819 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16820 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16821 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16822 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16823 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16824 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16825 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16826 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16827 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16828 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16829 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16830 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16831 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16832 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16833 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16834 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16835 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16836 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16837 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16838 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16839 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16840 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16841 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16842 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16843 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16844 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16845 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16846 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16847 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16848 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16849 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16850 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16851 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16852 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16853 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16854 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16855 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16856 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16857 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16858 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16859 | }; |
| 16860 | |
| 16861 | static inline void InitARMMCInstrInfo(MCInstrInfo *II) { |
| 16862 | II->InitMCInstrInfo(ARMDescs.Insts, ARMInstrNameIndices, ARMInstrNameData, ARMInstrDeprecationFeatures, ARMInstrComplexDeprecationInfos, 4496); |
| 16863 | } |
| 16864 | |
| 16865 | } // end namespace llvm |
| 16866 | #endif // GET_INSTRINFO_MC_DESC |
| 16867 | |
| 16868 | #ifdef GET_INSTRINFO_HEADER |
| 16869 | #undef GET_INSTRINFO_HEADER |
| 16870 | namespace llvm { |
| 16871 | struct ARMGenInstrInfo : public TargetInstrInfo { |
| 16872 | explicit ARMGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); |
| 16873 | ~ARMGenInstrInfo() override = default; |
| 16874 | |
| 16875 | }; |
| 16876 | } // end namespace llvm |
| 16877 | #endif // GET_INSTRINFO_HEADER |
| 16878 | |
| 16879 | #ifdef GET_INSTRINFO_HELPER_DECLS |
| 16880 | #undef GET_INSTRINFO_HELPER_DECLS |
| 16881 | |
| 16882 | |
| 16883 | #endif // GET_INSTRINFO_HELPER_DECLS |
| 16884 | |
| 16885 | #ifdef GET_INSTRINFO_HELPERS |
| 16886 | #undef GET_INSTRINFO_HELPERS |
| 16887 | |
| 16888 | #endif // GET_INSTRINFO_HELPERS |
| 16889 | |
| 16890 | #ifdef GET_INSTRINFO_CTOR_DTOR |
| 16891 | #undef GET_INSTRINFO_CTOR_DTOR |
| 16892 | namespace llvm { |
| 16893 | extern const ARMInstrTable ARMDescs; |
| 16894 | extern const unsigned ARMInstrNameIndices[]; |
| 16895 | extern const char ARMInstrNameData[]; |
| 16896 | extern const uint8_t ARMInstrDeprecationFeatures[]; |
| 16897 | extern const MCInstrInfo::ComplexDeprecationPredicate ARMInstrComplexDeprecationInfos[]; |
| 16898 | ARMGenInstrInfo::ARMGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) |
| 16899 | : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { |
| 16900 | InitMCInstrInfo(ARMDescs.Insts, ARMInstrNameIndices, ARMInstrNameData, ARMInstrDeprecationFeatures, ARMInstrComplexDeprecationInfos, 4496); |
| 16901 | } |
| 16902 | } // end namespace llvm |
| 16903 | #endif // GET_INSTRINFO_CTOR_DTOR |
| 16904 | |
| 16905 | #ifdef GET_INSTRINFO_OPERAND_ENUM |
| 16906 | #undef GET_INSTRINFO_OPERAND_ENUM |
| 16907 | namespace llvm { |
| 16908 | namespace ARM { |
| 16909 | namespace OpName { |
| 16910 | enum { |
| 16911 | OPERAND_LAST |
| 16912 | }; |
| 16913 | } // end namespace OpName |
| 16914 | } // end namespace ARM |
| 16915 | } // end namespace llvm |
| 16916 | #endif //GET_INSTRINFO_OPERAND_ENUM |
| 16917 | |
| 16918 | #ifdef GET_INSTRINFO_NAMED_OPS |
| 16919 | #undef GET_INSTRINFO_NAMED_OPS |
| 16920 | namespace llvm { |
| 16921 | namespace ARM { |
| 16922 | LLVM_READONLY |
| 16923 | int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { |
| 16924 | return -1; |
| 16925 | } |
| 16926 | } // end namespace ARM |
| 16927 | } // end namespace llvm |
| 16928 | #endif //GET_INSTRINFO_NAMED_OPS |
| 16929 | |
| 16930 | #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM |
| 16931 | #undef GET_INSTRINFO_OPERAND_TYPES_ENUM |
| 16932 | namespace llvm { |
| 16933 | namespace ARM { |
| 16934 | namespace OpTypes { |
| 16935 | enum OperandType { |
| 16936 | MVEPairVectorIndex0 = 0, |
| 16937 | MVEPairVectorIndex2 = 1, |
| 16938 | MVE_VIDUP_imm = 2, |
| 16939 | VecListFourDByteIndexed = 3, |
| 16940 | VecListFourDHWordIndexed = 4, |
| 16941 | VecListFourDWordIndexed = 5, |
| 16942 | VecListFourQHWordIndexed = 6, |
| 16943 | VecListFourQWordIndexed = 7, |
| 16944 | VecListOneDByteIndexed = 8, |
| 16945 | VecListOneDHWordIndexed = 9, |
| 16946 | VecListOneDWordIndexed = 10, |
| 16947 | VecListThreeDByteIndexed = 11, |
| 16948 | VecListThreeDHWordIndexed = 12, |
| 16949 | VecListThreeDWordIndexed = 13, |
| 16950 | VecListThreeQHWordIndexed = 14, |
| 16951 | VecListThreeQWordIndexed = 15, |
| 16952 | VecListTwoDByteIndexed = 16, |
| 16953 | VecListTwoDHWordIndexed = 17, |
| 16954 | VecListTwoDWordIndexed = 18, |
| 16955 | VecListTwoQHWordIndexed = 19, |
| 16956 | VecListTwoQWordIndexed = 20, |
| 16957 | VectorIndex8 = 21, |
| 16958 | VectorIndex16 = 22, |
| 16959 | VectorIndex32 = 23, |
| 16960 | VectorIndex64 = 24, |
| 16961 | addr_offset_none = 25, |
| 16962 | addrmode3 = 26, |
| 16963 | addrmode3_pre = 27, |
| 16964 | addrmode5 = 28, |
| 16965 | addrmode5_pre = 29, |
| 16966 | addrmode5fp16 = 30, |
| 16967 | addrmode6 = 31, |
| 16968 | addrmode6align16 = 32, |
| 16969 | addrmode6align32 = 33, |
| 16970 | addrmode6align64 = 34, |
| 16971 | addrmode6align64or128 = 35, |
| 16972 | addrmode6align64or128or256 = 36, |
| 16973 | addrmode6alignNone = 37, |
| 16974 | addrmode6dup = 38, |
| 16975 | addrmode6dupalign16 = 39, |
| 16976 | addrmode6dupalign32 = 40, |
| 16977 | addrmode6dupalign64 = 41, |
| 16978 | addrmode6dupalign64or128 = 42, |
| 16979 | addrmode6dupalignNone = 43, |
| 16980 | addrmode6oneL32 = 44, |
| 16981 | addrmode_imm12 = 45, |
| 16982 | addrmode_imm12_pre = 46, |
| 16983 | addrmode_tbb = 47, |
| 16984 | addrmode_tbh = 48, |
| 16985 | addrmodepc = 49, |
| 16986 | adrlabel = 50, |
| 16987 | am2offset_imm = 51, |
| 16988 | am2offset_reg = 52, |
| 16989 | am3offset = 53, |
| 16990 | am6offset = 54, |
| 16991 | arm_bl_target = 87, |
| 16992 | arm_blx_target = 88, |
| 16993 | arm_br_target = 89, |
| 16994 | banked_reg = 90, |
| 16995 | bf_inv_mask_imm = 91, |
| 16996 | bfafter_target = 92, |
| 16997 | bflabel_s12 = 93, |
| 16998 | bflabel_s16 = 94, |
| 16999 | bflabel_s18 = 95, |
| 17000 | bflabel_u4 = 96, |
| 17001 | brtarget = 97, |
| 17002 | c_imm = 98, |
| 17003 | cc_out = 99, |
| 17004 | cmovpred = 100, |
| 17005 | complexrotateop = 101, |
| 17006 | complexrotateopodd = 102, |
| 17007 | const_pool_asm_imm = 103, |
| 17008 | coproc_option_imm = 104, |
| 17009 | cpinst_operand = 105, |
| 17010 | dpr_reglist = 106, |
| 17011 | f32imm = 107, |
| 17012 | f64imm = 108, |
| 17013 | fbits16 = 109, |
| 17014 | fbits32 = 110, |
| 17015 | fp_dreglist_with_vpr = 111, |
| 17016 | fp_sreglist_with_vpr = 112, |
| 17017 | i1imm = 113, |
| 17018 | i8imm = 114, |
| 17019 | i16imm = 115, |
| 17020 | i32imm = 116, |
| 17021 | i64imm = 117, |
| 17022 | iflags_op = 118, |
| 17023 | imm0_1 = 119, |
| 17024 | imm0_3 = 120, |
| 17025 | imm0_7 = 121, |
| 17026 | imm0_15 = 122, |
| 17027 | imm0_31 = 123, |
| 17028 | imm0_32 = 124, |
| 17029 | imm0_63 = 125, |
| 17030 | imm0_239 = 126, |
| 17031 | imm0_255 = 127, |
| 17032 | imm0_255_expr = 128, |
| 17033 | imm0_4095 = 129, |
| 17034 | imm0_4095_neg = 130, |
| 17035 | imm0_65535 = 131, |
| 17036 | imm0_65535_expr = 132, |
| 17037 | imm0_65535_neg = 133, |
| 17038 | imm1_7 = 134, |
| 17039 | imm1_15 = 135, |
| 17040 | imm1_16 = 136, |
| 17041 | imm1_31 = 137, |
| 17042 | imm1_32 = 138, |
| 17043 | imm8 = 139, |
| 17044 | imm8_255 = 140, |
| 17045 | imm16 = 141, |
| 17046 | imm24b = 142, |
| 17047 | imm32 = 143, |
| 17048 | imm256_65535_expr = 144, |
| 17049 | imm_3b = 145, |
| 17050 | imm_4b = 146, |
| 17051 | imm_6b = 147, |
| 17052 | imm_7b = 148, |
| 17053 | imm_9b = 149, |
| 17054 | imm_11b = 150, |
| 17055 | imm_12b = 151, |
| 17056 | imm_13b = 152, |
| 17057 | imm_sr = 153, |
| 17058 | imod_op = 154, |
| 17059 | instsyncb_opt = 155, |
| 17060 | it_mask = 156, |
| 17061 | it_pred = 157, |
| 17062 | ldst_so_reg = 158, |
| 17063 | ldstm_mode = 159, |
| 17064 | lelabel_u11 = 160, |
| 17065 | long_shift = 161, |
| 17066 | memb_opt = 162, |
| 17067 | mod_imm = 163, |
| 17068 | mod_imm1_7_neg = 164, |
| 17069 | mod_imm8_255_neg = 165, |
| 17070 | mod_imm_neg = 166, |
| 17071 | mod_imm_not = 167, |
| 17072 | msr_mask = 168, |
| 17073 | mve_shift_imm1_7 = 169, |
| 17074 | mve_shift_imm1_15 = 170, |
| 17075 | nImmSplatI8 = 171, |
| 17076 | nImmSplatI16 = 172, |
| 17077 | nImmSplatI32 = 173, |
| 17078 | nImmSplatI64 = 174, |
| 17079 | nImmSplatNotI16 = 175, |
| 17080 | nImmSplatNotI32 = 176, |
| 17081 | nImmVMOVF32 = 177, |
| 17082 | nImmVMOVI32 = 178, |
| 17083 | nImmVMOVI32Neg = 179, |
| 17084 | nModImm = 180, |
| 17085 | neon_vcvt_imm32 = 181, |
| 17086 | nohash_imm = 182, |
| 17087 | p_imm = 183, |
| 17088 | pclabel = 184, |
| 17089 | pkh_asr_amt = 185, |
| 17090 | pkh_lsl_amt = 186, |
| 17091 | postidx_imm8 = 187, |
| 17092 | postidx_imm8s4 = 188, |
| 17093 | postidx_reg = 189, |
| 17094 | pred = 190, |
| 17095 | pred_basic_fp = 191, |
| 17096 | pred_basic_i = 192, |
| 17097 | pred_basic_s = 193, |
| 17098 | pred_basic_u = 194, |
| 17099 | pred_noal = 195, |
| 17100 | pred_noal_inv = 196, |
| 17101 | ptype0 = 197, |
| 17102 | ptype1 = 198, |
| 17103 | ptype2 = 199, |
| 17104 | ptype3 = 200, |
| 17105 | ptype4 = 201, |
| 17106 | ptype5 = 202, |
| 17107 | reglist = 203, |
| 17108 | reglist_with_apsr = 204, |
| 17109 | rot_imm = 205, |
| 17110 | s_cc_out = 206, |
| 17111 | saturateop = 207, |
| 17112 | setend_op = 208, |
| 17113 | shift_imm = 209, |
| 17114 | shift_so_reg_imm = 210, |
| 17115 | shift_so_reg_reg = 211, |
| 17116 | shr_imm8 = 212, |
| 17117 | shr_imm16 = 213, |
| 17118 | shr_imm32 = 214, |
| 17119 | shr_imm64 = 215, |
| 17120 | so_reg_imm = 216, |
| 17121 | so_reg_reg = 217, |
| 17122 | spr_reglist = 218, |
| 17123 | t2_addr_offset_none = 219, |
| 17124 | t2_nosp_addr_offset_none = 220, |
| 17125 | t2_shift_imm = 221, |
| 17126 | t2_so_imm = 222, |
| 17127 | t2_so_imm_neg = 223, |
| 17128 | t2_so_imm_not = 224, |
| 17129 | t2_so_imm_notSext = 225, |
| 17130 | t2_so_reg = 226, |
| 17131 | t2_so_reg_oneuse = 227, |
| 17132 | t2addrmode_imm0_1020s4 = 228, |
| 17133 | t2addrmode_imm7s4 = 229, |
| 17134 | t2addrmode_imm7s4_pre = 230, |
| 17135 | t2addrmode_imm8 = 231, |
| 17136 | t2addrmode_imm8_pre = 232, |
| 17137 | t2addrmode_imm8s4 = 233, |
| 17138 | t2addrmode_imm8s4_pre = 234, |
| 17139 | t2addrmode_imm12 = 235, |
| 17140 | t2addrmode_negimm8 = 236, |
| 17141 | t2addrmode_posimm8 = 237, |
| 17142 | t2addrmode_so_reg = 238, |
| 17143 | t2adrlabel = 239, |
| 17144 | t2am_imm7s4_offset = 240, |
| 17145 | t2am_imm8_offset = 241, |
| 17146 | t2am_imm8s4_offset = 242, |
| 17147 | t2ldr_pcrel_imm12 = 243, |
| 17148 | t2ldrlabel = 244, |
| 17149 | t_addr_offset_none = 245, |
| 17150 | t_addrmode_is1 = 246, |
| 17151 | t_addrmode_is2 = 247, |
| 17152 | t_addrmode_is4 = 248, |
| 17153 | t_addrmode_pc = 249, |
| 17154 | t_addrmode_rr = 250, |
| 17155 | t_addrmode_rr_sext = 251, |
| 17156 | t_addrmode_rrs1 = 252, |
| 17157 | t_addrmode_rrs2 = 253, |
| 17158 | t_addrmode_rrs4 = 254, |
| 17159 | t_addrmode_sp = 255, |
| 17160 | t_adrlabel = 256, |
| 17161 | t_brtarget = 257, |
| 17162 | t_imm0_508s4 = 258, |
| 17163 | t_imm0_508s4_neg = 259, |
| 17164 | t_imm0_1020s4 = 260, |
| 17165 | thumb_bcc_target = 261, |
| 17166 | thumb_bl_target = 262, |
| 17167 | thumb_blx_target = 263, |
| 17168 | thumb_br_target = 264, |
| 17169 | thumb_cb_target = 265, |
| 17170 | tsb_opt = 266, |
| 17171 | type0 = 267, |
| 17172 | type1 = 268, |
| 17173 | type2 = 269, |
| 17174 | type3 = 270, |
| 17175 | type4 = 271, |
| 17176 | type5 = 272, |
| 17177 | untyped_imm_0 = 273, |
| 17178 | vfp_f16imm = 274, |
| 17179 | vfp_f32imm = 275, |
| 17180 | vfp_f64imm = 276, |
| 17181 | vpred_n = 277, |
| 17182 | vpred_r = 278, |
| 17183 | vpt_mask = 279, |
| 17184 | wlslabel_u11 = 280, |
| 17185 | CDEDualRegOp = 281, |
| 17186 | GPRPairOp = 282, |
| 17187 | VecList2Q = 283, |
| 17188 | VecList4Q = 284, |
| 17189 | VecListDPair = 285, |
| 17190 | VecListDPairAllLanes = 286, |
| 17191 | VecListDPairSpaced = 287, |
| 17192 | VecListDPairSpacedAllLanes = 288, |
| 17193 | VecListFourD = 289, |
| 17194 | VecListFourDAllLanes = 290, |
| 17195 | VecListFourQ = 291, |
| 17196 | VecListFourQAllLanes = 292, |
| 17197 | VecListOneD = 293, |
| 17198 | VecListOneDAllLanes = 294, |
| 17199 | VecListThreeD = 295, |
| 17200 | VecListThreeDAllLanes = 296, |
| 17201 | VecListThreeQ = 297, |
| 17202 | VecListThreeQAllLanes = 298, |
| 17203 | CCR = 299, |
| 17204 | DPR = 300, |
| 17205 | DPR_8 = 301, |
| 17206 | DPR_VFP2 = 302, |
| 17207 | DPair = 303, |
| 17208 | DPairSpc = 304, |
| 17209 | DQuad = 305, |
| 17210 | DQuadSpc = 306, |
| 17211 | DTriple = 307, |
| 17212 | DTripleSpc = 308, |
| 17213 | FPCXTRegs = 309, |
| 17214 | FPWithVPR = 310, |
| 17215 | GPR = 311, |
| 17216 | GPRPair = 312, |
| 17217 | GPRPairnosp = 313, |
| 17218 | GPRlr = 314, |
| 17219 | GPRnoip = 315, |
| 17220 | GPRnopc = 316, |
| 17221 | GPRnosp = 317, |
| 17222 | GPRsp = 318, |
| 17223 | GPRwithAPSR = 319, |
| 17224 | GPRwithAPSR_NZCVnosp = 320, |
| 17225 | GPRwithAPSRnosp = 321, |
| 17226 | GPRwithZR = 322, |
| 17227 | GPRwithZRnosp = 323, |
| 17228 | HPR = 324, |
| 17229 | MQPR = 325, |
| 17230 | MQQPR = 326, |
| 17231 | MQQQQPR = 327, |
| 17232 | QPR = 328, |
| 17233 | QPR_8 = 329, |
| 17234 | QPR_VFP2 = 330, |
| 17235 | QQPR = 331, |
| 17236 | QQQQPR = 332, |
| 17237 | SPR = 333, |
| 17238 | SPR_8 = 334, |
| 17239 | VCCR = 335, |
| 17240 | cl_FPSCR_NZCV = 336, |
| 17241 | hGPR = 337, |
| 17242 | rGPR = 338, |
| 17243 | tGPR = 339, |
| 17244 | tGPREven = 340, |
| 17245 | tGPROdd = 341, |
| 17246 | tGPRwithpc = 342, |
| 17247 | tcGPR = 343, |
| 17248 | tcGPRnotr12 = 344, |
| 17249 | OPERAND_TYPE_LIST_END |
| 17250 | }; |
| 17251 | } // end namespace OpTypes |
| 17252 | } // end namespace ARM |
| 17253 | } // end namespace llvm |
| 17254 | #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM |
| 17255 | |
| 17256 | #ifdef GET_INSTRINFO_OPERAND_TYPE |
| 17257 | #undef GET_INSTRINFO_OPERAND_TYPE |
| 17258 | namespace llvm { |
| 17259 | namespace ARM { |
| 17260 | LLVM_READONLY |
| 17261 | static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { |
| 17262 | static const uint16_t Offsets[] = { |
| 17263 | /* PHI */ |
| 17264 | 0, |
| 17265 | /* INLINEASM */ |
| 17266 | 1, |
| 17267 | /* INLINEASM_BR */ |
| 17268 | 1, |
| 17269 | /* CFI_INSTRUCTION */ |
| 17270 | 1, |
| 17271 | /* EH_LABEL */ |
| 17272 | 2, |
| 17273 | /* GC_LABEL */ |
| 17274 | 3, |
| 17275 | /* ANNOTATION_LABEL */ |
| 17276 | 4, |
| 17277 | /* KILL */ |
| 17278 | 5, |
| 17279 | /* EXTRACT_SUBREG */ |
| 17280 | 5, |
| 17281 | /* INSERT_SUBREG */ |
| 17282 | 8, |
| 17283 | /* IMPLICIT_DEF */ |
| 17284 | 12, |
| 17285 | /* SUBREG_TO_REG */ |
| 17286 | 13, |
| 17287 | /* COPY_TO_REGCLASS */ |
| 17288 | 17, |
| 17289 | /* DBG_VALUE */ |
| 17290 | 20, |
| 17291 | /* DBG_VALUE_LIST */ |
| 17292 | 20, |
| 17293 | /* DBG_INSTR_REF */ |
| 17294 | 20, |
| 17295 | /* DBG_PHI */ |
| 17296 | 20, |
| 17297 | /* DBG_LABEL */ |
| 17298 | 20, |
| 17299 | /* REG_SEQUENCE */ |
| 17300 | 21, |
| 17301 | /* COPY */ |
| 17302 | 23, |
| 17303 | /* BUNDLE */ |
| 17304 | 25, |
| 17305 | /* LIFETIME_START */ |
| 17306 | 25, |
| 17307 | /* LIFETIME_END */ |
| 17308 | 26, |
| 17309 | /* PSEUDO_PROBE */ |
| 17310 | 27, |
| 17311 | /* ARITH_FENCE */ |
| 17312 | 31, |
| 17313 | /* STACKMAP */ |
| 17314 | 33, |
| 17315 | /* FENTRY_CALL */ |
| 17316 | 35, |
| 17317 | /* PATCHPOINT */ |
| 17318 | 35, |
| 17319 | /* LOAD_STACK_GUARD */ |
| 17320 | 41, |
| 17321 | /* PREALLOCATED_SETUP */ |
| 17322 | 42, |
| 17323 | /* PREALLOCATED_ARG */ |
| 17324 | 43, |
| 17325 | /* STATEPOINT */ |
| 17326 | 46, |
| 17327 | /* LOCAL_ESCAPE */ |
| 17328 | 46, |
| 17329 | /* FAULTING_OP */ |
| 17330 | 48, |
| 17331 | /* PATCHABLE_OP */ |
| 17332 | 49, |
| 17333 | /* PATCHABLE_FUNCTION_ENTER */ |
| 17334 | 49, |
| 17335 | /* PATCHABLE_RET */ |
| 17336 | 49, |
| 17337 | /* PATCHABLE_FUNCTION_EXIT */ |
| 17338 | 49, |
| 17339 | /* PATCHABLE_TAIL_CALL */ |
| 17340 | 49, |
| 17341 | /* PATCHABLE_EVENT_CALL */ |
| 17342 | 49, |
| 17343 | /* PATCHABLE_TYPED_EVENT_CALL */ |
| 17344 | 51, |
| 17345 | /* ICALL_BRANCH_FUNNEL */ |
| 17346 | 54, |
| 17347 | /* MEMBARRIER */ |
| 17348 | 54, |
| 17349 | /* JUMP_TABLE_DEBUG_INFO */ |
| 17350 | 54, |
| 17351 | /* CONVERGENCECTRL_ENTRY */ |
| 17352 | 55, |
| 17353 | /* CONVERGENCECTRL_ANCHOR */ |
| 17354 | 56, |
| 17355 | /* CONVERGENCECTRL_LOOP */ |
| 17356 | 57, |
| 17357 | /* CONVERGENCECTRL_GLUE */ |
| 17358 | 59, |
| 17359 | /* G_ASSERT_SEXT */ |
| 17360 | 60, |
| 17361 | /* G_ASSERT_ZEXT */ |
| 17362 | 63, |
| 17363 | /* G_ASSERT_ALIGN */ |
| 17364 | 66, |
| 17365 | /* G_ADD */ |
| 17366 | 69, |
| 17367 | /* G_SUB */ |
| 17368 | 72, |
| 17369 | /* G_MUL */ |
| 17370 | 75, |
| 17371 | /* G_SDIV */ |
| 17372 | 78, |
| 17373 | /* G_UDIV */ |
| 17374 | 81, |
| 17375 | /* G_SREM */ |
| 17376 | 84, |
| 17377 | /* G_UREM */ |
| 17378 | 87, |
| 17379 | /* G_SDIVREM */ |
| 17380 | 90, |
| 17381 | /* G_UDIVREM */ |
| 17382 | 94, |
| 17383 | /* G_AND */ |
| 17384 | 98, |
| 17385 | /* G_OR */ |
| 17386 | 101, |
| 17387 | /* G_XOR */ |
| 17388 | 104, |
| 17389 | /* G_IMPLICIT_DEF */ |
| 17390 | 107, |
| 17391 | /* G_PHI */ |
| 17392 | 108, |
| 17393 | /* G_FRAME_INDEX */ |
| 17394 | 109, |
| 17395 | /* G_GLOBAL_VALUE */ |
| 17396 | 111, |
| 17397 | /* G_PTRAUTH_GLOBAL_VALUE */ |
| 17398 | 113, |
| 17399 | /* G_CONSTANT_POOL */ |
| 17400 | 118, |
| 17401 | /* G_EXTRACT */ |
| 17402 | 120, |
| 17403 | /* G_UNMERGE_VALUES */ |
| 17404 | 123, |
| 17405 | /* G_INSERT */ |
| 17406 | 125, |
| 17407 | /* G_MERGE_VALUES */ |
| 17408 | 129, |
| 17409 | /* G_BUILD_VECTOR */ |
| 17410 | 131, |
| 17411 | /* G_BUILD_VECTOR_TRUNC */ |
| 17412 | 133, |
| 17413 | /* G_CONCAT_VECTORS */ |
| 17414 | 135, |
| 17415 | /* G_PTRTOINT */ |
| 17416 | 137, |
| 17417 | /* G_INTTOPTR */ |
| 17418 | 139, |
| 17419 | /* G_BITCAST */ |
| 17420 | 141, |
| 17421 | /* G_FREEZE */ |
| 17422 | 143, |
| 17423 | /* G_CONSTANT_FOLD_BARRIER */ |
| 17424 | 145, |
| 17425 | /* G_INTRINSIC_FPTRUNC_ROUND */ |
| 17426 | 147, |
| 17427 | /* G_INTRINSIC_TRUNC */ |
| 17428 | 150, |
| 17429 | /* G_INTRINSIC_ROUND */ |
| 17430 | 152, |
| 17431 | /* G_INTRINSIC_LRINT */ |
| 17432 | 154, |
| 17433 | /* G_INTRINSIC_LLRINT */ |
| 17434 | 156, |
| 17435 | /* G_INTRINSIC_ROUNDEVEN */ |
| 17436 | 158, |
| 17437 | /* G_READCYCLECOUNTER */ |
| 17438 | 160, |
| 17439 | /* G_READSTEADYCOUNTER */ |
| 17440 | 161, |
| 17441 | /* G_LOAD */ |
| 17442 | 162, |
| 17443 | /* G_SEXTLOAD */ |
| 17444 | 164, |
| 17445 | /* G_ZEXTLOAD */ |
| 17446 | 166, |
| 17447 | /* G_INDEXED_LOAD */ |
| 17448 | 168, |
| 17449 | /* G_INDEXED_SEXTLOAD */ |
| 17450 | 173, |
| 17451 | /* G_INDEXED_ZEXTLOAD */ |
| 17452 | 178, |
| 17453 | /* G_STORE */ |
| 17454 | 183, |
| 17455 | /* G_INDEXED_STORE */ |
| 17456 | 185, |
| 17457 | /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ |
| 17458 | 190, |
| 17459 | /* G_ATOMIC_CMPXCHG */ |
| 17460 | 195, |
| 17461 | /* G_ATOMICRMW_XCHG */ |
| 17462 | 199, |
| 17463 | /* G_ATOMICRMW_ADD */ |
| 17464 | 202, |
| 17465 | /* G_ATOMICRMW_SUB */ |
| 17466 | 205, |
| 17467 | /* G_ATOMICRMW_AND */ |
| 17468 | 208, |
| 17469 | /* G_ATOMICRMW_NAND */ |
| 17470 | 211, |
| 17471 | /* G_ATOMICRMW_OR */ |
| 17472 | 214, |
| 17473 | /* G_ATOMICRMW_XOR */ |
| 17474 | 217, |
| 17475 | /* G_ATOMICRMW_MAX */ |
| 17476 | 220, |
| 17477 | /* G_ATOMICRMW_MIN */ |
| 17478 | 223, |
| 17479 | /* G_ATOMICRMW_UMAX */ |
| 17480 | 226, |
| 17481 | /* G_ATOMICRMW_UMIN */ |
| 17482 | 229, |
| 17483 | /* G_ATOMICRMW_FADD */ |
| 17484 | 232, |
| 17485 | /* G_ATOMICRMW_FSUB */ |
| 17486 | 235, |
| 17487 | /* G_ATOMICRMW_FMAX */ |
| 17488 | 238, |
| 17489 | /* G_ATOMICRMW_FMIN */ |
| 17490 | 241, |
| 17491 | /* G_ATOMICRMW_UINC_WRAP */ |
| 17492 | 244, |
| 17493 | /* G_ATOMICRMW_UDEC_WRAP */ |
| 17494 | 247, |
| 17495 | /* G_FENCE */ |
| 17496 | 250, |
| 17497 | /* G_PREFETCH */ |
| 17498 | 252, |
| 17499 | /* G_BRCOND */ |
| 17500 | 256, |
| 17501 | /* G_BRINDIRECT */ |
| 17502 | 258, |
| 17503 | /* G_INVOKE_REGION_START */ |
| 17504 | 259, |
| 17505 | /* G_INTRINSIC */ |
| 17506 | 259, |
| 17507 | /* G_INTRINSIC_W_SIDE_EFFECTS */ |
| 17508 | 260, |
| 17509 | /* G_INTRINSIC_CONVERGENT */ |
| 17510 | 261, |
| 17511 | /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ |
| 17512 | 262, |
| 17513 | /* G_ANYEXT */ |
| 17514 | 263, |
| 17515 | /* G_TRUNC */ |
| 17516 | 265, |
| 17517 | /* G_CONSTANT */ |
| 17518 | 267, |
| 17519 | /* G_FCONSTANT */ |
| 17520 | 269, |
| 17521 | /* G_VASTART */ |
| 17522 | 271, |
| 17523 | /* G_VAARG */ |
| 17524 | 272, |
| 17525 | /* G_SEXT */ |
| 17526 | 275, |
| 17527 | /* G_SEXT_INREG */ |
| 17528 | 277, |
| 17529 | /* G_ZEXT */ |
| 17530 | 280, |
| 17531 | /* G_SHL */ |
| 17532 | 282, |
| 17533 | /* G_LSHR */ |
| 17534 | 285, |
| 17535 | /* G_ASHR */ |
| 17536 | 288, |
| 17537 | /* G_FSHL */ |
| 17538 | 291, |
| 17539 | /* G_FSHR */ |
| 17540 | 295, |
| 17541 | /* G_ROTR */ |
| 17542 | 299, |
| 17543 | /* G_ROTL */ |
| 17544 | 302, |
| 17545 | /* G_ICMP */ |
| 17546 | 305, |
| 17547 | /* G_FCMP */ |
| 17548 | 309, |
| 17549 | /* G_SCMP */ |
| 17550 | 313, |
| 17551 | /* G_UCMP */ |
| 17552 | 316, |
| 17553 | /* G_SELECT */ |
| 17554 | 319, |
| 17555 | /* G_UADDO */ |
| 17556 | 323, |
| 17557 | /* G_UADDE */ |
| 17558 | 327, |
| 17559 | /* G_USUBO */ |
| 17560 | 332, |
| 17561 | /* G_USUBE */ |
| 17562 | 336, |
| 17563 | /* G_SADDO */ |
| 17564 | 341, |
| 17565 | /* G_SADDE */ |
| 17566 | 345, |
| 17567 | /* G_SSUBO */ |
| 17568 | 350, |
| 17569 | /* G_SSUBE */ |
| 17570 | 354, |
| 17571 | /* G_UMULO */ |
| 17572 | 359, |
| 17573 | /* G_SMULO */ |
| 17574 | 363, |
| 17575 | /* G_UMULH */ |
| 17576 | 367, |
| 17577 | /* G_SMULH */ |
| 17578 | 370, |
| 17579 | /* G_UADDSAT */ |
| 17580 | 373, |
| 17581 | /* G_SADDSAT */ |
| 17582 | 376, |
| 17583 | /* G_USUBSAT */ |
| 17584 | 379, |
| 17585 | /* G_SSUBSAT */ |
| 17586 | 382, |
| 17587 | /* G_USHLSAT */ |
| 17588 | 385, |
| 17589 | /* G_SSHLSAT */ |
| 17590 | 388, |
| 17591 | /* G_SMULFIX */ |
| 17592 | 391, |
| 17593 | /* G_UMULFIX */ |
| 17594 | 395, |
| 17595 | /* G_SMULFIXSAT */ |
| 17596 | 399, |
| 17597 | /* G_UMULFIXSAT */ |
| 17598 | 403, |
| 17599 | /* G_SDIVFIX */ |
| 17600 | 407, |
| 17601 | /* G_UDIVFIX */ |
| 17602 | 411, |
| 17603 | /* G_SDIVFIXSAT */ |
| 17604 | 415, |
| 17605 | /* G_UDIVFIXSAT */ |
| 17606 | 419, |
| 17607 | /* G_FADD */ |
| 17608 | 423, |
| 17609 | /* G_FSUB */ |
| 17610 | 426, |
| 17611 | /* G_FMUL */ |
| 17612 | 429, |
| 17613 | /* G_FMA */ |
| 17614 | 432, |
| 17615 | /* G_FMAD */ |
| 17616 | 436, |
| 17617 | /* G_FDIV */ |
| 17618 | 440, |
| 17619 | /* G_FREM */ |
| 17620 | 443, |
| 17621 | /* G_FPOW */ |
| 17622 | 446, |
| 17623 | /* G_FPOWI */ |
| 17624 | 449, |
| 17625 | /* G_FEXP */ |
| 17626 | 452, |
| 17627 | /* G_FEXP2 */ |
| 17628 | 454, |
| 17629 | /* G_FEXP10 */ |
| 17630 | 456, |
| 17631 | /* G_FLOG */ |
| 17632 | 458, |
| 17633 | /* G_FLOG2 */ |
| 17634 | 460, |
| 17635 | /* G_FLOG10 */ |
| 17636 | 462, |
| 17637 | /* G_FLDEXP */ |
| 17638 | 464, |
| 17639 | /* G_FFREXP */ |
| 17640 | 467, |
| 17641 | /* G_FNEG */ |
| 17642 | 470, |
| 17643 | /* G_FPEXT */ |
| 17644 | 472, |
| 17645 | /* G_FPTRUNC */ |
| 17646 | 474, |
| 17647 | /* G_FPTOSI */ |
| 17648 | 476, |
| 17649 | /* G_FPTOUI */ |
| 17650 | 478, |
| 17651 | /* G_SITOFP */ |
| 17652 | 480, |
| 17653 | /* G_UITOFP */ |
| 17654 | 482, |
| 17655 | /* G_FABS */ |
| 17656 | 484, |
| 17657 | /* G_FCOPYSIGN */ |
| 17658 | 486, |
| 17659 | /* G_IS_FPCLASS */ |
| 17660 | 489, |
| 17661 | /* G_FCANONICALIZE */ |
| 17662 | 492, |
| 17663 | /* G_FMINNUM */ |
| 17664 | 494, |
| 17665 | /* G_FMAXNUM */ |
| 17666 | 497, |
| 17667 | /* G_FMINNUM_IEEE */ |
| 17668 | 500, |
| 17669 | /* G_FMAXNUM_IEEE */ |
| 17670 | 503, |
| 17671 | /* G_FMINIMUM */ |
| 17672 | 506, |
| 17673 | /* G_FMAXIMUM */ |
| 17674 | 509, |
| 17675 | /* G_GET_FPENV */ |
| 17676 | 512, |
| 17677 | /* G_SET_FPENV */ |
| 17678 | 513, |
| 17679 | /* G_RESET_FPENV */ |
| 17680 | 514, |
| 17681 | /* G_GET_FPMODE */ |
| 17682 | 514, |
| 17683 | /* G_SET_FPMODE */ |
| 17684 | 515, |
| 17685 | /* G_RESET_FPMODE */ |
| 17686 | 516, |
| 17687 | /* G_PTR_ADD */ |
| 17688 | 516, |
| 17689 | /* G_PTRMASK */ |
| 17690 | 519, |
| 17691 | /* G_SMIN */ |
| 17692 | 522, |
| 17693 | /* G_SMAX */ |
| 17694 | 525, |
| 17695 | /* G_UMIN */ |
| 17696 | 528, |
| 17697 | /* G_UMAX */ |
| 17698 | 531, |
| 17699 | /* G_ABS */ |
| 17700 | 534, |
| 17701 | /* G_LROUND */ |
| 17702 | 536, |
| 17703 | /* G_LLROUND */ |
| 17704 | 538, |
| 17705 | /* G_BR */ |
| 17706 | 540, |
| 17707 | /* G_BRJT */ |
| 17708 | 541, |
| 17709 | /* G_VSCALE */ |
| 17710 | 544, |
| 17711 | /* G_INSERT_SUBVECTOR */ |
| 17712 | 546, |
| 17713 | /* G_EXTRACT_SUBVECTOR */ |
| 17714 | 550, |
| 17715 | /* G_INSERT_VECTOR_ELT */ |
| 17716 | 553, |
| 17717 | /* G_EXTRACT_VECTOR_ELT */ |
| 17718 | 557, |
| 17719 | /* G_SHUFFLE_VECTOR */ |
| 17720 | 560, |
| 17721 | /* G_SPLAT_VECTOR */ |
| 17722 | 564, |
| 17723 | /* G_VECTOR_COMPRESS */ |
| 17724 | 566, |
| 17725 | /* G_CTTZ */ |
| 17726 | 570, |
| 17727 | /* G_CTTZ_ZERO_UNDEF */ |
| 17728 | 572, |
| 17729 | /* G_CTLZ */ |
| 17730 | 574, |
| 17731 | /* G_CTLZ_ZERO_UNDEF */ |
| 17732 | 576, |
| 17733 | /* G_CTPOP */ |
| 17734 | 578, |
| 17735 | /* G_BSWAP */ |
| 17736 | 580, |
| 17737 | /* G_BITREVERSE */ |
| 17738 | 582, |
| 17739 | /* G_FCEIL */ |
| 17740 | 584, |
| 17741 | /* G_FCOS */ |
| 17742 | 586, |
| 17743 | /* G_FSIN */ |
| 17744 | 588, |
| 17745 | /* G_FTAN */ |
| 17746 | 590, |
| 17747 | /* G_FACOS */ |
| 17748 | 592, |
| 17749 | /* G_FASIN */ |
| 17750 | 594, |
| 17751 | /* G_FATAN */ |
| 17752 | 596, |
| 17753 | /* G_FCOSH */ |
| 17754 | 598, |
| 17755 | /* G_FSINH */ |
| 17756 | 600, |
| 17757 | /* G_FTANH */ |
| 17758 | 602, |
| 17759 | /* G_FSQRT */ |
| 17760 | 604, |
| 17761 | /* G_FFLOOR */ |
| 17762 | 606, |
| 17763 | /* G_FRINT */ |
| 17764 | 608, |
| 17765 | /* G_FNEARBYINT */ |
| 17766 | 610, |
| 17767 | /* G_ADDRSPACE_CAST */ |
| 17768 | 612, |
| 17769 | /* G_BLOCK_ADDR */ |
| 17770 | 614, |
| 17771 | /* G_JUMP_TABLE */ |
| 17772 | 616, |
| 17773 | /* G_DYN_STACKALLOC */ |
| 17774 | 618, |
| 17775 | /* G_STACKSAVE */ |
| 17776 | 621, |
| 17777 | /* G_STACKRESTORE */ |
| 17778 | 622, |
| 17779 | /* G_STRICT_FADD */ |
| 17780 | 623, |
| 17781 | /* G_STRICT_FSUB */ |
| 17782 | 626, |
| 17783 | /* G_STRICT_FMUL */ |
| 17784 | 629, |
| 17785 | /* G_STRICT_FDIV */ |
| 17786 | 632, |
| 17787 | /* G_STRICT_FREM */ |
| 17788 | 635, |
| 17789 | /* G_STRICT_FMA */ |
| 17790 | 638, |
| 17791 | /* G_STRICT_FSQRT */ |
| 17792 | 642, |
| 17793 | /* G_STRICT_FLDEXP */ |
| 17794 | 644, |
| 17795 | /* G_READ_REGISTER */ |
| 17796 | 647, |
| 17797 | /* G_WRITE_REGISTER */ |
| 17798 | 649, |
| 17799 | /* G_MEMCPY */ |
| 17800 | 651, |
| 17801 | /* G_MEMCPY_INLINE */ |
| 17802 | 655, |
| 17803 | /* G_MEMMOVE */ |
| 17804 | 658, |
| 17805 | /* G_MEMSET */ |
| 17806 | 662, |
| 17807 | /* G_BZERO */ |
| 17808 | 666, |
| 17809 | /* G_TRAP */ |
| 17810 | 669, |
| 17811 | /* G_DEBUGTRAP */ |
| 17812 | 669, |
| 17813 | /* G_UBSANTRAP */ |
| 17814 | 669, |
| 17815 | /* G_VECREDUCE_SEQ_FADD */ |
| 17816 | 670, |
| 17817 | /* G_VECREDUCE_SEQ_FMUL */ |
| 17818 | 673, |
| 17819 | /* G_VECREDUCE_FADD */ |
| 17820 | 676, |
| 17821 | /* G_VECREDUCE_FMUL */ |
| 17822 | 678, |
| 17823 | /* G_VECREDUCE_FMAX */ |
| 17824 | 680, |
| 17825 | /* G_VECREDUCE_FMIN */ |
| 17826 | 682, |
| 17827 | /* G_VECREDUCE_FMAXIMUM */ |
| 17828 | 684, |
| 17829 | /* G_VECREDUCE_FMINIMUM */ |
| 17830 | 686, |
| 17831 | /* G_VECREDUCE_ADD */ |
| 17832 | 688, |
| 17833 | /* G_VECREDUCE_MUL */ |
| 17834 | 690, |
| 17835 | /* G_VECREDUCE_AND */ |
| 17836 | 692, |
| 17837 | /* G_VECREDUCE_OR */ |
| 17838 | 694, |
| 17839 | /* G_VECREDUCE_XOR */ |
| 17840 | 696, |
| 17841 | /* G_VECREDUCE_SMAX */ |
| 17842 | 698, |
| 17843 | /* G_VECREDUCE_SMIN */ |
| 17844 | 700, |
| 17845 | /* G_VECREDUCE_UMAX */ |
| 17846 | 702, |
| 17847 | /* G_VECREDUCE_UMIN */ |
| 17848 | 704, |
| 17849 | /* G_SBFX */ |
| 17850 | 706, |
| 17851 | /* G_UBFX */ |
| 17852 | 710, |
| 17853 | /* ABS */ |
| 17854 | 714, |
| 17855 | /* ADDSri */ |
| 17856 | 716, |
| 17857 | /* ADDSrr */ |
| 17858 | 721, |
| 17859 | /* ADDSrsi */ |
| 17860 | 726, |
| 17861 | /* ADDSrsr */ |
| 17862 | 732, |
| 17863 | /* ADJCALLSTACKDOWN */ |
| 17864 | 739, |
| 17865 | /* ADJCALLSTACKUP */ |
| 17866 | 743, |
| 17867 | /* ASRi */ |
| 17868 | 747, |
| 17869 | /* ASRr */ |
| 17870 | 753, |
| 17871 | /* B */ |
| 17872 | 759, |
| 17873 | /* BCCZi64 */ |
| 17874 | 760, |
| 17875 | /* BCCi64 */ |
| 17876 | 764, |
| 17877 | /* BLX_noip */ |
| 17878 | 770, |
| 17879 | /* BLX_pred_noip */ |
| 17880 | 771, |
| 17881 | /* BL_PUSHLR */ |
| 17882 | 772, |
| 17883 | /* BMOVPCB_CALL */ |
| 17884 | 774, |
| 17885 | /* BMOVPCRX_CALL */ |
| 17886 | 775, |
| 17887 | /* BR_JTadd */ |
| 17888 | 776, |
| 17889 | /* BR_JTm_i12 */ |
| 17890 | 779, |
| 17891 | /* BR_JTm_rs */ |
| 17892 | 782, |
| 17893 | /* BR_JTr */ |
| 17894 | 786, |
| 17895 | /* BX_CALL */ |
| 17896 | 788, |
| 17897 | /* CMP_SWAP_16 */ |
| 17898 | 789, |
| 17899 | /* CMP_SWAP_32 */ |
| 17900 | 794, |
| 17901 | /* CMP_SWAP_64 */ |
| 17902 | 799, |
| 17903 | /* CMP_SWAP_8 */ |
| 17904 | 804, |
| 17905 | /* CONSTPOOL_ENTRY */ |
| 17906 | 809, |
| 17907 | /* COPY_STRUCT_BYVAL_I32 */ |
| 17908 | 812, |
| 17909 | /* ITasm */ |
| 17910 | 816, |
| 17911 | /* Int_eh_sjlj_dispatchsetup */ |
| 17912 | 818, |
| 17913 | /* Int_eh_sjlj_longjmp */ |
| 17914 | 818, |
| 17915 | /* Int_eh_sjlj_setjmp */ |
| 17916 | 820, |
| 17917 | /* Int_eh_sjlj_setjmp_nofp */ |
| 17918 | 822, |
| 17919 | /* Int_eh_sjlj_setup_dispatch */ |
| 17920 | 824, |
| 17921 | /* JUMPTABLE_ADDRS */ |
| 17922 | 824, |
| 17923 | /* JUMPTABLE_INSTS */ |
| 17924 | 827, |
| 17925 | /* JUMPTABLE_TBB */ |
| 17926 | 830, |
| 17927 | /* JUMPTABLE_TBH */ |
| 17928 | 833, |
| 17929 | /* LDMIA_RET */ |
| 17930 | 836, |
| 17931 | /* LDRBT_POST */ |
| 17932 | 841, |
| 17933 | /* LDRConstPool */ |
| 17934 | 845, |
| 17935 | /* LDRHTii */ |
| 17936 | 849, |
| 17937 | /* LDRLIT_ga_abs */ |
| 17938 | 853, |
| 17939 | /* LDRLIT_ga_pcrel */ |
| 17940 | 855, |
| 17941 | /* LDRLIT_ga_pcrel_ldr */ |
| 17942 | 857, |
| 17943 | /* LDRSBTii */ |
| 17944 | 859, |
| 17945 | /* LDRSHTii */ |
| 17946 | 863, |
| 17947 | /* LDRT_POST */ |
| 17948 | 867, |
| 17949 | /* LEApcrel */ |
| 17950 | 871, |
| 17951 | /* LEApcrelJT */ |
| 17952 | 875, |
| 17953 | /* LOADDUAL */ |
| 17954 | 879, |
| 17955 | /* LSLi */ |
| 17956 | 883, |
| 17957 | /* LSLr */ |
| 17958 | 889, |
| 17959 | /* LSRi */ |
| 17960 | 895, |
| 17961 | /* LSRr */ |
| 17962 | 901, |
| 17963 | /* MEMCPY */ |
| 17964 | 907, |
| 17965 | /* MLAv5 */ |
| 17966 | 912, |
| 17967 | /* MOVCCi */ |
| 17968 | 919, |
| 17969 | /* MOVCCi16 */ |
| 17970 | 924, |
| 17971 | /* MOVCCi32imm */ |
| 17972 | 929, |
| 17973 | /* MOVCCr */ |
| 17974 | 934, |
| 17975 | /* MOVCCsi */ |
| 17976 | 939, |
| 17977 | /* MOVCCsr */ |
| 17978 | 945, |
| 17979 | /* MOVPCRX */ |
| 17980 | 952, |
| 17981 | /* MOVTi16_ga_pcrel */ |
| 17982 | 953, |
| 17983 | /* MOV_ga_pcrel */ |
| 17984 | 957, |
| 17985 | /* MOV_ga_pcrel_ldr */ |
| 17986 | 959, |
| 17987 | /* MOVi16_ga_pcrel */ |
| 17988 | 961, |
| 17989 | /* MOVi32imm */ |
| 17990 | 964, |
| 17991 | /* MOVsra_glue */ |
| 17992 | 966, |
| 17993 | /* MOVsrl_glue */ |
| 17994 | 968, |
| 17995 | /* MQPRCopy */ |
| 17996 | 970, |
| 17997 | /* MQQPRLoad */ |
| 17998 | 972, |
| 17999 | /* MQQPRStore */ |
| 18000 | 974, |
| 18001 | /* MQQQQPRLoad */ |
| 18002 | 976, |
| 18003 | /* MQQQQPRStore */ |
| 18004 | 978, |
| 18005 | /* MULv5 */ |
| 18006 | 980, |
| 18007 | /* MVE_MEMCPYLOOPINST */ |
| 18008 | 986, |
| 18009 | /* MVE_MEMSETLOOPINST */ |
| 18010 | 989, |
| 18011 | /* MVNCCi */ |
| 18012 | 992, |
| 18013 | /* PICADD */ |
| 18014 | 997, |
| 18015 | /* PICLDR */ |
| 18016 | 1002, |
| 18017 | /* PICLDRB */ |
| 18018 | 1007, |
| 18019 | /* PICLDRH */ |
| 18020 | 1012, |
| 18021 | /* PICLDRSB */ |
| 18022 | 1017, |
| 18023 | /* PICLDRSH */ |
| 18024 | 1022, |
| 18025 | /* PICSTR */ |
| 18026 | 1027, |
| 18027 | /* PICSTRB */ |
| 18028 | 1032, |
| 18029 | /* PICSTRH */ |
| 18030 | 1037, |
| 18031 | /* PseudoARMInitUndefDPR_VFP2 */ |
| 18032 | 1042, |
| 18033 | /* PseudoARMInitUndefGPR */ |
| 18034 | 1043, |
| 18035 | /* PseudoARMInitUndefMQPR */ |
| 18036 | 1044, |
| 18037 | /* PseudoARMInitUndefSPR */ |
| 18038 | 1045, |
| 18039 | /* RORi */ |
| 18040 | 1046, |
| 18041 | /* RORr */ |
| 18042 | 1052, |
| 18043 | /* RRX */ |
| 18044 | 1058, |
| 18045 | /* RRXi */ |
| 18046 | 1060, |
| 18047 | /* RSBSri */ |
| 18048 | 1065, |
| 18049 | /* RSBSrsi */ |
| 18050 | 1070, |
| 18051 | /* RSBSrsr */ |
| 18052 | 1076, |
| 18053 | /* SEH_EpilogEnd */ |
| 18054 | 1083, |
| 18055 | /* SEH_EpilogStart */ |
| 18056 | 1083, |
| 18057 | /* SEH_Nop */ |
| 18058 | 1083, |
| 18059 | /* SEH_Nop_Ret */ |
| 18060 | 1084, |
| 18061 | /* SEH_PrologEnd */ |
| 18062 | 1085, |
| 18063 | /* SEH_SaveFRegs */ |
| 18064 | 1085, |
| 18065 | /* SEH_SaveLR */ |
| 18066 | 1087, |
| 18067 | /* SEH_SaveRegs */ |
| 18068 | 1088, |
| 18069 | /* SEH_SaveRegs_Ret */ |
| 18070 | 1090, |
| 18071 | /* SEH_SaveSP */ |
| 18072 | 1092, |
| 18073 | /* SEH_StackAlloc */ |
| 18074 | 1093, |
| 18075 | /* SMLALv5 */ |
| 18076 | 1095, |
| 18077 | /* SMULLv5 */ |
| 18078 | 1104, |
| 18079 | /* SPACE */ |
| 18080 | 1111, |
| 18081 | /* STOREDUAL */ |
| 18082 | 1114, |
| 18083 | /* STRBT_POST */ |
| 18084 | 1118, |
| 18085 | /* STRBi_preidx */ |
| 18086 | 1122, |
| 18087 | /* STRBr_preidx */ |
| 18088 | 1129, |
| 18089 | /* STRH_preidx */ |
| 18090 | 1136, |
| 18091 | /* STRT_POST */ |
| 18092 | 1143, |
| 18093 | /* STRi_preidx */ |
| 18094 | 1147, |
| 18095 | /* STRr_preidx */ |
| 18096 | 1154, |
| 18097 | /* SUBS_PC_LR */ |
| 18098 | 1161, |
| 18099 | /* SUBSri */ |
| 18100 | 1164, |
| 18101 | /* SUBSrr */ |
| 18102 | 1169, |
| 18103 | /* SUBSrsi */ |
| 18104 | 1174, |
| 18105 | /* SUBSrsr */ |
| 18106 | 1180, |
| 18107 | /* SpeculationBarrierISBDSBEndBB */ |
| 18108 | 1187, |
| 18109 | /* SpeculationBarrierSBEndBB */ |
| 18110 | 1187, |
| 18111 | /* TAILJMPd */ |
| 18112 | 1187, |
| 18113 | /* TAILJMPr */ |
| 18114 | 1188, |
| 18115 | /* TAILJMPr4 */ |
| 18116 | 1189, |
| 18117 | /* TCRETURNdi */ |
| 18118 | 1190, |
| 18119 | /* TCRETURNri */ |
| 18120 | 1192, |
| 18121 | /* TCRETURNrinotr12 */ |
| 18122 | 1194, |
| 18123 | /* TPsoft */ |
| 18124 | 1196, |
| 18125 | /* UMLALv5 */ |
| 18126 | 1196, |
| 18127 | /* UMULLv5 */ |
| 18128 | 1205, |
| 18129 | /* VLD1LNdAsm_16 */ |
| 18130 | 1212, |
| 18131 | /* VLD1LNdAsm_32 */ |
| 18132 | 1218, |
| 18133 | /* VLD1LNdAsm_8 */ |
| 18134 | 1224, |
| 18135 | /* VLD1LNdWB_fixed_Asm_16 */ |
| 18136 | 1230, |
| 18137 | /* VLD1LNdWB_fixed_Asm_32 */ |
| 18138 | 1236, |
| 18139 | /* VLD1LNdWB_fixed_Asm_8 */ |
| 18140 | 1242, |
| 18141 | /* VLD1LNdWB_register_Asm_16 */ |
| 18142 | 1248, |
| 18143 | /* VLD1LNdWB_register_Asm_32 */ |
| 18144 | 1255, |
| 18145 | /* VLD1LNdWB_register_Asm_8 */ |
| 18146 | 1262, |
| 18147 | /* VLD2LNdAsm_16 */ |
| 18148 | 1269, |
| 18149 | /* VLD2LNdAsm_32 */ |
| 18150 | 1275, |
| 18151 | /* VLD2LNdAsm_8 */ |
| 18152 | 1281, |
| 18153 | /* VLD2LNdWB_fixed_Asm_16 */ |
| 18154 | 1287, |
| 18155 | /* VLD2LNdWB_fixed_Asm_32 */ |
| 18156 | 1293, |
| 18157 | /* VLD2LNdWB_fixed_Asm_8 */ |
| 18158 | 1299, |
| 18159 | /* VLD2LNdWB_register_Asm_16 */ |
| 18160 | 1305, |
| 18161 | /* VLD2LNdWB_register_Asm_32 */ |
| 18162 | 1312, |
| 18163 | /* VLD2LNdWB_register_Asm_8 */ |
| 18164 | 1319, |
| 18165 | /* VLD2LNqAsm_16 */ |
| 18166 | 1326, |
| 18167 | /* VLD2LNqAsm_32 */ |
| 18168 | 1332, |
| 18169 | /* VLD2LNqWB_fixed_Asm_16 */ |
| 18170 | 1338, |
| 18171 | /* VLD2LNqWB_fixed_Asm_32 */ |
| 18172 | 1344, |
| 18173 | /* VLD2LNqWB_register_Asm_16 */ |
| 18174 | 1350, |
| 18175 | /* VLD2LNqWB_register_Asm_32 */ |
| 18176 | 1357, |
| 18177 | /* VLD3DUPdAsm_16 */ |
| 18178 | 1364, |
| 18179 | /* VLD3DUPdAsm_32 */ |
| 18180 | 1369, |
| 18181 | /* VLD3DUPdAsm_8 */ |
| 18182 | 1374, |
| 18183 | /* VLD3DUPdWB_fixed_Asm_16 */ |
| 18184 | 1379, |
| 18185 | /* VLD3DUPdWB_fixed_Asm_32 */ |
| 18186 | 1384, |
| 18187 | /* VLD3DUPdWB_fixed_Asm_8 */ |
| 18188 | 1389, |
| 18189 | /* VLD3DUPdWB_register_Asm_16 */ |
| 18190 | 1394, |
| 18191 | /* VLD3DUPdWB_register_Asm_32 */ |
| 18192 | 1400, |
| 18193 | /* VLD3DUPdWB_register_Asm_8 */ |
| 18194 | 1406, |
| 18195 | /* VLD3DUPqAsm_16 */ |
| 18196 | 1412, |
| 18197 | /* VLD3DUPqAsm_32 */ |
| 18198 | 1417, |
| 18199 | /* VLD3DUPqAsm_8 */ |
| 18200 | 1422, |
| 18201 | /* VLD3DUPqWB_fixed_Asm_16 */ |
| 18202 | 1427, |
| 18203 | /* VLD3DUPqWB_fixed_Asm_32 */ |
| 18204 | 1432, |
| 18205 | /* VLD3DUPqWB_fixed_Asm_8 */ |
| 18206 | 1437, |
| 18207 | /* VLD3DUPqWB_register_Asm_16 */ |
| 18208 | 1442, |
| 18209 | /* VLD3DUPqWB_register_Asm_32 */ |
| 18210 | 1448, |
| 18211 | /* VLD3DUPqWB_register_Asm_8 */ |
| 18212 | 1454, |
| 18213 | /* VLD3LNdAsm_16 */ |
| 18214 | 1460, |
| 18215 | /* VLD3LNdAsm_32 */ |
| 18216 | 1466, |
| 18217 | /* VLD3LNdAsm_8 */ |
| 18218 | 1472, |
| 18219 | /* VLD3LNdWB_fixed_Asm_16 */ |
| 18220 | 1478, |
| 18221 | /* VLD3LNdWB_fixed_Asm_32 */ |
| 18222 | 1484, |
| 18223 | /* VLD3LNdWB_fixed_Asm_8 */ |
| 18224 | 1490, |
| 18225 | /* VLD3LNdWB_register_Asm_16 */ |
| 18226 | 1496, |
| 18227 | /* VLD3LNdWB_register_Asm_32 */ |
| 18228 | 1503, |
| 18229 | /* VLD3LNdWB_register_Asm_8 */ |
| 18230 | 1510, |
| 18231 | /* VLD3LNqAsm_16 */ |
| 18232 | 1517, |
| 18233 | /* VLD3LNqAsm_32 */ |
| 18234 | 1523, |
| 18235 | /* VLD3LNqWB_fixed_Asm_16 */ |
| 18236 | 1529, |
| 18237 | /* VLD3LNqWB_fixed_Asm_32 */ |
| 18238 | 1535, |
| 18239 | /* VLD3LNqWB_register_Asm_16 */ |
| 18240 | 1541, |
| 18241 | /* VLD3LNqWB_register_Asm_32 */ |
| 18242 | 1548, |
| 18243 | /* VLD3dAsm_16 */ |
| 18244 | 1555, |
| 18245 | /* VLD3dAsm_32 */ |
| 18246 | 1560, |
| 18247 | /* VLD3dAsm_8 */ |
| 18248 | 1565, |
| 18249 | /* VLD3dWB_fixed_Asm_16 */ |
| 18250 | 1570, |
| 18251 | /* VLD3dWB_fixed_Asm_32 */ |
| 18252 | 1575, |
| 18253 | /* VLD3dWB_fixed_Asm_8 */ |
| 18254 | 1580, |
| 18255 | /* VLD3dWB_register_Asm_16 */ |
| 18256 | 1585, |
| 18257 | /* VLD3dWB_register_Asm_32 */ |
| 18258 | 1591, |
| 18259 | /* VLD3dWB_register_Asm_8 */ |
| 18260 | 1597, |
| 18261 | /* VLD3qAsm_16 */ |
| 18262 | 1603, |
| 18263 | /* VLD3qAsm_32 */ |
| 18264 | 1608, |
| 18265 | /* VLD3qAsm_8 */ |
| 18266 | 1613, |
| 18267 | /* VLD3qWB_fixed_Asm_16 */ |
| 18268 | 1618, |
| 18269 | /* VLD3qWB_fixed_Asm_32 */ |
| 18270 | 1623, |
| 18271 | /* VLD3qWB_fixed_Asm_8 */ |
| 18272 | 1628, |
| 18273 | /* VLD3qWB_register_Asm_16 */ |
| 18274 | 1633, |
| 18275 | /* VLD3qWB_register_Asm_32 */ |
| 18276 | 1639, |
| 18277 | /* VLD3qWB_register_Asm_8 */ |
| 18278 | 1645, |
| 18279 | /* VLD4DUPdAsm_16 */ |
| 18280 | 1651, |
| 18281 | /* VLD4DUPdAsm_32 */ |
| 18282 | 1656, |
| 18283 | /* VLD4DUPdAsm_8 */ |
| 18284 | 1661, |
| 18285 | /* VLD4DUPdWB_fixed_Asm_16 */ |
| 18286 | 1666, |
| 18287 | /* VLD4DUPdWB_fixed_Asm_32 */ |
| 18288 | 1671, |
| 18289 | /* VLD4DUPdWB_fixed_Asm_8 */ |
| 18290 | 1676, |
| 18291 | /* VLD4DUPdWB_register_Asm_16 */ |
| 18292 | 1681, |
| 18293 | /* VLD4DUPdWB_register_Asm_32 */ |
| 18294 | 1687, |
| 18295 | /* VLD4DUPdWB_register_Asm_8 */ |
| 18296 | 1693, |
| 18297 | /* VLD4DUPqAsm_16 */ |
| 18298 | 1699, |
| 18299 | /* VLD4DUPqAsm_32 */ |
| 18300 | 1704, |
| 18301 | /* VLD4DUPqAsm_8 */ |
| 18302 | 1709, |
| 18303 | /* VLD4DUPqWB_fixed_Asm_16 */ |
| 18304 | 1714, |
| 18305 | /* VLD4DUPqWB_fixed_Asm_32 */ |
| 18306 | 1719, |
| 18307 | /* VLD4DUPqWB_fixed_Asm_8 */ |
| 18308 | 1724, |
| 18309 | /* VLD4DUPqWB_register_Asm_16 */ |
| 18310 | 1729, |
| 18311 | /* VLD4DUPqWB_register_Asm_32 */ |
| 18312 | 1735, |
| 18313 | /* VLD4DUPqWB_register_Asm_8 */ |
| 18314 | 1741, |
| 18315 | /* VLD4LNdAsm_16 */ |
| 18316 | 1747, |
| 18317 | /* VLD4LNdAsm_32 */ |
| 18318 | 1753, |
| 18319 | /* VLD4LNdAsm_8 */ |
| 18320 | 1759, |
| 18321 | /* VLD4LNdWB_fixed_Asm_16 */ |
| 18322 | 1765, |
| 18323 | /* VLD4LNdWB_fixed_Asm_32 */ |
| 18324 | 1771, |
| 18325 | /* VLD4LNdWB_fixed_Asm_8 */ |
| 18326 | 1777, |
| 18327 | /* VLD4LNdWB_register_Asm_16 */ |
| 18328 | 1783, |
| 18329 | /* VLD4LNdWB_register_Asm_32 */ |
| 18330 | 1790, |
| 18331 | /* VLD4LNdWB_register_Asm_8 */ |
| 18332 | 1797, |
| 18333 | /* VLD4LNqAsm_16 */ |
| 18334 | 1804, |
| 18335 | /* VLD4LNqAsm_32 */ |
| 18336 | 1810, |
| 18337 | /* VLD4LNqWB_fixed_Asm_16 */ |
| 18338 | 1816, |
| 18339 | /* VLD4LNqWB_fixed_Asm_32 */ |
| 18340 | 1822, |
| 18341 | /* VLD4LNqWB_register_Asm_16 */ |
| 18342 | 1828, |
| 18343 | /* VLD4LNqWB_register_Asm_32 */ |
| 18344 | 1835, |
| 18345 | /* VLD4dAsm_16 */ |
| 18346 | 1842, |
| 18347 | /* VLD4dAsm_32 */ |
| 18348 | 1847, |
| 18349 | /* VLD4dAsm_8 */ |
| 18350 | 1852, |
| 18351 | /* VLD4dWB_fixed_Asm_16 */ |
| 18352 | 1857, |
| 18353 | /* VLD4dWB_fixed_Asm_32 */ |
| 18354 | 1862, |
| 18355 | /* VLD4dWB_fixed_Asm_8 */ |
| 18356 | 1867, |
| 18357 | /* VLD4dWB_register_Asm_16 */ |
| 18358 | 1872, |
| 18359 | /* VLD4dWB_register_Asm_32 */ |
| 18360 | 1878, |
| 18361 | /* VLD4dWB_register_Asm_8 */ |
| 18362 | 1884, |
| 18363 | /* VLD4qAsm_16 */ |
| 18364 | 1890, |
| 18365 | /* VLD4qAsm_32 */ |
| 18366 | 1895, |
| 18367 | /* VLD4qAsm_8 */ |
| 18368 | 1900, |
| 18369 | /* VLD4qWB_fixed_Asm_16 */ |
| 18370 | 1905, |
| 18371 | /* VLD4qWB_fixed_Asm_32 */ |
| 18372 | 1910, |
| 18373 | /* VLD4qWB_fixed_Asm_8 */ |
| 18374 | 1915, |
| 18375 | /* VLD4qWB_register_Asm_16 */ |
| 18376 | 1920, |
| 18377 | /* VLD4qWB_register_Asm_32 */ |
| 18378 | 1926, |
| 18379 | /* VLD4qWB_register_Asm_8 */ |
| 18380 | 1932, |
| 18381 | /* VMOVD0 */ |
| 18382 | 1938, |
| 18383 | /* VMOVDcc */ |
| 18384 | 1939, |
| 18385 | /* VMOVHcc */ |
| 18386 | 1944, |
| 18387 | /* VMOVQ0 */ |
| 18388 | 1949, |
| 18389 | /* VMOVScc */ |
| 18390 | 1950, |
| 18391 | /* VST1LNdAsm_16 */ |
| 18392 | 1955, |
| 18393 | /* VST1LNdAsm_32 */ |
| 18394 | 1961, |
| 18395 | /* VST1LNdAsm_8 */ |
| 18396 | 1967, |
| 18397 | /* VST1LNdWB_fixed_Asm_16 */ |
| 18398 | 1973, |
| 18399 | /* VST1LNdWB_fixed_Asm_32 */ |
| 18400 | 1979, |
| 18401 | /* VST1LNdWB_fixed_Asm_8 */ |
| 18402 | 1985, |
| 18403 | /* VST1LNdWB_register_Asm_16 */ |
| 18404 | 1991, |
| 18405 | /* VST1LNdWB_register_Asm_32 */ |
| 18406 | 1998, |
| 18407 | /* VST1LNdWB_register_Asm_8 */ |
| 18408 | 2005, |
| 18409 | /* VST2LNdAsm_16 */ |
| 18410 | 2012, |
| 18411 | /* VST2LNdAsm_32 */ |
| 18412 | 2018, |
| 18413 | /* VST2LNdAsm_8 */ |
| 18414 | 2024, |
| 18415 | /* VST2LNdWB_fixed_Asm_16 */ |
| 18416 | 2030, |
| 18417 | /* VST2LNdWB_fixed_Asm_32 */ |
| 18418 | 2036, |
| 18419 | /* VST2LNdWB_fixed_Asm_8 */ |
| 18420 | 2042, |
| 18421 | /* VST2LNdWB_register_Asm_16 */ |
| 18422 | 2048, |
| 18423 | /* VST2LNdWB_register_Asm_32 */ |
| 18424 | 2055, |
| 18425 | /* VST2LNdWB_register_Asm_8 */ |
| 18426 | 2062, |
| 18427 | /* VST2LNqAsm_16 */ |
| 18428 | 2069, |
| 18429 | /* VST2LNqAsm_32 */ |
| 18430 | 2075, |
| 18431 | /* VST2LNqWB_fixed_Asm_16 */ |
| 18432 | 2081, |
| 18433 | /* VST2LNqWB_fixed_Asm_32 */ |
| 18434 | 2087, |
| 18435 | /* VST2LNqWB_register_Asm_16 */ |
| 18436 | 2093, |
| 18437 | /* VST2LNqWB_register_Asm_32 */ |
| 18438 | 2100, |
| 18439 | /* VST3LNdAsm_16 */ |
| 18440 | 2107, |
| 18441 | /* VST3LNdAsm_32 */ |
| 18442 | 2113, |
| 18443 | /* VST3LNdAsm_8 */ |
| 18444 | 2119, |
| 18445 | /* VST3LNdWB_fixed_Asm_16 */ |
| 18446 | 2125, |
| 18447 | /* VST3LNdWB_fixed_Asm_32 */ |
| 18448 | 2131, |
| 18449 | /* VST3LNdWB_fixed_Asm_8 */ |
| 18450 | 2137, |
| 18451 | /* VST3LNdWB_register_Asm_16 */ |
| 18452 | 2143, |
| 18453 | /* VST3LNdWB_register_Asm_32 */ |
| 18454 | 2150, |
| 18455 | /* VST3LNdWB_register_Asm_8 */ |
| 18456 | 2157, |
| 18457 | /* VST3LNqAsm_16 */ |
| 18458 | 2164, |
| 18459 | /* VST3LNqAsm_32 */ |
| 18460 | 2170, |
| 18461 | /* VST3LNqWB_fixed_Asm_16 */ |
| 18462 | 2176, |
| 18463 | /* VST3LNqWB_fixed_Asm_32 */ |
| 18464 | 2182, |
| 18465 | /* VST3LNqWB_register_Asm_16 */ |
| 18466 | 2188, |
| 18467 | /* VST3LNqWB_register_Asm_32 */ |
| 18468 | 2195, |
| 18469 | /* VST3dAsm_16 */ |
| 18470 | 2202, |
| 18471 | /* VST3dAsm_32 */ |
| 18472 | 2207, |
| 18473 | /* VST3dAsm_8 */ |
| 18474 | 2212, |
| 18475 | /* VST3dWB_fixed_Asm_16 */ |
| 18476 | 2217, |
| 18477 | /* VST3dWB_fixed_Asm_32 */ |
| 18478 | 2222, |
| 18479 | /* VST3dWB_fixed_Asm_8 */ |
| 18480 | 2227, |
| 18481 | /* VST3dWB_register_Asm_16 */ |
| 18482 | 2232, |
| 18483 | /* VST3dWB_register_Asm_32 */ |
| 18484 | 2238, |
| 18485 | /* VST3dWB_register_Asm_8 */ |
| 18486 | 2244, |
| 18487 | /* VST3qAsm_16 */ |
| 18488 | 2250, |
| 18489 | /* VST3qAsm_32 */ |
| 18490 | 2255, |
| 18491 | /* VST3qAsm_8 */ |
| 18492 | 2260, |
| 18493 | /* VST3qWB_fixed_Asm_16 */ |
| 18494 | 2265, |
| 18495 | /* VST3qWB_fixed_Asm_32 */ |
| 18496 | 2270, |
| 18497 | /* VST3qWB_fixed_Asm_8 */ |
| 18498 | 2275, |
| 18499 | /* VST3qWB_register_Asm_16 */ |
| 18500 | 2280, |
| 18501 | /* VST3qWB_register_Asm_32 */ |
| 18502 | 2286, |
| 18503 | /* VST3qWB_register_Asm_8 */ |
| 18504 | 2292, |
| 18505 | /* VST4LNdAsm_16 */ |
| 18506 | 2298, |
| 18507 | /* VST4LNdAsm_32 */ |
| 18508 | 2304, |
| 18509 | /* VST4LNdAsm_8 */ |
| 18510 | 2310, |
| 18511 | /* VST4LNdWB_fixed_Asm_16 */ |
| 18512 | 2316, |
| 18513 | /* VST4LNdWB_fixed_Asm_32 */ |
| 18514 | 2322, |
| 18515 | /* VST4LNdWB_fixed_Asm_8 */ |
| 18516 | 2328, |
| 18517 | /* VST4LNdWB_register_Asm_16 */ |
| 18518 | 2334, |
| 18519 | /* VST4LNdWB_register_Asm_32 */ |
| 18520 | 2341, |
| 18521 | /* VST4LNdWB_register_Asm_8 */ |
| 18522 | 2348, |
| 18523 | /* VST4LNqAsm_16 */ |
| 18524 | 2355, |
| 18525 | /* VST4LNqAsm_32 */ |
| 18526 | 2361, |
| 18527 | /* VST4LNqWB_fixed_Asm_16 */ |
| 18528 | 2367, |
| 18529 | /* VST4LNqWB_fixed_Asm_32 */ |
| 18530 | 2373, |
| 18531 | /* VST4LNqWB_register_Asm_16 */ |
| 18532 | 2379, |
| 18533 | /* VST4LNqWB_register_Asm_32 */ |
| 18534 | 2386, |
| 18535 | /* VST4dAsm_16 */ |
| 18536 | 2393, |
| 18537 | /* VST4dAsm_32 */ |
| 18538 | 2398, |
| 18539 | /* VST4dAsm_8 */ |
| 18540 | 2403, |
| 18541 | /* VST4dWB_fixed_Asm_16 */ |
| 18542 | 2408, |
| 18543 | /* VST4dWB_fixed_Asm_32 */ |
| 18544 | 2413, |
| 18545 | /* VST4dWB_fixed_Asm_8 */ |
| 18546 | 2418, |
| 18547 | /* VST4dWB_register_Asm_16 */ |
| 18548 | 2423, |
| 18549 | /* VST4dWB_register_Asm_32 */ |
| 18550 | 2429, |
| 18551 | /* VST4dWB_register_Asm_8 */ |
| 18552 | 2435, |
| 18553 | /* VST4qAsm_16 */ |
| 18554 | 2441, |
| 18555 | /* VST4qAsm_32 */ |
| 18556 | 2446, |
| 18557 | /* VST4qAsm_8 */ |
| 18558 | 2451, |
| 18559 | /* VST4qWB_fixed_Asm_16 */ |
| 18560 | 2456, |
| 18561 | /* VST4qWB_fixed_Asm_32 */ |
| 18562 | 2461, |
| 18563 | /* VST4qWB_fixed_Asm_8 */ |
| 18564 | 2466, |
| 18565 | /* VST4qWB_register_Asm_16 */ |
| 18566 | 2471, |
| 18567 | /* VST4qWB_register_Asm_32 */ |
| 18568 | 2477, |
| 18569 | /* VST4qWB_register_Asm_8 */ |
| 18570 | 2483, |
| 18571 | /* WIN__CHKSTK */ |
| 18572 | 2489, |
| 18573 | /* WIN__DBZCHK */ |
| 18574 | 2489, |
| 18575 | /* t2ABS */ |
| 18576 | 2490, |
| 18577 | /* t2ADDSri */ |
| 18578 | 2492, |
| 18579 | /* t2ADDSrr */ |
| 18580 | 2497, |
| 18581 | /* t2ADDSrs */ |
| 18582 | 2502, |
| 18583 | /* t2BF_LabelPseudo */ |
| 18584 | 2508, |
| 18585 | /* t2BR_JT */ |
| 18586 | 2509, |
| 18587 | /* t2CALL_BTI */ |
| 18588 | 2512, |
| 18589 | /* t2DoLoopStart */ |
| 18590 | 2515, |
| 18591 | /* t2DoLoopStartTP */ |
| 18592 | 2517, |
| 18593 | /* t2LDMIA_RET */ |
| 18594 | 2520, |
| 18595 | /* t2LDRB_OFFSET_imm */ |
| 18596 | 2525, |
| 18597 | /* t2LDRB_POST_imm */ |
| 18598 | 2530, |
| 18599 | /* t2LDRB_PRE_imm */ |
| 18600 | 2535, |
| 18601 | /* t2LDRBpcrel */ |
| 18602 | 2540, |
| 18603 | /* t2LDRConstPool */ |
| 18604 | 2544, |
| 18605 | /* t2LDRH_OFFSET_imm */ |
| 18606 | 2548, |
| 18607 | /* t2LDRH_POST_imm */ |
| 18608 | 2553, |
| 18609 | /* t2LDRH_PRE_imm */ |
| 18610 | 2558, |
| 18611 | /* t2LDRHpcrel */ |
| 18612 | 2563, |
| 18613 | /* t2LDRLIT_ga_pcrel */ |
| 18614 | 2567, |
| 18615 | /* t2LDRSB_OFFSET_imm */ |
| 18616 | 2569, |
| 18617 | /* t2LDRSB_POST_imm */ |
| 18618 | 2574, |
| 18619 | /* t2LDRSB_PRE_imm */ |
| 18620 | 2579, |
| 18621 | /* t2LDRSBpcrel */ |
| 18622 | 2584, |
| 18623 | /* t2LDRSH_OFFSET_imm */ |
| 18624 | 2588, |
| 18625 | /* t2LDRSH_POST_imm */ |
| 18626 | 2593, |
| 18627 | /* t2LDRSH_PRE_imm */ |
| 18628 | 2598, |
| 18629 | /* t2LDRSHpcrel */ |
| 18630 | 2603, |
| 18631 | /* t2LDR_POST_imm */ |
| 18632 | 2607, |
| 18633 | /* t2LDR_PRE_imm */ |
| 18634 | 2612, |
| 18635 | /* t2LDRpci_pic */ |
| 18636 | 2617, |
| 18637 | /* t2LDRpcrel */ |
| 18638 | 2620, |
| 18639 | /* t2LEApcrel */ |
| 18640 | 2624, |
| 18641 | /* t2LEApcrelJT */ |
| 18642 | 2628, |
| 18643 | /* t2LoopDec */ |
| 18644 | 2632, |
| 18645 | /* t2LoopEnd */ |
| 18646 | 2635, |
| 18647 | /* t2LoopEndDec */ |
| 18648 | 2637, |
| 18649 | /* t2MOVCCasr */ |
| 18650 | 2640, |
| 18651 | /* t2MOVCCi */ |
| 18652 | 2646, |
| 18653 | /* t2MOVCCi16 */ |
| 18654 | 2651, |
| 18655 | /* t2MOVCCi32imm */ |
| 18656 | 2656, |
| 18657 | /* t2MOVCClsl */ |
| 18658 | 2661, |
| 18659 | /* t2MOVCClsr */ |
| 18660 | 2667, |
| 18661 | /* t2MOVCCr */ |
| 18662 | 2673, |
| 18663 | /* t2MOVCCror */ |
| 18664 | 2678, |
| 18665 | /* t2MOVSsi */ |
| 18666 | 2684, |
| 18667 | /* t2MOVSsr */ |
| 18668 | 2689, |
| 18669 | /* t2MOVTi16_ga_pcrel */ |
| 18670 | 2695, |
| 18671 | /* t2MOV_ga_pcrel */ |
| 18672 | 2699, |
| 18673 | /* t2MOVi16_ga_pcrel */ |
| 18674 | 2701, |
| 18675 | /* t2MOVi32imm */ |
| 18676 | 2704, |
| 18677 | /* t2MOVsi */ |
| 18678 | 2706, |
| 18679 | /* t2MOVsr */ |
| 18680 | 2711, |
| 18681 | /* t2MVNCCi */ |
| 18682 | 2717, |
| 18683 | /* t2RSBSri */ |
| 18684 | 2722, |
| 18685 | /* t2RSBSrs */ |
| 18686 | 2727, |
| 18687 | /* t2STRB_OFFSET_imm */ |
| 18688 | 2733, |
| 18689 | /* t2STRB_POST_imm */ |
| 18690 | 2738, |
| 18691 | /* t2STRB_PRE_imm */ |
| 18692 | 2743, |
| 18693 | /* t2STRB_preidx */ |
| 18694 | 2748, |
| 18695 | /* t2STRH_OFFSET_imm */ |
| 18696 | 2754, |
| 18697 | /* t2STRH_POST_imm */ |
| 18698 | 2759, |
| 18699 | /* t2STRH_PRE_imm */ |
| 18700 | 2764, |
| 18701 | /* t2STRH_preidx */ |
| 18702 | 2769, |
| 18703 | /* t2STR_POST_imm */ |
| 18704 | 2775, |
| 18705 | /* t2STR_PRE_imm */ |
| 18706 | 2780, |
| 18707 | /* t2STR_preidx */ |
| 18708 | 2785, |
| 18709 | /* t2SUBSri */ |
| 18710 | 2791, |
| 18711 | /* t2SUBSrr */ |
| 18712 | 2796, |
| 18713 | /* t2SUBSrs */ |
| 18714 | 2801, |
| 18715 | /* t2SpeculationBarrierISBDSBEndBB */ |
| 18716 | 2807, |
| 18717 | /* t2SpeculationBarrierSBEndBB */ |
| 18718 | 2807, |
| 18719 | /* t2TBB_JT */ |
| 18720 | 2807, |
| 18721 | /* t2TBH_JT */ |
| 18722 | 2811, |
| 18723 | /* t2WhileLoopSetup */ |
| 18724 | 2815, |
| 18725 | /* t2WhileLoopStart */ |
| 18726 | 2817, |
| 18727 | /* t2WhileLoopStartLR */ |
| 18728 | 2819, |
| 18729 | /* t2WhileLoopStartTP */ |
| 18730 | 2822, |
| 18731 | /* tADCS */ |
| 18732 | 2826, |
| 18733 | /* tADDSi3 */ |
| 18734 | 2829, |
| 18735 | /* tADDSi8 */ |
| 18736 | 2832, |
| 18737 | /* tADDSrr */ |
| 18738 | 2835, |
| 18739 | /* tADDframe */ |
| 18740 | 2838, |
| 18741 | /* tADJCALLSTACKDOWN */ |
| 18742 | 2841, |
| 18743 | /* tADJCALLSTACKUP */ |
| 18744 | 2843, |
| 18745 | /* tBLXNS_CALL */ |
| 18746 | 2845, |
| 18747 | /* tBLXr_noip */ |
| 18748 | 2846, |
| 18749 | /* tBL_PUSHLR */ |
| 18750 | 2849, |
| 18751 | /* tBRIND */ |
| 18752 | 2853, |
| 18753 | /* tBR_JTr */ |
| 18754 | 2856, |
| 18755 | /* tBXNS_RET */ |
| 18756 | 2858, |
| 18757 | /* tBX_CALL */ |
| 18758 | 2858, |
| 18759 | /* tBX_RET */ |
| 18760 | 2859, |
| 18761 | /* tBX_RET_vararg */ |
| 18762 | 2861, |
| 18763 | /* tBfar */ |
| 18764 | 2864, |
| 18765 | /* tCMP_SWAP_16 */ |
| 18766 | 2867, |
| 18767 | /* tCMP_SWAP_32 */ |
| 18768 | 2872, |
| 18769 | /* tCMP_SWAP_8 */ |
| 18770 | 2877, |
| 18771 | /* tLDMIA_UPD */ |
| 18772 | 2882, |
| 18773 | /* tLDRConstPool */ |
| 18774 | 2887, |
| 18775 | /* tLDRLIT_ga_abs */ |
| 18776 | 2891, |
| 18777 | /* tLDRLIT_ga_pcrel */ |
| 18778 | 2893, |
| 18779 | /* tLDR_postidx */ |
| 18780 | 2895, |
| 18781 | /* tLDRpci_pic */ |
| 18782 | 2900, |
| 18783 | /* tLEApcrel */ |
| 18784 | 2903, |
| 18785 | /* tLEApcrelJT */ |
| 18786 | 2907, |
| 18787 | /* tLSLSri */ |
| 18788 | 2911, |
| 18789 | /* tMOVCCr_pseudo */ |
| 18790 | 2914, |
| 18791 | /* tMOVi32imm */ |
| 18792 | 2919, |
| 18793 | /* tPOP_RET */ |
| 18794 | 2921, |
| 18795 | /* tRSBS */ |
| 18796 | 2924, |
| 18797 | /* tSBCS */ |
| 18798 | 2926, |
| 18799 | /* tSUBSi3 */ |
| 18800 | 2929, |
| 18801 | /* tSUBSi8 */ |
| 18802 | 2932, |
| 18803 | /* tSUBSrr */ |
| 18804 | 2935, |
| 18805 | /* tTAILJMPd */ |
| 18806 | 2938, |
| 18807 | /* tTAILJMPdND */ |
| 18808 | 2941, |
| 18809 | /* tTAILJMPr */ |
| 18810 | 2944, |
| 18811 | /* tTBB_JT */ |
| 18812 | 2945, |
| 18813 | /* tTBH_JT */ |
| 18814 | 2949, |
| 18815 | /* tTPsoft */ |
| 18816 | 2953, |
| 18817 | /* ADCri */ |
| 18818 | 2953, |
| 18819 | /* ADCrr */ |
| 18820 | 2959, |
| 18821 | /* ADCrsi */ |
| 18822 | 2965, |
| 18823 | /* ADCrsr */ |
| 18824 | 2972, |
| 18825 | /* ADDri */ |
| 18826 | 2980, |
| 18827 | /* ADDrr */ |
| 18828 | 2986, |
| 18829 | /* ADDrsi */ |
| 18830 | 2992, |
| 18831 | /* ADDrsr */ |
| 18832 | 2999, |
| 18833 | /* ADR */ |
| 18834 | 3007, |
| 18835 | /* AESD */ |
| 18836 | 3011, |
| 18837 | /* AESE */ |
| 18838 | 3014, |
| 18839 | /* AESIMC */ |
| 18840 | 3017, |
| 18841 | /* AESMC */ |
| 18842 | 3019, |
| 18843 | /* ANDri */ |
| 18844 | 3021, |
| 18845 | /* ANDrr */ |
| 18846 | 3027, |
| 18847 | /* ANDrsi */ |
| 18848 | 3033, |
| 18849 | /* ANDrsr */ |
| 18850 | 3040, |
| 18851 | /* BF16VDOTI_VDOTD */ |
| 18852 | 3048, |
| 18853 | /* BF16VDOTI_VDOTQ */ |
| 18854 | 3053, |
| 18855 | /* BF16VDOTS_VDOTD */ |
| 18856 | 3058, |
| 18857 | /* BF16VDOTS_VDOTQ */ |
| 18858 | 3062, |
| 18859 | /* BF16_VCVT */ |
| 18860 | 3066, |
| 18861 | /* BF16_VCVTB */ |
| 18862 | 3070, |
| 18863 | /* BF16_VCVTT */ |
| 18864 | 3075, |
| 18865 | /* BFC */ |
| 18866 | 3080, |
| 18867 | /* BFI */ |
| 18868 | 3085, |
| 18869 | /* BICri */ |
| 18870 | 3091, |
| 18871 | /* BICrr */ |
| 18872 | 3097, |
| 18873 | /* BICrsi */ |
| 18874 | 3103, |
| 18875 | /* BICrsr */ |
| 18876 | 3110, |
| 18877 | /* BKPT */ |
| 18878 | 3118, |
| 18879 | /* BL */ |
| 18880 | 3119, |
| 18881 | /* BLX */ |
| 18882 | 3120, |
| 18883 | /* BLX_pred */ |
| 18884 | 3121, |
| 18885 | /* BLXi */ |
| 18886 | 3124, |
| 18887 | /* BL_pred */ |
| 18888 | 3125, |
| 18889 | /* BX */ |
| 18890 | 3128, |
| 18891 | /* BXJ */ |
| 18892 | 3129, |
| 18893 | /* BX_RET */ |
| 18894 | 3132, |
| 18895 | /* BX_pred */ |
| 18896 | 3134, |
| 18897 | /* Bcc */ |
| 18898 | 3137, |
| 18899 | /* CDE_CX1 */ |
| 18900 | 3140, |
| 18901 | /* CDE_CX1A */ |
| 18902 | 3143, |
| 18903 | /* CDE_CX1D */ |
| 18904 | 3149, |
| 18905 | /* CDE_CX1DA */ |
| 18906 | 3152, |
| 18907 | /* CDE_CX2 */ |
| 18908 | 3158, |
| 18909 | /* CDE_CX2A */ |
| 18910 | 3162, |
| 18911 | /* CDE_CX2D */ |
| 18912 | 3169, |
| 18913 | /* CDE_CX2DA */ |
| 18914 | 3173, |
| 18915 | /* CDE_CX3 */ |
| 18916 | 3180, |
| 18917 | /* CDE_CX3A */ |
| 18918 | 3185, |
| 18919 | /* CDE_CX3D */ |
| 18920 | 3193, |
| 18921 | /* CDE_CX3DA */ |
| 18922 | 3198, |
| 18923 | /* CDE_VCX1A_fpdp */ |
| 18924 | 3206, |
| 18925 | /* CDE_VCX1A_fpsp */ |
| 18926 | 3210, |
| 18927 | /* CDE_VCX1A_vec */ |
| 18928 | 3214, |
| 18929 | /* CDE_VCX1_fpdp */ |
| 18930 | 3221, |
| 18931 | /* CDE_VCX1_fpsp */ |
| 18932 | 3224, |
| 18933 | /* CDE_VCX1_vec */ |
| 18934 | 3227, |
| 18935 | /* CDE_VCX2A_fpdp */ |
| 18936 | 3234, |
| 18937 | /* CDE_VCX2A_fpsp */ |
| 18938 | 3239, |
| 18939 | /* CDE_VCX2A_vec */ |
| 18940 | 3244, |
| 18941 | /* CDE_VCX2_fpdp */ |
| 18942 | 3252, |
| 18943 | /* CDE_VCX2_fpsp */ |
| 18944 | 3256, |
| 18945 | /* CDE_VCX2_vec */ |
| 18946 | 3260, |
| 18947 | /* CDE_VCX3A_fpdp */ |
| 18948 | 3268, |
| 18949 | /* CDE_VCX3A_fpsp */ |
| 18950 | 3274, |
| 18951 | /* CDE_VCX3A_vec */ |
| 18952 | 3280, |
| 18953 | /* CDE_VCX3_fpdp */ |
| 18954 | 3289, |
| 18955 | /* CDE_VCX3_fpsp */ |
| 18956 | 3294, |
| 18957 | /* CDE_VCX3_vec */ |
| 18958 | 3299, |
| 18959 | /* CDP */ |
| 18960 | 3308, |
| 18961 | /* CDP2 */ |
| 18962 | 3316, |
| 18963 | /* CLREX */ |
| 18964 | 3322, |
| 18965 | /* CLZ */ |
| 18966 | 3322, |
| 18967 | /* CMNri */ |
| 18968 | 3326, |
| 18969 | /* CMNzrr */ |
| 18970 | 3330, |
| 18971 | /* CMNzrsi */ |
| 18972 | 3334, |
| 18973 | /* CMNzrsr */ |
| 18974 | 3339, |
| 18975 | /* CMPri */ |
| 18976 | 3345, |
| 18977 | /* CMPrr */ |
| 18978 | 3349, |
| 18979 | /* CMPrsi */ |
| 18980 | 3353, |
| 18981 | /* CMPrsr */ |
| 18982 | 3358, |
| 18983 | /* CPS1p */ |
| 18984 | 3364, |
| 18985 | /* CPS2p */ |
| 18986 | 3365, |
| 18987 | /* CPS3p */ |
| 18988 | 3367, |
| 18989 | /* CRC32B */ |
| 18990 | 3370, |
| 18991 | /* CRC32CB */ |
| 18992 | 3373, |
| 18993 | /* CRC32CH */ |
| 18994 | 3376, |
| 18995 | /* CRC32CW */ |
| 18996 | 3379, |
| 18997 | /* CRC32H */ |
| 18998 | 3382, |
| 18999 | /* CRC32W */ |
| 19000 | 3385, |
| 19001 | /* DBG */ |
| 19002 | 3388, |
| 19003 | /* DMB */ |
| 19004 | 3391, |
| 19005 | /* DSB */ |
| 19006 | 3392, |
| 19007 | /* EORri */ |
| 19008 | 3393, |
| 19009 | /* EORrr */ |
| 19010 | 3399, |
| 19011 | /* EORrsi */ |
| 19012 | 3405, |
| 19013 | /* EORrsr */ |
| 19014 | 3412, |
| 19015 | /* ERET */ |
| 19016 | 3420, |
| 19017 | /* FCONSTD */ |
| 19018 | 3422, |
| 19019 | /* FCONSTH */ |
| 19020 | 3426, |
| 19021 | /* FCONSTS */ |
| 19022 | 3430, |
| 19023 | /* FLDMXDB_UPD */ |
| 19024 | 3434, |
| 19025 | /* FLDMXIA */ |
| 19026 | 3439, |
| 19027 | /* FLDMXIA_UPD */ |
| 19028 | 3443, |
| 19029 | /* FMSTAT */ |
| 19030 | 3448, |
| 19031 | /* FSTMXDB_UPD */ |
| 19032 | 3450, |
| 19033 | /* FSTMXIA */ |
| 19034 | 3455, |
| 19035 | /* FSTMXIA_UPD */ |
| 19036 | 3459, |
| 19037 | /* HINT */ |
| 19038 | 3464, |
| 19039 | /* HLT */ |
| 19040 | 3467, |
| 19041 | /* HVC */ |
| 19042 | 3468, |
| 19043 | /* ISB */ |
| 19044 | 3469, |
| 19045 | /* LDA */ |
| 19046 | 3470, |
| 19047 | /* LDAB */ |
| 19048 | 3474, |
| 19049 | /* LDAEX */ |
| 19050 | 3478, |
| 19051 | /* LDAEXB */ |
| 19052 | 3482, |
| 19053 | /* LDAEXD */ |
| 19054 | 3486, |
| 19055 | /* LDAEXH */ |
| 19056 | 3490, |
| 19057 | /* LDAH */ |
| 19058 | 3494, |
| 19059 | /* LDC2L_OFFSET */ |
| 19060 | 3498, |
| 19061 | /* LDC2L_OPTION */ |
| 19062 | 3502, |
| 19063 | /* LDC2L_POST */ |
| 19064 | 3506, |
| 19065 | /* LDC2L_PRE */ |
| 19066 | 3510, |
| 19067 | /* LDC2_OFFSET */ |
| 19068 | 3514, |
| 19069 | /* LDC2_OPTION */ |
| 19070 | 3518, |
| 19071 | /* LDC2_POST */ |
| 19072 | 3522, |
| 19073 | /* LDC2_PRE */ |
| 19074 | 3526, |
| 19075 | /* LDCL_OFFSET */ |
| 19076 | 3530, |
| 19077 | /* LDCL_OPTION */ |
| 19078 | 3536, |
| 19079 | /* LDCL_POST */ |
| 19080 | 3542, |
| 19081 | /* LDCL_PRE */ |
| 19082 | 3548, |
| 19083 | /* LDC_OFFSET */ |
| 19084 | 3554, |
| 19085 | /* LDC_OPTION */ |
| 19086 | 3560, |
| 19087 | /* LDC_POST */ |
| 19088 | 3566, |
| 19089 | /* LDC_PRE */ |
| 19090 | 3572, |
| 19091 | /* LDMDA */ |
| 19092 | 3578, |
| 19093 | /* LDMDA_UPD */ |
| 19094 | 3582, |
| 19095 | /* LDMDB */ |
| 19096 | 3587, |
| 19097 | /* LDMDB_UPD */ |
| 19098 | 3591, |
| 19099 | /* LDMIA */ |
| 19100 | 3596, |
| 19101 | /* LDMIA_UPD */ |
| 19102 | 3600, |
| 19103 | /* LDMIB */ |
| 19104 | 3605, |
| 19105 | /* LDMIB_UPD */ |
| 19106 | 3609, |
| 19107 | /* LDRBT_POST_IMM */ |
| 19108 | 3614, |
| 19109 | /* LDRBT_POST_REG */ |
| 19110 | 3621, |
| 19111 | /* LDRB_POST_IMM */ |
| 19112 | 3628, |
| 19113 | /* LDRB_POST_REG */ |
| 19114 | 3635, |
| 19115 | /* LDRB_PRE_IMM */ |
| 19116 | 3642, |
| 19117 | /* LDRB_PRE_REG */ |
| 19118 | 3648, |
| 19119 | /* LDRBi12 */ |
| 19120 | 3655, |
| 19121 | /* LDRBrs */ |
| 19122 | 3660, |
| 19123 | /* LDRD */ |
| 19124 | 3666, |
| 19125 | /* LDRD_POST */ |
| 19126 | 3673, |
| 19127 | /* LDRD_PRE */ |
| 19128 | 3681, |
| 19129 | /* LDREX */ |
| 19130 | 3689, |
| 19131 | /* LDREXB */ |
| 19132 | 3693, |
| 19133 | /* LDREXD */ |
| 19134 | 3697, |
| 19135 | /* LDREXH */ |
| 19136 | 3701, |
| 19137 | /* LDRH */ |
| 19138 | 3705, |
| 19139 | /* LDRHTi */ |
| 19140 | 3711, |
| 19141 | /* LDRHTr */ |
| 19142 | 3717, |
| 19143 | /* LDRH_POST */ |
| 19144 | 3724, |
| 19145 | /* LDRH_PRE */ |
| 19146 | 3731, |
| 19147 | /* LDRSB */ |
| 19148 | 3738, |
| 19149 | /* LDRSBTi */ |
| 19150 | 3744, |
| 19151 | /* LDRSBTr */ |
| 19152 | 3750, |
| 19153 | /* LDRSB_POST */ |
| 19154 | 3757, |
| 19155 | /* LDRSB_PRE */ |
| 19156 | 3764, |
| 19157 | /* LDRSH */ |
| 19158 | 3771, |
| 19159 | /* LDRSHTi */ |
| 19160 | 3777, |
| 19161 | /* LDRSHTr */ |
| 19162 | 3783, |
| 19163 | /* LDRSH_POST */ |
| 19164 | 3790, |
| 19165 | /* LDRSH_PRE */ |
| 19166 | 3797, |
| 19167 | /* LDRT_POST_IMM */ |
| 19168 | 3804, |
| 19169 | /* LDRT_POST_REG */ |
| 19170 | 3811, |
| 19171 | /* LDR_POST_IMM */ |
| 19172 | 3818, |
| 19173 | /* LDR_POST_REG */ |
| 19174 | 3825, |
| 19175 | /* LDR_PRE_IMM */ |
| 19176 | 3832, |
| 19177 | /* LDR_PRE_REG */ |
| 19178 | 3838, |
| 19179 | /* LDRcp */ |
| 19180 | 3845, |
| 19181 | /* LDRi12 */ |
| 19182 | 3850, |
| 19183 | /* LDRrs */ |
| 19184 | 3855, |
| 19185 | /* MCR */ |
| 19186 | 3861, |
| 19187 | /* MCR2 */ |
| 19188 | 3869, |
| 19189 | /* MCRR */ |
| 19190 | 3875, |
| 19191 | /* MCRR2 */ |
| 19192 | 3882, |
| 19193 | /* MLA */ |
| 19194 | 3887, |
| 19195 | /* MLS */ |
| 19196 | 3894, |
| 19197 | /* MOVPCLR */ |
| 19198 | 3900, |
| 19199 | /* MOVTi16 */ |
| 19200 | 3902, |
| 19201 | /* MOVi */ |
| 19202 | 3907, |
| 19203 | /* MOVi16 */ |
| 19204 | 3912, |
| 19205 | /* MOVr */ |
| 19206 | 3916, |
| 19207 | /* MOVr_TC */ |
| 19208 | 3921, |
| 19209 | /* MOVsi */ |
| 19210 | 3926, |
| 19211 | /* MOVsr */ |
| 19212 | 3932, |
| 19213 | /* MRC */ |
| 19214 | 3939, |
| 19215 | /* MRC2 */ |
| 19216 | 3947, |
| 19217 | /* MRRC */ |
| 19218 | 3953, |
| 19219 | /* MRRC2 */ |
| 19220 | 3960, |
| 19221 | /* MRS */ |
| 19222 | 3965, |
| 19223 | /* MRSbanked */ |
| 19224 | 3968, |
| 19225 | /* MRSsys */ |
| 19226 | 3972, |
| 19227 | /* MSR */ |
| 19228 | 3975, |
| 19229 | /* MSRbanked */ |
| 19230 | 3979, |
| 19231 | /* MSRi */ |
| 19232 | 3983, |
| 19233 | /* MUL */ |
| 19234 | 3987, |
| 19235 | /* MVE_ASRLi */ |
| 19236 | 3993, |
| 19237 | /* MVE_ASRLr */ |
| 19238 | 4000, |
| 19239 | /* MVE_DLSTP_16 */ |
| 19240 | 4007, |
| 19241 | /* MVE_DLSTP_32 */ |
| 19242 | 4009, |
| 19243 | /* MVE_DLSTP_64 */ |
| 19244 | 4011, |
| 19245 | /* MVE_DLSTP_8 */ |
| 19246 | 4013, |
| 19247 | /* MVE_LCTP */ |
| 19248 | 4015, |
| 19249 | /* MVE_LETP */ |
| 19250 | 4017, |
| 19251 | /* MVE_LSLLi */ |
| 19252 | 4020, |
| 19253 | /* MVE_LSLLr */ |
| 19254 | 4027, |
| 19255 | /* MVE_LSRL */ |
| 19256 | 4034, |
| 19257 | /* MVE_SQRSHR */ |
| 19258 | 4041, |
| 19259 | /* MVE_SQRSHRL */ |
| 19260 | 4046, |
| 19261 | /* MVE_SQSHL */ |
| 19262 | 4054, |
| 19263 | /* MVE_SQSHLL */ |
| 19264 | 4059, |
| 19265 | /* MVE_SRSHR */ |
| 19266 | 4066, |
| 19267 | /* MVE_SRSHRL */ |
| 19268 | 4071, |
| 19269 | /* MVE_UQRSHL */ |
| 19270 | 4078, |
| 19271 | /* MVE_UQRSHLL */ |
| 19272 | 4083, |
| 19273 | /* MVE_UQSHL */ |
| 19274 | 4091, |
| 19275 | /* MVE_UQSHLL */ |
| 19276 | 4096, |
| 19277 | /* MVE_URSHR */ |
| 19278 | 4103, |
| 19279 | /* MVE_URSHRL */ |
| 19280 | 4108, |
| 19281 | /* MVE_VABAVs16 */ |
| 19282 | 4115, |
| 19283 | /* MVE_VABAVs32 */ |
| 19284 | 4122, |
| 19285 | /* MVE_VABAVs8 */ |
| 19286 | 4129, |
| 19287 | /* MVE_VABAVu16 */ |
| 19288 | 4136, |
| 19289 | /* MVE_VABAVu32 */ |
| 19290 | 4143, |
| 19291 | /* MVE_VABAVu8 */ |
| 19292 | 4150, |
| 19293 | /* MVE_VABDf16 */ |
| 19294 | 4157, |
| 19295 | /* MVE_VABDf32 */ |
| 19296 | 4164, |
| 19297 | /* MVE_VABDs16 */ |
| 19298 | 4171, |
| 19299 | /* MVE_VABDs32 */ |
| 19300 | 4178, |
| 19301 | /* MVE_VABDs8 */ |
| 19302 | 4185, |
| 19303 | /* MVE_VABDu16 */ |
| 19304 | 4192, |
| 19305 | /* MVE_VABDu32 */ |
| 19306 | 4199, |
| 19307 | /* MVE_VABDu8 */ |
| 19308 | 4206, |
| 19309 | /* MVE_VABSf16 */ |
| 19310 | 4213, |
| 19311 | /* MVE_VABSf32 */ |
| 19312 | 4219, |
| 19313 | /* MVE_VABSs16 */ |
| 19314 | 4225, |
| 19315 | /* MVE_VABSs32 */ |
| 19316 | 4231, |
| 19317 | /* MVE_VABSs8 */ |
| 19318 | 4237, |
| 19319 | /* MVE_VADC */ |
| 19320 | 4243, |
| 19321 | /* MVE_VADCI */ |
| 19322 | 4252, |
| 19323 | /* MVE_VADDLVs32acc */ |
| 19324 | 4260, |
| 19325 | /* MVE_VADDLVs32no_acc */ |
| 19326 | 4268, |
| 19327 | /* MVE_VADDLVu32acc */ |
| 19328 | 4274, |
| 19329 | /* MVE_VADDLVu32no_acc */ |
| 19330 | 4282, |
| 19331 | /* MVE_VADDVs16acc */ |
| 19332 | 4288, |
| 19333 | /* MVE_VADDVs16no_acc */ |
| 19334 | 4294, |
| 19335 | /* MVE_VADDVs32acc */ |
| 19336 | 4299, |
| 19337 | /* MVE_VADDVs32no_acc */ |
| 19338 | 4305, |
| 19339 | /* MVE_VADDVs8acc */ |
| 19340 | 4310, |
| 19341 | /* MVE_VADDVs8no_acc */ |
| 19342 | 4316, |
| 19343 | /* MVE_VADDVu16acc */ |
| 19344 | 4321, |
| 19345 | /* MVE_VADDVu16no_acc */ |
| 19346 | 4327, |
| 19347 | /* MVE_VADDVu32acc */ |
| 19348 | 4332, |
| 19349 | /* MVE_VADDVu32no_acc */ |
| 19350 | 4338, |
| 19351 | /* MVE_VADDVu8acc */ |
| 19352 | 4343, |
| 19353 | /* MVE_VADDVu8no_acc */ |
| 19354 | 4349, |
| 19355 | /* MVE_VADD_qr_f16 */ |
| 19356 | 4354, |
| 19357 | /* MVE_VADD_qr_f32 */ |
| 19358 | 4361, |
| 19359 | /* MVE_VADD_qr_i16 */ |
| 19360 | 4368, |
| 19361 | /* MVE_VADD_qr_i32 */ |
| 19362 | 4375, |
| 19363 | /* MVE_VADD_qr_i8 */ |
| 19364 | 4382, |
| 19365 | /* MVE_VADDf16 */ |
| 19366 | 4389, |
| 19367 | /* MVE_VADDf32 */ |
| 19368 | 4396, |
| 19369 | /* MVE_VADDi16 */ |
| 19370 | 4403, |
| 19371 | /* MVE_VADDi32 */ |
| 19372 | 4410, |
| 19373 | /* MVE_VADDi8 */ |
| 19374 | 4417, |
| 19375 | /* MVE_VAND */ |
| 19376 | 4424, |
| 19377 | /* MVE_VBIC */ |
| 19378 | 4431, |
| 19379 | /* MVE_VBICimmi16 */ |
| 19380 | 4438, |
| 19381 | /* MVE_VBICimmi32 */ |
| 19382 | 4444, |
| 19383 | /* MVE_VBRSR16 */ |
| 19384 | 4450, |
| 19385 | /* MVE_VBRSR32 */ |
| 19386 | 4457, |
| 19387 | /* MVE_VBRSR8 */ |
| 19388 | 4464, |
| 19389 | /* MVE_VCADDf16 */ |
| 19390 | 4471, |
| 19391 | /* MVE_VCADDf32 */ |
| 19392 | 4479, |
| 19393 | /* MVE_VCADDi16 */ |
| 19394 | 4487, |
| 19395 | /* MVE_VCADDi32 */ |
| 19396 | 4495, |
| 19397 | /* MVE_VCADDi8 */ |
| 19398 | 4503, |
| 19399 | /* MVE_VCLSs16 */ |
| 19400 | 4511, |
| 19401 | /* MVE_VCLSs32 */ |
| 19402 | 4517, |
| 19403 | /* MVE_VCLSs8 */ |
| 19404 | 4523, |
| 19405 | /* MVE_VCLZs16 */ |
| 19406 | 4529, |
| 19407 | /* MVE_VCLZs32 */ |
| 19408 | 4535, |
| 19409 | /* MVE_VCLZs8 */ |
| 19410 | 4541, |
| 19411 | /* MVE_VCMLAf16 */ |
| 19412 | 4547, |
| 19413 | /* MVE_VCMLAf32 */ |
| 19414 | 4555, |
| 19415 | /* MVE_VCMPf16 */ |
| 19416 | 4563, |
| 19417 | /* MVE_VCMPf16r */ |
| 19418 | 4570, |
| 19419 | /* MVE_VCMPf32 */ |
| 19420 | 4577, |
| 19421 | /* MVE_VCMPf32r */ |
| 19422 | 4584, |
| 19423 | /* MVE_VCMPi16 */ |
| 19424 | 4591, |
| 19425 | /* MVE_VCMPi16r */ |
| 19426 | 4598, |
| 19427 | /* MVE_VCMPi32 */ |
| 19428 | 4605, |
| 19429 | /* MVE_VCMPi32r */ |
| 19430 | 4612, |
| 19431 | /* MVE_VCMPi8 */ |
| 19432 | 4619, |
| 19433 | /* MVE_VCMPi8r */ |
| 19434 | 4626, |
| 19435 | /* MVE_VCMPs16 */ |
| 19436 | 4633, |
| 19437 | /* MVE_VCMPs16r */ |
| 19438 | 4640, |
| 19439 | /* MVE_VCMPs32 */ |
| 19440 | 4647, |
| 19441 | /* MVE_VCMPs32r */ |
| 19442 | 4654, |
| 19443 | /* MVE_VCMPs8 */ |
| 19444 | 4661, |
| 19445 | /* MVE_VCMPs8r */ |
| 19446 | 4668, |
| 19447 | /* MVE_VCMPu16 */ |
| 19448 | 4675, |
| 19449 | /* MVE_VCMPu16r */ |
| 19450 | 4682, |
| 19451 | /* MVE_VCMPu32 */ |
| 19452 | 4689, |
| 19453 | /* MVE_VCMPu32r */ |
| 19454 | 4696, |
| 19455 | /* MVE_VCMPu8 */ |
| 19456 | 4703, |
| 19457 | /* MVE_VCMPu8r */ |
| 19458 | 4710, |
| 19459 | /* MVE_VCMULf16 */ |
| 19460 | 4717, |
| 19461 | /* MVE_VCMULf32 */ |
| 19462 | 4725, |
| 19463 | /* MVE_VCTP16 */ |
| 19464 | 4733, |
| 19465 | /* MVE_VCTP32 */ |
| 19466 | 4738, |
| 19467 | /* MVE_VCTP64 */ |
| 19468 | 4743, |
| 19469 | /* MVE_VCTP8 */ |
| 19470 | 4748, |
| 19471 | /* MVE_VCVTf16f32bh */ |
| 19472 | 4753, |
| 19473 | /* MVE_VCVTf16f32th */ |
| 19474 | 4759, |
| 19475 | /* MVE_VCVTf16s16_fix */ |
| 19476 | 4765, |
| 19477 | /* MVE_VCVTf16s16n */ |
| 19478 | 4772, |
| 19479 | /* MVE_VCVTf16u16_fix */ |
| 19480 | 4778, |
| 19481 | /* MVE_VCVTf16u16n */ |
| 19482 | 4785, |
| 19483 | /* MVE_VCVTf32f16bh */ |
| 19484 | 4791, |
| 19485 | /* MVE_VCVTf32f16th */ |
| 19486 | 4797, |
| 19487 | /* MVE_VCVTf32s32_fix */ |
| 19488 | 4803, |
| 19489 | /* MVE_VCVTf32s32n */ |
| 19490 | 4810, |
| 19491 | /* MVE_VCVTf32u32_fix */ |
| 19492 | 4816, |
| 19493 | /* MVE_VCVTf32u32n */ |
| 19494 | 4823, |
| 19495 | /* MVE_VCVTs16f16_fix */ |
| 19496 | 4829, |
| 19497 | /* MVE_VCVTs16f16a */ |
| 19498 | 4836, |
| 19499 | /* MVE_VCVTs16f16m */ |
| 19500 | 4842, |
| 19501 | /* MVE_VCVTs16f16n */ |
| 19502 | 4848, |
| 19503 | /* MVE_VCVTs16f16p */ |
| 19504 | 4854, |
| 19505 | /* MVE_VCVTs16f16z */ |
| 19506 | 4860, |
| 19507 | /* MVE_VCVTs32f32_fix */ |
| 19508 | 4866, |
| 19509 | /* MVE_VCVTs32f32a */ |
| 19510 | 4873, |
| 19511 | /* MVE_VCVTs32f32m */ |
| 19512 | 4879, |
| 19513 | /* MVE_VCVTs32f32n */ |
| 19514 | 4885, |
| 19515 | /* MVE_VCVTs32f32p */ |
| 19516 | 4891, |
| 19517 | /* MVE_VCVTs32f32z */ |
| 19518 | 4897, |
| 19519 | /* MVE_VCVTu16f16_fix */ |
| 19520 | 4903, |
| 19521 | /* MVE_VCVTu16f16a */ |
| 19522 | 4910, |
| 19523 | /* MVE_VCVTu16f16m */ |
| 19524 | 4916, |
| 19525 | /* MVE_VCVTu16f16n */ |
| 19526 | 4922, |
| 19527 | /* MVE_VCVTu16f16p */ |
| 19528 | 4928, |
| 19529 | /* MVE_VCVTu16f16z */ |
| 19530 | 4934, |
| 19531 | /* MVE_VCVTu32f32_fix */ |
| 19532 | 4940, |
| 19533 | /* MVE_VCVTu32f32a */ |
| 19534 | 4947, |
| 19535 | /* MVE_VCVTu32f32m */ |
| 19536 | 4953, |
| 19537 | /* MVE_VCVTu32f32n */ |
| 19538 | 4959, |
| 19539 | /* MVE_VCVTu32f32p */ |
| 19540 | 4965, |
| 19541 | /* MVE_VCVTu32f32z */ |
| 19542 | 4971, |
| 19543 | /* MVE_VDDUPu16 */ |
| 19544 | 4977, |
| 19545 | /* MVE_VDDUPu32 */ |
| 19546 | 4985, |
| 19547 | /* MVE_VDDUPu8 */ |
| 19548 | 4993, |
| 19549 | /* MVE_VDUP16 */ |
| 19550 | 5001, |
| 19551 | /* MVE_VDUP32 */ |
| 19552 | 5007, |
| 19553 | /* MVE_VDUP8 */ |
| 19554 | 5013, |
| 19555 | /* MVE_VDWDUPu16 */ |
| 19556 | 5019, |
| 19557 | /* MVE_VDWDUPu32 */ |
| 19558 | 5028, |
| 19559 | /* MVE_VDWDUPu8 */ |
| 19560 | 5037, |
| 19561 | /* MVE_VEOR */ |
| 19562 | 5046, |
| 19563 | /* MVE_VFMA_qr_Sf16 */ |
| 19564 | 5053, |
| 19565 | /* MVE_VFMA_qr_Sf32 */ |
| 19566 | 5060, |
| 19567 | /* MVE_VFMA_qr_f16 */ |
| 19568 | 5067, |
| 19569 | /* MVE_VFMA_qr_f32 */ |
| 19570 | 5074, |
| 19571 | /* MVE_VFMAf16 */ |
| 19572 | 5081, |
| 19573 | /* MVE_VFMAf32 */ |
| 19574 | 5088, |
| 19575 | /* MVE_VFMSf16 */ |
| 19576 | 5095, |
| 19577 | /* MVE_VFMSf32 */ |
| 19578 | 5102, |
| 19579 | /* MVE_VHADD_qr_s16 */ |
| 19580 | 5109, |
| 19581 | /* MVE_VHADD_qr_s32 */ |
| 19582 | 5116, |
| 19583 | /* MVE_VHADD_qr_s8 */ |
| 19584 | 5123, |
| 19585 | /* MVE_VHADD_qr_u16 */ |
| 19586 | 5130, |
| 19587 | /* MVE_VHADD_qr_u32 */ |
| 19588 | 5137, |
| 19589 | /* MVE_VHADD_qr_u8 */ |
| 19590 | 5144, |
| 19591 | /* MVE_VHADDs16 */ |
| 19592 | 5151, |
| 19593 | /* MVE_VHADDs32 */ |
| 19594 | 5158, |
| 19595 | /* MVE_VHADDs8 */ |
| 19596 | 5165, |
| 19597 | /* MVE_VHADDu16 */ |
| 19598 | 5172, |
| 19599 | /* MVE_VHADDu32 */ |
| 19600 | 5179, |
| 19601 | /* MVE_VHADDu8 */ |
| 19602 | 5186, |
| 19603 | /* MVE_VHCADDs16 */ |
| 19604 | 5193, |
| 19605 | /* MVE_VHCADDs32 */ |
| 19606 | 5201, |
| 19607 | /* MVE_VHCADDs8 */ |
| 19608 | 5209, |
| 19609 | /* MVE_VHSUB_qr_s16 */ |
| 19610 | 5217, |
| 19611 | /* MVE_VHSUB_qr_s32 */ |
| 19612 | 5224, |
| 19613 | /* MVE_VHSUB_qr_s8 */ |
| 19614 | 5231, |
| 19615 | /* MVE_VHSUB_qr_u16 */ |
| 19616 | 5238, |
| 19617 | /* MVE_VHSUB_qr_u32 */ |
| 19618 | 5245, |
| 19619 | /* MVE_VHSUB_qr_u8 */ |
| 19620 | 5252, |
| 19621 | /* MVE_VHSUBs16 */ |
| 19622 | 5259, |
| 19623 | /* MVE_VHSUBs32 */ |
| 19624 | 5266, |
| 19625 | /* MVE_VHSUBs8 */ |
| 19626 | 5273, |
| 19627 | /* MVE_VHSUBu16 */ |
| 19628 | 5280, |
| 19629 | /* MVE_VHSUBu32 */ |
| 19630 | 5287, |
| 19631 | /* MVE_VHSUBu8 */ |
| 19632 | 5294, |
| 19633 | /* MVE_VIDUPu16 */ |
| 19634 | 5301, |
| 19635 | /* MVE_VIDUPu32 */ |
| 19636 | 5309, |
| 19637 | /* MVE_VIDUPu8 */ |
| 19638 | 5317, |
| 19639 | /* MVE_VIWDUPu16 */ |
| 19640 | 5325, |
| 19641 | /* MVE_VIWDUPu32 */ |
| 19642 | 5334, |
| 19643 | /* MVE_VIWDUPu8 */ |
| 19644 | 5343, |
| 19645 | /* MVE_VLD20_16 */ |
| 19646 | 5352, |
| 19647 | /* MVE_VLD20_16_wb */ |
| 19648 | 5355, |
| 19649 | /* MVE_VLD20_32 */ |
| 19650 | 5359, |
| 19651 | /* MVE_VLD20_32_wb */ |
| 19652 | 5362, |
| 19653 | /* MVE_VLD20_8 */ |
| 19654 | 5366, |
| 19655 | /* MVE_VLD20_8_wb */ |
| 19656 | 5369, |
| 19657 | /* MVE_VLD21_16 */ |
| 19658 | 5373, |
| 19659 | /* MVE_VLD21_16_wb */ |
| 19660 | 5376, |
| 19661 | /* MVE_VLD21_32 */ |
| 19662 | 5380, |
| 19663 | /* MVE_VLD21_32_wb */ |
| 19664 | 5383, |
| 19665 | /* MVE_VLD21_8 */ |
| 19666 | 5387, |
| 19667 | /* MVE_VLD21_8_wb */ |
| 19668 | 5390, |
| 19669 | /* MVE_VLD40_16 */ |
| 19670 | 5394, |
| 19671 | /* MVE_VLD40_16_wb */ |
| 19672 | 5397, |
| 19673 | /* MVE_VLD40_32 */ |
| 19674 | 5401, |
| 19675 | /* MVE_VLD40_32_wb */ |
| 19676 | 5404, |
| 19677 | /* MVE_VLD40_8 */ |
| 19678 | 5408, |
| 19679 | /* MVE_VLD40_8_wb */ |
| 19680 | 5411, |
| 19681 | /* MVE_VLD41_16 */ |
| 19682 | 5415, |
| 19683 | /* MVE_VLD41_16_wb */ |
| 19684 | 5418, |
| 19685 | /* MVE_VLD41_32 */ |
| 19686 | 5422, |
| 19687 | /* MVE_VLD41_32_wb */ |
| 19688 | 5425, |
| 19689 | /* MVE_VLD41_8 */ |
| 19690 | 5429, |
| 19691 | /* MVE_VLD41_8_wb */ |
| 19692 | 5432, |
| 19693 | /* MVE_VLD42_16 */ |
| 19694 | 5436, |
| 19695 | /* MVE_VLD42_16_wb */ |
| 19696 | 5439, |
| 19697 | /* MVE_VLD42_32 */ |
| 19698 | 5443, |
| 19699 | /* MVE_VLD42_32_wb */ |
| 19700 | 5446, |
| 19701 | /* MVE_VLD42_8 */ |
| 19702 | 5450, |
| 19703 | /* MVE_VLD42_8_wb */ |
| 19704 | 5453, |
| 19705 | /* MVE_VLD43_16 */ |
| 19706 | 5457, |
| 19707 | /* MVE_VLD43_16_wb */ |
| 19708 | 5460, |
| 19709 | /* MVE_VLD43_32 */ |
| 19710 | 5464, |
| 19711 | /* MVE_VLD43_32_wb */ |
| 19712 | 5467, |
| 19713 | /* MVE_VLD43_8 */ |
| 19714 | 5471, |
| 19715 | /* MVE_VLD43_8_wb */ |
| 19716 | 5474, |
| 19717 | /* MVE_VLDRBS16 */ |
| 19718 | 5478, |
| 19719 | /* MVE_VLDRBS16_post */ |
| 19720 | 5484, |
| 19721 | /* MVE_VLDRBS16_pre */ |
| 19722 | 5491, |
| 19723 | /* MVE_VLDRBS16_rq */ |
| 19724 | 5498, |
| 19725 | /* MVE_VLDRBS32 */ |
| 19726 | 5504, |
| 19727 | /* MVE_VLDRBS32_post */ |
| 19728 | 5510, |
| 19729 | /* MVE_VLDRBS32_pre */ |
| 19730 | 5517, |
| 19731 | /* MVE_VLDRBS32_rq */ |
| 19732 | 5524, |
| 19733 | /* MVE_VLDRBU16 */ |
| 19734 | 5530, |
| 19735 | /* MVE_VLDRBU16_post */ |
| 19736 | 5536, |
| 19737 | /* MVE_VLDRBU16_pre */ |
| 19738 | 5543, |
| 19739 | /* MVE_VLDRBU16_rq */ |
| 19740 | 5550, |
| 19741 | /* MVE_VLDRBU32 */ |
| 19742 | 5556, |
| 19743 | /* MVE_VLDRBU32_post */ |
| 19744 | 5562, |
| 19745 | /* MVE_VLDRBU32_pre */ |
| 19746 | 5569, |
| 19747 | /* MVE_VLDRBU32_rq */ |
| 19748 | 5576, |
| 19749 | /* MVE_VLDRBU8 */ |
| 19750 | 5582, |
| 19751 | /* MVE_VLDRBU8_post */ |
| 19752 | 5588, |
| 19753 | /* MVE_VLDRBU8_pre */ |
| 19754 | 5595, |
| 19755 | /* MVE_VLDRBU8_rq */ |
| 19756 | 5602, |
| 19757 | /* MVE_VLDRDU64_qi */ |
| 19758 | 5608, |
| 19759 | /* MVE_VLDRDU64_qi_pre */ |
| 19760 | 5614, |
| 19761 | /* MVE_VLDRDU64_rq */ |
| 19762 | 5621, |
| 19763 | /* MVE_VLDRDU64_rq_u */ |
| 19764 | 5627, |
| 19765 | /* MVE_VLDRHS32 */ |
| 19766 | 5633, |
| 19767 | /* MVE_VLDRHS32_post */ |
| 19768 | 5639, |
| 19769 | /* MVE_VLDRHS32_pre */ |
| 19770 | 5646, |
| 19771 | /* MVE_VLDRHS32_rq */ |
| 19772 | 5653, |
| 19773 | /* MVE_VLDRHS32_rq_u */ |
| 19774 | 5659, |
| 19775 | /* MVE_VLDRHU16 */ |
| 19776 | 5665, |
| 19777 | /* MVE_VLDRHU16_post */ |
| 19778 | 5671, |
| 19779 | /* MVE_VLDRHU16_pre */ |
| 19780 | 5678, |
| 19781 | /* MVE_VLDRHU16_rq */ |
| 19782 | 5685, |
| 19783 | /* MVE_VLDRHU16_rq_u */ |
| 19784 | 5691, |
| 19785 | /* MVE_VLDRHU32 */ |
| 19786 | 5697, |
| 19787 | /* MVE_VLDRHU32_post */ |
| 19788 | 5703, |
| 19789 | /* MVE_VLDRHU32_pre */ |
| 19790 | 5710, |
| 19791 | /* MVE_VLDRHU32_rq */ |
| 19792 | 5717, |
| 19793 | /* MVE_VLDRHU32_rq_u */ |
| 19794 | 5723, |
| 19795 | /* MVE_VLDRWU32 */ |
| 19796 | 5729, |
| 19797 | /* MVE_VLDRWU32_post */ |
| 19798 | 5735, |
| 19799 | /* MVE_VLDRWU32_pre */ |
| 19800 | 5742, |
| 19801 | /* MVE_VLDRWU32_qi */ |
| 19802 | 5749, |
| 19803 | /* MVE_VLDRWU32_qi_pre */ |
| 19804 | 5755, |
| 19805 | /* MVE_VLDRWU32_rq */ |
| 19806 | 5762, |
| 19807 | /* MVE_VLDRWU32_rq_u */ |
| 19808 | 5768, |
| 19809 | /* MVE_VMAXAVs16 */ |
| 19810 | 5774, |
| 19811 | /* MVE_VMAXAVs32 */ |
| 19812 | 5780, |
| 19813 | /* MVE_VMAXAVs8 */ |
| 19814 | 5786, |
| 19815 | /* MVE_VMAXAs16 */ |
| 19816 | 5792, |
| 19817 | /* MVE_VMAXAs32 */ |
| 19818 | 5798, |
| 19819 | /* MVE_VMAXAs8 */ |
| 19820 | 5804, |
| 19821 | /* MVE_VMAXNMAVf16 */ |
| 19822 | 5810, |
| 19823 | /* MVE_VMAXNMAVf32 */ |
| 19824 | 5816, |
| 19825 | /* MVE_VMAXNMAf16 */ |
| 19826 | 5822, |
| 19827 | /* MVE_VMAXNMAf32 */ |
| 19828 | 5828, |
| 19829 | /* MVE_VMAXNMVf16 */ |
| 19830 | 5834, |
| 19831 | /* MVE_VMAXNMVf32 */ |
| 19832 | 5840, |
| 19833 | /* MVE_VMAXNMf16 */ |
| 19834 | 5846, |
| 19835 | /* MVE_VMAXNMf32 */ |
| 19836 | 5853, |
| 19837 | /* MVE_VMAXVs16 */ |
| 19838 | 5860, |
| 19839 | /* MVE_VMAXVs32 */ |
| 19840 | 5866, |
| 19841 | /* MVE_VMAXVs8 */ |
| 19842 | 5872, |
| 19843 | /* MVE_VMAXVu16 */ |
| 19844 | 5878, |
| 19845 | /* MVE_VMAXVu32 */ |
| 19846 | 5884, |
| 19847 | /* MVE_VMAXVu8 */ |
| 19848 | 5890, |
| 19849 | /* MVE_VMAXs16 */ |
| 19850 | 5896, |
| 19851 | /* MVE_VMAXs32 */ |
| 19852 | 5903, |
| 19853 | /* MVE_VMAXs8 */ |
| 19854 | 5910, |
| 19855 | /* MVE_VMAXu16 */ |
| 19856 | 5917, |
| 19857 | /* MVE_VMAXu32 */ |
| 19858 | 5924, |
| 19859 | /* MVE_VMAXu8 */ |
| 19860 | 5931, |
| 19861 | /* MVE_VMINAVs16 */ |
| 19862 | 5938, |
| 19863 | /* MVE_VMINAVs32 */ |
| 19864 | 5944, |
| 19865 | /* MVE_VMINAVs8 */ |
| 19866 | 5950, |
| 19867 | /* MVE_VMINAs16 */ |
| 19868 | 5956, |
| 19869 | /* MVE_VMINAs32 */ |
| 19870 | 5962, |
| 19871 | /* MVE_VMINAs8 */ |
| 19872 | 5968, |
| 19873 | /* MVE_VMINNMAVf16 */ |
| 19874 | 5974, |
| 19875 | /* MVE_VMINNMAVf32 */ |
| 19876 | 5980, |
| 19877 | /* MVE_VMINNMAf16 */ |
| 19878 | 5986, |
| 19879 | /* MVE_VMINNMAf32 */ |
| 19880 | 5992, |
| 19881 | /* MVE_VMINNMVf16 */ |
| 19882 | 5998, |
| 19883 | /* MVE_VMINNMVf32 */ |
| 19884 | 6004, |
| 19885 | /* MVE_VMINNMf16 */ |
| 19886 | 6010, |
| 19887 | /* MVE_VMINNMf32 */ |
| 19888 | 6017, |
| 19889 | /* MVE_VMINVs16 */ |
| 19890 | 6024, |
| 19891 | /* MVE_VMINVs32 */ |
| 19892 | 6030, |
| 19893 | /* MVE_VMINVs8 */ |
| 19894 | 6036, |
| 19895 | /* MVE_VMINVu16 */ |
| 19896 | 6042, |
| 19897 | /* MVE_VMINVu32 */ |
| 19898 | 6048, |
| 19899 | /* MVE_VMINVu8 */ |
| 19900 | 6054, |
| 19901 | /* MVE_VMINs16 */ |
| 19902 | 6060, |
| 19903 | /* MVE_VMINs32 */ |
| 19904 | 6067, |
| 19905 | /* MVE_VMINs8 */ |
| 19906 | 6074, |
| 19907 | /* MVE_VMINu16 */ |
| 19908 | 6081, |
| 19909 | /* MVE_VMINu32 */ |
| 19910 | 6088, |
| 19911 | /* MVE_VMINu8 */ |
| 19912 | 6095, |
| 19913 | /* MVE_VMLADAVas16 */ |
| 19914 | 6102, |
| 19915 | /* MVE_VMLADAVas32 */ |
| 19916 | 6109, |
| 19917 | /* MVE_VMLADAVas8 */ |
| 19918 | 6116, |
| 19919 | /* MVE_VMLADAVau16 */ |
| 19920 | 6123, |
| 19921 | /* MVE_VMLADAVau32 */ |
| 19922 | 6130, |
| 19923 | /* MVE_VMLADAVau8 */ |
| 19924 | 6137, |
| 19925 | /* MVE_VMLADAVaxs16 */ |
| 19926 | 6144, |
| 19927 | /* MVE_VMLADAVaxs32 */ |
| 19928 | 6151, |
| 19929 | /* MVE_VMLADAVaxs8 */ |
| 19930 | 6158, |
| 19931 | /* MVE_VMLADAVs16 */ |
| 19932 | 6165, |
| 19933 | /* MVE_VMLADAVs32 */ |
| 19934 | 6171, |
| 19935 | /* MVE_VMLADAVs8 */ |
| 19936 | 6177, |
| 19937 | /* MVE_VMLADAVu16 */ |
| 19938 | 6183, |
| 19939 | /* MVE_VMLADAVu32 */ |
| 19940 | 6189, |
| 19941 | /* MVE_VMLADAVu8 */ |
| 19942 | 6195, |
| 19943 | /* MVE_VMLADAVxs16 */ |
| 19944 | 6201, |
| 19945 | /* MVE_VMLADAVxs32 */ |
| 19946 | 6207, |
| 19947 | /* MVE_VMLADAVxs8 */ |
| 19948 | 6213, |
| 19949 | /* MVE_VMLALDAVas16 */ |
| 19950 | 6219, |
| 19951 | /* MVE_VMLALDAVas32 */ |
| 19952 | 6228, |
| 19953 | /* MVE_VMLALDAVau16 */ |
| 19954 | 6237, |
| 19955 | /* MVE_VMLALDAVau32 */ |
| 19956 | 6246, |
| 19957 | /* MVE_VMLALDAVaxs16 */ |
| 19958 | 6255, |
| 19959 | /* MVE_VMLALDAVaxs32 */ |
| 19960 | 6264, |
| 19961 | /* MVE_VMLALDAVs16 */ |
| 19962 | 6273, |
| 19963 | /* MVE_VMLALDAVs32 */ |
| 19964 | 6280, |
| 19965 | /* MVE_VMLALDAVu16 */ |
| 19966 | 6287, |
| 19967 | /* MVE_VMLALDAVu32 */ |
| 19968 | 6294, |
| 19969 | /* MVE_VMLALDAVxs16 */ |
| 19970 | 6301, |
| 19971 | /* MVE_VMLALDAVxs32 */ |
| 19972 | 6308, |
| 19973 | /* MVE_VMLAS_qr_i16 */ |
| 19974 | 6315, |
| 19975 | /* MVE_VMLAS_qr_i32 */ |
| 19976 | 6322, |
| 19977 | /* MVE_VMLAS_qr_i8 */ |
| 19978 | 6329, |
| 19979 | /* MVE_VMLA_qr_i16 */ |
| 19980 | 6336, |
| 19981 | /* MVE_VMLA_qr_i32 */ |
| 19982 | 6343, |
| 19983 | /* MVE_VMLA_qr_i8 */ |
| 19984 | 6350, |
| 19985 | /* MVE_VMLSDAVas16 */ |
| 19986 | 6357, |
| 19987 | /* MVE_VMLSDAVas32 */ |
| 19988 | 6364, |
| 19989 | /* MVE_VMLSDAVas8 */ |
| 19990 | 6371, |
| 19991 | /* MVE_VMLSDAVaxs16 */ |
| 19992 | 6378, |
| 19993 | /* MVE_VMLSDAVaxs32 */ |
| 19994 | 6385, |
| 19995 | /* MVE_VMLSDAVaxs8 */ |
| 19996 | 6392, |
| 19997 | /* MVE_VMLSDAVs16 */ |
| 19998 | 6399, |
| 19999 | /* MVE_VMLSDAVs32 */ |
| 20000 | 6405, |
| 20001 | /* MVE_VMLSDAVs8 */ |
| 20002 | 6411, |
| 20003 | /* MVE_VMLSDAVxs16 */ |
| 20004 | 6417, |
| 20005 | /* MVE_VMLSDAVxs32 */ |
| 20006 | 6423, |
| 20007 | /* MVE_VMLSDAVxs8 */ |
| 20008 | 6429, |
| 20009 | /* MVE_VMLSLDAVas16 */ |
| 20010 | 6435, |
| 20011 | /* MVE_VMLSLDAVas32 */ |
| 20012 | 6444, |
| 20013 | /* MVE_VMLSLDAVaxs16 */ |
| 20014 | 6453, |
| 20015 | /* MVE_VMLSLDAVaxs32 */ |
| 20016 | 6462, |
| 20017 | /* MVE_VMLSLDAVs16 */ |
| 20018 | 6471, |
| 20019 | /* MVE_VMLSLDAVs32 */ |
| 20020 | 6478, |
| 20021 | /* MVE_VMLSLDAVxs16 */ |
| 20022 | 6485, |
| 20023 | /* MVE_VMLSLDAVxs32 */ |
| 20024 | 6492, |
| 20025 | /* MVE_VMOVLs16bh */ |
| 20026 | 6499, |
| 20027 | /* MVE_VMOVLs16th */ |
| 20028 | 6505, |
| 20029 | /* MVE_VMOVLs8bh */ |
| 20030 | 6511, |
| 20031 | /* MVE_VMOVLs8th */ |
| 20032 | 6517, |
| 20033 | /* MVE_VMOVLu16bh */ |
| 20034 | 6523, |
| 20035 | /* MVE_VMOVLu16th */ |
| 20036 | 6529, |
| 20037 | /* MVE_VMOVLu8bh */ |
| 20038 | 6535, |
| 20039 | /* MVE_VMOVLu8th */ |
| 20040 | 6541, |
| 20041 | /* MVE_VMOVNi16bh */ |
| 20042 | 6547, |
| 20043 | /* MVE_VMOVNi16th */ |
| 20044 | 6553, |
| 20045 | /* MVE_VMOVNi32bh */ |
| 20046 | 6559, |
| 20047 | /* MVE_VMOVNi32th */ |
| 20048 | 6565, |
| 20049 | /* MVE_VMOV_from_lane_32 */ |
| 20050 | 6571, |
| 20051 | /* MVE_VMOV_from_lane_s16 */ |
| 20052 | 6576, |
| 20053 | /* MVE_VMOV_from_lane_s8 */ |
| 20054 | 6581, |
| 20055 | /* MVE_VMOV_from_lane_u16 */ |
| 20056 | 6586, |
| 20057 | /* MVE_VMOV_from_lane_u8 */ |
| 20058 | 6591, |
| 20059 | /* MVE_VMOV_q_rr */ |
| 20060 | 6596, |
| 20061 | /* MVE_VMOV_rr_q */ |
| 20062 | 6604, |
| 20063 | /* MVE_VMOV_to_lane_16 */ |
| 20064 | 6611, |
| 20065 | /* MVE_VMOV_to_lane_32 */ |
| 20066 | 6617, |
| 20067 | /* MVE_VMOV_to_lane_8 */ |
| 20068 | 6623, |
| 20069 | /* MVE_VMOVimmf32 */ |
| 20070 | 6629, |
| 20071 | /* MVE_VMOVimmi16 */ |
| 20072 | 6635, |
| 20073 | /* MVE_VMOVimmi32 */ |
| 20074 | 6641, |
| 20075 | /* MVE_VMOVimmi64 */ |
| 20076 | 6647, |
| 20077 | /* MVE_VMOVimmi8 */ |
| 20078 | 6653, |
| 20079 | /* MVE_VMULHs16 */ |
| 20080 | 6659, |
| 20081 | /* MVE_VMULHs32 */ |
| 20082 | 6666, |
| 20083 | /* MVE_VMULHs8 */ |
| 20084 | 6673, |
| 20085 | /* MVE_VMULHu16 */ |
| 20086 | 6680, |
| 20087 | /* MVE_VMULHu32 */ |
| 20088 | 6687, |
| 20089 | /* MVE_VMULHu8 */ |
| 20090 | 6694, |
| 20091 | /* MVE_VMULLBp16 */ |
| 20092 | 6701, |
| 20093 | /* MVE_VMULLBp8 */ |
| 20094 | 6708, |
| 20095 | /* MVE_VMULLBs16 */ |
| 20096 | 6715, |
| 20097 | /* MVE_VMULLBs32 */ |
| 20098 | 6722, |
| 20099 | /* MVE_VMULLBs8 */ |
| 20100 | 6729, |
| 20101 | /* MVE_VMULLBu16 */ |
| 20102 | 6736, |
| 20103 | /* MVE_VMULLBu32 */ |
| 20104 | 6743, |
| 20105 | /* MVE_VMULLBu8 */ |
| 20106 | 6750, |
| 20107 | /* MVE_VMULLTp16 */ |
| 20108 | 6757, |
| 20109 | /* MVE_VMULLTp8 */ |
| 20110 | 6764, |
| 20111 | /* MVE_VMULLTs16 */ |
| 20112 | 6771, |
| 20113 | /* MVE_VMULLTs32 */ |
| 20114 | 6778, |
| 20115 | /* MVE_VMULLTs8 */ |
| 20116 | 6785, |
| 20117 | /* MVE_VMULLTu16 */ |
| 20118 | 6792, |
| 20119 | /* MVE_VMULLTu32 */ |
| 20120 | 6799, |
| 20121 | /* MVE_VMULLTu8 */ |
| 20122 | 6806, |
| 20123 | /* MVE_VMUL_qr_f16 */ |
| 20124 | 6813, |
| 20125 | /* MVE_VMUL_qr_f32 */ |
| 20126 | 6820, |
| 20127 | /* MVE_VMUL_qr_i16 */ |
| 20128 | 6827, |
| 20129 | /* MVE_VMUL_qr_i32 */ |
| 20130 | 6834, |
| 20131 | /* MVE_VMUL_qr_i8 */ |
| 20132 | 6841, |
| 20133 | /* MVE_VMULf16 */ |
| 20134 | 6848, |
| 20135 | /* MVE_VMULf32 */ |
| 20136 | 6855, |
| 20137 | /* MVE_VMULi16 */ |
| 20138 | 6862, |
| 20139 | /* MVE_VMULi32 */ |
| 20140 | 6869, |
| 20141 | /* MVE_VMULi8 */ |
| 20142 | 6876, |
| 20143 | /* MVE_VMVN */ |
| 20144 | 6883, |
| 20145 | /* MVE_VMVNimmi16 */ |
| 20146 | 6889, |
| 20147 | /* MVE_VMVNimmi32 */ |
| 20148 | 6895, |
| 20149 | /* MVE_VNEGf16 */ |
| 20150 | 6901, |
| 20151 | /* MVE_VNEGf32 */ |
| 20152 | 6907, |
| 20153 | /* MVE_VNEGs16 */ |
| 20154 | 6913, |
| 20155 | /* MVE_VNEGs32 */ |
| 20156 | 6919, |
| 20157 | /* MVE_VNEGs8 */ |
| 20158 | 6925, |
| 20159 | /* MVE_VORN */ |
| 20160 | 6931, |
| 20161 | /* MVE_VORR */ |
| 20162 | 6938, |
| 20163 | /* MVE_VORRimmi16 */ |
| 20164 | 6945, |
| 20165 | /* MVE_VORRimmi32 */ |
| 20166 | 6951, |
| 20167 | /* MVE_VPNOT */ |
| 20168 | 6957, |
| 20169 | /* MVE_VPSEL */ |
| 20170 | 6962, |
| 20171 | /* MVE_VPST */ |
| 20172 | 6968, |
| 20173 | /* MVE_VPTv16i8 */ |
| 20174 | 6969, |
| 20175 | /* MVE_VPTv16i8r */ |
| 20176 | 6973, |
| 20177 | /* MVE_VPTv16s8 */ |
| 20178 | 6977, |
| 20179 | /* MVE_VPTv16s8r */ |
| 20180 | 6981, |
| 20181 | /* MVE_VPTv16u8 */ |
| 20182 | 6985, |
| 20183 | /* MVE_VPTv16u8r */ |
| 20184 | 6989, |
| 20185 | /* MVE_VPTv4f32 */ |
| 20186 | 6993, |
| 20187 | /* MVE_VPTv4f32r */ |
| 20188 | 6997, |
| 20189 | /* MVE_VPTv4i32 */ |
| 20190 | 7001, |
| 20191 | /* MVE_VPTv4i32r */ |
| 20192 | 7005, |
| 20193 | /* MVE_VPTv4s32 */ |
| 20194 | 7009, |
| 20195 | /* MVE_VPTv4s32r */ |
| 20196 | 7013, |
| 20197 | /* MVE_VPTv4u32 */ |
| 20198 | 7017, |
| 20199 | /* MVE_VPTv4u32r */ |
| 20200 | 7021, |
| 20201 | /* MVE_VPTv8f16 */ |
| 20202 | 7025, |
| 20203 | /* MVE_VPTv8f16r */ |
| 20204 | 7029, |
| 20205 | /* MVE_VPTv8i16 */ |
| 20206 | 7033, |
| 20207 | /* MVE_VPTv8i16r */ |
| 20208 | 7037, |
| 20209 | /* MVE_VPTv8s16 */ |
| 20210 | 7041, |
| 20211 | /* MVE_VPTv8s16r */ |
| 20212 | 7045, |
| 20213 | /* MVE_VPTv8u16 */ |
| 20214 | 7049, |
| 20215 | /* MVE_VPTv8u16r */ |
| 20216 | 7053, |
| 20217 | /* MVE_VQABSs16 */ |
| 20218 | 7057, |
| 20219 | /* MVE_VQABSs32 */ |
| 20220 | 7063, |
| 20221 | /* MVE_VQABSs8 */ |
| 20222 | 7069, |
| 20223 | /* MVE_VQADD_qr_s16 */ |
| 20224 | 7075, |
| 20225 | /* MVE_VQADD_qr_s32 */ |
| 20226 | 7082, |
| 20227 | /* MVE_VQADD_qr_s8 */ |
| 20228 | 7089, |
| 20229 | /* MVE_VQADD_qr_u16 */ |
| 20230 | 7096, |
| 20231 | /* MVE_VQADD_qr_u32 */ |
| 20232 | 7103, |
| 20233 | /* MVE_VQADD_qr_u8 */ |
| 20234 | 7110, |
| 20235 | /* MVE_VQADDs16 */ |
| 20236 | 7117, |
| 20237 | /* MVE_VQADDs32 */ |
| 20238 | 7124, |
| 20239 | /* MVE_VQADDs8 */ |
| 20240 | 7131, |
| 20241 | /* MVE_VQADDu16 */ |
| 20242 | 7138, |
| 20243 | /* MVE_VQADDu32 */ |
| 20244 | 7145, |
| 20245 | /* MVE_VQADDu8 */ |
| 20246 | 7152, |
| 20247 | /* MVE_VQDMLADHXs16 */ |
| 20248 | 7159, |
| 20249 | /* MVE_VQDMLADHXs32 */ |
| 20250 | 7166, |
| 20251 | /* MVE_VQDMLADHXs8 */ |
| 20252 | 7173, |
| 20253 | /* MVE_VQDMLADHs16 */ |
| 20254 | 7180, |
| 20255 | /* MVE_VQDMLADHs32 */ |
| 20256 | 7187, |
| 20257 | /* MVE_VQDMLADHs8 */ |
| 20258 | 7194, |
| 20259 | /* MVE_VQDMLAH_qrs16 */ |
| 20260 | 7201, |
| 20261 | /* MVE_VQDMLAH_qrs32 */ |
| 20262 | 7208, |
| 20263 | /* MVE_VQDMLAH_qrs8 */ |
| 20264 | 7215, |
| 20265 | /* MVE_VQDMLASH_qrs16 */ |
| 20266 | 7222, |
| 20267 | /* MVE_VQDMLASH_qrs32 */ |
| 20268 | 7229, |
| 20269 | /* MVE_VQDMLASH_qrs8 */ |
| 20270 | 7236, |
| 20271 | /* MVE_VQDMLSDHXs16 */ |
| 20272 | 7243, |
| 20273 | /* MVE_VQDMLSDHXs32 */ |
| 20274 | 7250, |
| 20275 | /* MVE_VQDMLSDHXs8 */ |
| 20276 | 7257, |
| 20277 | /* MVE_VQDMLSDHs16 */ |
| 20278 | 7264, |
| 20279 | /* MVE_VQDMLSDHs32 */ |
| 20280 | 7271, |
| 20281 | /* MVE_VQDMLSDHs8 */ |
| 20282 | 7278, |
| 20283 | /* MVE_VQDMULH_qr_s16 */ |
| 20284 | 7285, |
| 20285 | /* MVE_VQDMULH_qr_s32 */ |
| 20286 | 7292, |
| 20287 | /* MVE_VQDMULH_qr_s8 */ |
| 20288 | 7299, |
| 20289 | /* MVE_VQDMULHi16 */ |
| 20290 | 7306, |
| 20291 | /* MVE_VQDMULHi32 */ |
| 20292 | 7313, |
| 20293 | /* MVE_VQDMULHi8 */ |
| 20294 | 7320, |
| 20295 | /* MVE_VQDMULL_qr_s16bh */ |
| 20296 | 7327, |
| 20297 | /* MVE_VQDMULL_qr_s16th */ |
| 20298 | 7334, |
| 20299 | /* MVE_VQDMULL_qr_s32bh */ |
| 20300 | 7341, |
| 20301 | /* MVE_VQDMULL_qr_s32th */ |
| 20302 | 7348, |
| 20303 | /* MVE_VQDMULLs16bh */ |
| 20304 | 7355, |
| 20305 | /* MVE_VQDMULLs16th */ |
| 20306 | 7362, |
| 20307 | /* MVE_VQDMULLs32bh */ |
| 20308 | 7369, |
| 20309 | /* MVE_VQDMULLs32th */ |
| 20310 | 7376, |
| 20311 | /* MVE_VQMOVNs16bh */ |
| 20312 | 7383, |
| 20313 | /* MVE_VQMOVNs16th */ |
| 20314 | 7389, |
| 20315 | /* MVE_VQMOVNs32bh */ |
| 20316 | 7395, |
| 20317 | /* MVE_VQMOVNs32th */ |
| 20318 | 7401, |
| 20319 | /* MVE_VQMOVNu16bh */ |
| 20320 | 7407, |
| 20321 | /* MVE_VQMOVNu16th */ |
| 20322 | 7413, |
| 20323 | /* MVE_VQMOVNu32bh */ |
| 20324 | 7419, |
| 20325 | /* MVE_VQMOVNu32th */ |
| 20326 | 7425, |
| 20327 | /* MVE_VQMOVUNs16bh */ |
| 20328 | 7431, |
| 20329 | /* MVE_VQMOVUNs16th */ |
| 20330 | 7437, |
| 20331 | /* MVE_VQMOVUNs32bh */ |
| 20332 | 7443, |
| 20333 | /* MVE_VQMOVUNs32th */ |
| 20334 | 7449, |
| 20335 | /* MVE_VQNEGs16 */ |
| 20336 | 7455, |
| 20337 | /* MVE_VQNEGs32 */ |
| 20338 | 7461, |
| 20339 | /* MVE_VQNEGs8 */ |
| 20340 | 7467, |
| 20341 | /* MVE_VQRDMLADHXs16 */ |
| 20342 | 7473, |
| 20343 | /* MVE_VQRDMLADHXs32 */ |
| 20344 | 7480, |
| 20345 | /* MVE_VQRDMLADHXs8 */ |
| 20346 | 7487, |
| 20347 | /* MVE_VQRDMLADHs16 */ |
| 20348 | 7494, |
| 20349 | /* MVE_VQRDMLADHs32 */ |
| 20350 | 7501, |
| 20351 | /* MVE_VQRDMLADHs8 */ |
| 20352 | 7508, |
| 20353 | /* MVE_VQRDMLAH_qrs16 */ |
| 20354 | 7515, |
| 20355 | /* MVE_VQRDMLAH_qrs32 */ |
| 20356 | 7522, |
| 20357 | /* MVE_VQRDMLAH_qrs8 */ |
| 20358 | 7529, |
| 20359 | /* MVE_VQRDMLASH_qrs16 */ |
| 20360 | 7536, |
| 20361 | /* MVE_VQRDMLASH_qrs32 */ |
| 20362 | 7543, |
| 20363 | /* MVE_VQRDMLASH_qrs8 */ |
| 20364 | 7550, |
| 20365 | /* MVE_VQRDMLSDHXs16 */ |
| 20366 | 7557, |
| 20367 | /* MVE_VQRDMLSDHXs32 */ |
| 20368 | 7564, |
| 20369 | /* MVE_VQRDMLSDHXs8 */ |
| 20370 | 7571, |
| 20371 | /* MVE_VQRDMLSDHs16 */ |
| 20372 | 7578, |
| 20373 | /* MVE_VQRDMLSDHs32 */ |
| 20374 | 7585, |
| 20375 | /* MVE_VQRDMLSDHs8 */ |
| 20376 | 7592, |
| 20377 | /* MVE_VQRDMULH_qr_s16 */ |
| 20378 | 7599, |
| 20379 | /* MVE_VQRDMULH_qr_s32 */ |
| 20380 | 7606, |
| 20381 | /* MVE_VQRDMULH_qr_s8 */ |
| 20382 | 7613, |
| 20383 | /* MVE_VQRDMULHi16 */ |
| 20384 | 7620, |
| 20385 | /* MVE_VQRDMULHi32 */ |
| 20386 | 7627, |
| 20387 | /* MVE_VQRDMULHi8 */ |
| 20388 | 7634, |
| 20389 | /* MVE_VQRSHL_by_vecs16 */ |
| 20390 | 7641, |
| 20391 | /* MVE_VQRSHL_by_vecs32 */ |
| 20392 | 7648, |
| 20393 | /* MVE_VQRSHL_by_vecs8 */ |
| 20394 | 7655, |
| 20395 | /* MVE_VQRSHL_by_vecu16 */ |
| 20396 | 7662, |
| 20397 | /* MVE_VQRSHL_by_vecu32 */ |
| 20398 | 7669, |
| 20399 | /* MVE_VQRSHL_by_vecu8 */ |
| 20400 | 7676, |
| 20401 | /* MVE_VQRSHL_qrs16 */ |
| 20402 | 7683, |
| 20403 | /* MVE_VQRSHL_qrs32 */ |
| 20404 | 7689, |
| 20405 | /* MVE_VQRSHL_qrs8 */ |
| 20406 | 7695, |
| 20407 | /* MVE_VQRSHL_qru16 */ |
| 20408 | 7701, |
| 20409 | /* MVE_VQRSHL_qru32 */ |
| 20410 | 7707, |
| 20411 | /* MVE_VQRSHL_qru8 */ |
| 20412 | 7713, |
| 20413 | /* MVE_VQRSHRNbhs16 */ |
| 20414 | 7719, |
| 20415 | /* MVE_VQRSHRNbhs32 */ |
| 20416 | 7726, |
| 20417 | /* MVE_VQRSHRNbhu16 */ |
| 20418 | 7733, |
| 20419 | /* MVE_VQRSHRNbhu32 */ |
| 20420 | 7740, |
| 20421 | /* MVE_VQRSHRNths16 */ |
| 20422 | 7747, |
| 20423 | /* MVE_VQRSHRNths32 */ |
| 20424 | 7754, |
| 20425 | /* MVE_VQRSHRNthu16 */ |
| 20426 | 7761, |
| 20427 | /* MVE_VQRSHRNthu32 */ |
| 20428 | 7768, |
| 20429 | /* MVE_VQRSHRUNs16bh */ |
| 20430 | 7775, |
| 20431 | /* MVE_VQRSHRUNs16th */ |
| 20432 | 7782, |
| 20433 | /* MVE_VQRSHRUNs32bh */ |
| 20434 | 7789, |
| 20435 | /* MVE_VQRSHRUNs32th */ |
| 20436 | 7796, |
| 20437 | /* MVE_VQSHLU_imms16 */ |
| 20438 | 7803, |
| 20439 | /* MVE_VQSHLU_imms32 */ |
| 20440 | 7810, |
| 20441 | /* MVE_VQSHLU_imms8 */ |
| 20442 | 7817, |
| 20443 | /* MVE_VQSHL_by_vecs16 */ |
| 20444 | 7824, |
| 20445 | /* MVE_VQSHL_by_vecs32 */ |
| 20446 | 7831, |
| 20447 | /* MVE_VQSHL_by_vecs8 */ |
| 20448 | 7838, |
| 20449 | /* MVE_VQSHL_by_vecu16 */ |
| 20450 | 7845, |
| 20451 | /* MVE_VQSHL_by_vecu32 */ |
| 20452 | 7852, |
| 20453 | /* MVE_VQSHL_by_vecu8 */ |
| 20454 | 7859, |
| 20455 | /* MVE_VQSHL_qrs16 */ |
| 20456 | 7866, |
| 20457 | /* MVE_VQSHL_qrs32 */ |
| 20458 | 7872, |
| 20459 | /* MVE_VQSHL_qrs8 */ |
| 20460 | 7878, |
| 20461 | /* MVE_VQSHL_qru16 */ |
| 20462 | 7884, |
| 20463 | /* MVE_VQSHL_qru32 */ |
| 20464 | 7890, |
| 20465 | /* MVE_VQSHL_qru8 */ |
| 20466 | 7896, |
| 20467 | /* MVE_VQSHLimms16 */ |
| 20468 | 7902, |
| 20469 | /* MVE_VQSHLimms32 */ |
| 20470 | 7909, |
| 20471 | /* MVE_VQSHLimms8 */ |
| 20472 | 7916, |
| 20473 | /* MVE_VQSHLimmu16 */ |
| 20474 | 7923, |
| 20475 | /* MVE_VQSHLimmu32 */ |
| 20476 | 7930, |
| 20477 | /* MVE_VQSHLimmu8 */ |
| 20478 | 7937, |
| 20479 | /* MVE_VQSHRNbhs16 */ |
| 20480 | 7944, |
| 20481 | /* MVE_VQSHRNbhs32 */ |
| 20482 | 7951, |
| 20483 | /* MVE_VQSHRNbhu16 */ |
| 20484 | 7958, |
| 20485 | /* MVE_VQSHRNbhu32 */ |
| 20486 | 7965, |
| 20487 | /* MVE_VQSHRNths16 */ |
| 20488 | 7972, |
| 20489 | /* MVE_VQSHRNths32 */ |
| 20490 | 7979, |
| 20491 | /* MVE_VQSHRNthu16 */ |
| 20492 | 7986, |
| 20493 | /* MVE_VQSHRNthu32 */ |
| 20494 | 7993, |
| 20495 | /* MVE_VQSHRUNs16bh */ |
| 20496 | 8000, |
| 20497 | /* MVE_VQSHRUNs16th */ |
| 20498 | 8007, |
| 20499 | /* MVE_VQSHRUNs32bh */ |
| 20500 | 8014, |
| 20501 | /* MVE_VQSHRUNs32th */ |
| 20502 | 8021, |
| 20503 | /* MVE_VQSUB_qr_s16 */ |
| 20504 | 8028, |
| 20505 | /* MVE_VQSUB_qr_s32 */ |
| 20506 | 8035, |
| 20507 | /* MVE_VQSUB_qr_s8 */ |
| 20508 | 8042, |
| 20509 | /* MVE_VQSUB_qr_u16 */ |
| 20510 | 8049, |
| 20511 | /* MVE_VQSUB_qr_u32 */ |
| 20512 | 8056, |
| 20513 | /* MVE_VQSUB_qr_u8 */ |
| 20514 | 8063, |
| 20515 | /* MVE_VQSUBs16 */ |
| 20516 | 8070, |
| 20517 | /* MVE_VQSUBs32 */ |
| 20518 | 8077, |
| 20519 | /* MVE_VQSUBs8 */ |
| 20520 | 8084, |
| 20521 | /* MVE_VQSUBu16 */ |
| 20522 | 8091, |
| 20523 | /* MVE_VQSUBu32 */ |
| 20524 | 8098, |
| 20525 | /* MVE_VQSUBu8 */ |
| 20526 | 8105, |
| 20527 | /* MVE_VREV16_8 */ |
| 20528 | 8112, |
| 20529 | /* MVE_VREV32_16 */ |
| 20530 | 8118, |
| 20531 | /* MVE_VREV32_8 */ |
| 20532 | 8124, |
| 20533 | /* MVE_VREV64_16 */ |
| 20534 | 8130, |
| 20535 | /* MVE_VREV64_32 */ |
| 20536 | 8136, |
| 20537 | /* MVE_VREV64_8 */ |
| 20538 | 8142, |
| 20539 | /* MVE_VRHADDs16 */ |
| 20540 | 8148, |
| 20541 | /* MVE_VRHADDs32 */ |
| 20542 | 8155, |
| 20543 | /* MVE_VRHADDs8 */ |
| 20544 | 8162, |
| 20545 | /* MVE_VRHADDu16 */ |
| 20546 | 8169, |
| 20547 | /* MVE_VRHADDu32 */ |
| 20548 | 8176, |
| 20549 | /* MVE_VRHADDu8 */ |
| 20550 | 8183, |
| 20551 | /* MVE_VRINTf16A */ |
| 20552 | 8190, |
| 20553 | /* MVE_VRINTf16M */ |
| 20554 | 8196, |
| 20555 | /* MVE_VRINTf16N */ |
| 20556 | 8202, |
| 20557 | /* MVE_VRINTf16P */ |
| 20558 | 8208, |
| 20559 | /* MVE_VRINTf16X */ |
| 20560 | 8214, |
| 20561 | /* MVE_VRINTf16Z */ |
| 20562 | 8220, |
| 20563 | /* MVE_VRINTf32A */ |
| 20564 | 8226, |
| 20565 | /* MVE_VRINTf32M */ |
| 20566 | 8232, |
| 20567 | /* MVE_VRINTf32N */ |
| 20568 | 8238, |
| 20569 | /* MVE_VRINTf32P */ |
| 20570 | 8244, |
| 20571 | /* MVE_VRINTf32X */ |
| 20572 | 8250, |
| 20573 | /* MVE_VRINTf32Z */ |
| 20574 | 8256, |
| 20575 | /* MVE_VRMLALDAVHas32 */ |
| 20576 | 8262, |
| 20577 | /* MVE_VRMLALDAVHau32 */ |
| 20578 | 8271, |
| 20579 | /* MVE_VRMLALDAVHaxs32 */ |
| 20580 | 8280, |
| 20581 | /* MVE_VRMLALDAVHs32 */ |
| 20582 | 8289, |
| 20583 | /* MVE_VRMLALDAVHu32 */ |
| 20584 | 8296, |
| 20585 | /* MVE_VRMLALDAVHxs32 */ |
| 20586 | 8303, |
| 20587 | /* MVE_VRMLSLDAVHas32 */ |
| 20588 | 8310, |
| 20589 | /* MVE_VRMLSLDAVHaxs32 */ |
| 20590 | 8319, |
| 20591 | /* MVE_VRMLSLDAVHs32 */ |
| 20592 | 8328, |
| 20593 | /* MVE_VRMLSLDAVHxs32 */ |
| 20594 | 8335, |
| 20595 | /* MVE_VRMULHs16 */ |
| 20596 | 8342, |
| 20597 | /* MVE_VRMULHs32 */ |
| 20598 | 8349, |
| 20599 | /* MVE_VRMULHs8 */ |
| 20600 | 8356, |
| 20601 | /* MVE_VRMULHu16 */ |
| 20602 | 8363, |
| 20603 | /* MVE_VRMULHu32 */ |
| 20604 | 8370, |
| 20605 | /* MVE_VRMULHu8 */ |
| 20606 | 8377, |
| 20607 | /* MVE_VRSHL_by_vecs16 */ |
| 20608 | 8384, |
| 20609 | /* MVE_VRSHL_by_vecs32 */ |
| 20610 | 8391, |
| 20611 | /* MVE_VRSHL_by_vecs8 */ |
| 20612 | 8398, |
| 20613 | /* MVE_VRSHL_by_vecu16 */ |
| 20614 | 8405, |
| 20615 | /* MVE_VRSHL_by_vecu32 */ |
| 20616 | 8412, |
| 20617 | /* MVE_VRSHL_by_vecu8 */ |
| 20618 | 8419, |
| 20619 | /* MVE_VRSHL_qrs16 */ |
| 20620 | 8426, |
| 20621 | /* MVE_VRSHL_qrs32 */ |
| 20622 | 8432, |
| 20623 | /* MVE_VRSHL_qrs8 */ |
| 20624 | 8438, |
| 20625 | /* MVE_VRSHL_qru16 */ |
| 20626 | 8444, |
| 20627 | /* MVE_VRSHL_qru32 */ |
| 20628 | 8450, |
| 20629 | /* MVE_VRSHL_qru8 */ |
| 20630 | 8456, |
| 20631 | /* MVE_VRSHRNi16bh */ |
| 20632 | 8462, |
| 20633 | /* MVE_VRSHRNi16th */ |
| 20634 | 8469, |
| 20635 | /* MVE_VRSHRNi32bh */ |
| 20636 | 8476, |
| 20637 | /* MVE_VRSHRNi32th */ |
| 20638 | 8483, |
| 20639 | /* MVE_VRSHR_imms16 */ |
| 20640 | 8490, |
| 20641 | /* MVE_VRSHR_imms32 */ |
| 20642 | 8497, |
| 20643 | /* MVE_VRSHR_imms8 */ |
| 20644 | 8504, |
| 20645 | /* MVE_VRSHR_immu16 */ |
| 20646 | 8511, |
| 20647 | /* MVE_VRSHR_immu32 */ |
| 20648 | 8518, |
| 20649 | /* MVE_VRSHR_immu8 */ |
| 20650 | 8525, |
| 20651 | /* MVE_VSBC */ |
| 20652 | 8532, |
| 20653 | /* MVE_VSBCI */ |
| 20654 | 8541, |
| 20655 | /* MVE_VSHLC */ |
| 20656 | 8549, |
| 20657 | /* MVE_VSHLL_imms16bh */ |
| 20658 | 8557, |
| 20659 | /* MVE_VSHLL_imms16th */ |
| 20660 | 8564, |
| 20661 | /* MVE_VSHLL_imms8bh */ |
| 20662 | 8571, |
| 20663 | /* MVE_VSHLL_imms8th */ |
| 20664 | 8578, |
| 20665 | /* MVE_VSHLL_immu16bh */ |
| 20666 | 8585, |
| 20667 | /* MVE_VSHLL_immu16th */ |
| 20668 | 8592, |
| 20669 | /* MVE_VSHLL_immu8bh */ |
| 20670 | 8599, |
| 20671 | /* MVE_VSHLL_immu8th */ |
| 20672 | 8606, |
| 20673 | /* MVE_VSHLL_lws16bh */ |
| 20674 | 8613, |
| 20675 | /* MVE_VSHLL_lws16th */ |
| 20676 | 8619, |
| 20677 | /* MVE_VSHLL_lws8bh */ |
| 20678 | 8625, |
| 20679 | /* MVE_VSHLL_lws8th */ |
| 20680 | 8631, |
| 20681 | /* MVE_VSHLL_lwu16bh */ |
| 20682 | 8637, |
| 20683 | /* MVE_VSHLL_lwu16th */ |
| 20684 | 8643, |
| 20685 | /* MVE_VSHLL_lwu8bh */ |
| 20686 | 8649, |
| 20687 | /* MVE_VSHLL_lwu8th */ |
| 20688 | 8655, |
| 20689 | /* MVE_VSHL_by_vecs16 */ |
| 20690 | 8661, |
| 20691 | /* MVE_VSHL_by_vecs32 */ |
| 20692 | 8668, |
| 20693 | /* MVE_VSHL_by_vecs8 */ |
| 20694 | 8675, |
| 20695 | /* MVE_VSHL_by_vecu16 */ |
| 20696 | 8682, |
| 20697 | /* MVE_VSHL_by_vecu32 */ |
| 20698 | 8689, |
| 20699 | /* MVE_VSHL_by_vecu8 */ |
| 20700 | 8696, |
| 20701 | /* MVE_VSHL_immi16 */ |
| 20702 | 8703, |
| 20703 | /* MVE_VSHL_immi32 */ |
| 20704 | 8710, |
| 20705 | /* MVE_VSHL_immi8 */ |
| 20706 | 8717, |
| 20707 | /* MVE_VSHL_qrs16 */ |
| 20708 | 8724, |
| 20709 | /* MVE_VSHL_qrs32 */ |
| 20710 | 8730, |
| 20711 | /* MVE_VSHL_qrs8 */ |
| 20712 | 8736, |
| 20713 | /* MVE_VSHL_qru16 */ |
| 20714 | 8742, |
| 20715 | /* MVE_VSHL_qru32 */ |
| 20716 | 8748, |
| 20717 | /* MVE_VSHL_qru8 */ |
| 20718 | 8754, |
| 20719 | /* MVE_VSHRNi16bh */ |
| 20720 | 8760, |
| 20721 | /* MVE_VSHRNi16th */ |
| 20722 | 8767, |
| 20723 | /* MVE_VSHRNi32bh */ |
| 20724 | 8774, |
| 20725 | /* MVE_VSHRNi32th */ |
| 20726 | 8781, |
| 20727 | /* MVE_VSHR_imms16 */ |
| 20728 | 8788, |
| 20729 | /* MVE_VSHR_imms32 */ |
| 20730 | 8795, |
| 20731 | /* MVE_VSHR_imms8 */ |
| 20732 | 8802, |
| 20733 | /* MVE_VSHR_immu16 */ |
| 20734 | 8809, |
| 20735 | /* MVE_VSHR_immu32 */ |
| 20736 | 8816, |
| 20737 | /* MVE_VSHR_immu8 */ |
| 20738 | 8823, |
| 20739 | /* MVE_VSLIimm16 */ |
| 20740 | 8830, |
| 20741 | /* MVE_VSLIimm32 */ |
| 20742 | 8837, |
| 20743 | /* MVE_VSLIimm8 */ |
| 20744 | 8844, |
| 20745 | /* MVE_VSRIimm16 */ |
| 20746 | 8851, |
| 20747 | /* MVE_VSRIimm32 */ |
| 20748 | 8858, |
| 20749 | /* MVE_VSRIimm8 */ |
| 20750 | 8865, |
| 20751 | /* MVE_VST20_16 */ |
| 20752 | 8872, |
| 20753 | /* MVE_VST20_16_wb */ |
| 20754 | 8874, |
| 20755 | /* MVE_VST20_32 */ |
| 20756 | 8877, |
| 20757 | /* MVE_VST20_32_wb */ |
| 20758 | 8879, |
| 20759 | /* MVE_VST20_8 */ |
| 20760 | 8882, |
| 20761 | /* MVE_VST20_8_wb */ |
| 20762 | 8884, |
| 20763 | /* MVE_VST21_16 */ |
| 20764 | 8887, |
| 20765 | /* MVE_VST21_16_wb */ |
| 20766 | 8889, |
| 20767 | /* MVE_VST21_32 */ |
| 20768 | 8892, |
| 20769 | /* MVE_VST21_32_wb */ |
| 20770 | 8894, |
| 20771 | /* MVE_VST21_8 */ |
| 20772 | 8897, |
| 20773 | /* MVE_VST21_8_wb */ |
| 20774 | 8899, |
| 20775 | /* MVE_VST40_16 */ |
| 20776 | 8902, |
| 20777 | /* MVE_VST40_16_wb */ |
| 20778 | 8904, |
| 20779 | /* MVE_VST40_32 */ |
| 20780 | 8907, |
| 20781 | /* MVE_VST40_32_wb */ |
| 20782 | 8909, |
| 20783 | /* MVE_VST40_8 */ |
| 20784 | 8912, |
| 20785 | /* MVE_VST40_8_wb */ |
| 20786 | 8914, |
| 20787 | /* MVE_VST41_16 */ |
| 20788 | 8917, |
| 20789 | /* MVE_VST41_16_wb */ |
| 20790 | 8919, |
| 20791 | /* MVE_VST41_32 */ |
| 20792 | 8922, |
| 20793 | /* MVE_VST41_32_wb */ |
| 20794 | 8924, |
| 20795 | /* MVE_VST41_8 */ |
| 20796 | 8927, |
| 20797 | /* MVE_VST41_8_wb */ |
| 20798 | 8929, |
| 20799 | /* MVE_VST42_16 */ |
| 20800 | 8932, |
| 20801 | /* MVE_VST42_16_wb */ |
| 20802 | 8934, |
| 20803 | /* MVE_VST42_32 */ |
| 20804 | 8937, |
| 20805 | /* MVE_VST42_32_wb */ |
| 20806 | 8939, |
| 20807 | /* MVE_VST42_8 */ |
| 20808 | 8942, |
| 20809 | /* MVE_VST42_8_wb */ |
| 20810 | 8944, |
| 20811 | /* MVE_VST43_16 */ |
| 20812 | 8947, |
| 20813 | /* MVE_VST43_16_wb */ |
| 20814 | 8949, |
| 20815 | /* MVE_VST43_32 */ |
| 20816 | 8952, |
| 20817 | /* MVE_VST43_32_wb */ |
| 20818 | 8954, |
| 20819 | /* MVE_VST43_8 */ |
| 20820 | 8957, |
| 20821 | /* MVE_VST43_8_wb */ |
| 20822 | 8959, |
| 20823 | /* MVE_VSTRB16 */ |
| 20824 | 8962, |
| 20825 | /* MVE_VSTRB16_post */ |
| 20826 | 8968, |
| 20827 | /* MVE_VSTRB16_pre */ |
| 20828 | 8975, |
| 20829 | /* MVE_VSTRB16_rq */ |
| 20830 | 8982, |
| 20831 | /* MVE_VSTRB32 */ |
| 20832 | 8988, |
| 20833 | /* MVE_VSTRB32_post */ |
| 20834 | 8994, |
| 20835 | /* MVE_VSTRB32_pre */ |
| 20836 | 9001, |
| 20837 | /* MVE_VSTRB32_rq */ |
| 20838 | 9008, |
| 20839 | /* MVE_VSTRB8_rq */ |
| 20840 | 9014, |
| 20841 | /* MVE_VSTRBU8 */ |
| 20842 | 9020, |
| 20843 | /* MVE_VSTRBU8_post */ |
| 20844 | 9026, |
| 20845 | /* MVE_VSTRBU8_pre */ |
| 20846 | 9033, |
| 20847 | /* MVE_VSTRD64_qi */ |
| 20848 | 9040, |
| 20849 | /* MVE_VSTRD64_qi_pre */ |
| 20850 | 9046, |
| 20851 | /* MVE_VSTRD64_rq */ |
| 20852 | 9053, |
| 20853 | /* MVE_VSTRD64_rq_u */ |
| 20854 | 9059, |
| 20855 | /* MVE_VSTRH16_rq */ |
| 20856 | 9065, |
| 20857 | /* MVE_VSTRH16_rq_u */ |
| 20858 | 9071, |
| 20859 | /* MVE_VSTRH32 */ |
| 20860 | 9077, |
| 20861 | /* MVE_VSTRH32_post */ |
| 20862 | 9083, |
| 20863 | /* MVE_VSTRH32_pre */ |
| 20864 | 9090, |
| 20865 | /* MVE_VSTRH32_rq */ |
| 20866 | 9097, |
| 20867 | /* MVE_VSTRH32_rq_u */ |
| 20868 | 9103, |
| 20869 | /* MVE_VSTRHU16 */ |
| 20870 | 9109, |
| 20871 | /* MVE_VSTRHU16_post */ |
| 20872 | 9115, |
| 20873 | /* MVE_VSTRHU16_pre */ |
| 20874 | 9122, |
| 20875 | /* MVE_VSTRW32_qi */ |
| 20876 | 9129, |
| 20877 | /* MVE_VSTRW32_qi_pre */ |
| 20878 | 9135, |
| 20879 | /* MVE_VSTRW32_rq */ |
| 20880 | 9142, |
| 20881 | /* MVE_VSTRW32_rq_u */ |
| 20882 | 9148, |
| 20883 | /* MVE_VSTRWU32 */ |
| 20884 | 9154, |
| 20885 | /* MVE_VSTRWU32_post */ |
| 20886 | 9160, |
| 20887 | /* MVE_VSTRWU32_pre */ |
| 20888 | 9167, |
| 20889 | /* MVE_VSUB_qr_f16 */ |
| 20890 | 9174, |
| 20891 | /* MVE_VSUB_qr_f32 */ |
| 20892 | 9181, |
| 20893 | /* MVE_VSUB_qr_i16 */ |
| 20894 | 9188, |
| 20895 | /* MVE_VSUB_qr_i32 */ |
| 20896 | 9195, |
| 20897 | /* MVE_VSUB_qr_i8 */ |
| 20898 | 9202, |
| 20899 | /* MVE_VSUBf16 */ |
| 20900 | 9209, |
| 20901 | /* MVE_VSUBf32 */ |
| 20902 | 9216, |
| 20903 | /* MVE_VSUBi16 */ |
| 20904 | 9223, |
| 20905 | /* MVE_VSUBi32 */ |
| 20906 | 9230, |
| 20907 | /* MVE_VSUBi8 */ |
| 20908 | 9237, |
| 20909 | /* MVE_WLSTP_16 */ |
| 20910 | 9244, |
| 20911 | /* MVE_WLSTP_32 */ |
| 20912 | 9247, |
| 20913 | /* MVE_WLSTP_64 */ |
| 20914 | 9250, |
| 20915 | /* MVE_WLSTP_8 */ |
| 20916 | 9253, |
| 20917 | /* MVNi */ |
| 20918 | 9256, |
| 20919 | /* MVNr */ |
| 20920 | 9261, |
| 20921 | /* MVNsi */ |
| 20922 | 9266, |
| 20923 | /* MVNsr */ |
| 20924 | 9272, |
| 20925 | /* NEON_VMAXNMNDf */ |
| 20926 | 9279, |
| 20927 | /* NEON_VMAXNMNDh */ |
| 20928 | 9282, |
| 20929 | /* NEON_VMAXNMNQf */ |
| 20930 | 9285, |
| 20931 | /* NEON_VMAXNMNQh */ |
| 20932 | 9288, |
| 20933 | /* NEON_VMINNMNDf */ |
| 20934 | 9291, |
| 20935 | /* NEON_VMINNMNDh */ |
| 20936 | 9294, |
| 20937 | /* NEON_VMINNMNQf */ |
| 20938 | 9297, |
| 20939 | /* NEON_VMINNMNQh */ |
| 20940 | 9300, |
| 20941 | /* ORRri */ |
| 20942 | 9303, |
| 20943 | /* ORRrr */ |
| 20944 | 9309, |
| 20945 | /* ORRrsi */ |
| 20946 | 9315, |
| 20947 | /* ORRrsr */ |
| 20948 | 9322, |
| 20949 | /* PKHBT */ |
| 20950 | 9330, |
| 20951 | /* PKHTB */ |
| 20952 | 9336, |
| 20953 | /* PLDWi12 */ |
| 20954 | 9342, |
| 20955 | /* PLDWrs */ |
| 20956 | 9344, |
| 20957 | /* PLDi12 */ |
| 20958 | 9347, |
| 20959 | /* PLDrs */ |
| 20960 | 9349, |
| 20961 | /* PLIi12 */ |
| 20962 | 9352, |
| 20963 | /* PLIrs */ |
| 20964 | 9354, |
| 20965 | /* QADD */ |
| 20966 | 9357, |
| 20967 | /* QADD16 */ |
| 20968 | 9362, |
| 20969 | /* QADD8 */ |
| 20970 | 9367, |
| 20971 | /* QASX */ |
| 20972 | 9372, |
| 20973 | /* QDADD */ |
| 20974 | 9377, |
| 20975 | /* QDSUB */ |
| 20976 | 9382, |
| 20977 | /* QSAX */ |
| 20978 | 9387, |
| 20979 | /* QSUB */ |
| 20980 | 9392, |
| 20981 | /* QSUB16 */ |
| 20982 | 9397, |
| 20983 | /* QSUB8 */ |
| 20984 | 9402, |
| 20985 | /* RBIT */ |
| 20986 | 9407, |
| 20987 | /* REV */ |
| 20988 | 9411, |
| 20989 | /* REV16 */ |
| 20990 | 9415, |
| 20991 | /* REVSH */ |
| 20992 | 9419, |
| 20993 | /* RFEDA */ |
| 20994 | 9423, |
| 20995 | /* RFEDA_UPD */ |
| 20996 | 9424, |
| 20997 | /* RFEDB */ |
| 20998 | 9425, |
| 20999 | /* RFEDB_UPD */ |
| 21000 | 9426, |
| 21001 | /* RFEIA */ |
| 21002 | 9427, |
| 21003 | /* RFEIA_UPD */ |
| 21004 | 9428, |
| 21005 | /* RFEIB */ |
| 21006 | 9429, |
| 21007 | /* RFEIB_UPD */ |
| 21008 | 9430, |
| 21009 | /* RSBri */ |
| 21010 | 9431, |
| 21011 | /* RSBrr */ |
| 21012 | 9437, |
| 21013 | /* RSBrsi */ |
| 21014 | 9443, |
| 21015 | /* RSBrsr */ |
| 21016 | 9450, |
| 21017 | /* RSCri */ |
| 21018 | 9458, |
| 21019 | /* RSCrr */ |
| 21020 | 9464, |
| 21021 | /* RSCrsi */ |
| 21022 | 9470, |
| 21023 | /* RSCrsr */ |
| 21024 | 9477, |
| 21025 | /* SADD16 */ |
| 21026 | 9485, |
| 21027 | /* SADD8 */ |
| 21028 | 9490, |
| 21029 | /* SASX */ |
| 21030 | 9495, |
| 21031 | /* SB */ |
| 21032 | 9500, |
| 21033 | /* SBCri */ |
| 21034 | 9500, |
| 21035 | /* SBCrr */ |
| 21036 | 9506, |
| 21037 | /* SBCrsi */ |
| 21038 | 9512, |
| 21039 | /* SBCrsr */ |
| 21040 | 9519, |
| 21041 | /* SBFX */ |
| 21042 | 9527, |
| 21043 | /* SDIV */ |
| 21044 | 9533, |
| 21045 | /* SEL */ |
| 21046 | 9538, |
| 21047 | /* SETEND */ |
| 21048 | 9543, |
| 21049 | /* SETPAN */ |
| 21050 | 9544, |
| 21051 | /* SHA1C */ |
| 21052 | 9545, |
| 21053 | /* SHA1H */ |
| 21054 | 9549, |
| 21055 | /* SHA1M */ |
| 21056 | 9551, |
| 21057 | /* SHA1P */ |
| 21058 | 9555, |
| 21059 | /* SHA1SU0 */ |
| 21060 | 9559, |
| 21061 | /* SHA1SU1 */ |
| 21062 | 9563, |
| 21063 | /* SHA256H */ |
| 21064 | 9566, |
| 21065 | /* SHA256H2 */ |
| 21066 | 9570, |
| 21067 | /* SHA256SU0 */ |
| 21068 | 9574, |
| 21069 | /* SHA256SU1 */ |
| 21070 | 9577, |
| 21071 | /* SHADD16 */ |
| 21072 | 9581, |
| 21073 | /* SHADD8 */ |
| 21074 | 9586, |
| 21075 | /* SHASX */ |
| 21076 | 9591, |
| 21077 | /* SHSAX */ |
| 21078 | 9596, |
| 21079 | /* SHSUB16 */ |
| 21080 | 9601, |
| 21081 | /* SHSUB8 */ |
| 21082 | 9606, |
| 21083 | /* SMC */ |
| 21084 | 9611, |
| 21085 | /* SMLABB */ |
| 21086 | 9614, |
| 21087 | /* SMLABT */ |
| 21088 | 9620, |
| 21089 | /* SMLAD */ |
| 21090 | 9626, |
| 21091 | /* SMLADX */ |
| 21092 | 9632, |
| 21093 | /* SMLAL */ |
| 21094 | 9638, |
| 21095 | /* SMLALBB */ |
| 21096 | 9647, |
| 21097 | /* SMLALBT */ |
| 21098 | 9655, |
| 21099 | /* SMLALD */ |
| 21100 | 9663, |
| 21101 | /* SMLALDX */ |
| 21102 | 9671, |
| 21103 | /* SMLALTB */ |
| 21104 | 9679, |
| 21105 | /* SMLALTT */ |
| 21106 | 9687, |
| 21107 | /* SMLATB */ |
| 21108 | 9695, |
| 21109 | /* SMLATT */ |
| 21110 | 9701, |
| 21111 | /* SMLAWB */ |
| 21112 | 9707, |
| 21113 | /* SMLAWT */ |
| 21114 | 9713, |
| 21115 | /* SMLSD */ |
| 21116 | 9719, |
| 21117 | /* SMLSDX */ |
| 21118 | 9725, |
| 21119 | /* SMLSLD */ |
| 21120 | 9731, |
| 21121 | /* SMLSLDX */ |
| 21122 | 9739, |
| 21123 | /* SMMLA */ |
| 21124 | 9747, |
| 21125 | /* SMMLAR */ |
| 21126 | 9753, |
| 21127 | /* SMMLS */ |
| 21128 | 9759, |
| 21129 | /* SMMLSR */ |
| 21130 | 9765, |
| 21131 | /* SMMUL */ |
| 21132 | 9771, |
| 21133 | /* SMMULR */ |
| 21134 | 9776, |
| 21135 | /* SMUAD */ |
| 21136 | 9781, |
| 21137 | /* SMUADX */ |
| 21138 | 9786, |
| 21139 | /* SMULBB */ |
| 21140 | 9791, |
| 21141 | /* SMULBT */ |
| 21142 | 9796, |
| 21143 | /* SMULL */ |
| 21144 | 9801, |
| 21145 | /* SMULTB */ |
| 21146 | 9808, |
| 21147 | /* SMULTT */ |
| 21148 | 9813, |
| 21149 | /* SMULWB */ |
| 21150 | 9818, |
| 21151 | /* SMULWT */ |
| 21152 | 9823, |
| 21153 | /* SMUSD */ |
| 21154 | 9828, |
| 21155 | /* SMUSDX */ |
| 21156 | 9833, |
| 21157 | /* SRSDA */ |
| 21158 | 9838, |
| 21159 | /* SRSDA_UPD */ |
| 21160 | 9839, |
| 21161 | /* SRSDB */ |
| 21162 | 9840, |
| 21163 | /* SRSDB_UPD */ |
| 21164 | 9841, |
| 21165 | /* SRSIA */ |
| 21166 | 9842, |
| 21167 | /* SRSIA_UPD */ |
| 21168 | 9843, |
| 21169 | /* SRSIB */ |
| 21170 | 9844, |
| 21171 | /* SRSIB_UPD */ |
| 21172 | 9845, |
| 21173 | /* SSAT */ |
| 21174 | 9846, |
| 21175 | /* SSAT16 */ |
| 21176 | 9852, |
| 21177 | /* SSAX */ |
| 21178 | 9857, |
| 21179 | /* SSUB16 */ |
| 21180 | 9862, |
| 21181 | /* SSUB8 */ |
| 21182 | 9867, |
| 21183 | /* STC2L_OFFSET */ |
| 21184 | 9872, |
| 21185 | /* STC2L_OPTION */ |
| 21186 | 9876, |
| 21187 | /* STC2L_POST */ |
| 21188 | 9880, |
| 21189 | /* STC2L_PRE */ |
| 21190 | 9884, |
| 21191 | /* STC2_OFFSET */ |
| 21192 | 9888, |
| 21193 | /* STC2_OPTION */ |
| 21194 | 9892, |
| 21195 | /* STC2_POST */ |
| 21196 | 9896, |
| 21197 | /* STC2_PRE */ |
| 21198 | 9900, |
| 21199 | /* STCL_OFFSET */ |
| 21200 | 9904, |
| 21201 | /* STCL_OPTION */ |
| 21202 | 9910, |
| 21203 | /* STCL_POST */ |
| 21204 | 9916, |
| 21205 | /* STCL_PRE */ |
| 21206 | 9922, |
| 21207 | /* STC_OFFSET */ |
| 21208 | 9928, |
| 21209 | /* STC_OPTION */ |
| 21210 | 9934, |
| 21211 | /* STC_POST */ |
| 21212 | 9940, |
| 21213 | /* STC_PRE */ |
| 21214 | 9946, |
| 21215 | /* STL */ |
| 21216 | 9952, |
| 21217 | /* STLB */ |
| 21218 | 9956, |
| 21219 | /* STLEX */ |
| 21220 | 9960, |
| 21221 | /* STLEXB */ |
| 21222 | 9965, |
| 21223 | /* STLEXD */ |
| 21224 | 9970, |
| 21225 | /* STLEXH */ |
| 21226 | 9975, |
| 21227 | /* STLH */ |
| 21228 | 9980, |
| 21229 | /* STMDA */ |
| 21230 | 9984, |
| 21231 | /* STMDA_UPD */ |
| 21232 | 9988, |
| 21233 | /* STMDB */ |
| 21234 | 9993, |
| 21235 | /* STMDB_UPD */ |
| 21236 | 9997, |
| 21237 | /* STMIA */ |
| 21238 | 10002, |
| 21239 | /* STMIA_UPD */ |
| 21240 | 10006, |
| 21241 | /* STMIB */ |
| 21242 | 10011, |
| 21243 | /* STMIB_UPD */ |
| 21244 | 10015, |
| 21245 | /* STRBT_POST_IMM */ |
| 21246 | 10020, |
| 21247 | /* STRBT_POST_REG */ |
| 21248 | 10027, |
| 21249 | /* STRB_POST_IMM */ |
| 21250 | 10034, |
| 21251 | /* STRB_POST_REG */ |
| 21252 | 10041, |
| 21253 | /* STRB_PRE_IMM */ |
| 21254 | 10048, |
| 21255 | /* STRB_PRE_REG */ |
| 21256 | 10054, |
| 21257 | /* STRBi12 */ |
| 21258 | 10061, |
| 21259 | /* STRBrs */ |
| 21260 | 10066, |
| 21261 | /* STRD */ |
| 21262 | 10072, |
| 21263 | /* STRD_POST */ |
| 21264 | 10079, |
| 21265 | /* STRD_PRE */ |
| 21266 | 10087, |
| 21267 | /* STREX */ |
| 21268 | 10095, |
| 21269 | /* STREXB */ |
| 21270 | 10100, |
| 21271 | /* STREXD */ |
| 21272 | 10105, |
| 21273 | /* STREXH */ |
| 21274 | 10110, |
| 21275 | /* STRH */ |
| 21276 | 10115, |
| 21277 | /* STRHTi */ |
| 21278 | 10121, |
| 21279 | /* STRHTr */ |
| 21280 | 10127, |
| 21281 | /* STRH_POST */ |
| 21282 | 10134, |
| 21283 | /* STRH_PRE */ |
| 21284 | 10141, |
| 21285 | /* STRT_POST_IMM */ |
| 21286 | 10148, |
| 21287 | /* STRT_POST_REG */ |
| 21288 | 10155, |
| 21289 | /* STR_POST_IMM */ |
| 21290 | 10162, |
| 21291 | /* STR_POST_REG */ |
| 21292 | 10169, |
| 21293 | /* STR_PRE_IMM */ |
| 21294 | 10176, |
| 21295 | /* STR_PRE_REG */ |
| 21296 | 10182, |
| 21297 | /* STRi12 */ |
| 21298 | 10189, |
| 21299 | /* STRrs */ |
| 21300 | 10194, |
| 21301 | /* SUBri */ |
| 21302 | 10200, |
| 21303 | /* SUBrr */ |
| 21304 | 10206, |
| 21305 | /* SUBrsi */ |
| 21306 | 10212, |
| 21307 | /* SUBrsr */ |
| 21308 | 10219, |
| 21309 | /* SVC */ |
| 21310 | 10227, |
| 21311 | /* SWP */ |
| 21312 | 10230, |
| 21313 | /* SWPB */ |
| 21314 | 10235, |
| 21315 | /* SXTAB */ |
| 21316 | 10240, |
| 21317 | /* SXTAB16 */ |
| 21318 | 10246, |
| 21319 | /* SXTAH */ |
| 21320 | 10252, |
| 21321 | /* SXTB */ |
| 21322 | 10258, |
| 21323 | /* SXTB16 */ |
| 21324 | 10263, |
| 21325 | /* SXTH */ |
| 21326 | 10268, |
| 21327 | /* TEQri */ |
| 21328 | 10273, |
| 21329 | /* TEQrr */ |
| 21330 | 10277, |
| 21331 | /* TEQrsi */ |
| 21332 | 10281, |
| 21333 | /* TEQrsr */ |
| 21334 | 10286, |
| 21335 | /* TRAP */ |
| 21336 | 10292, |
| 21337 | /* TRAPNaCl */ |
| 21338 | 10292, |
| 21339 | /* TSB */ |
| 21340 | 10292, |
| 21341 | /* TSTri */ |
| 21342 | 10293, |
| 21343 | /* TSTrr */ |
| 21344 | 10297, |
| 21345 | /* TSTrsi */ |
| 21346 | 10301, |
| 21347 | /* TSTrsr */ |
| 21348 | 10306, |
| 21349 | /* UADD16 */ |
| 21350 | 10312, |
| 21351 | /* UADD8 */ |
| 21352 | 10317, |
| 21353 | /* UASX */ |
| 21354 | 10322, |
| 21355 | /* UBFX */ |
| 21356 | 10327, |
| 21357 | /* UDF */ |
| 21358 | 10333, |
| 21359 | /* UDIV */ |
| 21360 | 10334, |
| 21361 | /* UHADD16 */ |
| 21362 | 10339, |
| 21363 | /* UHADD8 */ |
| 21364 | 10344, |
| 21365 | /* UHASX */ |
| 21366 | 10349, |
| 21367 | /* UHSAX */ |
| 21368 | 10354, |
| 21369 | /* UHSUB16 */ |
| 21370 | 10359, |
| 21371 | /* UHSUB8 */ |
| 21372 | 10364, |
| 21373 | /* UMAAL */ |
| 21374 | 10369, |
| 21375 | /* UMLAL */ |
| 21376 | 10377, |
| 21377 | /* UMULL */ |
| 21378 | 10386, |
| 21379 | /* UQADD16 */ |
| 21380 | 10393, |
| 21381 | /* UQADD8 */ |
| 21382 | 10398, |
| 21383 | /* UQASX */ |
| 21384 | 10403, |
| 21385 | /* UQSAX */ |
| 21386 | 10408, |
| 21387 | /* UQSUB16 */ |
| 21388 | 10413, |
| 21389 | /* UQSUB8 */ |
| 21390 | 10418, |
| 21391 | /* USAD8 */ |
| 21392 | 10423, |
| 21393 | /* USADA8 */ |
| 21394 | 10428, |
| 21395 | /* USAT */ |
| 21396 | 10434, |
| 21397 | /* USAT16 */ |
| 21398 | 10440, |
| 21399 | /* USAX */ |
| 21400 | 10445, |
| 21401 | /* USUB16 */ |
| 21402 | 10450, |
| 21403 | /* USUB8 */ |
| 21404 | 10455, |
| 21405 | /* UXTAB */ |
| 21406 | 10460, |
| 21407 | /* UXTAB16 */ |
| 21408 | 10466, |
| 21409 | /* UXTAH */ |
| 21410 | 10472, |
| 21411 | /* UXTB */ |
| 21412 | 10478, |
| 21413 | /* UXTB16 */ |
| 21414 | 10483, |
| 21415 | /* UXTH */ |
| 21416 | 10488, |
| 21417 | /* VABALsv2i64 */ |
| 21418 | 10493, |
| 21419 | /* VABALsv4i32 */ |
| 21420 | 10499, |
| 21421 | /* VABALsv8i16 */ |
| 21422 | 10505, |
| 21423 | /* VABALuv2i64 */ |
| 21424 | 10511, |
| 21425 | /* VABALuv4i32 */ |
| 21426 | 10517, |
| 21427 | /* VABALuv8i16 */ |
| 21428 | 10523, |
| 21429 | /* VABAsv16i8 */ |
| 21430 | 10529, |
| 21431 | /* VABAsv2i32 */ |
| 21432 | 10535, |
| 21433 | /* VABAsv4i16 */ |
| 21434 | 10541, |
| 21435 | /* VABAsv4i32 */ |
| 21436 | 10547, |
| 21437 | /* VABAsv8i16 */ |
| 21438 | 10553, |
| 21439 | /* VABAsv8i8 */ |
| 21440 | 10559, |
| 21441 | /* VABAuv16i8 */ |
| 21442 | 10565, |
| 21443 | /* VABAuv2i32 */ |
| 21444 | 10571, |
| 21445 | /* VABAuv4i16 */ |
| 21446 | 10577, |
| 21447 | /* VABAuv4i32 */ |
| 21448 | 10583, |
| 21449 | /* VABAuv8i16 */ |
| 21450 | 10589, |
| 21451 | /* VABAuv8i8 */ |
| 21452 | 10595, |
| 21453 | /* VABDLsv2i64 */ |
| 21454 | 10601, |
| 21455 | /* VABDLsv4i32 */ |
| 21456 | 10606, |
| 21457 | /* VABDLsv8i16 */ |
| 21458 | 10611, |
| 21459 | /* VABDLuv2i64 */ |
| 21460 | 10616, |
| 21461 | /* VABDLuv4i32 */ |
| 21462 | 10621, |
| 21463 | /* VABDLuv8i16 */ |
| 21464 | 10626, |
| 21465 | /* VABDfd */ |
| 21466 | 10631, |
| 21467 | /* VABDfq */ |
| 21468 | 10636, |
| 21469 | /* VABDhd */ |
| 21470 | 10641, |
| 21471 | /* VABDhq */ |
| 21472 | 10646, |
| 21473 | /* VABDsv16i8 */ |
| 21474 | 10651, |
| 21475 | /* VABDsv2i32 */ |
| 21476 | 10656, |
| 21477 | /* VABDsv4i16 */ |
| 21478 | 10661, |
| 21479 | /* VABDsv4i32 */ |
| 21480 | 10666, |
| 21481 | /* VABDsv8i16 */ |
| 21482 | 10671, |
| 21483 | /* VABDsv8i8 */ |
| 21484 | 10676, |
| 21485 | /* VABDuv16i8 */ |
| 21486 | 10681, |
| 21487 | /* VABDuv2i32 */ |
| 21488 | 10686, |
| 21489 | /* VABDuv4i16 */ |
| 21490 | 10691, |
| 21491 | /* VABDuv4i32 */ |
| 21492 | 10696, |
| 21493 | /* VABDuv8i16 */ |
| 21494 | 10701, |
| 21495 | /* VABDuv8i8 */ |
| 21496 | 10706, |
| 21497 | /* VABSD */ |
| 21498 | 10711, |
| 21499 | /* VABSH */ |
| 21500 | 10715, |
| 21501 | /* VABSS */ |
| 21502 | 10719, |
| 21503 | /* VABSfd */ |
| 21504 | 10723, |
| 21505 | /* VABSfq */ |
| 21506 | 10727, |
| 21507 | /* VABShd */ |
| 21508 | 10731, |
| 21509 | /* VABShq */ |
| 21510 | 10735, |
| 21511 | /* VABSv16i8 */ |
| 21512 | 10739, |
| 21513 | /* VABSv2i32 */ |
| 21514 | 10743, |
| 21515 | /* VABSv4i16 */ |
| 21516 | 10747, |
| 21517 | /* VABSv4i32 */ |
| 21518 | 10751, |
| 21519 | /* VABSv8i16 */ |
| 21520 | 10755, |
| 21521 | /* VABSv8i8 */ |
| 21522 | 10759, |
| 21523 | /* VACGEfd */ |
| 21524 | 10763, |
| 21525 | /* VACGEfq */ |
| 21526 | 10768, |
| 21527 | /* VACGEhd */ |
| 21528 | 10773, |
| 21529 | /* VACGEhq */ |
| 21530 | 10778, |
| 21531 | /* VACGTfd */ |
| 21532 | 10783, |
| 21533 | /* VACGTfq */ |
| 21534 | 10788, |
| 21535 | /* VACGThd */ |
| 21536 | 10793, |
| 21537 | /* VACGThq */ |
| 21538 | 10798, |
| 21539 | /* VADDD */ |
| 21540 | 10803, |
| 21541 | /* VADDH */ |
| 21542 | 10808, |
| 21543 | /* VADDHNv2i32 */ |
| 21544 | 10813, |
| 21545 | /* VADDHNv4i16 */ |
| 21546 | 10818, |
| 21547 | /* VADDHNv8i8 */ |
| 21548 | 10823, |
| 21549 | /* VADDLsv2i64 */ |
| 21550 | 10828, |
| 21551 | /* VADDLsv4i32 */ |
| 21552 | 10833, |
| 21553 | /* VADDLsv8i16 */ |
| 21554 | 10838, |
| 21555 | /* VADDLuv2i64 */ |
| 21556 | 10843, |
| 21557 | /* VADDLuv4i32 */ |
| 21558 | 10848, |
| 21559 | /* VADDLuv8i16 */ |
| 21560 | 10853, |
| 21561 | /* VADDS */ |
| 21562 | 10858, |
| 21563 | /* VADDWsv2i64 */ |
| 21564 | 10863, |
| 21565 | /* VADDWsv4i32 */ |
| 21566 | 10868, |
| 21567 | /* VADDWsv8i16 */ |
| 21568 | 10873, |
| 21569 | /* VADDWuv2i64 */ |
| 21570 | 10878, |
| 21571 | /* VADDWuv4i32 */ |
| 21572 | 10883, |
| 21573 | /* VADDWuv8i16 */ |
| 21574 | 10888, |
| 21575 | /* VADDfd */ |
| 21576 | 10893, |
| 21577 | /* VADDfq */ |
| 21578 | 10898, |
| 21579 | /* VADDhd */ |
| 21580 | 10903, |
| 21581 | /* VADDhq */ |
| 21582 | 10908, |
| 21583 | /* VADDv16i8 */ |
| 21584 | 10913, |
| 21585 | /* VADDv1i64 */ |
| 21586 | 10918, |
| 21587 | /* VADDv2i32 */ |
| 21588 | 10923, |
| 21589 | /* VADDv2i64 */ |
| 21590 | 10928, |
| 21591 | /* VADDv4i16 */ |
| 21592 | 10933, |
| 21593 | /* VADDv4i32 */ |
| 21594 | 10938, |
| 21595 | /* VADDv8i16 */ |
| 21596 | 10943, |
| 21597 | /* VADDv8i8 */ |
| 21598 | 10948, |
| 21599 | /* VANDd */ |
| 21600 | 10953, |
| 21601 | /* VANDq */ |
| 21602 | 10958, |
| 21603 | /* VBF16MALBQ */ |
| 21604 | 10963, |
| 21605 | /* VBF16MALBQI */ |
| 21606 | 10967, |
| 21607 | /* VBF16MALTQ */ |
| 21608 | 10972, |
| 21609 | /* VBF16MALTQI */ |
| 21610 | 10976, |
| 21611 | /* VBICd */ |
| 21612 | 10981, |
| 21613 | /* VBICiv2i32 */ |
| 21614 | 10986, |
| 21615 | /* VBICiv4i16 */ |
| 21616 | 10991, |
| 21617 | /* VBICiv4i32 */ |
| 21618 | 10996, |
| 21619 | /* VBICiv8i16 */ |
| 21620 | 11001, |
| 21621 | /* VBICq */ |
| 21622 | 11006, |
| 21623 | /* VBIFd */ |
| 21624 | 11011, |
| 21625 | /* VBIFq */ |
| 21626 | 11017, |
| 21627 | /* VBITd */ |
| 21628 | 11023, |
| 21629 | /* VBITq */ |
| 21630 | 11029, |
| 21631 | /* VBSLd */ |
| 21632 | 11035, |
| 21633 | /* VBSLq */ |
| 21634 | 11041, |
| 21635 | /* VBSPd */ |
| 21636 | 11047, |
| 21637 | /* VBSPq */ |
| 21638 | 11053, |
| 21639 | /* VCADDv2f32 */ |
| 21640 | 11059, |
| 21641 | /* VCADDv4f16 */ |
| 21642 | 11063, |
| 21643 | /* VCADDv4f32 */ |
| 21644 | 11067, |
| 21645 | /* VCADDv8f16 */ |
| 21646 | 11071, |
| 21647 | /* VCEQfd */ |
| 21648 | 11075, |
| 21649 | /* VCEQfq */ |
| 21650 | 11080, |
| 21651 | /* VCEQhd */ |
| 21652 | 11085, |
| 21653 | /* VCEQhq */ |
| 21654 | 11090, |
| 21655 | /* VCEQv16i8 */ |
| 21656 | 11095, |
| 21657 | /* VCEQv2i32 */ |
| 21658 | 11100, |
| 21659 | /* VCEQv4i16 */ |
| 21660 | 11105, |
| 21661 | /* VCEQv4i32 */ |
| 21662 | 11110, |
| 21663 | /* VCEQv8i16 */ |
| 21664 | 11115, |
| 21665 | /* VCEQv8i8 */ |
| 21666 | 11120, |
| 21667 | /* VCEQzv16i8 */ |
| 21668 | 11125, |
| 21669 | /* VCEQzv2f32 */ |
| 21670 | 11129, |
| 21671 | /* VCEQzv2i32 */ |
| 21672 | 11133, |
| 21673 | /* VCEQzv4f16 */ |
| 21674 | 11137, |
| 21675 | /* VCEQzv4f32 */ |
| 21676 | 11141, |
| 21677 | /* VCEQzv4i16 */ |
| 21678 | 11145, |
| 21679 | /* VCEQzv4i32 */ |
| 21680 | 11149, |
| 21681 | /* VCEQzv8f16 */ |
| 21682 | 11153, |
| 21683 | /* VCEQzv8i16 */ |
| 21684 | 11157, |
| 21685 | /* VCEQzv8i8 */ |
| 21686 | 11161, |
| 21687 | /* VCGEfd */ |
| 21688 | 11165, |
| 21689 | /* VCGEfq */ |
| 21690 | 11170, |
| 21691 | /* VCGEhd */ |
| 21692 | 11175, |
| 21693 | /* VCGEhq */ |
| 21694 | 11180, |
| 21695 | /* VCGEsv16i8 */ |
| 21696 | 11185, |
| 21697 | /* VCGEsv2i32 */ |
| 21698 | 11190, |
| 21699 | /* VCGEsv4i16 */ |
| 21700 | 11195, |
| 21701 | /* VCGEsv4i32 */ |
| 21702 | 11200, |
| 21703 | /* VCGEsv8i16 */ |
| 21704 | 11205, |
| 21705 | /* VCGEsv8i8 */ |
| 21706 | 11210, |
| 21707 | /* VCGEuv16i8 */ |
| 21708 | 11215, |
| 21709 | /* VCGEuv2i32 */ |
| 21710 | 11220, |
| 21711 | /* VCGEuv4i16 */ |
| 21712 | 11225, |
| 21713 | /* VCGEuv4i32 */ |
| 21714 | 11230, |
| 21715 | /* VCGEuv8i16 */ |
| 21716 | 11235, |
| 21717 | /* VCGEuv8i8 */ |
| 21718 | 11240, |
| 21719 | /* VCGEzv16i8 */ |
| 21720 | 11245, |
| 21721 | /* VCGEzv2f32 */ |
| 21722 | 11249, |
| 21723 | /* VCGEzv2i32 */ |
| 21724 | 11253, |
| 21725 | /* VCGEzv4f16 */ |
| 21726 | 11257, |
| 21727 | /* VCGEzv4f32 */ |
| 21728 | 11261, |
| 21729 | /* VCGEzv4i16 */ |
| 21730 | 11265, |
| 21731 | /* VCGEzv4i32 */ |
| 21732 | 11269, |
| 21733 | /* VCGEzv8f16 */ |
| 21734 | 11273, |
| 21735 | /* VCGEzv8i16 */ |
| 21736 | 11277, |
| 21737 | /* VCGEzv8i8 */ |
| 21738 | 11281, |
| 21739 | /* VCGTfd */ |
| 21740 | 11285, |
| 21741 | /* VCGTfq */ |
| 21742 | 11290, |
| 21743 | /* VCGThd */ |
| 21744 | 11295, |
| 21745 | /* VCGThq */ |
| 21746 | 11300, |
| 21747 | /* VCGTsv16i8 */ |
| 21748 | 11305, |
| 21749 | /* VCGTsv2i32 */ |
| 21750 | 11310, |
| 21751 | /* VCGTsv4i16 */ |
| 21752 | 11315, |
| 21753 | /* VCGTsv4i32 */ |
| 21754 | 11320, |
| 21755 | /* VCGTsv8i16 */ |
| 21756 | 11325, |
| 21757 | /* VCGTsv8i8 */ |
| 21758 | 11330, |
| 21759 | /* VCGTuv16i8 */ |
| 21760 | 11335, |
| 21761 | /* VCGTuv2i32 */ |
| 21762 | 11340, |
| 21763 | /* VCGTuv4i16 */ |
| 21764 | 11345, |
| 21765 | /* VCGTuv4i32 */ |
| 21766 | 11350, |
| 21767 | /* VCGTuv8i16 */ |
| 21768 | 11355, |
| 21769 | /* VCGTuv8i8 */ |
| 21770 | 11360, |
| 21771 | /* VCGTzv16i8 */ |
| 21772 | 11365, |
| 21773 | /* VCGTzv2f32 */ |
| 21774 | 11369, |
| 21775 | /* VCGTzv2i32 */ |
| 21776 | 11373, |
| 21777 | /* VCGTzv4f16 */ |
| 21778 | 11377, |
| 21779 | /* VCGTzv4f32 */ |
| 21780 | 11381, |
| 21781 | /* VCGTzv4i16 */ |
| 21782 | 11385, |
| 21783 | /* VCGTzv4i32 */ |
| 21784 | 11389, |
| 21785 | /* VCGTzv8f16 */ |
| 21786 | 11393, |
| 21787 | /* VCGTzv8i16 */ |
| 21788 | 11397, |
| 21789 | /* VCGTzv8i8 */ |
| 21790 | 11401, |
| 21791 | /* VCLEzv16i8 */ |
| 21792 | 11405, |
| 21793 | /* VCLEzv2f32 */ |
| 21794 | 11409, |
| 21795 | /* VCLEzv2i32 */ |
| 21796 | 11413, |
| 21797 | /* VCLEzv4f16 */ |
| 21798 | 11417, |
| 21799 | /* VCLEzv4f32 */ |
| 21800 | 11421, |
| 21801 | /* VCLEzv4i16 */ |
| 21802 | 11425, |
| 21803 | /* VCLEzv4i32 */ |
| 21804 | 11429, |
| 21805 | /* VCLEzv8f16 */ |
| 21806 | 11433, |
| 21807 | /* VCLEzv8i16 */ |
| 21808 | 11437, |
| 21809 | /* VCLEzv8i8 */ |
| 21810 | 11441, |
| 21811 | /* VCLSv16i8 */ |
| 21812 | 11445, |
| 21813 | /* VCLSv2i32 */ |
| 21814 | 11449, |
| 21815 | /* VCLSv4i16 */ |
| 21816 | 11453, |
| 21817 | /* VCLSv4i32 */ |
| 21818 | 11457, |
| 21819 | /* VCLSv8i16 */ |
| 21820 | 11461, |
| 21821 | /* VCLSv8i8 */ |
| 21822 | 11465, |
| 21823 | /* VCLTzv16i8 */ |
| 21824 | 11469, |
| 21825 | /* VCLTzv2f32 */ |
| 21826 | 11473, |
| 21827 | /* VCLTzv2i32 */ |
| 21828 | 11477, |
| 21829 | /* VCLTzv4f16 */ |
| 21830 | 11481, |
| 21831 | /* VCLTzv4f32 */ |
| 21832 | 11485, |
| 21833 | /* VCLTzv4i16 */ |
| 21834 | 11489, |
| 21835 | /* VCLTzv4i32 */ |
| 21836 | 11493, |
| 21837 | /* VCLTzv8f16 */ |
| 21838 | 11497, |
| 21839 | /* VCLTzv8i16 */ |
| 21840 | 11501, |
| 21841 | /* VCLTzv8i8 */ |
| 21842 | 11505, |
| 21843 | /* VCLZv16i8 */ |
| 21844 | 11509, |
| 21845 | /* VCLZv2i32 */ |
| 21846 | 11513, |
| 21847 | /* VCLZv4i16 */ |
| 21848 | 11517, |
| 21849 | /* VCLZv4i32 */ |
| 21850 | 11521, |
| 21851 | /* VCLZv8i16 */ |
| 21852 | 11525, |
| 21853 | /* VCLZv8i8 */ |
| 21854 | 11529, |
| 21855 | /* VCMLAv2f32 */ |
| 21856 | 11533, |
| 21857 | /* VCMLAv2f32_indexed */ |
| 21858 | 11538, |
| 21859 | /* VCMLAv4f16 */ |
| 21860 | 11544, |
| 21861 | /* VCMLAv4f16_indexed */ |
| 21862 | 11549, |
| 21863 | /* VCMLAv4f32 */ |
| 21864 | 11555, |
| 21865 | /* VCMLAv4f32_indexed */ |
| 21866 | 11560, |
| 21867 | /* VCMLAv8f16 */ |
| 21868 | 11566, |
| 21869 | /* VCMLAv8f16_indexed */ |
| 21870 | 11571, |
| 21871 | /* VCMPD */ |
| 21872 | 11577, |
| 21873 | /* VCMPED */ |
| 21874 | 11581, |
| 21875 | /* VCMPEH */ |
| 21876 | 11585, |
| 21877 | /* VCMPES */ |
| 21878 | 11589, |
| 21879 | /* VCMPEZD */ |
| 21880 | 11593, |
| 21881 | /* VCMPEZH */ |
| 21882 | 11596, |
| 21883 | /* VCMPEZS */ |
| 21884 | 11599, |
| 21885 | /* VCMPH */ |
| 21886 | 11602, |
| 21887 | /* VCMPS */ |
| 21888 | 11606, |
| 21889 | /* VCMPZD */ |
| 21890 | 11610, |
| 21891 | /* VCMPZH */ |
| 21892 | 11613, |
| 21893 | /* VCMPZS */ |
| 21894 | 11616, |
| 21895 | /* VCNTd */ |
| 21896 | 11619, |
| 21897 | /* VCNTq */ |
| 21898 | 11623, |
| 21899 | /* VCVTANSDf */ |
| 21900 | 11627, |
| 21901 | /* VCVTANSDh */ |
| 21902 | 11629, |
| 21903 | /* VCVTANSQf */ |
| 21904 | 11631, |
| 21905 | /* VCVTANSQh */ |
| 21906 | 11633, |
| 21907 | /* VCVTANUDf */ |
| 21908 | 11635, |
| 21909 | /* VCVTANUDh */ |
| 21910 | 11637, |
| 21911 | /* VCVTANUQf */ |
| 21912 | 11639, |
| 21913 | /* VCVTANUQh */ |
| 21914 | 11641, |
| 21915 | /* VCVTASD */ |
| 21916 | 11643, |
| 21917 | /* VCVTASH */ |
| 21918 | 11645, |
| 21919 | /* VCVTASS */ |
| 21920 | 11647, |
| 21921 | /* VCVTAUD */ |
| 21922 | 11649, |
| 21923 | /* VCVTAUH */ |
| 21924 | 11651, |
| 21925 | /* VCVTAUS */ |
| 21926 | 11653, |
| 21927 | /* VCVTBDH */ |
| 21928 | 11655, |
| 21929 | /* VCVTBHD */ |
| 21930 | 11660, |
| 21931 | /* VCVTBHS */ |
| 21932 | 11664, |
| 21933 | /* VCVTBSH */ |
| 21934 | 11668, |
| 21935 | /* VCVTDS */ |
| 21936 | 11673, |
| 21937 | /* VCVTMNSDf */ |
| 21938 | 11677, |
| 21939 | /* VCVTMNSDh */ |
| 21940 | 11679, |
| 21941 | /* VCVTMNSQf */ |
| 21942 | 11681, |
| 21943 | /* VCVTMNSQh */ |
| 21944 | 11683, |
| 21945 | /* VCVTMNUDf */ |
| 21946 | 11685, |
| 21947 | /* VCVTMNUDh */ |
| 21948 | 11687, |
| 21949 | /* VCVTMNUQf */ |
| 21950 | 11689, |
| 21951 | /* VCVTMNUQh */ |
| 21952 | 11691, |
| 21953 | /* VCVTMSD */ |
| 21954 | 11693, |
| 21955 | /* VCVTMSH */ |
| 21956 | 11695, |
| 21957 | /* VCVTMSS */ |
| 21958 | 11697, |
| 21959 | /* VCVTMUD */ |
| 21960 | 11699, |
| 21961 | /* VCVTMUH */ |
| 21962 | 11701, |
| 21963 | /* VCVTMUS */ |
| 21964 | 11703, |
| 21965 | /* VCVTNNSDf */ |
| 21966 | 11705, |
| 21967 | /* VCVTNNSDh */ |
| 21968 | 11707, |
| 21969 | /* VCVTNNSQf */ |
| 21970 | 11709, |
| 21971 | /* VCVTNNSQh */ |
| 21972 | 11711, |
| 21973 | /* VCVTNNUDf */ |
| 21974 | 11713, |
| 21975 | /* VCVTNNUDh */ |
| 21976 | 11715, |
| 21977 | /* VCVTNNUQf */ |
| 21978 | 11717, |
| 21979 | /* VCVTNNUQh */ |
| 21980 | 11719, |
| 21981 | /* VCVTNSD */ |
| 21982 | 11721, |
| 21983 | /* VCVTNSH */ |
| 21984 | 11723, |
| 21985 | /* VCVTNSS */ |
| 21986 | 11725, |
| 21987 | /* VCVTNUD */ |
| 21988 | 11727, |
| 21989 | /* VCVTNUH */ |
| 21990 | 11729, |
| 21991 | /* VCVTNUS */ |
| 21992 | 11731, |
| 21993 | /* VCVTPNSDf */ |
| 21994 | 11733, |
| 21995 | /* VCVTPNSDh */ |
| 21996 | 11735, |
| 21997 | /* VCVTPNSQf */ |
| 21998 | 11737, |
| 21999 | /* VCVTPNSQh */ |
| 22000 | 11739, |
| 22001 | /* VCVTPNUDf */ |
| 22002 | 11741, |
| 22003 | /* VCVTPNUDh */ |
| 22004 | 11743, |
| 22005 | /* VCVTPNUQf */ |
| 22006 | 11745, |
| 22007 | /* VCVTPNUQh */ |
| 22008 | 11747, |
| 22009 | /* VCVTPSD */ |
| 22010 | 11749, |
| 22011 | /* VCVTPSH */ |
| 22012 | 11751, |
| 22013 | /* VCVTPSS */ |
| 22014 | 11753, |
| 22015 | /* VCVTPUD */ |
| 22016 | 11755, |
| 22017 | /* VCVTPUH */ |
| 22018 | 11757, |
| 22019 | /* VCVTPUS */ |
| 22020 | 11759, |
| 22021 | /* VCVTSD */ |
| 22022 | 11761, |
| 22023 | /* VCVTTDH */ |
| 22024 | 11765, |
| 22025 | /* VCVTTHD */ |
| 22026 | 11770, |
| 22027 | /* VCVTTHS */ |
| 22028 | 11774, |
| 22029 | /* VCVTTSH */ |
| 22030 | 11778, |
| 22031 | /* VCVTf2h */ |
| 22032 | 11783, |
| 22033 | /* VCVTf2sd */ |
| 22034 | 11787, |
| 22035 | /* VCVTf2sq */ |
| 22036 | 11791, |
| 22037 | /* VCVTf2ud */ |
| 22038 | 11795, |
| 22039 | /* VCVTf2uq */ |
| 22040 | 11799, |
| 22041 | /* VCVTf2xsd */ |
| 22042 | 11803, |
| 22043 | /* VCVTf2xsq */ |
| 22044 | 11808, |
| 22045 | /* VCVTf2xud */ |
| 22046 | 11813, |
| 22047 | /* VCVTf2xuq */ |
| 22048 | 11818, |
| 22049 | /* VCVTh2f */ |
| 22050 | 11823, |
| 22051 | /* VCVTh2sd */ |
| 22052 | 11827, |
| 22053 | /* VCVTh2sq */ |
| 22054 | 11831, |
| 22055 | /* VCVTh2ud */ |
| 22056 | 11835, |
| 22057 | /* VCVTh2uq */ |
| 22058 | 11839, |
| 22059 | /* VCVTh2xsd */ |
| 22060 | 11843, |
| 22061 | /* VCVTh2xsq */ |
| 22062 | 11848, |
| 22063 | /* VCVTh2xud */ |
| 22064 | 11853, |
| 22065 | /* VCVTh2xuq */ |
| 22066 | 11858, |
| 22067 | /* VCVTs2fd */ |
| 22068 | 11863, |
| 22069 | /* VCVTs2fq */ |
| 22070 | 11867, |
| 22071 | /* VCVTs2hd */ |
| 22072 | 11871, |
| 22073 | /* VCVTs2hq */ |
| 22074 | 11875, |
| 22075 | /* VCVTu2fd */ |
| 22076 | 11879, |
| 22077 | /* VCVTu2fq */ |
| 22078 | 11883, |
| 22079 | /* VCVTu2hd */ |
| 22080 | 11887, |
| 22081 | /* VCVTu2hq */ |
| 22082 | 11891, |
| 22083 | /* VCVTxs2fd */ |
| 22084 | 11895, |
| 22085 | /* VCVTxs2fq */ |
| 22086 | 11900, |
| 22087 | /* VCVTxs2hd */ |
| 22088 | 11905, |
| 22089 | /* VCVTxs2hq */ |
| 22090 | 11910, |
| 22091 | /* VCVTxu2fd */ |
| 22092 | 11915, |
| 22093 | /* VCVTxu2fq */ |
| 22094 | 11920, |
| 22095 | /* VCVTxu2hd */ |
| 22096 | 11925, |
| 22097 | /* VCVTxu2hq */ |
| 22098 | 11930, |
| 22099 | /* VDIVD */ |
| 22100 | 11935, |
| 22101 | /* VDIVH */ |
| 22102 | 11940, |
| 22103 | /* VDIVS */ |
| 22104 | 11945, |
| 22105 | /* VDUP16d */ |
| 22106 | 11950, |
| 22107 | /* VDUP16q */ |
| 22108 | 11954, |
| 22109 | /* VDUP32d */ |
| 22110 | 11958, |
| 22111 | /* VDUP32q */ |
| 22112 | 11962, |
| 22113 | /* VDUP8d */ |
| 22114 | 11966, |
| 22115 | /* VDUP8q */ |
| 22116 | 11970, |
| 22117 | /* VDUPLN16d */ |
| 22118 | 11974, |
| 22119 | /* VDUPLN16q */ |
| 22120 | 11979, |
| 22121 | /* VDUPLN32d */ |
| 22122 | 11984, |
| 22123 | /* VDUPLN32q */ |
| 22124 | 11989, |
| 22125 | /* VDUPLN8d */ |
| 22126 | 11994, |
| 22127 | /* VDUPLN8q */ |
| 22128 | 11999, |
| 22129 | /* VEORd */ |
| 22130 | 12004, |
| 22131 | /* VEORq */ |
| 22132 | 12009, |
| 22133 | /* VEXTd16 */ |
| 22134 | 12014, |
| 22135 | /* VEXTd32 */ |
| 22136 | 12020, |
| 22137 | /* VEXTd8 */ |
| 22138 | 12026, |
| 22139 | /* VEXTq16 */ |
| 22140 | 12032, |
| 22141 | /* VEXTq32 */ |
| 22142 | 12038, |
| 22143 | /* VEXTq64 */ |
| 22144 | 12044, |
| 22145 | /* VEXTq8 */ |
| 22146 | 12050, |
| 22147 | /* VFMAD */ |
| 22148 | 12056, |
| 22149 | /* VFMAH */ |
| 22150 | 12062, |
| 22151 | /* VFMALD */ |
| 22152 | 12068, |
| 22153 | /* VFMALDI */ |
| 22154 | 12071, |
| 22155 | /* VFMALQ */ |
| 22156 | 12075, |
| 22157 | /* VFMALQI */ |
| 22158 | 12078, |
| 22159 | /* VFMAS */ |
| 22160 | 12082, |
| 22161 | /* VFMAfd */ |
| 22162 | 12088, |
| 22163 | /* VFMAfq */ |
| 22164 | 12094, |
| 22165 | /* VFMAhd */ |
| 22166 | 12100, |
| 22167 | /* VFMAhq */ |
| 22168 | 12106, |
| 22169 | /* VFMSD */ |
| 22170 | 12112, |
| 22171 | /* VFMSH */ |
| 22172 | 12118, |
| 22173 | /* VFMSLD */ |
| 22174 | 12124, |
| 22175 | /* VFMSLDI */ |
| 22176 | 12127, |
| 22177 | /* VFMSLQ */ |
| 22178 | 12131, |
| 22179 | /* VFMSLQI */ |
| 22180 | 12134, |
| 22181 | /* VFMSS */ |
| 22182 | 12138, |
| 22183 | /* VFMSfd */ |
| 22184 | 12144, |
| 22185 | /* VFMSfq */ |
| 22186 | 12150, |
| 22187 | /* VFMShd */ |
| 22188 | 12156, |
| 22189 | /* VFMShq */ |
| 22190 | 12162, |
| 22191 | /* VFNMAD */ |
| 22192 | 12168, |
| 22193 | /* VFNMAH */ |
| 22194 | 12174, |
| 22195 | /* VFNMAS */ |
| 22196 | 12180, |
| 22197 | /* VFNMSD */ |
| 22198 | 12186, |
| 22199 | /* VFNMSH */ |
| 22200 | 12192, |
| 22201 | /* VFNMSS */ |
| 22202 | 12198, |
| 22203 | /* VFP_VMAXNMD */ |
| 22204 | 12204, |
| 22205 | /* VFP_VMAXNMH */ |
| 22206 | 12207, |
| 22207 | /* VFP_VMAXNMS */ |
| 22208 | 12210, |
| 22209 | /* VFP_VMINNMD */ |
| 22210 | 12213, |
| 22211 | /* VFP_VMINNMH */ |
| 22212 | 12216, |
| 22213 | /* VFP_VMINNMS */ |
| 22214 | 12219, |
| 22215 | /* VGETLNi32 */ |
| 22216 | 12222, |
| 22217 | /* VGETLNs16 */ |
| 22218 | 12227, |
| 22219 | /* VGETLNs8 */ |
| 22220 | 12232, |
| 22221 | /* VGETLNu16 */ |
| 22222 | 12237, |
| 22223 | /* VGETLNu8 */ |
| 22224 | 12242, |
| 22225 | /* VHADDsv16i8 */ |
| 22226 | 12247, |
| 22227 | /* VHADDsv2i32 */ |
| 22228 | 12252, |
| 22229 | /* VHADDsv4i16 */ |
| 22230 | 12257, |
| 22231 | /* VHADDsv4i32 */ |
| 22232 | 12262, |
| 22233 | /* VHADDsv8i16 */ |
| 22234 | 12267, |
| 22235 | /* VHADDsv8i8 */ |
| 22236 | 12272, |
| 22237 | /* VHADDuv16i8 */ |
| 22238 | 12277, |
| 22239 | /* VHADDuv2i32 */ |
| 22240 | 12282, |
| 22241 | /* VHADDuv4i16 */ |
| 22242 | 12287, |
| 22243 | /* VHADDuv4i32 */ |
| 22244 | 12292, |
| 22245 | /* VHADDuv8i16 */ |
| 22246 | 12297, |
| 22247 | /* VHADDuv8i8 */ |
| 22248 | 12302, |
| 22249 | /* VHSUBsv16i8 */ |
| 22250 | 12307, |
| 22251 | /* VHSUBsv2i32 */ |
| 22252 | 12312, |
| 22253 | /* VHSUBsv4i16 */ |
| 22254 | 12317, |
| 22255 | /* VHSUBsv4i32 */ |
| 22256 | 12322, |
| 22257 | /* VHSUBsv8i16 */ |
| 22258 | 12327, |
| 22259 | /* VHSUBsv8i8 */ |
| 22260 | 12332, |
| 22261 | /* VHSUBuv16i8 */ |
| 22262 | 12337, |
| 22263 | /* VHSUBuv2i32 */ |
| 22264 | 12342, |
| 22265 | /* VHSUBuv4i16 */ |
| 22266 | 12347, |
| 22267 | /* VHSUBuv4i32 */ |
| 22268 | 12352, |
| 22269 | /* VHSUBuv8i16 */ |
| 22270 | 12357, |
| 22271 | /* VHSUBuv8i8 */ |
| 22272 | 12362, |
| 22273 | /* VINSH */ |
| 22274 | 12367, |
| 22275 | /* VJCVT */ |
| 22276 | 12370, |
| 22277 | /* VLD1DUPd16 */ |
| 22278 | 12374, |
| 22279 | /* VLD1DUPd16wb_fixed */ |
| 22280 | 12379, |
| 22281 | /* VLD1DUPd16wb_register */ |
| 22282 | 12385, |
| 22283 | /* VLD1DUPd32 */ |
| 22284 | 12392, |
| 22285 | /* VLD1DUPd32wb_fixed */ |
| 22286 | 12397, |
| 22287 | /* VLD1DUPd32wb_register */ |
| 22288 | 12403, |
| 22289 | /* VLD1DUPd8 */ |
| 22290 | 12410, |
| 22291 | /* VLD1DUPd8wb_fixed */ |
| 22292 | 12415, |
| 22293 | /* VLD1DUPd8wb_register */ |
| 22294 | 12421, |
| 22295 | /* VLD1DUPq16 */ |
| 22296 | 12428, |
| 22297 | /* VLD1DUPq16wb_fixed */ |
| 22298 | 12433, |
| 22299 | /* VLD1DUPq16wb_register */ |
| 22300 | 12439, |
| 22301 | /* VLD1DUPq32 */ |
| 22302 | 12446, |
| 22303 | /* VLD1DUPq32wb_fixed */ |
| 22304 | 12451, |
| 22305 | /* VLD1DUPq32wb_register */ |
| 22306 | 12457, |
| 22307 | /* VLD1DUPq8 */ |
| 22308 | 12464, |
| 22309 | /* VLD1DUPq8wb_fixed */ |
| 22310 | 12469, |
| 22311 | /* VLD1DUPq8wb_register */ |
| 22312 | 12475, |
| 22313 | /* VLD1LNd16 */ |
| 22314 | 12482, |
| 22315 | /* VLD1LNd16_UPD */ |
| 22316 | 12489, |
| 22317 | /* VLD1LNd32 */ |
| 22318 | 12498, |
| 22319 | /* VLD1LNd32_UPD */ |
| 22320 | 12505, |
| 22321 | /* VLD1LNd8 */ |
| 22322 | 12514, |
| 22323 | /* VLD1LNd8_UPD */ |
| 22324 | 12521, |
| 22325 | /* VLD1LNq16Pseudo */ |
| 22326 | 12530, |
| 22327 | /* VLD1LNq16Pseudo_UPD */ |
| 22328 | 12537, |
| 22329 | /* VLD1LNq32Pseudo */ |
| 22330 | 12546, |
| 22331 | /* VLD1LNq32Pseudo_UPD */ |
| 22332 | 12553, |
| 22333 | /* VLD1LNq8Pseudo */ |
| 22334 | 12562, |
| 22335 | /* VLD1LNq8Pseudo_UPD */ |
| 22336 | 12569, |
| 22337 | /* VLD1d16 */ |
| 22338 | 12578, |
| 22339 | /* VLD1d16Q */ |
| 22340 | 12583, |
| 22341 | /* VLD1d16QPseudo */ |
| 22342 | 12588, |
| 22343 | /* VLD1d16QPseudoWB_fixed */ |
| 22344 | 12593, |
| 22345 | /* VLD1d16QPseudoWB_register */ |
| 22346 | 12599, |
| 22347 | /* VLD1d16Qwb_fixed */ |
| 22348 | 12606, |
| 22349 | /* VLD1d16Qwb_register */ |
| 22350 | 12612, |
| 22351 | /* VLD1d16T */ |
| 22352 | 12619, |
| 22353 | /* VLD1d16TPseudo */ |
| 22354 | 12624, |
| 22355 | /* VLD1d16TPseudoWB_fixed */ |
| 22356 | 12629, |
| 22357 | /* VLD1d16TPseudoWB_register */ |
| 22358 | 12635, |
| 22359 | /* VLD1d16Twb_fixed */ |
| 22360 | 12642, |
| 22361 | /* VLD1d16Twb_register */ |
| 22362 | 12648, |
| 22363 | /* VLD1d16wb_fixed */ |
| 22364 | 12655, |
| 22365 | /* VLD1d16wb_register */ |
| 22366 | 12661, |
| 22367 | /* VLD1d32 */ |
| 22368 | 12668, |
| 22369 | /* VLD1d32Q */ |
| 22370 | 12673, |
| 22371 | /* VLD1d32QPseudo */ |
| 22372 | 12678, |
| 22373 | /* VLD1d32QPseudoWB_fixed */ |
| 22374 | 12683, |
| 22375 | /* VLD1d32QPseudoWB_register */ |
| 22376 | 12689, |
| 22377 | /* VLD1d32Qwb_fixed */ |
| 22378 | 12696, |
| 22379 | /* VLD1d32Qwb_register */ |
| 22380 | 12702, |
| 22381 | /* VLD1d32T */ |
| 22382 | 12709, |
| 22383 | /* VLD1d32TPseudo */ |
| 22384 | 12714, |
| 22385 | /* VLD1d32TPseudoWB_fixed */ |
| 22386 | 12719, |
| 22387 | /* VLD1d32TPseudoWB_register */ |
| 22388 | 12725, |
| 22389 | /* VLD1d32Twb_fixed */ |
| 22390 | 12732, |
| 22391 | /* VLD1d32Twb_register */ |
| 22392 | 12738, |
| 22393 | /* VLD1d32wb_fixed */ |
| 22394 | 12745, |
| 22395 | /* VLD1d32wb_register */ |
| 22396 | 12751, |
| 22397 | /* VLD1d64 */ |
| 22398 | 12758, |
| 22399 | /* VLD1d64Q */ |
| 22400 | 12763, |
| 22401 | /* VLD1d64QPseudo */ |
| 22402 | 12768, |
| 22403 | /* VLD1d64QPseudoWB_fixed */ |
| 22404 | 12773, |
| 22405 | /* VLD1d64QPseudoWB_register */ |
| 22406 | 12779, |
| 22407 | /* VLD1d64Qwb_fixed */ |
| 22408 | 12786, |
| 22409 | /* VLD1d64Qwb_register */ |
| 22410 | 12792, |
| 22411 | /* VLD1d64T */ |
| 22412 | 12799, |
| 22413 | /* VLD1d64TPseudo */ |
| 22414 | 12804, |
| 22415 | /* VLD1d64TPseudoWB_fixed */ |
| 22416 | 12809, |
| 22417 | /* VLD1d64TPseudoWB_register */ |
| 22418 | 12815, |
| 22419 | /* VLD1d64Twb_fixed */ |
| 22420 | 12822, |
| 22421 | /* VLD1d64Twb_register */ |
| 22422 | 12828, |
| 22423 | /* VLD1d64wb_fixed */ |
| 22424 | 12835, |
| 22425 | /* VLD1d64wb_register */ |
| 22426 | 12841, |
| 22427 | /* VLD1d8 */ |
| 22428 | 12848, |
| 22429 | /* VLD1d8Q */ |
| 22430 | 12853, |
| 22431 | /* VLD1d8QPseudo */ |
| 22432 | 12858, |
| 22433 | /* VLD1d8QPseudoWB_fixed */ |
| 22434 | 12863, |
| 22435 | /* VLD1d8QPseudoWB_register */ |
| 22436 | 12869, |
| 22437 | /* VLD1d8Qwb_fixed */ |
| 22438 | 12876, |
| 22439 | /* VLD1d8Qwb_register */ |
| 22440 | 12882, |
| 22441 | /* VLD1d8T */ |
| 22442 | 12889, |
| 22443 | /* VLD1d8TPseudo */ |
| 22444 | 12894, |
| 22445 | /* VLD1d8TPseudoWB_fixed */ |
| 22446 | 12899, |
| 22447 | /* VLD1d8TPseudoWB_register */ |
| 22448 | 12905, |
| 22449 | /* VLD1d8Twb_fixed */ |
| 22450 | 12912, |
| 22451 | /* VLD1d8Twb_register */ |
| 22452 | 12918, |
| 22453 | /* VLD1d8wb_fixed */ |
| 22454 | 12925, |
| 22455 | /* VLD1d8wb_register */ |
| 22456 | 12931, |
| 22457 | /* VLD1q16 */ |
| 22458 | 12938, |
| 22459 | /* VLD1q16HighQPseudo */ |
| 22460 | 12943, |
| 22461 | /* VLD1q16HighQPseudo_UPD */ |
| 22462 | 12949, |
| 22463 | /* VLD1q16HighTPseudo */ |
| 22464 | 12957, |
| 22465 | /* VLD1q16HighTPseudo_UPD */ |
| 22466 | 12963, |
| 22467 | /* VLD1q16LowQPseudo_UPD */ |
| 22468 | 12971, |
| 22469 | /* VLD1q16LowTPseudo_UPD */ |
| 22470 | 12979, |
| 22471 | /* VLD1q16wb_fixed */ |
| 22472 | 12987, |
| 22473 | /* VLD1q16wb_register */ |
| 22474 | 12993, |
| 22475 | /* VLD1q32 */ |
| 22476 | 13000, |
| 22477 | /* VLD1q32HighQPseudo */ |
| 22478 | 13005, |
| 22479 | /* VLD1q32HighQPseudo_UPD */ |
| 22480 | 13011, |
| 22481 | /* VLD1q32HighTPseudo */ |
| 22482 | 13019, |
| 22483 | /* VLD1q32HighTPseudo_UPD */ |
| 22484 | 13025, |
| 22485 | /* VLD1q32LowQPseudo_UPD */ |
| 22486 | 13033, |
| 22487 | /* VLD1q32LowTPseudo_UPD */ |
| 22488 | 13041, |
| 22489 | /* VLD1q32wb_fixed */ |
| 22490 | 13049, |
| 22491 | /* VLD1q32wb_register */ |
| 22492 | 13055, |
| 22493 | /* VLD1q64 */ |
| 22494 | 13062, |
| 22495 | /* VLD1q64HighQPseudo */ |
| 22496 | 13067, |
| 22497 | /* VLD1q64HighQPseudo_UPD */ |
| 22498 | 13073, |
| 22499 | /* VLD1q64HighTPseudo */ |
| 22500 | 13081, |
| 22501 | /* VLD1q64HighTPseudo_UPD */ |
| 22502 | 13087, |
| 22503 | /* VLD1q64LowQPseudo_UPD */ |
| 22504 | 13095, |
| 22505 | /* VLD1q64LowTPseudo_UPD */ |
| 22506 | 13103, |
| 22507 | /* VLD1q64wb_fixed */ |
| 22508 | 13111, |
| 22509 | /* VLD1q64wb_register */ |
| 22510 | 13117, |
| 22511 | /* VLD1q8 */ |
| 22512 | 13124, |
| 22513 | /* VLD1q8HighQPseudo */ |
| 22514 | 13129, |
| 22515 | /* VLD1q8HighQPseudo_UPD */ |
| 22516 | 13135, |
| 22517 | /* VLD1q8HighTPseudo */ |
| 22518 | 13143, |
| 22519 | /* VLD1q8HighTPseudo_UPD */ |
| 22520 | 13149, |
| 22521 | /* VLD1q8LowQPseudo_UPD */ |
| 22522 | 13157, |
| 22523 | /* VLD1q8LowTPseudo_UPD */ |
| 22524 | 13165, |
| 22525 | /* VLD1q8wb_fixed */ |
| 22526 | 13173, |
| 22527 | /* VLD1q8wb_register */ |
| 22528 | 13179, |
| 22529 | /* VLD2DUPd16 */ |
| 22530 | 13186, |
| 22531 | /* VLD2DUPd16wb_fixed */ |
| 22532 | 13191, |
| 22533 | /* VLD2DUPd16wb_register */ |
| 22534 | 13197, |
| 22535 | /* VLD2DUPd16x2 */ |
| 22536 | 13204, |
| 22537 | /* VLD2DUPd16x2wb_fixed */ |
| 22538 | 13209, |
| 22539 | /* VLD2DUPd16x2wb_register */ |
| 22540 | 13215, |
| 22541 | /* VLD2DUPd32 */ |
| 22542 | 13222, |
| 22543 | /* VLD2DUPd32wb_fixed */ |
| 22544 | 13227, |
| 22545 | /* VLD2DUPd32wb_register */ |
| 22546 | 13233, |
| 22547 | /* VLD2DUPd32x2 */ |
| 22548 | 13240, |
| 22549 | /* VLD2DUPd32x2wb_fixed */ |
| 22550 | 13245, |
| 22551 | /* VLD2DUPd32x2wb_register */ |
| 22552 | 13251, |
| 22553 | /* VLD2DUPd8 */ |
| 22554 | 13258, |
| 22555 | /* VLD2DUPd8wb_fixed */ |
| 22556 | 13263, |
| 22557 | /* VLD2DUPd8wb_register */ |
| 22558 | 13269, |
| 22559 | /* VLD2DUPd8x2 */ |
| 22560 | 13276, |
| 22561 | /* VLD2DUPd8x2wb_fixed */ |
| 22562 | 13281, |
| 22563 | /* VLD2DUPd8x2wb_register */ |
| 22564 | 13287, |
| 22565 | /* VLD2DUPq16EvenPseudo */ |
| 22566 | 13294, |
| 22567 | /* VLD2DUPq16OddPseudo */ |
| 22568 | 13300, |
| 22569 | /* VLD2DUPq16OddPseudoWB_fixed */ |
| 22570 | 13306, |
| 22571 | /* VLD2DUPq16OddPseudoWB_register */ |
| 22572 | 13313, |
| 22573 | /* VLD2DUPq32EvenPseudo */ |
| 22574 | 13321, |
| 22575 | /* VLD2DUPq32OddPseudo */ |
| 22576 | 13327, |
| 22577 | /* VLD2DUPq32OddPseudoWB_fixed */ |
| 22578 | 13333, |
| 22579 | /* VLD2DUPq32OddPseudoWB_register */ |
| 22580 | 13340, |
| 22581 | /* VLD2DUPq8EvenPseudo */ |
| 22582 | 13348, |
| 22583 | /* VLD2DUPq8OddPseudo */ |
| 22584 | 13354, |
| 22585 | /* VLD2DUPq8OddPseudoWB_fixed */ |
| 22586 | 13360, |
| 22587 | /* VLD2DUPq8OddPseudoWB_register */ |
| 22588 | 13367, |
| 22589 | /* VLD2LNd16 */ |
| 22590 | 13375, |
| 22591 | /* VLD2LNd16Pseudo */ |
| 22592 | 13384, |
| 22593 | /* VLD2LNd16Pseudo_UPD */ |
| 22594 | 13391, |
| 22595 | /* VLD2LNd16_UPD */ |
| 22596 | 13400, |
| 22597 | /* VLD2LNd32 */ |
| 22598 | 13411, |
| 22599 | /* VLD2LNd32Pseudo */ |
| 22600 | 13420, |
| 22601 | /* VLD2LNd32Pseudo_UPD */ |
| 22602 | 13427, |
| 22603 | /* VLD2LNd32_UPD */ |
| 22604 | 13436, |
| 22605 | /* VLD2LNd8 */ |
| 22606 | 13447, |
| 22607 | /* VLD2LNd8Pseudo */ |
| 22608 | 13456, |
| 22609 | /* VLD2LNd8Pseudo_UPD */ |
| 22610 | 13463, |
| 22611 | /* VLD2LNd8_UPD */ |
| 22612 | 13472, |
| 22613 | /* VLD2LNq16 */ |
| 22614 | 13483, |
| 22615 | /* VLD2LNq16Pseudo */ |
| 22616 | 13492, |
| 22617 | /* VLD2LNq16Pseudo_UPD */ |
| 22618 | 13499, |
| 22619 | /* VLD2LNq16_UPD */ |
| 22620 | 13508, |
| 22621 | /* VLD2LNq32 */ |
| 22622 | 13519, |
| 22623 | /* VLD2LNq32Pseudo */ |
| 22624 | 13528, |
| 22625 | /* VLD2LNq32Pseudo_UPD */ |
| 22626 | 13535, |
| 22627 | /* VLD2LNq32_UPD */ |
| 22628 | 13544, |
| 22629 | /* VLD2b16 */ |
| 22630 | 13555, |
| 22631 | /* VLD2b16wb_fixed */ |
| 22632 | 13560, |
| 22633 | /* VLD2b16wb_register */ |
| 22634 | 13566, |
| 22635 | /* VLD2b32 */ |
| 22636 | 13573, |
| 22637 | /* VLD2b32wb_fixed */ |
| 22638 | 13578, |
| 22639 | /* VLD2b32wb_register */ |
| 22640 | 13584, |
| 22641 | /* VLD2b8 */ |
| 22642 | 13591, |
| 22643 | /* VLD2b8wb_fixed */ |
| 22644 | 13596, |
| 22645 | /* VLD2b8wb_register */ |
| 22646 | 13602, |
| 22647 | /* VLD2d16 */ |
| 22648 | 13609, |
| 22649 | /* VLD2d16wb_fixed */ |
| 22650 | 13614, |
| 22651 | /* VLD2d16wb_register */ |
| 22652 | 13620, |
| 22653 | /* VLD2d32 */ |
| 22654 | 13627, |
| 22655 | /* VLD2d32wb_fixed */ |
| 22656 | 13632, |
| 22657 | /* VLD2d32wb_register */ |
| 22658 | 13638, |
| 22659 | /* VLD2d8 */ |
| 22660 | 13645, |
| 22661 | /* VLD2d8wb_fixed */ |
| 22662 | 13650, |
| 22663 | /* VLD2d8wb_register */ |
| 22664 | 13656, |
| 22665 | /* VLD2q16 */ |
| 22666 | 13663, |
| 22667 | /* VLD2q16Pseudo */ |
| 22668 | 13668, |
| 22669 | /* VLD2q16PseudoWB_fixed */ |
| 22670 | 13673, |
| 22671 | /* VLD2q16PseudoWB_register */ |
| 22672 | 13679, |
| 22673 | /* VLD2q16wb_fixed */ |
| 22674 | 13686, |
| 22675 | /* VLD2q16wb_register */ |
| 22676 | 13692, |
| 22677 | /* VLD2q32 */ |
| 22678 | 13699, |
| 22679 | /* VLD2q32Pseudo */ |
| 22680 | 13704, |
| 22681 | /* VLD2q32PseudoWB_fixed */ |
| 22682 | 13709, |
| 22683 | /* VLD2q32PseudoWB_register */ |
| 22684 | 13715, |
| 22685 | /* VLD2q32wb_fixed */ |
| 22686 | 13722, |
| 22687 | /* VLD2q32wb_register */ |
| 22688 | 13728, |
| 22689 | /* VLD2q8 */ |
| 22690 | 13735, |
| 22691 | /* VLD2q8Pseudo */ |
| 22692 | 13740, |
| 22693 | /* VLD2q8PseudoWB_fixed */ |
| 22694 | 13745, |
| 22695 | /* VLD2q8PseudoWB_register */ |
| 22696 | 13751, |
| 22697 | /* VLD2q8wb_fixed */ |
| 22698 | 13758, |
| 22699 | /* VLD2q8wb_register */ |
| 22700 | 13764, |
| 22701 | /* VLD3DUPd16 */ |
| 22702 | 13771, |
| 22703 | /* VLD3DUPd16Pseudo */ |
| 22704 | 13778, |
| 22705 | /* VLD3DUPd16Pseudo_UPD */ |
| 22706 | 13783, |
| 22707 | /* VLD3DUPd16_UPD */ |
| 22708 | 13790, |
| 22709 | /* VLD3DUPd32 */ |
| 22710 | 13799, |
| 22711 | /* VLD3DUPd32Pseudo */ |
| 22712 | 13806, |
| 22713 | /* VLD3DUPd32Pseudo_UPD */ |
| 22714 | 13811, |
| 22715 | /* VLD3DUPd32_UPD */ |
| 22716 | 13818, |
| 22717 | /* VLD3DUPd8 */ |
| 22718 | 13827, |
| 22719 | /* VLD3DUPd8Pseudo */ |
| 22720 | 13834, |
| 22721 | /* VLD3DUPd8Pseudo_UPD */ |
| 22722 | 13839, |
| 22723 | /* VLD3DUPd8_UPD */ |
| 22724 | 13846, |
| 22725 | /* VLD3DUPq16 */ |
| 22726 | 13855, |
| 22727 | /* VLD3DUPq16EvenPseudo */ |
| 22728 | 13862, |
| 22729 | /* VLD3DUPq16OddPseudo */ |
| 22730 | 13868, |
| 22731 | /* VLD3DUPq16OddPseudo_UPD */ |
| 22732 | 13874, |
| 22733 | /* VLD3DUPq16_UPD */ |
| 22734 | 13882, |
| 22735 | /* VLD3DUPq32 */ |
| 22736 | 13891, |
| 22737 | /* VLD3DUPq32EvenPseudo */ |
| 22738 | 13898, |
| 22739 | /* VLD3DUPq32OddPseudo */ |
| 22740 | 13904, |
| 22741 | /* VLD3DUPq32OddPseudo_UPD */ |
| 22742 | 13910, |
| 22743 | /* VLD3DUPq32_UPD */ |
| 22744 | 13918, |
| 22745 | /* VLD3DUPq8 */ |
| 22746 | 13927, |
| 22747 | /* VLD3DUPq8EvenPseudo */ |
| 22748 | 13934, |
| 22749 | /* VLD3DUPq8OddPseudo */ |
| 22750 | 13940, |
| 22751 | /* VLD3DUPq8OddPseudo_UPD */ |
| 22752 | 13946, |
| 22753 | /* VLD3DUPq8_UPD */ |
| 22754 | 13954, |
| 22755 | /* VLD3LNd16 */ |
| 22756 | 13963, |
| 22757 | /* VLD3LNd16Pseudo */ |
| 22758 | 13974, |
| 22759 | /* VLD3LNd16Pseudo_UPD */ |
| 22760 | 13981, |
| 22761 | /* VLD3LNd16_UPD */ |
| 22762 | 13990, |
| 22763 | /* VLD3LNd32 */ |
| 22764 | 14003, |
| 22765 | /* VLD3LNd32Pseudo */ |
| 22766 | 14014, |
| 22767 | /* VLD3LNd32Pseudo_UPD */ |
| 22768 | 14021, |
| 22769 | /* VLD3LNd32_UPD */ |
| 22770 | 14030, |
| 22771 | /* VLD3LNd8 */ |
| 22772 | 14043, |
| 22773 | /* VLD3LNd8Pseudo */ |
| 22774 | 14054, |
| 22775 | /* VLD3LNd8Pseudo_UPD */ |
| 22776 | 14061, |
| 22777 | /* VLD3LNd8_UPD */ |
| 22778 | 14070, |
| 22779 | /* VLD3LNq16 */ |
| 22780 | 14083, |
| 22781 | /* VLD3LNq16Pseudo */ |
| 22782 | 14094, |
| 22783 | /* VLD3LNq16Pseudo_UPD */ |
| 22784 | 14101, |
| 22785 | /* VLD3LNq16_UPD */ |
| 22786 | 14110, |
| 22787 | /* VLD3LNq32 */ |
| 22788 | 14123, |
| 22789 | /* VLD3LNq32Pseudo */ |
| 22790 | 14134, |
| 22791 | /* VLD3LNq32Pseudo_UPD */ |
| 22792 | 14141, |
| 22793 | /* VLD3LNq32_UPD */ |
| 22794 | 14150, |
| 22795 | /* VLD3d16 */ |
| 22796 | 14163, |
| 22797 | /* VLD3d16Pseudo */ |
| 22798 | 14170, |
| 22799 | /* VLD3d16Pseudo_UPD */ |
| 22800 | 14175, |
| 22801 | /* VLD3d16_UPD */ |
| 22802 | 14182, |
| 22803 | /* VLD3d32 */ |
| 22804 | 14191, |
| 22805 | /* VLD3d32Pseudo */ |
| 22806 | 14198, |
| 22807 | /* VLD3d32Pseudo_UPD */ |
| 22808 | 14203, |
| 22809 | /* VLD3d32_UPD */ |
| 22810 | 14210, |
| 22811 | /* VLD3d8 */ |
| 22812 | 14219, |
| 22813 | /* VLD3d8Pseudo */ |
| 22814 | 14226, |
| 22815 | /* VLD3d8Pseudo_UPD */ |
| 22816 | 14231, |
| 22817 | /* VLD3d8_UPD */ |
| 22818 | 14238, |
| 22819 | /* VLD3q16 */ |
| 22820 | 14247, |
| 22821 | /* VLD3q16Pseudo_UPD */ |
| 22822 | 14254, |
| 22823 | /* VLD3q16_UPD */ |
| 22824 | 14262, |
| 22825 | /* VLD3q16oddPseudo */ |
| 22826 | 14271, |
| 22827 | /* VLD3q16oddPseudo_UPD */ |
| 22828 | 14277, |
| 22829 | /* VLD3q32 */ |
| 22830 | 14285, |
| 22831 | /* VLD3q32Pseudo_UPD */ |
| 22832 | 14292, |
| 22833 | /* VLD3q32_UPD */ |
| 22834 | 14300, |
| 22835 | /* VLD3q32oddPseudo */ |
| 22836 | 14309, |
| 22837 | /* VLD3q32oddPseudo_UPD */ |
| 22838 | 14315, |
| 22839 | /* VLD3q8 */ |
| 22840 | 14323, |
| 22841 | /* VLD3q8Pseudo_UPD */ |
| 22842 | 14330, |
| 22843 | /* VLD3q8_UPD */ |
| 22844 | 14338, |
| 22845 | /* VLD3q8oddPseudo */ |
| 22846 | 14347, |
| 22847 | /* VLD3q8oddPseudo_UPD */ |
| 22848 | 14353, |
| 22849 | /* VLD4DUPd16 */ |
| 22850 | 14361, |
| 22851 | /* VLD4DUPd16Pseudo */ |
| 22852 | 14369, |
| 22853 | /* VLD4DUPd16Pseudo_UPD */ |
| 22854 | 14374, |
| 22855 | /* VLD4DUPd16_UPD */ |
| 22856 | 14381, |
| 22857 | /* VLD4DUPd32 */ |
| 22858 | 14391, |
| 22859 | /* VLD4DUPd32Pseudo */ |
| 22860 | 14399, |
| 22861 | /* VLD4DUPd32Pseudo_UPD */ |
| 22862 | 14404, |
| 22863 | /* VLD4DUPd32_UPD */ |
| 22864 | 14411, |
| 22865 | /* VLD4DUPd8 */ |
| 22866 | 14421, |
| 22867 | /* VLD4DUPd8Pseudo */ |
| 22868 | 14429, |
| 22869 | /* VLD4DUPd8Pseudo_UPD */ |
| 22870 | 14434, |
| 22871 | /* VLD4DUPd8_UPD */ |
| 22872 | 14441, |
| 22873 | /* VLD4DUPq16 */ |
| 22874 | 14451, |
| 22875 | /* VLD4DUPq16EvenPseudo */ |
| 22876 | 14459, |
| 22877 | /* VLD4DUPq16OddPseudo */ |
| 22878 | 14465, |
| 22879 | /* VLD4DUPq16OddPseudo_UPD */ |
| 22880 | 14471, |
| 22881 | /* VLD4DUPq16_UPD */ |
| 22882 | 14479, |
| 22883 | /* VLD4DUPq32 */ |
| 22884 | 14489, |
| 22885 | /* VLD4DUPq32EvenPseudo */ |
| 22886 | 14497, |
| 22887 | /* VLD4DUPq32OddPseudo */ |
| 22888 | 14503, |
| 22889 | /* VLD4DUPq32OddPseudo_UPD */ |
| 22890 | 14509, |
| 22891 | /* VLD4DUPq32_UPD */ |
| 22892 | 14517, |
| 22893 | /* VLD4DUPq8 */ |
| 22894 | 14527, |
| 22895 | /* VLD4DUPq8EvenPseudo */ |
| 22896 | 14535, |
| 22897 | /* VLD4DUPq8OddPseudo */ |
| 22898 | 14541, |
| 22899 | /* VLD4DUPq8OddPseudo_UPD */ |
| 22900 | 14547, |
| 22901 | /* VLD4DUPq8_UPD */ |
| 22902 | 14555, |
| 22903 | /* VLD4LNd16 */ |
| 22904 | 14565, |
| 22905 | /* VLD4LNd16Pseudo */ |
| 22906 | 14578, |
| 22907 | /* VLD4LNd16Pseudo_UPD */ |
| 22908 | 14585, |
| 22909 | /* VLD4LNd16_UPD */ |
| 22910 | 14594, |
| 22911 | /* VLD4LNd32 */ |
| 22912 | 14609, |
| 22913 | /* VLD4LNd32Pseudo */ |
| 22914 | 14622, |
| 22915 | /* VLD4LNd32Pseudo_UPD */ |
| 22916 | 14629, |
| 22917 | /* VLD4LNd32_UPD */ |
| 22918 | 14638, |
| 22919 | /* VLD4LNd8 */ |
| 22920 | 14653, |
| 22921 | /* VLD4LNd8Pseudo */ |
| 22922 | 14666, |
| 22923 | /* VLD4LNd8Pseudo_UPD */ |
| 22924 | 14673, |
| 22925 | /* VLD4LNd8_UPD */ |
| 22926 | 14682, |
| 22927 | /* VLD4LNq16 */ |
| 22928 | 14697, |
| 22929 | /* VLD4LNq16Pseudo */ |
| 22930 | 14710, |
| 22931 | /* VLD4LNq16Pseudo_UPD */ |
| 22932 | 14717, |
| 22933 | /* VLD4LNq16_UPD */ |
| 22934 | 14726, |
| 22935 | /* VLD4LNq32 */ |
| 22936 | 14741, |
| 22937 | /* VLD4LNq32Pseudo */ |
| 22938 | 14754, |
| 22939 | /* VLD4LNq32Pseudo_UPD */ |
| 22940 | 14761, |
| 22941 | /* VLD4LNq32_UPD */ |
| 22942 | 14770, |
| 22943 | /* VLD4d16 */ |
| 22944 | 14785, |
| 22945 | /* VLD4d16Pseudo */ |
| 22946 | 14793, |
| 22947 | /* VLD4d16Pseudo_UPD */ |
| 22948 | 14798, |
| 22949 | /* VLD4d16_UPD */ |
| 22950 | 14805, |
| 22951 | /* VLD4d32 */ |
| 22952 | 14815, |
| 22953 | /* VLD4d32Pseudo */ |
| 22954 | 14823, |
| 22955 | /* VLD4d32Pseudo_UPD */ |
| 22956 | 14828, |
| 22957 | /* VLD4d32_UPD */ |
| 22958 | 14835, |
| 22959 | /* VLD4d8 */ |
| 22960 | 14845, |
| 22961 | /* VLD4d8Pseudo */ |
| 22962 | 14853, |
| 22963 | /* VLD4d8Pseudo_UPD */ |
| 22964 | 14858, |
| 22965 | /* VLD4d8_UPD */ |
| 22966 | 14865, |
| 22967 | /* VLD4q16 */ |
| 22968 | 14875, |
| 22969 | /* VLD4q16Pseudo_UPD */ |
| 22970 | 14883, |
| 22971 | /* VLD4q16_UPD */ |
| 22972 | 14891, |
| 22973 | /* VLD4q16oddPseudo */ |
| 22974 | 14901, |
| 22975 | /* VLD4q16oddPseudo_UPD */ |
| 22976 | 14907, |
| 22977 | /* VLD4q32 */ |
| 22978 | 14915, |
| 22979 | /* VLD4q32Pseudo_UPD */ |
| 22980 | 14923, |
| 22981 | /* VLD4q32_UPD */ |
| 22982 | 14931, |
| 22983 | /* VLD4q32oddPseudo */ |
| 22984 | 14941, |
| 22985 | /* VLD4q32oddPseudo_UPD */ |
| 22986 | 14947, |
| 22987 | /* VLD4q8 */ |
| 22988 | 14955, |
| 22989 | /* VLD4q8Pseudo_UPD */ |
| 22990 | 14963, |
| 22991 | /* VLD4q8_UPD */ |
| 22992 | 14971, |
| 22993 | /* VLD4q8oddPseudo */ |
| 22994 | 14981, |
| 22995 | /* VLD4q8oddPseudo_UPD */ |
| 22996 | 14987, |
| 22997 | /* VLDMDDB_UPD */ |
| 22998 | 14995, |
| 22999 | /* VLDMDIA */ |
| 23000 | 15000, |
| 23001 | /* VLDMDIA_UPD */ |
| 23002 | 15004, |
| 23003 | /* VLDMQIA */ |
| 23004 | 15009, |
| 23005 | /* VLDMSDB_UPD */ |
| 23006 | 15013, |
| 23007 | /* VLDMSIA */ |
| 23008 | 15018, |
| 23009 | /* VLDMSIA_UPD */ |
| 23010 | 15022, |
| 23011 | /* VLDRD */ |
| 23012 | 15027, |
| 23013 | /* VLDRH */ |
| 23014 | 15032, |
| 23015 | /* VLDRS */ |
| 23016 | 15037, |
| 23017 | /* VLDR_FPCXTNS_off */ |
| 23018 | 15042, |
| 23019 | /* VLDR_FPCXTNS_post */ |
| 23020 | 15046, |
| 23021 | /* VLDR_FPCXTNS_pre */ |
| 23022 | 15051, |
| 23023 | /* VLDR_FPCXTS_off */ |
| 23024 | 15056, |
| 23025 | /* VLDR_FPCXTS_post */ |
| 23026 | 15060, |
| 23027 | /* VLDR_FPCXTS_pre */ |
| 23028 | 15065, |
| 23029 | /* VLDR_FPSCR_NZCVQC_off */ |
| 23030 | 15070, |
| 23031 | /* VLDR_FPSCR_NZCVQC_post */ |
| 23032 | 15074, |
| 23033 | /* VLDR_FPSCR_NZCVQC_pre */ |
| 23034 | 15079, |
| 23035 | /* VLDR_FPSCR_off */ |
| 23036 | 15084, |
| 23037 | /* VLDR_FPSCR_post */ |
| 23038 | 15088, |
| 23039 | /* VLDR_FPSCR_pre */ |
| 23040 | 15093, |
| 23041 | /* VLDR_P0_off */ |
| 23042 | 15098, |
| 23043 | /* VLDR_P0_post */ |
| 23044 | 15103, |
| 23045 | /* VLDR_P0_pre */ |
| 23046 | 15109, |
| 23047 | /* VLDR_VPR_off */ |
| 23048 | 15115, |
| 23049 | /* VLDR_VPR_post */ |
| 23050 | 15119, |
| 23051 | /* VLDR_VPR_pre */ |
| 23052 | 15124, |
| 23053 | /* VLLDM */ |
| 23054 | 15129, |
| 23055 | /* VLLDM_T2 */ |
| 23056 | 15133, |
| 23057 | /* VLSTM */ |
| 23058 | 15137, |
| 23059 | /* VLSTM_T2 */ |
| 23060 | 15141, |
| 23061 | /* VMAXfd */ |
| 23062 | 15145, |
| 23063 | /* VMAXfq */ |
| 23064 | 15150, |
| 23065 | /* VMAXhd */ |
| 23066 | 15155, |
| 23067 | /* VMAXhq */ |
| 23068 | 15160, |
| 23069 | /* VMAXsv16i8 */ |
| 23070 | 15165, |
| 23071 | /* VMAXsv2i32 */ |
| 23072 | 15170, |
| 23073 | /* VMAXsv4i16 */ |
| 23074 | 15175, |
| 23075 | /* VMAXsv4i32 */ |
| 23076 | 15180, |
| 23077 | /* VMAXsv8i16 */ |
| 23078 | 15185, |
| 23079 | /* VMAXsv8i8 */ |
| 23080 | 15190, |
| 23081 | /* VMAXuv16i8 */ |
| 23082 | 15195, |
| 23083 | /* VMAXuv2i32 */ |
| 23084 | 15200, |
| 23085 | /* VMAXuv4i16 */ |
| 23086 | 15205, |
| 23087 | /* VMAXuv4i32 */ |
| 23088 | 15210, |
| 23089 | /* VMAXuv8i16 */ |
| 23090 | 15215, |
| 23091 | /* VMAXuv8i8 */ |
| 23092 | 15220, |
| 23093 | /* VMINfd */ |
| 23094 | 15225, |
| 23095 | /* VMINfq */ |
| 23096 | 15230, |
| 23097 | /* VMINhd */ |
| 23098 | 15235, |
| 23099 | /* VMINhq */ |
| 23100 | 15240, |
| 23101 | /* VMINsv16i8 */ |
| 23102 | 15245, |
| 23103 | /* VMINsv2i32 */ |
| 23104 | 15250, |
| 23105 | /* VMINsv4i16 */ |
| 23106 | 15255, |
| 23107 | /* VMINsv4i32 */ |
| 23108 | 15260, |
| 23109 | /* VMINsv8i16 */ |
| 23110 | 15265, |
| 23111 | /* VMINsv8i8 */ |
| 23112 | 15270, |
| 23113 | /* VMINuv16i8 */ |
| 23114 | 15275, |
| 23115 | /* VMINuv2i32 */ |
| 23116 | 15280, |
| 23117 | /* VMINuv4i16 */ |
| 23118 | 15285, |
| 23119 | /* VMINuv4i32 */ |
| 23120 | 15290, |
| 23121 | /* VMINuv8i16 */ |
| 23122 | 15295, |
| 23123 | /* VMINuv8i8 */ |
| 23124 | 15300, |
| 23125 | /* VMLAD */ |
| 23126 | 15305, |
| 23127 | /* VMLAH */ |
| 23128 | 15311, |
| 23129 | /* VMLALslsv2i32 */ |
| 23130 | 15317, |
| 23131 | /* VMLALslsv4i16 */ |
| 23132 | 15324, |
| 23133 | /* VMLALsluv2i32 */ |
| 23134 | 15331, |
| 23135 | /* VMLALsluv4i16 */ |
| 23136 | 15338, |
| 23137 | /* VMLALsv2i64 */ |
| 23138 | 15345, |
| 23139 | /* VMLALsv4i32 */ |
| 23140 | 15351, |
| 23141 | /* VMLALsv8i16 */ |
| 23142 | 15357, |
| 23143 | /* VMLALuv2i64 */ |
| 23144 | 15363, |
| 23145 | /* VMLALuv4i32 */ |
| 23146 | 15369, |
| 23147 | /* VMLALuv8i16 */ |
| 23148 | 15375, |
| 23149 | /* VMLAS */ |
| 23150 | 15381, |
| 23151 | /* VMLAfd */ |
| 23152 | 15387, |
| 23153 | /* VMLAfq */ |
| 23154 | 15393, |
| 23155 | /* VMLAhd */ |
| 23156 | 15399, |
| 23157 | /* VMLAhq */ |
| 23158 | 15405, |
| 23159 | /* VMLAslfd */ |
| 23160 | 15411, |
| 23161 | /* VMLAslfq */ |
| 23162 | 15418, |
| 23163 | /* VMLAslhd */ |
| 23164 | 15425, |
| 23165 | /* VMLAslhq */ |
| 23166 | 15432, |
| 23167 | /* VMLAslv2i32 */ |
| 23168 | 15439, |
| 23169 | /* VMLAslv4i16 */ |
| 23170 | 15446, |
| 23171 | /* VMLAslv4i32 */ |
| 23172 | 15453, |
| 23173 | /* VMLAslv8i16 */ |
| 23174 | 15460, |
| 23175 | /* VMLAv16i8 */ |
| 23176 | 15467, |
| 23177 | /* VMLAv2i32 */ |
| 23178 | 15473, |
| 23179 | /* VMLAv4i16 */ |
| 23180 | 15479, |
| 23181 | /* VMLAv4i32 */ |
| 23182 | 15485, |
| 23183 | /* VMLAv8i16 */ |
| 23184 | 15491, |
| 23185 | /* VMLAv8i8 */ |
| 23186 | 15497, |
| 23187 | /* VMLSD */ |
| 23188 | 15503, |
| 23189 | /* VMLSH */ |
| 23190 | 15509, |
| 23191 | /* VMLSLslsv2i32 */ |
| 23192 | 15515, |
| 23193 | /* VMLSLslsv4i16 */ |
| 23194 | 15522, |
| 23195 | /* VMLSLsluv2i32 */ |
| 23196 | 15529, |
| 23197 | /* VMLSLsluv4i16 */ |
| 23198 | 15536, |
| 23199 | /* VMLSLsv2i64 */ |
| 23200 | 15543, |
| 23201 | /* VMLSLsv4i32 */ |
| 23202 | 15549, |
| 23203 | /* VMLSLsv8i16 */ |
| 23204 | 15555, |
| 23205 | /* VMLSLuv2i64 */ |
| 23206 | 15561, |
| 23207 | /* VMLSLuv4i32 */ |
| 23208 | 15567, |
| 23209 | /* VMLSLuv8i16 */ |
| 23210 | 15573, |
| 23211 | /* VMLSS */ |
| 23212 | 15579, |
| 23213 | /* VMLSfd */ |
| 23214 | 15585, |
| 23215 | /* VMLSfq */ |
| 23216 | 15591, |
| 23217 | /* VMLShd */ |
| 23218 | 15597, |
| 23219 | /* VMLShq */ |
| 23220 | 15603, |
| 23221 | /* VMLSslfd */ |
| 23222 | 15609, |
| 23223 | /* VMLSslfq */ |
| 23224 | 15616, |
| 23225 | /* VMLSslhd */ |
| 23226 | 15623, |
| 23227 | /* VMLSslhq */ |
| 23228 | 15630, |
| 23229 | /* VMLSslv2i32 */ |
| 23230 | 15637, |
| 23231 | /* VMLSslv4i16 */ |
| 23232 | 15644, |
| 23233 | /* VMLSslv4i32 */ |
| 23234 | 15651, |
| 23235 | /* VMLSslv8i16 */ |
| 23236 | 15658, |
| 23237 | /* VMLSv16i8 */ |
| 23238 | 15665, |
| 23239 | /* VMLSv2i32 */ |
| 23240 | 15671, |
| 23241 | /* VMLSv4i16 */ |
| 23242 | 15677, |
| 23243 | /* VMLSv4i32 */ |
| 23244 | 15683, |
| 23245 | /* VMLSv8i16 */ |
| 23246 | 15689, |
| 23247 | /* VMLSv8i8 */ |
| 23248 | 15695, |
| 23249 | /* VMMLA */ |
| 23250 | 15701, |
| 23251 | /* VMOVD */ |
| 23252 | 15705, |
| 23253 | /* VMOVDRR */ |
| 23254 | 15709, |
| 23255 | /* VMOVH */ |
| 23256 | 15714, |
| 23257 | /* VMOVHR */ |
| 23258 | 15716, |
| 23259 | /* VMOVLsv2i64 */ |
| 23260 | 15720, |
| 23261 | /* VMOVLsv4i32 */ |
| 23262 | 15724, |
| 23263 | /* VMOVLsv8i16 */ |
| 23264 | 15728, |
| 23265 | /* VMOVLuv2i64 */ |
| 23266 | 15732, |
| 23267 | /* VMOVLuv4i32 */ |
| 23268 | 15736, |
| 23269 | /* VMOVLuv8i16 */ |
| 23270 | 15740, |
| 23271 | /* VMOVNv2i32 */ |
| 23272 | 15744, |
| 23273 | /* VMOVNv4i16 */ |
| 23274 | 15748, |
| 23275 | /* VMOVNv8i8 */ |
| 23276 | 15752, |
| 23277 | /* VMOVRH */ |
| 23278 | 15756, |
| 23279 | /* VMOVRRD */ |
| 23280 | 15760, |
| 23281 | /* VMOVRRS */ |
| 23282 | 15765, |
| 23283 | /* VMOVRS */ |
| 23284 | 15771, |
| 23285 | /* VMOVS */ |
| 23286 | 15775, |
| 23287 | /* VMOVSR */ |
| 23288 | 15779, |
| 23289 | /* VMOVSRR */ |
| 23290 | 15783, |
| 23291 | /* VMOVv16i8 */ |
| 23292 | 15789, |
| 23293 | /* VMOVv1i64 */ |
| 23294 | 15793, |
| 23295 | /* VMOVv2f32 */ |
| 23296 | 15797, |
| 23297 | /* VMOVv2i32 */ |
| 23298 | 15801, |
| 23299 | /* VMOVv2i64 */ |
| 23300 | 15805, |
| 23301 | /* VMOVv4f32 */ |
| 23302 | 15809, |
| 23303 | /* VMOVv4i16 */ |
| 23304 | 15813, |
| 23305 | /* VMOVv4i32 */ |
| 23306 | 15817, |
| 23307 | /* VMOVv8i16 */ |
| 23308 | 15821, |
| 23309 | /* VMOVv8i8 */ |
| 23310 | 15825, |
| 23311 | /* VMRS */ |
| 23312 | 15829, |
| 23313 | /* VMRS_FPCXTNS */ |
| 23314 | 15832, |
| 23315 | /* VMRS_FPCXTS */ |
| 23316 | 15835, |
| 23317 | /* VMRS_FPEXC */ |
| 23318 | 15838, |
| 23319 | /* VMRS_FPINST */ |
| 23320 | 15841, |
| 23321 | /* VMRS_FPINST2 */ |
| 23322 | 15844, |
| 23323 | /* VMRS_FPSCR_NZCVQC */ |
| 23324 | 15847, |
| 23325 | /* VMRS_FPSID */ |
| 23326 | 15851, |
| 23327 | /* VMRS_MVFR0 */ |
| 23328 | 15854, |
| 23329 | /* VMRS_MVFR1 */ |
| 23330 | 15857, |
| 23331 | /* VMRS_MVFR2 */ |
| 23332 | 15860, |
| 23333 | /* VMRS_P0 */ |
| 23334 | 15863, |
| 23335 | /* VMRS_VPR */ |
| 23336 | 15867, |
| 23337 | /* VMSR */ |
| 23338 | 15870, |
| 23339 | /* VMSR_FPCXTNS */ |
| 23340 | 15873, |
| 23341 | /* VMSR_FPCXTS */ |
| 23342 | 15876, |
| 23343 | /* VMSR_FPEXC */ |
| 23344 | 15879, |
| 23345 | /* VMSR_FPINST */ |
| 23346 | 15882, |
| 23347 | /* VMSR_FPINST2 */ |
| 23348 | 15885, |
| 23349 | /* VMSR_FPSCR_NZCVQC */ |
| 23350 | 15888, |
| 23351 | /* VMSR_FPSID */ |
| 23352 | 15892, |
| 23353 | /* VMSR_P0 */ |
| 23354 | 15895, |
| 23355 | /* VMSR_VPR */ |
| 23356 | 15899, |
| 23357 | /* VMULD */ |
| 23358 | 15902, |
| 23359 | /* VMULH */ |
| 23360 | 15907, |
| 23361 | /* VMULLp64 */ |
| 23362 | 15912, |
| 23363 | /* VMULLp8 */ |
| 23364 | 15915, |
| 23365 | /* VMULLslsv2i32 */ |
| 23366 | 15920, |
| 23367 | /* VMULLslsv4i16 */ |
| 23368 | 15926, |
| 23369 | /* VMULLsluv2i32 */ |
| 23370 | 15932, |
| 23371 | /* VMULLsluv4i16 */ |
| 23372 | 15938, |
| 23373 | /* VMULLsv2i64 */ |
| 23374 | 15944, |
| 23375 | /* VMULLsv4i32 */ |
| 23376 | 15949, |
| 23377 | /* VMULLsv8i16 */ |
| 23378 | 15954, |
| 23379 | /* VMULLuv2i64 */ |
| 23380 | 15959, |
| 23381 | /* VMULLuv4i32 */ |
| 23382 | 15964, |
| 23383 | /* VMULLuv8i16 */ |
| 23384 | 15969, |
| 23385 | /* VMULS */ |
| 23386 | 15974, |
| 23387 | /* VMULfd */ |
| 23388 | 15979, |
| 23389 | /* VMULfq */ |
| 23390 | 15984, |
| 23391 | /* VMULhd */ |
| 23392 | 15989, |
| 23393 | /* VMULhq */ |
| 23394 | 15994, |
| 23395 | /* VMULpd */ |
| 23396 | 15999, |
| 23397 | /* VMULpq */ |
| 23398 | 16004, |
| 23399 | /* VMULslfd */ |
| 23400 | 16009, |
| 23401 | /* VMULslfq */ |
| 23402 | 16015, |
| 23403 | /* VMULslhd */ |
| 23404 | 16021, |
| 23405 | /* VMULslhq */ |
| 23406 | 16027, |
| 23407 | /* VMULslv2i32 */ |
| 23408 | 16033, |
| 23409 | /* VMULslv4i16 */ |
| 23410 | 16039, |
| 23411 | /* VMULslv4i32 */ |
| 23412 | 16045, |
| 23413 | /* VMULslv8i16 */ |
| 23414 | 16051, |
| 23415 | /* VMULv16i8 */ |
| 23416 | 16057, |
| 23417 | /* VMULv2i32 */ |
| 23418 | 16062, |
| 23419 | /* VMULv4i16 */ |
| 23420 | 16067, |
| 23421 | /* VMULv4i32 */ |
| 23422 | 16072, |
| 23423 | /* VMULv8i16 */ |
| 23424 | 16077, |
| 23425 | /* VMULv8i8 */ |
| 23426 | 16082, |
| 23427 | /* VMVNd */ |
| 23428 | 16087, |
| 23429 | /* VMVNq */ |
| 23430 | 16091, |
| 23431 | /* VMVNv2i32 */ |
| 23432 | 16095, |
| 23433 | /* VMVNv4i16 */ |
| 23434 | 16099, |
| 23435 | /* VMVNv4i32 */ |
| 23436 | 16103, |
| 23437 | /* VMVNv8i16 */ |
| 23438 | 16107, |
| 23439 | /* VNEGD */ |
| 23440 | 16111, |
| 23441 | /* VNEGH */ |
| 23442 | 16115, |
| 23443 | /* VNEGS */ |
| 23444 | 16119, |
| 23445 | /* VNEGf32q */ |
| 23446 | 16123, |
| 23447 | /* VNEGfd */ |
| 23448 | 16127, |
| 23449 | /* VNEGhd */ |
| 23450 | 16131, |
| 23451 | /* VNEGhq */ |
| 23452 | 16135, |
| 23453 | /* VNEGs16d */ |
| 23454 | 16139, |
| 23455 | /* VNEGs16q */ |
| 23456 | 16143, |
| 23457 | /* VNEGs32d */ |
| 23458 | 16147, |
| 23459 | /* VNEGs32q */ |
| 23460 | 16151, |
| 23461 | /* VNEGs8d */ |
| 23462 | 16155, |
| 23463 | /* VNEGs8q */ |
| 23464 | 16159, |
| 23465 | /* VNMLAD */ |
| 23466 | 16163, |
| 23467 | /* VNMLAH */ |
| 23468 | 16169, |
| 23469 | /* VNMLAS */ |
| 23470 | 16175, |
| 23471 | /* VNMLSD */ |
| 23472 | 16181, |
| 23473 | /* VNMLSH */ |
| 23474 | 16187, |
| 23475 | /* VNMLSS */ |
| 23476 | 16193, |
| 23477 | /* VNMULD */ |
| 23478 | 16199, |
| 23479 | /* VNMULH */ |
| 23480 | 16204, |
| 23481 | /* VNMULS */ |
| 23482 | 16209, |
| 23483 | /* VORNd */ |
| 23484 | 16214, |
| 23485 | /* VORNq */ |
| 23486 | 16219, |
| 23487 | /* VORRd */ |
| 23488 | 16224, |
| 23489 | /* VORRiv2i32 */ |
| 23490 | 16229, |
| 23491 | /* VORRiv4i16 */ |
| 23492 | 16234, |
| 23493 | /* VORRiv4i32 */ |
| 23494 | 16239, |
| 23495 | /* VORRiv8i16 */ |
| 23496 | 16244, |
| 23497 | /* VORRq */ |
| 23498 | 16249, |
| 23499 | /* VPADALsv16i8 */ |
| 23500 | 16254, |
| 23501 | /* VPADALsv2i32 */ |
| 23502 | 16259, |
| 23503 | /* VPADALsv4i16 */ |
| 23504 | 16264, |
| 23505 | /* VPADALsv4i32 */ |
| 23506 | 16269, |
| 23507 | /* VPADALsv8i16 */ |
| 23508 | 16274, |
| 23509 | /* VPADALsv8i8 */ |
| 23510 | 16279, |
| 23511 | /* VPADALuv16i8 */ |
| 23512 | 16284, |
| 23513 | /* VPADALuv2i32 */ |
| 23514 | 16289, |
| 23515 | /* VPADALuv4i16 */ |
| 23516 | 16294, |
| 23517 | /* VPADALuv4i32 */ |
| 23518 | 16299, |
| 23519 | /* VPADALuv8i16 */ |
| 23520 | 16304, |
| 23521 | /* VPADALuv8i8 */ |
| 23522 | 16309, |
| 23523 | /* VPADDLsv16i8 */ |
| 23524 | 16314, |
| 23525 | /* VPADDLsv2i32 */ |
| 23526 | 16318, |
| 23527 | /* VPADDLsv4i16 */ |
| 23528 | 16322, |
| 23529 | /* VPADDLsv4i32 */ |
| 23530 | 16326, |
| 23531 | /* VPADDLsv8i16 */ |
| 23532 | 16330, |
| 23533 | /* VPADDLsv8i8 */ |
| 23534 | 16334, |
| 23535 | /* VPADDLuv16i8 */ |
| 23536 | 16338, |
| 23537 | /* VPADDLuv2i32 */ |
| 23538 | 16342, |
| 23539 | /* VPADDLuv4i16 */ |
| 23540 | 16346, |
| 23541 | /* VPADDLuv4i32 */ |
| 23542 | 16350, |
| 23543 | /* VPADDLuv8i16 */ |
| 23544 | 16354, |
| 23545 | /* VPADDLuv8i8 */ |
| 23546 | 16358, |
| 23547 | /* VPADDf */ |
| 23548 | 16362, |
| 23549 | /* VPADDh */ |
| 23550 | 16367, |
| 23551 | /* VPADDi16 */ |
| 23552 | 16372, |
| 23553 | /* VPADDi32 */ |
| 23554 | 16377, |
| 23555 | /* VPADDi8 */ |
| 23556 | 16382, |
| 23557 | /* VPMAXf */ |
| 23558 | 16387, |
| 23559 | /* VPMAXh */ |
| 23560 | 16392, |
| 23561 | /* VPMAXs16 */ |
| 23562 | 16397, |
| 23563 | /* VPMAXs32 */ |
| 23564 | 16402, |
| 23565 | /* VPMAXs8 */ |
| 23566 | 16407, |
| 23567 | /* VPMAXu16 */ |
| 23568 | 16412, |
| 23569 | /* VPMAXu32 */ |
| 23570 | 16417, |
| 23571 | /* VPMAXu8 */ |
| 23572 | 16422, |
| 23573 | /* VPMINf */ |
| 23574 | 16427, |
| 23575 | /* VPMINh */ |
| 23576 | 16432, |
| 23577 | /* VPMINs16 */ |
| 23578 | 16437, |
| 23579 | /* VPMINs32 */ |
| 23580 | 16442, |
| 23581 | /* VPMINs8 */ |
| 23582 | 16447, |
| 23583 | /* VPMINu16 */ |
| 23584 | 16452, |
| 23585 | /* VPMINu32 */ |
| 23586 | 16457, |
| 23587 | /* VPMINu8 */ |
| 23588 | 16462, |
| 23589 | /* VQABSv16i8 */ |
| 23590 | 16467, |
| 23591 | /* VQABSv2i32 */ |
| 23592 | 16471, |
| 23593 | /* VQABSv4i16 */ |
| 23594 | 16475, |
| 23595 | /* VQABSv4i32 */ |
| 23596 | 16479, |
| 23597 | /* VQABSv8i16 */ |
| 23598 | 16483, |
| 23599 | /* VQABSv8i8 */ |
| 23600 | 16487, |
| 23601 | /* VQADDsv16i8 */ |
| 23602 | 16491, |
| 23603 | /* VQADDsv1i64 */ |
| 23604 | 16496, |
| 23605 | /* VQADDsv2i32 */ |
| 23606 | 16501, |
| 23607 | /* VQADDsv2i64 */ |
| 23608 | 16506, |
| 23609 | /* VQADDsv4i16 */ |
| 23610 | 16511, |
| 23611 | /* VQADDsv4i32 */ |
| 23612 | 16516, |
| 23613 | /* VQADDsv8i16 */ |
| 23614 | 16521, |
| 23615 | /* VQADDsv8i8 */ |
| 23616 | 16526, |
| 23617 | /* VQADDuv16i8 */ |
| 23618 | 16531, |
| 23619 | /* VQADDuv1i64 */ |
| 23620 | 16536, |
| 23621 | /* VQADDuv2i32 */ |
| 23622 | 16541, |
| 23623 | /* VQADDuv2i64 */ |
| 23624 | 16546, |
| 23625 | /* VQADDuv4i16 */ |
| 23626 | 16551, |
| 23627 | /* VQADDuv4i32 */ |
| 23628 | 16556, |
| 23629 | /* VQADDuv8i16 */ |
| 23630 | 16561, |
| 23631 | /* VQADDuv8i8 */ |
| 23632 | 16566, |
| 23633 | /* VQDMLALslv2i32 */ |
| 23634 | 16571, |
| 23635 | /* VQDMLALslv4i16 */ |
| 23636 | 16578, |
| 23637 | /* VQDMLALv2i64 */ |
| 23638 | 16585, |
| 23639 | /* VQDMLALv4i32 */ |
| 23640 | 16591, |
| 23641 | /* VQDMLSLslv2i32 */ |
| 23642 | 16597, |
| 23643 | /* VQDMLSLslv4i16 */ |
| 23644 | 16604, |
| 23645 | /* VQDMLSLv2i64 */ |
| 23646 | 16611, |
| 23647 | /* VQDMLSLv4i32 */ |
| 23648 | 16617, |
| 23649 | /* VQDMULHslv2i32 */ |
| 23650 | 16623, |
| 23651 | /* VQDMULHslv4i16 */ |
| 23652 | 16629, |
| 23653 | /* VQDMULHslv4i32 */ |
| 23654 | 16635, |
| 23655 | /* VQDMULHslv8i16 */ |
| 23656 | 16641, |
| 23657 | /* VQDMULHv2i32 */ |
| 23658 | 16647, |
| 23659 | /* VQDMULHv4i16 */ |
| 23660 | 16652, |
| 23661 | /* VQDMULHv4i32 */ |
| 23662 | 16657, |
| 23663 | /* VQDMULHv8i16 */ |
| 23664 | 16662, |
| 23665 | /* VQDMULLslv2i32 */ |
| 23666 | 16667, |
| 23667 | /* VQDMULLslv4i16 */ |
| 23668 | 16673, |
| 23669 | /* VQDMULLv2i64 */ |
| 23670 | 16679, |
| 23671 | /* VQDMULLv4i32 */ |
| 23672 | 16684, |
| 23673 | /* VQMOVNsuv2i32 */ |
| 23674 | 16689, |
| 23675 | /* VQMOVNsuv4i16 */ |
| 23676 | 16693, |
| 23677 | /* VQMOVNsuv8i8 */ |
| 23678 | 16697, |
| 23679 | /* VQMOVNsv2i32 */ |
| 23680 | 16701, |
| 23681 | /* VQMOVNsv4i16 */ |
| 23682 | 16705, |
| 23683 | /* VQMOVNsv8i8 */ |
| 23684 | 16709, |
| 23685 | /* VQMOVNuv2i32 */ |
| 23686 | 16713, |
| 23687 | /* VQMOVNuv4i16 */ |
| 23688 | 16717, |
| 23689 | /* VQMOVNuv8i8 */ |
| 23690 | 16721, |
| 23691 | /* VQNEGv16i8 */ |
| 23692 | 16725, |
| 23693 | /* VQNEGv2i32 */ |
| 23694 | 16729, |
| 23695 | /* VQNEGv4i16 */ |
| 23696 | 16733, |
| 23697 | /* VQNEGv4i32 */ |
| 23698 | 16737, |
| 23699 | /* VQNEGv8i16 */ |
| 23700 | 16741, |
| 23701 | /* VQNEGv8i8 */ |
| 23702 | 16745, |
| 23703 | /* VQRDMLAHslv2i32 */ |
| 23704 | 16749, |
| 23705 | /* VQRDMLAHslv4i16 */ |
| 23706 | 16756, |
| 23707 | /* VQRDMLAHslv4i32 */ |
| 23708 | 16763, |
| 23709 | /* VQRDMLAHslv8i16 */ |
| 23710 | 16770, |
| 23711 | /* VQRDMLAHv2i32 */ |
| 23712 | 16777, |
| 23713 | /* VQRDMLAHv4i16 */ |
| 23714 | 16783, |
| 23715 | /* VQRDMLAHv4i32 */ |
| 23716 | 16789, |
| 23717 | /* VQRDMLAHv8i16 */ |
| 23718 | 16795, |
| 23719 | /* VQRDMLSHslv2i32 */ |
| 23720 | 16801, |
| 23721 | /* VQRDMLSHslv4i16 */ |
| 23722 | 16808, |
| 23723 | /* VQRDMLSHslv4i32 */ |
| 23724 | 16815, |
| 23725 | /* VQRDMLSHslv8i16 */ |
| 23726 | 16822, |
| 23727 | /* VQRDMLSHv2i32 */ |
| 23728 | 16829, |
| 23729 | /* VQRDMLSHv4i16 */ |
| 23730 | 16835, |
| 23731 | /* VQRDMLSHv4i32 */ |
| 23732 | 16841, |
| 23733 | /* VQRDMLSHv8i16 */ |
| 23734 | 16847, |
| 23735 | /* VQRDMULHslv2i32 */ |
| 23736 | 16853, |
| 23737 | /* VQRDMULHslv4i16 */ |
| 23738 | 16859, |
| 23739 | /* VQRDMULHslv4i32 */ |
| 23740 | 16865, |
| 23741 | /* VQRDMULHslv8i16 */ |
| 23742 | 16871, |
| 23743 | /* VQRDMULHv2i32 */ |
| 23744 | 16877, |
| 23745 | /* VQRDMULHv4i16 */ |
| 23746 | 16882, |
| 23747 | /* VQRDMULHv4i32 */ |
| 23748 | 16887, |
| 23749 | /* VQRDMULHv8i16 */ |
| 23750 | 16892, |
| 23751 | /* VQRSHLsv16i8 */ |
| 23752 | 16897, |
| 23753 | /* VQRSHLsv1i64 */ |
| 23754 | 16902, |
| 23755 | /* VQRSHLsv2i32 */ |
| 23756 | 16907, |
| 23757 | /* VQRSHLsv2i64 */ |
| 23758 | 16912, |
| 23759 | /* VQRSHLsv4i16 */ |
| 23760 | 16917, |
| 23761 | /* VQRSHLsv4i32 */ |
| 23762 | 16922, |
| 23763 | /* VQRSHLsv8i16 */ |
| 23764 | 16927, |
| 23765 | /* VQRSHLsv8i8 */ |
| 23766 | 16932, |
| 23767 | /* VQRSHLuv16i8 */ |
| 23768 | 16937, |
| 23769 | /* VQRSHLuv1i64 */ |
| 23770 | 16942, |
| 23771 | /* VQRSHLuv2i32 */ |
| 23772 | 16947, |
| 23773 | /* VQRSHLuv2i64 */ |
| 23774 | 16952, |
| 23775 | /* VQRSHLuv4i16 */ |
| 23776 | 16957, |
| 23777 | /* VQRSHLuv4i32 */ |
| 23778 | 16962, |
| 23779 | /* VQRSHLuv8i16 */ |
| 23780 | 16967, |
| 23781 | /* VQRSHLuv8i8 */ |
| 23782 | 16972, |
| 23783 | /* VQRSHRNsv2i32 */ |
| 23784 | 16977, |
| 23785 | /* VQRSHRNsv4i16 */ |
| 23786 | 16982, |
| 23787 | /* VQRSHRNsv8i8 */ |
| 23788 | 16987, |
| 23789 | /* VQRSHRNuv2i32 */ |
| 23790 | 16992, |
| 23791 | /* VQRSHRNuv4i16 */ |
| 23792 | 16997, |
| 23793 | /* VQRSHRNuv8i8 */ |
| 23794 | 17002, |
| 23795 | /* VQRSHRUNv2i32 */ |
| 23796 | 17007, |
| 23797 | /* VQRSHRUNv4i16 */ |
| 23798 | 17012, |
| 23799 | /* VQRSHRUNv8i8 */ |
| 23800 | 17017, |
| 23801 | /* VQSHLsiv16i8 */ |
| 23802 | 17022, |
| 23803 | /* VQSHLsiv1i64 */ |
| 23804 | 17027, |
| 23805 | /* VQSHLsiv2i32 */ |
| 23806 | 17032, |
| 23807 | /* VQSHLsiv2i64 */ |
| 23808 | 17037, |
| 23809 | /* VQSHLsiv4i16 */ |
| 23810 | 17042, |
| 23811 | /* VQSHLsiv4i32 */ |
| 23812 | 17047, |
| 23813 | /* VQSHLsiv8i16 */ |
| 23814 | 17052, |
| 23815 | /* VQSHLsiv8i8 */ |
| 23816 | 17057, |
| 23817 | /* VQSHLsuv16i8 */ |
| 23818 | 17062, |
| 23819 | /* VQSHLsuv1i64 */ |
| 23820 | 17067, |
| 23821 | /* VQSHLsuv2i32 */ |
| 23822 | 17072, |
| 23823 | /* VQSHLsuv2i64 */ |
| 23824 | 17077, |
| 23825 | /* VQSHLsuv4i16 */ |
| 23826 | 17082, |
| 23827 | /* VQSHLsuv4i32 */ |
| 23828 | 17087, |
| 23829 | /* VQSHLsuv8i16 */ |
| 23830 | 17092, |
| 23831 | /* VQSHLsuv8i8 */ |
| 23832 | 17097, |
| 23833 | /* VQSHLsv16i8 */ |
| 23834 | 17102, |
| 23835 | /* VQSHLsv1i64 */ |
| 23836 | 17107, |
| 23837 | /* VQSHLsv2i32 */ |
| 23838 | 17112, |
| 23839 | /* VQSHLsv2i64 */ |
| 23840 | 17117, |
| 23841 | /* VQSHLsv4i16 */ |
| 23842 | 17122, |
| 23843 | /* VQSHLsv4i32 */ |
| 23844 | 17127, |
| 23845 | /* VQSHLsv8i16 */ |
| 23846 | 17132, |
| 23847 | /* VQSHLsv8i8 */ |
| 23848 | 17137, |
| 23849 | /* VQSHLuiv16i8 */ |
| 23850 | 17142, |
| 23851 | /* VQSHLuiv1i64 */ |
| 23852 | 17147, |
| 23853 | /* VQSHLuiv2i32 */ |
| 23854 | 17152, |
| 23855 | /* VQSHLuiv2i64 */ |
| 23856 | 17157, |
| 23857 | /* VQSHLuiv4i16 */ |
| 23858 | 17162, |
| 23859 | /* VQSHLuiv4i32 */ |
| 23860 | 17167, |
| 23861 | /* VQSHLuiv8i16 */ |
| 23862 | 17172, |
| 23863 | /* VQSHLuiv8i8 */ |
| 23864 | 17177, |
| 23865 | /* VQSHLuv16i8 */ |
| 23866 | 17182, |
| 23867 | /* VQSHLuv1i64 */ |
| 23868 | 17187, |
| 23869 | /* VQSHLuv2i32 */ |
| 23870 | 17192, |
| 23871 | /* VQSHLuv2i64 */ |
| 23872 | 17197, |
| 23873 | /* VQSHLuv4i16 */ |
| 23874 | 17202, |
| 23875 | /* VQSHLuv4i32 */ |
| 23876 | 17207, |
| 23877 | /* VQSHLuv8i16 */ |
| 23878 | 17212, |
| 23879 | /* VQSHLuv8i8 */ |
| 23880 | 17217, |
| 23881 | /* VQSHRNsv2i32 */ |
| 23882 | 17222, |
| 23883 | /* VQSHRNsv4i16 */ |
| 23884 | 17227, |
| 23885 | /* VQSHRNsv8i8 */ |
| 23886 | 17232, |
| 23887 | /* VQSHRNuv2i32 */ |
| 23888 | 17237, |
| 23889 | /* VQSHRNuv4i16 */ |
| 23890 | 17242, |
| 23891 | /* VQSHRNuv8i8 */ |
| 23892 | 17247, |
| 23893 | /* VQSHRUNv2i32 */ |
| 23894 | 17252, |
| 23895 | /* VQSHRUNv4i16 */ |
| 23896 | 17257, |
| 23897 | /* VQSHRUNv8i8 */ |
| 23898 | 17262, |
| 23899 | /* VQSUBsv16i8 */ |
| 23900 | 17267, |
| 23901 | /* VQSUBsv1i64 */ |
| 23902 | 17272, |
| 23903 | /* VQSUBsv2i32 */ |
| 23904 | 17277, |
| 23905 | /* VQSUBsv2i64 */ |
| 23906 | 17282, |
| 23907 | /* VQSUBsv4i16 */ |
| 23908 | 17287, |
| 23909 | /* VQSUBsv4i32 */ |
| 23910 | 17292, |
| 23911 | /* VQSUBsv8i16 */ |
| 23912 | 17297, |
| 23913 | /* VQSUBsv8i8 */ |
| 23914 | 17302, |
| 23915 | /* VQSUBuv16i8 */ |
| 23916 | 17307, |
| 23917 | /* VQSUBuv1i64 */ |
| 23918 | 17312, |
| 23919 | /* VQSUBuv2i32 */ |
| 23920 | 17317, |
| 23921 | /* VQSUBuv2i64 */ |
| 23922 | 17322, |
| 23923 | /* VQSUBuv4i16 */ |
| 23924 | 17327, |
| 23925 | /* VQSUBuv4i32 */ |
| 23926 | 17332, |
| 23927 | /* VQSUBuv8i16 */ |
| 23928 | 17337, |
| 23929 | /* VQSUBuv8i8 */ |
| 23930 | 17342, |
| 23931 | /* VRADDHNv2i32 */ |
| 23932 | 17347, |
| 23933 | /* VRADDHNv4i16 */ |
| 23934 | 17352, |
| 23935 | /* VRADDHNv8i8 */ |
| 23936 | 17357, |
| 23937 | /* VRECPEd */ |
| 23938 | 17362, |
| 23939 | /* VRECPEfd */ |
| 23940 | 17366, |
| 23941 | /* VRECPEfq */ |
| 23942 | 17370, |
| 23943 | /* VRECPEhd */ |
| 23944 | 17374, |
| 23945 | /* VRECPEhq */ |
| 23946 | 17378, |
| 23947 | /* VRECPEq */ |
| 23948 | 17382, |
| 23949 | /* VRECPSfd */ |
| 23950 | 17386, |
| 23951 | /* VRECPSfq */ |
| 23952 | 17391, |
| 23953 | /* VRECPShd */ |
| 23954 | 17396, |
| 23955 | /* VRECPShq */ |
| 23956 | 17401, |
| 23957 | /* VREV16d8 */ |
| 23958 | 17406, |
| 23959 | /* VREV16q8 */ |
| 23960 | 17410, |
| 23961 | /* VREV32d16 */ |
| 23962 | 17414, |
| 23963 | /* VREV32d8 */ |
| 23964 | 17418, |
| 23965 | /* VREV32q16 */ |
| 23966 | 17422, |
| 23967 | /* VREV32q8 */ |
| 23968 | 17426, |
| 23969 | /* VREV64d16 */ |
| 23970 | 17430, |
| 23971 | /* VREV64d32 */ |
| 23972 | 17434, |
| 23973 | /* VREV64d8 */ |
| 23974 | 17438, |
| 23975 | /* VREV64q16 */ |
| 23976 | 17442, |
| 23977 | /* VREV64q32 */ |
| 23978 | 17446, |
| 23979 | /* VREV64q8 */ |
| 23980 | 17450, |
| 23981 | /* VRHADDsv16i8 */ |
| 23982 | 17454, |
| 23983 | /* VRHADDsv2i32 */ |
| 23984 | 17459, |
| 23985 | /* VRHADDsv4i16 */ |
| 23986 | 17464, |
| 23987 | /* VRHADDsv4i32 */ |
| 23988 | 17469, |
| 23989 | /* VRHADDsv8i16 */ |
| 23990 | 17474, |
| 23991 | /* VRHADDsv8i8 */ |
| 23992 | 17479, |
| 23993 | /* VRHADDuv16i8 */ |
| 23994 | 17484, |
| 23995 | /* VRHADDuv2i32 */ |
| 23996 | 17489, |
| 23997 | /* VRHADDuv4i16 */ |
| 23998 | 17494, |
| 23999 | /* VRHADDuv4i32 */ |
| 24000 | 17499, |
| 24001 | /* VRHADDuv8i16 */ |
| 24002 | 17504, |
| 24003 | /* VRHADDuv8i8 */ |
| 24004 | 17509, |
| 24005 | /* VRINTAD */ |
| 24006 | 17514, |
| 24007 | /* VRINTAH */ |
| 24008 | 17516, |
| 24009 | /* VRINTANDf */ |
| 24010 | 17518, |
| 24011 | /* VRINTANDh */ |
| 24012 | 17520, |
| 24013 | /* VRINTANQf */ |
| 24014 | 17522, |
| 24015 | /* VRINTANQh */ |
| 24016 | 17524, |
| 24017 | /* VRINTAS */ |
| 24018 | 17526, |
| 24019 | /* VRINTMD */ |
| 24020 | 17528, |
| 24021 | /* VRINTMH */ |
| 24022 | 17530, |
| 24023 | /* VRINTMNDf */ |
| 24024 | 17532, |
| 24025 | /* VRINTMNDh */ |
| 24026 | 17534, |
| 24027 | /* VRINTMNQf */ |
| 24028 | 17536, |
| 24029 | /* VRINTMNQh */ |
| 24030 | 17538, |
| 24031 | /* VRINTMS */ |
| 24032 | 17540, |
| 24033 | /* VRINTND */ |
| 24034 | 17542, |
| 24035 | /* VRINTNH */ |
| 24036 | 17544, |
| 24037 | /* VRINTNNDf */ |
| 24038 | 17546, |
| 24039 | /* VRINTNNDh */ |
| 24040 | 17548, |
| 24041 | /* VRINTNNQf */ |
| 24042 | 17550, |
| 24043 | /* VRINTNNQh */ |
| 24044 | 17552, |
| 24045 | /* VRINTNS */ |
| 24046 | 17554, |
| 24047 | /* VRINTPD */ |
| 24048 | 17556, |
| 24049 | /* VRINTPH */ |
| 24050 | 17558, |
| 24051 | /* VRINTPNDf */ |
| 24052 | 17560, |
| 24053 | /* VRINTPNDh */ |
| 24054 | 17562, |
| 24055 | /* VRINTPNQf */ |
| 24056 | 17564, |
| 24057 | /* VRINTPNQh */ |
| 24058 | 17566, |
| 24059 | /* VRINTPS */ |
| 24060 | 17568, |
| 24061 | /* VRINTRD */ |
| 24062 | 17570, |
| 24063 | /* VRINTRH */ |
| 24064 | 17574, |
| 24065 | /* VRINTRS */ |
| 24066 | 17578, |
| 24067 | /* VRINTXD */ |
| 24068 | 17582, |
| 24069 | /* VRINTXH */ |
| 24070 | 17586, |
| 24071 | /* VRINTXNDf */ |
| 24072 | 17590, |
| 24073 | /* VRINTXNDh */ |
| 24074 | 17592, |
| 24075 | /* VRINTXNQf */ |
| 24076 | 17594, |
| 24077 | /* VRINTXNQh */ |
| 24078 | 17596, |
| 24079 | /* VRINTXS */ |
| 24080 | 17598, |
| 24081 | /* VRINTZD */ |
| 24082 | 17602, |
| 24083 | /* VRINTZH */ |
| 24084 | 17606, |
| 24085 | /* VRINTZNDf */ |
| 24086 | 17610, |
| 24087 | /* VRINTZNDh */ |
| 24088 | 17612, |
| 24089 | /* VRINTZNQf */ |
| 24090 | 17614, |
| 24091 | /* VRINTZNQh */ |
| 24092 | 17616, |
| 24093 | /* VRINTZS */ |
| 24094 | 17618, |
| 24095 | /* VRSHLsv16i8 */ |
| 24096 | 17622, |
| 24097 | /* VRSHLsv1i64 */ |
| 24098 | 17627, |
| 24099 | /* VRSHLsv2i32 */ |
| 24100 | 17632, |
| 24101 | /* VRSHLsv2i64 */ |
| 24102 | 17637, |
| 24103 | /* VRSHLsv4i16 */ |
| 24104 | 17642, |
| 24105 | /* VRSHLsv4i32 */ |
| 24106 | 17647, |
| 24107 | /* VRSHLsv8i16 */ |
| 24108 | 17652, |
| 24109 | /* VRSHLsv8i8 */ |
| 24110 | 17657, |
| 24111 | /* VRSHLuv16i8 */ |
| 24112 | 17662, |
| 24113 | /* VRSHLuv1i64 */ |
| 24114 | 17667, |
| 24115 | /* VRSHLuv2i32 */ |
| 24116 | 17672, |
| 24117 | /* VRSHLuv2i64 */ |
| 24118 | 17677, |
| 24119 | /* VRSHLuv4i16 */ |
| 24120 | 17682, |
| 24121 | /* VRSHLuv4i32 */ |
| 24122 | 17687, |
| 24123 | /* VRSHLuv8i16 */ |
| 24124 | 17692, |
| 24125 | /* VRSHLuv8i8 */ |
| 24126 | 17697, |
| 24127 | /* VRSHRNv2i32 */ |
| 24128 | 17702, |
| 24129 | /* VRSHRNv4i16 */ |
| 24130 | 17707, |
| 24131 | /* VRSHRNv8i8 */ |
| 24132 | 17712, |
| 24133 | /* VRSHRsv16i8 */ |
| 24134 | 17717, |
| 24135 | /* VRSHRsv1i64 */ |
| 24136 | 17722, |
| 24137 | /* VRSHRsv2i32 */ |
| 24138 | 17727, |
| 24139 | /* VRSHRsv2i64 */ |
| 24140 | 17732, |
| 24141 | /* VRSHRsv4i16 */ |
| 24142 | 17737, |
| 24143 | /* VRSHRsv4i32 */ |
| 24144 | 17742, |
| 24145 | /* VRSHRsv8i16 */ |
| 24146 | 17747, |
| 24147 | /* VRSHRsv8i8 */ |
| 24148 | 17752, |
| 24149 | /* VRSHRuv16i8 */ |
| 24150 | 17757, |
| 24151 | /* VRSHRuv1i64 */ |
| 24152 | 17762, |
| 24153 | /* VRSHRuv2i32 */ |
| 24154 | 17767, |
| 24155 | /* VRSHRuv2i64 */ |
| 24156 | 17772, |
| 24157 | /* VRSHRuv4i16 */ |
| 24158 | 17777, |
| 24159 | /* VRSHRuv4i32 */ |
| 24160 | 17782, |
| 24161 | /* VRSHRuv8i16 */ |
| 24162 | 17787, |
| 24163 | /* VRSHRuv8i8 */ |
| 24164 | 17792, |
| 24165 | /* VRSQRTEd */ |
| 24166 | 17797, |
| 24167 | /* VRSQRTEfd */ |
| 24168 | 17801, |
| 24169 | /* VRSQRTEfq */ |
| 24170 | 17805, |
| 24171 | /* VRSQRTEhd */ |
| 24172 | 17809, |
| 24173 | /* VRSQRTEhq */ |
| 24174 | 17813, |
| 24175 | /* VRSQRTEq */ |
| 24176 | 17817, |
| 24177 | /* VRSQRTSfd */ |
| 24178 | 17821, |
| 24179 | /* VRSQRTSfq */ |
| 24180 | 17826, |
| 24181 | /* VRSQRTShd */ |
| 24182 | 17831, |
| 24183 | /* VRSQRTShq */ |
| 24184 | 17836, |
| 24185 | /* VRSRAsv16i8 */ |
| 24186 | 17841, |
| 24187 | /* VRSRAsv1i64 */ |
| 24188 | 17847, |
| 24189 | /* VRSRAsv2i32 */ |
| 24190 | 17853, |
| 24191 | /* VRSRAsv2i64 */ |
| 24192 | 17859, |
| 24193 | /* VRSRAsv4i16 */ |
| 24194 | 17865, |
| 24195 | /* VRSRAsv4i32 */ |
| 24196 | 17871, |
| 24197 | /* VRSRAsv8i16 */ |
| 24198 | 17877, |
| 24199 | /* VRSRAsv8i8 */ |
| 24200 | 17883, |
| 24201 | /* VRSRAuv16i8 */ |
| 24202 | 17889, |
| 24203 | /* VRSRAuv1i64 */ |
| 24204 | 17895, |
| 24205 | /* VRSRAuv2i32 */ |
| 24206 | 17901, |
| 24207 | /* VRSRAuv2i64 */ |
| 24208 | 17907, |
| 24209 | /* VRSRAuv4i16 */ |
| 24210 | 17913, |
| 24211 | /* VRSRAuv4i32 */ |
| 24212 | 17919, |
| 24213 | /* VRSRAuv8i16 */ |
| 24214 | 17925, |
| 24215 | /* VRSRAuv8i8 */ |
| 24216 | 17931, |
| 24217 | /* VRSUBHNv2i32 */ |
| 24218 | 17937, |
| 24219 | /* VRSUBHNv4i16 */ |
| 24220 | 17942, |
| 24221 | /* VRSUBHNv8i8 */ |
| 24222 | 17947, |
| 24223 | /* VSCCLRMD */ |
| 24224 | 17952, |
| 24225 | /* VSCCLRMS */ |
| 24226 | 17955, |
| 24227 | /* VSDOTD */ |
| 24228 | 17958, |
| 24229 | /* VSDOTDI */ |
| 24230 | 17962, |
| 24231 | /* VSDOTQ */ |
| 24232 | 17967, |
| 24233 | /* VSDOTQI */ |
| 24234 | 17971, |
| 24235 | /* VSELEQD */ |
| 24236 | 17976, |
| 24237 | /* VSELEQH */ |
| 24238 | 17979, |
| 24239 | /* VSELEQS */ |
| 24240 | 17982, |
| 24241 | /* VSELGED */ |
| 24242 | 17985, |
| 24243 | /* VSELGEH */ |
| 24244 | 17988, |
| 24245 | /* VSELGES */ |
| 24246 | 17991, |
| 24247 | /* VSELGTD */ |
| 24248 | 17994, |
| 24249 | /* VSELGTH */ |
| 24250 | 17997, |
| 24251 | /* VSELGTS */ |
| 24252 | 18000, |
| 24253 | /* VSELVSD */ |
| 24254 | 18003, |
| 24255 | /* VSELVSH */ |
| 24256 | 18006, |
| 24257 | /* VSELVSS */ |
| 24258 | 18009, |
| 24259 | /* VSETLNi16 */ |
| 24260 | 18012, |
| 24261 | /* VSETLNi32 */ |
| 24262 | 18018, |
| 24263 | /* VSETLNi8 */ |
| 24264 | 18024, |
| 24265 | /* VSHLLi16 */ |
| 24266 | 18030, |
| 24267 | /* VSHLLi32 */ |
| 24268 | 18035, |
| 24269 | /* VSHLLi8 */ |
| 24270 | 18040, |
| 24271 | /* VSHLLsv2i64 */ |
| 24272 | 18045, |
| 24273 | /* VSHLLsv4i32 */ |
| 24274 | 18050, |
| 24275 | /* VSHLLsv8i16 */ |
| 24276 | 18055, |
| 24277 | /* VSHLLuv2i64 */ |
| 24278 | 18060, |
| 24279 | /* VSHLLuv4i32 */ |
| 24280 | 18065, |
| 24281 | /* VSHLLuv8i16 */ |
| 24282 | 18070, |
| 24283 | /* VSHLiv16i8 */ |
| 24284 | 18075, |
| 24285 | /* VSHLiv1i64 */ |
| 24286 | 18080, |
| 24287 | /* VSHLiv2i32 */ |
| 24288 | 18085, |
| 24289 | /* VSHLiv2i64 */ |
| 24290 | 18090, |
| 24291 | /* VSHLiv4i16 */ |
| 24292 | 18095, |
| 24293 | /* VSHLiv4i32 */ |
| 24294 | 18100, |
| 24295 | /* VSHLiv8i16 */ |
| 24296 | 18105, |
| 24297 | /* VSHLiv8i8 */ |
| 24298 | 18110, |
| 24299 | /* VSHLsv16i8 */ |
| 24300 | 18115, |
| 24301 | /* VSHLsv1i64 */ |
| 24302 | 18120, |
| 24303 | /* VSHLsv2i32 */ |
| 24304 | 18125, |
| 24305 | /* VSHLsv2i64 */ |
| 24306 | 18130, |
| 24307 | /* VSHLsv4i16 */ |
| 24308 | 18135, |
| 24309 | /* VSHLsv4i32 */ |
| 24310 | 18140, |
| 24311 | /* VSHLsv8i16 */ |
| 24312 | 18145, |
| 24313 | /* VSHLsv8i8 */ |
| 24314 | 18150, |
| 24315 | /* VSHLuv16i8 */ |
| 24316 | 18155, |
| 24317 | /* VSHLuv1i64 */ |
| 24318 | 18160, |
| 24319 | /* VSHLuv2i32 */ |
| 24320 | 18165, |
| 24321 | /* VSHLuv2i64 */ |
| 24322 | 18170, |
| 24323 | /* VSHLuv4i16 */ |
| 24324 | 18175, |
| 24325 | /* VSHLuv4i32 */ |
| 24326 | 18180, |
| 24327 | /* VSHLuv8i16 */ |
| 24328 | 18185, |
| 24329 | /* VSHLuv8i8 */ |
| 24330 | 18190, |
| 24331 | /* VSHRNv2i32 */ |
| 24332 | 18195, |
| 24333 | /* VSHRNv4i16 */ |
| 24334 | 18200, |
| 24335 | /* VSHRNv8i8 */ |
| 24336 | 18205, |
| 24337 | /* VSHRsv16i8 */ |
| 24338 | 18210, |
| 24339 | /* VSHRsv1i64 */ |
| 24340 | 18215, |
| 24341 | /* VSHRsv2i32 */ |
| 24342 | 18220, |
| 24343 | /* VSHRsv2i64 */ |
| 24344 | 18225, |
| 24345 | /* VSHRsv4i16 */ |
| 24346 | 18230, |
| 24347 | /* VSHRsv4i32 */ |
| 24348 | 18235, |
| 24349 | /* VSHRsv8i16 */ |
| 24350 | 18240, |
| 24351 | /* VSHRsv8i8 */ |
| 24352 | 18245, |
| 24353 | /* VSHRuv16i8 */ |
| 24354 | 18250, |
| 24355 | /* VSHRuv1i64 */ |
| 24356 | 18255, |
| 24357 | /* VSHRuv2i32 */ |
| 24358 | 18260, |
| 24359 | /* VSHRuv2i64 */ |
| 24360 | 18265, |
| 24361 | /* VSHRuv4i16 */ |
| 24362 | 18270, |
| 24363 | /* VSHRuv4i32 */ |
| 24364 | 18275, |
| 24365 | /* VSHRuv8i16 */ |
| 24366 | 18280, |
| 24367 | /* VSHRuv8i8 */ |
| 24368 | 18285, |
| 24369 | /* VSHTOD */ |
| 24370 | 18290, |
| 24371 | /* VSHTOH */ |
| 24372 | 18295, |
| 24373 | /* VSHTOS */ |
| 24374 | 18300, |
| 24375 | /* VSITOD */ |
| 24376 | 18305, |
| 24377 | /* VSITOH */ |
| 24378 | 18309, |
| 24379 | /* VSITOS */ |
| 24380 | 18313, |
| 24381 | /* VSLIv16i8 */ |
| 24382 | 18317, |
| 24383 | /* VSLIv1i64 */ |
| 24384 | 18323, |
| 24385 | /* VSLIv2i32 */ |
| 24386 | 18329, |
| 24387 | /* VSLIv2i64 */ |
| 24388 | 18335, |
| 24389 | /* VSLIv4i16 */ |
| 24390 | 18341, |
| 24391 | /* VSLIv4i32 */ |
| 24392 | 18347, |
| 24393 | /* VSLIv8i16 */ |
| 24394 | 18353, |
| 24395 | /* VSLIv8i8 */ |
| 24396 | 18359, |
| 24397 | /* VSLTOD */ |
| 24398 | 18365, |
| 24399 | /* VSLTOH */ |
| 24400 | 18370, |
| 24401 | /* VSLTOS */ |
| 24402 | 18375, |
| 24403 | /* VSMMLA */ |
| 24404 | 18380, |
| 24405 | /* VSQRTD */ |
| 24406 | 18384, |
| 24407 | /* VSQRTH */ |
| 24408 | 18388, |
| 24409 | /* VSQRTS */ |
| 24410 | 18392, |
| 24411 | /* VSRAsv16i8 */ |
| 24412 | 18396, |
| 24413 | /* VSRAsv1i64 */ |
| 24414 | 18402, |
| 24415 | /* VSRAsv2i32 */ |
| 24416 | 18408, |
| 24417 | /* VSRAsv2i64 */ |
| 24418 | 18414, |
| 24419 | /* VSRAsv4i16 */ |
| 24420 | 18420, |
| 24421 | /* VSRAsv4i32 */ |
| 24422 | 18426, |
| 24423 | /* VSRAsv8i16 */ |
| 24424 | 18432, |
| 24425 | /* VSRAsv8i8 */ |
| 24426 | 18438, |
| 24427 | /* VSRAuv16i8 */ |
| 24428 | 18444, |
| 24429 | /* VSRAuv1i64 */ |
| 24430 | 18450, |
| 24431 | /* VSRAuv2i32 */ |
| 24432 | 18456, |
| 24433 | /* VSRAuv2i64 */ |
| 24434 | 18462, |
| 24435 | /* VSRAuv4i16 */ |
| 24436 | 18468, |
| 24437 | /* VSRAuv4i32 */ |
| 24438 | 18474, |
| 24439 | /* VSRAuv8i16 */ |
| 24440 | 18480, |
| 24441 | /* VSRAuv8i8 */ |
| 24442 | 18486, |
| 24443 | /* VSRIv16i8 */ |
| 24444 | 18492, |
| 24445 | /* VSRIv1i64 */ |
| 24446 | 18498, |
| 24447 | /* VSRIv2i32 */ |
| 24448 | 18504, |
| 24449 | /* VSRIv2i64 */ |
| 24450 | 18510, |
| 24451 | /* VSRIv4i16 */ |
| 24452 | 18516, |
| 24453 | /* VSRIv4i32 */ |
| 24454 | 18522, |
| 24455 | /* VSRIv8i16 */ |
| 24456 | 18528, |
| 24457 | /* VSRIv8i8 */ |
| 24458 | 18534, |
| 24459 | /* VST1LNd16 */ |
| 24460 | 18540, |
| 24461 | /* VST1LNd16_UPD */ |
| 24462 | 18546, |
| 24463 | /* VST1LNd32 */ |
| 24464 | 18554, |
| 24465 | /* VST1LNd32_UPD */ |
| 24466 | 18560, |
| 24467 | /* VST1LNd8 */ |
| 24468 | 18568, |
| 24469 | /* VST1LNd8_UPD */ |
| 24470 | 18574, |
| 24471 | /* VST1LNq16Pseudo */ |
| 24472 | 18582, |
| 24473 | /* VST1LNq16Pseudo_UPD */ |
| 24474 | 18588, |
| 24475 | /* VST1LNq32Pseudo */ |
| 24476 | 18596, |
| 24477 | /* VST1LNq32Pseudo_UPD */ |
| 24478 | 18602, |
| 24479 | /* VST1LNq8Pseudo */ |
| 24480 | 18610, |
| 24481 | /* VST1LNq8Pseudo_UPD */ |
| 24482 | 18616, |
| 24483 | /* VST1d16 */ |
| 24484 | 18624, |
| 24485 | /* VST1d16Q */ |
| 24486 | 18629, |
| 24487 | /* VST1d16QPseudo */ |
| 24488 | 18634, |
| 24489 | /* VST1d16QPseudoWB_fixed */ |
| 24490 | 18639, |
| 24491 | /* VST1d16QPseudoWB_register */ |
| 24492 | 18645, |
| 24493 | /* VST1d16Qwb_fixed */ |
| 24494 | 18652, |
| 24495 | /* VST1d16Qwb_register */ |
| 24496 | 18658, |
| 24497 | /* VST1d16T */ |
| 24498 | 18665, |
| 24499 | /* VST1d16TPseudo */ |
| 24500 | 18670, |
| 24501 | /* VST1d16TPseudoWB_fixed */ |
| 24502 | 18675, |
| 24503 | /* VST1d16TPseudoWB_register */ |
| 24504 | 18681, |
| 24505 | /* VST1d16Twb_fixed */ |
| 24506 | 18688, |
| 24507 | /* VST1d16Twb_register */ |
| 24508 | 18694, |
| 24509 | /* VST1d16wb_fixed */ |
| 24510 | 18701, |
| 24511 | /* VST1d16wb_register */ |
| 24512 | 18707, |
| 24513 | /* VST1d32 */ |
| 24514 | 18714, |
| 24515 | /* VST1d32Q */ |
| 24516 | 18719, |
| 24517 | /* VST1d32QPseudo */ |
| 24518 | 18724, |
| 24519 | /* VST1d32QPseudoWB_fixed */ |
| 24520 | 18729, |
| 24521 | /* VST1d32QPseudoWB_register */ |
| 24522 | 18735, |
| 24523 | /* VST1d32Qwb_fixed */ |
| 24524 | 18742, |
| 24525 | /* VST1d32Qwb_register */ |
| 24526 | 18748, |
| 24527 | /* VST1d32T */ |
| 24528 | 18755, |
| 24529 | /* VST1d32TPseudo */ |
| 24530 | 18760, |
| 24531 | /* VST1d32TPseudoWB_fixed */ |
| 24532 | 18765, |
| 24533 | /* VST1d32TPseudoWB_register */ |
| 24534 | 18771, |
| 24535 | /* VST1d32Twb_fixed */ |
| 24536 | 18778, |
| 24537 | /* VST1d32Twb_register */ |
| 24538 | 18784, |
| 24539 | /* VST1d32wb_fixed */ |
| 24540 | 18791, |
| 24541 | /* VST1d32wb_register */ |
| 24542 | 18797, |
| 24543 | /* VST1d64 */ |
| 24544 | 18804, |
| 24545 | /* VST1d64Q */ |
| 24546 | 18809, |
| 24547 | /* VST1d64QPseudo */ |
| 24548 | 18814, |
| 24549 | /* VST1d64QPseudoWB_fixed */ |
| 24550 | 18819, |
| 24551 | /* VST1d64QPseudoWB_register */ |
| 24552 | 18825, |
| 24553 | /* VST1d64Qwb_fixed */ |
| 24554 | 18832, |
| 24555 | /* VST1d64Qwb_register */ |
| 24556 | 18838, |
| 24557 | /* VST1d64T */ |
| 24558 | 18845, |
| 24559 | /* VST1d64TPseudo */ |
| 24560 | 18850, |
| 24561 | /* VST1d64TPseudoWB_fixed */ |
| 24562 | 18855, |
| 24563 | /* VST1d64TPseudoWB_register */ |
| 24564 | 18861, |
| 24565 | /* VST1d64Twb_fixed */ |
| 24566 | 18868, |
| 24567 | /* VST1d64Twb_register */ |
| 24568 | 18874, |
| 24569 | /* VST1d64wb_fixed */ |
| 24570 | 18881, |
| 24571 | /* VST1d64wb_register */ |
| 24572 | 18887, |
| 24573 | /* VST1d8 */ |
| 24574 | 18894, |
| 24575 | /* VST1d8Q */ |
| 24576 | 18899, |
| 24577 | /* VST1d8QPseudo */ |
| 24578 | 18904, |
| 24579 | /* VST1d8QPseudoWB_fixed */ |
| 24580 | 18909, |
| 24581 | /* VST1d8QPseudoWB_register */ |
| 24582 | 18915, |
| 24583 | /* VST1d8Qwb_fixed */ |
| 24584 | 18922, |
| 24585 | /* VST1d8Qwb_register */ |
| 24586 | 18928, |
| 24587 | /* VST1d8T */ |
| 24588 | 18935, |
| 24589 | /* VST1d8TPseudo */ |
| 24590 | 18940, |
| 24591 | /* VST1d8TPseudoWB_fixed */ |
| 24592 | 18945, |
| 24593 | /* VST1d8TPseudoWB_register */ |
| 24594 | 18951, |
| 24595 | /* VST1d8Twb_fixed */ |
| 24596 | 18958, |
| 24597 | /* VST1d8Twb_register */ |
| 24598 | 18964, |
| 24599 | /* VST1d8wb_fixed */ |
| 24600 | 18971, |
| 24601 | /* VST1d8wb_register */ |
| 24602 | 18977, |
| 24603 | /* VST1q16 */ |
| 24604 | 18984, |
| 24605 | /* VST1q16HighQPseudo */ |
| 24606 | 18989, |
| 24607 | /* VST1q16HighQPseudo_UPD */ |
| 24608 | 18994, |
| 24609 | /* VST1q16HighTPseudo */ |
| 24610 | 19001, |
| 24611 | /* VST1q16HighTPseudo_UPD */ |
| 24612 | 19006, |
| 24613 | /* VST1q16LowQPseudo_UPD */ |
| 24614 | 19013, |
| 24615 | /* VST1q16LowTPseudo_UPD */ |
| 24616 | 19020, |
| 24617 | /* VST1q16wb_fixed */ |
| 24618 | 19027, |
| 24619 | /* VST1q16wb_register */ |
| 24620 | 19033, |
| 24621 | /* VST1q32 */ |
| 24622 | 19040, |
| 24623 | /* VST1q32HighQPseudo */ |
| 24624 | 19045, |
| 24625 | /* VST1q32HighQPseudo_UPD */ |
| 24626 | 19050, |
| 24627 | /* VST1q32HighTPseudo */ |
| 24628 | 19057, |
| 24629 | /* VST1q32HighTPseudo_UPD */ |
| 24630 | 19062, |
| 24631 | /* VST1q32LowQPseudo_UPD */ |
| 24632 | 19069, |
| 24633 | /* VST1q32LowTPseudo_UPD */ |
| 24634 | 19076, |
| 24635 | /* VST1q32wb_fixed */ |
| 24636 | 19083, |
| 24637 | /* VST1q32wb_register */ |
| 24638 | 19089, |
| 24639 | /* VST1q64 */ |
| 24640 | 19096, |
| 24641 | /* VST1q64HighQPseudo */ |
| 24642 | 19101, |
| 24643 | /* VST1q64HighQPseudo_UPD */ |
| 24644 | 19106, |
| 24645 | /* VST1q64HighTPseudo */ |
| 24646 | 19113, |
| 24647 | /* VST1q64HighTPseudo_UPD */ |
| 24648 | 19118, |
| 24649 | /* VST1q64LowQPseudo_UPD */ |
| 24650 | 19125, |
| 24651 | /* VST1q64LowTPseudo_UPD */ |
| 24652 | 19132, |
| 24653 | /* VST1q64wb_fixed */ |
| 24654 | 19139, |
| 24655 | /* VST1q64wb_register */ |
| 24656 | 19145, |
| 24657 | /* VST1q8 */ |
| 24658 | 19152, |
| 24659 | /* VST1q8HighQPseudo */ |
| 24660 | 19157, |
| 24661 | /* VST1q8HighQPseudo_UPD */ |
| 24662 | 19162, |
| 24663 | /* VST1q8HighTPseudo */ |
| 24664 | 19169, |
| 24665 | /* VST1q8HighTPseudo_UPD */ |
| 24666 | 19174, |
| 24667 | /* VST1q8LowQPseudo_UPD */ |
| 24668 | 19181, |
| 24669 | /* VST1q8LowTPseudo_UPD */ |
| 24670 | 19188, |
| 24671 | /* VST1q8wb_fixed */ |
| 24672 | 19195, |
| 24673 | /* VST1q8wb_register */ |
| 24674 | 19201, |
| 24675 | /* VST2LNd16 */ |
| 24676 | 19208, |
| 24677 | /* VST2LNd16Pseudo */ |
| 24678 | 19215, |
| 24679 | /* VST2LNd16Pseudo_UPD */ |
| 24680 | 19221, |
| 24681 | /* VST2LNd16_UPD */ |
| 24682 | 19229, |
| 24683 | /* VST2LNd32 */ |
| 24684 | 19238, |
| 24685 | /* VST2LNd32Pseudo */ |
| 24686 | 19245, |
| 24687 | /* VST2LNd32Pseudo_UPD */ |
| 24688 | 19251, |
| 24689 | /* VST2LNd32_UPD */ |
| 24690 | 19259, |
| 24691 | /* VST2LNd8 */ |
| 24692 | 19268, |
| 24693 | /* VST2LNd8Pseudo */ |
| 24694 | 19275, |
| 24695 | /* VST2LNd8Pseudo_UPD */ |
| 24696 | 19281, |
| 24697 | /* VST2LNd8_UPD */ |
| 24698 | 19289, |
| 24699 | /* VST2LNq16 */ |
| 24700 | 19298, |
| 24701 | /* VST2LNq16Pseudo */ |
| 24702 | 19305, |
| 24703 | /* VST2LNq16Pseudo_UPD */ |
| 24704 | 19311, |
| 24705 | /* VST2LNq16_UPD */ |
| 24706 | 19319, |
| 24707 | /* VST2LNq32 */ |
| 24708 | 19328, |
| 24709 | /* VST2LNq32Pseudo */ |
| 24710 | 19335, |
| 24711 | /* VST2LNq32Pseudo_UPD */ |
| 24712 | 19341, |
| 24713 | /* VST2LNq32_UPD */ |
| 24714 | 19349, |
| 24715 | /* VST2b16 */ |
| 24716 | 19358, |
| 24717 | /* VST2b16wb_fixed */ |
| 24718 | 19363, |
| 24719 | /* VST2b16wb_register */ |
| 24720 | 19369, |
| 24721 | /* VST2b32 */ |
| 24722 | 19376, |
| 24723 | /* VST2b32wb_fixed */ |
| 24724 | 19381, |
| 24725 | /* VST2b32wb_register */ |
| 24726 | 19387, |
| 24727 | /* VST2b8 */ |
| 24728 | 19394, |
| 24729 | /* VST2b8wb_fixed */ |
| 24730 | 19399, |
| 24731 | /* VST2b8wb_register */ |
| 24732 | 19405, |
| 24733 | /* VST2d16 */ |
| 24734 | 19412, |
| 24735 | /* VST2d16wb_fixed */ |
| 24736 | 19417, |
| 24737 | /* VST2d16wb_register */ |
| 24738 | 19423, |
| 24739 | /* VST2d32 */ |
| 24740 | 19430, |
| 24741 | /* VST2d32wb_fixed */ |
| 24742 | 19435, |
| 24743 | /* VST2d32wb_register */ |
| 24744 | 19441, |
| 24745 | /* VST2d8 */ |
| 24746 | 19448, |
| 24747 | /* VST2d8wb_fixed */ |
| 24748 | 19453, |
| 24749 | /* VST2d8wb_register */ |
| 24750 | 19459, |
| 24751 | /* VST2q16 */ |
| 24752 | 19466, |
| 24753 | /* VST2q16Pseudo */ |
| 24754 | 19471, |
| 24755 | /* VST2q16PseudoWB_fixed */ |
| 24756 | 19476, |
| 24757 | /* VST2q16PseudoWB_register */ |
| 24758 | 19482, |
| 24759 | /* VST2q16wb_fixed */ |
| 24760 | 19489, |
| 24761 | /* VST2q16wb_register */ |
| 24762 | 19495, |
| 24763 | /* VST2q32 */ |
| 24764 | 19502, |
| 24765 | /* VST2q32Pseudo */ |
| 24766 | 19507, |
| 24767 | /* VST2q32PseudoWB_fixed */ |
| 24768 | 19512, |
| 24769 | /* VST2q32PseudoWB_register */ |
| 24770 | 19518, |
| 24771 | /* VST2q32wb_fixed */ |
| 24772 | 19525, |
| 24773 | /* VST2q32wb_register */ |
| 24774 | 19531, |
| 24775 | /* VST2q8 */ |
| 24776 | 19538, |
| 24777 | /* VST2q8Pseudo */ |
| 24778 | 19543, |
| 24779 | /* VST2q8PseudoWB_fixed */ |
| 24780 | 19548, |
| 24781 | /* VST2q8PseudoWB_register */ |
| 24782 | 19554, |
| 24783 | /* VST2q8wb_fixed */ |
| 24784 | 19561, |
| 24785 | /* VST2q8wb_register */ |
| 24786 | 19567, |
| 24787 | /* VST3LNd16 */ |
| 24788 | 19574, |
| 24789 | /* VST3LNd16Pseudo */ |
| 24790 | 19582, |
| 24791 | /* VST3LNd16Pseudo_UPD */ |
| 24792 | 19588, |
| 24793 | /* VST3LNd16_UPD */ |
| 24794 | 19596, |
| 24795 | /* VST3LNd32 */ |
| 24796 | 19606, |
| 24797 | /* VST3LNd32Pseudo */ |
| 24798 | 19614, |
| 24799 | /* VST3LNd32Pseudo_UPD */ |
| 24800 | 19620, |
| 24801 | /* VST3LNd32_UPD */ |
| 24802 | 19628, |
| 24803 | /* VST3LNd8 */ |
| 24804 | 19638, |
| 24805 | /* VST3LNd8Pseudo */ |
| 24806 | 19646, |
| 24807 | /* VST3LNd8Pseudo_UPD */ |
| 24808 | 19652, |
| 24809 | /* VST3LNd8_UPD */ |
| 24810 | 19660, |
| 24811 | /* VST3LNq16 */ |
| 24812 | 19670, |
| 24813 | /* VST3LNq16Pseudo */ |
| 24814 | 19678, |
| 24815 | /* VST3LNq16Pseudo_UPD */ |
| 24816 | 19684, |
| 24817 | /* VST3LNq16_UPD */ |
| 24818 | 19692, |
| 24819 | /* VST3LNq32 */ |
| 24820 | 19702, |
| 24821 | /* VST3LNq32Pseudo */ |
| 24822 | 19710, |
| 24823 | /* VST3LNq32Pseudo_UPD */ |
| 24824 | 19716, |
| 24825 | /* VST3LNq32_UPD */ |
| 24826 | 19724, |
| 24827 | /* VST3d16 */ |
| 24828 | 19734, |
| 24829 | /* VST3d16Pseudo */ |
| 24830 | 19741, |
| 24831 | /* VST3d16Pseudo_UPD */ |
| 24832 | 19746, |
| 24833 | /* VST3d16_UPD */ |
| 24834 | 19753, |
| 24835 | /* VST3d32 */ |
| 24836 | 19762, |
| 24837 | /* VST3d32Pseudo */ |
| 24838 | 19769, |
| 24839 | /* VST3d32Pseudo_UPD */ |
| 24840 | 19774, |
| 24841 | /* VST3d32_UPD */ |
| 24842 | 19781, |
| 24843 | /* VST3d8 */ |
| 24844 | 19790, |
| 24845 | /* VST3d8Pseudo */ |
| 24846 | 19797, |
| 24847 | /* VST3d8Pseudo_UPD */ |
| 24848 | 19802, |
| 24849 | /* VST3d8_UPD */ |
| 24850 | 19809, |
| 24851 | /* VST3q16 */ |
| 24852 | 19818, |
| 24853 | /* VST3q16Pseudo_UPD */ |
| 24854 | 19825, |
| 24855 | /* VST3q16_UPD */ |
| 24856 | 19832, |
| 24857 | /* VST3q16oddPseudo */ |
| 24858 | 19841, |
| 24859 | /* VST3q16oddPseudo_UPD */ |
| 24860 | 19846, |
| 24861 | /* VST3q32 */ |
| 24862 | 19853, |
| 24863 | /* VST3q32Pseudo_UPD */ |
| 24864 | 19860, |
| 24865 | /* VST3q32_UPD */ |
| 24866 | 19867, |
| 24867 | /* VST3q32oddPseudo */ |
| 24868 | 19876, |
| 24869 | /* VST3q32oddPseudo_UPD */ |
| 24870 | 19881, |
| 24871 | /* VST3q8 */ |
| 24872 | 19888, |
| 24873 | /* VST3q8Pseudo_UPD */ |
| 24874 | 19895, |
| 24875 | /* VST3q8_UPD */ |
| 24876 | 19902, |
| 24877 | /* VST3q8oddPseudo */ |
| 24878 | 19911, |
| 24879 | /* VST3q8oddPseudo_UPD */ |
| 24880 | 19916, |
| 24881 | /* VST4LNd16 */ |
| 24882 | 19923, |
| 24883 | /* VST4LNd16Pseudo */ |
| 24884 | 19932, |
| 24885 | /* VST4LNd16Pseudo_UPD */ |
| 24886 | 19938, |
| 24887 | /* VST4LNd16_UPD */ |
| 24888 | 19946, |
| 24889 | /* VST4LNd32 */ |
| 24890 | 19957, |
| 24891 | /* VST4LNd32Pseudo */ |
| 24892 | 19966, |
| 24893 | /* VST4LNd32Pseudo_UPD */ |
| 24894 | 19972, |
| 24895 | /* VST4LNd32_UPD */ |
| 24896 | 19980, |
| 24897 | /* VST4LNd8 */ |
| 24898 | 19991, |
| 24899 | /* VST4LNd8Pseudo */ |
| 24900 | 20000, |
| 24901 | /* VST4LNd8Pseudo_UPD */ |
| 24902 | 20006, |
| 24903 | /* VST4LNd8_UPD */ |
| 24904 | 20014, |
| 24905 | /* VST4LNq16 */ |
| 24906 | 20025, |
| 24907 | /* VST4LNq16Pseudo */ |
| 24908 | 20034, |
| 24909 | /* VST4LNq16Pseudo_UPD */ |
| 24910 | 20040, |
| 24911 | /* VST4LNq16_UPD */ |
| 24912 | 20048, |
| 24913 | /* VST4LNq32 */ |
| 24914 | 20059, |
| 24915 | /* VST4LNq32Pseudo */ |
| 24916 | 20068, |
| 24917 | /* VST4LNq32Pseudo_UPD */ |
| 24918 | 20074, |
| 24919 | /* VST4LNq32_UPD */ |
| 24920 | 20082, |
| 24921 | /* VST4d16 */ |
| 24922 | 20093, |
| 24923 | /* VST4d16Pseudo */ |
| 24924 | 20101, |
| 24925 | /* VST4d16Pseudo_UPD */ |
| 24926 | 20106, |
| 24927 | /* VST4d16_UPD */ |
| 24928 | 20113, |
| 24929 | /* VST4d32 */ |
| 24930 | 20123, |
| 24931 | /* VST4d32Pseudo */ |
| 24932 | 20131, |
| 24933 | /* VST4d32Pseudo_UPD */ |
| 24934 | 20136, |
| 24935 | /* VST4d32_UPD */ |
| 24936 | 20143, |
| 24937 | /* VST4d8 */ |
| 24938 | 20153, |
| 24939 | /* VST4d8Pseudo */ |
| 24940 | 20161, |
| 24941 | /* VST4d8Pseudo_UPD */ |
| 24942 | 20166, |
| 24943 | /* VST4d8_UPD */ |
| 24944 | 20173, |
| 24945 | /* VST4q16 */ |
| 24946 | 20183, |
| 24947 | /* VST4q16Pseudo_UPD */ |
| 24948 | 20191, |
| 24949 | /* VST4q16_UPD */ |
| 24950 | 20198, |
| 24951 | /* VST4q16oddPseudo */ |
| 24952 | 20208, |
| 24953 | /* VST4q16oddPseudo_UPD */ |
| 24954 | 20213, |
| 24955 | /* VST4q32 */ |
| 24956 | 20220, |
| 24957 | /* VST4q32Pseudo_UPD */ |
| 24958 | 20228, |
| 24959 | /* VST4q32_UPD */ |
| 24960 | 20235, |
| 24961 | /* VST4q32oddPseudo */ |
| 24962 | 20245, |
| 24963 | /* VST4q32oddPseudo_UPD */ |
| 24964 | 20250, |
| 24965 | /* VST4q8 */ |
| 24966 | 20257, |
| 24967 | /* VST4q8Pseudo_UPD */ |
| 24968 | 20265, |
| 24969 | /* VST4q8_UPD */ |
| 24970 | 20272, |
| 24971 | /* VST4q8oddPseudo */ |
| 24972 | 20282, |
| 24973 | /* VST4q8oddPseudo_UPD */ |
| 24974 | 20287, |
| 24975 | /* VSTMDDB_UPD */ |
| 24976 | 20294, |
| 24977 | /* VSTMDIA */ |
| 24978 | 20299, |
| 24979 | /* VSTMDIA_UPD */ |
| 24980 | 20303, |
| 24981 | /* VSTMQIA */ |
| 24982 | 20308, |
| 24983 | /* VSTMSDB_UPD */ |
| 24984 | 20312, |
| 24985 | /* VSTMSIA */ |
| 24986 | 20317, |
| 24987 | /* VSTMSIA_UPD */ |
| 24988 | 20321, |
| 24989 | /* VSTRD */ |
| 24990 | 20326, |
| 24991 | /* VSTRH */ |
| 24992 | 20331, |
| 24993 | /* VSTRS */ |
| 24994 | 20336, |
| 24995 | /* VSTR_FPCXTNS_off */ |
| 24996 | 20341, |
| 24997 | /* VSTR_FPCXTNS_post */ |
| 24998 | 20345, |
| 24999 | /* VSTR_FPCXTNS_pre */ |
| 25000 | 20350, |
| 25001 | /* VSTR_FPCXTS_off */ |
| 25002 | 20355, |
| 25003 | /* VSTR_FPCXTS_post */ |
| 25004 | 20359, |
| 25005 | /* VSTR_FPCXTS_pre */ |
| 25006 | 20364, |
| 25007 | /* VSTR_FPSCR_NZCVQC_off */ |
| 25008 | 20369, |
| 25009 | /* VSTR_FPSCR_NZCVQC_post */ |
| 25010 | 20373, |
| 25011 | /* VSTR_FPSCR_NZCVQC_pre */ |
| 25012 | 20378, |
| 25013 | /* VSTR_FPSCR_off */ |
| 25014 | 20383, |
| 25015 | /* VSTR_FPSCR_post */ |
| 25016 | 20387, |
| 25017 | /* VSTR_FPSCR_pre */ |
| 25018 | 20392, |
| 25019 | /* VSTR_P0_off */ |
| 25020 | 20397, |
| 25021 | /* VSTR_P0_post */ |
| 25022 | 20402, |
| 25023 | /* VSTR_P0_pre */ |
| 25024 | 20408, |
| 25025 | /* VSTR_VPR_off */ |
| 25026 | 20414, |
| 25027 | /* VSTR_VPR_post */ |
| 25028 | 20418, |
| 25029 | /* VSTR_VPR_pre */ |
| 25030 | 20423, |
| 25031 | /* VSUBD */ |
| 25032 | 20428, |
| 25033 | /* VSUBH */ |
| 25034 | 20433, |
| 25035 | /* VSUBHNv2i32 */ |
| 25036 | 20438, |
| 25037 | /* VSUBHNv4i16 */ |
| 25038 | 20443, |
| 25039 | /* VSUBHNv8i8 */ |
| 25040 | 20448, |
| 25041 | /* VSUBLsv2i64 */ |
| 25042 | 20453, |
| 25043 | /* VSUBLsv4i32 */ |
| 25044 | 20458, |
| 25045 | /* VSUBLsv8i16 */ |
| 25046 | 20463, |
| 25047 | /* VSUBLuv2i64 */ |
| 25048 | 20468, |
| 25049 | /* VSUBLuv4i32 */ |
| 25050 | 20473, |
| 25051 | /* VSUBLuv8i16 */ |
| 25052 | 20478, |
| 25053 | /* VSUBS */ |
| 25054 | 20483, |
| 25055 | /* VSUBWsv2i64 */ |
| 25056 | 20488, |
| 25057 | /* VSUBWsv4i32 */ |
| 25058 | 20493, |
| 25059 | /* VSUBWsv8i16 */ |
| 25060 | 20498, |
| 25061 | /* VSUBWuv2i64 */ |
| 25062 | 20503, |
| 25063 | /* VSUBWuv4i32 */ |
| 25064 | 20508, |
| 25065 | /* VSUBWuv8i16 */ |
| 25066 | 20513, |
| 25067 | /* VSUBfd */ |
| 25068 | 20518, |
| 25069 | /* VSUBfq */ |
| 25070 | 20523, |
| 25071 | /* VSUBhd */ |
| 25072 | 20528, |
| 25073 | /* VSUBhq */ |
| 25074 | 20533, |
| 25075 | /* VSUBv16i8 */ |
| 25076 | 20538, |
| 25077 | /* VSUBv1i64 */ |
| 25078 | 20543, |
| 25079 | /* VSUBv2i32 */ |
| 25080 | 20548, |
| 25081 | /* VSUBv2i64 */ |
| 25082 | 20553, |
| 25083 | /* VSUBv4i16 */ |
| 25084 | 20558, |
| 25085 | /* VSUBv4i32 */ |
| 25086 | 20563, |
| 25087 | /* VSUBv8i16 */ |
| 25088 | 20568, |
| 25089 | /* VSUBv8i8 */ |
| 25090 | 20573, |
| 25091 | /* VSUDOTDI */ |
| 25092 | 20578, |
| 25093 | /* VSUDOTQI */ |
| 25094 | 20583, |
| 25095 | /* VSWPd */ |
| 25096 | 20588, |
| 25097 | /* VSWPq */ |
| 25098 | 20594, |
| 25099 | /* VTBL1 */ |
| 25100 | 20600, |
| 25101 | /* VTBL2 */ |
| 25102 | 20605, |
| 25103 | /* VTBL3 */ |
| 25104 | 20610, |
| 25105 | /* VTBL3Pseudo */ |
| 25106 | 20615, |
| 25107 | /* VTBL4 */ |
| 25108 | 20620, |
| 25109 | /* VTBL4Pseudo */ |
| 25110 | 20625, |
| 25111 | /* VTBX1 */ |
| 25112 | 20630, |
| 25113 | /* VTBX2 */ |
| 25114 | 20636, |
| 25115 | /* VTBX3 */ |
| 25116 | 20642, |
| 25117 | /* VTBX3Pseudo */ |
| 25118 | 20648, |
| 25119 | /* VTBX4 */ |
| 25120 | 20654, |
| 25121 | /* VTBX4Pseudo */ |
| 25122 | 20660, |
| 25123 | /* VTOSHD */ |
| 25124 | 20666, |
| 25125 | /* VTOSHH */ |
| 25126 | 20671, |
| 25127 | /* VTOSHS */ |
| 25128 | 20676, |
| 25129 | /* VTOSIRD */ |
| 25130 | 20681, |
| 25131 | /* VTOSIRH */ |
| 25132 | 20685, |
| 25133 | /* VTOSIRS */ |
| 25134 | 20689, |
| 25135 | /* VTOSIZD */ |
| 25136 | 20693, |
| 25137 | /* VTOSIZH */ |
| 25138 | 20697, |
| 25139 | /* VTOSIZS */ |
| 25140 | 20701, |
| 25141 | /* VTOSLD */ |
| 25142 | 20705, |
| 25143 | /* VTOSLH */ |
| 25144 | 20710, |
| 25145 | /* VTOSLS */ |
| 25146 | 20715, |
| 25147 | /* VTOUHD */ |
| 25148 | 20720, |
| 25149 | /* VTOUHH */ |
| 25150 | 20725, |
| 25151 | /* VTOUHS */ |
| 25152 | 20730, |
| 25153 | /* VTOUIRD */ |
| 25154 | 20735, |
| 25155 | /* VTOUIRH */ |
| 25156 | 20739, |
| 25157 | /* VTOUIRS */ |
| 25158 | 20743, |
| 25159 | /* VTOUIZD */ |
| 25160 | 20747, |
| 25161 | /* VTOUIZH */ |
| 25162 | 20751, |
| 25163 | /* VTOUIZS */ |
| 25164 | 20755, |
| 25165 | /* VTOULD */ |
| 25166 | 20759, |
| 25167 | /* VTOULH */ |
| 25168 | 20764, |
| 25169 | /* VTOULS */ |
| 25170 | 20769, |
| 25171 | /* VTRNd16 */ |
| 25172 | 20774, |
| 25173 | /* VTRNd32 */ |
| 25174 | 20780, |
| 25175 | /* VTRNd8 */ |
| 25176 | 20786, |
| 25177 | /* VTRNq16 */ |
| 25178 | 20792, |
| 25179 | /* VTRNq32 */ |
| 25180 | 20798, |
| 25181 | /* VTRNq8 */ |
| 25182 | 20804, |
| 25183 | /* VTSTv16i8 */ |
| 25184 | 20810, |
| 25185 | /* VTSTv2i32 */ |
| 25186 | 20815, |
| 25187 | /* VTSTv4i16 */ |
| 25188 | 20820, |
| 25189 | /* VTSTv4i32 */ |
| 25190 | 20825, |
| 25191 | /* VTSTv8i16 */ |
| 25192 | 20830, |
| 25193 | /* VTSTv8i8 */ |
| 25194 | 20835, |
| 25195 | /* VUDOTD */ |
| 25196 | 20840, |
| 25197 | /* VUDOTDI */ |
| 25198 | 20844, |
| 25199 | /* VUDOTQ */ |
| 25200 | 20849, |
| 25201 | /* VUDOTQI */ |
| 25202 | 20853, |
| 25203 | /* VUHTOD */ |
| 25204 | 20858, |
| 25205 | /* VUHTOH */ |
| 25206 | 20863, |
| 25207 | /* VUHTOS */ |
| 25208 | 20868, |
| 25209 | /* VUITOD */ |
| 25210 | 20873, |
| 25211 | /* VUITOH */ |
| 25212 | 20877, |
| 25213 | /* VUITOS */ |
| 25214 | 20881, |
| 25215 | /* VULTOD */ |
| 25216 | 20885, |
| 25217 | /* VULTOH */ |
| 25218 | 20890, |
| 25219 | /* VULTOS */ |
| 25220 | 20895, |
| 25221 | /* VUMMLA */ |
| 25222 | 20900, |
| 25223 | /* VUSDOTD */ |
| 25224 | 20904, |
| 25225 | /* VUSDOTDI */ |
| 25226 | 20908, |
| 25227 | /* VUSDOTQ */ |
| 25228 | 20913, |
| 25229 | /* VUSDOTQI */ |
| 25230 | 20917, |
| 25231 | /* VUSMMLA */ |
| 25232 | 20922, |
| 25233 | /* VUZPd16 */ |
| 25234 | 20926, |
| 25235 | /* VUZPd8 */ |
| 25236 | 20932, |
| 25237 | /* VUZPq16 */ |
| 25238 | 20938, |
| 25239 | /* VUZPq32 */ |
| 25240 | 20944, |
| 25241 | /* VUZPq8 */ |
| 25242 | 20950, |
| 25243 | /* VZIPd16 */ |
| 25244 | 20956, |
| 25245 | /* VZIPd8 */ |
| 25246 | 20962, |
| 25247 | /* VZIPq16 */ |
| 25248 | 20968, |
| 25249 | /* VZIPq32 */ |
| 25250 | 20974, |
| 25251 | /* VZIPq8 */ |
| 25252 | 20980, |
| 25253 | /* sysLDMDA */ |
| 25254 | 20986, |
| 25255 | /* sysLDMDA_UPD */ |
| 25256 | 20990, |
| 25257 | /* sysLDMDB */ |
| 25258 | 20995, |
| 25259 | /* sysLDMDB_UPD */ |
| 25260 | 20999, |
| 25261 | /* sysLDMIA */ |
| 25262 | 21004, |
| 25263 | /* sysLDMIA_UPD */ |
| 25264 | 21008, |
| 25265 | /* sysLDMIB */ |
| 25266 | 21013, |
| 25267 | /* sysLDMIB_UPD */ |
| 25268 | 21017, |
| 25269 | /* sysSTMDA */ |
| 25270 | 21022, |
| 25271 | /* sysSTMDA_UPD */ |
| 25272 | 21026, |
| 25273 | /* sysSTMDB */ |
| 25274 | 21031, |
| 25275 | /* sysSTMDB_UPD */ |
| 25276 | 21035, |
| 25277 | /* sysSTMIA */ |
| 25278 | 21040, |
| 25279 | /* sysSTMIA_UPD */ |
| 25280 | 21044, |
| 25281 | /* sysSTMIB */ |
| 25282 | 21049, |
| 25283 | /* sysSTMIB_UPD */ |
| 25284 | 21053, |
| 25285 | /* t2ADCri */ |
| 25286 | 21058, |
| 25287 | /* t2ADCrr */ |
| 25288 | 21064, |
| 25289 | /* t2ADCrs */ |
| 25290 | 21070, |
| 25291 | /* t2ADDri */ |
| 25292 | 21077, |
| 25293 | /* t2ADDri12 */ |
| 25294 | 21083, |
| 25295 | /* t2ADDrr */ |
| 25296 | 21088, |
| 25297 | /* t2ADDrs */ |
| 25298 | 21094, |
| 25299 | /* t2ADDspImm */ |
| 25300 | 21101, |
| 25301 | /* t2ADDspImm12 */ |
| 25302 | 21107, |
| 25303 | /* t2ADR */ |
| 25304 | 21112, |
| 25305 | /* t2ANDri */ |
| 25306 | 21116, |
| 25307 | /* t2ANDrr */ |
| 25308 | 21122, |
| 25309 | /* t2ANDrs */ |
| 25310 | 21128, |
| 25311 | /* t2ASRri */ |
| 25312 | 21135, |
| 25313 | /* t2ASRrr */ |
| 25314 | 21141, |
| 25315 | /* t2AUT */ |
| 25316 | 21147, |
| 25317 | /* t2AUTG */ |
| 25318 | 21147, |
| 25319 | /* t2B */ |
| 25320 | 21152, |
| 25321 | /* t2BFC */ |
| 25322 | 21155, |
| 25323 | /* t2BFI */ |
| 25324 | 21160, |
| 25325 | /* t2BFLi */ |
| 25326 | 21166, |
| 25327 | /* t2BFLr */ |
| 25328 | 21170, |
| 25329 | /* t2BFi */ |
| 25330 | 21174, |
| 25331 | /* t2BFic */ |
| 25332 | 21178, |
| 25333 | /* t2BFr */ |
| 25334 | 21182, |
| 25335 | /* t2BICri */ |
| 25336 | 21186, |
| 25337 | /* t2BICrr */ |
| 25338 | 21192, |
| 25339 | /* t2BICrs */ |
| 25340 | 21198, |
| 25341 | /* t2BTI */ |
| 25342 | 21205, |
| 25343 | /* t2BXAUT */ |
| 25344 | 21205, |
| 25345 | /* t2BXJ */ |
| 25346 | 21210, |
| 25347 | /* t2Bcc */ |
| 25348 | 21213, |
| 25349 | /* t2CDP */ |
| 25350 | 21216, |
| 25351 | /* t2CDP2 */ |
| 25352 | 21224, |
| 25353 | /* t2CLREX */ |
| 25354 | 21232, |
| 25355 | /* t2CLRM */ |
| 25356 | 21234, |
| 25357 | /* t2CLZ */ |
| 25358 | 21237, |
| 25359 | /* t2CMNri */ |
| 25360 | 21241, |
| 25361 | /* t2CMNzrr */ |
| 25362 | 21245, |
| 25363 | /* t2CMNzrs */ |
| 25364 | 21249, |
| 25365 | /* t2CMPri */ |
| 25366 | 21254, |
| 25367 | /* t2CMPrr */ |
| 25368 | 21258, |
| 25369 | /* t2CMPrs */ |
| 25370 | 21262, |
| 25371 | /* t2CPS1p */ |
| 25372 | 21267, |
| 25373 | /* t2CPS2p */ |
| 25374 | 21268, |
| 25375 | /* t2CPS3p */ |
| 25376 | 21270, |
| 25377 | /* t2CRC32B */ |
| 25378 | 21273, |
| 25379 | /* t2CRC32CB */ |
| 25380 | 21276, |
| 25381 | /* t2CRC32CH */ |
| 25382 | 21279, |
| 25383 | /* t2CRC32CW */ |
| 25384 | 21282, |
| 25385 | /* t2CRC32H */ |
| 25386 | 21285, |
| 25387 | /* t2CRC32W */ |
| 25388 | 21288, |
| 25389 | /* t2CSEL */ |
| 25390 | 21291, |
| 25391 | /* t2CSINC */ |
| 25392 | 21295, |
| 25393 | /* t2CSINV */ |
| 25394 | 21299, |
| 25395 | /* t2CSNEG */ |
| 25396 | 21303, |
| 25397 | /* t2DBG */ |
| 25398 | 21307, |
| 25399 | /* t2DCPS1 */ |
| 25400 | 21310, |
| 25401 | /* t2DCPS2 */ |
| 25402 | 21312, |
| 25403 | /* t2DCPS3 */ |
| 25404 | 21314, |
| 25405 | /* t2DLS */ |
| 25406 | 21316, |
| 25407 | /* t2DMB */ |
| 25408 | 21318, |
| 25409 | /* t2DSB */ |
| 25410 | 21321, |
| 25411 | /* t2EORri */ |
| 25412 | 21324, |
| 25413 | /* t2EORrr */ |
| 25414 | 21330, |
| 25415 | /* t2EORrs */ |
| 25416 | 21336, |
| 25417 | /* t2HINT */ |
| 25418 | 21343, |
| 25419 | /* t2HVC */ |
| 25420 | 21346, |
| 25421 | /* t2ISB */ |
| 25422 | 21347, |
| 25423 | /* t2IT */ |
| 25424 | 21350, |
| 25425 | /* t2Int_eh_sjlj_setjmp */ |
| 25426 | 21352, |
| 25427 | /* t2Int_eh_sjlj_setjmp_nofp */ |
| 25428 | 21354, |
| 25429 | /* t2LDA */ |
| 25430 | 21356, |
| 25431 | /* t2LDAB */ |
| 25432 | 21360, |
| 25433 | /* t2LDAEX */ |
| 25434 | 21364, |
| 25435 | /* t2LDAEXB */ |
| 25436 | 21368, |
| 25437 | /* t2LDAEXD */ |
| 25438 | 21372, |
| 25439 | /* t2LDAEXH */ |
| 25440 | 21377, |
| 25441 | /* t2LDAH */ |
| 25442 | 21381, |
| 25443 | /* t2LDC2L_OFFSET */ |
| 25444 | 21385, |
| 25445 | /* t2LDC2L_OPTION */ |
| 25446 | 21391, |
| 25447 | /* t2LDC2L_POST */ |
| 25448 | 21397, |
| 25449 | /* t2LDC2L_PRE */ |
| 25450 | 21403, |
| 25451 | /* t2LDC2_OFFSET */ |
| 25452 | 21409, |
| 25453 | /* t2LDC2_OPTION */ |
| 25454 | 21415, |
| 25455 | /* t2LDC2_POST */ |
| 25456 | 21421, |
| 25457 | /* t2LDC2_PRE */ |
| 25458 | 21427, |
| 25459 | /* t2LDCL_OFFSET */ |
| 25460 | 21433, |
| 25461 | /* t2LDCL_OPTION */ |
| 25462 | 21439, |
| 25463 | /* t2LDCL_POST */ |
| 25464 | 21445, |
| 25465 | /* t2LDCL_PRE */ |
| 25466 | 21451, |
| 25467 | /* t2LDC_OFFSET */ |
| 25468 | 21457, |
| 25469 | /* t2LDC_OPTION */ |
| 25470 | 21463, |
| 25471 | /* t2LDC_POST */ |
| 25472 | 21469, |
| 25473 | /* t2LDC_PRE */ |
| 25474 | 21475, |
| 25475 | /* t2LDMDB */ |
| 25476 | 21481, |
| 25477 | /* t2LDMDB_UPD */ |
| 25478 | 21485, |
| 25479 | /* t2LDMIA */ |
| 25480 | 21490, |
| 25481 | /* t2LDMIA_UPD */ |
| 25482 | 21494, |
| 25483 | /* t2LDRBT */ |
| 25484 | 21499, |
| 25485 | /* t2LDRB_POST */ |
| 25486 | 21504, |
| 25487 | /* t2LDRB_PRE */ |
| 25488 | 21510, |
| 25489 | /* t2LDRBi12 */ |
| 25490 | 21516, |
| 25491 | /* t2LDRBi8 */ |
| 25492 | 21521, |
| 25493 | /* t2LDRBpci */ |
| 25494 | 21526, |
| 25495 | /* t2LDRBs */ |
| 25496 | 21530, |
| 25497 | /* t2LDRD_POST */ |
| 25498 | 21536, |
| 25499 | /* t2LDRD_PRE */ |
| 25500 | 21543, |
| 25501 | /* t2LDRDi8 */ |
| 25502 | 21550, |
| 25503 | /* t2LDREX */ |
| 25504 | 21556, |
| 25505 | /* t2LDREXB */ |
| 25506 | 21561, |
| 25507 | /* t2LDREXD */ |
| 25508 | 21565, |
| 25509 | /* t2LDREXH */ |
| 25510 | 21570, |
| 25511 | /* t2LDRHT */ |
| 25512 | 21574, |
| 25513 | /* t2LDRH_POST */ |
| 25514 | 21579, |
| 25515 | /* t2LDRH_PRE */ |
| 25516 | 21585, |
| 25517 | /* t2LDRHi12 */ |
| 25518 | 21591, |
| 25519 | /* t2LDRHi8 */ |
| 25520 | 21596, |
| 25521 | /* t2LDRHpci */ |
| 25522 | 21601, |
| 25523 | /* t2LDRHs */ |
| 25524 | 21605, |
| 25525 | /* t2LDRSBT */ |
| 25526 | 21611, |
| 25527 | /* t2LDRSB_POST */ |
| 25528 | 21616, |
| 25529 | /* t2LDRSB_PRE */ |
| 25530 | 21622, |
| 25531 | /* t2LDRSBi12 */ |
| 25532 | 21628, |
| 25533 | /* t2LDRSBi8 */ |
| 25534 | 21633, |
| 25535 | /* t2LDRSBpci */ |
| 25536 | 21638, |
| 25537 | /* t2LDRSBs */ |
| 25538 | 21642, |
| 25539 | /* t2LDRSHT */ |
| 25540 | 21648, |
| 25541 | /* t2LDRSH_POST */ |
| 25542 | 21653, |
| 25543 | /* t2LDRSH_PRE */ |
| 25544 | 21659, |
| 25545 | /* t2LDRSHi12 */ |
| 25546 | 21665, |
| 25547 | /* t2LDRSHi8 */ |
| 25548 | 21670, |
| 25549 | /* t2LDRSHpci */ |
| 25550 | 21675, |
| 25551 | /* t2LDRSHs */ |
| 25552 | 21679, |
| 25553 | /* t2LDRT */ |
| 25554 | 21685, |
| 25555 | /* t2LDR_POST */ |
| 25556 | 21690, |
| 25557 | /* t2LDR_PRE */ |
| 25558 | 21696, |
| 25559 | /* t2LDRi12 */ |
| 25560 | 21702, |
| 25561 | /* t2LDRi8 */ |
| 25562 | 21707, |
| 25563 | /* t2LDRpci */ |
| 25564 | 21712, |
| 25565 | /* t2LDRs */ |
| 25566 | 21716, |
| 25567 | /* t2LE */ |
| 25568 | 21722, |
| 25569 | /* t2LEUpdate */ |
| 25570 | 21723, |
| 25571 | /* t2LSLri */ |
| 25572 | 21726, |
| 25573 | /* t2LSLrr */ |
| 25574 | 21732, |
| 25575 | /* t2LSRri */ |
| 25576 | 21738, |
| 25577 | /* t2LSRrr */ |
| 25578 | 21744, |
| 25579 | /* t2MCR */ |
| 25580 | 21750, |
| 25581 | /* t2MCR2 */ |
| 25582 | 21758, |
| 25583 | /* t2MCRR */ |
| 25584 | 21766, |
| 25585 | /* t2MCRR2 */ |
| 25586 | 21773, |
| 25587 | /* t2MLA */ |
| 25588 | 21780, |
| 25589 | /* t2MLS */ |
| 25590 | 21786, |
| 25591 | /* t2MOVTi16 */ |
| 25592 | 21792, |
| 25593 | /* t2MOVi */ |
| 25594 | 21797, |
| 25595 | /* t2MOVi16 */ |
| 25596 | 21802, |
| 25597 | /* t2MOVr */ |
| 25598 | 21806, |
| 25599 | /* t2MOVsra_glue */ |
| 25600 | 21811, |
| 25601 | /* t2MOVsrl_glue */ |
| 25602 | 21815, |
| 25603 | /* t2MRC */ |
| 25604 | 21819, |
| 25605 | /* t2MRC2 */ |
| 25606 | 21827, |
| 25607 | /* t2MRRC */ |
| 25608 | 21835, |
| 25609 | /* t2MRRC2 */ |
| 25610 | 21842, |
| 25611 | /* t2MRS_AR */ |
| 25612 | 21849, |
| 25613 | /* t2MRS_M */ |
| 25614 | 21852, |
| 25615 | /* t2MRSbanked */ |
| 25616 | 21856, |
| 25617 | /* t2MRSsys_AR */ |
| 25618 | 21860, |
| 25619 | /* t2MSR_AR */ |
| 25620 | 21863, |
| 25621 | /* t2MSR_M */ |
| 25622 | 21867, |
| 25623 | /* t2MSRbanked */ |
| 25624 | 21871, |
| 25625 | /* t2MUL */ |
| 25626 | 21875, |
| 25627 | /* t2MVNi */ |
| 25628 | 21880, |
| 25629 | /* t2MVNr */ |
| 25630 | 21885, |
| 25631 | /* t2MVNs */ |
| 25632 | 21890, |
| 25633 | /* t2ORNri */ |
| 25634 | 21896, |
| 25635 | /* t2ORNrr */ |
| 25636 | 21902, |
| 25637 | /* t2ORNrs */ |
| 25638 | 21908, |
| 25639 | /* t2ORRri */ |
| 25640 | 21915, |
| 25641 | /* t2ORRrr */ |
| 25642 | 21921, |
| 25643 | /* t2ORRrs */ |
| 25644 | 21927, |
| 25645 | /* t2PAC */ |
| 25646 | 21934, |
| 25647 | /* t2PACBTI */ |
| 25648 | 21934, |
| 25649 | /* t2PACG */ |
| 25650 | 21934, |
| 25651 | /* t2PKHBT */ |
| 25652 | 21939, |
| 25653 | /* t2PKHTB */ |
| 25654 | 21945, |
| 25655 | /* t2PLDWi12 */ |
| 25656 | 21951, |
| 25657 | /* t2PLDWi8 */ |
| 25658 | 21955, |
| 25659 | /* t2PLDWs */ |
| 25660 | 21959, |
| 25661 | /* t2PLDi12 */ |
| 25662 | 21964, |
| 25663 | /* t2PLDi8 */ |
| 25664 | 21968, |
| 25665 | /* t2PLDpci */ |
| 25666 | 21972, |
| 25667 | /* t2PLDs */ |
| 25668 | 21975, |
| 25669 | /* t2PLIi12 */ |
| 25670 | 21980, |
| 25671 | /* t2PLIi8 */ |
| 25672 | 21984, |
| 25673 | /* t2PLIpci */ |
| 25674 | 21988, |
| 25675 | /* t2PLIs */ |
| 25676 | 21991, |
| 25677 | /* t2QADD */ |
| 25678 | 21996, |
| 25679 | /* t2QADD16 */ |
| 25680 | 22001, |
| 25681 | /* t2QADD8 */ |
| 25682 | 22006, |
| 25683 | /* t2QASX */ |
| 25684 | 22011, |
| 25685 | /* t2QDADD */ |
| 25686 | 22016, |
| 25687 | /* t2QDSUB */ |
| 25688 | 22021, |
| 25689 | /* t2QSAX */ |
| 25690 | 22026, |
| 25691 | /* t2QSUB */ |
| 25692 | 22031, |
| 25693 | /* t2QSUB16 */ |
| 25694 | 22036, |
| 25695 | /* t2QSUB8 */ |
| 25696 | 22041, |
| 25697 | /* t2RBIT */ |
| 25698 | 22046, |
| 25699 | /* t2REV */ |
| 25700 | 22050, |
| 25701 | /* t2REV16 */ |
| 25702 | 22054, |
| 25703 | /* t2REVSH */ |
| 25704 | 22058, |
| 25705 | /* t2RFEDB */ |
| 25706 | 22062, |
| 25707 | /* t2RFEDBW */ |
| 25708 | 22065, |
| 25709 | /* t2RFEIA */ |
| 25710 | 22068, |
| 25711 | /* t2RFEIAW */ |
| 25712 | 22071, |
| 25713 | /* t2RORri */ |
| 25714 | 22074, |
| 25715 | /* t2RORrr */ |
| 25716 | 22080, |
| 25717 | /* t2RRX */ |
| 25718 | 22086, |
| 25719 | /* t2RSBri */ |
| 25720 | 22091, |
| 25721 | /* t2RSBrr */ |
| 25722 | 22097, |
| 25723 | /* t2RSBrs */ |
| 25724 | 22103, |
| 25725 | /* t2SADD16 */ |
| 25726 | 22110, |
| 25727 | /* t2SADD8 */ |
| 25728 | 22115, |
| 25729 | /* t2SASX */ |
| 25730 | 22120, |
| 25731 | /* t2SB */ |
| 25732 | 22125, |
| 25733 | /* t2SBCri */ |
| 25734 | 22125, |
| 25735 | /* t2SBCrr */ |
| 25736 | 22131, |
| 25737 | /* t2SBCrs */ |
| 25738 | 22137, |
| 25739 | /* t2SBFX */ |
| 25740 | 22144, |
| 25741 | /* t2SDIV */ |
| 25742 | 22150, |
| 25743 | /* t2SEL */ |
| 25744 | 22155, |
| 25745 | /* t2SETPAN */ |
| 25746 | 22160, |
| 25747 | /* t2SG */ |
| 25748 | 22161, |
| 25749 | /* t2SHADD16 */ |
| 25750 | 22163, |
| 25751 | /* t2SHADD8 */ |
| 25752 | 22168, |
| 25753 | /* t2SHASX */ |
| 25754 | 22173, |
| 25755 | /* t2SHSAX */ |
| 25756 | 22178, |
| 25757 | /* t2SHSUB16 */ |
| 25758 | 22183, |
| 25759 | /* t2SHSUB8 */ |
| 25760 | 22188, |
| 25761 | /* t2SMC */ |
| 25762 | 22193, |
| 25763 | /* t2SMLABB */ |
| 25764 | 22196, |
| 25765 | /* t2SMLABT */ |
| 25766 | 22202, |
| 25767 | /* t2SMLAD */ |
| 25768 | 22208, |
| 25769 | /* t2SMLADX */ |
| 25770 | 22214, |
| 25771 | /* t2SMLAL */ |
| 25772 | 22220, |
| 25773 | /* t2SMLALBB */ |
| 25774 | 22228, |
| 25775 | /* t2SMLALBT */ |
| 25776 | 22236, |
| 25777 | /* t2SMLALD */ |
| 25778 | 22244, |
| 25779 | /* t2SMLALDX */ |
| 25780 | 22252, |
| 25781 | /* t2SMLALTB */ |
| 25782 | 22260, |
| 25783 | /* t2SMLALTT */ |
| 25784 | 22268, |
| 25785 | /* t2SMLATB */ |
| 25786 | 22276, |
| 25787 | /* t2SMLATT */ |
| 25788 | 22282, |
| 25789 | /* t2SMLAWB */ |
| 25790 | 22288, |
| 25791 | /* t2SMLAWT */ |
| 25792 | 22294, |
| 25793 | /* t2SMLSD */ |
| 25794 | 22300, |
| 25795 | /* t2SMLSDX */ |
| 25796 | 22306, |
| 25797 | /* t2SMLSLD */ |
| 25798 | 22312, |
| 25799 | /* t2SMLSLDX */ |
| 25800 | 22320, |
| 25801 | /* t2SMMLA */ |
| 25802 | 22328, |
| 25803 | /* t2SMMLAR */ |
| 25804 | 22334, |
| 25805 | /* t2SMMLS */ |
| 25806 | 22340, |
| 25807 | /* t2SMMLSR */ |
| 25808 | 22346, |
| 25809 | /* t2SMMUL */ |
| 25810 | 22352, |
| 25811 | /* t2SMMULR */ |
| 25812 | 22357, |
| 25813 | /* t2SMUAD */ |
| 25814 | 22362, |
| 25815 | /* t2SMUADX */ |
| 25816 | 22367, |
| 25817 | /* t2SMULBB */ |
| 25818 | 22372, |
| 25819 | /* t2SMULBT */ |
| 25820 | 22377, |
| 25821 | /* t2SMULL */ |
| 25822 | 22382, |
| 25823 | /* t2SMULTB */ |
| 25824 | 22388, |
| 25825 | /* t2SMULTT */ |
| 25826 | 22393, |
| 25827 | /* t2SMULWB */ |
| 25828 | 22398, |
| 25829 | /* t2SMULWT */ |
| 25830 | 22403, |
| 25831 | /* t2SMUSD */ |
| 25832 | 22408, |
| 25833 | /* t2SMUSDX */ |
| 25834 | 22413, |
| 25835 | /* t2SRSDB */ |
| 25836 | 22418, |
| 25837 | /* t2SRSDB_UPD */ |
| 25838 | 22421, |
| 25839 | /* t2SRSIA */ |
| 25840 | 22424, |
| 25841 | /* t2SRSIA_UPD */ |
| 25842 | 22427, |
| 25843 | /* t2SSAT */ |
| 25844 | 22430, |
| 25845 | /* t2SSAT16 */ |
| 25846 | 22436, |
| 25847 | /* t2SSAX */ |
| 25848 | 22441, |
| 25849 | /* t2SSUB16 */ |
| 25850 | 22446, |
| 25851 | /* t2SSUB8 */ |
| 25852 | 22451, |
| 25853 | /* t2STC2L_OFFSET */ |
| 25854 | 22456, |
| 25855 | /* t2STC2L_OPTION */ |
| 25856 | 22462, |
| 25857 | /* t2STC2L_POST */ |
| 25858 | 22468, |
| 25859 | /* t2STC2L_PRE */ |
| 25860 | 22474, |
| 25861 | /* t2STC2_OFFSET */ |
| 25862 | 22480, |
| 25863 | /* t2STC2_OPTION */ |
| 25864 | 22486, |
| 25865 | /* t2STC2_POST */ |
| 25866 | 22492, |
| 25867 | /* t2STC2_PRE */ |
| 25868 | 22498, |
| 25869 | /* t2STCL_OFFSET */ |
| 25870 | 22504, |
| 25871 | /* t2STCL_OPTION */ |
| 25872 | 22510, |
| 25873 | /* t2STCL_POST */ |
| 25874 | 22516, |
| 25875 | /* t2STCL_PRE */ |
| 25876 | 22522, |
| 25877 | /* t2STC_OFFSET */ |
| 25878 | 22528, |
| 25879 | /* t2STC_OPTION */ |
| 25880 | 22534, |
| 25881 | /* t2STC_POST */ |
| 25882 | 22540, |
| 25883 | /* t2STC_PRE */ |
| 25884 | 22546, |
| 25885 | /* t2STL */ |
| 25886 | 22552, |
| 25887 | /* t2STLB */ |
| 25888 | 22556, |
| 25889 | /* t2STLEX */ |
| 25890 | 22560, |
| 25891 | /* t2STLEXB */ |
| 25892 | 22565, |
| 25893 | /* t2STLEXD */ |
| 25894 | 22570, |
| 25895 | /* t2STLEXH */ |
| 25896 | 22576, |
| 25897 | /* t2STLH */ |
| 25898 | 22581, |
| 25899 | /* t2STMDB */ |
| 25900 | 22585, |
| 25901 | /* t2STMDB_UPD */ |
| 25902 | 22589, |
| 25903 | /* t2STMIA */ |
| 25904 | 22594, |
| 25905 | /* t2STMIA_UPD */ |
| 25906 | 22598, |
| 25907 | /* t2STRBT */ |
| 25908 | 22603, |
| 25909 | /* t2STRB_POST */ |
| 25910 | 22608, |
| 25911 | /* t2STRB_PRE */ |
| 25912 | 22614, |
| 25913 | /* t2STRBi12 */ |
| 25914 | 22620, |
| 25915 | /* t2STRBi8 */ |
| 25916 | 22625, |
| 25917 | /* t2STRBs */ |
| 25918 | 22630, |
| 25919 | /* t2STRD_POST */ |
| 25920 | 22636, |
| 25921 | /* t2STRD_PRE */ |
| 25922 | 22643, |
| 25923 | /* t2STRDi8 */ |
| 25924 | 22650, |
| 25925 | /* t2STREX */ |
| 25926 | 22656, |
| 25927 | /* t2STREXB */ |
| 25928 | 22662, |
| 25929 | /* t2STREXD */ |
| 25930 | 22667, |
| 25931 | /* t2STREXH */ |
| 25932 | 22673, |
| 25933 | /* t2STRHT */ |
| 25934 | 22678, |
| 25935 | /* t2STRH_POST */ |
| 25936 | 22683, |
| 25937 | /* t2STRH_PRE */ |
| 25938 | 22689, |
| 25939 | /* t2STRHi12 */ |
| 25940 | 22695, |
| 25941 | /* t2STRHi8 */ |
| 25942 | 22700, |
| 25943 | /* t2STRHs */ |
| 25944 | 22705, |
| 25945 | /* t2STRT */ |
| 25946 | 22711, |
| 25947 | /* t2STR_POST */ |
| 25948 | 22716, |
| 25949 | /* t2STR_PRE */ |
| 25950 | 22722, |
| 25951 | /* t2STRi12 */ |
| 25952 | 22728, |
| 25953 | /* t2STRi8 */ |
| 25954 | 22733, |
| 25955 | /* t2STRs */ |
| 25956 | 22738, |
| 25957 | /* t2SUBS_PC_LR */ |
| 25958 | 22744, |
| 25959 | /* t2SUBri */ |
| 25960 | 22747, |
| 25961 | /* t2SUBri12 */ |
| 25962 | 22753, |
| 25963 | /* t2SUBrr */ |
| 25964 | 22758, |
| 25965 | /* t2SUBrs */ |
| 25966 | 22764, |
| 25967 | /* t2SUBspImm */ |
| 25968 | 22771, |
| 25969 | /* t2SUBspImm12 */ |
| 25970 | 22777, |
| 25971 | /* t2SXTAB */ |
| 25972 | 22782, |
| 25973 | /* t2SXTAB16 */ |
| 25974 | 22788, |
| 25975 | /* t2SXTAH */ |
| 25976 | 22794, |
| 25977 | /* t2SXTB */ |
| 25978 | 22800, |
| 25979 | /* t2SXTB16 */ |
| 25980 | 22805, |
| 25981 | /* t2SXTH */ |
| 25982 | 22810, |
| 25983 | /* t2TBB */ |
| 25984 | 22815, |
| 25985 | /* t2TBH */ |
| 25986 | 22819, |
| 25987 | /* t2TEQri */ |
| 25988 | 22823, |
| 25989 | /* t2TEQrr */ |
| 25990 | 22827, |
| 25991 | /* t2TEQrs */ |
| 25992 | 22831, |
| 25993 | /* t2TSB */ |
| 25994 | 22836, |
| 25995 | /* t2TSTri */ |
| 25996 | 22839, |
| 25997 | /* t2TSTrr */ |
| 25998 | 22843, |
| 25999 | /* t2TSTrs */ |
| 26000 | 22847, |
| 26001 | /* t2TT */ |
| 26002 | 22852, |
| 26003 | /* t2TTA */ |
| 26004 | 22856, |
| 26005 | /* t2TTAT */ |
| 26006 | 22860, |
| 26007 | /* t2TTT */ |
| 26008 | 22864, |
| 26009 | /* t2UADD16 */ |
| 26010 | 22868, |
| 26011 | /* t2UADD8 */ |
| 26012 | 22873, |
| 26013 | /* t2UASX */ |
| 26014 | 22878, |
| 26015 | /* t2UBFX */ |
| 26016 | 22883, |
| 26017 | /* t2UDF */ |
| 26018 | 22889, |
| 26019 | /* t2UDIV */ |
| 26020 | 22890, |
| 26021 | /* t2UHADD16 */ |
| 26022 | 22895, |
| 26023 | /* t2UHADD8 */ |
| 26024 | 22900, |
| 26025 | /* t2UHASX */ |
| 26026 | 22905, |
| 26027 | /* t2UHSAX */ |
| 26028 | 22910, |
| 26029 | /* t2UHSUB16 */ |
| 26030 | 22915, |
| 26031 | /* t2UHSUB8 */ |
| 26032 | 22920, |
| 26033 | /* t2UMAAL */ |
| 26034 | 22925, |
| 26035 | /* t2UMLAL */ |
| 26036 | 22933, |
| 26037 | /* t2UMULL */ |
| 26038 | 22941, |
| 26039 | /* t2UQADD16 */ |
| 26040 | 22947, |
| 26041 | /* t2UQADD8 */ |
| 26042 | 22952, |
| 26043 | /* t2UQASX */ |
| 26044 | 22957, |
| 26045 | /* t2UQSAX */ |
| 26046 | 22962, |
| 26047 | /* t2UQSUB16 */ |
| 26048 | 22967, |
| 26049 | /* t2UQSUB8 */ |
| 26050 | 22972, |
| 26051 | /* t2USAD8 */ |
| 26052 | 22977, |
| 26053 | /* t2USADA8 */ |
| 26054 | 22982, |
| 26055 | /* t2USAT */ |
| 26056 | 22988, |
| 26057 | /* t2USAT16 */ |
| 26058 | 22994, |
| 26059 | /* t2USAX */ |
| 26060 | 22999, |
| 26061 | /* t2USUB16 */ |
| 26062 | 23004, |
| 26063 | /* t2USUB8 */ |
| 26064 | 23009, |
| 26065 | /* t2UXTAB */ |
| 26066 | 23014, |
| 26067 | /* t2UXTAB16 */ |
| 26068 | 23020, |
| 26069 | /* t2UXTAH */ |
| 26070 | 23026, |
| 26071 | /* t2UXTB */ |
| 26072 | 23032, |
| 26073 | /* t2UXTB16 */ |
| 26074 | 23037, |
| 26075 | /* t2UXTH */ |
| 26076 | 23042, |
| 26077 | /* t2WLS */ |
| 26078 | 23047, |
| 26079 | /* tADC */ |
| 26080 | 23050, |
| 26081 | /* tADDhirr */ |
| 26082 | 23056, |
| 26083 | /* tADDi3 */ |
| 26084 | 23061, |
| 26085 | /* tADDi8 */ |
| 26086 | 23067, |
| 26087 | /* tADDrSP */ |
| 26088 | 23073, |
| 26089 | /* tADDrSPi */ |
| 26090 | 23078, |
| 26091 | /* tADDrr */ |
| 26092 | 23083, |
| 26093 | /* tADDspi */ |
| 26094 | 23089, |
| 26095 | /* tADDspr */ |
| 26096 | 23094, |
| 26097 | /* tADR */ |
| 26098 | 23099, |
| 26099 | /* tAND */ |
| 26100 | 23103, |
| 26101 | /* tASRri */ |
| 26102 | 23109, |
| 26103 | /* tASRrr */ |
| 26104 | 23115, |
| 26105 | /* tB */ |
| 26106 | 23121, |
| 26107 | /* tBIC */ |
| 26108 | 23124, |
| 26109 | /* tBKPT */ |
| 26110 | 23130, |
| 26111 | /* tBL */ |
| 26112 | 23131, |
| 26113 | /* tBLXNSr */ |
| 26114 | 23134, |
| 26115 | /* tBLXi */ |
| 26116 | 23137, |
| 26117 | /* tBLXr */ |
| 26118 | 23140, |
| 26119 | /* tBX */ |
| 26120 | 23143, |
| 26121 | /* tBXNS */ |
| 26122 | 23146, |
| 26123 | /* tBcc */ |
| 26124 | 23149, |
| 26125 | /* tCBNZ */ |
| 26126 | 23152, |
| 26127 | /* tCBZ */ |
| 26128 | 23154, |
| 26129 | /* tCMNz */ |
| 26130 | 23156, |
| 26131 | /* tCMPhir */ |
| 26132 | 23160, |
| 26133 | /* tCMPi8 */ |
| 26134 | 23164, |
| 26135 | /* tCMPr */ |
| 26136 | 23168, |
| 26137 | /* tCPS */ |
| 26138 | 23172, |
| 26139 | /* tEOR */ |
| 26140 | 23174, |
| 26141 | /* tHINT */ |
| 26142 | 23180, |
| 26143 | /* tHLT */ |
| 26144 | 23183, |
| 26145 | /* tInt_WIN_eh_sjlj_longjmp */ |
| 26146 | 23184, |
| 26147 | /* tInt_eh_sjlj_longjmp */ |
| 26148 | 23186, |
| 26149 | /* tInt_eh_sjlj_setjmp */ |
| 26150 | 23188, |
| 26151 | /* tLDMIA */ |
| 26152 | 23190, |
| 26153 | /* tLDRBi */ |
| 26154 | 23194, |
| 26155 | /* tLDRBr */ |
| 26156 | 23199, |
| 26157 | /* tLDRHi */ |
| 26158 | 23204, |
| 26159 | /* tLDRHr */ |
| 26160 | 23209, |
| 26161 | /* tLDRSB */ |
| 26162 | 23214, |
| 26163 | /* tLDRSH */ |
| 26164 | 23219, |
| 26165 | /* tLDRi */ |
| 26166 | 23224, |
| 26167 | /* tLDRpci */ |
| 26168 | 23229, |
| 26169 | /* tLDRr */ |
| 26170 | 23233, |
| 26171 | /* tLDRspi */ |
| 26172 | 23238, |
| 26173 | /* tLSLri */ |
| 26174 | 23243, |
| 26175 | /* tLSLrr */ |
| 26176 | 23249, |
| 26177 | /* tLSRri */ |
| 26178 | 23255, |
| 26179 | /* tLSRrr */ |
| 26180 | 23261, |
| 26181 | /* tMOVSr */ |
| 26182 | 23267, |
| 26183 | /* tMOVi8 */ |
| 26184 | 23269, |
| 26185 | /* tMOVr */ |
| 26186 | 23274, |
| 26187 | /* tMUL */ |
| 26188 | 23278, |
| 26189 | /* tMVN */ |
| 26190 | 23284, |
| 26191 | /* tORR */ |
| 26192 | 23289, |
| 26193 | /* tPICADD */ |
| 26194 | 23295, |
| 26195 | /* tPOP */ |
| 26196 | 23298, |
| 26197 | /* tPUSH */ |
| 26198 | 23301, |
| 26199 | /* tREV */ |
| 26200 | 23304, |
| 26201 | /* tREV16 */ |
| 26202 | 23308, |
| 26203 | /* tREVSH */ |
| 26204 | 23312, |
| 26205 | /* tROR */ |
| 26206 | 23316, |
| 26207 | /* tRSB */ |
| 26208 | 23322, |
| 26209 | /* tSBC */ |
| 26210 | 23327, |
| 26211 | /* tSETEND */ |
| 26212 | 23333, |
| 26213 | /* tSTMIA_UPD */ |
| 26214 | 23334, |
| 26215 | /* tSTRBi */ |
| 26216 | 23339, |
| 26217 | /* tSTRBr */ |
| 26218 | 23344, |
| 26219 | /* tSTRHi */ |
| 26220 | 23349, |
| 26221 | /* tSTRHr */ |
| 26222 | 23354, |
| 26223 | /* tSTRi */ |
| 26224 | 23359, |
| 26225 | /* tSTRr */ |
| 26226 | 23364, |
| 26227 | /* tSTRspi */ |
| 26228 | 23369, |
| 26229 | /* tSUBi3 */ |
| 26230 | 23374, |
| 26231 | /* tSUBi8 */ |
| 26232 | 23380, |
| 26233 | /* tSUBrr */ |
| 26234 | 23386, |
| 26235 | /* tSUBspi */ |
| 26236 | 23392, |
| 26237 | /* tSVC */ |
| 26238 | 23397, |
| 26239 | /* tSXTB */ |
| 26240 | 23400, |
| 26241 | /* tSXTH */ |
| 26242 | 23404, |
| 26243 | /* tTRAP */ |
| 26244 | 23408, |
| 26245 | /* tTST */ |
| 26246 | 23408, |
| 26247 | /* tUDF */ |
| 26248 | 23412, |
| 26249 | /* tUXTB */ |
| 26250 | 23413, |
| 26251 | /* tUXTH */ |
| 26252 | 23417, |
| 26253 | /* t__brkdiv0 */ |
| 26254 | 23421, |
| 26255 | }; |
| 26256 | |
| 26257 | using namespace OpTypes; |
| 26258 | static const int16_t OpcodeOperandTypes[] = { |
| 26259 | |
| 26260 | /* PHI */ |
| 26261 | -1, |
| 26262 | /* INLINEASM */ |
| 26263 | /* INLINEASM_BR */ |
| 26264 | /* CFI_INSTRUCTION */ |
| 26265 | i32imm, |
| 26266 | /* EH_LABEL */ |
| 26267 | i32imm, |
| 26268 | /* GC_LABEL */ |
| 26269 | i32imm, |
| 26270 | /* ANNOTATION_LABEL */ |
| 26271 | i32imm, |
| 26272 | /* KILL */ |
| 26273 | /* EXTRACT_SUBREG */ |
| 26274 | -1, -1, i32imm, |
| 26275 | /* INSERT_SUBREG */ |
| 26276 | -1, -1, -1, i32imm, |
| 26277 | /* IMPLICIT_DEF */ |
| 26278 | -1, |
| 26279 | /* SUBREG_TO_REG */ |
| 26280 | -1, -1, -1, i32imm, |
| 26281 | /* COPY_TO_REGCLASS */ |
| 26282 | -1, -1, i32imm, |
| 26283 | /* DBG_VALUE */ |
| 26284 | /* DBG_VALUE_LIST */ |
| 26285 | /* DBG_INSTR_REF */ |
| 26286 | /* DBG_PHI */ |
| 26287 | /* DBG_LABEL */ |
| 26288 | -1, |
| 26289 | /* REG_SEQUENCE */ |
| 26290 | -1, -1, |
| 26291 | /* COPY */ |
| 26292 | -1, -1, |
| 26293 | /* BUNDLE */ |
| 26294 | /* LIFETIME_START */ |
| 26295 | i32imm, |
| 26296 | /* LIFETIME_END */ |
| 26297 | i32imm, |
| 26298 | /* PSEUDO_PROBE */ |
| 26299 | i64imm, i64imm, i8imm, i32imm, |
| 26300 | /* ARITH_FENCE */ |
| 26301 | -1, -1, |
| 26302 | /* STACKMAP */ |
| 26303 | i64imm, i32imm, |
| 26304 | /* FENTRY_CALL */ |
| 26305 | /* PATCHPOINT */ |
| 26306 | -1, i64imm, i32imm, -1, i32imm, i32imm, |
| 26307 | /* LOAD_STACK_GUARD */ |
| 26308 | -1, |
| 26309 | /* PREALLOCATED_SETUP */ |
| 26310 | i32imm, |
| 26311 | /* PREALLOCATED_ARG */ |
| 26312 | -1, i32imm, i32imm, |
| 26313 | /* STATEPOINT */ |
| 26314 | /* LOCAL_ESCAPE */ |
| 26315 | -1, i32imm, |
| 26316 | /* FAULTING_OP */ |
| 26317 | -1, |
| 26318 | /* PATCHABLE_OP */ |
| 26319 | /* PATCHABLE_FUNCTION_ENTER */ |
| 26320 | /* PATCHABLE_RET */ |
| 26321 | /* PATCHABLE_FUNCTION_EXIT */ |
| 26322 | /* PATCHABLE_TAIL_CALL */ |
| 26323 | /* PATCHABLE_EVENT_CALL */ |
| 26324 | -1, -1, |
| 26325 | /* PATCHABLE_TYPED_EVENT_CALL */ |
| 26326 | -1, -1, -1, |
| 26327 | /* ICALL_BRANCH_FUNNEL */ |
| 26328 | /* MEMBARRIER */ |
| 26329 | /* JUMP_TABLE_DEBUG_INFO */ |
| 26330 | i64imm, |
| 26331 | /* CONVERGENCECTRL_ENTRY */ |
| 26332 | -1, |
| 26333 | /* CONVERGENCECTRL_ANCHOR */ |
| 26334 | -1, |
| 26335 | /* CONVERGENCECTRL_LOOP */ |
| 26336 | -1, -1, |
| 26337 | /* CONVERGENCECTRL_GLUE */ |
| 26338 | -1, |
| 26339 | /* G_ASSERT_SEXT */ |
| 26340 | type0, type0, untyped_imm_0, |
| 26341 | /* G_ASSERT_ZEXT */ |
| 26342 | type0, type0, untyped_imm_0, |
| 26343 | /* G_ASSERT_ALIGN */ |
| 26344 | type0, type0, untyped_imm_0, |
| 26345 | /* G_ADD */ |
| 26346 | type0, type0, type0, |
| 26347 | /* G_SUB */ |
| 26348 | type0, type0, type0, |
| 26349 | /* G_MUL */ |
| 26350 | type0, type0, type0, |
| 26351 | /* G_SDIV */ |
| 26352 | type0, type0, type0, |
| 26353 | /* G_UDIV */ |
| 26354 | type0, type0, type0, |
| 26355 | /* G_SREM */ |
| 26356 | type0, type0, type0, |
| 26357 | /* G_UREM */ |
| 26358 | type0, type0, type0, |
| 26359 | /* G_SDIVREM */ |
| 26360 | type0, type0, type0, type0, |
| 26361 | /* G_UDIVREM */ |
| 26362 | type0, type0, type0, type0, |
| 26363 | /* G_AND */ |
| 26364 | type0, type0, type0, |
| 26365 | /* G_OR */ |
| 26366 | type0, type0, type0, |
| 26367 | /* G_XOR */ |
| 26368 | type0, type0, type0, |
| 26369 | /* G_IMPLICIT_DEF */ |
| 26370 | type0, |
| 26371 | /* G_PHI */ |
| 26372 | type0, |
| 26373 | /* G_FRAME_INDEX */ |
| 26374 | type0, -1, |
| 26375 | /* G_GLOBAL_VALUE */ |
| 26376 | type0, -1, |
| 26377 | /* G_PTRAUTH_GLOBAL_VALUE */ |
| 26378 | type0, -1, i32imm, type1, i64imm, |
| 26379 | /* G_CONSTANT_POOL */ |
| 26380 | type0, -1, |
| 26381 | /* G_EXTRACT */ |
| 26382 | type0, type1, untyped_imm_0, |
| 26383 | /* G_UNMERGE_VALUES */ |
| 26384 | type0, type1, |
| 26385 | /* G_INSERT */ |
| 26386 | type0, type0, type1, untyped_imm_0, |
| 26387 | /* G_MERGE_VALUES */ |
| 26388 | type0, type1, |
| 26389 | /* G_BUILD_VECTOR */ |
| 26390 | type0, type1, |
| 26391 | /* G_BUILD_VECTOR_TRUNC */ |
| 26392 | type0, type1, |
| 26393 | /* G_CONCAT_VECTORS */ |
| 26394 | type0, type1, |
| 26395 | /* G_PTRTOINT */ |
| 26396 | type0, type1, |
| 26397 | /* G_INTTOPTR */ |
| 26398 | type0, type1, |
| 26399 | /* G_BITCAST */ |
| 26400 | type0, type1, |
| 26401 | /* G_FREEZE */ |
| 26402 | type0, type0, |
| 26403 | /* G_CONSTANT_FOLD_BARRIER */ |
| 26404 | type0, type0, |
| 26405 | /* G_INTRINSIC_FPTRUNC_ROUND */ |
| 26406 | type0, type1, i32imm, |
| 26407 | /* G_INTRINSIC_TRUNC */ |
| 26408 | type0, type0, |
| 26409 | /* G_INTRINSIC_ROUND */ |
| 26410 | type0, type0, |
| 26411 | /* G_INTRINSIC_LRINT */ |
| 26412 | type0, type1, |
| 26413 | /* G_INTRINSIC_LLRINT */ |
| 26414 | type0, type1, |
| 26415 | /* G_INTRINSIC_ROUNDEVEN */ |
| 26416 | type0, type0, |
| 26417 | /* G_READCYCLECOUNTER */ |
| 26418 | type0, |
| 26419 | /* G_READSTEADYCOUNTER */ |
| 26420 | type0, |
| 26421 | /* G_LOAD */ |
| 26422 | type0, ptype1, |
| 26423 | /* G_SEXTLOAD */ |
| 26424 | type0, ptype1, |
| 26425 | /* G_ZEXTLOAD */ |
| 26426 | type0, ptype1, |
| 26427 | /* G_INDEXED_LOAD */ |
| 26428 | type0, ptype1, ptype1, type2, -1, |
| 26429 | /* G_INDEXED_SEXTLOAD */ |
| 26430 | type0, ptype1, ptype1, type2, -1, |
| 26431 | /* G_INDEXED_ZEXTLOAD */ |
| 26432 | type0, ptype1, ptype1, type2, -1, |
| 26433 | /* G_STORE */ |
| 26434 | type0, ptype1, |
| 26435 | /* G_INDEXED_STORE */ |
| 26436 | ptype0, type1, ptype0, ptype2, -1, |
| 26437 | /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ |
| 26438 | type0, type1, type2, type0, type0, |
| 26439 | /* G_ATOMIC_CMPXCHG */ |
| 26440 | type0, ptype1, type0, type0, |
| 26441 | /* G_ATOMICRMW_XCHG */ |
| 26442 | type0, ptype1, type0, |
| 26443 | /* G_ATOMICRMW_ADD */ |
| 26444 | type0, ptype1, type0, |
| 26445 | /* G_ATOMICRMW_SUB */ |
| 26446 | type0, ptype1, type0, |
| 26447 | /* G_ATOMICRMW_AND */ |
| 26448 | type0, ptype1, type0, |
| 26449 | /* G_ATOMICRMW_NAND */ |
| 26450 | type0, ptype1, type0, |
| 26451 | /* G_ATOMICRMW_OR */ |
| 26452 | type0, ptype1, type0, |
| 26453 | /* G_ATOMICRMW_XOR */ |
| 26454 | type0, ptype1, type0, |
| 26455 | /* G_ATOMICRMW_MAX */ |
| 26456 | type0, ptype1, type0, |
| 26457 | /* G_ATOMICRMW_MIN */ |
| 26458 | type0, ptype1, type0, |
| 26459 | /* G_ATOMICRMW_UMAX */ |
| 26460 | type0, ptype1, type0, |
| 26461 | /* G_ATOMICRMW_UMIN */ |
| 26462 | type0, ptype1, type0, |
| 26463 | /* G_ATOMICRMW_FADD */ |
| 26464 | type0, ptype1, type0, |
| 26465 | /* G_ATOMICRMW_FSUB */ |
| 26466 | type0, ptype1, type0, |
| 26467 | /* G_ATOMICRMW_FMAX */ |
| 26468 | type0, ptype1, type0, |
| 26469 | /* G_ATOMICRMW_FMIN */ |
| 26470 | type0, ptype1, type0, |
| 26471 | /* G_ATOMICRMW_UINC_WRAP */ |
| 26472 | type0, ptype1, type0, |
| 26473 | /* G_ATOMICRMW_UDEC_WRAP */ |
| 26474 | type0, ptype1, type0, |
| 26475 | /* G_FENCE */ |
| 26476 | i32imm, i32imm, |
| 26477 | /* G_PREFETCH */ |
| 26478 | ptype0, i32imm, i32imm, i32imm, |
| 26479 | /* G_BRCOND */ |
| 26480 | type0, -1, |
| 26481 | /* G_BRINDIRECT */ |
| 26482 | type0, |
| 26483 | /* G_INVOKE_REGION_START */ |
| 26484 | /* G_INTRINSIC */ |
| 26485 | -1, |
| 26486 | /* G_INTRINSIC_W_SIDE_EFFECTS */ |
| 26487 | -1, |
| 26488 | /* G_INTRINSIC_CONVERGENT */ |
| 26489 | -1, |
| 26490 | /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ |
| 26491 | -1, |
| 26492 | /* G_ANYEXT */ |
| 26493 | type0, type1, |
| 26494 | /* G_TRUNC */ |
| 26495 | type0, type1, |
| 26496 | /* G_CONSTANT */ |
| 26497 | type0, -1, |
| 26498 | /* G_FCONSTANT */ |
| 26499 | type0, -1, |
| 26500 | /* G_VASTART */ |
| 26501 | type0, |
| 26502 | /* G_VAARG */ |
| 26503 | type0, type1, -1, |
| 26504 | /* G_SEXT */ |
| 26505 | type0, type1, |
| 26506 | /* G_SEXT_INREG */ |
| 26507 | type0, type0, untyped_imm_0, |
| 26508 | /* G_ZEXT */ |
| 26509 | type0, type1, |
| 26510 | /* G_SHL */ |
| 26511 | type0, type0, type1, |
| 26512 | /* G_LSHR */ |
| 26513 | type0, type0, type1, |
| 26514 | /* G_ASHR */ |
| 26515 | type0, type0, type1, |
| 26516 | /* G_FSHL */ |
| 26517 | type0, type0, type0, type1, |
| 26518 | /* G_FSHR */ |
| 26519 | type0, type0, type0, type1, |
| 26520 | /* G_ROTR */ |
| 26521 | type0, type0, type1, |
| 26522 | /* G_ROTL */ |
| 26523 | type0, type0, type1, |
| 26524 | /* G_ICMP */ |
| 26525 | type0, -1, type1, type1, |
| 26526 | /* G_FCMP */ |
| 26527 | type0, -1, type1, type1, |
| 26528 | /* G_SCMP */ |
| 26529 | type0, type1, type1, |
| 26530 | /* G_UCMP */ |
| 26531 | type0, type1, type1, |
| 26532 | /* G_SELECT */ |
| 26533 | type0, type1, type0, type0, |
| 26534 | /* G_UADDO */ |
| 26535 | type0, type1, type0, type0, |
| 26536 | /* G_UADDE */ |
| 26537 | type0, type1, type0, type0, type1, |
| 26538 | /* G_USUBO */ |
| 26539 | type0, type1, type0, type0, |
| 26540 | /* G_USUBE */ |
| 26541 | type0, type1, type0, type0, type1, |
| 26542 | /* G_SADDO */ |
| 26543 | type0, type1, type0, type0, |
| 26544 | /* G_SADDE */ |
| 26545 | type0, type1, type0, type0, type1, |
| 26546 | /* G_SSUBO */ |
| 26547 | type0, type1, type0, type0, |
| 26548 | /* G_SSUBE */ |
| 26549 | type0, type1, type0, type0, type1, |
| 26550 | /* G_UMULO */ |
| 26551 | type0, type1, type0, type0, |
| 26552 | /* G_SMULO */ |
| 26553 | type0, type1, type0, type0, |
| 26554 | /* G_UMULH */ |
| 26555 | type0, type0, type0, |
| 26556 | /* G_SMULH */ |
| 26557 | type0, type0, type0, |
| 26558 | /* G_UADDSAT */ |
| 26559 | type0, type0, type0, |
| 26560 | /* G_SADDSAT */ |
| 26561 | type0, type0, type0, |
| 26562 | /* G_USUBSAT */ |
| 26563 | type0, type0, type0, |
| 26564 | /* G_SSUBSAT */ |
| 26565 | type0, type0, type0, |
| 26566 | /* G_USHLSAT */ |
| 26567 | type0, type0, type1, |
| 26568 | /* G_SSHLSAT */ |
| 26569 | type0, type0, type1, |
| 26570 | /* G_SMULFIX */ |
| 26571 | type0, type0, type0, untyped_imm_0, |
| 26572 | /* G_UMULFIX */ |
| 26573 | type0, type0, type0, untyped_imm_0, |
| 26574 | /* G_SMULFIXSAT */ |
| 26575 | type0, type0, type0, untyped_imm_0, |
| 26576 | /* G_UMULFIXSAT */ |
| 26577 | type0, type0, type0, untyped_imm_0, |
| 26578 | /* G_SDIVFIX */ |
| 26579 | type0, type0, type0, untyped_imm_0, |
| 26580 | /* G_UDIVFIX */ |
| 26581 | type0, type0, type0, untyped_imm_0, |
| 26582 | /* G_SDIVFIXSAT */ |
| 26583 | type0, type0, type0, untyped_imm_0, |
| 26584 | /* G_UDIVFIXSAT */ |
| 26585 | type0, type0, type0, untyped_imm_0, |
| 26586 | /* G_FADD */ |
| 26587 | type0, type0, type0, |
| 26588 | /* G_FSUB */ |
| 26589 | type0, type0, type0, |
| 26590 | /* G_FMUL */ |
| 26591 | type0, type0, type0, |
| 26592 | /* G_FMA */ |
| 26593 | type0, type0, type0, type0, |
| 26594 | /* G_FMAD */ |
| 26595 | type0, type0, type0, type0, |
| 26596 | /* G_FDIV */ |
| 26597 | type0, type0, type0, |
| 26598 | /* G_FREM */ |
| 26599 | type0, type0, type0, |
| 26600 | /* G_FPOW */ |
| 26601 | type0, type0, type0, |
| 26602 | /* G_FPOWI */ |
| 26603 | type0, type0, type1, |
| 26604 | /* G_FEXP */ |
| 26605 | type0, type0, |
| 26606 | /* G_FEXP2 */ |
| 26607 | type0, type0, |
| 26608 | /* G_FEXP10 */ |
| 26609 | type0, type0, |
| 26610 | /* G_FLOG */ |
| 26611 | type0, type0, |
| 26612 | /* G_FLOG2 */ |
| 26613 | type0, type0, |
| 26614 | /* G_FLOG10 */ |
| 26615 | type0, type0, |
| 26616 | /* G_FLDEXP */ |
| 26617 | type0, type0, type1, |
| 26618 | /* G_FFREXP */ |
| 26619 | type0, type1, type0, |
| 26620 | /* G_FNEG */ |
| 26621 | type0, type0, |
| 26622 | /* G_FPEXT */ |
| 26623 | type0, type1, |
| 26624 | /* G_FPTRUNC */ |
| 26625 | type0, type1, |
| 26626 | /* G_FPTOSI */ |
| 26627 | type0, type1, |
| 26628 | /* G_FPTOUI */ |
| 26629 | type0, type1, |
| 26630 | /* G_SITOFP */ |
| 26631 | type0, type1, |
| 26632 | /* G_UITOFP */ |
| 26633 | type0, type1, |
| 26634 | /* G_FABS */ |
| 26635 | type0, type0, |
| 26636 | /* G_FCOPYSIGN */ |
| 26637 | type0, type0, type1, |
| 26638 | /* G_IS_FPCLASS */ |
| 26639 | type0, type1, -1, |
| 26640 | /* G_FCANONICALIZE */ |
| 26641 | type0, type0, |
| 26642 | /* G_FMINNUM */ |
| 26643 | type0, type0, type0, |
| 26644 | /* G_FMAXNUM */ |
| 26645 | type0, type0, type0, |
| 26646 | /* G_FMINNUM_IEEE */ |
| 26647 | type0, type0, type0, |
| 26648 | /* G_FMAXNUM_IEEE */ |
| 26649 | type0, type0, type0, |
| 26650 | /* G_FMINIMUM */ |
| 26651 | type0, type0, type0, |
| 26652 | /* G_FMAXIMUM */ |
| 26653 | type0, type0, type0, |
| 26654 | /* G_GET_FPENV */ |
| 26655 | type0, |
| 26656 | /* G_SET_FPENV */ |
| 26657 | type0, |
| 26658 | /* G_RESET_FPENV */ |
| 26659 | /* G_GET_FPMODE */ |
| 26660 | type0, |
| 26661 | /* G_SET_FPMODE */ |
| 26662 | type0, |
| 26663 | /* G_RESET_FPMODE */ |
| 26664 | /* G_PTR_ADD */ |
| 26665 | ptype0, ptype0, type1, |
| 26666 | /* G_PTRMASK */ |
| 26667 | ptype0, ptype0, type1, |
| 26668 | /* G_SMIN */ |
| 26669 | type0, type0, type0, |
| 26670 | /* G_SMAX */ |
| 26671 | type0, type0, type0, |
| 26672 | /* G_UMIN */ |
| 26673 | type0, type0, type0, |
| 26674 | /* G_UMAX */ |
| 26675 | type0, type0, type0, |
| 26676 | /* G_ABS */ |
| 26677 | type0, type0, |
| 26678 | /* G_LROUND */ |
| 26679 | type0, type1, |
| 26680 | /* G_LLROUND */ |
| 26681 | type0, type1, |
| 26682 | /* G_BR */ |
| 26683 | -1, |
| 26684 | /* G_BRJT */ |
| 26685 | ptype0, -1, type1, |
| 26686 | /* G_VSCALE */ |
| 26687 | type0, -1, |
| 26688 | /* G_INSERT_SUBVECTOR */ |
| 26689 | type0, type0, type1, untyped_imm_0, |
| 26690 | /* G_EXTRACT_SUBVECTOR */ |
| 26691 | type0, type0, untyped_imm_0, |
| 26692 | /* G_INSERT_VECTOR_ELT */ |
| 26693 | type0, type0, type1, type2, |
| 26694 | /* G_EXTRACT_VECTOR_ELT */ |
| 26695 | type0, type1, type2, |
| 26696 | /* G_SHUFFLE_VECTOR */ |
| 26697 | type0, type1, type1, -1, |
| 26698 | /* G_SPLAT_VECTOR */ |
| 26699 | type0, type1, |
| 26700 | /* G_VECTOR_COMPRESS */ |
| 26701 | type0, type0, type1, type0, |
| 26702 | /* G_CTTZ */ |
| 26703 | type0, type1, |
| 26704 | /* G_CTTZ_ZERO_UNDEF */ |
| 26705 | type0, type1, |
| 26706 | /* G_CTLZ */ |
| 26707 | type0, type1, |
| 26708 | /* G_CTLZ_ZERO_UNDEF */ |
| 26709 | type0, type1, |
| 26710 | /* G_CTPOP */ |
| 26711 | type0, type1, |
| 26712 | /* G_BSWAP */ |
| 26713 | type0, type0, |
| 26714 | /* G_BITREVERSE */ |
| 26715 | type0, type0, |
| 26716 | /* G_FCEIL */ |
| 26717 | type0, type0, |
| 26718 | /* G_FCOS */ |
| 26719 | type0, type0, |
| 26720 | /* G_FSIN */ |
| 26721 | type0, type0, |
| 26722 | /* G_FTAN */ |
| 26723 | type0, type0, |
| 26724 | /* G_FACOS */ |
| 26725 | type0, type0, |
| 26726 | /* G_FASIN */ |
| 26727 | type0, type0, |
| 26728 | /* G_FATAN */ |
| 26729 | type0, type0, |
| 26730 | /* G_FCOSH */ |
| 26731 | type0, type0, |
| 26732 | /* G_FSINH */ |
| 26733 | type0, type0, |
| 26734 | /* G_FTANH */ |
| 26735 | type0, type0, |
| 26736 | /* G_FSQRT */ |
| 26737 | type0, type0, |
| 26738 | /* G_FFLOOR */ |
| 26739 | type0, type0, |
| 26740 | /* G_FRINT */ |
| 26741 | type0, type0, |
| 26742 | /* G_FNEARBYINT */ |
| 26743 | type0, type0, |
| 26744 | /* G_ADDRSPACE_CAST */ |
| 26745 | type0, type1, |
| 26746 | /* G_BLOCK_ADDR */ |
| 26747 | type0, -1, |
| 26748 | /* G_JUMP_TABLE */ |
| 26749 | type0, -1, |
| 26750 | /* G_DYN_STACKALLOC */ |
| 26751 | ptype0, type1, i32imm, |
| 26752 | /* G_STACKSAVE */ |
| 26753 | ptype0, |
| 26754 | /* G_STACKRESTORE */ |
| 26755 | ptype0, |
| 26756 | /* G_STRICT_FADD */ |
| 26757 | type0, type0, type0, |
| 26758 | /* G_STRICT_FSUB */ |
| 26759 | type0, type0, type0, |
| 26760 | /* G_STRICT_FMUL */ |
| 26761 | type0, type0, type0, |
| 26762 | /* G_STRICT_FDIV */ |
| 26763 | type0, type0, type0, |
| 26764 | /* G_STRICT_FREM */ |
| 26765 | type0, type0, type0, |
| 26766 | /* G_STRICT_FMA */ |
| 26767 | type0, type0, type0, type0, |
| 26768 | /* G_STRICT_FSQRT */ |
| 26769 | type0, type0, |
| 26770 | /* G_STRICT_FLDEXP */ |
| 26771 | type0, type0, type1, |
| 26772 | /* G_READ_REGISTER */ |
| 26773 | type0, -1, |
| 26774 | /* G_WRITE_REGISTER */ |
| 26775 | -1, type0, |
| 26776 | /* G_MEMCPY */ |
| 26777 | ptype0, ptype1, type2, untyped_imm_0, |
| 26778 | /* G_MEMCPY_INLINE */ |
| 26779 | ptype0, ptype1, type2, |
| 26780 | /* G_MEMMOVE */ |
| 26781 | ptype0, ptype1, type2, untyped_imm_0, |
| 26782 | /* G_MEMSET */ |
| 26783 | ptype0, type1, type2, untyped_imm_0, |
| 26784 | /* G_BZERO */ |
| 26785 | ptype0, type1, untyped_imm_0, |
| 26786 | /* G_TRAP */ |
| 26787 | /* G_DEBUGTRAP */ |
| 26788 | /* G_UBSANTRAP */ |
| 26789 | i8imm, |
| 26790 | /* G_VECREDUCE_SEQ_FADD */ |
| 26791 | type0, type1, type2, |
| 26792 | /* G_VECREDUCE_SEQ_FMUL */ |
| 26793 | type0, type1, type2, |
| 26794 | /* G_VECREDUCE_FADD */ |
| 26795 | type0, type1, |
| 26796 | /* G_VECREDUCE_FMUL */ |
| 26797 | type0, type1, |
| 26798 | /* G_VECREDUCE_FMAX */ |
| 26799 | type0, type1, |
| 26800 | /* G_VECREDUCE_FMIN */ |
| 26801 | type0, type1, |
| 26802 | /* G_VECREDUCE_FMAXIMUM */ |
| 26803 | type0, type1, |
| 26804 | /* G_VECREDUCE_FMINIMUM */ |
| 26805 | type0, type1, |
| 26806 | /* G_VECREDUCE_ADD */ |
| 26807 | type0, type1, |
| 26808 | /* G_VECREDUCE_MUL */ |
| 26809 | type0, type1, |
| 26810 | /* G_VECREDUCE_AND */ |
| 26811 | type0, type1, |
| 26812 | /* G_VECREDUCE_OR */ |
| 26813 | type0, type1, |
| 26814 | /* G_VECREDUCE_XOR */ |
| 26815 | type0, type1, |
| 26816 | /* G_VECREDUCE_SMAX */ |
| 26817 | type0, type1, |
| 26818 | /* G_VECREDUCE_SMIN */ |
| 26819 | type0, type1, |
| 26820 | /* G_VECREDUCE_UMAX */ |
| 26821 | type0, type1, |
| 26822 | /* G_VECREDUCE_UMIN */ |
| 26823 | type0, type1, |
| 26824 | /* G_SBFX */ |
| 26825 | type0, type0, type1, type1, |
| 26826 | /* G_UBFX */ |
| 26827 | type0, type0, type1, type1, |
| 26828 | /* ABS */ |
| 26829 | GPR, GPR, |
| 26830 | /* ADDSri */ |
| 26831 | GPR, GPR, mod_imm, i32imm, i32imm, |
| 26832 | /* ADDSrr */ |
| 26833 | GPR, GPR, GPR, i32imm, i32imm, |
| 26834 | /* ADDSrsi */ |
| 26835 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 26836 | /* ADDSrsr */ |
| 26837 | GPR, GPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 26838 | /* ADJCALLSTACKDOWN */ |
| 26839 | i32imm, i32imm, i32imm, i32imm, |
| 26840 | /* ADJCALLSTACKUP */ |
| 26841 | i32imm, i32imm, i32imm, i32imm, |
| 26842 | /* ASRi */ |
| 26843 | GPR, GPR, imm0_32, i32imm, i32imm, CCR, |
| 26844 | /* ASRr */ |
| 26845 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, CCR, |
| 26846 | /* B */ |
| 26847 | arm_br_target, |
| 26848 | /* BCCZi64 */ |
| 26849 | i32imm, GPR, GPR, brtarget, |
| 26850 | /* BCCi64 */ |
| 26851 | i32imm, GPR, GPR, GPR, GPR, brtarget, |
| 26852 | /* BLX_noip */ |
| 26853 | GPRnoip, |
| 26854 | /* BLX_pred_noip */ |
| 26855 | GPRnoip, |
| 26856 | /* BL_PUSHLR */ |
| 26857 | GPRlr, arm_bl_target, |
| 26858 | /* BMOVPCB_CALL */ |
| 26859 | arm_bl_target, |
| 26860 | /* BMOVPCRX_CALL */ |
| 26861 | tGPR, |
| 26862 | /* BR_JTadd */ |
| 26863 | GPR, GPR, i32imm, |
| 26864 | /* BR_JTm_i12 */ |
| 26865 | GPR, i32imm, i32imm, |
| 26866 | /* BR_JTm_rs */ |
| 26867 | GPR, GPRnopc, i32imm, i32imm, |
| 26868 | /* BR_JTr */ |
| 26869 | GPR, i32imm, |
| 26870 | /* BX_CALL */ |
| 26871 | tGPR, |
| 26872 | /* CMP_SWAP_16 */ |
| 26873 | GPR, GPR, GPR, GPR, GPR, |
| 26874 | /* CMP_SWAP_32 */ |
| 26875 | GPR, GPR, GPR, GPR, GPR, |
| 26876 | /* CMP_SWAP_64 */ |
| 26877 | GPRPair, GPR, GPR, GPRPair, GPRPair, |
| 26878 | /* CMP_SWAP_8 */ |
| 26879 | GPR, GPR, GPR, GPR, GPR, |
| 26880 | /* CONSTPOOL_ENTRY */ |
| 26881 | cpinst_operand, cpinst_operand, i32imm, |
| 26882 | /* COPY_STRUCT_BYVAL_I32 */ |
| 26883 | GPR, GPR, i32imm, i32imm, |
| 26884 | /* ITasm */ |
| 26885 | it_pred, it_mask, |
| 26886 | /* Int_eh_sjlj_dispatchsetup */ |
| 26887 | /* Int_eh_sjlj_longjmp */ |
| 26888 | GPR, GPR, |
| 26889 | /* Int_eh_sjlj_setjmp */ |
| 26890 | GPR, GPR, |
| 26891 | /* Int_eh_sjlj_setjmp_nofp */ |
| 26892 | GPR, GPR, |
| 26893 | /* Int_eh_sjlj_setup_dispatch */ |
| 26894 | /* JUMPTABLE_ADDRS */ |
| 26895 | cpinst_operand, cpinst_operand, i32imm, |
| 26896 | /* JUMPTABLE_INSTS */ |
| 26897 | cpinst_operand, cpinst_operand, i32imm, |
| 26898 | /* JUMPTABLE_TBB */ |
| 26899 | cpinst_operand, cpinst_operand, i32imm, |
| 26900 | /* JUMPTABLE_TBH */ |
| 26901 | cpinst_operand, cpinst_operand, i32imm, |
| 26902 | /* LDMIA_RET */ |
| 26903 | GPR, GPR, i32imm, i32imm, reglist, |
| 26904 | /* LDRBT_POST */ |
| 26905 | GPR, GPR, i32imm, i32imm, |
| 26906 | /* LDRConstPool */ |
| 26907 | GPR, const_pool_asm_imm, i32imm, i32imm, |
| 26908 | /* LDRHTii */ |
| 26909 | GPR, GPR, i32imm, i32imm, |
| 26910 | /* LDRLIT_ga_abs */ |
| 26911 | GPR, i32imm, |
| 26912 | /* LDRLIT_ga_pcrel */ |
| 26913 | GPR, i32imm, |
| 26914 | /* LDRLIT_ga_pcrel_ldr */ |
| 26915 | GPR, i32imm, |
| 26916 | /* LDRSBTii */ |
| 26917 | GPR, GPR, i32imm, i32imm, |
| 26918 | /* LDRSHTii */ |
| 26919 | GPR, GPR, i32imm, i32imm, |
| 26920 | /* LDRT_POST */ |
| 26921 | GPR, GPR, i32imm, i32imm, |
| 26922 | /* LEApcrel */ |
| 26923 | GPR, i32imm, i32imm, i32imm, |
| 26924 | /* LEApcrelJT */ |
| 26925 | GPR, i32imm, i32imm, i32imm, |
| 26926 | /* LOADDUAL */ |
| 26927 | GPRPairOp, GPR, GPR, i32imm, |
| 26928 | /* LSLi */ |
| 26929 | GPR, GPR, imm0_31, i32imm, i32imm, CCR, |
| 26930 | /* LSLr */ |
| 26931 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, CCR, |
| 26932 | /* LSRi */ |
| 26933 | GPR, GPR, imm0_32, i32imm, i32imm, CCR, |
| 26934 | /* LSRr */ |
| 26935 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, CCR, |
| 26936 | /* MEMCPY */ |
| 26937 | GPR, GPR, GPR, GPR, i32imm, |
| 26938 | /* MLAv5 */ |
| 26939 | GPRnopc, GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, CCR, |
| 26940 | /* MOVCCi */ |
| 26941 | GPR, GPR, mod_imm, i32imm, i32imm, |
| 26942 | /* MOVCCi16 */ |
| 26943 | GPR, GPR, imm0_65535_expr, i32imm, i32imm, |
| 26944 | /* MOVCCi32imm */ |
| 26945 | GPR, GPR, i32imm, i32imm, i32imm, |
| 26946 | /* MOVCCr */ |
| 26947 | GPR, GPR, GPR, i32imm, i32imm, |
| 26948 | /* MOVCCsi */ |
| 26949 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 26950 | /* MOVCCsr */ |
| 26951 | GPR, GPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 26952 | /* MOVPCRX */ |
| 26953 | GPR, |
| 26954 | /* MOVTi16_ga_pcrel */ |
| 26955 | GPR, GPR, i32imm, pclabel, |
| 26956 | /* MOV_ga_pcrel */ |
| 26957 | GPR, i32imm, |
| 26958 | /* MOV_ga_pcrel_ldr */ |
| 26959 | GPR, i32imm, |
| 26960 | /* MOVi16_ga_pcrel */ |
| 26961 | GPR, i32imm, pclabel, |
| 26962 | /* MOVi32imm */ |
| 26963 | GPR, i32imm, |
| 26964 | /* MOVsra_glue */ |
| 26965 | GPR, GPR, |
| 26966 | /* MOVsrl_glue */ |
| 26967 | GPR, GPR, |
| 26968 | /* MQPRCopy */ |
| 26969 | MQPR, MQPR, |
| 26970 | /* MQQPRLoad */ |
| 26971 | MQQPR, GPRnopc, |
| 26972 | /* MQQPRStore */ |
| 26973 | MQQPR, GPRnopc, |
| 26974 | /* MQQQQPRLoad */ |
| 26975 | MQQQQPR, GPRnopc, |
| 26976 | /* MQQQQPRStore */ |
| 26977 | MQQQQPR, GPRnopc, |
| 26978 | /* MULv5 */ |
| 26979 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, CCR, |
| 26980 | /* MVE_MEMCPYLOOPINST */ |
| 26981 | rGPR, rGPR, rGPR, |
| 26982 | /* MVE_MEMSETLOOPINST */ |
| 26983 | rGPR, MQPR, rGPR, |
| 26984 | /* MVNCCi */ |
| 26985 | GPR, GPR, mod_imm, i32imm, i32imm, |
| 26986 | /* PICADD */ |
| 26987 | GPR, GPR, pclabel, i32imm, i32imm, |
| 26988 | /* PICLDR */ |
| 26989 | GPR, GPR, i32imm, i32imm, i32imm, |
| 26990 | /* PICLDRB */ |
| 26991 | GPR, GPR, i32imm, i32imm, i32imm, |
| 26992 | /* PICLDRH */ |
| 26993 | GPR, GPR, i32imm, i32imm, i32imm, |
| 26994 | /* PICLDRSB */ |
| 26995 | GPR, GPR, i32imm, i32imm, i32imm, |
| 26996 | /* PICLDRSH */ |
| 26997 | GPR, GPR, i32imm, i32imm, i32imm, |
| 26998 | /* PICSTR */ |
| 26999 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27000 | /* PICSTRB */ |
| 27001 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27002 | /* PICSTRH */ |
| 27003 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27004 | /* PseudoARMInitUndefDPR_VFP2 */ |
| 27005 | DPR_VFP2, |
| 27006 | /* PseudoARMInitUndefGPR */ |
| 27007 | GPR, |
| 27008 | /* PseudoARMInitUndefMQPR */ |
| 27009 | MQPR, |
| 27010 | /* PseudoARMInitUndefSPR */ |
| 27011 | SPR, |
| 27012 | /* RORi */ |
| 27013 | GPR, GPR, imm0_31, i32imm, i32imm, CCR, |
| 27014 | /* RORr */ |
| 27015 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, CCR, |
| 27016 | /* RRX */ |
| 27017 | GPR, GPR, |
| 27018 | /* RRXi */ |
| 27019 | GPR, GPR, i32imm, i32imm, CCR, |
| 27020 | /* RSBSri */ |
| 27021 | GPR, GPR, mod_imm, i32imm, i32imm, |
| 27022 | /* RSBSrsi */ |
| 27023 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 27024 | /* RSBSrsr */ |
| 27025 | GPR, GPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 27026 | /* SEH_EpilogEnd */ |
| 27027 | /* SEH_EpilogStart */ |
| 27028 | /* SEH_Nop */ |
| 27029 | i32imm, |
| 27030 | /* SEH_Nop_Ret */ |
| 27031 | i32imm, |
| 27032 | /* SEH_PrologEnd */ |
| 27033 | /* SEH_SaveFRegs */ |
| 27034 | i32imm, i32imm, |
| 27035 | /* SEH_SaveLR */ |
| 27036 | i32imm, |
| 27037 | /* SEH_SaveRegs */ |
| 27038 | i32imm, i32imm, |
| 27039 | /* SEH_SaveRegs_Ret */ |
| 27040 | i32imm, i32imm, |
| 27041 | /* SEH_SaveSP */ |
| 27042 | i32imm, |
| 27043 | /* SEH_StackAlloc */ |
| 27044 | i32imm, i32imm, |
| 27045 | /* SMLALv5 */ |
| 27046 | GPR, GPR, GPR, GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 27047 | /* SMULLv5 */ |
| 27048 | GPR, GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 27049 | /* SPACE */ |
| 27050 | GPR, i32imm, GPR, |
| 27051 | /* STOREDUAL */ |
| 27052 | GPRPairOp, GPR, GPR, i32imm, |
| 27053 | /* STRBT_POST */ |
| 27054 | GPR, GPR, i32imm, i32imm, |
| 27055 | /* STRBi_preidx */ |
| 27056 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 27057 | /* STRBr_preidx */ |
| 27058 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 27059 | /* STRH_preidx */ |
| 27060 | GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 27061 | /* STRT_POST */ |
| 27062 | GPR, GPR, i32imm, i32imm, |
| 27063 | /* STRi_preidx */ |
| 27064 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 27065 | /* STRr_preidx */ |
| 27066 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 27067 | /* SUBS_PC_LR */ |
| 27068 | i32imm, i32imm, i32imm, |
| 27069 | /* SUBSri */ |
| 27070 | GPR, GPR, mod_imm, i32imm, i32imm, |
| 27071 | /* SUBSrr */ |
| 27072 | GPR, GPR, GPR, i32imm, i32imm, |
| 27073 | /* SUBSrsi */ |
| 27074 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 27075 | /* SUBSrsr */ |
| 27076 | GPR, GPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 27077 | /* SpeculationBarrierISBDSBEndBB */ |
| 27078 | /* SpeculationBarrierSBEndBB */ |
| 27079 | /* TAILJMPd */ |
| 27080 | arm_br_target, |
| 27081 | /* TAILJMPr */ |
| 27082 | tcGPR, |
| 27083 | /* TAILJMPr4 */ |
| 27084 | GPR, |
| 27085 | /* TCRETURNdi */ |
| 27086 | i32imm, i32imm, |
| 27087 | /* TCRETURNri */ |
| 27088 | tcGPR, i32imm, |
| 27089 | /* TCRETURNrinotr12 */ |
| 27090 | tcGPRnotr12, i32imm, |
| 27091 | /* TPsoft */ |
| 27092 | /* UMLALv5 */ |
| 27093 | GPR, GPR, GPR, GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 27094 | /* UMULLv5 */ |
| 27095 | GPR, GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 27096 | /* VLD1LNdAsm_16 */ |
| 27097 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27098 | /* VLD1LNdAsm_32 */ |
| 27099 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27100 | /* VLD1LNdAsm_8 */ |
| 27101 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27102 | /* VLD1LNdWB_fixed_Asm_16 */ |
| 27103 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27104 | /* VLD1LNdWB_fixed_Asm_32 */ |
| 27105 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27106 | /* VLD1LNdWB_fixed_Asm_8 */ |
| 27107 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27108 | /* VLD1LNdWB_register_Asm_16 */ |
| 27109 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27110 | /* VLD1LNdWB_register_Asm_32 */ |
| 27111 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27112 | /* VLD1LNdWB_register_Asm_8 */ |
| 27113 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27114 | /* VLD2LNdAsm_16 */ |
| 27115 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27116 | /* VLD2LNdAsm_32 */ |
| 27117 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27118 | /* VLD2LNdAsm_8 */ |
| 27119 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27120 | /* VLD2LNdWB_fixed_Asm_16 */ |
| 27121 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27122 | /* VLD2LNdWB_fixed_Asm_32 */ |
| 27123 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27124 | /* VLD2LNdWB_fixed_Asm_8 */ |
| 27125 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27126 | /* VLD2LNdWB_register_Asm_16 */ |
| 27127 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27128 | /* VLD2LNdWB_register_Asm_32 */ |
| 27129 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27130 | /* VLD2LNdWB_register_Asm_8 */ |
| 27131 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27132 | /* VLD2LNqAsm_16 */ |
| 27133 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27134 | /* VLD2LNqAsm_32 */ |
| 27135 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27136 | /* VLD2LNqWB_fixed_Asm_16 */ |
| 27137 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27138 | /* VLD2LNqWB_fixed_Asm_32 */ |
| 27139 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27140 | /* VLD2LNqWB_register_Asm_16 */ |
| 27141 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27142 | /* VLD2LNqWB_register_Asm_32 */ |
| 27143 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27144 | /* VLD3DUPdAsm_16 */ |
| 27145 | VecListThreeDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27146 | /* VLD3DUPdAsm_32 */ |
| 27147 | VecListThreeDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27148 | /* VLD3DUPdAsm_8 */ |
| 27149 | VecListThreeDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27150 | /* VLD3DUPdWB_fixed_Asm_16 */ |
| 27151 | VecListThreeDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27152 | /* VLD3DUPdWB_fixed_Asm_32 */ |
| 27153 | VecListThreeDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27154 | /* VLD3DUPdWB_fixed_Asm_8 */ |
| 27155 | VecListThreeDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27156 | /* VLD3DUPdWB_register_Asm_16 */ |
| 27157 | VecListThreeDAllLanes, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27158 | /* VLD3DUPdWB_register_Asm_32 */ |
| 27159 | VecListThreeDAllLanes, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27160 | /* VLD3DUPdWB_register_Asm_8 */ |
| 27161 | VecListThreeDAllLanes, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27162 | /* VLD3DUPqAsm_16 */ |
| 27163 | VecListThreeQAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27164 | /* VLD3DUPqAsm_32 */ |
| 27165 | VecListThreeQAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27166 | /* VLD3DUPqAsm_8 */ |
| 27167 | VecListThreeQAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27168 | /* VLD3DUPqWB_fixed_Asm_16 */ |
| 27169 | VecListThreeQAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27170 | /* VLD3DUPqWB_fixed_Asm_32 */ |
| 27171 | VecListThreeQAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27172 | /* VLD3DUPqWB_fixed_Asm_8 */ |
| 27173 | VecListThreeQAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27174 | /* VLD3DUPqWB_register_Asm_16 */ |
| 27175 | VecListThreeQAllLanes, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27176 | /* VLD3DUPqWB_register_Asm_32 */ |
| 27177 | VecListThreeQAllLanes, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27178 | /* VLD3DUPqWB_register_Asm_8 */ |
| 27179 | VecListThreeQAllLanes, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27180 | /* VLD3LNdAsm_16 */ |
| 27181 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27182 | /* VLD3LNdAsm_32 */ |
| 27183 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27184 | /* VLD3LNdAsm_8 */ |
| 27185 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27186 | /* VLD3LNdWB_fixed_Asm_16 */ |
| 27187 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27188 | /* VLD3LNdWB_fixed_Asm_32 */ |
| 27189 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27190 | /* VLD3LNdWB_fixed_Asm_8 */ |
| 27191 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27192 | /* VLD3LNdWB_register_Asm_16 */ |
| 27193 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27194 | /* VLD3LNdWB_register_Asm_32 */ |
| 27195 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27196 | /* VLD3LNdWB_register_Asm_8 */ |
| 27197 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27198 | /* VLD3LNqAsm_16 */ |
| 27199 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27200 | /* VLD3LNqAsm_32 */ |
| 27201 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27202 | /* VLD3LNqWB_fixed_Asm_16 */ |
| 27203 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27204 | /* VLD3LNqWB_fixed_Asm_32 */ |
| 27205 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27206 | /* VLD3LNqWB_register_Asm_16 */ |
| 27207 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27208 | /* VLD3LNqWB_register_Asm_32 */ |
| 27209 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27210 | /* VLD3dAsm_16 */ |
| 27211 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 27212 | /* VLD3dAsm_32 */ |
| 27213 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 27214 | /* VLD3dAsm_8 */ |
| 27215 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 27216 | /* VLD3dWB_fixed_Asm_16 */ |
| 27217 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 27218 | /* VLD3dWB_fixed_Asm_32 */ |
| 27219 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 27220 | /* VLD3dWB_fixed_Asm_8 */ |
| 27221 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 27222 | /* VLD3dWB_register_Asm_16 */ |
| 27223 | VecListThreeD, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27224 | /* VLD3dWB_register_Asm_32 */ |
| 27225 | VecListThreeD, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27226 | /* VLD3dWB_register_Asm_8 */ |
| 27227 | VecListThreeD, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27228 | /* VLD3qAsm_16 */ |
| 27229 | VecListThreeQ, GPR, i32imm, i32imm, i32imm, |
| 27230 | /* VLD3qAsm_32 */ |
| 27231 | VecListThreeQ, GPR, i32imm, i32imm, i32imm, |
| 27232 | /* VLD3qAsm_8 */ |
| 27233 | VecListThreeQ, GPR, i32imm, i32imm, i32imm, |
| 27234 | /* VLD3qWB_fixed_Asm_16 */ |
| 27235 | VecListThreeQ, GPR, i32imm, i32imm, i32imm, |
| 27236 | /* VLD3qWB_fixed_Asm_32 */ |
| 27237 | VecListThreeQ, GPR, i32imm, i32imm, i32imm, |
| 27238 | /* VLD3qWB_fixed_Asm_8 */ |
| 27239 | VecListThreeQ, GPR, i32imm, i32imm, i32imm, |
| 27240 | /* VLD3qWB_register_Asm_16 */ |
| 27241 | VecListThreeQ, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27242 | /* VLD3qWB_register_Asm_32 */ |
| 27243 | VecListThreeQ, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27244 | /* VLD3qWB_register_Asm_8 */ |
| 27245 | VecListThreeQ, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27246 | /* VLD4DUPdAsm_16 */ |
| 27247 | VecListFourDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27248 | /* VLD4DUPdAsm_32 */ |
| 27249 | VecListFourDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27250 | /* VLD4DUPdAsm_8 */ |
| 27251 | VecListFourDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27252 | /* VLD4DUPdWB_fixed_Asm_16 */ |
| 27253 | VecListFourDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27254 | /* VLD4DUPdWB_fixed_Asm_32 */ |
| 27255 | VecListFourDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27256 | /* VLD4DUPdWB_fixed_Asm_8 */ |
| 27257 | VecListFourDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27258 | /* VLD4DUPdWB_register_Asm_16 */ |
| 27259 | VecListFourDAllLanes, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27260 | /* VLD4DUPdWB_register_Asm_32 */ |
| 27261 | VecListFourDAllLanes, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27262 | /* VLD4DUPdWB_register_Asm_8 */ |
| 27263 | VecListFourDAllLanes, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27264 | /* VLD4DUPqAsm_16 */ |
| 27265 | VecListFourQAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27266 | /* VLD4DUPqAsm_32 */ |
| 27267 | VecListFourQAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27268 | /* VLD4DUPqAsm_8 */ |
| 27269 | VecListFourQAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27270 | /* VLD4DUPqWB_fixed_Asm_16 */ |
| 27271 | VecListFourQAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27272 | /* VLD4DUPqWB_fixed_Asm_32 */ |
| 27273 | VecListFourQAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27274 | /* VLD4DUPqWB_fixed_Asm_8 */ |
| 27275 | VecListFourQAllLanes, GPR, i32imm, i32imm, i32imm, |
| 27276 | /* VLD4DUPqWB_register_Asm_16 */ |
| 27277 | VecListFourQAllLanes, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27278 | /* VLD4DUPqWB_register_Asm_32 */ |
| 27279 | VecListFourQAllLanes, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27280 | /* VLD4DUPqWB_register_Asm_8 */ |
| 27281 | VecListFourQAllLanes, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27282 | /* VLD4LNdAsm_16 */ |
| 27283 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27284 | /* VLD4LNdAsm_32 */ |
| 27285 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27286 | /* VLD4LNdAsm_8 */ |
| 27287 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27288 | /* VLD4LNdWB_fixed_Asm_16 */ |
| 27289 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27290 | /* VLD4LNdWB_fixed_Asm_32 */ |
| 27291 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27292 | /* VLD4LNdWB_fixed_Asm_8 */ |
| 27293 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27294 | /* VLD4LNdWB_register_Asm_16 */ |
| 27295 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27296 | /* VLD4LNdWB_register_Asm_32 */ |
| 27297 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27298 | /* VLD4LNdWB_register_Asm_8 */ |
| 27299 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27300 | /* VLD4LNqAsm_16 */ |
| 27301 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27302 | /* VLD4LNqAsm_32 */ |
| 27303 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27304 | /* VLD4LNqWB_fixed_Asm_16 */ |
| 27305 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27306 | /* VLD4LNqWB_fixed_Asm_32 */ |
| 27307 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27308 | /* VLD4LNqWB_register_Asm_16 */ |
| 27309 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27310 | /* VLD4LNqWB_register_Asm_32 */ |
| 27311 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27312 | /* VLD4dAsm_16 */ |
| 27313 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 27314 | /* VLD4dAsm_32 */ |
| 27315 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 27316 | /* VLD4dAsm_8 */ |
| 27317 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 27318 | /* VLD4dWB_fixed_Asm_16 */ |
| 27319 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 27320 | /* VLD4dWB_fixed_Asm_32 */ |
| 27321 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 27322 | /* VLD4dWB_fixed_Asm_8 */ |
| 27323 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 27324 | /* VLD4dWB_register_Asm_16 */ |
| 27325 | VecListFourD, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27326 | /* VLD4dWB_register_Asm_32 */ |
| 27327 | VecListFourD, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27328 | /* VLD4dWB_register_Asm_8 */ |
| 27329 | VecListFourD, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27330 | /* VLD4qAsm_16 */ |
| 27331 | VecListFourQ, GPR, i32imm, i32imm, i32imm, |
| 27332 | /* VLD4qAsm_32 */ |
| 27333 | VecListFourQ, GPR, i32imm, i32imm, i32imm, |
| 27334 | /* VLD4qAsm_8 */ |
| 27335 | VecListFourQ, GPR, i32imm, i32imm, i32imm, |
| 27336 | /* VLD4qWB_fixed_Asm_16 */ |
| 27337 | VecListFourQ, GPR, i32imm, i32imm, i32imm, |
| 27338 | /* VLD4qWB_fixed_Asm_32 */ |
| 27339 | VecListFourQ, GPR, i32imm, i32imm, i32imm, |
| 27340 | /* VLD4qWB_fixed_Asm_8 */ |
| 27341 | VecListFourQ, GPR, i32imm, i32imm, i32imm, |
| 27342 | /* VLD4qWB_register_Asm_16 */ |
| 27343 | VecListFourQ, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27344 | /* VLD4qWB_register_Asm_32 */ |
| 27345 | VecListFourQ, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27346 | /* VLD4qWB_register_Asm_8 */ |
| 27347 | VecListFourQ, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27348 | /* VMOVD0 */ |
| 27349 | DPR, |
| 27350 | /* VMOVDcc */ |
| 27351 | DPR, DPR, DPR, i32imm, i32imm, |
| 27352 | /* VMOVHcc */ |
| 27353 | HPR, HPR, HPR, i32imm, i32imm, |
| 27354 | /* VMOVQ0 */ |
| 27355 | QPR, |
| 27356 | /* VMOVScc */ |
| 27357 | SPR, SPR, SPR, i32imm, i32imm, |
| 27358 | /* VST1LNdAsm_16 */ |
| 27359 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27360 | /* VST1LNdAsm_32 */ |
| 27361 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27362 | /* VST1LNdAsm_8 */ |
| 27363 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27364 | /* VST1LNdWB_fixed_Asm_16 */ |
| 27365 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27366 | /* VST1LNdWB_fixed_Asm_32 */ |
| 27367 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27368 | /* VST1LNdWB_fixed_Asm_8 */ |
| 27369 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27370 | /* VST1LNdWB_register_Asm_16 */ |
| 27371 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27372 | /* VST1LNdWB_register_Asm_32 */ |
| 27373 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27374 | /* VST1LNdWB_register_Asm_8 */ |
| 27375 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27376 | /* VST2LNdAsm_16 */ |
| 27377 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27378 | /* VST2LNdAsm_32 */ |
| 27379 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27380 | /* VST2LNdAsm_8 */ |
| 27381 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27382 | /* VST2LNdWB_fixed_Asm_16 */ |
| 27383 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27384 | /* VST2LNdWB_fixed_Asm_32 */ |
| 27385 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27386 | /* VST2LNdWB_fixed_Asm_8 */ |
| 27387 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27388 | /* VST2LNdWB_register_Asm_16 */ |
| 27389 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27390 | /* VST2LNdWB_register_Asm_32 */ |
| 27391 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27392 | /* VST2LNdWB_register_Asm_8 */ |
| 27393 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27394 | /* VST2LNqAsm_16 */ |
| 27395 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27396 | /* VST2LNqAsm_32 */ |
| 27397 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27398 | /* VST2LNqWB_fixed_Asm_16 */ |
| 27399 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27400 | /* VST2LNqWB_fixed_Asm_32 */ |
| 27401 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27402 | /* VST2LNqWB_register_Asm_16 */ |
| 27403 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27404 | /* VST2LNqWB_register_Asm_32 */ |
| 27405 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27406 | /* VST3LNdAsm_16 */ |
| 27407 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27408 | /* VST3LNdAsm_32 */ |
| 27409 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27410 | /* VST3LNdAsm_8 */ |
| 27411 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27412 | /* VST3LNdWB_fixed_Asm_16 */ |
| 27413 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27414 | /* VST3LNdWB_fixed_Asm_32 */ |
| 27415 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27416 | /* VST3LNdWB_fixed_Asm_8 */ |
| 27417 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27418 | /* VST3LNdWB_register_Asm_16 */ |
| 27419 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27420 | /* VST3LNdWB_register_Asm_32 */ |
| 27421 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27422 | /* VST3LNdWB_register_Asm_8 */ |
| 27423 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27424 | /* VST3LNqAsm_16 */ |
| 27425 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27426 | /* VST3LNqAsm_32 */ |
| 27427 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27428 | /* VST3LNqWB_fixed_Asm_16 */ |
| 27429 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27430 | /* VST3LNqWB_fixed_Asm_32 */ |
| 27431 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27432 | /* VST3LNqWB_register_Asm_16 */ |
| 27433 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27434 | /* VST3LNqWB_register_Asm_32 */ |
| 27435 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27436 | /* VST3dAsm_16 */ |
| 27437 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 27438 | /* VST3dAsm_32 */ |
| 27439 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 27440 | /* VST3dAsm_8 */ |
| 27441 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 27442 | /* VST3dWB_fixed_Asm_16 */ |
| 27443 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 27444 | /* VST3dWB_fixed_Asm_32 */ |
| 27445 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 27446 | /* VST3dWB_fixed_Asm_8 */ |
| 27447 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 27448 | /* VST3dWB_register_Asm_16 */ |
| 27449 | VecListThreeD, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27450 | /* VST3dWB_register_Asm_32 */ |
| 27451 | VecListThreeD, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27452 | /* VST3dWB_register_Asm_8 */ |
| 27453 | VecListThreeD, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27454 | /* VST3qAsm_16 */ |
| 27455 | VecListThreeQ, GPR, i32imm, i32imm, i32imm, |
| 27456 | /* VST3qAsm_32 */ |
| 27457 | VecListThreeQ, GPR, i32imm, i32imm, i32imm, |
| 27458 | /* VST3qAsm_8 */ |
| 27459 | VecListThreeQ, GPR, i32imm, i32imm, i32imm, |
| 27460 | /* VST3qWB_fixed_Asm_16 */ |
| 27461 | VecListThreeQ, GPR, i32imm, i32imm, i32imm, |
| 27462 | /* VST3qWB_fixed_Asm_32 */ |
| 27463 | VecListThreeQ, GPR, i32imm, i32imm, i32imm, |
| 27464 | /* VST3qWB_fixed_Asm_8 */ |
| 27465 | VecListThreeQ, GPR, i32imm, i32imm, i32imm, |
| 27466 | /* VST3qWB_register_Asm_16 */ |
| 27467 | VecListThreeQ, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27468 | /* VST3qWB_register_Asm_32 */ |
| 27469 | VecListThreeQ, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27470 | /* VST3qWB_register_Asm_8 */ |
| 27471 | VecListThreeQ, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27472 | /* VST4LNdAsm_16 */ |
| 27473 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27474 | /* VST4LNdAsm_32 */ |
| 27475 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27476 | /* VST4LNdAsm_8 */ |
| 27477 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27478 | /* VST4LNdWB_fixed_Asm_16 */ |
| 27479 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27480 | /* VST4LNdWB_fixed_Asm_32 */ |
| 27481 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27482 | /* VST4LNdWB_fixed_Asm_8 */ |
| 27483 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27484 | /* VST4LNdWB_register_Asm_16 */ |
| 27485 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27486 | /* VST4LNdWB_register_Asm_32 */ |
| 27487 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27488 | /* VST4LNdWB_register_Asm_8 */ |
| 27489 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27490 | /* VST4LNqAsm_16 */ |
| 27491 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27492 | /* VST4LNqAsm_32 */ |
| 27493 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27494 | /* VST4LNqWB_fixed_Asm_16 */ |
| 27495 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27496 | /* VST4LNqWB_fixed_Asm_32 */ |
| 27497 | DPR, i32imm, GPR, i32imm, i32imm, i32imm, |
| 27498 | /* VST4LNqWB_register_Asm_16 */ |
| 27499 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27500 | /* VST4LNqWB_register_Asm_32 */ |
| 27501 | DPR, i32imm, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27502 | /* VST4dAsm_16 */ |
| 27503 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 27504 | /* VST4dAsm_32 */ |
| 27505 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 27506 | /* VST4dAsm_8 */ |
| 27507 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 27508 | /* VST4dWB_fixed_Asm_16 */ |
| 27509 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 27510 | /* VST4dWB_fixed_Asm_32 */ |
| 27511 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 27512 | /* VST4dWB_fixed_Asm_8 */ |
| 27513 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 27514 | /* VST4dWB_register_Asm_16 */ |
| 27515 | VecListFourD, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27516 | /* VST4dWB_register_Asm_32 */ |
| 27517 | VecListFourD, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27518 | /* VST4dWB_register_Asm_8 */ |
| 27519 | VecListFourD, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27520 | /* VST4qAsm_16 */ |
| 27521 | VecListFourQ, GPR, i32imm, i32imm, i32imm, |
| 27522 | /* VST4qAsm_32 */ |
| 27523 | VecListFourQ, GPR, i32imm, i32imm, i32imm, |
| 27524 | /* VST4qAsm_8 */ |
| 27525 | VecListFourQ, GPR, i32imm, i32imm, i32imm, |
| 27526 | /* VST4qWB_fixed_Asm_16 */ |
| 27527 | VecListFourQ, GPR, i32imm, i32imm, i32imm, |
| 27528 | /* VST4qWB_fixed_Asm_32 */ |
| 27529 | VecListFourQ, GPR, i32imm, i32imm, i32imm, |
| 27530 | /* VST4qWB_fixed_Asm_8 */ |
| 27531 | VecListFourQ, GPR, i32imm, i32imm, i32imm, |
| 27532 | /* VST4qWB_register_Asm_16 */ |
| 27533 | VecListFourQ, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27534 | /* VST4qWB_register_Asm_32 */ |
| 27535 | VecListFourQ, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27536 | /* VST4qWB_register_Asm_8 */ |
| 27537 | VecListFourQ, GPR, i32imm, rGPR, i32imm, i32imm, |
| 27538 | /* WIN__CHKSTK */ |
| 27539 | /* WIN__DBZCHK */ |
| 27540 | tGPR, |
| 27541 | /* t2ABS */ |
| 27542 | rGPR, rGPR, |
| 27543 | /* t2ADDSri */ |
| 27544 | rGPR, GPRnopc, t2_so_imm, i32imm, i32imm, |
| 27545 | /* t2ADDSrr */ |
| 27546 | rGPR, GPRnopc, rGPR, i32imm, i32imm, |
| 27547 | /* t2ADDSrs */ |
| 27548 | rGPR, GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 27549 | /* t2BF_LabelPseudo */ |
| 27550 | pclabel, |
| 27551 | /* t2BR_JT */ |
| 27552 | GPR, GPR, i32imm, |
| 27553 | /* t2CALL_BTI */ |
| 27554 | i32imm, i32imm, thumb_bl_target, |
| 27555 | /* t2DoLoopStart */ |
| 27556 | GPRlr, rGPR, |
| 27557 | /* t2DoLoopStartTP */ |
| 27558 | GPRlr, rGPR, rGPR, |
| 27559 | /* t2LDMIA_RET */ |
| 27560 | GPR, GPR, i32imm, i32imm, reglist, |
| 27561 | /* t2LDRB_OFFSET_imm */ |
| 27562 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27563 | /* t2LDRB_POST_imm */ |
| 27564 | GPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 27565 | /* t2LDRB_PRE_imm */ |
| 27566 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27567 | /* t2LDRBpcrel */ |
| 27568 | GPRnopc, t2ldr_pcrel_imm12, i32imm, i32imm, |
| 27569 | /* t2LDRConstPool */ |
| 27570 | GPR, const_pool_asm_imm, i32imm, i32imm, |
| 27571 | /* t2LDRH_OFFSET_imm */ |
| 27572 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27573 | /* t2LDRH_POST_imm */ |
| 27574 | GPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 27575 | /* t2LDRH_PRE_imm */ |
| 27576 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27577 | /* t2LDRHpcrel */ |
| 27578 | GPRnopc, t2ldr_pcrel_imm12, i32imm, i32imm, |
| 27579 | /* t2LDRLIT_ga_pcrel */ |
| 27580 | rGPR, i32imm, |
| 27581 | /* t2LDRSB_OFFSET_imm */ |
| 27582 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27583 | /* t2LDRSB_POST_imm */ |
| 27584 | GPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 27585 | /* t2LDRSB_PRE_imm */ |
| 27586 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27587 | /* t2LDRSBpcrel */ |
| 27588 | GPRnopc, t2ldr_pcrel_imm12, i32imm, i32imm, |
| 27589 | /* t2LDRSH_OFFSET_imm */ |
| 27590 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27591 | /* t2LDRSH_POST_imm */ |
| 27592 | GPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 27593 | /* t2LDRSH_PRE_imm */ |
| 27594 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27595 | /* t2LDRSHpcrel */ |
| 27596 | GPRnopc, t2ldr_pcrel_imm12, i32imm, i32imm, |
| 27597 | /* t2LDR_POST_imm */ |
| 27598 | GPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 27599 | /* t2LDR_PRE_imm */ |
| 27600 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27601 | /* t2LDRpci_pic */ |
| 27602 | rGPR, i32imm, pclabel, |
| 27603 | /* t2LDRpcrel */ |
| 27604 | GPR, t2ldr_pcrel_imm12, i32imm, i32imm, |
| 27605 | /* t2LEApcrel */ |
| 27606 | rGPR, i32imm, i32imm, i32imm, |
| 27607 | /* t2LEApcrelJT */ |
| 27608 | rGPR, i32imm, i32imm, i32imm, |
| 27609 | /* t2LoopDec */ |
| 27610 | GPRlr, GPRlr, imm0_7, |
| 27611 | /* t2LoopEnd */ |
| 27612 | GPRlr, brtarget, |
| 27613 | /* t2LoopEndDec */ |
| 27614 | GPRlr, GPRlr, brtarget, |
| 27615 | /* t2MOVCCasr */ |
| 27616 | rGPR, rGPR, rGPR, i32imm, i32imm, i32imm, |
| 27617 | /* t2MOVCCi */ |
| 27618 | rGPR, rGPR, t2_so_imm, i32imm, i32imm, |
| 27619 | /* t2MOVCCi16 */ |
| 27620 | rGPR, rGPR, imm0_65535_expr, i32imm, i32imm, |
| 27621 | /* t2MOVCCi32imm */ |
| 27622 | rGPR, rGPR, i32imm, i32imm, i32imm, |
| 27623 | /* t2MOVCClsl */ |
| 27624 | rGPR, rGPR, rGPR, i32imm, i32imm, i32imm, |
| 27625 | /* t2MOVCClsr */ |
| 27626 | rGPR, rGPR, rGPR, i32imm, i32imm, i32imm, |
| 27627 | /* t2MOVCCr */ |
| 27628 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 27629 | /* t2MOVCCror */ |
| 27630 | rGPR, rGPR, rGPR, i32imm, i32imm, i32imm, |
| 27631 | /* t2MOVSsi */ |
| 27632 | rGPR, rGPR, i32imm, i32imm, i32imm, |
| 27633 | /* t2MOVSsr */ |
| 27634 | rGPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 27635 | /* t2MOVTi16_ga_pcrel */ |
| 27636 | rGPR, rGPR, i32imm, pclabel, |
| 27637 | /* t2MOV_ga_pcrel */ |
| 27638 | rGPR, i32imm, |
| 27639 | /* t2MOVi16_ga_pcrel */ |
| 27640 | rGPR, i32imm, pclabel, |
| 27641 | /* t2MOVi32imm */ |
| 27642 | rGPR, i32imm, |
| 27643 | /* t2MOVsi */ |
| 27644 | rGPR, rGPR, i32imm, i32imm, i32imm, |
| 27645 | /* t2MOVsr */ |
| 27646 | rGPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 27647 | /* t2MVNCCi */ |
| 27648 | rGPR, rGPR, t2_so_imm, i32imm, i32imm, |
| 27649 | /* t2RSBSri */ |
| 27650 | rGPR, rGPR, t2_so_imm, i32imm, i32imm, |
| 27651 | /* t2RSBSrs */ |
| 27652 | rGPR, rGPR, rGPR, i32imm, i32imm, i32imm, |
| 27653 | /* t2STRB_OFFSET_imm */ |
| 27654 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27655 | /* t2STRB_POST_imm */ |
| 27656 | GPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 27657 | /* t2STRB_PRE_imm */ |
| 27658 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27659 | /* t2STRB_preidx */ |
| 27660 | GPRnopc, rGPR, GPRnopc, t2am_imm8_offset, i32imm, i32imm, |
| 27661 | /* t2STRH_OFFSET_imm */ |
| 27662 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27663 | /* t2STRH_POST_imm */ |
| 27664 | GPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 27665 | /* t2STRH_PRE_imm */ |
| 27666 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27667 | /* t2STRH_preidx */ |
| 27668 | GPRnopc, rGPR, GPRnopc, t2am_imm8_offset, i32imm, i32imm, |
| 27669 | /* t2STR_POST_imm */ |
| 27670 | GPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 27671 | /* t2STR_PRE_imm */ |
| 27672 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27673 | /* t2STR_preidx */ |
| 27674 | GPRnopc, rGPR, GPRnopc, t2am_imm8_offset, i32imm, i32imm, |
| 27675 | /* t2SUBSri */ |
| 27676 | rGPR, GPRnopc, t2_so_imm, i32imm, i32imm, |
| 27677 | /* t2SUBSrr */ |
| 27678 | rGPR, GPRnopc, rGPR, i32imm, i32imm, |
| 27679 | /* t2SUBSrs */ |
| 27680 | rGPR, GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 27681 | /* t2SpeculationBarrierISBDSBEndBB */ |
| 27682 | /* t2SpeculationBarrierSBEndBB */ |
| 27683 | /* t2TBB_JT */ |
| 27684 | GPR, GPR, i32imm, i32imm, |
| 27685 | /* t2TBH_JT */ |
| 27686 | GPR, GPR, i32imm, i32imm, |
| 27687 | /* t2WhileLoopSetup */ |
| 27688 | GPRlr, rGPR, |
| 27689 | /* t2WhileLoopStart */ |
| 27690 | GPRlr, brtarget, |
| 27691 | /* t2WhileLoopStartLR */ |
| 27692 | GPRlr, rGPR, brtarget, |
| 27693 | /* t2WhileLoopStartTP */ |
| 27694 | GPRlr, rGPR, rGPR, brtarget, |
| 27695 | /* tADCS */ |
| 27696 | tGPR, tGPR, tGPR, |
| 27697 | /* tADDSi3 */ |
| 27698 | tGPR, tGPR, imm0_7, |
| 27699 | /* tADDSi8 */ |
| 27700 | tGPR, tGPR, imm0_255_expr, |
| 27701 | /* tADDSrr */ |
| 27702 | tGPR, tGPR, tGPR, |
| 27703 | /* tADDframe */ |
| 27704 | tGPR, i32imm, i32imm, |
| 27705 | /* tADJCALLSTACKDOWN */ |
| 27706 | i32imm, i32imm, |
| 27707 | /* tADJCALLSTACKUP */ |
| 27708 | i32imm, i32imm, |
| 27709 | /* tBLXNS_CALL */ |
| 27710 | GPRnopc, |
| 27711 | /* tBLXr_noip */ |
| 27712 | i32imm, i32imm, GPRnoip, |
| 27713 | /* tBL_PUSHLR */ |
| 27714 | GPRlr, i32imm, i32imm, thumb_bl_target, |
| 27715 | /* tBRIND */ |
| 27716 | GPR, i32imm, i32imm, |
| 27717 | /* tBR_JTr */ |
| 27718 | tGPR, i32imm, |
| 27719 | /* tBXNS_RET */ |
| 27720 | /* tBX_CALL */ |
| 27721 | tGPR, |
| 27722 | /* tBX_RET */ |
| 27723 | i32imm, i32imm, |
| 27724 | /* tBX_RET_vararg */ |
| 27725 | tGPR, i32imm, i32imm, |
| 27726 | /* tBfar */ |
| 27727 | thumb_bl_target, i32imm, i32imm, |
| 27728 | /* tCMP_SWAP_16 */ |
| 27729 | GPR, tGPR, GPR, tGPR, GPR, |
| 27730 | /* tCMP_SWAP_32 */ |
| 27731 | GPR, tGPR, GPR, GPR, GPR, |
| 27732 | /* tCMP_SWAP_8 */ |
| 27733 | GPR, tGPR, GPR, tGPR, GPR, |
| 27734 | /* tLDMIA_UPD */ |
| 27735 | tGPR, tGPR, i32imm, i32imm, reglist, |
| 27736 | /* tLDRConstPool */ |
| 27737 | tGPR, const_pool_asm_imm, i32imm, i32imm, |
| 27738 | /* tLDRLIT_ga_abs */ |
| 27739 | tGPR, i32imm, |
| 27740 | /* tLDRLIT_ga_pcrel */ |
| 27741 | tGPR, i32imm, |
| 27742 | /* tLDR_postidx */ |
| 27743 | tGPR, tGPR, tGPR, i32imm, i32imm, |
| 27744 | /* tLDRpci_pic */ |
| 27745 | tGPR, i32imm, pclabel, |
| 27746 | /* tLEApcrel */ |
| 27747 | tGPR, i32imm, i32imm, i32imm, |
| 27748 | /* tLEApcrelJT */ |
| 27749 | tGPR, i32imm, i32imm, i32imm, |
| 27750 | /* tLSLSri */ |
| 27751 | tGPR, tGPR, imm0_31, |
| 27752 | /* tMOVCCr_pseudo */ |
| 27753 | tGPR, tGPR, tGPR, i32imm, i32imm, |
| 27754 | /* tMOVi32imm */ |
| 27755 | rGPR, i32imm, |
| 27756 | /* tPOP_RET */ |
| 27757 | i32imm, i32imm, reglist, |
| 27758 | /* tRSBS */ |
| 27759 | tGPR, tGPR, |
| 27760 | /* tSBCS */ |
| 27761 | tGPR, tGPR, tGPR, |
| 27762 | /* tSUBSi3 */ |
| 27763 | tGPR, tGPR, imm0_7, |
| 27764 | /* tSUBSi8 */ |
| 27765 | tGPR, tGPR, imm0_255, |
| 27766 | /* tSUBSrr */ |
| 27767 | tGPR, tGPR, tGPR, |
| 27768 | /* tTAILJMPd */ |
| 27769 | thumb_br_target, i32imm, i32imm, |
| 27770 | /* tTAILJMPdND */ |
| 27771 | t_brtarget, i32imm, i32imm, |
| 27772 | /* tTAILJMPr */ |
| 27773 | tcGPR, |
| 27774 | /* tTBB_JT */ |
| 27775 | tGPRwithpc, tGPR, i32imm, i32imm, |
| 27776 | /* tTBH_JT */ |
| 27777 | tGPRwithpc, tGPR, i32imm, i32imm, |
| 27778 | /* tTPsoft */ |
| 27779 | /* ADCri */ |
| 27780 | GPR, GPR, mod_imm, i32imm, i32imm, CCR, |
| 27781 | /* ADCrr */ |
| 27782 | GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 27783 | /* ADCrsi */ |
| 27784 | GPR, GPR, GPR, i32imm, i32imm, i32imm, CCR, |
| 27785 | /* ADCrsr */ |
| 27786 | GPRnopc, GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, CCR, |
| 27787 | /* ADDri */ |
| 27788 | GPR, GPR, mod_imm, i32imm, i32imm, CCR, |
| 27789 | /* ADDrr */ |
| 27790 | GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 27791 | /* ADDrsi */ |
| 27792 | GPR, GPR, GPR, i32imm, i32imm, i32imm, CCR, |
| 27793 | /* ADDrsr */ |
| 27794 | GPR, GPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, CCR, |
| 27795 | /* ADR */ |
| 27796 | GPR, adrlabel, i32imm, i32imm, |
| 27797 | /* AESD */ |
| 27798 | QPR, QPR, QPR, |
| 27799 | /* AESE */ |
| 27800 | QPR, QPR, QPR, |
| 27801 | /* AESIMC */ |
| 27802 | QPR, QPR, |
| 27803 | /* AESMC */ |
| 27804 | QPR, QPR, |
| 27805 | /* ANDri */ |
| 27806 | GPR, GPR, mod_imm, i32imm, i32imm, CCR, |
| 27807 | /* ANDrr */ |
| 27808 | GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 27809 | /* ANDrsi */ |
| 27810 | GPR, GPR, GPR, i32imm, i32imm, i32imm, CCR, |
| 27811 | /* ANDrsr */ |
| 27812 | GPR, GPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, CCR, |
| 27813 | /* BF16VDOTI_VDOTD */ |
| 27814 | DPR, DPR, DPR, DPR_VFP2, i32imm, |
| 27815 | /* BF16VDOTI_VDOTQ */ |
| 27816 | QPR, QPR, QPR, DPR_VFP2, i32imm, |
| 27817 | /* BF16VDOTS_VDOTD */ |
| 27818 | DPR, DPR, DPR, DPR, |
| 27819 | /* BF16VDOTS_VDOTQ */ |
| 27820 | QPR, QPR, QPR, QPR, |
| 27821 | /* BF16_VCVT */ |
| 27822 | DPR, QPR, i32imm, i32imm, |
| 27823 | /* BF16_VCVTB */ |
| 27824 | SPR, SPR, SPR, i32imm, i32imm, |
| 27825 | /* BF16_VCVTT */ |
| 27826 | SPR, SPR, SPR, i32imm, i32imm, |
| 27827 | /* BFC */ |
| 27828 | GPR, GPR, bf_inv_mask_imm, i32imm, i32imm, |
| 27829 | /* BFI */ |
| 27830 | GPRnopc, GPRnopc, GPR, bf_inv_mask_imm, i32imm, i32imm, |
| 27831 | /* BICri */ |
| 27832 | GPR, GPR, mod_imm, i32imm, i32imm, CCR, |
| 27833 | /* BICrr */ |
| 27834 | GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 27835 | /* BICrsi */ |
| 27836 | GPR, GPR, GPR, i32imm, i32imm, i32imm, CCR, |
| 27837 | /* BICrsr */ |
| 27838 | GPR, GPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, CCR, |
| 27839 | /* BKPT */ |
| 27840 | imm0_65535, |
| 27841 | /* BL */ |
| 27842 | arm_bl_target, |
| 27843 | /* BLX */ |
| 27844 | GPR, |
| 27845 | /* BLX_pred */ |
| 27846 | GPR, i32imm, i32imm, |
| 27847 | /* BLXi */ |
| 27848 | arm_blx_target, |
| 27849 | /* BL_pred */ |
| 27850 | arm_bl_target, i32imm, i32imm, |
| 27851 | /* BX */ |
| 27852 | GPR, |
| 27853 | /* BXJ */ |
| 27854 | GPR, i32imm, i32imm, |
| 27855 | /* BX_RET */ |
| 27856 | i32imm, i32imm, |
| 27857 | /* BX_pred */ |
| 27858 | GPR, i32imm, i32imm, |
| 27859 | /* Bcc */ |
| 27860 | arm_br_target, i32imm, i32imm, |
| 27861 | /* CDE_CX1 */ |
| 27862 | GPRwithAPSR_NZCVnosp, p_imm, imm_13b, |
| 27863 | /* CDE_CX1A */ |
| 27864 | GPRwithAPSR_NZCVnosp, p_imm, GPRwithAPSR_NZCVnosp, imm_13b, i32imm, i32imm, |
| 27865 | /* CDE_CX1D */ |
| 27866 | CDEDualRegOp, p_imm, imm_13b, |
| 27867 | /* CDE_CX1DA */ |
| 27868 | CDEDualRegOp, p_imm, CDEDualRegOp, imm_13b, i32imm, i32imm, |
| 27869 | /* CDE_CX2 */ |
| 27870 | GPRwithAPSR_NZCVnosp, p_imm, GPRwithAPSR_NZCVnosp, imm_9b, |
| 27871 | /* CDE_CX2A */ |
| 27872 | GPRwithAPSR_NZCVnosp, p_imm, GPRwithAPSR_NZCVnosp, GPRwithAPSR_NZCVnosp, imm_9b, i32imm, i32imm, |
| 27873 | /* CDE_CX2D */ |
| 27874 | CDEDualRegOp, p_imm, GPRwithAPSR_NZCVnosp, imm_9b, |
| 27875 | /* CDE_CX2DA */ |
| 27876 | CDEDualRegOp, p_imm, CDEDualRegOp, GPRwithAPSR_NZCVnosp, imm_9b, i32imm, i32imm, |
| 27877 | /* CDE_CX3 */ |
| 27878 | GPRwithAPSR_NZCVnosp, p_imm, GPRwithAPSR_NZCVnosp, GPRwithAPSR_NZCVnosp, imm_6b, |
| 27879 | /* CDE_CX3A */ |
| 27880 | GPRwithAPSR_NZCVnosp, p_imm, GPRwithAPSR_NZCVnosp, GPRwithAPSR_NZCVnosp, GPRwithAPSR_NZCVnosp, imm_6b, i32imm, i32imm, |
| 27881 | /* CDE_CX3D */ |
| 27882 | CDEDualRegOp, p_imm, GPRwithAPSR_NZCVnosp, GPRwithAPSR_NZCVnosp, imm_6b, |
| 27883 | /* CDE_CX3DA */ |
| 27884 | CDEDualRegOp, p_imm, CDEDualRegOp, GPRwithAPSR_NZCVnosp, GPRwithAPSR_NZCVnosp, imm_6b, i32imm, i32imm, |
| 27885 | /* CDE_VCX1A_fpdp */ |
| 27886 | DPR_VFP2, p_imm, DPR_VFP2, imm_11b, |
| 27887 | /* CDE_VCX1A_fpsp */ |
| 27888 | SPR, p_imm, SPR, imm_11b, |
| 27889 | /* CDE_VCX1A_vec */ |
| 27890 | MQPR, p_imm, MQPR, imm_12b, i32imm, VCCR, GPRlr, |
| 27891 | /* CDE_VCX1_fpdp */ |
| 27892 | DPR_VFP2, p_imm, imm_11b, |
| 27893 | /* CDE_VCX1_fpsp */ |
| 27894 | SPR, p_imm, imm_11b, |
| 27895 | /* CDE_VCX1_vec */ |
| 27896 | MQPR, p_imm, imm_12b, i32imm, VCCR, GPRlr, MQPR, |
| 27897 | /* CDE_VCX2A_fpdp */ |
| 27898 | DPR_VFP2, p_imm, DPR_VFP2, DPR_VFP2, imm_6b, |
| 27899 | /* CDE_VCX2A_fpsp */ |
| 27900 | SPR, p_imm, SPR, SPR, imm_6b, |
| 27901 | /* CDE_VCX2A_vec */ |
| 27902 | MQPR, p_imm, MQPR, MQPR, imm_7b, i32imm, VCCR, GPRlr, |
| 27903 | /* CDE_VCX2_fpdp */ |
| 27904 | DPR_VFP2, p_imm, DPR_VFP2, imm_6b, |
| 27905 | /* CDE_VCX2_fpsp */ |
| 27906 | SPR, p_imm, SPR, imm_6b, |
| 27907 | /* CDE_VCX2_vec */ |
| 27908 | MQPR, p_imm, MQPR, imm_7b, i32imm, VCCR, GPRlr, MQPR, |
| 27909 | /* CDE_VCX3A_fpdp */ |
| 27910 | DPR_VFP2, p_imm, DPR_VFP2, DPR_VFP2, DPR_VFP2, imm_3b, |
| 27911 | /* CDE_VCX3A_fpsp */ |
| 27912 | SPR, p_imm, SPR, SPR, SPR, imm_3b, |
| 27913 | /* CDE_VCX3A_vec */ |
| 27914 | MQPR, p_imm, MQPR, MQPR, MQPR, imm_4b, i32imm, VCCR, GPRlr, |
| 27915 | /* CDE_VCX3_fpdp */ |
| 27916 | DPR_VFP2, p_imm, DPR_VFP2, DPR_VFP2, imm_3b, |
| 27917 | /* CDE_VCX3_fpsp */ |
| 27918 | SPR, p_imm, SPR, SPR, imm_3b, |
| 27919 | /* CDE_VCX3_vec */ |
| 27920 | MQPR, p_imm, MQPR, MQPR, imm_4b, i32imm, VCCR, GPRlr, MQPR, |
| 27921 | /* CDP */ |
| 27922 | p_imm, imm0_15, c_imm, c_imm, c_imm, imm0_7, i32imm, i32imm, |
| 27923 | /* CDP2 */ |
| 27924 | p_imm, imm0_15, c_imm, c_imm, c_imm, imm0_7, |
| 27925 | /* CLREX */ |
| 27926 | /* CLZ */ |
| 27927 | GPR, GPR, i32imm, i32imm, |
| 27928 | /* CMNri */ |
| 27929 | GPR, mod_imm, i32imm, i32imm, |
| 27930 | /* CMNzrr */ |
| 27931 | GPR, GPR, i32imm, i32imm, |
| 27932 | /* CMNzrsi */ |
| 27933 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27934 | /* CMNzrsr */ |
| 27935 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 27936 | /* CMPri */ |
| 27937 | GPR, mod_imm, i32imm, i32imm, |
| 27938 | /* CMPrr */ |
| 27939 | GPR, GPR, i32imm, i32imm, |
| 27940 | /* CMPrsi */ |
| 27941 | GPR, GPR, i32imm, i32imm, i32imm, |
| 27942 | /* CMPrsr */ |
| 27943 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 27944 | /* CPS1p */ |
| 27945 | imm0_31, |
| 27946 | /* CPS2p */ |
| 27947 | imod_op, iflags_op, |
| 27948 | /* CPS3p */ |
| 27949 | imod_op, iflags_op, imm0_31, |
| 27950 | /* CRC32B */ |
| 27951 | GPRnopc, GPRnopc, GPRnopc, |
| 27952 | /* CRC32CB */ |
| 27953 | GPRnopc, GPRnopc, GPRnopc, |
| 27954 | /* CRC32CH */ |
| 27955 | GPRnopc, GPRnopc, GPRnopc, |
| 27956 | /* CRC32CW */ |
| 27957 | GPRnopc, GPRnopc, GPRnopc, |
| 27958 | /* CRC32H */ |
| 27959 | GPRnopc, GPRnopc, GPRnopc, |
| 27960 | /* CRC32W */ |
| 27961 | GPRnopc, GPRnopc, GPRnopc, |
| 27962 | /* DBG */ |
| 27963 | imm0_15, i32imm, i32imm, |
| 27964 | /* DMB */ |
| 27965 | memb_opt, |
| 27966 | /* DSB */ |
| 27967 | memb_opt, |
| 27968 | /* EORri */ |
| 27969 | GPR, GPR, mod_imm, i32imm, i32imm, CCR, |
| 27970 | /* EORrr */ |
| 27971 | GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 27972 | /* EORrsi */ |
| 27973 | GPR, GPR, GPR, i32imm, i32imm, i32imm, CCR, |
| 27974 | /* EORrsr */ |
| 27975 | GPR, GPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, CCR, |
| 27976 | /* ERET */ |
| 27977 | i32imm, i32imm, |
| 27978 | /* FCONSTD */ |
| 27979 | DPR, vfp_f64imm, i32imm, i32imm, |
| 27980 | /* FCONSTH */ |
| 27981 | HPR, vfp_f16imm, i32imm, i32imm, |
| 27982 | /* FCONSTS */ |
| 27983 | SPR, vfp_f32imm, i32imm, i32imm, |
| 27984 | /* FLDMXDB_UPD */ |
| 27985 | GPR, GPR, i32imm, i32imm, dpr_reglist, |
| 27986 | /* FLDMXIA */ |
| 27987 | GPR, i32imm, i32imm, dpr_reglist, |
| 27988 | /* FLDMXIA_UPD */ |
| 27989 | GPR, GPR, i32imm, i32imm, dpr_reglist, |
| 27990 | /* FMSTAT */ |
| 27991 | i32imm, i32imm, |
| 27992 | /* FSTMXDB_UPD */ |
| 27993 | GPR, GPR, i32imm, i32imm, dpr_reglist, |
| 27994 | /* FSTMXIA */ |
| 27995 | GPR, i32imm, i32imm, dpr_reglist, |
| 27996 | /* FSTMXIA_UPD */ |
| 27997 | GPR, GPR, i32imm, i32imm, dpr_reglist, |
| 27998 | /* HINT */ |
| 27999 | imm0_239, i32imm, i32imm, |
| 28000 | /* HLT */ |
| 28001 | imm0_65535, |
| 28002 | /* HVC */ |
| 28003 | imm0_65535, |
| 28004 | /* ISB */ |
| 28005 | instsyncb_opt, |
| 28006 | /* LDA */ |
| 28007 | GPR, GPR, i32imm, i32imm, |
| 28008 | /* LDAB */ |
| 28009 | GPR, GPR, i32imm, i32imm, |
| 28010 | /* LDAEX */ |
| 28011 | GPR, GPR, i32imm, i32imm, |
| 28012 | /* LDAEXB */ |
| 28013 | GPR, GPR, i32imm, i32imm, |
| 28014 | /* LDAEXD */ |
| 28015 | GPRPairOp, GPR, i32imm, i32imm, |
| 28016 | /* LDAEXH */ |
| 28017 | GPR, GPR, i32imm, i32imm, |
| 28018 | /* LDAH */ |
| 28019 | GPR, GPR, i32imm, i32imm, |
| 28020 | /* LDC2L_OFFSET */ |
| 28021 | p_imm, c_imm, GPR, i32imm, |
| 28022 | /* LDC2L_OPTION */ |
| 28023 | p_imm, c_imm, GPR, coproc_option_imm, |
| 28024 | /* LDC2L_POST */ |
| 28025 | p_imm, c_imm, GPR, i32imm, |
| 28026 | /* LDC2L_PRE */ |
| 28027 | p_imm, c_imm, GPR, i32imm, |
| 28028 | /* LDC2_OFFSET */ |
| 28029 | p_imm, c_imm, GPR, i32imm, |
| 28030 | /* LDC2_OPTION */ |
| 28031 | p_imm, c_imm, GPR, coproc_option_imm, |
| 28032 | /* LDC2_POST */ |
| 28033 | p_imm, c_imm, GPR, i32imm, |
| 28034 | /* LDC2_PRE */ |
| 28035 | p_imm, c_imm, GPR, i32imm, |
| 28036 | /* LDCL_OFFSET */ |
| 28037 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 28038 | /* LDCL_OPTION */ |
| 28039 | p_imm, c_imm, GPR, coproc_option_imm, i32imm, i32imm, |
| 28040 | /* LDCL_POST */ |
| 28041 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 28042 | /* LDCL_PRE */ |
| 28043 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 28044 | /* LDC_OFFSET */ |
| 28045 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 28046 | /* LDC_OPTION */ |
| 28047 | p_imm, c_imm, GPR, coproc_option_imm, i32imm, i32imm, |
| 28048 | /* LDC_POST */ |
| 28049 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 28050 | /* LDC_PRE */ |
| 28051 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 28052 | /* LDMDA */ |
| 28053 | GPR, i32imm, i32imm, reglist, |
| 28054 | /* LDMDA_UPD */ |
| 28055 | GPR, GPR, i32imm, i32imm, reglist, |
| 28056 | /* LDMDB */ |
| 28057 | GPR, i32imm, i32imm, reglist, |
| 28058 | /* LDMDB_UPD */ |
| 28059 | GPR, GPR, i32imm, i32imm, reglist, |
| 28060 | /* LDMIA */ |
| 28061 | GPR, i32imm, i32imm, reglist, |
| 28062 | /* LDMIA_UPD */ |
| 28063 | GPR, GPR, i32imm, i32imm, reglist, |
| 28064 | /* LDMIB */ |
| 28065 | GPR, i32imm, i32imm, reglist, |
| 28066 | /* LDMIB_UPD */ |
| 28067 | GPR, GPR, i32imm, i32imm, reglist, |
| 28068 | /* LDRBT_POST_IMM */ |
| 28069 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28070 | /* LDRBT_POST_REG */ |
| 28071 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28072 | /* LDRB_POST_IMM */ |
| 28073 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28074 | /* LDRB_POST_REG */ |
| 28075 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28076 | /* LDRB_PRE_IMM */ |
| 28077 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28078 | /* LDRB_PRE_REG */ |
| 28079 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28080 | /* LDRBi12 */ |
| 28081 | GPRnopc, GPR, i32imm, i32imm, i32imm, |
| 28082 | /* LDRBrs */ |
| 28083 | GPRnopc, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28084 | /* LDRD */ |
| 28085 | GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28086 | /* LDRD_POST */ |
| 28087 | GPR, GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28088 | /* LDRD_PRE */ |
| 28089 | GPR, GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28090 | /* LDREX */ |
| 28091 | GPR, GPR, i32imm, i32imm, |
| 28092 | /* LDREXB */ |
| 28093 | GPR, GPR, i32imm, i32imm, |
| 28094 | /* LDREXD */ |
| 28095 | GPRPairOp, GPR, i32imm, i32imm, |
| 28096 | /* LDREXH */ |
| 28097 | GPR, GPR, i32imm, i32imm, |
| 28098 | /* LDRH */ |
| 28099 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28100 | /* LDRHTi */ |
| 28101 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28102 | /* LDRHTr */ |
| 28103 | GPRnopc, GPRnopc, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28104 | /* LDRH_POST */ |
| 28105 | GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28106 | /* LDRH_PRE */ |
| 28107 | GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28108 | /* LDRSB */ |
| 28109 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28110 | /* LDRSBTi */ |
| 28111 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28112 | /* LDRSBTr */ |
| 28113 | GPRnopc, GPRnopc, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28114 | /* LDRSB_POST */ |
| 28115 | GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28116 | /* LDRSB_PRE */ |
| 28117 | GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28118 | /* LDRSH */ |
| 28119 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28120 | /* LDRSHTi */ |
| 28121 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28122 | /* LDRSHTr */ |
| 28123 | GPRnopc, GPRnopc, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28124 | /* LDRSH_POST */ |
| 28125 | GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28126 | /* LDRSH_PRE */ |
| 28127 | GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28128 | /* LDRT_POST_IMM */ |
| 28129 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28130 | /* LDRT_POST_REG */ |
| 28131 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28132 | /* LDR_POST_IMM */ |
| 28133 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28134 | /* LDR_POST_REG */ |
| 28135 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28136 | /* LDR_PRE_IMM */ |
| 28137 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 28138 | /* LDR_PRE_REG */ |
| 28139 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28140 | /* LDRcp */ |
| 28141 | GPR, GPR, i32imm, i32imm, i32imm, |
| 28142 | /* LDRi12 */ |
| 28143 | GPR, GPR, i32imm, i32imm, i32imm, |
| 28144 | /* LDRrs */ |
| 28145 | GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 28146 | /* MCR */ |
| 28147 | p_imm, imm0_7, GPR, c_imm, c_imm, imm0_7, i32imm, i32imm, |
| 28148 | /* MCR2 */ |
| 28149 | p_imm, imm0_7, GPR, c_imm, c_imm, imm0_7, |
| 28150 | /* MCRR */ |
| 28151 | p_imm, imm0_15, GPRnopc, GPRnopc, c_imm, i32imm, i32imm, |
| 28152 | /* MCRR2 */ |
| 28153 | p_imm, imm0_15, GPRnopc, GPRnopc, c_imm, |
| 28154 | /* MLA */ |
| 28155 | GPRnopc, GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, CCR, |
| 28156 | /* MLS */ |
| 28157 | GPR, GPR, GPR, GPR, i32imm, i32imm, |
| 28158 | /* MOVPCLR */ |
| 28159 | i32imm, i32imm, |
| 28160 | /* MOVTi16 */ |
| 28161 | GPRnopc, GPR, imm0_65535_expr, i32imm, i32imm, |
| 28162 | /* MOVi */ |
| 28163 | GPR, mod_imm, i32imm, i32imm, CCR, |
| 28164 | /* MOVi16 */ |
| 28165 | GPR, imm0_65535_expr, i32imm, i32imm, |
| 28166 | /* MOVr */ |
| 28167 | GPR, GPR, i32imm, i32imm, CCR, |
| 28168 | /* MOVr_TC */ |
| 28169 | tcGPR, tcGPR, i32imm, i32imm, CCR, |
| 28170 | /* MOVsi */ |
| 28171 | GPR, GPR, i32imm, i32imm, i32imm, CCR, |
| 28172 | /* MOVsr */ |
| 28173 | GPRnopc, GPR, GPR, i32imm, i32imm, i32imm, CCR, |
| 28174 | /* MRC */ |
| 28175 | GPRwithAPSR, p_imm, imm0_7, c_imm, c_imm, imm0_7, i32imm, i32imm, |
| 28176 | /* MRC2 */ |
| 28177 | GPRwithAPSR, p_imm, imm0_7, c_imm, c_imm, imm0_7, |
| 28178 | /* MRRC */ |
| 28179 | GPRnopc, GPRnopc, p_imm, imm0_15, c_imm, i32imm, i32imm, |
| 28180 | /* MRRC2 */ |
| 28181 | GPRnopc, GPRnopc, p_imm, imm0_15, c_imm, |
| 28182 | /* MRS */ |
| 28183 | GPRnopc, i32imm, i32imm, |
| 28184 | /* MRSbanked */ |
| 28185 | GPRnopc, banked_reg, i32imm, i32imm, |
| 28186 | /* MRSsys */ |
| 28187 | GPRnopc, i32imm, i32imm, |
| 28188 | /* MSR */ |
| 28189 | msr_mask, GPR, i32imm, i32imm, |
| 28190 | /* MSRbanked */ |
| 28191 | banked_reg, GPRnopc, i32imm, i32imm, |
| 28192 | /* MSRi */ |
| 28193 | msr_mask, mod_imm, i32imm, i32imm, |
| 28194 | /* MUL */ |
| 28195 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, CCR, |
| 28196 | /* MVE_ASRLi */ |
| 28197 | tGPREven, tGPROdd, tGPREven, tGPROdd, long_shift, i32imm, i32imm, |
| 28198 | /* MVE_ASRLr */ |
| 28199 | tGPREven, tGPROdd, tGPREven, tGPROdd, rGPR, i32imm, i32imm, |
| 28200 | /* MVE_DLSTP_16 */ |
| 28201 | GPRlr, rGPR, |
| 28202 | /* MVE_DLSTP_32 */ |
| 28203 | GPRlr, rGPR, |
| 28204 | /* MVE_DLSTP_64 */ |
| 28205 | GPRlr, rGPR, |
| 28206 | /* MVE_DLSTP_8 */ |
| 28207 | GPRlr, rGPR, |
| 28208 | /* MVE_LCTP */ |
| 28209 | i32imm, i32imm, |
| 28210 | /* MVE_LETP */ |
| 28211 | GPRlr, GPRlr, lelabel_u11, |
| 28212 | /* MVE_LSLLi */ |
| 28213 | tGPREven, tGPROdd, tGPREven, tGPROdd, long_shift, i32imm, i32imm, |
| 28214 | /* MVE_LSLLr */ |
| 28215 | tGPREven, tGPROdd, tGPREven, tGPROdd, rGPR, i32imm, i32imm, |
| 28216 | /* MVE_LSRL */ |
| 28217 | tGPREven, tGPROdd, tGPREven, tGPROdd, long_shift, i32imm, i32imm, |
| 28218 | /* MVE_SQRSHR */ |
| 28219 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 28220 | /* MVE_SQRSHRL */ |
| 28221 | tGPREven, tGPROdd, tGPREven, tGPROdd, rGPR, saturateop, i32imm, i32imm, |
| 28222 | /* MVE_SQSHL */ |
| 28223 | rGPR, rGPR, long_shift, i32imm, i32imm, |
| 28224 | /* MVE_SQSHLL */ |
| 28225 | tGPREven, tGPROdd, tGPREven, tGPROdd, long_shift, i32imm, i32imm, |
| 28226 | /* MVE_SRSHR */ |
| 28227 | rGPR, rGPR, long_shift, i32imm, i32imm, |
| 28228 | /* MVE_SRSHRL */ |
| 28229 | tGPREven, tGPROdd, tGPREven, tGPROdd, long_shift, i32imm, i32imm, |
| 28230 | /* MVE_UQRSHL */ |
| 28231 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 28232 | /* MVE_UQRSHLL */ |
| 28233 | tGPREven, tGPROdd, tGPREven, tGPROdd, rGPR, saturateop, i32imm, i32imm, |
| 28234 | /* MVE_UQSHL */ |
| 28235 | rGPR, rGPR, long_shift, i32imm, i32imm, |
| 28236 | /* MVE_UQSHLL */ |
| 28237 | tGPREven, tGPROdd, tGPREven, tGPROdd, long_shift, i32imm, i32imm, |
| 28238 | /* MVE_URSHR */ |
| 28239 | rGPR, rGPR, long_shift, i32imm, i32imm, |
| 28240 | /* MVE_URSHRL */ |
| 28241 | tGPREven, tGPROdd, tGPREven, tGPROdd, long_shift, i32imm, i32imm, |
| 28242 | /* MVE_VABAVs16 */ |
| 28243 | rGPR, rGPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28244 | /* MVE_VABAVs32 */ |
| 28245 | rGPR, rGPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28246 | /* MVE_VABAVs8 */ |
| 28247 | rGPR, rGPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28248 | /* MVE_VABAVu16 */ |
| 28249 | rGPR, rGPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28250 | /* MVE_VABAVu32 */ |
| 28251 | rGPR, rGPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28252 | /* MVE_VABAVu8 */ |
| 28253 | rGPR, rGPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28254 | /* MVE_VABDf16 */ |
| 28255 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28256 | /* MVE_VABDf32 */ |
| 28257 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28258 | /* MVE_VABDs16 */ |
| 28259 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28260 | /* MVE_VABDs32 */ |
| 28261 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28262 | /* MVE_VABDs8 */ |
| 28263 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28264 | /* MVE_VABDu16 */ |
| 28265 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28266 | /* MVE_VABDu32 */ |
| 28267 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28268 | /* MVE_VABDu8 */ |
| 28269 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28270 | /* MVE_VABSf16 */ |
| 28271 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28272 | /* MVE_VABSf32 */ |
| 28273 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28274 | /* MVE_VABSs16 */ |
| 28275 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28276 | /* MVE_VABSs32 */ |
| 28277 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28278 | /* MVE_VABSs8 */ |
| 28279 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28280 | /* MVE_VADC */ |
| 28281 | MQPR, cl_FPSCR_NZCV, MQPR, MQPR, cl_FPSCR_NZCV, i32imm, VCCR, GPRlr, MQPR, |
| 28282 | /* MVE_VADCI */ |
| 28283 | MQPR, cl_FPSCR_NZCV, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28284 | /* MVE_VADDLVs32acc */ |
| 28285 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, i32imm, VCCR, GPRlr, |
| 28286 | /* MVE_VADDLVs32no_acc */ |
| 28287 | tGPREven, tGPROdd, MQPR, i32imm, VCCR, GPRlr, |
| 28288 | /* MVE_VADDLVu32acc */ |
| 28289 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, i32imm, VCCR, GPRlr, |
| 28290 | /* MVE_VADDLVu32no_acc */ |
| 28291 | tGPREven, tGPROdd, MQPR, i32imm, VCCR, GPRlr, |
| 28292 | /* MVE_VADDVs16acc */ |
| 28293 | tGPREven, tGPREven, MQPR, i32imm, VCCR, GPRlr, |
| 28294 | /* MVE_VADDVs16no_acc */ |
| 28295 | tGPREven, MQPR, i32imm, VCCR, GPRlr, |
| 28296 | /* MVE_VADDVs32acc */ |
| 28297 | tGPREven, tGPREven, MQPR, i32imm, VCCR, GPRlr, |
| 28298 | /* MVE_VADDVs32no_acc */ |
| 28299 | tGPREven, MQPR, i32imm, VCCR, GPRlr, |
| 28300 | /* MVE_VADDVs8acc */ |
| 28301 | tGPREven, tGPREven, MQPR, i32imm, VCCR, GPRlr, |
| 28302 | /* MVE_VADDVs8no_acc */ |
| 28303 | tGPREven, MQPR, i32imm, VCCR, GPRlr, |
| 28304 | /* MVE_VADDVu16acc */ |
| 28305 | tGPREven, tGPREven, MQPR, i32imm, VCCR, GPRlr, |
| 28306 | /* MVE_VADDVu16no_acc */ |
| 28307 | tGPREven, MQPR, i32imm, VCCR, GPRlr, |
| 28308 | /* MVE_VADDVu32acc */ |
| 28309 | tGPREven, tGPREven, MQPR, i32imm, VCCR, GPRlr, |
| 28310 | /* MVE_VADDVu32no_acc */ |
| 28311 | tGPREven, MQPR, i32imm, VCCR, GPRlr, |
| 28312 | /* MVE_VADDVu8acc */ |
| 28313 | tGPREven, tGPREven, MQPR, i32imm, VCCR, GPRlr, |
| 28314 | /* MVE_VADDVu8no_acc */ |
| 28315 | tGPREven, MQPR, i32imm, VCCR, GPRlr, |
| 28316 | /* MVE_VADD_qr_f16 */ |
| 28317 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28318 | /* MVE_VADD_qr_f32 */ |
| 28319 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28320 | /* MVE_VADD_qr_i16 */ |
| 28321 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28322 | /* MVE_VADD_qr_i32 */ |
| 28323 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28324 | /* MVE_VADD_qr_i8 */ |
| 28325 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28326 | /* MVE_VADDf16 */ |
| 28327 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28328 | /* MVE_VADDf32 */ |
| 28329 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28330 | /* MVE_VADDi16 */ |
| 28331 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28332 | /* MVE_VADDi32 */ |
| 28333 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28334 | /* MVE_VADDi8 */ |
| 28335 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28336 | /* MVE_VAND */ |
| 28337 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28338 | /* MVE_VBIC */ |
| 28339 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28340 | /* MVE_VBICimmi16 */ |
| 28341 | MQPR, MQPR, nImmSplatI16, i32imm, VCCR, GPRlr, |
| 28342 | /* MVE_VBICimmi32 */ |
| 28343 | MQPR, MQPR, nImmSplatI32, i32imm, VCCR, GPRlr, |
| 28344 | /* MVE_VBRSR16 */ |
| 28345 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28346 | /* MVE_VBRSR32 */ |
| 28347 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28348 | /* MVE_VBRSR8 */ |
| 28349 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28350 | /* MVE_VCADDf16 */ |
| 28351 | MQPR, MQPR, MQPR, complexrotateopodd, i32imm, VCCR, GPRlr, MQPR, |
| 28352 | /* MVE_VCADDf32 */ |
| 28353 | MQPR, MQPR, MQPR, complexrotateopodd, i32imm, VCCR, GPRlr, MQPR, |
| 28354 | /* MVE_VCADDi16 */ |
| 28355 | MQPR, MQPR, MQPR, complexrotateopodd, i32imm, VCCR, GPRlr, MQPR, |
| 28356 | /* MVE_VCADDi32 */ |
| 28357 | MQPR, MQPR, MQPR, complexrotateopodd, i32imm, VCCR, GPRlr, MQPR, |
| 28358 | /* MVE_VCADDi8 */ |
| 28359 | MQPR, MQPR, MQPR, complexrotateopodd, i32imm, VCCR, GPRlr, MQPR, |
| 28360 | /* MVE_VCLSs16 */ |
| 28361 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28362 | /* MVE_VCLSs32 */ |
| 28363 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28364 | /* MVE_VCLSs8 */ |
| 28365 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28366 | /* MVE_VCLZs16 */ |
| 28367 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28368 | /* MVE_VCLZs32 */ |
| 28369 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28370 | /* MVE_VCLZs8 */ |
| 28371 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28372 | /* MVE_VCMLAf16 */ |
| 28373 | MQPR, MQPR, MQPR, MQPR, complexrotateop, i32imm, VCCR, GPRlr, |
| 28374 | /* MVE_VCMLAf32 */ |
| 28375 | MQPR, MQPR, MQPR, MQPR, complexrotateop, i32imm, VCCR, GPRlr, |
| 28376 | /* MVE_VCMPf16 */ |
| 28377 | VCCR, MQPR, MQPR, pred_basic_fp, i32imm, VCCR, GPRlr, |
| 28378 | /* MVE_VCMPf16r */ |
| 28379 | VCCR, MQPR, GPRwithZR, pred_basic_fp, i32imm, VCCR, GPRlr, |
| 28380 | /* MVE_VCMPf32 */ |
| 28381 | VCCR, MQPR, MQPR, pred_basic_fp, i32imm, VCCR, GPRlr, |
| 28382 | /* MVE_VCMPf32r */ |
| 28383 | VCCR, MQPR, GPRwithZR, pred_basic_fp, i32imm, VCCR, GPRlr, |
| 28384 | /* MVE_VCMPi16 */ |
| 28385 | VCCR, MQPR, MQPR, pred_basic_i, i32imm, VCCR, GPRlr, |
| 28386 | /* MVE_VCMPi16r */ |
| 28387 | VCCR, MQPR, GPRwithZR, pred_basic_i, i32imm, VCCR, GPRlr, |
| 28388 | /* MVE_VCMPi32 */ |
| 28389 | VCCR, MQPR, MQPR, pred_basic_i, i32imm, VCCR, GPRlr, |
| 28390 | /* MVE_VCMPi32r */ |
| 28391 | VCCR, MQPR, GPRwithZR, pred_basic_i, i32imm, VCCR, GPRlr, |
| 28392 | /* MVE_VCMPi8 */ |
| 28393 | VCCR, MQPR, MQPR, pred_basic_i, i32imm, VCCR, GPRlr, |
| 28394 | /* MVE_VCMPi8r */ |
| 28395 | VCCR, MQPR, GPRwithZR, pred_basic_i, i32imm, VCCR, GPRlr, |
| 28396 | /* MVE_VCMPs16 */ |
| 28397 | VCCR, MQPR, MQPR, pred_basic_s, i32imm, VCCR, GPRlr, |
| 28398 | /* MVE_VCMPs16r */ |
| 28399 | VCCR, MQPR, GPRwithZR, pred_basic_s, i32imm, VCCR, GPRlr, |
| 28400 | /* MVE_VCMPs32 */ |
| 28401 | VCCR, MQPR, MQPR, pred_basic_s, i32imm, VCCR, GPRlr, |
| 28402 | /* MVE_VCMPs32r */ |
| 28403 | VCCR, MQPR, GPRwithZR, pred_basic_s, i32imm, VCCR, GPRlr, |
| 28404 | /* MVE_VCMPs8 */ |
| 28405 | VCCR, MQPR, MQPR, pred_basic_s, i32imm, VCCR, GPRlr, |
| 28406 | /* MVE_VCMPs8r */ |
| 28407 | VCCR, MQPR, GPRwithZR, pred_basic_s, i32imm, VCCR, GPRlr, |
| 28408 | /* MVE_VCMPu16 */ |
| 28409 | VCCR, MQPR, MQPR, pred_basic_u, i32imm, VCCR, GPRlr, |
| 28410 | /* MVE_VCMPu16r */ |
| 28411 | VCCR, MQPR, GPRwithZR, pred_basic_u, i32imm, VCCR, GPRlr, |
| 28412 | /* MVE_VCMPu32 */ |
| 28413 | VCCR, MQPR, MQPR, pred_basic_u, i32imm, VCCR, GPRlr, |
| 28414 | /* MVE_VCMPu32r */ |
| 28415 | VCCR, MQPR, GPRwithZR, pred_basic_u, i32imm, VCCR, GPRlr, |
| 28416 | /* MVE_VCMPu8 */ |
| 28417 | VCCR, MQPR, MQPR, pred_basic_u, i32imm, VCCR, GPRlr, |
| 28418 | /* MVE_VCMPu8r */ |
| 28419 | VCCR, MQPR, GPRwithZR, pred_basic_u, i32imm, VCCR, GPRlr, |
| 28420 | /* MVE_VCMULf16 */ |
| 28421 | MQPR, MQPR, MQPR, complexrotateop, i32imm, VCCR, GPRlr, MQPR, |
| 28422 | /* MVE_VCMULf32 */ |
| 28423 | MQPR, MQPR, MQPR, complexrotateop, i32imm, VCCR, GPRlr, MQPR, |
| 28424 | /* MVE_VCTP16 */ |
| 28425 | VCCR, rGPR, i32imm, VCCR, GPRlr, |
| 28426 | /* MVE_VCTP32 */ |
| 28427 | VCCR, rGPR, i32imm, VCCR, GPRlr, |
| 28428 | /* MVE_VCTP64 */ |
| 28429 | VCCR, rGPR, i32imm, VCCR, GPRlr, |
| 28430 | /* MVE_VCTP8 */ |
| 28431 | VCCR, rGPR, i32imm, VCCR, GPRlr, |
| 28432 | /* MVE_VCVTf16f32bh */ |
| 28433 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28434 | /* MVE_VCVTf16f32th */ |
| 28435 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28436 | /* MVE_VCVTf16s16_fix */ |
| 28437 | MQPR, MQPR, -1, i32imm, VCCR, GPRlr, MQPR, |
| 28438 | /* MVE_VCVTf16s16n */ |
| 28439 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28440 | /* MVE_VCVTf16u16_fix */ |
| 28441 | MQPR, MQPR, -1, i32imm, VCCR, GPRlr, MQPR, |
| 28442 | /* MVE_VCVTf16u16n */ |
| 28443 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28444 | /* MVE_VCVTf32f16bh */ |
| 28445 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28446 | /* MVE_VCVTf32f16th */ |
| 28447 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28448 | /* MVE_VCVTf32s32_fix */ |
| 28449 | MQPR, MQPR, -1, i32imm, VCCR, GPRlr, MQPR, |
| 28450 | /* MVE_VCVTf32s32n */ |
| 28451 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28452 | /* MVE_VCVTf32u32_fix */ |
| 28453 | MQPR, MQPR, -1, i32imm, VCCR, GPRlr, MQPR, |
| 28454 | /* MVE_VCVTf32u32n */ |
| 28455 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28456 | /* MVE_VCVTs16f16_fix */ |
| 28457 | MQPR, MQPR, -1, i32imm, VCCR, GPRlr, MQPR, |
| 28458 | /* MVE_VCVTs16f16a */ |
| 28459 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28460 | /* MVE_VCVTs16f16m */ |
| 28461 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28462 | /* MVE_VCVTs16f16n */ |
| 28463 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28464 | /* MVE_VCVTs16f16p */ |
| 28465 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28466 | /* MVE_VCVTs16f16z */ |
| 28467 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28468 | /* MVE_VCVTs32f32_fix */ |
| 28469 | MQPR, MQPR, -1, i32imm, VCCR, GPRlr, MQPR, |
| 28470 | /* MVE_VCVTs32f32a */ |
| 28471 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28472 | /* MVE_VCVTs32f32m */ |
| 28473 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28474 | /* MVE_VCVTs32f32n */ |
| 28475 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28476 | /* MVE_VCVTs32f32p */ |
| 28477 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28478 | /* MVE_VCVTs32f32z */ |
| 28479 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28480 | /* MVE_VCVTu16f16_fix */ |
| 28481 | MQPR, MQPR, -1, i32imm, VCCR, GPRlr, MQPR, |
| 28482 | /* MVE_VCVTu16f16a */ |
| 28483 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28484 | /* MVE_VCVTu16f16m */ |
| 28485 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28486 | /* MVE_VCVTu16f16n */ |
| 28487 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28488 | /* MVE_VCVTu16f16p */ |
| 28489 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28490 | /* MVE_VCVTu16f16z */ |
| 28491 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28492 | /* MVE_VCVTu32f32_fix */ |
| 28493 | MQPR, MQPR, -1, i32imm, VCCR, GPRlr, MQPR, |
| 28494 | /* MVE_VCVTu32f32a */ |
| 28495 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28496 | /* MVE_VCVTu32f32m */ |
| 28497 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28498 | /* MVE_VCVTu32f32n */ |
| 28499 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28500 | /* MVE_VCVTu32f32p */ |
| 28501 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28502 | /* MVE_VCVTu32f32z */ |
| 28503 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28504 | /* MVE_VDDUPu16 */ |
| 28505 | MQPR, tGPREven, tGPREven, MVE_VIDUP_imm, i32imm, VCCR, GPRlr, MQPR, |
| 28506 | /* MVE_VDDUPu32 */ |
| 28507 | MQPR, tGPREven, tGPREven, MVE_VIDUP_imm, i32imm, VCCR, GPRlr, MQPR, |
| 28508 | /* MVE_VDDUPu8 */ |
| 28509 | MQPR, tGPREven, tGPREven, MVE_VIDUP_imm, i32imm, VCCR, GPRlr, MQPR, |
| 28510 | /* MVE_VDUP16 */ |
| 28511 | MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28512 | /* MVE_VDUP32 */ |
| 28513 | MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28514 | /* MVE_VDUP8 */ |
| 28515 | MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28516 | /* MVE_VDWDUPu16 */ |
| 28517 | MQPR, tGPREven, tGPREven, tGPROdd, MVE_VIDUP_imm, i32imm, VCCR, GPRlr, MQPR, |
| 28518 | /* MVE_VDWDUPu32 */ |
| 28519 | MQPR, tGPREven, tGPREven, tGPROdd, MVE_VIDUP_imm, i32imm, VCCR, GPRlr, MQPR, |
| 28520 | /* MVE_VDWDUPu8 */ |
| 28521 | MQPR, tGPREven, tGPREven, tGPROdd, MVE_VIDUP_imm, i32imm, VCCR, GPRlr, MQPR, |
| 28522 | /* MVE_VEOR */ |
| 28523 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28524 | /* MVE_VFMA_qr_Sf16 */ |
| 28525 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 28526 | /* MVE_VFMA_qr_Sf32 */ |
| 28527 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 28528 | /* MVE_VFMA_qr_f16 */ |
| 28529 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 28530 | /* MVE_VFMA_qr_f32 */ |
| 28531 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 28532 | /* MVE_VFMAf16 */ |
| 28533 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28534 | /* MVE_VFMAf32 */ |
| 28535 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28536 | /* MVE_VFMSf16 */ |
| 28537 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28538 | /* MVE_VFMSf32 */ |
| 28539 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28540 | /* MVE_VHADD_qr_s16 */ |
| 28541 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28542 | /* MVE_VHADD_qr_s32 */ |
| 28543 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28544 | /* MVE_VHADD_qr_s8 */ |
| 28545 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28546 | /* MVE_VHADD_qr_u16 */ |
| 28547 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28548 | /* MVE_VHADD_qr_u32 */ |
| 28549 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28550 | /* MVE_VHADD_qr_u8 */ |
| 28551 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28552 | /* MVE_VHADDs16 */ |
| 28553 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28554 | /* MVE_VHADDs32 */ |
| 28555 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28556 | /* MVE_VHADDs8 */ |
| 28557 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28558 | /* MVE_VHADDu16 */ |
| 28559 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28560 | /* MVE_VHADDu32 */ |
| 28561 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28562 | /* MVE_VHADDu8 */ |
| 28563 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28564 | /* MVE_VHCADDs16 */ |
| 28565 | MQPR, MQPR, MQPR, complexrotateopodd, i32imm, VCCR, GPRlr, MQPR, |
| 28566 | /* MVE_VHCADDs32 */ |
| 28567 | MQPR, MQPR, MQPR, complexrotateopodd, i32imm, VCCR, GPRlr, MQPR, |
| 28568 | /* MVE_VHCADDs8 */ |
| 28569 | MQPR, MQPR, MQPR, complexrotateopodd, i32imm, VCCR, GPRlr, MQPR, |
| 28570 | /* MVE_VHSUB_qr_s16 */ |
| 28571 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28572 | /* MVE_VHSUB_qr_s32 */ |
| 28573 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28574 | /* MVE_VHSUB_qr_s8 */ |
| 28575 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28576 | /* MVE_VHSUB_qr_u16 */ |
| 28577 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28578 | /* MVE_VHSUB_qr_u32 */ |
| 28579 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28580 | /* MVE_VHSUB_qr_u8 */ |
| 28581 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 28582 | /* MVE_VHSUBs16 */ |
| 28583 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28584 | /* MVE_VHSUBs32 */ |
| 28585 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28586 | /* MVE_VHSUBs8 */ |
| 28587 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28588 | /* MVE_VHSUBu16 */ |
| 28589 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28590 | /* MVE_VHSUBu32 */ |
| 28591 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28592 | /* MVE_VHSUBu8 */ |
| 28593 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28594 | /* MVE_VIDUPu16 */ |
| 28595 | MQPR, tGPREven, tGPREven, MVE_VIDUP_imm, i32imm, VCCR, GPRlr, MQPR, |
| 28596 | /* MVE_VIDUPu32 */ |
| 28597 | MQPR, tGPREven, tGPREven, MVE_VIDUP_imm, i32imm, VCCR, GPRlr, MQPR, |
| 28598 | /* MVE_VIDUPu8 */ |
| 28599 | MQPR, tGPREven, tGPREven, MVE_VIDUP_imm, i32imm, VCCR, GPRlr, MQPR, |
| 28600 | /* MVE_VIWDUPu16 */ |
| 28601 | MQPR, tGPREven, tGPREven, tGPROdd, MVE_VIDUP_imm, i32imm, VCCR, GPRlr, MQPR, |
| 28602 | /* MVE_VIWDUPu32 */ |
| 28603 | MQPR, tGPREven, tGPREven, tGPROdd, MVE_VIDUP_imm, i32imm, VCCR, GPRlr, MQPR, |
| 28604 | /* MVE_VIWDUPu8 */ |
| 28605 | MQPR, tGPREven, tGPREven, tGPROdd, MVE_VIDUP_imm, i32imm, VCCR, GPRlr, MQPR, |
| 28606 | /* MVE_VLD20_16 */ |
| 28607 | VecList2Q, VecList2Q, GPRnopc, |
| 28608 | /* MVE_VLD20_16_wb */ |
| 28609 | VecList2Q, rGPR, VecList2Q, rGPR, |
| 28610 | /* MVE_VLD20_32 */ |
| 28611 | VecList2Q, VecList2Q, GPRnopc, |
| 28612 | /* MVE_VLD20_32_wb */ |
| 28613 | VecList2Q, rGPR, VecList2Q, rGPR, |
| 28614 | /* MVE_VLD20_8 */ |
| 28615 | VecList2Q, VecList2Q, GPRnopc, |
| 28616 | /* MVE_VLD20_8_wb */ |
| 28617 | VecList2Q, rGPR, VecList2Q, rGPR, |
| 28618 | /* MVE_VLD21_16 */ |
| 28619 | VecList2Q, VecList2Q, GPRnopc, |
| 28620 | /* MVE_VLD21_16_wb */ |
| 28621 | VecList2Q, rGPR, VecList2Q, rGPR, |
| 28622 | /* MVE_VLD21_32 */ |
| 28623 | VecList2Q, VecList2Q, GPRnopc, |
| 28624 | /* MVE_VLD21_32_wb */ |
| 28625 | VecList2Q, rGPR, VecList2Q, rGPR, |
| 28626 | /* MVE_VLD21_8 */ |
| 28627 | VecList2Q, VecList2Q, GPRnopc, |
| 28628 | /* MVE_VLD21_8_wb */ |
| 28629 | VecList2Q, rGPR, VecList2Q, rGPR, |
| 28630 | /* MVE_VLD40_16 */ |
| 28631 | VecList4Q, VecList4Q, GPRnopc, |
| 28632 | /* MVE_VLD40_16_wb */ |
| 28633 | VecList4Q, rGPR, VecList4Q, rGPR, |
| 28634 | /* MVE_VLD40_32 */ |
| 28635 | VecList4Q, VecList4Q, GPRnopc, |
| 28636 | /* MVE_VLD40_32_wb */ |
| 28637 | VecList4Q, rGPR, VecList4Q, rGPR, |
| 28638 | /* MVE_VLD40_8 */ |
| 28639 | VecList4Q, VecList4Q, GPRnopc, |
| 28640 | /* MVE_VLD40_8_wb */ |
| 28641 | VecList4Q, rGPR, VecList4Q, rGPR, |
| 28642 | /* MVE_VLD41_16 */ |
| 28643 | VecList4Q, VecList4Q, GPRnopc, |
| 28644 | /* MVE_VLD41_16_wb */ |
| 28645 | VecList4Q, rGPR, VecList4Q, rGPR, |
| 28646 | /* MVE_VLD41_32 */ |
| 28647 | VecList4Q, VecList4Q, GPRnopc, |
| 28648 | /* MVE_VLD41_32_wb */ |
| 28649 | VecList4Q, rGPR, VecList4Q, rGPR, |
| 28650 | /* MVE_VLD41_8 */ |
| 28651 | VecList4Q, VecList4Q, GPRnopc, |
| 28652 | /* MVE_VLD41_8_wb */ |
| 28653 | VecList4Q, rGPR, VecList4Q, rGPR, |
| 28654 | /* MVE_VLD42_16 */ |
| 28655 | VecList4Q, VecList4Q, GPRnopc, |
| 28656 | /* MVE_VLD42_16_wb */ |
| 28657 | VecList4Q, rGPR, VecList4Q, rGPR, |
| 28658 | /* MVE_VLD42_32 */ |
| 28659 | VecList4Q, VecList4Q, GPRnopc, |
| 28660 | /* MVE_VLD42_32_wb */ |
| 28661 | VecList4Q, rGPR, VecList4Q, rGPR, |
| 28662 | /* MVE_VLD42_8 */ |
| 28663 | VecList4Q, VecList4Q, GPRnopc, |
| 28664 | /* MVE_VLD42_8_wb */ |
| 28665 | VecList4Q, rGPR, VecList4Q, rGPR, |
| 28666 | /* MVE_VLD43_16 */ |
| 28667 | VecList4Q, VecList4Q, GPRnopc, |
| 28668 | /* MVE_VLD43_16_wb */ |
| 28669 | VecList4Q, rGPR, VecList4Q, rGPR, |
| 28670 | /* MVE_VLD43_32 */ |
| 28671 | VecList4Q, VecList4Q, GPRnopc, |
| 28672 | /* MVE_VLD43_32_wb */ |
| 28673 | VecList4Q, rGPR, VecList4Q, rGPR, |
| 28674 | /* MVE_VLD43_8 */ |
| 28675 | VecList4Q, VecList4Q, GPRnopc, |
| 28676 | /* MVE_VLD43_8_wb */ |
| 28677 | VecList4Q, rGPR, VecList4Q, rGPR, |
| 28678 | /* MVE_VLDRBS16 */ |
| 28679 | MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28680 | /* MVE_VLDRBS16_post */ |
| 28681 | tGPR, MQPR, tGPR, -1, i32imm, VCCR, GPRlr, |
| 28682 | /* MVE_VLDRBS16_pre */ |
| 28683 | tGPR, MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28684 | /* MVE_VLDRBS16_rq */ |
| 28685 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28686 | /* MVE_VLDRBS32 */ |
| 28687 | MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28688 | /* MVE_VLDRBS32_post */ |
| 28689 | tGPR, MQPR, tGPR, -1, i32imm, VCCR, GPRlr, |
| 28690 | /* MVE_VLDRBS32_pre */ |
| 28691 | tGPR, MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28692 | /* MVE_VLDRBS32_rq */ |
| 28693 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28694 | /* MVE_VLDRBU16 */ |
| 28695 | MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28696 | /* MVE_VLDRBU16_post */ |
| 28697 | tGPR, MQPR, tGPR, -1, i32imm, VCCR, GPRlr, |
| 28698 | /* MVE_VLDRBU16_pre */ |
| 28699 | tGPR, MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28700 | /* MVE_VLDRBU16_rq */ |
| 28701 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28702 | /* MVE_VLDRBU32 */ |
| 28703 | MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28704 | /* MVE_VLDRBU32_post */ |
| 28705 | tGPR, MQPR, tGPR, -1, i32imm, VCCR, GPRlr, |
| 28706 | /* MVE_VLDRBU32_pre */ |
| 28707 | tGPR, MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28708 | /* MVE_VLDRBU32_rq */ |
| 28709 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28710 | /* MVE_VLDRBU8 */ |
| 28711 | MQPR, GPRnopc, i32imm, i32imm, VCCR, GPRlr, |
| 28712 | /* MVE_VLDRBU8_post */ |
| 28713 | rGPR, MQPR, rGPR, -1, i32imm, VCCR, GPRlr, |
| 28714 | /* MVE_VLDRBU8_pre */ |
| 28715 | rGPR, MQPR, rGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28716 | /* MVE_VLDRBU8_rq */ |
| 28717 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28718 | /* MVE_VLDRDU64_qi */ |
| 28719 | MQPR, MQPR, i32imm, i32imm, VCCR, GPRlr, |
| 28720 | /* MVE_VLDRDU64_qi_pre */ |
| 28721 | MQPR, MQPR, MQPR, i32imm, i32imm, VCCR, GPRlr, |
| 28722 | /* MVE_VLDRDU64_rq */ |
| 28723 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28724 | /* MVE_VLDRDU64_rq_u */ |
| 28725 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28726 | /* MVE_VLDRHS32 */ |
| 28727 | MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28728 | /* MVE_VLDRHS32_post */ |
| 28729 | tGPR, MQPR, tGPR, -1, i32imm, VCCR, GPRlr, |
| 28730 | /* MVE_VLDRHS32_pre */ |
| 28731 | tGPR, MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28732 | /* MVE_VLDRHS32_rq */ |
| 28733 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28734 | /* MVE_VLDRHS32_rq_u */ |
| 28735 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28736 | /* MVE_VLDRHU16 */ |
| 28737 | MQPR, GPRnopc, i32imm, i32imm, VCCR, GPRlr, |
| 28738 | /* MVE_VLDRHU16_post */ |
| 28739 | rGPR, MQPR, rGPR, -1, i32imm, VCCR, GPRlr, |
| 28740 | /* MVE_VLDRHU16_pre */ |
| 28741 | rGPR, MQPR, rGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28742 | /* MVE_VLDRHU16_rq */ |
| 28743 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28744 | /* MVE_VLDRHU16_rq_u */ |
| 28745 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28746 | /* MVE_VLDRHU32 */ |
| 28747 | MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28748 | /* MVE_VLDRHU32_post */ |
| 28749 | tGPR, MQPR, tGPR, -1, i32imm, VCCR, GPRlr, |
| 28750 | /* MVE_VLDRHU32_pre */ |
| 28751 | tGPR, MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28752 | /* MVE_VLDRHU32_rq */ |
| 28753 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28754 | /* MVE_VLDRHU32_rq_u */ |
| 28755 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28756 | /* MVE_VLDRWU32 */ |
| 28757 | MQPR, GPRnopc, i32imm, i32imm, VCCR, GPRlr, |
| 28758 | /* MVE_VLDRWU32_post */ |
| 28759 | rGPR, MQPR, rGPR, -1, i32imm, VCCR, GPRlr, |
| 28760 | /* MVE_VLDRWU32_pre */ |
| 28761 | rGPR, MQPR, rGPR, i32imm, i32imm, VCCR, GPRlr, |
| 28762 | /* MVE_VLDRWU32_qi */ |
| 28763 | MQPR, MQPR, i32imm, i32imm, VCCR, GPRlr, |
| 28764 | /* MVE_VLDRWU32_qi_pre */ |
| 28765 | MQPR, MQPR, MQPR, i32imm, i32imm, VCCR, GPRlr, |
| 28766 | /* MVE_VLDRWU32_rq */ |
| 28767 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28768 | /* MVE_VLDRWU32_rq_u */ |
| 28769 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 28770 | /* MVE_VMAXAVs16 */ |
| 28771 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28772 | /* MVE_VMAXAVs32 */ |
| 28773 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28774 | /* MVE_VMAXAVs8 */ |
| 28775 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28776 | /* MVE_VMAXAs16 */ |
| 28777 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28778 | /* MVE_VMAXAs32 */ |
| 28779 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28780 | /* MVE_VMAXAs8 */ |
| 28781 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28782 | /* MVE_VMAXNMAVf16 */ |
| 28783 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28784 | /* MVE_VMAXNMAVf32 */ |
| 28785 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28786 | /* MVE_VMAXNMAf16 */ |
| 28787 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28788 | /* MVE_VMAXNMAf32 */ |
| 28789 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28790 | /* MVE_VMAXNMVf16 */ |
| 28791 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28792 | /* MVE_VMAXNMVf32 */ |
| 28793 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28794 | /* MVE_VMAXNMf16 */ |
| 28795 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28796 | /* MVE_VMAXNMf32 */ |
| 28797 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28798 | /* MVE_VMAXVs16 */ |
| 28799 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28800 | /* MVE_VMAXVs32 */ |
| 28801 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28802 | /* MVE_VMAXVs8 */ |
| 28803 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28804 | /* MVE_VMAXVu16 */ |
| 28805 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28806 | /* MVE_VMAXVu32 */ |
| 28807 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28808 | /* MVE_VMAXVu8 */ |
| 28809 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28810 | /* MVE_VMAXs16 */ |
| 28811 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28812 | /* MVE_VMAXs32 */ |
| 28813 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28814 | /* MVE_VMAXs8 */ |
| 28815 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28816 | /* MVE_VMAXu16 */ |
| 28817 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28818 | /* MVE_VMAXu32 */ |
| 28819 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28820 | /* MVE_VMAXu8 */ |
| 28821 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28822 | /* MVE_VMINAVs16 */ |
| 28823 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28824 | /* MVE_VMINAVs32 */ |
| 28825 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28826 | /* MVE_VMINAVs8 */ |
| 28827 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28828 | /* MVE_VMINAs16 */ |
| 28829 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28830 | /* MVE_VMINAs32 */ |
| 28831 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28832 | /* MVE_VMINAs8 */ |
| 28833 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28834 | /* MVE_VMINNMAVf16 */ |
| 28835 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28836 | /* MVE_VMINNMAVf32 */ |
| 28837 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28838 | /* MVE_VMINNMAf16 */ |
| 28839 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28840 | /* MVE_VMINNMAf32 */ |
| 28841 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28842 | /* MVE_VMINNMVf16 */ |
| 28843 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28844 | /* MVE_VMINNMVf32 */ |
| 28845 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28846 | /* MVE_VMINNMf16 */ |
| 28847 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28848 | /* MVE_VMINNMf32 */ |
| 28849 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28850 | /* MVE_VMINVs16 */ |
| 28851 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28852 | /* MVE_VMINVs32 */ |
| 28853 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28854 | /* MVE_VMINVs8 */ |
| 28855 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28856 | /* MVE_VMINVu16 */ |
| 28857 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28858 | /* MVE_VMINVu32 */ |
| 28859 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28860 | /* MVE_VMINVu8 */ |
| 28861 | rGPR, rGPR, MQPR, i32imm, VCCR, GPRlr, |
| 28862 | /* MVE_VMINs16 */ |
| 28863 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28864 | /* MVE_VMINs32 */ |
| 28865 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28866 | /* MVE_VMINs8 */ |
| 28867 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28868 | /* MVE_VMINu16 */ |
| 28869 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28870 | /* MVE_VMINu32 */ |
| 28871 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28872 | /* MVE_VMINu8 */ |
| 28873 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28874 | /* MVE_VMLADAVas16 */ |
| 28875 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28876 | /* MVE_VMLADAVas32 */ |
| 28877 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28878 | /* MVE_VMLADAVas8 */ |
| 28879 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28880 | /* MVE_VMLADAVau16 */ |
| 28881 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28882 | /* MVE_VMLADAVau32 */ |
| 28883 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28884 | /* MVE_VMLADAVau8 */ |
| 28885 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28886 | /* MVE_VMLADAVaxs16 */ |
| 28887 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28888 | /* MVE_VMLADAVaxs32 */ |
| 28889 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28890 | /* MVE_VMLADAVaxs8 */ |
| 28891 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28892 | /* MVE_VMLADAVs16 */ |
| 28893 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28894 | /* MVE_VMLADAVs32 */ |
| 28895 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28896 | /* MVE_VMLADAVs8 */ |
| 28897 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28898 | /* MVE_VMLADAVu16 */ |
| 28899 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28900 | /* MVE_VMLADAVu32 */ |
| 28901 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28902 | /* MVE_VMLADAVu8 */ |
| 28903 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28904 | /* MVE_VMLADAVxs16 */ |
| 28905 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28906 | /* MVE_VMLADAVxs32 */ |
| 28907 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28908 | /* MVE_VMLADAVxs8 */ |
| 28909 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28910 | /* MVE_VMLALDAVas16 */ |
| 28911 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28912 | /* MVE_VMLALDAVas32 */ |
| 28913 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28914 | /* MVE_VMLALDAVau16 */ |
| 28915 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28916 | /* MVE_VMLALDAVau32 */ |
| 28917 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28918 | /* MVE_VMLALDAVaxs16 */ |
| 28919 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28920 | /* MVE_VMLALDAVaxs32 */ |
| 28921 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28922 | /* MVE_VMLALDAVs16 */ |
| 28923 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28924 | /* MVE_VMLALDAVs32 */ |
| 28925 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28926 | /* MVE_VMLALDAVu16 */ |
| 28927 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28928 | /* MVE_VMLALDAVu32 */ |
| 28929 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28930 | /* MVE_VMLALDAVxs16 */ |
| 28931 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28932 | /* MVE_VMLALDAVxs32 */ |
| 28933 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28934 | /* MVE_VMLAS_qr_i16 */ |
| 28935 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 28936 | /* MVE_VMLAS_qr_i32 */ |
| 28937 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 28938 | /* MVE_VMLAS_qr_i8 */ |
| 28939 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 28940 | /* MVE_VMLA_qr_i16 */ |
| 28941 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 28942 | /* MVE_VMLA_qr_i32 */ |
| 28943 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 28944 | /* MVE_VMLA_qr_i8 */ |
| 28945 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 28946 | /* MVE_VMLSDAVas16 */ |
| 28947 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28948 | /* MVE_VMLSDAVas32 */ |
| 28949 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28950 | /* MVE_VMLSDAVas8 */ |
| 28951 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28952 | /* MVE_VMLSDAVaxs16 */ |
| 28953 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28954 | /* MVE_VMLSDAVaxs32 */ |
| 28955 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28956 | /* MVE_VMLSDAVaxs8 */ |
| 28957 | tGPREven, tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28958 | /* MVE_VMLSDAVs16 */ |
| 28959 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28960 | /* MVE_VMLSDAVs32 */ |
| 28961 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28962 | /* MVE_VMLSDAVs8 */ |
| 28963 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28964 | /* MVE_VMLSDAVxs16 */ |
| 28965 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28966 | /* MVE_VMLSDAVxs32 */ |
| 28967 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28968 | /* MVE_VMLSDAVxs8 */ |
| 28969 | tGPREven, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28970 | /* MVE_VMLSLDAVas16 */ |
| 28971 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28972 | /* MVE_VMLSLDAVas32 */ |
| 28973 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28974 | /* MVE_VMLSLDAVaxs16 */ |
| 28975 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28976 | /* MVE_VMLSLDAVaxs32 */ |
| 28977 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28978 | /* MVE_VMLSLDAVs16 */ |
| 28979 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28980 | /* MVE_VMLSLDAVs32 */ |
| 28981 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28982 | /* MVE_VMLSLDAVxs16 */ |
| 28983 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28984 | /* MVE_VMLSLDAVxs32 */ |
| 28985 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 28986 | /* MVE_VMOVLs16bh */ |
| 28987 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28988 | /* MVE_VMOVLs16th */ |
| 28989 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28990 | /* MVE_VMOVLs8bh */ |
| 28991 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28992 | /* MVE_VMOVLs8th */ |
| 28993 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28994 | /* MVE_VMOVLu16bh */ |
| 28995 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28996 | /* MVE_VMOVLu16th */ |
| 28997 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 28998 | /* MVE_VMOVLu8bh */ |
| 28999 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29000 | /* MVE_VMOVLu8th */ |
| 29001 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29002 | /* MVE_VMOVNi16bh */ |
| 29003 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29004 | /* MVE_VMOVNi16th */ |
| 29005 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29006 | /* MVE_VMOVNi32bh */ |
| 29007 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29008 | /* MVE_VMOVNi32th */ |
| 29009 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29010 | /* MVE_VMOV_from_lane_32 */ |
| 29011 | rGPR, MQPR, i32imm, i32imm, i32imm, |
| 29012 | /* MVE_VMOV_from_lane_s16 */ |
| 29013 | rGPR, MQPR, i32imm, i32imm, i32imm, |
| 29014 | /* MVE_VMOV_from_lane_s8 */ |
| 29015 | rGPR, MQPR, i32imm, i32imm, i32imm, |
| 29016 | /* MVE_VMOV_from_lane_u16 */ |
| 29017 | rGPR, MQPR, i32imm, i32imm, i32imm, |
| 29018 | /* MVE_VMOV_from_lane_u8 */ |
| 29019 | rGPR, MQPR, i32imm, i32imm, i32imm, |
| 29020 | /* MVE_VMOV_q_rr */ |
| 29021 | MQPR, MQPR, rGPR, rGPR, i32imm, i32imm, i32imm, i32imm, |
| 29022 | /* MVE_VMOV_rr_q */ |
| 29023 | rGPR, rGPR, MQPR, i32imm, i32imm, i32imm, i32imm, |
| 29024 | /* MVE_VMOV_to_lane_16 */ |
| 29025 | MQPR, MQPR, rGPR, i32imm, i32imm, i32imm, |
| 29026 | /* MVE_VMOV_to_lane_32 */ |
| 29027 | MQPR, MQPR, rGPR, i32imm, i32imm, i32imm, |
| 29028 | /* MVE_VMOV_to_lane_8 */ |
| 29029 | MQPR, MQPR, rGPR, i32imm, i32imm, i32imm, |
| 29030 | /* MVE_VMOVimmf32 */ |
| 29031 | MQPR, nImmVMOVF32, i32imm, VCCR, GPRlr, MQPR, |
| 29032 | /* MVE_VMOVimmi16 */ |
| 29033 | MQPR, nImmSplatI16, i32imm, VCCR, GPRlr, MQPR, |
| 29034 | /* MVE_VMOVimmi32 */ |
| 29035 | MQPR, nImmVMOVI32, i32imm, VCCR, GPRlr, MQPR, |
| 29036 | /* MVE_VMOVimmi64 */ |
| 29037 | MQPR, nImmSplatI64, i32imm, VCCR, GPRlr, MQPR, |
| 29038 | /* MVE_VMOVimmi8 */ |
| 29039 | MQPR, nImmSplatI8, i32imm, VCCR, GPRlr, MQPR, |
| 29040 | /* MVE_VMULHs16 */ |
| 29041 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29042 | /* MVE_VMULHs32 */ |
| 29043 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29044 | /* MVE_VMULHs8 */ |
| 29045 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29046 | /* MVE_VMULHu16 */ |
| 29047 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29048 | /* MVE_VMULHu32 */ |
| 29049 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29050 | /* MVE_VMULHu8 */ |
| 29051 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29052 | /* MVE_VMULLBp16 */ |
| 29053 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29054 | /* MVE_VMULLBp8 */ |
| 29055 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29056 | /* MVE_VMULLBs16 */ |
| 29057 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29058 | /* MVE_VMULLBs32 */ |
| 29059 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29060 | /* MVE_VMULLBs8 */ |
| 29061 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29062 | /* MVE_VMULLBu16 */ |
| 29063 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29064 | /* MVE_VMULLBu32 */ |
| 29065 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29066 | /* MVE_VMULLBu8 */ |
| 29067 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29068 | /* MVE_VMULLTp16 */ |
| 29069 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29070 | /* MVE_VMULLTp8 */ |
| 29071 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29072 | /* MVE_VMULLTs16 */ |
| 29073 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29074 | /* MVE_VMULLTs32 */ |
| 29075 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29076 | /* MVE_VMULLTs8 */ |
| 29077 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29078 | /* MVE_VMULLTu16 */ |
| 29079 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29080 | /* MVE_VMULLTu32 */ |
| 29081 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29082 | /* MVE_VMULLTu8 */ |
| 29083 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29084 | /* MVE_VMUL_qr_f16 */ |
| 29085 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29086 | /* MVE_VMUL_qr_f32 */ |
| 29087 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29088 | /* MVE_VMUL_qr_i16 */ |
| 29089 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29090 | /* MVE_VMUL_qr_i32 */ |
| 29091 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29092 | /* MVE_VMUL_qr_i8 */ |
| 29093 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29094 | /* MVE_VMULf16 */ |
| 29095 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29096 | /* MVE_VMULf32 */ |
| 29097 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29098 | /* MVE_VMULi16 */ |
| 29099 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29100 | /* MVE_VMULi32 */ |
| 29101 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29102 | /* MVE_VMULi8 */ |
| 29103 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29104 | /* MVE_VMVN */ |
| 29105 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29106 | /* MVE_VMVNimmi16 */ |
| 29107 | MQPR, nImmSplatI16, i32imm, VCCR, GPRlr, MQPR, |
| 29108 | /* MVE_VMVNimmi32 */ |
| 29109 | MQPR, nImmVMOVI32, i32imm, VCCR, GPRlr, MQPR, |
| 29110 | /* MVE_VNEGf16 */ |
| 29111 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29112 | /* MVE_VNEGf32 */ |
| 29113 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29114 | /* MVE_VNEGs16 */ |
| 29115 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29116 | /* MVE_VNEGs32 */ |
| 29117 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29118 | /* MVE_VNEGs8 */ |
| 29119 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29120 | /* MVE_VORN */ |
| 29121 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29122 | /* MVE_VORR */ |
| 29123 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29124 | /* MVE_VORRimmi16 */ |
| 29125 | MQPR, MQPR, nImmSplatI16, i32imm, VCCR, GPRlr, |
| 29126 | /* MVE_VORRimmi32 */ |
| 29127 | MQPR, MQPR, nImmSplatI32, i32imm, VCCR, GPRlr, |
| 29128 | /* MVE_VPNOT */ |
| 29129 | VCCR, VCCR, i32imm, VCCR, GPRlr, |
| 29130 | /* MVE_VPSEL */ |
| 29131 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29132 | /* MVE_VPST */ |
| 29133 | vpt_mask, |
| 29134 | /* MVE_VPTv16i8 */ |
| 29135 | vpt_mask, MQPR, MQPR, pred_basic_i, |
| 29136 | /* MVE_VPTv16i8r */ |
| 29137 | vpt_mask, MQPR, GPRwithZR, pred_basic_i, |
| 29138 | /* MVE_VPTv16s8 */ |
| 29139 | vpt_mask, MQPR, MQPR, pred_basic_s, |
| 29140 | /* MVE_VPTv16s8r */ |
| 29141 | vpt_mask, MQPR, GPRwithZR, pred_basic_s, |
| 29142 | /* MVE_VPTv16u8 */ |
| 29143 | vpt_mask, MQPR, MQPR, pred_basic_u, |
| 29144 | /* MVE_VPTv16u8r */ |
| 29145 | vpt_mask, MQPR, GPRwithZR, pred_basic_u, |
| 29146 | /* MVE_VPTv4f32 */ |
| 29147 | vpt_mask, MQPR, MQPR, pred_basic_fp, |
| 29148 | /* MVE_VPTv4f32r */ |
| 29149 | vpt_mask, MQPR, GPRwithZR, pred_basic_fp, |
| 29150 | /* MVE_VPTv4i32 */ |
| 29151 | vpt_mask, MQPR, MQPR, pred_basic_i, |
| 29152 | /* MVE_VPTv4i32r */ |
| 29153 | vpt_mask, MQPR, GPRwithZR, pred_basic_i, |
| 29154 | /* MVE_VPTv4s32 */ |
| 29155 | vpt_mask, MQPR, MQPR, pred_basic_s, |
| 29156 | /* MVE_VPTv4s32r */ |
| 29157 | vpt_mask, MQPR, GPRwithZR, pred_basic_s, |
| 29158 | /* MVE_VPTv4u32 */ |
| 29159 | vpt_mask, MQPR, MQPR, pred_basic_u, |
| 29160 | /* MVE_VPTv4u32r */ |
| 29161 | vpt_mask, MQPR, GPRwithZR, pred_basic_u, |
| 29162 | /* MVE_VPTv8f16 */ |
| 29163 | vpt_mask, MQPR, MQPR, pred_basic_fp, |
| 29164 | /* MVE_VPTv8f16r */ |
| 29165 | vpt_mask, MQPR, GPRwithZR, pred_basic_fp, |
| 29166 | /* MVE_VPTv8i16 */ |
| 29167 | vpt_mask, MQPR, MQPR, pred_basic_i, |
| 29168 | /* MVE_VPTv8i16r */ |
| 29169 | vpt_mask, MQPR, GPRwithZR, pred_basic_i, |
| 29170 | /* MVE_VPTv8s16 */ |
| 29171 | vpt_mask, MQPR, MQPR, pred_basic_s, |
| 29172 | /* MVE_VPTv8s16r */ |
| 29173 | vpt_mask, MQPR, GPRwithZR, pred_basic_s, |
| 29174 | /* MVE_VPTv8u16 */ |
| 29175 | vpt_mask, MQPR, MQPR, pred_basic_u, |
| 29176 | /* MVE_VPTv8u16r */ |
| 29177 | vpt_mask, MQPR, GPRwithZR, pred_basic_u, |
| 29178 | /* MVE_VQABSs16 */ |
| 29179 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29180 | /* MVE_VQABSs32 */ |
| 29181 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29182 | /* MVE_VQABSs8 */ |
| 29183 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29184 | /* MVE_VQADD_qr_s16 */ |
| 29185 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29186 | /* MVE_VQADD_qr_s32 */ |
| 29187 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29188 | /* MVE_VQADD_qr_s8 */ |
| 29189 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29190 | /* MVE_VQADD_qr_u16 */ |
| 29191 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29192 | /* MVE_VQADD_qr_u32 */ |
| 29193 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29194 | /* MVE_VQADD_qr_u8 */ |
| 29195 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29196 | /* MVE_VQADDs16 */ |
| 29197 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29198 | /* MVE_VQADDs32 */ |
| 29199 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29200 | /* MVE_VQADDs8 */ |
| 29201 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29202 | /* MVE_VQADDu16 */ |
| 29203 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29204 | /* MVE_VQADDu32 */ |
| 29205 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29206 | /* MVE_VQADDu8 */ |
| 29207 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29208 | /* MVE_VQDMLADHXs16 */ |
| 29209 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29210 | /* MVE_VQDMLADHXs32 */ |
| 29211 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29212 | /* MVE_VQDMLADHXs8 */ |
| 29213 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29214 | /* MVE_VQDMLADHs16 */ |
| 29215 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29216 | /* MVE_VQDMLADHs32 */ |
| 29217 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29218 | /* MVE_VQDMLADHs8 */ |
| 29219 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29220 | /* MVE_VQDMLAH_qrs16 */ |
| 29221 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29222 | /* MVE_VQDMLAH_qrs32 */ |
| 29223 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29224 | /* MVE_VQDMLAH_qrs8 */ |
| 29225 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29226 | /* MVE_VQDMLASH_qrs16 */ |
| 29227 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29228 | /* MVE_VQDMLASH_qrs32 */ |
| 29229 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29230 | /* MVE_VQDMLASH_qrs8 */ |
| 29231 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29232 | /* MVE_VQDMLSDHXs16 */ |
| 29233 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29234 | /* MVE_VQDMLSDHXs32 */ |
| 29235 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29236 | /* MVE_VQDMLSDHXs8 */ |
| 29237 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29238 | /* MVE_VQDMLSDHs16 */ |
| 29239 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29240 | /* MVE_VQDMLSDHs32 */ |
| 29241 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29242 | /* MVE_VQDMLSDHs8 */ |
| 29243 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29244 | /* MVE_VQDMULH_qr_s16 */ |
| 29245 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29246 | /* MVE_VQDMULH_qr_s32 */ |
| 29247 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29248 | /* MVE_VQDMULH_qr_s8 */ |
| 29249 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29250 | /* MVE_VQDMULHi16 */ |
| 29251 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29252 | /* MVE_VQDMULHi32 */ |
| 29253 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29254 | /* MVE_VQDMULHi8 */ |
| 29255 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29256 | /* MVE_VQDMULL_qr_s16bh */ |
| 29257 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29258 | /* MVE_VQDMULL_qr_s16th */ |
| 29259 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29260 | /* MVE_VQDMULL_qr_s32bh */ |
| 29261 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29262 | /* MVE_VQDMULL_qr_s32th */ |
| 29263 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29264 | /* MVE_VQDMULLs16bh */ |
| 29265 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29266 | /* MVE_VQDMULLs16th */ |
| 29267 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29268 | /* MVE_VQDMULLs32bh */ |
| 29269 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29270 | /* MVE_VQDMULLs32th */ |
| 29271 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29272 | /* MVE_VQMOVNs16bh */ |
| 29273 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29274 | /* MVE_VQMOVNs16th */ |
| 29275 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29276 | /* MVE_VQMOVNs32bh */ |
| 29277 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29278 | /* MVE_VQMOVNs32th */ |
| 29279 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29280 | /* MVE_VQMOVNu16bh */ |
| 29281 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29282 | /* MVE_VQMOVNu16th */ |
| 29283 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29284 | /* MVE_VQMOVNu32bh */ |
| 29285 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29286 | /* MVE_VQMOVNu32th */ |
| 29287 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29288 | /* MVE_VQMOVUNs16bh */ |
| 29289 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29290 | /* MVE_VQMOVUNs16th */ |
| 29291 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29292 | /* MVE_VQMOVUNs32bh */ |
| 29293 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29294 | /* MVE_VQMOVUNs32th */ |
| 29295 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29296 | /* MVE_VQNEGs16 */ |
| 29297 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29298 | /* MVE_VQNEGs32 */ |
| 29299 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29300 | /* MVE_VQNEGs8 */ |
| 29301 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29302 | /* MVE_VQRDMLADHXs16 */ |
| 29303 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29304 | /* MVE_VQRDMLADHXs32 */ |
| 29305 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29306 | /* MVE_VQRDMLADHXs8 */ |
| 29307 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29308 | /* MVE_VQRDMLADHs16 */ |
| 29309 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29310 | /* MVE_VQRDMLADHs32 */ |
| 29311 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29312 | /* MVE_VQRDMLADHs8 */ |
| 29313 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29314 | /* MVE_VQRDMLAH_qrs16 */ |
| 29315 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29316 | /* MVE_VQRDMLAH_qrs32 */ |
| 29317 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29318 | /* MVE_VQRDMLAH_qrs8 */ |
| 29319 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29320 | /* MVE_VQRDMLASH_qrs16 */ |
| 29321 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29322 | /* MVE_VQRDMLASH_qrs32 */ |
| 29323 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29324 | /* MVE_VQRDMLASH_qrs8 */ |
| 29325 | MQPR, MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29326 | /* MVE_VQRDMLSDHXs16 */ |
| 29327 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29328 | /* MVE_VQRDMLSDHXs32 */ |
| 29329 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29330 | /* MVE_VQRDMLSDHXs8 */ |
| 29331 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29332 | /* MVE_VQRDMLSDHs16 */ |
| 29333 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29334 | /* MVE_VQRDMLSDHs32 */ |
| 29335 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29336 | /* MVE_VQRDMLSDHs8 */ |
| 29337 | MQPR, MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29338 | /* MVE_VQRDMULH_qr_s16 */ |
| 29339 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29340 | /* MVE_VQRDMULH_qr_s32 */ |
| 29341 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29342 | /* MVE_VQRDMULH_qr_s8 */ |
| 29343 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29344 | /* MVE_VQRDMULHi16 */ |
| 29345 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29346 | /* MVE_VQRDMULHi32 */ |
| 29347 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29348 | /* MVE_VQRDMULHi8 */ |
| 29349 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29350 | /* MVE_VQRSHL_by_vecs16 */ |
| 29351 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29352 | /* MVE_VQRSHL_by_vecs32 */ |
| 29353 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29354 | /* MVE_VQRSHL_by_vecs8 */ |
| 29355 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29356 | /* MVE_VQRSHL_by_vecu16 */ |
| 29357 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29358 | /* MVE_VQRSHL_by_vecu32 */ |
| 29359 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29360 | /* MVE_VQRSHL_by_vecu8 */ |
| 29361 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29362 | /* MVE_VQRSHL_qrs16 */ |
| 29363 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29364 | /* MVE_VQRSHL_qrs32 */ |
| 29365 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29366 | /* MVE_VQRSHL_qrs8 */ |
| 29367 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29368 | /* MVE_VQRSHL_qru16 */ |
| 29369 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29370 | /* MVE_VQRSHL_qru32 */ |
| 29371 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29372 | /* MVE_VQRSHL_qru8 */ |
| 29373 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29374 | /* MVE_VQRSHRNbhs16 */ |
| 29375 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29376 | /* MVE_VQRSHRNbhs32 */ |
| 29377 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29378 | /* MVE_VQRSHRNbhu16 */ |
| 29379 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29380 | /* MVE_VQRSHRNbhu32 */ |
| 29381 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29382 | /* MVE_VQRSHRNths16 */ |
| 29383 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29384 | /* MVE_VQRSHRNths32 */ |
| 29385 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29386 | /* MVE_VQRSHRNthu16 */ |
| 29387 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29388 | /* MVE_VQRSHRNthu32 */ |
| 29389 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29390 | /* MVE_VQRSHRUNs16bh */ |
| 29391 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29392 | /* MVE_VQRSHRUNs16th */ |
| 29393 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29394 | /* MVE_VQRSHRUNs32bh */ |
| 29395 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29396 | /* MVE_VQRSHRUNs32th */ |
| 29397 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29398 | /* MVE_VQSHLU_imms16 */ |
| 29399 | MQPR, MQPR, imm0_15, i32imm, VCCR, GPRlr, MQPR, |
| 29400 | /* MVE_VQSHLU_imms32 */ |
| 29401 | MQPR, MQPR, imm0_31, i32imm, VCCR, GPRlr, MQPR, |
| 29402 | /* MVE_VQSHLU_imms8 */ |
| 29403 | MQPR, MQPR, imm0_7, i32imm, VCCR, GPRlr, MQPR, |
| 29404 | /* MVE_VQSHL_by_vecs16 */ |
| 29405 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29406 | /* MVE_VQSHL_by_vecs32 */ |
| 29407 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29408 | /* MVE_VQSHL_by_vecs8 */ |
| 29409 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29410 | /* MVE_VQSHL_by_vecu16 */ |
| 29411 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29412 | /* MVE_VQSHL_by_vecu32 */ |
| 29413 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29414 | /* MVE_VQSHL_by_vecu8 */ |
| 29415 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29416 | /* MVE_VQSHL_qrs16 */ |
| 29417 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29418 | /* MVE_VQSHL_qrs32 */ |
| 29419 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29420 | /* MVE_VQSHL_qrs8 */ |
| 29421 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29422 | /* MVE_VQSHL_qru16 */ |
| 29423 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29424 | /* MVE_VQSHL_qru32 */ |
| 29425 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29426 | /* MVE_VQSHL_qru8 */ |
| 29427 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29428 | /* MVE_VQSHLimms16 */ |
| 29429 | MQPR, MQPR, imm0_15, i32imm, VCCR, GPRlr, MQPR, |
| 29430 | /* MVE_VQSHLimms32 */ |
| 29431 | MQPR, MQPR, imm0_31, i32imm, VCCR, GPRlr, MQPR, |
| 29432 | /* MVE_VQSHLimms8 */ |
| 29433 | MQPR, MQPR, imm0_7, i32imm, VCCR, GPRlr, MQPR, |
| 29434 | /* MVE_VQSHLimmu16 */ |
| 29435 | MQPR, MQPR, imm0_15, i32imm, VCCR, GPRlr, MQPR, |
| 29436 | /* MVE_VQSHLimmu32 */ |
| 29437 | MQPR, MQPR, imm0_31, i32imm, VCCR, GPRlr, MQPR, |
| 29438 | /* MVE_VQSHLimmu8 */ |
| 29439 | MQPR, MQPR, imm0_7, i32imm, VCCR, GPRlr, MQPR, |
| 29440 | /* MVE_VQSHRNbhs16 */ |
| 29441 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29442 | /* MVE_VQSHRNbhs32 */ |
| 29443 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29444 | /* MVE_VQSHRNbhu16 */ |
| 29445 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29446 | /* MVE_VQSHRNbhu32 */ |
| 29447 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29448 | /* MVE_VQSHRNths16 */ |
| 29449 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29450 | /* MVE_VQSHRNths32 */ |
| 29451 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29452 | /* MVE_VQSHRNthu16 */ |
| 29453 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29454 | /* MVE_VQSHRNthu32 */ |
| 29455 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29456 | /* MVE_VQSHRUNs16bh */ |
| 29457 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29458 | /* MVE_VQSHRUNs16th */ |
| 29459 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29460 | /* MVE_VQSHRUNs32bh */ |
| 29461 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29462 | /* MVE_VQSHRUNs32th */ |
| 29463 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29464 | /* MVE_VQSUB_qr_s16 */ |
| 29465 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29466 | /* MVE_VQSUB_qr_s32 */ |
| 29467 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29468 | /* MVE_VQSUB_qr_s8 */ |
| 29469 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29470 | /* MVE_VQSUB_qr_u16 */ |
| 29471 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29472 | /* MVE_VQSUB_qr_u32 */ |
| 29473 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29474 | /* MVE_VQSUB_qr_u8 */ |
| 29475 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29476 | /* MVE_VQSUBs16 */ |
| 29477 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29478 | /* MVE_VQSUBs32 */ |
| 29479 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29480 | /* MVE_VQSUBs8 */ |
| 29481 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29482 | /* MVE_VQSUBu16 */ |
| 29483 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29484 | /* MVE_VQSUBu32 */ |
| 29485 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29486 | /* MVE_VQSUBu8 */ |
| 29487 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29488 | /* MVE_VREV16_8 */ |
| 29489 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29490 | /* MVE_VREV32_16 */ |
| 29491 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29492 | /* MVE_VREV32_8 */ |
| 29493 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29494 | /* MVE_VREV64_16 */ |
| 29495 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29496 | /* MVE_VREV64_32 */ |
| 29497 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29498 | /* MVE_VREV64_8 */ |
| 29499 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29500 | /* MVE_VRHADDs16 */ |
| 29501 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29502 | /* MVE_VRHADDs32 */ |
| 29503 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29504 | /* MVE_VRHADDs8 */ |
| 29505 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29506 | /* MVE_VRHADDu16 */ |
| 29507 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29508 | /* MVE_VRHADDu32 */ |
| 29509 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29510 | /* MVE_VRHADDu8 */ |
| 29511 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29512 | /* MVE_VRINTf16A */ |
| 29513 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29514 | /* MVE_VRINTf16M */ |
| 29515 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29516 | /* MVE_VRINTf16N */ |
| 29517 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29518 | /* MVE_VRINTf16P */ |
| 29519 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29520 | /* MVE_VRINTf16X */ |
| 29521 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29522 | /* MVE_VRINTf16Z */ |
| 29523 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29524 | /* MVE_VRINTf32A */ |
| 29525 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29526 | /* MVE_VRINTf32M */ |
| 29527 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29528 | /* MVE_VRINTf32N */ |
| 29529 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29530 | /* MVE_VRINTf32P */ |
| 29531 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29532 | /* MVE_VRINTf32X */ |
| 29533 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29534 | /* MVE_VRINTf32Z */ |
| 29535 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29536 | /* MVE_VRMLALDAVHas32 */ |
| 29537 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29538 | /* MVE_VRMLALDAVHau32 */ |
| 29539 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29540 | /* MVE_VRMLALDAVHaxs32 */ |
| 29541 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29542 | /* MVE_VRMLALDAVHs32 */ |
| 29543 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29544 | /* MVE_VRMLALDAVHu32 */ |
| 29545 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29546 | /* MVE_VRMLALDAVHxs32 */ |
| 29547 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29548 | /* MVE_VRMLSLDAVHas32 */ |
| 29549 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29550 | /* MVE_VRMLSLDAVHaxs32 */ |
| 29551 | tGPREven, tGPROdd, tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29552 | /* MVE_VRMLSLDAVHs32 */ |
| 29553 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29554 | /* MVE_VRMLSLDAVHxs32 */ |
| 29555 | tGPREven, tGPROdd, MQPR, MQPR, i32imm, VCCR, GPRlr, |
| 29556 | /* MVE_VRMULHs16 */ |
| 29557 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29558 | /* MVE_VRMULHs32 */ |
| 29559 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29560 | /* MVE_VRMULHs8 */ |
| 29561 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29562 | /* MVE_VRMULHu16 */ |
| 29563 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29564 | /* MVE_VRMULHu32 */ |
| 29565 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29566 | /* MVE_VRMULHu8 */ |
| 29567 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29568 | /* MVE_VRSHL_by_vecs16 */ |
| 29569 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29570 | /* MVE_VRSHL_by_vecs32 */ |
| 29571 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29572 | /* MVE_VRSHL_by_vecs8 */ |
| 29573 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29574 | /* MVE_VRSHL_by_vecu16 */ |
| 29575 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29576 | /* MVE_VRSHL_by_vecu32 */ |
| 29577 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29578 | /* MVE_VRSHL_by_vecu8 */ |
| 29579 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29580 | /* MVE_VRSHL_qrs16 */ |
| 29581 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29582 | /* MVE_VRSHL_qrs32 */ |
| 29583 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29584 | /* MVE_VRSHL_qrs8 */ |
| 29585 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29586 | /* MVE_VRSHL_qru16 */ |
| 29587 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29588 | /* MVE_VRSHL_qru32 */ |
| 29589 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29590 | /* MVE_VRSHL_qru8 */ |
| 29591 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29592 | /* MVE_VRSHRNi16bh */ |
| 29593 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29594 | /* MVE_VRSHRNi16th */ |
| 29595 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29596 | /* MVE_VRSHRNi32bh */ |
| 29597 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29598 | /* MVE_VRSHRNi32th */ |
| 29599 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29600 | /* MVE_VRSHR_imms16 */ |
| 29601 | MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, MQPR, |
| 29602 | /* MVE_VRSHR_imms32 */ |
| 29603 | MQPR, MQPR, shr_imm32, i32imm, VCCR, GPRlr, MQPR, |
| 29604 | /* MVE_VRSHR_imms8 */ |
| 29605 | MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, MQPR, |
| 29606 | /* MVE_VRSHR_immu16 */ |
| 29607 | MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, MQPR, |
| 29608 | /* MVE_VRSHR_immu32 */ |
| 29609 | MQPR, MQPR, shr_imm32, i32imm, VCCR, GPRlr, MQPR, |
| 29610 | /* MVE_VRSHR_immu8 */ |
| 29611 | MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, MQPR, |
| 29612 | /* MVE_VSBC */ |
| 29613 | MQPR, cl_FPSCR_NZCV, MQPR, MQPR, cl_FPSCR_NZCV, i32imm, VCCR, GPRlr, MQPR, |
| 29614 | /* MVE_VSBCI */ |
| 29615 | MQPR, cl_FPSCR_NZCV, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29616 | /* MVE_VSHLC */ |
| 29617 | rGPR, MQPR, MQPR, rGPR, long_shift, i32imm, VCCR, GPRlr, |
| 29618 | /* MVE_VSHLL_imms16bh */ |
| 29619 | MQPR, MQPR, mve_shift_imm1_15, i32imm, VCCR, GPRlr, MQPR, |
| 29620 | /* MVE_VSHLL_imms16th */ |
| 29621 | MQPR, MQPR, mve_shift_imm1_15, i32imm, VCCR, GPRlr, MQPR, |
| 29622 | /* MVE_VSHLL_imms8bh */ |
| 29623 | MQPR, MQPR, mve_shift_imm1_7, i32imm, VCCR, GPRlr, MQPR, |
| 29624 | /* MVE_VSHLL_imms8th */ |
| 29625 | MQPR, MQPR, mve_shift_imm1_7, i32imm, VCCR, GPRlr, MQPR, |
| 29626 | /* MVE_VSHLL_immu16bh */ |
| 29627 | MQPR, MQPR, mve_shift_imm1_15, i32imm, VCCR, GPRlr, MQPR, |
| 29628 | /* MVE_VSHLL_immu16th */ |
| 29629 | MQPR, MQPR, mve_shift_imm1_15, i32imm, VCCR, GPRlr, MQPR, |
| 29630 | /* MVE_VSHLL_immu8bh */ |
| 29631 | MQPR, MQPR, mve_shift_imm1_7, i32imm, VCCR, GPRlr, MQPR, |
| 29632 | /* MVE_VSHLL_immu8th */ |
| 29633 | MQPR, MQPR, mve_shift_imm1_7, i32imm, VCCR, GPRlr, MQPR, |
| 29634 | /* MVE_VSHLL_lws16bh */ |
| 29635 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29636 | /* MVE_VSHLL_lws16th */ |
| 29637 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29638 | /* MVE_VSHLL_lws8bh */ |
| 29639 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29640 | /* MVE_VSHLL_lws8th */ |
| 29641 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29642 | /* MVE_VSHLL_lwu16bh */ |
| 29643 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29644 | /* MVE_VSHLL_lwu16th */ |
| 29645 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29646 | /* MVE_VSHLL_lwu8bh */ |
| 29647 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29648 | /* MVE_VSHLL_lwu8th */ |
| 29649 | MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29650 | /* MVE_VSHL_by_vecs16 */ |
| 29651 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29652 | /* MVE_VSHL_by_vecs32 */ |
| 29653 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29654 | /* MVE_VSHL_by_vecs8 */ |
| 29655 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29656 | /* MVE_VSHL_by_vecu16 */ |
| 29657 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29658 | /* MVE_VSHL_by_vecu32 */ |
| 29659 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29660 | /* MVE_VSHL_by_vecu8 */ |
| 29661 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29662 | /* MVE_VSHL_immi16 */ |
| 29663 | MQPR, MQPR, imm0_15, i32imm, VCCR, GPRlr, MQPR, |
| 29664 | /* MVE_VSHL_immi32 */ |
| 29665 | MQPR, MQPR, imm0_31, i32imm, VCCR, GPRlr, MQPR, |
| 29666 | /* MVE_VSHL_immi8 */ |
| 29667 | MQPR, MQPR, imm0_7, i32imm, VCCR, GPRlr, MQPR, |
| 29668 | /* MVE_VSHL_qrs16 */ |
| 29669 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29670 | /* MVE_VSHL_qrs32 */ |
| 29671 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29672 | /* MVE_VSHL_qrs8 */ |
| 29673 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29674 | /* MVE_VSHL_qru16 */ |
| 29675 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29676 | /* MVE_VSHL_qru32 */ |
| 29677 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29678 | /* MVE_VSHL_qru8 */ |
| 29679 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, |
| 29680 | /* MVE_VSHRNi16bh */ |
| 29681 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29682 | /* MVE_VSHRNi16th */ |
| 29683 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29684 | /* MVE_VSHRNi32bh */ |
| 29685 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29686 | /* MVE_VSHRNi32th */ |
| 29687 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29688 | /* MVE_VSHR_imms16 */ |
| 29689 | MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, MQPR, |
| 29690 | /* MVE_VSHR_imms32 */ |
| 29691 | MQPR, MQPR, shr_imm32, i32imm, VCCR, GPRlr, MQPR, |
| 29692 | /* MVE_VSHR_imms8 */ |
| 29693 | MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, MQPR, |
| 29694 | /* MVE_VSHR_immu16 */ |
| 29695 | MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, MQPR, |
| 29696 | /* MVE_VSHR_immu32 */ |
| 29697 | MQPR, MQPR, shr_imm32, i32imm, VCCR, GPRlr, MQPR, |
| 29698 | /* MVE_VSHR_immu8 */ |
| 29699 | MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, MQPR, |
| 29700 | /* MVE_VSLIimm16 */ |
| 29701 | MQPR, MQPR, MQPR, imm0_15, i32imm, VCCR, GPRlr, |
| 29702 | /* MVE_VSLIimm32 */ |
| 29703 | MQPR, MQPR, MQPR, imm0_31, i32imm, VCCR, GPRlr, |
| 29704 | /* MVE_VSLIimm8 */ |
| 29705 | MQPR, MQPR, MQPR, imm0_7, i32imm, VCCR, GPRlr, |
| 29706 | /* MVE_VSRIimm16 */ |
| 29707 | MQPR, MQPR, MQPR, shr_imm16, i32imm, VCCR, GPRlr, |
| 29708 | /* MVE_VSRIimm32 */ |
| 29709 | MQPR, MQPR, MQPR, shr_imm32, i32imm, VCCR, GPRlr, |
| 29710 | /* MVE_VSRIimm8 */ |
| 29711 | MQPR, MQPR, MQPR, shr_imm8, i32imm, VCCR, GPRlr, |
| 29712 | /* MVE_VST20_16 */ |
| 29713 | VecList2Q, GPRnopc, |
| 29714 | /* MVE_VST20_16_wb */ |
| 29715 | rGPR, VecList2Q, rGPR, |
| 29716 | /* MVE_VST20_32 */ |
| 29717 | VecList2Q, GPRnopc, |
| 29718 | /* MVE_VST20_32_wb */ |
| 29719 | rGPR, VecList2Q, rGPR, |
| 29720 | /* MVE_VST20_8 */ |
| 29721 | VecList2Q, GPRnopc, |
| 29722 | /* MVE_VST20_8_wb */ |
| 29723 | rGPR, VecList2Q, rGPR, |
| 29724 | /* MVE_VST21_16 */ |
| 29725 | VecList2Q, GPRnopc, |
| 29726 | /* MVE_VST21_16_wb */ |
| 29727 | rGPR, VecList2Q, rGPR, |
| 29728 | /* MVE_VST21_32 */ |
| 29729 | VecList2Q, GPRnopc, |
| 29730 | /* MVE_VST21_32_wb */ |
| 29731 | rGPR, VecList2Q, rGPR, |
| 29732 | /* MVE_VST21_8 */ |
| 29733 | VecList2Q, GPRnopc, |
| 29734 | /* MVE_VST21_8_wb */ |
| 29735 | rGPR, VecList2Q, rGPR, |
| 29736 | /* MVE_VST40_16 */ |
| 29737 | VecList4Q, GPRnopc, |
| 29738 | /* MVE_VST40_16_wb */ |
| 29739 | rGPR, VecList4Q, rGPR, |
| 29740 | /* MVE_VST40_32 */ |
| 29741 | VecList4Q, GPRnopc, |
| 29742 | /* MVE_VST40_32_wb */ |
| 29743 | rGPR, VecList4Q, rGPR, |
| 29744 | /* MVE_VST40_8 */ |
| 29745 | VecList4Q, GPRnopc, |
| 29746 | /* MVE_VST40_8_wb */ |
| 29747 | rGPR, VecList4Q, rGPR, |
| 29748 | /* MVE_VST41_16 */ |
| 29749 | VecList4Q, GPRnopc, |
| 29750 | /* MVE_VST41_16_wb */ |
| 29751 | rGPR, VecList4Q, rGPR, |
| 29752 | /* MVE_VST41_32 */ |
| 29753 | VecList4Q, GPRnopc, |
| 29754 | /* MVE_VST41_32_wb */ |
| 29755 | rGPR, VecList4Q, rGPR, |
| 29756 | /* MVE_VST41_8 */ |
| 29757 | VecList4Q, GPRnopc, |
| 29758 | /* MVE_VST41_8_wb */ |
| 29759 | rGPR, VecList4Q, rGPR, |
| 29760 | /* MVE_VST42_16 */ |
| 29761 | VecList4Q, GPRnopc, |
| 29762 | /* MVE_VST42_16_wb */ |
| 29763 | rGPR, VecList4Q, rGPR, |
| 29764 | /* MVE_VST42_32 */ |
| 29765 | VecList4Q, GPRnopc, |
| 29766 | /* MVE_VST42_32_wb */ |
| 29767 | rGPR, VecList4Q, rGPR, |
| 29768 | /* MVE_VST42_8 */ |
| 29769 | VecList4Q, GPRnopc, |
| 29770 | /* MVE_VST42_8_wb */ |
| 29771 | rGPR, VecList4Q, rGPR, |
| 29772 | /* MVE_VST43_16 */ |
| 29773 | VecList4Q, GPRnopc, |
| 29774 | /* MVE_VST43_16_wb */ |
| 29775 | rGPR, VecList4Q, rGPR, |
| 29776 | /* MVE_VST43_32 */ |
| 29777 | VecList4Q, GPRnopc, |
| 29778 | /* MVE_VST43_32_wb */ |
| 29779 | rGPR, VecList4Q, rGPR, |
| 29780 | /* MVE_VST43_8 */ |
| 29781 | VecList4Q, GPRnopc, |
| 29782 | /* MVE_VST43_8_wb */ |
| 29783 | rGPR, VecList4Q, rGPR, |
| 29784 | /* MVE_VSTRB16 */ |
| 29785 | MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 29786 | /* MVE_VSTRB16_post */ |
| 29787 | tGPR, MQPR, tGPR, -1, i32imm, VCCR, GPRlr, |
| 29788 | /* MVE_VSTRB16_pre */ |
| 29789 | tGPR, MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 29790 | /* MVE_VSTRB16_rq */ |
| 29791 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 29792 | /* MVE_VSTRB32 */ |
| 29793 | MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 29794 | /* MVE_VSTRB32_post */ |
| 29795 | tGPR, MQPR, tGPR, -1, i32imm, VCCR, GPRlr, |
| 29796 | /* MVE_VSTRB32_pre */ |
| 29797 | tGPR, MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 29798 | /* MVE_VSTRB32_rq */ |
| 29799 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 29800 | /* MVE_VSTRB8_rq */ |
| 29801 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 29802 | /* MVE_VSTRBU8 */ |
| 29803 | MQPR, GPRnopc, i32imm, i32imm, VCCR, GPRlr, |
| 29804 | /* MVE_VSTRBU8_post */ |
| 29805 | rGPR, MQPR, rGPR, -1, i32imm, VCCR, GPRlr, |
| 29806 | /* MVE_VSTRBU8_pre */ |
| 29807 | rGPR, MQPR, rGPR, i32imm, i32imm, VCCR, GPRlr, |
| 29808 | /* MVE_VSTRD64_qi */ |
| 29809 | MQPR, MQPR, i32imm, i32imm, VCCR, GPRlr, |
| 29810 | /* MVE_VSTRD64_qi_pre */ |
| 29811 | MQPR, MQPR, MQPR, i32imm, i32imm, VCCR, GPRlr, |
| 29812 | /* MVE_VSTRD64_rq */ |
| 29813 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 29814 | /* MVE_VSTRD64_rq_u */ |
| 29815 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 29816 | /* MVE_VSTRH16_rq */ |
| 29817 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 29818 | /* MVE_VSTRH16_rq_u */ |
| 29819 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 29820 | /* MVE_VSTRH32 */ |
| 29821 | MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 29822 | /* MVE_VSTRH32_post */ |
| 29823 | tGPR, MQPR, tGPR, -1, i32imm, VCCR, GPRlr, |
| 29824 | /* MVE_VSTRH32_pre */ |
| 29825 | tGPR, MQPR, tGPR, i32imm, i32imm, VCCR, GPRlr, |
| 29826 | /* MVE_VSTRH32_rq */ |
| 29827 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 29828 | /* MVE_VSTRH32_rq_u */ |
| 29829 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 29830 | /* MVE_VSTRHU16 */ |
| 29831 | MQPR, GPRnopc, i32imm, i32imm, VCCR, GPRlr, |
| 29832 | /* MVE_VSTRHU16_post */ |
| 29833 | rGPR, MQPR, rGPR, -1, i32imm, VCCR, GPRlr, |
| 29834 | /* MVE_VSTRHU16_pre */ |
| 29835 | rGPR, MQPR, rGPR, i32imm, i32imm, VCCR, GPRlr, |
| 29836 | /* MVE_VSTRW32_qi */ |
| 29837 | MQPR, MQPR, i32imm, i32imm, VCCR, GPRlr, |
| 29838 | /* MVE_VSTRW32_qi_pre */ |
| 29839 | MQPR, MQPR, MQPR, i32imm, i32imm, VCCR, GPRlr, |
| 29840 | /* MVE_VSTRW32_rq */ |
| 29841 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 29842 | /* MVE_VSTRW32_rq_u */ |
| 29843 | MQPR, GPRnopc, MQPR, i32imm, VCCR, GPRlr, |
| 29844 | /* MVE_VSTRWU32 */ |
| 29845 | MQPR, GPRnopc, i32imm, i32imm, VCCR, GPRlr, |
| 29846 | /* MVE_VSTRWU32_post */ |
| 29847 | rGPR, MQPR, rGPR, -1, i32imm, VCCR, GPRlr, |
| 29848 | /* MVE_VSTRWU32_pre */ |
| 29849 | rGPR, MQPR, rGPR, i32imm, i32imm, VCCR, GPRlr, |
| 29850 | /* MVE_VSUB_qr_f16 */ |
| 29851 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29852 | /* MVE_VSUB_qr_f32 */ |
| 29853 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29854 | /* MVE_VSUB_qr_i16 */ |
| 29855 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29856 | /* MVE_VSUB_qr_i32 */ |
| 29857 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29858 | /* MVE_VSUB_qr_i8 */ |
| 29859 | MQPR, MQPR, rGPR, i32imm, VCCR, GPRlr, MQPR, |
| 29860 | /* MVE_VSUBf16 */ |
| 29861 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29862 | /* MVE_VSUBf32 */ |
| 29863 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29864 | /* MVE_VSUBi16 */ |
| 29865 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29866 | /* MVE_VSUBi32 */ |
| 29867 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29868 | /* MVE_VSUBi8 */ |
| 29869 | MQPR, MQPR, MQPR, i32imm, VCCR, GPRlr, MQPR, |
| 29870 | /* MVE_WLSTP_16 */ |
| 29871 | GPRlr, rGPR, wlslabel_u11, |
| 29872 | /* MVE_WLSTP_32 */ |
| 29873 | GPRlr, rGPR, wlslabel_u11, |
| 29874 | /* MVE_WLSTP_64 */ |
| 29875 | GPRlr, rGPR, wlslabel_u11, |
| 29876 | /* MVE_WLSTP_8 */ |
| 29877 | GPRlr, rGPR, wlslabel_u11, |
| 29878 | /* MVNi */ |
| 29879 | GPR, mod_imm, i32imm, i32imm, CCR, |
| 29880 | /* MVNr */ |
| 29881 | GPR, GPR, i32imm, i32imm, CCR, |
| 29882 | /* MVNsi */ |
| 29883 | GPR, GPR, i32imm, i32imm, i32imm, CCR, |
| 29884 | /* MVNsr */ |
| 29885 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, CCR, |
| 29886 | /* NEON_VMAXNMNDf */ |
| 29887 | DPR, DPR, DPR, |
| 29888 | /* NEON_VMAXNMNDh */ |
| 29889 | DPR, DPR, DPR, |
| 29890 | /* NEON_VMAXNMNQf */ |
| 29891 | QPR, QPR, QPR, |
| 29892 | /* NEON_VMAXNMNQh */ |
| 29893 | QPR, QPR, QPR, |
| 29894 | /* NEON_VMINNMNDf */ |
| 29895 | DPR, DPR, DPR, |
| 29896 | /* NEON_VMINNMNDh */ |
| 29897 | DPR, DPR, DPR, |
| 29898 | /* NEON_VMINNMNQf */ |
| 29899 | QPR, QPR, QPR, |
| 29900 | /* NEON_VMINNMNQh */ |
| 29901 | QPR, QPR, QPR, |
| 29902 | /* ORRri */ |
| 29903 | GPR, GPR, mod_imm, i32imm, i32imm, CCR, |
| 29904 | /* ORRrr */ |
| 29905 | GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 29906 | /* ORRrsi */ |
| 29907 | GPR, GPR, GPR, i32imm, i32imm, i32imm, CCR, |
| 29908 | /* ORRrsr */ |
| 29909 | GPR, GPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, CCR, |
| 29910 | /* PKHBT */ |
| 29911 | GPRnopc, GPRnopc, GPRnopc, pkh_lsl_amt, i32imm, i32imm, |
| 29912 | /* PKHTB */ |
| 29913 | GPRnopc, GPRnopc, GPRnopc, pkh_asr_amt, i32imm, i32imm, |
| 29914 | /* PLDWi12 */ |
| 29915 | GPR, i32imm, |
| 29916 | /* PLDWrs */ |
| 29917 | GPR, GPRnopc, i32imm, |
| 29918 | /* PLDi12 */ |
| 29919 | GPR, i32imm, |
| 29920 | /* PLDrs */ |
| 29921 | GPR, GPRnopc, i32imm, |
| 29922 | /* PLIi12 */ |
| 29923 | GPR, i32imm, |
| 29924 | /* PLIrs */ |
| 29925 | GPR, GPRnopc, i32imm, |
| 29926 | /* QADD */ |
| 29927 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 29928 | /* QADD16 */ |
| 29929 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 29930 | /* QADD8 */ |
| 29931 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 29932 | /* QASX */ |
| 29933 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 29934 | /* QDADD */ |
| 29935 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 29936 | /* QDSUB */ |
| 29937 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 29938 | /* QSAX */ |
| 29939 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 29940 | /* QSUB */ |
| 29941 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 29942 | /* QSUB16 */ |
| 29943 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 29944 | /* QSUB8 */ |
| 29945 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 29946 | /* RBIT */ |
| 29947 | GPR, GPR, i32imm, i32imm, |
| 29948 | /* REV */ |
| 29949 | GPR, GPR, i32imm, i32imm, |
| 29950 | /* REV16 */ |
| 29951 | GPR, GPR, i32imm, i32imm, |
| 29952 | /* REVSH */ |
| 29953 | GPR, GPR, i32imm, i32imm, |
| 29954 | /* RFEDA */ |
| 29955 | GPR, |
| 29956 | /* RFEDA_UPD */ |
| 29957 | GPR, |
| 29958 | /* RFEDB */ |
| 29959 | GPR, |
| 29960 | /* RFEDB_UPD */ |
| 29961 | GPR, |
| 29962 | /* RFEIA */ |
| 29963 | GPR, |
| 29964 | /* RFEIA_UPD */ |
| 29965 | GPR, |
| 29966 | /* RFEIB */ |
| 29967 | GPR, |
| 29968 | /* RFEIB_UPD */ |
| 29969 | GPR, |
| 29970 | /* RSBri */ |
| 29971 | GPR, GPR, mod_imm, i32imm, i32imm, CCR, |
| 29972 | /* RSBrr */ |
| 29973 | GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 29974 | /* RSBrsi */ |
| 29975 | GPR, GPR, GPR, i32imm, i32imm, i32imm, CCR, |
| 29976 | /* RSBrsr */ |
| 29977 | GPR, GPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, CCR, |
| 29978 | /* RSCri */ |
| 29979 | GPR, GPR, mod_imm, i32imm, i32imm, CCR, |
| 29980 | /* RSCrr */ |
| 29981 | GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 29982 | /* RSCrsi */ |
| 29983 | GPR, GPR, GPR, i32imm, i32imm, i32imm, CCR, |
| 29984 | /* RSCrsr */ |
| 29985 | GPR, GPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, CCR, |
| 29986 | /* SADD16 */ |
| 29987 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 29988 | /* SADD8 */ |
| 29989 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 29990 | /* SASX */ |
| 29991 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 29992 | /* SB */ |
| 29993 | /* SBCri */ |
| 29994 | GPR, GPR, mod_imm, i32imm, i32imm, CCR, |
| 29995 | /* SBCrr */ |
| 29996 | GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 29997 | /* SBCrsi */ |
| 29998 | GPR, GPR, GPR, i32imm, i32imm, i32imm, CCR, |
| 29999 | /* SBCrsr */ |
| 30000 | GPRnopc, GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, CCR, |
| 30001 | /* SBFX */ |
| 30002 | GPRnopc, GPRnopc, imm0_31, imm1_32, i32imm, i32imm, |
| 30003 | /* SDIV */ |
| 30004 | GPR, GPR, GPR, i32imm, i32imm, |
| 30005 | /* SEL */ |
| 30006 | GPR, GPR, GPR, i32imm, i32imm, |
| 30007 | /* SETEND */ |
| 30008 | setend_op, |
| 30009 | /* SETPAN */ |
| 30010 | imm0_1, |
| 30011 | /* SHA1C */ |
| 30012 | QPR, QPR, QPR, QPR, |
| 30013 | /* SHA1H */ |
| 30014 | QPR, QPR, |
| 30015 | /* SHA1M */ |
| 30016 | QPR, QPR, QPR, QPR, |
| 30017 | /* SHA1P */ |
| 30018 | QPR, QPR, QPR, QPR, |
| 30019 | /* SHA1SU0 */ |
| 30020 | QPR, QPR, QPR, QPR, |
| 30021 | /* SHA1SU1 */ |
| 30022 | QPR, QPR, QPR, |
| 30023 | /* SHA256H */ |
| 30024 | QPR, QPR, QPR, QPR, |
| 30025 | /* SHA256H2 */ |
| 30026 | QPR, QPR, QPR, QPR, |
| 30027 | /* SHA256SU0 */ |
| 30028 | QPR, QPR, QPR, |
| 30029 | /* SHA256SU1 */ |
| 30030 | QPR, QPR, QPR, QPR, |
| 30031 | /* SHADD16 */ |
| 30032 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30033 | /* SHADD8 */ |
| 30034 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30035 | /* SHASX */ |
| 30036 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30037 | /* SHSAX */ |
| 30038 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30039 | /* SHSUB16 */ |
| 30040 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30041 | /* SHSUB8 */ |
| 30042 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30043 | /* SMC */ |
| 30044 | imm0_15, i32imm, i32imm, |
| 30045 | /* SMLABB */ |
| 30046 | GPRnopc, GPRnopc, GPRnopc, GPR, i32imm, i32imm, |
| 30047 | /* SMLABT */ |
| 30048 | GPRnopc, GPRnopc, GPRnopc, GPR, i32imm, i32imm, |
| 30049 | /* SMLAD */ |
| 30050 | GPRnopc, GPRnopc, GPRnopc, GPR, i32imm, i32imm, |
| 30051 | /* SMLADX */ |
| 30052 | GPRnopc, GPRnopc, GPRnopc, GPR, i32imm, i32imm, |
| 30053 | /* SMLAL */ |
| 30054 | GPR, GPR, GPR, GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 30055 | /* SMLALBB */ |
| 30056 | GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30057 | /* SMLALBT */ |
| 30058 | GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30059 | /* SMLALD */ |
| 30060 | GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30061 | /* SMLALDX */ |
| 30062 | GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30063 | /* SMLALTB */ |
| 30064 | GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30065 | /* SMLALTT */ |
| 30066 | GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30067 | /* SMLATB */ |
| 30068 | GPRnopc, GPRnopc, GPRnopc, GPR, i32imm, i32imm, |
| 30069 | /* SMLATT */ |
| 30070 | GPRnopc, GPRnopc, GPRnopc, GPR, i32imm, i32imm, |
| 30071 | /* SMLAWB */ |
| 30072 | GPRnopc, GPRnopc, GPRnopc, GPR, i32imm, i32imm, |
| 30073 | /* SMLAWT */ |
| 30074 | GPRnopc, GPRnopc, GPRnopc, GPR, i32imm, i32imm, |
| 30075 | /* SMLSD */ |
| 30076 | GPRnopc, GPRnopc, GPRnopc, GPR, i32imm, i32imm, |
| 30077 | /* SMLSDX */ |
| 30078 | GPRnopc, GPRnopc, GPRnopc, GPR, i32imm, i32imm, |
| 30079 | /* SMLSLD */ |
| 30080 | GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30081 | /* SMLSLDX */ |
| 30082 | GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30083 | /* SMMLA */ |
| 30084 | GPR, GPR, GPR, GPR, i32imm, i32imm, |
| 30085 | /* SMMLAR */ |
| 30086 | GPR, GPR, GPR, GPR, i32imm, i32imm, |
| 30087 | /* SMMLS */ |
| 30088 | GPR, GPR, GPR, GPR, i32imm, i32imm, |
| 30089 | /* SMMLSR */ |
| 30090 | GPR, GPR, GPR, GPR, i32imm, i32imm, |
| 30091 | /* SMMUL */ |
| 30092 | GPR, GPR, GPR, i32imm, i32imm, |
| 30093 | /* SMMULR */ |
| 30094 | GPR, GPR, GPR, i32imm, i32imm, |
| 30095 | /* SMUAD */ |
| 30096 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30097 | /* SMUADX */ |
| 30098 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30099 | /* SMULBB */ |
| 30100 | GPR, GPR, GPR, i32imm, i32imm, |
| 30101 | /* SMULBT */ |
| 30102 | GPR, GPR, GPR, i32imm, i32imm, |
| 30103 | /* SMULL */ |
| 30104 | GPR, GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 30105 | /* SMULTB */ |
| 30106 | GPR, GPR, GPR, i32imm, i32imm, |
| 30107 | /* SMULTT */ |
| 30108 | GPR, GPR, GPR, i32imm, i32imm, |
| 30109 | /* SMULWB */ |
| 30110 | GPR, GPR, GPR, i32imm, i32imm, |
| 30111 | /* SMULWT */ |
| 30112 | GPR, GPR, GPR, i32imm, i32imm, |
| 30113 | /* SMUSD */ |
| 30114 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30115 | /* SMUSDX */ |
| 30116 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30117 | /* SRSDA */ |
| 30118 | imm0_31, |
| 30119 | /* SRSDA_UPD */ |
| 30120 | imm0_31, |
| 30121 | /* SRSDB */ |
| 30122 | imm0_31, |
| 30123 | /* SRSDB_UPD */ |
| 30124 | imm0_31, |
| 30125 | /* SRSIA */ |
| 30126 | imm0_31, |
| 30127 | /* SRSIA_UPD */ |
| 30128 | imm0_31, |
| 30129 | /* SRSIB */ |
| 30130 | imm0_31, |
| 30131 | /* SRSIB_UPD */ |
| 30132 | imm0_31, |
| 30133 | /* SSAT */ |
| 30134 | GPRnopc, imm1_32, GPRnopc, shift_imm, i32imm, i32imm, |
| 30135 | /* SSAT16 */ |
| 30136 | GPRnopc, imm1_16, GPRnopc, i32imm, i32imm, |
| 30137 | /* SSAX */ |
| 30138 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30139 | /* SSUB16 */ |
| 30140 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30141 | /* SSUB8 */ |
| 30142 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30143 | /* STC2L_OFFSET */ |
| 30144 | p_imm, c_imm, GPR, i32imm, |
| 30145 | /* STC2L_OPTION */ |
| 30146 | p_imm, c_imm, GPR, coproc_option_imm, |
| 30147 | /* STC2L_POST */ |
| 30148 | p_imm, c_imm, GPR, i32imm, |
| 30149 | /* STC2L_PRE */ |
| 30150 | p_imm, c_imm, GPR, i32imm, |
| 30151 | /* STC2_OFFSET */ |
| 30152 | p_imm, c_imm, GPR, i32imm, |
| 30153 | /* STC2_OPTION */ |
| 30154 | p_imm, c_imm, GPR, coproc_option_imm, |
| 30155 | /* STC2_POST */ |
| 30156 | p_imm, c_imm, GPR, i32imm, |
| 30157 | /* STC2_PRE */ |
| 30158 | p_imm, c_imm, GPR, i32imm, |
| 30159 | /* STCL_OFFSET */ |
| 30160 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 30161 | /* STCL_OPTION */ |
| 30162 | p_imm, c_imm, GPR, coproc_option_imm, i32imm, i32imm, |
| 30163 | /* STCL_POST */ |
| 30164 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 30165 | /* STCL_PRE */ |
| 30166 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 30167 | /* STC_OFFSET */ |
| 30168 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 30169 | /* STC_OPTION */ |
| 30170 | p_imm, c_imm, GPR, coproc_option_imm, i32imm, i32imm, |
| 30171 | /* STC_POST */ |
| 30172 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 30173 | /* STC_PRE */ |
| 30174 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 30175 | /* STL */ |
| 30176 | GPR, GPR, i32imm, i32imm, |
| 30177 | /* STLB */ |
| 30178 | GPR, GPR, i32imm, i32imm, |
| 30179 | /* STLEX */ |
| 30180 | GPR, GPR, GPR, i32imm, i32imm, |
| 30181 | /* STLEXB */ |
| 30182 | GPR, GPR, GPR, i32imm, i32imm, |
| 30183 | /* STLEXD */ |
| 30184 | GPR, GPRPairOp, GPR, i32imm, i32imm, |
| 30185 | /* STLEXH */ |
| 30186 | GPR, GPR, GPR, i32imm, i32imm, |
| 30187 | /* STLH */ |
| 30188 | GPR, GPR, i32imm, i32imm, |
| 30189 | /* STMDA */ |
| 30190 | GPR, i32imm, i32imm, reglist, |
| 30191 | /* STMDA_UPD */ |
| 30192 | GPR, GPR, i32imm, i32imm, reglist, |
| 30193 | /* STMDB */ |
| 30194 | GPR, i32imm, i32imm, reglist, |
| 30195 | /* STMDB_UPD */ |
| 30196 | GPR, GPR, i32imm, i32imm, reglist, |
| 30197 | /* STMIA */ |
| 30198 | GPR, i32imm, i32imm, reglist, |
| 30199 | /* STMIA_UPD */ |
| 30200 | GPR, GPR, i32imm, i32imm, reglist, |
| 30201 | /* STMIB */ |
| 30202 | GPR, i32imm, i32imm, reglist, |
| 30203 | /* STMIB_UPD */ |
| 30204 | GPR, GPR, i32imm, i32imm, reglist, |
| 30205 | /* STRBT_POST_IMM */ |
| 30206 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 30207 | /* STRBT_POST_REG */ |
| 30208 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 30209 | /* STRB_POST_IMM */ |
| 30210 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 30211 | /* STRB_POST_REG */ |
| 30212 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 30213 | /* STRB_PRE_IMM */ |
| 30214 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 30215 | /* STRB_PRE_REG */ |
| 30216 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 30217 | /* STRBi12 */ |
| 30218 | GPRnopc, GPR, i32imm, i32imm, i32imm, |
| 30219 | /* STRBrs */ |
| 30220 | GPRnopc, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 30221 | /* STRD */ |
| 30222 | GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 30223 | /* STRD_POST */ |
| 30224 | GPR, GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 30225 | /* STRD_PRE */ |
| 30226 | GPR, GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 30227 | /* STREX */ |
| 30228 | GPR, GPR, GPR, i32imm, i32imm, |
| 30229 | /* STREXB */ |
| 30230 | GPR, GPR, GPR, i32imm, i32imm, |
| 30231 | /* STREXD */ |
| 30232 | GPR, GPRPairOp, GPR, i32imm, i32imm, |
| 30233 | /* STREXH */ |
| 30234 | GPR, GPR, GPR, i32imm, i32imm, |
| 30235 | /* STRH */ |
| 30236 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 30237 | /* STRHTi */ |
| 30238 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 30239 | /* STRHTr */ |
| 30240 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 30241 | /* STRH_POST */ |
| 30242 | GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 30243 | /* STRH_PRE */ |
| 30244 | GPR, GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 30245 | /* STRT_POST_IMM */ |
| 30246 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 30247 | /* STRT_POST_REG */ |
| 30248 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 30249 | /* STR_POST_IMM */ |
| 30250 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 30251 | /* STR_POST_REG */ |
| 30252 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 30253 | /* STR_PRE_IMM */ |
| 30254 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 30255 | /* STR_PRE_REG */ |
| 30256 | GPR, GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 30257 | /* STRi12 */ |
| 30258 | GPR, GPR, i32imm, i32imm, i32imm, |
| 30259 | /* STRrs */ |
| 30260 | GPR, GPR, GPRnopc, i32imm, i32imm, i32imm, |
| 30261 | /* SUBri */ |
| 30262 | GPR, GPR, mod_imm, i32imm, i32imm, CCR, |
| 30263 | /* SUBrr */ |
| 30264 | GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 30265 | /* SUBrsi */ |
| 30266 | GPR, GPR, GPR, i32imm, i32imm, i32imm, CCR, |
| 30267 | /* SUBrsr */ |
| 30268 | GPR, GPR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, CCR, |
| 30269 | /* SVC */ |
| 30270 | imm24b, i32imm, i32imm, |
| 30271 | /* SWP */ |
| 30272 | GPRnopc, GPRnopc, GPR, i32imm, i32imm, |
| 30273 | /* SWPB */ |
| 30274 | GPRnopc, GPRnopc, GPR, i32imm, i32imm, |
| 30275 | /* SXTAB */ |
| 30276 | GPRnopc, GPR, GPRnopc, rot_imm, i32imm, i32imm, |
| 30277 | /* SXTAB16 */ |
| 30278 | GPRnopc, GPR, GPRnopc, rot_imm, i32imm, i32imm, |
| 30279 | /* SXTAH */ |
| 30280 | GPRnopc, GPR, GPRnopc, rot_imm, i32imm, i32imm, |
| 30281 | /* SXTB */ |
| 30282 | GPRnopc, GPRnopc, rot_imm, i32imm, i32imm, |
| 30283 | /* SXTB16 */ |
| 30284 | GPRnopc, GPRnopc, rot_imm, i32imm, i32imm, |
| 30285 | /* SXTH */ |
| 30286 | GPRnopc, GPRnopc, rot_imm, i32imm, i32imm, |
| 30287 | /* TEQri */ |
| 30288 | GPR, mod_imm, i32imm, i32imm, |
| 30289 | /* TEQrr */ |
| 30290 | GPR, GPR, i32imm, i32imm, |
| 30291 | /* TEQrsi */ |
| 30292 | GPR, GPR, i32imm, i32imm, i32imm, |
| 30293 | /* TEQrsr */ |
| 30294 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 30295 | /* TRAP */ |
| 30296 | /* TRAPNaCl */ |
| 30297 | /* TSB */ |
| 30298 | tsb_opt, |
| 30299 | /* TSTri */ |
| 30300 | GPR, mod_imm, i32imm, i32imm, |
| 30301 | /* TSTrr */ |
| 30302 | GPR, GPR, i32imm, i32imm, |
| 30303 | /* TSTrsi */ |
| 30304 | GPR, GPR, i32imm, i32imm, i32imm, |
| 30305 | /* TSTrsr */ |
| 30306 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 30307 | /* UADD16 */ |
| 30308 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30309 | /* UADD8 */ |
| 30310 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30311 | /* UASX */ |
| 30312 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30313 | /* UBFX */ |
| 30314 | GPRnopc, GPRnopc, imm0_31, imm1_32, i32imm, i32imm, |
| 30315 | /* UDF */ |
| 30316 | imm0_65535, |
| 30317 | /* UDIV */ |
| 30318 | GPR, GPR, GPR, i32imm, i32imm, |
| 30319 | /* UHADD16 */ |
| 30320 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30321 | /* UHADD8 */ |
| 30322 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30323 | /* UHASX */ |
| 30324 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30325 | /* UHSAX */ |
| 30326 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30327 | /* UHSUB16 */ |
| 30328 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30329 | /* UHSUB8 */ |
| 30330 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30331 | /* UMAAL */ |
| 30332 | GPR, GPR, GPR, GPR, GPR, GPR, i32imm, i32imm, |
| 30333 | /* UMLAL */ |
| 30334 | GPR, GPR, GPR, GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 30335 | /* UMULL */ |
| 30336 | GPR, GPR, GPR, GPR, i32imm, i32imm, CCR, |
| 30337 | /* UQADD16 */ |
| 30338 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30339 | /* UQADD8 */ |
| 30340 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30341 | /* UQASX */ |
| 30342 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30343 | /* UQSAX */ |
| 30344 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30345 | /* UQSUB16 */ |
| 30346 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30347 | /* UQSUB8 */ |
| 30348 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30349 | /* USAD8 */ |
| 30350 | GPR, GPR, GPR, i32imm, i32imm, |
| 30351 | /* USADA8 */ |
| 30352 | GPR, GPR, GPR, GPR, i32imm, i32imm, |
| 30353 | /* USAT */ |
| 30354 | GPRnopc, imm0_31, GPRnopc, shift_imm, i32imm, i32imm, |
| 30355 | /* USAT16 */ |
| 30356 | GPRnopc, imm0_15, GPRnopc, i32imm, i32imm, |
| 30357 | /* USAX */ |
| 30358 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30359 | /* USUB16 */ |
| 30360 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30361 | /* USUB8 */ |
| 30362 | GPRnopc, GPRnopc, GPRnopc, i32imm, i32imm, |
| 30363 | /* UXTAB */ |
| 30364 | GPRnopc, GPR, GPRnopc, rot_imm, i32imm, i32imm, |
| 30365 | /* UXTAB16 */ |
| 30366 | GPRnopc, GPR, GPRnopc, rot_imm, i32imm, i32imm, |
| 30367 | /* UXTAH */ |
| 30368 | GPRnopc, GPR, GPRnopc, rot_imm, i32imm, i32imm, |
| 30369 | /* UXTB */ |
| 30370 | GPRnopc, GPRnopc, rot_imm, i32imm, i32imm, |
| 30371 | /* UXTB16 */ |
| 30372 | GPRnopc, GPRnopc, rot_imm, i32imm, i32imm, |
| 30373 | /* UXTH */ |
| 30374 | GPRnopc, GPRnopc, rot_imm, i32imm, i32imm, |
| 30375 | /* VABALsv2i64 */ |
| 30376 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 30377 | /* VABALsv4i32 */ |
| 30378 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 30379 | /* VABALsv8i16 */ |
| 30380 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 30381 | /* VABALuv2i64 */ |
| 30382 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 30383 | /* VABALuv4i32 */ |
| 30384 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 30385 | /* VABALuv8i16 */ |
| 30386 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 30387 | /* VABAsv16i8 */ |
| 30388 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 30389 | /* VABAsv2i32 */ |
| 30390 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 30391 | /* VABAsv4i16 */ |
| 30392 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 30393 | /* VABAsv4i32 */ |
| 30394 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 30395 | /* VABAsv8i16 */ |
| 30396 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 30397 | /* VABAsv8i8 */ |
| 30398 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 30399 | /* VABAuv16i8 */ |
| 30400 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 30401 | /* VABAuv2i32 */ |
| 30402 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 30403 | /* VABAuv4i16 */ |
| 30404 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 30405 | /* VABAuv4i32 */ |
| 30406 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 30407 | /* VABAuv8i16 */ |
| 30408 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 30409 | /* VABAuv8i8 */ |
| 30410 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 30411 | /* VABDLsv2i64 */ |
| 30412 | QPR, DPR, DPR, i32imm, i32imm, |
| 30413 | /* VABDLsv4i32 */ |
| 30414 | QPR, DPR, DPR, i32imm, i32imm, |
| 30415 | /* VABDLsv8i16 */ |
| 30416 | QPR, DPR, DPR, i32imm, i32imm, |
| 30417 | /* VABDLuv2i64 */ |
| 30418 | QPR, DPR, DPR, i32imm, i32imm, |
| 30419 | /* VABDLuv4i32 */ |
| 30420 | QPR, DPR, DPR, i32imm, i32imm, |
| 30421 | /* VABDLuv8i16 */ |
| 30422 | QPR, DPR, DPR, i32imm, i32imm, |
| 30423 | /* VABDfd */ |
| 30424 | DPR, DPR, DPR, i32imm, i32imm, |
| 30425 | /* VABDfq */ |
| 30426 | QPR, QPR, QPR, i32imm, i32imm, |
| 30427 | /* VABDhd */ |
| 30428 | DPR, DPR, DPR, i32imm, i32imm, |
| 30429 | /* VABDhq */ |
| 30430 | QPR, QPR, QPR, i32imm, i32imm, |
| 30431 | /* VABDsv16i8 */ |
| 30432 | QPR, QPR, QPR, i32imm, i32imm, |
| 30433 | /* VABDsv2i32 */ |
| 30434 | DPR, DPR, DPR, i32imm, i32imm, |
| 30435 | /* VABDsv4i16 */ |
| 30436 | DPR, DPR, DPR, i32imm, i32imm, |
| 30437 | /* VABDsv4i32 */ |
| 30438 | QPR, QPR, QPR, i32imm, i32imm, |
| 30439 | /* VABDsv8i16 */ |
| 30440 | QPR, QPR, QPR, i32imm, i32imm, |
| 30441 | /* VABDsv8i8 */ |
| 30442 | DPR, DPR, DPR, i32imm, i32imm, |
| 30443 | /* VABDuv16i8 */ |
| 30444 | QPR, QPR, QPR, i32imm, i32imm, |
| 30445 | /* VABDuv2i32 */ |
| 30446 | DPR, DPR, DPR, i32imm, i32imm, |
| 30447 | /* VABDuv4i16 */ |
| 30448 | DPR, DPR, DPR, i32imm, i32imm, |
| 30449 | /* VABDuv4i32 */ |
| 30450 | QPR, QPR, QPR, i32imm, i32imm, |
| 30451 | /* VABDuv8i16 */ |
| 30452 | QPR, QPR, QPR, i32imm, i32imm, |
| 30453 | /* VABDuv8i8 */ |
| 30454 | DPR, DPR, DPR, i32imm, i32imm, |
| 30455 | /* VABSD */ |
| 30456 | DPR, DPR, i32imm, i32imm, |
| 30457 | /* VABSH */ |
| 30458 | HPR, HPR, i32imm, i32imm, |
| 30459 | /* VABSS */ |
| 30460 | SPR, SPR, i32imm, i32imm, |
| 30461 | /* VABSfd */ |
| 30462 | DPR, DPR, i32imm, i32imm, |
| 30463 | /* VABSfq */ |
| 30464 | QPR, QPR, i32imm, i32imm, |
| 30465 | /* VABShd */ |
| 30466 | DPR, DPR, i32imm, i32imm, |
| 30467 | /* VABShq */ |
| 30468 | QPR, QPR, i32imm, i32imm, |
| 30469 | /* VABSv16i8 */ |
| 30470 | QPR, QPR, i32imm, i32imm, |
| 30471 | /* VABSv2i32 */ |
| 30472 | DPR, DPR, i32imm, i32imm, |
| 30473 | /* VABSv4i16 */ |
| 30474 | DPR, DPR, i32imm, i32imm, |
| 30475 | /* VABSv4i32 */ |
| 30476 | QPR, QPR, i32imm, i32imm, |
| 30477 | /* VABSv8i16 */ |
| 30478 | QPR, QPR, i32imm, i32imm, |
| 30479 | /* VABSv8i8 */ |
| 30480 | DPR, DPR, i32imm, i32imm, |
| 30481 | /* VACGEfd */ |
| 30482 | DPR, DPR, DPR, i32imm, i32imm, |
| 30483 | /* VACGEfq */ |
| 30484 | QPR, QPR, QPR, i32imm, i32imm, |
| 30485 | /* VACGEhd */ |
| 30486 | DPR, DPR, DPR, i32imm, i32imm, |
| 30487 | /* VACGEhq */ |
| 30488 | QPR, QPR, QPR, i32imm, i32imm, |
| 30489 | /* VACGTfd */ |
| 30490 | DPR, DPR, DPR, i32imm, i32imm, |
| 30491 | /* VACGTfq */ |
| 30492 | QPR, QPR, QPR, i32imm, i32imm, |
| 30493 | /* VACGThd */ |
| 30494 | DPR, DPR, DPR, i32imm, i32imm, |
| 30495 | /* VACGThq */ |
| 30496 | QPR, QPR, QPR, i32imm, i32imm, |
| 30497 | /* VADDD */ |
| 30498 | DPR, DPR, DPR, i32imm, i32imm, |
| 30499 | /* VADDH */ |
| 30500 | HPR, HPR, HPR, i32imm, i32imm, |
| 30501 | /* VADDHNv2i32 */ |
| 30502 | DPR, QPR, QPR, i32imm, i32imm, |
| 30503 | /* VADDHNv4i16 */ |
| 30504 | DPR, QPR, QPR, i32imm, i32imm, |
| 30505 | /* VADDHNv8i8 */ |
| 30506 | DPR, QPR, QPR, i32imm, i32imm, |
| 30507 | /* VADDLsv2i64 */ |
| 30508 | QPR, DPR, DPR, i32imm, i32imm, |
| 30509 | /* VADDLsv4i32 */ |
| 30510 | QPR, DPR, DPR, i32imm, i32imm, |
| 30511 | /* VADDLsv8i16 */ |
| 30512 | QPR, DPR, DPR, i32imm, i32imm, |
| 30513 | /* VADDLuv2i64 */ |
| 30514 | QPR, DPR, DPR, i32imm, i32imm, |
| 30515 | /* VADDLuv4i32 */ |
| 30516 | QPR, DPR, DPR, i32imm, i32imm, |
| 30517 | /* VADDLuv8i16 */ |
| 30518 | QPR, DPR, DPR, i32imm, i32imm, |
| 30519 | /* VADDS */ |
| 30520 | SPR, SPR, SPR, i32imm, i32imm, |
| 30521 | /* VADDWsv2i64 */ |
| 30522 | QPR, QPR, DPR, i32imm, i32imm, |
| 30523 | /* VADDWsv4i32 */ |
| 30524 | QPR, QPR, DPR, i32imm, i32imm, |
| 30525 | /* VADDWsv8i16 */ |
| 30526 | QPR, QPR, DPR, i32imm, i32imm, |
| 30527 | /* VADDWuv2i64 */ |
| 30528 | QPR, QPR, DPR, i32imm, i32imm, |
| 30529 | /* VADDWuv4i32 */ |
| 30530 | QPR, QPR, DPR, i32imm, i32imm, |
| 30531 | /* VADDWuv8i16 */ |
| 30532 | QPR, QPR, DPR, i32imm, i32imm, |
| 30533 | /* VADDfd */ |
| 30534 | DPR, DPR, DPR, i32imm, i32imm, |
| 30535 | /* VADDfq */ |
| 30536 | QPR, QPR, QPR, i32imm, i32imm, |
| 30537 | /* VADDhd */ |
| 30538 | DPR, DPR, DPR, i32imm, i32imm, |
| 30539 | /* VADDhq */ |
| 30540 | QPR, QPR, QPR, i32imm, i32imm, |
| 30541 | /* VADDv16i8 */ |
| 30542 | QPR, QPR, QPR, i32imm, i32imm, |
| 30543 | /* VADDv1i64 */ |
| 30544 | DPR, DPR, DPR, i32imm, i32imm, |
| 30545 | /* VADDv2i32 */ |
| 30546 | DPR, DPR, DPR, i32imm, i32imm, |
| 30547 | /* VADDv2i64 */ |
| 30548 | QPR, QPR, QPR, i32imm, i32imm, |
| 30549 | /* VADDv4i16 */ |
| 30550 | DPR, DPR, DPR, i32imm, i32imm, |
| 30551 | /* VADDv4i32 */ |
| 30552 | QPR, QPR, QPR, i32imm, i32imm, |
| 30553 | /* VADDv8i16 */ |
| 30554 | QPR, QPR, QPR, i32imm, i32imm, |
| 30555 | /* VADDv8i8 */ |
| 30556 | DPR, DPR, DPR, i32imm, i32imm, |
| 30557 | /* VANDd */ |
| 30558 | DPR, DPR, DPR, i32imm, i32imm, |
| 30559 | /* VANDq */ |
| 30560 | QPR, QPR, QPR, i32imm, i32imm, |
| 30561 | /* VBF16MALBQ */ |
| 30562 | QPR, QPR, QPR, QPR, |
| 30563 | /* VBF16MALBQI */ |
| 30564 | QPR, QPR, QPR, DPR_8, i32imm, |
| 30565 | /* VBF16MALTQ */ |
| 30566 | QPR, QPR, QPR, QPR, |
| 30567 | /* VBF16MALTQI */ |
| 30568 | QPR, QPR, QPR, DPR_8, i32imm, |
| 30569 | /* VBICd */ |
| 30570 | DPR, DPR, DPR, i32imm, i32imm, |
| 30571 | /* VBICiv2i32 */ |
| 30572 | DPR, nImmSplatI32, DPR, i32imm, i32imm, |
| 30573 | /* VBICiv4i16 */ |
| 30574 | DPR, nImmSplatI16, DPR, i32imm, i32imm, |
| 30575 | /* VBICiv4i32 */ |
| 30576 | QPR, nImmSplatI32, QPR, i32imm, i32imm, |
| 30577 | /* VBICiv8i16 */ |
| 30578 | QPR, nImmSplatI16, QPR, i32imm, i32imm, |
| 30579 | /* VBICq */ |
| 30580 | QPR, QPR, QPR, i32imm, i32imm, |
| 30581 | /* VBIFd */ |
| 30582 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 30583 | /* VBIFq */ |
| 30584 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 30585 | /* VBITd */ |
| 30586 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 30587 | /* VBITq */ |
| 30588 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 30589 | /* VBSLd */ |
| 30590 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 30591 | /* VBSLq */ |
| 30592 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 30593 | /* VBSPd */ |
| 30594 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 30595 | /* VBSPq */ |
| 30596 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 30597 | /* VCADDv2f32 */ |
| 30598 | DPR, DPR, DPR, complexrotateopodd, |
| 30599 | /* VCADDv4f16 */ |
| 30600 | DPR, DPR, DPR, complexrotateopodd, |
| 30601 | /* VCADDv4f32 */ |
| 30602 | QPR, QPR, QPR, complexrotateopodd, |
| 30603 | /* VCADDv8f16 */ |
| 30604 | QPR, QPR, QPR, complexrotateopodd, |
| 30605 | /* VCEQfd */ |
| 30606 | DPR, DPR, DPR, i32imm, i32imm, |
| 30607 | /* VCEQfq */ |
| 30608 | QPR, QPR, QPR, i32imm, i32imm, |
| 30609 | /* VCEQhd */ |
| 30610 | DPR, DPR, DPR, i32imm, i32imm, |
| 30611 | /* VCEQhq */ |
| 30612 | QPR, QPR, QPR, i32imm, i32imm, |
| 30613 | /* VCEQv16i8 */ |
| 30614 | QPR, QPR, QPR, i32imm, i32imm, |
| 30615 | /* VCEQv2i32 */ |
| 30616 | DPR, DPR, DPR, i32imm, i32imm, |
| 30617 | /* VCEQv4i16 */ |
| 30618 | DPR, DPR, DPR, i32imm, i32imm, |
| 30619 | /* VCEQv4i32 */ |
| 30620 | QPR, QPR, QPR, i32imm, i32imm, |
| 30621 | /* VCEQv8i16 */ |
| 30622 | QPR, QPR, QPR, i32imm, i32imm, |
| 30623 | /* VCEQv8i8 */ |
| 30624 | DPR, DPR, DPR, i32imm, i32imm, |
| 30625 | /* VCEQzv16i8 */ |
| 30626 | QPR, QPR, i32imm, i32imm, |
| 30627 | /* VCEQzv2f32 */ |
| 30628 | DPR, DPR, i32imm, i32imm, |
| 30629 | /* VCEQzv2i32 */ |
| 30630 | DPR, DPR, i32imm, i32imm, |
| 30631 | /* VCEQzv4f16 */ |
| 30632 | DPR, DPR, i32imm, i32imm, |
| 30633 | /* VCEQzv4f32 */ |
| 30634 | QPR, QPR, i32imm, i32imm, |
| 30635 | /* VCEQzv4i16 */ |
| 30636 | DPR, DPR, i32imm, i32imm, |
| 30637 | /* VCEQzv4i32 */ |
| 30638 | QPR, QPR, i32imm, i32imm, |
| 30639 | /* VCEQzv8f16 */ |
| 30640 | QPR, QPR, i32imm, i32imm, |
| 30641 | /* VCEQzv8i16 */ |
| 30642 | QPR, QPR, i32imm, i32imm, |
| 30643 | /* VCEQzv8i8 */ |
| 30644 | DPR, DPR, i32imm, i32imm, |
| 30645 | /* VCGEfd */ |
| 30646 | DPR, DPR, DPR, i32imm, i32imm, |
| 30647 | /* VCGEfq */ |
| 30648 | QPR, QPR, QPR, i32imm, i32imm, |
| 30649 | /* VCGEhd */ |
| 30650 | DPR, DPR, DPR, i32imm, i32imm, |
| 30651 | /* VCGEhq */ |
| 30652 | QPR, QPR, QPR, i32imm, i32imm, |
| 30653 | /* VCGEsv16i8 */ |
| 30654 | QPR, QPR, QPR, i32imm, i32imm, |
| 30655 | /* VCGEsv2i32 */ |
| 30656 | DPR, DPR, DPR, i32imm, i32imm, |
| 30657 | /* VCGEsv4i16 */ |
| 30658 | DPR, DPR, DPR, i32imm, i32imm, |
| 30659 | /* VCGEsv4i32 */ |
| 30660 | QPR, QPR, QPR, i32imm, i32imm, |
| 30661 | /* VCGEsv8i16 */ |
| 30662 | QPR, QPR, QPR, i32imm, i32imm, |
| 30663 | /* VCGEsv8i8 */ |
| 30664 | DPR, DPR, DPR, i32imm, i32imm, |
| 30665 | /* VCGEuv16i8 */ |
| 30666 | QPR, QPR, QPR, i32imm, i32imm, |
| 30667 | /* VCGEuv2i32 */ |
| 30668 | DPR, DPR, DPR, i32imm, i32imm, |
| 30669 | /* VCGEuv4i16 */ |
| 30670 | DPR, DPR, DPR, i32imm, i32imm, |
| 30671 | /* VCGEuv4i32 */ |
| 30672 | QPR, QPR, QPR, i32imm, i32imm, |
| 30673 | /* VCGEuv8i16 */ |
| 30674 | QPR, QPR, QPR, i32imm, i32imm, |
| 30675 | /* VCGEuv8i8 */ |
| 30676 | DPR, DPR, DPR, i32imm, i32imm, |
| 30677 | /* VCGEzv16i8 */ |
| 30678 | QPR, QPR, i32imm, i32imm, |
| 30679 | /* VCGEzv2f32 */ |
| 30680 | DPR, DPR, i32imm, i32imm, |
| 30681 | /* VCGEzv2i32 */ |
| 30682 | DPR, DPR, i32imm, i32imm, |
| 30683 | /* VCGEzv4f16 */ |
| 30684 | DPR, DPR, i32imm, i32imm, |
| 30685 | /* VCGEzv4f32 */ |
| 30686 | QPR, QPR, i32imm, i32imm, |
| 30687 | /* VCGEzv4i16 */ |
| 30688 | DPR, DPR, i32imm, i32imm, |
| 30689 | /* VCGEzv4i32 */ |
| 30690 | QPR, QPR, i32imm, i32imm, |
| 30691 | /* VCGEzv8f16 */ |
| 30692 | QPR, QPR, i32imm, i32imm, |
| 30693 | /* VCGEzv8i16 */ |
| 30694 | QPR, QPR, i32imm, i32imm, |
| 30695 | /* VCGEzv8i8 */ |
| 30696 | DPR, DPR, i32imm, i32imm, |
| 30697 | /* VCGTfd */ |
| 30698 | DPR, DPR, DPR, i32imm, i32imm, |
| 30699 | /* VCGTfq */ |
| 30700 | QPR, QPR, QPR, i32imm, i32imm, |
| 30701 | /* VCGThd */ |
| 30702 | DPR, DPR, DPR, i32imm, i32imm, |
| 30703 | /* VCGThq */ |
| 30704 | QPR, QPR, QPR, i32imm, i32imm, |
| 30705 | /* VCGTsv16i8 */ |
| 30706 | QPR, QPR, QPR, i32imm, i32imm, |
| 30707 | /* VCGTsv2i32 */ |
| 30708 | DPR, DPR, DPR, i32imm, i32imm, |
| 30709 | /* VCGTsv4i16 */ |
| 30710 | DPR, DPR, DPR, i32imm, i32imm, |
| 30711 | /* VCGTsv4i32 */ |
| 30712 | QPR, QPR, QPR, i32imm, i32imm, |
| 30713 | /* VCGTsv8i16 */ |
| 30714 | QPR, QPR, QPR, i32imm, i32imm, |
| 30715 | /* VCGTsv8i8 */ |
| 30716 | DPR, DPR, DPR, i32imm, i32imm, |
| 30717 | /* VCGTuv16i8 */ |
| 30718 | QPR, QPR, QPR, i32imm, i32imm, |
| 30719 | /* VCGTuv2i32 */ |
| 30720 | DPR, DPR, DPR, i32imm, i32imm, |
| 30721 | /* VCGTuv4i16 */ |
| 30722 | DPR, DPR, DPR, i32imm, i32imm, |
| 30723 | /* VCGTuv4i32 */ |
| 30724 | QPR, QPR, QPR, i32imm, i32imm, |
| 30725 | /* VCGTuv8i16 */ |
| 30726 | QPR, QPR, QPR, i32imm, i32imm, |
| 30727 | /* VCGTuv8i8 */ |
| 30728 | DPR, DPR, DPR, i32imm, i32imm, |
| 30729 | /* VCGTzv16i8 */ |
| 30730 | QPR, QPR, i32imm, i32imm, |
| 30731 | /* VCGTzv2f32 */ |
| 30732 | DPR, DPR, i32imm, i32imm, |
| 30733 | /* VCGTzv2i32 */ |
| 30734 | DPR, DPR, i32imm, i32imm, |
| 30735 | /* VCGTzv4f16 */ |
| 30736 | DPR, DPR, i32imm, i32imm, |
| 30737 | /* VCGTzv4f32 */ |
| 30738 | QPR, QPR, i32imm, i32imm, |
| 30739 | /* VCGTzv4i16 */ |
| 30740 | DPR, DPR, i32imm, i32imm, |
| 30741 | /* VCGTzv4i32 */ |
| 30742 | QPR, QPR, i32imm, i32imm, |
| 30743 | /* VCGTzv8f16 */ |
| 30744 | QPR, QPR, i32imm, i32imm, |
| 30745 | /* VCGTzv8i16 */ |
| 30746 | QPR, QPR, i32imm, i32imm, |
| 30747 | /* VCGTzv8i8 */ |
| 30748 | DPR, DPR, i32imm, i32imm, |
| 30749 | /* VCLEzv16i8 */ |
| 30750 | QPR, QPR, i32imm, i32imm, |
| 30751 | /* VCLEzv2f32 */ |
| 30752 | DPR, DPR, i32imm, i32imm, |
| 30753 | /* VCLEzv2i32 */ |
| 30754 | DPR, DPR, i32imm, i32imm, |
| 30755 | /* VCLEzv4f16 */ |
| 30756 | DPR, DPR, i32imm, i32imm, |
| 30757 | /* VCLEzv4f32 */ |
| 30758 | QPR, QPR, i32imm, i32imm, |
| 30759 | /* VCLEzv4i16 */ |
| 30760 | DPR, DPR, i32imm, i32imm, |
| 30761 | /* VCLEzv4i32 */ |
| 30762 | QPR, QPR, i32imm, i32imm, |
| 30763 | /* VCLEzv8f16 */ |
| 30764 | QPR, QPR, i32imm, i32imm, |
| 30765 | /* VCLEzv8i16 */ |
| 30766 | QPR, QPR, i32imm, i32imm, |
| 30767 | /* VCLEzv8i8 */ |
| 30768 | DPR, DPR, i32imm, i32imm, |
| 30769 | /* VCLSv16i8 */ |
| 30770 | QPR, QPR, i32imm, i32imm, |
| 30771 | /* VCLSv2i32 */ |
| 30772 | DPR, DPR, i32imm, i32imm, |
| 30773 | /* VCLSv4i16 */ |
| 30774 | DPR, DPR, i32imm, i32imm, |
| 30775 | /* VCLSv4i32 */ |
| 30776 | QPR, QPR, i32imm, i32imm, |
| 30777 | /* VCLSv8i16 */ |
| 30778 | QPR, QPR, i32imm, i32imm, |
| 30779 | /* VCLSv8i8 */ |
| 30780 | DPR, DPR, i32imm, i32imm, |
| 30781 | /* VCLTzv16i8 */ |
| 30782 | QPR, QPR, i32imm, i32imm, |
| 30783 | /* VCLTzv2f32 */ |
| 30784 | DPR, DPR, i32imm, i32imm, |
| 30785 | /* VCLTzv2i32 */ |
| 30786 | DPR, DPR, i32imm, i32imm, |
| 30787 | /* VCLTzv4f16 */ |
| 30788 | DPR, DPR, i32imm, i32imm, |
| 30789 | /* VCLTzv4f32 */ |
| 30790 | QPR, QPR, i32imm, i32imm, |
| 30791 | /* VCLTzv4i16 */ |
| 30792 | DPR, DPR, i32imm, i32imm, |
| 30793 | /* VCLTzv4i32 */ |
| 30794 | QPR, QPR, i32imm, i32imm, |
| 30795 | /* VCLTzv8f16 */ |
| 30796 | QPR, QPR, i32imm, i32imm, |
| 30797 | /* VCLTzv8i16 */ |
| 30798 | QPR, QPR, i32imm, i32imm, |
| 30799 | /* VCLTzv8i8 */ |
| 30800 | DPR, DPR, i32imm, i32imm, |
| 30801 | /* VCLZv16i8 */ |
| 30802 | QPR, QPR, i32imm, i32imm, |
| 30803 | /* VCLZv2i32 */ |
| 30804 | DPR, DPR, i32imm, i32imm, |
| 30805 | /* VCLZv4i16 */ |
| 30806 | DPR, DPR, i32imm, i32imm, |
| 30807 | /* VCLZv4i32 */ |
| 30808 | QPR, QPR, i32imm, i32imm, |
| 30809 | /* VCLZv8i16 */ |
| 30810 | QPR, QPR, i32imm, i32imm, |
| 30811 | /* VCLZv8i8 */ |
| 30812 | DPR, DPR, i32imm, i32imm, |
| 30813 | /* VCMLAv2f32 */ |
| 30814 | DPR, DPR, DPR, DPR, complexrotateop, |
| 30815 | /* VCMLAv2f32_indexed */ |
| 30816 | DPR, DPR, DPR, DPR, i32imm, complexrotateop, |
| 30817 | /* VCMLAv4f16 */ |
| 30818 | DPR, DPR, DPR, DPR, complexrotateop, |
| 30819 | /* VCMLAv4f16_indexed */ |
| 30820 | DPR, DPR, DPR, DPR_VFP2, i32imm, complexrotateop, |
| 30821 | /* VCMLAv4f32 */ |
| 30822 | QPR, QPR, QPR, QPR, complexrotateop, |
| 30823 | /* VCMLAv4f32_indexed */ |
| 30824 | QPR, QPR, QPR, DPR, i32imm, complexrotateop, |
| 30825 | /* VCMLAv8f16 */ |
| 30826 | QPR, QPR, QPR, QPR, complexrotateop, |
| 30827 | /* VCMLAv8f16_indexed */ |
| 30828 | QPR, QPR, QPR, DPR_VFP2, i32imm, complexrotateop, |
| 30829 | /* VCMPD */ |
| 30830 | DPR, DPR, i32imm, i32imm, |
| 30831 | /* VCMPED */ |
| 30832 | DPR, DPR, i32imm, i32imm, |
| 30833 | /* VCMPEH */ |
| 30834 | HPR, HPR, i32imm, i32imm, |
| 30835 | /* VCMPES */ |
| 30836 | SPR, SPR, i32imm, i32imm, |
| 30837 | /* VCMPEZD */ |
| 30838 | DPR, i32imm, i32imm, |
| 30839 | /* VCMPEZH */ |
| 30840 | HPR, i32imm, i32imm, |
| 30841 | /* VCMPEZS */ |
| 30842 | SPR, i32imm, i32imm, |
| 30843 | /* VCMPH */ |
| 30844 | HPR, HPR, i32imm, i32imm, |
| 30845 | /* VCMPS */ |
| 30846 | SPR, SPR, i32imm, i32imm, |
| 30847 | /* VCMPZD */ |
| 30848 | DPR, i32imm, i32imm, |
| 30849 | /* VCMPZH */ |
| 30850 | HPR, i32imm, i32imm, |
| 30851 | /* VCMPZS */ |
| 30852 | SPR, i32imm, i32imm, |
| 30853 | /* VCNTd */ |
| 30854 | DPR, DPR, i32imm, i32imm, |
| 30855 | /* VCNTq */ |
| 30856 | QPR, QPR, i32imm, i32imm, |
| 30857 | /* VCVTANSDf */ |
| 30858 | DPR, DPR, |
| 30859 | /* VCVTANSDh */ |
| 30860 | DPR, DPR, |
| 30861 | /* VCVTANSQf */ |
| 30862 | QPR, QPR, |
| 30863 | /* VCVTANSQh */ |
| 30864 | QPR, QPR, |
| 30865 | /* VCVTANUDf */ |
| 30866 | DPR, DPR, |
| 30867 | /* VCVTANUDh */ |
| 30868 | DPR, DPR, |
| 30869 | /* VCVTANUQf */ |
| 30870 | QPR, QPR, |
| 30871 | /* VCVTANUQh */ |
| 30872 | QPR, QPR, |
| 30873 | /* VCVTASD */ |
| 30874 | SPR, DPR, |
| 30875 | /* VCVTASH */ |
| 30876 | SPR, HPR, |
| 30877 | /* VCVTASS */ |
| 30878 | SPR, SPR, |
| 30879 | /* VCVTAUD */ |
| 30880 | SPR, DPR, |
| 30881 | /* VCVTAUH */ |
| 30882 | SPR, HPR, |
| 30883 | /* VCVTAUS */ |
| 30884 | SPR, SPR, |
| 30885 | /* VCVTBDH */ |
| 30886 | SPR, SPR, DPR, i32imm, i32imm, |
| 30887 | /* VCVTBHD */ |
| 30888 | DPR, SPR, i32imm, i32imm, |
| 30889 | /* VCVTBHS */ |
| 30890 | SPR, SPR, i32imm, i32imm, |
| 30891 | /* VCVTBSH */ |
| 30892 | SPR, SPR, SPR, i32imm, i32imm, |
| 30893 | /* VCVTDS */ |
| 30894 | DPR, SPR, i32imm, i32imm, |
| 30895 | /* VCVTMNSDf */ |
| 30896 | DPR, DPR, |
| 30897 | /* VCVTMNSDh */ |
| 30898 | DPR, DPR, |
| 30899 | /* VCVTMNSQf */ |
| 30900 | QPR, QPR, |
| 30901 | /* VCVTMNSQh */ |
| 30902 | QPR, QPR, |
| 30903 | /* VCVTMNUDf */ |
| 30904 | DPR, DPR, |
| 30905 | /* VCVTMNUDh */ |
| 30906 | DPR, DPR, |
| 30907 | /* VCVTMNUQf */ |
| 30908 | QPR, QPR, |
| 30909 | /* VCVTMNUQh */ |
| 30910 | QPR, QPR, |
| 30911 | /* VCVTMSD */ |
| 30912 | SPR, DPR, |
| 30913 | /* VCVTMSH */ |
| 30914 | SPR, HPR, |
| 30915 | /* VCVTMSS */ |
| 30916 | SPR, SPR, |
| 30917 | /* VCVTMUD */ |
| 30918 | SPR, DPR, |
| 30919 | /* VCVTMUH */ |
| 30920 | SPR, HPR, |
| 30921 | /* VCVTMUS */ |
| 30922 | SPR, SPR, |
| 30923 | /* VCVTNNSDf */ |
| 30924 | DPR, DPR, |
| 30925 | /* VCVTNNSDh */ |
| 30926 | DPR, DPR, |
| 30927 | /* VCVTNNSQf */ |
| 30928 | QPR, QPR, |
| 30929 | /* VCVTNNSQh */ |
| 30930 | QPR, QPR, |
| 30931 | /* VCVTNNUDf */ |
| 30932 | DPR, DPR, |
| 30933 | /* VCVTNNUDh */ |
| 30934 | DPR, DPR, |
| 30935 | /* VCVTNNUQf */ |
| 30936 | QPR, QPR, |
| 30937 | /* VCVTNNUQh */ |
| 30938 | QPR, QPR, |
| 30939 | /* VCVTNSD */ |
| 30940 | SPR, DPR, |
| 30941 | /* VCVTNSH */ |
| 30942 | SPR, HPR, |
| 30943 | /* VCVTNSS */ |
| 30944 | SPR, SPR, |
| 30945 | /* VCVTNUD */ |
| 30946 | SPR, DPR, |
| 30947 | /* VCVTNUH */ |
| 30948 | SPR, HPR, |
| 30949 | /* VCVTNUS */ |
| 30950 | SPR, SPR, |
| 30951 | /* VCVTPNSDf */ |
| 30952 | DPR, DPR, |
| 30953 | /* VCVTPNSDh */ |
| 30954 | DPR, DPR, |
| 30955 | /* VCVTPNSQf */ |
| 30956 | QPR, QPR, |
| 30957 | /* VCVTPNSQh */ |
| 30958 | QPR, QPR, |
| 30959 | /* VCVTPNUDf */ |
| 30960 | DPR, DPR, |
| 30961 | /* VCVTPNUDh */ |
| 30962 | DPR, DPR, |
| 30963 | /* VCVTPNUQf */ |
| 30964 | QPR, QPR, |
| 30965 | /* VCVTPNUQh */ |
| 30966 | QPR, QPR, |
| 30967 | /* VCVTPSD */ |
| 30968 | SPR, DPR, |
| 30969 | /* VCVTPSH */ |
| 30970 | SPR, HPR, |
| 30971 | /* VCVTPSS */ |
| 30972 | SPR, SPR, |
| 30973 | /* VCVTPUD */ |
| 30974 | SPR, DPR, |
| 30975 | /* VCVTPUH */ |
| 30976 | SPR, HPR, |
| 30977 | /* VCVTPUS */ |
| 30978 | SPR, SPR, |
| 30979 | /* VCVTSD */ |
| 30980 | SPR, DPR, i32imm, i32imm, |
| 30981 | /* VCVTTDH */ |
| 30982 | SPR, SPR, DPR, i32imm, i32imm, |
| 30983 | /* VCVTTHD */ |
| 30984 | DPR, SPR, i32imm, i32imm, |
| 30985 | /* VCVTTHS */ |
| 30986 | SPR, SPR, i32imm, i32imm, |
| 30987 | /* VCVTTSH */ |
| 30988 | SPR, SPR, SPR, i32imm, i32imm, |
| 30989 | /* VCVTf2h */ |
| 30990 | DPR, QPR, i32imm, i32imm, |
| 30991 | /* VCVTf2sd */ |
| 30992 | DPR, DPR, i32imm, i32imm, |
| 30993 | /* VCVTf2sq */ |
| 30994 | QPR, QPR, i32imm, i32imm, |
| 30995 | /* VCVTf2ud */ |
| 30996 | DPR, DPR, i32imm, i32imm, |
| 30997 | /* VCVTf2uq */ |
| 30998 | QPR, QPR, i32imm, i32imm, |
| 30999 | /* VCVTf2xsd */ |
| 31000 | DPR, DPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31001 | /* VCVTf2xsq */ |
| 31002 | QPR, QPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31003 | /* VCVTf2xud */ |
| 31004 | DPR, DPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31005 | /* VCVTf2xuq */ |
| 31006 | QPR, QPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31007 | /* VCVTh2f */ |
| 31008 | QPR, DPR, i32imm, i32imm, |
| 31009 | /* VCVTh2sd */ |
| 31010 | DPR, DPR, i32imm, i32imm, |
| 31011 | /* VCVTh2sq */ |
| 31012 | QPR, QPR, i32imm, i32imm, |
| 31013 | /* VCVTh2ud */ |
| 31014 | DPR, DPR, i32imm, i32imm, |
| 31015 | /* VCVTh2uq */ |
| 31016 | QPR, QPR, i32imm, i32imm, |
| 31017 | /* VCVTh2xsd */ |
| 31018 | DPR, DPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31019 | /* VCVTh2xsq */ |
| 31020 | QPR, QPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31021 | /* VCVTh2xud */ |
| 31022 | DPR, DPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31023 | /* VCVTh2xuq */ |
| 31024 | QPR, QPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31025 | /* VCVTs2fd */ |
| 31026 | DPR, DPR, i32imm, i32imm, |
| 31027 | /* VCVTs2fq */ |
| 31028 | QPR, QPR, i32imm, i32imm, |
| 31029 | /* VCVTs2hd */ |
| 31030 | DPR, DPR, i32imm, i32imm, |
| 31031 | /* VCVTs2hq */ |
| 31032 | QPR, QPR, i32imm, i32imm, |
| 31033 | /* VCVTu2fd */ |
| 31034 | DPR, DPR, i32imm, i32imm, |
| 31035 | /* VCVTu2fq */ |
| 31036 | QPR, QPR, i32imm, i32imm, |
| 31037 | /* VCVTu2hd */ |
| 31038 | DPR, DPR, i32imm, i32imm, |
| 31039 | /* VCVTu2hq */ |
| 31040 | QPR, QPR, i32imm, i32imm, |
| 31041 | /* VCVTxs2fd */ |
| 31042 | DPR, DPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31043 | /* VCVTxs2fq */ |
| 31044 | QPR, QPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31045 | /* VCVTxs2hd */ |
| 31046 | DPR, DPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31047 | /* VCVTxs2hq */ |
| 31048 | QPR, QPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31049 | /* VCVTxu2fd */ |
| 31050 | DPR, DPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31051 | /* VCVTxu2fq */ |
| 31052 | QPR, QPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31053 | /* VCVTxu2hd */ |
| 31054 | DPR, DPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31055 | /* VCVTxu2hq */ |
| 31056 | QPR, QPR, neon_vcvt_imm32, i32imm, i32imm, |
| 31057 | /* VDIVD */ |
| 31058 | DPR, DPR, DPR, i32imm, i32imm, |
| 31059 | /* VDIVH */ |
| 31060 | HPR, HPR, HPR, i32imm, i32imm, |
| 31061 | /* VDIVS */ |
| 31062 | SPR, SPR, SPR, i32imm, i32imm, |
| 31063 | /* VDUP16d */ |
| 31064 | DPR, GPR, i32imm, i32imm, |
| 31065 | /* VDUP16q */ |
| 31066 | QPR, GPR, i32imm, i32imm, |
| 31067 | /* VDUP32d */ |
| 31068 | DPR, GPR, i32imm, i32imm, |
| 31069 | /* VDUP32q */ |
| 31070 | QPR, GPR, i32imm, i32imm, |
| 31071 | /* VDUP8d */ |
| 31072 | DPR, GPR, i32imm, i32imm, |
| 31073 | /* VDUP8q */ |
| 31074 | QPR, GPR, i32imm, i32imm, |
| 31075 | /* VDUPLN16d */ |
| 31076 | DPR, DPR, i32imm, i32imm, i32imm, |
| 31077 | /* VDUPLN16q */ |
| 31078 | QPR, DPR, i32imm, i32imm, i32imm, |
| 31079 | /* VDUPLN32d */ |
| 31080 | DPR, DPR, i32imm, i32imm, i32imm, |
| 31081 | /* VDUPLN32q */ |
| 31082 | QPR, DPR, i32imm, i32imm, i32imm, |
| 31083 | /* VDUPLN8d */ |
| 31084 | DPR, DPR, i32imm, i32imm, i32imm, |
| 31085 | /* VDUPLN8q */ |
| 31086 | QPR, DPR, i32imm, i32imm, i32imm, |
| 31087 | /* VEORd */ |
| 31088 | DPR, DPR, DPR, i32imm, i32imm, |
| 31089 | /* VEORq */ |
| 31090 | QPR, QPR, QPR, i32imm, i32imm, |
| 31091 | /* VEXTd16 */ |
| 31092 | DPR, DPR, DPR, imm0_3, i32imm, i32imm, |
| 31093 | /* VEXTd32 */ |
| 31094 | DPR, DPR, DPR, imm0_1, i32imm, i32imm, |
| 31095 | /* VEXTd8 */ |
| 31096 | DPR, DPR, DPR, imm0_7, i32imm, i32imm, |
| 31097 | /* VEXTq16 */ |
| 31098 | QPR, QPR, QPR, imm0_7, i32imm, i32imm, |
| 31099 | /* VEXTq32 */ |
| 31100 | QPR, QPR, QPR, imm0_3, i32imm, i32imm, |
| 31101 | /* VEXTq64 */ |
| 31102 | QPR, QPR, QPR, imm0_1, i32imm, i32imm, |
| 31103 | /* VEXTq8 */ |
| 31104 | QPR, QPR, QPR, imm0_15, i32imm, i32imm, |
| 31105 | /* VFMAD */ |
| 31106 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 31107 | /* VFMAH */ |
| 31108 | HPR, HPR, HPR, HPR, i32imm, i32imm, |
| 31109 | /* VFMALD */ |
| 31110 | DPR, SPR, SPR, |
| 31111 | /* VFMALDI */ |
| 31112 | DPR, SPR, SPR_8, i32imm, |
| 31113 | /* VFMALQ */ |
| 31114 | QPR, DPR, DPR, |
| 31115 | /* VFMALQI */ |
| 31116 | QPR, DPR, DPR_8, i32imm, |
| 31117 | /* VFMAS */ |
| 31118 | SPR, SPR, SPR, SPR, i32imm, i32imm, |
| 31119 | /* VFMAfd */ |
| 31120 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 31121 | /* VFMAfq */ |
| 31122 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 31123 | /* VFMAhd */ |
| 31124 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 31125 | /* VFMAhq */ |
| 31126 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 31127 | /* VFMSD */ |
| 31128 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 31129 | /* VFMSH */ |
| 31130 | HPR, HPR, HPR, HPR, i32imm, i32imm, |
| 31131 | /* VFMSLD */ |
| 31132 | DPR, SPR, SPR, |
| 31133 | /* VFMSLDI */ |
| 31134 | DPR, SPR, SPR_8, i32imm, |
| 31135 | /* VFMSLQ */ |
| 31136 | QPR, DPR, DPR, |
| 31137 | /* VFMSLQI */ |
| 31138 | QPR, DPR, DPR_8, i32imm, |
| 31139 | /* VFMSS */ |
| 31140 | SPR, SPR, SPR, SPR, i32imm, i32imm, |
| 31141 | /* VFMSfd */ |
| 31142 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 31143 | /* VFMSfq */ |
| 31144 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 31145 | /* VFMShd */ |
| 31146 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 31147 | /* VFMShq */ |
| 31148 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 31149 | /* VFNMAD */ |
| 31150 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 31151 | /* VFNMAH */ |
| 31152 | HPR, HPR, HPR, HPR, i32imm, i32imm, |
| 31153 | /* VFNMAS */ |
| 31154 | SPR, SPR, SPR, SPR, i32imm, i32imm, |
| 31155 | /* VFNMSD */ |
| 31156 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 31157 | /* VFNMSH */ |
| 31158 | HPR, HPR, HPR, HPR, i32imm, i32imm, |
| 31159 | /* VFNMSS */ |
| 31160 | SPR, SPR, SPR, SPR, i32imm, i32imm, |
| 31161 | /* VFP_VMAXNMD */ |
| 31162 | DPR, DPR, DPR, |
| 31163 | /* VFP_VMAXNMH */ |
| 31164 | HPR, HPR, HPR, |
| 31165 | /* VFP_VMAXNMS */ |
| 31166 | SPR, SPR, SPR, |
| 31167 | /* VFP_VMINNMD */ |
| 31168 | DPR, DPR, DPR, |
| 31169 | /* VFP_VMINNMH */ |
| 31170 | HPR, HPR, HPR, |
| 31171 | /* VFP_VMINNMS */ |
| 31172 | SPR, SPR, SPR, |
| 31173 | /* VGETLNi32 */ |
| 31174 | GPR, DPR, i32imm, i32imm, i32imm, |
| 31175 | /* VGETLNs16 */ |
| 31176 | GPR, DPR, i32imm, i32imm, i32imm, |
| 31177 | /* VGETLNs8 */ |
| 31178 | GPR, DPR, i32imm, i32imm, i32imm, |
| 31179 | /* VGETLNu16 */ |
| 31180 | GPR, DPR, i32imm, i32imm, i32imm, |
| 31181 | /* VGETLNu8 */ |
| 31182 | GPR, DPR, i32imm, i32imm, i32imm, |
| 31183 | /* VHADDsv16i8 */ |
| 31184 | QPR, QPR, QPR, i32imm, i32imm, |
| 31185 | /* VHADDsv2i32 */ |
| 31186 | DPR, DPR, DPR, i32imm, i32imm, |
| 31187 | /* VHADDsv4i16 */ |
| 31188 | DPR, DPR, DPR, i32imm, i32imm, |
| 31189 | /* VHADDsv4i32 */ |
| 31190 | QPR, QPR, QPR, i32imm, i32imm, |
| 31191 | /* VHADDsv8i16 */ |
| 31192 | QPR, QPR, QPR, i32imm, i32imm, |
| 31193 | /* VHADDsv8i8 */ |
| 31194 | DPR, DPR, DPR, i32imm, i32imm, |
| 31195 | /* VHADDuv16i8 */ |
| 31196 | QPR, QPR, QPR, i32imm, i32imm, |
| 31197 | /* VHADDuv2i32 */ |
| 31198 | DPR, DPR, DPR, i32imm, i32imm, |
| 31199 | /* VHADDuv4i16 */ |
| 31200 | DPR, DPR, DPR, i32imm, i32imm, |
| 31201 | /* VHADDuv4i32 */ |
| 31202 | QPR, QPR, QPR, i32imm, i32imm, |
| 31203 | /* VHADDuv8i16 */ |
| 31204 | QPR, QPR, QPR, i32imm, i32imm, |
| 31205 | /* VHADDuv8i8 */ |
| 31206 | DPR, DPR, DPR, i32imm, i32imm, |
| 31207 | /* VHSUBsv16i8 */ |
| 31208 | QPR, QPR, QPR, i32imm, i32imm, |
| 31209 | /* VHSUBsv2i32 */ |
| 31210 | DPR, DPR, DPR, i32imm, i32imm, |
| 31211 | /* VHSUBsv4i16 */ |
| 31212 | DPR, DPR, DPR, i32imm, i32imm, |
| 31213 | /* VHSUBsv4i32 */ |
| 31214 | QPR, QPR, QPR, i32imm, i32imm, |
| 31215 | /* VHSUBsv8i16 */ |
| 31216 | QPR, QPR, QPR, i32imm, i32imm, |
| 31217 | /* VHSUBsv8i8 */ |
| 31218 | DPR, DPR, DPR, i32imm, i32imm, |
| 31219 | /* VHSUBuv16i8 */ |
| 31220 | QPR, QPR, QPR, i32imm, i32imm, |
| 31221 | /* VHSUBuv2i32 */ |
| 31222 | DPR, DPR, DPR, i32imm, i32imm, |
| 31223 | /* VHSUBuv4i16 */ |
| 31224 | DPR, DPR, DPR, i32imm, i32imm, |
| 31225 | /* VHSUBuv4i32 */ |
| 31226 | QPR, QPR, QPR, i32imm, i32imm, |
| 31227 | /* VHSUBuv8i16 */ |
| 31228 | QPR, QPR, QPR, i32imm, i32imm, |
| 31229 | /* VHSUBuv8i8 */ |
| 31230 | DPR, DPR, DPR, i32imm, i32imm, |
| 31231 | /* VINSH */ |
| 31232 | SPR, SPR, SPR, |
| 31233 | /* VJCVT */ |
| 31234 | SPR, DPR, i32imm, i32imm, |
| 31235 | /* VLD1DUPd16 */ |
| 31236 | VecListOneDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 31237 | /* VLD1DUPd16wb_fixed */ |
| 31238 | VecListOneDAllLanes, GPR, GPR, i32imm, i32imm, i32imm, |
| 31239 | /* VLD1DUPd16wb_register */ |
| 31240 | VecListOneDAllLanes, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31241 | /* VLD1DUPd32 */ |
| 31242 | VecListOneDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 31243 | /* VLD1DUPd32wb_fixed */ |
| 31244 | VecListOneDAllLanes, GPR, GPR, i32imm, i32imm, i32imm, |
| 31245 | /* VLD1DUPd32wb_register */ |
| 31246 | VecListOneDAllLanes, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31247 | /* VLD1DUPd8 */ |
| 31248 | VecListOneDAllLanes, GPR, i32imm, i32imm, i32imm, |
| 31249 | /* VLD1DUPd8wb_fixed */ |
| 31250 | VecListOneDAllLanes, GPR, GPR, i32imm, i32imm, i32imm, |
| 31251 | /* VLD1DUPd8wb_register */ |
| 31252 | VecListOneDAllLanes, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31253 | /* VLD1DUPq16 */ |
| 31254 | VecListDPairAllLanes, GPR, i32imm, i32imm, i32imm, |
| 31255 | /* VLD1DUPq16wb_fixed */ |
| 31256 | VecListDPairAllLanes, GPR, GPR, i32imm, i32imm, i32imm, |
| 31257 | /* VLD1DUPq16wb_register */ |
| 31258 | VecListDPairAllLanes, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31259 | /* VLD1DUPq32 */ |
| 31260 | VecListDPairAllLanes, GPR, i32imm, i32imm, i32imm, |
| 31261 | /* VLD1DUPq32wb_fixed */ |
| 31262 | VecListDPairAllLanes, GPR, GPR, i32imm, i32imm, i32imm, |
| 31263 | /* VLD1DUPq32wb_register */ |
| 31264 | VecListDPairAllLanes, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31265 | /* VLD1DUPq8 */ |
| 31266 | VecListDPairAllLanes, GPR, i32imm, i32imm, i32imm, |
| 31267 | /* VLD1DUPq8wb_fixed */ |
| 31268 | VecListDPairAllLanes, GPR, GPR, i32imm, i32imm, i32imm, |
| 31269 | /* VLD1DUPq8wb_register */ |
| 31270 | VecListDPairAllLanes, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31271 | /* VLD1LNd16 */ |
| 31272 | DPR, GPR, i32imm, DPR, nohash_imm, i32imm, i32imm, |
| 31273 | /* VLD1LNd16_UPD */ |
| 31274 | DPR, GPR, GPR, i32imm, GPR, DPR, nohash_imm, i32imm, i32imm, |
| 31275 | /* VLD1LNd32 */ |
| 31276 | DPR, GPR, i32imm, DPR, nohash_imm, i32imm, i32imm, |
| 31277 | /* VLD1LNd32_UPD */ |
| 31278 | DPR, GPR, GPR, i32imm, GPR, DPR, nohash_imm, i32imm, i32imm, |
| 31279 | /* VLD1LNd8 */ |
| 31280 | DPR, GPR, i32imm, DPR, nohash_imm, i32imm, i32imm, |
| 31281 | /* VLD1LNd8_UPD */ |
| 31282 | DPR, GPR, GPR, i32imm, GPR, DPR, nohash_imm, i32imm, i32imm, |
| 31283 | /* VLD1LNq16Pseudo */ |
| 31284 | QPR, GPR, i32imm, QPR, nohash_imm, i32imm, i32imm, |
| 31285 | /* VLD1LNq16Pseudo_UPD */ |
| 31286 | QPR, GPR, GPR, i32imm, GPR, QPR, nohash_imm, i32imm, i32imm, |
| 31287 | /* VLD1LNq32Pseudo */ |
| 31288 | QPR, GPR, i32imm, QPR, nohash_imm, i32imm, i32imm, |
| 31289 | /* VLD1LNq32Pseudo_UPD */ |
| 31290 | QPR, GPR, GPR, i32imm, GPR, QPR, nohash_imm, i32imm, i32imm, |
| 31291 | /* VLD1LNq8Pseudo */ |
| 31292 | QPR, GPR, i32imm, QPR, nohash_imm, i32imm, i32imm, |
| 31293 | /* VLD1LNq8Pseudo_UPD */ |
| 31294 | QPR, GPR, GPR, i32imm, GPR, QPR, nohash_imm, i32imm, i32imm, |
| 31295 | /* VLD1d16 */ |
| 31296 | VecListOneD, GPR, i32imm, i32imm, i32imm, |
| 31297 | /* VLD1d16Q */ |
| 31298 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 31299 | /* VLD1d16QPseudo */ |
| 31300 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31301 | /* VLD1d16QPseudoWB_fixed */ |
| 31302 | QQPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 31303 | /* VLD1d16QPseudoWB_register */ |
| 31304 | QQPR, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31305 | /* VLD1d16Qwb_fixed */ |
| 31306 | VecListFourD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31307 | /* VLD1d16Qwb_register */ |
| 31308 | VecListFourD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31309 | /* VLD1d16T */ |
| 31310 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 31311 | /* VLD1d16TPseudo */ |
| 31312 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31313 | /* VLD1d16TPseudoWB_fixed */ |
| 31314 | QQPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 31315 | /* VLD1d16TPseudoWB_register */ |
| 31316 | QQPR, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31317 | /* VLD1d16Twb_fixed */ |
| 31318 | VecListThreeD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31319 | /* VLD1d16Twb_register */ |
| 31320 | VecListThreeD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31321 | /* VLD1d16wb_fixed */ |
| 31322 | VecListOneD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31323 | /* VLD1d16wb_register */ |
| 31324 | VecListOneD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31325 | /* VLD1d32 */ |
| 31326 | VecListOneD, GPR, i32imm, i32imm, i32imm, |
| 31327 | /* VLD1d32Q */ |
| 31328 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 31329 | /* VLD1d32QPseudo */ |
| 31330 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31331 | /* VLD1d32QPseudoWB_fixed */ |
| 31332 | QQPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 31333 | /* VLD1d32QPseudoWB_register */ |
| 31334 | QQPR, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31335 | /* VLD1d32Qwb_fixed */ |
| 31336 | VecListFourD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31337 | /* VLD1d32Qwb_register */ |
| 31338 | VecListFourD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31339 | /* VLD1d32T */ |
| 31340 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 31341 | /* VLD1d32TPseudo */ |
| 31342 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31343 | /* VLD1d32TPseudoWB_fixed */ |
| 31344 | QQPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 31345 | /* VLD1d32TPseudoWB_register */ |
| 31346 | QQPR, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31347 | /* VLD1d32Twb_fixed */ |
| 31348 | VecListThreeD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31349 | /* VLD1d32Twb_register */ |
| 31350 | VecListThreeD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31351 | /* VLD1d32wb_fixed */ |
| 31352 | VecListOneD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31353 | /* VLD1d32wb_register */ |
| 31354 | VecListOneD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31355 | /* VLD1d64 */ |
| 31356 | VecListOneD, GPR, i32imm, i32imm, i32imm, |
| 31357 | /* VLD1d64Q */ |
| 31358 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 31359 | /* VLD1d64QPseudo */ |
| 31360 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31361 | /* VLD1d64QPseudoWB_fixed */ |
| 31362 | QQPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 31363 | /* VLD1d64QPseudoWB_register */ |
| 31364 | QQPR, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31365 | /* VLD1d64Qwb_fixed */ |
| 31366 | VecListFourD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31367 | /* VLD1d64Qwb_register */ |
| 31368 | VecListFourD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31369 | /* VLD1d64T */ |
| 31370 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 31371 | /* VLD1d64TPseudo */ |
| 31372 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31373 | /* VLD1d64TPseudoWB_fixed */ |
| 31374 | QQPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 31375 | /* VLD1d64TPseudoWB_register */ |
| 31376 | QQPR, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31377 | /* VLD1d64Twb_fixed */ |
| 31378 | VecListThreeD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31379 | /* VLD1d64Twb_register */ |
| 31380 | VecListThreeD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31381 | /* VLD1d64wb_fixed */ |
| 31382 | VecListOneD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31383 | /* VLD1d64wb_register */ |
| 31384 | VecListOneD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31385 | /* VLD1d8 */ |
| 31386 | VecListOneD, GPR, i32imm, i32imm, i32imm, |
| 31387 | /* VLD1d8Q */ |
| 31388 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 31389 | /* VLD1d8QPseudo */ |
| 31390 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31391 | /* VLD1d8QPseudoWB_fixed */ |
| 31392 | QQPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 31393 | /* VLD1d8QPseudoWB_register */ |
| 31394 | QQPR, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31395 | /* VLD1d8Qwb_fixed */ |
| 31396 | VecListFourD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31397 | /* VLD1d8Qwb_register */ |
| 31398 | VecListFourD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31399 | /* VLD1d8T */ |
| 31400 | VecListThreeD, GPR, i32imm, i32imm, i32imm, |
| 31401 | /* VLD1d8TPseudo */ |
| 31402 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31403 | /* VLD1d8TPseudoWB_fixed */ |
| 31404 | QQPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 31405 | /* VLD1d8TPseudoWB_register */ |
| 31406 | QQPR, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31407 | /* VLD1d8Twb_fixed */ |
| 31408 | VecListThreeD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31409 | /* VLD1d8Twb_register */ |
| 31410 | VecListThreeD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31411 | /* VLD1d8wb_fixed */ |
| 31412 | VecListOneD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31413 | /* VLD1d8wb_register */ |
| 31414 | VecListOneD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31415 | /* VLD1q16 */ |
| 31416 | VecListDPair, GPR, i32imm, i32imm, i32imm, |
| 31417 | /* VLD1q16HighQPseudo */ |
| 31418 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31419 | /* VLD1q16HighQPseudo_UPD */ |
| 31420 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31421 | /* VLD1q16HighTPseudo */ |
| 31422 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31423 | /* VLD1q16HighTPseudo_UPD */ |
| 31424 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31425 | /* VLD1q16LowQPseudo_UPD */ |
| 31426 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31427 | /* VLD1q16LowTPseudo_UPD */ |
| 31428 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31429 | /* VLD1q16wb_fixed */ |
| 31430 | VecListDPair, GPR, GPR, i32imm, i32imm, i32imm, |
| 31431 | /* VLD1q16wb_register */ |
| 31432 | VecListDPair, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31433 | /* VLD1q32 */ |
| 31434 | VecListDPair, GPR, i32imm, i32imm, i32imm, |
| 31435 | /* VLD1q32HighQPseudo */ |
| 31436 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31437 | /* VLD1q32HighQPseudo_UPD */ |
| 31438 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31439 | /* VLD1q32HighTPseudo */ |
| 31440 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31441 | /* VLD1q32HighTPseudo_UPD */ |
| 31442 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31443 | /* VLD1q32LowQPseudo_UPD */ |
| 31444 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31445 | /* VLD1q32LowTPseudo_UPD */ |
| 31446 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31447 | /* VLD1q32wb_fixed */ |
| 31448 | VecListDPair, GPR, GPR, i32imm, i32imm, i32imm, |
| 31449 | /* VLD1q32wb_register */ |
| 31450 | VecListDPair, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31451 | /* VLD1q64 */ |
| 31452 | VecListDPair, GPR, i32imm, i32imm, i32imm, |
| 31453 | /* VLD1q64HighQPseudo */ |
| 31454 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31455 | /* VLD1q64HighQPseudo_UPD */ |
| 31456 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31457 | /* VLD1q64HighTPseudo */ |
| 31458 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31459 | /* VLD1q64HighTPseudo_UPD */ |
| 31460 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31461 | /* VLD1q64LowQPseudo_UPD */ |
| 31462 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31463 | /* VLD1q64LowTPseudo_UPD */ |
| 31464 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31465 | /* VLD1q64wb_fixed */ |
| 31466 | VecListDPair, GPR, GPR, i32imm, i32imm, i32imm, |
| 31467 | /* VLD1q64wb_register */ |
| 31468 | VecListDPair, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31469 | /* VLD1q8 */ |
| 31470 | VecListDPair, GPR, i32imm, i32imm, i32imm, |
| 31471 | /* VLD1q8HighQPseudo */ |
| 31472 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31473 | /* VLD1q8HighQPseudo_UPD */ |
| 31474 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31475 | /* VLD1q8HighTPseudo */ |
| 31476 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31477 | /* VLD1q8HighTPseudo_UPD */ |
| 31478 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31479 | /* VLD1q8LowQPseudo_UPD */ |
| 31480 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31481 | /* VLD1q8LowTPseudo_UPD */ |
| 31482 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31483 | /* VLD1q8wb_fixed */ |
| 31484 | VecListDPair, GPR, GPR, i32imm, i32imm, i32imm, |
| 31485 | /* VLD1q8wb_register */ |
| 31486 | VecListDPair, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31487 | /* VLD2DUPd16 */ |
| 31488 | VecListDPairAllLanes, GPR, i32imm, i32imm, i32imm, |
| 31489 | /* VLD2DUPd16wb_fixed */ |
| 31490 | VecListDPairAllLanes, GPR, GPR, i32imm, i32imm, i32imm, |
| 31491 | /* VLD2DUPd16wb_register */ |
| 31492 | VecListDPairAllLanes, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31493 | /* VLD2DUPd16x2 */ |
| 31494 | VecListDPairSpacedAllLanes, GPR, i32imm, i32imm, i32imm, |
| 31495 | /* VLD2DUPd16x2wb_fixed */ |
| 31496 | VecListDPairSpacedAllLanes, GPR, GPR, i32imm, i32imm, i32imm, |
| 31497 | /* VLD2DUPd16x2wb_register */ |
| 31498 | VecListDPairSpacedAllLanes, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31499 | /* VLD2DUPd32 */ |
| 31500 | VecListDPairAllLanes, GPR, i32imm, i32imm, i32imm, |
| 31501 | /* VLD2DUPd32wb_fixed */ |
| 31502 | VecListDPairAllLanes, GPR, GPR, i32imm, i32imm, i32imm, |
| 31503 | /* VLD2DUPd32wb_register */ |
| 31504 | VecListDPairAllLanes, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31505 | /* VLD2DUPd32x2 */ |
| 31506 | VecListDPairSpacedAllLanes, GPR, i32imm, i32imm, i32imm, |
| 31507 | /* VLD2DUPd32x2wb_fixed */ |
| 31508 | VecListDPairSpacedAllLanes, GPR, GPR, i32imm, i32imm, i32imm, |
| 31509 | /* VLD2DUPd32x2wb_register */ |
| 31510 | VecListDPairSpacedAllLanes, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31511 | /* VLD2DUPd8 */ |
| 31512 | VecListDPairAllLanes, GPR, i32imm, i32imm, i32imm, |
| 31513 | /* VLD2DUPd8wb_fixed */ |
| 31514 | VecListDPairAllLanes, GPR, GPR, i32imm, i32imm, i32imm, |
| 31515 | /* VLD2DUPd8wb_register */ |
| 31516 | VecListDPairAllLanes, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31517 | /* VLD2DUPd8x2 */ |
| 31518 | VecListDPairSpacedAllLanes, GPR, i32imm, i32imm, i32imm, |
| 31519 | /* VLD2DUPd8x2wb_fixed */ |
| 31520 | VecListDPairSpacedAllLanes, GPR, GPR, i32imm, i32imm, i32imm, |
| 31521 | /* VLD2DUPd8x2wb_register */ |
| 31522 | VecListDPairSpacedAllLanes, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31523 | /* VLD2DUPq16EvenPseudo */ |
| 31524 | QQPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 31525 | /* VLD2DUPq16OddPseudo */ |
| 31526 | QQPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 31527 | /* VLD2DUPq16OddPseudoWB_fixed */ |
| 31528 | QQPR, GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 31529 | /* VLD2DUPq16OddPseudoWB_register */ |
| 31530 | QQPR, GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 31531 | /* VLD2DUPq32EvenPseudo */ |
| 31532 | QQPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 31533 | /* VLD2DUPq32OddPseudo */ |
| 31534 | QQPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 31535 | /* VLD2DUPq32OddPseudoWB_fixed */ |
| 31536 | QQPR, GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 31537 | /* VLD2DUPq32OddPseudoWB_register */ |
| 31538 | QQPR, GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 31539 | /* VLD2DUPq8EvenPseudo */ |
| 31540 | QQPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 31541 | /* VLD2DUPq8OddPseudo */ |
| 31542 | QQPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 31543 | /* VLD2DUPq8OddPseudoWB_fixed */ |
| 31544 | QQPR, GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 31545 | /* VLD2DUPq8OddPseudoWB_register */ |
| 31546 | QQPR, GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 31547 | /* VLD2LNd16 */ |
| 31548 | DPR, DPR, GPR, i32imm, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31549 | /* VLD2LNd16Pseudo */ |
| 31550 | QPR, GPR, i32imm, QPR, nohash_imm, i32imm, i32imm, |
| 31551 | /* VLD2LNd16Pseudo_UPD */ |
| 31552 | QPR, GPR, GPR, i32imm, GPR, QPR, nohash_imm, i32imm, i32imm, |
| 31553 | /* VLD2LNd16_UPD */ |
| 31554 | DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31555 | /* VLD2LNd32 */ |
| 31556 | DPR, DPR, GPR, i32imm, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31557 | /* VLD2LNd32Pseudo */ |
| 31558 | QPR, GPR, i32imm, QPR, nohash_imm, i32imm, i32imm, |
| 31559 | /* VLD2LNd32Pseudo_UPD */ |
| 31560 | QPR, GPR, GPR, i32imm, GPR, QPR, nohash_imm, i32imm, i32imm, |
| 31561 | /* VLD2LNd32_UPD */ |
| 31562 | DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31563 | /* VLD2LNd8 */ |
| 31564 | DPR, DPR, GPR, i32imm, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31565 | /* VLD2LNd8Pseudo */ |
| 31566 | QPR, GPR, i32imm, QPR, nohash_imm, i32imm, i32imm, |
| 31567 | /* VLD2LNd8Pseudo_UPD */ |
| 31568 | QPR, GPR, GPR, i32imm, GPR, QPR, nohash_imm, i32imm, i32imm, |
| 31569 | /* VLD2LNd8_UPD */ |
| 31570 | DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31571 | /* VLD2LNq16 */ |
| 31572 | DPR, DPR, GPR, i32imm, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31573 | /* VLD2LNq16Pseudo */ |
| 31574 | QQPR, GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 31575 | /* VLD2LNq16Pseudo_UPD */ |
| 31576 | QQPR, GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 31577 | /* VLD2LNq16_UPD */ |
| 31578 | DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31579 | /* VLD2LNq32 */ |
| 31580 | DPR, DPR, GPR, i32imm, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31581 | /* VLD2LNq32Pseudo */ |
| 31582 | QQPR, GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 31583 | /* VLD2LNq32Pseudo_UPD */ |
| 31584 | QQPR, GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 31585 | /* VLD2LNq32_UPD */ |
| 31586 | DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31587 | /* VLD2b16 */ |
| 31588 | VecListDPairSpaced, GPR, i32imm, i32imm, i32imm, |
| 31589 | /* VLD2b16wb_fixed */ |
| 31590 | VecListDPairSpaced, GPR, GPR, i32imm, i32imm, i32imm, |
| 31591 | /* VLD2b16wb_register */ |
| 31592 | VecListDPairSpaced, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31593 | /* VLD2b32 */ |
| 31594 | VecListDPairSpaced, GPR, i32imm, i32imm, i32imm, |
| 31595 | /* VLD2b32wb_fixed */ |
| 31596 | VecListDPairSpaced, GPR, GPR, i32imm, i32imm, i32imm, |
| 31597 | /* VLD2b32wb_register */ |
| 31598 | VecListDPairSpaced, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31599 | /* VLD2b8 */ |
| 31600 | VecListDPairSpaced, GPR, i32imm, i32imm, i32imm, |
| 31601 | /* VLD2b8wb_fixed */ |
| 31602 | VecListDPairSpaced, GPR, GPR, i32imm, i32imm, i32imm, |
| 31603 | /* VLD2b8wb_register */ |
| 31604 | VecListDPairSpaced, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31605 | /* VLD2d16 */ |
| 31606 | VecListDPair, GPR, i32imm, i32imm, i32imm, |
| 31607 | /* VLD2d16wb_fixed */ |
| 31608 | VecListDPair, GPR, GPR, i32imm, i32imm, i32imm, |
| 31609 | /* VLD2d16wb_register */ |
| 31610 | VecListDPair, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31611 | /* VLD2d32 */ |
| 31612 | VecListDPair, GPR, i32imm, i32imm, i32imm, |
| 31613 | /* VLD2d32wb_fixed */ |
| 31614 | VecListDPair, GPR, GPR, i32imm, i32imm, i32imm, |
| 31615 | /* VLD2d32wb_register */ |
| 31616 | VecListDPair, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31617 | /* VLD2d8 */ |
| 31618 | VecListDPair, GPR, i32imm, i32imm, i32imm, |
| 31619 | /* VLD2d8wb_fixed */ |
| 31620 | VecListDPair, GPR, GPR, i32imm, i32imm, i32imm, |
| 31621 | /* VLD2d8wb_register */ |
| 31622 | VecListDPair, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31623 | /* VLD2q16 */ |
| 31624 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 31625 | /* VLD2q16Pseudo */ |
| 31626 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31627 | /* VLD2q16PseudoWB_fixed */ |
| 31628 | QQPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 31629 | /* VLD2q16PseudoWB_register */ |
| 31630 | QQPR, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31631 | /* VLD2q16wb_fixed */ |
| 31632 | VecListFourD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31633 | /* VLD2q16wb_register */ |
| 31634 | VecListFourD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31635 | /* VLD2q32 */ |
| 31636 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 31637 | /* VLD2q32Pseudo */ |
| 31638 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31639 | /* VLD2q32PseudoWB_fixed */ |
| 31640 | QQPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 31641 | /* VLD2q32PseudoWB_register */ |
| 31642 | QQPR, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31643 | /* VLD2q32wb_fixed */ |
| 31644 | VecListFourD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31645 | /* VLD2q32wb_register */ |
| 31646 | VecListFourD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31647 | /* VLD2q8 */ |
| 31648 | VecListFourD, GPR, i32imm, i32imm, i32imm, |
| 31649 | /* VLD2q8Pseudo */ |
| 31650 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31651 | /* VLD2q8PseudoWB_fixed */ |
| 31652 | QQPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 31653 | /* VLD2q8PseudoWB_register */ |
| 31654 | QQPR, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31655 | /* VLD2q8wb_fixed */ |
| 31656 | VecListFourD, GPR, GPR, i32imm, i32imm, i32imm, |
| 31657 | /* VLD2q8wb_register */ |
| 31658 | VecListFourD, GPR, GPR, i32imm, rGPR, i32imm, i32imm, |
| 31659 | /* VLD3DUPd16 */ |
| 31660 | DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31661 | /* VLD3DUPd16Pseudo */ |
| 31662 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31663 | /* VLD3DUPd16Pseudo_UPD */ |
| 31664 | QQPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31665 | /* VLD3DUPd16_UPD */ |
| 31666 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31667 | /* VLD3DUPd32 */ |
| 31668 | DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31669 | /* VLD3DUPd32Pseudo */ |
| 31670 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31671 | /* VLD3DUPd32Pseudo_UPD */ |
| 31672 | QQPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31673 | /* VLD3DUPd32_UPD */ |
| 31674 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31675 | /* VLD3DUPd8 */ |
| 31676 | DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31677 | /* VLD3DUPd8Pseudo */ |
| 31678 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31679 | /* VLD3DUPd8Pseudo_UPD */ |
| 31680 | QQPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31681 | /* VLD3DUPd8_UPD */ |
| 31682 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31683 | /* VLD3DUPq16 */ |
| 31684 | DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31685 | /* VLD3DUPq16EvenPseudo */ |
| 31686 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31687 | /* VLD3DUPq16OddPseudo */ |
| 31688 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31689 | /* VLD3DUPq16OddPseudo_UPD */ |
| 31690 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31691 | /* VLD3DUPq16_UPD */ |
| 31692 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31693 | /* VLD3DUPq32 */ |
| 31694 | DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31695 | /* VLD3DUPq32EvenPseudo */ |
| 31696 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31697 | /* VLD3DUPq32OddPseudo */ |
| 31698 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31699 | /* VLD3DUPq32OddPseudo_UPD */ |
| 31700 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31701 | /* VLD3DUPq32_UPD */ |
| 31702 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31703 | /* VLD3DUPq8 */ |
| 31704 | DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31705 | /* VLD3DUPq8EvenPseudo */ |
| 31706 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31707 | /* VLD3DUPq8OddPseudo */ |
| 31708 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31709 | /* VLD3DUPq8OddPseudo_UPD */ |
| 31710 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31711 | /* VLD3DUPq8_UPD */ |
| 31712 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31713 | /* VLD3LNd16 */ |
| 31714 | DPR, DPR, DPR, GPR, i32imm, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31715 | /* VLD3LNd16Pseudo */ |
| 31716 | QQPR, GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 31717 | /* VLD3LNd16Pseudo_UPD */ |
| 31718 | QQPR, GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 31719 | /* VLD3LNd16_UPD */ |
| 31720 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31721 | /* VLD3LNd32 */ |
| 31722 | DPR, DPR, DPR, GPR, i32imm, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31723 | /* VLD3LNd32Pseudo */ |
| 31724 | QQPR, GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 31725 | /* VLD3LNd32Pseudo_UPD */ |
| 31726 | QQPR, GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 31727 | /* VLD3LNd32_UPD */ |
| 31728 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31729 | /* VLD3LNd8 */ |
| 31730 | DPR, DPR, DPR, GPR, i32imm, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31731 | /* VLD3LNd8Pseudo */ |
| 31732 | QQPR, GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 31733 | /* VLD3LNd8Pseudo_UPD */ |
| 31734 | QQPR, GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 31735 | /* VLD3LNd8_UPD */ |
| 31736 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31737 | /* VLD3LNq16 */ |
| 31738 | DPR, DPR, DPR, GPR, i32imm, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31739 | /* VLD3LNq16Pseudo */ |
| 31740 | QQQQPR, GPR, i32imm, QQQQPR, nohash_imm, i32imm, i32imm, |
| 31741 | /* VLD3LNq16Pseudo_UPD */ |
| 31742 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, nohash_imm, i32imm, i32imm, |
| 31743 | /* VLD3LNq16_UPD */ |
| 31744 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31745 | /* VLD3LNq32 */ |
| 31746 | DPR, DPR, DPR, GPR, i32imm, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31747 | /* VLD3LNq32Pseudo */ |
| 31748 | QQQQPR, GPR, i32imm, QQQQPR, nohash_imm, i32imm, i32imm, |
| 31749 | /* VLD3LNq32Pseudo_UPD */ |
| 31750 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, nohash_imm, i32imm, i32imm, |
| 31751 | /* VLD3LNq32_UPD */ |
| 31752 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31753 | /* VLD3d16 */ |
| 31754 | DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31755 | /* VLD3d16Pseudo */ |
| 31756 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31757 | /* VLD3d16Pseudo_UPD */ |
| 31758 | QQPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31759 | /* VLD3d16_UPD */ |
| 31760 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31761 | /* VLD3d32 */ |
| 31762 | DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31763 | /* VLD3d32Pseudo */ |
| 31764 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31765 | /* VLD3d32Pseudo_UPD */ |
| 31766 | QQPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31767 | /* VLD3d32_UPD */ |
| 31768 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31769 | /* VLD3d8 */ |
| 31770 | DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31771 | /* VLD3d8Pseudo */ |
| 31772 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31773 | /* VLD3d8Pseudo_UPD */ |
| 31774 | QQPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31775 | /* VLD3d8_UPD */ |
| 31776 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31777 | /* VLD3q16 */ |
| 31778 | DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31779 | /* VLD3q16Pseudo_UPD */ |
| 31780 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31781 | /* VLD3q16_UPD */ |
| 31782 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31783 | /* VLD3q16oddPseudo */ |
| 31784 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31785 | /* VLD3q16oddPseudo_UPD */ |
| 31786 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31787 | /* VLD3q32 */ |
| 31788 | DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31789 | /* VLD3q32Pseudo_UPD */ |
| 31790 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31791 | /* VLD3q32_UPD */ |
| 31792 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31793 | /* VLD3q32oddPseudo */ |
| 31794 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31795 | /* VLD3q32oddPseudo_UPD */ |
| 31796 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31797 | /* VLD3q8 */ |
| 31798 | DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31799 | /* VLD3q8Pseudo_UPD */ |
| 31800 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31801 | /* VLD3q8_UPD */ |
| 31802 | DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31803 | /* VLD3q8oddPseudo */ |
| 31804 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31805 | /* VLD3q8oddPseudo_UPD */ |
| 31806 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31807 | /* VLD4DUPd16 */ |
| 31808 | DPR, DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31809 | /* VLD4DUPd16Pseudo */ |
| 31810 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31811 | /* VLD4DUPd16Pseudo_UPD */ |
| 31812 | QQPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31813 | /* VLD4DUPd16_UPD */ |
| 31814 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31815 | /* VLD4DUPd32 */ |
| 31816 | DPR, DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31817 | /* VLD4DUPd32Pseudo */ |
| 31818 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31819 | /* VLD4DUPd32Pseudo_UPD */ |
| 31820 | QQPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31821 | /* VLD4DUPd32_UPD */ |
| 31822 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31823 | /* VLD4DUPd8 */ |
| 31824 | DPR, DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31825 | /* VLD4DUPd8Pseudo */ |
| 31826 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31827 | /* VLD4DUPd8Pseudo_UPD */ |
| 31828 | QQPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31829 | /* VLD4DUPd8_UPD */ |
| 31830 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31831 | /* VLD4DUPq16 */ |
| 31832 | DPR, DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31833 | /* VLD4DUPq16EvenPseudo */ |
| 31834 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31835 | /* VLD4DUPq16OddPseudo */ |
| 31836 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31837 | /* VLD4DUPq16OddPseudo_UPD */ |
| 31838 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31839 | /* VLD4DUPq16_UPD */ |
| 31840 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31841 | /* VLD4DUPq32 */ |
| 31842 | DPR, DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31843 | /* VLD4DUPq32EvenPseudo */ |
| 31844 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31845 | /* VLD4DUPq32OddPseudo */ |
| 31846 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31847 | /* VLD4DUPq32OddPseudo_UPD */ |
| 31848 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31849 | /* VLD4DUPq32_UPD */ |
| 31850 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31851 | /* VLD4DUPq8 */ |
| 31852 | DPR, DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31853 | /* VLD4DUPq8EvenPseudo */ |
| 31854 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31855 | /* VLD4DUPq8OddPseudo */ |
| 31856 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31857 | /* VLD4DUPq8OddPseudo_UPD */ |
| 31858 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31859 | /* VLD4DUPq8_UPD */ |
| 31860 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31861 | /* VLD4LNd16 */ |
| 31862 | DPR, DPR, DPR, DPR, GPR, i32imm, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31863 | /* VLD4LNd16Pseudo */ |
| 31864 | QQPR, GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 31865 | /* VLD4LNd16Pseudo_UPD */ |
| 31866 | QQPR, GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 31867 | /* VLD4LNd16_UPD */ |
| 31868 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31869 | /* VLD4LNd32 */ |
| 31870 | DPR, DPR, DPR, DPR, GPR, i32imm, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31871 | /* VLD4LNd32Pseudo */ |
| 31872 | QQPR, GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 31873 | /* VLD4LNd32Pseudo_UPD */ |
| 31874 | QQPR, GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 31875 | /* VLD4LNd32_UPD */ |
| 31876 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31877 | /* VLD4LNd8 */ |
| 31878 | DPR, DPR, DPR, DPR, GPR, i32imm, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31879 | /* VLD4LNd8Pseudo */ |
| 31880 | QQPR, GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 31881 | /* VLD4LNd8Pseudo_UPD */ |
| 31882 | QQPR, GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 31883 | /* VLD4LNd8_UPD */ |
| 31884 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31885 | /* VLD4LNq16 */ |
| 31886 | DPR, DPR, DPR, DPR, GPR, i32imm, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31887 | /* VLD4LNq16Pseudo */ |
| 31888 | QQQQPR, GPR, i32imm, QQQQPR, nohash_imm, i32imm, i32imm, |
| 31889 | /* VLD4LNq16Pseudo_UPD */ |
| 31890 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, nohash_imm, i32imm, i32imm, |
| 31891 | /* VLD4LNq16_UPD */ |
| 31892 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31893 | /* VLD4LNq32 */ |
| 31894 | DPR, DPR, DPR, DPR, GPR, i32imm, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31895 | /* VLD4LNq32Pseudo */ |
| 31896 | QQQQPR, GPR, i32imm, QQQQPR, nohash_imm, i32imm, i32imm, |
| 31897 | /* VLD4LNq32Pseudo_UPD */ |
| 31898 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, nohash_imm, i32imm, i32imm, |
| 31899 | /* VLD4LNq32_UPD */ |
| 31900 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 31901 | /* VLD4d16 */ |
| 31902 | DPR, DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31903 | /* VLD4d16Pseudo */ |
| 31904 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31905 | /* VLD4d16Pseudo_UPD */ |
| 31906 | QQPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31907 | /* VLD4d16_UPD */ |
| 31908 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31909 | /* VLD4d32 */ |
| 31910 | DPR, DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31911 | /* VLD4d32Pseudo */ |
| 31912 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31913 | /* VLD4d32Pseudo_UPD */ |
| 31914 | QQPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31915 | /* VLD4d32_UPD */ |
| 31916 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31917 | /* VLD4d8 */ |
| 31918 | DPR, DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31919 | /* VLD4d8Pseudo */ |
| 31920 | QQPR, GPR, i32imm, i32imm, i32imm, |
| 31921 | /* VLD4d8Pseudo_UPD */ |
| 31922 | QQPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31923 | /* VLD4d8_UPD */ |
| 31924 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31925 | /* VLD4q16 */ |
| 31926 | DPR, DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31927 | /* VLD4q16Pseudo_UPD */ |
| 31928 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31929 | /* VLD4q16_UPD */ |
| 31930 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31931 | /* VLD4q16oddPseudo */ |
| 31932 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31933 | /* VLD4q16oddPseudo_UPD */ |
| 31934 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31935 | /* VLD4q32 */ |
| 31936 | DPR, DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31937 | /* VLD4q32Pseudo_UPD */ |
| 31938 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31939 | /* VLD4q32_UPD */ |
| 31940 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31941 | /* VLD4q32oddPseudo */ |
| 31942 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31943 | /* VLD4q32oddPseudo_UPD */ |
| 31944 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31945 | /* VLD4q8 */ |
| 31946 | DPR, DPR, DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 31947 | /* VLD4q8Pseudo_UPD */ |
| 31948 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31949 | /* VLD4q8_UPD */ |
| 31950 | DPR, DPR, DPR, DPR, GPR, GPR, i32imm, GPR, i32imm, i32imm, |
| 31951 | /* VLD4q8oddPseudo */ |
| 31952 | QQQQPR, GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 31953 | /* VLD4q8oddPseudo_UPD */ |
| 31954 | QQQQPR, GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 31955 | /* VLDMDDB_UPD */ |
| 31956 | GPR, GPR, i32imm, i32imm, dpr_reglist, |
| 31957 | /* VLDMDIA */ |
| 31958 | GPR, i32imm, i32imm, dpr_reglist, |
| 31959 | /* VLDMDIA_UPD */ |
| 31960 | GPR, GPR, i32imm, i32imm, dpr_reglist, |
| 31961 | /* VLDMQIA */ |
| 31962 | DPair, GPR, i32imm, i32imm, |
| 31963 | /* VLDMSDB_UPD */ |
| 31964 | GPR, GPR, i32imm, i32imm, spr_reglist, |
| 31965 | /* VLDMSIA */ |
| 31966 | GPR, i32imm, i32imm, spr_reglist, |
| 31967 | /* VLDMSIA_UPD */ |
| 31968 | GPR, GPR, i32imm, i32imm, spr_reglist, |
| 31969 | /* VLDRD */ |
| 31970 | DPR, GPR, i32imm, i32imm, i32imm, |
| 31971 | /* VLDRH */ |
| 31972 | HPR, GPR, i32imm, i32imm, i32imm, |
| 31973 | /* VLDRS */ |
| 31974 | SPR, GPR, i32imm, i32imm, i32imm, |
| 31975 | /* VLDR_FPCXTNS_off */ |
| 31976 | GPRnopc, i32imm, i32imm, i32imm, |
| 31977 | /* VLDR_FPCXTNS_post */ |
| 31978 | GPRnopc, GPRnopc, t2am_imm7s4_offset, i32imm, i32imm, |
| 31979 | /* VLDR_FPCXTNS_pre */ |
| 31980 | GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 31981 | /* VLDR_FPCXTS_off */ |
| 31982 | GPRnopc, i32imm, i32imm, i32imm, |
| 31983 | /* VLDR_FPCXTS_post */ |
| 31984 | GPRnopc, GPRnopc, t2am_imm7s4_offset, i32imm, i32imm, |
| 31985 | /* VLDR_FPCXTS_pre */ |
| 31986 | GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 31987 | /* VLDR_FPSCR_NZCVQC_off */ |
| 31988 | GPRnopc, i32imm, i32imm, i32imm, |
| 31989 | /* VLDR_FPSCR_NZCVQC_post */ |
| 31990 | GPRnopc, GPRnopc, t2am_imm7s4_offset, i32imm, i32imm, |
| 31991 | /* VLDR_FPSCR_NZCVQC_pre */ |
| 31992 | GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 31993 | /* VLDR_FPSCR_off */ |
| 31994 | GPRnopc, i32imm, i32imm, i32imm, |
| 31995 | /* VLDR_FPSCR_post */ |
| 31996 | GPRnopc, GPRnopc, t2am_imm7s4_offset, i32imm, i32imm, |
| 31997 | /* VLDR_FPSCR_pre */ |
| 31998 | GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 31999 | /* VLDR_P0_off */ |
| 32000 | VCCR, GPRnopc, i32imm, i32imm, i32imm, |
| 32001 | /* VLDR_P0_post */ |
| 32002 | VCCR, GPRnopc, GPRnopc, t2am_imm7s4_offset, i32imm, i32imm, |
| 32003 | /* VLDR_P0_pre */ |
| 32004 | VCCR, GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 32005 | /* VLDR_VPR_off */ |
| 32006 | GPRnopc, i32imm, i32imm, i32imm, |
| 32007 | /* VLDR_VPR_post */ |
| 32008 | GPRnopc, GPRnopc, t2am_imm7s4_offset, i32imm, i32imm, |
| 32009 | /* VLDR_VPR_pre */ |
| 32010 | GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 32011 | /* VLLDM */ |
| 32012 | GPRnopc, i32imm, i32imm, dpr_reglist, |
| 32013 | /* VLLDM_T2 */ |
| 32014 | GPRnopc, i32imm, i32imm, dpr_reglist, |
| 32015 | /* VLSTM */ |
| 32016 | GPRnopc, i32imm, i32imm, dpr_reglist, |
| 32017 | /* VLSTM_T2 */ |
| 32018 | GPRnopc, i32imm, i32imm, dpr_reglist, |
| 32019 | /* VMAXfd */ |
| 32020 | DPR, DPR, DPR, i32imm, i32imm, |
| 32021 | /* VMAXfq */ |
| 32022 | QPR, QPR, QPR, i32imm, i32imm, |
| 32023 | /* VMAXhd */ |
| 32024 | DPR, DPR, DPR, i32imm, i32imm, |
| 32025 | /* VMAXhq */ |
| 32026 | QPR, QPR, QPR, i32imm, i32imm, |
| 32027 | /* VMAXsv16i8 */ |
| 32028 | QPR, QPR, QPR, i32imm, i32imm, |
| 32029 | /* VMAXsv2i32 */ |
| 32030 | DPR, DPR, DPR, i32imm, i32imm, |
| 32031 | /* VMAXsv4i16 */ |
| 32032 | DPR, DPR, DPR, i32imm, i32imm, |
| 32033 | /* VMAXsv4i32 */ |
| 32034 | QPR, QPR, QPR, i32imm, i32imm, |
| 32035 | /* VMAXsv8i16 */ |
| 32036 | QPR, QPR, QPR, i32imm, i32imm, |
| 32037 | /* VMAXsv8i8 */ |
| 32038 | DPR, DPR, DPR, i32imm, i32imm, |
| 32039 | /* VMAXuv16i8 */ |
| 32040 | QPR, QPR, QPR, i32imm, i32imm, |
| 32041 | /* VMAXuv2i32 */ |
| 32042 | DPR, DPR, DPR, i32imm, i32imm, |
| 32043 | /* VMAXuv4i16 */ |
| 32044 | DPR, DPR, DPR, i32imm, i32imm, |
| 32045 | /* VMAXuv4i32 */ |
| 32046 | QPR, QPR, QPR, i32imm, i32imm, |
| 32047 | /* VMAXuv8i16 */ |
| 32048 | QPR, QPR, QPR, i32imm, i32imm, |
| 32049 | /* VMAXuv8i8 */ |
| 32050 | DPR, DPR, DPR, i32imm, i32imm, |
| 32051 | /* VMINfd */ |
| 32052 | DPR, DPR, DPR, i32imm, i32imm, |
| 32053 | /* VMINfq */ |
| 32054 | QPR, QPR, QPR, i32imm, i32imm, |
| 32055 | /* VMINhd */ |
| 32056 | DPR, DPR, DPR, i32imm, i32imm, |
| 32057 | /* VMINhq */ |
| 32058 | QPR, QPR, QPR, i32imm, i32imm, |
| 32059 | /* VMINsv16i8 */ |
| 32060 | QPR, QPR, QPR, i32imm, i32imm, |
| 32061 | /* VMINsv2i32 */ |
| 32062 | DPR, DPR, DPR, i32imm, i32imm, |
| 32063 | /* VMINsv4i16 */ |
| 32064 | DPR, DPR, DPR, i32imm, i32imm, |
| 32065 | /* VMINsv4i32 */ |
| 32066 | QPR, QPR, QPR, i32imm, i32imm, |
| 32067 | /* VMINsv8i16 */ |
| 32068 | QPR, QPR, QPR, i32imm, i32imm, |
| 32069 | /* VMINsv8i8 */ |
| 32070 | DPR, DPR, DPR, i32imm, i32imm, |
| 32071 | /* VMINuv16i8 */ |
| 32072 | QPR, QPR, QPR, i32imm, i32imm, |
| 32073 | /* VMINuv2i32 */ |
| 32074 | DPR, DPR, DPR, i32imm, i32imm, |
| 32075 | /* VMINuv4i16 */ |
| 32076 | DPR, DPR, DPR, i32imm, i32imm, |
| 32077 | /* VMINuv4i32 */ |
| 32078 | QPR, QPR, QPR, i32imm, i32imm, |
| 32079 | /* VMINuv8i16 */ |
| 32080 | QPR, QPR, QPR, i32imm, i32imm, |
| 32081 | /* VMINuv8i8 */ |
| 32082 | DPR, DPR, DPR, i32imm, i32imm, |
| 32083 | /* VMLAD */ |
| 32084 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32085 | /* VMLAH */ |
| 32086 | HPR, HPR, HPR, HPR, i32imm, i32imm, |
| 32087 | /* VMLALslsv2i32 */ |
| 32088 | QPR, QPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32089 | /* VMLALslsv4i16 */ |
| 32090 | QPR, QPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32091 | /* VMLALsluv2i32 */ |
| 32092 | QPR, QPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32093 | /* VMLALsluv4i16 */ |
| 32094 | QPR, QPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32095 | /* VMLALsv2i64 */ |
| 32096 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32097 | /* VMLALsv4i32 */ |
| 32098 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32099 | /* VMLALsv8i16 */ |
| 32100 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32101 | /* VMLALuv2i64 */ |
| 32102 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32103 | /* VMLALuv4i32 */ |
| 32104 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32105 | /* VMLALuv8i16 */ |
| 32106 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32107 | /* VMLAS */ |
| 32108 | SPR, SPR, SPR, SPR, i32imm, i32imm, |
| 32109 | /* VMLAfd */ |
| 32110 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32111 | /* VMLAfq */ |
| 32112 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32113 | /* VMLAhd */ |
| 32114 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32115 | /* VMLAhq */ |
| 32116 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32117 | /* VMLAslfd */ |
| 32118 | DPR, DPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32119 | /* VMLAslfq */ |
| 32120 | QPR, QPR, QPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32121 | /* VMLAslhd */ |
| 32122 | DPR, DPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32123 | /* VMLAslhq */ |
| 32124 | QPR, QPR, QPR, DPR_8, i32imm, i32imm, i32imm, |
| 32125 | /* VMLAslv2i32 */ |
| 32126 | DPR, DPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32127 | /* VMLAslv4i16 */ |
| 32128 | DPR, DPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32129 | /* VMLAslv4i32 */ |
| 32130 | QPR, QPR, QPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32131 | /* VMLAslv8i16 */ |
| 32132 | QPR, QPR, QPR, DPR_8, i32imm, i32imm, i32imm, |
| 32133 | /* VMLAv16i8 */ |
| 32134 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32135 | /* VMLAv2i32 */ |
| 32136 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32137 | /* VMLAv4i16 */ |
| 32138 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32139 | /* VMLAv4i32 */ |
| 32140 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32141 | /* VMLAv8i16 */ |
| 32142 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32143 | /* VMLAv8i8 */ |
| 32144 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32145 | /* VMLSD */ |
| 32146 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32147 | /* VMLSH */ |
| 32148 | HPR, HPR, HPR, HPR, i32imm, i32imm, |
| 32149 | /* VMLSLslsv2i32 */ |
| 32150 | QPR, QPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32151 | /* VMLSLslsv4i16 */ |
| 32152 | QPR, QPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32153 | /* VMLSLsluv2i32 */ |
| 32154 | QPR, QPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32155 | /* VMLSLsluv4i16 */ |
| 32156 | QPR, QPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32157 | /* VMLSLsv2i64 */ |
| 32158 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32159 | /* VMLSLsv4i32 */ |
| 32160 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32161 | /* VMLSLsv8i16 */ |
| 32162 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32163 | /* VMLSLuv2i64 */ |
| 32164 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32165 | /* VMLSLuv4i32 */ |
| 32166 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32167 | /* VMLSLuv8i16 */ |
| 32168 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32169 | /* VMLSS */ |
| 32170 | SPR, SPR, SPR, SPR, i32imm, i32imm, |
| 32171 | /* VMLSfd */ |
| 32172 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32173 | /* VMLSfq */ |
| 32174 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32175 | /* VMLShd */ |
| 32176 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32177 | /* VMLShq */ |
| 32178 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32179 | /* VMLSslfd */ |
| 32180 | DPR, DPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32181 | /* VMLSslfq */ |
| 32182 | QPR, QPR, QPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32183 | /* VMLSslhd */ |
| 32184 | DPR, DPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32185 | /* VMLSslhq */ |
| 32186 | QPR, QPR, QPR, DPR_8, i32imm, i32imm, i32imm, |
| 32187 | /* VMLSslv2i32 */ |
| 32188 | DPR, DPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32189 | /* VMLSslv4i16 */ |
| 32190 | DPR, DPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32191 | /* VMLSslv4i32 */ |
| 32192 | QPR, QPR, QPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32193 | /* VMLSslv8i16 */ |
| 32194 | QPR, QPR, QPR, DPR_8, i32imm, i32imm, i32imm, |
| 32195 | /* VMLSv16i8 */ |
| 32196 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32197 | /* VMLSv2i32 */ |
| 32198 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32199 | /* VMLSv4i16 */ |
| 32200 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32201 | /* VMLSv4i32 */ |
| 32202 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32203 | /* VMLSv8i16 */ |
| 32204 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32205 | /* VMLSv8i8 */ |
| 32206 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32207 | /* VMMLA */ |
| 32208 | QPR, QPR, QPR, QPR, |
| 32209 | /* VMOVD */ |
| 32210 | DPR, DPR, i32imm, i32imm, |
| 32211 | /* VMOVDRR */ |
| 32212 | DPR, GPR, GPR, i32imm, i32imm, |
| 32213 | /* VMOVH */ |
| 32214 | SPR, SPR, |
| 32215 | /* VMOVHR */ |
| 32216 | HPR, rGPR, i32imm, i32imm, |
| 32217 | /* VMOVLsv2i64 */ |
| 32218 | QPR, DPR, i32imm, i32imm, |
| 32219 | /* VMOVLsv4i32 */ |
| 32220 | QPR, DPR, i32imm, i32imm, |
| 32221 | /* VMOVLsv8i16 */ |
| 32222 | QPR, DPR, i32imm, i32imm, |
| 32223 | /* VMOVLuv2i64 */ |
| 32224 | QPR, DPR, i32imm, i32imm, |
| 32225 | /* VMOVLuv4i32 */ |
| 32226 | QPR, DPR, i32imm, i32imm, |
| 32227 | /* VMOVLuv8i16 */ |
| 32228 | QPR, DPR, i32imm, i32imm, |
| 32229 | /* VMOVNv2i32 */ |
| 32230 | DPR, QPR, i32imm, i32imm, |
| 32231 | /* VMOVNv4i16 */ |
| 32232 | DPR, QPR, i32imm, i32imm, |
| 32233 | /* VMOVNv8i8 */ |
| 32234 | DPR, QPR, i32imm, i32imm, |
| 32235 | /* VMOVRH */ |
| 32236 | rGPR, HPR, i32imm, i32imm, |
| 32237 | /* VMOVRRD */ |
| 32238 | GPR, GPR, DPR, i32imm, i32imm, |
| 32239 | /* VMOVRRS */ |
| 32240 | GPR, GPR, SPR, SPR, i32imm, i32imm, |
| 32241 | /* VMOVRS */ |
| 32242 | GPR, SPR, i32imm, i32imm, |
| 32243 | /* VMOVS */ |
| 32244 | SPR, SPR, i32imm, i32imm, |
| 32245 | /* VMOVSR */ |
| 32246 | SPR, GPR, i32imm, i32imm, |
| 32247 | /* VMOVSRR */ |
| 32248 | SPR, SPR, GPR, GPR, i32imm, i32imm, |
| 32249 | /* VMOVv16i8 */ |
| 32250 | QPR, nImmSplatI8, i32imm, i32imm, |
| 32251 | /* VMOVv1i64 */ |
| 32252 | DPR, nImmSplatI64, i32imm, i32imm, |
| 32253 | /* VMOVv2f32 */ |
| 32254 | DPR, nImmVMOVF32, i32imm, i32imm, |
| 32255 | /* VMOVv2i32 */ |
| 32256 | DPR, nImmVMOVI32, i32imm, i32imm, |
| 32257 | /* VMOVv2i64 */ |
| 32258 | QPR, nImmSplatI64, i32imm, i32imm, |
| 32259 | /* VMOVv4f32 */ |
| 32260 | QPR, nImmVMOVF32, i32imm, i32imm, |
| 32261 | /* VMOVv4i16 */ |
| 32262 | DPR, nImmSplatI16, i32imm, i32imm, |
| 32263 | /* VMOVv4i32 */ |
| 32264 | QPR, nImmVMOVI32, i32imm, i32imm, |
| 32265 | /* VMOVv8i16 */ |
| 32266 | QPR, nImmSplatI16, i32imm, i32imm, |
| 32267 | /* VMOVv8i8 */ |
| 32268 | DPR, nImmSplatI8, i32imm, i32imm, |
| 32269 | /* VMRS */ |
| 32270 | GPRnopc, i32imm, i32imm, |
| 32271 | /* VMRS_FPCXTNS */ |
| 32272 | GPR, i32imm, i32imm, |
| 32273 | /* VMRS_FPCXTS */ |
| 32274 | GPR, i32imm, i32imm, |
| 32275 | /* VMRS_FPEXC */ |
| 32276 | GPRnopc, i32imm, i32imm, |
| 32277 | /* VMRS_FPINST */ |
| 32278 | GPRnopc, i32imm, i32imm, |
| 32279 | /* VMRS_FPINST2 */ |
| 32280 | GPRnopc, i32imm, i32imm, |
| 32281 | /* VMRS_FPSCR_NZCVQC */ |
| 32282 | GPR, cl_FPSCR_NZCV, i32imm, i32imm, |
| 32283 | /* VMRS_FPSID */ |
| 32284 | GPRnopc, i32imm, i32imm, |
| 32285 | /* VMRS_MVFR0 */ |
| 32286 | GPRnopc, i32imm, i32imm, |
| 32287 | /* VMRS_MVFR1 */ |
| 32288 | GPRnopc, i32imm, i32imm, |
| 32289 | /* VMRS_MVFR2 */ |
| 32290 | GPRnopc, i32imm, i32imm, |
| 32291 | /* VMRS_P0 */ |
| 32292 | GPR, VCCR, i32imm, i32imm, |
| 32293 | /* VMRS_VPR */ |
| 32294 | GPR, i32imm, i32imm, |
| 32295 | /* VMSR */ |
| 32296 | GPRnopc, i32imm, i32imm, |
| 32297 | /* VMSR_FPCXTNS */ |
| 32298 | GPR, i32imm, i32imm, |
| 32299 | /* VMSR_FPCXTS */ |
| 32300 | GPR, i32imm, i32imm, |
| 32301 | /* VMSR_FPEXC */ |
| 32302 | GPRnopc, i32imm, i32imm, |
| 32303 | /* VMSR_FPINST */ |
| 32304 | GPRnopc, i32imm, i32imm, |
| 32305 | /* VMSR_FPINST2 */ |
| 32306 | GPRnopc, i32imm, i32imm, |
| 32307 | /* VMSR_FPSCR_NZCVQC */ |
| 32308 | cl_FPSCR_NZCV, GPR, i32imm, i32imm, |
| 32309 | /* VMSR_FPSID */ |
| 32310 | GPRnopc, i32imm, i32imm, |
| 32311 | /* VMSR_P0 */ |
| 32312 | VCCR, GPR, i32imm, i32imm, |
| 32313 | /* VMSR_VPR */ |
| 32314 | GPR, i32imm, i32imm, |
| 32315 | /* VMULD */ |
| 32316 | DPR, DPR, DPR, i32imm, i32imm, |
| 32317 | /* VMULH */ |
| 32318 | HPR, HPR, HPR, i32imm, i32imm, |
| 32319 | /* VMULLp64 */ |
| 32320 | QPR, DPR, DPR, |
| 32321 | /* VMULLp8 */ |
| 32322 | QPR, DPR, DPR, i32imm, i32imm, |
| 32323 | /* VMULLslsv2i32 */ |
| 32324 | QPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32325 | /* VMULLslsv4i16 */ |
| 32326 | QPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32327 | /* VMULLsluv2i32 */ |
| 32328 | QPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32329 | /* VMULLsluv4i16 */ |
| 32330 | QPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32331 | /* VMULLsv2i64 */ |
| 32332 | QPR, DPR, DPR, i32imm, i32imm, |
| 32333 | /* VMULLsv4i32 */ |
| 32334 | QPR, DPR, DPR, i32imm, i32imm, |
| 32335 | /* VMULLsv8i16 */ |
| 32336 | QPR, DPR, DPR, i32imm, i32imm, |
| 32337 | /* VMULLuv2i64 */ |
| 32338 | QPR, DPR, DPR, i32imm, i32imm, |
| 32339 | /* VMULLuv4i32 */ |
| 32340 | QPR, DPR, DPR, i32imm, i32imm, |
| 32341 | /* VMULLuv8i16 */ |
| 32342 | QPR, DPR, DPR, i32imm, i32imm, |
| 32343 | /* VMULS */ |
| 32344 | SPR, SPR, SPR, i32imm, i32imm, |
| 32345 | /* VMULfd */ |
| 32346 | DPR, DPR, DPR, i32imm, i32imm, |
| 32347 | /* VMULfq */ |
| 32348 | QPR, QPR, QPR, i32imm, i32imm, |
| 32349 | /* VMULhd */ |
| 32350 | DPR, DPR, DPR, i32imm, i32imm, |
| 32351 | /* VMULhq */ |
| 32352 | QPR, QPR, QPR, i32imm, i32imm, |
| 32353 | /* VMULpd */ |
| 32354 | DPR, DPR, DPR, i32imm, i32imm, |
| 32355 | /* VMULpq */ |
| 32356 | QPR, QPR, QPR, i32imm, i32imm, |
| 32357 | /* VMULslfd */ |
| 32358 | DPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32359 | /* VMULslfq */ |
| 32360 | QPR, QPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32361 | /* VMULslhd */ |
| 32362 | DPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32363 | /* VMULslhq */ |
| 32364 | QPR, QPR, DPR_8, i32imm, i32imm, i32imm, |
| 32365 | /* VMULslv2i32 */ |
| 32366 | DPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32367 | /* VMULslv4i16 */ |
| 32368 | DPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32369 | /* VMULslv4i32 */ |
| 32370 | QPR, QPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32371 | /* VMULslv8i16 */ |
| 32372 | QPR, QPR, DPR_8, i32imm, i32imm, i32imm, |
| 32373 | /* VMULv16i8 */ |
| 32374 | QPR, QPR, QPR, i32imm, i32imm, |
| 32375 | /* VMULv2i32 */ |
| 32376 | DPR, DPR, DPR, i32imm, i32imm, |
| 32377 | /* VMULv4i16 */ |
| 32378 | DPR, DPR, DPR, i32imm, i32imm, |
| 32379 | /* VMULv4i32 */ |
| 32380 | QPR, QPR, QPR, i32imm, i32imm, |
| 32381 | /* VMULv8i16 */ |
| 32382 | QPR, QPR, QPR, i32imm, i32imm, |
| 32383 | /* VMULv8i8 */ |
| 32384 | DPR, DPR, DPR, i32imm, i32imm, |
| 32385 | /* VMVNd */ |
| 32386 | DPR, DPR, i32imm, i32imm, |
| 32387 | /* VMVNq */ |
| 32388 | QPR, QPR, i32imm, i32imm, |
| 32389 | /* VMVNv2i32 */ |
| 32390 | DPR, nImmVMOVI32, i32imm, i32imm, |
| 32391 | /* VMVNv4i16 */ |
| 32392 | DPR, nImmSplatI16, i32imm, i32imm, |
| 32393 | /* VMVNv4i32 */ |
| 32394 | QPR, nImmVMOVI32, i32imm, i32imm, |
| 32395 | /* VMVNv8i16 */ |
| 32396 | QPR, nImmSplatI16, i32imm, i32imm, |
| 32397 | /* VNEGD */ |
| 32398 | DPR, DPR, i32imm, i32imm, |
| 32399 | /* VNEGH */ |
| 32400 | HPR, HPR, i32imm, i32imm, |
| 32401 | /* VNEGS */ |
| 32402 | SPR, SPR, i32imm, i32imm, |
| 32403 | /* VNEGf32q */ |
| 32404 | QPR, QPR, i32imm, i32imm, |
| 32405 | /* VNEGfd */ |
| 32406 | DPR, DPR, i32imm, i32imm, |
| 32407 | /* VNEGhd */ |
| 32408 | DPR, DPR, i32imm, i32imm, |
| 32409 | /* VNEGhq */ |
| 32410 | QPR, QPR, i32imm, i32imm, |
| 32411 | /* VNEGs16d */ |
| 32412 | DPR, DPR, i32imm, i32imm, |
| 32413 | /* VNEGs16q */ |
| 32414 | QPR, QPR, i32imm, i32imm, |
| 32415 | /* VNEGs32d */ |
| 32416 | DPR, DPR, i32imm, i32imm, |
| 32417 | /* VNEGs32q */ |
| 32418 | QPR, QPR, i32imm, i32imm, |
| 32419 | /* VNEGs8d */ |
| 32420 | DPR, DPR, i32imm, i32imm, |
| 32421 | /* VNEGs8q */ |
| 32422 | QPR, QPR, i32imm, i32imm, |
| 32423 | /* VNMLAD */ |
| 32424 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32425 | /* VNMLAH */ |
| 32426 | HPR, HPR, HPR, HPR, i32imm, i32imm, |
| 32427 | /* VNMLAS */ |
| 32428 | SPR, SPR, SPR, SPR, i32imm, i32imm, |
| 32429 | /* VNMLSD */ |
| 32430 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32431 | /* VNMLSH */ |
| 32432 | HPR, HPR, HPR, HPR, i32imm, i32imm, |
| 32433 | /* VNMLSS */ |
| 32434 | SPR, SPR, SPR, SPR, i32imm, i32imm, |
| 32435 | /* VNMULD */ |
| 32436 | DPR, DPR, DPR, i32imm, i32imm, |
| 32437 | /* VNMULH */ |
| 32438 | HPR, HPR, HPR, i32imm, i32imm, |
| 32439 | /* VNMULS */ |
| 32440 | SPR, SPR, SPR, i32imm, i32imm, |
| 32441 | /* VORNd */ |
| 32442 | DPR, DPR, DPR, i32imm, i32imm, |
| 32443 | /* VORNq */ |
| 32444 | QPR, QPR, QPR, i32imm, i32imm, |
| 32445 | /* VORRd */ |
| 32446 | DPR, DPR, DPR, i32imm, i32imm, |
| 32447 | /* VORRiv2i32 */ |
| 32448 | DPR, nImmSplatI32, DPR, i32imm, i32imm, |
| 32449 | /* VORRiv4i16 */ |
| 32450 | DPR, nImmSplatI16, DPR, i32imm, i32imm, |
| 32451 | /* VORRiv4i32 */ |
| 32452 | QPR, nImmSplatI32, QPR, i32imm, i32imm, |
| 32453 | /* VORRiv8i16 */ |
| 32454 | QPR, nImmSplatI16, QPR, i32imm, i32imm, |
| 32455 | /* VORRq */ |
| 32456 | QPR, QPR, QPR, i32imm, i32imm, |
| 32457 | /* VPADALsv16i8 */ |
| 32458 | QPR, QPR, QPR, i32imm, i32imm, |
| 32459 | /* VPADALsv2i32 */ |
| 32460 | DPR, DPR, DPR, i32imm, i32imm, |
| 32461 | /* VPADALsv4i16 */ |
| 32462 | DPR, DPR, DPR, i32imm, i32imm, |
| 32463 | /* VPADALsv4i32 */ |
| 32464 | QPR, QPR, QPR, i32imm, i32imm, |
| 32465 | /* VPADALsv8i16 */ |
| 32466 | QPR, QPR, QPR, i32imm, i32imm, |
| 32467 | /* VPADALsv8i8 */ |
| 32468 | DPR, DPR, DPR, i32imm, i32imm, |
| 32469 | /* VPADALuv16i8 */ |
| 32470 | QPR, QPR, QPR, i32imm, i32imm, |
| 32471 | /* VPADALuv2i32 */ |
| 32472 | DPR, DPR, DPR, i32imm, i32imm, |
| 32473 | /* VPADALuv4i16 */ |
| 32474 | DPR, DPR, DPR, i32imm, i32imm, |
| 32475 | /* VPADALuv4i32 */ |
| 32476 | QPR, QPR, QPR, i32imm, i32imm, |
| 32477 | /* VPADALuv8i16 */ |
| 32478 | QPR, QPR, QPR, i32imm, i32imm, |
| 32479 | /* VPADALuv8i8 */ |
| 32480 | DPR, DPR, DPR, i32imm, i32imm, |
| 32481 | /* VPADDLsv16i8 */ |
| 32482 | QPR, QPR, i32imm, i32imm, |
| 32483 | /* VPADDLsv2i32 */ |
| 32484 | DPR, DPR, i32imm, i32imm, |
| 32485 | /* VPADDLsv4i16 */ |
| 32486 | DPR, DPR, i32imm, i32imm, |
| 32487 | /* VPADDLsv4i32 */ |
| 32488 | QPR, QPR, i32imm, i32imm, |
| 32489 | /* VPADDLsv8i16 */ |
| 32490 | QPR, QPR, i32imm, i32imm, |
| 32491 | /* VPADDLsv8i8 */ |
| 32492 | DPR, DPR, i32imm, i32imm, |
| 32493 | /* VPADDLuv16i8 */ |
| 32494 | QPR, QPR, i32imm, i32imm, |
| 32495 | /* VPADDLuv2i32 */ |
| 32496 | DPR, DPR, i32imm, i32imm, |
| 32497 | /* VPADDLuv4i16 */ |
| 32498 | DPR, DPR, i32imm, i32imm, |
| 32499 | /* VPADDLuv4i32 */ |
| 32500 | QPR, QPR, i32imm, i32imm, |
| 32501 | /* VPADDLuv8i16 */ |
| 32502 | QPR, QPR, i32imm, i32imm, |
| 32503 | /* VPADDLuv8i8 */ |
| 32504 | DPR, DPR, i32imm, i32imm, |
| 32505 | /* VPADDf */ |
| 32506 | DPR, DPR, DPR, i32imm, i32imm, |
| 32507 | /* VPADDh */ |
| 32508 | DPR, DPR, DPR, i32imm, i32imm, |
| 32509 | /* VPADDi16 */ |
| 32510 | DPR, DPR, DPR, i32imm, i32imm, |
| 32511 | /* VPADDi32 */ |
| 32512 | DPR, DPR, DPR, i32imm, i32imm, |
| 32513 | /* VPADDi8 */ |
| 32514 | DPR, DPR, DPR, i32imm, i32imm, |
| 32515 | /* VPMAXf */ |
| 32516 | DPR, DPR, DPR, i32imm, i32imm, |
| 32517 | /* VPMAXh */ |
| 32518 | DPR, DPR, DPR, i32imm, i32imm, |
| 32519 | /* VPMAXs16 */ |
| 32520 | DPR, DPR, DPR, i32imm, i32imm, |
| 32521 | /* VPMAXs32 */ |
| 32522 | DPR, DPR, DPR, i32imm, i32imm, |
| 32523 | /* VPMAXs8 */ |
| 32524 | DPR, DPR, DPR, i32imm, i32imm, |
| 32525 | /* VPMAXu16 */ |
| 32526 | DPR, DPR, DPR, i32imm, i32imm, |
| 32527 | /* VPMAXu32 */ |
| 32528 | DPR, DPR, DPR, i32imm, i32imm, |
| 32529 | /* VPMAXu8 */ |
| 32530 | DPR, DPR, DPR, i32imm, i32imm, |
| 32531 | /* VPMINf */ |
| 32532 | DPR, DPR, DPR, i32imm, i32imm, |
| 32533 | /* VPMINh */ |
| 32534 | DPR, DPR, DPR, i32imm, i32imm, |
| 32535 | /* VPMINs16 */ |
| 32536 | DPR, DPR, DPR, i32imm, i32imm, |
| 32537 | /* VPMINs32 */ |
| 32538 | DPR, DPR, DPR, i32imm, i32imm, |
| 32539 | /* VPMINs8 */ |
| 32540 | DPR, DPR, DPR, i32imm, i32imm, |
| 32541 | /* VPMINu16 */ |
| 32542 | DPR, DPR, DPR, i32imm, i32imm, |
| 32543 | /* VPMINu32 */ |
| 32544 | DPR, DPR, DPR, i32imm, i32imm, |
| 32545 | /* VPMINu8 */ |
| 32546 | DPR, DPR, DPR, i32imm, i32imm, |
| 32547 | /* VQABSv16i8 */ |
| 32548 | QPR, QPR, i32imm, i32imm, |
| 32549 | /* VQABSv2i32 */ |
| 32550 | DPR, DPR, i32imm, i32imm, |
| 32551 | /* VQABSv4i16 */ |
| 32552 | DPR, DPR, i32imm, i32imm, |
| 32553 | /* VQABSv4i32 */ |
| 32554 | QPR, QPR, i32imm, i32imm, |
| 32555 | /* VQABSv8i16 */ |
| 32556 | QPR, QPR, i32imm, i32imm, |
| 32557 | /* VQABSv8i8 */ |
| 32558 | DPR, DPR, i32imm, i32imm, |
| 32559 | /* VQADDsv16i8 */ |
| 32560 | QPR, QPR, QPR, i32imm, i32imm, |
| 32561 | /* VQADDsv1i64 */ |
| 32562 | DPR, DPR, DPR, i32imm, i32imm, |
| 32563 | /* VQADDsv2i32 */ |
| 32564 | DPR, DPR, DPR, i32imm, i32imm, |
| 32565 | /* VQADDsv2i64 */ |
| 32566 | QPR, QPR, QPR, i32imm, i32imm, |
| 32567 | /* VQADDsv4i16 */ |
| 32568 | DPR, DPR, DPR, i32imm, i32imm, |
| 32569 | /* VQADDsv4i32 */ |
| 32570 | QPR, QPR, QPR, i32imm, i32imm, |
| 32571 | /* VQADDsv8i16 */ |
| 32572 | QPR, QPR, QPR, i32imm, i32imm, |
| 32573 | /* VQADDsv8i8 */ |
| 32574 | DPR, DPR, DPR, i32imm, i32imm, |
| 32575 | /* VQADDuv16i8 */ |
| 32576 | QPR, QPR, QPR, i32imm, i32imm, |
| 32577 | /* VQADDuv1i64 */ |
| 32578 | DPR, DPR, DPR, i32imm, i32imm, |
| 32579 | /* VQADDuv2i32 */ |
| 32580 | DPR, DPR, DPR, i32imm, i32imm, |
| 32581 | /* VQADDuv2i64 */ |
| 32582 | QPR, QPR, QPR, i32imm, i32imm, |
| 32583 | /* VQADDuv4i16 */ |
| 32584 | DPR, DPR, DPR, i32imm, i32imm, |
| 32585 | /* VQADDuv4i32 */ |
| 32586 | QPR, QPR, QPR, i32imm, i32imm, |
| 32587 | /* VQADDuv8i16 */ |
| 32588 | QPR, QPR, QPR, i32imm, i32imm, |
| 32589 | /* VQADDuv8i8 */ |
| 32590 | DPR, DPR, DPR, i32imm, i32imm, |
| 32591 | /* VQDMLALslv2i32 */ |
| 32592 | QPR, QPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32593 | /* VQDMLALslv4i16 */ |
| 32594 | QPR, QPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32595 | /* VQDMLALv2i64 */ |
| 32596 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32597 | /* VQDMLALv4i32 */ |
| 32598 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32599 | /* VQDMLSLslv2i32 */ |
| 32600 | QPR, QPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32601 | /* VQDMLSLslv4i16 */ |
| 32602 | QPR, QPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32603 | /* VQDMLSLv2i64 */ |
| 32604 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32605 | /* VQDMLSLv4i32 */ |
| 32606 | QPR, QPR, DPR, DPR, i32imm, i32imm, |
| 32607 | /* VQDMULHslv2i32 */ |
| 32608 | DPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32609 | /* VQDMULHslv4i16 */ |
| 32610 | DPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32611 | /* VQDMULHslv4i32 */ |
| 32612 | QPR, QPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32613 | /* VQDMULHslv8i16 */ |
| 32614 | QPR, QPR, DPR_8, i32imm, i32imm, i32imm, |
| 32615 | /* VQDMULHv2i32 */ |
| 32616 | DPR, DPR, DPR, i32imm, i32imm, |
| 32617 | /* VQDMULHv4i16 */ |
| 32618 | DPR, DPR, DPR, i32imm, i32imm, |
| 32619 | /* VQDMULHv4i32 */ |
| 32620 | QPR, QPR, QPR, i32imm, i32imm, |
| 32621 | /* VQDMULHv8i16 */ |
| 32622 | QPR, QPR, QPR, i32imm, i32imm, |
| 32623 | /* VQDMULLslv2i32 */ |
| 32624 | QPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32625 | /* VQDMULLslv4i16 */ |
| 32626 | QPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32627 | /* VQDMULLv2i64 */ |
| 32628 | QPR, DPR, DPR, i32imm, i32imm, |
| 32629 | /* VQDMULLv4i32 */ |
| 32630 | QPR, DPR, DPR, i32imm, i32imm, |
| 32631 | /* VQMOVNsuv2i32 */ |
| 32632 | DPR, QPR, i32imm, i32imm, |
| 32633 | /* VQMOVNsuv4i16 */ |
| 32634 | DPR, QPR, i32imm, i32imm, |
| 32635 | /* VQMOVNsuv8i8 */ |
| 32636 | DPR, QPR, i32imm, i32imm, |
| 32637 | /* VQMOVNsv2i32 */ |
| 32638 | DPR, QPR, i32imm, i32imm, |
| 32639 | /* VQMOVNsv4i16 */ |
| 32640 | DPR, QPR, i32imm, i32imm, |
| 32641 | /* VQMOVNsv8i8 */ |
| 32642 | DPR, QPR, i32imm, i32imm, |
| 32643 | /* VQMOVNuv2i32 */ |
| 32644 | DPR, QPR, i32imm, i32imm, |
| 32645 | /* VQMOVNuv4i16 */ |
| 32646 | DPR, QPR, i32imm, i32imm, |
| 32647 | /* VQMOVNuv8i8 */ |
| 32648 | DPR, QPR, i32imm, i32imm, |
| 32649 | /* VQNEGv16i8 */ |
| 32650 | QPR, QPR, i32imm, i32imm, |
| 32651 | /* VQNEGv2i32 */ |
| 32652 | DPR, DPR, i32imm, i32imm, |
| 32653 | /* VQNEGv4i16 */ |
| 32654 | DPR, DPR, i32imm, i32imm, |
| 32655 | /* VQNEGv4i32 */ |
| 32656 | QPR, QPR, i32imm, i32imm, |
| 32657 | /* VQNEGv8i16 */ |
| 32658 | QPR, QPR, i32imm, i32imm, |
| 32659 | /* VQNEGv8i8 */ |
| 32660 | DPR, DPR, i32imm, i32imm, |
| 32661 | /* VQRDMLAHslv2i32 */ |
| 32662 | DPR, DPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32663 | /* VQRDMLAHslv4i16 */ |
| 32664 | DPR, DPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32665 | /* VQRDMLAHslv4i32 */ |
| 32666 | QPR, QPR, QPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32667 | /* VQRDMLAHslv8i16 */ |
| 32668 | QPR, QPR, QPR, DPR_8, i32imm, i32imm, i32imm, |
| 32669 | /* VQRDMLAHv2i32 */ |
| 32670 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32671 | /* VQRDMLAHv4i16 */ |
| 32672 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32673 | /* VQRDMLAHv4i32 */ |
| 32674 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32675 | /* VQRDMLAHv8i16 */ |
| 32676 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32677 | /* VQRDMLSHslv2i32 */ |
| 32678 | DPR, DPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32679 | /* VQRDMLSHslv4i16 */ |
| 32680 | DPR, DPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32681 | /* VQRDMLSHslv4i32 */ |
| 32682 | QPR, QPR, QPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32683 | /* VQRDMLSHslv8i16 */ |
| 32684 | QPR, QPR, QPR, DPR_8, i32imm, i32imm, i32imm, |
| 32685 | /* VQRDMLSHv2i32 */ |
| 32686 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32687 | /* VQRDMLSHv4i16 */ |
| 32688 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 32689 | /* VQRDMLSHv4i32 */ |
| 32690 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32691 | /* VQRDMLSHv8i16 */ |
| 32692 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 32693 | /* VQRDMULHslv2i32 */ |
| 32694 | DPR, DPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32695 | /* VQRDMULHslv4i16 */ |
| 32696 | DPR, DPR, DPR_8, i32imm, i32imm, i32imm, |
| 32697 | /* VQRDMULHslv4i32 */ |
| 32698 | QPR, QPR, DPR_VFP2, i32imm, i32imm, i32imm, |
| 32699 | /* VQRDMULHslv8i16 */ |
| 32700 | QPR, QPR, DPR_8, i32imm, i32imm, i32imm, |
| 32701 | /* VQRDMULHv2i32 */ |
| 32702 | DPR, DPR, DPR, i32imm, i32imm, |
| 32703 | /* VQRDMULHv4i16 */ |
| 32704 | DPR, DPR, DPR, i32imm, i32imm, |
| 32705 | /* VQRDMULHv4i32 */ |
| 32706 | QPR, QPR, QPR, i32imm, i32imm, |
| 32707 | /* VQRDMULHv8i16 */ |
| 32708 | QPR, QPR, QPR, i32imm, i32imm, |
| 32709 | /* VQRSHLsv16i8 */ |
| 32710 | QPR, QPR, QPR, i32imm, i32imm, |
| 32711 | /* VQRSHLsv1i64 */ |
| 32712 | DPR, DPR, DPR, i32imm, i32imm, |
| 32713 | /* VQRSHLsv2i32 */ |
| 32714 | DPR, DPR, DPR, i32imm, i32imm, |
| 32715 | /* VQRSHLsv2i64 */ |
| 32716 | QPR, QPR, QPR, i32imm, i32imm, |
| 32717 | /* VQRSHLsv4i16 */ |
| 32718 | DPR, DPR, DPR, i32imm, i32imm, |
| 32719 | /* VQRSHLsv4i32 */ |
| 32720 | QPR, QPR, QPR, i32imm, i32imm, |
| 32721 | /* VQRSHLsv8i16 */ |
| 32722 | QPR, QPR, QPR, i32imm, i32imm, |
| 32723 | /* VQRSHLsv8i8 */ |
| 32724 | DPR, DPR, DPR, i32imm, i32imm, |
| 32725 | /* VQRSHLuv16i8 */ |
| 32726 | QPR, QPR, QPR, i32imm, i32imm, |
| 32727 | /* VQRSHLuv1i64 */ |
| 32728 | DPR, DPR, DPR, i32imm, i32imm, |
| 32729 | /* VQRSHLuv2i32 */ |
| 32730 | DPR, DPR, DPR, i32imm, i32imm, |
| 32731 | /* VQRSHLuv2i64 */ |
| 32732 | QPR, QPR, QPR, i32imm, i32imm, |
| 32733 | /* VQRSHLuv4i16 */ |
| 32734 | DPR, DPR, DPR, i32imm, i32imm, |
| 32735 | /* VQRSHLuv4i32 */ |
| 32736 | QPR, QPR, QPR, i32imm, i32imm, |
| 32737 | /* VQRSHLuv8i16 */ |
| 32738 | QPR, QPR, QPR, i32imm, i32imm, |
| 32739 | /* VQRSHLuv8i8 */ |
| 32740 | DPR, DPR, DPR, i32imm, i32imm, |
| 32741 | /* VQRSHRNsv2i32 */ |
| 32742 | DPR, QPR, shr_imm32, i32imm, i32imm, |
| 32743 | /* VQRSHRNsv4i16 */ |
| 32744 | DPR, QPR, shr_imm16, i32imm, i32imm, |
| 32745 | /* VQRSHRNsv8i8 */ |
| 32746 | DPR, QPR, shr_imm8, i32imm, i32imm, |
| 32747 | /* VQRSHRNuv2i32 */ |
| 32748 | DPR, QPR, shr_imm32, i32imm, i32imm, |
| 32749 | /* VQRSHRNuv4i16 */ |
| 32750 | DPR, QPR, shr_imm16, i32imm, i32imm, |
| 32751 | /* VQRSHRNuv8i8 */ |
| 32752 | DPR, QPR, shr_imm8, i32imm, i32imm, |
| 32753 | /* VQRSHRUNv2i32 */ |
| 32754 | DPR, QPR, shr_imm32, i32imm, i32imm, |
| 32755 | /* VQRSHRUNv4i16 */ |
| 32756 | DPR, QPR, shr_imm16, i32imm, i32imm, |
| 32757 | /* VQRSHRUNv8i8 */ |
| 32758 | DPR, QPR, shr_imm8, i32imm, i32imm, |
| 32759 | /* VQSHLsiv16i8 */ |
| 32760 | QPR, QPR, i32imm, i32imm, i32imm, |
| 32761 | /* VQSHLsiv1i64 */ |
| 32762 | DPR, DPR, i32imm, i32imm, i32imm, |
| 32763 | /* VQSHLsiv2i32 */ |
| 32764 | DPR, DPR, i32imm, i32imm, i32imm, |
| 32765 | /* VQSHLsiv2i64 */ |
| 32766 | QPR, QPR, i32imm, i32imm, i32imm, |
| 32767 | /* VQSHLsiv4i16 */ |
| 32768 | DPR, DPR, i32imm, i32imm, i32imm, |
| 32769 | /* VQSHLsiv4i32 */ |
| 32770 | QPR, QPR, i32imm, i32imm, i32imm, |
| 32771 | /* VQSHLsiv8i16 */ |
| 32772 | QPR, QPR, i32imm, i32imm, i32imm, |
| 32773 | /* VQSHLsiv8i8 */ |
| 32774 | DPR, DPR, i32imm, i32imm, i32imm, |
| 32775 | /* VQSHLsuv16i8 */ |
| 32776 | QPR, QPR, i32imm, i32imm, i32imm, |
| 32777 | /* VQSHLsuv1i64 */ |
| 32778 | DPR, DPR, i32imm, i32imm, i32imm, |
| 32779 | /* VQSHLsuv2i32 */ |
| 32780 | DPR, DPR, i32imm, i32imm, i32imm, |
| 32781 | /* VQSHLsuv2i64 */ |
| 32782 | QPR, QPR, i32imm, i32imm, i32imm, |
| 32783 | /* VQSHLsuv4i16 */ |
| 32784 | DPR, DPR, i32imm, i32imm, i32imm, |
| 32785 | /* VQSHLsuv4i32 */ |
| 32786 | QPR, QPR, i32imm, i32imm, i32imm, |
| 32787 | /* VQSHLsuv8i16 */ |
| 32788 | QPR, QPR, i32imm, i32imm, i32imm, |
| 32789 | /* VQSHLsuv8i8 */ |
| 32790 | DPR, DPR, i32imm, i32imm, i32imm, |
| 32791 | /* VQSHLsv16i8 */ |
| 32792 | QPR, QPR, QPR, i32imm, i32imm, |
| 32793 | /* VQSHLsv1i64 */ |
| 32794 | DPR, DPR, DPR, i32imm, i32imm, |
| 32795 | /* VQSHLsv2i32 */ |
| 32796 | DPR, DPR, DPR, i32imm, i32imm, |
| 32797 | /* VQSHLsv2i64 */ |
| 32798 | QPR, QPR, QPR, i32imm, i32imm, |
| 32799 | /* VQSHLsv4i16 */ |
| 32800 | DPR, DPR, DPR, i32imm, i32imm, |
| 32801 | /* VQSHLsv4i32 */ |
| 32802 | QPR, QPR, QPR, i32imm, i32imm, |
| 32803 | /* VQSHLsv8i16 */ |
| 32804 | QPR, QPR, QPR, i32imm, i32imm, |
| 32805 | /* VQSHLsv8i8 */ |
| 32806 | DPR, DPR, DPR, i32imm, i32imm, |
| 32807 | /* VQSHLuiv16i8 */ |
| 32808 | QPR, QPR, i32imm, i32imm, i32imm, |
| 32809 | /* VQSHLuiv1i64 */ |
| 32810 | DPR, DPR, i32imm, i32imm, i32imm, |
| 32811 | /* VQSHLuiv2i32 */ |
| 32812 | DPR, DPR, i32imm, i32imm, i32imm, |
| 32813 | /* VQSHLuiv2i64 */ |
| 32814 | QPR, QPR, i32imm, i32imm, i32imm, |
| 32815 | /* VQSHLuiv4i16 */ |
| 32816 | DPR, DPR, i32imm, i32imm, i32imm, |
| 32817 | /* VQSHLuiv4i32 */ |
| 32818 | QPR, QPR, i32imm, i32imm, i32imm, |
| 32819 | /* VQSHLuiv8i16 */ |
| 32820 | QPR, QPR, i32imm, i32imm, i32imm, |
| 32821 | /* VQSHLuiv8i8 */ |
| 32822 | DPR, DPR, i32imm, i32imm, i32imm, |
| 32823 | /* VQSHLuv16i8 */ |
| 32824 | QPR, QPR, QPR, i32imm, i32imm, |
| 32825 | /* VQSHLuv1i64 */ |
| 32826 | DPR, DPR, DPR, i32imm, i32imm, |
| 32827 | /* VQSHLuv2i32 */ |
| 32828 | DPR, DPR, DPR, i32imm, i32imm, |
| 32829 | /* VQSHLuv2i64 */ |
| 32830 | QPR, QPR, QPR, i32imm, i32imm, |
| 32831 | /* VQSHLuv4i16 */ |
| 32832 | DPR, DPR, DPR, i32imm, i32imm, |
| 32833 | /* VQSHLuv4i32 */ |
| 32834 | QPR, QPR, QPR, i32imm, i32imm, |
| 32835 | /* VQSHLuv8i16 */ |
| 32836 | QPR, QPR, QPR, i32imm, i32imm, |
| 32837 | /* VQSHLuv8i8 */ |
| 32838 | DPR, DPR, DPR, i32imm, i32imm, |
| 32839 | /* VQSHRNsv2i32 */ |
| 32840 | DPR, QPR, shr_imm32, i32imm, i32imm, |
| 32841 | /* VQSHRNsv4i16 */ |
| 32842 | DPR, QPR, shr_imm16, i32imm, i32imm, |
| 32843 | /* VQSHRNsv8i8 */ |
| 32844 | DPR, QPR, shr_imm8, i32imm, i32imm, |
| 32845 | /* VQSHRNuv2i32 */ |
| 32846 | DPR, QPR, shr_imm32, i32imm, i32imm, |
| 32847 | /* VQSHRNuv4i16 */ |
| 32848 | DPR, QPR, shr_imm16, i32imm, i32imm, |
| 32849 | /* VQSHRNuv8i8 */ |
| 32850 | DPR, QPR, shr_imm8, i32imm, i32imm, |
| 32851 | /* VQSHRUNv2i32 */ |
| 32852 | DPR, QPR, shr_imm32, i32imm, i32imm, |
| 32853 | /* VQSHRUNv4i16 */ |
| 32854 | DPR, QPR, shr_imm16, i32imm, i32imm, |
| 32855 | /* VQSHRUNv8i8 */ |
| 32856 | DPR, QPR, shr_imm8, i32imm, i32imm, |
| 32857 | /* VQSUBsv16i8 */ |
| 32858 | QPR, QPR, QPR, i32imm, i32imm, |
| 32859 | /* VQSUBsv1i64 */ |
| 32860 | DPR, DPR, DPR, i32imm, i32imm, |
| 32861 | /* VQSUBsv2i32 */ |
| 32862 | DPR, DPR, DPR, i32imm, i32imm, |
| 32863 | /* VQSUBsv2i64 */ |
| 32864 | QPR, QPR, QPR, i32imm, i32imm, |
| 32865 | /* VQSUBsv4i16 */ |
| 32866 | DPR, DPR, DPR, i32imm, i32imm, |
| 32867 | /* VQSUBsv4i32 */ |
| 32868 | QPR, QPR, QPR, i32imm, i32imm, |
| 32869 | /* VQSUBsv8i16 */ |
| 32870 | QPR, QPR, QPR, i32imm, i32imm, |
| 32871 | /* VQSUBsv8i8 */ |
| 32872 | DPR, DPR, DPR, i32imm, i32imm, |
| 32873 | /* VQSUBuv16i8 */ |
| 32874 | QPR, QPR, QPR, i32imm, i32imm, |
| 32875 | /* VQSUBuv1i64 */ |
| 32876 | DPR, DPR, DPR, i32imm, i32imm, |
| 32877 | /* VQSUBuv2i32 */ |
| 32878 | DPR, DPR, DPR, i32imm, i32imm, |
| 32879 | /* VQSUBuv2i64 */ |
| 32880 | QPR, QPR, QPR, i32imm, i32imm, |
| 32881 | /* VQSUBuv4i16 */ |
| 32882 | DPR, DPR, DPR, i32imm, i32imm, |
| 32883 | /* VQSUBuv4i32 */ |
| 32884 | QPR, QPR, QPR, i32imm, i32imm, |
| 32885 | /* VQSUBuv8i16 */ |
| 32886 | QPR, QPR, QPR, i32imm, i32imm, |
| 32887 | /* VQSUBuv8i8 */ |
| 32888 | DPR, DPR, DPR, i32imm, i32imm, |
| 32889 | /* VRADDHNv2i32 */ |
| 32890 | DPR, QPR, QPR, i32imm, i32imm, |
| 32891 | /* VRADDHNv4i16 */ |
| 32892 | DPR, QPR, QPR, i32imm, i32imm, |
| 32893 | /* VRADDHNv8i8 */ |
| 32894 | DPR, QPR, QPR, i32imm, i32imm, |
| 32895 | /* VRECPEd */ |
| 32896 | DPR, DPR, i32imm, i32imm, |
| 32897 | /* VRECPEfd */ |
| 32898 | DPR, DPR, i32imm, i32imm, |
| 32899 | /* VRECPEfq */ |
| 32900 | QPR, QPR, i32imm, i32imm, |
| 32901 | /* VRECPEhd */ |
| 32902 | DPR, DPR, i32imm, i32imm, |
| 32903 | /* VRECPEhq */ |
| 32904 | QPR, QPR, i32imm, i32imm, |
| 32905 | /* VRECPEq */ |
| 32906 | QPR, QPR, i32imm, i32imm, |
| 32907 | /* VRECPSfd */ |
| 32908 | DPR, DPR, DPR, i32imm, i32imm, |
| 32909 | /* VRECPSfq */ |
| 32910 | QPR, QPR, QPR, i32imm, i32imm, |
| 32911 | /* VRECPShd */ |
| 32912 | DPR, DPR, DPR, i32imm, i32imm, |
| 32913 | /* VRECPShq */ |
| 32914 | QPR, QPR, QPR, i32imm, i32imm, |
| 32915 | /* VREV16d8 */ |
| 32916 | DPR, DPR, i32imm, i32imm, |
| 32917 | /* VREV16q8 */ |
| 32918 | QPR, QPR, i32imm, i32imm, |
| 32919 | /* VREV32d16 */ |
| 32920 | DPR, DPR, i32imm, i32imm, |
| 32921 | /* VREV32d8 */ |
| 32922 | DPR, DPR, i32imm, i32imm, |
| 32923 | /* VREV32q16 */ |
| 32924 | QPR, QPR, i32imm, i32imm, |
| 32925 | /* VREV32q8 */ |
| 32926 | QPR, QPR, i32imm, i32imm, |
| 32927 | /* VREV64d16 */ |
| 32928 | DPR, DPR, i32imm, i32imm, |
| 32929 | /* VREV64d32 */ |
| 32930 | DPR, DPR, i32imm, i32imm, |
| 32931 | /* VREV64d8 */ |
| 32932 | DPR, DPR, i32imm, i32imm, |
| 32933 | /* VREV64q16 */ |
| 32934 | QPR, QPR, i32imm, i32imm, |
| 32935 | /* VREV64q32 */ |
| 32936 | QPR, QPR, i32imm, i32imm, |
| 32937 | /* VREV64q8 */ |
| 32938 | QPR, QPR, i32imm, i32imm, |
| 32939 | /* VRHADDsv16i8 */ |
| 32940 | QPR, QPR, QPR, i32imm, i32imm, |
| 32941 | /* VRHADDsv2i32 */ |
| 32942 | DPR, DPR, DPR, i32imm, i32imm, |
| 32943 | /* VRHADDsv4i16 */ |
| 32944 | DPR, DPR, DPR, i32imm, i32imm, |
| 32945 | /* VRHADDsv4i32 */ |
| 32946 | QPR, QPR, QPR, i32imm, i32imm, |
| 32947 | /* VRHADDsv8i16 */ |
| 32948 | QPR, QPR, QPR, i32imm, i32imm, |
| 32949 | /* VRHADDsv8i8 */ |
| 32950 | DPR, DPR, DPR, i32imm, i32imm, |
| 32951 | /* VRHADDuv16i8 */ |
| 32952 | QPR, QPR, QPR, i32imm, i32imm, |
| 32953 | /* VRHADDuv2i32 */ |
| 32954 | DPR, DPR, DPR, i32imm, i32imm, |
| 32955 | /* VRHADDuv4i16 */ |
| 32956 | DPR, DPR, DPR, i32imm, i32imm, |
| 32957 | /* VRHADDuv4i32 */ |
| 32958 | QPR, QPR, QPR, i32imm, i32imm, |
| 32959 | /* VRHADDuv8i16 */ |
| 32960 | QPR, QPR, QPR, i32imm, i32imm, |
| 32961 | /* VRHADDuv8i8 */ |
| 32962 | DPR, DPR, DPR, i32imm, i32imm, |
| 32963 | /* VRINTAD */ |
| 32964 | DPR, DPR, |
| 32965 | /* VRINTAH */ |
| 32966 | HPR, HPR, |
| 32967 | /* VRINTANDf */ |
| 32968 | DPR, DPR, |
| 32969 | /* VRINTANDh */ |
| 32970 | DPR, DPR, |
| 32971 | /* VRINTANQf */ |
| 32972 | QPR, QPR, |
| 32973 | /* VRINTANQh */ |
| 32974 | QPR, QPR, |
| 32975 | /* VRINTAS */ |
| 32976 | SPR, SPR, |
| 32977 | /* VRINTMD */ |
| 32978 | DPR, DPR, |
| 32979 | /* VRINTMH */ |
| 32980 | HPR, HPR, |
| 32981 | /* VRINTMNDf */ |
| 32982 | DPR, DPR, |
| 32983 | /* VRINTMNDh */ |
| 32984 | DPR, DPR, |
| 32985 | /* VRINTMNQf */ |
| 32986 | QPR, QPR, |
| 32987 | /* VRINTMNQh */ |
| 32988 | QPR, QPR, |
| 32989 | /* VRINTMS */ |
| 32990 | SPR, SPR, |
| 32991 | /* VRINTND */ |
| 32992 | DPR, DPR, |
| 32993 | /* VRINTNH */ |
| 32994 | HPR, HPR, |
| 32995 | /* VRINTNNDf */ |
| 32996 | DPR, DPR, |
| 32997 | /* VRINTNNDh */ |
| 32998 | DPR, DPR, |
| 32999 | /* VRINTNNQf */ |
| 33000 | QPR, QPR, |
| 33001 | /* VRINTNNQh */ |
| 33002 | QPR, QPR, |
| 33003 | /* VRINTNS */ |
| 33004 | SPR, SPR, |
| 33005 | /* VRINTPD */ |
| 33006 | DPR, DPR, |
| 33007 | /* VRINTPH */ |
| 33008 | HPR, HPR, |
| 33009 | /* VRINTPNDf */ |
| 33010 | DPR, DPR, |
| 33011 | /* VRINTPNDh */ |
| 33012 | DPR, DPR, |
| 33013 | /* VRINTPNQf */ |
| 33014 | QPR, QPR, |
| 33015 | /* VRINTPNQh */ |
| 33016 | QPR, QPR, |
| 33017 | /* VRINTPS */ |
| 33018 | SPR, SPR, |
| 33019 | /* VRINTRD */ |
| 33020 | DPR, DPR, i32imm, i32imm, |
| 33021 | /* VRINTRH */ |
| 33022 | HPR, HPR, i32imm, i32imm, |
| 33023 | /* VRINTRS */ |
| 33024 | SPR, SPR, i32imm, i32imm, |
| 33025 | /* VRINTXD */ |
| 33026 | DPR, DPR, i32imm, i32imm, |
| 33027 | /* VRINTXH */ |
| 33028 | HPR, HPR, i32imm, i32imm, |
| 33029 | /* VRINTXNDf */ |
| 33030 | DPR, DPR, |
| 33031 | /* VRINTXNDh */ |
| 33032 | DPR, DPR, |
| 33033 | /* VRINTXNQf */ |
| 33034 | QPR, QPR, |
| 33035 | /* VRINTXNQh */ |
| 33036 | QPR, QPR, |
| 33037 | /* VRINTXS */ |
| 33038 | SPR, SPR, i32imm, i32imm, |
| 33039 | /* VRINTZD */ |
| 33040 | DPR, DPR, i32imm, i32imm, |
| 33041 | /* VRINTZH */ |
| 33042 | HPR, HPR, i32imm, i32imm, |
| 33043 | /* VRINTZNDf */ |
| 33044 | DPR, DPR, |
| 33045 | /* VRINTZNDh */ |
| 33046 | DPR, DPR, |
| 33047 | /* VRINTZNQf */ |
| 33048 | QPR, QPR, |
| 33049 | /* VRINTZNQh */ |
| 33050 | QPR, QPR, |
| 33051 | /* VRINTZS */ |
| 33052 | SPR, SPR, i32imm, i32imm, |
| 33053 | /* VRSHLsv16i8 */ |
| 33054 | QPR, QPR, QPR, i32imm, i32imm, |
| 33055 | /* VRSHLsv1i64 */ |
| 33056 | DPR, DPR, DPR, i32imm, i32imm, |
| 33057 | /* VRSHLsv2i32 */ |
| 33058 | DPR, DPR, DPR, i32imm, i32imm, |
| 33059 | /* VRSHLsv2i64 */ |
| 33060 | QPR, QPR, QPR, i32imm, i32imm, |
| 33061 | /* VRSHLsv4i16 */ |
| 33062 | DPR, DPR, DPR, i32imm, i32imm, |
| 33063 | /* VRSHLsv4i32 */ |
| 33064 | QPR, QPR, QPR, i32imm, i32imm, |
| 33065 | /* VRSHLsv8i16 */ |
| 33066 | QPR, QPR, QPR, i32imm, i32imm, |
| 33067 | /* VRSHLsv8i8 */ |
| 33068 | DPR, DPR, DPR, i32imm, i32imm, |
| 33069 | /* VRSHLuv16i8 */ |
| 33070 | QPR, QPR, QPR, i32imm, i32imm, |
| 33071 | /* VRSHLuv1i64 */ |
| 33072 | DPR, DPR, DPR, i32imm, i32imm, |
| 33073 | /* VRSHLuv2i32 */ |
| 33074 | DPR, DPR, DPR, i32imm, i32imm, |
| 33075 | /* VRSHLuv2i64 */ |
| 33076 | QPR, QPR, QPR, i32imm, i32imm, |
| 33077 | /* VRSHLuv4i16 */ |
| 33078 | DPR, DPR, DPR, i32imm, i32imm, |
| 33079 | /* VRSHLuv4i32 */ |
| 33080 | QPR, QPR, QPR, i32imm, i32imm, |
| 33081 | /* VRSHLuv8i16 */ |
| 33082 | QPR, QPR, QPR, i32imm, i32imm, |
| 33083 | /* VRSHLuv8i8 */ |
| 33084 | DPR, DPR, DPR, i32imm, i32imm, |
| 33085 | /* VRSHRNv2i32 */ |
| 33086 | DPR, QPR, shr_imm32, i32imm, i32imm, |
| 33087 | /* VRSHRNv4i16 */ |
| 33088 | DPR, QPR, shr_imm16, i32imm, i32imm, |
| 33089 | /* VRSHRNv8i8 */ |
| 33090 | DPR, QPR, shr_imm8, i32imm, i32imm, |
| 33091 | /* VRSHRsv16i8 */ |
| 33092 | QPR, QPR, shr_imm8, i32imm, i32imm, |
| 33093 | /* VRSHRsv1i64 */ |
| 33094 | DPR, DPR, shr_imm64, i32imm, i32imm, |
| 33095 | /* VRSHRsv2i32 */ |
| 33096 | DPR, DPR, shr_imm32, i32imm, i32imm, |
| 33097 | /* VRSHRsv2i64 */ |
| 33098 | QPR, QPR, shr_imm64, i32imm, i32imm, |
| 33099 | /* VRSHRsv4i16 */ |
| 33100 | DPR, DPR, shr_imm16, i32imm, i32imm, |
| 33101 | /* VRSHRsv4i32 */ |
| 33102 | QPR, QPR, shr_imm32, i32imm, i32imm, |
| 33103 | /* VRSHRsv8i16 */ |
| 33104 | QPR, QPR, shr_imm16, i32imm, i32imm, |
| 33105 | /* VRSHRsv8i8 */ |
| 33106 | DPR, DPR, shr_imm8, i32imm, i32imm, |
| 33107 | /* VRSHRuv16i8 */ |
| 33108 | QPR, QPR, shr_imm8, i32imm, i32imm, |
| 33109 | /* VRSHRuv1i64 */ |
| 33110 | DPR, DPR, shr_imm64, i32imm, i32imm, |
| 33111 | /* VRSHRuv2i32 */ |
| 33112 | DPR, DPR, shr_imm32, i32imm, i32imm, |
| 33113 | /* VRSHRuv2i64 */ |
| 33114 | QPR, QPR, shr_imm64, i32imm, i32imm, |
| 33115 | /* VRSHRuv4i16 */ |
| 33116 | DPR, DPR, shr_imm16, i32imm, i32imm, |
| 33117 | /* VRSHRuv4i32 */ |
| 33118 | QPR, QPR, shr_imm32, i32imm, i32imm, |
| 33119 | /* VRSHRuv8i16 */ |
| 33120 | QPR, QPR, shr_imm16, i32imm, i32imm, |
| 33121 | /* VRSHRuv8i8 */ |
| 33122 | DPR, DPR, shr_imm8, i32imm, i32imm, |
| 33123 | /* VRSQRTEd */ |
| 33124 | DPR, DPR, i32imm, i32imm, |
| 33125 | /* VRSQRTEfd */ |
| 33126 | DPR, DPR, i32imm, i32imm, |
| 33127 | /* VRSQRTEfq */ |
| 33128 | QPR, QPR, i32imm, i32imm, |
| 33129 | /* VRSQRTEhd */ |
| 33130 | DPR, DPR, i32imm, i32imm, |
| 33131 | /* VRSQRTEhq */ |
| 33132 | QPR, QPR, i32imm, i32imm, |
| 33133 | /* VRSQRTEq */ |
| 33134 | QPR, QPR, i32imm, i32imm, |
| 33135 | /* VRSQRTSfd */ |
| 33136 | DPR, DPR, DPR, i32imm, i32imm, |
| 33137 | /* VRSQRTSfq */ |
| 33138 | QPR, QPR, QPR, i32imm, i32imm, |
| 33139 | /* VRSQRTShd */ |
| 33140 | DPR, DPR, DPR, i32imm, i32imm, |
| 33141 | /* VRSQRTShq */ |
| 33142 | QPR, QPR, QPR, i32imm, i32imm, |
| 33143 | /* VRSRAsv16i8 */ |
| 33144 | QPR, QPR, QPR, shr_imm8, i32imm, i32imm, |
| 33145 | /* VRSRAsv1i64 */ |
| 33146 | DPR, DPR, DPR, shr_imm64, i32imm, i32imm, |
| 33147 | /* VRSRAsv2i32 */ |
| 33148 | DPR, DPR, DPR, shr_imm32, i32imm, i32imm, |
| 33149 | /* VRSRAsv2i64 */ |
| 33150 | QPR, QPR, QPR, shr_imm64, i32imm, i32imm, |
| 33151 | /* VRSRAsv4i16 */ |
| 33152 | DPR, DPR, DPR, shr_imm16, i32imm, i32imm, |
| 33153 | /* VRSRAsv4i32 */ |
| 33154 | QPR, QPR, QPR, shr_imm32, i32imm, i32imm, |
| 33155 | /* VRSRAsv8i16 */ |
| 33156 | QPR, QPR, QPR, shr_imm16, i32imm, i32imm, |
| 33157 | /* VRSRAsv8i8 */ |
| 33158 | DPR, DPR, DPR, shr_imm8, i32imm, i32imm, |
| 33159 | /* VRSRAuv16i8 */ |
| 33160 | QPR, QPR, QPR, shr_imm8, i32imm, i32imm, |
| 33161 | /* VRSRAuv1i64 */ |
| 33162 | DPR, DPR, DPR, shr_imm64, i32imm, i32imm, |
| 33163 | /* VRSRAuv2i32 */ |
| 33164 | DPR, DPR, DPR, shr_imm32, i32imm, i32imm, |
| 33165 | /* VRSRAuv2i64 */ |
| 33166 | QPR, QPR, QPR, shr_imm64, i32imm, i32imm, |
| 33167 | /* VRSRAuv4i16 */ |
| 33168 | DPR, DPR, DPR, shr_imm16, i32imm, i32imm, |
| 33169 | /* VRSRAuv4i32 */ |
| 33170 | QPR, QPR, QPR, shr_imm32, i32imm, i32imm, |
| 33171 | /* VRSRAuv8i16 */ |
| 33172 | QPR, QPR, QPR, shr_imm16, i32imm, i32imm, |
| 33173 | /* VRSRAuv8i8 */ |
| 33174 | DPR, DPR, DPR, shr_imm8, i32imm, i32imm, |
| 33175 | /* VRSUBHNv2i32 */ |
| 33176 | DPR, QPR, QPR, i32imm, i32imm, |
| 33177 | /* VRSUBHNv4i16 */ |
| 33178 | DPR, QPR, QPR, i32imm, i32imm, |
| 33179 | /* VRSUBHNv8i8 */ |
| 33180 | DPR, QPR, QPR, i32imm, i32imm, |
| 33181 | /* VSCCLRMD */ |
| 33182 | i32imm, i32imm, fp_dreglist_with_vpr, |
| 33183 | /* VSCCLRMS */ |
| 33184 | i32imm, i32imm, fp_sreglist_with_vpr, |
| 33185 | /* VSDOTD */ |
| 33186 | DPR, DPR, DPR, DPR, |
| 33187 | /* VSDOTDI */ |
| 33188 | DPR, DPR, DPR, DPR_VFP2, i32imm, |
| 33189 | /* VSDOTQ */ |
| 33190 | QPR, QPR, QPR, QPR, |
| 33191 | /* VSDOTQI */ |
| 33192 | QPR, QPR, QPR, DPR_VFP2, i32imm, |
| 33193 | /* VSELEQD */ |
| 33194 | DPR, DPR, DPR, |
| 33195 | /* VSELEQH */ |
| 33196 | HPR, HPR, HPR, |
| 33197 | /* VSELEQS */ |
| 33198 | SPR, SPR, SPR, |
| 33199 | /* VSELGED */ |
| 33200 | DPR, DPR, DPR, |
| 33201 | /* VSELGEH */ |
| 33202 | HPR, HPR, HPR, |
| 33203 | /* VSELGES */ |
| 33204 | SPR, SPR, SPR, |
| 33205 | /* VSELGTD */ |
| 33206 | DPR, DPR, DPR, |
| 33207 | /* VSELGTH */ |
| 33208 | HPR, HPR, HPR, |
| 33209 | /* VSELGTS */ |
| 33210 | SPR, SPR, SPR, |
| 33211 | /* VSELVSD */ |
| 33212 | DPR, DPR, DPR, |
| 33213 | /* VSELVSH */ |
| 33214 | HPR, HPR, HPR, |
| 33215 | /* VSELVSS */ |
| 33216 | SPR, SPR, SPR, |
| 33217 | /* VSETLNi16 */ |
| 33218 | DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 33219 | /* VSETLNi32 */ |
| 33220 | DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 33221 | /* VSETLNi8 */ |
| 33222 | DPR, DPR, GPR, i32imm, i32imm, i32imm, |
| 33223 | /* VSHLLi16 */ |
| 33224 | QPR, DPR, imm16, i32imm, i32imm, |
| 33225 | /* VSHLLi32 */ |
| 33226 | QPR, DPR, imm32, i32imm, i32imm, |
| 33227 | /* VSHLLi8 */ |
| 33228 | QPR, DPR, imm8, i32imm, i32imm, |
| 33229 | /* VSHLLsv2i64 */ |
| 33230 | QPR, DPR, imm1_31, i32imm, i32imm, |
| 33231 | /* VSHLLsv4i32 */ |
| 33232 | QPR, DPR, imm1_15, i32imm, i32imm, |
| 33233 | /* VSHLLsv8i16 */ |
| 33234 | QPR, DPR, imm1_7, i32imm, i32imm, |
| 33235 | /* VSHLLuv2i64 */ |
| 33236 | QPR, DPR, imm1_31, i32imm, i32imm, |
| 33237 | /* VSHLLuv4i32 */ |
| 33238 | QPR, DPR, imm1_15, i32imm, i32imm, |
| 33239 | /* VSHLLuv8i16 */ |
| 33240 | QPR, DPR, imm1_7, i32imm, i32imm, |
| 33241 | /* VSHLiv16i8 */ |
| 33242 | QPR, QPR, i32imm, i32imm, i32imm, |
| 33243 | /* VSHLiv1i64 */ |
| 33244 | DPR, DPR, i32imm, i32imm, i32imm, |
| 33245 | /* VSHLiv2i32 */ |
| 33246 | DPR, DPR, i32imm, i32imm, i32imm, |
| 33247 | /* VSHLiv2i64 */ |
| 33248 | QPR, QPR, i32imm, i32imm, i32imm, |
| 33249 | /* VSHLiv4i16 */ |
| 33250 | DPR, DPR, i32imm, i32imm, i32imm, |
| 33251 | /* VSHLiv4i32 */ |
| 33252 | QPR, QPR, i32imm, i32imm, i32imm, |
| 33253 | /* VSHLiv8i16 */ |
| 33254 | QPR, QPR, i32imm, i32imm, i32imm, |
| 33255 | /* VSHLiv8i8 */ |
| 33256 | DPR, DPR, i32imm, i32imm, i32imm, |
| 33257 | /* VSHLsv16i8 */ |
| 33258 | QPR, QPR, QPR, i32imm, i32imm, |
| 33259 | /* VSHLsv1i64 */ |
| 33260 | DPR, DPR, DPR, i32imm, i32imm, |
| 33261 | /* VSHLsv2i32 */ |
| 33262 | DPR, DPR, DPR, i32imm, i32imm, |
| 33263 | /* VSHLsv2i64 */ |
| 33264 | QPR, QPR, QPR, i32imm, i32imm, |
| 33265 | /* VSHLsv4i16 */ |
| 33266 | DPR, DPR, DPR, i32imm, i32imm, |
| 33267 | /* VSHLsv4i32 */ |
| 33268 | QPR, QPR, QPR, i32imm, i32imm, |
| 33269 | /* VSHLsv8i16 */ |
| 33270 | QPR, QPR, QPR, i32imm, i32imm, |
| 33271 | /* VSHLsv8i8 */ |
| 33272 | DPR, DPR, DPR, i32imm, i32imm, |
| 33273 | /* VSHLuv16i8 */ |
| 33274 | QPR, QPR, QPR, i32imm, i32imm, |
| 33275 | /* VSHLuv1i64 */ |
| 33276 | DPR, DPR, DPR, i32imm, i32imm, |
| 33277 | /* VSHLuv2i32 */ |
| 33278 | DPR, DPR, DPR, i32imm, i32imm, |
| 33279 | /* VSHLuv2i64 */ |
| 33280 | QPR, QPR, QPR, i32imm, i32imm, |
| 33281 | /* VSHLuv4i16 */ |
| 33282 | DPR, DPR, DPR, i32imm, i32imm, |
| 33283 | /* VSHLuv4i32 */ |
| 33284 | QPR, QPR, QPR, i32imm, i32imm, |
| 33285 | /* VSHLuv8i16 */ |
| 33286 | QPR, QPR, QPR, i32imm, i32imm, |
| 33287 | /* VSHLuv8i8 */ |
| 33288 | DPR, DPR, DPR, i32imm, i32imm, |
| 33289 | /* VSHRNv2i32 */ |
| 33290 | DPR, QPR, shr_imm32, i32imm, i32imm, |
| 33291 | /* VSHRNv4i16 */ |
| 33292 | DPR, QPR, shr_imm16, i32imm, i32imm, |
| 33293 | /* VSHRNv8i8 */ |
| 33294 | DPR, QPR, shr_imm8, i32imm, i32imm, |
| 33295 | /* VSHRsv16i8 */ |
| 33296 | QPR, QPR, shr_imm8, i32imm, i32imm, |
| 33297 | /* VSHRsv1i64 */ |
| 33298 | DPR, DPR, shr_imm64, i32imm, i32imm, |
| 33299 | /* VSHRsv2i32 */ |
| 33300 | DPR, DPR, shr_imm32, i32imm, i32imm, |
| 33301 | /* VSHRsv2i64 */ |
| 33302 | QPR, QPR, shr_imm64, i32imm, i32imm, |
| 33303 | /* VSHRsv4i16 */ |
| 33304 | DPR, DPR, shr_imm16, i32imm, i32imm, |
| 33305 | /* VSHRsv4i32 */ |
| 33306 | QPR, QPR, shr_imm32, i32imm, i32imm, |
| 33307 | /* VSHRsv8i16 */ |
| 33308 | QPR, QPR, shr_imm16, i32imm, i32imm, |
| 33309 | /* VSHRsv8i8 */ |
| 33310 | DPR, DPR, shr_imm8, i32imm, i32imm, |
| 33311 | /* VSHRuv16i8 */ |
| 33312 | QPR, QPR, shr_imm8, i32imm, i32imm, |
| 33313 | /* VSHRuv1i64 */ |
| 33314 | DPR, DPR, shr_imm64, i32imm, i32imm, |
| 33315 | /* VSHRuv2i32 */ |
| 33316 | DPR, DPR, shr_imm32, i32imm, i32imm, |
| 33317 | /* VSHRuv2i64 */ |
| 33318 | QPR, QPR, shr_imm64, i32imm, i32imm, |
| 33319 | /* VSHRuv4i16 */ |
| 33320 | DPR, DPR, shr_imm16, i32imm, i32imm, |
| 33321 | /* VSHRuv4i32 */ |
| 33322 | QPR, QPR, shr_imm32, i32imm, i32imm, |
| 33323 | /* VSHRuv8i16 */ |
| 33324 | QPR, QPR, shr_imm16, i32imm, i32imm, |
| 33325 | /* VSHRuv8i8 */ |
| 33326 | DPR, DPR, shr_imm8, i32imm, i32imm, |
| 33327 | /* VSHTOD */ |
| 33328 | DPR, DPR, fbits16, i32imm, i32imm, |
| 33329 | /* VSHTOH */ |
| 33330 | SPR, SPR, fbits16, i32imm, i32imm, |
| 33331 | /* VSHTOS */ |
| 33332 | SPR, SPR, fbits16, i32imm, i32imm, |
| 33333 | /* VSITOD */ |
| 33334 | DPR, SPR, i32imm, i32imm, |
| 33335 | /* VSITOH */ |
| 33336 | HPR, SPR, i32imm, i32imm, |
| 33337 | /* VSITOS */ |
| 33338 | SPR, SPR, i32imm, i32imm, |
| 33339 | /* VSLIv16i8 */ |
| 33340 | QPR, QPR, QPR, i32imm, i32imm, i32imm, |
| 33341 | /* VSLIv1i64 */ |
| 33342 | DPR, DPR, DPR, i32imm, i32imm, i32imm, |
| 33343 | /* VSLIv2i32 */ |
| 33344 | DPR, DPR, DPR, i32imm, i32imm, i32imm, |
| 33345 | /* VSLIv2i64 */ |
| 33346 | QPR, QPR, QPR, i32imm, i32imm, i32imm, |
| 33347 | /* VSLIv4i16 */ |
| 33348 | DPR, DPR, DPR, i32imm, i32imm, i32imm, |
| 33349 | /* VSLIv4i32 */ |
| 33350 | QPR, QPR, QPR, i32imm, i32imm, i32imm, |
| 33351 | /* VSLIv8i16 */ |
| 33352 | QPR, QPR, QPR, i32imm, i32imm, i32imm, |
| 33353 | /* VSLIv8i8 */ |
| 33354 | DPR, DPR, DPR, i32imm, i32imm, i32imm, |
| 33355 | /* VSLTOD */ |
| 33356 | DPR, DPR, fbits32, i32imm, i32imm, |
| 33357 | /* VSLTOH */ |
| 33358 | SPR, SPR, fbits32, i32imm, i32imm, |
| 33359 | /* VSLTOS */ |
| 33360 | SPR, SPR, fbits32, i32imm, i32imm, |
| 33361 | /* VSMMLA */ |
| 33362 | QPR, QPR, QPR, QPR, |
| 33363 | /* VSQRTD */ |
| 33364 | DPR, DPR, i32imm, i32imm, |
| 33365 | /* VSQRTH */ |
| 33366 | HPR, HPR, i32imm, i32imm, |
| 33367 | /* VSQRTS */ |
| 33368 | SPR, SPR, i32imm, i32imm, |
| 33369 | /* VSRAsv16i8 */ |
| 33370 | QPR, QPR, QPR, shr_imm8, i32imm, i32imm, |
| 33371 | /* VSRAsv1i64 */ |
| 33372 | DPR, DPR, DPR, shr_imm64, i32imm, i32imm, |
| 33373 | /* VSRAsv2i32 */ |
| 33374 | DPR, DPR, DPR, shr_imm32, i32imm, i32imm, |
| 33375 | /* VSRAsv2i64 */ |
| 33376 | QPR, QPR, QPR, shr_imm64, i32imm, i32imm, |
| 33377 | /* VSRAsv4i16 */ |
| 33378 | DPR, DPR, DPR, shr_imm16, i32imm, i32imm, |
| 33379 | /* VSRAsv4i32 */ |
| 33380 | QPR, QPR, QPR, shr_imm32, i32imm, i32imm, |
| 33381 | /* VSRAsv8i16 */ |
| 33382 | QPR, QPR, QPR, shr_imm16, i32imm, i32imm, |
| 33383 | /* VSRAsv8i8 */ |
| 33384 | DPR, DPR, DPR, shr_imm8, i32imm, i32imm, |
| 33385 | /* VSRAuv16i8 */ |
| 33386 | QPR, QPR, QPR, shr_imm8, i32imm, i32imm, |
| 33387 | /* VSRAuv1i64 */ |
| 33388 | DPR, DPR, DPR, shr_imm64, i32imm, i32imm, |
| 33389 | /* VSRAuv2i32 */ |
| 33390 | DPR, DPR, DPR, shr_imm32, i32imm, i32imm, |
| 33391 | /* VSRAuv2i64 */ |
| 33392 | QPR, QPR, QPR, shr_imm64, i32imm, i32imm, |
| 33393 | /* VSRAuv4i16 */ |
| 33394 | DPR, DPR, DPR, shr_imm16, i32imm, i32imm, |
| 33395 | /* VSRAuv4i32 */ |
| 33396 | QPR, QPR, QPR, shr_imm32, i32imm, i32imm, |
| 33397 | /* VSRAuv8i16 */ |
| 33398 | QPR, QPR, QPR, shr_imm16, i32imm, i32imm, |
| 33399 | /* VSRAuv8i8 */ |
| 33400 | DPR, DPR, DPR, shr_imm8, i32imm, i32imm, |
| 33401 | /* VSRIv16i8 */ |
| 33402 | QPR, QPR, QPR, shr_imm8, i32imm, i32imm, |
| 33403 | /* VSRIv1i64 */ |
| 33404 | DPR, DPR, DPR, shr_imm64, i32imm, i32imm, |
| 33405 | /* VSRIv2i32 */ |
| 33406 | DPR, DPR, DPR, shr_imm32, i32imm, i32imm, |
| 33407 | /* VSRIv2i64 */ |
| 33408 | QPR, QPR, QPR, shr_imm64, i32imm, i32imm, |
| 33409 | /* VSRIv4i16 */ |
| 33410 | DPR, DPR, DPR, shr_imm16, i32imm, i32imm, |
| 33411 | /* VSRIv4i32 */ |
| 33412 | QPR, QPR, QPR, shr_imm32, i32imm, i32imm, |
| 33413 | /* VSRIv8i16 */ |
| 33414 | QPR, QPR, QPR, shr_imm16, i32imm, i32imm, |
| 33415 | /* VSRIv8i8 */ |
| 33416 | DPR, DPR, DPR, shr_imm8, i32imm, i32imm, |
| 33417 | /* VST1LNd16 */ |
| 33418 | GPR, i32imm, DPR, nohash_imm, i32imm, i32imm, |
| 33419 | /* VST1LNd16_UPD */ |
| 33420 | GPR, GPR, i32imm, GPR, DPR, nohash_imm, i32imm, i32imm, |
| 33421 | /* VST1LNd32 */ |
| 33422 | GPR, i32imm, DPR, nohash_imm, i32imm, i32imm, |
| 33423 | /* VST1LNd32_UPD */ |
| 33424 | GPR, GPR, i32imm, GPR, DPR, nohash_imm, i32imm, i32imm, |
| 33425 | /* VST1LNd8 */ |
| 33426 | GPR, i32imm, DPR, nohash_imm, i32imm, i32imm, |
| 33427 | /* VST1LNd8_UPD */ |
| 33428 | GPR, GPR, i32imm, GPR, DPR, nohash_imm, i32imm, i32imm, |
| 33429 | /* VST1LNq16Pseudo */ |
| 33430 | GPR, i32imm, QPR, nohash_imm, i32imm, i32imm, |
| 33431 | /* VST1LNq16Pseudo_UPD */ |
| 33432 | GPR, GPR, i32imm, GPR, QPR, nohash_imm, i32imm, i32imm, |
| 33433 | /* VST1LNq32Pseudo */ |
| 33434 | GPR, i32imm, QPR, nohash_imm, i32imm, i32imm, |
| 33435 | /* VST1LNq32Pseudo_UPD */ |
| 33436 | GPR, GPR, i32imm, GPR, QPR, nohash_imm, i32imm, i32imm, |
| 33437 | /* VST1LNq8Pseudo */ |
| 33438 | GPR, i32imm, QPR, nohash_imm, i32imm, i32imm, |
| 33439 | /* VST1LNq8Pseudo_UPD */ |
| 33440 | GPR, GPR, i32imm, GPR, QPR, nohash_imm, i32imm, i32imm, |
| 33441 | /* VST1d16 */ |
| 33442 | GPR, i32imm, VecListOneD, i32imm, i32imm, |
| 33443 | /* VST1d16Q */ |
| 33444 | GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33445 | /* VST1d16QPseudo */ |
| 33446 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33447 | /* VST1d16QPseudoWB_fixed */ |
| 33448 | GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 33449 | /* VST1d16QPseudoWB_register */ |
| 33450 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33451 | /* VST1d16Qwb_fixed */ |
| 33452 | GPR, GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33453 | /* VST1d16Qwb_register */ |
| 33454 | GPR, GPR, i32imm, rGPR, VecListFourD, i32imm, i32imm, |
| 33455 | /* VST1d16T */ |
| 33456 | GPR, i32imm, VecListThreeD, i32imm, i32imm, |
| 33457 | /* VST1d16TPseudo */ |
| 33458 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33459 | /* VST1d16TPseudoWB_fixed */ |
| 33460 | GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 33461 | /* VST1d16TPseudoWB_register */ |
| 33462 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33463 | /* VST1d16Twb_fixed */ |
| 33464 | GPR, GPR, i32imm, VecListThreeD, i32imm, i32imm, |
| 33465 | /* VST1d16Twb_register */ |
| 33466 | GPR, GPR, i32imm, rGPR, VecListThreeD, i32imm, i32imm, |
| 33467 | /* VST1d16wb_fixed */ |
| 33468 | GPR, GPR, i32imm, VecListOneD, i32imm, i32imm, |
| 33469 | /* VST1d16wb_register */ |
| 33470 | GPR, GPR, i32imm, rGPR, VecListOneD, i32imm, i32imm, |
| 33471 | /* VST1d32 */ |
| 33472 | GPR, i32imm, VecListOneD, i32imm, i32imm, |
| 33473 | /* VST1d32Q */ |
| 33474 | GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33475 | /* VST1d32QPseudo */ |
| 33476 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33477 | /* VST1d32QPseudoWB_fixed */ |
| 33478 | GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 33479 | /* VST1d32QPseudoWB_register */ |
| 33480 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33481 | /* VST1d32Qwb_fixed */ |
| 33482 | GPR, GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33483 | /* VST1d32Qwb_register */ |
| 33484 | GPR, GPR, i32imm, rGPR, VecListFourD, i32imm, i32imm, |
| 33485 | /* VST1d32T */ |
| 33486 | GPR, i32imm, VecListThreeD, i32imm, i32imm, |
| 33487 | /* VST1d32TPseudo */ |
| 33488 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33489 | /* VST1d32TPseudoWB_fixed */ |
| 33490 | GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 33491 | /* VST1d32TPseudoWB_register */ |
| 33492 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33493 | /* VST1d32Twb_fixed */ |
| 33494 | GPR, GPR, i32imm, VecListThreeD, i32imm, i32imm, |
| 33495 | /* VST1d32Twb_register */ |
| 33496 | GPR, GPR, i32imm, rGPR, VecListThreeD, i32imm, i32imm, |
| 33497 | /* VST1d32wb_fixed */ |
| 33498 | GPR, GPR, i32imm, VecListOneD, i32imm, i32imm, |
| 33499 | /* VST1d32wb_register */ |
| 33500 | GPR, GPR, i32imm, rGPR, VecListOneD, i32imm, i32imm, |
| 33501 | /* VST1d64 */ |
| 33502 | GPR, i32imm, VecListOneD, i32imm, i32imm, |
| 33503 | /* VST1d64Q */ |
| 33504 | GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33505 | /* VST1d64QPseudo */ |
| 33506 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33507 | /* VST1d64QPseudoWB_fixed */ |
| 33508 | GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 33509 | /* VST1d64QPseudoWB_register */ |
| 33510 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33511 | /* VST1d64Qwb_fixed */ |
| 33512 | GPR, GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33513 | /* VST1d64Qwb_register */ |
| 33514 | GPR, GPR, i32imm, rGPR, VecListFourD, i32imm, i32imm, |
| 33515 | /* VST1d64T */ |
| 33516 | GPR, i32imm, VecListThreeD, i32imm, i32imm, |
| 33517 | /* VST1d64TPseudo */ |
| 33518 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33519 | /* VST1d64TPseudoWB_fixed */ |
| 33520 | GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 33521 | /* VST1d64TPseudoWB_register */ |
| 33522 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33523 | /* VST1d64Twb_fixed */ |
| 33524 | GPR, GPR, i32imm, VecListThreeD, i32imm, i32imm, |
| 33525 | /* VST1d64Twb_register */ |
| 33526 | GPR, GPR, i32imm, rGPR, VecListThreeD, i32imm, i32imm, |
| 33527 | /* VST1d64wb_fixed */ |
| 33528 | GPR, GPR, i32imm, VecListOneD, i32imm, i32imm, |
| 33529 | /* VST1d64wb_register */ |
| 33530 | GPR, GPR, i32imm, rGPR, VecListOneD, i32imm, i32imm, |
| 33531 | /* VST1d8 */ |
| 33532 | GPR, i32imm, VecListOneD, i32imm, i32imm, |
| 33533 | /* VST1d8Q */ |
| 33534 | GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33535 | /* VST1d8QPseudo */ |
| 33536 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33537 | /* VST1d8QPseudoWB_fixed */ |
| 33538 | GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 33539 | /* VST1d8QPseudoWB_register */ |
| 33540 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33541 | /* VST1d8Qwb_fixed */ |
| 33542 | GPR, GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33543 | /* VST1d8Qwb_register */ |
| 33544 | GPR, GPR, i32imm, rGPR, VecListFourD, i32imm, i32imm, |
| 33545 | /* VST1d8T */ |
| 33546 | GPR, i32imm, VecListThreeD, i32imm, i32imm, |
| 33547 | /* VST1d8TPseudo */ |
| 33548 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33549 | /* VST1d8TPseudoWB_fixed */ |
| 33550 | GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 33551 | /* VST1d8TPseudoWB_register */ |
| 33552 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33553 | /* VST1d8Twb_fixed */ |
| 33554 | GPR, GPR, i32imm, VecListThreeD, i32imm, i32imm, |
| 33555 | /* VST1d8Twb_register */ |
| 33556 | GPR, GPR, i32imm, rGPR, VecListThreeD, i32imm, i32imm, |
| 33557 | /* VST1d8wb_fixed */ |
| 33558 | GPR, GPR, i32imm, VecListOneD, i32imm, i32imm, |
| 33559 | /* VST1d8wb_register */ |
| 33560 | GPR, GPR, i32imm, rGPR, VecListOneD, i32imm, i32imm, |
| 33561 | /* VST1q16 */ |
| 33562 | GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33563 | /* VST1q16HighQPseudo */ |
| 33564 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33565 | /* VST1q16HighQPseudo_UPD */ |
| 33566 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33567 | /* VST1q16HighTPseudo */ |
| 33568 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33569 | /* VST1q16HighTPseudo_UPD */ |
| 33570 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33571 | /* VST1q16LowQPseudo_UPD */ |
| 33572 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33573 | /* VST1q16LowTPseudo_UPD */ |
| 33574 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33575 | /* VST1q16wb_fixed */ |
| 33576 | GPR, GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33577 | /* VST1q16wb_register */ |
| 33578 | GPR, GPR, i32imm, rGPR, VecListDPair, i32imm, i32imm, |
| 33579 | /* VST1q32 */ |
| 33580 | GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33581 | /* VST1q32HighQPseudo */ |
| 33582 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33583 | /* VST1q32HighQPseudo_UPD */ |
| 33584 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33585 | /* VST1q32HighTPseudo */ |
| 33586 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33587 | /* VST1q32HighTPseudo_UPD */ |
| 33588 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33589 | /* VST1q32LowQPseudo_UPD */ |
| 33590 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33591 | /* VST1q32LowTPseudo_UPD */ |
| 33592 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33593 | /* VST1q32wb_fixed */ |
| 33594 | GPR, GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33595 | /* VST1q32wb_register */ |
| 33596 | GPR, GPR, i32imm, rGPR, VecListDPair, i32imm, i32imm, |
| 33597 | /* VST1q64 */ |
| 33598 | GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33599 | /* VST1q64HighQPseudo */ |
| 33600 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33601 | /* VST1q64HighQPseudo_UPD */ |
| 33602 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33603 | /* VST1q64HighTPseudo */ |
| 33604 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33605 | /* VST1q64HighTPseudo_UPD */ |
| 33606 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33607 | /* VST1q64LowQPseudo_UPD */ |
| 33608 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33609 | /* VST1q64LowTPseudo_UPD */ |
| 33610 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33611 | /* VST1q64wb_fixed */ |
| 33612 | GPR, GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33613 | /* VST1q64wb_register */ |
| 33614 | GPR, GPR, i32imm, rGPR, VecListDPair, i32imm, i32imm, |
| 33615 | /* VST1q8 */ |
| 33616 | GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33617 | /* VST1q8HighQPseudo */ |
| 33618 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33619 | /* VST1q8HighQPseudo_UPD */ |
| 33620 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33621 | /* VST1q8HighTPseudo */ |
| 33622 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33623 | /* VST1q8HighTPseudo_UPD */ |
| 33624 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33625 | /* VST1q8LowQPseudo_UPD */ |
| 33626 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33627 | /* VST1q8LowTPseudo_UPD */ |
| 33628 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33629 | /* VST1q8wb_fixed */ |
| 33630 | GPR, GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33631 | /* VST1q8wb_register */ |
| 33632 | GPR, GPR, i32imm, rGPR, VecListDPair, i32imm, i32imm, |
| 33633 | /* VST2LNd16 */ |
| 33634 | GPR, i32imm, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33635 | /* VST2LNd16Pseudo */ |
| 33636 | GPR, i32imm, QPR, nohash_imm, i32imm, i32imm, |
| 33637 | /* VST2LNd16Pseudo_UPD */ |
| 33638 | GPR, GPR, i32imm, GPR, QPR, nohash_imm, i32imm, i32imm, |
| 33639 | /* VST2LNd16_UPD */ |
| 33640 | GPR, GPR, i32imm, GPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33641 | /* VST2LNd32 */ |
| 33642 | GPR, i32imm, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33643 | /* VST2LNd32Pseudo */ |
| 33644 | GPR, i32imm, QPR, nohash_imm, i32imm, i32imm, |
| 33645 | /* VST2LNd32Pseudo_UPD */ |
| 33646 | GPR, GPR, i32imm, GPR, QPR, nohash_imm, i32imm, i32imm, |
| 33647 | /* VST2LNd32_UPD */ |
| 33648 | GPR, GPR, i32imm, GPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33649 | /* VST2LNd8 */ |
| 33650 | GPR, i32imm, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33651 | /* VST2LNd8Pseudo */ |
| 33652 | GPR, i32imm, QPR, nohash_imm, i32imm, i32imm, |
| 33653 | /* VST2LNd8Pseudo_UPD */ |
| 33654 | GPR, GPR, i32imm, GPR, QPR, nohash_imm, i32imm, i32imm, |
| 33655 | /* VST2LNd8_UPD */ |
| 33656 | GPR, GPR, i32imm, GPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33657 | /* VST2LNq16 */ |
| 33658 | GPR, i32imm, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33659 | /* VST2LNq16Pseudo */ |
| 33660 | GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 33661 | /* VST2LNq16Pseudo_UPD */ |
| 33662 | GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 33663 | /* VST2LNq16_UPD */ |
| 33664 | GPR, GPR, i32imm, GPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33665 | /* VST2LNq32 */ |
| 33666 | GPR, i32imm, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33667 | /* VST2LNq32Pseudo */ |
| 33668 | GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 33669 | /* VST2LNq32Pseudo_UPD */ |
| 33670 | GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 33671 | /* VST2LNq32_UPD */ |
| 33672 | GPR, GPR, i32imm, GPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33673 | /* VST2b16 */ |
| 33674 | GPR, i32imm, VecListDPairSpaced, i32imm, i32imm, |
| 33675 | /* VST2b16wb_fixed */ |
| 33676 | GPR, GPR, i32imm, VecListDPairSpaced, i32imm, i32imm, |
| 33677 | /* VST2b16wb_register */ |
| 33678 | GPR, GPR, i32imm, rGPR, VecListDPairSpaced, i32imm, i32imm, |
| 33679 | /* VST2b32 */ |
| 33680 | GPR, i32imm, VecListDPairSpaced, i32imm, i32imm, |
| 33681 | /* VST2b32wb_fixed */ |
| 33682 | GPR, GPR, i32imm, VecListDPairSpaced, i32imm, i32imm, |
| 33683 | /* VST2b32wb_register */ |
| 33684 | GPR, GPR, i32imm, rGPR, VecListDPairSpaced, i32imm, i32imm, |
| 33685 | /* VST2b8 */ |
| 33686 | GPR, i32imm, VecListDPairSpaced, i32imm, i32imm, |
| 33687 | /* VST2b8wb_fixed */ |
| 33688 | GPR, GPR, i32imm, VecListDPairSpaced, i32imm, i32imm, |
| 33689 | /* VST2b8wb_register */ |
| 33690 | GPR, GPR, i32imm, rGPR, VecListDPairSpaced, i32imm, i32imm, |
| 33691 | /* VST2d16 */ |
| 33692 | GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33693 | /* VST2d16wb_fixed */ |
| 33694 | GPR, GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33695 | /* VST2d16wb_register */ |
| 33696 | GPR, GPR, i32imm, rGPR, VecListDPair, i32imm, i32imm, |
| 33697 | /* VST2d32 */ |
| 33698 | GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33699 | /* VST2d32wb_fixed */ |
| 33700 | GPR, GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33701 | /* VST2d32wb_register */ |
| 33702 | GPR, GPR, i32imm, rGPR, VecListDPair, i32imm, i32imm, |
| 33703 | /* VST2d8 */ |
| 33704 | GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33705 | /* VST2d8wb_fixed */ |
| 33706 | GPR, GPR, i32imm, VecListDPair, i32imm, i32imm, |
| 33707 | /* VST2d8wb_register */ |
| 33708 | GPR, GPR, i32imm, rGPR, VecListDPair, i32imm, i32imm, |
| 33709 | /* VST2q16 */ |
| 33710 | GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33711 | /* VST2q16Pseudo */ |
| 33712 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33713 | /* VST2q16PseudoWB_fixed */ |
| 33714 | GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 33715 | /* VST2q16PseudoWB_register */ |
| 33716 | GPR, GPR, i32imm, rGPR, QQPR, i32imm, i32imm, |
| 33717 | /* VST2q16wb_fixed */ |
| 33718 | GPR, GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33719 | /* VST2q16wb_register */ |
| 33720 | GPR, GPR, i32imm, rGPR, VecListFourD, i32imm, i32imm, |
| 33721 | /* VST2q32 */ |
| 33722 | GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33723 | /* VST2q32Pseudo */ |
| 33724 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33725 | /* VST2q32PseudoWB_fixed */ |
| 33726 | GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 33727 | /* VST2q32PseudoWB_register */ |
| 33728 | GPR, GPR, i32imm, rGPR, QQPR, i32imm, i32imm, |
| 33729 | /* VST2q32wb_fixed */ |
| 33730 | GPR, GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33731 | /* VST2q32wb_register */ |
| 33732 | GPR, GPR, i32imm, rGPR, VecListFourD, i32imm, i32imm, |
| 33733 | /* VST2q8 */ |
| 33734 | GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33735 | /* VST2q8Pseudo */ |
| 33736 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33737 | /* VST2q8PseudoWB_fixed */ |
| 33738 | GPR, GPR, i32imm, QQPR, i32imm, i32imm, |
| 33739 | /* VST2q8PseudoWB_register */ |
| 33740 | GPR, GPR, i32imm, rGPR, QQPR, i32imm, i32imm, |
| 33741 | /* VST2q8wb_fixed */ |
| 33742 | GPR, GPR, i32imm, VecListFourD, i32imm, i32imm, |
| 33743 | /* VST2q8wb_register */ |
| 33744 | GPR, GPR, i32imm, rGPR, VecListFourD, i32imm, i32imm, |
| 33745 | /* VST3LNd16 */ |
| 33746 | GPR, i32imm, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33747 | /* VST3LNd16Pseudo */ |
| 33748 | GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 33749 | /* VST3LNd16Pseudo_UPD */ |
| 33750 | GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 33751 | /* VST3LNd16_UPD */ |
| 33752 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33753 | /* VST3LNd32 */ |
| 33754 | GPR, i32imm, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33755 | /* VST3LNd32Pseudo */ |
| 33756 | GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 33757 | /* VST3LNd32Pseudo_UPD */ |
| 33758 | GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 33759 | /* VST3LNd32_UPD */ |
| 33760 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33761 | /* VST3LNd8 */ |
| 33762 | GPR, i32imm, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33763 | /* VST3LNd8Pseudo */ |
| 33764 | GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 33765 | /* VST3LNd8Pseudo_UPD */ |
| 33766 | GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 33767 | /* VST3LNd8_UPD */ |
| 33768 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33769 | /* VST3LNq16 */ |
| 33770 | GPR, i32imm, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33771 | /* VST3LNq16Pseudo */ |
| 33772 | GPR, i32imm, QQQQPR, nohash_imm, i32imm, i32imm, |
| 33773 | /* VST3LNq16Pseudo_UPD */ |
| 33774 | GPR, GPR, i32imm, GPR, QQQQPR, nohash_imm, i32imm, i32imm, |
| 33775 | /* VST3LNq16_UPD */ |
| 33776 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33777 | /* VST3LNq32 */ |
| 33778 | GPR, i32imm, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33779 | /* VST3LNq32Pseudo */ |
| 33780 | GPR, i32imm, QQQQPR, nohash_imm, i32imm, i32imm, |
| 33781 | /* VST3LNq32Pseudo_UPD */ |
| 33782 | GPR, GPR, i32imm, GPR, QQQQPR, nohash_imm, i32imm, i32imm, |
| 33783 | /* VST3LNq32_UPD */ |
| 33784 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33785 | /* VST3d16 */ |
| 33786 | GPR, i32imm, DPR, DPR, DPR, i32imm, i32imm, |
| 33787 | /* VST3d16Pseudo */ |
| 33788 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33789 | /* VST3d16Pseudo_UPD */ |
| 33790 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33791 | /* VST3d16_UPD */ |
| 33792 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33793 | /* VST3d32 */ |
| 33794 | GPR, i32imm, DPR, DPR, DPR, i32imm, i32imm, |
| 33795 | /* VST3d32Pseudo */ |
| 33796 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33797 | /* VST3d32Pseudo_UPD */ |
| 33798 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33799 | /* VST3d32_UPD */ |
| 33800 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33801 | /* VST3d8 */ |
| 33802 | GPR, i32imm, DPR, DPR, DPR, i32imm, i32imm, |
| 33803 | /* VST3d8Pseudo */ |
| 33804 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33805 | /* VST3d8Pseudo_UPD */ |
| 33806 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33807 | /* VST3d8_UPD */ |
| 33808 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33809 | /* VST3q16 */ |
| 33810 | GPR, i32imm, DPR, DPR, DPR, i32imm, i32imm, |
| 33811 | /* VST3q16Pseudo_UPD */ |
| 33812 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33813 | /* VST3q16_UPD */ |
| 33814 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33815 | /* VST3q16oddPseudo */ |
| 33816 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33817 | /* VST3q16oddPseudo_UPD */ |
| 33818 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33819 | /* VST3q32 */ |
| 33820 | GPR, i32imm, DPR, DPR, DPR, i32imm, i32imm, |
| 33821 | /* VST3q32Pseudo_UPD */ |
| 33822 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33823 | /* VST3q32_UPD */ |
| 33824 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33825 | /* VST3q32oddPseudo */ |
| 33826 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33827 | /* VST3q32oddPseudo_UPD */ |
| 33828 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33829 | /* VST3q8 */ |
| 33830 | GPR, i32imm, DPR, DPR, DPR, i32imm, i32imm, |
| 33831 | /* VST3q8Pseudo_UPD */ |
| 33832 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33833 | /* VST3q8_UPD */ |
| 33834 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33835 | /* VST3q8oddPseudo */ |
| 33836 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33837 | /* VST3q8oddPseudo_UPD */ |
| 33838 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33839 | /* VST4LNd16 */ |
| 33840 | GPR, i32imm, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33841 | /* VST4LNd16Pseudo */ |
| 33842 | GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 33843 | /* VST4LNd16Pseudo_UPD */ |
| 33844 | GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 33845 | /* VST4LNd16_UPD */ |
| 33846 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33847 | /* VST4LNd32 */ |
| 33848 | GPR, i32imm, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33849 | /* VST4LNd32Pseudo */ |
| 33850 | GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 33851 | /* VST4LNd32Pseudo_UPD */ |
| 33852 | GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 33853 | /* VST4LNd32_UPD */ |
| 33854 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33855 | /* VST4LNd8 */ |
| 33856 | GPR, i32imm, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33857 | /* VST4LNd8Pseudo */ |
| 33858 | GPR, i32imm, QQPR, nohash_imm, i32imm, i32imm, |
| 33859 | /* VST4LNd8Pseudo_UPD */ |
| 33860 | GPR, GPR, i32imm, GPR, QQPR, nohash_imm, i32imm, i32imm, |
| 33861 | /* VST4LNd8_UPD */ |
| 33862 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33863 | /* VST4LNq16 */ |
| 33864 | GPR, i32imm, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33865 | /* VST4LNq16Pseudo */ |
| 33866 | GPR, i32imm, QQQQPR, nohash_imm, i32imm, i32imm, |
| 33867 | /* VST4LNq16Pseudo_UPD */ |
| 33868 | GPR, GPR, i32imm, GPR, QQQQPR, nohash_imm, i32imm, i32imm, |
| 33869 | /* VST4LNq16_UPD */ |
| 33870 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33871 | /* VST4LNq32 */ |
| 33872 | GPR, i32imm, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33873 | /* VST4LNq32Pseudo */ |
| 33874 | GPR, i32imm, QQQQPR, nohash_imm, i32imm, i32imm, |
| 33875 | /* VST4LNq32Pseudo_UPD */ |
| 33876 | GPR, GPR, i32imm, GPR, QQQQPR, nohash_imm, i32imm, i32imm, |
| 33877 | /* VST4LNq32_UPD */ |
| 33878 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, nohash_imm, i32imm, i32imm, |
| 33879 | /* VST4d16 */ |
| 33880 | GPR, i32imm, DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33881 | /* VST4d16Pseudo */ |
| 33882 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33883 | /* VST4d16Pseudo_UPD */ |
| 33884 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33885 | /* VST4d16_UPD */ |
| 33886 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33887 | /* VST4d32 */ |
| 33888 | GPR, i32imm, DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33889 | /* VST4d32Pseudo */ |
| 33890 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33891 | /* VST4d32Pseudo_UPD */ |
| 33892 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33893 | /* VST4d32_UPD */ |
| 33894 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33895 | /* VST4d8 */ |
| 33896 | GPR, i32imm, DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33897 | /* VST4d8Pseudo */ |
| 33898 | GPR, i32imm, QQPR, i32imm, i32imm, |
| 33899 | /* VST4d8Pseudo_UPD */ |
| 33900 | GPR, GPR, i32imm, GPR, QQPR, i32imm, i32imm, |
| 33901 | /* VST4d8_UPD */ |
| 33902 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33903 | /* VST4q16 */ |
| 33904 | GPR, i32imm, DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33905 | /* VST4q16Pseudo_UPD */ |
| 33906 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33907 | /* VST4q16_UPD */ |
| 33908 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33909 | /* VST4q16oddPseudo */ |
| 33910 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33911 | /* VST4q16oddPseudo_UPD */ |
| 33912 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33913 | /* VST4q32 */ |
| 33914 | GPR, i32imm, DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33915 | /* VST4q32Pseudo_UPD */ |
| 33916 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33917 | /* VST4q32_UPD */ |
| 33918 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33919 | /* VST4q32oddPseudo */ |
| 33920 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33921 | /* VST4q32oddPseudo_UPD */ |
| 33922 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33923 | /* VST4q8 */ |
| 33924 | GPR, i32imm, DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33925 | /* VST4q8Pseudo_UPD */ |
| 33926 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33927 | /* VST4q8_UPD */ |
| 33928 | GPR, GPR, i32imm, GPR, DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 33929 | /* VST4q8oddPseudo */ |
| 33930 | GPR, i32imm, QQQQPR, i32imm, i32imm, |
| 33931 | /* VST4q8oddPseudo_UPD */ |
| 33932 | GPR, GPR, i32imm, GPR, QQQQPR, i32imm, i32imm, |
| 33933 | /* VSTMDDB_UPD */ |
| 33934 | GPR, GPR, i32imm, i32imm, dpr_reglist, |
| 33935 | /* VSTMDIA */ |
| 33936 | GPR, i32imm, i32imm, dpr_reglist, |
| 33937 | /* VSTMDIA_UPD */ |
| 33938 | GPR, GPR, i32imm, i32imm, dpr_reglist, |
| 33939 | /* VSTMQIA */ |
| 33940 | DPair, GPR, i32imm, i32imm, |
| 33941 | /* VSTMSDB_UPD */ |
| 33942 | GPR, GPR, i32imm, i32imm, spr_reglist, |
| 33943 | /* VSTMSIA */ |
| 33944 | GPR, i32imm, i32imm, spr_reglist, |
| 33945 | /* VSTMSIA_UPD */ |
| 33946 | GPR, GPR, i32imm, i32imm, spr_reglist, |
| 33947 | /* VSTRD */ |
| 33948 | DPR, GPR, i32imm, i32imm, i32imm, |
| 33949 | /* VSTRH */ |
| 33950 | HPR, GPR, i32imm, i32imm, i32imm, |
| 33951 | /* VSTRS */ |
| 33952 | SPR, GPR, i32imm, i32imm, i32imm, |
| 33953 | /* VSTR_FPCXTNS_off */ |
| 33954 | GPRnopc, i32imm, i32imm, i32imm, |
| 33955 | /* VSTR_FPCXTNS_post */ |
| 33956 | GPRnopc, GPRnopc, t2am_imm7s4_offset, i32imm, i32imm, |
| 33957 | /* VSTR_FPCXTNS_pre */ |
| 33958 | GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 33959 | /* VSTR_FPCXTS_off */ |
| 33960 | GPRnopc, i32imm, i32imm, i32imm, |
| 33961 | /* VSTR_FPCXTS_post */ |
| 33962 | GPRnopc, GPRnopc, t2am_imm7s4_offset, i32imm, i32imm, |
| 33963 | /* VSTR_FPCXTS_pre */ |
| 33964 | GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 33965 | /* VSTR_FPSCR_NZCVQC_off */ |
| 33966 | GPRnopc, i32imm, i32imm, i32imm, |
| 33967 | /* VSTR_FPSCR_NZCVQC_post */ |
| 33968 | GPRnopc, GPRnopc, t2am_imm7s4_offset, i32imm, i32imm, |
| 33969 | /* VSTR_FPSCR_NZCVQC_pre */ |
| 33970 | GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 33971 | /* VSTR_FPSCR_off */ |
| 33972 | GPRnopc, i32imm, i32imm, i32imm, |
| 33973 | /* VSTR_FPSCR_post */ |
| 33974 | GPRnopc, GPRnopc, t2am_imm7s4_offset, i32imm, i32imm, |
| 33975 | /* VSTR_FPSCR_pre */ |
| 33976 | GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 33977 | /* VSTR_P0_off */ |
| 33978 | VCCR, GPRnopc, i32imm, i32imm, i32imm, |
| 33979 | /* VSTR_P0_post */ |
| 33980 | GPRnopc, VCCR, GPRnopc, t2am_imm7s4_offset, i32imm, i32imm, |
| 33981 | /* VSTR_P0_pre */ |
| 33982 | GPRnopc, VCCR, GPRnopc, i32imm, i32imm, i32imm, |
| 33983 | /* VSTR_VPR_off */ |
| 33984 | GPRnopc, i32imm, i32imm, i32imm, |
| 33985 | /* VSTR_VPR_post */ |
| 33986 | GPRnopc, GPRnopc, t2am_imm7s4_offset, i32imm, i32imm, |
| 33987 | /* VSTR_VPR_pre */ |
| 33988 | GPRnopc, GPRnopc, i32imm, i32imm, i32imm, |
| 33989 | /* VSUBD */ |
| 33990 | DPR, DPR, DPR, i32imm, i32imm, |
| 33991 | /* VSUBH */ |
| 33992 | HPR, HPR, HPR, i32imm, i32imm, |
| 33993 | /* VSUBHNv2i32 */ |
| 33994 | DPR, QPR, QPR, i32imm, i32imm, |
| 33995 | /* VSUBHNv4i16 */ |
| 33996 | DPR, QPR, QPR, i32imm, i32imm, |
| 33997 | /* VSUBHNv8i8 */ |
| 33998 | DPR, QPR, QPR, i32imm, i32imm, |
| 33999 | /* VSUBLsv2i64 */ |
| 34000 | QPR, DPR, DPR, i32imm, i32imm, |
| 34001 | /* VSUBLsv4i32 */ |
| 34002 | QPR, DPR, DPR, i32imm, i32imm, |
| 34003 | /* VSUBLsv8i16 */ |
| 34004 | QPR, DPR, DPR, i32imm, i32imm, |
| 34005 | /* VSUBLuv2i64 */ |
| 34006 | QPR, DPR, DPR, i32imm, i32imm, |
| 34007 | /* VSUBLuv4i32 */ |
| 34008 | QPR, DPR, DPR, i32imm, i32imm, |
| 34009 | /* VSUBLuv8i16 */ |
| 34010 | QPR, DPR, DPR, i32imm, i32imm, |
| 34011 | /* VSUBS */ |
| 34012 | SPR, SPR, SPR, i32imm, i32imm, |
| 34013 | /* VSUBWsv2i64 */ |
| 34014 | QPR, QPR, DPR, i32imm, i32imm, |
| 34015 | /* VSUBWsv4i32 */ |
| 34016 | QPR, QPR, DPR, i32imm, i32imm, |
| 34017 | /* VSUBWsv8i16 */ |
| 34018 | QPR, QPR, DPR, i32imm, i32imm, |
| 34019 | /* VSUBWuv2i64 */ |
| 34020 | QPR, QPR, DPR, i32imm, i32imm, |
| 34021 | /* VSUBWuv4i32 */ |
| 34022 | QPR, QPR, DPR, i32imm, i32imm, |
| 34023 | /* VSUBWuv8i16 */ |
| 34024 | QPR, QPR, DPR, i32imm, i32imm, |
| 34025 | /* VSUBfd */ |
| 34026 | DPR, DPR, DPR, i32imm, i32imm, |
| 34027 | /* VSUBfq */ |
| 34028 | QPR, QPR, QPR, i32imm, i32imm, |
| 34029 | /* VSUBhd */ |
| 34030 | DPR, DPR, DPR, i32imm, i32imm, |
| 34031 | /* VSUBhq */ |
| 34032 | QPR, QPR, QPR, i32imm, i32imm, |
| 34033 | /* VSUBv16i8 */ |
| 34034 | QPR, QPR, QPR, i32imm, i32imm, |
| 34035 | /* VSUBv1i64 */ |
| 34036 | DPR, DPR, DPR, i32imm, i32imm, |
| 34037 | /* VSUBv2i32 */ |
| 34038 | DPR, DPR, DPR, i32imm, i32imm, |
| 34039 | /* VSUBv2i64 */ |
| 34040 | QPR, QPR, QPR, i32imm, i32imm, |
| 34041 | /* VSUBv4i16 */ |
| 34042 | DPR, DPR, DPR, i32imm, i32imm, |
| 34043 | /* VSUBv4i32 */ |
| 34044 | QPR, QPR, QPR, i32imm, i32imm, |
| 34045 | /* VSUBv8i16 */ |
| 34046 | QPR, QPR, QPR, i32imm, i32imm, |
| 34047 | /* VSUBv8i8 */ |
| 34048 | DPR, DPR, DPR, i32imm, i32imm, |
| 34049 | /* VSUDOTDI */ |
| 34050 | DPR, DPR, DPR, DPR_VFP2, i32imm, |
| 34051 | /* VSUDOTQI */ |
| 34052 | QPR, QPR, QPR, DPR_VFP2, i32imm, |
| 34053 | /* VSWPd */ |
| 34054 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 34055 | /* VSWPq */ |
| 34056 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 34057 | /* VTBL1 */ |
| 34058 | DPR, VecListOneD, DPR, i32imm, i32imm, |
| 34059 | /* VTBL2 */ |
| 34060 | DPR, VecListDPair, DPR, i32imm, i32imm, |
| 34061 | /* VTBL3 */ |
| 34062 | DPR, VecListThreeD, DPR, i32imm, i32imm, |
| 34063 | /* VTBL3Pseudo */ |
| 34064 | DPR, QQPR, DPR, i32imm, i32imm, |
| 34065 | /* VTBL4 */ |
| 34066 | DPR, VecListFourD, DPR, i32imm, i32imm, |
| 34067 | /* VTBL4Pseudo */ |
| 34068 | DPR, QQPR, DPR, i32imm, i32imm, |
| 34069 | /* VTBX1 */ |
| 34070 | DPR, DPR, VecListOneD, DPR, i32imm, i32imm, |
| 34071 | /* VTBX2 */ |
| 34072 | DPR, DPR, VecListDPair, DPR, i32imm, i32imm, |
| 34073 | /* VTBX3 */ |
| 34074 | DPR, DPR, VecListThreeD, DPR, i32imm, i32imm, |
| 34075 | /* VTBX3Pseudo */ |
| 34076 | DPR, DPR, QQPR, DPR, i32imm, i32imm, |
| 34077 | /* VTBX4 */ |
| 34078 | DPR, DPR, VecListFourD, DPR, i32imm, i32imm, |
| 34079 | /* VTBX4Pseudo */ |
| 34080 | DPR, DPR, QQPR, DPR, i32imm, i32imm, |
| 34081 | /* VTOSHD */ |
| 34082 | DPR, DPR, fbits16, i32imm, i32imm, |
| 34083 | /* VTOSHH */ |
| 34084 | SPR, SPR, fbits16, i32imm, i32imm, |
| 34085 | /* VTOSHS */ |
| 34086 | SPR, SPR, fbits16, i32imm, i32imm, |
| 34087 | /* VTOSIRD */ |
| 34088 | SPR, DPR, i32imm, i32imm, |
| 34089 | /* VTOSIRH */ |
| 34090 | SPR, SPR, i32imm, i32imm, |
| 34091 | /* VTOSIRS */ |
| 34092 | SPR, SPR, i32imm, i32imm, |
| 34093 | /* VTOSIZD */ |
| 34094 | SPR, DPR, i32imm, i32imm, |
| 34095 | /* VTOSIZH */ |
| 34096 | SPR, HPR, i32imm, i32imm, |
| 34097 | /* VTOSIZS */ |
| 34098 | SPR, SPR, i32imm, i32imm, |
| 34099 | /* VTOSLD */ |
| 34100 | DPR, DPR, fbits32, i32imm, i32imm, |
| 34101 | /* VTOSLH */ |
| 34102 | SPR, SPR, fbits32, i32imm, i32imm, |
| 34103 | /* VTOSLS */ |
| 34104 | SPR, SPR, fbits32, i32imm, i32imm, |
| 34105 | /* VTOUHD */ |
| 34106 | DPR, DPR, fbits16, i32imm, i32imm, |
| 34107 | /* VTOUHH */ |
| 34108 | SPR, SPR, fbits16, i32imm, i32imm, |
| 34109 | /* VTOUHS */ |
| 34110 | SPR, SPR, fbits16, i32imm, i32imm, |
| 34111 | /* VTOUIRD */ |
| 34112 | SPR, DPR, i32imm, i32imm, |
| 34113 | /* VTOUIRH */ |
| 34114 | SPR, SPR, i32imm, i32imm, |
| 34115 | /* VTOUIRS */ |
| 34116 | SPR, SPR, i32imm, i32imm, |
| 34117 | /* VTOUIZD */ |
| 34118 | SPR, DPR, i32imm, i32imm, |
| 34119 | /* VTOUIZH */ |
| 34120 | SPR, HPR, i32imm, i32imm, |
| 34121 | /* VTOUIZS */ |
| 34122 | SPR, SPR, i32imm, i32imm, |
| 34123 | /* VTOULD */ |
| 34124 | DPR, DPR, fbits32, i32imm, i32imm, |
| 34125 | /* VTOULH */ |
| 34126 | SPR, SPR, fbits32, i32imm, i32imm, |
| 34127 | /* VTOULS */ |
| 34128 | SPR, SPR, fbits32, i32imm, i32imm, |
| 34129 | /* VTRNd16 */ |
| 34130 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 34131 | /* VTRNd32 */ |
| 34132 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 34133 | /* VTRNd8 */ |
| 34134 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 34135 | /* VTRNq16 */ |
| 34136 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 34137 | /* VTRNq32 */ |
| 34138 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 34139 | /* VTRNq8 */ |
| 34140 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 34141 | /* VTSTv16i8 */ |
| 34142 | QPR, QPR, QPR, i32imm, i32imm, |
| 34143 | /* VTSTv2i32 */ |
| 34144 | DPR, DPR, DPR, i32imm, i32imm, |
| 34145 | /* VTSTv4i16 */ |
| 34146 | DPR, DPR, DPR, i32imm, i32imm, |
| 34147 | /* VTSTv4i32 */ |
| 34148 | QPR, QPR, QPR, i32imm, i32imm, |
| 34149 | /* VTSTv8i16 */ |
| 34150 | QPR, QPR, QPR, i32imm, i32imm, |
| 34151 | /* VTSTv8i8 */ |
| 34152 | DPR, DPR, DPR, i32imm, i32imm, |
| 34153 | /* VUDOTD */ |
| 34154 | DPR, DPR, DPR, DPR, |
| 34155 | /* VUDOTDI */ |
| 34156 | DPR, DPR, DPR, DPR_VFP2, i32imm, |
| 34157 | /* VUDOTQ */ |
| 34158 | QPR, QPR, QPR, QPR, |
| 34159 | /* VUDOTQI */ |
| 34160 | QPR, QPR, QPR, DPR_VFP2, i32imm, |
| 34161 | /* VUHTOD */ |
| 34162 | DPR, DPR, fbits16, i32imm, i32imm, |
| 34163 | /* VUHTOH */ |
| 34164 | SPR, SPR, fbits16, i32imm, i32imm, |
| 34165 | /* VUHTOS */ |
| 34166 | SPR, SPR, fbits16, i32imm, i32imm, |
| 34167 | /* VUITOD */ |
| 34168 | DPR, SPR, i32imm, i32imm, |
| 34169 | /* VUITOH */ |
| 34170 | HPR, SPR, i32imm, i32imm, |
| 34171 | /* VUITOS */ |
| 34172 | SPR, SPR, i32imm, i32imm, |
| 34173 | /* VULTOD */ |
| 34174 | DPR, DPR, fbits32, i32imm, i32imm, |
| 34175 | /* VULTOH */ |
| 34176 | SPR, SPR, fbits32, i32imm, i32imm, |
| 34177 | /* VULTOS */ |
| 34178 | SPR, SPR, fbits32, i32imm, i32imm, |
| 34179 | /* VUMMLA */ |
| 34180 | QPR, QPR, QPR, QPR, |
| 34181 | /* VUSDOTD */ |
| 34182 | DPR, DPR, DPR, DPR, |
| 34183 | /* VUSDOTDI */ |
| 34184 | DPR, DPR, DPR, DPR_VFP2, i32imm, |
| 34185 | /* VUSDOTQ */ |
| 34186 | QPR, QPR, QPR, QPR, |
| 34187 | /* VUSDOTQI */ |
| 34188 | QPR, QPR, QPR, DPR_VFP2, i32imm, |
| 34189 | /* VUSMMLA */ |
| 34190 | QPR, QPR, QPR, QPR, |
| 34191 | /* VUZPd16 */ |
| 34192 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 34193 | /* VUZPd8 */ |
| 34194 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 34195 | /* VUZPq16 */ |
| 34196 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 34197 | /* VUZPq32 */ |
| 34198 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 34199 | /* VUZPq8 */ |
| 34200 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 34201 | /* VZIPd16 */ |
| 34202 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 34203 | /* VZIPd8 */ |
| 34204 | DPR, DPR, DPR, DPR, i32imm, i32imm, |
| 34205 | /* VZIPq16 */ |
| 34206 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 34207 | /* VZIPq32 */ |
| 34208 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 34209 | /* VZIPq8 */ |
| 34210 | QPR, QPR, QPR, QPR, i32imm, i32imm, |
| 34211 | /* sysLDMDA */ |
| 34212 | GPR, i32imm, i32imm, reglist, |
| 34213 | /* sysLDMDA_UPD */ |
| 34214 | GPR, GPR, i32imm, i32imm, reglist, |
| 34215 | /* sysLDMDB */ |
| 34216 | GPR, i32imm, i32imm, reglist, |
| 34217 | /* sysLDMDB_UPD */ |
| 34218 | GPR, GPR, i32imm, i32imm, reglist, |
| 34219 | /* sysLDMIA */ |
| 34220 | GPR, i32imm, i32imm, reglist, |
| 34221 | /* sysLDMIA_UPD */ |
| 34222 | GPR, GPR, i32imm, i32imm, reglist, |
| 34223 | /* sysLDMIB */ |
| 34224 | GPR, i32imm, i32imm, reglist, |
| 34225 | /* sysLDMIB_UPD */ |
| 34226 | GPR, GPR, i32imm, i32imm, reglist, |
| 34227 | /* sysSTMDA */ |
| 34228 | GPR, i32imm, i32imm, reglist, |
| 34229 | /* sysSTMDA_UPD */ |
| 34230 | GPR, GPR, i32imm, i32imm, reglist, |
| 34231 | /* sysSTMDB */ |
| 34232 | GPR, i32imm, i32imm, reglist, |
| 34233 | /* sysSTMDB_UPD */ |
| 34234 | GPR, GPR, i32imm, i32imm, reglist, |
| 34235 | /* sysSTMIA */ |
| 34236 | GPR, i32imm, i32imm, reglist, |
| 34237 | /* sysSTMIA_UPD */ |
| 34238 | GPR, GPR, i32imm, i32imm, reglist, |
| 34239 | /* sysSTMIB */ |
| 34240 | GPR, i32imm, i32imm, reglist, |
| 34241 | /* sysSTMIB_UPD */ |
| 34242 | GPR, GPR, i32imm, i32imm, reglist, |
| 34243 | /* t2ADCri */ |
| 34244 | rGPR, rGPR, t2_so_imm, i32imm, i32imm, CCR, |
| 34245 | /* t2ADCrr */ |
| 34246 | rGPR, rGPR, rGPR, i32imm, i32imm, CCR, |
| 34247 | /* t2ADCrs */ |
| 34248 | rGPR, rGPR, rGPR, i32imm, i32imm, i32imm, CCR, |
| 34249 | /* t2ADDri */ |
| 34250 | rGPR, GPRnopc, t2_so_imm, i32imm, i32imm, CCR, |
| 34251 | /* t2ADDri12 */ |
| 34252 | rGPR, GPR, imm0_4095, i32imm, i32imm, |
| 34253 | /* t2ADDrr */ |
| 34254 | GPRnopc, GPRnopc, rGPR, i32imm, i32imm, CCR, |
| 34255 | /* t2ADDrs */ |
| 34256 | GPRnopc, GPRnopc, rGPR, i32imm, i32imm, i32imm, CCR, |
| 34257 | /* t2ADDspImm */ |
| 34258 | GPRsp, GPRsp, t2_so_imm, i32imm, i32imm, CCR, |
| 34259 | /* t2ADDspImm12 */ |
| 34260 | GPRsp, GPRsp, imm0_4095, i32imm, i32imm, |
| 34261 | /* t2ADR */ |
| 34262 | rGPR, t2adrlabel, i32imm, i32imm, |
| 34263 | /* t2ANDri */ |
| 34264 | rGPR, rGPR, t2_so_imm, i32imm, i32imm, CCR, |
| 34265 | /* t2ANDrr */ |
| 34266 | rGPR, rGPR, rGPR, i32imm, i32imm, CCR, |
| 34267 | /* t2ANDrs */ |
| 34268 | rGPR, rGPR, rGPR, i32imm, i32imm, i32imm, CCR, |
| 34269 | /* t2ASRri */ |
| 34270 | rGPR, rGPR, imm_sr, i32imm, i32imm, CCR, |
| 34271 | /* t2ASRrr */ |
| 34272 | rGPR, rGPR, rGPR, i32imm, i32imm, CCR, |
| 34273 | /* t2AUT */ |
| 34274 | /* t2AUTG */ |
| 34275 | i32imm, i32imm, GPRnosp, GPRnopc, GPRnopc, |
| 34276 | /* t2B */ |
| 34277 | thumb_br_target, i32imm, i32imm, |
| 34278 | /* t2BFC */ |
| 34279 | rGPR, rGPR, bf_inv_mask_imm, i32imm, i32imm, |
| 34280 | /* t2BFI */ |
| 34281 | rGPR, rGPR, rGPR, bf_inv_mask_imm, i32imm, i32imm, |
| 34282 | /* t2BFLi */ |
| 34283 | bflabel_u4, bflabel_s18, i32imm, i32imm, |
| 34284 | /* t2BFLr */ |
| 34285 | bflabel_u4, rGPR, i32imm, i32imm, |
| 34286 | /* t2BFi */ |
| 34287 | bflabel_u4, bflabel_s16, i32imm, i32imm, |
| 34288 | /* t2BFic */ |
| 34289 | bflabel_u4, bflabel_s12, bfafter_target, pred_noal, |
| 34290 | /* t2BFr */ |
| 34291 | bflabel_u4, rGPR, i32imm, i32imm, |
| 34292 | /* t2BICri */ |
| 34293 | rGPR, rGPR, t2_so_imm, i32imm, i32imm, CCR, |
| 34294 | /* t2BICrr */ |
| 34295 | rGPR, rGPR, rGPR, i32imm, i32imm, CCR, |
| 34296 | /* t2BICrs */ |
| 34297 | rGPR, rGPR, rGPR, i32imm, i32imm, i32imm, CCR, |
| 34298 | /* t2BTI */ |
| 34299 | /* t2BXAUT */ |
| 34300 | i32imm, i32imm, GPRnosp, rGPR, GPRnopc, |
| 34301 | /* t2BXJ */ |
| 34302 | GPRnopc, i32imm, i32imm, |
| 34303 | /* t2Bcc */ |
| 34304 | brtarget, i32imm, i32imm, |
| 34305 | /* t2CDP */ |
| 34306 | p_imm, imm0_15, c_imm, c_imm, c_imm, imm0_7, i32imm, i32imm, |
| 34307 | /* t2CDP2 */ |
| 34308 | p_imm, imm0_15, c_imm, c_imm, c_imm, imm0_7, i32imm, i32imm, |
| 34309 | /* t2CLREX */ |
| 34310 | i32imm, i32imm, |
| 34311 | /* t2CLRM */ |
| 34312 | i32imm, i32imm, reglist_with_apsr, |
| 34313 | /* t2CLZ */ |
| 34314 | rGPR, rGPR, i32imm, i32imm, |
| 34315 | /* t2CMNri */ |
| 34316 | GPRnopc, t2_so_imm, i32imm, i32imm, |
| 34317 | /* t2CMNzrr */ |
| 34318 | GPRnopc, rGPR, i32imm, i32imm, |
| 34319 | /* t2CMNzrs */ |
| 34320 | GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 34321 | /* t2CMPri */ |
| 34322 | GPRnopc, t2_so_imm, i32imm, i32imm, |
| 34323 | /* t2CMPrr */ |
| 34324 | GPRnopc, rGPR, i32imm, i32imm, |
| 34325 | /* t2CMPrs */ |
| 34326 | GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 34327 | /* t2CPS1p */ |
| 34328 | imm0_31, |
| 34329 | /* t2CPS2p */ |
| 34330 | imod_op, iflags_op, |
| 34331 | /* t2CPS3p */ |
| 34332 | imod_op, iflags_op, i32imm, |
| 34333 | /* t2CRC32B */ |
| 34334 | rGPR, rGPR, rGPR, |
| 34335 | /* t2CRC32CB */ |
| 34336 | rGPR, rGPR, rGPR, |
| 34337 | /* t2CRC32CH */ |
| 34338 | rGPR, rGPR, rGPR, |
| 34339 | /* t2CRC32CW */ |
| 34340 | rGPR, rGPR, rGPR, |
| 34341 | /* t2CRC32H */ |
| 34342 | rGPR, rGPR, rGPR, |
| 34343 | /* t2CRC32W */ |
| 34344 | rGPR, rGPR, rGPR, |
| 34345 | /* t2CSEL */ |
| 34346 | rGPR, GPRwithZRnosp, GPRwithZRnosp, pred_noal, |
| 34347 | /* t2CSINC */ |
| 34348 | rGPR, GPRwithZRnosp, GPRwithZRnosp, pred_noal, |
| 34349 | /* t2CSINV */ |
| 34350 | rGPR, GPRwithZRnosp, GPRwithZRnosp, pred_noal, |
| 34351 | /* t2CSNEG */ |
| 34352 | rGPR, GPRwithZRnosp, GPRwithZRnosp, pred_noal, |
| 34353 | /* t2DBG */ |
| 34354 | imm0_15, i32imm, i32imm, |
| 34355 | /* t2DCPS1 */ |
| 34356 | i32imm, i32imm, |
| 34357 | /* t2DCPS2 */ |
| 34358 | i32imm, i32imm, |
| 34359 | /* t2DCPS3 */ |
| 34360 | i32imm, i32imm, |
| 34361 | /* t2DLS */ |
| 34362 | GPRlr, rGPR, |
| 34363 | /* t2DMB */ |
| 34364 | memb_opt, i32imm, i32imm, |
| 34365 | /* t2DSB */ |
| 34366 | memb_opt, i32imm, i32imm, |
| 34367 | /* t2EORri */ |
| 34368 | rGPR, rGPR, t2_so_imm, i32imm, i32imm, CCR, |
| 34369 | /* t2EORrr */ |
| 34370 | rGPR, rGPR, rGPR, i32imm, i32imm, CCR, |
| 34371 | /* t2EORrs */ |
| 34372 | rGPR, rGPR, rGPR, i32imm, i32imm, i32imm, CCR, |
| 34373 | /* t2HINT */ |
| 34374 | imm0_239, i32imm, i32imm, |
| 34375 | /* t2HVC */ |
| 34376 | imm0_65535, |
| 34377 | /* t2ISB */ |
| 34378 | instsyncb_opt, i32imm, i32imm, |
| 34379 | /* t2IT */ |
| 34380 | it_pred, it_mask, |
| 34381 | /* t2Int_eh_sjlj_setjmp */ |
| 34382 | tGPR, tGPR, |
| 34383 | /* t2Int_eh_sjlj_setjmp_nofp */ |
| 34384 | tGPR, tGPR, |
| 34385 | /* t2LDA */ |
| 34386 | rGPR, GPR, i32imm, i32imm, |
| 34387 | /* t2LDAB */ |
| 34388 | rGPR, GPR, i32imm, i32imm, |
| 34389 | /* t2LDAEX */ |
| 34390 | rGPR, GPR, i32imm, i32imm, |
| 34391 | /* t2LDAEXB */ |
| 34392 | rGPR, GPR, i32imm, i32imm, |
| 34393 | /* t2LDAEXD */ |
| 34394 | rGPR, rGPR, GPR, i32imm, i32imm, |
| 34395 | /* t2LDAEXH */ |
| 34396 | rGPR, GPR, i32imm, i32imm, |
| 34397 | /* t2LDAH */ |
| 34398 | rGPR, GPR, i32imm, i32imm, |
| 34399 | /* t2LDC2L_OFFSET */ |
| 34400 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34401 | /* t2LDC2L_OPTION */ |
| 34402 | p_imm, c_imm, GPR, coproc_option_imm, i32imm, i32imm, |
| 34403 | /* t2LDC2L_POST */ |
| 34404 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34405 | /* t2LDC2L_PRE */ |
| 34406 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34407 | /* t2LDC2_OFFSET */ |
| 34408 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34409 | /* t2LDC2_OPTION */ |
| 34410 | p_imm, c_imm, GPR, coproc_option_imm, i32imm, i32imm, |
| 34411 | /* t2LDC2_POST */ |
| 34412 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34413 | /* t2LDC2_PRE */ |
| 34414 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34415 | /* t2LDCL_OFFSET */ |
| 34416 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34417 | /* t2LDCL_OPTION */ |
| 34418 | p_imm, c_imm, GPR, coproc_option_imm, i32imm, i32imm, |
| 34419 | /* t2LDCL_POST */ |
| 34420 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34421 | /* t2LDCL_PRE */ |
| 34422 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34423 | /* t2LDC_OFFSET */ |
| 34424 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34425 | /* t2LDC_OPTION */ |
| 34426 | p_imm, c_imm, GPR, coproc_option_imm, i32imm, i32imm, |
| 34427 | /* t2LDC_POST */ |
| 34428 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34429 | /* t2LDC_PRE */ |
| 34430 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34431 | /* t2LDMDB */ |
| 34432 | GPR, i32imm, i32imm, reglist, |
| 34433 | /* t2LDMDB_UPD */ |
| 34434 | GPR, GPR, i32imm, i32imm, reglist, |
| 34435 | /* t2LDMIA */ |
| 34436 | GPR, i32imm, i32imm, reglist, |
| 34437 | /* t2LDMIA_UPD */ |
| 34438 | GPR, GPR, i32imm, i32imm, reglist, |
| 34439 | /* t2LDRBT */ |
| 34440 | rGPR, GPR, i32imm, i32imm, i32imm, |
| 34441 | /* t2LDRB_POST */ |
| 34442 | GPR, GPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 34443 | /* t2LDRB_PRE */ |
| 34444 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 34445 | /* t2LDRBi12 */ |
| 34446 | GPRnopc, GPR, i32imm, i32imm, i32imm, |
| 34447 | /* t2LDRBi8 */ |
| 34448 | GPRnopc, GPR, i32imm, i32imm, i32imm, |
| 34449 | /* t2LDRBpci */ |
| 34450 | GPRnopc, t2ldrlabel, i32imm, i32imm, |
| 34451 | /* t2LDRBs */ |
| 34452 | GPRnopc, GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 34453 | /* t2LDRD_POST */ |
| 34454 | rGPR, rGPR, GPR, GPR, t2am_imm8s4_offset, i32imm, i32imm, |
| 34455 | /* t2LDRD_PRE */ |
| 34456 | rGPR, rGPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 34457 | /* t2LDRDi8 */ |
| 34458 | rGPR, rGPR, GPR, i32imm, i32imm, i32imm, |
| 34459 | /* t2LDREX */ |
| 34460 | rGPR, GPRnopc, i32imm, i32imm, i32imm, |
| 34461 | /* t2LDREXB */ |
| 34462 | rGPR, GPR, i32imm, i32imm, |
| 34463 | /* t2LDREXD */ |
| 34464 | rGPR, rGPR, GPR, i32imm, i32imm, |
| 34465 | /* t2LDREXH */ |
| 34466 | rGPR, GPR, i32imm, i32imm, |
| 34467 | /* t2LDRHT */ |
| 34468 | rGPR, GPR, i32imm, i32imm, i32imm, |
| 34469 | /* t2LDRH_POST */ |
| 34470 | GPR, GPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 34471 | /* t2LDRH_PRE */ |
| 34472 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 34473 | /* t2LDRHi12 */ |
| 34474 | GPRnopc, GPR, i32imm, i32imm, i32imm, |
| 34475 | /* t2LDRHi8 */ |
| 34476 | GPRnopc, GPR, i32imm, i32imm, i32imm, |
| 34477 | /* t2LDRHpci */ |
| 34478 | GPRnopc, t2ldrlabel, i32imm, i32imm, |
| 34479 | /* t2LDRHs */ |
| 34480 | GPRnopc, GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 34481 | /* t2LDRSBT */ |
| 34482 | rGPR, GPR, i32imm, i32imm, i32imm, |
| 34483 | /* t2LDRSB_POST */ |
| 34484 | GPR, GPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 34485 | /* t2LDRSB_PRE */ |
| 34486 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 34487 | /* t2LDRSBi12 */ |
| 34488 | GPRnopc, GPR, i32imm, i32imm, i32imm, |
| 34489 | /* t2LDRSBi8 */ |
| 34490 | GPRnopc, GPR, i32imm, i32imm, i32imm, |
| 34491 | /* t2LDRSBpci */ |
| 34492 | GPRnopc, t2ldrlabel, i32imm, i32imm, |
| 34493 | /* t2LDRSBs */ |
| 34494 | GPRnopc, GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 34495 | /* t2LDRSHT */ |
| 34496 | rGPR, GPR, i32imm, i32imm, i32imm, |
| 34497 | /* t2LDRSH_POST */ |
| 34498 | GPR, GPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 34499 | /* t2LDRSH_PRE */ |
| 34500 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 34501 | /* t2LDRSHi12 */ |
| 34502 | GPRnopc, GPR, i32imm, i32imm, i32imm, |
| 34503 | /* t2LDRSHi8 */ |
| 34504 | GPRnopc, GPR, i32imm, i32imm, i32imm, |
| 34505 | /* t2LDRSHpci */ |
| 34506 | GPRnopc, t2ldrlabel, i32imm, i32imm, |
| 34507 | /* t2LDRSHs */ |
| 34508 | GPRnopc, GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 34509 | /* t2LDRT */ |
| 34510 | rGPR, GPR, i32imm, i32imm, i32imm, |
| 34511 | /* t2LDR_POST */ |
| 34512 | GPR, GPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 34513 | /* t2LDR_PRE */ |
| 34514 | GPR, GPR, GPR, i32imm, i32imm, i32imm, |
| 34515 | /* t2LDRi12 */ |
| 34516 | GPR, GPR, i32imm, i32imm, i32imm, |
| 34517 | /* t2LDRi8 */ |
| 34518 | GPR, GPR, i32imm, i32imm, i32imm, |
| 34519 | /* t2LDRpci */ |
| 34520 | GPR, t2ldrlabel, i32imm, i32imm, |
| 34521 | /* t2LDRs */ |
| 34522 | GPR, GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 34523 | /* t2LE */ |
| 34524 | lelabel_u11, |
| 34525 | /* t2LEUpdate */ |
| 34526 | GPRlr, GPRlr, lelabel_u11, |
| 34527 | /* t2LSLri */ |
| 34528 | rGPR, rGPR, imm1_31, i32imm, i32imm, CCR, |
| 34529 | /* t2LSLrr */ |
| 34530 | rGPR, rGPR, rGPR, i32imm, i32imm, CCR, |
| 34531 | /* t2LSRri */ |
| 34532 | rGPR, rGPR, imm_sr, i32imm, i32imm, CCR, |
| 34533 | /* t2LSRrr */ |
| 34534 | rGPR, rGPR, rGPR, i32imm, i32imm, CCR, |
| 34535 | /* t2MCR */ |
| 34536 | p_imm, imm0_7, GPR, c_imm, c_imm, imm0_7, i32imm, i32imm, |
| 34537 | /* t2MCR2 */ |
| 34538 | p_imm, imm0_7, GPR, c_imm, c_imm, imm0_7, i32imm, i32imm, |
| 34539 | /* t2MCRR */ |
| 34540 | p_imm, imm0_15, GPR, GPR, c_imm, i32imm, i32imm, |
| 34541 | /* t2MCRR2 */ |
| 34542 | p_imm, imm0_15, GPR, GPR, c_imm, i32imm, i32imm, |
| 34543 | /* t2MLA */ |
| 34544 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34545 | /* t2MLS */ |
| 34546 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34547 | /* t2MOVTi16 */ |
| 34548 | rGPR, rGPR, imm0_65535_expr, i32imm, i32imm, |
| 34549 | /* t2MOVi */ |
| 34550 | rGPR, t2_so_imm, i32imm, i32imm, CCR, |
| 34551 | /* t2MOVi16 */ |
| 34552 | rGPR, imm0_65535_expr, i32imm, i32imm, |
| 34553 | /* t2MOVr */ |
| 34554 | GPRnopc, GPRnopc, i32imm, i32imm, CCR, |
| 34555 | /* t2MOVsra_glue */ |
| 34556 | rGPR, rGPR, i32imm, i32imm, |
| 34557 | /* t2MOVsrl_glue */ |
| 34558 | rGPR, rGPR, i32imm, i32imm, |
| 34559 | /* t2MRC */ |
| 34560 | GPRwithAPSR, p_imm, imm0_7, c_imm, c_imm, imm0_7, i32imm, i32imm, |
| 34561 | /* t2MRC2 */ |
| 34562 | GPRwithAPSR, p_imm, imm0_7, c_imm, c_imm, imm0_7, i32imm, i32imm, |
| 34563 | /* t2MRRC */ |
| 34564 | GPR, GPR, p_imm, imm0_15, c_imm, i32imm, i32imm, |
| 34565 | /* t2MRRC2 */ |
| 34566 | GPR, GPR, p_imm, imm0_15, c_imm, i32imm, i32imm, |
| 34567 | /* t2MRS_AR */ |
| 34568 | GPR, i32imm, i32imm, |
| 34569 | /* t2MRS_M */ |
| 34570 | rGPR, msr_mask, i32imm, i32imm, |
| 34571 | /* t2MRSbanked */ |
| 34572 | rGPR, banked_reg, i32imm, i32imm, |
| 34573 | /* t2MRSsys_AR */ |
| 34574 | GPR, i32imm, i32imm, |
| 34575 | /* t2MSR_AR */ |
| 34576 | msr_mask, rGPR, i32imm, i32imm, |
| 34577 | /* t2MSR_M */ |
| 34578 | msr_mask, rGPR, i32imm, i32imm, |
| 34579 | /* t2MSRbanked */ |
| 34580 | banked_reg, rGPR, i32imm, i32imm, |
| 34581 | /* t2MUL */ |
| 34582 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34583 | /* t2MVNi */ |
| 34584 | rGPR, t2_so_imm, i32imm, i32imm, CCR, |
| 34585 | /* t2MVNr */ |
| 34586 | rGPR, rGPR, i32imm, i32imm, CCR, |
| 34587 | /* t2MVNs */ |
| 34588 | rGPR, rGPR, i32imm, i32imm, i32imm, CCR, |
| 34589 | /* t2ORNri */ |
| 34590 | rGPR, rGPR, t2_so_imm, i32imm, i32imm, CCR, |
| 34591 | /* t2ORNrr */ |
| 34592 | rGPR, rGPR, rGPR, i32imm, i32imm, CCR, |
| 34593 | /* t2ORNrs */ |
| 34594 | rGPR, rGPR, rGPR, i32imm, i32imm, i32imm, CCR, |
| 34595 | /* t2ORRri */ |
| 34596 | rGPR, rGPR, t2_so_imm, i32imm, i32imm, CCR, |
| 34597 | /* t2ORRrr */ |
| 34598 | rGPR, rGPR, rGPR, i32imm, i32imm, CCR, |
| 34599 | /* t2ORRrs */ |
| 34600 | rGPR, rGPR, rGPR, i32imm, i32imm, i32imm, CCR, |
| 34601 | /* t2PAC */ |
| 34602 | /* t2PACBTI */ |
| 34603 | /* t2PACG */ |
| 34604 | rGPR, i32imm, i32imm, GPRnopc, GPRnopc, |
| 34605 | /* t2PKHBT */ |
| 34606 | rGPR, rGPR, rGPR, pkh_lsl_amt, i32imm, i32imm, |
| 34607 | /* t2PKHTB */ |
| 34608 | rGPR, rGPR, rGPR, pkh_asr_amt, i32imm, i32imm, |
| 34609 | /* t2PLDWi12 */ |
| 34610 | GPR, i32imm, i32imm, i32imm, |
| 34611 | /* t2PLDWi8 */ |
| 34612 | GPR, i32imm, i32imm, i32imm, |
| 34613 | /* t2PLDWs */ |
| 34614 | GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 34615 | /* t2PLDi12 */ |
| 34616 | GPR, i32imm, i32imm, i32imm, |
| 34617 | /* t2PLDi8 */ |
| 34618 | GPR, i32imm, i32imm, i32imm, |
| 34619 | /* t2PLDpci */ |
| 34620 | t2ldrlabel, i32imm, i32imm, |
| 34621 | /* t2PLDs */ |
| 34622 | GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 34623 | /* t2PLIi12 */ |
| 34624 | GPR, i32imm, i32imm, i32imm, |
| 34625 | /* t2PLIi8 */ |
| 34626 | GPR, i32imm, i32imm, i32imm, |
| 34627 | /* t2PLIpci */ |
| 34628 | t2ldrlabel, i32imm, i32imm, |
| 34629 | /* t2PLIs */ |
| 34630 | GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 34631 | /* t2QADD */ |
| 34632 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34633 | /* t2QADD16 */ |
| 34634 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34635 | /* t2QADD8 */ |
| 34636 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34637 | /* t2QASX */ |
| 34638 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34639 | /* t2QDADD */ |
| 34640 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34641 | /* t2QDSUB */ |
| 34642 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34643 | /* t2QSAX */ |
| 34644 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34645 | /* t2QSUB */ |
| 34646 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34647 | /* t2QSUB16 */ |
| 34648 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34649 | /* t2QSUB8 */ |
| 34650 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34651 | /* t2RBIT */ |
| 34652 | rGPR, rGPR, i32imm, i32imm, |
| 34653 | /* t2REV */ |
| 34654 | rGPR, rGPR, i32imm, i32imm, |
| 34655 | /* t2REV16 */ |
| 34656 | rGPR, rGPR, i32imm, i32imm, |
| 34657 | /* t2REVSH */ |
| 34658 | rGPR, rGPR, i32imm, i32imm, |
| 34659 | /* t2RFEDB */ |
| 34660 | GPR, i32imm, i32imm, |
| 34661 | /* t2RFEDBW */ |
| 34662 | GPR, i32imm, i32imm, |
| 34663 | /* t2RFEIA */ |
| 34664 | GPR, i32imm, i32imm, |
| 34665 | /* t2RFEIAW */ |
| 34666 | GPR, i32imm, i32imm, |
| 34667 | /* t2RORri */ |
| 34668 | rGPR, rGPR, imm1_31, i32imm, i32imm, CCR, |
| 34669 | /* t2RORrr */ |
| 34670 | rGPR, rGPR, rGPR, i32imm, i32imm, CCR, |
| 34671 | /* t2RRX */ |
| 34672 | rGPR, rGPR, i32imm, i32imm, CCR, |
| 34673 | /* t2RSBri */ |
| 34674 | rGPR, rGPR, t2_so_imm, i32imm, i32imm, CCR, |
| 34675 | /* t2RSBrr */ |
| 34676 | rGPR, rGPR, rGPR, i32imm, i32imm, CCR, |
| 34677 | /* t2RSBrs */ |
| 34678 | rGPR, rGPR, rGPR, i32imm, i32imm, i32imm, CCR, |
| 34679 | /* t2SADD16 */ |
| 34680 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34681 | /* t2SADD8 */ |
| 34682 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34683 | /* t2SASX */ |
| 34684 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34685 | /* t2SB */ |
| 34686 | /* t2SBCri */ |
| 34687 | rGPR, rGPR, t2_so_imm, i32imm, i32imm, CCR, |
| 34688 | /* t2SBCrr */ |
| 34689 | rGPR, rGPR, rGPR, i32imm, i32imm, CCR, |
| 34690 | /* t2SBCrs */ |
| 34691 | rGPR, rGPR, rGPR, i32imm, i32imm, i32imm, CCR, |
| 34692 | /* t2SBFX */ |
| 34693 | rGPR, rGPR, imm0_31, imm1_32, i32imm, i32imm, |
| 34694 | /* t2SDIV */ |
| 34695 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34696 | /* t2SEL */ |
| 34697 | GPR, GPR, GPR, i32imm, i32imm, |
| 34698 | /* t2SETPAN */ |
| 34699 | imm0_1, |
| 34700 | /* t2SG */ |
| 34701 | i32imm, i32imm, |
| 34702 | /* t2SHADD16 */ |
| 34703 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34704 | /* t2SHADD8 */ |
| 34705 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34706 | /* t2SHASX */ |
| 34707 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34708 | /* t2SHSAX */ |
| 34709 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34710 | /* t2SHSUB16 */ |
| 34711 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34712 | /* t2SHSUB8 */ |
| 34713 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34714 | /* t2SMC */ |
| 34715 | imm0_15, i32imm, i32imm, |
| 34716 | /* t2SMLABB */ |
| 34717 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34718 | /* t2SMLABT */ |
| 34719 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34720 | /* t2SMLAD */ |
| 34721 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34722 | /* t2SMLADX */ |
| 34723 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34724 | /* t2SMLAL */ |
| 34725 | rGPR, rGPR, rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34726 | /* t2SMLALBB */ |
| 34727 | rGPR, rGPR, rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34728 | /* t2SMLALBT */ |
| 34729 | rGPR, rGPR, rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34730 | /* t2SMLALD */ |
| 34731 | rGPR, rGPR, rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34732 | /* t2SMLALDX */ |
| 34733 | rGPR, rGPR, rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34734 | /* t2SMLALTB */ |
| 34735 | rGPR, rGPR, rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34736 | /* t2SMLALTT */ |
| 34737 | rGPR, rGPR, rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34738 | /* t2SMLATB */ |
| 34739 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34740 | /* t2SMLATT */ |
| 34741 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34742 | /* t2SMLAWB */ |
| 34743 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34744 | /* t2SMLAWT */ |
| 34745 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34746 | /* t2SMLSD */ |
| 34747 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34748 | /* t2SMLSDX */ |
| 34749 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34750 | /* t2SMLSLD */ |
| 34751 | rGPR, rGPR, rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34752 | /* t2SMLSLDX */ |
| 34753 | rGPR, rGPR, rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34754 | /* t2SMMLA */ |
| 34755 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34756 | /* t2SMMLAR */ |
| 34757 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34758 | /* t2SMMLS */ |
| 34759 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34760 | /* t2SMMLSR */ |
| 34761 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34762 | /* t2SMMUL */ |
| 34763 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34764 | /* t2SMMULR */ |
| 34765 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34766 | /* t2SMUAD */ |
| 34767 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34768 | /* t2SMUADX */ |
| 34769 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34770 | /* t2SMULBB */ |
| 34771 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34772 | /* t2SMULBT */ |
| 34773 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34774 | /* t2SMULL */ |
| 34775 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34776 | /* t2SMULTB */ |
| 34777 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34778 | /* t2SMULTT */ |
| 34779 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34780 | /* t2SMULWB */ |
| 34781 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34782 | /* t2SMULWT */ |
| 34783 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34784 | /* t2SMUSD */ |
| 34785 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34786 | /* t2SMUSDX */ |
| 34787 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34788 | /* t2SRSDB */ |
| 34789 | imm0_31, i32imm, i32imm, |
| 34790 | /* t2SRSDB_UPD */ |
| 34791 | imm0_31, i32imm, i32imm, |
| 34792 | /* t2SRSIA */ |
| 34793 | imm0_31, i32imm, i32imm, |
| 34794 | /* t2SRSIA_UPD */ |
| 34795 | imm0_31, i32imm, i32imm, |
| 34796 | /* t2SSAT */ |
| 34797 | rGPR, imm1_32, rGPR, t2_shift_imm, i32imm, i32imm, |
| 34798 | /* t2SSAT16 */ |
| 34799 | rGPR, imm1_16, rGPR, i32imm, i32imm, |
| 34800 | /* t2SSAX */ |
| 34801 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34802 | /* t2SSUB16 */ |
| 34803 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34804 | /* t2SSUB8 */ |
| 34805 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34806 | /* t2STC2L_OFFSET */ |
| 34807 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34808 | /* t2STC2L_OPTION */ |
| 34809 | p_imm, c_imm, GPR, coproc_option_imm, i32imm, i32imm, |
| 34810 | /* t2STC2L_POST */ |
| 34811 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34812 | /* t2STC2L_PRE */ |
| 34813 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34814 | /* t2STC2_OFFSET */ |
| 34815 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34816 | /* t2STC2_OPTION */ |
| 34817 | p_imm, c_imm, GPR, coproc_option_imm, i32imm, i32imm, |
| 34818 | /* t2STC2_POST */ |
| 34819 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34820 | /* t2STC2_PRE */ |
| 34821 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34822 | /* t2STCL_OFFSET */ |
| 34823 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34824 | /* t2STCL_OPTION */ |
| 34825 | p_imm, c_imm, GPR, coproc_option_imm, i32imm, i32imm, |
| 34826 | /* t2STCL_POST */ |
| 34827 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34828 | /* t2STCL_PRE */ |
| 34829 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34830 | /* t2STC_OFFSET */ |
| 34831 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34832 | /* t2STC_OPTION */ |
| 34833 | p_imm, c_imm, GPR, coproc_option_imm, i32imm, i32imm, |
| 34834 | /* t2STC_POST */ |
| 34835 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34836 | /* t2STC_PRE */ |
| 34837 | p_imm, c_imm, GPR, i32imm, i32imm, i32imm, |
| 34838 | /* t2STL */ |
| 34839 | rGPR, GPR, i32imm, i32imm, |
| 34840 | /* t2STLB */ |
| 34841 | rGPR, GPR, i32imm, i32imm, |
| 34842 | /* t2STLEX */ |
| 34843 | rGPR, rGPR, GPR, i32imm, i32imm, |
| 34844 | /* t2STLEXB */ |
| 34845 | rGPR, rGPR, GPR, i32imm, i32imm, |
| 34846 | /* t2STLEXD */ |
| 34847 | rGPR, rGPR, rGPR, GPR, i32imm, i32imm, |
| 34848 | /* t2STLEXH */ |
| 34849 | rGPR, rGPR, GPR, i32imm, i32imm, |
| 34850 | /* t2STLH */ |
| 34851 | rGPR, GPR, i32imm, i32imm, |
| 34852 | /* t2STMDB */ |
| 34853 | GPR, i32imm, i32imm, reglist, |
| 34854 | /* t2STMDB_UPD */ |
| 34855 | GPR, GPR, i32imm, i32imm, reglist, |
| 34856 | /* t2STMIA */ |
| 34857 | GPR, i32imm, i32imm, reglist, |
| 34858 | /* t2STMIA_UPD */ |
| 34859 | GPR, GPR, i32imm, i32imm, reglist, |
| 34860 | /* t2STRBT */ |
| 34861 | rGPR, GPR, i32imm, i32imm, i32imm, |
| 34862 | /* t2STRB_POST */ |
| 34863 | GPRnopc, rGPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 34864 | /* t2STRB_PRE */ |
| 34865 | GPRnopc, rGPR, GPR, i32imm, i32imm, i32imm, |
| 34866 | /* t2STRBi12 */ |
| 34867 | rGPR, GPR, i32imm, i32imm, i32imm, |
| 34868 | /* t2STRBi8 */ |
| 34869 | rGPR, GPR, i32imm, i32imm, i32imm, |
| 34870 | /* t2STRBs */ |
| 34871 | rGPR, GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 34872 | /* t2STRD_POST */ |
| 34873 | GPR, rGPR, rGPR, GPR, t2am_imm8s4_offset, i32imm, i32imm, |
| 34874 | /* t2STRD_PRE */ |
| 34875 | GPR, rGPR, rGPR, GPR, i32imm, i32imm, i32imm, |
| 34876 | /* t2STRDi8 */ |
| 34877 | rGPR, rGPR, GPR, i32imm, i32imm, i32imm, |
| 34878 | /* t2STREX */ |
| 34879 | rGPR, rGPR, GPRnopc, i32imm, i32imm, i32imm, |
| 34880 | /* t2STREXB */ |
| 34881 | rGPR, rGPR, GPR, i32imm, i32imm, |
| 34882 | /* t2STREXD */ |
| 34883 | rGPR, rGPR, rGPR, GPR, i32imm, i32imm, |
| 34884 | /* t2STREXH */ |
| 34885 | rGPR, rGPR, GPR, i32imm, i32imm, |
| 34886 | /* t2STRHT */ |
| 34887 | rGPR, GPR, i32imm, i32imm, i32imm, |
| 34888 | /* t2STRH_POST */ |
| 34889 | GPRnopc, rGPR, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 34890 | /* t2STRH_PRE */ |
| 34891 | GPRnopc, rGPR, GPR, i32imm, i32imm, i32imm, |
| 34892 | /* t2STRHi12 */ |
| 34893 | rGPR, GPR, i32imm, i32imm, i32imm, |
| 34894 | /* t2STRHi8 */ |
| 34895 | rGPR, GPR, i32imm, i32imm, i32imm, |
| 34896 | /* t2STRHs */ |
| 34897 | rGPR, GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 34898 | /* t2STRT */ |
| 34899 | rGPR, GPR, i32imm, i32imm, i32imm, |
| 34900 | /* t2STR_POST */ |
| 34901 | GPRnopc, GPRnopc, GPR, t2am_imm8_offset, i32imm, i32imm, |
| 34902 | /* t2STR_PRE */ |
| 34903 | GPRnopc, GPRnopc, GPR, i32imm, i32imm, i32imm, |
| 34904 | /* t2STRi12 */ |
| 34905 | GPR, GPR, i32imm, i32imm, i32imm, |
| 34906 | /* t2STRi8 */ |
| 34907 | GPR, GPR, i32imm, i32imm, i32imm, |
| 34908 | /* t2STRs */ |
| 34909 | GPR, GPRnopc, rGPR, i32imm, i32imm, i32imm, |
| 34910 | /* t2SUBS_PC_LR */ |
| 34911 | imm0_255, i32imm, i32imm, |
| 34912 | /* t2SUBri */ |
| 34913 | rGPR, GPRnopc, t2_so_imm, i32imm, i32imm, CCR, |
| 34914 | /* t2SUBri12 */ |
| 34915 | rGPR, GPR, imm0_4095, i32imm, i32imm, |
| 34916 | /* t2SUBrr */ |
| 34917 | GPRnopc, GPRnopc, rGPR, i32imm, i32imm, CCR, |
| 34918 | /* t2SUBrs */ |
| 34919 | GPRnopc, GPRnopc, rGPR, i32imm, i32imm, i32imm, CCR, |
| 34920 | /* t2SUBspImm */ |
| 34921 | GPRsp, GPRsp, t2_so_imm, i32imm, i32imm, CCR, |
| 34922 | /* t2SUBspImm12 */ |
| 34923 | GPRsp, GPRsp, imm0_4095, i32imm, i32imm, |
| 34924 | /* t2SXTAB */ |
| 34925 | rGPR, rGPR, rGPR, rot_imm, i32imm, i32imm, |
| 34926 | /* t2SXTAB16 */ |
| 34927 | rGPR, rGPR, rGPR, rot_imm, i32imm, i32imm, |
| 34928 | /* t2SXTAH */ |
| 34929 | rGPR, rGPR, rGPR, rot_imm, i32imm, i32imm, |
| 34930 | /* t2SXTB */ |
| 34931 | rGPR, rGPR, rot_imm, i32imm, i32imm, |
| 34932 | /* t2SXTB16 */ |
| 34933 | rGPR, rGPR, rot_imm, i32imm, i32imm, |
| 34934 | /* t2SXTH */ |
| 34935 | rGPR, rGPR, rot_imm, i32imm, i32imm, |
| 34936 | /* t2TBB */ |
| 34937 | GPR, rGPR, i32imm, i32imm, |
| 34938 | /* t2TBH */ |
| 34939 | GPR, rGPR, i32imm, i32imm, |
| 34940 | /* t2TEQri */ |
| 34941 | rGPR, t2_so_imm, i32imm, i32imm, |
| 34942 | /* t2TEQrr */ |
| 34943 | rGPR, rGPR, i32imm, i32imm, |
| 34944 | /* t2TEQrs */ |
| 34945 | rGPR, rGPR, i32imm, i32imm, i32imm, |
| 34946 | /* t2TSB */ |
| 34947 | tsb_opt, i32imm, i32imm, |
| 34948 | /* t2TSTri */ |
| 34949 | rGPR, t2_so_imm, i32imm, i32imm, |
| 34950 | /* t2TSTrr */ |
| 34951 | rGPR, rGPR, i32imm, i32imm, |
| 34952 | /* t2TSTrs */ |
| 34953 | rGPR, rGPR, i32imm, i32imm, i32imm, |
| 34954 | /* t2TT */ |
| 34955 | rGPR, GPRnopc, i32imm, i32imm, |
| 34956 | /* t2TTA */ |
| 34957 | rGPR, GPRnopc, i32imm, i32imm, |
| 34958 | /* t2TTAT */ |
| 34959 | rGPR, GPRnopc, i32imm, i32imm, |
| 34960 | /* t2TTT */ |
| 34961 | rGPR, GPRnopc, i32imm, i32imm, |
| 34962 | /* t2UADD16 */ |
| 34963 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34964 | /* t2UADD8 */ |
| 34965 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34966 | /* t2UASX */ |
| 34967 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34968 | /* t2UBFX */ |
| 34969 | rGPR, rGPR, imm0_31, imm1_32, i32imm, i32imm, |
| 34970 | /* t2UDF */ |
| 34971 | imm0_65535, |
| 34972 | /* t2UDIV */ |
| 34973 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34974 | /* t2UHADD16 */ |
| 34975 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34976 | /* t2UHADD8 */ |
| 34977 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34978 | /* t2UHASX */ |
| 34979 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34980 | /* t2UHSAX */ |
| 34981 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34982 | /* t2UHSUB16 */ |
| 34983 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34984 | /* t2UHSUB8 */ |
| 34985 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34986 | /* t2UMAAL */ |
| 34987 | rGPR, rGPR, rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34988 | /* t2UMLAL */ |
| 34989 | rGPR, rGPR, rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34990 | /* t2UMULL */ |
| 34991 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34992 | /* t2UQADD16 */ |
| 34993 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34994 | /* t2UQADD8 */ |
| 34995 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34996 | /* t2UQASX */ |
| 34997 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 34998 | /* t2UQSAX */ |
| 34999 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 35000 | /* t2UQSUB16 */ |
| 35001 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 35002 | /* t2UQSUB8 */ |
| 35003 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 35004 | /* t2USAD8 */ |
| 35005 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 35006 | /* t2USADA8 */ |
| 35007 | rGPR, rGPR, rGPR, rGPR, i32imm, i32imm, |
| 35008 | /* t2USAT */ |
| 35009 | rGPR, imm0_31, rGPR, t2_shift_imm, i32imm, i32imm, |
| 35010 | /* t2USAT16 */ |
| 35011 | rGPR, imm0_15, rGPR, i32imm, i32imm, |
| 35012 | /* t2USAX */ |
| 35013 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 35014 | /* t2USUB16 */ |
| 35015 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 35016 | /* t2USUB8 */ |
| 35017 | rGPR, rGPR, rGPR, i32imm, i32imm, |
| 35018 | /* t2UXTAB */ |
| 35019 | rGPR, rGPR, rGPR, rot_imm, i32imm, i32imm, |
| 35020 | /* t2UXTAB16 */ |
| 35021 | rGPR, rGPR, rGPR, rot_imm, i32imm, i32imm, |
| 35022 | /* t2UXTAH */ |
| 35023 | rGPR, rGPR, rGPR, rot_imm, i32imm, i32imm, |
| 35024 | /* t2UXTB */ |
| 35025 | rGPR, rGPR, rot_imm, i32imm, i32imm, |
| 35026 | /* t2UXTB16 */ |
| 35027 | rGPR, rGPR, rot_imm, i32imm, i32imm, |
| 35028 | /* t2UXTH */ |
| 35029 | rGPR, rGPR, rot_imm, i32imm, i32imm, |
| 35030 | /* t2WLS */ |
| 35031 | GPRlr, rGPR, wlslabel_u11, |
| 35032 | /* tADC */ |
| 35033 | tGPR, CCR, tGPR, tGPR, i32imm, i32imm, |
| 35034 | /* tADDhirr */ |
| 35035 | GPR, GPR, GPR, i32imm, i32imm, |
| 35036 | /* tADDi3 */ |
| 35037 | tGPR, CCR, tGPR, imm0_7, i32imm, i32imm, |
| 35038 | /* tADDi8 */ |
| 35039 | tGPR, CCR, tGPR, imm0_255_expr, i32imm, i32imm, |
| 35040 | /* tADDrSP */ |
| 35041 | GPR, GPRsp, GPR, i32imm, i32imm, |
| 35042 | /* tADDrSPi */ |
| 35043 | tGPR, GPRsp, t_imm0_1020s4, i32imm, i32imm, |
| 35044 | /* tADDrr */ |
| 35045 | tGPR, CCR, tGPR, tGPR, i32imm, i32imm, |
| 35046 | /* tADDspi */ |
| 35047 | GPRsp, GPRsp, t_imm0_508s4, i32imm, i32imm, |
| 35048 | /* tADDspr */ |
| 35049 | GPRsp, GPRsp, GPR, i32imm, i32imm, |
| 35050 | /* tADR */ |
| 35051 | tGPR, t_adrlabel, i32imm, i32imm, |
| 35052 | /* tAND */ |
| 35053 | tGPR, CCR, tGPR, tGPR, i32imm, i32imm, |
| 35054 | /* tASRri */ |
| 35055 | tGPR, CCR, tGPR, imm_sr, i32imm, i32imm, |
| 35056 | /* tASRrr */ |
| 35057 | tGPR, CCR, tGPR, tGPR, i32imm, i32imm, |
| 35058 | /* tB */ |
| 35059 | t_brtarget, i32imm, i32imm, |
| 35060 | /* tBIC */ |
| 35061 | tGPR, CCR, tGPR, tGPR, i32imm, i32imm, |
| 35062 | /* tBKPT */ |
| 35063 | imm0_255, |
| 35064 | /* tBL */ |
| 35065 | i32imm, i32imm, thumb_bl_target, |
| 35066 | /* tBLXNSr */ |
| 35067 | i32imm, i32imm, GPRnopc, |
| 35068 | /* tBLXi */ |
| 35069 | i32imm, i32imm, thumb_blx_target, |
| 35070 | /* tBLXr */ |
| 35071 | i32imm, i32imm, GPR, |
| 35072 | /* tBX */ |
| 35073 | GPR, i32imm, i32imm, |
| 35074 | /* tBXNS */ |
| 35075 | GPR, i32imm, i32imm, |
| 35076 | /* tBcc */ |
| 35077 | thumb_bcc_target, i32imm, i32imm, |
| 35078 | /* tCBNZ */ |
| 35079 | tGPR, thumb_cb_target, |
| 35080 | /* tCBZ */ |
| 35081 | tGPR, thumb_cb_target, |
| 35082 | /* tCMNz */ |
| 35083 | tGPR, tGPR, i32imm, i32imm, |
| 35084 | /* tCMPhir */ |
| 35085 | GPR, GPR, i32imm, i32imm, |
| 35086 | /* tCMPi8 */ |
| 35087 | tGPR, imm0_255, i32imm, i32imm, |
| 35088 | /* tCMPr */ |
| 35089 | tGPR, tGPR, i32imm, i32imm, |
| 35090 | /* tCPS */ |
| 35091 | imod_op, iflags_op, |
| 35092 | /* tEOR */ |
| 35093 | tGPR, CCR, tGPR, tGPR, i32imm, i32imm, |
| 35094 | /* tHINT */ |
| 35095 | imm0_15, i32imm, i32imm, |
| 35096 | /* tHLT */ |
| 35097 | imm0_63, |
| 35098 | /* tInt_WIN_eh_sjlj_longjmp */ |
| 35099 | GPR, GPR, |
| 35100 | /* tInt_eh_sjlj_longjmp */ |
| 35101 | tGPR, tGPR, |
| 35102 | /* tInt_eh_sjlj_setjmp */ |
| 35103 | tGPR, tGPR, |
| 35104 | /* tLDMIA */ |
| 35105 | tGPR, i32imm, i32imm, reglist, |
| 35106 | /* tLDRBi */ |
| 35107 | tGPR, tGPR, i32imm, i32imm, i32imm, |
| 35108 | /* tLDRBr */ |
| 35109 | tGPR, tGPR, tGPR, i32imm, i32imm, |
| 35110 | /* tLDRHi */ |
| 35111 | tGPR, tGPR, i32imm, i32imm, i32imm, |
| 35112 | /* tLDRHr */ |
| 35113 | tGPR, tGPR, tGPR, i32imm, i32imm, |
| 35114 | /* tLDRSB */ |
| 35115 | tGPR, tGPR, tGPR, i32imm, i32imm, |
| 35116 | /* tLDRSH */ |
| 35117 | tGPR, tGPR, tGPR, i32imm, i32imm, |
| 35118 | /* tLDRi */ |
| 35119 | tGPR, tGPR, i32imm, i32imm, i32imm, |
| 35120 | /* tLDRpci */ |
| 35121 | tGPR, t_addrmode_pc, i32imm, i32imm, |
| 35122 | /* tLDRr */ |
| 35123 | tGPR, tGPR, tGPR, i32imm, i32imm, |
| 35124 | /* tLDRspi */ |
| 35125 | tGPR, GPR, i32imm, i32imm, i32imm, |
| 35126 | /* tLSLri */ |
| 35127 | tGPR, CCR, tGPR, imm0_31, i32imm, i32imm, |
| 35128 | /* tLSLrr */ |
| 35129 | tGPR, CCR, tGPR, tGPR, i32imm, i32imm, |
| 35130 | /* tLSRri */ |
| 35131 | tGPR, CCR, tGPR, imm_sr, i32imm, i32imm, |
| 35132 | /* tLSRrr */ |
| 35133 | tGPR, CCR, tGPR, tGPR, i32imm, i32imm, |
| 35134 | /* tMOVSr */ |
| 35135 | tGPR, tGPR, |
| 35136 | /* tMOVi8 */ |
| 35137 | tGPR, CCR, imm0_255_expr, i32imm, i32imm, |
| 35138 | /* tMOVr */ |
| 35139 | GPR, GPR, i32imm, i32imm, |
| 35140 | /* tMUL */ |
| 35141 | tGPR, CCR, tGPR, tGPR, i32imm, i32imm, |
| 35142 | /* tMVN */ |
| 35143 | tGPR, CCR, tGPR, i32imm, i32imm, |
| 35144 | /* tORR */ |
| 35145 | tGPR, CCR, tGPR, tGPR, i32imm, i32imm, |
| 35146 | /* tPICADD */ |
| 35147 | GPR, GPR, pclabel, |
| 35148 | /* tPOP */ |
| 35149 | i32imm, i32imm, reglist, |
| 35150 | /* tPUSH */ |
| 35151 | i32imm, i32imm, reglist, |
| 35152 | /* tREV */ |
| 35153 | tGPR, tGPR, i32imm, i32imm, |
| 35154 | /* tREV16 */ |
| 35155 | tGPR, tGPR, i32imm, i32imm, |
| 35156 | /* tREVSH */ |
| 35157 | tGPR, tGPR, i32imm, i32imm, |
| 35158 | /* tROR */ |
| 35159 | tGPR, CCR, tGPR, tGPR, i32imm, i32imm, |
| 35160 | /* tRSB */ |
| 35161 | tGPR, CCR, tGPR, i32imm, i32imm, |
| 35162 | /* tSBC */ |
| 35163 | tGPR, CCR, tGPR, tGPR, i32imm, i32imm, |
| 35164 | /* tSETEND */ |
| 35165 | setend_op, |
| 35166 | /* tSTMIA_UPD */ |
| 35167 | tGPR, tGPR, i32imm, i32imm, reglist, |
| 35168 | /* tSTRBi */ |
| 35169 | tGPR, tGPR, i32imm, i32imm, i32imm, |
| 35170 | /* tSTRBr */ |
| 35171 | tGPR, tGPR, tGPR, i32imm, i32imm, |
| 35172 | /* tSTRHi */ |
| 35173 | tGPR, tGPR, i32imm, i32imm, i32imm, |
| 35174 | /* tSTRHr */ |
| 35175 | tGPR, tGPR, tGPR, i32imm, i32imm, |
| 35176 | /* tSTRi */ |
| 35177 | tGPR, tGPR, i32imm, i32imm, i32imm, |
| 35178 | /* tSTRr */ |
| 35179 | tGPR, tGPR, tGPR, i32imm, i32imm, |
| 35180 | /* tSTRspi */ |
| 35181 | tGPR, GPR, i32imm, i32imm, i32imm, |
| 35182 | /* tSUBi3 */ |
| 35183 | tGPR, CCR, tGPR, imm0_7, i32imm, i32imm, |
| 35184 | /* tSUBi8 */ |
| 35185 | tGPR, CCR, tGPR, imm0_255, i32imm, i32imm, |
| 35186 | /* tSUBrr */ |
| 35187 | tGPR, CCR, tGPR, tGPR, i32imm, i32imm, |
| 35188 | /* tSUBspi */ |
| 35189 | GPRsp, GPRsp, t_imm0_508s4, i32imm, i32imm, |
| 35190 | /* tSVC */ |
| 35191 | imm0_255, i32imm, i32imm, |
| 35192 | /* tSXTB */ |
| 35193 | tGPR, tGPR, i32imm, i32imm, |
| 35194 | /* tSXTH */ |
| 35195 | tGPR, tGPR, i32imm, i32imm, |
| 35196 | /* tTRAP */ |
| 35197 | /* tTST */ |
| 35198 | tGPR, tGPR, i32imm, i32imm, |
| 35199 | /* tUDF */ |
| 35200 | imm0_255, |
| 35201 | /* tUXTB */ |
| 35202 | tGPR, tGPR, i32imm, i32imm, |
| 35203 | /* tUXTH */ |
| 35204 | tGPR, tGPR, i32imm, i32imm, |
| 35205 | }; |
| 35206 | return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; |
| 35207 | } |
| 35208 | } // end namespace ARM |
| 35209 | } // end namespace llvm |
| 35210 | #endif // GET_INSTRINFO_OPERAND_TYPE |
| 35211 | |
| 35212 | #ifdef GET_INSTRINFO_MEM_OPERAND_SIZE |
| 35213 | #undef GET_INSTRINFO_MEM_OPERAND_SIZE |
| 35214 | namespace llvm { |
| 35215 | namespace ARM { |
| 35216 | LLVM_READONLY |
| 35217 | static int getMemOperandSize(int OpType) { |
| 35218 | switch (OpType) { |
| 35219 | default: return 0; |
| 35220 | } |
| 35221 | } |
| 35222 | } // end namespace ARM |
| 35223 | } // end namespace llvm |
| 35224 | #endif // GET_INSTRINFO_MEM_OPERAND_SIZE |
| 35225 | |
| 35226 | #ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP |
| 35227 | #undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP |
| 35228 | namespace llvm { |
| 35229 | namespace ARM { |
| 35230 | LLVM_READONLY static unsigned |
| 35231 | getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) { |
| 35232 | return LogicalOpIdx; |
| 35233 | } |
| 35234 | LLVM_READONLY static inline unsigned |
| 35235 | getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) { |
| 35236 | auto S = 0U; |
| 35237 | for (auto i = 0U; i < LogicalOpIdx; ++i) |
| 35238 | S += getLogicalOperandSize(Opcode, i); |
| 35239 | return S; |
| 35240 | } |
| 35241 | } // end namespace ARM |
| 35242 | } // end namespace llvm |
| 35243 | #endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP |
| 35244 | |
| 35245 | #ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP |
| 35246 | #undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP |
| 35247 | namespace llvm { |
| 35248 | namespace ARM { |
| 35249 | LLVM_READONLY static int |
| 35250 | getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) { |
| 35251 | return -1; |
| 35252 | } |
| 35253 | } // end namespace ARM |
| 35254 | } // end namespace llvm |
| 35255 | #endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP |
| 35256 | |
| 35257 | #ifdef GET_INSTRINFO_MC_HELPER_DECLS |
| 35258 | #undef GET_INSTRINFO_MC_HELPER_DECLS |
| 35259 | |
| 35260 | namespace llvm { |
| 35261 | class MCInst; |
| 35262 | class FeatureBitset; |
| 35263 | |
| 35264 | namespace ARM_MC { |
| 35265 | |
| 35266 | void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); |
| 35267 | |
| 35268 | } // end namespace ARM_MC |
| 35269 | } // end namespace llvm |
| 35270 | |
| 35271 | #endif // GET_INSTRINFO_MC_HELPER_DECLS |
| 35272 | |
| 35273 | #ifdef GET_INSTRINFO_MC_HELPERS |
| 35274 | #undef GET_INSTRINFO_MC_HELPERS |
| 35275 | |
| 35276 | namespace llvm { |
| 35277 | namespace ARM_MC { |
| 35278 | |
| 35279 | } // end namespace ARM_MC |
| 35280 | } // end namespace llvm |
| 35281 | |
| 35282 | #endif // GET_GENISTRINFO_MC_HELPERS |
| 35283 | |
| 35284 | #if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ |
| 35285 | defined(GET_AVAILABLE_OPCODE_CHECKER) |
| 35286 | #define GET_COMPUTE_FEATURES |
| 35287 | #endif |
| 35288 | #ifdef GET_COMPUTE_FEATURES |
| 35289 | #undef GET_COMPUTE_FEATURES |
| 35290 | namespace llvm { |
| 35291 | namespace ARM_MC { |
| 35292 | |
| 35293 | // Bits for subtarget features that participate in instruction matching. |
| 35294 | enum SubtargetFeatureBits : uint8_t { |
| 35295 | Feature_HasV4TBit = 35, |
| 35296 | Feature_HasV5TBit = 36, |
| 35297 | Feature_HasV5TEBit = 37, |
| 35298 | Feature_HasV6Bit = 38, |
| 35299 | Feature_HasV6MBit = 40, |
| 35300 | Feature_HasV8MBaselineBit = 45, |
| 35301 | Feature_HasV8MMainlineBit = 46, |
| 35302 | Feature_HasV8_1MMainlineBit = 47, |
| 35303 | Feature_HasMVEIntBit = 26, |
| 35304 | Feature_HasMVEFloatBit = 25, |
| 35305 | Feature_HasCDEBit = 4, |
| 35306 | Feature_HasFPRegsBit = 18, |
| 35307 | Feature_HasFPRegs16Bit = 19, |
| 35308 | Feature_HasNoFPRegs16Bit = 29, |
| 35309 | Feature_HasFPRegs64Bit = 20, |
| 35310 | Feature_HasFPRegsV8_1MBit = 21, |
| 35311 | Feature_HasV6T2Bit = 41, |
| 35312 | Feature_HasV6KBit = 39, |
| 35313 | Feature_HasV7Bit = 42, |
| 35314 | Feature_HasV8Bit = 44, |
| 35315 | Feature_PreV8Bit = 64, |
| 35316 | Feature_HasV8_1aBit = 48, |
| 35317 | Feature_HasV8_2aBit = 49, |
| 35318 | Feature_HasV8_3aBit = 50, |
| 35319 | Feature_HasV8_4aBit = 51, |
| 35320 | Feature_HasV8_5aBit = 52, |
| 35321 | Feature_HasV8_6aBit = 53, |
| 35322 | Feature_HasV8_7aBit = 54, |
| 35323 | Feature_HasVFP2Bit = 55, |
| 35324 | Feature_HasVFP3Bit = 56, |
| 35325 | Feature_HasVFP4Bit = 57, |
| 35326 | Feature_HasDPVFPBit = 10, |
| 35327 | Feature_HasFPARMv8Bit = 17, |
| 35328 | Feature_HasNEONBit = 28, |
| 35329 | Feature_HasSHA2Bit = 33, |
| 35330 | Feature_HasAESBit = 1, |
| 35331 | Feature_HasCryptoBit = 7, |
| 35332 | Feature_HasDotProdBit = 14, |
| 35333 | Feature_HasCRCBit = 6, |
| 35334 | Feature_HasRASBit = 31, |
| 35335 | Feature_HasLOBBit = 23, |
| 35336 | Feature_HasPACBTIBit = 30, |
| 35337 | Feature_HasFP16Bit = 15, |
| 35338 | Feature_HasFullFP16Bit = 22, |
| 35339 | Feature_HasFP16FMLBit = 16, |
| 35340 | Feature_HasBF16Bit = 3, |
| 35341 | Feature_HasMatMulInt8Bit = 27, |
| 35342 | Feature_HasDivideInThumbBit = 13, |
| 35343 | Feature_HasDivideInARMBit = 12, |
| 35344 | Feature_HasDSPBit = 11, |
| 35345 | Feature_HasDBBit = 8, |
| 35346 | Feature_HasDFBBit = 9, |
| 35347 | Feature_HasV7ClrexBit = 43, |
| 35348 | Feature_HasAcquireReleaseBit = 2, |
| 35349 | Feature_HasMPBit = 24, |
| 35350 | Feature_HasVirtualizationBit = 58, |
| 35351 | Feature_HasTrustZoneBit = 34, |
| 35352 | Feature_Has8MSecExtBit = 0, |
| 35353 | Feature_IsThumbBit = 62, |
| 35354 | Feature_IsThumb2Bit = 63, |
| 35355 | Feature_IsMClassBit = 60, |
| 35356 | Feature_IsNotMClassBit = 61, |
| 35357 | Feature_IsARMBit = 59, |
| 35358 | Feature_UseNaClTrapBit = 65, |
| 35359 | Feature_UseNegativeImmediatesBit = 66, |
| 35360 | Feature_HasSBBit = 32, |
| 35361 | Feature_HasCLRBHBBit = 5, |
| 35362 | }; |
| 35363 | |
| 35364 | inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { |
| 35365 | FeatureBitset Features; |
| 35366 | if (FB[ARM::HasV4TOps]) |
| 35367 | Features.set(Feature_HasV4TBit); |
| 35368 | if (FB[ARM::HasV5TOps]) |
| 35369 | Features.set(Feature_HasV5TBit); |
| 35370 | if (FB[ARM::HasV5TEOps]) |
| 35371 | Features.set(Feature_HasV5TEBit); |
| 35372 | if (FB[ARM::HasV6Ops]) |
| 35373 | Features.set(Feature_HasV6Bit); |
| 35374 | if (FB[ARM::HasV6MOps]) |
| 35375 | Features.set(Feature_HasV6MBit); |
| 35376 | if (FB[ARM::HasV8MBaselineOps]) |
| 35377 | Features.set(Feature_HasV8MBaselineBit); |
| 35378 | if (FB[ARM::HasV8MMainlineOps]) |
| 35379 | Features.set(Feature_HasV8MMainlineBit); |
| 35380 | if (FB[ARM::HasV8_1MMainlineOps]) |
| 35381 | Features.set(Feature_HasV8_1MMainlineBit); |
| 35382 | if (FB[ARM::HasMVEIntegerOps]) |
| 35383 | Features.set(Feature_HasMVEIntBit); |
| 35384 | if (FB[ARM::HasMVEFloatOps]) |
| 35385 | Features.set(Feature_HasMVEFloatBit); |
| 35386 | if (FB[ARM::HasCDEOps]) |
| 35387 | Features.set(Feature_HasCDEBit); |
| 35388 | if (FB[ARM::FeatureFPRegs]) |
| 35389 | Features.set(Feature_HasFPRegsBit); |
| 35390 | if (FB[ARM::FeatureFPRegs16]) |
| 35391 | Features.set(Feature_HasFPRegs16Bit); |
| 35392 | if (!FB[ARM::FeatureFPRegs16]) |
| 35393 | Features.set(Feature_HasNoFPRegs16Bit); |
| 35394 | if (FB[ARM::FeatureFPRegs64]) |
| 35395 | Features.set(Feature_HasFPRegs64Bit); |
| 35396 | if (FB[ARM::FeatureFPRegs] && FB[ARM::HasV8_1MMainlineOps]) |
| 35397 | Features.set(Feature_HasFPRegsV8_1MBit); |
| 35398 | if (FB[ARM::HasV6T2Ops]) |
| 35399 | Features.set(Feature_HasV6T2Bit); |
| 35400 | if (FB[ARM::HasV6KOps]) |
| 35401 | Features.set(Feature_HasV6KBit); |
| 35402 | if (FB[ARM::HasV7Ops]) |
| 35403 | Features.set(Feature_HasV7Bit); |
| 35404 | if (FB[ARM::HasV8Ops]) |
| 35405 | Features.set(Feature_HasV8Bit); |
| 35406 | if (!FB[ARM::HasV8Ops]) |
| 35407 | Features.set(Feature_PreV8Bit); |
| 35408 | if (FB[ARM::HasV8_1aOps]) |
| 35409 | Features.set(Feature_HasV8_1aBit); |
| 35410 | if (FB[ARM::HasV8_2aOps]) |
| 35411 | Features.set(Feature_HasV8_2aBit); |
| 35412 | if (FB[ARM::HasV8_3aOps]) |
| 35413 | Features.set(Feature_HasV8_3aBit); |
| 35414 | if (FB[ARM::HasV8_4aOps]) |
| 35415 | Features.set(Feature_HasV8_4aBit); |
| 35416 | if (FB[ARM::HasV8_5aOps]) |
| 35417 | Features.set(Feature_HasV8_5aBit); |
| 35418 | if (FB[ARM::HasV8_6aOps]) |
| 35419 | Features.set(Feature_HasV8_6aBit); |
| 35420 | if (FB[ARM::HasV8_7aOps]) |
| 35421 | Features.set(Feature_HasV8_7aBit); |
| 35422 | if (FB[ARM::FeatureVFP2_SP]) |
| 35423 | Features.set(Feature_HasVFP2Bit); |
| 35424 | if (FB[ARM::FeatureVFP3_D16_SP]) |
| 35425 | Features.set(Feature_HasVFP3Bit); |
| 35426 | if (FB[ARM::FeatureVFP4_D16_SP]) |
| 35427 | Features.set(Feature_HasVFP4Bit); |
| 35428 | if (FB[ARM::FeatureFP64]) |
| 35429 | Features.set(Feature_HasDPVFPBit); |
| 35430 | if (FB[ARM::FeatureFPARMv8_D16_SP]) |
| 35431 | Features.set(Feature_HasFPARMv8Bit); |
| 35432 | if (FB[ARM::FeatureNEON]) |
| 35433 | Features.set(Feature_HasNEONBit); |
| 35434 | if (FB[ARM::FeatureSHA2]) |
| 35435 | Features.set(Feature_HasSHA2Bit); |
| 35436 | if (FB[ARM::FeatureAES]) |
| 35437 | Features.set(Feature_HasAESBit); |
| 35438 | if (FB[ARM::FeatureCrypto]) |
| 35439 | Features.set(Feature_HasCryptoBit); |
| 35440 | if (FB[ARM::FeatureDotProd]) |
| 35441 | Features.set(Feature_HasDotProdBit); |
| 35442 | if (FB[ARM::FeatureCRC]) |
| 35443 | Features.set(Feature_HasCRCBit); |
| 35444 | if (FB[ARM::FeatureRAS]) |
| 35445 | Features.set(Feature_HasRASBit); |
| 35446 | if (FB[ARM::FeatureLOB]) |
| 35447 | Features.set(Feature_HasLOBBit); |
| 35448 | if (FB[ARM::FeaturePACBTI]) |
| 35449 | Features.set(Feature_HasPACBTIBit); |
| 35450 | if (FB[ARM::FeatureFP16]) |
| 35451 | Features.set(Feature_HasFP16Bit); |
| 35452 | if (FB[ARM::FeatureFullFP16]) |
| 35453 | Features.set(Feature_HasFullFP16Bit); |
| 35454 | if (FB[ARM::FeatureFP16FML]) |
| 35455 | Features.set(Feature_HasFP16FMLBit); |
| 35456 | if (FB[ARM::FeatureBF16]) |
| 35457 | Features.set(Feature_HasBF16Bit); |
| 35458 | if (FB[ARM::FeatureMatMulInt8]) |
| 35459 | Features.set(Feature_HasMatMulInt8Bit); |
| 35460 | if (FB[ARM::FeatureHWDivThumb]) |
| 35461 | Features.set(Feature_HasDivideInThumbBit); |
| 35462 | if (FB[ARM::FeatureHWDivARM]) |
| 35463 | Features.set(Feature_HasDivideInARMBit); |
| 35464 | if (FB[ARM::FeatureDSP]) |
| 35465 | Features.set(Feature_HasDSPBit); |
| 35466 | if (FB[ARM::FeatureDB]) |
| 35467 | Features.set(Feature_HasDBBit); |
| 35468 | if (FB[ARM::FeatureDFB]) |
| 35469 | Features.set(Feature_HasDFBBit); |
| 35470 | if (FB[ARM::FeatureV7Clrex]) |
| 35471 | Features.set(Feature_HasV7ClrexBit); |
| 35472 | if (FB[ARM::FeatureAcquireRelease]) |
| 35473 | Features.set(Feature_HasAcquireReleaseBit); |
| 35474 | if (FB[ARM::FeatureMP]) |
| 35475 | Features.set(Feature_HasMPBit); |
| 35476 | if (FB[ARM::FeatureVirtualization]) |
| 35477 | Features.set(Feature_HasVirtualizationBit); |
| 35478 | if (FB[ARM::FeatureTrustZone]) |
| 35479 | Features.set(Feature_HasTrustZoneBit); |
| 35480 | if (FB[ARM::Feature8MSecExt]) |
| 35481 | Features.set(Feature_Has8MSecExtBit); |
| 35482 | if (FB[ARM::ModeThumb]) |
| 35483 | Features.set(Feature_IsThumbBit); |
| 35484 | if (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) |
| 35485 | Features.set(Feature_IsThumb2Bit); |
| 35486 | if (FB[ARM::FeatureMClass]) |
| 35487 | Features.set(Feature_IsMClassBit); |
| 35488 | if (!FB[ARM::FeatureMClass]) |
| 35489 | Features.set(Feature_IsNotMClassBit); |
| 35490 | if (!FB[ARM::ModeThumb]) |
| 35491 | Features.set(Feature_IsARMBit); |
| 35492 | if (FB[ARM::FeatureNaClTrap]) |
| 35493 | Features.set(Feature_UseNaClTrapBit); |
| 35494 | if (!FB[ARM::FeatureNoNegativeImmediates]) |
| 35495 | Features.set(Feature_UseNegativeImmediatesBit); |
| 35496 | if (FB[ARM::FeatureSB]) |
| 35497 | Features.set(Feature_HasSBBit); |
| 35498 | if (FB[ARM::FeatureCLRBHB]) |
| 35499 | Features.set(Feature_HasCLRBHBBit); |
| 35500 | return Features; |
| 35501 | } |
| 35502 | |
| 35503 | inline FeatureBitset computeRequiredFeatures(unsigned Opcode) { |
| 35504 | enum : uint8_t { |
| 35505 | CEFBS_None, |
| 35506 | CEFBS_Has8MSecExt, |
| 35507 | CEFBS_HasBF16, |
| 35508 | CEFBS_HasCDE, |
| 35509 | CEFBS_HasDotProd, |
| 35510 | CEFBS_HasFP16, |
| 35511 | CEFBS_HasFPARMv8, |
| 35512 | CEFBS_HasFPRegs, |
| 35513 | CEFBS_HasFPRegs16, |
| 35514 | CEFBS_HasFPRegs64, |
| 35515 | CEFBS_HasFPRegsV8_1M, |
| 35516 | CEFBS_HasFullFP16, |
| 35517 | CEFBS_HasMVEFloat, |
| 35518 | CEFBS_HasMVEInt, |
| 35519 | CEFBS_HasMatMulInt8, |
| 35520 | CEFBS_HasNEON, |
| 35521 | CEFBS_HasV8_1MMainline, |
| 35522 | CEFBS_HasVFP2, |
| 35523 | CEFBS_HasVFP3, |
| 35524 | CEFBS_HasVFP4, |
| 35525 | CEFBS_IsARM, |
| 35526 | CEFBS_IsThumb, |
| 35527 | CEFBS_IsThumb2, |
| 35528 | CEFBS_HasBF16_HasNEON, |
| 35529 | CEFBS_HasCDE_HasFPRegs, |
| 35530 | CEFBS_HasCDE_HasMVEInt, |
| 35531 | CEFBS_HasDSP_IsThumb2, |
| 35532 | CEFBS_HasFPARMv8_HasDPVFP, |
| 35533 | CEFBS_HasFPARMv8_HasNEON, |
| 35534 | CEFBS_HasFPARMv8_HasV8_3a, |
| 35535 | CEFBS_HasFPRegs_HasV8_1MMainline, |
| 35536 | CEFBS_HasNEON_HasFP16, |
| 35537 | CEFBS_HasNEON_HasFP16FML, |
| 35538 | CEFBS_HasNEON_HasFullFP16, |
| 35539 | CEFBS_HasNEON_HasV8_1a, |
| 35540 | CEFBS_HasNEON_HasV8_3a, |
| 35541 | CEFBS_HasNEON_HasVFP4, |
| 35542 | CEFBS_HasV7_IsMClass, |
| 35543 | CEFBS_HasV8_HasAES, |
| 35544 | CEFBS_HasV8_HasNEON, |
| 35545 | CEFBS_HasV8_HasSHA2, |
| 35546 | CEFBS_HasV8MMainline_Has8MSecExt, |
| 35547 | CEFBS_HasV8_1MMainline_Has8MSecExt, |
| 35548 | CEFBS_HasV8_1MMainline_HasFPRegs, |
| 35549 | CEFBS_HasV8_1MMainline_HasMVEInt, |
| 35550 | CEFBS_HasVFP2_HasDPVFP, |
| 35551 | CEFBS_HasVFP3_HasDPVFP, |
| 35552 | CEFBS_HasVFP4_HasDPVFP, |
| 35553 | CEFBS_IsARM_HasAcquireRelease, |
| 35554 | CEFBS_IsARM_HasCRC, |
| 35555 | CEFBS_IsARM_HasDB, |
| 35556 | CEFBS_IsARM_HasDivideInARM, |
| 35557 | CEFBS_IsARM_HasSB, |
| 35558 | CEFBS_IsARM_HasTrustZone, |
| 35559 | CEFBS_IsARM_HasV4T, |
| 35560 | CEFBS_IsARM_HasV5T, |
| 35561 | CEFBS_IsARM_HasV5TE, |
| 35562 | CEFBS_IsARM_HasV6, |
| 35563 | CEFBS_IsARM_HasV6K, |
| 35564 | CEFBS_IsARM_HasV6T2, |
| 35565 | CEFBS_IsARM_HasV7, |
| 35566 | CEFBS_IsARM_HasV8, |
| 35567 | CEFBS_IsARM_HasV8_4a, |
| 35568 | CEFBS_IsARM_HasVFP2, |
| 35569 | CEFBS_IsARM_HasVirtualization, |
| 35570 | CEFBS_IsARM_PreV8, |
| 35571 | CEFBS_IsARM_UseNaClTrap, |
| 35572 | CEFBS_IsThumb_Has8MSecExt, |
| 35573 | CEFBS_IsThumb_HasAcquireRelease, |
| 35574 | CEFBS_IsThumb_HasDB, |
| 35575 | CEFBS_IsThumb_HasV5T, |
| 35576 | CEFBS_IsThumb_HasV6, |
| 35577 | CEFBS_IsThumb_HasV6M, |
| 35578 | CEFBS_IsThumb_HasV7Clrex, |
| 35579 | CEFBS_IsThumb_HasV8, |
| 35580 | CEFBS_IsThumb_HasV8MBaseline, |
| 35581 | CEFBS_IsThumb_HasV8_4a, |
| 35582 | CEFBS_IsThumb_HasVirtualization, |
| 35583 | CEFBS_IsThumb_IsMClass, |
| 35584 | CEFBS_IsThumb_IsNotMClass, |
| 35585 | CEFBS_IsThumb2_HasCRC, |
| 35586 | CEFBS_IsThumb2_HasDSP, |
| 35587 | CEFBS_IsThumb2_HasSB, |
| 35588 | CEFBS_IsThumb2_HasTrustZone, |
| 35589 | CEFBS_IsThumb2_HasV7, |
| 35590 | CEFBS_IsThumb2_HasV8, |
| 35591 | CEFBS_IsThumb2_HasVFP2, |
| 35592 | CEFBS_IsThumb2_HasVirtualization, |
| 35593 | CEFBS_IsThumb2_IsNotMClass, |
| 35594 | CEFBS_IsThumb2_PreV8, |
| 35595 | CEFBS_PreV8_IsThumb2, |
| 35596 | CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, |
| 35597 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, |
| 35598 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, |
| 35599 | CEFBS_HasV8_HasNEON_HasFullFP16, |
| 35600 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, |
| 35601 | CEFBS_IsARM_HasV7_HasMP, |
| 35602 | CEFBS_IsARM_HasV8_HasV8_1a, |
| 35603 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, |
| 35604 | CEFBS_IsThumb_HasV5T_IsNotMClass, |
| 35605 | CEFBS_IsThumb2_HasV7_HasMP, |
| 35606 | CEFBS_IsThumb2_HasV8_HasV8_1a, |
| 35607 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, |
| 35608 | CEFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, |
| 35609 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, |
| 35610 | }; |
| 35611 | |
| 35612 | static constexpr FeatureBitset FeatureBitsets[] = { |
| 35613 | {}, // CEFBS_None |
| 35614 | {Feature_Has8MSecExtBit, }, |
| 35615 | {Feature_HasBF16Bit, }, |
| 35616 | {Feature_HasCDEBit, }, |
| 35617 | {Feature_HasDotProdBit, }, |
| 35618 | {Feature_HasFP16Bit, }, |
| 35619 | {Feature_HasFPARMv8Bit, }, |
| 35620 | {Feature_HasFPRegsBit, }, |
| 35621 | {Feature_HasFPRegs16Bit, }, |
| 35622 | {Feature_HasFPRegs64Bit, }, |
| 35623 | {Feature_HasFPRegsV8_1MBit, }, |
| 35624 | {Feature_HasFullFP16Bit, }, |
| 35625 | {Feature_HasMVEFloatBit, }, |
| 35626 | {Feature_HasMVEIntBit, }, |
| 35627 | {Feature_HasMatMulInt8Bit, }, |
| 35628 | {Feature_HasNEONBit, }, |
| 35629 | {Feature_HasV8_1MMainlineBit, }, |
| 35630 | {Feature_HasVFP2Bit, }, |
| 35631 | {Feature_HasVFP3Bit, }, |
| 35632 | {Feature_HasVFP4Bit, }, |
| 35633 | {Feature_IsARMBit, }, |
| 35634 | {Feature_IsThumbBit, }, |
| 35635 | {Feature_IsThumb2Bit, }, |
| 35636 | {Feature_HasBF16Bit, Feature_HasNEONBit, }, |
| 35637 | {Feature_HasCDEBit, Feature_HasFPRegsBit, }, |
| 35638 | {Feature_HasCDEBit, Feature_HasMVEIntBit, }, |
| 35639 | {Feature_HasDSPBit, Feature_IsThumb2Bit, }, |
| 35640 | {Feature_HasFPARMv8Bit, Feature_HasDPVFPBit, }, |
| 35641 | {Feature_HasFPARMv8Bit, Feature_HasNEONBit, }, |
| 35642 | {Feature_HasFPARMv8Bit, Feature_HasV8_3aBit, }, |
| 35643 | {Feature_HasFPRegsBit, Feature_HasV8_1MMainlineBit, }, |
| 35644 | {Feature_HasNEONBit, Feature_HasFP16Bit, }, |
| 35645 | {Feature_HasNEONBit, Feature_HasFP16FMLBit, }, |
| 35646 | {Feature_HasNEONBit, Feature_HasFullFP16Bit, }, |
| 35647 | {Feature_HasNEONBit, Feature_HasV8_1aBit, }, |
| 35648 | {Feature_HasNEONBit, Feature_HasV8_3aBit, }, |
| 35649 | {Feature_HasNEONBit, Feature_HasVFP4Bit, }, |
| 35650 | {Feature_HasV7Bit, Feature_IsMClassBit, }, |
| 35651 | {Feature_HasV8Bit, Feature_HasAESBit, }, |
| 35652 | {Feature_HasV8Bit, Feature_HasNEONBit, }, |
| 35653 | {Feature_HasV8Bit, Feature_HasSHA2Bit, }, |
| 35654 | {Feature_HasV8MMainlineBit, Feature_Has8MSecExtBit, }, |
| 35655 | {Feature_HasV8_1MMainlineBit, Feature_Has8MSecExtBit, }, |
| 35656 | {Feature_HasV8_1MMainlineBit, Feature_HasFPRegsBit, }, |
| 35657 | {Feature_HasV8_1MMainlineBit, Feature_HasMVEIntBit, }, |
| 35658 | {Feature_HasVFP2Bit, Feature_HasDPVFPBit, }, |
| 35659 | {Feature_HasVFP3Bit, Feature_HasDPVFPBit, }, |
| 35660 | {Feature_HasVFP4Bit, Feature_HasDPVFPBit, }, |
| 35661 | {Feature_IsARMBit, Feature_HasAcquireReleaseBit, }, |
| 35662 | {Feature_IsARMBit, Feature_HasCRCBit, }, |
| 35663 | {Feature_IsARMBit, Feature_HasDBBit, }, |
| 35664 | {Feature_IsARMBit, Feature_HasDivideInARMBit, }, |
| 35665 | {Feature_IsARMBit, Feature_HasSBBit, }, |
| 35666 | {Feature_IsARMBit, Feature_HasTrustZoneBit, }, |
| 35667 | {Feature_IsARMBit, Feature_HasV4TBit, }, |
| 35668 | {Feature_IsARMBit, Feature_HasV5TBit, }, |
| 35669 | {Feature_IsARMBit, Feature_HasV5TEBit, }, |
| 35670 | {Feature_IsARMBit, Feature_HasV6Bit, }, |
| 35671 | {Feature_IsARMBit, Feature_HasV6KBit, }, |
| 35672 | {Feature_IsARMBit, Feature_HasV6T2Bit, }, |
| 35673 | {Feature_IsARMBit, Feature_HasV7Bit, }, |
| 35674 | {Feature_IsARMBit, Feature_HasV8Bit, }, |
| 35675 | {Feature_IsARMBit, Feature_HasV8_4aBit, }, |
| 35676 | {Feature_IsARMBit, Feature_HasVFP2Bit, }, |
| 35677 | {Feature_IsARMBit, Feature_HasVirtualizationBit, }, |
| 35678 | {Feature_IsARMBit, Feature_PreV8Bit, }, |
| 35679 | {Feature_IsARMBit, Feature_UseNaClTrapBit, }, |
| 35680 | {Feature_IsThumbBit, Feature_Has8MSecExtBit, }, |
| 35681 | {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, }, |
| 35682 | {Feature_IsThumbBit, Feature_HasDBBit, }, |
| 35683 | {Feature_IsThumbBit, Feature_HasV5TBit, }, |
| 35684 | {Feature_IsThumbBit, Feature_HasV6Bit, }, |
| 35685 | {Feature_IsThumbBit, Feature_HasV6MBit, }, |
| 35686 | {Feature_IsThumbBit, Feature_HasV7ClrexBit, }, |
| 35687 | {Feature_IsThumbBit, Feature_HasV8Bit, }, |
| 35688 | {Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, |
| 35689 | {Feature_IsThumbBit, Feature_HasV8_4aBit, }, |
| 35690 | {Feature_IsThumbBit, Feature_HasVirtualizationBit, }, |
| 35691 | {Feature_IsThumbBit, Feature_IsMClassBit, }, |
| 35692 | {Feature_IsThumbBit, Feature_IsNotMClassBit, }, |
| 35693 | {Feature_IsThumb2Bit, Feature_HasCRCBit, }, |
| 35694 | {Feature_IsThumb2Bit, Feature_HasDSPBit, }, |
| 35695 | {Feature_IsThumb2Bit, Feature_HasSBBit, }, |
| 35696 | {Feature_IsThumb2Bit, Feature_HasTrustZoneBit, }, |
| 35697 | {Feature_IsThumb2Bit, Feature_HasV7Bit, }, |
| 35698 | {Feature_IsThumb2Bit, Feature_HasV8Bit, }, |
| 35699 | {Feature_IsThumb2Bit, Feature_HasVFP2Bit, }, |
| 35700 | {Feature_IsThumb2Bit, Feature_HasVirtualizationBit, }, |
| 35701 | {Feature_IsThumb2Bit, Feature_IsNotMClassBit, }, |
| 35702 | {Feature_IsThumb2Bit, Feature_PreV8Bit, }, |
| 35703 | {Feature_PreV8Bit, Feature_IsThumb2Bit, }, |
| 35704 | {Feature_HasDivideInThumbBit, Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, |
| 35705 | {Feature_HasFPARMv8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, }, |
| 35706 | {Feature_HasNEONBit, Feature_HasV8_3aBit, Feature_HasFullFP16Bit, }, |
| 35707 | {Feature_HasV8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, }, |
| 35708 | {Feature_IsARMBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, |
| 35709 | {Feature_IsARMBit, Feature_HasV7Bit, Feature_HasMPBit, }, |
| 35710 | {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, |
| 35711 | {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, |
| 35712 | {Feature_IsThumbBit, Feature_HasV5TBit, Feature_IsNotMClassBit, }, |
| 35713 | {Feature_IsThumb2Bit, Feature_HasV7Bit, Feature_HasMPBit, }, |
| 35714 | {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, |
| 35715 | {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasLOBBit, }, |
| 35716 | {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasPACBTIBit, }, |
| 35717 | {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, Feature_IsNotMClassBit, }, |
| 35718 | }; |
| 35719 | static constexpr uint8_t RequiredFeaturesRefs[] = { |
| 35720 | CEFBS_None, // PHI = 0 |
| 35721 | CEFBS_None, // INLINEASM = 1 |
| 35722 | CEFBS_None, // INLINEASM_BR = 2 |
| 35723 | CEFBS_None, // CFI_INSTRUCTION = 3 |
| 35724 | CEFBS_None, // EH_LABEL = 4 |
| 35725 | CEFBS_None, // GC_LABEL = 5 |
| 35726 | CEFBS_None, // ANNOTATION_LABEL = 6 |
| 35727 | CEFBS_None, // KILL = 7 |
| 35728 | CEFBS_None, // EXTRACT_SUBREG = 8 |
| 35729 | CEFBS_None, // INSERT_SUBREG = 9 |
| 35730 | CEFBS_None, // IMPLICIT_DEF = 10 |
| 35731 | CEFBS_None, // SUBREG_TO_REG = 11 |
| 35732 | CEFBS_None, // COPY_TO_REGCLASS = 12 |
| 35733 | CEFBS_None, // DBG_VALUE = 13 |
| 35734 | CEFBS_None, // DBG_VALUE_LIST = 14 |
| 35735 | CEFBS_None, // DBG_INSTR_REF = 15 |
| 35736 | CEFBS_None, // DBG_PHI = 16 |
| 35737 | CEFBS_None, // DBG_LABEL = 17 |
| 35738 | CEFBS_None, // REG_SEQUENCE = 18 |
| 35739 | CEFBS_None, // COPY = 19 |
| 35740 | CEFBS_None, // BUNDLE = 20 |
| 35741 | CEFBS_None, // LIFETIME_START = 21 |
| 35742 | CEFBS_None, // LIFETIME_END = 22 |
| 35743 | CEFBS_None, // PSEUDO_PROBE = 23 |
| 35744 | CEFBS_None, // ARITH_FENCE = 24 |
| 35745 | CEFBS_None, // STACKMAP = 25 |
| 35746 | CEFBS_None, // FENTRY_CALL = 26 |
| 35747 | CEFBS_None, // PATCHPOINT = 27 |
| 35748 | CEFBS_None, // LOAD_STACK_GUARD = 28 |
| 35749 | CEFBS_None, // PREALLOCATED_SETUP = 29 |
| 35750 | CEFBS_None, // PREALLOCATED_ARG = 30 |
| 35751 | CEFBS_None, // STATEPOINT = 31 |
| 35752 | CEFBS_None, // LOCAL_ESCAPE = 32 |
| 35753 | CEFBS_None, // FAULTING_OP = 33 |
| 35754 | CEFBS_None, // PATCHABLE_OP = 34 |
| 35755 | CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35 |
| 35756 | CEFBS_None, // PATCHABLE_RET = 36 |
| 35757 | CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37 |
| 35758 | CEFBS_None, // PATCHABLE_TAIL_CALL = 38 |
| 35759 | CEFBS_None, // PATCHABLE_EVENT_CALL = 39 |
| 35760 | CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40 |
| 35761 | CEFBS_None, // ICALL_BRANCH_FUNNEL = 41 |
| 35762 | CEFBS_None, // MEMBARRIER = 42 |
| 35763 | CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43 |
| 35764 | CEFBS_None, // CONVERGENCECTRL_ENTRY = 44 |
| 35765 | CEFBS_None, // CONVERGENCECTRL_ANCHOR = 45 |
| 35766 | CEFBS_None, // CONVERGENCECTRL_LOOP = 46 |
| 35767 | CEFBS_None, // CONVERGENCECTRL_GLUE = 47 |
| 35768 | CEFBS_None, // G_ASSERT_SEXT = 48 |
| 35769 | CEFBS_None, // G_ASSERT_ZEXT = 49 |
| 35770 | CEFBS_None, // G_ASSERT_ALIGN = 50 |
| 35771 | CEFBS_None, // G_ADD = 51 |
| 35772 | CEFBS_None, // G_SUB = 52 |
| 35773 | CEFBS_None, // G_MUL = 53 |
| 35774 | CEFBS_None, // G_SDIV = 54 |
| 35775 | CEFBS_None, // G_UDIV = 55 |
| 35776 | CEFBS_None, // G_SREM = 56 |
| 35777 | CEFBS_None, // G_UREM = 57 |
| 35778 | CEFBS_None, // G_SDIVREM = 58 |
| 35779 | CEFBS_None, // G_UDIVREM = 59 |
| 35780 | CEFBS_None, // G_AND = 60 |
| 35781 | CEFBS_None, // G_OR = 61 |
| 35782 | CEFBS_None, // G_XOR = 62 |
| 35783 | CEFBS_None, // G_IMPLICIT_DEF = 63 |
| 35784 | CEFBS_None, // G_PHI = 64 |
| 35785 | CEFBS_None, // G_FRAME_INDEX = 65 |
| 35786 | CEFBS_None, // G_GLOBAL_VALUE = 66 |
| 35787 | CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 67 |
| 35788 | CEFBS_None, // G_CONSTANT_POOL = 68 |
| 35789 | CEFBS_None, // G_EXTRACT = 69 |
| 35790 | CEFBS_None, // G_UNMERGE_VALUES = 70 |
| 35791 | CEFBS_None, // G_INSERT = 71 |
| 35792 | CEFBS_None, // G_MERGE_VALUES = 72 |
| 35793 | CEFBS_None, // G_BUILD_VECTOR = 73 |
| 35794 | CEFBS_None, // G_BUILD_VECTOR_TRUNC = 74 |
| 35795 | CEFBS_None, // G_CONCAT_VECTORS = 75 |
| 35796 | CEFBS_None, // G_PTRTOINT = 76 |
| 35797 | CEFBS_None, // G_INTTOPTR = 77 |
| 35798 | CEFBS_None, // G_BITCAST = 78 |
| 35799 | CEFBS_None, // G_FREEZE = 79 |
| 35800 | CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 80 |
| 35801 | CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 81 |
| 35802 | CEFBS_None, // G_INTRINSIC_TRUNC = 82 |
| 35803 | CEFBS_None, // G_INTRINSIC_ROUND = 83 |
| 35804 | CEFBS_None, // G_INTRINSIC_LRINT = 84 |
| 35805 | CEFBS_None, // G_INTRINSIC_LLRINT = 85 |
| 35806 | CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 86 |
| 35807 | CEFBS_None, // G_READCYCLECOUNTER = 87 |
| 35808 | CEFBS_None, // G_READSTEADYCOUNTER = 88 |
| 35809 | CEFBS_None, // G_LOAD = 89 |
| 35810 | CEFBS_None, // G_SEXTLOAD = 90 |
| 35811 | CEFBS_None, // G_ZEXTLOAD = 91 |
| 35812 | CEFBS_None, // G_INDEXED_LOAD = 92 |
| 35813 | CEFBS_None, // G_INDEXED_SEXTLOAD = 93 |
| 35814 | CEFBS_None, // G_INDEXED_ZEXTLOAD = 94 |
| 35815 | CEFBS_None, // G_STORE = 95 |
| 35816 | CEFBS_None, // G_INDEXED_STORE = 96 |
| 35817 | CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97 |
| 35818 | CEFBS_None, // G_ATOMIC_CMPXCHG = 98 |
| 35819 | CEFBS_None, // G_ATOMICRMW_XCHG = 99 |
| 35820 | CEFBS_None, // G_ATOMICRMW_ADD = 100 |
| 35821 | CEFBS_None, // G_ATOMICRMW_SUB = 101 |
| 35822 | CEFBS_None, // G_ATOMICRMW_AND = 102 |
| 35823 | CEFBS_None, // G_ATOMICRMW_NAND = 103 |
| 35824 | CEFBS_None, // G_ATOMICRMW_OR = 104 |
| 35825 | CEFBS_None, // G_ATOMICRMW_XOR = 105 |
| 35826 | CEFBS_None, // G_ATOMICRMW_MAX = 106 |
| 35827 | CEFBS_None, // G_ATOMICRMW_MIN = 107 |
| 35828 | CEFBS_None, // G_ATOMICRMW_UMAX = 108 |
| 35829 | CEFBS_None, // G_ATOMICRMW_UMIN = 109 |
| 35830 | CEFBS_None, // G_ATOMICRMW_FADD = 110 |
| 35831 | CEFBS_None, // G_ATOMICRMW_FSUB = 111 |
| 35832 | CEFBS_None, // G_ATOMICRMW_FMAX = 112 |
| 35833 | CEFBS_None, // G_ATOMICRMW_FMIN = 113 |
| 35834 | CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 114 |
| 35835 | CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 115 |
| 35836 | CEFBS_None, // G_FENCE = 116 |
| 35837 | CEFBS_None, // G_PREFETCH = 117 |
| 35838 | CEFBS_None, // G_BRCOND = 118 |
| 35839 | CEFBS_None, // G_BRINDIRECT = 119 |
| 35840 | CEFBS_None, // G_INVOKE_REGION_START = 120 |
| 35841 | CEFBS_None, // G_INTRINSIC = 121 |
| 35842 | CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 122 |
| 35843 | CEFBS_None, // G_INTRINSIC_CONVERGENT = 123 |
| 35844 | CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124 |
| 35845 | CEFBS_None, // G_ANYEXT = 125 |
| 35846 | CEFBS_None, // G_TRUNC = 126 |
| 35847 | CEFBS_None, // G_CONSTANT = 127 |
| 35848 | CEFBS_None, // G_FCONSTANT = 128 |
| 35849 | CEFBS_None, // G_VASTART = 129 |
| 35850 | CEFBS_None, // G_VAARG = 130 |
| 35851 | CEFBS_None, // G_SEXT = 131 |
| 35852 | CEFBS_None, // G_SEXT_INREG = 132 |
| 35853 | CEFBS_None, // G_ZEXT = 133 |
| 35854 | CEFBS_None, // G_SHL = 134 |
| 35855 | CEFBS_None, // G_LSHR = 135 |
| 35856 | CEFBS_None, // G_ASHR = 136 |
| 35857 | CEFBS_None, // G_FSHL = 137 |
| 35858 | CEFBS_None, // G_FSHR = 138 |
| 35859 | CEFBS_None, // G_ROTR = 139 |
| 35860 | CEFBS_None, // G_ROTL = 140 |
| 35861 | CEFBS_None, // G_ICMP = 141 |
| 35862 | CEFBS_None, // G_FCMP = 142 |
| 35863 | CEFBS_None, // G_SCMP = 143 |
| 35864 | CEFBS_None, // G_UCMP = 144 |
| 35865 | CEFBS_None, // G_SELECT = 145 |
| 35866 | CEFBS_None, // G_UADDO = 146 |
| 35867 | CEFBS_None, // G_UADDE = 147 |
| 35868 | CEFBS_None, // G_USUBO = 148 |
| 35869 | CEFBS_None, // G_USUBE = 149 |
| 35870 | CEFBS_None, // G_SADDO = 150 |
| 35871 | CEFBS_None, // G_SADDE = 151 |
| 35872 | CEFBS_None, // G_SSUBO = 152 |
| 35873 | CEFBS_None, // G_SSUBE = 153 |
| 35874 | CEFBS_None, // G_UMULO = 154 |
| 35875 | CEFBS_None, // G_SMULO = 155 |
| 35876 | CEFBS_None, // G_UMULH = 156 |
| 35877 | CEFBS_None, // G_SMULH = 157 |
| 35878 | CEFBS_None, // G_UADDSAT = 158 |
| 35879 | CEFBS_None, // G_SADDSAT = 159 |
| 35880 | CEFBS_None, // G_USUBSAT = 160 |
| 35881 | CEFBS_None, // G_SSUBSAT = 161 |
| 35882 | CEFBS_None, // G_USHLSAT = 162 |
| 35883 | CEFBS_None, // G_SSHLSAT = 163 |
| 35884 | CEFBS_None, // G_SMULFIX = 164 |
| 35885 | CEFBS_None, // G_UMULFIX = 165 |
| 35886 | CEFBS_None, // G_SMULFIXSAT = 166 |
| 35887 | CEFBS_None, // G_UMULFIXSAT = 167 |
| 35888 | CEFBS_None, // G_SDIVFIX = 168 |
| 35889 | CEFBS_None, // G_UDIVFIX = 169 |
| 35890 | CEFBS_None, // G_SDIVFIXSAT = 170 |
| 35891 | CEFBS_None, // G_UDIVFIXSAT = 171 |
| 35892 | CEFBS_None, // G_FADD = 172 |
| 35893 | CEFBS_None, // G_FSUB = 173 |
| 35894 | CEFBS_None, // G_FMUL = 174 |
| 35895 | CEFBS_None, // G_FMA = 175 |
| 35896 | CEFBS_None, // G_FMAD = 176 |
| 35897 | CEFBS_None, // G_FDIV = 177 |
| 35898 | CEFBS_None, // G_FREM = 178 |
| 35899 | CEFBS_None, // G_FPOW = 179 |
| 35900 | CEFBS_None, // G_FPOWI = 180 |
| 35901 | CEFBS_None, // G_FEXP = 181 |
| 35902 | CEFBS_None, // G_FEXP2 = 182 |
| 35903 | CEFBS_None, // G_FEXP10 = 183 |
| 35904 | CEFBS_None, // G_FLOG = 184 |
| 35905 | CEFBS_None, // G_FLOG2 = 185 |
| 35906 | CEFBS_None, // G_FLOG10 = 186 |
| 35907 | CEFBS_None, // G_FLDEXP = 187 |
| 35908 | CEFBS_None, // G_FFREXP = 188 |
| 35909 | CEFBS_None, // G_FNEG = 189 |
| 35910 | CEFBS_None, // G_FPEXT = 190 |
| 35911 | CEFBS_None, // G_FPTRUNC = 191 |
| 35912 | CEFBS_None, // G_FPTOSI = 192 |
| 35913 | CEFBS_None, // G_FPTOUI = 193 |
| 35914 | CEFBS_None, // G_SITOFP = 194 |
| 35915 | CEFBS_None, // G_UITOFP = 195 |
| 35916 | CEFBS_None, // G_FABS = 196 |
| 35917 | CEFBS_None, // G_FCOPYSIGN = 197 |
| 35918 | CEFBS_None, // G_IS_FPCLASS = 198 |
| 35919 | CEFBS_None, // G_FCANONICALIZE = 199 |
| 35920 | CEFBS_None, // G_FMINNUM = 200 |
| 35921 | CEFBS_None, // G_FMAXNUM = 201 |
| 35922 | CEFBS_None, // G_FMINNUM_IEEE = 202 |
| 35923 | CEFBS_None, // G_FMAXNUM_IEEE = 203 |
| 35924 | CEFBS_None, // G_FMINIMUM = 204 |
| 35925 | CEFBS_None, // G_FMAXIMUM = 205 |
| 35926 | CEFBS_None, // G_GET_FPENV = 206 |
| 35927 | CEFBS_None, // G_SET_FPENV = 207 |
| 35928 | CEFBS_None, // G_RESET_FPENV = 208 |
| 35929 | CEFBS_None, // G_GET_FPMODE = 209 |
| 35930 | CEFBS_None, // G_SET_FPMODE = 210 |
| 35931 | CEFBS_None, // G_RESET_FPMODE = 211 |
| 35932 | CEFBS_None, // G_PTR_ADD = 212 |
| 35933 | CEFBS_None, // G_PTRMASK = 213 |
| 35934 | CEFBS_None, // G_SMIN = 214 |
| 35935 | CEFBS_None, // G_SMAX = 215 |
| 35936 | CEFBS_None, // G_UMIN = 216 |
| 35937 | CEFBS_None, // G_UMAX = 217 |
| 35938 | CEFBS_None, // G_ABS = 218 |
| 35939 | CEFBS_None, // G_LROUND = 219 |
| 35940 | CEFBS_None, // G_LLROUND = 220 |
| 35941 | CEFBS_None, // G_BR = 221 |
| 35942 | CEFBS_None, // G_BRJT = 222 |
| 35943 | CEFBS_None, // G_VSCALE = 223 |
| 35944 | CEFBS_None, // G_INSERT_SUBVECTOR = 224 |
| 35945 | CEFBS_None, // G_EXTRACT_SUBVECTOR = 225 |
| 35946 | CEFBS_None, // G_INSERT_VECTOR_ELT = 226 |
| 35947 | CEFBS_None, // G_EXTRACT_VECTOR_ELT = 227 |
| 35948 | CEFBS_None, // G_SHUFFLE_VECTOR = 228 |
| 35949 | CEFBS_None, // G_SPLAT_VECTOR = 229 |
| 35950 | CEFBS_None, // G_VECTOR_COMPRESS = 230 |
| 35951 | CEFBS_None, // G_CTTZ = 231 |
| 35952 | CEFBS_None, // G_CTTZ_ZERO_UNDEF = 232 |
| 35953 | CEFBS_None, // G_CTLZ = 233 |
| 35954 | CEFBS_None, // G_CTLZ_ZERO_UNDEF = 234 |
| 35955 | CEFBS_None, // G_CTPOP = 235 |
| 35956 | CEFBS_None, // G_BSWAP = 236 |
| 35957 | CEFBS_None, // G_BITREVERSE = 237 |
| 35958 | CEFBS_None, // G_FCEIL = 238 |
| 35959 | CEFBS_None, // G_FCOS = 239 |
| 35960 | CEFBS_None, // G_FSIN = 240 |
| 35961 | CEFBS_None, // G_FTAN = 241 |
| 35962 | CEFBS_None, // G_FACOS = 242 |
| 35963 | CEFBS_None, // G_FASIN = 243 |
| 35964 | CEFBS_None, // G_FATAN = 244 |
| 35965 | CEFBS_None, // G_FCOSH = 245 |
| 35966 | CEFBS_None, // G_FSINH = 246 |
| 35967 | CEFBS_None, // G_FTANH = 247 |
| 35968 | CEFBS_None, // G_FSQRT = 248 |
| 35969 | CEFBS_None, // G_FFLOOR = 249 |
| 35970 | CEFBS_None, // G_FRINT = 250 |
| 35971 | CEFBS_None, // G_FNEARBYINT = 251 |
| 35972 | CEFBS_None, // G_ADDRSPACE_CAST = 252 |
| 35973 | CEFBS_None, // G_BLOCK_ADDR = 253 |
| 35974 | CEFBS_None, // G_JUMP_TABLE = 254 |
| 35975 | CEFBS_None, // G_DYN_STACKALLOC = 255 |
| 35976 | CEFBS_None, // G_STACKSAVE = 256 |
| 35977 | CEFBS_None, // G_STACKRESTORE = 257 |
| 35978 | CEFBS_None, // G_STRICT_FADD = 258 |
| 35979 | CEFBS_None, // G_STRICT_FSUB = 259 |
| 35980 | CEFBS_None, // G_STRICT_FMUL = 260 |
| 35981 | CEFBS_None, // G_STRICT_FDIV = 261 |
| 35982 | CEFBS_None, // G_STRICT_FREM = 262 |
| 35983 | CEFBS_None, // G_STRICT_FMA = 263 |
| 35984 | CEFBS_None, // G_STRICT_FSQRT = 264 |
| 35985 | CEFBS_None, // G_STRICT_FLDEXP = 265 |
| 35986 | CEFBS_None, // G_READ_REGISTER = 266 |
| 35987 | CEFBS_None, // G_WRITE_REGISTER = 267 |
| 35988 | CEFBS_None, // G_MEMCPY = 268 |
| 35989 | CEFBS_None, // G_MEMCPY_INLINE = 269 |
| 35990 | CEFBS_None, // G_MEMMOVE = 270 |
| 35991 | CEFBS_None, // G_MEMSET = 271 |
| 35992 | CEFBS_None, // G_BZERO = 272 |
| 35993 | CEFBS_None, // G_TRAP = 273 |
| 35994 | CEFBS_None, // G_DEBUGTRAP = 274 |
| 35995 | CEFBS_None, // G_UBSANTRAP = 275 |
| 35996 | CEFBS_None, // G_VECREDUCE_SEQ_FADD = 276 |
| 35997 | CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 277 |
| 35998 | CEFBS_None, // G_VECREDUCE_FADD = 278 |
| 35999 | CEFBS_None, // G_VECREDUCE_FMUL = 279 |
| 36000 | CEFBS_None, // G_VECREDUCE_FMAX = 280 |
| 36001 | CEFBS_None, // G_VECREDUCE_FMIN = 281 |
| 36002 | CEFBS_None, // G_VECREDUCE_FMAXIMUM = 282 |
| 36003 | CEFBS_None, // G_VECREDUCE_FMINIMUM = 283 |
| 36004 | CEFBS_None, // G_VECREDUCE_ADD = 284 |
| 36005 | CEFBS_None, // G_VECREDUCE_MUL = 285 |
| 36006 | CEFBS_None, // G_VECREDUCE_AND = 286 |
| 36007 | CEFBS_None, // G_VECREDUCE_OR = 287 |
| 36008 | CEFBS_None, // G_VECREDUCE_XOR = 288 |
| 36009 | CEFBS_None, // G_VECREDUCE_SMAX = 289 |
| 36010 | CEFBS_None, // G_VECREDUCE_SMIN = 290 |
| 36011 | CEFBS_None, // G_VECREDUCE_UMAX = 291 |
| 36012 | CEFBS_None, // G_VECREDUCE_UMIN = 292 |
| 36013 | CEFBS_None, // G_SBFX = 293 |
| 36014 | CEFBS_None, // G_UBFX = 294 |
| 36015 | CEFBS_IsARM, // ABS = 295 |
| 36016 | CEFBS_IsARM, // ADDSri = 296 |
| 36017 | CEFBS_IsARM, // ADDSrr = 297 |
| 36018 | CEFBS_IsARM, // ADDSrsi = 298 |
| 36019 | CEFBS_IsARM, // ADDSrsr = 299 |
| 36020 | CEFBS_None, // ADJCALLSTACKDOWN = 300 |
| 36021 | CEFBS_None, // ADJCALLSTACKUP = 301 |
| 36022 | CEFBS_IsARM, // ASRi = 302 |
| 36023 | CEFBS_IsARM, // ASRr = 303 |
| 36024 | CEFBS_IsARM, // B = 304 |
| 36025 | CEFBS_None, // BCCZi64 = 305 |
| 36026 | CEFBS_None, // BCCi64 = 306 |
| 36027 | CEFBS_IsARM_HasV5T, // BLX_noip = 307 |
| 36028 | CEFBS_IsARM_HasV5T, // BLX_pred_noip = 308 |
| 36029 | CEFBS_IsARM, // BL_PUSHLR = 309 |
| 36030 | CEFBS_IsARM, // BMOVPCB_CALL = 310 |
| 36031 | CEFBS_IsARM, // BMOVPCRX_CALL = 311 |
| 36032 | CEFBS_IsARM, // BR_JTadd = 312 |
| 36033 | CEFBS_IsARM, // BR_JTm_i12 = 313 |
| 36034 | CEFBS_IsARM, // BR_JTm_rs = 314 |
| 36035 | CEFBS_IsARM, // BR_JTr = 315 |
| 36036 | CEFBS_IsARM_HasV4T, // BX_CALL = 316 |
| 36037 | CEFBS_None, // CMP_SWAP_16 = 317 |
| 36038 | CEFBS_None, // CMP_SWAP_32 = 318 |
| 36039 | CEFBS_None, // CMP_SWAP_64 = 319 |
| 36040 | CEFBS_None, // CMP_SWAP_8 = 320 |
| 36041 | CEFBS_None, // CONSTPOOL_ENTRY = 321 |
| 36042 | CEFBS_None, // COPY_STRUCT_BYVAL_I32 = 322 |
| 36043 | CEFBS_IsARM, // ITasm = 323 |
| 36044 | CEFBS_None, // Int_eh_sjlj_dispatchsetup = 324 |
| 36045 | CEFBS_IsARM, // Int_eh_sjlj_longjmp = 325 |
| 36046 | CEFBS_IsARM_HasVFP2, // Int_eh_sjlj_setjmp = 326 |
| 36047 | CEFBS_IsARM, // Int_eh_sjlj_setjmp_nofp = 327 |
| 36048 | CEFBS_None, // Int_eh_sjlj_setup_dispatch = 328 |
| 36049 | CEFBS_None, // JUMPTABLE_ADDRS = 329 |
| 36050 | CEFBS_None, // JUMPTABLE_INSTS = 330 |
| 36051 | CEFBS_None, // JUMPTABLE_TBB = 331 |
| 36052 | CEFBS_None, // JUMPTABLE_TBH = 332 |
| 36053 | CEFBS_IsARM, // LDMIA_RET = 333 |
| 36054 | CEFBS_IsARM, // LDRBT_POST = 334 |
| 36055 | CEFBS_IsARM, // LDRConstPool = 335 |
| 36056 | CEFBS_IsARM, // LDRHTii = 336 |
| 36057 | CEFBS_IsARM, // LDRLIT_ga_abs = 337 |
| 36058 | CEFBS_IsARM, // LDRLIT_ga_pcrel = 338 |
| 36059 | CEFBS_IsARM, // LDRLIT_ga_pcrel_ldr = 339 |
| 36060 | CEFBS_IsARM, // LDRSBTii = 340 |
| 36061 | CEFBS_IsARM, // LDRSHTii = 341 |
| 36062 | CEFBS_IsARM, // LDRT_POST = 342 |
| 36063 | CEFBS_IsARM, // LEApcrel = 343 |
| 36064 | CEFBS_IsARM, // LEApcrelJT = 344 |
| 36065 | CEFBS_IsARM_HasV5TE, // LOADDUAL = 345 |
| 36066 | CEFBS_IsARM, // LSLi = 346 |
| 36067 | CEFBS_IsARM, // LSLr = 347 |
| 36068 | CEFBS_IsARM, // LSRi = 348 |
| 36069 | CEFBS_IsARM, // LSRr = 349 |
| 36070 | CEFBS_None, // MEMCPY = 350 |
| 36071 | CEFBS_IsARM, // MLAv5 = 351 |
| 36072 | CEFBS_IsARM, // MOVCCi = 352 |
| 36073 | CEFBS_IsARM_HasV6T2, // MOVCCi16 = 353 |
| 36074 | CEFBS_IsARM_HasV6T2, // MOVCCi32imm = 354 |
| 36075 | CEFBS_IsARM, // MOVCCr = 355 |
| 36076 | CEFBS_IsARM, // MOVCCsi = 356 |
| 36077 | CEFBS_IsARM, // MOVCCsr = 357 |
| 36078 | CEFBS_IsARM, // MOVPCRX = 358 |
| 36079 | CEFBS_None, // MOVTi16_ga_pcrel = 359 |
| 36080 | CEFBS_IsARM, // MOV_ga_pcrel = 360 |
| 36081 | CEFBS_IsARM, // MOV_ga_pcrel_ldr = 361 |
| 36082 | CEFBS_None, // MOVi16_ga_pcrel = 362 |
| 36083 | CEFBS_IsARM, // MOVi32imm = 363 |
| 36084 | CEFBS_IsARM, // MOVsra_glue = 364 |
| 36085 | CEFBS_IsARM, // MOVsrl_glue = 365 |
| 36086 | CEFBS_HasMVEInt, // MQPRCopy = 366 |
| 36087 | CEFBS_HasMVEInt, // MQQPRLoad = 367 |
| 36088 | CEFBS_HasMVEInt, // MQQPRStore = 368 |
| 36089 | CEFBS_HasMVEInt, // MQQQQPRLoad = 369 |
| 36090 | CEFBS_HasMVEInt, // MQQQQPRStore = 370 |
| 36091 | CEFBS_IsARM, // MULv5 = 371 |
| 36092 | CEFBS_None, // MVE_MEMCPYLOOPINST = 372 |
| 36093 | CEFBS_None, // MVE_MEMSETLOOPINST = 373 |
| 36094 | CEFBS_IsARM, // MVNCCi = 374 |
| 36095 | CEFBS_IsARM, // PICADD = 375 |
| 36096 | CEFBS_IsARM, // PICLDR = 376 |
| 36097 | CEFBS_IsARM, // PICLDRB = 377 |
| 36098 | CEFBS_IsARM, // PICLDRH = 378 |
| 36099 | CEFBS_IsARM, // PICLDRSB = 379 |
| 36100 | CEFBS_IsARM, // PICLDRSH = 380 |
| 36101 | CEFBS_IsARM, // PICSTR = 381 |
| 36102 | CEFBS_IsARM, // PICSTRB = 382 |
| 36103 | CEFBS_IsARM, // PICSTRH = 383 |
| 36104 | CEFBS_None, // PseudoARMInitUndefDPR_VFP2 = 384 |
| 36105 | CEFBS_None, // PseudoARMInitUndefGPR = 385 |
| 36106 | CEFBS_None, // PseudoARMInitUndefMQPR = 386 |
| 36107 | CEFBS_None, // PseudoARMInitUndefSPR = 387 |
| 36108 | CEFBS_IsARM, // RORi = 388 |
| 36109 | CEFBS_IsARM, // RORr = 389 |
| 36110 | CEFBS_IsARM, // RRX = 390 |
| 36111 | CEFBS_IsARM, // RRXi = 391 |
| 36112 | CEFBS_IsARM, // RSBSri = 392 |
| 36113 | CEFBS_IsARM, // RSBSrsi = 393 |
| 36114 | CEFBS_IsARM, // RSBSrsr = 394 |
| 36115 | CEFBS_None, // SEH_EpilogEnd = 395 |
| 36116 | CEFBS_None, // SEH_EpilogStart = 396 |
| 36117 | CEFBS_None, // SEH_Nop = 397 |
| 36118 | CEFBS_None, // SEH_Nop_Ret = 398 |
| 36119 | CEFBS_None, // SEH_PrologEnd = 399 |
| 36120 | CEFBS_None, // SEH_SaveFRegs = 400 |
| 36121 | CEFBS_None, // SEH_SaveLR = 401 |
| 36122 | CEFBS_None, // SEH_SaveRegs = 402 |
| 36123 | CEFBS_None, // SEH_SaveRegs_Ret = 403 |
| 36124 | CEFBS_None, // SEH_SaveSP = 404 |
| 36125 | CEFBS_None, // SEH_StackAlloc = 405 |
| 36126 | CEFBS_IsARM, // SMLALv5 = 406 |
| 36127 | CEFBS_IsARM, // SMULLv5 = 407 |
| 36128 | CEFBS_None, // SPACE = 408 |
| 36129 | CEFBS_IsARM_HasV5TE, // STOREDUAL = 409 |
| 36130 | CEFBS_IsARM, // STRBT_POST = 410 |
| 36131 | CEFBS_IsARM, // STRBi_preidx = 411 |
| 36132 | CEFBS_IsARM, // STRBr_preidx = 412 |
| 36133 | CEFBS_IsARM, // STRH_preidx = 413 |
| 36134 | CEFBS_IsARM, // STRT_POST = 414 |
| 36135 | CEFBS_IsARM, // STRi_preidx = 415 |
| 36136 | CEFBS_IsARM, // STRr_preidx = 416 |
| 36137 | CEFBS_IsARM, // SUBS_PC_LR = 417 |
| 36138 | CEFBS_IsARM, // SUBSri = 418 |
| 36139 | CEFBS_IsARM, // SUBSrr = 419 |
| 36140 | CEFBS_IsARM, // SUBSrsi = 420 |
| 36141 | CEFBS_IsARM, // SUBSrsr = 421 |
| 36142 | CEFBS_None, // SpeculationBarrierISBDSBEndBB = 422 |
| 36143 | CEFBS_None, // SpeculationBarrierSBEndBB = 423 |
| 36144 | CEFBS_IsARM, // TAILJMPd = 424 |
| 36145 | CEFBS_IsARM_HasV4T, // TAILJMPr = 425 |
| 36146 | CEFBS_IsARM, // TAILJMPr4 = 426 |
| 36147 | CEFBS_None, // TCRETURNdi = 427 |
| 36148 | CEFBS_None, // TCRETURNri = 428 |
| 36149 | CEFBS_None, // TCRETURNrinotr12 = 429 |
| 36150 | CEFBS_IsARM, // TPsoft = 430 |
| 36151 | CEFBS_IsARM, // UMLALv5 = 431 |
| 36152 | CEFBS_IsARM, // UMULLv5 = 432 |
| 36153 | CEFBS_HasNEON, // VLD1LNdAsm_16 = 433 |
| 36154 | CEFBS_HasNEON, // VLD1LNdAsm_32 = 434 |
| 36155 | CEFBS_HasNEON, // VLD1LNdAsm_8 = 435 |
| 36156 | CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_16 = 436 |
| 36157 | CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_32 = 437 |
| 36158 | CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_8 = 438 |
| 36159 | CEFBS_HasNEON, // VLD1LNdWB_register_Asm_16 = 439 |
| 36160 | CEFBS_HasNEON, // VLD1LNdWB_register_Asm_32 = 440 |
| 36161 | CEFBS_HasNEON, // VLD1LNdWB_register_Asm_8 = 441 |
| 36162 | CEFBS_HasNEON, // VLD2LNdAsm_16 = 442 |
| 36163 | CEFBS_HasNEON, // VLD2LNdAsm_32 = 443 |
| 36164 | CEFBS_HasNEON, // VLD2LNdAsm_8 = 444 |
| 36165 | CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_16 = 445 |
| 36166 | CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_32 = 446 |
| 36167 | CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_8 = 447 |
| 36168 | CEFBS_HasNEON, // VLD2LNdWB_register_Asm_16 = 448 |
| 36169 | CEFBS_HasNEON, // VLD2LNdWB_register_Asm_32 = 449 |
| 36170 | CEFBS_HasNEON, // VLD2LNdWB_register_Asm_8 = 450 |
| 36171 | CEFBS_HasNEON, // VLD2LNqAsm_16 = 451 |
| 36172 | CEFBS_HasNEON, // VLD2LNqAsm_32 = 452 |
| 36173 | CEFBS_HasNEON, // VLD2LNqWB_fixed_Asm_16 = 453 |
| 36174 | CEFBS_HasNEON, // VLD2LNqWB_fixed_Asm_32 = 454 |
| 36175 | CEFBS_HasNEON, // VLD2LNqWB_register_Asm_16 = 455 |
| 36176 | CEFBS_HasNEON, // VLD2LNqWB_register_Asm_32 = 456 |
| 36177 | CEFBS_HasNEON, // VLD3DUPdAsm_16 = 457 |
| 36178 | CEFBS_HasNEON, // VLD3DUPdAsm_32 = 458 |
| 36179 | CEFBS_HasNEON, // VLD3DUPdAsm_8 = 459 |
| 36180 | CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_16 = 460 |
| 36181 | CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_32 = 461 |
| 36182 | CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_8 = 462 |
| 36183 | CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_16 = 463 |
| 36184 | CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_32 = 464 |
| 36185 | CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_8 = 465 |
| 36186 | CEFBS_HasNEON, // VLD3DUPqAsm_16 = 466 |
| 36187 | CEFBS_HasNEON, // VLD3DUPqAsm_32 = 467 |
| 36188 | CEFBS_HasNEON, // VLD3DUPqAsm_8 = 468 |
| 36189 | CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_16 = 469 |
| 36190 | CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_32 = 470 |
| 36191 | CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_8 = 471 |
| 36192 | CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_16 = 472 |
| 36193 | CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_32 = 473 |
| 36194 | CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_8 = 474 |
| 36195 | CEFBS_HasNEON, // VLD3LNdAsm_16 = 475 |
| 36196 | CEFBS_HasNEON, // VLD3LNdAsm_32 = 476 |
| 36197 | CEFBS_HasNEON, // VLD3LNdAsm_8 = 477 |
| 36198 | CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_16 = 478 |
| 36199 | CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_32 = 479 |
| 36200 | CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_8 = 480 |
| 36201 | CEFBS_HasNEON, // VLD3LNdWB_register_Asm_16 = 481 |
| 36202 | CEFBS_HasNEON, // VLD3LNdWB_register_Asm_32 = 482 |
| 36203 | CEFBS_HasNEON, // VLD3LNdWB_register_Asm_8 = 483 |
| 36204 | CEFBS_HasNEON, // VLD3LNqAsm_16 = 484 |
| 36205 | CEFBS_HasNEON, // VLD3LNqAsm_32 = 485 |
| 36206 | CEFBS_HasNEON, // VLD3LNqWB_fixed_Asm_16 = 486 |
| 36207 | CEFBS_HasNEON, // VLD3LNqWB_fixed_Asm_32 = 487 |
| 36208 | CEFBS_HasNEON, // VLD3LNqWB_register_Asm_16 = 488 |
| 36209 | CEFBS_HasNEON, // VLD3LNqWB_register_Asm_32 = 489 |
| 36210 | CEFBS_HasNEON, // VLD3dAsm_16 = 490 |
| 36211 | CEFBS_HasNEON, // VLD3dAsm_32 = 491 |
| 36212 | CEFBS_HasNEON, // VLD3dAsm_8 = 492 |
| 36213 | CEFBS_HasNEON, // VLD3dWB_fixed_Asm_16 = 493 |
| 36214 | CEFBS_HasNEON, // VLD3dWB_fixed_Asm_32 = 494 |
| 36215 | CEFBS_HasNEON, // VLD3dWB_fixed_Asm_8 = 495 |
| 36216 | CEFBS_HasNEON, // VLD3dWB_register_Asm_16 = 496 |
| 36217 | CEFBS_HasNEON, // VLD3dWB_register_Asm_32 = 497 |
| 36218 | CEFBS_HasNEON, // VLD3dWB_register_Asm_8 = 498 |
| 36219 | CEFBS_HasNEON, // VLD3qAsm_16 = 499 |
| 36220 | CEFBS_HasNEON, // VLD3qAsm_32 = 500 |
| 36221 | CEFBS_HasNEON, // VLD3qAsm_8 = 501 |
| 36222 | CEFBS_HasNEON, // VLD3qWB_fixed_Asm_16 = 502 |
| 36223 | CEFBS_HasNEON, // VLD3qWB_fixed_Asm_32 = 503 |
| 36224 | CEFBS_HasNEON, // VLD3qWB_fixed_Asm_8 = 504 |
| 36225 | CEFBS_HasNEON, // VLD3qWB_register_Asm_16 = 505 |
| 36226 | CEFBS_HasNEON, // VLD3qWB_register_Asm_32 = 506 |
| 36227 | CEFBS_HasNEON, // VLD3qWB_register_Asm_8 = 507 |
| 36228 | CEFBS_HasNEON, // VLD4DUPdAsm_16 = 508 |
| 36229 | CEFBS_HasNEON, // VLD4DUPdAsm_32 = 509 |
| 36230 | CEFBS_HasNEON, // VLD4DUPdAsm_8 = 510 |
| 36231 | CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_16 = 511 |
| 36232 | CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_32 = 512 |
| 36233 | CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_8 = 513 |
| 36234 | CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_16 = 514 |
| 36235 | CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_32 = 515 |
| 36236 | CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_8 = 516 |
| 36237 | CEFBS_HasNEON, // VLD4DUPqAsm_16 = 517 |
| 36238 | CEFBS_HasNEON, // VLD4DUPqAsm_32 = 518 |
| 36239 | CEFBS_HasNEON, // VLD4DUPqAsm_8 = 519 |
| 36240 | CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_16 = 520 |
| 36241 | CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_32 = 521 |
| 36242 | CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_8 = 522 |
| 36243 | CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_16 = 523 |
| 36244 | CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_32 = 524 |
| 36245 | CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_8 = 525 |
| 36246 | CEFBS_HasNEON, // VLD4LNdAsm_16 = 526 |
| 36247 | CEFBS_HasNEON, // VLD4LNdAsm_32 = 527 |
| 36248 | CEFBS_HasNEON, // VLD4LNdAsm_8 = 528 |
| 36249 | CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_16 = 529 |
| 36250 | CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_32 = 530 |
| 36251 | CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_8 = 531 |
| 36252 | CEFBS_HasNEON, // VLD4LNdWB_register_Asm_16 = 532 |
| 36253 | CEFBS_HasNEON, // VLD4LNdWB_register_Asm_32 = 533 |
| 36254 | CEFBS_HasNEON, // VLD4LNdWB_register_Asm_8 = 534 |
| 36255 | CEFBS_HasNEON, // VLD4LNqAsm_16 = 535 |
| 36256 | CEFBS_HasNEON, // VLD4LNqAsm_32 = 536 |
| 36257 | CEFBS_HasNEON, // VLD4LNqWB_fixed_Asm_16 = 537 |
| 36258 | CEFBS_HasNEON, // VLD4LNqWB_fixed_Asm_32 = 538 |
| 36259 | CEFBS_HasNEON, // VLD4LNqWB_register_Asm_16 = 539 |
| 36260 | CEFBS_HasNEON, // VLD4LNqWB_register_Asm_32 = 540 |
| 36261 | CEFBS_HasNEON, // VLD4dAsm_16 = 541 |
| 36262 | CEFBS_HasNEON, // VLD4dAsm_32 = 542 |
| 36263 | CEFBS_HasNEON, // VLD4dAsm_8 = 543 |
| 36264 | CEFBS_HasNEON, // VLD4dWB_fixed_Asm_16 = 544 |
| 36265 | CEFBS_HasNEON, // VLD4dWB_fixed_Asm_32 = 545 |
| 36266 | CEFBS_HasNEON, // VLD4dWB_fixed_Asm_8 = 546 |
| 36267 | CEFBS_HasNEON, // VLD4dWB_register_Asm_16 = 547 |
| 36268 | CEFBS_HasNEON, // VLD4dWB_register_Asm_32 = 548 |
| 36269 | CEFBS_HasNEON, // VLD4dWB_register_Asm_8 = 549 |
| 36270 | CEFBS_HasNEON, // VLD4qAsm_16 = 550 |
| 36271 | CEFBS_HasNEON, // VLD4qAsm_32 = 551 |
| 36272 | CEFBS_HasNEON, // VLD4qAsm_8 = 552 |
| 36273 | CEFBS_HasNEON, // VLD4qWB_fixed_Asm_16 = 553 |
| 36274 | CEFBS_HasNEON, // VLD4qWB_fixed_Asm_32 = 554 |
| 36275 | CEFBS_HasNEON, // VLD4qWB_fixed_Asm_8 = 555 |
| 36276 | CEFBS_HasNEON, // VLD4qWB_register_Asm_16 = 556 |
| 36277 | CEFBS_HasNEON, // VLD4qWB_register_Asm_32 = 557 |
| 36278 | CEFBS_HasNEON, // VLD4qWB_register_Asm_8 = 558 |
| 36279 | CEFBS_None, // VMOVD0 = 559 |
| 36280 | CEFBS_HasFPRegs64, // VMOVDcc = 560 |
| 36281 | CEFBS_HasFPRegs, // VMOVHcc = 561 |
| 36282 | CEFBS_None, // VMOVQ0 = 562 |
| 36283 | CEFBS_HasFPRegs, // VMOVScc = 563 |
| 36284 | CEFBS_HasNEON, // VST1LNdAsm_16 = 564 |
| 36285 | CEFBS_HasNEON, // VST1LNdAsm_32 = 565 |
| 36286 | CEFBS_HasNEON, // VST1LNdAsm_8 = 566 |
| 36287 | CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_16 = 567 |
| 36288 | CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_32 = 568 |
| 36289 | CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_8 = 569 |
| 36290 | CEFBS_HasNEON, // VST1LNdWB_register_Asm_16 = 570 |
| 36291 | CEFBS_HasNEON, // VST1LNdWB_register_Asm_32 = 571 |
| 36292 | CEFBS_HasNEON, // VST1LNdWB_register_Asm_8 = 572 |
| 36293 | CEFBS_HasNEON, // VST2LNdAsm_16 = 573 |
| 36294 | CEFBS_HasNEON, // VST2LNdAsm_32 = 574 |
| 36295 | CEFBS_HasNEON, // VST2LNdAsm_8 = 575 |
| 36296 | CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_16 = 576 |
| 36297 | CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_32 = 577 |
| 36298 | CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_8 = 578 |
| 36299 | CEFBS_HasNEON, // VST2LNdWB_register_Asm_16 = 579 |
| 36300 | CEFBS_HasNEON, // VST2LNdWB_register_Asm_32 = 580 |
| 36301 | CEFBS_HasNEON, // VST2LNdWB_register_Asm_8 = 581 |
| 36302 | CEFBS_HasNEON, // VST2LNqAsm_16 = 582 |
| 36303 | CEFBS_HasNEON, // VST2LNqAsm_32 = 583 |
| 36304 | CEFBS_HasNEON, // VST2LNqWB_fixed_Asm_16 = 584 |
| 36305 | CEFBS_HasNEON, // VST2LNqWB_fixed_Asm_32 = 585 |
| 36306 | CEFBS_HasNEON, // VST2LNqWB_register_Asm_16 = 586 |
| 36307 | CEFBS_HasNEON, // VST2LNqWB_register_Asm_32 = 587 |
| 36308 | CEFBS_HasNEON, // VST3LNdAsm_16 = 588 |
| 36309 | CEFBS_HasNEON, // VST3LNdAsm_32 = 589 |
| 36310 | CEFBS_HasNEON, // VST3LNdAsm_8 = 590 |
| 36311 | CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_16 = 591 |
| 36312 | CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_32 = 592 |
| 36313 | CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_8 = 593 |
| 36314 | CEFBS_HasNEON, // VST3LNdWB_register_Asm_16 = 594 |
| 36315 | CEFBS_HasNEON, // VST3LNdWB_register_Asm_32 = 595 |
| 36316 | CEFBS_HasNEON, // VST3LNdWB_register_Asm_8 = 596 |
| 36317 | CEFBS_HasNEON, // VST3LNqAsm_16 = 597 |
| 36318 | CEFBS_HasNEON, // VST3LNqAsm_32 = 598 |
| 36319 | CEFBS_HasNEON, // VST3LNqWB_fixed_Asm_16 = 599 |
| 36320 | CEFBS_HasNEON, // VST3LNqWB_fixed_Asm_32 = 600 |
| 36321 | CEFBS_HasNEON, // VST3LNqWB_register_Asm_16 = 601 |
| 36322 | CEFBS_HasNEON, // VST3LNqWB_register_Asm_32 = 602 |
| 36323 | CEFBS_HasNEON, // VST3dAsm_16 = 603 |
| 36324 | CEFBS_HasNEON, // VST3dAsm_32 = 604 |
| 36325 | CEFBS_HasNEON, // VST3dAsm_8 = 605 |
| 36326 | CEFBS_HasNEON, // VST3dWB_fixed_Asm_16 = 606 |
| 36327 | CEFBS_HasNEON, // VST3dWB_fixed_Asm_32 = 607 |
| 36328 | CEFBS_HasNEON, // VST3dWB_fixed_Asm_8 = 608 |
| 36329 | CEFBS_HasNEON, // VST3dWB_register_Asm_16 = 609 |
| 36330 | CEFBS_HasNEON, // VST3dWB_register_Asm_32 = 610 |
| 36331 | CEFBS_HasNEON, // VST3dWB_register_Asm_8 = 611 |
| 36332 | CEFBS_HasNEON, // VST3qAsm_16 = 612 |
| 36333 | CEFBS_HasNEON, // VST3qAsm_32 = 613 |
| 36334 | CEFBS_HasNEON, // VST3qAsm_8 = 614 |
| 36335 | CEFBS_HasNEON, // VST3qWB_fixed_Asm_16 = 615 |
| 36336 | CEFBS_HasNEON, // VST3qWB_fixed_Asm_32 = 616 |
| 36337 | CEFBS_HasNEON, // VST3qWB_fixed_Asm_8 = 617 |
| 36338 | CEFBS_HasNEON, // VST3qWB_register_Asm_16 = 618 |
| 36339 | CEFBS_HasNEON, // VST3qWB_register_Asm_32 = 619 |
| 36340 | CEFBS_HasNEON, // VST3qWB_register_Asm_8 = 620 |
| 36341 | CEFBS_HasNEON, // VST4LNdAsm_16 = 621 |
| 36342 | CEFBS_HasNEON, // VST4LNdAsm_32 = 622 |
| 36343 | CEFBS_HasNEON, // VST4LNdAsm_8 = 623 |
| 36344 | CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_16 = 624 |
| 36345 | CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_32 = 625 |
| 36346 | CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_8 = 626 |
| 36347 | CEFBS_HasNEON, // VST4LNdWB_register_Asm_16 = 627 |
| 36348 | CEFBS_HasNEON, // VST4LNdWB_register_Asm_32 = 628 |
| 36349 | CEFBS_HasNEON, // VST4LNdWB_register_Asm_8 = 629 |
| 36350 | CEFBS_HasNEON, // VST4LNqAsm_16 = 630 |
| 36351 | CEFBS_HasNEON, // VST4LNqAsm_32 = 631 |
| 36352 | CEFBS_HasNEON, // VST4LNqWB_fixed_Asm_16 = 632 |
| 36353 | CEFBS_HasNEON, // VST4LNqWB_fixed_Asm_32 = 633 |
| 36354 | CEFBS_HasNEON, // VST4LNqWB_register_Asm_16 = 634 |
| 36355 | CEFBS_HasNEON, // VST4LNqWB_register_Asm_32 = 635 |
| 36356 | CEFBS_HasNEON, // VST4dAsm_16 = 636 |
| 36357 | CEFBS_HasNEON, // VST4dAsm_32 = 637 |
| 36358 | CEFBS_HasNEON, // VST4dAsm_8 = 638 |
| 36359 | CEFBS_HasNEON, // VST4dWB_fixed_Asm_16 = 639 |
| 36360 | CEFBS_HasNEON, // VST4dWB_fixed_Asm_32 = 640 |
| 36361 | CEFBS_HasNEON, // VST4dWB_fixed_Asm_8 = 641 |
| 36362 | CEFBS_HasNEON, // VST4dWB_register_Asm_16 = 642 |
| 36363 | CEFBS_HasNEON, // VST4dWB_register_Asm_32 = 643 |
| 36364 | CEFBS_HasNEON, // VST4dWB_register_Asm_8 = 644 |
| 36365 | CEFBS_HasNEON, // VST4qAsm_16 = 645 |
| 36366 | CEFBS_HasNEON, // VST4qAsm_32 = 646 |
| 36367 | CEFBS_HasNEON, // VST4qAsm_8 = 647 |
| 36368 | CEFBS_HasNEON, // VST4qWB_fixed_Asm_16 = 648 |
| 36369 | CEFBS_HasNEON, // VST4qWB_fixed_Asm_32 = 649 |
| 36370 | CEFBS_HasNEON, // VST4qWB_fixed_Asm_8 = 650 |
| 36371 | CEFBS_HasNEON, // VST4qWB_register_Asm_16 = 651 |
| 36372 | CEFBS_HasNEON, // VST4qWB_register_Asm_32 = 652 |
| 36373 | CEFBS_HasNEON, // VST4qWB_register_Asm_8 = 653 |
| 36374 | CEFBS_None, // WIN__CHKSTK = 654 |
| 36375 | CEFBS_None, // WIN__DBZCHK = 655 |
| 36376 | CEFBS_IsThumb2, // t2ABS = 656 |
| 36377 | CEFBS_IsThumb2, // t2ADDSri = 657 |
| 36378 | CEFBS_IsThumb2, // t2ADDSrr = 658 |
| 36379 | CEFBS_IsThumb2, // t2ADDSrs = 659 |
| 36380 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BF_LabelPseudo = 660 |
| 36381 | CEFBS_IsThumb_HasV8MBaseline, // t2BR_JT = 661 |
| 36382 | CEFBS_IsThumb2, // t2CALL_BTI = 662 |
| 36383 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2DoLoopStart = 663 |
| 36384 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2DoLoopStartTP = 664 |
| 36385 | CEFBS_IsThumb2, // t2LDMIA_RET = 665 |
| 36386 | CEFBS_IsThumb2, // t2LDRB_OFFSET_imm = 666 |
| 36387 | CEFBS_IsThumb2, // t2LDRB_POST_imm = 667 |
| 36388 | CEFBS_IsThumb2, // t2LDRB_PRE_imm = 668 |
| 36389 | CEFBS_IsThumb2, // t2LDRBpcrel = 669 |
| 36390 | CEFBS_IsThumb2, // t2LDRConstPool = 670 |
| 36391 | CEFBS_IsThumb2, // t2LDRH_OFFSET_imm = 671 |
| 36392 | CEFBS_IsThumb2, // t2LDRH_POST_imm = 672 |
| 36393 | CEFBS_IsThumb2, // t2LDRH_PRE_imm = 673 |
| 36394 | CEFBS_IsThumb2, // t2LDRHpcrel = 674 |
| 36395 | CEFBS_IsThumb_HasV8MBaseline, // t2LDRLIT_ga_pcrel = 675 |
| 36396 | CEFBS_IsThumb2, // t2LDRSB_OFFSET_imm = 676 |
| 36397 | CEFBS_IsThumb2, // t2LDRSB_POST_imm = 677 |
| 36398 | CEFBS_IsThumb2, // t2LDRSB_PRE_imm = 678 |
| 36399 | CEFBS_IsThumb2, // t2LDRSBpcrel = 679 |
| 36400 | CEFBS_IsThumb2, // t2LDRSH_OFFSET_imm = 680 |
| 36401 | CEFBS_IsThumb2, // t2LDRSH_POST_imm = 681 |
| 36402 | CEFBS_IsThumb2, // t2LDRSH_PRE_imm = 682 |
| 36403 | CEFBS_IsThumb2, // t2LDRSHpcrel = 683 |
| 36404 | CEFBS_IsThumb2, // t2LDR_POST_imm = 684 |
| 36405 | CEFBS_IsThumb2, // t2LDR_PRE_imm = 685 |
| 36406 | CEFBS_IsThumb2, // t2LDRpci_pic = 686 |
| 36407 | CEFBS_IsThumb2, // t2LDRpcrel = 687 |
| 36408 | CEFBS_IsThumb2, // t2LEApcrel = 688 |
| 36409 | CEFBS_IsThumb2, // t2LEApcrelJT = 689 |
| 36410 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LoopDec = 690 |
| 36411 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LoopEnd = 691 |
| 36412 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LoopEndDec = 692 |
| 36413 | CEFBS_IsThumb2, // t2MOVCCasr = 693 |
| 36414 | CEFBS_IsThumb2, // t2MOVCCi = 694 |
| 36415 | CEFBS_IsThumb2, // t2MOVCCi16 = 695 |
| 36416 | CEFBS_IsThumb2, // t2MOVCCi32imm = 696 |
| 36417 | CEFBS_IsThumb2, // t2MOVCClsl = 697 |
| 36418 | CEFBS_IsThumb2, // t2MOVCClsr = 698 |
| 36419 | CEFBS_IsThumb2, // t2MOVCCr = 699 |
| 36420 | CEFBS_IsThumb2, // t2MOVCCror = 700 |
| 36421 | CEFBS_IsThumb2, // t2MOVSsi = 701 |
| 36422 | CEFBS_IsThumb2, // t2MOVSsr = 702 |
| 36423 | CEFBS_IsThumb_HasV8MBaseline, // t2MOVTi16_ga_pcrel = 703 |
| 36424 | CEFBS_IsThumb_HasV8MBaseline, // t2MOV_ga_pcrel = 704 |
| 36425 | CEFBS_None, // t2MOVi16_ga_pcrel = 705 |
| 36426 | CEFBS_IsThumb, // t2MOVi32imm = 706 |
| 36427 | CEFBS_IsThumb2, // t2MOVsi = 707 |
| 36428 | CEFBS_IsThumb2, // t2MOVsr = 708 |
| 36429 | CEFBS_IsThumb2, // t2MVNCCi = 709 |
| 36430 | CEFBS_IsThumb2, // t2RSBSri = 710 |
| 36431 | CEFBS_IsThumb2, // t2RSBSrs = 711 |
| 36432 | CEFBS_IsThumb2, // t2STRB_OFFSET_imm = 712 |
| 36433 | CEFBS_IsThumb2, // t2STRB_POST_imm = 713 |
| 36434 | CEFBS_IsThumb2, // t2STRB_PRE_imm = 714 |
| 36435 | CEFBS_IsThumb2, // t2STRB_preidx = 715 |
| 36436 | CEFBS_IsThumb2, // t2STRH_OFFSET_imm = 716 |
| 36437 | CEFBS_IsThumb2, // t2STRH_POST_imm = 717 |
| 36438 | CEFBS_IsThumb2, // t2STRH_PRE_imm = 718 |
| 36439 | CEFBS_IsThumb2, // t2STRH_preidx = 719 |
| 36440 | CEFBS_IsThumb2, // t2STR_POST_imm = 720 |
| 36441 | CEFBS_IsThumb2, // t2STR_PRE_imm = 721 |
| 36442 | CEFBS_IsThumb2, // t2STR_preidx = 722 |
| 36443 | CEFBS_IsThumb2, // t2SUBSri = 723 |
| 36444 | CEFBS_IsThumb2, // t2SUBSrr = 724 |
| 36445 | CEFBS_IsThumb2, // t2SUBSrs = 725 |
| 36446 | CEFBS_None, // t2SpeculationBarrierISBDSBEndBB = 726 |
| 36447 | CEFBS_None, // t2SpeculationBarrierSBEndBB = 727 |
| 36448 | CEFBS_IsThumb2, // t2TBB_JT = 728 |
| 36449 | CEFBS_IsThumb2, // t2TBH_JT = 729 |
| 36450 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WhileLoopSetup = 730 |
| 36451 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WhileLoopStart = 731 |
| 36452 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WhileLoopStartLR = 732 |
| 36453 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WhileLoopStartTP = 733 |
| 36454 | CEFBS_None, // tADCS = 734 |
| 36455 | CEFBS_None, // tADDSi3 = 735 |
| 36456 | CEFBS_None, // tADDSi8 = 736 |
| 36457 | CEFBS_None, // tADDSrr = 737 |
| 36458 | CEFBS_IsThumb, // tADDframe = 738 |
| 36459 | CEFBS_IsThumb, // tADJCALLSTACKDOWN = 739 |
| 36460 | CEFBS_IsThumb, // tADJCALLSTACKUP = 740 |
| 36461 | CEFBS_IsThumb_Has8MSecExt, // tBLXNS_CALL = 741 |
| 36462 | CEFBS_IsThumb_HasV5T, // tBLXr_noip = 742 |
| 36463 | CEFBS_IsThumb, // tBL_PUSHLR = 743 |
| 36464 | CEFBS_IsThumb, // tBRIND = 744 |
| 36465 | CEFBS_IsThumb, // tBR_JTr = 745 |
| 36466 | CEFBS_IsThumb, // tBXNS_RET = 746 |
| 36467 | CEFBS_IsThumb, // tBX_CALL = 747 |
| 36468 | CEFBS_IsThumb, // tBX_RET = 748 |
| 36469 | CEFBS_IsThumb, // tBX_RET_vararg = 749 |
| 36470 | CEFBS_IsThumb, // tBfar = 750 |
| 36471 | CEFBS_None, // tCMP_SWAP_16 = 751 |
| 36472 | CEFBS_None, // tCMP_SWAP_32 = 752 |
| 36473 | CEFBS_None, // tCMP_SWAP_8 = 753 |
| 36474 | CEFBS_IsThumb, // tLDMIA_UPD = 754 |
| 36475 | CEFBS_IsThumb, // tLDRConstPool = 755 |
| 36476 | CEFBS_IsThumb, // tLDRLIT_ga_abs = 756 |
| 36477 | CEFBS_IsThumb, // tLDRLIT_ga_pcrel = 757 |
| 36478 | CEFBS_IsThumb, // tLDR_postidx = 758 |
| 36479 | CEFBS_IsThumb, // tLDRpci_pic = 759 |
| 36480 | CEFBS_IsThumb, // tLEApcrel = 760 |
| 36481 | CEFBS_IsThumb, // tLEApcrelJT = 761 |
| 36482 | CEFBS_None, // tLSLSri = 762 |
| 36483 | CEFBS_None, // tMOVCCr_pseudo = 763 |
| 36484 | CEFBS_None, // tMOVi32imm = 764 |
| 36485 | CEFBS_IsThumb, // tPOP_RET = 765 |
| 36486 | CEFBS_None, // tRSBS = 766 |
| 36487 | CEFBS_None, // tSBCS = 767 |
| 36488 | CEFBS_None, // tSUBSi3 = 768 |
| 36489 | CEFBS_None, // tSUBSi8 = 769 |
| 36490 | CEFBS_None, // tSUBSrr = 770 |
| 36491 | CEFBS_IsThumb2, // tTAILJMPd = 771 |
| 36492 | CEFBS_IsThumb, // tTAILJMPdND = 772 |
| 36493 | CEFBS_IsThumb, // tTAILJMPr = 773 |
| 36494 | CEFBS_IsThumb, // tTBB_JT = 774 |
| 36495 | CEFBS_IsThumb, // tTBH_JT = 775 |
| 36496 | CEFBS_IsThumb, // tTPsoft = 776 |
| 36497 | CEFBS_IsARM, // ADCri = 777 |
| 36498 | CEFBS_IsARM, // ADCrr = 778 |
| 36499 | CEFBS_IsARM, // ADCrsi = 779 |
| 36500 | CEFBS_IsARM, // ADCrsr = 780 |
| 36501 | CEFBS_IsARM, // ADDri = 781 |
| 36502 | CEFBS_IsARM, // ADDrr = 782 |
| 36503 | CEFBS_IsARM, // ADDrsi = 783 |
| 36504 | CEFBS_IsARM, // ADDrsr = 784 |
| 36505 | CEFBS_IsARM, // ADR = 785 |
| 36506 | CEFBS_HasV8_HasAES, // AESD = 786 |
| 36507 | CEFBS_HasV8_HasAES, // AESE = 787 |
| 36508 | CEFBS_HasV8_HasAES, // AESIMC = 788 |
| 36509 | CEFBS_HasV8_HasAES, // AESMC = 789 |
| 36510 | CEFBS_IsARM, // ANDri = 790 |
| 36511 | CEFBS_IsARM, // ANDrr = 791 |
| 36512 | CEFBS_IsARM, // ANDrsi = 792 |
| 36513 | CEFBS_IsARM, // ANDrsr = 793 |
| 36514 | CEFBS_HasBF16_HasNEON, // BF16VDOTI_VDOTD = 794 |
| 36515 | CEFBS_HasBF16_HasNEON, // BF16VDOTI_VDOTQ = 795 |
| 36516 | CEFBS_HasBF16_HasNEON, // BF16VDOTS_VDOTD = 796 |
| 36517 | CEFBS_HasBF16_HasNEON, // BF16VDOTS_VDOTQ = 797 |
| 36518 | CEFBS_HasBF16_HasNEON, // BF16_VCVT = 798 |
| 36519 | CEFBS_HasBF16, // BF16_VCVTB = 799 |
| 36520 | CEFBS_HasBF16, // BF16_VCVTT = 800 |
| 36521 | CEFBS_IsARM_HasV6T2, // BFC = 801 |
| 36522 | CEFBS_IsARM_HasV6T2, // BFI = 802 |
| 36523 | CEFBS_IsARM, // BICri = 803 |
| 36524 | CEFBS_IsARM, // BICrr = 804 |
| 36525 | CEFBS_IsARM, // BICrsi = 805 |
| 36526 | CEFBS_IsARM, // BICrsr = 806 |
| 36527 | CEFBS_IsARM, // BKPT = 807 |
| 36528 | CEFBS_IsARM, // BL = 808 |
| 36529 | CEFBS_IsARM_HasV5T, // BLX = 809 |
| 36530 | CEFBS_IsARM_HasV5T, // BLX_pred = 810 |
| 36531 | CEFBS_IsARM_HasV5T, // BLXi = 811 |
| 36532 | CEFBS_IsARM, // BL_pred = 812 |
| 36533 | CEFBS_IsARM_HasV4T, // BX = 813 |
| 36534 | CEFBS_IsARM, // BXJ = 814 |
| 36535 | CEFBS_IsARM_HasV4T, // BX_RET = 815 |
| 36536 | CEFBS_IsARM_HasV4T, // BX_pred = 816 |
| 36537 | CEFBS_IsARM, // Bcc = 817 |
| 36538 | CEFBS_HasCDE, // CDE_CX1 = 818 |
| 36539 | CEFBS_HasCDE, // CDE_CX1A = 819 |
| 36540 | CEFBS_HasCDE, // CDE_CX1D = 820 |
| 36541 | CEFBS_HasCDE, // CDE_CX1DA = 821 |
| 36542 | CEFBS_HasCDE, // CDE_CX2 = 822 |
| 36543 | CEFBS_HasCDE, // CDE_CX2A = 823 |
| 36544 | CEFBS_HasCDE, // CDE_CX2D = 824 |
| 36545 | CEFBS_HasCDE, // CDE_CX2DA = 825 |
| 36546 | CEFBS_HasCDE, // CDE_CX3 = 826 |
| 36547 | CEFBS_HasCDE, // CDE_CX3A = 827 |
| 36548 | CEFBS_HasCDE, // CDE_CX3D = 828 |
| 36549 | CEFBS_HasCDE, // CDE_CX3DA = 829 |
| 36550 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX1A_fpdp = 830 |
| 36551 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX1A_fpsp = 831 |
| 36552 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX1A_vec = 832 |
| 36553 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX1_fpdp = 833 |
| 36554 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX1_fpsp = 834 |
| 36555 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX1_vec = 835 |
| 36556 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX2A_fpdp = 836 |
| 36557 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX2A_fpsp = 837 |
| 36558 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX2A_vec = 838 |
| 36559 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX2_fpdp = 839 |
| 36560 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX2_fpsp = 840 |
| 36561 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX2_vec = 841 |
| 36562 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX3A_fpdp = 842 |
| 36563 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX3A_fpsp = 843 |
| 36564 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX3A_vec = 844 |
| 36565 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX3_fpdp = 845 |
| 36566 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX3_fpsp = 846 |
| 36567 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX3_vec = 847 |
| 36568 | CEFBS_IsARM_PreV8, // CDP = 848 |
| 36569 | CEFBS_IsARM_PreV8, // CDP2 = 849 |
| 36570 | CEFBS_IsARM_HasV6K, // CLREX = 850 |
| 36571 | CEFBS_IsARM_HasV5T, // CLZ = 851 |
| 36572 | CEFBS_IsARM, // CMNri = 852 |
| 36573 | CEFBS_IsARM, // CMNzrr = 853 |
| 36574 | CEFBS_IsARM, // CMNzrsi = 854 |
| 36575 | CEFBS_IsARM, // CMNzrsr = 855 |
| 36576 | CEFBS_IsARM, // CMPri = 856 |
| 36577 | CEFBS_IsARM, // CMPrr = 857 |
| 36578 | CEFBS_IsARM, // CMPrsi = 858 |
| 36579 | CEFBS_IsARM, // CMPrsr = 859 |
| 36580 | CEFBS_IsARM, // CPS1p = 860 |
| 36581 | CEFBS_IsARM, // CPS2p = 861 |
| 36582 | CEFBS_IsARM, // CPS3p = 862 |
| 36583 | CEFBS_IsARM_HasCRC, // CRC32B = 863 |
| 36584 | CEFBS_IsARM_HasCRC, // CRC32CB = 864 |
| 36585 | CEFBS_IsARM_HasCRC, // CRC32CH = 865 |
| 36586 | CEFBS_IsARM_HasCRC, // CRC32CW = 866 |
| 36587 | CEFBS_IsARM_HasCRC, // CRC32H = 867 |
| 36588 | CEFBS_IsARM_HasCRC, // CRC32W = 868 |
| 36589 | CEFBS_IsARM_HasV7, // DBG = 869 |
| 36590 | CEFBS_IsARM_HasDB, // DMB = 870 |
| 36591 | CEFBS_IsARM_HasDB, // DSB = 871 |
| 36592 | CEFBS_IsARM, // EORri = 872 |
| 36593 | CEFBS_IsARM, // EORrr = 873 |
| 36594 | CEFBS_IsARM, // EORrsi = 874 |
| 36595 | CEFBS_IsARM, // EORrsr = 875 |
| 36596 | CEFBS_IsARM_HasVirtualization, // ERET = 876 |
| 36597 | CEFBS_HasVFP3_HasDPVFP, // FCONSTD = 877 |
| 36598 | CEFBS_HasFullFP16, // FCONSTH = 878 |
| 36599 | CEFBS_HasVFP3, // FCONSTS = 879 |
| 36600 | CEFBS_HasFPRegs, // FLDMXDB_UPD = 880 |
| 36601 | CEFBS_HasFPRegs, // FLDMXIA = 881 |
| 36602 | CEFBS_HasFPRegs, // FLDMXIA_UPD = 882 |
| 36603 | CEFBS_HasFPRegs, // FMSTAT = 883 |
| 36604 | CEFBS_HasFPRegs, // FSTMXDB_UPD = 884 |
| 36605 | CEFBS_HasFPRegs, // FSTMXIA = 885 |
| 36606 | CEFBS_HasFPRegs, // FSTMXIA_UPD = 886 |
| 36607 | CEFBS_IsARM_HasV6, // HINT = 887 |
| 36608 | CEFBS_IsARM_HasV8, // HLT = 888 |
| 36609 | CEFBS_IsARM_HasVirtualization, // HVC = 889 |
| 36610 | CEFBS_IsARM_HasDB, // ISB = 890 |
| 36611 | CEFBS_IsARM_HasAcquireRelease, // LDA = 891 |
| 36612 | CEFBS_IsARM_HasAcquireRelease, // LDAB = 892 |
| 36613 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEX = 893 |
| 36614 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXB = 894 |
| 36615 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXD = 895 |
| 36616 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXH = 896 |
| 36617 | CEFBS_IsARM_HasAcquireRelease, // LDAH = 897 |
| 36618 | CEFBS_IsARM_PreV8, // LDC2L_OFFSET = 898 |
| 36619 | CEFBS_IsARM_PreV8, // LDC2L_OPTION = 899 |
| 36620 | CEFBS_IsARM_PreV8, // LDC2L_POST = 900 |
| 36621 | CEFBS_IsARM_PreV8, // LDC2L_PRE = 901 |
| 36622 | CEFBS_IsARM_PreV8, // LDC2_OFFSET = 902 |
| 36623 | CEFBS_IsARM_PreV8, // LDC2_OPTION = 903 |
| 36624 | CEFBS_IsARM_PreV8, // LDC2_POST = 904 |
| 36625 | CEFBS_IsARM_PreV8, // LDC2_PRE = 905 |
| 36626 | CEFBS_IsARM, // LDCL_OFFSET = 906 |
| 36627 | CEFBS_IsARM, // LDCL_OPTION = 907 |
| 36628 | CEFBS_IsARM, // LDCL_POST = 908 |
| 36629 | CEFBS_IsARM, // LDCL_PRE = 909 |
| 36630 | CEFBS_IsARM, // LDC_OFFSET = 910 |
| 36631 | CEFBS_IsARM, // LDC_OPTION = 911 |
| 36632 | CEFBS_IsARM, // LDC_POST = 912 |
| 36633 | CEFBS_IsARM, // LDC_PRE = 913 |
| 36634 | CEFBS_IsARM, // LDMDA = 914 |
| 36635 | CEFBS_IsARM, // LDMDA_UPD = 915 |
| 36636 | CEFBS_IsARM, // LDMDB = 916 |
| 36637 | CEFBS_IsARM, // LDMDB_UPD = 917 |
| 36638 | CEFBS_IsARM, // LDMIA = 918 |
| 36639 | CEFBS_IsARM, // LDMIA_UPD = 919 |
| 36640 | CEFBS_IsARM, // LDMIB = 920 |
| 36641 | CEFBS_IsARM, // LDMIB_UPD = 921 |
| 36642 | CEFBS_IsARM, // LDRBT_POST_IMM = 922 |
| 36643 | CEFBS_IsARM, // LDRBT_POST_REG = 923 |
| 36644 | CEFBS_IsARM, // LDRB_POST_IMM = 924 |
| 36645 | CEFBS_IsARM, // LDRB_POST_REG = 925 |
| 36646 | CEFBS_IsARM, // LDRB_PRE_IMM = 926 |
| 36647 | CEFBS_IsARM, // LDRB_PRE_REG = 927 |
| 36648 | CEFBS_IsARM, // LDRBi12 = 928 |
| 36649 | CEFBS_IsARM, // LDRBrs = 929 |
| 36650 | CEFBS_IsARM_HasV5TE, // LDRD = 930 |
| 36651 | CEFBS_IsARM, // LDRD_POST = 931 |
| 36652 | CEFBS_IsARM, // LDRD_PRE = 932 |
| 36653 | CEFBS_IsARM, // LDREX = 933 |
| 36654 | CEFBS_IsARM, // LDREXB = 934 |
| 36655 | CEFBS_IsARM, // LDREXD = 935 |
| 36656 | CEFBS_IsARM, // LDREXH = 936 |
| 36657 | CEFBS_IsARM, // LDRH = 937 |
| 36658 | CEFBS_IsARM, // LDRHTi = 938 |
| 36659 | CEFBS_IsARM, // LDRHTr = 939 |
| 36660 | CEFBS_IsARM, // LDRH_POST = 940 |
| 36661 | CEFBS_IsARM, // LDRH_PRE = 941 |
| 36662 | CEFBS_IsARM, // LDRSB = 942 |
| 36663 | CEFBS_IsARM, // LDRSBTi = 943 |
| 36664 | CEFBS_IsARM, // LDRSBTr = 944 |
| 36665 | CEFBS_IsARM, // LDRSB_POST = 945 |
| 36666 | CEFBS_IsARM, // LDRSB_PRE = 946 |
| 36667 | CEFBS_IsARM, // LDRSH = 947 |
| 36668 | CEFBS_IsARM, // LDRSHTi = 948 |
| 36669 | CEFBS_IsARM, // LDRSHTr = 949 |
| 36670 | CEFBS_IsARM, // LDRSH_POST = 950 |
| 36671 | CEFBS_IsARM, // LDRSH_PRE = 951 |
| 36672 | CEFBS_IsARM, // LDRT_POST_IMM = 952 |
| 36673 | CEFBS_IsARM, // LDRT_POST_REG = 953 |
| 36674 | CEFBS_IsARM, // LDR_POST_IMM = 954 |
| 36675 | CEFBS_IsARM, // LDR_POST_REG = 955 |
| 36676 | CEFBS_IsARM, // LDR_PRE_IMM = 956 |
| 36677 | CEFBS_IsARM, // LDR_PRE_REG = 957 |
| 36678 | CEFBS_IsARM, // LDRcp = 958 |
| 36679 | CEFBS_IsARM, // LDRi12 = 959 |
| 36680 | CEFBS_IsARM, // LDRrs = 960 |
| 36681 | CEFBS_IsARM, // MCR = 961 |
| 36682 | CEFBS_IsARM_PreV8, // MCR2 = 962 |
| 36683 | CEFBS_IsARM, // MCRR = 963 |
| 36684 | CEFBS_IsARM_PreV8, // MCRR2 = 964 |
| 36685 | CEFBS_IsARM_HasV6, // MLA = 965 |
| 36686 | CEFBS_IsARM_HasV6T2, // MLS = 966 |
| 36687 | CEFBS_IsARM, // MOVPCLR = 967 |
| 36688 | CEFBS_IsARM_HasV6T2, // MOVTi16 = 968 |
| 36689 | CEFBS_IsARM, // MOVi = 969 |
| 36690 | CEFBS_IsARM_HasV6T2, // MOVi16 = 970 |
| 36691 | CEFBS_IsARM, // MOVr = 971 |
| 36692 | CEFBS_IsARM, // MOVr_TC = 972 |
| 36693 | CEFBS_IsARM, // MOVsi = 973 |
| 36694 | CEFBS_IsARM, // MOVsr = 974 |
| 36695 | CEFBS_IsARM, // MRC = 975 |
| 36696 | CEFBS_IsARM_PreV8, // MRC2 = 976 |
| 36697 | CEFBS_IsARM, // MRRC = 977 |
| 36698 | CEFBS_IsARM_PreV8, // MRRC2 = 978 |
| 36699 | CEFBS_IsARM, // MRS = 979 |
| 36700 | CEFBS_IsARM_HasVirtualization, // MRSbanked = 980 |
| 36701 | CEFBS_IsARM, // MRSsys = 981 |
| 36702 | CEFBS_IsARM, // MSR = 982 |
| 36703 | CEFBS_IsARM_HasVirtualization, // MSRbanked = 983 |
| 36704 | CEFBS_IsARM, // MSRi = 984 |
| 36705 | CEFBS_IsARM_HasV6, // MUL = 985 |
| 36706 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_ASRLi = 986 |
| 36707 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_ASRLr = 987 |
| 36708 | CEFBS_HasMVEInt, // MVE_DLSTP_16 = 988 |
| 36709 | CEFBS_HasMVEInt, // MVE_DLSTP_32 = 989 |
| 36710 | CEFBS_HasMVEInt, // MVE_DLSTP_64 = 990 |
| 36711 | CEFBS_HasMVEInt, // MVE_DLSTP_8 = 991 |
| 36712 | CEFBS_HasMVEInt, // MVE_LCTP = 992 |
| 36713 | CEFBS_HasMVEInt, // MVE_LETP = 993 |
| 36714 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSLLi = 994 |
| 36715 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSLLr = 995 |
| 36716 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSRL = 996 |
| 36717 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQRSHR = 997 |
| 36718 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQRSHRL = 998 |
| 36719 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQSHL = 999 |
| 36720 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQSHLL = 1000 |
| 36721 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SRSHR = 1001 |
| 36722 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SRSHRL = 1002 |
| 36723 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQRSHL = 1003 |
| 36724 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQRSHLL = 1004 |
| 36725 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQSHL = 1005 |
| 36726 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQSHLL = 1006 |
| 36727 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_URSHR = 1007 |
| 36728 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_URSHRL = 1008 |
| 36729 | CEFBS_HasMVEInt, // MVE_VABAVs16 = 1009 |
| 36730 | CEFBS_HasMVEInt, // MVE_VABAVs32 = 1010 |
| 36731 | CEFBS_HasMVEInt, // MVE_VABAVs8 = 1011 |
| 36732 | CEFBS_HasMVEInt, // MVE_VABAVu16 = 1012 |
| 36733 | CEFBS_HasMVEInt, // MVE_VABAVu32 = 1013 |
| 36734 | CEFBS_HasMVEInt, // MVE_VABAVu8 = 1014 |
| 36735 | CEFBS_HasMVEFloat, // MVE_VABDf16 = 1015 |
| 36736 | CEFBS_HasMVEFloat, // MVE_VABDf32 = 1016 |
| 36737 | CEFBS_HasMVEInt, // MVE_VABDs16 = 1017 |
| 36738 | CEFBS_HasMVEInt, // MVE_VABDs32 = 1018 |
| 36739 | CEFBS_HasMVEInt, // MVE_VABDs8 = 1019 |
| 36740 | CEFBS_HasMVEInt, // MVE_VABDu16 = 1020 |
| 36741 | CEFBS_HasMVEInt, // MVE_VABDu32 = 1021 |
| 36742 | CEFBS_HasMVEInt, // MVE_VABDu8 = 1022 |
| 36743 | CEFBS_HasMVEFloat, // MVE_VABSf16 = 1023 |
| 36744 | CEFBS_HasMVEFloat, // MVE_VABSf32 = 1024 |
| 36745 | CEFBS_HasMVEInt, // MVE_VABSs16 = 1025 |
| 36746 | CEFBS_HasMVEInt, // MVE_VABSs32 = 1026 |
| 36747 | CEFBS_HasMVEInt, // MVE_VABSs8 = 1027 |
| 36748 | CEFBS_HasMVEInt, // MVE_VADC = 1028 |
| 36749 | CEFBS_HasMVEInt, // MVE_VADCI = 1029 |
| 36750 | CEFBS_HasMVEInt, // MVE_VADDLVs32acc = 1030 |
| 36751 | CEFBS_HasMVEInt, // MVE_VADDLVs32no_acc = 1031 |
| 36752 | CEFBS_HasMVEInt, // MVE_VADDLVu32acc = 1032 |
| 36753 | CEFBS_HasMVEInt, // MVE_VADDLVu32no_acc = 1033 |
| 36754 | CEFBS_HasMVEInt, // MVE_VADDVs16acc = 1034 |
| 36755 | CEFBS_HasMVEInt, // MVE_VADDVs16no_acc = 1035 |
| 36756 | CEFBS_HasMVEInt, // MVE_VADDVs32acc = 1036 |
| 36757 | CEFBS_HasMVEInt, // MVE_VADDVs32no_acc = 1037 |
| 36758 | CEFBS_HasMVEInt, // MVE_VADDVs8acc = 1038 |
| 36759 | CEFBS_HasMVEInt, // MVE_VADDVs8no_acc = 1039 |
| 36760 | CEFBS_HasMVEInt, // MVE_VADDVu16acc = 1040 |
| 36761 | CEFBS_HasMVEInt, // MVE_VADDVu16no_acc = 1041 |
| 36762 | CEFBS_HasMVEInt, // MVE_VADDVu32acc = 1042 |
| 36763 | CEFBS_HasMVEInt, // MVE_VADDVu32no_acc = 1043 |
| 36764 | CEFBS_HasMVEInt, // MVE_VADDVu8acc = 1044 |
| 36765 | CEFBS_HasMVEInt, // MVE_VADDVu8no_acc = 1045 |
| 36766 | CEFBS_HasMVEFloat, // MVE_VADD_qr_f16 = 1046 |
| 36767 | CEFBS_HasMVEFloat, // MVE_VADD_qr_f32 = 1047 |
| 36768 | CEFBS_HasMVEInt, // MVE_VADD_qr_i16 = 1048 |
| 36769 | CEFBS_HasMVEInt, // MVE_VADD_qr_i32 = 1049 |
| 36770 | CEFBS_HasMVEInt, // MVE_VADD_qr_i8 = 1050 |
| 36771 | CEFBS_HasMVEFloat, // MVE_VADDf16 = 1051 |
| 36772 | CEFBS_HasMVEFloat, // MVE_VADDf32 = 1052 |
| 36773 | CEFBS_HasMVEInt, // MVE_VADDi16 = 1053 |
| 36774 | CEFBS_HasMVEInt, // MVE_VADDi32 = 1054 |
| 36775 | CEFBS_HasMVEInt, // MVE_VADDi8 = 1055 |
| 36776 | CEFBS_HasMVEInt, // MVE_VAND = 1056 |
| 36777 | CEFBS_HasMVEInt, // MVE_VBIC = 1057 |
| 36778 | CEFBS_HasMVEInt, // MVE_VBICimmi16 = 1058 |
| 36779 | CEFBS_HasMVEInt, // MVE_VBICimmi32 = 1059 |
| 36780 | CEFBS_HasMVEInt, // MVE_VBRSR16 = 1060 |
| 36781 | CEFBS_HasMVEInt, // MVE_VBRSR32 = 1061 |
| 36782 | CEFBS_HasMVEInt, // MVE_VBRSR8 = 1062 |
| 36783 | CEFBS_HasMVEFloat, // MVE_VCADDf16 = 1063 |
| 36784 | CEFBS_HasMVEFloat, // MVE_VCADDf32 = 1064 |
| 36785 | CEFBS_HasMVEInt, // MVE_VCADDi16 = 1065 |
| 36786 | CEFBS_HasMVEInt, // MVE_VCADDi32 = 1066 |
| 36787 | CEFBS_HasMVEInt, // MVE_VCADDi8 = 1067 |
| 36788 | CEFBS_HasMVEInt, // MVE_VCLSs16 = 1068 |
| 36789 | CEFBS_HasMVEInt, // MVE_VCLSs32 = 1069 |
| 36790 | CEFBS_HasMVEInt, // MVE_VCLSs8 = 1070 |
| 36791 | CEFBS_HasMVEInt, // MVE_VCLZs16 = 1071 |
| 36792 | CEFBS_HasMVEInt, // MVE_VCLZs32 = 1072 |
| 36793 | CEFBS_HasMVEInt, // MVE_VCLZs8 = 1073 |
| 36794 | CEFBS_HasMVEFloat, // MVE_VCMLAf16 = 1074 |
| 36795 | CEFBS_HasMVEFloat, // MVE_VCMLAf32 = 1075 |
| 36796 | CEFBS_HasMVEFloat, // MVE_VCMPf16 = 1076 |
| 36797 | CEFBS_HasMVEFloat, // MVE_VCMPf16r = 1077 |
| 36798 | CEFBS_HasMVEFloat, // MVE_VCMPf32 = 1078 |
| 36799 | CEFBS_HasMVEFloat, // MVE_VCMPf32r = 1079 |
| 36800 | CEFBS_HasMVEInt, // MVE_VCMPi16 = 1080 |
| 36801 | CEFBS_HasMVEInt, // MVE_VCMPi16r = 1081 |
| 36802 | CEFBS_HasMVEInt, // MVE_VCMPi32 = 1082 |
| 36803 | CEFBS_HasMVEInt, // MVE_VCMPi32r = 1083 |
| 36804 | CEFBS_HasMVEInt, // MVE_VCMPi8 = 1084 |
| 36805 | CEFBS_HasMVEInt, // MVE_VCMPi8r = 1085 |
| 36806 | CEFBS_HasMVEInt, // MVE_VCMPs16 = 1086 |
| 36807 | CEFBS_HasMVEInt, // MVE_VCMPs16r = 1087 |
| 36808 | CEFBS_HasMVEInt, // MVE_VCMPs32 = 1088 |
| 36809 | CEFBS_HasMVEInt, // MVE_VCMPs32r = 1089 |
| 36810 | CEFBS_HasMVEInt, // MVE_VCMPs8 = 1090 |
| 36811 | CEFBS_HasMVEInt, // MVE_VCMPs8r = 1091 |
| 36812 | CEFBS_HasMVEInt, // MVE_VCMPu16 = 1092 |
| 36813 | CEFBS_HasMVEInt, // MVE_VCMPu16r = 1093 |
| 36814 | CEFBS_HasMVEInt, // MVE_VCMPu32 = 1094 |
| 36815 | CEFBS_HasMVEInt, // MVE_VCMPu32r = 1095 |
| 36816 | CEFBS_HasMVEInt, // MVE_VCMPu8 = 1096 |
| 36817 | CEFBS_HasMVEInt, // MVE_VCMPu8r = 1097 |
| 36818 | CEFBS_HasMVEFloat, // MVE_VCMULf16 = 1098 |
| 36819 | CEFBS_HasMVEFloat, // MVE_VCMULf32 = 1099 |
| 36820 | CEFBS_HasMVEInt, // MVE_VCTP16 = 1100 |
| 36821 | CEFBS_HasMVEInt, // MVE_VCTP32 = 1101 |
| 36822 | CEFBS_HasMVEInt, // MVE_VCTP64 = 1102 |
| 36823 | CEFBS_HasMVEInt, // MVE_VCTP8 = 1103 |
| 36824 | CEFBS_HasMVEFloat, // MVE_VCVTf16f32bh = 1104 |
| 36825 | CEFBS_HasMVEFloat, // MVE_VCVTf16f32th = 1105 |
| 36826 | CEFBS_HasMVEFloat, // MVE_VCVTf16s16_fix = 1106 |
| 36827 | CEFBS_HasMVEFloat, // MVE_VCVTf16s16n = 1107 |
| 36828 | CEFBS_HasMVEFloat, // MVE_VCVTf16u16_fix = 1108 |
| 36829 | CEFBS_HasMVEFloat, // MVE_VCVTf16u16n = 1109 |
| 36830 | CEFBS_HasMVEFloat, // MVE_VCVTf32f16bh = 1110 |
| 36831 | CEFBS_HasMVEFloat, // MVE_VCVTf32f16th = 1111 |
| 36832 | CEFBS_HasMVEFloat, // MVE_VCVTf32s32_fix = 1112 |
| 36833 | CEFBS_HasMVEFloat, // MVE_VCVTf32s32n = 1113 |
| 36834 | CEFBS_HasMVEFloat, // MVE_VCVTf32u32_fix = 1114 |
| 36835 | CEFBS_HasMVEFloat, // MVE_VCVTf32u32n = 1115 |
| 36836 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16_fix = 1116 |
| 36837 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16a = 1117 |
| 36838 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16m = 1118 |
| 36839 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16n = 1119 |
| 36840 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16p = 1120 |
| 36841 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16z = 1121 |
| 36842 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32_fix = 1122 |
| 36843 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32a = 1123 |
| 36844 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32m = 1124 |
| 36845 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32n = 1125 |
| 36846 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32p = 1126 |
| 36847 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32z = 1127 |
| 36848 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16_fix = 1128 |
| 36849 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16a = 1129 |
| 36850 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16m = 1130 |
| 36851 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16n = 1131 |
| 36852 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16p = 1132 |
| 36853 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16z = 1133 |
| 36854 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32_fix = 1134 |
| 36855 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32a = 1135 |
| 36856 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32m = 1136 |
| 36857 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32n = 1137 |
| 36858 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32p = 1138 |
| 36859 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32z = 1139 |
| 36860 | CEFBS_HasMVEInt, // MVE_VDDUPu16 = 1140 |
| 36861 | CEFBS_HasMVEInt, // MVE_VDDUPu32 = 1141 |
| 36862 | CEFBS_HasMVEInt, // MVE_VDDUPu8 = 1142 |
| 36863 | CEFBS_HasMVEInt, // MVE_VDUP16 = 1143 |
| 36864 | CEFBS_HasMVEInt, // MVE_VDUP32 = 1144 |
| 36865 | CEFBS_HasMVEInt, // MVE_VDUP8 = 1145 |
| 36866 | CEFBS_HasMVEInt, // MVE_VDWDUPu16 = 1146 |
| 36867 | CEFBS_HasMVEInt, // MVE_VDWDUPu32 = 1147 |
| 36868 | CEFBS_HasMVEInt, // MVE_VDWDUPu8 = 1148 |
| 36869 | CEFBS_HasMVEInt, // MVE_VEOR = 1149 |
| 36870 | CEFBS_HasMVEFloat, // MVE_VFMA_qr_Sf16 = 1150 |
| 36871 | CEFBS_HasMVEFloat, // MVE_VFMA_qr_Sf32 = 1151 |
| 36872 | CEFBS_HasMVEFloat, // MVE_VFMA_qr_f16 = 1152 |
| 36873 | CEFBS_HasMVEFloat, // MVE_VFMA_qr_f32 = 1153 |
| 36874 | CEFBS_HasMVEFloat, // MVE_VFMAf16 = 1154 |
| 36875 | CEFBS_HasMVEFloat, // MVE_VFMAf32 = 1155 |
| 36876 | CEFBS_HasMVEFloat, // MVE_VFMSf16 = 1156 |
| 36877 | CEFBS_HasMVEFloat, // MVE_VFMSf32 = 1157 |
| 36878 | CEFBS_HasMVEInt, // MVE_VHADD_qr_s16 = 1158 |
| 36879 | CEFBS_HasMVEInt, // MVE_VHADD_qr_s32 = 1159 |
| 36880 | CEFBS_HasMVEInt, // MVE_VHADD_qr_s8 = 1160 |
| 36881 | CEFBS_HasMVEInt, // MVE_VHADD_qr_u16 = 1161 |
| 36882 | CEFBS_HasMVEInt, // MVE_VHADD_qr_u32 = 1162 |
| 36883 | CEFBS_HasMVEInt, // MVE_VHADD_qr_u8 = 1163 |
| 36884 | CEFBS_HasMVEInt, // MVE_VHADDs16 = 1164 |
| 36885 | CEFBS_HasMVEInt, // MVE_VHADDs32 = 1165 |
| 36886 | CEFBS_HasMVEInt, // MVE_VHADDs8 = 1166 |
| 36887 | CEFBS_HasMVEInt, // MVE_VHADDu16 = 1167 |
| 36888 | CEFBS_HasMVEInt, // MVE_VHADDu32 = 1168 |
| 36889 | CEFBS_HasMVEInt, // MVE_VHADDu8 = 1169 |
| 36890 | CEFBS_HasMVEInt, // MVE_VHCADDs16 = 1170 |
| 36891 | CEFBS_HasMVEInt, // MVE_VHCADDs32 = 1171 |
| 36892 | CEFBS_HasMVEInt, // MVE_VHCADDs8 = 1172 |
| 36893 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_s16 = 1173 |
| 36894 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_s32 = 1174 |
| 36895 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_s8 = 1175 |
| 36896 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_u16 = 1176 |
| 36897 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_u32 = 1177 |
| 36898 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_u8 = 1178 |
| 36899 | CEFBS_HasMVEInt, // MVE_VHSUBs16 = 1179 |
| 36900 | CEFBS_HasMVEInt, // MVE_VHSUBs32 = 1180 |
| 36901 | CEFBS_HasMVEInt, // MVE_VHSUBs8 = 1181 |
| 36902 | CEFBS_HasMVEInt, // MVE_VHSUBu16 = 1182 |
| 36903 | CEFBS_HasMVEInt, // MVE_VHSUBu32 = 1183 |
| 36904 | CEFBS_HasMVEInt, // MVE_VHSUBu8 = 1184 |
| 36905 | CEFBS_HasMVEInt, // MVE_VIDUPu16 = 1185 |
| 36906 | CEFBS_HasMVEInt, // MVE_VIDUPu32 = 1186 |
| 36907 | CEFBS_HasMVEInt, // MVE_VIDUPu8 = 1187 |
| 36908 | CEFBS_HasMVEInt, // MVE_VIWDUPu16 = 1188 |
| 36909 | CEFBS_HasMVEInt, // MVE_VIWDUPu32 = 1189 |
| 36910 | CEFBS_HasMVEInt, // MVE_VIWDUPu8 = 1190 |
| 36911 | CEFBS_HasMVEInt, // MVE_VLD20_16 = 1191 |
| 36912 | CEFBS_HasMVEInt, // MVE_VLD20_16_wb = 1192 |
| 36913 | CEFBS_HasMVEInt, // MVE_VLD20_32 = 1193 |
| 36914 | CEFBS_HasMVEInt, // MVE_VLD20_32_wb = 1194 |
| 36915 | CEFBS_HasMVEInt, // MVE_VLD20_8 = 1195 |
| 36916 | CEFBS_HasMVEInt, // MVE_VLD20_8_wb = 1196 |
| 36917 | CEFBS_HasMVEInt, // MVE_VLD21_16 = 1197 |
| 36918 | CEFBS_HasMVEInt, // MVE_VLD21_16_wb = 1198 |
| 36919 | CEFBS_HasMVEInt, // MVE_VLD21_32 = 1199 |
| 36920 | CEFBS_HasMVEInt, // MVE_VLD21_32_wb = 1200 |
| 36921 | CEFBS_HasMVEInt, // MVE_VLD21_8 = 1201 |
| 36922 | CEFBS_HasMVEInt, // MVE_VLD21_8_wb = 1202 |
| 36923 | CEFBS_HasMVEInt, // MVE_VLD40_16 = 1203 |
| 36924 | CEFBS_HasMVEInt, // MVE_VLD40_16_wb = 1204 |
| 36925 | CEFBS_HasMVEInt, // MVE_VLD40_32 = 1205 |
| 36926 | CEFBS_HasMVEInt, // MVE_VLD40_32_wb = 1206 |
| 36927 | CEFBS_HasMVEInt, // MVE_VLD40_8 = 1207 |
| 36928 | CEFBS_HasMVEInt, // MVE_VLD40_8_wb = 1208 |
| 36929 | CEFBS_HasMVEInt, // MVE_VLD41_16 = 1209 |
| 36930 | CEFBS_HasMVEInt, // MVE_VLD41_16_wb = 1210 |
| 36931 | CEFBS_HasMVEInt, // MVE_VLD41_32 = 1211 |
| 36932 | CEFBS_HasMVEInt, // MVE_VLD41_32_wb = 1212 |
| 36933 | CEFBS_HasMVEInt, // MVE_VLD41_8 = 1213 |
| 36934 | CEFBS_HasMVEInt, // MVE_VLD41_8_wb = 1214 |
| 36935 | CEFBS_HasMVEInt, // MVE_VLD42_16 = 1215 |
| 36936 | CEFBS_HasMVEInt, // MVE_VLD42_16_wb = 1216 |
| 36937 | CEFBS_HasMVEInt, // MVE_VLD42_32 = 1217 |
| 36938 | CEFBS_HasMVEInt, // MVE_VLD42_32_wb = 1218 |
| 36939 | CEFBS_HasMVEInt, // MVE_VLD42_8 = 1219 |
| 36940 | CEFBS_HasMVEInt, // MVE_VLD42_8_wb = 1220 |
| 36941 | CEFBS_HasMVEInt, // MVE_VLD43_16 = 1221 |
| 36942 | CEFBS_HasMVEInt, // MVE_VLD43_16_wb = 1222 |
| 36943 | CEFBS_HasMVEInt, // MVE_VLD43_32 = 1223 |
| 36944 | CEFBS_HasMVEInt, // MVE_VLD43_32_wb = 1224 |
| 36945 | CEFBS_HasMVEInt, // MVE_VLD43_8 = 1225 |
| 36946 | CEFBS_HasMVEInt, // MVE_VLD43_8_wb = 1226 |
| 36947 | CEFBS_HasMVEInt, // MVE_VLDRBS16 = 1227 |
| 36948 | CEFBS_HasMVEInt, // MVE_VLDRBS16_post = 1228 |
| 36949 | CEFBS_HasMVEInt, // MVE_VLDRBS16_pre = 1229 |
| 36950 | CEFBS_HasMVEInt, // MVE_VLDRBS16_rq = 1230 |
| 36951 | CEFBS_HasMVEInt, // MVE_VLDRBS32 = 1231 |
| 36952 | CEFBS_HasMVEInt, // MVE_VLDRBS32_post = 1232 |
| 36953 | CEFBS_HasMVEInt, // MVE_VLDRBS32_pre = 1233 |
| 36954 | CEFBS_HasMVEInt, // MVE_VLDRBS32_rq = 1234 |
| 36955 | CEFBS_HasMVEInt, // MVE_VLDRBU16 = 1235 |
| 36956 | CEFBS_HasMVEInt, // MVE_VLDRBU16_post = 1236 |
| 36957 | CEFBS_HasMVEInt, // MVE_VLDRBU16_pre = 1237 |
| 36958 | CEFBS_HasMVEInt, // MVE_VLDRBU16_rq = 1238 |
| 36959 | CEFBS_HasMVEInt, // MVE_VLDRBU32 = 1239 |
| 36960 | CEFBS_HasMVEInt, // MVE_VLDRBU32_post = 1240 |
| 36961 | CEFBS_HasMVEInt, // MVE_VLDRBU32_pre = 1241 |
| 36962 | CEFBS_HasMVEInt, // MVE_VLDRBU32_rq = 1242 |
| 36963 | CEFBS_HasMVEInt, // MVE_VLDRBU8 = 1243 |
| 36964 | CEFBS_HasMVEInt, // MVE_VLDRBU8_post = 1244 |
| 36965 | CEFBS_HasMVEInt, // MVE_VLDRBU8_pre = 1245 |
| 36966 | CEFBS_HasMVEInt, // MVE_VLDRBU8_rq = 1246 |
| 36967 | CEFBS_HasMVEInt, // MVE_VLDRDU64_qi = 1247 |
| 36968 | CEFBS_HasMVEInt, // MVE_VLDRDU64_qi_pre = 1248 |
| 36969 | CEFBS_HasMVEInt, // MVE_VLDRDU64_rq = 1249 |
| 36970 | CEFBS_HasMVEInt, // MVE_VLDRDU64_rq_u = 1250 |
| 36971 | CEFBS_HasMVEInt, // MVE_VLDRHS32 = 1251 |
| 36972 | CEFBS_HasMVEInt, // MVE_VLDRHS32_post = 1252 |
| 36973 | CEFBS_HasMVEInt, // MVE_VLDRHS32_pre = 1253 |
| 36974 | CEFBS_HasMVEInt, // MVE_VLDRHS32_rq = 1254 |
| 36975 | CEFBS_HasMVEInt, // MVE_VLDRHS32_rq_u = 1255 |
| 36976 | CEFBS_HasMVEInt, // MVE_VLDRHU16 = 1256 |
| 36977 | CEFBS_HasMVEInt, // MVE_VLDRHU16_post = 1257 |
| 36978 | CEFBS_HasMVEInt, // MVE_VLDRHU16_pre = 1258 |
| 36979 | CEFBS_HasMVEInt, // MVE_VLDRHU16_rq = 1259 |
| 36980 | CEFBS_HasMVEInt, // MVE_VLDRHU16_rq_u = 1260 |
| 36981 | CEFBS_HasMVEInt, // MVE_VLDRHU32 = 1261 |
| 36982 | CEFBS_HasMVEInt, // MVE_VLDRHU32_post = 1262 |
| 36983 | CEFBS_HasMVEInt, // MVE_VLDRHU32_pre = 1263 |
| 36984 | CEFBS_HasMVEInt, // MVE_VLDRHU32_rq = 1264 |
| 36985 | CEFBS_HasMVEInt, // MVE_VLDRHU32_rq_u = 1265 |
| 36986 | CEFBS_HasMVEInt, // MVE_VLDRWU32 = 1266 |
| 36987 | CEFBS_HasMVEInt, // MVE_VLDRWU32_post = 1267 |
| 36988 | CEFBS_HasMVEInt, // MVE_VLDRWU32_pre = 1268 |
| 36989 | CEFBS_HasMVEInt, // MVE_VLDRWU32_qi = 1269 |
| 36990 | CEFBS_HasMVEInt, // MVE_VLDRWU32_qi_pre = 1270 |
| 36991 | CEFBS_HasMVEInt, // MVE_VLDRWU32_rq = 1271 |
| 36992 | CEFBS_HasMVEInt, // MVE_VLDRWU32_rq_u = 1272 |
| 36993 | CEFBS_HasMVEInt, // MVE_VMAXAVs16 = 1273 |
| 36994 | CEFBS_HasMVEInt, // MVE_VMAXAVs32 = 1274 |
| 36995 | CEFBS_HasMVEInt, // MVE_VMAXAVs8 = 1275 |
| 36996 | CEFBS_HasMVEInt, // MVE_VMAXAs16 = 1276 |
| 36997 | CEFBS_HasMVEInt, // MVE_VMAXAs32 = 1277 |
| 36998 | CEFBS_HasMVEInt, // MVE_VMAXAs8 = 1278 |
| 36999 | CEFBS_HasMVEFloat, // MVE_VMAXNMAVf16 = 1279 |
| 37000 | CEFBS_HasMVEFloat, // MVE_VMAXNMAVf32 = 1280 |
| 37001 | CEFBS_HasMVEFloat, // MVE_VMAXNMAf16 = 1281 |
| 37002 | CEFBS_HasMVEFloat, // MVE_VMAXNMAf32 = 1282 |
| 37003 | CEFBS_HasMVEFloat, // MVE_VMAXNMVf16 = 1283 |
| 37004 | CEFBS_HasMVEFloat, // MVE_VMAXNMVf32 = 1284 |
| 37005 | CEFBS_HasMVEFloat, // MVE_VMAXNMf16 = 1285 |
| 37006 | CEFBS_HasMVEFloat, // MVE_VMAXNMf32 = 1286 |
| 37007 | CEFBS_HasMVEInt, // MVE_VMAXVs16 = 1287 |
| 37008 | CEFBS_HasMVEInt, // MVE_VMAXVs32 = 1288 |
| 37009 | CEFBS_HasMVEInt, // MVE_VMAXVs8 = 1289 |
| 37010 | CEFBS_HasMVEInt, // MVE_VMAXVu16 = 1290 |
| 37011 | CEFBS_HasMVEInt, // MVE_VMAXVu32 = 1291 |
| 37012 | CEFBS_HasMVEInt, // MVE_VMAXVu8 = 1292 |
| 37013 | CEFBS_HasMVEInt, // MVE_VMAXs16 = 1293 |
| 37014 | CEFBS_HasMVEInt, // MVE_VMAXs32 = 1294 |
| 37015 | CEFBS_HasMVEInt, // MVE_VMAXs8 = 1295 |
| 37016 | CEFBS_HasMVEInt, // MVE_VMAXu16 = 1296 |
| 37017 | CEFBS_HasMVEInt, // MVE_VMAXu32 = 1297 |
| 37018 | CEFBS_HasMVEInt, // MVE_VMAXu8 = 1298 |
| 37019 | CEFBS_HasMVEInt, // MVE_VMINAVs16 = 1299 |
| 37020 | CEFBS_HasMVEInt, // MVE_VMINAVs32 = 1300 |
| 37021 | CEFBS_HasMVEInt, // MVE_VMINAVs8 = 1301 |
| 37022 | CEFBS_HasMVEInt, // MVE_VMINAs16 = 1302 |
| 37023 | CEFBS_HasMVEInt, // MVE_VMINAs32 = 1303 |
| 37024 | CEFBS_HasMVEInt, // MVE_VMINAs8 = 1304 |
| 37025 | CEFBS_HasMVEFloat, // MVE_VMINNMAVf16 = 1305 |
| 37026 | CEFBS_HasMVEFloat, // MVE_VMINNMAVf32 = 1306 |
| 37027 | CEFBS_HasMVEFloat, // MVE_VMINNMAf16 = 1307 |
| 37028 | CEFBS_HasMVEFloat, // MVE_VMINNMAf32 = 1308 |
| 37029 | CEFBS_HasMVEFloat, // MVE_VMINNMVf16 = 1309 |
| 37030 | CEFBS_HasMVEFloat, // MVE_VMINNMVf32 = 1310 |
| 37031 | CEFBS_HasMVEFloat, // MVE_VMINNMf16 = 1311 |
| 37032 | CEFBS_HasMVEFloat, // MVE_VMINNMf32 = 1312 |
| 37033 | CEFBS_HasMVEInt, // MVE_VMINVs16 = 1313 |
| 37034 | CEFBS_HasMVEInt, // MVE_VMINVs32 = 1314 |
| 37035 | CEFBS_HasMVEInt, // MVE_VMINVs8 = 1315 |
| 37036 | CEFBS_HasMVEInt, // MVE_VMINVu16 = 1316 |
| 37037 | CEFBS_HasMVEInt, // MVE_VMINVu32 = 1317 |
| 37038 | CEFBS_HasMVEInt, // MVE_VMINVu8 = 1318 |
| 37039 | CEFBS_HasMVEInt, // MVE_VMINs16 = 1319 |
| 37040 | CEFBS_HasMVEInt, // MVE_VMINs32 = 1320 |
| 37041 | CEFBS_HasMVEInt, // MVE_VMINs8 = 1321 |
| 37042 | CEFBS_HasMVEInt, // MVE_VMINu16 = 1322 |
| 37043 | CEFBS_HasMVEInt, // MVE_VMINu32 = 1323 |
| 37044 | CEFBS_HasMVEInt, // MVE_VMINu8 = 1324 |
| 37045 | CEFBS_HasMVEInt, // MVE_VMLADAVas16 = 1325 |
| 37046 | CEFBS_HasMVEInt, // MVE_VMLADAVas32 = 1326 |
| 37047 | CEFBS_HasMVEInt, // MVE_VMLADAVas8 = 1327 |
| 37048 | CEFBS_HasMVEInt, // MVE_VMLADAVau16 = 1328 |
| 37049 | CEFBS_HasMVEInt, // MVE_VMLADAVau32 = 1329 |
| 37050 | CEFBS_HasMVEInt, // MVE_VMLADAVau8 = 1330 |
| 37051 | CEFBS_HasMVEInt, // MVE_VMLADAVaxs16 = 1331 |
| 37052 | CEFBS_HasMVEInt, // MVE_VMLADAVaxs32 = 1332 |
| 37053 | CEFBS_HasMVEInt, // MVE_VMLADAVaxs8 = 1333 |
| 37054 | CEFBS_HasMVEInt, // MVE_VMLADAVs16 = 1334 |
| 37055 | CEFBS_HasMVEInt, // MVE_VMLADAVs32 = 1335 |
| 37056 | CEFBS_HasMVEInt, // MVE_VMLADAVs8 = 1336 |
| 37057 | CEFBS_HasMVEInt, // MVE_VMLADAVu16 = 1337 |
| 37058 | CEFBS_HasMVEInt, // MVE_VMLADAVu32 = 1338 |
| 37059 | CEFBS_HasMVEInt, // MVE_VMLADAVu8 = 1339 |
| 37060 | CEFBS_HasMVEInt, // MVE_VMLADAVxs16 = 1340 |
| 37061 | CEFBS_HasMVEInt, // MVE_VMLADAVxs32 = 1341 |
| 37062 | CEFBS_HasMVEInt, // MVE_VMLADAVxs8 = 1342 |
| 37063 | CEFBS_HasMVEInt, // MVE_VMLALDAVas16 = 1343 |
| 37064 | CEFBS_HasMVEInt, // MVE_VMLALDAVas32 = 1344 |
| 37065 | CEFBS_HasMVEInt, // MVE_VMLALDAVau16 = 1345 |
| 37066 | CEFBS_HasMVEInt, // MVE_VMLALDAVau32 = 1346 |
| 37067 | CEFBS_HasMVEInt, // MVE_VMLALDAVaxs16 = 1347 |
| 37068 | CEFBS_HasMVEInt, // MVE_VMLALDAVaxs32 = 1348 |
| 37069 | CEFBS_HasMVEInt, // MVE_VMLALDAVs16 = 1349 |
| 37070 | CEFBS_HasMVEInt, // MVE_VMLALDAVs32 = 1350 |
| 37071 | CEFBS_HasMVEInt, // MVE_VMLALDAVu16 = 1351 |
| 37072 | CEFBS_HasMVEInt, // MVE_VMLALDAVu32 = 1352 |
| 37073 | CEFBS_HasMVEInt, // MVE_VMLALDAVxs16 = 1353 |
| 37074 | CEFBS_HasMVEInt, // MVE_VMLALDAVxs32 = 1354 |
| 37075 | CEFBS_HasMVEInt, // MVE_VMLAS_qr_i16 = 1355 |
| 37076 | CEFBS_HasMVEInt, // MVE_VMLAS_qr_i32 = 1356 |
| 37077 | CEFBS_HasMVEInt, // MVE_VMLAS_qr_i8 = 1357 |
| 37078 | CEFBS_HasMVEInt, // MVE_VMLA_qr_i16 = 1358 |
| 37079 | CEFBS_HasMVEInt, // MVE_VMLA_qr_i32 = 1359 |
| 37080 | CEFBS_HasMVEInt, // MVE_VMLA_qr_i8 = 1360 |
| 37081 | CEFBS_HasMVEInt, // MVE_VMLSDAVas16 = 1361 |
| 37082 | CEFBS_HasMVEInt, // MVE_VMLSDAVas32 = 1362 |
| 37083 | CEFBS_HasMVEInt, // MVE_VMLSDAVas8 = 1363 |
| 37084 | CEFBS_HasMVEInt, // MVE_VMLSDAVaxs16 = 1364 |
| 37085 | CEFBS_HasMVEInt, // MVE_VMLSDAVaxs32 = 1365 |
| 37086 | CEFBS_HasMVEInt, // MVE_VMLSDAVaxs8 = 1366 |
| 37087 | CEFBS_HasMVEInt, // MVE_VMLSDAVs16 = 1367 |
| 37088 | CEFBS_HasMVEInt, // MVE_VMLSDAVs32 = 1368 |
| 37089 | CEFBS_HasMVEInt, // MVE_VMLSDAVs8 = 1369 |
| 37090 | CEFBS_HasMVEInt, // MVE_VMLSDAVxs16 = 1370 |
| 37091 | CEFBS_HasMVEInt, // MVE_VMLSDAVxs32 = 1371 |
| 37092 | CEFBS_HasMVEInt, // MVE_VMLSDAVxs8 = 1372 |
| 37093 | CEFBS_HasMVEInt, // MVE_VMLSLDAVas16 = 1373 |
| 37094 | CEFBS_HasMVEInt, // MVE_VMLSLDAVas32 = 1374 |
| 37095 | CEFBS_HasMVEInt, // MVE_VMLSLDAVaxs16 = 1375 |
| 37096 | CEFBS_HasMVEInt, // MVE_VMLSLDAVaxs32 = 1376 |
| 37097 | CEFBS_HasMVEInt, // MVE_VMLSLDAVs16 = 1377 |
| 37098 | CEFBS_HasMVEInt, // MVE_VMLSLDAVs32 = 1378 |
| 37099 | CEFBS_HasMVEInt, // MVE_VMLSLDAVxs16 = 1379 |
| 37100 | CEFBS_HasMVEInt, // MVE_VMLSLDAVxs32 = 1380 |
| 37101 | CEFBS_HasMVEInt, // MVE_VMOVLs16bh = 1381 |
| 37102 | CEFBS_HasMVEInt, // MVE_VMOVLs16th = 1382 |
| 37103 | CEFBS_HasMVEInt, // MVE_VMOVLs8bh = 1383 |
| 37104 | CEFBS_HasMVEInt, // MVE_VMOVLs8th = 1384 |
| 37105 | CEFBS_HasMVEInt, // MVE_VMOVLu16bh = 1385 |
| 37106 | CEFBS_HasMVEInt, // MVE_VMOVLu16th = 1386 |
| 37107 | CEFBS_HasMVEInt, // MVE_VMOVLu8bh = 1387 |
| 37108 | CEFBS_HasMVEInt, // MVE_VMOVLu8th = 1388 |
| 37109 | CEFBS_HasMVEInt, // MVE_VMOVNi16bh = 1389 |
| 37110 | CEFBS_HasMVEInt, // MVE_VMOVNi16th = 1390 |
| 37111 | CEFBS_HasMVEInt, // MVE_VMOVNi32bh = 1391 |
| 37112 | CEFBS_HasMVEInt, // MVE_VMOVNi32th = 1392 |
| 37113 | CEFBS_HasFPRegsV8_1M, // MVE_VMOV_from_lane_32 = 1393 |
| 37114 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_s16 = 1394 |
| 37115 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_s8 = 1395 |
| 37116 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_u16 = 1396 |
| 37117 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_u8 = 1397 |
| 37118 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_q_rr = 1398 |
| 37119 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_rr_q = 1399 |
| 37120 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_to_lane_16 = 1400 |
| 37121 | CEFBS_HasFPRegsV8_1M, // MVE_VMOV_to_lane_32 = 1401 |
| 37122 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_to_lane_8 = 1402 |
| 37123 | CEFBS_HasMVEInt, // MVE_VMOVimmf32 = 1403 |
| 37124 | CEFBS_HasMVEInt, // MVE_VMOVimmi16 = 1404 |
| 37125 | CEFBS_HasMVEInt, // MVE_VMOVimmi32 = 1405 |
| 37126 | CEFBS_HasMVEInt, // MVE_VMOVimmi64 = 1406 |
| 37127 | CEFBS_HasMVEInt, // MVE_VMOVimmi8 = 1407 |
| 37128 | CEFBS_HasMVEInt, // MVE_VMULHs16 = 1408 |
| 37129 | CEFBS_HasMVEInt, // MVE_VMULHs32 = 1409 |
| 37130 | CEFBS_HasMVEInt, // MVE_VMULHs8 = 1410 |
| 37131 | CEFBS_HasMVEInt, // MVE_VMULHu16 = 1411 |
| 37132 | CEFBS_HasMVEInt, // MVE_VMULHu32 = 1412 |
| 37133 | CEFBS_HasMVEInt, // MVE_VMULHu8 = 1413 |
| 37134 | CEFBS_HasMVEInt, // MVE_VMULLBp16 = 1414 |
| 37135 | CEFBS_HasMVEInt, // MVE_VMULLBp8 = 1415 |
| 37136 | CEFBS_HasMVEInt, // MVE_VMULLBs16 = 1416 |
| 37137 | CEFBS_HasMVEInt, // MVE_VMULLBs32 = 1417 |
| 37138 | CEFBS_HasMVEInt, // MVE_VMULLBs8 = 1418 |
| 37139 | CEFBS_HasMVEInt, // MVE_VMULLBu16 = 1419 |
| 37140 | CEFBS_HasMVEInt, // MVE_VMULLBu32 = 1420 |
| 37141 | CEFBS_HasMVEInt, // MVE_VMULLBu8 = 1421 |
| 37142 | CEFBS_HasMVEInt, // MVE_VMULLTp16 = 1422 |
| 37143 | CEFBS_HasMVEInt, // MVE_VMULLTp8 = 1423 |
| 37144 | CEFBS_HasMVEInt, // MVE_VMULLTs16 = 1424 |
| 37145 | CEFBS_HasMVEInt, // MVE_VMULLTs32 = 1425 |
| 37146 | CEFBS_HasMVEInt, // MVE_VMULLTs8 = 1426 |
| 37147 | CEFBS_HasMVEInt, // MVE_VMULLTu16 = 1427 |
| 37148 | CEFBS_HasMVEInt, // MVE_VMULLTu32 = 1428 |
| 37149 | CEFBS_HasMVEInt, // MVE_VMULLTu8 = 1429 |
| 37150 | CEFBS_HasMVEFloat, // MVE_VMUL_qr_f16 = 1430 |
| 37151 | CEFBS_HasMVEFloat, // MVE_VMUL_qr_f32 = 1431 |
| 37152 | CEFBS_HasMVEInt, // MVE_VMUL_qr_i16 = 1432 |
| 37153 | CEFBS_HasMVEInt, // MVE_VMUL_qr_i32 = 1433 |
| 37154 | CEFBS_HasMVEInt, // MVE_VMUL_qr_i8 = 1434 |
| 37155 | CEFBS_HasMVEFloat, // MVE_VMULf16 = 1435 |
| 37156 | CEFBS_HasMVEFloat, // MVE_VMULf32 = 1436 |
| 37157 | CEFBS_HasMVEInt, // MVE_VMULi16 = 1437 |
| 37158 | CEFBS_HasMVEInt, // MVE_VMULi32 = 1438 |
| 37159 | CEFBS_HasMVEInt, // MVE_VMULi8 = 1439 |
| 37160 | CEFBS_HasMVEInt, // MVE_VMVN = 1440 |
| 37161 | CEFBS_HasMVEInt, // MVE_VMVNimmi16 = 1441 |
| 37162 | CEFBS_HasMVEInt, // MVE_VMVNimmi32 = 1442 |
| 37163 | CEFBS_HasMVEFloat, // MVE_VNEGf16 = 1443 |
| 37164 | CEFBS_HasMVEFloat, // MVE_VNEGf32 = 1444 |
| 37165 | CEFBS_HasMVEInt, // MVE_VNEGs16 = 1445 |
| 37166 | CEFBS_HasMVEInt, // MVE_VNEGs32 = 1446 |
| 37167 | CEFBS_HasMVEInt, // MVE_VNEGs8 = 1447 |
| 37168 | CEFBS_HasMVEInt, // MVE_VORN = 1448 |
| 37169 | CEFBS_HasMVEInt, // MVE_VORR = 1449 |
| 37170 | CEFBS_HasMVEInt, // MVE_VORRimmi16 = 1450 |
| 37171 | CEFBS_HasMVEInt, // MVE_VORRimmi32 = 1451 |
| 37172 | CEFBS_HasMVEInt, // MVE_VPNOT = 1452 |
| 37173 | CEFBS_HasMVEInt, // MVE_VPSEL = 1453 |
| 37174 | CEFBS_HasMVEInt, // MVE_VPST = 1454 |
| 37175 | CEFBS_HasMVEInt, // MVE_VPTv16i8 = 1455 |
| 37176 | CEFBS_HasMVEInt, // MVE_VPTv16i8r = 1456 |
| 37177 | CEFBS_HasMVEInt, // MVE_VPTv16s8 = 1457 |
| 37178 | CEFBS_HasMVEInt, // MVE_VPTv16s8r = 1458 |
| 37179 | CEFBS_HasMVEInt, // MVE_VPTv16u8 = 1459 |
| 37180 | CEFBS_HasMVEInt, // MVE_VPTv16u8r = 1460 |
| 37181 | CEFBS_HasMVEFloat, // MVE_VPTv4f32 = 1461 |
| 37182 | CEFBS_HasMVEFloat, // MVE_VPTv4f32r = 1462 |
| 37183 | CEFBS_HasMVEInt, // MVE_VPTv4i32 = 1463 |
| 37184 | CEFBS_HasMVEInt, // MVE_VPTv4i32r = 1464 |
| 37185 | CEFBS_HasMVEInt, // MVE_VPTv4s32 = 1465 |
| 37186 | CEFBS_HasMVEInt, // MVE_VPTv4s32r = 1466 |
| 37187 | CEFBS_HasMVEInt, // MVE_VPTv4u32 = 1467 |
| 37188 | CEFBS_HasMVEInt, // MVE_VPTv4u32r = 1468 |
| 37189 | CEFBS_HasMVEFloat, // MVE_VPTv8f16 = 1469 |
| 37190 | CEFBS_HasMVEFloat, // MVE_VPTv8f16r = 1470 |
| 37191 | CEFBS_HasMVEInt, // MVE_VPTv8i16 = 1471 |
| 37192 | CEFBS_HasMVEInt, // MVE_VPTv8i16r = 1472 |
| 37193 | CEFBS_HasMVEInt, // MVE_VPTv8s16 = 1473 |
| 37194 | CEFBS_HasMVEInt, // MVE_VPTv8s16r = 1474 |
| 37195 | CEFBS_HasMVEInt, // MVE_VPTv8u16 = 1475 |
| 37196 | CEFBS_HasMVEInt, // MVE_VPTv8u16r = 1476 |
| 37197 | CEFBS_HasMVEInt, // MVE_VQABSs16 = 1477 |
| 37198 | CEFBS_HasMVEInt, // MVE_VQABSs32 = 1478 |
| 37199 | CEFBS_HasMVEInt, // MVE_VQABSs8 = 1479 |
| 37200 | CEFBS_HasMVEInt, // MVE_VQADD_qr_s16 = 1480 |
| 37201 | CEFBS_HasMVEInt, // MVE_VQADD_qr_s32 = 1481 |
| 37202 | CEFBS_HasMVEInt, // MVE_VQADD_qr_s8 = 1482 |
| 37203 | CEFBS_HasMVEInt, // MVE_VQADD_qr_u16 = 1483 |
| 37204 | CEFBS_HasMVEInt, // MVE_VQADD_qr_u32 = 1484 |
| 37205 | CEFBS_HasMVEInt, // MVE_VQADD_qr_u8 = 1485 |
| 37206 | CEFBS_HasMVEInt, // MVE_VQADDs16 = 1486 |
| 37207 | CEFBS_HasMVEInt, // MVE_VQADDs32 = 1487 |
| 37208 | CEFBS_HasMVEInt, // MVE_VQADDs8 = 1488 |
| 37209 | CEFBS_HasMVEInt, // MVE_VQADDu16 = 1489 |
| 37210 | CEFBS_HasMVEInt, // MVE_VQADDu32 = 1490 |
| 37211 | CEFBS_HasMVEInt, // MVE_VQADDu8 = 1491 |
| 37212 | CEFBS_HasMVEInt, // MVE_VQDMLADHXs16 = 1492 |
| 37213 | CEFBS_HasMVEInt, // MVE_VQDMLADHXs32 = 1493 |
| 37214 | CEFBS_HasMVEInt, // MVE_VQDMLADHXs8 = 1494 |
| 37215 | CEFBS_HasMVEInt, // MVE_VQDMLADHs16 = 1495 |
| 37216 | CEFBS_HasMVEInt, // MVE_VQDMLADHs32 = 1496 |
| 37217 | CEFBS_HasMVEInt, // MVE_VQDMLADHs8 = 1497 |
| 37218 | CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs16 = 1498 |
| 37219 | CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs32 = 1499 |
| 37220 | CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs8 = 1500 |
| 37221 | CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs16 = 1501 |
| 37222 | CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs32 = 1502 |
| 37223 | CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs8 = 1503 |
| 37224 | CEFBS_HasMVEInt, // MVE_VQDMLSDHXs16 = 1504 |
| 37225 | CEFBS_HasMVEInt, // MVE_VQDMLSDHXs32 = 1505 |
| 37226 | CEFBS_HasMVEInt, // MVE_VQDMLSDHXs8 = 1506 |
| 37227 | CEFBS_HasMVEInt, // MVE_VQDMLSDHs16 = 1507 |
| 37228 | CEFBS_HasMVEInt, // MVE_VQDMLSDHs32 = 1508 |
| 37229 | CEFBS_HasMVEInt, // MVE_VQDMLSDHs8 = 1509 |
| 37230 | CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s16 = 1510 |
| 37231 | CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s32 = 1511 |
| 37232 | CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s8 = 1512 |
| 37233 | CEFBS_HasMVEInt, // MVE_VQDMULHi16 = 1513 |
| 37234 | CEFBS_HasMVEInt, // MVE_VQDMULHi32 = 1514 |
| 37235 | CEFBS_HasMVEInt, // MVE_VQDMULHi8 = 1515 |
| 37236 | CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s16bh = 1516 |
| 37237 | CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s16th = 1517 |
| 37238 | CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s32bh = 1518 |
| 37239 | CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s32th = 1519 |
| 37240 | CEFBS_HasMVEInt, // MVE_VQDMULLs16bh = 1520 |
| 37241 | CEFBS_HasMVEInt, // MVE_VQDMULLs16th = 1521 |
| 37242 | CEFBS_HasMVEInt, // MVE_VQDMULLs32bh = 1522 |
| 37243 | CEFBS_HasMVEInt, // MVE_VQDMULLs32th = 1523 |
| 37244 | CEFBS_HasMVEInt, // MVE_VQMOVNs16bh = 1524 |
| 37245 | CEFBS_HasMVEInt, // MVE_VQMOVNs16th = 1525 |
| 37246 | CEFBS_HasMVEInt, // MVE_VQMOVNs32bh = 1526 |
| 37247 | CEFBS_HasMVEInt, // MVE_VQMOVNs32th = 1527 |
| 37248 | CEFBS_HasMVEInt, // MVE_VQMOVNu16bh = 1528 |
| 37249 | CEFBS_HasMVEInt, // MVE_VQMOVNu16th = 1529 |
| 37250 | CEFBS_HasMVEInt, // MVE_VQMOVNu32bh = 1530 |
| 37251 | CEFBS_HasMVEInt, // MVE_VQMOVNu32th = 1531 |
| 37252 | CEFBS_HasMVEInt, // MVE_VQMOVUNs16bh = 1532 |
| 37253 | CEFBS_HasMVEInt, // MVE_VQMOVUNs16th = 1533 |
| 37254 | CEFBS_HasMVEInt, // MVE_VQMOVUNs32bh = 1534 |
| 37255 | CEFBS_HasMVEInt, // MVE_VQMOVUNs32th = 1535 |
| 37256 | CEFBS_HasMVEInt, // MVE_VQNEGs16 = 1536 |
| 37257 | CEFBS_HasMVEInt, // MVE_VQNEGs32 = 1537 |
| 37258 | CEFBS_HasMVEInt, // MVE_VQNEGs8 = 1538 |
| 37259 | CEFBS_HasMVEInt, // MVE_VQRDMLADHXs16 = 1539 |
| 37260 | CEFBS_HasMVEInt, // MVE_VQRDMLADHXs32 = 1540 |
| 37261 | CEFBS_HasMVEInt, // MVE_VQRDMLADHXs8 = 1541 |
| 37262 | CEFBS_HasMVEInt, // MVE_VQRDMLADHs16 = 1542 |
| 37263 | CEFBS_HasMVEInt, // MVE_VQRDMLADHs32 = 1543 |
| 37264 | CEFBS_HasMVEInt, // MVE_VQRDMLADHs8 = 1544 |
| 37265 | CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs16 = 1545 |
| 37266 | CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs32 = 1546 |
| 37267 | CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs8 = 1547 |
| 37268 | CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs16 = 1548 |
| 37269 | CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs32 = 1549 |
| 37270 | CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs8 = 1550 |
| 37271 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs16 = 1551 |
| 37272 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs32 = 1552 |
| 37273 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs8 = 1553 |
| 37274 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHs16 = 1554 |
| 37275 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHs32 = 1555 |
| 37276 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHs8 = 1556 |
| 37277 | CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s16 = 1557 |
| 37278 | CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s32 = 1558 |
| 37279 | CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s8 = 1559 |
| 37280 | CEFBS_HasMVEInt, // MVE_VQRDMULHi16 = 1560 |
| 37281 | CEFBS_HasMVEInt, // MVE_VQRDMULHi32 = 1561 |
| 37282 | CEFBS_HasMVEInt, // MVE_VQRDMULHi8 = 1562 |
| 37283 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs16 = 1563 |
| 37284 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs32 = 1564 |
| 37285 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs8 = 1565 |
| 37286 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu16 = 1566 |
| 37287 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu32 = 1567 |
| 37288 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu8 = 1568 |
| 37289 | CEFBS_HasMVEInt, // MVE_VQRSHL_qrs16 = 1569 |
| 37290 | CEFBS_HasMVEInt, // MVE_VQRSHL_qrs32 = 1570 |
| 37291 | CEFBS_HasMVEInt, // MVE_VQRSHL_qrs8 = 1571 |
| 37292 | CEFBS_HasMVEInt, // MVE_VQRSHL_qru16 = 1572 |
| 37293 | CEFBS_HasMVEInt, // MVE_VQRSHL_qru32 = 1573 |
| 37294 | CEFBS_HasMVEInt, // MVE_VQRSHL_qru8 = 1574 |
| 37295 | CEFBS_HasMVEInt, // MVE_VQRSHRNbhs16 = 1575 |
| 37296 | CEFBS_HasMVEInt, // MVE_VQRSHRNbhs32 = 1576 |
| 37297 | CEFBS_HasMVEInt, // MVE_VQRSHRNbhu16 = 1577 |
| 37298 | CEFBS_HasMVEInt, // MVE_VQRSHRNbhu32 = 1578 |
| 37299 | CEFBS_HasMVEInt, // MVE_VQRSHRNths16 = 1579 |
| 37300 | CEFBS_HasMVEInt, // MVE_VQRSHRNths32 = 1580 |
| 37301 | CEFBS_HasMVEInt, // MVE_VQRSHRNthu16 = 1581 |
| 37302 | CEFBS_HasMVEInt, // MVE_VQRSHRNthu32 = 1582 |
| 37303 | CEFBS_HasMVEInt, // MVE_VQRSHRUNs16bh = 1583 |
| 37304 | CEFBS_HasMVEInt, // MVE_VQRSHRUNs16th = 1584 |
| 37305 | CEFBS_HasMVEInt, // MVE_VQRSHRUNs32bh = 1585 |
| 37306 | CEFBS_HasMVEInt, // MVE_VQRSHRUNs32th = 1586 |
| 37307 | CEFBS_HasMVEInt, // MVE_VQSHLU_imms16 = 1587 |
| 37308 | CEFBS_HasMVEInt, // MVE_VQSHLU_imms32 = 1588 |
| 37309 | CEFBS_HasMVEInt, // MVE_VQSHLU_imms8 = 1589 |
| 37310 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs16 = 1590 |
| 37311 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs32 = 1591 |
| 37312 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs8 = 1592 |
| 37313 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu16 = 1593 |
| 37314 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu32 = 1594 |
| 37315 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu8 = 1595 |
| 37316 | CEFBS_HasMVEInt, // MVE_VQSHL_qrs16 = 1596 |
| 37317 | CEFBS_HasMVEInt, // MVE_VQSHL_qrs32 = 1597 |
| 37318 | CEFBS_HasMVEInt, // MVE_VQSHL_qrs8 = 1598 |
| 37319 | CEFBS_HasMVEInt, // MVE_VQSHL_qru16 = 1599 |
| 37320 | CEFBS_HasMVEInt, // MVE_VQSHL_qru32 = 1600 |
| 37321 | CEFBS_HasMVEInt, // MVE_VQSHL_qru8 = 1601 |
| 37322 | CEFBS_HasMVEInt, // MVE_VQSHLimms16 = 1602 |
| 37323 | CEFBS_HasMVEInt, // MVE_VQSHLimms32 = 1603 |
| 37324 | CEFBS_HasMVEInt, // MVE_VQSHLimms8 = 1604 |
| 37325 | CEFBS_HasMVEInt, // MVE_VQSHLimmu16 = 1605 |
| 37326 | CEFBS_HasMVEInt, // MVE_VQSHLimmu32 = 1606 |
| 37327 | CEFBS_HasMVEInt, // MVE_VQSHLimmu8 = 1607 |
| 37328 | CEFBS_HasMVEInt, // MVE_VQSHRNbhs16 = 1608 |
| 37329 | CEFBS_HasMVEInt, // MVE_VQSHRNbhs32 = 1609 |
| 37330 | CEFBS_HasMVEInt, // MVE_VQSHRNbhu16 = 1610 |
| 37331 | CEFBS_HasMVEInt, // MVE_VQSHRNbhu32 = 1611 |
| 37332 | CEFBS_HasMVEInt, // MVE_VQSHRNths16 = 1612 |
| 37333 | CEFBS_HasMVEInt, // MVE_VQSHRNths32 = 1613 |
| 37334 | CEFBS_HasMVEInt, // MVE_VQSHRNthu16 = 1614 |
| 37335 | CEFBS_HasMVEInt, // MVE_VQSHRNthu32 = 1615 |
| 37336 | CEFBS_HasMVEInt, // MVE_VQSHRUNs16bh = 1616 |
| 37337 | CEFBS_HasMVEInt, // MVE_VQSHRUNs16th = 1617 |
| 37338 | CEFBS_HasMVEInt, // MVE_VQSHRUNs32bh = 1618 |
| 37339 | CEFBS_HasMVEInt, // MVE_VQSHRUNs32th = 1619 |
| 37340 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_s16 = 1620 |
| 37341 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_s32 = 1621 |
| 37342 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_s8 = 1622 |
| 37343 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_u16 = 1623 |
| 37344 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_u32 = 1624 |
| 37345 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_u8 = 1625 |
| 37346 | CEFBS_HasMVEInt, // MVE_VQSUBs16 = 1626 |
| 37347 | CEFBS_HasMVEInt, // MVE_VQSUBs32 = 1627 |
| 37348 | CEFBS_HasMVEInt, // MVE_VQSUBs8 = 1628 |
| 37349 | CEFBS_HasMVEInt, // MVE_VQSUBu16 = 1629 |
| 37350 | CEFBS_HasMVEInt, // MVE_VQSUBu32 = 1630 |
| 37351 | CEFBS_HasMVEInt, // MVE_VQSUBu8 = 1631 |
| 37352 | CEFBS_HasMVEInt, // MVE_VREV16_8 = 1632 |
| 37353 | CEFBS_HasMVEInt, // MVE_VREV32_16 = 1633 |
| 37354 | CEFBS_HasMVEInt, // MVE_VREV32_8 = 1634 |
| 37355 | CEFBS_HasMVEInt, // MVE_VREV64_16 = 1635 |
| 37356 | CEFBS_HasMVEInt, // MVE_VREV64_32 = 1636 |
| 37357 | CEFBS_HasMVEInt, // MVE_VREV64_8 = 1637 |
| 37358 | CEFBS_HasMVEInt, // MVE_VRHADDs16 = 1638 |
| 37359 | CEFBS_HasMVEInt, // MVE_VRHADDs32 = 1639 |
| 37360 | CEFBS_HasMVEInt, // MVE_VRHADDs8 = 1640 |
| 37361 | CEFBS_HasMVEInt, // MVE_VRHADDu16 = 1641 |
| 37362 | CEFBS_HasMVEInt, // MVE_VRHADDu32 = 1642 |
| 37363 | CEFBS_HasMVEInt, // MVE_VRHADDu8 = 1643 |
| 37364 | CEFBS_HasMVEFloat, // MVE_VRINTf16A = 1644 |
| 37365 | CEFBS_HasMVEFloat, // MVE_VRINTf16M = 1645 |
| 37366 | CEFBS_HasMVEFloat, // MVE_VRINTf16N = 1646 |
| 37367 | CEFBS_HasMVEFloat, // MVE_VRINTf16P = 1647 |
| 37368 | CEFBS_HasMVEFloat, // MVE_VRINTf16X = 1648 |
| 37369 | CEFBS_HasMVEFloat, // MVE_VRINTf16Z = 1649 |
| 37370 | CEFBS_HasMVEFloat, // MVE_VRINTf32A = 1650 |
| 37371 | CEFBS_HasMVEFloat, // MVE_VRINTf32M = 1651 |
| 37372 | CEFBS_HasMVEFloat, // MVE_VRINTf32N = 1652 |
| 37373 | CEFBS_HasMVEFloat, // MVE_VRINTf32P = 1653 |
| 37374 | CEFBS_HasMVEFloat, // MVE_VRINTf32X = 1654 |
| 37375 | CEFBS_HasMVEFloat, // MVE_VRINTf32Z = 1655 |
| 37376 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHas32 = 1656 |
| 37377 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHau32 = 1657 |
| 37378 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHaxs32 = 1658 |
| 37379 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHs32 = 1659 |
| 37380 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHu32 = 1660 |
| 37381 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHxs32 = 1661 |
| 37382 | CEFBS_HasMVEInt, // MVE_VRMLSLDAVHas32 = 1662 |
| 37383 | CEFBS_HasMVEInt, // MVE_VRMLSLDAVHaxs32 = 1663 |
| 37384 | CEFBS_HasMVEInt, // MVE_VRMLSLDAVHs32 = 1664 |
| 37385 | CEFBS_HasMVEInt, // MVE_VRMLSLDAVHxs32 = 1665 |
| 37386 | CEFBS_HasMVEInt, // MVE_VRMULHs16 = 1666 |
| 37387 | CEFBS_HasMVEInt, // MVE_VRMULHs32 = 1667 |
| 37388 | CEFBS_HasMVEInt, // MVE_VRMULHs8 = 1668 |
| 37389 | CEFBS_HasMVEInt, // MVE_VRMULHu16 = 1669 |
| 37390 | CEFBS_HasMVEInt, // MVE_VRMULHu32 = 1670 |
| 37391 | CEFBS_HasMVEInt, // MVE_VRMULHu8 = 1671 |
| 37392 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs16 = 1672 |
| 37393 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs32 = 1673 |
| 37394 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs8 = 1674 |
| 37395 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu16 = 1675 |
| 37396 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu32 = 1676 |
| 37397 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu8 = 1677 |
| 37398 | CEFBS_HasMVEInt, // MVE_VRSHL_qrs16 = 1678 |
| 37399 | CEFBS_HasMVEInt, // MVE_VRSHL_qrs32 = 1679 |
| 37400 | CEFBS_HasMVEInt, // MVE_VRSHL_qrs8 = 1680 |
| 37401 | CEFBS_HasMVEInt, // MVE_VRSHL_qru16 = 1681 |
| 37402 | CEFBS_HasMVEInt, // MVE_VRSHL_qru32 = 1682 |
| 37403 | CEFBS_HasMVEInt, // MVE_VRSHL_qru8 = 1683 |
| 37404 | CEFBS_HasMVEInt, // MVE_VRSHRNi16bh = 1684 |
| 37405 | CEFBS_HasMVEInt, // MVE_VRSHRNi16th = 1685 |
| 37406 | CEFBS_HasMVEInt, // MVE_VRSHRNi32bh = 1686 |
| 37407 | CEFBS_HasMVEInt, // MVE_VRSHRNi32th = 1687 |
| 37408 | CEFBS_HasMVEInt, // MVE_VRSHR_imms16 = 1688 |
| 37409 | CEFBS_HasMVEInt, // MVE_VRSHR_imms32 = 1689 |
| 37410 | CEFBS_HasMVEInt, // MVE_VRSHR_imms8 = 1690 |
| 37411 | CEFBS_HasMVEInt, // MVE_VRSHR_immu16 = 1691 |
| 37412 | CEFBS_HasMVEInt, // MVE_VRSHR_immu32 = 1692 |
| 37413 | CEFBS_HasMVEInt, // MVE_VRSHR_immu8 = 1693 |
| 37414 | CEFBS_HasMVEInt, // MVE_VSBC = 1694 |
| 37415 | CEFBS_HasMVEInt, // MVE_VSBCI = 1695 |
| 37416 | CEFBS_HasMVEInt, // MVE_VSHLC = 1696 |
| 37417 | CEFBS_HasMVEInt, // MVE_VSHLL_imms16bh = 1697 |
| 37418 | CEFBS_HasMVEInt, // MVE_VSHLL_imms16th = 1698 |
| 37419 | CEFBS_HasMVEInt, // MVE_VSHLL_imms8bh = 1699 |
| 37420 | CEFBS_HasMVEInt, // MVE_VSHLL_imms8th = 1700 |
| 37421 | CEFBS_HasMVEInt, // MVE_VSHLL_immu16bh = 1701 |
| 37422 | CEFBS_HasMVEInt, // MVE_VSHLL_immu16th = 1702 |
| 37423 | CEFBS_HasMVEInt, // MVE_VSHLL_immu8bh = 1703 |
| 37424 | CEFBS_HasMVEInt, // MVE_VSHLL_immu8th = 1704 |
| 37425 | CEFBS_HasMVEInt, // MVE_VSHLL_lws16bh = 1705 |
| 37426 | CEFBS_HasMVEInt, // MVE_VSHLL_lws16th = 1706 |
| 37427 | CEFBS_HasMVEInt, // MVE_VSHLL_lws8bh = 1707 |
| 37428 | CEFBS_HasMVEInt, // MVE_VSHLL_lws8th = 1708 |
| 37429 | CEFBS_HasMVEInt, // MVE_VSHLL_lwu16bh = 1709 |
| 37430 | CEFBS_HasMVEInt, // MVE_VSHLL_lwu16th = 1710 |
| 37431 | CEFBS_HasMVEInt, // MVE_VSHLL_lwu8bh = 1711 |
| 37432 | CEFBS_HasMVEInt, // MVE_VSHLL_lwu8th = 1712 |
| 37433 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecs16 = 1713 |
| 37434 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecs32 = 1714 |
| 37435 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecs8 = 1715 |
| 37436 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecu16 = 1716 |
| 37437 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecu32 = 1717 |
| 37438 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecu8 = 1718 |
| 37439 | CEFBS_HasMVEInt, // MVE_VSHL_immi16 = 1719 |
| 37440 | CEFBS_HasMVEInt, // MVE_VSHL_immi32 = 1720 |
| 37441 | CEFBS_HasMVEInt, // MVE_VSHL_immi8 = 1721 |
| 37442 | CEFBS_HasMVEInt, // MVE_VSHL_qrs16 = 1722 |
| 37443 | CEFBS_HasMVEInt, // MVE_VSHL_qrs32 = 1723 |
| 37444 | CEFBS_HasMVEInt, // MVE_VSHL_qrs8 = 1724 |
| 37445 | CEFBS_HasMVEInt, // MVE_VSHL_qru16 = 1725 |
| 37446 | CEFBS_HasMVEInt, // MVE_VSHL_qru32 = 1726 |
| 37447 | CEFBS_HasMVEInt, // MVE_VSHL_qru8 = 1727 |
| 37448 | CEFBS_HasMVEInt, // MVE_VSHRNi16bh = 1728 |
| 37449 | CEFBS_HasMVEInt, // MVE_VSHRNi16th = 1729 |
| 37450 | CEFBS_HasMVEInt, // MVE_VSHRNi32bh = 1730 |
| 37451 | CEFBS_HasMVEInt, // MVE_VSHRNi32th = 1731 |
| 37452 | CEFBS_HasMVEInt, // MVE_VSHR_imms16 = 1732 |
| 37453 | CEFBS_HasMVEInt, // MVE_VSHR_imms32 = 1733 |
| 37454 | CEFBS_HasMVEInt, // MVE_VSHR_imms8 = 1734 |
| 37455 | CEFBS_HasMVEInt, // MVE_VSHR_immu16 = 1735 |
| 37456 | CEFBS_HasMVEInt, // MVE_VSHR_immu32 = 1736 |
| 37457 | CEFBS_HasMVEInt, // MVE_VSHR_immu8 = 1737 |
| 37458 | CEFBS_HasMVEInt, // MVE_VSLIimm16 = 1738 |
| 37459 | CEFBS_HasMVEInt, // MVE_VSLIimm32 = 1739 |
| 37460 | CEFBS_HasMVEInt, // MVE_VSLIimm8 = 1740 |
| 37461 | CEFBS_HasMVEInt, // MVE_VSRIimm16 = 1741 |
| 37462 | CEFBS_HasMVEInt, // MVE_VSRIimm32 = 1742 |
| 37463 | CEFBS_HasMVEInt, // MVE_VSRIimm8 = 1743 |
| 37464 | CEFBS_HasMVEInt, // MVE_VST20_16 = 1744 |
| 37465 | CEFBS_HasMVEInt, // MVE_VST20_16_wb = 1745 |
| 37466 | CEFBS_HasMVEInt, // MVE_VST20_32 = 1746 |
| 37467 | CEFBS_HasMVEInt, // MVE_VST20_32_wb = 1747 |
| 37468 | CEFBS_HasMVEInt, // MVE_VST20_8 = 1748 |
| 37469 | CEFBS_HasMVEInt, // MVE_VST20_8_wb = 1749 |
| 37470 | CEFBS_HasMVEInt, // MVE_VST21_16 = 1750 |
| 37471 | CEFBS_HasMVEInt, // MVE_VST21_16_wb = 1751 |
| 37472 | CEFBS_HasMVEInt, // MVE_VST21_32 = 1752 |
| 37473 | CEFBS_HasMVEInt, // MVE_VST21_32_wb = 1753 |
| 37474 | CEFBS_HasMVEInt, // MVE_VST21_8 = 1754 |
| 37475 | CEFBS_HasMVEInt, // MVE_VST21_8_wb = 1755 |
| 37476 | CEFBS_HasMVEInt, // MVE_VST40_16 = 1756 |
| 37477 | CEFBS_HasMVEInt, // MVE_VST40_16_wb = 1757 |
| 37478 | CEFBS_HasMVEInt, // MVE_VST40_32 = 1758 |
| 37479 | CEFBS_HasMVEInt, // MVE_VST40_32_wb = 1759 |
| 37480 | CEFBS_HasMVEInt, // MVE_VST40_8 = 1760 |
| 37481 | CEFBS_HasMVEInt, // MVE_VST40_8_wb = 1761 |
| 37482 | CEFBS_HasMVEInt, // MVE_VST41_16 = 1762 |
| 37483 | CEFBS_HasMVEInt, // MVE_VST41_16_wb = 1763 |
| 37484 | CEFBS_HasMVEInt, // MVE_VST41_32 = 1764 |
| 37485 | CEFBS_HasMVEInt, // MVE_VST41_32_wb = 1765 |
| 37486 | CEFBS_HasMVEInt, // MVE_VST41_8 = 1766 |
| 37487 | CEFBS_HasMVEInt, // MVE_VST41_8_wb = 1767 |
| 37488 | CEFBS_HasMVEInt, // MVE_VST42_16 = 1768 |
| 37489 | CEFBS_HasMVEInt, // MVE_VST42_16_wb = 1769 |
| 37490 | CEFBS_HasMVEInt, // MVE_VST42_32 = 1770 |
| 37491 | CEFBS_HasMVEInt, // MVE_VST42_32_wb = 1771 |
| 37492 | CEFBS_HasMVEInt, // MVE_VST42_8 = 1772 |
| 37493 | CEFBS_HasMVEInt, // MVE_VST42_8_wb = 1773 |
| 37494 | CEFBS_HasMVEInt, // MVE_VST43_16 = 1774 |
| 37495 | CEFBS_HasMVEInt, // MVE_VST43_16_wb = 1775 |
| 37496 | CEFBS_HasMVEInt, // MVE_VST43_32 = 1776 |
| 37497 | CEFBS_HasMVEInt, // MVE_VST43_32_wb = 1777 |
| 37498 | CEFBS_HasMVEInt, // MVE_VST43_8 = 1778 |
| 37499 | CEFBS_HasMVEInt, // MVE_VST43_8_wb = 1779 |
| 37500 | CEFBS_HasMVEInt, // MVE_VSTRB16 = 1780 |
| 37501 | CEFBS_HasMVEInt, // MVE_VSTRB16_post = 1781 |
| 37502 | CEFBS_HasMVEInt, // MVE_VSTRB16_pre = 1782 |
| 37503 | CEFBS_HasMVEInt, // MVE_VSTRB16_rq = 1783 |
| 37504 | CEFBS_HasMVEInt, // MVE_VSTRB32 = 1784 |
| 37505 | CEFBS_HasMVEInt, // MVE_VSTRB32_post = 1785 |
| 37506 | CEFBS_HasMVEInt, // MVE_VSTRB32_pre = 1786 |
| 37507 | CEFBS_HasMVEInt, // MVE_VSTRB32_rq = 1787 |
| 37508 | CEFBS_HasMVEInt, // MVE_VSTRB8_rq = 1788 |
| 37509 | CEFBS_HasMVEInt, // MVE_VSTRBU8 = 1789 |
| 37510 | CEFBS_HasMVEInt, // MVE_VSTRBU8_post = 1790 |
| 37511 | CEFBS_HasMVEInt, // MVE_VSTRBU8_pre = 1791 |
| 37512 | CEFBS_HasMVEInt, // MVE_VSTRD64_qi = 1792 |
| 37513 | CEFBS_HasMVEInt, // MVE_VSTRD64_qi_pre = 1793 |
| 37514 | CEFBS_HasMVEInt, // MVE_VSTRD64_rq = 1794 |
| 37515 | CEFBS_HasMVEInt, // MVE_VSTRD64_rq_u = 1795 |
| 37516 | CEFBS_HasMVEInt, // MVE_VSTRH16_rq = 1796 |
| 37517 | CEFBS_HasMVEInt, // MVE_VSTRH16_rq_u = 1797 |
| 37518 | CEFBS_HasMVEInt, // MVE_VSTRH32 = 1798 |
| 37519 | CEFBS_HasMVEInt, // MVE_VSTRH32_post = 1799 |
| 37520 | CEFBS_HasMVEInt, // MVE_VSTRH32_pre = 1800 |
| 37521 | CEFBS_HasMVEInt, // MVE_VSTRH32_rq = 1801 |
| 37522 | CEFBS_HasMVEInt, // MVE_VSTRH32_rq_u = 1802 |
| 37523 | CEFBS_HasMVEInt, // MVE_VSTRHU16 = 1803 |
| 37524 | CEFBS_HasMVEInt, // MVE_VSTRHU16_post = 1804 |
| 37525 | CEFBS_HasMVEInt, // MVE_VSTRHU16_pre = 1805 |
| 37526 | CEFBS_HasMVEInt, // MVE_VSTRW32_qi = 1806 |
| 37527 | CEFBS_HasMVEInt, // MVE_VSTRW32_qi_pre = 1807 |
| 37528 | CEFBS_HasMVEInt, // MVE_VSTRW32_rq = 1808 |
| 37529 | CEFBS_HasMVEInt, // MVE_VSTRW32_rq_u = 1809 |
| 37530 | CEFBS_HasMVEInt, // MVE_VSTRWU32 = 1810 |
| 37531 | CEFBS_HasMVEInt, // MVE_VSTRWU32_post = 1811 |
| 37532 | CEFBS_HasMVEInt, // MVE_VSTRWU32_pre = 1812 |
| 37533 | CEFBS_HasMVEFloat, // MVE_VSUB_qr_f16 = 1813 |
| 37534 | CEFBS_HasMVEFloat, // MVE_VSUB_qr_f32 = 1814 |
| 37535 | CEFBS_HasMVEInt, // MVE_VSUB_qr_i16 = 1815 |
| 37536 | CEFBS_HasMVEInt, // MVE_VSUB_qr_i32 = 1816 |
| 37537 | CEFBS_HasMVEInt, // MVE_VSUB_qr_i8 = 1817 |
| 37538 | CEFBS_HasMVEFloat, // MVE_VSUBf16 = 1818 |
| 37539 | CEFBS_HasMVEFloat, // MVE_VSUBf32 = 1819 |
| 37540 | CEFBS_HasMVEInt, // MVE_VSUBi16 = 1820 |
| 37541 | CEFBS_HasMVEInt, // MVE_VSUBi32 = 1821 |
| 37542 | CEFBS_HasMVEInt, // MVE_VSUBi8 = 1822 |
| 37543 | CEFBS_HasMVEInt, // MVE_WLSTP_16 = 1823 |
| 37544 | CEFBS_HasMVEInt, // MVE_WLSTP_32 = 1824 |
| 37545 | CEFBS_HasMVEInt, // MVE_WLSTP_64 = 1825 |
| 37546 | CEFBS_HasMVEInt, // MVE_WLSTP_8 = 1826 |
| 37547 | CEFBS_IsARM, // MVNi = 1827 |
| 37548 | CEFBS_IsARM, // MVNr = 1828 |
| 37549 | CEFBS_IsARM, // MVNsi = 1829 |
| 37550 | CEFBS_IsARM, // MVNsr = 1830 |
| 37551 | CEFBS_HasFPARMv8_HasNEON, // NEON_VMAXNMNDf = 1831 |
| 37552 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, // NEON_VMAXNMNDh = 1832 |
| 37553 | CEFBS_HasFPARMv8_HasNEON, // NEON_VMAXNMNQf = 1833 |
| 37554 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, // NEON_VMAXNMNQh = 1834 |
| 37555 | CEFBS_HasFPARMv8_HasNEON, // NEON_VMINNMNDf = 1835 |
| 37556 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, // NEON_VMINNMNDh = 1836 |
| 37557 | CEFBS_HasFPARMv8_HasNEON, // NEON_VMINNMNQf = 1837 |
| 37558 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, // NEON_VMINNMNQh = 1838 |
| 37559 | CEFBS_IsARM, // ORRri = 1839 |
| 37560 | CEFBS_IsARM, // ORRrr = 1840 |
| 37561 | CEFBS_IsARM, // ORRrsi = 1841 |
| 37562 | CEFBS_IsARM, // ORRrsr = 1842 |
| 37563 | CEFBS_IsARM_HasV6, // PKHBT = 1843 |
| 37564 | CEFBS_IsARM_HasV6, // PKHTB = 1844 |
| 37565 | CEFBS_IsARM_HasV7_HasMP, // PLDWi12 = 1845 |
| 37566 | CEFBS_IsARM_HasV7_HasMP, // PLDWrs = 1846 |
| 37567 | CEFBS_IsARM, // PLDi12 = 1847 |
| 37568 | CEFBS_IsARM, // PLDrs = 1848 |
| 37569 | CEFBS_IsARM_HasV7, // PLIi12 = 1849 |
| 37570 | CEFBS_IsARM_HasV7, // PLIrs = 1850 |
| 37571 | CEFBS_IsARM, // QADD = 1851 |
| 37572 | CEFBS_IsARM, // QADD16 = 1852 |
| 37573 | CEFBS_IsARM, // QADD8 = 1853 |
| 37574 | CEFBS_IsARM, // QASX = 1854 |
| 37575 | CEFBS_IsARM, // QDADD = 1855 |
| 37576 | CEFBS_IsARM, // QDSUB = 1856 |
| 37577 | CEFBS_IsARM, // QSAX = 1857 |
| 37578 | CEFBS_IsARM, // QSUB = 1858 |
| 37579 | CEFBS_IsARM, // QSUB16 = 1859 |
| 37580 | CEFBS_IsARM, // QSUB8 = 1860 |
| 37581 | CEFBS_IsARM_HasV6T2, // RBIT = 1861 |
| 37582 | CEFBS_IsARM_HasV6, // REV = 1862 |
| 37583 | CEFBS_IsARM_HasV6, // REV16 = 1863 |
| 37584 | CEFBS_IsARM_HasV6, // REVSH = 1864 |
| 37585 | CEFBS_IsARM, // RFEDA = 1865 |
| 37586 | CEFBS_IsARM, // RFEDA_UPD = 1866 |
| 37587 | CEFBS_IsARM, // RFEDB = 1867 |
| 37588 | CEFBS_IsARM, // RFEDB_UPD = 1868 |
| 37589 | CEFBS_IsARM, // RFEIA = 1869 |
| 37590 | CEFBS_IsARM, // RFEIA_UPD = 1870 |
| 37591 | CEFBS_IsARM, // RFEIB = 1871 |
| 37592 | CEFBS_IsARM, // RFEIB_UPD = 1872 |
| 37593 | CEFBS_IsARM, // RSBri = 1873 |
| 37594 | CEFBS_IsARM, // RSBrr = 1874 |
| 37595 | CEFBS_IsARM, // RSBrsi = 1875 |
| 37596 | CEFBS_IsARM, // RSBrsr = 1876 |
| 37597 | CEFBS_IsARM, // RSCri = 1877 |
| 37598 | CEFBS_IsARM, // RSCrr = 1878 |
| 37599 | CEFBS_IsARM, // RSCrsi = 1879 |
| 37600 | CEFBS_IsARM, // RSCrsr = 1880 |
| 37601 | CEFBS_IsARM, // SADD16 = 1881 |
| 37602 | CEFBS_IsARM, // SADD8 = 1882 |
| 37603 | CEFBS_IsARM, // SASX = 1883 |
| 37604 | CEFBS_IsARM_HasSB, // SB = 1884 |
| 37605 | CEFBS_IsARM, // SBCri = 1885 |
| 37606 | CEFBS_IsARM, // SBCrr = 1886 |
| 37607 | CEFBS_IsARM, // SBCrsi = 1887 |
| 37608 | CEFBS_IsARM, // SBCrsr = 1888 |
| 37609 | CEFBS_IsARM_HasV6T2, // SBFX = 1889 |
| 37610 | CEFBS_IsARM_HasDivideInARM, // SDIV = 1890 |
| 37611 | CEFBS_IsARM_HasV6, // SEL = 1891 |
| 37612 | CEFBS_IsARM, // SETEND = 1892 |
| 37613 | CEFBS_IsARM_HasV8_HasV8_1a, // SETPAN = 1893 |
| 37614 | CEFBS_HasV8_HasSHA2, // SHA1C = 1894 |
| 37615 | CEFBS_HasV8_HasSHA2, // SHA1H = 1895 |
| 37616 | CEFBS_HasV8_HasSHA2, // SHA1M = 1896 |
| 37617 | CEFBS_HasV8_HasSHA2, // SHA1P = 1897 |
| 37618 | CEFBS_HasV8_HasSHA2, // SHA1SU0 = 1898 |
| 37619 | CEFBS_HasV8_HasSHA2, // SHA1SU1 = 1899 |
| 37620 | CEFBS_HasV8_HasSHA2, // SHA256H = 1900 |
| 37621 | CEFBS_HasV8_HasSHA2, // SHA256H2 = 1901 |
| 37622 | CEFBS_HasV8_HasSHA2, // SHA256SU0 = 1902 |
| 37623 | CEFBS_HasV8_HasSHA2, // SHA256SU1 = 1903 |
| 37624 | CEFBS_IsARM, // SHADD16 = 1904 |
| 37625 | CEFBS_IsARM, // SHADD8 = 1905 |
| 37626 | CEFBS_IsARM, // SHASX = 1906 |
| 37627 | CEFBS_IsARM, // SHSAX = 1907 |
| 37628 | CEFBS_IsARM, // SHSUB16 = 1908 |
| 37629 | CEFBS_IsARM, // SHSUB8 = 1909 |
| 37630 | CEFBS_IsARM_HasTrustZone, // SMC = 1910 |
| 37631 | CEFBS_IsARM_HasV5TE, // SMLABB = 1911 |
| 37632 | CEFBS_IsARM_HasV5TE, // SMLABT = 1912 |
| 37633 | CEFBS_IsARM_HasV6, // SMLAD = 1913 |
| 37634 | CEFBS_IsARM_HasV6, // SMLADX = 1914 |
| 37635 | CEFBS_IsARM_HasV6, // SMLAL = 1915 |
| 37636 | CEFBS_IsARM_HasV5TE, // SMLALBB = 1916 |
| 37637 | CEFBS_IsARM_HasV5TE, // SMLALBT = 1917 |
| 37638 | CEFBS_IsARM_HasV6, // SMLALD = 1918 |
| 37639 | CEFBS_IsARM_HasV6, // SMLALDX = 1919 |
| 37640 | CEFBS_IsARM_HasV5TE, // SMLALTB = 1920 |
| 37641 | CEFBS_IsARM_HasV5TE, // SMLALTT = 1921 |
| 37642 | CEFBS_IsARM_HasV5TE, // SMLATB = 1922 |
| 37643 | CEFBS_IsARM_HasV5TE, // SMLATT = 1923 |
| 37644 | CEFBS_IsARM_HasV5TE, // SMLAWB = 1924 |
| 37645 | CEFBS_IsARM_HasV5TE, // SMLAWT = 1925 |
| 37646 | CEFBS_IsARM_HasV6, // SMLSD = 1926 |
| 37647 | CEFBS_IsARM_HasV6, // SMLSDX = 1927 |
| 37648 | CEFBS_IsARM_HasV6, // SMLSLD = 1928 |
| 37649 | CEFBS_IsARM_HasV6, // SMLSLDX = 1929 |
| 37650 | CEFBS_IsARM_HasV6, // SMMLA = 1930 |
| 37651 | CEFBS_IsARM_HasV6, // SMMLAR = 1931 |
| 37652 | CEFBS_IsARM_HasV6, // SMMLS = 1932 |
| 37653 | CEFBS_IsARM_HasV6, // SMMLSR = 1933 |
| 37654 | CEFBS_IsARM_HasV6, // SMMUL = 1934 |
| 37655 | CEFBS_IsARM_HasV6, // SMMULR = 1935 |
| 37656 | CEFBS_IsARM_HasV6, // SMUAD = 1936 |
| 37657 | CEFBS_IsARM_HasV6, // SMUADX = 1937 |
| 37658 | CEFBS_IsARM_HasV5TE, // SMULBB = 1938 |
| 37659 | CEFBS_IsARM_HasV5TE, // SMULBT = 1939 |
| 37660 | CEFBS_IsARM_HasV6, // SMULL = 1940 |
| 37661 | CEFBS_IsARM_HasV5TE, // SMULTB = 1941 |
| 37662 | CEFBS_IsARM_HasV5TE, // SMULTT = 1942 |
| 37663 | CEFBS_IsARM_HasV5TE, // SMULWB = 1943 |
| 37664 | CEFBS_IsARM_HasV5TE, // SMULWT = 1944 |
| 37665 | CEFBS_IsARM_HasV6, // SMUSD = 1945 |
| 37666 | CEFBS_IsARM_HasV6, // SMUSDX = 1946 |
| 37667 | CEFBS_IsARM, // SRSDA = 1947 |
| 37668 | CEFBS_IsARM, // SRSDA_UPD = 1948 |
| 37669 | CEFBS_IsARM, // SRSDB = 1949 |
| 37670 | CEFBS_IsARM, // SRSDB_UPD = 1950 |
| 37671 | CEFBS_IsARM, // SRSIA = 1951 |
| 37672 | CEFBS_IsARM, // SRSIA_UPD = 1952 |
| 37673 | CEFBS_IsARM, // SRSIB = 1953 |
| 37674 | CEFBS_IsARM, // SRSIB_UPD = 1954 |
| 37675 | CEFBS_IsARM_HasV6, // SSAT = 1955 |
| 37676 | CEFBS_IsARM_HasV6, // SSAT16 = 1956 |
| 37677 | CEFBS_IsARM, // SSAX = 1957 |
| 37678 | CEFBS_IsARM, // SSUB16 = 1958 |
| 37679 | CEFBS_IsARM, // SSUB8 = 1959 |
| 37680 | CEFBS_IsARM_PreV8, // STC2L_OFFSET = 1960 |
| 37681 | CEFBS_IsARM_PreV8, // STC2L_OPTION = 1961 |
| 37682 | CEFBS_IsARM_PreV8, // STC2L_POST = 1962 |
| 37683 | CEFBS_IsARM_PreV8, // STC2L_PRE = 1963 |
| 37684 | CEFBS_IsARM_PreV8, // STC2_OFFSET = 1964 |
| 37685 | CEFBS_IsARM_PreV8, // STC2_OPTION = 1965 |
| 37686 | CEFBS_IsARM_PreV8, // STC2_POST = 1966 |
| 37687 | CEFBS_IsARM_PreV8, // STC2_PRE = 1967 |
| 37688 | CEFBS_IsARM, // STCL_OFFSET = 1968 |
| 37689 | CEFBS_IsARM, // STCL_OPTION = 1969 |
| 37690 | CEFBS_IsARM, // STCL_POST = 1970 |
| 37691 | CEFBS_IsARM, // STCL_PRE = 1971 |
| 37692 | CEFBS_IsARM, // STC_OFFSET = 1972 |
| 37693 | CEFBS_IsARM, // STC_OPTION = 1973 |
| 37694 | CEFBS_IsARM, // STC_POST = 1974 |
| 37695 | CEFBS_IsARM, // STC_PRE = 1975 |
| 37696 | CEFBS_IsARM_HasAcquireRelease, // STL = 1976 |
| 37697 | CEFBS_IsARM_HasAcquireRelease, // STLB = 1977 |
| 37698 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEX = 1978 |
| 37699 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXB = 1979 |
| 37700 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXD = 1980 |
| 37701 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXH = 1981 |
| 37702 | CEFBS_IsARM_HasAcquireRelease, // STLH = 1982 |
| 37703 | CEFBS_IsARM, // STMDA = 1983 |
| 37704 | CEFBS_IsARM, // STMDA_UPD = 1984 |
| 37705 | CEFBS_IsARM, // STMDB = 1985 |
| 37706 | CEFBS_IsARM, // STMDB_UPD = 1986 |
| 37707 | CEFBS_IsARM, // STMIA = 1987 |
| 37708 | CEFBS_IsARM, // STMIA_UPD = 1988 |
| 37709 | CEFBS_IsARM, // STMIB = 1989 |
| 37710 | CEFBS_IsARM, // STMIB_UPD = 1990 |
| 37711 | CEFBS_IsARM, // STRBT_POST_IMM = 1991 |
| 37712 | CEFBS_IsARM, // STRBT_POST_REG = 1992 |
| 37713 | CEFBS_IsARM, // STRB_POST_IMM = 1993 |
| 37714 | CEFBS_IsARM, // STRB_POST_REG = 1994 |
| 37715 | CEFBS_IsARM, // STRB_PRE_IMM = 1995 |
| 37716 | CEFBS_IsARM, // STRB_PRE_REG = 1996 |
| 37717 | CEFBS_IsARM, // STRBi12 = 1997 |
| 37718 | CEFBS_IsARM, // STRBrs = 1998 |
| 37719 | CEFBS_IsARM_HasV5TE, // STRD = 1999 |
| 37720 | CEFBS_IsARM, // STRD_POST = 2000 |
| 37721 | CEFBS_IsARM, // STRD_PRE = 2001 |
| 37722 | CEFBS_IsARM, // STREX = 2002 |
| 37723 | CEFBS_IsARM, // STREXB = 2003 |
| 37724 | CEFBS_IsARM, // STREXD = 2004 |
| 37725 | CEFBS_IsARM, // STREXH = 2005 |
| 37726 | CEFBS_IsARM, // STRH = 2006 |
| 37727 | CEFBS_IsARM, // STRHTi = 2007 |
| 37728 | CEFBS_IsARM, // STRHTr = 2008 |
| 37729 | CEFBS_IsARM, // STRH_POST = 2009 |
| 37730 | CEFBS_IsARM, // STRH_PRE = 2010 |
| 37731 | CEFBS_IsARM, // STRT_POST_IMM = 2011 |
| 37732 | CEFBS_IsARM, // STRT_POST_REG = 2012 |
| 37733 | CEFBS_IsARM, // STR_POST_IMM = 2013 |
| 37734 | CEFBS_IsARM, // STR_POST_REG = 2014 |
| 37735 | CEFBS_IsARM, // STR_PRE_IMM = 2015 |
| 37736 | CEFBS_IsARM, // STR_PRE_REG = 2016 |
| 37737 | CEFBS_IsARM, // STRi12 = 2017 |
| 37738 | CEFBS_IsARM, // STRrs = 2018 |
| 37739 | CEFBS_IsARM, // SUBri = 2019 |
| 37740 | CEFBS_IsARM, // SUBrr = 2020 |
| 37741 | CEFBS_IsARM, // SUBrsi = 2021 |
| 37742 | CEFBS_IsARM, // SUBrsr = 2022 |
| 37743 | CEFBS_IsARM, // SVC = 2023 |
| 37744 | CEFBS_IsARM_PreV8, // SWP = 2024 |
| 37745 | CEFBS_IsARM_PreV8, // SWPB = 2025 |
| 37746 | CEFBS_IsARM_HasV6, // SXTAB = 2026 |
| 37747 | CEFBS_IsARM_HasV6, // SXTAB16 = 2027 |
| 37748 | CEFBS_IsARM_HasV6, // SXTAH = 2028 |
| 37749 | CEFBS_IsARM_HasV6, // SXTB = 2029 |
| 37750 | CEFBS_IsARM_HasV6, // SXTB16 = 2030 |
| 37751 | CEFBS_IsARM_HasV6, // SXTH = 2031 |
| 37752 | CEFBS_IsARM, // TEQri = 2032 |
| 37753 | CEFBS_IsARM, // TEQrr = 2033 |
| 37754 | CEFBS_IsARM, // TEQrsi = 2034 |
| 37755 | CEFBS_IsARM, // TEQrsr = 2035 |
| 37756 | CEFBS_IsARM, // TRAP = 2036 |
| 37757 | CEFBS_IsARM_UseNaClTrap, // TRAPNaCl = 2037 |
| 37758 | CEFBS_IsARM_HasV8_4a, // TSB = 2038 |
| 37759 | CEFBS_IsARM, // TSTri = 2039 |
| 37760 | CEFBS_IsARM, // TSTrr = 2040 |
| 37761 | CEFBS_IsARM, // TSTrsi = 2041 |
| 37762 | CEFBS_IsARM, // TSTrsr = 2042 |
| 37763 | CEFBS_IsARM, // UADD16 = 2043 |
| 37764 | CEFBS_IsARM, // UADD8 = 2044 |
| 37765 | CEFBS_IsARM, // UASX = 2045 |
| 37766 | CEFBS_IsARM_HasV6T2, // UBFX = 2046 |
| 37767 | CEFBS_IsARM, // UDF = 2047 |
| 37768 | CEFBS_IsARM_HasDivideInARM, // UDIV = 2048 |
| 37769 | CEFBS_IsARM, // UHADD16 = 2049 |
| 37770 | CEFBS_IsARM, // UHADD8 = 2050 |
| 37771 | CEFBS_IsARM, // UHASX = 2051 |
| 37772 | CEFBS_IsARM, // UHSAX = 2052 |
| 37773 | CEFBS_IsARM, // UHSUB16 = 2053 |
| 37774 | CEFBS_IsARM, // UHSUB8 = 2054 |
| 37775 | CEFBS_IsARM_HasV6, // UMAAL = 2055 |
| 37776 | CEFBS_IsARM_HasV6, // UMLAL = 2056 |
| 37777 | CEFBS_IsARM_HasV6, // UMULL = 2057 |
| 37778 | CEFBS_IsARM, // UQADD16 = 2058 |
| 37779 | CEFBS_IsARM, // UQADD8 = 2059 |
| 37780 | CEFBS_IsARM, // UQASX = 2060 |
| 37781 | CEFBS_IsARM, // UQSAX = 2061 |
| 37782 | CEFBS_IsARM, // UQSUB16 = 2062 |
| 37783 | CEFBS_IsARM, // UQSUB8 = 2063 |
| 37784 | CEFBS_IsARM_HasV6, // USAD8 = 2064 |
| 37785 | CEFBS_IsARM_HasV6, // USADA8 = 2065 |
| 37786 | CEFBS_IsARM_HasV6, // USAT = 2066 |
| 37787 | CEFBS_IsARM_HasV6, // USAT16 = 2067 |
| 37788 | CEFBS_IsARM, // USAX = 2068 |
| 37789 | CEFBS_IsARM, // USUB16 = 2069 |
| 37790 | CEFBS_IsARM, // USUB8 = 2070 |
| 37791 | CEFBS_IsARM_HasV6, // UXTAB = 2071 |
| 37792 | CEFBS_IsARM_HasV6, // UXTAB16 = 2072 |
| 37793 | CEFBS_IsARM_HasV6, // UXTAH = 2073 |
| 37794 | CEFBS_IsARM_HasV6, // UXTB = 2074 |
| 37795 | CEFBS_IsARM_HasV6, // UXTB16 = 2075 |
| 37796 | CEFBS_IsARM_HasV6, // UXTH = 2076 |
| 37797 | CEFBS_HasNEON, // VABALsv2i64 = 2077 |
| 37798 | CEFBS_HasNEON, // VABALsv4i32 = 2078 |
| 37799 | CEFBS_HasNEON, // VABALsv8i16 = 2079 |
| 37800 | CEFBS_HasNEON, // VABALuv2i64 = 2080 |
| 37801 | CEFBS_HasNEON, // VABALuv4i32 = 2081 |
| 37802 | CEFBS_HasNEON, // VABALuv8i16 = 2082 |
| 37803 | CEFBS_HasNEON, // VABAsv16i8 = 2083 |
| 37804 | CEFBS_HasNEON, // VABAsv2i32 = 2084 |
| 37805 | CEFBS_HasNEON, // VABAsv4i16 = 2085 |
| 37806 | CEFBS_HasNEON, // VABAsv4i32 = 2086 |
| 37807 | CEFBS_HasNEON, // VABAsv8i16 = 2087 |
| 37808 | CEFBS_HasNEON, // VABAsv8i8 = 2088 |
| 37809 | CEFBS_HasNEON, // VABAuv16i8 = 2089 |
| 37810 | CEFBS_HasNEON, // VABAuv2i32 = 2090 |
| 37811 | CEFBS_HasNEON, // VABAuv4i16 = 2091 |
| 37812 | CEFBS_HasNEON, // VABAuv4i32 = 2092 |
| 37813 | CEFBS_HasNEON, // VABAuv8i16 = 2093 |
| 37814 | CEFBS_HasNEON, // VABAuv8i8 = 2094 |
| 37815 | CEFBS_HasNEON, // VABDLsv2i64 = 2095 |
| 37816 | CEFBS_HasNEON, // VABDLsv4i32 = 2096 |
| 37817 | CEFBS_HasNEON, // VABDLsv8i16 = 2097 |
| 37818 | CEFBS_HasNEON, // VABDLuv2i64 = 2098 |
| 37819 | CEFBS_HasNEON, // VABDLuv4i32 = 2099 |
| 37820 | CEFBS_HasNEON, // VABDLuv8i16 = 2100 |
| 37821 | CEFBS_HasNEON, // VABDfd = 2101 |
| 37822 | CEFBS_HasNEON, // VABDfq = 2102 |
| 37823 | CEFBS_HasNEON_HasFullFP16, // VABDhd = 2103 |
| 37824 | CEFBS_HasNEON_HasFullFP16, // VABDhq = 2104 |
| 37825 | CEFBS_HasNEON, // VABDsv16i8 = 2105 |
| 37826 | CEFBS_HasNEON, // VABDsv2i32 = 2106 |
| 37827 | CEFBS_HasNEON, // VABDsv4i16 = 2107 |
| 37828 | CEFBS_HasNEON, // VABDsv4i32 = 2108 |
| 37829 | CEFBS_HasNEON, // VABDsv8i16 = 2109 |
| 37830 | CEFBS_HasNEON, // VABDsv8i8 = 2110 |
| 37831 | CEFBS_HasNEON, // VABDuv16i8 = 2111 |
| 37832 | CEFBS_HasNEON, // VABDuv2i32 = 2112 |
| 37833 | CEFBS_HasNEON, // VABDuv4i16 = 2113 |
| 37834 | CEFBS_HasNEON, // VABDuv4i32 = 2114 |
| 37835 | CEFBS_HasNEON, // VABDuv8i16 = 2115 |
| 37836 | CEFBS_HasNEON, // VABDuv8i8 = 2116 |
| 37837 | CEFBS_HasVFP2_HasDPVFP, // VABSD = 2117 |
| 37838 | CEFBS_HasFullFP16, // VABSH = 2118 |
| 37839 | CEFBS_HasVFP2, // VABSS = 2119 |
| 37840 | CEFBS_HasNEON, // VABSfd = 2120 |
| 37841 | CEFBS_HasNEON, // VABSfq = 2121 |
| 37842 | CEFBS_HasNEON_HasFullFP16, // VABShd = 2122 |
| 37843 | CEFBS_HasNEON_HasFullFP16, // VABShq = 2123 |
| 37844 | CEFBS_HasNEON, // VABSv16i8 = 2124 |
| 37845 | CEFBS_HasNEON, // VABSv2i32 = 2125 |
| 37846 | CEFBS_HasNEON, // VABSv4i16 = 2126 |
| 37847 | CEFBS_HasNEON, // VABSv4i32 = 2127 |
| 37848 | CEFBS_HasNEON, // VABSv8i16 = 2128 |
| 37849 | CEFBS_HasNEON, // VABSv8i8 = 2129 |
| 37850 | CEFBS_HasNEON, // VACGEfd = 2130 |
| 37851 | CEFBS_HasNEON, // VACGEfq = 2131 |
| 37852 | CEFBS_HasNEON_HasFullFP16, // VACGEhd = 2132 |
| 37853 | CEFBS_HasNEON_HasFullFP16, // VACGEhq = 2133 |
| 37854 | CEFBS_HasNEON, // VACGTfd = 2134 |
| 37855 | CEFBS_HasNEON, // VACGTfq = 2135 |
| 37856 | CEFBS_HasNEON_HasFullFP16, // VACGThd = 2136 |
| 37857 | CEFBS_HasNEON_HasFullFP16, // VACGThq = 2137 |
| 37858 | CEFBS_HasVFP2_HasDPVFP, // VADDD = 2138 |
| 37859 | CEFBS_HasFullFP16, // VADDH = 2139 |
| 37860 | CEFBS_HasNEON, // VADDHNv2i32 = 2140 |
| 37861 | CEFBS_HasNEON, // VADDHNv4i16 = 2141 |
| 37862 | CEFBS_HasNEON, // VADDHNv8i8 = 2142 |
| 37863 | CEFBS_HasNEON, // VADDLsv2i64 = 2143 |
| 37864 | CEFBS_HasNEON, // VADDLsv4i32 = 2144 |
| 37865 | CEFBS_HasNEON, // VADDLsv8i16 = 2145 |
| 37866 | CEFBS_HasNEON, // VADDLuv2i64 = 2146 |
| 37867 | CEFBS_HasNEON, // VADDLuv4i32 = 2147 |
| 37868 | CEFBS_HasNEON, // VADDLuv8i16 = 2148 |
| 37869 | CEFBS_HasVFP2, // VADDS = 2149 |
| 37870 | CEFBS_HasNEON, // VADDWsv2i64 = 2150 |
| 37871 | CEFBS_HasNEON, // VADDWsv4i32 = 2151 |
| 37872 | CEFBS_HasNEON, // VADDWsv8i16 = 2152 |
| 37873 | CEFBS_HasNEON, // VADDWuv2i64 = 2153 |
| 37874 | CEFBS_HasNEON, // VADDWuv4i32 = 2154 |
| 37875 | CEFBS_HasNEON, // VADDWuv8i16 = 2155 |
| 37876 | CEFBS_HasNEON, // VADDfd = 2156 |
| 37877 | CEFBS_HasNEON, // VADDfq = 2157 |
| 37878 | CEFBS_HasNEON_HasFullFP16, // VADDhd = 2158 |
| 37879 | CEFBS_HasNEON_HasFullFP16, // VADDhq = 2159 |
| 37880 | CEFBS_HasNEON, // VADDv16i8 = 2160 |
| 37881 | CEFBS_HasNEON, // VADDv1i64 = 2161 |
| 37882 | CEFBS_HasNEON, // VADDv2i32 = 2162 |
| 37883 | CEFBS_HasNEON, // VADDv2i64 = 2163 |
| 37884 | CEFBS_HasNEON, // VADDv4i16 = 2164 |
| 37885 | CEFBS_HasNEON, // VADDv4i32 = 2165 |
| 37886 | CEFBS_HasNEON, // VADDv8i16 = 2166 |
| 37887 | CEFBS_HasNEON, // VADDv8i8 = 2167 |
| 37888 | CEFBS_HasNEON, // VANDd = 2168 |
| 37889 | CEFBS_HasNEON, // VANDq = 2169 |
| 37890 | CEFBS_HasBF16_HasNEON, // VBF16MALBQ = 2170 |
| 37891 | CEFBS_HasBF16_HasNEON, // VBF16MALBQI = 2171 |
| 37892 | CEFBS_HasBF16_HasNEON, // VBF16MALTQ = 2172 |
| 37893 | CEFBS_HasBF16_HasNEON, // VBF16MALTQI = 2173 |
| 37894 | CEFBS_HasNEON, // VBICd = 2174 |
| 37895 | CEFBS_HasNEON, // VBICiv2i32 = 2175 |
| 37896 | CEFBS_HasNEON, // VBICiv4i16 = 2176 |
| 37897 | CEFBS_HasNEON, // VBICiv4i32 = 2177 |
| 37898 | CEFBS_HasNEON, // VBICiv8i16 = 2178 |
| 37899 | CEFBS_HasNEON, // VBICq = 2179 |
| 37900 | CEFBS_HasNEON, // VBIFd = 2180 |
| 37901 | CEFBS_HasNEON, // VBIFq = 2181 |
| 37902 | CEFBS_HasNEON, // VBITd = 2182 |
| 37903 | CEFBS_HasNEON, // VBITq = 2183 |
| 37904 | CEFBS_HasNEON, // VBSLd = 2184 |
| 37905 | CEFBS_HasNEON, // VBSLq = 2185 |
| 37906 | CEFBS_HasNEON, // VBSPd = 2186 |
| 37907 | CEFBS_HasNEON, // VBSPq = 2187 |
| 37908 | CEFBS_HasNEON_HasV8_3a, // VCADDv2f32 = 2188 |
| 37909 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCADDv4f16 = 2189 |
| 37910 | CEFBS_HasNEON_HasV8_3a, // VCADDv4f32 = 2190 |
| 37911 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCADDv8f16 = 2191 |
| 37912 | CEFBS_HasNEON, // VCEQfd = 2192 |
| 37913 | CEFBS_HasNEON, // VCEQfq = 2193 |
| 37914 | CEFBS_HasNEON_HasFullFP16, // VCEQhd = 2194 |
| 37915 | CEFBS_HasNEON_HasFullFP16, // VCEQhq = 2195 |
| 37916 | CEFBS_HasNEON, // VCEQv16i8 = 2196 |
| 37917 | CEFBS_HasNEON, // VCEQv2i32 = 2197 |
| 37918 | CEFBS_HasNEON, // VCEQv4i16 = 2198 |
| 37919 | CEFBS_HasNEON, // VCEQv4i32 = 2199 |
| 37920 | CEFBS_HasNEON, // VCEQv8i16 = 2200 |
| 37921 | CEFBS_HasNEON, // VCEQv8i8 = 2201 |
| 37922 | CEFBS_HasNEON, // VCEQzv16i8 = 2202 |
| 37923 | CEFBS_HasNEON, // VCEQzv2f32 = 2203 |
| 37924 | CEFBS_HasNEON, // VCEQzv2i32 = 2204 |
| 37925 | CEFBS_HasNEON_HasFullFP16, // VCEQzv4f16 = 2205 |
| 37926 | CEFBS_HasNEON, // VCEQzv4f32 = 2206 |
| 37927 | CEFBS_HasNEON, // VCEQzv4i16 = 2207 |
| 37928 | CEFBS_HasNEON, // VCEQzv4i32 = 2208 |
| 37929 | CEFBS_HasNEON_HasFullFP16, // VCEQzv8f16 = 2209 |
| 37930 | CEFBS_HasNEON, // VCEQzv8i16 = 2210 |
| 37931 | CEFBS_HasNEON, // VCEQzv8i8 = 2211 |
| 37932 | CEFBS_HasNEON, // VCGEfd = 2212 |
| 37933 | CEFBS_HasNEON, // VCGEfq = 2213 |
| 37934 | CEFBS_HasNEON_HasFullFP16, // VCGEhd = 2214 |
| 37935 | CEFBS_HasNEON_HasFullFP16, // VCGEhq = 2215 |
| 37936 | CEFBS_HasNEON, // VCGEsv16i8 = 2216 |
| 37937 | CEFBS_HasNEON, // VCGEsv2i32 = 2217 |
| 37938 | CEFBS_HasNEON, // VCGEsv4i16 = 2218 |
| 37939 | CEFBS_HasNEON, // VCGEsv4i32 = 2219 |
| 37940 | CEFBS_HasNEON, // VCGEsv8i16 = 2220 |
| 37941 | CEFBS_HasNEON, // VCGEsv8i8 = 2221 |
| 37942 | CEFBS_HasNEON, // VCGEuv16i8 = 2222 |
| 37943 | CEFBS_HasNEON, // VCGEuv2i32 = 2223 |
| 37944 | CEFBS_HasNEON, // VCGEuv4i16 = 2224 |
| 37945 | CEFBS_HasNEON, // VCGEuv4i32 = 2225 |
| 37946 | CEFBS_HasNEON, // VCGEuv8i16 = 2226 |
| 37947 | CEFBS_HasNEON, // VCGEuv8i8 = 2227 |
| 37948 | CEFBS_HasNEON, // VCGEzv16i8 = 2228 |
| 37949 | CEFBS_HasNEON, // VCGEzv2f32 = 2229 |
| 37950 | CEFBS_HasNEON, // VCGEzv2i32 = 2230 |
| 37951 | CEFBS_HasNEON_HasFullFP16, // VCGEzv4f16 = 2231 |
| 37952 | CEFBS_HasNEON, // VCGEzv4f32 = 2232 |
| 37953 | CEFBS_HasNEON, // VCGEzv4i16 = 2233 |
| 37954 | CEFBS_HasNEON, // VCGEzv4i32 = 2234 |
| 37955 | CEFBS_HasNEON_HasFullFP16, // VCGEzv8f16 = 2235 |
| 37956 | CEFBS_HasNEON, // VCGEzv8i16 = 2236 |
| 37957 | CEFBS_HasNEON, // VCGEzv8i8 = 2237 |
| 37958 | CEFBS_HasNEON, // VCGTfd = 2238 |
| 37959 | CEFBS_HasNEON, // VCGTfq = 2239 |
| 37960 | CEFBS_HasNEON_HasFullFP16, // VCGThd = 2240 |
| 37961 | CEFBS_HasNEON_HasFullFP16, // VCGThq = 2241 |
| 37962 | CEFBS_HasNEON, // VCGTsv16i8 = 2242 |
| 37963 | CEFBS_HasNEON, // VCGTsv2i32 = 2243 |
| 37964 | CEFBS_HasNEON, // VCGTsv4i16 = 2244 |
| 37965 | CEFBS_HasNEON, // VCGTsv4i32 = 2245 |
| 37966 | CEFBS_HasNEON, // VCGTsv8i16 = 2246 |
| 37967 | CEFBS_HasNEON, // VCGTsv8i8 = 2247 |
| 37968 | CEFBS_HasNEON, // VCGTuv16i8 = 2248 |
| 37969 | CEFBS_HasNEON, // VCGTuv2i32 = 2249 |
| 37970 | CEFBS_HasNEON, // VCGTuv4i16 = 2250 |
| 37971 | CEFBS_HasNEON, // VCGTuv4i32 = 2251 |
| 37972 | CEFBS_HasNEON, // VCGTuv8i16 = 2252 |
| 37973 | CEFBS_HasNEON, // VCGTuv8i8 = 2253 |
| 37974 | CEFBS_HasNEON, // VCGTzv16i8 = 2254 |
| 37975 | CEFBS_HasNEON, // VCGTzv2f32 = 2255 |
| 37976 | CEFBS_HasNEON, // VCGTzv2i32 = 2256 |
| 37977 | CEFBS_HasNEON_HasFullFP16, // VCGTzv4f16 = 2257 |
| 37978 | CEFBS_HasNEON, // VCGTzv4f32 = 2258 |
| 37979 | CEFBS_HasNEON, // VCGTzv4i16 = 2259 |
| 37980 | CEFBS_HasNEON, // VCGTzv4i32 = 2260 |
| 37981 | CEFBS_HasNEON_HasFullFP16, // VCGTzv8f16 = 2261 |
| 37982 | CEFBS_HasNEON, // VCGTzv8i16 = 2262 |
| 37983 | CEFBS_HasNEON, // VCGTzv8i8 = 2263 |
| 37984 | CEFBS_HasNEON, // VCLEzv16i8 = 2264 |
| 37985 | CEFBS_HasNEON, // VCLEzv2f32 = 2265 |
| 37986 | CEFBS_HasNEON, // VCLEzv2i32 = 2266 |
| 37987 | CEFBS_HasNEON_HasFullFP16, // VCLEzv4f16 = 2267 |
| 37988 | CEFBS_HasNEON, // VCLEzv4f32 = 2268 |
| 37989 | CEFBS_HasNEON, // VCLEzv4i16 = 2269 |
| 37990 | CEFBS_HasNEON, // VCLEzv4i32 = 2270 |
| 37991 | CEFBS_HasNEON_HasFullFP16, // VCLEzv8f16 = 2271 |
| 37992 | CEFBS_HasNEON, // VCLEzv8i16 = 2272 |
| 37993 | CEFBS_HasNEON, // VCLEzv8i8 = 2273 |
| 37994 | CEFBS_HasNEON, // VCLSv16i8 = 2274 |
| 37995 | CEFBS_HasNEON, // VCLSv2i32 = 2275 |
| 37996 | CEFBS_HasNEON, // VCLSv4i16 = 2276 |
| 37997 | CEFBS_HasNEON, // VCLSv4i32 = 2277 |
| 37998 | CEFBS_HasNEON, // VCLSv8i16 = 2278 |
| 37999 | CEFBS_HasNEON, // VCLSv8i8 = 2279 |
| 38000 | CEFBS_HasNEON, // VCLTzv16i8 = 2280 |
| 38001 | CEFBS_HasNEON, // VCLTzv2f32 = 2281 |
| 38002 | CEFBS_HasNEON, // VCLTzv2i32 = 2282 |
| 38003 | CEFBS_HasNEON_HasFullFP16, // VCLTzv4f16 = 2283 |
| 38004 | CEFBS_HasNEON, // VCLTzv4f32 = 2284 |
| 38005 | CEFBS_HasNEON, // VCLTzv4i16 = 2285 |
| 38006 | CEFBS_HasNEON, // VCLTzv4i32 = 2286 |
| 38007 | CEFBS_HasNEON_HasFullFP16, // VCLTzv8f16 = 2287 |
| 38008 | CEFBS_HasNEON, // VCLTzv8i16 = 2288 |
| 38009 | CEFBS_HasNEON, // VCLTzv8i8 = 2289 |
| 38010 | CEFBS_HasNEON, // VCLZv16i8 = 2290 |
| 38011 | CEFBS_HasNEON, // VCLZv2i32 = 2291 |
| 38012 | CEFBS_HasNEON, // VCLZv4i16 = 2292 |
| 38013 | CEFBS_HasNEON, // VCLZv4i32 = 2293 |
| 38014 | CEFBS_HasNEON, // VCLZv8i16 = 2294 |
| 38015 | CEFBS_HasNEON, // VCLZv8i8 = 2295 |
| 38016 | CEFBS_HasNEON_HasV8_3a, // VCMLAv2f32 = 2296 |
| 38017 | CEFBS_HasNEON_HasV8_3a, // VCMLAv2f32_indexed = 2297 |
| 38018 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv4f16 = 2298 |
| 38019 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv4f16_indexed = 2299 |
| 38020 | CEFBS_HasNEON_HasV8_3a, // VCMLAv4f32 = 2300 |
| 38021 | CEFBS_HasNEON_HasV8_3a, // VCMLAv4f32_indexed = 2301 |
| 38022 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv8f16 = 2302 |
| 38023 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv8f16_indexed = 2303 |
| 38024 | CEFBS_HasVFP2_HasDPVFP, // VCMPD = 2304 |
| 38025 | CEFBS_HasVFP2_HasDPVFP, // VCMPED = 2305 |
| 38026 | CEFBS_HasFullFP16, // VCMPEH = 2306 |
| 38027 | CEFBS_HasVFP2, // VCMPES = 2307 |
| 38028 | CEFBS_HasVFP2_HasDPVFP, // VCMPEZD = 2308 |
| 38029 | CEFBS_HasFullFP16, // VCMPEZH = 2309 |
| 38030 | CEFBS_HasVFP2, // VCMPEZS = 2310 |
| 38031 | CEFBS_HasFullFP16, // VCMPH = 2311 |
| 38032 | CEFBS_HasVFP2, // VCMPS = 2312 |
| 38033 | CEFBS_HasVFP2_HasDPVFP, // VCMPZD = 2313 |
| 38034 | CEFBS_HasFullFP16, // VCMPZH = 2314 |
| 38035 | CEFBS_HasVFP2, // VCMPZS = 2315 |
| 38036 | CEFBS_HasNEON, // VCNTd = 2316 |
| 38037 | CEFBS_HasNEON, // VCNTq = 2317 |
| 38038 | CEFBS_HasV8_HasNEON, // VCVTANSDf = 2318 |
| 38039 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANSDh = 2319 |
| 38040 | CEFBS_HasV8_HasNEON, // VCVTANSQf = 2320 |
| 38041 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANSQh = 2321 |
| 38042 | CEFBS_HasV8_HasNEON, // VCVTANUDf = 2322 |
| 38043 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANUDh = 2323 |
| 38044 | CEFBS_HasV8_HasNEON, // VCVTANUQf = 2324 |
| 38045 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANUQh = 2325 |
| 38046 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTASD = 2326 |
| 38047 | CEFBS_HasFullFP16, // VCVTASH = 2327 |
| 38048 | CEFBS_HasFPARMv8, // VCVTASS = 2328 |
| 38049 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTAUD = 2329 |
| 38050 | CEFBS_HasFullFP16, // VCVTAUH = 2330 |
| 38051 | CEFBS_HasFPARMv8, // VCVTAUS = 2331 |
| 38052 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTBDH = 2332 |
| 38053 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTBHD = 2333 |
| 38054 | CEFBS_HasFP16, // VCVTBHS = 2334 |
| 38055 | CEFBS_HasFP16, // VCVTBSH = 2335 |
| 38056 | CEFBS_HasVFP2_HasDPVFP, // VCVTDS = 2336 |
| 38057 | CEFBS_HasV8_HasNEON, // VCVTMNSDf = 2337 |
| 38058 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNSDh = 2338 |
| 38059 | CEFBS_HasV8_HasNEON, // VCVTMNSQf = 2339 |
| 38060 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNSQh = 2340 |
| 38061 | CEFBS_HasV8_HasNEON, // VCVTMNUDf = 2341 |
| 38062 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNUDh = 2342 |
| 38063 | CEFBS_HasV8_HasNEON, // VCVTMNUQf = 2343 |
| 38064 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNUQh = 2344 |
| 38065 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTMSD = 2345 |
| 38066 | CEFBS_HasFullFP16, // VCVTMSH = 2346 |
| 38067 | CEFBS_HasFPARMv8, // VCVTMSS = 2347 |
| 38068 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTMUD = 2348 |
| 38069 | CEFBS_HasFullFP16, // VCVTMUH = 2349 |
| 38070 | CEFBS_HasFPARMv8, // VCVTMUS = 2350 |
| 38071 | CEFBS_HasV8_HasNEON, // VCVTNNSDf = 2351 |
| 38072 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNSDh = 2352 |
| 38073 | CEFBS_HasV8_HasNEON, // VCVTNNSQf = 2353 |
| 38074 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNSQh = 2354 |
| 38075 | CEFBS_HasV8_HasNEON, // VCVTNNUDf = 2355 |
| 38076 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNUDh = 2356 |
| 38077 | CEFBS_HasV8_HasNEON, // VCVTNNUQf = 2357 |
| 38078 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNUQh = 2358 |
| 38079 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTNSD = 2359 |
| 38080 | CEFBS_HasFullFP16, // VCVTNSH = 2360 |
| 38081 | CEFBS_HasFPARMv8, // VCVTNSS = 2361 |
| 38082 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTNUD = 2362 |
| 38083 | CEFBS_HasFullFP16, // VCVTNUH = 2363 |
| 38084 | CEFBS_HasFPARMv8, // VCVTNUS = 2364 |
| 38085 | CEFBS_HasV8_HasNEON, // VCVTPNSDf = 2365 |
| 38086 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNSDh = 2366 |
| 38087 | CEFBS_HasV8_HasNEON, // VCVTPNSQf = 2367 |
| 38088 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNSQh = 2368 |
| 38089 | CEFBS_HasV8_HasNEON, // VCVTPNUDf = 2369 |
| 38090 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNUDh = 2370 |
| 38091 | CEFBS_HasV8_HasNEON, // VCVTPNUQf = 2371 |
| 38092 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNUQh = 2372 |
| 38093 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTPSD = 2373 |
| 38094 | CEFBS_HasFullFP16, // VCVTPSH = 2374 |
| 38095 | CEFBS_HasFPARMv8, // VCVTPSS = 2375 |
| 38096 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTPUD = 2376 |
| 38097 | CEFBS_HasFullFP16, // VCVTPUH = 2377 |
| 38098 | CEFBS_HasFPARMv8, // VCVTPUS = 2378 |
| 38099 | CEFBS_HasVFP2_HasDPVFP, // VCVTSD = 2379 |
| 38100 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTTDH = 2380 |
| 38101 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTTHD = 2381 |
| 38102 | CEFBS_HasFP16, // VCVTTHS = 2382 |
| 38103 | CEFBS_HasFP16, // VCVTTSH = 2383 |
| 38104 | CEFBS_HasNEON_HasFP16, // VCVTf2h = 2384 |
| 38105 | CEFBS_HasNEON, // VCVTf2sd = 2385 |
| 38106 | CEFBS_HasNEON, // VCVTf2sq = 2386 |
| 38107 | CEFBS_HasNEON, // VCVTf2ud = 2387 |
| 38108 | CEFBS_HasNEON, // VCVTf2uq = 2388 |
| 38109 | CEFBS_HasNEON, // VCVTf2xsd = 2389 |
| 38110 | CEFBS_HasNEON, // VCVTf2xsq = 2390 |
| 38111 | CEFBS_HasNEON, // VCVTf2xud = 2391 |
| 38112 | CEFBS_HasNEON, // VCVTf2xuq = 2392 |
| 38113 | CEFBS_HasNEON_HasFP16, // VCVTh2f = 2393 |
| 38114 | CEFBS_HasNEON_HasFullFP16, // VCVTh2sd = 2394 |
| 38115 | CEFBS_HasNEON_HasFullFP16, // VCVTh2sq = 2395 |
| 38116 | CEFBS_HasNEON_HasFullFP16, // VCVTh2ud = 2396 |
| 38117 | CEFBS_HasNEON_HasFullFP16, // VCVTh2uq = 2397 |
| 38118 | CEFBS_HasNEON_HasFullFP16, // VCVTh2xsd = 2398 |
| 38119 | CEFBS_HasNEON_HasFullFP16, // VCVTh2xsq = 2399 |
| 38120 | CEFBS_HasNEON_HasFullFP16, // VCVTh2xud = 2400 |
| 38121 | CEFBS_HasNEON_HasFullFP16, // VCVTh2xuq = 2401 |
| 38122 | CEFBS_HasNEON, // VCVTs2fd = 2402 |
| 38123 | CEFBS_HasNEON, // VCVTs2fq = 2403 |
| 38124 | CEFBS_HasNEON_HasFullFP16, // VCVTs2hd = 2404 |
| 38125 | CEFBS_HasNEON_HasFullFP16, // VCVTs2hq = 2405 |
| 38126 | CEFBS_HasNEON, // VCVTu2fd = 2406 |
| 38127 | CEFBS_HasNEON, // VCVTu2fq = 2407 |
| 38128 | CEFBS_HasNEON_HasFullFP16, // VCVTu2hd = 2408 |
| 38129 | CEFBS_HasNEON_HasFullFP16, // VCVTu2hq = 2409 |
| 38130 | CEFBS_HasNEON, // VCVTxs2fd = 2410 |
| 38131 | CEFBS_HasNEON, // VCVTxs2fq = 2411 |
| 38132 | CEFBS_HasNEON_HasFullFP16, // VCVTxs2hd = 2412 |
| 38133 | CEFBS_HasNEON_HasFullFP16, // VCVTxs2hq = 2413 |
| 38134 | CEFBS_HasNEON, // VCVTxu2fd = 2414 |
| 38135 | CEFBS_HasNEON, // VCVTxu2fq = 2415 |
| 38136 | CEFBS_HasNEON_HasFullFP16, // VCVTxu2hd = 2416 |
| 38137 | CEFBS_HasNEON_HasFullFP16, // VCVTxu2hq = 2417 |
| 38138 | CEFBS_HasVFP2_HasDPVFP, // VDIVD = 2418 |
| 38139 | CEFBS_HasFullFP16, // VDIVH = 2419 |
| 38140 | CEFBS_HasVFP2, // VDIVS = 2420 |
| 38141 | CEFBS_HasNEON, // VDUP16d = 2421 |
| 38142 | CEFBS_HasNEON, // VDUP16q = 2422 |
| 38143 | CEFBS_HasNEON, // VDUP32d = 2423 |
| 38144 | CEFBS_HasNEON, // VDUP32q = 2424 |
| 38145 | CEFBS_HasNEON, // VDUP8d = 2425 |
| 38146 | CEFBS_HasNEON, // VDUP8q = 2426 |
| 38147 | CEFBS_HasNEON, // VDUPLN16d = 2427 |
| 38148 | CEFBS_HasNEON, // VDUPLN16q = 2428 |
| 38149 | CEFBS_HasNEON, // VDUPLN32d = 2429 |
| 38150 | CEFBS_HasNEON, // VDUPLN32q = 2430 |
| 38151 | CEFBS_HasNEON, // VDUPLN8d = 2431 |
| 38152 | CEFBS_HasNEON, // VDUPLN8q = 2432 |
| 38153 | CEFBS_HasNEON, // VEORd = 2433 |
| 38154 | CEFBS_HasNEON, // VEORq = 2434 |
| 38155 | CEFBS_HasNEON, // VEXTd16 = 2435 |
| 38156 | CEFBS_HasNEON, // VEXTd32 = 2436 |
| 38157 | CEFBS_HasNEON, // VEXTd8 = 2437 |
| 38158 | CEFBS_HasNEON, // VEXTq16 = 2438 |
| 38159 | CEFBS_HasNEON, // VEXTq32 = 2439 |
| 38160 | CEFBS_HasNEON, // VEXTq64 = 2440 |
| 38161 | CEFBS_HasNEON, // VEXTq8 = 2441 |
| 38162 | CEFBS_HasVFP4_HasDPVFP, // VFMAD = 2442 |
| 38163 | CEFBS_HasFullFP16, // VFMAH = 2443 |
| 38164 | CEFBS_HasNEON_HasFP16FML, // VFMALD = 2444 |
| 38165 | CEFBS_HasNEON_HasFP16FML, // VFMALDI = 2445 |
| 38166 | CEFBS_HasNEON_HasFP16FML, // VFMALQ = 2446 |
| 38167 | CEFBS_HasNEON_HasFP16FML, // VFMALQI = 2447 |
| 38168 | CEFBS_HasVFP4, // VFMAS = 2448 |
| 38169 | CEFBS_HasNEON_HasVFP4, // VFMAfd = 2449 |
| 38170 | CEFBS_HasNEON_HasVFP4, // VFMAfq = 2450 |
| 38171 | CEFBS_HasNEON_HasFullFP16, // VFMAhd = 2451 |
| 38172 | CEFBS_HasNEON_HasFullFP16, // VFMAhq = 2452 |
| 38173 | CEFBS_HasVFP4_HasDPVFP, // VFMSD = 2453 |
| 38174 | CEFBS_HasFullFP16, // VFMSH = 2454 |
| 38175 | CEFBS_HasNEON_HasFP16FML, // VFMSLD = 2455 |
| 38176 | CEFBS_HasNEON_HasFP16FML, // VFMSLDI = 2456 |
| 38177 | CEFBS_HasNEON_HasFP16FML, // VFMSLQ = 2457 |
| 38178 | CEFBS_HasNEON_HasFP16FML, // VFMSLQI = 2458 |
| 38179 | CEFBS_HasVFP4, // VFMSS = 2459 |
| 38180 | CEFBS_HasNEON_HasVFP4, // VFMSfd = 2460 |
| 38181 | CEFBS_HasNEON_HasVFP4, // VFMSfq = 2461 |
| 38182 | CEFBS_HasNEON_HasFullFP16, // VFMShd = 2462 |
| 38183 | CEFBS_HasNEON_HasFullFP16, // VFMShq = 2463 |
| 38184 | CEFBS_HasVFP4_HasDPVFP, // VFNMAD = 2464 |
| 38185 | CEFBS_HasFullFP16, // VFNMAH = 2465 |
| 38186 | CEFBS_HasVFP4, // VFNMAS = 2466 |
| 38187 | CEFBS_HasVFP4_HasDPVFP, // VFNMSD = 2467 |
| 38188 | CEFBS_HasFullFP16, // VFNMSH = 2468 |
| 38189 | CEFBS_HasVFP4, // VFNMSS = 2469 |
| 38190 | CEFBS_HasFPARMv8_HasDPVFP, // VFP_VMAXNMD = 2470 |
| 38191 | CEFBS_HasFullFP16, // VFP_VMAXNMH = 2471 |
| 38192 | CEFBS_HasFPARMv8, // VFP_VMAXNMS = 2472 |
| 38193 | CEFBS_HasFPARMv8_HasDPVFP, // VFP_VMINNMD = 2473 |
| 38194 | CEFBS_HasFullFP16, // VFP_VMINNMH = 2474 |
| 38195 | CEFBS_HasFPARMv8, // VFP_VMINNMS = 2475 |
| 38196 | CEFBS_HasFPRegs, // VGETLNi32 = 2476 |
| 38197 | CEFBS_HasNEON, // VGETLNs16 = 2477 |
| 38198 | CEFBS_HasNEON, // VGETLNs8 = 2478 |
| 38199 | CEFBS_HasNEON, // VGETLNu16 = 2479 |
| 38200 | CEFBS_HasNEON, // VGETLNu8 = 2480 |
| 38201 | CEFBS_HasNEON, // VHADDsv16i8 = 2481 |
| 38202 | CEFBS_HasNEON, // VHADDsv2i32 = 2482 |
| 38203 | CEFBS_HasNEON, // VHADDsv4i16 = 2483 |
| 38204 | CEFBS_HasNEON, // VHADDsv4i32 = 2484 |
| 38205 | CEFBS_HasNEON, // VHADDsv8i16 = 2485 |
| 38206 | CEFBS_HasNEON, // VHADDsv8i8 = 2486 |
| 38207 | CEFBS_HasNEON, // VHADDuv16i8 = 2487 |
| 38208 | CEFBS_HasNEON, // VHADDuv2i32 = 2488 |
| 38209 | CEFBS_HasNEON, // VHADDuv4i16 = 2489 |
| 38210 | CEFBS_HasNEON, // VHADDuv4i32 = 2490 |
| 38211 | CEFBS_HasNEON, // VHADDuv8i16 = 2491 |
| 38212 | CEFBS_HasNEON, // VHADDuv8i8 = 2492 |
| 38213 | CEFBS_HasNEON, // VHSUBsv16i8 = 2493 |
| 38214 | CEFBS_HasNEON, // VHSUBsv2i32 = 2494 |
| 38215 | CEFBS_HasNEON, // VHSUBsv4i16 = 2495 |
| 38216 | CEFBS_HasNEON, // VHSUBsv4i32 = 2496 |
| 38217 | CEFBS_HasNEON, // VHSUBsv8i16 = 2497 |
| 38218 | CEFBS_HasNEON, // VHSUBsv8i8 = 2498 |
| 38219 | CEFBS_HasNEON, // VHSUBuv16i8 = 2499 |
| 38220 | CEFBS_HasNEON, // VHSUBuv2i32 = 2500 |
| 38221 | CEFBS_HasNEON, // VHSUBuv4i16 = 2501 |
| 38222 | CEFBS_HasNEON, // VHSUBuv4i32 = 2502 |
| 38223 | CEFBS_HasNEON, // VHSUBuv8i16 = 2503 |
| 38224 | CEFBS_HasNEON, // VHSUBuv8i8 = 2504 |
| 38225 | CEFBS_HasFullFP16, // VINSH = 2505 |
| 38226 | CEFBS_HasFPARMv8_HasV8_3a, // VJCVT = 2506 |
| 38227 | CEFBS_HasNEON, // VLD1DUPd16 = 2507 |
| 38228 | CEFBS_HasNEON, // VLD1DUPd16wb_fixed = 2508 |
| 38229 | CEFBS_HasNEON, // VLD1DUPd16wb_register = 2509 |
| 38230 | CEFBS_HasNEON, // VLD1DUPd32 = 2510 |
| 38231 | CEFBS_HasNEON, // VLD1DUPd32wb_fixed = 2511 |
| 38232 | CEFBS_HasNEON, // VLD1DUPd32wb_register = 2512 |
| 38233 | CEFBS_HasNEON, // VLD1DUPd8 = 2513 |
| 38234 | CEFBS_HasNEON, // VLD1DUPd8wb_fixed = 2514 |
| 38235 | CEFBS_HasNEON, // VLD1DUPd8wb_register = 2515 |
| 38236 | CEFBS_HasNEON, // VLD1DUPq16 = 2516 |
| 38237 | CEFBS_HasNEON, // VLD1DUPq16wb_fixed = 2517 |
| 38238 | CEFBS_HasNEON, // VLD1DUPq16wb_register = 2518 |
| 38239 | CEFBS_HasNEON, // VLD1DUPq32 = 2519 |
| 38240 | CEFBS_HasNEON, // VLD1DUPq32wb_fixed = 2520 |
| 38241 | CEFBS_HasNEON, // VLD1DUPq32wb_register = 2521 |
| 38242 | CEFBS_HasNEON, // VLD1DUPq8 = 2522 |
| 38243 | CEFBS_HasNEON, // VLD1DUPq8wb_fixed = 2523 |
| 38244 | CEFBS_HasNEON, // VLD1DUPq8wb_register = 2524 |
| 38245 | CEFBS_HasNEON, // VLD1LNd16 = 2525 |
| 38246 | CEFBS_HasNEON, // VLD1LNd16_UPD = 2526 |
| 38247 | CEFBS_HasNEON, // VLD1LNd32 = 2527 |
| 38248 | CEFBS_HasNEON, // VLD1LNd32_UPD = 2528 |
| 38249 | CEFBS_HasNEON, // VLD1LNd8 = 2529 |
| 38250 | CEFBS_HasNEON, // VLD1LNd8_UPD = 2530 |
| 38251 | CEFBS_HasNEON, // VLD1LNq16Pseudo = 2531 |
| 38252 | CEFBS_HasNEON, // VLD1LNq16Pseudo_UPD = 2532 |
| 38253 | CEFBS_HasNEON, // VLD1LNq32Pseudo = 2533 |
| 38254 | CEFBS_HasNEON, // VLD1LNq32Pseudo_UPD = 2534 |
| 38255 | CEFBS_HasNEON, // VLD1LNq8Pseudo = 2535 |
| 38256 | CEFBS_HasNEON, // VLD1LNq8Pseudo_UPD = 2536 |
| 38257 | CEFBS_HasNEON, // VLD1d16 = 2537 |
| 38258 | CEFBS_HasNEON, // VLD1d16Q = 2538 |
| 38259 | CEFBS_HasNEON, // VLD1d16QPseudo = 2539 |
| 38260 | CEFBS_HasNEON, // VLD1d16QPseudoWB_fixed = 2540 |
| 38261 | CEFBS_HasNEON, // VLD1d16QPseudoWB_register = 2541 |
| 38262 | CEFBS_HasNEON, // VLD1d16Qwb_fixed = 2542 |
| 38263 | CEFBS_HasNEON, // VLD1d16Qwb_register = 2543 |
| 38264 | CEFBS_HasNEON, // VLD1d16T = 2544 |
| 38265 | CEFBS_HasNEON, // VLD1d16TPseudo = 2545 |
| 38266 | CEFBS_HasNEON, // VLD1d16TPseudoWB_fixed = 2546 |
| 38267 | CEFBS_HasNEON, // VLD1d16TPseudoWB_register = 2547 |
| 38268 | CEFBS_HasNEON, // VLD1d16Twb_fixed = 2548 |
| 38269 | CEFBS_HasNEON, // VLD1d16Twb_register = 2549 |
| 38270 | CEFBS_HasNEON, // VLD1d16wb_fixed = 2550 |
| 38271 | CEFBS_HasNEON, // VLD1d16wb_register = 2551 |
| 38272 | CEFBS_HasNEON, // VLD1d32 = 2552 |
| 38273 | CEFBS_HasNEON, // VLD1d32Q = 2553 |
| 38274 | CEFBS_HasNEON, // VLD1d32QPseudo = 2554 |
| 38275 | CEFBS_HasNEON, // VLD1d32QPseudoWB_fixed = 2555 |
| 38276 | CEFBS_HasNEON, // VLD1d32QPseudoWB_register = 2556 |
| 38277 | CEFBS_HasNEON, // VLD1d32Qwb_fixed = 2557 |
| 38278 | CEFBS_HasNEON, // VLD1d32Qwb_register = 2558 |
| 38279 | CEFBS_HasNEON, // VLD1d32T = 2559 |
| 38280 | CEFBS_HasNEON, // VLD1d32TPseudo = 2560 |
| 38281 | CEFBS_HasNEON, // VLD1d32TPseudoWB_fixed = 2561 |
| 38282 | CEFBS_HasNEON, // VLD1d32TPseudoWB_register = 2562 |
| 38283 | CEFBS_HasNEON, // VLD1d32Twb_fixed = 2563 |
| 38284 | CEFBS_HasNEON, // VLD1d32Twb_register = 2564 |
| 38285 | CEFBS_HasNEON, // VLD1d32wb_fixed = 2565 |
| 38286 | CEFBS_HasNEON, // VLD1d32wb_register = 2566 |
| 38287 | CEFBS_HasNEON, // VLD1d64 = 2567 |
| 38288 | CEFBS_HasNEON, // VLD1d64Q = 2568 |
| 38289 | CEFBS_HasNEON, // VLD1d64QPseudo = 2569 |
| 38290 | CEFBS_HasNEON, // VLD1d64QPseudoWB_fixed = 2570 |
| 38291 | CEFBS_HasNEON, // VLD1d64QPseudoWB_register = 2571 |
| 38292 | CEFBS_HasNEON, // VLD1d64Qwb_fixed = 2572 |
| 38293 | CEFBS_HasNEON, // VLD1d64Qwb_register = 2573 |
| 38294 | CEFBS_HasNEON, // VLD1d64T = 2574 |
| 38295 | CEFBS_HasNEON, // VLD1d64TPseudo = 2575 |
| 38296 | CEFBS_HasNEON, // VLD1d64TPseudoWB_fixed = 2576 |
| 38297 | CEFBS_HasNEON, // VLD1d64TPseudoWB_register = 2577 |
| 38298 | CEFBS_HasNEON, // VLD1d64Twb_fixed = 2578 |
| 38299 | CEFBS_HasNEON, // VLD1d64Twb_register = 2579 |
| 38300 | CEFBS_HasNEON, // VLD1d64wb_fixed = 2580 |
| 38301 | CEFBS_HasNEON, // VLD1d64wb_register = 2581 |
| 38302 | CEFBS_HasNEON, // VLD1d8 = 2582 |
| 38303 | CEFBS_HasNEON, // VLD1d8Q = 2583 |
| 38304 | CEFBS_HasNEON, // VLD1d8QPseudo = 2584 |
| 38305 | CEFBS_HasNEON, // VLD1d8QPseudoWB_fixed = 2585 |
| 38306 | CEFBS_HasNEON, // VLD1d8QPseudoWB_register = 2586 |
| 38307 | CEFBS_HasNEON, // VLD1d8Qwb_fixed = 2587 |
| 38308 | CEFBS_HasNEON, // VLD1d8Qwb_register = 2588 |
| 38309 | CEFBS_HasNEON, // VLD1d8T = 2589 |
| 38310 | CEFBS_HasNEON, // VLD1d8TPseudo = 2590 |
| 38311 | CEFBS_HasNEON, // VLD1d8TPseudoWB_fixed = 2591 |
| 38312 | CEFBS_HasNEON, // VLD1d8TPseudoWB_register = 2592 |
| 38313 | CEFBS_HasNEON, // VLD1d8Twb_fixed = 2593 |
| 38314 | CEFBS_HasNEON, // VLD1d8Twb_register = 2594 |
| 38315 | CEFBS_HasNEON, // VLD1d8wb_fixed = 2595 |
| 38316 | CEFBS_HasNEON, // VLD1d8wb_register = 2596 |
| 38317 | CEFBS_HasNEON, // VLD1q16 = 2597 |
| 38318 | CEFBS_HasNEON, // VLD1q16HighQPseudo = 2598 |
| 38319 | CEFBS_HasNEON, // VLD1q16HighQPseudo_UPD = 2599 |
| 38320 | CEFBS_HasNEON, // VLD1q16HighTPseudo = 2600 |
| 38321 | CEFBS_HasNEON, // VLD1q16HighTPseudo_UPD = 2601 |
| 38322 | CEFBS_HasNEON, // VLD1q16LowQPseudo_UPD = 2602 |
| 38323 | CEFBS_HasNEON, // VLD1q16LowTPseudo_UPD = 2603 |
| 38324 | CEFBS_HasNEON, // VLD1q16wb_fixed = 2604 |
| 38325 | CEFBS_HasNEON, // VLD1q16wb_register = 2605 |
| 38326 | CEFBS_HasNEON, // VLD1q32 = 2606 |
| 38327 | CEFBS_HasNEON, // VLD1q32HighQPseudo = 2607 |
| 38328 | CEFBS_HasNEON, // VLD1q32HighQPseudo_UPD = 2608 |
| 38329 | CEFBS_HasNEON, // VLD1q32HighTPseudo = 2609 |
| 38330 | CEFBS_HasNEON, // VLD1q32HighTPseudo_UPD = 2610 |
| 38331 | CEFBS_HasNEON, // VLD1q32LowQPseudo_UPD = 2611 |
| 38332 | CEFBS_HasNEON, // VLD1q32LowTPseudo_UPD = 2612 |
| 38333 | CEFBS_HasNEON, // VLD1q32wb_fixed = 2613 |
| 38334 | CEFBS_HasNEON, // VLD1q32wb_register = 2614 |
| 38335 | CEFBS_HasNEON, // VLD1q64 = 2615 |
| 38336 | CEFBS_HasNEON, // VLD1q64HighQPseudo = 2616 |
| 38337 | CEFBS_HasNEON, // VLD1q64HighQPseudo_UPD = 2617 |
| 38338 | CEFBS_HasNEON, // VLD1q64HighTPseudo = 2618 |
| 38339 | CEFBS_HasNEON, // VLD1q64HighTPseudo_UPD = 2619 |
| 38340 | CEFBS_HasNEON, // VLD1q64LowQPseudo_UPD = 2620 |
| 38341 | CEFBS_HasNEON, // VLD1q64LowTPseudo_UPD = 2621 |
| 38342 | CEFBS_HasNEON, // VLD1q64wb_fixed = 2622 |
| 38343 | CEFBS_HasNEON, // VLD1q64wb_register = 2623 |
| 38344 | CEFBS_HasNEON, // VLD1q8 = 2624 |
| 38345 | CEFBS_HasNEON, // VLD1q8HighQPseudo = 2625 |
| 38346 | CEFBS_HasNEON, // VLD1q8HighQPseudo_UPD = 2626 |
| 38347 | CEFBS_HasNEON, // VLD1q8HighTPseudo = 2627 |
| 38348 | CEFBS_HasNEON, // VLD1q8HighTPseudo_UPD = 2628 |
| 38349 | CEFBS_HasNEON, // VLD1q8LowQPseudo_UPD = 2629 |
| 38350 | CEFBS_HasNEON, // VLD1q8LowTPseudo_UPD = 2630 |
| 38351 | CEFBS_HasNEON, // VLD1q8wb_fixed = 2631 |
| 38352 | CEFBS_HasNEON, // VLD1q8wb_register = 2632 |
| 38353 | CEFBS_HasNEON, // VLD2DUPd16 = 2633 |
| 38354 | CEFBS_HasNEON, // VLD2DUPd16wb_fixed = 2634 |
| 38355 | CEFBS_HasNEON, // VLD2DUPd16wb_register = 2635 |
| 38356 | CEFBS_HasNEON, // VLD2DUPd16x2 = 2636 |
| 38357 | CEFBS_HasNEON, // VLD2DUPd16x2wb_fixed = 2637 |
| 38358 | CEFBS_HasNEON, // VLD2DUPd16x2wb_register = 2638 |
| 38359 | CEFBS_HasNEON, // VLD2DUPd32 = 2639 |
| 38360 | CEFBS_HasNEON, // VLD2DUPd32wb_fixed = 2640 |
| 38361 | CEFBS_HasNEON, // VLD2DUPd32wb_register = 2641 |
| 38362 | CEFBS_HasNEON, // VLD2DUPd32x2 = 2642 |
| 38363 | CEFBS_HasNEON, // VLD2DUPd32x2wb_fixed = 2643 |
| 38364 | CEFBS_HasNEON, // VLD2DUPd32x2wb_register = 2644 |
| 38365 | CEFBS_HasNEON, // VLD2DUPd8 = 2645 |
| 38366 | CEFBS_HasNEON, // VLD2DUPd8wb_fixed = 2646 |
| 38367 | CEFBS_HasNEON, // VLD2DUPd8wb_register = 2647 |
| 38368 | CEFBS_HasNEON, // VLD2DUPd8x2 = 2648 |
| 38369 | CEFBS_HasNEON, // VLD2DUPd8x2wb_fixed = 2649 |
| 38370 | CEFBS_HasNEON, // VLD2DUPd8x2wb_register = 2650 |
| 38371 | CEFBS_HasNEON, // VLD2DUPq16EvenPseudo = 2651 |
| 38372 | CEFBS_HasNEON, // VLD2DUPq16OddPseudo = 2652 |
| 38373 | CEFBS_HasNEON, // VLD2DUPq16OddPseudoWB_fixed = 2653 |
| 38374 | CEFBS_HasNEON, // VLD2DUPq16OddPseudoWB_register = 2654 |
| 38375 | CEFBS_HasNEON, // VLD2DUPq32EvenPseudo = 2655 |
| 38376 | CEFBS_HasNEON, // VLD2DUPq32OddPseudo = 2656 |
| 38377 | CEFBS_HasNEON, // VLD2DUPq32OddPseudoWB_fixed = 2657 |
| 38378 | CEFBS_HasNEON, // VLD2DUPq32OddPseudoWB_register = 2658 |
| 38379 | CEFBS_HasNEON, // VLD2DUPq8EvenPseudo = 2659 |
| 38380 | CEFBS_HasNEON, // VLD2DUPq8OddPseudo = 2660 |
| 38381 | CEFBS_HasNEON, // VLD2DUPq8OddPseudoWB_fixed = 2661 |
| 38382 | CEFBS_HasNEON, // VLD2DUPq8OddPseudoWB_register = 2662 |
| 38383 | CEFBS_HasNEON, // VLD2LNd16 = 2663 |
| 38384 | CEFBS_HasNEON, // VLD2LNd16Pseudo = 2664 |
| 38385 | CEFBS_HasNEON, // VLD2LNd16Pseudo_UPD = 2665 |
| 38386 | CEFBS_HasNEON, // VLD2LNd16_UPD = 2666 |
| 38387 | CEFBS_HasNEON, // VLD2LNd32 = 2667 |
| 38388 | CEFBS_HasNEON, // VLD2LNd32Pseudo = 2668 |
| 38389 | CEFBS_HasNEON, // VLD2LNd32Pseudo_UPD = 2669 |
| 38390 | CEFBS_HasNEON, // VLD2LNd32_UPD = 2670 |
| 38391 | CEFBS_HasNEON, // VLD2LNd8 = 2671 |
| 38392 | CEFBS_HasNEON, // VLD2LNd8Pseudo = 2672 |
| 38393 | CEFBS_HasNEON, // VLD2LNd8Pseudo_UPD = 2673 |
| 38394 | CEFBS_HasNEON, // VLD2LNd8_UPD = 2674 |
| 38395 | CEFBS_HasNEON, // VLD2LNq16 = 2675 |
| 38396 | CEFBS_HasNEON, // VLD2LNq16Pseudo = 2676 |
| 38397 | CEFBS_HasNEON, // VLD2LNq16Pseudo_UPD = 2677 |
| 38398 | CEFBS_HasNEON, // VLD2LNq16_UPD = 2678 |
| 38399 | CEFBS_HasNEON, // VLD2LNq32 = 2679 |
| 38400 | CEFBS_HasNEON, // VLD2LNq32Pseudo = 2680 |
| 38401 | CEFBS_HasNEON, // VLD2LNq32Pseudo_UPD = 2681 |
| 38402 | CEFBS_HasNEON, // VLD2LNq32_UPD = 2682 |
| 38403 | CEFBS_HasNEON, // VLD2b16 = 2683 |
| 38404 | CEFBS_HasNEON, // VLD2b16wb_fixed = 2684 |
| 38405 | CEFBS_HasNEON, // VLD2b16wb_register = 2685 |
| 38406 | CEFBS_HasNEON, // VLD2b32 = 2686 |
| 38407 | CEFBS_HasNEON, // VLD2b32wb_fixed = 2687 |
| 38408 | CEFBS_HasNEON, // VLD2b32wb_register = 2688 |
| 38409 | CEFBS_HasNEON, // VLD2b8 = 2689 |
| 38410 | CEFBS_HasNEON, // VLD2b8wb_fixed = 2690 |
| 38411 | CEFBS_HasNEON, // VLD2b8wb_register = 2691 |
| 38412 | CEFBS_HasNEON, // VLD2d16 = 2692 |
| 38413 | CEFBS_HasNEON, // VLD2d16wb_fixed = 2693 |
| 38414 | CEFBS_HasNEON, // VLD2d16wb_register = 2694 |
| 38415 | CEFBS_HasNEON, // VLD2d32 = 2695 |
| 38416 | CEFBS_HasNEON, // VLD2d32wb_fixed = 2696 |
| 38417 | CEFBS_HasNEON, // VLD2d32wb_register = 2697 |
| 38418 | CEFBS_HasNEON, // VLD2d8 = 2698 |
| 38419 | CEFBS_HasNEON, // VLD2d8wb_fixed = 2699 |
| 38420 | CEFBS_HasNEON, // VLD2d8wb_register = 2700 |
| 38421 | CEFBS_HasNEON, // VLD2q16 = 2701 |
| 38422 | CEFBS_HasNEON, // VLD2q16Pseudo = 2702 |
| 38423 | CEFBS_HasNEON, // VLD2q16PseudoWB_fixed = 2703 |
| 38424 | CEFBS_HasNEON, // VLD2q16PseudoWB_register = 2704 |
| 38425 | CEFBS_HasNEON, // VLD2q16wb_fixed = 2705 |
| 38426 | CEFBS_HasNEON, // VLD2q16wb_register = 2706 |
| 38427 | CEFBS_HasNEON, // VLD2q32 = 2707 |
| 38428 | CEFBS_HasNEON, // VLD2q32Pseudo = 2708 |
| 38429 | CEFBS_HasNEON, // VLD2q32PseudoWB_fixed = 2709 |
| 38430 | CEFBS_HasNEON, // VLD2q32PseudoWB_register = 2710 |
| 38431 | CEFBS_HasNEON, // VLD2q32wb_fixed = 2711 |
| 38432 | CEFBS_HasNEON, // VLD2q32wb_register = 2712 |
| 38433 | CEFBS_HasNEON, // VLD2q8 = 2713 |
| 38434 | CEFBS_HasNEON, // VLD2q8Pseudo = 2714 |
| 38435 | CEFBS_HasNEON, // VLD2q8PseudoWB_fixed = 2715 |
| 38436 | CEFBS_HasNEON, // VLD2q8PseudoWB_register = 2716 |
| 38437 | CEFBS_HasNEON, // VLD2q8wb_fixed = 2717 |
| 38438 | CEFBS_HasNEON, // VLD2q8wb_register = 2718 |
| 38439 | CEFBS_HasNEON, // VLD3DUPd16 = 2719 |
| 38440 | CEFBS_HasNEON, // VLD3DUPd16Pseudo = 2720 |
| 38441 | CEFBS_HasNEON, // VLD3DUPd16Pseudo_UPD = 2721 |
| 38442 | CEFBS_HasNEON, // VLD3DUPd16_UPD = 2722 |
| 38443 | CEFBS_HasNEON, // VLD3DUPd32 = 2723 |
| 38444 | CEFBS_HasNEON, // VLD3DUPd32Pseudo = 2724 |
| 38445 | CEFBS_HasNEON, // VLD3DUPd32Pseudo_UPD = 2725 |
| 38446 | CEFBS_HasNEON, // VLD3DUPd32_UPD = 2726 |
| 38447 | CEFBS_HasNEON, // VLD3DUPd8 = 2727 |
| 38448 | CEFBS_HasNEON, // VLD3DUPd8Pseudo = 2728 |
| 38449 | CEFBS_HasNEON, // VLD3DUPd8Pseudo_UPD = 2729 |
| 38450 | CEFBS_HasNEON, // VLD3DUPd8_UPD = 2730 |
| 38451 | CEFBS_HasNEON, // VLD3DUPq16 = 2731 |
| 38452 | CEFBS_HasNEON, // VLD3DUPq16EvenPseudo = 2732 |
| 38453 | CEFBS_HasNEON, // VLD3DUPq16OddPseudo = 2733 |
| 38454 | CEFBS_HasNEON, // VLD3DUPq16OddPseudo_UPD = 2734 |
| 38455 | CEFBS_HasNEON, // VLD3DUPq16_UPD = 2735 |
| 38456 | CEFBS_HasNEON, // VLD3DUPq32 = 2736 |
| 38457 | CEFBS_HasNEON, // VLD3DUPq32EvenPseudo = 2737 |
| 38458 | CEFBS_HasNEON, // VLD3DUPq32OddPseudo = 2738 |
| 38459 | CEFBS_HasNEON, // VLD3DUPq32OddPseudo_UPD = 2739 |
| 38460 | CEFBS_HasNEON, // VLD3DUPq32_UPD = 2740 |
| 38461 | CEFBS_HasNEON, // VLD3DUPq8 = 2741 |
| 38462 | CEFBS_HasNEON, // VLD3DUPq8EvenPseudo = 2742 |
| 38463 | CEFBS_HasNEON, // VLD3DUPq8OddPseudo = 2743 |
| 38464 | CEFBS_HasNEON, // VLD3DUPq8OddPseudo_UPD = 2744 |
| 38465 | CEFBS_HasNEON, // VLD3DUPq8_UPD = 2745 |
| 38466 | CEFBS_HasNEON, // VLD3LNd16 = 2746 |
| 38467 | CEFBS_HasNEON, // VLD3LNd16Pseudo = 2747 |
| 38468 | CEFBS_HasNEON, // VLD3LNd16Pseudo_UPD = 2748 |
| 38469 | CEFBS_HasNEON, // VLD3LNd16_UPD = 2749 |
| 38470 | CEFBS_HasNEON, // VLD3LNd32 = 2750 |
| 38471 | CEFBS_HasNEON, // VLD3LNd32Pseudo = 2751 |
| 38472 | CEFBS_HasNEON, // VLD3LNd32Pseudo_UPD = 2752 |
| 38473 | CEFBS_HasNEON, // VLD3LNd32_UPD = 2753 |
| 38474 | CEFBS_HasNEON, // VLD3LNd8 = 2754 |
| 38475 | CEFBS_HasNEON, // VLD3LNd8Pseudo = 2755 |
| 38476 | CEFBS_HasNEON, // VLD3LNd8Pseudo_UPD = 2756 |
| 38477 | CEFBS_HasNEON, // VLD3LNd8_UPD = 2757 |
| 38478 | CEFBS_HasNEON, // VLD3LNq16 = 2758 |
| 38479 | CEFBS_HasNEON, // VLD3LNq16Pseudo = 2759 |
| 38480 | CEFBS_HasNEON, // VLD3LNq16Pseudo_UPD = 2760 |
| 38481 | CEFBS_HasNEON, // VLD3LNq16_UPD = 2761 |
| 38482 | CEFBS_HasNEON, // VLD3LNq32 = 2762 |
| 38483 | CEFBS_HasNEON, // VLD3LNq32Pseudo = 2763 |
| 38484 | CEFBS_HasNEON, // VLD3LNq32Pseudo_UPD = 2764 |
| 38485 | CEFBS_HasNEON, // VLD3LNq32_UPD = 2765 |
| 38486 | CEFBS_HasNEON, // VLD3d16 = 2766 |
| 38487 | CEFBS_HasNEON, // VLD3d16Pseudo = 2767 |
| 38488 | CEFBS_HasNEON, // VLD3d16Pseudo_UPD = 2768 |
| 38489 | CEFBS_HasNEON, // VLD3d16_UPD = 2769 |
| 38490 | CEFBS_HasNEON, // VLD3d32 = 2770 |
| 38491 | CEFBS_HasNEON, // VLD3d32Pseudo = 2771 |
| 38492 | CEFBS_HasNEON, // VLD3d32Pseudo_UPD = 2772 |
| 38493 | CEFBS_HasNEON, // VLD3d32_UPD = 2773 |
| 38494 | CEFBS_HasNEON, // VLD3d8 = 2774 |
| 38495 | CEFBS_HasNEON, // VLD3d8Pseudo = 2775 |
| 38496 | CEFBS_HasNEON, // VLD3d8Pseudo_UPD = 2776 |
| 38497 | CEFBS_HasNEON, // VLD3d8_UPD = 2777 |
| 38498 | CEFBS_HasNEON, // VLD3q16 = 2778 |
| 38499 | CEFBS_HasNEON, // VLD3q16Pseudo_UPD = 2779 |
| 38500 | CEFBS_HasNEON, // VLD3q16_UPD = 2780 |
| 38501 | CEFBS_HasNEON, // VLD3q16oddPseudo = 2781 |
| 38502 | CEFBS_HasNEON, // VLD3q16oddPseudo_UPD = 2782 |
| 38503 | CEFBS_HasNEON, // VLD3q32 = 2783 |
| 38504 | CEFBS_HasNEON, // VLD3q32Pseudo_UPD = 2784 |
| 38505 | CEFBS_HasNEON, // VLD3q32_UPD = 2785 |
| 38506 | CEFBS_HasNEON, // VLD3q32oddPseudo = 2786 |
| 38507 | CEFBS_HasNEON, // VLD3q32oddPseudo_UPD = 2787 |
| 38508 | CEFBS_HasNEON, // VLD3q8 = 2788 |
| 38509 | CEFBS_HasNEON, // VLD3q8Pseudo_UPD = 2789 |
| 38510 | CEFBS_HasNEON, // VLD3q8_UPD = 2790 |
| 38511 | CEFBS_HasNEON, // VLD3q8oddPseudo = 2791 |
| 38512 | CEFBS_HasNEON, // VLD3q8oddPseudo_UPD = 2792 |
| 38513 | CEFBS_HasNEON, // VLD4DUPd16 = 2793 |
| 38514 | CEFBS_HasNEON, // VLD4DUPd16Pseudo = 2794 |
| 38515 | CEFBS_HasNEON, // VLD4DUPd16Pseudo_UPD = 2795 |
| 38516 | CEFBS_HasNEON, // VLD4DUPd16_UPD = 2796 |
| 38517 | CEFBS_HasNEON, // VLD4DUPd32 = 2797 |
| 38518 | CEFBS_HasNEON, // VLD4DUPd32Pseudo = 2798 |
| 38519 | CEFBS_HasNEON, // VLD4DUPd32Pseudo_UPD = 2799 |
| 38520 | CEFBS_HasNEON, // VLD4DUPd32_UPD = 2800 |
| 38521 | CEFBS_HasNEON, // VLD4DUPd8 = 2801 |
| 38522 | CEFBS_HasNEON, // VLD4DUPd8Pseudo = 2802 |
| 38523 | CEFBS_HasNEON, // VLD4DUPd8Pseudo_UPD = 2803 |
| 38524 | CEFBS_HasNEON, // VLD4DUPd8_UPD = 2804 |
| 38525 | CEFBS_HasNEON, // VLD4DUPq16 = 2805 |
| 38526 | CEFBS_HasNEON, // VLD4DUPq16EvenPseudo = 2806 |
| 38527 | CEFBS_HasNEON, // VLD4DUPq16OddPseudo = 2807 |
| 38528 | CEFBS_HasNEON, // VLD4DUPq16OddPseudo_UPD = 2808 |
| 38529 | CEFBS_HasNEON, // VLD4DUPq16_UPD = 2809 |
| 38530 | CEFBS_HasNEON, // VLD4DUPq32 = 2810 |
| 38531 | CEFBS_HasNEON, // VLD4DUPq32EvenPseudo = 2811 |
| 38532 | CEFBS_HasNEON, // VLD4DUPq32OddPseudo = 2812 |
| 38533 | CEFBS_HasNEON, // VLD4DUPq32OddPseudo_UPD = 2813 |
| 38534 | CEFBS_HasNEON, // VLD4DUPq32_UPD = 2814 |
| 38535 | CEFBS_HasNEON, // VLD4DUPq8 = 2815 |
| 38536 | CEFBS_HasNEON, // VLD4DUPq8EvenPseudo = 2816 |
| 38537 | CEFBS_HasNEON, // VLD4DUPq8OddPseudo = 2817 |
| 38538 | CEFBS_HasNEON, // VLD4DUPq8OddPseudo_UPD = 2818 |
| 38539 | CEFBS_HasNEON, // VLD4DUPq8_UPD = 2819 |
| 38540 | CEFBS_HasNEON, // VLD4LNd16 = 2820 |
| 38541 | CEFBS_HasNEON, // VLD4LNd16Pseudo = 2821 |
| 38542 | CEFBS_HasNEON, // VLD4LNd16Pseudo_UPD = 2822 |
| 38543 | CEFBS_HasNEON, // VLD4LNd16_UPD = 2823 |
| 38544 | CEFBS_HasNEON, // VLD4LNd32 = 2824 |
| 38545 | CEFBS_HasNEON, // VLD4LNd32Pseudo = 2825 |
| 38546 | CEFBS_HasNEON, // VLD4LNd32Pseudo_UPD = 2826 |
| 38547 | CEFBS_HasNEON, // VLD4LNd32_UPD = 2827 |
| 38548 | CEFBS_HasNEON, // VLD4LNd8 = 2828 |
| 38549 | CEFBS_HasNEON, // VLD4LNd8Pseudo = 2829 |
| 38550 | CEFBS_HasNEON, // VLD4LNd8Pseudo_UPD = 2830 |
| 38551 | CEFBS_HasNEON, // VLD4LNd8_UPD = 2831 |
| 38552 | CEFBS_HasNEON, // VLD4LNq16 = 2832 |
| 38553 | CEFBS_HasNEON, // VLD4LNq16Pseudo = 2833 |
| 38554 | CEFBS_HasNEON, // VLD4LNq16Pseudo_UPD = 2834 |
| 38555 | CEFBS_HasNEON, // VLD4LNq16_UPD = 2835 |
| 38556 | CEFBS_HasNEON, // VLD4LNq32 = 2836 |
| 38557 | CEFBS_HasNEON, // VLD4LNq32Pseudo = 2837 |
| 38558 | CEFBS_HasNEON, // VLD4LNq32Pseudo_UPD = 2838 |
| 38559 | CEFBS_HasNEON, // VLD4LNq32_UPD = 2839 |
| 38560 | CEFBS_HasNEON, // VLD4d16 = 2840 |
| 38561 | CEFBS_HasNEON, // VLD4d16Pseudo = 2841 |
| 38562 | CEFBS_HasNEON, // VLD4d16Pseudo_UPD = 2842 |
| 38563 | CEFBS_HasNEON, // VLD4d16_UPD = 2843 |
| 38564 | CEFBS_HasNEON, // VLD4d32 = 2844 |
| 38565 | CEFBS_HasNEON, // VLD4d32Pseudo = 2845 |
| 38566 | CEFBS_HasNEON, // VLD4d32Pseudo_UPD = 2846 |
| 38567 | CEFBS_HasNEON, // VLD4d32_UPD = 2847 |
| 38568 | CEFBS_HasNEON, // VLD4d8 = 2848 |
| 38569 | CEFBS_HasNEON, // VLD4d8Pseudo = 2849 |
| 38570 | CEFBS_HasNEON, // VLD4d8Pseudo_UPD = 2850 |
| 38571 | CEFBS_HasNEON, // VLD4d8_UPD = 2851 |
| 38572 | CEFBS_HasNEON, // VLD4q16 = 2852 |
| 38573 | CEFBS_HasNEON, // VLD4q16Pseudo_UPD = 2853 |
| 38574 | CEFBS_HasNEON, // VLD4q16_UPD = 2854 |
| 38575 | CEFBS_HasNEON, // VLD4q16oddPseudo = 2855 |
| 38576 | CEFBS_HasNEON, // VLD4q16oddPseudo_UPD = 2856 |
| 38577 | CEFBS_HasNEON, // VLD4q32 = 2857 |
| 38578 | CEFBS_HasNEON, // VLD4q32Pseudo_UPD = 2858 |
| 38579 | CEFBS_HasNEON, // VLD4q32_UPD = 2859 |
| 38580 | CEFBS_HasNEON, // VLD4q32oddPseudo = 2860 |
| 38581 | CEFBS_HasNEON, // VLD4q32oddPseudo_UPD = 2861 |
| 38582 | CEFBS_HasNEON, // VLD4q8 = 2862 |
| 38583 | CEFBS_HasNEON, // VLD4q8Pseudo_UPD = 2863 |
| 38584 | CEFBS_HasNEON, // VLD4q8_UPD = 2864 |
| 38585 | CEFBS_HasNEON, // VLD4q8oddPseudo = 2865 |
| 38586 | CEFBS_HasNEON, // VLD4q8oddPseudo_UPD = 2866 |
| 38587 | CEFBS_HasFPRegs, // VLDMDDB_UPD = 2867 |
| 38588 | CEFBS_HasFPRegs, // VLDMDIA = 2868 |
| 38589 | CEFBS_HasFPRegs, // VLDMDIA_UPD = 2869 |
| 38590 | CEFBS_HasVFP2, // VLDMQIA = 2870 |
| 38591 | CEFBS_HasFPRegs, // VLDMSDB_UPD = 2871 |
| 38592 | CEFBS_HasFPRegs, // VLDMSIA = 2872 |
| 38593 | CEFBS_HasFPRegs, // VLDMSIA_UPD = 2873 |
| 38594 | CEFBS_HasFPRegs, // VLDRD = 2874 |
| 38595 | CEFBS_HasFPRegs16, // VLDRH = 2875 |
| 38596 | CEFBS_HasFPRegs, // VLDRS = 2876 |
| 38597 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_off = 2877 |
| 38598 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_post = 2878 |
| 38599 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_pre = 2879 |
| 38600 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_off = 2880 |
| 38601 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_post = 2881 |
| 38602 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_pre = 2882 |
| 38603 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_off = 2883 |
| 38604 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_post = 2884 |
| 38605 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_pre = 2885 |
| 38606 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_off = 2886 |
| 38607 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_post = 2887 |
| 38608 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_pre = 2888 |
| 38609 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_off = 2889 |
| 38610 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_post = 2890 |
| 38611 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_pre = 2891 |
| 38612 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_off = 2892 |
| 38613 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_post = 2893 |
| 38614 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_pre = 2894 |
| 38615 | CEFBS_HasV8MMainline_Has8MSecExt, // VLLDM = 2895 |
| 38616 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLLDM_T2 = 2896 |
| 38617 | CEFBS_HasV8MMainline_Has8MSecExt, // VLSTM = 2897 |
| 38618 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLSTM_T2 = 2898 |
| 38619 | CEFBS_HasNEON, // VMAXfd = 2899 |
| 38620 | CEFBS_HasNEON, // VMAXfq = 2900 |
| 38621 | CEFBS_HasNEON_HasFullFP16, // VMAXhd = 2901 |
| 38622 | CEFBS_HasNEON_HasFullFP16, // VMAXhq = 2902 |
| 38623 | CEFBS_HasNEON, // VMAXsv16i8 = 2903 |
| 38624 | CEFBS_HasNEON, // VMAXsv2i32 = 2904 |
| 38625 | CEFBS_HasNEON, // VMAXsv4i16 = 2905 |
| 38626 | CEFBS_HasNEON, // VMAXsv4i32 = 2906 |
| 38627 | CEFBS_HasNEON, // VMAXsv8i16 = 2907 |
| 38628 | CEFBS_HasNEON, // VMAXsv8i8 = 2908 |
| 38629 | CEFBS_HasNEON, // VMAXuv16i8 = 2909 |
| 38630 | CEFBS_HasNEON, // VMAXuv2i32 = 2910 |
| 38631 | CEFBS_HasNEON, // VMAXuv4i16 = 2911 |
| 38632 | CEFBS_HasNEON, // VMAXuv4i32 = 2912 |
| 38633 | CEFBS_HasNEON, // VMAXuv8i16 = 2913 |
| 38634 | CEFBS_HasNEON, // VMAXuv8i8 = 2914 |
| 38635 | CEFBS_HasNEON, // VMINfd = 2915 |
| 38636 | CEFBS_HasNEON, // VMINfq = 2916 |
| 38637 | CEFBS_HasNEON_HasFullFP16, // VMINhd = 2917 |
| 38638 | CEFBS_HasNEON_HasFullFP16, // VMINhq = 2918 |
| 38639 | CEFBS_HasNEON, // VMINsv16i8 = 2919 |
| 38640 | CEFBS_HasNEON, // VMINsv2i32 = 2920 |
| 38641 | CEFBS_HasNEON, // VMINsv4i16 = 2921 |
| 38642 | CEFBS_HasNEON, // VMINsv4i32 = 2922 |
| 38643 | CEFBS_HasNEON, // VMINsv8i16 = 2923 |
| 38644 | CEFBS_HasNEON, // VMINsv8i8 = 2924 |
| 38645 | CEFBS_HasNEON, // VMINuv16i8 = 2925 |
| 38646 | CEFBS_HasNEON, // VMINuv2i32 = 2926 |
| 38647 | CEFBS_HasNEON, // VMINuv4i16 = 2927 |
| 38648 | CEFBS_HasNEON, // VMINuv4i32 = 2928 |
| 38649 | CEFBS_HasNEON, // VMINuv8i16 = 2929 |
| 38650 | CEFBS_HasNEON, // VMINuv8i8 = 2930 |
| 38651 | CEFBS_HasVFP2_HasDPVFP, // VMLAD = 2931 |
| 38652 | CEFBS_HasFullFP16, // VMLAH = 2932 |
| 38653 | CEFBS_HasNEON, // VMLALslsv2i32 = 2933 |
| 38654 | CEFBS_HasNEON, // VMLALslsv4i16 = 2934 |
| 38655 | CEFBS_HasNEON, // VMLALsluv2i32 = 2935 |
| 38656 | CEFBS_HasNEON, // VMLALsluv4i16 = 2936 |
| 38657 | CEFBS_HasNEON, // VMLALsv2i64 = 2937 |
| 38658 | CEFBS_HasNEON, // VMLALsv4i32 = 2938 |
| 38659 | CEFBS_HasNEON, // VMLALsv8i16 = 2939 |
| 38660 | CEFBS_HasNEON, // VMLALuv2i64 = 2940 |
| 38661 | CEFBS_HasNEON, // VMLALuv4i32 = 2941 |
| 38662 | CEFBS_HasNEON, // VMLALuv8i16 = 2942 |
| 38663 | CEFBS_HasVFP2, // VMLAS = 2943 |
| 38664 | CEFBS_HasNEON, // VMLAfd = 2944 |
| 38665 | CEFBS_HasNEON, // VMLAfq = 2945 |
| 38666 | CEFBS_HasNEON_HasFullFP16, // VMLAhd = 2946 |
| 38667 | CEFBS_HasNEON_HasFullFP16, // VMLAhq = 2947 |
| 38668 | CEFBS_HasNEON, // VMLAslfd = 2948 |
| 38669 | CEFBS_HasNEON, // VMLAslfq = 2949 |
| 38670 | CEFBS_HasNEON_HasFullFP16, // VMLAslhd = 2950 |
| 38671 | CEFBS_HasNEON_HasFullFP16, // VMLAslhq = 2951 |
| 38672 | CEFBS_HasNEON, // VMLAslv2i32 = 2952 |
| 38673 | CEFBS_HasNEON, // VMLAslv4i16 = 2953 |
| 38674 | CEFBS_HasNEON, // VMLAslv4i32 = 2954 |
| 38675 | CEFBS_HasNEON, // VMLAslv8i16 = 2955 |
| 38676 | CEFBS_HasNEON, // VMLAv16i8 = 2956 |
| 38677 | CEFBS_HasNEON, // VMLAv2i32 = 2957 |
| 38678 | CEFBS_HasNEON, // VMLAv4i16 = 2958 |
| 38679 | CEFBS_HasNEON, // VMLAv4i32 = 2959 |
| 38680 | CEFBS_HasNEON, // VMLAv8i16 = 2960 |
| 38681 | CEFBS_HasNEON, // VMLAv8i8 = 2961 |
| 38682 | CEFBS_HasVFP2_HasDPVFP, // VMLSD = 2962 |
| 38683 | CEFBS_HasFullFP16, // VMLSH = 2963 |
| 38684 | CEFBS_HasNEON, // VMLSLslsv2i32 = 2964 |
| 38685 | CEFBS_HasNEON, // VMLSLslsv4i16 = 2965 |
| 38686 | CEFBS_HasNEON, // VMLSLsluv2i32 = 2966 |
| 38687 | CEFBS_HasNEON, // VMLSLsluv4i16 = 2967 |
| 38688 | CEFBS_HasNEON, // VMLSLsv2i64 = 2968 |
| 38689 | CEFBS_HasNEON, // VMLSLsv4i32 = 2969 |
| 38690 | CEFBS_HasNEON, // VMLSLsv8i16 = 2970 |
| 38691 | CEFBS_HasNEON, // VMLSLuv2i64 = 2971 |
| 38692 | CEFBS_HasNEON, // VMLSLuv4i32 = 2972 |
| 38693 | CEFBS_HasNEON, // VMLSLuv8i16 = 2973 |
| 38694 | CEFBS_HasVFP2, // VMLSS = 2974 |
| 38695 | CEFBS_HasNEON, // VMLSfd = 2975 |
| 38696 | CEFBS_HasNEON, // VMLSfq = 2976 |
| 38697 | CEFBS_HasNEON_HasFullFP16, // VMLShd = 2977 |
| 38698 | CEFBS_HasNEON_HasFullFP16, // VMLShq = 2978 |
| 38699 | CEFBS_HasNEON, // VMLSslfd = 2979 |
| 38700 | CEFBS_HasNEON, // VMLSslfq = 2980 |
| 38701 | CEFBS_HasNEON_HasFullFP16, // VMLSslhd = 2981 |
| 38702 | CEFBS_HasNEON_HasFullFP16, // VMLSslhq = 2982 |
| 38703 | CEFBS_HasNEON, // VMLSslv2i32 = 2983 |
| 38704 | CEFBS_HasNEON, // VMLSslv4i16 = 2984 |
| 38705 | CEFBS_HasNEON, // VMLSslv4i32 = 2985 |
| 38706 | CEFBS_HasNEON, // VMLSslv8i16 = 2986 |
| 38707 | CEFBS_HasNEON, // VMLSv16i8 = 2987 |
| 38708 | CEFBS_HasNEON, // VMLSv2i32 = 2988 |
| 38709 | CEFBS_HasNEON, // VMLSv4i16 = 2989 |
| 38710 | CEFBS_HasNEON, // VMLSv4i32 = 2990 |
| 38711 | CEFBS_HasNEON, // VMLSv8i16 = 2991 |
| 38712 | CEFBS_HasNEON, // VMLSv8i8 = 2992 |
| 38713 | CEFBS_HasBF16_HasNEON, // VMMLA = 2993 |
| 38714 | CEFBS_HasFPRegs64, // VMOVD = 2994 |
| 38715 | CEFBS_HasFPRegs, // VMOVDRR = 2995 |
| 38716 | CEFBS_HasFullFP16, // VMOVH = 2996 |
| 38717 | CEFBS_HasFPRegs16, // VMOVHR = 2997 |
| 38718 | CEFBS_HasNEON, // VMOVLsv2i64 = 2998 |
| 38719 | CEFBS_HasNEON, // VMOVLsv4i32 = 2999 |
| 38720 | CEFBS_HasNEON, // VMOVLsv8i16 = 3000 |
| 38721 | CEFBS_HasNEON, // VMOVLuv2i64 = 3001 |
| 38722 | CEFBS_HasNEON, // VMOVLuv4i32 = 3002 |
| 38723 | CEFBS_HasNEON, // VMOVLuv8i16 = 3003 |
| 38724 | CEFBS_HasNEON, // VMOVNv2i32 = 3004 |
| 38725 | CEFBS_HasNEON, // VMOVNv4i16 = 3005 |
| 38726 | CEFBS_HasNEON, // VMOVNv8i8 = 3006 |
| 38727 | CEFBS_HasFPRegs16, // VMOVRH = 3007 |
| 38728 | CEFBS_HasFPRegs, // VMOVRRD = 3008 |
| 38729 | CEFBS_HasFPRegs, // VMOVRRS = 3009 |
| 38730 | CEFBS_HasFPRegs, // VMOVRS = 3010 |
| 38731 | CEFBS_HasFPRegs, // VMOVS = 3011 |
| 38732 | CEFBS_HasFPRegs, // VMOVSR = 3012 |
| 38733 | CEFBS_HasFPRegs, // VMOVSRR = 3013 |
| 38734 | CEFBS_HasNEON, // VMOVv16i8 = 3014 |
| 38735 | CEFBS_HasNEON, // VMOVv1i64 = 3015 |
| 38736 | CEFBS_HasNEON, // VMOVv2f32 = 3016 |
| 38737 | CEFBS_HasNEON, // VMOVv2i32 = 3017 |
| 38738 | CEFBS_HasNEON, // VMOVv2i64 = 3018 |
| 38739 | CEFBS_HasNEON, // VMOVv4f32 = 3019 |
| 38740 | CEFBS_HasNEON, // VMOVv4i16 = 3020 |
| 38741 | CEFBS_HasNEON, // VMOVv4i32 = 3021 |
| 38742 | CEFBS_HasNEON, // VMOVv8i16 = 3022 |
| 38743 | CEFBS_HasNEON, // VMOVv8i8 = 3023 |
| 38744 | CEFBS_HasFPRegs, // VMRS = 3024 |
| 38745 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VMRS_FPCXTNS = 3025 |
| 38746 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VMRS_FPCXTS = 3026 |
| 38747 | CEFBS_HasVFP2, // VMRS_FPEXC = 3027 |
| 38748 | CEFBS_HasVFP2, // VMRS_FPINST = 3028 |
| 38749 | CEFBS_HasVFP2, // VMRS_FPINST2 = 3029 |
| 38750 | CEFBS_HasV8_1MMainline_HasFPRegs, // VMRS_FPSCR_NZCVQC = 3030 |
| 38751 | CEFBS_HasVFP2, // VMRS_FPSID = 3031 |
| 38752 | CEFBS_HasVFP2, // VMRS_MVFR0 = 3032 |
| 38753 | CEFBS_HasVFP2, // VMRS_MVFR1 = 3033 |
| 38754 | CEFBS_HasFPARMv8, // VMRS_MVFR2 = 3034 |
| 38755 | CEFBS_HasV8_1MMainline_HasMVEInt, // VMRS_P0 = 3035 |
| 38756 | CEFBS_HasV8_1MMainline_HasMVEInt, // VMRS_VPR = 3036 |
| 38757 | CEFBS_HasFPRegs, // VMSR = 3037 |
| 38758 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VMSR_FPCXTNS = 3038 |
| 38759 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VMSR_FPCXTS = 3039 |
| 38760 | CEFBS_HasVFP2, // VMSR_FPEXC = 3040 |
| 38761 | CEFBS_HasVFP2, // VMSR_FPINST = 3041 |
| 38762 | CEFBS_HasVFP2, // VMSR_FPINST2 = 3042 |
| 38763 | CEFBS_HasV8_1MMainline_HasFPRegs, // VMSR_FPSCR_NZCVQC = 3043 |
| 38764 | CEFBS_HasVFP2, // VMSR_FPSID = 3044 |
| 38765 | CEFBS_HasV8_1MMainline_HasMVEInt, // VMSR_P0 = 3045 |
| 38766 | CEFBS_HasV8_1MMainline_HasMVEInt, // VMSR_VPR = 3046 |
| 38767 | CEFBS_HasVFP2_HasDPVFP, // VMULD = 3047 |
| 38768 | CEFBS_HasFullFP16, // VMULH = 3048 |
| 38769 | CEFBS_HasV8_HasAES, // VMULLp64 = 3049 |
| 38770 | CEFBS_HasNEON, // VMULLp8 = 3050 |
| 38771 | CEFBS_HasNEON, // VMULLslsv2i32 = 3051 |
| 38772 | CEFBS_HasNEON, // VMULLslsv4i16 = 3052 |
| 38773 | CEFBS_HasNEON, // VMULLsluv2i32 = 3053 |
| 38774 | CEFBS_HasNEON, // VMULLsluv4i16 = 3054 |
| 38775 | CEFBS_HasNEON, // VMULLsv2i64 = 3055 |
| 38776 | CEFBS_HasNEON, // VMULLsv4i32 = 3056 |
| 38777 | CEFBS_HasNEON, // VMULLsv8i16 = 3057 |
| 38778 | CEFBS_HasNEON, // VMULLuv2i64 = 3058 |
| 38779 | CEFBS_HasNEON, // VMULLuv4i32 = 3059 |
| 38780 | CEFBS_HasNEON, // VMULLuv8i16 = 3060 |
| 38781 | CEFBS_HasVFP2, // VMULS = 3061 |
| 38782 | CEFBS_HasNEON, // VMULfd = 3062 |
| 38783 | CEFBS_HasNEON, // VMULfq = 3063 |
| 38784 | CEFBS_HasNEON_HasFullFP16, // VMULhd = 3064 |
| 38785 | CEFBS_HasNEON_HasFullFP16, // VMULhq = 3065 |
| 38786 | CEFBS_HasNEON, // VMULpd = 3066 |
| 38787 | CEFBS_HasNEON, // VMULpq = 3067 |
| 38788 | CEFBS_HasNEON, // VMULslfd = 3068 |
| 38789 | CEFBS_HasNEON, // VMULslfq = 3069 |
| 38790 | CEFBS_HasNEON_HasFullFP16, // VMULslhd = 3070 |
| 38791 | CEFBS_HasNEON_HasFullFP16, // VMULslhq = 3071 |
| 38792 | CEFBS_HasNEON, // VMULslv2i32 = 3072 |
| 38793 | CEFBS_HasNEON, // VMULslv4i16 = 3073 |
| 38794 | CEFBS_HasNEON, // VMULslv4i32 = 3074 |
| 38795 | CEFBS_HasNEON, // VMULslv8i16 = 3075 |
| 38796 | CEFBS_HasNEON, // VMULv16i8 = 3076 |
| 38797 | CEFBS_HasNEON, // VMULv2i32 = 3077 |
| 38798 | CEFBS_HasNEON, // VMULv4i16 = 3078 |
| 38799 | CEFBS_HasNEON, // VMULv4i32 = 3079 |
| 38800 | CEFBS_HasNEON, // VMULv8i16 = 3080 |
| 38801 | CEFBS_HasNEON, // VMULv8i8 = 3081 |
| 38802 | CEFBS_HasNEON, // VMVNd = 3082 |
| 38803 | CEFBS_HasNEON, // VMVNq = 3083 |
| 38804 | CEFBS_HasNEON, // VMVNv2i32 = 3084 |
| 38805 | CEFBS_HasNEON, // VMVNv4i16 = 3085 |
| 38806 | CEFBS_HasNEON, // VMVNv4i32 = 3086 |
| 38807 | CEFBS_HasNEON, // VMVNv8i16 = 3087 |
| 38808 | CEFBS_HasVFP2_HasDPVFP, // VNEGD = 3088 |
| 38809 | CEFBS_HasFullFP16, // VNEGH = 3089 |
| 38810 | CEFBS_HasVFP2, // VNEGS = 3090 |
| 38811 | CEFBS_HasNEON, // VNEGf32q = 3091 |
| 38812 | CEFBS_HasNEON, // VNEGfd = 3092 |
| 38813 | CEFBS_HasNEON_HasFullFP16, // VNEGhd = 3093 |
| 38814 | CEFBS_HasNEON_HasFullFP16, // VNEGhq = 3094 |
| 38815 | CEFBS_HasNEON, // VNEGs16d = 3095 |
| 38816 | CEFBS_HasNEON, // VNEGs16q = 3096 |
| 38817 | CEFBS_HasNEON, // VNEGs32d = 3097 |
| 38818 | CEFBS_HasNEON, // VNEGs32q = 3098 |
| 38819 | CEFBS_HasNEON, // VNEGs8d = 3099 |
| 38820 | CEFBS_HasNEON, // VNEGs8q = 3100 |
| 38821 | CEFBS_HasVFP2_HasDPVFP, // VNMLAD = 3101 |
| 38822 | CEFBS_HasFullFP16, // VNMLAH = 3102 |
| 38823 | CEFBS_HasVFP2, // VNMLAS = 3103 |
| 38824 | CEFBS_HasVFP2_HasDPVFP, // VNMLSD = 3104 |
| 38825 | CEFBS_HasFullFP16, // VNMLSH = 3105 |
| 38826 | CEFBS_HasVFP2, // VNMLSS = 3106 |
| 38827 | CEFBS_HasVFP2_HasDPVFP, // VNMULD = 3107 |
| 38828 | CEFBS_HasFullFP16, // VNMULH = 3108 |
| 38829 | CEFBS_HasVFP2, // VNMULS = 3109 |
| 38830 | CEFBS_HasNEON, // VORNd = 3110 |
| 38831 | CEFBS_HasNEON, // VORNq = 3111 |
| 38832 | CEFBS_HasNEON, // VORRd = 3112 |
| 38833 | CEFBS_HasNEON, // VORRiv2i32 = 3113 |
| 38834 | CEFBS_HasNEON, // VORRiv4i16 = 3114 |
| 38835 | CEFBS_HasNEON, // VORRiv4i32 = 3115 |
| 38836 | CEFBS_HasNEON, // VORRiv8i16 = 3116 |
| 38837 | CEFBS_HasNEON, // VORRq = 3117 |
| 38838 | CEFBS_HasNEON, // VPADALsv16i8 = 3118 |
| 38839 | CEFBS_HasNEON, // VPADALsv2i32 = 3119 |
| 38840 | CEFBS_HasNEON, // VPADALsv4i16 = 3120 |
| 38841 | CEFBS_HasNEON, // VPADALsv4i32 = 3121 |
| 38842 | CEFBS_HasNEON, // VPADALsv8i16 = 3122 |
| 38843 | CEFBS_HasNEON, // VPADALsv8i8 = 3123 |
| 38844 | CEFBS_HasNEON, // VPADALuv16i8 = 3124 |
| 38845 | CEFBS_HasNEON, // VPADALuv2i32 = 3125 |
| 38846 | CEFBS_HasNEON, // VPADALuv4i16 = 3126 |
| 38847 | CEFBS_HasNEON, // VPADALuv4i32 = 3127 |
| 38848 | CEFBS_HasNEON, // VPADALuv8i16 = 3128 |
| 38849 | CEFBS_HasNEON, // VPADALuv8i8 = 3129 |
| 38850 | CEFBS_HasNEON, // VPADDLsv16i8 = 3130 |
| 38851 | CEFBS_HasNEON, // VPADDLsv2i32 = 3131 |
| 38852 | CEFBS_HasNEON, // VPADDLsv4i16 = 3132 |
| 38853 | CEFBS_HasNEON, // VPADDLsv4i32 = 3133 |
| 38854 | CEFBS_HasNEON, // VPADDLsv8i16 = 3134 |
| 38855 | CEFBS_HasNEON, // VPADDLsv8i8 = 3135 |
| 38856 | CEFBS_HasNEON, // VPADDLuv16i8 = 3136 |
| 38857 | CEFBS_HasNEON, // VPADDLuv2i32 = 3137 |
| 38858 | CEFBS_HasNEON, // VPADDLuv4i16 = 3138 |
| 38859 | CEFBS_HasNEON, // VPADDLuv4i32 = 3139 |
| 38860 | CEFBS_HasNEON, // VPADDLuv8i16 = 3140 |
| 38861 | CEFBS_HasNEON, // VPADDLuv8i8 = 3141 |
| 38862 | CEFBS_HasNEON, // VPADDf = 3142 |
| 38863 | CEFBS_HasNEON_HasFullFP16, // VPADDh = 3143 |
| 38864 | CEFBS_HasNEON, // VPADDi16 = 3144 |
| 38865 | CEFBS_HasNEON, // VPADDi32 = 3145 |
| 38866 | CEFBS_HasNEON, // VPADDi8 = 3146 |
| 38867 | CEFBS_HasNEON, // VPMAXf = 3147 |
| 38868 | CEFBS_HasNEON_HasFullFP16, // VPMAXh = 3148 |
| 38869 | CEFBS_HasNEON, // VPMAXs16 = 3149 |
| 38870 | CEFBS_HasNEON, // VPMAXs32 = 3150 |
| 38871 | CEFBS_HasNEON, // VPMAXs8 = 3151 |
| 38872 | CEFBS_HasNEON, // VPMAXu16 = 3152 |
| 38873 | CEFBS_HasNEON, // VPMAXu32 = 3153 |
| 38874 | CEFBS_HasNEON, // VPMAXu8 = 3154 |
| 38875 | CEFBS_HasNEON, // VPMINf = 3155 |
| 38876 | CEFBS_HasNEON_HasFullFP16, // VPMINh = 3156 |
| 38877 | CEFBS_HasNEON, // VPMINs16 = 3157 |
| 38878 | CEFBS_HasNEON, // VPMINs32 = 3158 |
| 38879 | CEFBS_HasNEON, // VPMINs8 = 3159 |
| 38880 | CEFBS_HasNEON, // VPMINu16 = 3160 |
| 38881 | CEFBS_HasNEON, // VPMINu32 = 3161 |
| 38882 | CEFBS_HasNEON, // VPMINu8 = 3162 |
| 38883 | CEFBS_HasNEON, // VQABSv16i8 = 3163 |
| 38884 | CEFBS_HasNEON, // VQABSv2i32 = 3164 |
| 38885 | CEFBS_HasNEON, // VQABSv4i16 = 3165 |
| 38886 | CEFBS_HasNEON, // VQABSv4i32 = 3166 |
| 38887 | CEFBS_HasNEON, // VQABSv8i16 = 3167 |
| 38888 | CEFBS_HasNEON, // VQABSv8i8 = 3168 |
| 38889 | CEFBS_HasNEON, // VQADDsv16i8 = 3169 |
| 38890 | CEFBS_HasNEON, // VQADDsv1i64 = 3170 |
| 38891 | CEFBS_HasNEON, // VQADDsv2i32 = 3171 |
| 38892 | CEFBS_HasNEON, // VQADDsv2i64 = 3172 |
| 38893 | CEFBS_HasNEON, // VQADDsv4i16 = 3173 |
| 38894 | CEFBS_HasNEON, // VQADDsv4i32 = 3174 |
| 38895 | CEFBS_HasNEON, // VQADDsv8i16 = 3175 |
| 38896 | CEFBS_HasNEON, // VQADDsv8i8 = 3176 |
| 38897 | CEFBS_HasNEON, // VQADDuv16i8 = 3177 |
| 38898 | CEFBS_HasNEON, // VQADDuv1i64 = 3178 |
| 38899 | CEFBS_HasNEON, // VQADDuv2i32 = 3179 |
| 38900 | CEFBS_HasNEON, // VQADDuv2i64 = 3180 |
| 38901 | CEFBS_HasNEON, // VQADDuv4i16 = 3181 |
| 38902 | CEFBS_HasNEON, // VQADDuv4i32 = 3182 |
| 38903 | CEFBS_HasNEON, // VQADDuv8i16 = 3183 |
| 38904 | CEFBS_HasNEON, // VQADDuv8i8 = 3184 |
| 38905 | CEFBS_HasNEON, // VQDMLALslv2i32 = 3185 |
| 38906 | CEFBS_HasNEON, // VQDMLALslv4i16 = 3186 |
| 38907 | CEFBS_HasNEON, // VQDMLALv2i64 = 3187 |
| 38908 | CEFBS_HasNEON, // VQDMLALv4i32 = 3188 |
| 38909 | CEFBS_HasNEON, // VQDMLSLslv2i32 = 3189 |
| 38910 | CEFBS_HasNEON, // VQDMLSLslv4i16 = 3190 |
| 38911 | CEFBS_HasNEON, // VQDMLSLv2i64 = 3191 |
| 38912 | CEFBS_HasNEON, // VQDMLSLv4i32 = 3192 |
| 38913 | CEFBS_HasNEON, // VQDMULHslv2i32 = 3193 |
| 38914 | CEFBS_HasNEON, // VQDMULHslv4i16 = 3194 |
| 38915 | CEFBS_HasNEON, // VQDMULHslv4i32 = 3195 |
| 38916 | CEFBS_HasNEON, // VQDMULHslv8i16 = 3196 |
| 38917 | CEFBS_HasNEON, // VQDMULHv2i32 = 3197 |
| 38918 | CEFBS_HasNEON, // VQDMULHv4i16 = 3198 |
| 38919 | CEFBS_HasNEON, // VQDMULHv4i32 = 3199 |
| 38920 | CEFBS_HasNEON, // VQDMULHv8i16 = 3200 |
| 38921 | CEFBS_HasNEON, // VQDMULLslv2i32 = 3201 |
| 38922 | CEFBS_HasNEON, // VQDMULLslv4i16 = 3202 |
| 38923 | CEFBS_HasNEON, // VQDMULLv2i64 = 3203 |
| 38924 | CEFBS_HasNEON, // VQDMULLv4i32 = 3204 |
| 38925 | CEFBS_HasNEON, // VQMOVNsuv2i32 = 3205 |
| 38926 | CEFBS_HasNEON, // VQMOVNsuv4i16 = 3206 |
| 38927 | CEFBS_HasNEON, // VQMOVNsuv8i8 = 3207 |
| 38928 | CEFBS_HasNEON, // VQMOVNsv2i32 = 3208 |
| 38929 | CEFBS_HasNEON, // VQMOVNsv4i16 = 3209 |
| 38930 | CEFBS_HasNEON, // VQMOVNsv8i8 = 3210 |
| 38931 | CEFBS_HasNEON, // VQMOVNuv2i32 = 3211 |
| 38932 | CEFBS_HasNEON, // VQMOVNuv4i16 = 3212 |
| 38933 | CEFBS_HasNEON, // VQMOVNuv8i8 = 3213 |
| 38934 | CEFBS_HasNEON, // VQNEGv16i8 = 3214 |
| 38935 | CEFBS_HasNEON, // VQNEGv2i32 = 3215 |
| 38936 | CEFBS_HasNEON, // VQNEGv4i16 = 3216 |
| 38937 | CEFBS_HasNEON, // VQNEGv4i32 = 3217 |
| 38938 | CEFBS_HasNEON, // VQNEGv8i16 = 3218 |
| 38939 | CEFBS_HasNEON, // VQNEGv8i8 = 3219 |
| 38940 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv2i32 = 3220 |
| 38941 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv4i16 = 3221 |
| 38942 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv4i32 = 3222 |
| 38943 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv8i16 = 3223 |
| 38944 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv2i32 = 3224 |
| 38945 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv4i16 = 3225 |
| 38946 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv4i32 = 3226 |
| 38947 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv8i16 = 3227 |
| 38948 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv2i32 = 3228 |
| 38949 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv4i16 = 3229 |
| 38950 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv4i32 = 3230 |
| 38951 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv8i16 = 3231 |
| 38952 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv2i32 = 3232 |
| 38953 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv4i16 = 3233 |
| 38954 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv4i32 = 3234 |
| 38955 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv8i16 = 3235 |
| 38956 | CEFBS_HasNEON, // VQRDMULHslv2i32 = 3236 |
| 38957 | CEFBS_HasNEON, // VQRDMULHslv4i16 = 3237 |
| 38958 | CEFBS_HasNEON, // VQRDMULHslv4i32 = 3238 |
| 38959 | CEFBS_HasNEON, // VQRDMULHslv8i16 = 3239 |
| 38960 | CEFBS_HasNEON, // VQRDMULHv2i32 = 3240 |
| 38961 | CEFBS_HasNEON, // VQRDMULHv4i16 = 3241 |
| 38962 | CEFBS_HasNEON, // VQRDMULHv4i32 = 3242 |
| 38963 | CEFBS_HasNEON, // VQRDMULHv8i16 = 3243 |
| 38964 | CEFBS_HasNEON, // VQRSHLsv16i8 = 3244 |
| 38965 | CEFBS_HasNEON, // VQRSHLsv1i64 = 3245 |
| 38966 | CEFBS_HasNEON, // VQRSHLsv2i32 = 3246 |
| 38967 | CEFBS_HasNEON, // VQRSHLsv2i64 = 3247 |
| 38968 | CEFBS_HasNEON, // VQRSHLsv4i16 = 3248 |
| 38969 | CEFBS_HasNEON, // VQRSHLsv4i32 = 3249 |
| 38970 | CEFBS_HasNEON, // VQRSHLsv8i16 = 3250 |
| 38971 | CEFBS_HasNEON, // VQRSHLsv8i8 = 3251 |
| 38972 | CEFBS_HasNEON, // VQRSHLuv16i8 = 3252 |
| 38973 | CEFBS_HasNEON, // VQRSHLuv1i64 = 3253 |
| 38974 | CEFBS_HasNEON, // VQRSHLuv2i32 = 3254 |
| 38975 | CEFBS_HasNEON, // VQRSHLuv2i64 = 3255 |
| 38976 | CEFBS_HasNEON, // VQRSHLuv4i16 = 3256 |
| 38977 | CEFBS_HasNEON, // VQRSHLuv4i32 = 3257 |
| 38978 | CEFBS_HasNEON, // VQRSHLuv8i16 = 3258 |
| 38979 | CEFBS_HasNEON, // VQRSHLuv8i8 = 3259 |
| 38980 | CEFBS_HasNEON, // VQRSHRNsv2i32 = 3260 |
| 38981 | CEFBS_HasNEON, // VQRSHRNsv4i16 = 3261 |
| 38982 | CEFBS_HasNEON, // VQRSHRNsv8i8 = 3262 |
| 38983 | CEFBS_HasNEON, // VQRSHRNuv2i32 = 3263 |
| 38984 | CEFBS_HasNEON, // VQRSHRNuv4i16 = 3264 |
| 38985 | CEFBS_HasNEON, // VQRSHRNuv8i8 = 3265 |
| 38986 | CEFBS_HasNEON, // VQRSHRUNv2i32 = 3266 |
| 38987 | CEFBS_HasNEON, // VQRSHRUNv4i16 = 3267 |
| 38988 | CEFBS_HasNEON, // VQRSHRUNv8i8 = 3268 |
| 38989 | CEFBS_HasNEON, // VQSHLsiv16i8 = 3269 |
| 38990 | CEFBS_HasNEON, // VQSHLsiv1i64 = 3270 |
| 38991 | CEFBS_HasNEON, // VQSHLsiv2i32 = 3271 |
| 38992 | CEFBS_HasNEON, // VQSHLsiv2i64 = 3272 |
| 38993 | CEFBS_HasNEON, // VQSHLsiv4i16 = 3273 |
| 38994 | CEFBS_HasNEON, // VQSHLsiv4i32 = 3274 |
| 38995 | CEFBS_HasNEON, // VQSHLsiv8i16 = 3275 |
| 38996 | CEFBS_HasNEON, // VQSHLsiv8i8 = 3276 |
| 38997 | CEFBS_HasNEON, // VQSHLsuv16i8 = 3277 |
| 38998 | CEFBS_HasNEON, // VQSHLsuv1i64 = 3278 |
| 38999 | CEFBS_HasNEON, // VQSHLsuv2i32 = 3279 |
| 39000 | CEFBS_HasNEON, // VQSHLsuv2i64 = 3280 |
| 39001 | CEFBS_HasNEON, // VQSHLsuv4i16 = 3281 |
| 39002 | CEFBS_HasNEON, // VQSHLsuv4i32 = 3282 |
| 39003 | CEFBS_HasNEON, // VQSHLsuv8i16 = 3283 |
| 39004 | CEFBS_HasNEON, // VQSHLsuv8i8 = 3284 |
| 39005 | CEFBS_HasNEON, // VQSHLsv16i8 = 3285 |
| 39006 | CEFBS_HasNEON, // VQSHLsv1i64 = 3286 |
| 39007 | CEFBS_HasNEON, // VQSHLsv2i32 = 3287 |
| 39008 | CEFBS_HasNEON, // VQSHLsv2i64 = 3288 |
| 39009 | CEFBS_HasNEON, // VQSHLsv4i16 = 3289 |
| 39010 | CEFBS_HasNEON, // VQSHLsv4i32 = 3290 |
| 39011 | CEFBS_HasNEON, // VQSHLsv8i16 = 3291 |
| 39012 | CEFBS_HasNEON, // VQSHLsv8i8 = 3292 |
| 39013 | CEFBS_HasNEON, // VQSHLuiv16i8 = 3293 |
| 39014 | CEFBS_HasNEON, // VQSHLuiv1i64 = 3294 |
| 39015 | CEFBS_HasNEON, // VQSHLuiv2i32 = 3295 |
| 39016 | CEFBS_HasNEON, // VQSHLuiv2i64 = 3296 |
| 39017 | CEFBS_HasNEON, // VQSHLuiv4i16 = 3297 |
| 39018 | CEFBS_HasNEON, // VQSHLuiv4i32 = 3298 |
| 39019 | CEFBS_HasNEON, // VQSHLuiv8i16 = 3299 |
| 39020 | CEFBS_HasNEON, // VQSHLuiv8i8 = 3300 |
| 39021 | CEFBS_HasNEON, // VQSHLuv16i8 = 3301 |
| 39022 | CEFBS_HasNEON, // VQSHLuv1i64 = 3302 |
| 39023 | CEFBS_HasNEON, // VQSHLuv2i32 = 3303 |
| 39024 | CEFBS_HasNEON, // VQSHLuv2i64 = 3304 |
| 39025 | CEFBS_HasNEON, // VQSHLuv4i16 = 3305 |
| 39026 | CEFBS_HasNEON, // VQSHLuv4i32 = 3306 |
| 39027 | CEFBS_HasNEON, // VQSHLuv8i16 = 3307 |
| 39028 | CEFBS_HasNEON, // VQSHLuv8i8 = 3308 |
| 39029 | CEFBS_HasNEON, // VQSHRNsv2i32 = 3309 |
| 39030 | CEFBS_HasNEON, // VQSHRNsv4i16 = 3310 |
| 39031 | CEFBS_HasNEON, // VQSHRNsv8i8 = 3311 |
| 39032 | CEFBS_HasNEON, // VQSHRNuv2i32 = 3312 |
| 39033 | CEFBS_HasNEON, // VQSHRNuv4i16 = 3313 |
| 39034 | CEFBS_HasNEON, // VQSHRNuv8i8 = 3314 |
| 39035 | CEFBS_HasNEON, // VQSHRUNv2i32 = 3315 |
| 39036 | CEFBS_HasNEON, // VQSHRUNv4i16 = 3316 |
| 39037 | CEFBS_HasNEON, // VQSHRUNv8i8 = 3317 |
| 39038 | CEFBS_HasNEON, // VQSUBsv16i8 = 3318 |
| 39039 | CEFBS_HasNEON, // VQSUBsv1i64 = 3319 |
| 39040 | CEFBS_HasNEON, // VQSUBsv2i32 = 3320 |
| 39041 | CEFBS_HasNEON, // VQSUBsv2i64 = 3321 |
| 39042 | CEFBS_HasNEON, // VQSUBsv4i16 = 3322 |
| 39043 | CEFBS_HasNEON, // VQSUBsv4i32 = 3323 |
| 39044 | CEFBS_HasNEON, // VQSUBsv8i16 = 3324 |
| 39045 | CEFBS_HasNEON, // VQSUBsv8i8 = 3325 |
| 39046 | CEFBS_HasNEON, // VQSUBuv16i8 = 3326 |
| 39047 | CEFBS_HasNEON, // VQSUBuv1i64 = 3327 |
| 39048 | CEFBS_HasNEON, // VQSUBuv2i32 = 3328 |
| 39049 | CEFBS_HasNEON, // VQSUBuv2i64 = 3329 |
| 39050 | CEFBS_HasNEON, // VQSUBuv4i16 = 3330 |
| 39051 | CEFBS_HasNEON, // VQSUBuv4i32 = 3331 |
| 39052 | CEFBS_HasNEON, // VQSUBuv8i16 = 3332 |
| 39053 | CEFBS_HasNEON, // VQSUBuv8i8 = 3333 |
| 39054 | CEFBS_HasNEON, // VRADDHNv2i32 = 3334 |
| 39055 | CEFBS_HasNEON, // VRADDHNv4i16 = 3335 |
| 39056 | CEFBS_HasNEON, // VRADDHNv8i8 = 3336 |
| 39057 | CEFBS_HasNEON, // VRECPEd = 3337 |
| 39058 | CEFBS_HasNEON, // VRECPEfd = 3338 |
| 39059 | CEFBS_HasNEON, // VRECPEfq = 3339 |
| 39060 | CEFBS_HasNEON_HasFullFP16, // VRECPEhd = 3340 |
| 39061 | CEFBS_HasNEON_HasFullFP16, // VRECPEhq = 3341 |
| 39062 | CEFBS_HasNEON, // VRECPEq = 3342 |
| 39063 | CEFBS_HasNEON, // VRECPSfd = 3343 |
| 39064 | CEFBS_HasNEON, // VRECPSfq = 3344 |
| 39065 | CEFBS_HasNEON_HasFullFP16, // VRECPShd = 3345 |
| 39066 | CEFBS_HasNEON_HasFullFP16, // VRECPShq = 3346 |
| 39067 | CEFBS_HasNEON, // VREV16d8 = 3347 |
| 39068 | CEFBS_HasNEON, // VREV16q8 = 3348 |
| 39069 | CEFBS_HasNEON, // VREV32d16 = 3349 |
| 39070 | CEFBS_HasNEON, // VREV32d8 = 3350 |
| 39071 | CEFBS_HasNEON, // VREV32q16 = 3351 |
| 39072 | CEFBS_HasNEON, // VREV32q8 = 3352 |
| 39073 | CEFBS_HasNEON, // VREV64d16 = 3353 |
| 39074 | CEFBS_HasNEON, // VREV64d32 = 3354 |
| 39075 | CEFBS_HasNEON, // VREV64d8 = 3355 |
| 39076 | CEFBS_HasNEON, // VREV64q16 = 3356 |
| 39077 | CEFBS_HasNEON, // VREV64q32 = 3357 |
| 39078 | CEFBS_HasNEON, // VREV64q8 = 3358 |
| 39079 | CEFBS_HasNEON, // VRHADDsv16i8 = 3359 |
| 39080 | CEFBS_HasNEON, // VRHADDsv2i32 = 3360 |
| 39081 | CEFBS_HasNEON, // VRHADDsv4i16 = 3361 |
| 39082 | CEFBS_HasNEON, // VRHADDsv4i32 = 3362 |
| 39083 | CEFBS_HasNEON, // VRHADDsv8i16 = 3363 |
| 39084 | CEFBS_HasNEON, // VRHADDsv8i8 = 3364 |
| 39085 | CEFBS_HasNEON, // VRHADDuv16i8 = 3365 |
| 39086 | CEFBS_HasNEON, // VRHADDuv2i32 = 3366 |
| 39087 | CEFBS_HasNEON, // VRHADDuv4i16 = 3367 |
| 39088 | CEFBS_HasNEON, // VRHADDuv4i32 = 3368 |
| 39089 | CEFBS_HasNEON, // VRHADDuv8i16 = 3369 |
| 39090 | CEFBS_HasNEON, // VRHADDuv8i8 = 3370 |
| 39091 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTAD = 3371 |
| 39092 | CEFBS_HasFullFP16, // VRINTAH = 3372 |
| 39093 | CEFBS_HasV8_HasNEON, // VRINTANDf = 3373 |
| 39094 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTANDh = 3374 |
| 39095 | CEFBS_HasV8_HasNEON, // VRINTANQf = 3375 |
| 39096 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTANQh = 3376 |
| 39097 | CEFBS_HasFPARMv8, // VRINTAS = 3377 |
| 39098 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTMD = 3378 |
| 39099 | CEFBS_HasFullFP16, // VRINTMH = 3379 |
| 39100 | CEFBS_HasV8_HasNEON, // VRINTMNDf = 3380 |
| 39101 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTMNDh = 3381 |
| 39102 | CEFBS_HasV8_HasNEON, // VRINTMNQf = 3382 |
| 39103 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTMNQh = 3383 |
| 39104 | CEFBS_HasFPARMv8, // VRINTMS = 3384 |
| 39105 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTND = 3385 |
| 39106 | CEFBS_HasFullFP16, // VRINTNH = 3386 |
| 39107 | CEFBS_HasV8_HasNEON, // VRINTNNDf = 3387 |
| 39108 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTNNDh = 3388 |
| 39109 | CEFBS_HasV8_HasNEON, // VRINTNNQf = 3389 |
| 39110 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTNNQh = 3390 |
| 39111 | CEFBS_HasFPARMv8, // VRINTNS = 3391 |
| 39112 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTPD = 3392 |
| 39113 | CEFBS_HasFullFP16, // VRINTPH = 3393 |
| 39114 | CEFBS_HasV8_HasNEON, // VRINTPNDf = 3394 |
| 39115 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTPNDh = 3395 |
| 39116 | CEFBS_HasV8_HasNEON, // VRINTPNQf = 3396 |
| 39117 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTPNQh = 3397 |
| 39118 | CEFBS_HasFPARMv8, // VRINTPS = 3398 |
| 39119 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTRD = 3399 |
| 39120 | CEFBS_HasFullFP16, // VRINTRH = 3400 |
| 39121 | CEFBS_HasFPARMv8, // VRINTRS = 3401 |
| 39122 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTXD = 3402 |
| 39123 | CEFBS_HasFullFP16, // VRINTXH = 3403 |
| 39124 | CEFBS_HasV8_HasNEON, // VRINTXNDf = 3404 |
| 39125 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTXNDh = 3405 |
| 39126 | CEFBS_HasV8_HasNEON, // VRINTXNQf = 3406 |
| 39127 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTXNQh = 3407 |
| 39128 | CEFBS_HasFPARMv8, // VRINTXS = 3408 |
| 39129 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTZD = 3409 |
| 39130 | CEFBS_HasFullFP16, // VRINTZH = 3410 |
| 39131 | CEFBS_HasV8_HasNEON, // VRINTZNDf = 3411 |
| 39132 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTZNDh = 3412 |
| 39133 | CEFBS_HasV8_HasNEON, // VRINTZNQf = 3413 |
| 39134 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTZNQh = 3414 |
| 39135 | CEFBS_HasFPARMv8, // VRINTZS = 3415 |
| 39136 | CEFBS_HasNEON, // VRSHLsv16i8 = 3416 |
| 39137 | CEFBS_HasNEON, // VRSHLsv1i64 = 3417 |
| 39138 | CEFBS_HasNEON, // VRSHLsv2i32 = 3418 |
| 39139 | CEFBS_HasNEON, // VRSHLsv2i64 = 3419 |
| 39140 | CEFBS_HasNEON, // VRSHLsv4i16 = 3420 |
| 39141 | CEFBS_HasNEON, // VRSHLsv4i32 = 3421 |
| 39142 | CEFBS_HasNEON, // VRSHLsv8i16 = 3422 |
| 39143 | CEFBS_HasNEON, // VRSHLsv8i8 = 3423 |
| 39144 | CEFBS_HasNEON, // VRSHLuv16i8 = 3424 |
| 39145 | CEFBS_HasNEON, // VRSHLuv1i64 = 3425 |
| 39146 | CEFBS_HasNEON, // VRSHLuv2i32 = 3426 |
| 39147 | CEFBS_HasNEON, // VRSHLuv2i64 = 3427 |
| 39148 | CEFBS_HasNEON, // VRSHLuv4i16 = 3428 |
| 39149 | CEFBS_HasNEON, // VRSHLuv4i32 = 3429 |
| 39150 | CEFBS_HasNEON, // VRSHLuv8i16 = 3430 |
| 39151 | CEFBS_HasNEON, // VRSHLuv8i8 = 3431 |
| 39152 | CEFBS_HasNEON, // VRSHRNv2i32 = 3432 |
| 39153 | CEFBS_HasNEON, // VRSHRNv4i16 = 3433 |
| 39154 | CEFBS_HasNEON, // VRSHRNv8i8 = 3434 |
| 39155 | CEFBS_HasNEON, // VRSHRsv16i8 = 3435 |
| 39156 | CEFBS_HasNEON, // VRSHRsv1i64 = 3436 |
| 39157 | CEFBS_HasNEON, // VRSHRsv2i32 = 3437 |
| 39158 | CEFBS_HasNEON, // VRSHRsv2i64 = 3438 |
| 39159 | CEFBS_HasNEON, // VRSHRsv4i16 = 3439 |
| 39160 | CEFBS_HasNEON, // VRSHRsv4i32 = 3440 |
| 39161 | CEFBS_HasNEON, // VRSHRsv8i16 = 3441 |
| 39162 | CEFBS_HasNEON, // VRSHRsv8i8 = 3442 |
| 39163 | CEFBS_HasNEON, // VRSHRuv16i8 = 3443 |
| 39164 | CEFBS_HasNEON, // VRSHRuv1i64 = 3444 |
| 39165 | CEFBS_HasNEON, // VRSHRuv2i32 = 3445 |
| 39166 | CEFBS_HasNEON, // VRSHRuv2i64 = 3446 |
| 39167 | CEFBS_HasNEON, // VRSHRuv4i16 = 3447 |
| 39168 | CEFBS_HasNEON, // VRSHRuv4i32 = 3448 |
| 39169 | CEFBS_HasNEON, // VRSHRuv8i16 = 3449 |
| 39170 | CEFBS_HasNEON, // VRSHRuv8i8 = 3450 |
| 39171 | CEFBS_HasNEON, // VRSQRTEd = 3451 |
| 39172 | CEFBS_HasNEON, // VRSQRTEfd = 3452 |
| 39173 | CEFBS_HasNEON, // VRSQRTEfq = 3453 |
| 39174 | CEFBS_HasNEON_HasFullFP16, // VRSQRTEhd = 3454 |
| 39175 | CEFBS_HasNEON_HasFullFP16, // VRSQRTEhq = 3455 |
| 39176 | CEFBS_HasNEON, // VRSQRTEq = 3456 |
| 39177 | CEFBS_HasNEON, // VRSQRTSfd = 3457 |
| 39178 | CEFBS_HasNEON, // VRSQRTSfq = 3458 |
| 39179 | CEFBS_HasNEON_HasFullFP16, // VRSQRTShd = 3459 |
| 39180 | CEFBS_HasNEON_HasFullFP16, // VRSQRTShq = 3460 |
| 39181 | CEFBS_HasNEON, // VRSRAsv16i8 = 3461 |
| 39182 | CEFBS_HasNEON, // VRSRAsv1i64 = 3462 |
| 39183 | CEFBS_HasNEON, // VRSRAsv2i32 = 3463 |
| 39184 | CEFBS_HasNEON, // VRSRAsv2i64 = 3464 |
| 39185 | CEFBS_HasNEON, // VRSRAsv4i16 = 3465 |
| 39186 | CEFBS_HasNEON, // VRSRAsv4i32 = 3466 |
| 39187 | CEFBS_HasNEON, // VRSRAsv8i16 = 3467 |
| 39188 | CEFBS_HasNEON, // VRSRAsv8i8 = 3468 |
| 39189 | CEFBS_HasNEON, // VRSRAuv16i8 = 3469 |
| 39190 | CEFBS_HasNEON, // VRSRAuv1i64 = 3470 |
| 39191 | CEFBS_HasNEON, // VRSRAuv2i32 = 3471 |
| 39192 | CEFBS_HasNEON, // VRSRAuv2i64 = 3472 |
| 39193 | CEFBS_HasNEON, // VRSRAuv4i16 = 3473 |
| 39194 | CEFBS_HasNEON, // VRSRAuv4i32 = 3474 |
| 39195 | CEFBS_HasNEON, // VRSRAuv8i16 = 3475 |
| 39196 | CEFBS_HasNEON, // VRSRAuv8i8 = 3476 |
| 39197 | CEFBS_HasNEON, // VRSUBHNv2i32 = 3477 |
| 39198 | CEFBS_HasNEON, // VRSUBHNv4i16 = 3478 |
| 39199 | CEFBS_HasNEON, // VRSUBHNv8i8 = 3479 |
| 39200 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSCCLRMD = 3480 |
| 39201 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSCCLRMS = 3481 |
| 39202 | CEFBS_HasDotProd, // VSDOTD = 3482 |
| 39203 | CEFBS_HasDotProd, // VSDOTDI = 3483 |
| 39204 | CEFBS_HasDotProd, // VSDOTQ = 3484 |
| 39205 | CEFBS_HasDotProd, // VSDOTQI = 3485 |
| 39206 | CEFBS_HasFPARMv8_HasDPVFP, // VSELEQD = 3486 |
| 39207 | CEFBS_HasFullFP16, // VSELEQH = 3487 |
| 39208 | CEFBS_HasFPARMv8, // VSELEQS = 3488 |
| 39209 | CEFBS_HasFPARMv8_HasDPVFP, // VSELGED = 3489 |
| 39210 | CEFBS_HasFullFP16, // VSELGEH = 3490 |
| 39211 | CEFBS_HasFPARMv8, // VSELGES = 3491 |
| 39212 | CEFBS_HasFPARMv8_HasDPVFP, // VSELGTD = 3492 |
| 39213 | CEFBS_HasFullFP16, // VSELGTH = 3493 |
| 39214 | CEFBS_HasFPARMv8, // VSELGTS = 3494 |
| 39215 | CEFBS_HasFPARMv8_HasDPVFP, // VSELVSD = 3495 |
| 39216 | CEFBS_HasFullFP16, // VSELVSH = 3496 |
| 39217 | CEFBS_HasFPARMv8, // VSELVSS = 3497 |
| 39218 | CEFBS_HasNEON, // VSETLNi16 = 3498 |
| 39219 | CEFBS_HasVFP2, // VSETLNi32 = 3499 |
| 39220 | CEFBS_HasNEON, // VSETLNi8 = 3500 |
| 39221 | CEFBS_HasNEON, // VSHLLi16 = 3501 |
| 39222 | CEFBS_HasNEON, // VSHLLi32 = 3502 |
| 39223 | CEFBS_HasNEON, // VSHLLi8 = 3503 |
| 39224 | CEFBS_HasNEON, // VSHLLsv2i64 = 3504 |
| 39225 | CEFBS_HasNEON, // VSHLLsv4i32 = 3505 |
| 39226 | CEFBS_HasNEON, // VSHLLsv8i16 = 3506 |
| 39227 | CEFBS_HasNEON, // VSHLLuv2i64 = 3507 |
| 39228 | CEFBS_HasNEON, // VSHLLuv4i32 = 3508 |
| 39229 | CEFBS_HasNEON, // VSHLLuv8i16 = 3509 |
| 39230 | CEFBS_HasNEON, // VSHLiv16i8 = 3510 |
| 39231 | CEFBS_HasNEON, // VSHLiv1i64 = 3511 |
| 39232 | CEFBS_HasNEON, // VSHLiv2i32 = 3512 |
| 39233 | CEFBS_HasNEON, // VSHLiv2i64 = 3513 |
| 39234 | CEFBS_HasNEON, // VSHLiv4i16 = 3514 |
| 39235 | CEFBS_HasNEON, // VSHLiv4i32 = 3515 |
| 39236 | CEFBS_HasNEON, // VSHLiv8i16 = 3516 |
| 39237 | CEFBS_HasNEON, // VSHLiv8i8 = 3517 |
| 39238 | CEFBS_HasNEON, // VSHLsv16i8 = 3518 |
| 39239 | CEFBS_HasNEON, // VSHLsv1i64 = 3519 |
| 39240 | CEFBS_HasNEON, // VSHLsv2i32 = 3520 |
| 39241 | CEFBS_HasNEON, // VSHLsv2i64 = 3521 |
| 39242 | CEFBS_HasNEON, // VSHLsv4i16 = 3522 |
| 39243 | CEFBS_HasNEON, // VSHLsv4i32 = 3523 |
| 39244 | CEFBS_HasNEON, // VSHLsv8i16 = 3524 |
| 39245 | CEFBS_HasNEON, // VSHLsv8i8 = 3525 |
| 39246 | CEFBS_HasNEON, // VSHLuv16i8 = 3526 |
| 39247 | CEFBS_HasNEON, // VSHLuv1i64 = 3527 |
| 39248 | CEFBS_HasNEON, // VSHLuv2i32 = 3528 |
| 39249 | CEFBS_HasNEON, // VSHLuv2i64 = 3529 |
| 39250 | CEFBS_HasNEON, // VSHLuv4i16 = 3530 |
| 39251 | CEFBS_HasNEON, // VSHLuv4i32 = 3531 |
| 39252 | CEFBS_HasNEON, // VSHLuv8i16 = 3532 |
| 39253 | CEFBS_HasNEON, // VSHLuv8i8 = 3533 |
| 39254 | CEFBS_HasNEON, // VSHRNv2i32 = 3534 |
| 39255 | CEFBS_HasNEON, // VSHRNv4i16 = 3535 |
| 39256 | CEFBS_HasNEON, // VSHRNv8i8 = 3536 |
| 39257 | CEFBS_HasNEON, // VSHRsv16i8 = 3537 |
| 39258 | CEFBS_HasNEON, // VSHRsv1i64 = 3538 |
| 39259 | CEFBS_HasNEON, // VSHRsv2i32 = 3539 |
| 39260 | CEFBS_HasNEON, // VSHRsv2i64 = 3540 |
| 39261 | CEFBS_HasNEON, // VSHRsv4i16 = 3541 |
| 39262 | CEFBS_HasNEON, // VSHRsv4i32 = 3542 |
| 39263 | CEFBS_HasNEON, // VSHRsv8i16 = 3543 |
| 39264 | CEFBS_HasNEON, // VSHRsv8i8 = 3544 |
| 39265 | CEFBS_HasNEON, // VSHRuv16i8 = 3545 |
| 39266 | CEFBS_HasNEON, // VSHRuv1i64 = 3546 |
| 39267 | CEFBS_HasNEON, // VSHRuv2i32 = 3547 |
| 39268 | CEFBS_HasNEON, // VSHRuv2i64 = 3548 |
| 39269 | CEFBS_HasNEON, // VSHRuv4i16 = 3549 |
| 39270 | CEFBS_HasNEON, // VSHRuv4i32 = 3550 |
| 39271 | CEFBS_HasNEON, // VSHRuv8i16 = 3551 |
| 39272 | CEFBS_HasNEON, // VSHRuv8i8 = 3552 |
| 39273 | CEFBS_HasVFP2_HasDPVFP, // VSHTOD = 3553 |
| 39274 | CEFBS_HasFullFP16, // VSHTOH = 3554 |
| 39275 | CEFBS_HasVFP2, // VSHTOS = 3555 |
| 39276 | CEFBS_HasVFP2_HasDPVFP, // VSITOD = 3556 |
| 39277 | CEFBS_HasFullFP16, // VSITOH = 3557 |
| 39278 | CEFBS_HasVFP2, // VSITOS = 3558 |
| 39279 | CEFBS_HasNEON, // VSLIv16i8 = 3559 |
| 39280 | CEFBS_HasNEON, // VSLIv1i64 = 3560 |
| 39281 | CEFBS_HasNEON, // VSLIv2i32 = 3561 |
| 39282 | CEFBS_HasNEON, // VSLIv2i64 = 3562 |
| 39283 | CEFBS_HasNEON, // VSLIv4i16 = 3563 |
| 39284 | CEFBS_HasNEON, // VSLIv4i32 = 3564 |
| 39285 | CEFBS_HasNEON, // VSLIv8i16 = 3565 |
| 39286 | CEFBS_HasNEON, // VSLIv8i8 = 3566 |
| 39287 | CEFBS_HasVFP2_HasDPVFP, // VSLTOD = 3567 |
| 39288 | CEFBS_HasFullFP16, // VSLTOH = 3568 |
| 39289 | CEFBS_HasVFP2, // VSLTOS = 3569 |
| 39290 | CEFBS_HasMatMulInt8, // VSMMLA = 3570 |
| 39291 | CEFBS_HasVFP2_HasDPVFP, // VSQRTD = 3571 |
| 39292 | CEFBS_HasFullFP16, // VSQRTH = 3572 |
| 39293 | CEFBS_HasVFP2, // VSQRTS = 3573 |
| 39294 | CEFBS_HasNEON, // VSRAsv16i8 = 3574 |
| 39295 | CEFBS_HasNEON, // VSRAsv1i64 = 3575 |
| 39296 | CEFBS_HasNEON, // VSRAsv2i32 = 3576 |
| 39297 | CEFBS_HasNEON, // VSRAsv2i64 = 3577 |
| 39298 | CEFBS_HasNEON, // VSRAsv4i16 = 3578 |
| 39299 | CEFBS_HasNEON, // VSRAsv4i32 = 3579 |
| 39300 | CEFBS_HasNEON, // VSRAsv8i16 = 3580 |
| 39301 | CEFBS_HasNEON, // VSRAsv8i8 = 3581 |
| 39302 | CEFBS_HasNEON, // VSRAuv16i8 = 3582 |
| 39303 | CEFBS_HasNEON, // VSRAuv1i64 = 3583 |
| 39304 | CEFBS_HasNEON, // VSRAuv2i32 = 3584 |
| 39305 | CEFBS_HasNEON, // VSRAuv2i64 = 3585 |
| 39306 | CEFBS_HasNEON, // VSRAuv4i16 = 3586 |
| 39307 | CEFBS_HasNEON, // VSRAuv4i32 = 3587 |
| 39308 | CEFBS_HasNEON, // VSRAuv8i16 = 3588 |
| 39309 | CEFBS_HasNEON, // VSRAuv8i8 = 3589 |
| 39310 | CEFBS_HasNEON, // VSRIv16i8 = 3590 |
| 39311 | CEFBS_HasNEON, // VSRIv1i64 = 3591 |
| 39312 | CEFBS_HasNEON, // VSRIv2i32 = 3592 |
| 39313 | CEFBS_HasNEON, // VSRIv2i64 = 3593 |
| 39314 | CEFBS_HasNEON, // VSRIv4i16 = 3594 |
| 39315 | CEFBS_HasNEON, // VSRIv4i32 = 3595 |
| 39316 | CEFBS_HasNEON, // VSRIv8i16 = 3596 |
| 39317 | CEFBS_HasNEON, // VSRIv8i8 = 3597 |
| 39318 | CEFBS_HasNEON, // VST1LNd16 = 3598 |
| 39319 | CEFBS_HasNEON, // VST1LNd16_UPD = 3599 |
| 39320 | CEFBS_HasNEON, // VST1LNd32 = 3600 |
| 39321 | CEFBS_HasNEON, // VST1LNd32_UPD = 3601 |
| 39322 | CEFBS_HasNEON, // VST1LNd8 = 3602 |
| 39323 | CEFBS_HasNEON, // VST1LNd8_UPD = 3603 |
| 39324 | CEFBS_HasNEON, // VST1LNq16Pseudo = 3604 |
| 39325 | CEFBS_HasNEON, // VST1LNq16Pseudo_UPD = 3605 |
| 39326 | CEFBS_HasNEON, // VST1LNq32Pseudo = 3606 |
| 39327 | CEFBS_HasNEON, // VST1LNq32Pseudo_UPD = 3607 |
| 39328 | CEFBS_HasNEON, // VST1LNq8Pseudo = 3608 |
| 39329 | CEFBS_HasNEON, // VST1LNq8Pseudo_UPD = 3609 |
| 39330 | CEFBS_HasNEON, // VST1d16 = 3610 |
| 39331 | CEFBS_HasNEON, // VST1d16Q = 3611 |
| 39332 | CEFBS_HasNEON, // VST1d16QPseudo = 3612 |
| 39333 | CEFBS_HasNEON, // VST1d16QPseudoWB_fixed = 3613 |
| 39334 | CEFBS_HasNEON, // VST1d16QPseudoWB_register = 3614 |
| 39335 | CEFBS_HasNEON, // VST1d16Qwb_fixed = 3615 |
| 39336 | CEFBS_HasNEON, // VST1d16Qwb_register = 3616 |
| 39337 | CEFBS_HasNEON, // VST1d16T = 3617 |
| 39338 | CEFBS_HasNEON, // VST1d16TPseudo = 3618 |
| 39339 | CEFBS_HasNEON, // VST1d16TPseudoWB_fixed = 3619 |
| 39340 | CEFBS_HasNEON, // VST1d16TPseudoWB_register = 3620 |
| 39341 | CEFBS_HasNEON, // VST1d16Twb_fixed = 3621 |
| 39342 | CEFBS_HasNEON, // VST1d16Twb_register = 3622 |
| 39343 | CEFBS_HasNEON, // VST1d16wb_fixed = 3623 |
| 39344 | CEFBS_HasNEON, // VST1d16wb_register = 3624 |
| 39345 | CEFBS_HasNEON, // VST1d32 = 3625 |
| 39346 | CEFBS_HasNEON, // VST1d32Q = 3626 |
| 39347 | CEFBS_HasNEON, // VST1d32QPseudo = 3627 |
| 39348 | CEFBS_HasNEON, // VST1d32QPseudoWB_fixed = 3628 |
| 39349 | CEFBS_HasNEON, // VST1d32QPseudoWB_register = 3629 |
| 39350 | CEFBS_HasNEON, // VST1d32Qwb_fixed = 3630 |
| 39351 | CEFBS_HasNEON, // VST1d32Qwb_register = 3631 |
| 39352 | CEFBS_HasNEON, // VST1d32T = 3632 |
| 39353 | CEFBS_HasNEON, // VST1d32TPseudo = 3633 |
| 39354 | CEFBS_HasNEON, // VST1d32TPseudoWB_fixed = 3634 |
| 39355 | CEFBS_HasNEON, // VST1d32TPseudoWB_register = 3635 |
| 39356 | CEFBS_HasNEON, // VST1d32Twb_fixed = 3636 |
| 39357 | CEFBS_HasNEON, // VST1d32Twb_register = 3637 |
| 39358 | CEFBS_HasNEON, // VST1d32wb_fixed = 3638 |
| 39359 | CEFBS_HasNEON, // VST1d32wb_register = 3639 |
| 39360 | CEFBS_HasNEON, // VST1d64 = 3640 |
| 39361 | CEFBS_HasNEON, // VST1d64Q = 3641 |
| 39362 | CEFBS_HasNEON, // VST1d64QPseudo = 3642 |
| 39363 | CEFBS_HasNEON, // VST1d64QPseudoWB_fixed = 3643 |
| 39364 | CEFBS_HasNEON, // VST1d64QPseudoWB_register = 3644 |
| 39365 | CEFBS_HasNEON, // VST1d64Qwb_fixed = 3645 |
| 39366 | CEFBS_HasNEON, // VST1d64Qwb_register = 3646 |
| 39367 | CEFBS_HasNEON, // VST1d64T = 3647 |
| 39368 | CEFBS_HasNEON, // VST1d64TPseudo = 3648 |
| 39369 | CEFBS_HasNEON, // VST1d64TPseudoWB_fixed = 3649 |
| 39370 | CEFBS_HasNEON, // VST1d64TPseudoWB_register = 3650 |
| 39371 | CEFBS_HasNEON, // VST1d64Twb_fixed = 3651 |
| 39372 | CEFBS_HasNEON, // VST1d64Twb_register = 3652 |
| 39373 | CEFBS_HasNEON, // VST1d64wb_fixed = 3653 |
| 39374 | CEFBS_HasNEON, // VST1d64wb_register = 3654 |
| 39375 | CEFBS_HasNEON, // VST1d8 = 3655 |
| 39376 | CEFBS_HasNEON, // VST1d8Q = 3656 |
| 39377 | CEFBS_HasNEON, // VST1d8QPseudo = 3657 |
| 39378 | CEFBS_HasNEON, // VST1d8QPseudoWB_fixed = 3658 |
| 39379 | CEFBS_HasNEON, // VST1d8QPseudoWB_register = 3659 |
| 39380 | CEFBS_HasNEON, // VST1d8Qwb_fixed = 3660 |
| 39381 | CEFBS_HasNEON, // VST1d8Qwb_register = 3661 |
| 39382 | CEFBS_HasNEON, // VST1d8T = 3662 |
| 39383 | CEFBS_HasNEON, // VST1d8TPseudo = 3663 |
| 39384 | CEFBS_HasNEON, // VST1d8TPseudoWB_fixed = 3664 |
| 39385 | CEFBS_HasNEON, // VST1d8TPseudoWB_register = 3665 |
| 39386 | CEFBS_HasNEON, // VST1d8Twb_fixed = 3666 |
| 39387 | CEFBS_HasNEON, // VST1d8Twb_register = 3667 |
| 39388 | CEFBS_HasNEON, // VST1d8wb_fixed = 3668 |
| 39389 | CEFBS_HasNEON, // VST1d8wb_register = 3669 |
| 39390 | CEFBS_HasNEON, // VST1q16 = 3670 |
| 39391 | CEFBS_HasNEON, // VST1q16HighQPseudo = 3671 |
| 39392 | CEFBS_HasNEON, // VST1q16HighQPseudo_UPD = 3672 |
| 39393 | CEFBS_HasNEON, // VST1q16HighTPseudo = 3673 |
| 39394 | CEFBS_HasNEON, // VST1q16HighTPseudo_UPD = 3674 |
| 39395 | CEFBS_HasNEON, // VST1q16LowQPseudo_UPD = 3675 |
| 39396 | CEFBS_HasNEON, // VST1q16LowTPseudo_UPD = 3676 |
| 39397 | CEFBS_HasNEON, // VST1q16wb_fixed = 3677 |
| 39398 | CEFBS_HasNEON, // VST1q16wb_register = 3678 |
| 39399 | CEFBS_HasNEON, // VST1q32 = 3679 |
| 39400 | CEFBS_HasNEON, // VST1q32HighQPseudo = 3680 |
| 39401 | CEFBS_HasNEON, // VST1q32HighQPseudo_UPD = 3681 |
| 39402 | CEFBS_HasNEON, // VST1q32HighTPseudo = 3682 |
| 39403 | CEFBS_HasNEON, // VST1q32HighTPseudo_UPD = 3683 |
| 39404 | CEFBS_HasNEON, // VST1q32LowQPseudo_UPD = 3684 |
| 39405 | CEFBS_HasNEON, // VST1q32LowTPseudo_UPD = 3685 |
| 39406 | CEFBS_HasNEON, // VST1q32wb_fixed = 3686 |
| 39407 | CEFBS_HasNEON, // VST1q32wb_register = 3687 |
| 39408 | CEFBS_HasNEON, // VST1q64 = 3688 |
| 39409 | CEFBS_HasNEON, // VST1q64HighQPseudo = 3689 |
| 39410 | CEFBS_HasNEON, // VST1q64HighQPseudo_UPD = 3690 |
| 39411 | CEFBS_HasNEON, // VST1q64HighTPseudo = 3691 |
| 39412 | CEFBS_HasNEON, // VST1q64HighTPseudo_UPD = 3692 |
| 39413 | CEFBS_HasNEON, // VST1q64LowQPseudo_UPD = 3693 |
| 39414 | CEFBS_HasNEON, // VST1q64LowTPseudo_UPD = 3694 |
| 39415 | CEFBS_HasNEON, // VST1q64wb_fixed = 3695 |
| 39416 | CEFBS_HasNEON, // VST1q64wb_register = 3696 |
| 39417 | CEFBS_HasNEON, // VST1q8 = 3697 |
| 39418 | CEFBS_HasNEON, // VST1q8HighQPseudo = 3698 |
| 39419 | CEFBS_HasNEON, // VST1q8HighQPseudo_UPD = 3699 |
| 39420 | CEFBS_HasNEON, // VST1q8HighTPseudo = 3700 |
| 39421 | CEFBS_HasNEON, // VST1q8HighTPseudo_UPD = 3701 |
| 39422 | CEFBS_HasNEON, // VST1q8LowQPseudo_UPD = 3702 |
| 39423 | CEFBS_HasNEON, // VST1q8LowTPseudo_UPD = 3703 |
| 39424 | CEFBS_HasNEON, // VST1q8wb_fixed = 3704 |
| 39425 | CEFBS_HasNEON, // VST1q8wb_register = 3705 |
| 39426 | CEFBS_HasNEON, // VST2LNd16 = 3706 |
| 39427 | CEFBS_HasNEON, // VST2LNd16Pseudo = 3707 |
| 39428 | CEFBS_HasNEON, // VST2LNd16Pseudo_UPD = 3708 |
| 39429 | CEFBS_HasNEON, // VST2LNd16_UPD = 3709 |
| 39430 | CEFBS_HasNEON, // VST2LNd32 = 3710 |
| 39431 | CEFBS_HasNEON, // VST2LNd32Pseudo = 3711 |
| 39432 | CEFBS_HasNEON, // VST2LNd32Pseudo_UPD = 3712 |
| 39433 | CEFBS_HasNEON, // VST2LNd32_UPD = 3713 |
| 39434 | CEFBS_HasNEON, // VST2LNd8 = 3714 |
| 39435 | CEFBS_HasNEON, // VST2LNd8Pseudo = 3715 |
| 39436 | CEFBS_HasNEON, // VST2LNd8Pseudo_UPD = 3716 |
| 39437 | CEFBS_HasNEON, // VST2LNd8_UPD = 3717 |
| 39438 | CEFBS_HasNEON, // VST2LNq16 = 3718 |
| 39439 | CEFBS_HasNEON, // VST2LNq16Pseudo = 3719 |
| 39440 | CEFBS_HasNEON, // VST2LNq16Pseudo_UPD = 3720 |
| 39441 | CEFBS_HasNEON, // VST2LNq16_UPD = 3721 |
| 39442 | CEFBS_HasNEON, // VST2LNq32 = 3722 |
| 39443 | CEFBS_HasNEON, // VST2LNq32Pseudo = 3723 |
| 39444 | CEFBS_HasNEON, // VST2LNq32Pseudo_UPD = 3724 |
| 39445 | CEFBS_HasNEON, // VST2LNq32_UPD = 3725 |
| 39446 | CEFBS_HasNEON, // VST2b16 = 3726 |
| 39447 | CEFBS_HasNEON, // VST2b16wb_fixed = 3727 |
| 39448 | CEFBS_HasNEON, // VST2b16wb_register = 3728 |
| 39449 | CEFBS_HasNEON, // VST2b32 = 3729 |
| 39450 | CEFBS_HasNEON, // VST2b32wb_fixed = 3730 |
| 39451 | CEFBS_HasNEON, // VST2b32wb_register = 3731 |
| 39452 | CEFBS_HasNEON, // VST2b8 = 3732 |
| 39453 | CEFBS_HasNEON, // VST2b8wb_fixed = 3733 |
| 39454 | CEFBS_HasNEON, // VST2b8wb_register = 3734 |
| 39455 | CEFBS_HasNEON, // VST2d16 = 3735 |
| 39456 | CEFBS_HasNEON, // VST2d16wb_fixed = 3736 |
| 39457 | CEFBS_HasNEON, // VST2d16wb_register = 3737 |
| 39458 | CEFBS_HasNEON, // VST2d32 = 3738 |
| 39459 | CEFBS_HasNEON, // VST2d32wb_fixed = 3739 |
| 39460 | CEFBS_HasNEON, // VST2d32wb_register = 3740 |
| 39461 | CEFBS_HasNEON, // VST2d8 = 3741 |
| 39462 | CEFBS_HasNEON, // VST2d8wb_fixed = 3742 |
| 39463 | CEFBS_HasNEON, // VST2d8wb_register = 3743 |
| 39464 | CEFBS_HasNEON, // VST2q16 = 3744 |
| 39465 | CEFBS_HasNEON, // VST2q16Pseudo = 3745 |
| 39466 | CEFBS_HasNEON, // VST2q16PseudoWB_fixed = 3746 |
| 39467 | CEFBS_HasNEON, // VST2q16PseudoWB_register = 3747 |
| 39468 | CEFBS_HasNEON, // VST2q16wb_fixed = 3748 |
| 39469 | CEFBS_HasNEON, // VST2q16wb_register = 3749 |
| 39470 | CEFBS_HasNEON, // VST2q32 = 3750 |
| 39471 | CEFBS_HasNEON, // VST2q32Pseudo = 3751 |
| 39472 | CEFBS_HasNEON, // VST2q32PseudoWB_fixed = 3752 |
| 39473 | CEFBS_HasNEON, // VST2q32PseudoWB_register = 3753 |
| 39474 | CEFBS_HasNEON, // VST2q32wb_fixed = 3754 |
| 39475 | CEFBS_HasNEON, // VST2q32wb_register = 3755 |
| 39476 | CEFBS_HasNEON, // VST2q8 = 3756 |
| 39477 | CEFBS_HasNEON, // VST2q8Pseudo = 3757 |
| 39478 | CEFBS_HasNEON, // VST2q8PseudoWB_fixed = 3758 |
| 39479 | CEFBS_HasNEON, // VST2q8PseudoWB_register = 3759 |
| 39480 | CEFBS_HasNEON, // VST2q8wb_fixed = 3760 |
| 39481 | CEFBS_HasNEON, // VST2q8wb_register = 3761 |
| 39482 | CEFBS_HasNEON, // VST3LNd16 = 3762 |
| 39483 | CEFBS_HasNEON, // VST3LNd16Pseudo = 3763 |
| 39484 | CEFBS_HasNEON, // VST3LNd16Pseudo_UPD = 3764 |
| 39485 | CEFBS_HasNEON, // VST3LNd16_UPD = 3765 |
| 39486 | CEFBS_HasNEON, // VST3LNd32 = 3766 |
| 39487 | CEFBS_HasNEON, // VST3LNd32Pseudo = 3767 |
| 39488 | CEFBS_HasNEON, // VST3LNd32Pseudo_UPD = 3768 |
| 39489 | CEFBS_HasNEON, // VST3LNd32_UPD = 3769 |
| 39490 | CEFBS_HasNEON, // VST3LNd8 = 3770 |
| 39491 | CEFBS_HasNEON, // VST3LNd8Pseudo = 3771 |
| 39492 | CEFBS_HasNEON, // VST3LNd8Pseudo_UPD = 3772 |
| 39493 | CEFBS_HasNEON, // VST3LNd8_UPD = 3773 |
| 39494 | CEFBS_HasNEON, // VST3LNq16 = 3774 |
| 39495 | CEFBS_HasNEON, // VST3LNq16Pseudo = 3775 |
| 39496 | CEFBS_HasNEON, // VST3LNq16Pseudo_UPD = 3776 |
| 39497 | CEFBS_HasNEON, // VST3LNq16_UPD = 3777 |
| 39498 | CEFBS_HasNEON, // VST3LNq32 = 3778 |
| 39499 | CEFBS_HasNEON, // VST3LNq32Pseudo = 3779 |
| 39500 | CEFBS_HasNEON, // VST3LNq32Pseudo_UPD = 3780 |
| 39501 | CEFBS_HasNEON, // VST3LNq32_UPD = 3781 |
| 39502 | CEFBS_HasNEON, // VST3d16 = 3782 |
| 39503 | CEFBS_HasNEON, // VST3d16Pseudo = 3783 |
| 39504 | CEFBS_HasNEON, // VST3d16Pseudo_UPD = 3784 |
| 39505 | CEFBS_HasNEON, // VST3d16_UPD = 3785 |
| 39506 | CEFBS_HasNEON, // VST3d32 = 3786 |
| 39507 | CEFBS_HasNEON, // VST3d32Pseudo = 3787 |
| 39508 | CEFBS_HasNEON, // VST3d32Pseudo_UPD = 3788 |
| 39509 | CEFBS_HasNEON, // VST3d32_UPD = 3789 |
| 39510 | CEFBS_HasNEON, // VST3d8 = 3790 |
| 39511 | CEFBS_HasNEON, // VST3d8Pseudo = 3791 |
| 39512 | CEFBS_HasNEON, // VST3d8Pseudo_UPD = 3792 |
| 39513 | CEFBS_HasNEON, // VST3d8_UPD = 3793 |
| 39514 | CEFBS_HasNEON, // VST3q16 = 3794 |
| 39515 | CEFBS_HasNEON, // VST3q16Pseudo_UPD = 3795 |
| 39516 | CEFBS_HasNEON, // VST3q16_UPD = 3796 |
| 39517 | CEFBS_HasNEON, // VST3q16oddPseudo = 3797 |
| 39518 | CEFBS_HasNEON, // VST3q16oddPseudo_UPD = 3798 |
| 39519 | CEFBS_HasNEON, // VST3q32 = 3799 |
| 39520 | CEFBS_HasNEON, // VST3q32Pseudo_UPD = 3800 |
| 39521 | CEFBS_HasNEON, // VST3q32_UPD = 3801 |
| 39522 | CEFBS_HasNEON, // VST3q32oddPseudo = 3802 |
| 39523 | CEFBS_HasNEON, // VST3q32oddPseudo_UPD = 3803 |
| 39524 | CEFBS_HasNEON, // VST3q8 = 3804 |
| 39525 | CEFBS_HasNEON, // VST3q8Pseudo_UPD = 3805 |
| 39526 | CEFBS_HasNEON, // VST3q8_UPD = 3806 |
| 39527 | CEFBS_HasNEON, // VST3q8oddPseudo = 3807 |
| 39528 | CEFBS_HasNEON, // VST3q8oddPseudo_UPD = 3808 |
| 39529 | CEFBS_HasNEON, // VST4LNd16 = 3809 |
| 39530 | CEFBS_HasNEON, // VST4LNd16Pseudo = 3810 |
| 39531 | CEFBS_HasNEON, // VST4LNd16Pseudo_UPD = 3811 |
| 39532 | CEFBS_HasNEON, // VST4LNd16_UPD = 3812 |
| 39533 | CEFBS_HasNEON, // VST4LNd32 = 3813 |
| 39534 | CEFBS_HasNEON, // VST4LNd32Pseudo = 3814 |
| 39535 | CEFBS_HasNEON, // VST4LNd32Pseudo_UPD = 3815 |
| 39536 | CEFBS_HasNEON, // VST4LNd32_UPD = 3816 |
| 39537 | CEFBS_HasNEON, // VST4LNd8 = 3817 |
| 39538 | CEFBS_HasNEON, // VST4LNd8Pseudo = 3818 |
| 39539 | CEFBS_HasNEON, // VST4LNd8Pseudo_UPD = 3819 |
| 39540 | CEFBS_HasNEON, // VST4LNd8_UPD = 3820 |
| 39541 | CEFBS_HasNEON, // VST4LNq16 = 3821 |
| 39542 | CEFBS_HasNEON, // VST4LNq16Pseudo = 3822 |
| 39543 | CEFBS_HasNEON, // VST4LNq16Pseudo_UPD = 3823 |
| 39544 | CEFBS_HasNEON, // VST4LNq16_UPD = 3824 |
| 39545 | CEFBS_HasNEON, // VST4LNq32 = 3825 |
| 39546 | CEFBS_HasNEON, // VST4LNq32Pseudo = 3826 |
| 39547 | CEFBS_HasNEON, // VST4LNq32Pseudo_UPD = 3827 |
| 39548 | CEFBS_HasNEON, // VST4LNq32_UPD = 3828 |
| 39549 | CEFBS_HasNEON, // VST4d16 = 3829 |
| 39550 | CEFBS_HasNEON, // VST4d16Pseudo = 3830 |
| 39551 | CEFBS_HasNEON, // VST4d16Pseudo_UPD = 3831 |
| 39552 | CEFBS_HasNEON, // VST4d16_UPD = 3832 |
| 39553 | CEFBS_HasNEON, // VST4d32 = 3833 |
| 39554 | CEFBS_HasNEON, // VST4d32Pseudo = 3834 |
| 39555 | CEFBS_HasNEON, // VST4d32Pseudo_UPD = 3835 |
| 39556 | CEFBS_HasNEON, // VST4d32_UPD = 3836 |
| 39557 | CEFBS_HasNEON, // VST4d8 = 3837 |
| 39558 | CEFBS_HasNEON, // VST4d8Pseudo = 3838 |
| 39559 | CEFBS_HasNEON, // VST4d8Pseudo_UPD = 3839 |
| 39560 | CEFBS_HasNEON, // VST4d8_UPD = 3840 |
| 39561 | CEFBS_HasNEON, // VST4q16 = 3841 |
| 39562 | CEFBS_HasNEON, // VST4q16Pseudo_UPD = 3842 |
| 39563 | CEFBS_HasNEON, // VST4q16_UPD = 3843 |
| 39564 | CEFBS_HasNEON, // VST4q16oddPseudo = 3844 |
| 39565 | CEFBS_HasNEON, // VST4q16oddPseudo_UPD = 3845 |
| 39566 | CEFBS_HasNEON, // VST4q32 = 3846 |
| 39567 | CEFBS_HasNEON, // VST4q32Pseudo_UPD = 3847 |
| 39568 | CEFBS_HasNEON, // VST4q32_UPD = 3848 |
| 39569 | CEFBS_HasNEON, // VST4q32oddPseudo = 3849 |
| 39570 | CEFBS_HasNEON, // VST4q32oddPseudo_UPD = 3850 |
| 39571 | CEFBS_HasNEON, // VST4q8 = 3851 |
| 39572 | CEFBS_HasNEON, // VST4q8Pseudo_UPD = 3852 |
| 39573 | CEFBS_HasNEON, // VST4q8_UPD = 3853 |
| 39574 | CEFBS_HasNEON, // VST4q8oddPseudo = 3854 |
| 39575 | CEFBS_HasNEON, // VST4q8oddPseudo_UPD = 3855 |
| 39576 | CEFBS_HasFPRegs, // VSTMDDB_UPD = 3856 |
| 39577 | CEFBS_HasFPRegs, // VSTMDIA = 3857 |
| 39578 | CEFBS_HasFPRegs, // VSTMDIA_UPD = 3858 |
| 39579 | CEFBS_HasVFP2, // VSTMQIA = 3859 |
| 39580 | CEFBS_HasFPRegs, // VSTMSDB_UPD = 3860 |
| 39581 | CEFBS_HasFPRegs, // VSTMSIA = 3861 |
| 39582 | CEFBS_HasFPRegs, // VSTMSIA_UPD = 3862 |
| 39583 | CEFBS_HasFPRegs, // VSTRD = 3863 |
| 39584 | CEFBS_HasFPRegs16, // VSTRH = 3864 |
| 39585 | CEFBS_HasFPRegs, // VSTRS = 3865 |
| 39586 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_off = 3866 |
| 39587 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_post = 3867 |
| 39588 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_pre = 3868 |
| 39589 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_off = 3869 |
| 39590 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_post = 3870 |
| 39591 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_pre = 3871 |
| 39592 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_off = 3872 |
| 39593 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_post = 3873 |
| 39594 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_pre = 3874 |
| 39595 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_off = 3875 |
| 39596 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_post = 3876 |
| 39597 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_pre = 3877 |
| 39598 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_off = 3878 |
| 39599 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_post = 3879 |
| 39600 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_pre = 3880 |
| 39601 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_off = 3881 |
| 39602 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_post = 3882 |
| 39603 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_pre = 3883 |
| 39604 | CEFBS_HasVFP2_HasDPVFP, // VSUBD = 3884 |
| 39605 | CEFBS_HasFullFP16, // VSUBH = 3885 |
| 39606 | CEFBS_HasNEON, // VSUBHNv2i32 = 3886 |
| 39607 | CEFBS_HasNEON, // VSUBHNv4i16 = 3887 |
| 39608 | CEFBS_HasNEON, // VSUBHNv8i8 = 3888 |
| 39609 | CEFBS_HasNEON, // VSUBLsv2i64 = 3889 |
| 39610 | CEFBS_HasNEON, // VSUBLsv4i32 = 3890 |
| 39611 | CEFBS_HasNEON, // VSUBLsv8i16 = 3891 |
| 39612 | CEFBS_HasNEON, // VSUBLuv2i64 = 3892 |
| 39613 | CEFBS_HasNEON, // VSUBLuv4i32 = 3893 |
| 39614 | CEFBS_HasNEON, // VSUBLuv8i16 = 3894 |
| 39615 | CEFBS_HasVFP2, // VSUBS = 3895 |
| 39616 | CEFBS_HasNEON, // VSUBWsv2i64 = 3896 |
| 39617 | CEFBS_HasNEON, // VSUBWsv4i32 = 3897 |
| 39618 | CEFBS_HasNEON, // VSUBWsv8i16 = 3898 |
| 39619 | CEFBS_HasNEON, // VSUBWuv2i64 = 3899 |
| 39620 | CEFBS_HasNEON, // VSUBWuv4i32 = 3900 |
| 39621 | CEFBS_HasNEON, // VSUBWuv8i16 = 3901 |
| 39622 | CEFBS_HasNEON, // VSUBfd = 3902 |
| 39623 | CEFBS_HasNEON, // VSUBfq = 3903 |
| 39624 | CEFBS_HasNEON_HasFullFP16, // VSUBhd = 3904 |
| 39625 | CEFBS_HasNEON_HasFullFP16, // VSUBhq = 3905 |
| 39626 | CEFBS_HasNEON, // VSUBv16i8 = 3906 |
| 39627 | CEFBS_HasNEON, // VSUBv1i64 = 3907 |
| 39628 | CEFBS_HasNEON, // VSUBv2i32 = 3908 |
| 39629 | CEFBS_HasNEON, // VSUBv2i64 = 3909 |
| 39630 | CEFBS_HasNEON, // VSUBv4i16 = 3910 |
| 39631 | CEFBS_HasNEON, // VSUBv4i32 = 3911 |
| 39632 | CEFBS_HasNEON, // VSUBv8i16 = 3912 |
| 39633 | CEFBS_HasNEON, // VSUBv8i8 = 3913 |
| 39634 | CEFBS_HasMatMulInt8, // VSUDOTDI = 3914 |
| 39635 | CEFBS_HasMatMulInt8, // VSUDOTQI = 3915 |
| 39636 | CEFBS_HasNEON, // VSWPd = 3916 |
| 39637 | CEFBS_HasNEON, // VSWPq = 3917 |
| 39638 | CEFBS_HasNEON, // VTBL1 = 3918 |
| 39639 | CEFBS_HasNEON, // VTBL2 = 3919 |
| 39640 | CEFBS_HasNEON, // VTBL3 = 3920 |
| 39641 | CEFBS_HasNEON, // VTBL3Pseudo = 3921 |
| 39642 | CEFBS_HasNEON, // VTBL4 = 3922 |
| 39643 | CEFBS_HasNEON, // VTBL4Pseudo = 3923 |
| 39644 | CEFBS_HasNEON, // VTBX1 = 3924 |
| 39645 | CEFBS_HasNEON, // VTBX2 = 3925 |
| 39646 | CEFBS_HasNEON, // VTBX3 = 3926 |
| 39647 | CEFBS_HasNEON, // VTBX3Pseudo = 3927 |
| 39648 | CEFBS_HasNEON, // VTBX4 = 3928 |
| 39649 | CEFBS_HasNEON, // VTBX4Pseudo = 3929 |
| 39650 | CEFBS_HasVFP2_HasDPVFP, // VTOSHD = 3930 |
| 39651 | CEFBS_HasFullFP16, // VTOSHH = 3931 |
| 39652 | CEFBS_HasVFP2, // VTOSHS = 3932 |
| 39653 | CEFBS_HasVFP2_HasDPVFP, // VTOSIRD = 3933 |
| 39654 | CEFBS_HasFullFP16, // VTOSIRH = 3934 |
| 39655 | CEFBS_HasVFP2, // VTOSIRS = 3935 |
| 39656 | CEFBS_HasVFP2_HasDPVFP, // VTOSIZD = 3936 |
| 39657 | CEFBS_HasFullFP16, // VTOSIZH = 3937 |
| 39658 | CEFBS_HasVFP2, // VTOSIZS = 3938 |
| 39659 | CEFBS_HasVFP2_HasDPVFP, // VTOSLD = 3939 |
| 39660 | CEFBS_HasFullFP16, // VTOSLH = 3940 |
| 39661 | CEFBS_HasVFP2, // VTOSLS = 3941 |
| 39662 | CEFBS_HasVFP2_HasDPVFP, // VTOUHD = 3942 |
| 39663 | CEFBS_HasFullFP16, // VTOUHH = 3943 |
| 39664 | CEFBS_HasVFP2, // VTOUHS = 3944 |
| 39665 | CEFBS_HasVFP2_HasDPVFP, // VTOUIRD = 3945 |
| 39666 | CEFBS_HasFullFP16, // VTOUIRH = 3946 |
| 39667 | CEFBS_HasVFP2, // VTOUIRS = 3947 |
| 39668 | CEFBS_HasVFP2_HasDPVFP, // VTOUIZD = 3948 |
| 39669 | CEFBS_HasFullFP16, // VTOUIZH = 3949 |
| 39670 | CEFBS_HasVFP2, // VTOUIZS = 3950 |
| 39671 | CEFBS_HasVFP2_HasDPVFP, // VTOULD = 3951 |
| 39672 | CEFBS_HasFullFP16, // VTOULH = 3952 |
| 39673 | CEFBS_HasVFP2, // VTOULS = 3953 |
| 39674 | CEFBS_HasNEON, // VTRNd16 = 3954 |
| 39675 | CEFBS_HasNEON, // VTRNd32 = 3955 |
| 39676 | CEFBS_HasNEON, // VTRNd8 = 3956 |
| 39677 | CEFBS_HasNEON, // VTRNq16 = 3957 |
| 39678 | CEFBS_HasNEON, // VTRNq32 = 3958 |
| 39679 | CEFBS_HasNEON, // VTRNq8 = 3959 |
| 39680 | CEFBS_HasNEON, // VTSTv16i8 = 3960 |
| 39681 | CEFBS_HasNEON, // VTSTv2i32 = 3961 |
| 39682 | CEFBS_HasNEON, // VTSTv4i16 = 3962 |
| 39683 | CEFBS_HasNEON, // VTSTv4i32 = 3963 |
| 39684 | CEFBS_HasNEON, // VTSTv8i16 = 3964 |
| 39685 | CEFBS_HasNEON, // VTSTv8i8 = 3965 |
| 39686 | CEFBS_HasDotProd, // VUDOTD = 3966 |
| 39687 | CEFBS_HasDotProd, // VUDOTDI = 3967 |
| 39688 | CEFBS_HasDotProd, // VUDOTQ = 3968 |
| 39689 | CEFBS_HasDotProd, // VUDOTQI = 3969 |
| 39690 | CEFBS_HasVFP2_HasDPVFP, // VUHTOD = 3970 |
| 39691 | CEFBS_HasFullFP16, // VUHTOH = 3971 |
| 39692 | CEFBS_HasVFP2, // VUHTOS = 3972 |
| 39693 | CEFBS_HasVFP2_HasDPVFP, // VUITOD = 3973 |
| 39694 | CEFBS_HasFullFP16, // VUITOH = 3974 |
| 39695 | CEFBS_HasVFP2, // VUITOS = 3975 |
| 39696 | CEFBS_HasVFP2_HasDPVFP, // VULTOD = 3976 |
| 39697 | CEFBS_HasFullFP16, // VULTOH = 3977 |
| 39698 | CEFBS_HasVFP2, // VULTOS = 3978 |
| 39699 | CEFBS_HasMatMulInt8, // VUMMLA = 3979 |
| 39700 | CEFBS_HasMatMulInt8, // VUSDOTD = 3980 |
| 39701 | CEFBS_HasMatMulInt8, // VUSDOTDI = 3981 |
| 39702 | CEFBS_HasMatMulInt8, // VUSDOTQ = 3982 |
| 39703 | CEFBS_HasMatMulInt8, // VUSDOTQI = 3983 |
| 39704 | CEFBS_HasMatMulInt8, // VUSMMLA = 3984 |
| 39705 | CEFBS_HasNEON, // VUZPd16 = 3985 |
| 39706 | CEFBS_HasNEON, // VUZPd8 = 3986 |
| 39707 | CEFBS_HasNEON, // VUZPq16 = 3987 |
| 39708 | CEFBS_HasNEON, // VUZPq32 = 3988 |
| 39709 | CEFBS_HasNEON, // VUZPq8 = 3989 |
| 39710 | CEFBS_HasNEON, // VZIPd16 = 3990 |
| 39711 | CEFBS_HasNEON, // VZIPd8 = 3991 |
| 39712 | CEFBS_HasNEON, // VZIPq16 = 3992 |
| 39713 | CEFBS_HasNEON, // VZIPq32 = 3993 |
| 39714 | CEFBS_HasNEON, // VZIPq8 = 3994 |
| 39715 | CEFBS_IsARM, // sysLDMDA = 3995 |
| 39716 | CEFBS_IsARM, // sysLDMDA_UPD = 3996 |
| 39717 | CEFBS_IsARM, // sysLDMDB = 3997 |
| 39718 | CEFBS_IsARM, // sysLDMDB_UPD = 3998 |
| 39719 | CEFBS_IsARM, // sysLDMIA = 3999 |
| 39720 | CEFBS_IsARM, // sysLDMIA_UPD = 4000 |
| 39721 | CEFBS_IsARM, // sysLDMIB = 4001 |
| 39722 | CEFBS_IsARM, // sysLDMIB_UPD = 4002 |
| 39723 | CEFBS_IsARM, // sysSTMDA = 4003 |
| 39724 | CEFBS_IsARM, // sysSTMDA_UPD = 4004 |
| 39725 | CEFBS_IsARM, // sysSTMDB = 4005 |
| 39726 | CEFBS_IsARM, // sysSTMDB_UPD = 4006 |
| 39727 | CEFBS_IsARM, // sysSTMIA = 4007 |
| 39728 | CEFBS_IsARM, // sysSTMIA_UPD = 4008 |
| 39729 | CEFBS_IsARM, // sysSTMIB = 4009 |
| 39730 | CEFBS_IsARM, // sysSTMIB_UPD = 4010 |
| 39731 | CEFBS_IsThumb2, // t2ADCri = 4011 |
| 39732 | CEFBS_IsThumb2, // t2ADCrr = 4012 |
| 39733 | CEFBS_IsThumb2, // t2ADCrs = 4013 |
| 39734 | CEFBS_IsThumb2, // t2ADDri = 4014 |
| 39735 | CEFBS_IsThumb2, // t2ADDri12 = 4015 |
| 39736 | CEFBS_IsThumb2, // t2ADDrr = 4016 |
| 39737 | CEFBS_IsThumb2, // t2ADDrs = 4017 |
| 39738 | CEFBS_IsThumb2, // t2ADDspImm = 4018 |
| 39739 | CEFBS_IsThumb2, // t2ADDspImm12 = 4019 |
| 39740 | CEFBS_IsThumb2, // t2ADR = 4020 |
| 39741 | CEFBS_IsThumb2, // t2ANDri = 4021 |
| 39742 | CEFBS_IsThumb2, // t2ANDrr = 4022 |
| 39743 | CEFBS_IsThumb2, // t2ANDrs = 4023 |
| 39744 | CEFBS_IsThumb2, // t2ASRri = 4024 |
| 39745 | CEFBS_IsThumb2, // t2ASRrr = 4025 |
| 39746 | CEFBS_HasV7_IsMClass, // t2AUT = 4026 |
| 39747 | CEFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, // t2AUTG = 4027 |
| 39748 | CEFBS_IsThumb_HasV8MBaseline, // t2B = 4028 |
| 39749 | CEFBS_IsThumb2, // t2BFC = 4029 |
| 39750 | CEFBS_IsThumb2, // t2BFI = 4030 |
| 39751 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFLi = 4031 |
| 39752 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFLr = 4032 |
| 39753 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFi = 4033 |
| 39754 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFic = 4034 |
| 39755 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFr = 4035 |
| 39756 | CEFBS_IsThumb2, // t2BICri = 4036 |
| 39757 | CEFBS_IsThumb2, // t2BICrr = 4037 |
| 39758 | CEFBS_IsThumb2, // t2BICrs = 4038 |
| 39759 | CEFBS_HasV7_IsMClass, // t2BTI = 4039 |
| 39760 | CEFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, // t2BXAUT = 4040 |
| 39761 | CEFBS_IsThumb2_IsNotMClass, // t2BXJ = 4041 |
| 39762 | CEFBS_IsThumb2, // t2Bcc = 4042 |
| 39763 | CEFBS_IsThumb2_PreV8, // t2CDP = 4043 |
| 39764 | CEFBS_IsThumb2_PreV8, // t2CDP2 = 4044 |
| 39765 | CEFBS_IsThumb_HasV7Clrex, // t2CLREX = 4045 |
| 39766 | CEFBS_HasV8_1MMainline, // t2CLRM = 4046 |
| 39767 | CEFBS_IsThumb2, // t2CLZ = 4047 |
| 39768 | CEFBS_IsThumb2, // t2CMNri = 4048 |
| 39769 | CEFBS_IsThumb2, // t2CMNzrr = 4049 |
| 39770 | CEFBS_IsThumb2, // t2CMNzrs = 4050 |
| 39771 | CEFBS_IsThumb2, // t2CMPri = 4051 |
| 39772 | CEFBS_IsThumb2, // t2CMPrr = 4052 |
| 39773 | CEFBS_IsThumb2, // t2CMPrs = 4053 |
| 39774 | CEFBS_IsThumb2_IsNotMClass, // t2CPS1p = 4054 |
| 39775 | CEFBS_IsThumb2_IsNotMClass, // t2CPS2p = 4055 |
| 39776 | CEFBS_IsThumb2_IsNotMClass, // t2CPS3p = 4056 |
| 39777 | CEFBS_IsThumb2_HasCRC, // t2CRC32B = 4057 |
| 39778 | CEFBS_IsThumb2_HasCRC, // t2CRC32CB = 4058 |
| 39779 | CEFBS_IsThumb2_HasCRC, // t2CRC32CH = 4059 |
| 39780 | CEFBS_IsThumb2_HasCRC, // t2CRC32CW = 4060 |
| 39781 | CEFBS_IsThumb2_HasCRC, // t2CRC32H = 4061 |
| 39782 | CEFBS_IsThumb2_HasCRC, // t2CRC32W = 4062 |
| 39783 | CEFBS_HasV8_1MMainline, // t2CSEL = 4063 |
| 39784 | CEFBS_HasV8_1MMainline, // t2CSINC = 4064 |
| 39785 | CEFBS_HasV8_1MMainline, // t2CSINV = 4065 |
| 39786 | CEFBS_HasV8_1MMainline, // t2CSNEG = 4066 |
| 39787 | CEFBS_IsThumb2, // t2DBG = 4067 |
| 39788 | CEFBS_IsThumb2_HasV8, // t2DCPS1 = 4068 |
| 39789 | CEFBS_IsThumb2_HasV8, // t2DCPS2 = 4069 |
| 39790 | CEFBS_IsThumb2_HasV8, // t2DCPS3 = 4070 |
| 39791 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2DLS = 4071 |
| 39792 | CEFBS_IsThumb_HasDB, // t2DMB = 4072 |
| 39793 | CEFBS_IsThumb_HasDB, // t2DSB = 4073 |
| 39794 | CEFBS_IsThumb2, // t2EORri = 4074 |
| 39795 | CEFBS_IsThumb2, // t2EORrr = 4075 |
| 39796 | CEFBS_IsThumb2, // t2EORrs = 4076 |
| 39797 | CEFBS_IsThumb2, // t2HINT = 4077 |
| 39798 | CEFBS_IsThumb2_HasVirtualization, // t2HVC = 4078 |
| 39799 | CEFBS_IsThumb_HasDB, // t2ISB = 4079 |
| 39800 | CEFBS_IsThumb2, // t2IT = 4080 |
| 39801 | CEFBS_IsThumb2_HasVFP2, // t2Int_eh_sjlj_setjmp = 4081 |
| 39802 | CEFBS_IsThumb2, // t2Int_eh_sjlj_setjmp_nofp = 4082 |
| 39803 | CEFBS_IsThumb_HasAcquireRelease, // t2LDA = 4083 |
| 39804 | CEFBS_IsThumb_HasAcquireRelease, // t2LDAB = 4084 |
| 39805 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEX = 4085 |
| 39806 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEXB = 4086 |
| 39807 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, // t2LDAEXD = 4087 |
| 39808 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEXH = 4088 |
| 39809 | CEFBS_IsThumb_HasAcquireRelease, // t2LDAH = 4089 |
| 39810 | CEFBS_PreV8_IsThumb2, // t2LDC2L_OFFSET = 4090 |
| 39811 | CEFBS_PreV8_IsThumb2, // t2LDC2L_OPTION = 4091 |
| 39812 | CEFBS_PreV8_IsThumb2, // t2LDC2L_POST = 4092 |
| 39813 | CEFBS_PreV8_IsThumb2, // t2LDC2L_PRE = 4093 |
| 39814 | CEFBS_PreV8_IsThumb2, // t2LDC2_OFFSET = 4094 |
| 39815 | CEFBS_PreV8_IsThumb2, // t2LDC2_OPTION = 4095 |
| 39816 | CEFBS_PreV8_IsThumb2, // t2LDC2_POST = 4096 |
| 39817 | CEFBS_PreV8_IsThumb2, // t2LDC2_PRE = 4097 |
| 39818 | CEFBS_IsThumb2, // t2LDCL_OFFSET = 4098 |
| 39819 | CEFBS_IsThumb2, // t2LDCL_OPTION = 4099 |
| 39820 | CEFBS_IsThumb2, // t2LDCL_POST = 4100 |
| 39821 | CEFBS_IsThumb2, // t2LDCL_PRE = 4101 |
| 39822 | CEFBS_IsThumb2, // t2LDC_OFFSET = 4102 |
| 39823 | CEFBS_IsThumb2, // t2LDC_OPTION = 4103 |
| 39824 | CEFBS_IsThumb2, // t2LDC_POST = 4104 |
| 39825 | CEFBS_IsThumb2, // t2LDC_PRE = 4105 |
| 39826 | CEFBS_IsThumb2, // t2LDMDB = 4106 |
| 39827 | CEFBS_IsThumb2, // t2LDMDB_UPD = 4107 |
| 39828 | CEFBS_IsThumb2, // t2LDMIA = 4108 |
| 39829 | CEFBS_IsThumb2, // t2LDMIA_UPD = 4109 |
| 39830 | CEFBS_IsThumb2, // t2LDRBT = 4110 |
| 39831 | CEFBS_IsThumb2, // t2LDRB_POST = 4111 |
| 39832 | CEFBS_IsThumb2, // t2LDRB_PRE = 4112 |
| 39833 | CEFBS_IsThumb2, // t2LDRBi12 = 4113 |
| 39834 | CEFBS_IsThumb2, // t2LDRBi8 = 4114 |
| 39835 | CEFBS_IsThumb2, // t2LDRBpci = 4115 |
| 39836 | CEFBS_IsThumb2, // t2LDRBs = 4116 |
| 39837 | CEFBS_IsThumb2, // t2LDRD_POST = 4117 |
| 39838 | CEFBS_IsThumb2, // t2LDRD_PRE = 4118 |
| 39839 | CEFBS_IsThumb2, // t2LDRDi8 = 4119 |
| 39840 | CEFBS_IsThumb_HasV8MBaseline, // t2LDREX = 4120 |
| 39841 | CEFBS_IsThumb_HasV8MBaseline, // t2LDREXB = 4121 |
| 39842 | CEFBS_IsThumb2_IsNotMClass, // t2LDREXD = 4122 |
| 39843 | CEFBS_IsThumb_HasV8MBaseline, // t2LDREXH = 4123 |
| 39844 | CEFBS_IsThumb2, // t2LDRHT = 4124 |
| 39845 | CEFBS_IsThumb2, // t2LDRH_POST = 4125 |
| 39846 | CEFBS_IsThumb2, // t2LDRH_PRE = 4126 |
| 39847 | CEFBS_IsThumb2, // t2LDRHi12 = 4127 |
| 39848 | CEFBS_IsThumb2, // t2LDRHi8 = 4128 |
| 39849 | CEFBS_IsThumb2, // t2LDRHpci = 4129 |
| 39850 | CEFBS_IsThumb2, // t2LDRHs = 4130 |
| 39851 | CEFBS_IsThumb2, // t2LDRSBT = 4131 |
| 39852 | CEFBS_IsThumb2, // t2LDRSB_POST = 4132 |
| 39853 | CEFBS_IsThumb2, // t2LDRSB_PRE = 4133 |
| 39854 | CEFBS_IsThumb2, // t2LDRSBi12 = 4134 |
| 39855 | CEFBS_IsThumb2, // t2LDRSBi8 = 4135 |
| 39856 | CEFBS_IsThumb2, // t2LDRSBpci = 4136 |
| 39857 | CEFBS_IsThumb2, // t2LDRSBs = 4137 |
| 39858 | CEFBS_IsThumb2, // t2LDRSHT = 4138 |
| 39859 | CEFBS_IsThumb2, // t2LDRSH_POST = 4139 |
| 39860 | CEFBS_IsThumb2, // t2LDRSH_PRE = 4140 |
| 39861 | CEFBS_IsThumb2, // t2LDRSHi12 = 4141 |
| 39862 | CEFBS_IsThumb2, // t2LDRSHi8 = 4142 |
| 39863 | CEFBS_IsThumb2, // t2LDRSHpci = 4143 |
| 39864 | CEFBS_IsThumb2, // t2LDRSHs = 4144 |
| 39865 | CEFBS_IsThumb2, // t2LDRT = 4145 |
| 39866 | CEFBS_IsThumb2, // t2LDR_POST = 4146 |
| 39867 | CEFBS_IsThumb2, // t2LDR_PRE = 4147 |
| 39868 | CEFBS_IsThumb2, // t2LDRi12 = 4148 |
| 39869 | CEFBS_IsThumb2, // t2LDRi8 = 4149 |
| 39870 | CEFBS_IsThumb2, // t2LDRpci = 4150 |
| 39871 | CEFBS_IsThumb2, // t2LDRs = 4151 |
| 39872 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LE = 4152 |
| 39873 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LEUpdate = 4153 |
| 39874 | CEFBS_IsThumb2, // t2LSLri = 4154 |
| 39875 | CEFBS_IsThumb2, // t2LSLrr = 4155 |
| 39876 | CEFBS_IsThumb2, // t2LSRri = 4156 |
| 39877 | CEFBS_IsThumb2, // t2LSRrr = 4157 |
| 39878 | CEFBS_IsThumb2, // t2MCR = 4158 |
| 39879 | CEFBS_IsThumb2_PreV8, // t2MCR2 = 4159 |
| 39880 | CEFBS_IsThumb2, // t2MCRR = 4160 |
| 39881 | CEFBS_IsThumb2_PreV8, // t2MCRR2 = 4161 |
| 39882 | CEFBS_IsThumb2, // t2MLA = 4162 |
| 39883 | CEFBS_IsThumb2, // t2MLS = 4163 |
| 39884 | CEFBS_IsThumb_HasV8MBaseline, // t2MOVTi16 = 4164 |
| 39885 | CEFBS_IsThumb2, // t2MOVi = 4165 |
| 39886 | CEFBS_IsThumb_HasV8MBaseline, // t2MOVi16 = 4166 |
| 39887 | CEFBS_IsThumb2, // t2MOVr = 4167 |
| 39888 | CEFBS_IsThumb2, // t2MOVsra_glue = 4168 |
| 39889 | CEFBS_IsThumb2, // t2MOVsrl_glue = 4169 |
| 39890 | CEFBS_IsThumb2, // t2MRC = 4170 |
| 39891 | CEFBS_IsThumb2_PreV8, // t2MRC2 = 4171 |
| 39892 | CEFBS_IsThumb2, // t2MRRC = 4172 |
| 39893 | CEFBS_IsThumb2_PreV8, // t2MRRC2 = 4173 |
| 39894 | CEFBS_IsThumb2_IsNotMClass, // t2MRS_AR = 4174 |
| 39895 | CEFBS_IsThumb_IsMClass, // t2MRS_M = 4175 |
| 39896 | CEFBS_IsThumb_HasVirtualization, // t2MRSbanked = 4176 |
| 39897 | CEFBS_IsThumb2_IsNotMClass, // t2MRSsys_AR = 4177 |
| 39898 | CEFBS_IsThumb2_IsNotMClass, // t2MSR_AR = 4178 |
| 39899 | CEFBS_IsThumb_IsMClass, // t2MSR_M = 4179 |
| 39900 | CEFBS_IsThumb_HasVirtualization, // t2MSRbanked = 4180 |
| 39901 | CEFBS_IsThumb2, // t2MUL = 4181 |
| 39902 | CEFBS_IsThumb2, // t2MVNi = 4182 |
| 39903 | CEFBS_IsThumb2, // t2MVNr = 4183 |
| 39904 | CEFBS_IsThumb2, // t2MVNs = 4184 |
| 39905 | CEFBS_IsThumb2, // t2ORNri = 4185 |
| 39906 | CEFBS_IsThumb2, // t2ORNrr = 4186 |
| 39907 | CEFBS_IsThumb2, // t2ORNrs = 4187 |
| 39908 | CEFBS_IsThumb2, // t2ORRri = 4188 |
| 39909 | CEFBS_IsThumb2, // t2ORRrr = 4189 |
| 39910 | CEFBS_IsThumb2, // t2ORRrs = 4190 |
| 39911 | CEFBS_HasV7_IsMClass, // t2PAC = 4191 |
| 39912 | CEFBS_HasV7_IsMClass, // t2PACBTI = 4192 |
| 39913 | CEFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, // t2PACG = 4193 |
| 39914 | CEFBS_HasDSP_IsThumb2, // t2PKHBT = 4194 |
| 39915 | CEFBS_HasDSP_IsThumb2, // t2PKHTB = 4195 |
| 39916 | CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWi12 = 4196 |
| 39917 | CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWi8 = 4197 |
| 39918 | CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWs = 4198 |
| 39919 | CEFBS_IsThumb2, // t2PLDi12 = 4199 |
| 39920 | CEFBS_IsThumb2, // t2PLDi8 = 4200 |
| 39921 | CEFBS_IsThumb2, // t2PLDpci = 4201 |
| 39922 | CEFBS_IsThumb2, // t2PLDs = 4202 |
| 39923 | CEFBS_IsThumb2_HasV7, // t2PLIi12 = 4203 |
| 39924 | CEFBS_IsThumb2_HasV7, // t2PLIi8 = 4204 |
| 39925 | CEFBS_IsThumb2_HasV7, // t2PLIpci = 4205 |
| 39926 | CEFBS_IsThumb2_HasV7, // t2PLIs = 4206 |
| 39927 | CEFBS_IsThumb2_HasDSP, // t2QADD = 4207 |
| 39928 | CEFBS_IsThumb2_HasDSP, // t2QADD16 = 4208 |
| 39929 | CEFBS_IsThumb2_HasDSP, // t2QADD8 = 4209 |
| 39930 | CEFBS_IsThumb2_HasDSP, // t2QASX = 4210 |
| 39931 | CEFBS_IsThumb2_HasDSP, // t2QDADD = 4211 |
| 39932 | CEFBS_IsThumb2_HasDSP, // t2QDSUB = 4212 |
| 39933 | CEFBS_IsThumb2_HasDSP, // t2QSAX = 4213 |
| 39934 | CEFBS_IsThumb2_HasDSP, // t2QSUB = 4214 |
| 39935 | CEFBS_IsThumb2_HasDSP, // t2QSUB16 = 4215 |
| 39936 | CEFBS_IsThumb2_HasDSP, // t2QSUB8 = 4216 |
| 39937 | CEFBS_IsThumb2, // t2RBIT = 4217 |
| 39938 | CEFBS_IsThumb2, // t2REV = 4218 |
| 39939 | CEFBS_IsThumb2, // t2REV16 = 4219 |
| 39940 | CEFBS_IsThumb2, // t2REVSH = 4220 |
| 39941 | CEFBS_IsThumb2_IsNotMClass, // t2RFEDB = 4221 |
| 39942 | CEFBS_IsThumb2_IsNotMClass, // t2RFEDBW = 4222 |
| 39943 | CEFBS_IsThumb2_IsNotMClass, // t2RFEIA = 4223 |
| 39944 | CEFBS_IsThumb2_IsNotMClass, // t2RFEIAW = 4224 |
| 39945 | CEFBS_IsThumb2, // t2RORri = 4225 |
| 39946 | CEFBS_IsThumb2, // t2RORrr = 4226 |
| 39947 | CEFBS_IsThumb2, // t2RRX = 4227 |
| 39948 | CEFBS_IsThumb2, // t2RSBri = 4228 |
| 39949 | CEFBS_IsThumb2, // t2RSBrr = 4229 |
| 39950 | CEFBS_IsThumb2, // t2RSBrs = 4230 |
| 39951 | CEFBS_IsThumb2_HasDSP, // t2SADD16 = 4231 |
| 39952 | CEFBS_IsThumb2_HasDSP, // t2SADD8 = 4232 |
| 39953 | CEFBS_IsThumb2_HasDSP, // t2SASX = 4233 |
| 39954 | CEFBS_IsThumb2_HasSB, // t2SB = 4234 |
| 39955 | CEFBS_IsThumb2, // t2SBCri = 4235 |
| 39956 | CEFBS_IsThumb2, // t2SBCrr = 4236 |
| 39957 | CEFBS_IsThumb2, // t2SBCrs = 4237 |
| 39958 | CEFBS_IsThumb2, // t2SBFX = 4238 |
| 39959 | CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, // t2SDIV = 4239 |
| 39960 | CEFBS_IsThumb2_HasDSP, // t2SEL = 4240 |
| 39961 | CEFBS_IsThumb2_HasV8_HasV8_1a, // t2SETPAN = 4241 |
| 39962 | CEFBS_Has8MSecExt, // t2SG = 4242 |
| 39963 | CEFBS_IsThumb2_HasDSP, // t2SHADD16 = 4243 |
| 39964 | CEFBS_IsThumb2_HasDSP, // t2SHADD8 = 4244 |
| 39965 | CEFBS_IsThumb2_HasDSP, // t2SHASX = 4245 |
| 39966 | CEFBS_IsThumb2_HasDSP, // t2SHSAX = 4246 |
| 39967 | CEFBS_IsThumb2_HasDSP, // t2SHSUB16 = 4247 |
| 39968 | CEFBS_IsThumb2_HasDSP, // t2SHSUB8 = 4248 |
| 39969 | CEFBS_IsThumb2_HasTrustZone, // t2SMC = 4249 |
| 39970 | CEFBS_IsThumb2_HasDSP, // t2SMLABB = 4250 |
| 39971 | CEFBS_IsThumb2_HasDSP, // t2SMLABT = 4251 |
| 39972 | CEFBS_IsThumb2_HasDSP, // t2SMLAD = 4252 |
| 39973 | CEFBS_IsThumb2_HasDSP, // t2SMLADX = 4253 |
| 39974 | CEFBS_IsThumb2, // t2SMLAL = 4254 |
| 39975 | CEFBS_IsThumb2_HasDSP, // t2SMLALBB = 4255 |
| 39976 | CEFBS_IsThumb2_HasDSP, // t2SMLALBT = 4256 |
| 39977 | CEFBS_IsThumb2_HasDSP, // t2SMLALD = 4257 |
| 39978 | CEFBS_IsThumb2_HasDSP, // t2SMLALDX = 4258 |
| 39979 | CEFBS_IsThumb2_HasDSP, // t2SMLALTB = 4259 |
| 39980 | CEFBS_IsThumb2_HasDSP, // t2SMLALTT = 4260 |
| 39981 | CEFBS_IsThumb2_HasDSP, // t2SMLATB = 4261 |
| 39982 | CEFBS_IsThumb2_HasDSP, // t2SMLATT = 4262 |
| 39983 | CEFBS_IsThumb2_HasDSP, // t2SMLAWB = 4263 |
| 39984 | CEFBS_IsThumb2_HasDSP, // t2SMLAWT = 4264 |
| 39985 | CEFBS_IsThumb2_HasDSP, // t2SMLSD = 4265 |
| 39986 | CEFBS_IsThumb2_HasDSP, // t2SMLSDX = 4266 |
| 39987 | CEFBS_IsThumb2_HasDSP, // t2SMLSLD = 4267 |
| 39988 | CEFBS_IsThumb2_HasDSP, // t2SMLSLDX = 4268 |
| 39989 | CEFBS_IsThumb2_HasDSP, // t2SMMLA = 4269 |
| 39990 | CEFBS_IsThumb2_HasDSP, // t2SMMLAR = 4270 |
| 39991 | CEFBS_IsThumb2_HasDSP, // t2SMMLS = 4271 |
| 39992 | CEFBS_IsThumb2_HasDSP, // t2SMMLSR = 4272 |
| 39993 | CEFBS_IsThumb2_HasDSP, // t2SMMUL = 4273 |
| 39994 | CEFBS_IsThumb2_HasDSP, // t2SMMULR = 4274 |
| 39995 | CEFBS_IsThumb2_HasDSP, // t2SMUAD = 4275 |
| 39996 | CEFBS_IsThumb2_HasDSP, // t2SMUADX = 4276 |
| 39997 | CEFBS_IsThumb2_HasDSP, // t2SMULBB = 4277 |
| 39998 | CEFBS_IsThumb2_HasDSP, // t2SMULBT = 4278 |
| 39999 | CEFBS_IsThumb2, // t2SMULL = 4279 |
| 40000 | CEFBS_IsThumb2_HasDSP, // t2SMULTB = 4280 |
| 40001 | CEFBS_IsThumb2_HasDSP, // t2SMULTT = 4281 |
| 40002 | CEFBS_IsThumb2_HasDSP, // t2SMULWB = 4282 |
| 40003 | CEFBS_IsThumb2_HasDSP, // t2SMULWT = 4283 |
| 40004 | CEFBS_IsThumb2_HasDSP, // t2SMUSD = 4284 |
| 40005 | CEFBS_IsThumb2_HasDSP, // t2SMUSDX = 4285 |
| 40006 | CEFBS_IsThumb2_IsNotMClass, // t2SRSDB = 4286 |
| 40007 | CEFBS_IsThumb2_IsNotMClass, // t2SRSDB_UPD = 4287 |
| 40008 | CEFBS_IsThumb2_IsNotMClass, // t2SRSIA = 4288 |
| 40009 | CEFBS_IsThumb2_IsNotMClass, // t2SRSIA_UPD = 4289 |
| 40010 | CEFBS_IsThumb2, // t2SSAT = 4290 |
| 40011 | CEFBS_IsThumb2_HasDSP, // t2SSAT16 = 4291 |
| 40012 | CEFBS_IsThumb2_HasDSP, // t2SSAX = 4292 |
| 40013 | CEFBS_IsThumb2_HasDSP, // t2SSUB16 = 4293 |
| 40014 | CEFBS_IsThumb2_HasDSP, // t2SSUB8 = 4294 |
| 40015 | CEFBS_PreV8_IsThumb2, // t2STC2L_OFFSET = 4295 |
| 40016 | CEFBS_PreV8_IsThumb2, // t2STC2L_OPTION = 4296 |
| 40017 | CEFBS_PreV8_IsThumb2, // t2STC2L_POST = 4297 |
| 40018 | CEFBS_PreV8_IsThumb2, // t2STC2L_PRE = 4298 |
| 40019 | CEFBS_PreV8_IsThumb2, // t2STC2_OFFSET = 4299 |
| 40020 | CEFBS_PreV8_IsThumb2, // t2STC2_OPTION = 4300 |
| 40021 | CEFBS_PreV8_IsThumb2, // t2STC2_POST = 4301 |
| 40022 | CEFBS_PreV8_IsThumb2, // t2STC2_PRE = 4302 |
| 40023 | CEFBS_IsThumb2, // t2STCL_OFFSET = 4303 |
| 40024 | CEFBS_IsThumb2, // t2STCL_OPTION = 4304 |
| 40025 | CEFBS_IsThumb2, // t2STCL_POST = 4305 |
| 40026 | CEFBS_IsThumb2, // t2STCL_PRE = 4306 |
| 40027 | CEFBS_IsThumb2, // t2STC_OFFSET = 4307 |
| 40028 | CEFBS_IsThumb2, // t2STC_OPTION = 4308 |
| 40029 | CEFBS_IsThumb2, // t2STC_POST = 4309 |
| 40030 | CEFBS_IsThumb2, // t2STC_PRE = 4310 |
| 40031 | CEFBS_IsThumb_HasAcquireRelease, // t2STL = 4311 |
| 40032 | CEFBS_IsThumb_HasAcquireRelease, // t2STLB = 4312 |
| 40033 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEX = 4313 |
| 40034 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEXB = 4314 |
| 40035 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, // t2STLEXD = 4315 |
| 40036 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEXH = 4316 |
| 40037 | CEFBS_IsThumb_HasAcquireRelease, // t2STLH = 4317 |
| 40038 | CEFBS_IsThumb2, // t2STMDB = 4318 |
| 40039 | CEFBS_IsThumb2, // t2STMDB_UPD = 4319 |
| 40040 | CEFBS_IsThumb2, // t2STMIA = 4320 |
| 40041 | CEFBS_IsThumb2, // t2STMIA_UPD = 4321 |
| 40042 | CEFBS_IsThumb2, // t2STRBT = 4322 |
| 40043 | CEFBS_IsThumb2, // t2STRB_POST = 4323 |
| 40044 | CEFBS_IsThumb2, // t2STRB_PRE = 4324 |
| 40045 | CEFBS_IsThumb2, // t2STRBi12 = 4325 |
| 40046 | CEFBS_IsThumb2, // t2STRBi8 = 4326 |
| 40047 | CEFBS_IsThumb2, // t2STRBs = 4327 |
| 40048 | CEFBS_IsThumb2, // t2STRD_POST = 4328 |
| 40049 | CEFBS_IsThumb2, // t2STRD_PRE = 4329 |
| 40050 | CEFBS_IsThumb2, // t2STRDi8 = 4330 |
| 40051 | CEFBS_IsThumb_HasV8MBaseline, // t2STREX = 4331 |
| 40052 | CEFBS_IsThumb_HasV8MBaseline, // t2STREXB = 4332 |
| 40053 | CEFBS_IsThumb2_IsNotMClass, // t2STREXD = 4333 |
| 40054 | CEFBS_IsThumb_HasV8MBaseline, // t2STREXH = 4334 |
| 40055 | CEFBS_IsThumb2, // t2STRHT = 4335 |
| 40056 | CEFBS_IsThumb2, // t2STRH_POST = 4336 |
| 40057 | CEFBS_IsThumb2, // t2STRH_PRE = 4337 |
| 40058 | CEFBS_IsThumb2, // t2STRHi12 = 4338 |
| 40059 | CEFBS_IsThumb2, // t2STRHi8 = 4339 |
| 40060 | CEFBS_IsThumb2, // t2STRHs = 4340 |
| 40061 | CEFBS_IsThumb2, // t2STRT = 4341 |
| 40062 | CEFBS_IsThumb2, // t2STR_POST = 4342 |
| 40063 | CEFBS_IsThumb2, // t2STR_PRE = 4343 |
| 40064 | CEFBS_IsThumb2, // t2STRi12 = 4344 |
| 40065 | CEFBS_IsThumb2, // t2STRi8 = 4345 |
| 40066 | CEFBS_IsThumb2, // t2STRs = 4346 |
| 40067 | CEFBS_IsThumb2_IsNotMClass, // t2SUBS_PC_LR = 4347 |
| 40068 | CEFBS_IsThumb2, // t2SUBri = 4348 |
| 40069 | CEFBS_IsThumb2, // t2SUBri12 = 4349 |
| 40070 | CEFBS_IsThumb2, // t2SUBrr = 4350 |
| 40071 | CEFBS_IsThumb2, // t2SUBrs = 4351 |
| 40072 | CEFBS_IsThumb2, // t2SUBspImm = 4352 |
| 40073 | CEFBS_IsThumb2, // t2SUBspImm12 = 4353 |
| 40074 | CEFBS_HasDSP_IsThumb2, // t2SXTAB = 4354 |
| 40075 | CEFBS_HasDSP_IsThumb2, // t2SXTAB16 = 4355 |
| 40076 | CEFBS_HasDSP_IsThumb2, // t2SXTAH = 4356 |
| 40077 | CEFBS_IsThumb2, // t2SXTB = 4357 |
| 40078 | CEFBS_HasDSP_IsThumb2, // t2SXTB16 = 4358 |
| 40079 | CEFBS_IsThumb2, // t2SXTH = 4359 |
| 40080 | CEFBS_IsThumb2, // t2TBB = 4360 |
| 40081 | CEFBS_IsThumb2, // t2TBH = 4361 |
| 40082 | CEFBS_IsThumb2, // t2TEQri = 4362 |
| 40083 | CEFBS_IsThumb2, // t2TEQrr = 4363 |
| 40084 | CEFBS_IsThumb2, // t2TEQrs = 4364 |
| 40085 | CEFBS_IsThumb_HasV8_4a, // t2TSB = 4365 |
| 40086 | CEFBS_IsThumb2, // t2TSTri = 4366 |
| 40087 | CEFBS_IsThumb2, // t2TSTrr = 4367 |
| 40088 | CEFBS_IsThumb2, // t2TSTrs = 4368 |
| 40089 | CEFBS_IsThumb_Has8MSecExt, // t2TT = 4369 |
| 40090 | CEFBS_IsThumb_Has8MSecExt, // t2TTA = 4370 |
| 40091 | CEFBS_IsThumb_Has8MSecExt, // t2TTAT = 4371 |
| 40092 | CEFBS_IsThumb_Has8MSecExt, // t2TTT = 4372 |
| 40093 | CEFBS_IsThumb2_HasDSP, // t2UADD16 = 4373 |
| 40094 | CEFBS_IsThumb2_HasDSP, // t2UADD8 = 4374 |
| 40095 | CEFBS_IsThumb2_HasDSP, // t2UASX = 4375 |
| 40096 | CEFBS_IsThumb2, // t2UBFX = 4376 |
| 40097 | CEFBS_IsThumb2, // t2UDF = 4377 |
| 40098 | CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, // t2UDIV = 4378 |
| 40099 | CEFBS_IsThumb2_HasDSP, // t2UHADD16 = 4379 |
| 40100 | CEFBS_IsThumb2_HasDSP, // t2UHADD8 = 4380 |
| 40101 | CEFBS_IsThumb2_HasDSP, // t2UHASX = 4381 |
| 40102 | CEFBS_IsThumb2_HasDSP, // t2UHSAX = 4382 |
| 40103 | CEFBS_IsThumb2_HasDSP, // t2UHSUB16 = 4383 |
| 40104 | CEFBS_IsThumb2_HasDSP, // t2UHSUB8 = 4384 |
| 40105 | CEFBS_IsThumb2_HasDSP, // t2UMAAL = 4385 |
| 40106 | CEFBS_IsThumb2, // t2UMLAL = 4386 |
| 40107 | CEFBS_IsThumb2, // t2UMULL = 4387 |
| 40108 | CEFBS_IsThumb2_HasDSP, // t2UQADD16 = 4388 |
| 40109 | CEFBS_IsThumb2_HasDSP, // t2UQADD8 = 4389 |
| 40110 | CEFBS_IsThumb2_HasDSP, // t2UQASX = 4390 |
| 40111 | CEFBS_IsThumb2_HasDSP, // t2UQSAX = 4391 |
| 40112 | CEFBS_IsThumb2_HasDSP, // t2UQSUB16 = 4392 |
| 40113 | CEFBS_IsThumb2_HasDSP, // t2UQSUB8 = 4393 |
| 40114 | CEFBS_IsThumb2_HasDSP, // t2USAD8 = 4394 |
| 40115 | CEFBS_IsThumb2_HasDSP, // t2USADA8 = 4395 |
| 40116 | CEFBS_IsThumb2, // t2USAT = 4396 |
| 40117 | CEFBS_IsThumb2_HasDSP, // t2USAT16 = 4397 |
| 40118 | CEFBS_IsThumb2_HasDSP, // t2USAX = 4398 |
| 40119 | CEFBS_IsThumb2_HasDSP, // t2USUB16 = 4399 |
| 40120 | CEFBS_IsThumb2_HasDSP, // t2USUB8 = 4400 |
| 40121 | CEFBS_HasDSP_IsThumb2, // t2UXTAB = 4401 |
| 40122 | CEFBS_HasDSP_IsThumb2, // t2UXTAB16 = 4402 |
| 40123 | CEFBS_HasDSP_IsThumb2, // t2UXTAH = 4403 |
| 40124 | CEFBS_IsThumb2, // t2UXTB = 4404 |
| 40125 | CEFBS_HasDSP_IsThumb2, // t2UXTB16 = 4405 |
| 40126 | CEFBS_IsThumb2, // t2UXTH = 4406 |
| 40127 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WLS = 4407 |
| 40128 | CEFBS_IsThumb, // tADC = 4408 |
| 40129 | CEFBS_IsThumb, // tADDhirr = 4409 |
| 40130 | CEFBS_IsThumb, // tADDi3 = 4410 |
| 40131 | CEFBS_IsThumb, // tADDi8 = 4411 |
| 40132 | CEFBS_IsThumb, // tADDrSP = 4412 |
| 40133 | CEFBS_IsThumb, // tADDrSPi = 4413 |
| 40134 | CEFBS_IsThumb, // tADDrr = 4414 |
| 40135 | CEFBS_IsThumb, // tADDspi = 4415 |
| 40136 | CEFBS_IsThumb, // tADDspr = 4416 |
| 40137 | CEFBS_IsThumb, // tADR = 4417 |
| 40138 | CEFBS_IsThumb, // tAND = 4418 |
| 40139 | CEFBS_IsThumb, // tASRri = 4419 |
| 40140 | CEFBS_IsThumb, // tASRrr = 4420 |
| 40141 | CEFBS_IsThumb, // tB = 4421 |
| 40142 | CEFBS_IsThumb, // tBIC = 4422 |
| 40143 | CEFBS_IsThumb, // tBKPT = 4423 |
| 40144 | CEFBS_IsThumb, // tBL = 4424 |
| 40145 | CEFBS_IsThumb_Has8MSecExt, // tBLXNSr = 4425 |
| 40146 | CEFBS_IsThumb_HasV5T_IsNotMClass, // tBLXi = 4426 |
| 40147 | CEFBS_IsThumb_HasV5T, // tBLXr = 4427 |
| 40148 | CEFBS_IsThumb, // tBX = 4428 |
| 40149 | CEFBS_IsThumb_Has8MSecExt, // tBXNS = 4429 |
| 40150 | CEFBS_IsThumb, // tBcc = 4430 |
| 40151 | CEFBS_IsThumb_HasV8MBaseline, // tCBNZ = 4431 |
| 40152 | CEFBS_IsThumb_HasV8MBaseline, // tCBZ = 4432 |
| 40153 | CEFBS_IsThumb, // tCMNz = 4433 |
| 40154 | CEFBS_IsThumb, // tCMPhir = 4434 |
| 40155 | CEFBS_IsThumb, // tCMPi8 = 4435 |
| 40156 | CEFBS_IsThumb, // tCMPr = 4436 |
| 40157 | CEFBS_IsThumb, // tCPS = 4437 |
| 40158 | CEFBS_IsThumb, // tEOR = 4438 |
| 40159 | CEFBS_IsThumb_HasV6M, // tHINT = 4439 |
| 40160 | CEFBS_IsThumb_HasV8, // tHLT = 4440 |
| 40161 | CEFBS_IsThumb, // tInt_WIN_eh_sjlj_longjmp = 4441 |
| 40162 | CEFBS_IsThumb, // tInt_eh_sjlj_longjmp = 4442 |
| 40163 | CEFBS_IsThumb, // tInt_eh_sjlj_setjmp = 4443 |
| 40164 | CEFBS_IsThumb, // tLDMIA = 4444 |
| 40165 | CEFBS_IsThumb, // tLDRBi = 4445 |
| 40166 | CEFBS_IsThumb, // tLDRBr = 4446 |
| 40167 | CEFBS_IsThumb, // tLDRHi = 4447 |
| 40168 | CEFBS_IsThumb, // tLDRHr = 4448 |
| 40169 | CEFBS_IsThumb, // tLDRSB = 4449 |
| 40170 | CEFBS_IsThumb, // tLDRSH = 4450 |
| 40171 | CEFBS_IsThumb, // tLDRi = 4451 |
| 40172 | CEFBS_IsThumb, // tLDRpci = 4452 |
| 40173 | CEFBS_IsThumb, // tLDRr = 4453 |
| 40174 | CEFBS_IsThumb, // tLDRspi = 4454 |
| 40175 | CEFBS_IsThumb, // tLSLri = 4455 |
| 40176 | CEFBS_IsThumb, // tLSLrr = 4456 |
| 40177 | CEFBS_IsThumb, // tLSRri = 4457 |
| 40178 | CEFBS_IsThumb, // tLSRrr = 4458 |
| 40179 | CEFBS_IsThumb, // tMOVSr = 4459 |
| 40180 | CEFBS_IsThumb, // tMOVi8 = 4460 |
| 40181 | CEFBS_IsThumb, // tMOVr = 4461 |
| 40182 | CEFBS_IsThumb, // tMUL = 4462 |
| 40183 | CEFBS_IsThumb, // tMVN = 4463 |
| 40184 | CEFBS_IsThumb, // tORR = 4464 |
| 40185 | CEFBS_IsThumb, // tPICADD = 4465 |
| 40186 | CEFBS_IsThumb, // tPOP = 4466 |
| 40187 | CEFBS_IsThumb, // tPUSH = 4467 |
| 40188 | CEFBS_IsThumb_HasV6, // tREV = 4468 |
| 40189 | CEFBS_IsThumb_HasV6, // tREV16 = 4469 |
| 40190 | CEFBS_IsThumb_HasV6, // tREVSH = 4470 |
| 40191 | CEFBS_IsThumb, // tROR = 4471 |
| 40192 | CEFBS_IsThumb, // tRSB = 4472 |
| 40193 | CEFBS_IsThumb, // tSBC = 4473 |
| 40194 | CEFBS_IsThumb_IsNotMClass, // tSETEND = 4474 |
| 40195 | CEFBS_IsThumb, // tSTMIA_UPD = 4475 |
| 40196 | CEFBS_IsThumb, // tSTRBi = 4476 |
| 40197 | CEFBS_IsThumb, // tSTRBr = 4477 |
| 40198 | CEFBS_IsThumb, // tSTRHi = 4478 |
| 40199 | CEFBS_IsThumb, // tSTRHr = 4479 |
| 40200 | CEFBS_IsThumb, // tSTRi = 4480 |
| 40201 | CEFBS_IsThumb, // tSTRr = 4481 |
| 40202 | CEFBS_IsThumb, // tSTRspi = 4482 |
| 40203 | CEFBS_IsThumb, // tSUBi3 = 4483 |
| 40204 | CEFBS_IsThumb, // tSUBi8 = 4484 |
| 40205 | CEFBS_IsThumb, // tSUBrr = 4485 |
| 40206 | CEFBS_IsThumb, // tSUBspi = 4486 |
| 40207 | CEFBS_IsThumb, // tSVC = 4487 |
| 40208 | CEFBS_IsThumb_HasV6, // tSXTB = 4488 |
| 40209 | CEFBS_IsThumb_HasV6, // tSXTH = 4489 |
| 40210 | CEFBS_IsThumb, // tTRAP = 4490 |
| 40211 | CEFBS_IsThumb, // tTST = 4491 |
| 40212 | CEFBS_IsThumb, // tUDF = 4492 |
| 40213 | CEFBS_IsThumb_HasV6, // tUXTB = 4493 |
| 40214 | CEFBS_IsThumb_HasV6, // tUXTH = 4494 |
| 40215 | CEFBS_IsThumb, // t__brkdiv0 = 4495 |
| 40216 | }; |
| 40217 | |
| 40218 | assert(Opcode < 4496); |
| 40219 | return FeatureBitsets[RequiredFeaturesRefs[Opcode]]; |
| 40220 | } |
| 40221 | |
| 40222 | } // end namespace ARM_MC |
| 40223 | } // end namespace llvm |
| 40224 | #endif // GET_COMPUTE_FEATURES |
| 40225 | |
| 40226 | #ifdef GET_AVAILABLE_OPCODE_CHECKER |
| 40227 | #undef GET_AVAILABLE_OPCODE_CHECKER |
| 40228 | namespace llvm { |
| 40229 | namespace ARM_MC { |
| 40230 | bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) { |
| 40231 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 40232 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 40233 | FeatureBitset MissingFeatures = |
| 40234 | (AvailableFeatures & RequiredFeatures) ^ |
| 40235 | RequiredFeatures; |
| 40236 | return !MissingFeatures.any(); |
| 40237 | } |
| 40238 | } // end namespace ARM_MC |
| 40239 | } // end namespace llvm |
| 40240 | #endif // GET_AVAILABLE_OPCODE_CHECKER |
| 40241 | |
| 40242 | #ifdef ENABLE_INSTR_PREDICATE_VERIFIER |
| 40243 | #undef ENABLE_INSTR_PREDICATE_VERIFIER |
| 40244 | #include <sstream> |
| 40245 | |
| 40246 | namespace llvm { |
| 40247 | namespace ARM_MC { |
| 40248 | |
| 40249 | #ifndef NDEBUG |
| 40250 | static const char *SubtargetFeatureNames[] = { |
| 40251 | "Feature_Has8MSecExt", |
| 40252 | "Feature_HasAES", |
| 40253 | "Feature_HasAcquireRelease", |
| 40254 | "Feature_HasBF16", |
| 40255 | "Feature_HasCDE", |
| 40256 | "Feature_HasCLRBHB", |
| 40257 | "Feature_HasCRC", |
| 40258 | "Feature_HasCrypto", |
| 40259 | "Feature_HasDB", |
| 40260 | "Feature_HasDFB", |
| 40261 | "Feature_HasDPVFP", |
| 40262 | "Feature_HasDSP", |
| 40263 | "Feature_HasDivideInARM", |
| 40264 | "Feature_HasDivideInThumb", |
| 40265 | "Feature_HasDotProd", |
| 40266 | "Feature_HasFP16", |
| 40267 | "Feature_HasFP16FML", |
| 40268 | "Feature_HasFPARMv8", |
| 40269 | "Feature_HasFPRegs", |
| 40270 | "Feature_HasFPRegs16", |
| 40271 | "Feature_HasFPRegs64", |
| 40272 | "Feature_HasFPRegsV8_1M", |
| 40273 | "Feature_HasFullFP16", |
| 40274 | "Feature_HasLOB", |
| 40275 | "Feature_HasMP", |
| 40276 | "Feature_HasMVEFloat", |
| 40277 | "Feature_HasMVEInt", |
| 40278 | "Feature_HasMatMulInt8", |
| 40279 | "Feature_HasNEON", |
| 40280 | "Feature_HasNoFPRegs16", |
| 40281 | "Feature_HasPACBTI", |
| 40282 | "Feature_HasRAS", |
| 40283 | "Feature_HasSB", |
| 40284 | "Feature_HasSHA2", |
| 40285 | "Feature_HasTrustZone", |
| 40286 | "Feature_HasV4T", |
| 40287 | "Feature_HasV5T", |
| 40288 | "Feature_HasV5TE", |
| 40289 | "Feature_HasV6", |
| 40290 | "Feature_HasV6K", |
| 40291 | "Feature_HasV6M", |
| 40292 | "Feature_HasV6T2", |
| 40293 | "Feature_HasV7", |
| 40294 | "Feature_HasV7Clrex", |
| 40295 | "Feature_HasV8", |
| 40296 | "Feature_HasV8MBaseline", |
| 40297 | "Feature_HasV8MMainline", |
| 40298 | "Feature_HasV8_1MMainline", |
| 40299 | "Feature_HasV8_1a", |
| 40300 | "Feature_HasV8_2a", |
| 40301 | "Feature_HasV8_3a", |
| 40302 | "Feature_HasV8_4a", |
| 40303 | "Feature_HasV8_5a", |
| 40304 | "Feature_HasV8_6a", |
| 40305 | "Feature_HasV8_7a", |
| 40306 | "Feature_HasVFP2", |
| 40307 | "Feature_HasVFP3", |
| 40308 | "Feature_HasVFP4", |
| 40309 | "Feature_HasVirtualization", |
| 40310 | "Feature_IsARM", |
| 40311 | "Feature_IsMClass", |
| 40312 | "Feature_IsNotMClass", |
| 40313 | "Feature_IsThumb", |
| 40314 | "Feature_IsThumb2", |
| 40315 | "Feature_PreV8", |
| 40316 | "Feature_UseNaClTrap", |
| 40317 | "Feature_UseNegativeImmediates", |
| 40318 | nullptr |
| 40319 | }; |
| 40320 | |
| 40321 | #endif // NDEBUG |
| 40322 | |
| 40323 | void verifyInstructionPredicates( |
| 40324 | unsigned Opcode, const FeatureBitset &Features) { |
| 40325 | #ifndef NDEBUG |
| 40326 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 40327 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 40328 | FeatureBitset MissingFeatures = |
| 40329 | (AvailableFeatures & RequiredFeatures) ^ |
| 40330 | RequiredFeatures; |
| 40331 | if (MissingFeatures.any()) { |
| 40332 | std::ostringstream Msg; |
| 40333 | Msg << "Attempting to emit "<< &ARMInstrNameData[ARMInstrNameIndices[Opcode]] |
| 40334 | << " instruction but the "; |
| 40335 | for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) |
| 40336 | if (MissingFeatures.test(i)) |
| 40337 | Msg << SubtargetFeatureNames[i] << " "; |
| 40338 | Msg << "predicate(s) are not met"; |
| 40339 | report_fatal_error(Msg.str().c_str()); |
| 40340 | } |
| 40341 | #endif // NDEBUG |
| 40342 | } |
| 40343 | } // end namespace ARM_MC |
| 40344 | } // end namespace llvm |
| 40345 | #endif // ENABLE_INSTR_PREDICATE_VERIFIER |
| 40346 | |
| 40347 |
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