1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace ARM {
13enum : unsigned {
14 InvalidRegBankID = ~0u,
15 FPRRegBankID = 0,
16 GPRRegBankID = 1,
17 NumRegisterBanks,
18};
19} // end namespace ARM
20} // end namespace llvm
21#endif // GET_REGBANK_DECLARATIONS
22
23#ifdef GET_TARGET_REGBANK_CLASS
24#undef GET_TARGET_REGBANK_CLASS
25private:
26 static const RegisterBank *RegBanks[];
27 static const unsigned Sizes[];
28
29protected:
30 ARMGenRegisterBankInfo(unsigned HwMode = 0);
31
32#endif // GET_TARGET_REGBANK_CLASS
33
34#ifdef GET_TARGET_REGBANK_IMPL
35#undef GET_TARGET_REGBANK_IMPL
36namespace llvm {
37namespace ARM {
38const uint32_t FPRRegBankCoverageData[] = {
39 // 0-31
40 (1u << (ARM::HPRRegClassID - 0)) |
41 (1u << (ARM::SPRRegClassID - 0)) |
42 (1u << (ARM::SPR_8RegClassID - 0)) |
43 (1u << (ARM::FPWithVPRRegClassID - 0)) |
44 (1u << (ARM::FPWithVPR_with_ssub_0RegClassID - 0)) |
45 (1u << (ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID - 0)) |
46 0,
47 // 32-63
48 (1u << (ARM::DPRRegClassID - 32)) |
49 (1u << (ARM::DPR_VFP2RegClassID - 32)) |
50 (1u << (ARM::DPR_8RegClassID - 32)) |
51 0,
52 // 64-95
53 (1u << (ARM::QPRRegClassID - 64)) |
54 (1u << (ARM::MQPRRegClassID - 64)) |
55 (1u << (ARM::QPR_VFP2RegClassID - 64)) |
56 (1u << (ARM::QPR_8RegClassID - 64)) |
57 0,
58 // 96-127
59 0,
60 // 128-159
61 0,
62};
63const uint32_t GPRRegBankCoverageData[] = {
64 // 0-31
65 (1u << (ARM::GPRRegClassID - 0)) |
66 (1u << (ARM::GPRnopcRegClassID - 0)) |
67 (1u << (ARM::rGPRRegClassID - 0)) |
68 (1u << (ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID - 0)) |
69 (1u << (ARM::tGPRRegClassID - 0)) |
70 (1u << (ARM::GPRnoip_and_tGPREvenRegClassID - 0)) |
71 (1u << (ARM::tGPROddRegClassID - 0)) |
72 (1u << (ARM::tGPREvenRegClassID - 0)) |
73 (1u << (ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID - 0)) |
74 (1u << (ARM::tcGPRRegClassID - 0)) |
75 (1u << (ARM::GPRnoip_and_GPRnopcRegClassID - 0)) |
76 (1u << (ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID - 0)) |
77 (1u << (ARM::GPRnopc_and_hGPRRegClassID - 0)) |
78 (1u << (ARM::GPRnospRegClassID - 0)) |
79 (1u << (ARM::GPRnoip_and_GPRnospRegClassID - 0)) |
80 (1u << (ARM::tGPRwithpcRegClassID - 0)) |
81 (1u << (ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID - 0)) |
82 (1u << (ARM::GPRnosp_and_hGPRRegClassID - 0)) |
83 (1u << (ARM::GPRnoipRegClassID - 0)) |
84 (1u << (ARM::GPRnoip_and_hGPRRegClassID - 0)) |
85 (1u << (ARM::hGPRRegClassID - 0)) |
86 (1u << (ARM::GPRwithAPSRRegClassID - 0)) |
87 (1u << (ARM::GPRwithAPSR_NZCVnospRegClassID - 0)) |
88 0,
89 // 32-63
90 (1u << (ARM::tGPR_and_tGPREvenRegClassID - 32)) |
91 (1u << (ARM::tGPREven_and_tcGPRnotr12RegClassID - 32)) |
92 (1u << (ARM::tGPR_and_tGPROddRegClassID - 32)) |
93 (1u << (ARM::tGPROdd_and_tcGPRRegClassID - 32)) |
94 (1u << (ARM::tcGPRnotr12RegClassID - 32)) |
95 (1u << (ARM::hGPR_and_GPRnoip_and_tGPREvenRegClassID - 32)) |
96 (1u << (ARM::hGPR_and_tGPROddRegClassID - 32)) |
97 (1u << (ARM::GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID - 32)) |
98 (1u << (ARM::hGPR_and_tGPREvenRegClassID - 32)) |
99 (1u << (ARM::GPRlrRegClassID - 32)) |
100 (1u << (ARM::hGPR_and_tcGPRRegClassID - 32)) |
101 (1u << (ARM::tGPREven_and_tcGPRRegClassID - 32)) |
102 (1u << (ARM::GPRspRegClassID - 32)) |
103 (1u << (ARM::hGPR_and_tGPRwithpcRegClassID - 32)) |
104 0,
105 // 64-95
106 0,
107 // 96-127
108 0,
109 // 128-159
110 0,
111};
112
113constexpr RegisterBank FPRRegBank(/* ID */ ARM::FPRRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 136);
114constexpr RegisterBank GPRRegBank(/* ID */ ARM::GPRRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 136);
115} // end namespace ARM
116
117const RegisterBank *ARMGenRegisterBankInfo::RegBanks[] = {
118 &ARM::FPRRegBank,
119 &ARM::GPRRegBank,
120};
121
122const unsigned ARMGenRegisterBankInfo::Sizes[] = {
123 // Mode = 0 (Default)
124 128,
125 32,
126};
127
128ARMGenRegisterBankInfo::ARMGenRegisterBankInfo(unsigned HwMode)
129 : RegisterBankInfo(RegBanks, ARM::NumRegisterBanks, Sizes, HwMode) {
130 // Assert that RegBank indices match their ID's
131#ifndef NDEBUG
132 for (auto RB : enumerate(RegBanks))
133 assert(RB.index() == RB.value()->getID() && "Index != ID");
134#endif // NDEBUG
135}
136} // end namespace llvm
137#endif // GET_TARGET_REGBANK_IMPL
138