1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: AVR.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands);
18 void convertToMapAndConstraints(unsigned Kind,
19 const OperandVector &Operands) override;
20 unsigned MatchInstructionImpl(const OperandVector &Operands,
21 MCInst &Inst,
22 uint64_t &ErrorInfo,
23 FeatureBitset &MissingFeatures,
24 bool matchingInlineAsm,
25 unsigned VariantID = 0);
26 unsigned MatchInstructionImpl(const OperandVector &Operands,
27 MCInst &Inst,
28 uint64_t &ErrorInfo,
29 bool matchingInlineAsm,
30 unsigned VariantID = 0) {
31 FeatureBitset MissingFeatures;
32 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
33 matchingInlineAsm, VariantID);
34 }
35
36 ParseStatus MatchOperandParserImpl(
37 OperandVector &Operands,
38 StringRef Mnemonic,
39 bool ParseForAllFeatures = false);
40 ParseStatus tryCustomParseOperand(
41 OperandVector &Operands,
42 unsigned MCK);
43
44#endif // GET_ASSEMBLER_HEADER
45
46
47#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
48#undef GET_OPERAND_DIAGNOSTIC_TYPES
49
50#endif // GET_OPERAND_DIAGNOSTIC_TYPES
51
52
53#ifdef GET_REGISTER_MATCHER
54#undef GET_REGISTER_MATCHER
55
56// Bits for subtarget features that participate in instruction matching.
57enum SubtargetFeatureBits : uint8_t {
58 Feature_HasSRAMBit = 14,
59 Feature_HasJMPCALLBit = 7,
60 Feature_HasIJMPCALLBit = 6,
61 Feature_HasEIJMPCALLBit = 3,
62 Feature_HasADDSUBIWBit = 0,
63 Feature_HasSmallStackBit = 15,
64 Feature_HasMOVWBit = 10,
65 Feature_HasLPMBit = 8,
66 Feature_HasLPMXBit = 9,
67 Feature_HasELPMBit = 4,
68 Feature_HasELPMXBit = 5,
69 Feature_HasSPMBit = 12,
70 Feature_HasSPMXBit = 13,
71 Feature_HasDESBit = 2,
72 Feature_SupportsRMWBit = 18,
73 Feature_SupportsMultiplicationBit = 17,
74 Feature_HasBREAKBit = 1,
75 Feature_HasTinyEncodingBit = 16,
76 Feature_HasNonTinyEncodingBit = 11,
77};
78
79static MCRegister MatchRegisterName(StringRef Name) {
80 switch (Name.size()) {
81 default: break;
82 case 2: // 11 strings to match.
83 switch (Name[0]) {
84 default: break;
85 case 'S': // 1 string to match.
86 if (Name[1] != 'P')
87 break;
88 return AVR::SP; // "SP"
89 case 'r': // 10 strings to match.
90 switch (Name[1]) {
91 default: break;
92 case '0': // 1 string to match.
93 return AVR::R0; // "r0"
94 case '1': // 1 string to match.
95 return AVR::R1; // "r1"
96 case '2': // 1 string to match.
97 return AVR::R2; // "r2"
98 case '3': // 1 string to match.
99 return AVR::R3; // "r3"
100 case '4': // 1 string to match.
101 return AVR::R4; // "r4"
102 case '5': // 1 string to match.
103 return AVR::R5; // "r5"
104 case '6': // 1 string to match.
105 return AVR::R6; // "r6"
106 case '7': // 1 string to match.
107 return AVR::R7; // "r7"
108 case '8': // 1 string to match.
109 return AVR::R8; // "r8"
110 case '9': // 1 string to match.
111 return AVR::R9; // "r9"
112 }
113 break;
114 }
115 break;
116 case 3: // 24 strings to match.
117 switch (Name[0]) {
118 default: break;
119 case 'S': // 2 strings to match.
120 if (Name[1] != 'P')
121 break;
122 switch (Name[2]) {
123 default: break;
124 case 'H': // 1 string to match.
125 return AVR::SPH; // "SPH"
126 case 'L': // 1 string to match.
127 return AVR::SPL; // "SPL"
128 }
129 break;
130 case 'r': // 22 strings to match.
131 switch (Name[1]) {
132 default: break;
133 case '1': // 10 strings to match.
134 switch (Name[2]) {
135 default: break;
136 case '0': // 1 string to match.
137 return AVR::R10; // "r10"
138 case '1': // 1 string to match.
139 return AVR::R11; // "r11"
140 case '2': // 1 string to match.
141 return AVR::R12; // "r12"
142 case '3': // 1 string to match.
143 return AVR::R13; // "r13"
144 case '4': // 1 string to match.
145 return AVR::R14; // "r14"
146 case '5': // 1 string to match.
147 return AVR::R15; // "r15"
148 case '6': // 1 string to match.
149 return AVR::R16; // "r16"
150 case '7': // 1 string to match.
151 return AVR::R17; // "r17"
152 case '8': // 1 string to match.
153 return AVR::R18; // "r18"
154 case '9': // 1 string to match.
155 return AVR::R19; // "r19"
156 }
157 break;
158 case '2': // 10 strings to match.
159 switch (Name[2]) {
160 default: break;
161 case '0': // 1 string to match.
162 return AVR::R20; // "r20"
163 case '1': // 1 string to match.
164 return AVR::R21; // "r21"
165 case '2': // 1 string to match.
166 return AVR::R22; // "r22"
167 case '3': // 1 string to match.
168 return AVR::R23; // "r23"
169 case '4': // 1 string to match.
170 return AVR::R24; // "r24"
171 case '5': // 1 string to match.
172 return AVR::R25; // "r25"
173 case '6': // 1 string to match.
174 return AVR::R26; // "r26"
175 case '7': // 1 string to match.
176 return AVR::R27; // "r27"
177 case '8': // 1 string to match.
178 return AVR::R28; // "r28"
179 case '9': // 1 string to match.
180 return AVR::R29; // "r29"
181 }
182 break;
183 case '3': // 2 strings to match.
184 switch (Name[2]) {
185 default: break;
186 case '0': // 1 string to match.
187 return AVR::R30; // "r30"
188 case '1': // 1 string to match.
189 return AVR::R31; // "r31"
190 }
191 break;
192 }
193 break;
194 }
195 break;
196 case 5: // 6 strings to match.
197 switch (Name[0]) {
198 default: break;
199 case 'F': // 1 string to match.
200 if (memcmp(Name.data()+1, "LAGS", 4) != 0)
201 break;
202 return AVR::SREG; // "FLAGS"
203 case 'r': // 5 strings to match.
204 switch (Name[1]) {
205 default: break;
206 case '1': // 1 string to match.
207 if (memcmp(Name.data()+2, ":r0", 3) != 0)
208 break;
209 return AVR::R1R0; // "r1:r0"
210 case '3': // 1 string to match.
211 if (memcmp(Name.data()+2, ":r2", 3) != 0)
212 break;
213 return AVR::R3R2; // "r3:r2"
214 case '5': // 1 string to match.
215 if (memcmp(Name.data()+2, ":r4", 3) != 0)
216 break;
217 return AVR::R5R4; // "r5:r4"
218 case '7': // 1 string to match.
219 if (memcmp(Name.data()+2, ":r6", 3) != 0)
220 break;
221 return AVR::R7R6; // "r7:r6"
222 case '9': // 1 string to match.
223 if (memcmp(Name.data()+2, ":r8", 3) != 0)
224 break;
225 return AVR::R9R8; // "r9:r8"
226 }
227 break;
228 }
229 break;
230 case 6: // 1 string to match.
231 if (memcmp(Name.data()+0, "r10:r9", 6) != 0)
232 break;
233 return AVR::R10R9; // "r10:r9"
234 case 7: // 19 strings to match.
235 if (Name[0] != 'r')
236 break;
237 switch (Name[1]) {
238 default: break;
239 case '1': // 9 strings to match.
240 switch (Name[2]) {
241 default: break;
242 case '1': // 1 string to match.
243 if (memcmp(Name.data()+3, ":r10", 4) != 0)
244 break;
245 return AVR::R11R10; // "r11:r10"
246 case '2': // 1 string to match.
247 if (memcmp(Name.data()+3, ":r11", 4) != 0)
248 break;
249 return AVR::R12R11; // "r12:r11"
250 case '3': // 1 string to match.
251 if (memcmp(Name.data()+3, ":r12", 4) != 0)
252 break;
253 return AVR::R13R12; // "r13:r12"
254 case '4': // 1 string to match.
255 if (memcmp(Name.data()+3, ":r13", 4) != 0)
256 break;
257 return AVR::R14R13; // "r14:r13"
258 case '5': // 1 string to match.
259 if (memcmp(Name.data()+3, ":r14", 4) != 0)
260 break;
261 return AVR::R15R14; // "r15:r14"
262 case '6': // 1 string to match.
263 if (memcmp(Name.data()+3, ":r15", 4) != 0)
264 break;
265 return AVR::R16R15; // "r16:r15"
266 case '7': // 1 string to match.
267 if (memcmp(Name.data()+3, ":r16", 4) != 0)
268 break;
269 return AVR::R17R16; // "r17:r16"
270 case '8': // 1 string to match.
271 if (memcmp(Name.data()+3, ":r17", 4) != 0)
272 break;
273 return AVR::R18R17; // "r18:r17"
274 case '9': // 1 string to match.
275 if (memcmp(Name.data()+3, ":r18", 4) != 0)
276 break;
277 return AVR::R19R18; // "r19:r18"
278 }
279 break;
280 case '2': // 9 strings to match.
281 switch (Name[2]) {
282 default: break;
283 case '0': // 1 string to match.
284 if (memcmp(Name.data()+3, ":r19", 4) != 0)
285 break;
286 return AVR::R20R19; // "r20:r19"
287 case '1': // 1 string to match.
288 if (memcmp(Name.data()+3, ":r20", 4) != 0)
289 break;
290 return AVR::R21R20; // "r21:r20"
291 case '2': // 1 string to match.
292 if (memcmp(Name.data()+3, ":r21", 4) != 0)
293 break;
294 return AVR::R22R21; // "r22:r21"
295 case '3': // 1 string to match.
296 if (memcmp(Name.data()+3, ":r22", 4) != 0)
297 break;
298 return AVR::R23R22; // "r23:r22"
299 case '4': // 1 string to match.
300 if (memcmp(Name.data()+3, ":r23", 4) != 0)
301 break;
302 return AVR::R24R23; // "r24:r23"
303 case '5': // 1 string to match.
304 if (memcmp(Name.data()+3, ":r24", 4) != 0)
305 break;
306 return AVR::R25R24; // "r25:r24"
307 case '6': // 1 string to match.
308 if (memcmp(Name.data()+3, ":r25", 4) != 0)
309 break;
310 return AVR::R26R25; // "r26:r25"
311 case '7': // 1 string to match.
312 if (memcmp(Name.data()+3, ":r26", 4) != 0)
313 break;
314 return AVR::R27R26; // "r27:r26"
315 case '9': // 1 string to match.
316 if (memcmp(Name.data()+3, ":r28", 4) != 0)
317 break;
318 return AVR::R29R28; // "r29:r28"
319 }
320 break;
321 case '3': // 1 string to match.
322 if (memcmp(Name.data()+2, "1:r30", 5) != 0)
323 break;
324 return AVR::R31R30; // "r31:r30"
325 }
326 break;
327 }
328 return AVR::NoRegister;
329}
330
331static MCRegister MatchRegisterAltName(StringRef Name) {
332 switch (Name.size()) {
333 default: break;
334 case 1: // 3 strings to match.
335 switch (Name[0]) {
336 default: break;
337 case 'X': // 1 string to match.
338 return AVR::R27R26; // "X"
339 case 'Y': // 1 string to match.
340 return AVR::R29R28; // "Y"
341 case 'Z': // 1 string to match.
342 return AVR::R31R30; // "Z"
343 }
344 break;
345 case 2: // 6 strings to match.
346 switch (Name[0]) {
347 default: break;
348 case 'x': // 2 strings to match.
349 switch (Name[1]) {
350 default: break;
351 case 'h': // 1 string to match.
352 return AVR::R27; // "xh"
353 case 'l': // 1 string to match.
354 return AVR::R26; // "xl"
355 }
356 break;
357 case 'y': // 2 strings to match.
358 switch (Name[1]) {
359 default: break;
360 case 'h': // 1 string to match.
361 return AVR::R29; // "yh"
362 case 'l': // 1 string to match.
363 return AVR::R28; // "yl"
364 }
365 break;
366 case 'z': // 2 strings to match.
367 switch (Name[1]) {
368 default: break;
369 case 'h': // 1 string to match.
370 return AVR::R31; // "zh"
371 case 'l': // 1 string to match.
372 return AVR::R30; // "zl"
373 }
374 break;
375 }
376 break;
377 }
378 return AVR::NoRegister;
379}
380
381#endif // GET_REGISTER_MATCHER
382
383
384#ifdef GET_SUBTARGET_FEATURE_NAME
385#undef GET_SUBTARGET_FEATURE_NAME
386
387// User-level names for subtarget features that participate in
388// instruction matching.
389static const char *getSubtargetFeatureName(uint64_t Val) {
390 switch(Val) {
391 case Feature_HasSRAMBit: return "";
392 case Feature_HasJMPCALLBit: return "";
393 case Feature_HasIJMPCALLBit: return "";
394 case Feature_HasEIJMPCALLBit: return "";
395 case Feature_HasADDSUBIWBit: return "";
396 case Feature_HasSmallStackBit: return "";
397 case Feature_HasMOVWBit: return "";
398 case Feature_HasLPMBit: return "";
399 case Feature_HasLPMXBit: return "";
400 case Feature_HasELPMBit: return "";
401 case Feature_HasELPMXBit: return "";
402 case Feature_HasSPMBit: return "";
403 case Feature_HasSPMXBit: return "";
404 case Feature_HasDESBit: return "";
405 case Feature_SupportsRMWBit: return "";
406 case Feature_SupportsMultiplicationBit: return "";
407 case Feature_HasBREAKBit: return "";
408 case Feature_HasTinyEncodingBit: return "";
409 case Feature_HasNonTinyEncodingBit: return "";
410 default: return "(unknown)";
411 }
412}
413
414#endif // GET_SUBTARGET_FEATURE_NAME
415
416
417#ifdef GET_MATCHER_IMPLEMENTATION
418#undef GET_MATCHER_IMPLEMENTATION
419
420enum {
421 Tie0_1_1,
422 Tie0_2_2,
423 Tie1_2_2,
424 Tie1_3_3,
425};
426
427static const uint8_t TiedAsmOperandTable[][3] = {
428 /* Tie0_1_1 */ { 0, 1, 1 },
429 /* Tie0_2_2 */ { 0, 2, 2 },
430 /* Tie1_2_2 */ { 1, 2, 2 },
431 /* Tie1_3_3 */ { 1, 3, 3 },
432};
433
434namespace {
435enum OperatorConversionKind {
436 CVT_Done,
437 CVT_Reg,
438 CVT_Tied,
439 CVT_95_Reg,
440 CVT_95_addImmOperands,
441 CVT_imm_95_0,
442 CVT_imm_95_5,
443 CVT_imm_95_7,
444 CVT_imm_95_6,
445 CVT_imm_95_3,
446 CVT_95_addImmCom8Operands,
447 CVT_imm_95_2,
448 CVT_imm_95_4,
449 CVT_imm_95_1,
450 CVT_95_addRegOperands,
451 CVT_95_addMemriOperands,
452 CVT_imm_95_255,
453 CVT_NUM_CONVERTERS
454};
455
456enum InstructionConversionKind {
457 Convert__Reg1_0__Tie0_1_1__Reg1_1,
458 Convert__Reg1_0__Tie0_1_1__Imm1_1,
459 Convert__Reg1_0__Tie0_1_1,
460 Convert__Imm1_0,
461 Convert__Imm1_0__Imm1_1,
462 Convert__imm_95_0__Imm1_0,
463 Convert_NoOperands,
464 Convert__imm_95_5__Imm1_0,
465 Convert__imm_95_7__Imm1_0,
466 Convert__imm_95_6__Imm1_0,
467 Convert__imm_95_3__Imm1_0,
468 Convert__Reg1_0__Imm1_1,
469 Convert__Reg1_0__Tie0_1_1__ImmCom81_1,
470 Convert__imm_95_0,
471 Convert__imm_95_5,
472 Convert__imm_95_7,
473 Convert__imm_95_2,
474 Convert__Reg1_0__Tie0_1_1__Reg1_0,
475 Convert__imm_95_4,
476 Convert__imm_95_6,
477 Convert__imm_95_3,
478 Convert__imm_95_1,
479 Convert__Reg1_0__Reg1_1,
480 Convert__Reg1_1__Reg1_0,
481 Convert__Reg1_0__Reg1_2__Tie1_3_3,
482 Convert__Reg1_0__Reg1_1__Tie1_2_2,
483 Convert__Reg1_0__Memri2_1,
484 Convert__Imm1_0__Reg1_1,
485 Convert__Reg1_0,
486 Convert__Reg1_0__imm_95_255,
487 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0,
488 Convert__Reg1_0__Tie0_1_1__Reg1_2__imm_95_0,
489 Convert__Memri2_0__Reg1_1,
490 CVT_NUM_SIGNATURES
491};
492
493} // end anonymous namespace
494
495static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = {
496 // Convert__Reg1_0__Tie0_1_1__Reg1_1
497 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
498 // Convert__Reg1_0__Tie0_1_1__Imm1_1
499 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
500 // Convert__Reg1_0__Tie0_1_1
501 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
502 // Convert__Imm1_0
503 { CVT_95_addImmOperands, 1, CVT_Done },
504 // Convert__Imm1_0__Imm1_1
505 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
506 // Convert__imm_95_0__Imm1_0
507 { CVT_imm_95_0, 0, CVT_95_addImmOperands, 1, CVT_Done },
508 // Convert_NoOperands
509 { CVT_Done },
510 // Convert__imm_95_5__Imm1_0
511 { CVT_imm_95_5, 0, CVT_95_addImmOperands, 1, CVT_Done },
512 // Convert__imm_95_7__Imm1_0
513 { CVT_imm_95_7, 0, CVT_95_addImmOperands, 1, CVT_Done },
514 // Convert__imm_95_6__Imm1_0
515 { CVT_imm_95_6, 0, CVT_95_addImmOperands, 1, CVT_Done },
516 // Convert__imm_95_3__Imm1_0
517 { CVT_imm_95_3, 0, CVT_95_addImmOperands, 1, CVT_Done },
518 // Convert__Reg1_0__Imm1_1
519 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
520 // Convert__Reg1_0__Tie0_1_1__ImmCom81_1
521 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmCom8Operands, 2, CVT_Done },
522 // Convert__imm_95_0
523 { CVT_imm_95_0, 0, CVT_Done },
524 // Convert__imm_95_5
525 { CVT_imm_95_5, 0, CVT_Done },
526 // Convert__imm_95_7
527 { CVT_imm_95_7, 0, CVT_Done },
528 // Convert__imm_95_2
529 { CVT_imm_95_2, 0, CVT_Done },
530 // Convert__Reg1_0__Tie0_1_1__Reg1_0
531 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 1, CVT_Done },
532 // Convert__imm_95_4
533 { CVT_imm_95_4, 0, CVT_Done },
534 // Convert__imm_95_6
535 { CVT_imm_95_6, 0, CVT_Done },
536 // Convert__imm_95_3
537 { CVT_imm_95_3, 0, CVT_Done },
538 // Convert__imm_95_1
539 { CVT_imm_95_1, 0, CVT_Done },
540 // Convert__Reg1_0__Reg1_1
541 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
542 // Convert__Reg1_1__Reg1_0
543 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
544 // Convert__Reg1_0__Reg1_2__Tie1_3_3
545 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_Tied, Tie1_3_3, CVT_Done },
546 // Convert__Reg1_0__Reg1_1__Tie1_2_2
547 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie1_2_2, CVT_Done },
548 // Convert__Reg1_0__Memri2_1
549 { CVT_95_Reg, 1, CVT_95_addMemriOperands, 2, CVT_Done },
550 // Convert__Imm1_0__Reg1_1
551 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_Done },
552 // Convert__Reg1_0
553 { CVT_95_Reg, 1, CVT_Done },
554 // Convert__Reg1_0__imm_95_255
555 { CVT_95_Reg, 1, CVT_imm_95_255, 0, CVT_Done },
556 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0
557 { CVT_95_addRegOperands, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
558 // Convert__Reg1_0__Tie0_1_1__Reg1_2__imm_95_0
559 { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
560 // Convert__Memri2_0__Reg1_1
561 { CVT_95_addMemriOperands, 1, CVT_95_Reg, 2, CVT_Done },
562};
563
564void AVRAsmParser::
565convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
566 const OperandVector &Operands) {
567 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
568 const uint8_t *Converter = ConversionTable[Kind];
569 Inst.setOpcode(Opcode);
570 for (const uint8_t *p = Converter; *p; p += 2) {
571 unsigned OpIdx = *(p + 1);
572 switch (*p) {
573 default: llvm_unreachable("invalid conversion entry!");
574 case CVT_Reg:
575 static_cast<AVROperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
576 break;
577 case CVT_Tied: {
578 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
579 std::begin(TiedAsmOperandTable)) &&
580 "Tied operand not found");
581 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
582 if (TiedResOpnd != (uint8_t)-1)
583 Inst.addOperand(Inst.getOperand(TiedResOpnd));
584 break;
585 }
586 case CVT_95_Reg:
587 static_cast<AVROperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
588 break;
589 case CVT_95_addImmOperands:
590 static_cast<AVROperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
591 break;
592 case CVT_imm_95_0:
593 Inst.addOperand(MCOperand::createImm(0));
594 break;
595 case CVT_imm_95_5:
596 Inst.addOperand(MCOperand::createImm(5));
597 break;
598 case CVT_imm_95_7:
599 Inst.addOperand(MCOperand::createImm(7));
600 break;
601 case CVT_imm_95_6:
602 Inst.addOperand(MCOperand::createImm(6));
603 break;
604 case CVT_imm_95_3:
605 Inst.addOperand(MCOperand::createImm(3));
606 break;
607 case CVT_95_addImmCom8Operands:
608 static_cast<AVROperand &>(*Operands[OpIdx]).addImmCom8Operands(Inst, 1);
609 break;
610 case CVT_imm_95_2:
611 Inst.addOperand(MCOperand::createImm(2));
612 break;
613 case CVT_imm_95_4:
614 Inst.addOperand(MCOperand::createImm(4));
615 break;
616 case CVT_imm_95_1:
617 Inst.addOperand(MCOperand::createImm(1));
618 break;
619 case CVT_95_addRegOperands:
620 static_cast<AVROperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
621 break;
622 case CVT_95_addMemriOperands:
623 static_cast<AVROperand &>(*Operands[OpIdx]).addMemriOperands(Inst, 2);
624 break;
625 case CVT_imm_95_255:
626 Inst.addOperand(MCOperand::createImm(255));
627 break;
628 }
629 }
630}
631
632void AVRAsmParser::
633convertToMapAndConstraints(unsigned Kind,
634 const OperandVector &Operands) {
635 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
636 unsigned NumMCOperands = 0;
637 const uint8_t *Converter = ConversionTable[Kind];
638 for (const uint8_t *p = Converter; *p; p += 2) {
639 switch (*p) {
640 default: llvm_unreachable("invalid conversion entry!");
641 case CVT_Reg:
642 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
643 Operands[*(p + 1)]->setConstraint("r");
644 ++NumMCOperands;
645 break;
646 case CVT_Tied:
647 ++NumMCOperands;
648 break;
649 case CVT_95_Reg:
650 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
651 Operands[*(p + 1)]->setConstraint("r");
652 NumMCOperands += 1;
653 break;
654 case CVT_95_addImmOperands:
655 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
656 Operands[*(p + 1)]->setConstraint("m");
657 NumMCOperands += 1;
658 break;
659 case CVT_imm_95_0:
660 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
661 Operands[*(p + 1)]->setConstraint("");
662 ++NumMCOperands;
663 break;
664 case CVT_imm_95_5:
665 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
666 Operands[*(p + 1)]->setConstraint("");
667 ++NumMCOperands;
668 break;
669 case CVT_imm_95_7:
670 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
671 Operands[*(p + 1)]->setConstraint("");
672 ++NumMCOperands;
673 break;
674 case CVT_imm_95_6:
675 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
676 Operands[*(p + 1)]->setConstraint("");
677 ++NumMCOperands;
678 break;
679 case CVT_imm_95_3:
680 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
681 Operands[*(p + 1)]->setConstraint("");
682 ++NumMCOperands;
683 break;
684 case CVT_95_addImmCom8Operands:
685 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
686 Operands[*(p + 1)]->setConstraint("m");
687 NumMCOperands += 1;
688 break;
689 case CVT_imm_95_2:
690 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
691 Operands[*(p + 1)]->setConstraint("");
692 ++NumMCOperands;
693 break;
694 case CVT_imm_95_4:
695 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
696 Operands[*(p + 1)]->setConstraint("");
697 ++NumMCOperands;
698 break;
699 case CVT_imm_95_1:
700 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
701 Operands[*(p + 1)]->setConstraint("");
702 ++NumMCOperands;
703 break;
704 case CVT_95_addRegOperands:
705 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
706 Operands[*(p + 1)]->setConstraint("m");
707 NumMCOperands += 1;
708 break;
709 case CVT_95_addMemriOperands:
710 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
711 Operands[*(p + 1)]->setConstraint("m");
712 NumMCOperands += 2;
713 break;
714 case CVT_imm_95_255:
715 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
716 Operands[*(p + 1)]->setConstraint("");
717 ++NumMCOperands;
718 break;
719 }
720 }
721}
722
723namespace {
724
725/// MatchClassKind - The kinds of classes which participate in
726/// instruction matching.
727enum MatchClassKind {
728 InvalidMatchClass = 0,
729 OptionalMatchClass = 1,
730 MCK__43_, // '+'
731 MCK__MINUS_, // '-'
732 MCK_LAST_TOKEN = MCK__MINUS_,
733 MCK_Reg21, // derived register class
734 MCK_CCR, // register class 'CCR'
735 MCK_GPRSP, // register class 'GPRSP'
736 MCK_ZREG, // register class 'ZREG'
737 MCK_PTRDISPREGS, // register class 'PTRDISPREGS'
738 MCK_PTRREGS, // register class 'PTRREGS'
739 MCK_DREGSLD8lo, // register class 'DREGSLD8lo'
740 MCK_IWREGS, // register class 'IWREGS'
741 MCK_Reg16, // derived register class
742 MCK_Reg17, // derived register class
743 MCK_Reg15, // derived register class
744 MCK_DLDREGS, // register class 'DLDREGS'
745 MCK_DREGSlo, // register class 'DREGSlo'
746 MCK_LD8lo, // register class 'LD8lo'
747 MCK_Reg20, // derived register class
748 MCK_Reg19, // derived register class
749 MCK_Reg12, // derived register class
750 MCK_Reg13, // derived register class
751 MCK_DREGSMOVW, // register class 'DREGSMOVW'
752 MCK_GPR8lo, // register class 'GPR8lo'
753 MCK_LD8, // register class 'LD8'
754 MCK_DREGS, // register class 'DREGS'
755 MCK_GPR8, // register class 'GPR8'
756 MCK_LAST_REGISTER = MCK_GPR8,
757 MCK_Imm, // user defined class 'ImmAsmOperand'
758 MCK_Memri, // user defined class 'MemriAsmOperand'
759 MCK_Reg, // user defined class 'PtrRegAsmOperand'
760 MCK_ImmCom8, // user defined class 'imm_com8_asmoperand'
761 NumMatchClassKinds
762};
763
764} // end anonymous namespace
765
766static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
767 return MCTargetAsmParser::Match_InvalidOperand;
768}
769
770static MatchClassKind matchTokenString(StringRef Name) {
771 switch (Name.size()) {
772 default: break;
773 case 1: // 2 strings to match.
774 switch (Name[0]) {
775 default: break;
776 case '+': // 1 string to match.
777 return MCK__43_; // "+"
778 case '-': // 1 string to match.
779 return MCK__MINUS_; // "-"
780 }
781 break;
782 }
783 return InvalidMatchClass;
784}
785
786/// isSubclass - Compute whether \p A is a subclass of \p B.
787static bool isSubclass(MatchClassKind A, MatchClassKind B) {
788 if (A == B)
789 return true;
790
791 switch (A) {
792 default:
793 return false;
794
795 case MCK_Reg21:
796 switch (B) {
797 default: return false;
798 case MCK_Reg17: return true;
799 case MCK_Reg19: return true;
800 case MCK_Reg13: return true;
801 case MCK_DREGS: return true;
802 }
803
804 case MCK_ZREG:
805 switch (B) {
806 default: return false;
807 case MCK_PTRDISPREGS: return true;
808 case MCK_PTRREGS: return true;
809 case MCK_IWREGS: return true;
810 case MCK_DLDREGS: return true;
811 case MCK_Reg12: return true;
812 case MCK_Reg13: return true;
813 case MCK_DREGSMOVW: return true;
814 case MCK_DREGS: return true;
815 }
816
817 case MCK_PTRDISPREGS:
818 switch (B) {
819 default: return false;
820 case MCK_PTRREGS: return true;
821 case MCK_IWREGS: return true;
822 case MCK_DLDREGS: return true;
823 case MCK_Reg12: return true;
824 case MCK_Reg13: return true;
825 case MCK_DREGSMOVW: return true;
826 case MCK_DREGS: return true;
827 }
828
829 case MCK_PTRREGS:
830 switch (B) {
831 default: return false;
832 case MCK_IWREGS: return true;
833 case MCK_DLDREGS: return true;
834 case MCK_Reg12: return true;
835 case MCK_Reg13: return true;
836 case MCK_DREGSMOVW: return true;
837 case MCK_DREGS: return true;
838 }
839
840 case MCK_DREGSLD8lo:
841 switch (B) {
842 default: return false;
843 case MCK_Reg16: return true;
844 case MCK_Reg17: return true;
845 case MCK_Reg15: return true;
846 case MCK_DLDREGS: return true;
847 case MCK_Reg12: return true;
848 case MCK_Reg13: return true;
849 case MCK_DREGSMOVW: return true;
850 case MCK_DREGS: return true;
851 }
852
853 case MCK_IWREGS:
854 switch (B) {
855 default: return false;
856 case MCK_DLDREGS: return true;
857 case MCK_Reg12: return true;
858 case MCK_Reg13: return true;
859 case MCK_DREGSMOVW: return true;
860 case MCK_DREGS: return true;
861 }
862
863 case MCK_Reg16:
864 switch (B) {
865 default: return false;
866 case MCK_Reg17: return true;
867 case MCK_Reg15: return true;
868 case MCK_Reg12: return true;
869 case MCK_Reg13: return true;
870 case MCK_DREGS: return true;
871 }
872
873 case MCK_Reg17:
874 switch (B) {
875 default: return false;
876 case MCK_Reg13: return true;
877 case MCK_DREGS: return true;
878 }
879
880 case MCK_Reg15:
881 switch (B) {
882 default: return false;
883 case MCK_Reg12: return true;
884 case MCK_Reg13: return true;
885 case MCK_DREGS: return true;
886 }
887
888 case MCK_DLDREGS:
889 switch (B) {
890 default: return false;
891 case MCK_Reg12: return true;
892 case MCK_Reg13: return true;
893 case MCK_DREGSMOVW: return true;
894 case MCK_DREGS: return true;
895 }
896
897 case MCK_DREGSlo:
898 switch (B) {
899 default: return false;
900 case MCK_Reg20: return true;
901 case MCK_Reg19: return true;
902 case MCK_DREGSMOVW: return true;
903 case MCK_DREGS: return true;
904 }
905
906 case MCK_LD8lo:
907 switch (B) {
908 default: return false;
909 case MCK_LD8: return true;
910 case MCK_GPR8: return true;
911 }
912
913 case MCK_Reg20:
914 switch (B) {
915 default: return false;
916 case MCK_Reg19: return true;
917 case MCK_DREGS: return true;
918 }
919
920 case MCK_Reg19:
921 return B == MCK_DREGS;
922
923 case MCK_Reg12:
924 switch (B) {
925 default: return false;
926 case MCK_Reg13: return true;
927 case MCK_DREGS: return true;
928 }
929
930 case MCK_Reg13:
931 return B == MCK_DREGS;
932
933 case MCK_DREGSMOVW:
934 return B == MCK_DREGS;
935
936 case MCK_GPR8lo:
937 return B == MCK_GPR8;
938
939 case MCK_LD8:
940 return B == MCK_GPR8;
941 }
942}
943
944static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
945 AVROperand &Operand = (AVROperand &)GOp;
946 if (Kind == InvalidMatchClass)
947 return MCTargetAsmParser::Match_InvalidOperand;
948
949 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
950 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
951 MCTargetAsmParser::Match_Success :
952 MCTargetAsmParser::Match_InvalidOperand;
953
954 switch (Kind) {
955 default: break;
956 // 'Imm' class
957 case MCK_Imm: {
958 DiagnosticPredicate DP(Operand.isImm());
959 if (DP.isMatch())
960 return MCTargetAsmParser::Match_Success;
961 break;
962 }
963 // 'Memri' class
964 case MCK_Memri: {
965 DiagnosticPredicate DP(Operand.isMemri());
966 if (DP.isMatch())
967 return MCTargetAsmParser::Match_Success;
968 break;
969 }
970 // 'Reg' class
971 case MCK_Reg: {
972 DiagnosticPredicate DP(Operand.isReg());
973 if (DP.isMatch())
974 return MCTargetAsmParser::Match_Success;
975 break;
976 }
977 // 'ImmCom8' class
978 case MCK_ImmCom8: {
979 DiagnosticPredicate DP(Operand.isImmCom8());
980 if (DP.isMatch())
981 return MCTargetAsmParser::Match_Success;
982 break;
983 }
984 } // end switch (Kind)
985
986 if (Operand.isReg()) {
987 MatchClassKind OpKind;
988 switch (Operand.getReg().id()) {
989 default: OpKind = InvalidMatchClass; break;
990 case AVR::R0: OpKind = MCK_GPR8lo; break;
991 case AVR::R1: OpKind = MCK_GPR8lo; break;
992 case AVR::R2: OpKind = MCK_GPR8lo; break;
993 case AVR::R3: OpKind = MCK_GPR8lo; break;
994 case AVR::R4: OpKind = MCK_GPR8lo; break;
995 case AVR::R5: OpKind = MCK_GPR8lo; break;
996 case AVR::R6: OpKind = MCK_GPR8lo; break;
997 case AVR::R7: OpKind = MCK_GPR8lo; break;
998 case AVR::R8: OpKind = MCK_GPR8lo; break;
999 case AVR::R9: OpKind = MCK_GPR8lo; break;
1000 case AVR::R10: OpKind = MCK_GPR8lo; break;
1001 case AVR::R11: OpKind = MCK_GPR8lo; break;
1002 case AVR::R12: OpKind = MCK_GPR8lo; break;
1003 case AVR::R13: OpKind = MCK_GPR8lo; break;
1004 case AVR::R14: OpKind = MCK_GPR8lo; break;
1005 case AVR::R15: OpKind = MCK_GPR8lo; break;
1006 case AVR::R16: OpKind = MCK_LD8lo; break;
1007 case AVR::R17: OpKind = MCK_LD8lo; break;
1008 case AVR::R18: OpKind = MCK_LD8lo; break;
1009 case AVR::R19: OpKind = MCK_LD8lo; break;
1010 case AVR::R20: OpKind = MCK_LD8lo; break;
1011 case AVR::R21: OpKind = MCK_LD8lo; break;
1012 case AVR::R22: OpKind = MCK_LD8lo; break;
1013 case AVR::R23: OpKind = MCK_LD8lo; break;
1014 case AVR::R24: OpKind = MCK_LD8; break;
1015 case AVR::R25: OpKind = MCK_LD8; break;
1016 case AVR::R26: OpKind = MCK_LD8; break;
1017 case AVR::R27: OpKind = MCK_LD8; break;
1018 case AVR::R28: OpKind = MCK_LD8; break;
1019 case AVR::R29: OpKind = MCK_LD8; break;
1020 case AVR::R30: OpKind = MCK_LD8; break;
1021 case AVR::R31: OpKind = MCK_LD8; break;
1022 case AVR::SP: OpKind = MCK_GPRSP; break;
1023 case AVR::R31R30: OpKind = MCK_ZREG; break;
1024 case AVR::R29R28: OpKind = MCK_PTRDISPREGS; break;
1025 case AVR::R27R26: OpKind = MCK_PTRREGS; break;
1026 case AVR::R25R24: OpKind = MCK_IWREGS; break;
1027 case AVR::R23R22: OpKind = MCK_DREGSLD8lo; break;
1028 case AVR::R21R20: OpKind = MCK_DREGSLD8lo; break;
1029 case AVR::R19R18: OpKind = MCK_DREGSLD8lo; break;
1030 case AVR::R17R16: OpKind = MCK_DREGSLD8lo; break;
1031 case AVR::R15R14: OpKind = MCK_DREGSlo; break;
1032 case AVR::R13R12: OpKind = MCK_DREGSlo; break;
1033 case AVR::R11R10: OpKind = MCK_DREGSlo; break;
1034 case AVR::R9R8: OpKind = MCK_DREGSlo; break;
1035 case AVR::R7R6: OpKind = MCK_DREGSlo; break;
1036 case AVR::R5R4: OpKind = MCK_DREGSlo; break;
1037 case AVR::R3R2: OpKind = MCK_DREGSlo; break;
1038 case AVR::R1R0: OpKind = MCK_DREGSlo; break;
1039 case AVR::R26R25: OpKind = MCK_Reg12; break;
1040 case AVR::R24R23: OpKind = MCK_Reg15; break;
1041 case AVR::R22R21: OpKind = MCK_Reg16; break;
1042 case AVR::R20R19: OpKind = MCK_Reg16; break;
1043 case AVR::R18R17: OpKind = MCK_Reg16; break;
1044 case AVR::R16R15: OpKind = MCK_Reg21; break;
1045 case AVR::R14R13: OpKind = MCK_Reg20; break;
1046 case AVR::R12R11: OpKind = MCK_Reg20; break;
1047 case AVR::R10R9: OpKind = MCK_Reg20; break;
1048 case AVR::SREG: OpKind = MCK_CCR; break;
1049 }
1050 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
1051 getDiagKindFromRegisterClass(Kind);
1052 }
1053
1054 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
1055 return getDiagKindFromRegisterClass(Kind);
1056
1057 return MCTargetAsmParser::Match_InvalidOperand;
1058}
1059
1060#ifndef NDEBUG
1061const char *getMatchClassName(MatchClassKind Kind) {
1062 switch (Kind) {
1063 case InvalidMatchClass: return "InvalidMatchClass";
1064 case OptionalMatchClass: return "OptionalMatchClass";
1065 case MCK__43_: return "MCK__43_";
1066 case MCK__MINUS_: return "MCK__MINUS_";
1067 case MCK_Reg21: return "MCK_Reg21";
1068 case MCK_CCR: return "MCK_CCR";
1069 case MCK_GPRSP: return "MCK_GPRSP";
1070 case MCK_ZREG: return "MCK_ZREG";
1071 case MCK_PTRDISPREGS: return "MCK_PTRDISPREGS";
1072 case MCK_PTRREGS: return "MCK_PTRREGS";
1073 case MCK_DREGSLD8lo: return "MCK_DREGSLD8lo";
1074 case MCK_IWREGS: return "MCK_IWREGS";
1075 case MCK_Reg16: return "MCK_Reg16";
1076 case MCK_Reg17: return "MCK_Reg17";
1077 case MCK_Reg15: return "MCK_Reg15";
1078 case MCK_DLDREGS: return "MCK_DLDREGS";
1079 case MCK_DREGSlo: return "MCK_DREGSlo";
1080 case MCK_LD8lo: return "MCK_LD8lo";
1081 case MCK_Reg20: return "MCK_Reg20";
1082 case MCK_Reg19: return "MCK_Reg19";
1083 case MCK_Reg12: return "MCK_Reg12";
1084 case MCK_Reg13: return "MCK_Reg13";
1085 case MCK_DREGSMOVW: return "MCK_DREGSMOVW";
1086 case MCK_GPR8lo: return "MCK_GPR8lo";
1087 case MCK_LD8: return "MCK_LD8";
1088 case MCK_DREGS: return "MCK_DREGS";
1089 case MCK_GPR8: return "MCK_GPR8";
1090 case MCK_Imm: return "MCK_Imm";
1091 case MCK_Memri: return "MCK_Memri";
1092 case MCK_Reg: return "MCK_Reg";
1093 case MCK_ImmCom8: return "MCK_ImmCom8";
1094 case NumMatchClassKinds: return "NumMatchClassKinds";
1095 }
1096 llvm_unreachable("unhandled MatchClassKind!");
1097}
1098
1099#endif // NDEBUG
1100FeatureBitset AVRAsmParser::
1101ComputeAvailableFeatures(const FeatureBitset &FB) const {
1102 FeatureBitset Features;
1103 if (FB[AVR::FeatureSRAM])
1104 Features.set(Feature_HasSRAMBit);
1105 if (FB[AVR::FeatureJMPCALL])
1106 Features.set(Feature_HasJMPCALLBit);
1107 if (FB[AVR::FeatureIJMPCALL])
1108 Features.set(Feature_HasIJMPCALLBit);
1109 if (FB[AVR::FeatureEIJMPCALL])
1110 Features.set(Feature_HasEIJMPCALLBit);
1111 if (FB[AVR::FeatureADDSUBIW])
1112 Features.set(Feature_HasADDSUBIWBit);
1113 if (FB[AVR::FeatureSmallStack])
1114 Features.set(Feature_HasSmallStackBit);
1115 if (FB[AVR::FeatureMOVW])
1116 Features.set(Feature_HasMOVWBit);
1117 if (FB[AVR::FeatureLPM])
1118 Features.set(Feature_HasLPMBit);
1119 if (FB[AVR::FeatureLPMX])
1120 Features.set(Feature_HasLPMXBit);
1121 if (FB[AVR::FeatureELPM])
1122 Features.set(Feature_HasELPMBit);
1123 if (FB[AVR::FeatureELPMX])
1124 Features.set(Feature_HasELPMXBit);
1125 if (FB[AVR::FeatureSPM])
1126 Features.set(Feature_HasSPMBit);
1127 if (FB[AVR::FeatureSPMX])
1128 Features.set(Feature_HasSPMXBit);
1129 if (FB[AVR::FeatureDES])
1130 Features.set(Feature_HasDESBit);
1131 if (FB[AVR::FeatureRMW])
1132 Features.set(Feature_SupportsRMWBit);
1133 if (FB[AVR::FeatureMultiplication])
1134 Features.set(Feature_SupportsMultiplicationBit);
1135 if (FB[AVR::FeatureBREAK])
1136 Features.set(Feature_HasBREAKBit);
1137 if (FB[AVR::FeatureTinyEncoding])
1138 Features.set(Feature_HasTinyEncodingBit);
1139 if (!FB[AVR::FeatureTinyEncoding])
1140 Features.set(Feature_HasNonTinyEncodingBit);
1141 return Features;
1142}
1143
1144static bool checkAsmTiedOperandConstraints(const AVRAsmParser&AsmParser,
1145 unsigned Kind, const OperandVector &Operands,
1146 uint64_t &ErrorInfo) {
1147 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1148 const uint8_t *Converter = ConversionTable[Kind];
1149 for (const uint8_t *p = Converter; *p; p += 2) {
1150 switch (*p) {
1151 case CVT_Tied: {
1152 unsigned OpIdx = *(p + 1);
1153 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
1154 std::begin(TiedAsmOperandTable)) &&
1155 "Tied operand not found");
1156 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
1157 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
1158 if (OpndNum1 != OpndNum2) {
1159 auto &SrcOp1 = Operands[OpndNum1];
1160 auto &SrcOp2 = Operands[OpndNum2];
1161 if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
1162 ErrorInfo = OpndNum2;
1163 return false;
1164 }
1165 }
1166 break;
1167 }
1168 default:
1169 break;
1170 }
1171 }
1172 return true;
1173}
1174
1175static const char MnemonicTable[] =
1176 "\003adc\003add\004adiw\003and\004andi\003asr\004bclr\003bld\004brbc\004"
1177 "brbs\004brcc\004brcs\005break\004breq\004brge\004brhc\004brhs\004brid\004"
1178 "brie\004brlo\004brlt\004brmi\004brne\004brpl\004brsh\004brtc\004brts\004"
1179 "brvc\004brvs\004bset\003bst\004call\003cbi\003cbr\003clc\003clh\003cli\003"
1180 "cln\003clr\003cls\003clt\003clv\003clz\003com\002cp\003cpc\003cpi\004cp"
1181 "se\003dec\003des\006eicall\005eijmp\004elpm\003eor\004fmul\005fmuls\006"
1182 "fmulsu\005icall\004ijmp\002in\003inc\003jmp\003lac\003las\003lat\002ld\003"
1183 "ldd\003ldi\003lds\003lpm\003lsl\003lsr\003mov\004movw\003mul\004muls\005"
1184 "mulsu\003neg\003nop\002or\003ori\003out\003pop\004push\005rcall\003ret\004"
1185 "reti\004rjmp\003rol\003ror\003sbc\004sbci\003sbi\004sbic\004sbis\004sbi"
1186 "w\003sbr\004sbrc\004sbrs\003sec\003seh\003sei\003sen\003ser\003ses\003s"
1187 "et\003sev\003sez\005sleep\003spm\002st\003std\003sts\003sub\004subi\004"
1188 "swap\003tst\003wdr\003xch";
1189
1190// Feature bitsets.
1191enum : uint8_t {
1192 AMFBS_None,
1193 AMFBS_HasADDSUBIW,
1194 AMFBS_HasBREAK,
1195 AMFBS_HasDES,
1196 AMFBS_HasEIJMPCALL,
1197 AMFBS_HasELPM,
1198 AMFBS_HasELPMX,
1199 AMFBS_HasIJMPCALL,
1200 AMFBS_HasJMPCALL,
1201 AMFBS_HasLPM,
1202 AMFBS_HasLPMX,
1203 AMFBS_HasMOVW,
1204 AMFBS_HasSPM,
1205 AMFBS_HasSPMX,
1206 AMFBS_HasSRAM,
1207 AMFBS_SupportsMultiplication,
1208 AMFBS_SupportsRMW,
1209 AMFBS_HasSRAM_HasNonTinyEncoding,
1210 AMFBS_HasSRAM_HasTinyEncoding,
1211};
1212
1213static constexpr FeatureBitset FeatureBitsets[] = {
1214 {}, // AMFBS_None
1215 {Feature_HasADDSUBIWBit, },
1216 {Feature_HasBREAKBit, },
1217 {Feature_HasDESBit, },
1218 {Feature_HasEIJMPCALLBit, },
1219 {Feature_HasELPMBit, },
1220 {Feature_HasELPMXBit, },
1221 {Feature_HasIJMPCALLBit, },
1222 {Feature_HasJMPCALLBit, },
1223 {Feature_HasLPMBit, },
1224 {Feature_HasLPMXBit, },
1225 {Feature_HasMOVWBit, },
1226 {Feature_HasSPMBit, },
1227 {Feature_HasSPMXBit, },
1228 {Feature_HasSRAMBit, },
1229 {Feature_SupportsMultiplicationBit, },
1230 {Feature_SupportsRMWBit, },
1231 {Feature_HasSRAMBit, Feature_HasNonTinyEncodingBit, },
1232 {Feature_HasSRAMBit, Feature_HasTinyEncodingBit, },
1233};
1234
1235namespace {
1236 struct MatchEntry {
1237 uint16_t Mnemonic;
1238 uint16_t Opcode;
1239 uint8_t ConvertFn;
1240 uint8_t RequiredFeaturesIdx;
1241 uint8_t Classes[3];
1242 StringRef getMnemonic() const {
1243 return StringRef(MnemonicTable + Mnemonic + 1,
1244 MnemonicTable[Mnemonic]);
1245 }
1246 };
1247
1248 // Predicate for searching for an opcode.
1249 struct LessOpcode {
1250 bool operator()(const MatchEntry &LHS, StringRef RHS) {
1251 return LHS.getMnemonic() < RHS;
1252 }
1253 bool operator()(StringRef LHS, const MatchEntry &RHS) {
1254 return LHS < RHS.getMnemonic();
1255 }
1256 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
1257 return LHS.getMnemonic() < RHS.getMnemonic();
1258 }
1259 };
1260} // end anonymous namespace
1261
1262static const MatchEntry MatchTable0[] = {
1263 { 0 /* adc */, AVR::ADCRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1264 { 4 /* add */, AVR::ADDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1265 { 8 /* adiw */, AVR::ADIWRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_HasADDSUBIW, { MCK_IWREGS, MCK_Imm }, },
1266 { 13 /* and */, AVR::ANDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1267 { 17 /* andi */, AVR::ANDIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1268 { 22 /* asr */, AVR::ASRRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1269 { 26 /* bclr */, AVR::BCLRs, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1270 { 31 /* bld */, AVR::BLD, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1271 { 35 /* brbc */, AVR::BRBCsk, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1272 { 40 /* brbs */, AVR::BRBSsk, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1273 { 45 /* brcc */, AVR::BRBCsk, Convert__imm_95_0__Imm1_0, AMFBS_None, { MCK_Imm }, },
1274 { 50 /* brcs */, AVR::BRBSsk, Convert__imm_95_0__Imm1_0, AMFBS_None, { MCK_Imm }, },
1275 { 55 /* break */, AVR::BREAK, Convert_NoOperands, AMFBS_HasBREAK, { }, },
1276 { 61 /* breq */, AVR::BREQk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1277 { 66 /* brge */, AVR::BRGEk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1278 { 71 /* brhc */, AVR::BRBCsk, Convert__imm_95_5__Imm1_0, AMFBS_None, { MCK_Imm }, },
1279 { 76 /* brhs */, AVR::BRBSsk, Convert__imm_95_5__Imm1_0, AMFBS_None, { MCK_Imm }, },
1280 { 81 /* brid */, AVR::BRBCsk, Convert__imm_95_7__Imm1_0, AMFBS_None, { MCK_Imm }, },
1281 { 86 /* brie */, AVR::BRBSsk, Convert__imm_95_7__Imm1_0, AMFBS_None, { MCK_Imm }, },
1282 { 91 /* brlo */, AVR::BRLOk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1283 { 96 /* brlt */, AVR::BRLTk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1284 { 101 /* brmi */, AVR::BRMIk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1285 { 106 /* brne */, AVR::BRNEk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1286 { 111 /* brpl */, AVR::BRPLk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1287 { 116 /* brsh */, AVR::BRSHk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1288 { 121 /* brtc */, AVR::BRBCsk, Convert__imm_95_6__Imm1_0, AMFBS_None, { MCK_Imm }, },
1289 { 126 /* brts */, AVR::BRBSsk, Convert__imm_95_6__Imm1_0, AMFBS_None, { MCK_Imm }, },
1290 { 131 /* brvc */, AVR::BRBCsk, Convert__imm_95_3__Imm1_0, AMFBS_None, { MCK_Imm }, },
1291 { 136 /* brvs */, AVR::BRBSsk, Convert__imm_95_3__Imm1_0, AMFBS_None, { MCK_Imm }, },
1292 { 141 /* bset */, AVR::BSETs, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1293 { 146 /* bst */, AVR::BST, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1294 { 150 /* call */, AVR::CALLk, Convert__Imm1_0, AMFBS_HasJMPCALL, { MCK_Imm }, },
1295 { 155 /* cbi */, AVR::CBIAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1296 { 159 /* cbr */, AVR::ANDIRdK, Convert__Reg1_0__Tie0_1_1__ImmCom81_1, AMFBS_None, { MCK_LD8, MCK_ImmCom8 }, },
1297 { 163 /* clc */, AVR::BCLRs, Convert__imm_95_0, AMFBS_None, { }, },
1298 { 167 /* clh */, AVR::BCLRs, Convert__imm_95_5, AMFBS_None, { }, },
1299 { 171 /* cli */, AVR::BCLRs, Convert__imm_95_7, AMFBS_None, { }, },
1300 { 175 /* cln */, AVR::BCLRs, Convert__imm_95_2, AMFBS_None, { }, },
1301 { 179 /* clr */, AVR::EORRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1302 { 183 /* cls */, AVR::BCLRs, Convert__imm_95_4, AMFBS_None, { }, },
1303 { 187 /* clt */, AVR::BCLRs, Convert__imm_95_6, AMFBS_None, { }, },
1304 { 191 /* clv */, AVR::BCLRs, Convert__imm_95_3, AMFBS_None, { }, },
1305 { 195 /* clz */, AVR::BCLRs, Convert__imm_95_1, AMFBS_None, { }, },
1306 { 199 /* com */, AVR::COMRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1307 { 203 /* cp */, AVR::CPRdRr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1308 { 206 /* cpc */, AVR::CPCRdRr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1309 { 210 /* cpi */, AVR::CPIRdK, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1310 { 214 /* cpse */, AVR::CPSE, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1311 { 219 /* dec */, AVR::DECRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1312 { 223 /* des */, AVR::DESK, Convert__Imm1_0, AMFBS_HasDES, { MCK_Imm }, },
1313 { 227 /* eicall */, AVR::EICALL, Convert_NoOperands, AMFBS_HasEIJMPCALL, { }, },
1314 { 234 /* eijmp */, AVR::EIJMP, Convert_NoOperands, AMFBS_HasEIJMPCALL, { }, },
1315 { 240 /* elpm */, AVR::ELPM, Convert_NoOperands, AMFBS_HasELPM, { }, },
1316 { 240 /* elpm */, AVR::ELPMRdZ, Convert__Reg1_0__Reg1_1, AMFBS_HasELPMX, { MCK_GPR8, MCK_ZREG }, },
1317 { 240 /* elpm */, AVR::ELPMRdZPi, Convert__Reg1_0__Reg1_1, AMFBS_HasELPMX, { MCK_GPR8, MCK_ZREG, MCK__43_ }, },
1318 { 245 /* eor */, AVR::EORRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1319 { 249 /* fmul */, AVR::FMUL, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1320 { 254 /* fmuls */, AVR::FMULS, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1321 { 260 /* fmulsu */, AVR::FMULSU, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1322 { 267 /* icall */, AVR::ICALL, Convert_NoOperands, AMFBS_HasIJMPCALL, { }, },
1323 { 273 /* ijmp */, AVR::IJMP, Convert_NoOperands, AMFBS_HasIJMPCALL, { }, },
1324 { 278 /* in */, AVR::INRdA, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1325 { 281 /* inc */, AVR::INCRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1326 { 285 /* jmp */, AVR::JMPk, Convert__Imm1_0, AMFBS_HasJMPCALL, { MCK_Imm }, },
1327 { 289 /* lac */, AVR::LACZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1328 { 293 /* las */, AVR::LASZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1329 { 297 /* lat */, AVR::LATZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1330 { 301 /* ld */, AVR::LDRdPtr, Convert__Reg1_0__Reg1_1, AMFBS_HasSRAM, { MCK_GPR8, MCK_Reg }, },
1331 { 301 /* ld */, AVR::LDRdPtrPd, Convert__Reg1_0__Reg1_2__Tie1_3_3, AMFBS_HasSRAM, { MCK_GPR8, MCK__MINUS_, MCK_Reg }, },
1332 { 301 /* ld */, AVR::LDRdPtrPi, Convert__Reg1_0__Reg1_1__Tie1_2_2, AMFBS_HasSRAM, { MCK_GPR8, MCK_Reg, MCK__43_ }, },
1333 { 304 /* ldd */, AVR::LDDRdPtrQ, Convert__Reg1_0__Memri2_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_GPR8, MCK_Memri }, },
1334 { 308 /* ldi */, AVR::LDIRdK, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1335 { 312 /* lds */, AVR::LDSRdKTiny, Convert__Reg1_0__Imm1_1, AMFBS_HasSRAM_HasTinyEncoding, { MCK_LD8, MCK_Imm }, },
1336 { 312 /* lds */, AVR::LDSRdK, Convert__Reg1_0__Imm1_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_GPR8, MCK_Imm }, },
1337 { 316 /* lpm */, AVR::LPM, Convert_NoOperands, AMFBS_HasLPM, { }, },
1338 { 316 /* lpm */, AVR::LPMRdZ, Convert__Reg1_0__Reg1_1, AMFBS_HasLPMX, { MCK_GPR8, MCK_ZREG }, },
1339 { 316 /* lpm */, AVR::LPMRdZPi, Convert__Reg1_0__Reg1_1, AMFBS_HasLPMX, { MCK_GPR8, MCK_ZREG, MCK__43_ }, },
1340 { 320 /* lsl */, AVR::ADDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1341 { 324 /* lsr */, AVR::LSRRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1342 { 328 /* mov */, AVR::MOVRdRr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1343 { 332 /* movw */, AVR::MOVWRdRr, Convert__Reg1_0__Reg1_1, AMFBS_HasMOVW, { MCK_DREGS, MCK_DREGS }, },
1344 { 337 /* mul */, AVR::MULRdRr, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_GPR8, MCK_GPR8 }, },
1345 { 341 /* muls */, AVR::MULSRdRr, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8, MCK_LD8 }, },
1346 { 346 /* mulsu */, AVR::MULSURdRr, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1347 { 352 /* neg */, AVR::NEGRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1348 { 356 /* nop */, AVR::NOP, Convert_NoOperands, AMFBS_None, { }, },
1349 { 360 /* or */, AVR::ORRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1350 { 363 /* ori */, AVR::ORIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1351 { 367 /* out */, AVR::OUTARr, Convert__Imm1_0__Reg1_1, AMFBS_None, { MCK_Imm, MCK_GPR8 }, },
1352 { 371 /* pop */, AVR::POPRd, Convert__Reg1_0, AMFBS_HasSRAM, { MCK_GPR8 }, },
1353 { 375 /* push */, AVR::PUSHRr, Convert__Reg1_0, AMFBS_HasSRAM, { MCK_GPR8 }, },
1354 { 380 /* rcall */, AVR::RCALLk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1355 { 386 /* ret */, AVR::RET, Convert_NoOperands, AMFBS_None, { }, },
1356 { 390 /* reti */, AVR::RETI, Convert_NoOperands, AMFBS_None, { }, },
1357 { 395 /* rjmp */, AVR::RJMPk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1358 { 400 /* rol */, AVR::ADCRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1359 { 404 /* ror */, AVR::RORRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1360 { 408 /* sbc */, AVR::SBCRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1361 { 412 /* sbci */, AVR::SBCIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1362 { 417 /* sbi */, AVR::SBIAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1363 { 421 /* sbic */, AVR::SBICAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1364 { 426 /* sbis */, AVR::SBISAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1365 { 431 /* sbiw */, AVR::SBIWRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_HasADDSUBIW, { MCK_IWREGS, MCK_Imm }, },
1366 { 436 /* sbr */, AVR::ORIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1367 { 440 /* sbrc */, AVR::SBRCRrB, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1368 { 445 /* sbrs */, AVR::SBRSRrB, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1369 { 450 /* sec */, AVR::BSETs, Convert__imm_95_0, AMFBS_None, { }, },
1370 { 454 /* seh */, AVR::BSETs, Convert__imm_95_5, AMFBS_None, { }, },
1371 { 458 /* sei */, AVR::BSETs, Convert__imm_95_7, AMFBS_None, { }, },
1372 { 462 /* sen */, AVR::BSETs, Convert__imm_95_2, AMFBS_None, { }, },
1373 { 466 /* ser */, AVR::LDIRdK, Convert__Reg1_0__imm_95_255, AMFBS_None, { MCK_LD8 }, },
1374 { 470 /* ses */, AVR::BSETs, Convert__imm_95_4, AMFBS_None, { }, },
1375 { 474 /* set */, AVR::BSETs, Convert__imm_95_6, AMFBS_None, { }, },
1376 { 478 /* sev */, AVR::BSETs, Convert__imm_95_3, AMFBS_None, { }, },
1377 { 482 /* sez */, AVR::BSETs, Convert__imm_95_1, AMFBS_None, { }, },
1378 { 486 /* sleep */, AVR::SLEEP, Convert_NoOperands, AMFBS_None, { }, },
1379 { 492 /* spm */, AVR::SPM, Convert_NoOperands, AMFBS_HasSPM, { }, },
1380 { 492 /* spm */, AVR::SPMZPi, Convert__Reg1_0, AMFBS_HasSPMX, { MCK_ZREG, MCK__43_ }, },
1381 { 496 /* st */, AVR::STPtrRr, Convert__Reg1_0__Reg1_1, AMFBS_HasSRAM, { MCK_Reg, MCK_GPR8 }, },
1382 { 496 /* st */, AVR::STPtrPdRr, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0, AMFBS_HasSRAM, { MCK__MINUS_, MCK_Reg, MCK_GPR8 }, },
1383 { 496 /* st */, AVR::STPtrPiRr, Convert__Reg1_0__Tie0_1_1__Reg1_2__imm_95_0, AMFBS_HasSRAM, { MCK_Reg, MCK__43_, MCK_GPR8 }, },
1384 { 499 /* std */, AVR::STDPtrQRr, Convert__Memri2_0__Reg1_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_Memri, MCK_GPR8 }, },
1385 { 503 /* sts */, AVR::STSKRrTiny, Convert__Imm1_0__Reg1_1, AMFBS_HasSRAM_HasTinyEncoding, { MCK_Imm, MCK_LD8 }, },
1386 { 503 /* sts */, AVR::STSKRr, Convert__Imm1_0__Reg1_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_Imm, MCK_GPR8 }, },
1387 { 507 /* sub */, AVR::SUBRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1388 { 511 /* subi */, AVR::SUBIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1389 { 516 /* swap */, AVR::SWAPRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1390 { 521 /* tst */, AVR::ANDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1391 { 525 /* wdr */, AVR::WDR, Convert_NoOperands, AMFBS_None, { }, },
1392 { 529 /* xch */, AVR::XCHZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1393};
1394
1395#include "llvm/Support/Debug.h"
1396#include "llvm/Support/Format.h"
1397
1398unsigned AVRAsmParser::
1399MatchInstructionImpl(const OperandVector &Operands,
1400 MCInst &Inst,
1401 uint64_t &ErrorInfo,
1402 FeatureBitset &MissingFeatures,
1403 bool matchingInlineAsm, unsigned VariantID) {
1404 // Eliminate obvious mismatches.
1405 if (Operands.size() > 4) {
1406 ErrorInfo = 4;
1407 return Match_InvalidOperand;
1408 }
1409
1410 // Get the current feature set.
1411 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
1412
1413 // Get the instruction mnemonic, which is the first token.
1414 StringRef Mnemonic = ((AVROperand &)*Operands[0]).getToken();
1415
1416 // Some state to try to produce better error messages.
1417 bool HadMatchOtherThanFeatures = false;
1418 bool HadMatchOtherThanPredicate = false;
1419 unsigned RetCode = Match_InvalidOperand;
1420 MissingFeatures.set();
1421 // Set ErrorInfo to the operand that mismatches if it is
1422 // wrong for all instances of the instruction.
1423 ErrorInfo = ~0ULL;
1424 // Find the appropriate table for this asm variant.
1425 const MatchEntry *Start, *End;
1426 switch (VariantID) {
1427 default: llvm_unreachable("invalid variant!");
1428 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1429 }
1430 // Search the table.
1431 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
1432
1433 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
1434 std::distance(MnemonicRange.first, MnemonicRange.second) <<
1435 " encodings with mnemonic '" << Mnemonic << "'\n");
1436
1437 // Return a more specific error code if no mnemonics match.
1438 if (MnemonicRange.first == MnemonicRange.second)
1439 return Match_MnemonicFail;
1440
1441 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
1442 it != ie; ++it) {
1443 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
1444 bool HasRequiredFeatures =
1445 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
1446 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
1447 << MII.getName(it->Opcode) << "\n");
1448 // equal_range guarantees that instruction mnemonic matches.
1449 assert(Mnemonic == it->getMnemonic());
1450 bool OperandsValid = true;
1451 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 3; ++FormalIdx) {
1452 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
1453 DEBUG_WITH_TYPE("asm-matcher",
1454 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
1455 << " against actual operand at index " << ActualIdx);
1456 if (ActualIdx < Operands.size())
1457 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
1458 Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
1459 else
1460 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
1461 if (ActualIdx >= Operands.size()) {
1462 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
1463 if (Formal == InvalidMatchClass) {
1464 break;
1465 }
1466 if (isSubclass(Formal, OptionalMatchClass)) {
1467 continue;
1468 }
1469 OperandsValid = false;
1470 ErrorInfo = ActualIdx;
1471 break;
1472 }
1473 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
1474 unsigned Diag = validateOperandClass(Actual, Formal);
1475 if (Diag == Match_Success) {
1476 DEBUG_WITH_TYPE("asm-matcher",
1477 dbgs() << "match success using generic matcher\n");
1478 ++ActualIdx;
1479 continue;
1480 }
1481 // If the generic handler indicates an invalid operand
1482 // failure, check for a special case.
1483 if (Diag != Match_Success) {
1484 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
1485 if (TargetDiag == Match_Success) {
1486 DEBUG_WITH_TYPE("asm-matcher",
1487 dbgs() << "match success using target matcher\n");
1488 ++ActualIdx;
1489 continue;
1490 }
1491 // If the target matcher returned a specific error code use
1492 // that, else use the one from the generic matcher.
1493 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
1494 Diag = TargetDiag;
1495 }
1496 // If current formal operand wasn't matched and it is optional
1497 // then try to match next formal operand
1498 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
1499 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
1500 continue;
1501 }
1502 // If this operand is broken for all of the instances of this
1503 // mnemonic, keep track of it so we can report loc info.
1504 // If we already had a match that only failed due to a
1505 // target predicate, that diagnostic is preferred.
1506 if (!HadMatchOtherThanPredicate &&
1507 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
1508 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
1509 RetCode = Diag;
1510 ErrorInfo = ActualIdx;
1511 }
1512 // Otherwise, just reject this instance of the mnemonic.
1513 OperandsValid = false;
1514 break;
1515 }
1516
1517 if (!OperandsValid) {
1518 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
1519 "operand mismatches, ignoring "
1520 "this opcode\n");
1521 continue;
1522 }
1523 if (!HasRequiredFeatures) {
1524 HadMatchOtherThanFeatures = true;
1525 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
1526 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
1527 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
1528 if (NewMissingFeatures[I])
1529 dbgs() << ' ' << I;
1530 dbgs() << "\n");
1531 if (NewMissingFeatures.count() <=
1532 MissingFeatures.count())
1533 MissingFeatures = NewMissingFeatures;
1534 continue;
1535 }
1536
1537 Inst.clear();
1538
1539 Inst.setOpcode(it->Opcode);
1540 // We have a potential match but have not rendered the operands.
1541 // Check the target predicate to handle any context sensitive
1542 // constraints.
1543 // For example, Ties that are referenced multiple times must be
1544 // checked here to ensure the input is the same for each match
1545 // constraints. If we leave it any later the ties will have been
1546 // canonicalized
1547 unsigned MatchResult;
1548 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
1549 Inst.clear();
1550 DEBUG_WITH_TYPE(
1551 "asm-matcher",
1552 dbgs() << "Early target match predicate failed with diag code "
1553 << MatchResult << "\n");
1554 RetCode = MatchResult;
1555 HadMatchOtherThanPredicate = true;
1556 continue;
1557 }
1558
1559 if (matchingInlineAsm) {
1560 convertToMapAndConstraints(it->ConvertFn, Operands);
1561 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
1562 ErrorInfo))
1563 return Match_InvalidTiedOperand;
1564
1565 return Match_Success;
1566 }
1567
1568 // We have selected a definite instruction, convert the parsed
1569 // operands into the appropriate MCInst.
1570 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
1571
1572 // We have a potential match. Check the target predicate to
1573 // handle any context sensitive constraints.
1574 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
1575 DEBUG_WITH_TYPE("asm-matcher",
1576 dbgs() << "Target match predicate failed with diag code "
1577 << MatchResult << "\n");
1578 Inst.clear();
1579 RetCode = MatchResult;
1580 HadMatchOtherThanPredicate = true;
1581 continue;
1582 }
1583
1584 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
1585 ErrorInfo))
1586 return Match_InvalidTiedOperand;
1587
1588 DEBUG_WITH_TYPE(
1589 "asm-matcher",
1590 dbgs() << "Opcode result: complete match, selecting this opcode\n");
1591 return Match_Success;
1592 }
1593
1594 // Okay, we had no match. Try to return a useful error code.
1595 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
1596 return RetCode;
1597
1598 ErrorInfo = 0;
1599 return Match_MissingFeature;
1600}
1601
1602namespace {
1603 struct OperandMatchEntry {
1604 uint16_t Mnemonic;
1605 uint8_t OperandMask;
1606 uint8_t Class;
1607 uint8_t RequiredFeaturesIdx;
1608
1609 StringRef getMnemonic() const {
1610 return StringRef(MnemonicTable + Mnemonic + 1,
1611 MnemonicTable[Mnemonic]);
1612 }
1613 };
1614
1615 // Predicate for searching for an opcode.
1616 struct LessOpcodeOperand {
1617 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
1618 return LHS.getMnemonic() < RHS;
1619 }
1620 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
1621 return LHS < RHS.getMnemonic();
1622 }
1623 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
1624 return LHS.getMnemonic() < RHS.getMnemonic();
1625 }
1626 };
1627} // end anonymous namespace
1628
1629static const OperandMatchEntry OperandMatchTable[2] = {
1630 /* Operand List Mnemonic, Mask, Operand Class, Features */
1631 { 304 /* ldd */, 2 /* 1 */, MCK_Memri, AMFBS_HasSRAM_HasNonTinyEncoding },
1632 { 499 /* std */, 1 /* 0 */, MCK_Memri, AMFBS_HasSRAM_HasNonTinyEncoding },
1633};
1634
1635ParseStatus AVRAsmParser::
1636tryCustomParseOperand(OperandVector &Operands,
1637 unsigned MCK) {
1638
1639 switch(MCK) {
1640 case MCK_Memri:
1641 return parseMemriOperand(Operands);
1642 default:
1643 return ParseStatus::NoMatch;
1644 }
1645 return ParseStatus::NoMatch;
1646}
1647
1648ParseStatus AVRAsmParser::
1649MatchOperandParserImpl(OperandVector &Operands,
1650 StringRef Mnemonic,
1651 bool ParseForAllFeatures) {
1652 // Get the current feature set.
1653 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
1654
1655 // Get the next operand index.
1656 unsigned NextOpNum = Operands.size() - 1;
1657 // Search the table.
1658 auto MnemonicRange =
1659 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
1660 Mnemonic, LessOpcodeOperand());
1661
1662 if (MnemonicRange.first == MnemonicRange.second)
1663 return ParseStatus::NoMatch;
1664
1665 for (const OperandMatchEntry *it = MnemonicRange.first,
1666 *ie = MnemonicRange.second; it != ie; ++it) {
1667 // equal_range guarantees that instruction mnemonic matches.
1668 assert(Mnemonic == it->getMnemonic());
1669
1670 // check if the available features match
1671 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
1672 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
1673 continue;
1674
1675 // check if the operand in question has a custom parser.
1676 if (!(it->OperandMask & (1 << NextOpNum)))
1677 continue;
1678
1679 // call custom parse method to handle the operand
1680 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
1681 if (!Result.isNoMatch())
1682 return Result;
1683 }
1684
1685 // Okay, we had no match.
1686 return ParseStatus::NoMatch;
1687}
1688
1689#endif // GET_MATCHER_IMPLEMENTATION
1690
1691
1692#ifdef GET_MNEMONIC_SPELL_CHECKER
1693#undef GET_MNEMONIC_SPELL_CHECKER
1694
1695static std::string AVRMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
1696 const unsigned MaxEditDist = 2;
1697 std::vector<StringRef> Candidates;
1698 StringRef Prev = "";
1699
1700 // Find the appropriate table for this asm variant.
1701 const MatchEntry *Start, *End;
1702 switch (VariantID) {
1703 default: llvm_unreachable("invalid variant!");
1704 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1705 }
1706
1707 for (auto I = Start; I < End; I++) {
1708 // Ignore unsupported instructions.
1709 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
1710 if ((FBS & RequiredFeatures) != RequiredFeatures)
1711 continue;
1712
1713 StringRef T = I->getMnemonic();
1714 // Avoid recomputing the edit distance for the same string.
1715 if (T == Prev)
1716 continue;
1717
1718 Prev = T;
1719 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
1720 if (Dist <= MaxEditDist)
1721 Candidates.push_back(T);
1722 }
1723
1724 if (Candidates.empty())
1725 return "";
1726
1727 std::string Res = ", did you mean: ";
1728 unsigned i = 0;
1729 for (; i < Candidates.size() - 1; i++)
1730 Res += Candidates[i].str() + ", ";
1731 return Res + Candidates[i].str() + "?";
1732}
1733
1734#endif // GET_MNEMONIC_SPELL_CHECKER
1735
1736
1737#ifdef GET_MNEMONIC_CHECKER
1738#undef GET_MNEMONIC_CHECKER
1739
1740static bool AVRCheckMnemonic(StringRef Mnemonic,
1741 const FeatureBitset &AvailableFeatures,
1742 unsigned VariantID) {
1743 // Find the appropriate table for this asm variant.
1744 const MatchEntry *Start, *End;
1745 switch (VariantID) {
1746 default: llvm_unreachable("invalid variant!");
1747 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1748 }
1749
1750 // Search the table.
1751 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
1752
1753 if (MnemonicRange.first == MnemonicRange.second)
1754 return false;
1755
1756 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
1757 it != ie; ++it) {
1758 const FeatureBitset &RequiredFeatures =
1759 FeatureBitsets[it->RequiredFeaturesIdx];
1760 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
1761 return true;
1762 }
1763 return false;
1764}
1765
1766#endif // GET_MNEMONIC_CHECKER
1767
1768