1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm {
12
13namespace AVR {
14 enum {
15 PHI = 0,
16 INLINEASM = 1,
17 INLINEASM_BR = 2,
18 CFI_INSTRUCTION = 3,
19 EH_LABEL = 4,
20 GC_LABEL = 5,
21 ANNOTATION_LABEL = 6,
22 KILL = 7,
23 EXTRACT_SUBREG = 8,
24 INSERT_SUBREG = 9,
25 IMPLICIT_DEF = 10,
26 SUBREG_TO_REG = 11,
27 COPY_TO_REGCLASS = 12,
28 DBG_VALUE = 13,
29 DBG_VALUE_LIST = 14,
30 DBG_INSTR_REF = 15,
31 DBG_PHI = 16,
32 DBG_LABEL = 17,
33 REG_SEQUENCE = 18,
34 COPY = 19,
35 BUNDLE = 20,
36 LIFETIME_START = 21,
37 LIFETIME_END = 22,
38 PSEUDO_PROBE = 23,
39 ARITH_FENCE = 24,
40 STACKMAP = 25,
41 FENTRY_CALL = 26,
42 PATCHPOINT = 27,
43 LOAD_STACK_GUARD = 28,
44 PREALLOCATED_SETUP = 29,
45 PREALLOCATED_ARG = 30,
46 STATEPOINT = 31,
47 LOCAL_ESCAPE = 32,
48 FAULTING_OP = 33,
49 PATCHABLE_OP = 34,
50 PATCHABLE_FUNCTION_ENTER = 35,
51 PATCHABLE_RET = 36,
52 PATCHABLE_FUNCTION_EXIT = 37,
53 PATCHABLE_TAIL_CALL = 38,
54 PATCHABLE_EVENT_CALL = 39,
55 PATCHABLE_TYPED_EVENT_CALL = 40,
56 ICALL_BRANCH_FUNNEL = 41,
57 MEMBARRIER = 42,
58 JUMP_TABLE_DEBUG_INFO = 43,
59 CONVERGENCECTRL_ENTRY = 44,
60 CONVERGENCECTRL_ANCHOR = 45,
61 CONVERGENCECTRL_LOOP = 46,
62 CONVERGENCECTRL_GLUE = 47,
63 G_ASSERT_SEXT = 48,
64 G_ASSERT_ZEXT = 49,
65 G_ASSERT_ALIGN = 50,
66 G_ADD = 51,
67 G_SUB = 52,
68 G_MUL = 53,
69 G_SDIV = 54,
70 G_UDIV = 55,
71 G_SREM = 56,
72 G_UREM = 57,
73 G_SDIVREM = 58,
74 G_UDIVREM = 59,
75 G_AND = 60,
76 G_OR = 61,
77 G_XOR = 62,
78 G_IMPLICIT_DEF = 63,
79 G_PHI = 64,
80 G_FRAME_INDEX = 65,
81 G_GLOBAL_VALUE = 66,
82 G_PTRAUTH_GLOBAL_VALUE = 67,
83 G_CONSTANT_POOL = 68,
84 G_EXTRACT = 69,
85 G_UNMERGE_VALUES = 70,
86 G_INSERT = 71,
87 G_MERGE_VALUES = 72,
88 G_BUILD_VECTOR = 73,
89 G_BUILD_VECTOR_TRUNC = 74,
90 G_CONCAT_VECTORS = 75,
91 G_PTRTOINT = 76,
92 G_INTTOPTR = 77,
93 G_BITCAST = 78,
94 G_FREEZE = 79,
95 G_CONSTANT_FOLD_BARRIER = 80,
96 G_INTRINSIC_FPTRUNC_ROUND = 81,
97 G_INTRINSIC_TRUNC = 82,
98 G_INTRINSIC_ROUND = 83,
99 G_INTRINSIC_LRINT = 84,
100 G_INTRINSIC_LLRINT = 85,
101 G_INTRINSIC_ROUNDEVEN = 86,
102 G_READCYCLECOUNTER = 87,
103 G_READSTEADYCOUNTER = 88,
104 G_LOAD = 89,
105 G_SEXTLOAD = 90,
106 G_ZEXTLOAD = 91,
107 G_INDEXED_LOAD = 92,
108 G_INDEXED_SEXTLOAD = 93,
109 G_INDEXED_ZEXTLOAD = 94,
110 G_STORE = 95,
111 G_INDEXED_STORE = 96,
112 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97,
113 G_ATOMIC_CMPXCHG = 98,
114 G_ATOMICRMW_XCHG = 99,
115 G_ATOMICRMW_ADD = 100,
116 G_ATOMICRMW_SUB = 101,
117 G_ATOMICRMW_AND = 102,
118 G_ATOMICRMW_NAND = 103,
119 G_ATOMICRMW_OR = 104,
120 G_ATOMICRMW_XOR = 105,
121 G_ATOMICRMW_MAX = 106,
122 G_ATOMICRMW_MIN = 107,
123 G_ATOMICRMW_UMAX = 108,
124 G_ATOMICRMW_UMIN = 109,
125 G_ATOMICRMW_FADD = 110,
126 G_ATOMICRMW_FSUB = 111,
127 G_ATOMICRMW_FMAX = 112,
128 G_ATOMICRMW_FMIN = 113,
129 G_ATOMICRMW_UINC_WRAP = 114,
130 G_ATOMICRMW_UDEC_WRAP = 115,
131 G_FENCE = 116,
132 G_PREFETCH = 117,
133 G_BRCOND = 118,
134 G_BRINDIRECT = 119,
135 G_INVOKE_REGION_START = 120,
136 G_INTRINSIC = 121,
137 G_INTRINSIC_W_SIDE_EFFECTS = 122,
138 G_INTRINSIC_CONVERGENT = 123,
139 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124,
140 G_ANYEXT = 125,
141 G_TRUNC = 126,
142 G_CONSTANT = 127,
143 G_FCONSTANT = 128,
144 G_VASTART = 129,
145 G_VAARG = 130,
146 G_SEXT = 131,
147 G_SEXT_INREG = 132,
148 G_ZEXT = 133,
149 G_SHL = 134,
150 G_LSHR = 135,
151 G_ASHR = 136,
152 G_FSHL = 137,
153 G_FSHR = 138,
154 G_ROTR = 139,
155 G_ROTL = 140,
156 G_ICMP = 141,
157 G_FCMP = 142,
158 G_SCMP = 143,
159 G_UCMP = 144,
160 G_SELECT = 145,
161 G_UADDO = 146,
162 G_UADDE = 147,
163 G_USUBO = 148,
164 G_USUBE = 149,
165 G_SADDO = 150,
166 G_SADDE = 151,
167 G_SSUBO = 152,
168 G_SSUBE = 153,
169 G_UMULO = 154,
170 G_SMULO = 155,
171 G_UMULH = 156,
172 G_SMULH = 157,
173 G_UADDSAT = 158,
174 G_SADDSAT = 159,
175 G_USUBSAT = 160,
176 G_SSUBSAT = 161,
177 G_USHLSAT = 162,
178 G_SSHLSAT = 163,
179 G_SMULFIX = 164,
180 G_UMULFIX = 165,
181 G_SMULFIXSAT = 166,
182 G_UMULFIXSAT = 167,
183 G_SDIVFIX = 168,
184 G_UDIVFIX = 169,
185 G_SDIVFIXSAT = 170,
186 G_UDIVFIXSAT = 171,
187 G_FADD = 172,
188 G_FSUB = 173,
189 G_FMUL = 174,
190 G_FMA = 175,
191 G_FMAD = 176,
192 G_FDIV = 177,
193 G_FREM = 178,
194 G_FPOW = 179,
195 G_FPOWI = 180,
196 G_FEXP = 181,
197 G_FEXP2 = 182,
198 G_FEXP10 = 183,
199 G_FLOG = 184,
200 G_FLOG2 = 185,
201 G_FLOG10 = 186,
202 G_FLDEXP = 187,
203 G_FFREXP = 188,
204 G_FNEG = 189,
205 G_FPEXT = 190,
206 G_FPTRUNC = 191,
207 G_FPTOSI = 192,
208 G_FPTOUI = 193,
209 G_SITOFP = 194,
210 G_UITOFP = 195,
211 G_FABS = 196,
212 G_FCOPYSIGN = 197,
213 G_IS_FPCLASS = 198,
214 G_FCANONICALIZE = 199,
215 G_FMINNUM = 200,
216 G_FMAXNUM = 201,
217 G_FMINNUM_IEEE = 202,
218 G_FMAXNUM_IEEE = 203,
219 G_FMINIMUM = 204,
220 G_FMAXIMUM = 205,
221 G_GET_FPENV = 206,
222 G_SET_FPENV = 207,
223 G_RESET_FPENV = 208,
224 G_GET_FPMODE = 209,
225 G_SET_FPMODE = 210,
226 G_RESET_FPMODE = 211,
227 G_PTR_ADD = 212,
228 G_PTRMASK = 213,
229 G_SMIN = 214,
230 G_SMAX = 215,
231 G_UMIN = 216,
232 G_UMAX = 217,
233 G_ABS = 218,
234 G_LROUND = 219,
235 G_LLROUND = 220,
236 G_BR = 221,
237 G_BRJT = 222,
238 G_VSCALE = 223,
239 G_INSERT_SUBVECTOR = 224,
240 G_EXTRACT_SUBVECTOR = 225,
241 G_INSERT_VECTOR_ELT = 226,
242 G_EXTRACT_VECTOR_ELT = 227,
243 G_SHUFFLE_VECTOR = 228,
244 G_SPLAT_VECTOR = 229,
245 G_VECTOR_COMPRESS = 230,
246 G_CTTZ = 231,
247 G_CTTZ_ZERO_UNDEF = 232,
248 G_CTLZ = 233,
249 G_CTLZ_ZERO_UNDEF = 234,
250 G_CTPOP = 235,
251 G_BSWAP = 236,
252 G_BITREVERSE = 237,
253 G_FCEIL = 238,
254 G_FCOS = 239,
255 G_FSIN = 240,
256 G_FTAN = 241,
257 G_FACOS = 242,
258 G_FASIN = 243,
259 G_FATAN = 244,
260 G_FCOSH = 245,
261 G_FSINH = 246,
262 G_FTANH = 247,
263 G_FSQRT = 248,
264 G_FFLOOR = 249,
265 G_FRINT = 250,
266 G_FNEARBYINT = 251,
267 G_ADDRSPACE_CAST = 252,
268 G_BLOCK_ADDR = 253,
269 G_JUMP_TABLE = 254,
270 G_DYN_STACKALLOC = 255,
271 G_STACKSAVE = 256,
272 G_STACKRESTORE = 257,
273 G_STRICT_FADD = 258,
274 G_STRICT_FSUB = 259,
275 G_STRICT_FMUL = 260,
276 G_STRICT_FDIV = 261,
277 G_STRICT_FREM = 262,
278 G_STRICT_FMA = 263,
279 G_STRICT_FSQRT = 264,
280 G_STRICT_FLDEXP = 265,
281 G_READ_REGISTER = 266,
282 G_WRITE_REGISTER = 267,
283 G_MEMCPY = 268,
284 G_MEMCPY_INLINE = 269,
285 G_MEMMOVE = 270,
286 G_MEMSET = 271,
287 G_BZERO = 272,
288 G_TRAP = 273,
289 G_DEBUGTRAP = 274,
290 G_UBSANTRAP = 275,
291 G_VECREDUCE_SEQ_FADD = 276,
292 G_VECREDUCE_SEQ_FMUL = 277,
293 G_VECREDUCE_FADD = 278,
294 G_VECREDUCE_FMUL = 279,
295 G_VECREDUCE_FMAX = 280,
296 G_VECREDUCE_FMIN = 281,
297 G_VECREDUCE_FMAXIMUM = 282,
298 G_VECREDUCE_FMINIMUM = 283,
299 G_VECREDUCE_ADD = 284,
300 G_VECREDUCE_MUL = 285,
301 G_VECREDUCE_AND = 286,
302 G_VECREDUCE_OR = 287,
303 G_VECREDUCE_XOR = 288,
304 G_VECREDUCE_SMAX = 289,
305 G_VECREDUCE_SMIN = 290,
306 G_VECREDUCE_UMAX = 291,
307 G_VECREDUCE_UMIN = 292,
308 G_SBFX = 293,
309 G_UBFX = 294,
310 ADCWRdRr = 295,
311 ADDWRdRr = 296,
312 ADJCALLSTACKDOWN = 297,
313 ADJCALLSTACKUP = 298,
314 ANDIWRdK = 299,
315 ANDWRdRr = 300,
316 ASRBNRd = 301,
317 ASRWLoRd = 302,
318 ASRWNRd = 303,
319 ASRWRd = 304,
320 Asr16 = 305,
321 Asr32 = 306,
322 Asr8 = 307,
323 AtomicFence = 308,
324 AtomicLoad16 = 309,
325 AtomicLoad8 = 310,
326 AtomicLoadAdd16 = 311,
327 AtomicLoadAdd8 = 312,
328 AtomicLoadAnd16 = 313,
329 AtomicLoadAnd8 = 314,
330 AtomicLoadOr16 = 315,
331 AtomicLoadOr8 = 316,
332 AtomicLoadSub16 = 317,
333 AtomicLoadSub8 = 318,
334 AtomicLoadXor16 = 319,
335 AtomicLoadXor8 = 320,
336 AtomicStore16 = 321,
337 AtomicStore8 = 322,
338 COMWRd = 323,
339 CPCWRdRr = 324,
340 CPWRdRr = 325,
341 CopyZero = 326,
342 ELPMBRdZ = 327,
343 ELPMBRdZPi = 328,
344 ELPMWRdZ = 329,
345 ELPMWRdZPi = 330,
346 EORWRdRr = 331,
347 FRMIDX = 332,
348 INWRdA = 333,
349 LDDWRdPtrQ = 334,
350 LDDWRdYQ = 335,
351 LDIWRdK = 336,
352 LDSWRdK = 337,
353 LDWRdPtr = 338,
354 LDWRdPtrPd = 339,
355 LDWRdPtrPi = 340,
356 LPMBRdZ = 341,
357 LPMWRdZ = 342,
358 LPMWRdZPi = 343,
359 LSLBNRd = 344,
360 LSLWHiRd = 345,
361 LSLWNRd = 346,
362 LSLWRd = 347,
363 LSRBNRd = 348,
364 LSRWLoRd = 349,
365 LSRWNRd = 350,
366 LSRWRd = 351,
367 Lsl16 = 352,
368 Lsl32 = 353,
369 Lsl8 = 354,
370 Lsr16 = 355,
371 Lsr32 = 356,
372 Lsr8 = 357,
373 NEGWRd = 358,
374 ORIWRdK = 359,
375 ORWRdRr = 360,
376 OUTWARr = 361,
377 POPWRd = 362,
378 PUSHWRr = 363,
379 ROLBRdR1 = 364,
380 ROLBRdR17 = 365,
381 ROLWRd = 366,
382 RORBRd = 367,
383 RORWRd = 368,
384 Rol16 = 369,
385 Rol8 = 370,
386 Ror16 = 371,
387 Ror8 = 372,
388 SBCIWRdK = 373,
389 SBCWRdRr = 374,
390 SEXT = 375,
391 SPREAD = 376,
392 SPWRITE = 377,
393 STDSPQRr = 378,
394 STDWPtrQRr = 379,
395 STDWSPQRr = 380,
396 STSWKRr = 381,
397 STWPtrPdRr = 382,
398 STWPtrPiRr = 383,
399 STWPtrRr = 384,
400 SUBIWRdK = 385,
401 SUBWRdRr = 386,
402 Select16 = 387,
403 Select8 = 388,
404 ZEXT = 389,
405 ADCRdRr = 390,
406 ADDRdRr = 391,
407 ADIWRdK = 392,
408 ANDIRdK = 393,
409 ANDRdRr = 394,
410 ASRRd = 395,
411 BCLRs = 396,
412 BLD = 397,
413 BRBCsk = 398,
414 BRBSsk = 399,
415 BREAK = 400,
416 BREQk = 401,
417 BRGEk = 402,
418 BRLOk = 403,
419 BRLTk = 404,
420 BRMIk = 405,
421 BRNEk = 406,
422 BRPLk = 407,
423 BRSHk = 408,
424 BSETs = 409,
425 BST = 410,
426 CALLk = 411,
427 CBIAb = 412,
428 COMRd = 413,
429 CPCRdRr = 414,
430 CPIRdK = 415,
431 CPRdRr = 416,
432 CPSE = 417,
433 DECRd = 418,
434 DESK = 419,
435 EICALL = 420,
436 EIJMP = 421,
437 ELPM = 422,
438 ELPMRdZ = 423,
439 ELPMRdZPi = 424,
440 EORRdRr = 425,
441 FMUL = 426,
442 FMULS = 427,
443 FMULSU = 428,
444 ICALL = 429,
445 IJMP = 430,
446 INCRd = 431,
447 INRdA = 432,
448 JMPk = 433,
449 LACZRd = 434,
450 LASZRd = 435,
451 LATZRd = 436,
452 LDDRdPtrQ = 437,
453 LDIRdK = 438,
454 LDRdPtr = 439,
455 LDRdPtrPd = 440,
456 LDRdPtrPi = 441,
457 LDSRdK = 442,
458 LDSRdKTiny = 443,
459 LPM = 444,
460 LPMRdZ = 445,
461 LPMRdZPi = 446,
462 LSRRd = 447,
463 MOVRdRr = 448,
464 MOVWRdRr = 449,
465 MULRdRr = 450,
466 MULSRdRr = 451,
467 MULSURdRr = 452,
468 NEGRd = 453,
469 NOP = 454,
470 ORIRdK = 455,
471 ORRdRr = 456,
472 OUTARr = 457,
473 POPRd = 458,
474 PUSHRr = 459,
475 RCALLk = 460,
476 RET = 461,
477 RETI = 462,
478 RJMPk = 463,
479 RORRd = 464,
480 SBCIRdK = 465,
481 SBCRdRr = 466,
482 SBIAb = 467,
483 SBICAb = 468,
484 SBISAb = 469,
485 SBIWRdK = 470,
486 SBRCRrB = 471,
487 SBRSRrB = 472,
488 SLEEP = 473,
489 SPM = 474,
490 SPMZPi = 475,
491 STDPtrQRr = 476,
492 STPtrPdRr = 477,
493 STPtrPiRr = 478,
494 STPtrRr = 479,
495 STSKRr = 480,
496 STSKRrTiny = 481,
497 SUBIRdK = 482,
498 SUBRdRr = 483,
499 SWAPRd = 484,
500 WDR = 485,
501 XCHZRd = 486,
502 INSTRUCTION_LIST_END = 487
503 };
504
505} // end namespace AVR
506} // end namespace llvm
507#endif // GET_INSTRINFO_ENUM
508
509#ifdef GET_INSTRINFO_SCHED_ENUM
510#undef GET_INSTRINFO_SCHED_ENUM
511namespace llvm {
512
513namespace AVR {
514namespace Sched {
515 enum {
516 NoInstrModel = 0,
517 SCHED_LIST_END = 1
518 };
519} // end namespace Sched
520} // end namespace AVR
521} // end namespace llvm
522#endif // GET_INSTRINFO_SCHED_ENUM
523
524#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
525namespace llvm {
526
527struct AVRInstrTable {
528 MCInstrDesc Insts[487];
529 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
530 MCOperandInfo OperandInfo[319];
531 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
532 MCPhysReg ImplicitOps[44];
533};
534
535} // end namespace llvm
536#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
537
538#ifdef GET_INSTRINFO_MC_DESC
539#undef GET_INSTRINFO_MC_DESC
540namespace llvm {
541
542static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
543static constexpr unsigned AVRImpOpBase = sizeof AVRInstrTable::OperandInfo / (sizeof(MCPhysReg));
544
545extern const AVRInstrTable AVRDescs = {
546 {
547 { 486, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #486 = XCHZRd
548 { 485, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #485 = WDR
549 { 484, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #484 = SWAPRd
550 { 483, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 269, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #483 = SUBRdRr
551 { 482, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 275, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #482 = SUBIRdK
552 { 481, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 317, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #481 = STSKRrTiny
553 { 480, 2, 0, 4, 0, 0, 0, AVRImpOpBase + 0, 305, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #480 = STSKRr
554 { 479, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 315, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #479 = STPtrRr
555 { 478, 4, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #478 = STPtrPiRr
556 { 477, 4, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #477 = STPtrPdRr
557 { 476, 3, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 308, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #476 = STDPtrQRr
558 { 475, 1, 0, 2, 0, 2, 1, AVRImpOpBase + 41, 307, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #475 = SPMZPi
559 { 474, 0, 0, 2, 0, 3, 0, AVRImpOpBase + 38, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #474 = SPM
560 { 473, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #473 = SLEEP
561 { 472, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 283, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #472 = SBRSRrB
562 { 471, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 283, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #471 = SBRCRrB
563 { 470, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 272, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #470 = SBIWRdK
564 { 469, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #469 = SBISAb
565 { 468, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #468 = SBICAb
566 { 467, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 285, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #467 = SBIAb
567 { 466, 3, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 269, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #466 = SBCRdRr
568 { 465, 3, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 275, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #465 = SBCIRdK
569 { 464, 2, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #464 = RORRd
570 { 463, 1, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #463 = RJMPk
571 { 462, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #462 = RETI
572 { 461, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #461 = RET
573 { 460, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 16, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #460 = RCALLk
574 { 459, 1, 0, 2, 0, 1, 1, AVRImpOpBase + 10, 193, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #459 = PUSHRr
575 { 458, 1, 1, 2, 0, 1, 1, AVRImpOpBase + 10, 193, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #458 = POPRd
576 { 457, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 305, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #457 = OUTARr
577 { 456, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 269, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #456 = ORRdRr
578 { 455, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 275, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #455 = ORIRdK
579 { 454, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #454 = NOP
580 { 453, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = NEGRd
581 { 452, 2, 0, 2, 0, 0, 3, AVRImpOpBase + 35, 291, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = MULSURdRr
582 { 451, 2, 0, 2, 0, 0, 3, AVRImpOpBase + 35, 303, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #451 = MULSRdRr
583 { 450, 2, 0, 2, 0, 0, 3, AVRImpOpBase + 35, 287, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #450 = MULRdRr
584 { 449, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = MOVWRdRr
585 { 448, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 287, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = MOVRdRr
586 { 447, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #447 = LSRRd
587 { 446, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 9, 223, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #446 = LPMRdZPi
588 { 445, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 223, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = LPMRdZ
589 { 444, 0, 0, 2, 0, 1, 1, AVRImpOpBase + 33, 1, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = LPM
590 { 443, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 289, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #443 = LDSRdKTiny
591 { 442, 2, 1, 4, 0, 0, 0, AVRImpOpBase + 0, 293, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #442 = LDSRdK
592 { 441, 3, 2, 2, 0, 0, 0, AVRImpOpBase + 0, 300, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = LDRdPtrPi
593 { 440, 3, 2, 2, 0, 0, 0, AVRImpOpBase + 0, 300, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = LDRdPtrPd
594 { 439, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 298, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #439 = LDRdPtr
595 { 438, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 289, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #438 = LDIRdK
596 { 437, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 295, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #437 = LDDRdPtrQ
597 { 436, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #436 = LATZRd
598 { 435, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #435 = LASZRd
599 { 434, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #434 = LACZRd
600 { 433, 1, 0, 4, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #433 = JMPk
601 { 432, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 293, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #432 = INRdA
602 { 431, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #431 = INCRd
603 { 430, 0, 0, 2, 0, 1, 0, AVRImpOpBase + 9, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #430 = IJMP
604 { 429, 0, 0, 2, 0, 2, 0, AVRImpOpBase + 6, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #429 = ICALL
605 { 428, 2, 0, 2, 0, 0, 3, AVRImpOpBase + 35, 291, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #428 = FMULSU
606 { 427, 2, 0, 2, 0, 0, 3, AVRImpOpBase + 35, 291, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #427 = FMULS
607 { 426, 2, 0, 2, 0, 0, 3, AVRImpOpBase + 35, 291, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #426 = FMUL
608 { 425, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 269, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #425 = EORRdRr
609 { 424, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 9, 223, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #424 = ELPMRdZPi
610 { 423, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 223, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #423 = ELPMRdZ
611 { 422, 0, 0, 2, 0, 1, 1, AVRImpOpBase + 33, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #422 = ELPM
612 { 421, 0, 0, 2, 0, 1, 0, AVRImpOpBase + 9, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #421 = EIJMP
613 { 420, 0, 0, 2, 0, 2, 0, AVRImpOpBase + 6, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #420 = EICALL
614 { 419, 1, 0, 2, 0, 0, 16, AVRImpOpBase + 17, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #419 = DESK
615 { 418, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #418 = DECRd
616 { 417, 2, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #417 = CPSE
617 { 416, 2, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 287, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #416 = CPRdRr
618 { 415, 2, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 289, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #415 = CPIRdK
619 { 414, 2, 0, 2, 0, 1, 1, AVRImpOpBase + 0, 287, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #414 = CPCRdRr
620 { 413, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #413 = COMRd
621 { 412, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 285, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #412 = CBIAb
622 { 411, 1, 0, 4, 0, 1, 0, AVRImpOpBase + 16, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #411 = CALLk
623 { 410, 2, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 283, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #410 = BST
624 { 409, 1, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #409 = BSETs
625 { 408, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #408 = BRSHk
626 { 407, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #407 = BRPLk
627 { 406, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #406 = BRNEk
628 { 405, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #405 = BRMIk
629 { 404, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #404 = BRLTk
630 { 403, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #403 = BRLOk
631 { 402, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #402 = BRGEk
632 { 401, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #401 = BREQk
633 { 400, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #400 = BREAK
634 { 399, 2, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 281, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #399 = BRBSsk
635 { 398, 2, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 281, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #398 = BRBCsk
636 { 397, 3, 1, 2, 0, 1, 0, AVRImpOpBase + 2, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #397 = BLD
637 { 396, 1, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #396 = BCLRs
638 { 395, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #395 = ASRRd
639 { 394, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 269, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #394 = ANDRdRr
640 { 393, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 275, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = ANDIRdK
641 { 392, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 272, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = ADIWRdK
642 { 391, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 269, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = ADDRdRr
643 { 390, 3, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 269, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = ADCRdRr
644 { 389, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 240, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = ZEXT
645 { 388, 4, 1, 2, 0, 1, 0, AVRImpOpBase + 2, 265, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = Select8
646 { 387, 4, 1, 2, 0, 1, 0, AVRImpOpBase + 2, 261, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = Select16
647 { 386, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = SUBWRdRr
648 { 385, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 155, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = SUBIWRdK
649 { 384, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = STWPtrRr
650 { 383, 4, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 257, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = STWPtrPiRr
651 { 382, 4, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 257, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = STWPtrPdRr
652 { 381, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 255, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = STSWKRr
653 { 380, 3, 0, 2, 0, 0, 1, AVRImpOpBase + 16, 252, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = STDWSPQRr
654 { 379, 3, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 249, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = STDWPtrQRr
655 { 378, 3, 0, 2, 0, 0, 1, AVRImpOpBase + 16, 246, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = STDSPQRr
656 { 377, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 16, 244, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = SPWRITE
657 { 376, 2, 1, 2, 0, 1, 0, AVRImpOpBase + 16, 242, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = SPREAD
658 { 375, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 240, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = SEXT
659 { 374, 3, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = SBCWRdRr
660 { 373, 3, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = SBCIWRdK
661 { 372, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = Ror8
662 { 371, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = Ror16
663 { 370, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = Rol8
664 { 369, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = Rol16
665 { 368, 2, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = RORWRd
666 { 367, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = RORBRd
667 { 366, 2, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = ROLWRd
668 { 365, 2, 1, 2, 0, 1, 1, AVRImpOpBase + 14, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = ROLBRdR17
669 { 364, 2, 1, 2, 0, 1, 1, AVRImpOpBase + 12, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = ROLBRdR1
670 { 363, 1, 0, 2, 0, 1, 1, AVRImpOpBase + 10, 237, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = PUSHWRr
671 { 362, 1, 1, 2, 0, 1, 1, AVRImpOpBase + 10, 237, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = POPWRd
672 { 361, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 235, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = OUTWARr
673 { 360, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = ORWRdRr
674 { 359, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 155, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = ORIWRdK
675 { 358, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = NEGWRd
676 { 357, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = Lsr8
677 { 356, 5, 2, 2, 0, 0, 1, AVRImpOpBase + 2, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = Lsr32
678 { 355, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = Lsr16
679 { 354, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = Lsl8
680 { 353, 5, 2, 2, 0, 0, 1, AVRImpOpBase + 2, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = Lsl32
681 { 352, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = Lsl16
682 { 351, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = LSRWRd
683 { 350, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = LSRWNRd
684 { 349, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = LSRWLoRd
685 { 348, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 158, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = LSRBNRd
686 { 347, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = LSLWRd
687 { 346, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = LSLWNRd
688 { 345, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = LSLWHiRd
689 { 344, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 158, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = LSLBNRd
690 { 343, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 9, 227, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = LPMWRdZPi
691 { 342, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 8, 225, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = LPMWRdZ
692 { 341, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 8, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = LPMBRdZ
693 { 340, 3, 2, 2, 0, 0, 0, AVRImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = LDWRdPtrPi
694 { 339, 3, 2, 2, 0, 0, 0, AVRImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = LDWRdPtrPd
695 { 338, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 218, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = LDWRdPtr
696 { 337, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 216, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = LDSWRdK
697 { 336, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 214, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = LDIWRdK
698 { 335, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 211, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = LDDWRdYQ
699 { 334, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = LDDWRdPtrQ
700 { 333, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = INWRdA
701 { 332, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 203, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = FRMIDX
702 { 331, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = EORWRdRr
703 { 330, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 9, 200, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = ELPMWRdZPi
704 { 329, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 8, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = ELPMWRdZ
705 { 328, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 9, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = ELPMBRdZPi
706 { 327, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 8, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = ELPMBRdZ
707 { 326, 1, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 193, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = CopyZero
708 { 325, 2, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = CPWRdRr
709 { 324, 2, 0, 2, 0, 1, 1, AVRImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = CPCWRdRr
710 { 323, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = COMWRd
711 { 322, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 189, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = AtomicStore8
712 { 321, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #321 = AtomicStore16
713 { 320, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 184, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #320 = AtomicLoadXor8
714 { 319, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = AtomicLoadXor16
715 { 318, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 184, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = AtomicLoadSub8
716 { 317, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = AtomicLoadSub16
717 { 316, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 184, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = AtomicLoadOr8
718 { 315, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = AtomicLoadOr16
719 { 314, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 184, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = AtomicLoadAnd8
720 { 313, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #313 = AtomicLoadAnd16
721 { 312, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 184, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #312 = AtomicLoadAdd8
722 { 311, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #311 = AtomicLoadAdd16
723 { 310, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = AtomicLoad8
724 { 309, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 177, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = AtomicLoad16
725 { 308, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = AtomicFence
726 { 307, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #307 = Asr8
727 { 306, 5, 2, 2, 0, 0, 1, AVRImpOpBase + 2, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #306 = Asr32
728 { 305, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #305 = Asr16
729 { 304, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #304 = ASRWRd
730 { 303, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 163, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #303 = ASRWNRd
731 { 302, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = ASRWLoRd
732 { 301, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 158, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = ASRBNRd
733 { 300, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = ANDWRdRr
734 { 299, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 155, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #299 = ANDIWRdK
735 { 298, 2, 0, 2, 0, 1, 1, AVRImpOpBase + 6, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #298 = ADJCALLSTACKUP
736 { 297, 2, 0, 2, 0, 1, 2, AVRImpOpBase + 3, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #297 = ADJCALLSTACKDOWN
737 { 296, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = ADDWRdRr
738 { 295, 3, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = ADCWRdRr
739 { 294, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_UBFX
740 { 293, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_SBFX
741 { 292, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMIN
742 { 291, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_UMAX
743 { 290, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMIN
744 { 289, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_VECREDUCE_SMAX
745 { 288, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_VECREDUCE_XOR
746 { 287, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_VECREDUCE_OR
747 { 286, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_VECREDUCE_AND
748 { 285, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_VECREDUCE_MUL
749 { 284, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_VECREDUCE_ADD
750 { 283, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMINIMUM
751 { 282, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMAXIMUM
752 { 281, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMIN
753 { 280, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMAX
754 { 279, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_VECREDUCE_FMUL
755 { 278, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_VECREDUCE_FADD
756 { 277, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FMUL
757 { 276, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_VECREDUCE_SEQ_FADD
758 { 275, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_UBSANTRAP
759 { 274, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #274 = G_DEBUGTRAP
760 { 273, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #273 = G_TRAP
761 { 272, 3, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #272 = G_BZERO
762 { 271, 4, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_MEMSET
763 { 270, 4, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_MEMMOVE
764 { 269, 3, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_MEMCPY_INLINE
765 { 268, 4, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #268 = G_MEMCPY
766 { 267, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_WRITE_REGISTER
767 { 266, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #266 = G_READ_REGISTER
768 { 265, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_STRICT_FLDEXP
769 { 264, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_STRICT_FSQRT
770 { 263, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_STRICT_FMA
771 { 262, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_STRICT_FREM
772 { 261, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_STRICT_FDIV
773 { 260, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_STRICT_FMUL
774 { 259, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_STRICT_FSUB
775 { 258, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_STRICT_FADD
776 { 257, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_STACKRESTORE
777 { 256, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_STACKSAVE
778 { 255, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_DYN_STACKALLOC
779 { 254, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_JUMP_TABLE
780 { 253, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_BLOCK_ADDR
781 { 252, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_ADDRSPACE_CAST
782 { 251, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FNEARBYINT
783 { 250, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_FRINT
784 { 249, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_FFLOOR
785 { 248, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_FSQRT
786 { 247, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_FTANH
787 { 246, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_FSINH
788 { 245, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_FCOSH
789 { 244, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_FATAN
790 { 243, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_FASIN
791 { 242, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_FACOS
792 { 241, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_FTAN
793 { 240, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_FSIN
794 { 239, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_FCOS
795 { 238, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_FCEIL
796 { 237, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_BITREVERSE
797 { 236, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_BSWAP
798 { 235, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_CTPOP
799 { 234, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_CTLZ_ZERO_UNDEF
800 { 233, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_CTLZ
801 { 232, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_CTTZ_ZERO_UNDEF
802 { 231, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_CTTZ
803 { 230, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_VECTOR_COMPRESS
804 { 229, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_SPLAT_VECTOR
805 { 228, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_SHUFFLE_VECTOR
806 { 227, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_EXTRACT_VECTOR_ELT
807 { 226, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_INSERT_VECTOR_ELT
808 { 225, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_EXTRACT_SUBVECTOR
809 { 224, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_INSERT_SUBVECTOR
810 { 223, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_VSCALE
811 { 222, 3, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_BRJT
812 { 221, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_BR
813 { 220, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_LLROUND
814 { 219, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_LROUND
815 { 218, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_ABS
816 { 217, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_UMAX
817 { 216, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_UMIN
818 { 215, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_SMAX
819 { 214, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_SMIN
820 { 213, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_PTRMASK
821 { 212, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_PTR_ADD
822 { 211, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_RESET_FPMODE
823 { 210, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_SET_FPMODE
824 { 209, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_GET_FPMODE
825 { 208, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_RESET_FPENV
826 { 207, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_SET_FPENV
827 { 206, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_GET_FPENV
828 { 205, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FMAXIMUM
829 { 204, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_FMINIMUM
830 { 203, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_FMAXNUM_IEEE
831 { 202, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_FMINNUM_IEEE
832 { 201, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FMAXNUM
833 { 200, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FMINNUM
834 { 199, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_FCANONICALIZE
835 { 198, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_IS_FPCLASS
836 { 197, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FCOPYSIGN
837 { 196, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_FABS
838 { 195, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_UITOFP
839 { 194, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_SITOFP
840 { 193, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FPTOUI
841 { 192, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FPTOSI
842 { 191, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FPTRUNC
843 { 190, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FPEXT
844 { 189, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FNEG
845 { 188, 3, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FFREXP
846 { 187, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FLDEXP
847 { 186, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FLOG10
848 { 185, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FLOG2
849 { 184, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FLOG
850 { 183, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FEXP10
851 { 182, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FEXP2
852 { 181, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FEXP
853 { 180, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FPOWI
854 { 179, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #179 = G_FPOW
855 { 178, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #178 = G_FREM
856 { 177, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #177 = G_FDIV
857 { 176, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #176 = G_FMAD
858 { 175, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #175 = G_FMA
859 { 174, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #174 = G_FMUL
860 { 173, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #173 = G_FSUB
861 { 172, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #172 = G_FADD
862 { 171, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #171 = G_UDIVFIXSAT
863 { 170, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #170 = G_SDIVFIXSAT
864 { 169, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #169 = G_UDIVFIX
865 { 168, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #168 = G_SDIVFIX
866 { 167, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #167 = G_UMULFIXSAT
867 { 166, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #166 = G_SMULFIXSAT
868 { 165, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #165 = G_UMULFIX
869 { 164, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #164 = G_SMULFIX
870 { 163, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #163 = G_SSHLSAT
871 { 162, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #162 = G_USHLSAT
872 { 161, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #161 = G_SSUBSAT
873 { 160, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #160 = G_USUBSAT
874 { 159, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #159 = G_SADDSAT
875 { 158, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #158 = G_UADDSAT
876 { 157, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #157 = G_SMULH
877 { 156, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #156 = G_UMULH
878 { 155, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #155 = G_SMULO
879 { 154, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #154 = G_UMULO
880 { 153, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #153 = G_SSUBE
881 { 152, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #152 = G_SSUBO
882 { 151, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #151 = G_SADDE
883 { 150, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #150 = G_SADDO
884 { 149, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #149 = G_USUBE
885 { 148, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #148 = G_USUBO
886 { 147, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #147 = G_UADDE
887 { 146, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #146 = G_UADDO
888 { 145, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #145 = G_SELECT
889 { 144, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #144 = G_UCMP
890 { 143, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #143 = G_SCMP
891 { 142, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #142 = G_FCMP
892 { 141, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #141 = G_ICMP
893 { 140, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #140 = G_ROTL
894 { 139, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #139 = G_ROTR
895 { 138, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #138 = G_FSHR
896 { 137, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #137 = G_FSHL
897 { 136, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #136 = G_ASHR
898 { 135, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #135 = G_LSHR
899 { 134, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #134 = G_SHL
900 { 133, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #133 = G_ZEXT
901 { 132, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #132 = G_SEXT_INREG
902 { 131, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #131 = G_SEXT
903 { 130, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #130 = G_VAARG
904 { 129, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #129 = G_VASTART
905 { 128, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #128 = G_FCONSTANT
906 { 127, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #127 = G_CONSTANT
907 { 126, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #126 = G_TRUNC
908 { 125, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #125 = G_ANYEXT
909 { 124, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
910 { 123, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #123 = G_INTRINSIC_CONVERGENT
911 { 122, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #122 = G_INTRINSIC_W_SIDE_EFFECTS
912 { 121, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #121 = G_INTRINSIC
913 { 120, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #120 = G_INVOKE_REGION_START
914 { 119, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #119 = G_BRINDIRECT
915 { 118, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #118 = G_BRCOND
916 { 117, 4, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #117 = G_PREFETCH
917 { 116, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #116 = G_FENCE
918 { 115, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UDEC_WRAP
919 { 114, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #114 = G_ATOMICRMW_UINC_WRAP
920 { 113, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMIN
921 { 112, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FMAX
922 { 111, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FSUB
923 { 110, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #110 = G_ATOMICRMW_FADD
924 { 109, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMIN
925 { 108, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #108 = G_ATOMICRMW_UMAX
926 { 107, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MIN
927 { 106, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #106 = G_ATOMICRMW_MAX
928 { 105, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #105 = G_ATOMICRMW_XOR
929 { 104, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #104 = G_ATOMICRMW_OR
930 { 103, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #103 = G_ATOMICRMW_NAND
931 { 102, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #102 = G_ATOMICRMW_AND
932 { 101, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #101 = G_ATOMICRMW_SUB
933 { 100, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #100 = G_ATOMICRMW_ADD
934 { 99, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #99 = G_ATOMICRMW_XCHG
935 { 98, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG
936 { 97, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #97 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
937 { 96, 5, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #96 = G_INDEXED_STORE
938 { 95, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #95 = G_STORE
939 { 94, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #94 = G_INDEXED_ZEXTLOAD
940 { 93, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #93 = G_INDEXED_SEXTLOAD
941 { 92, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #92 = G_INDEXED_LOAD
942 { 91, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #91 = G_ZEXTLOAD
943 { 90, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #90 = G_SEXTLOAD
944 { 89, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #89 = G_LOAD
945 { 88, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #88 = G_READSTEADYCOUNTER
946 { 87, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #87 = G_READCYCLECOUNTER
947 { 86, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #86 = G_INTRINSIC_ROUNDEVEN
948 { 85, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #85 = G_INTRINSIC_LLRINT
949 { 84, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #84 = G_INTRINSIC_LRINT
950 { 83, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #83 = G_INTRINSIC_ROUND
951 { 82, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #82 = G_INTRINSIC_TRUNC
952 { 81, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #81 = G_INTRINSIC_FPTRUNC_ROUND
953 { 80, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #80 = G_CONSTANT_FOLD_BARRIER
954 { 79, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #79 = G_FREEZE
955 { 78, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #78 = G_BITCAST
956 { 77, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #77 = G_INTTOPTR
957 { 76, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #76 = G_PTRTOINT
958 { 75, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #75 = G_CONCAT_VECTORS
959 { 74, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR_TRUNC
960 { 73, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #73 = G_BUILD_VECTOR
961 { 72, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #72 = G_MERGE_VALUES
962 { 71, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #71 = G_INSERT
963 { 70, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #70 = G_UNMERGE_VALUES
964 { 69, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #69 = G_EXTRACT
965 { 68, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #68 = G_CONSTANT_POOL
966 { 67, 5, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #67 = G_PTRAUTH_GLOBAL_VALUE
967 { 66, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #66 = G_GLOBAL_VALUE
968 { 65, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #65 = G_FRAME_INDEX
969 { 64, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #64 = G_PHI
970 { 63, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #63 = G_IMPLICIT_DEF
971 { 62, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #62 = G_XOR
972 { 61, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #61 = G_OR
973 { 60, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #60 = G_AND
974 { 59, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #59 = G_UDIVREM
975 { 58, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #58 = G_SDIVREM
976 { 57, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #57 = G_UREM
977 { 56, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #56 = G_SREM
978 { 55, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #55 = G_UDIV
979 { 54, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #54 = G_SDIV
980 { 53, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #53 = G_MUL
981 { 52, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #52 = G_SUB
982 { 51, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #51 = G_ADD
983 { 50, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #50 = G_ASSERT_ALIGN
984 { 49, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #49 = G_ASSERT_ZEXT
985 { 48, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #48 = G_ASSERT_SEXT
986 { 47, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_GLUE
987 { 46, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_LOOP
988 { 45, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ANCHOR
989 { 44, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #44 = CONVERGENCECTRL_ENTRY
990 { 43, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #43 = JUMP_TABLE_DEBUG_INFO
991 { 42, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #42 = MEMBARRIER
992 { 41, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL
993 { 40, 3, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
994 { 39, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL
995 { 38, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL
996 { 37, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT
997 { 36, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #36 = PATCHABLE_RET
998 { 35, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER
999 { 34, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #34 = PATCHABLE_OP
1000 { 33, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #33 = FAULTING_OP
1001 { 32, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE
1002 { 31, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #31 = STATEPOINT
1003 { 30, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG
1004 { 29, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP
1005 { 28, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD
1006 { 27, 6, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #27 = PATCHPOINT
1007 { 26, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #26 = FENTRY_CALL
1008 { 25, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #25 = STACKMAP
1009 { 24, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #24 = ARITH_FENCE
1010 { 23, 4, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #23 = PSEUDO_PROBE
1011 { 22, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #22 = LIFETIME_END
1012 { 21, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #21 = LIFETIME_START
1013 { 20, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #20 = BUNDLE
1014 { 19, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #19 = COPY
1015 { 18, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #18 = REG_SEQUENCE
1016 { 17, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #17 = DBG_LABEL
1017 { 16, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #16 = DBG_PHI
1018 { 15, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #15 = DBG_INSTR_REF
1019 { 14, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST
1020 { 13, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #13 = DBG_VALUE
1021 { 12, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS
1022 { 11, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #11 = SUBREG_TO_REG
1023 { 10, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
1024 { 9, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #9 = INSERT_SUBREG
1025 { 8, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
1026 { 7, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #7 = KILL
1027 { 6, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
1028 { 5, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #5 = GC_LABEL
1029 { 4, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #4 = EH_LABEL
1030 { 3, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
1031 { 2, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #2 = INLINEASM_BR
1032 { 1, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1 = INLINEASM
1033 { 0, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #0 = PHI
1034 }, {
1035 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1036 /* 1 */
1037 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1038 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1039 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1040 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1041 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1042 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1043 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1044 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1045 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1046 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1047 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1048 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1049 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1050 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1051 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1052 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1053 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1054 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1055 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1056 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1057 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1058 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1059 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1060 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1061 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1062 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1063 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1064 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1065 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1066 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1067 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1068 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1069 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1070 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1071 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1072 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1073 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1074 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1075 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1076 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1077 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1078 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1079 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1080 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1081 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1082 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1083 /* 152 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1084 /* 155 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1085 /* 158 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1086 /* 161 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1087 /* 163 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1088 /* 166 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1089 /* 169 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1090 /* 174 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1091 /* 177 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1092 /* 179 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1093 /* 181 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1094 /* 184 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1095 /* 187 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1096 /* 189 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1097 /* 191 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1098 /* 193 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1099 /* 194 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1100 /* 197 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1101 /* 200 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1102 /* 203 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1103 /* 206 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1104 /* 208 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1105 /* 211 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1106 /* 214 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1107 /* 216 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1108 /* 218 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1109 /* 220 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
1110 /* 223 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1111 /* 225 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1112 /* 227 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1113 /* 229 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1114 /* 232 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1115 /* 235 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1116 /* 237 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1117 /* 238 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1118 /* 240 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1119 /* 242 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1120 /* 244 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1121 /* 246 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1122 /* 249 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1123 /* 252 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1124 /* 255 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1125 /* 257 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1126 /* 261 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1127 /* 265 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1128 /* 269 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1129 /* 272 */ { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1130 /* 275 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1131 /* 278 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1132 /* 281 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1133 /* 283 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1134 /* 285 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1135 /* 287 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1136 /* 289 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1137 /* 291 */ { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1138 /* 293 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1139 /* 295 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1140 /* 298 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1141 /* 300 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1142 /* 303 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1143 /* 305 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1144 /* 307 */ { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1145 /* 308 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1146 /* 311 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1147 /* 315 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1148 /* 317 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1149 }, {
1150 /* 0 */
1151 /* 0 */ AVR::SREG, AVR::SREG,
1152 /* 2 */ AVR::SREG,
1153 /* 3 */ AVR::SP, AVR::SP, AVR::SREG,
1154 /* 6 */ AVR::SP, AVR::R31R30,
1155 /* 8 */ AVR::R0,
1156 /* 9 */ AVR::R31R30,
1157 /* 10 */ AVR::SP, AVR::SP,
1158 /* 12 */ AVR::R1, AVR::SREG,
1159 /* 14 */ AVR::R17, AVR::SREG,
1160 /* 16 */ AVR::SP,
1161 /* 17 */ AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R1, AVR::R0,
1162 /* 33 */ AVR::R31R30, AVR::R0,
1163 /* 35 */ AVR::R1, AVR::R0, AVR::SREG,
1164 /* 38 */ AVR::R31R30, AVR::R1, AVR::R0,
1165 /* 41 */ AVR::R1, AVR::R0, AVR::R31R30,
1166 }
1167};
1168
1169
1170#ifdef __GNUC__
1171#pragma GCC diagnostic push
1172#pragma GCC diagnostic ignored "-Woverlength-strings"
1173#endif
1174extern const char AVRInstrNameData[] = {
1175 /* 0 */ "G_FLOG10\0"
1176 /* 9 */ "G_FEXP10\0"
1177 /* 18 */ "ROLBRdR1\0"
1178 /* 27 */ "Lsl32\0"
1179 /* 33 */ "Asr32\0"
1180 /* 39 */ "Lsr32\0"
1181 /* 45 */ "G_FLOG2\0"
1182 /* 53 */ "G_FEXP2\0"
1183 /* 61 */ "AtomicLoadSub16\0"
1184 /* 77 */ "AtomicLoad16\0"
1185 /* 90 */ "AtomicLoadAdd16\0"
1186 /* 106 */ "AtomicLoadAnd16\0"
1187 /* 122 */ "AtomicStore16\0"
1188 /* 136 */ "Rol16\0"
1189 /* 142 */ "Lsl16\0"
1190 /* 148 */ "AtomicLoadOr16\0"
1191 /* 163 */ "Ror16\0"
1192 /* 169 */ "AtomicLoadXor16\0"
1193 /* 185 */ "Asr16\0"
1194 /* 191 */ "Lsr16\0"
1195 /* 197 */ "Select16\0"
1196 /* 206 */ "ROLBRdR17\0"
1197 /* 216 */ "AtomicLoadSub8\0"
1198 /* 231 */ "AtomicLoad8\0"
1199 /* 243 */ "AtomicLoadAdd8\0"
1200 /* 258 */ "AtomicLoadAnd8\0"
1201 /* 273 */ "AtomicStore8\0"
1202 /* 286 */ "Rol8\0"
1203 /* 291 */ "Lsl8\0"
1204 /* 296 */ "AtomicLoadOr8\0"
1205 /* 310 */ "Ror8\0"
1206 /* 315 */ "AtomicLoadXor8\0"
1207 /* 330 */ "Asr8\0"
1208 /* 335 */ "Lsr8\0"
1209 /* 340 */ "Select8\0"
1210 /* 348 */ "G_FMA\0"
1211 /* 354 */ "G_STRICT_FMA\0"
1212 /* 367 */ "INRdA\0"
1213 /* 373 */ "INWRdA\0"
1214 /* 380 */ "G_FSUB\0"
1215 /* 387 */ "G_STRICT_FSUB\0"
1216 /* 401 */ "G_ATOMICRMW_FSUB\0"
1217 /* 418 */ "G_SUB\0"
1218 /* 424 */ "G_ATOMICRMW_SUB\0"
1219 /* 440 */ "SBRCRrB\0"
1220 /* 448 */ "SBRSRrB\0"
1221 /* 456 */ "G_INTRINSIC\0"
1222 /* 468 */ "G_FPTRUNC\0"
1223 /* 478 */ "G_INTRINSIC_TRUNC\0"
1224 /* 496 */ "G_TRUNC\0"
1225 /* 504 */ "G_BUILD_VECTOR_TRUNC\0"
1226 /* 525 */ "G_DYN_STACKALLOC\0"
1227 /* 542 */ "SPREAD\0"
1228 /* 549 */ "G_FMAD\0"
1229 /* 556 */ "G_INDEXED_SEXTLOAD\0"
1230 /* 575 */ "G_SEXTLOAD\0"
1231 /* 586 */ "G_INDEXED_ZEXTLOAD\0"
1232 /* 605 */ "G_ZEXTLOAD\0"
1233 /* 616 */ "G_INDEXED_LOAD\0"
1234 /* 631 */ "G_LOAD\0"
1235 /* 638 */ "G_VECREDUCE_FADD\0"
1236 /* 655 */ "G_FADD\0"
1237 /* 662 */ "G_VECREDUCE_SEQ_FADD\0"
1238 /* 683 */ "G_STRICT_FADD\0"
1239 /* 697 */ "G_ATOMICRMW_FADD\0"
1240 /* 714 */ "G_VECREDUCE_ADD\0"
1241 /* 730 */ "G_ADD\0"
1242 /* 736 */ "G_PTR_ADD\0"
1243 /* 746 */ "G_ATOMICRMW_ADD\0"
1244 /* 762 */ "BLD\0"
1245 /* 766 */ "G_ATOMICRMW_NAND\0"
1246 /* 783 */ "G_VECREDUCE_AND\0"
1247 /* 799 */ "G_AND\0"
1248 /* 805 */ "G_ATOMICRMW_AND\0"
1249 /* 821 */ "LIFETIME_END\0"
1250 /* 834 */ "G_BRCOND\0"
1251 /* 843 */ "G_LLROUND\0"
1252 /* 853 */ "G_LROUND\0"
1253 /* 862 */ "G_INTRINSIC_ROUND\0"
1254 /* 880 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
1255 /* 906 */ "LOAD_STACK_GUARD\0"
1256 /* 923 */ "PSEUDO_PROBE\0"
1257 /* 936 */ "G_SSUBE\0"
1258 /* 944 */ "G_USUBE\0"
1259 /* 952 */ "G_FENCE\0"
1260 /* 960 */ "ARITH_FENCE\0"
1261 /* 972 */ "REG_SEQUENCE\0"
1262 /* 985 */ "G_SADDE\0"
1263 /* 993 */ "G_UADDE\0"
1264 /* 1001 */ "G_GET_FPMODE\0"
1265 /* 1014 */ "G_RESET_FPMODE\0"
1266 /* 1029 */ "G_SET_FPMODE\0"
1267 /* 1042 */ "G_FMINNUM_IEEE\0"
1268 /* 1057 */ "G_FMAXNUM_IEEE\0"
1269 /* 1072 */ "G_VSCALE\0"
1270 /* 1081 */ "G_JUMP_TABLE\0"
1271 /* 1094 */ "BUNDLE\0"
1272 /* 1101 */ "G_MEMCPY_INLINE\0"
1273 /* 1117 */ "LOCAL_ESCAPE\0"
1274 /* 1130 */ "G_STACKRESTORE\0"
1275 /* 1145 */ "G_INDEXED_STORE\0"
1276 /* 1161 */ "G_STORE\0"
1277 /* 1169 */ "CPSE\0"
1278 /* 1174 */ "G_BITREVERSE\0"
1279 /* 1187 */ "SPWRITE\0"
1280 /* 1195 */ "DBG_VALUE\0"
1281 /* 1205 */ "G_GLOBAL_VALUE\0"
1282 /* 1220 */ "G_PTRAUTH_GLOBAL_VALUE\0"
1283 /* 1243 */ "CONVERGENCECTRL_GLUE\0"
1284 /* 1264 */ "G_STACKSAVE\0"
1285 /* 1276 */ "G_MEMMOVE\0"
1286 /* 1286 */ "G_FREEZE\0"
1287 /* 1295 */ "G_FCANONICALIZE\0"
1288 /* 1311 */ "G_CTLZ_ZERO_UNDEF\0"
1289 /* 1329 */ "G_CTTZ_ZERO_UNDEF\0"
1290 /* 1347 */ "G_IMPLICIT_DEF\0"
1291 /* 1362 */ "DBG_INSTR_REF\0"
1292 /* 1376 */ "G_FNEG\0"
1293 /* 1383 */ "EXTRACT_SUBREG\0"
1294 /* 1398 */ "INSERT_SUBREG\0"
1295 /* 1412 */ "G_SEXT_INREG\0"
1296 /* 1425 */ "SUBREG_TO_REG\0"
1297 /* 1439 */ "G_ATOMIC_CMPXCHG\0"
1298 /* 1456 */ "G_ATOMICRMW_XCHG\0"
1299 /* 1473 */ "G_FLOG\0"
1300 /* 1480 */ "G_VAARG\0"
1301 /* 1488 */ "PREALLOCATED_ARG\0"
1302 /* 1505 */ "G_PREFETCH\0"
1303 /* 1516 */ "G_SMULH\0"
1304 /* 1524 */ "G_UMULH\0"
1305 /* 1532 */ "G_FTANH\0"
1306 /* 1540 */ "G_FSINH\0"
1307 /* 1548 */ "G_FCOSH\0"
1308 /* 1556 */ "DBG_PHI\0"
1309 /* 1564 */ "G_FPTOSI\0"
1310 /* 1573 */ "RETI\0"
1311 /* 1578 */ "G_FPTOUI\0"
1312 /* 1587 */ "G_FPOWI\0"
1313 /* 1595 */ "BREAK\0"
1314 /* 1601 */ "G_PTRMASK\0"
1315 /* 1611 */ "DESK\0"
1316 /* 1616 */ "SUBIRdK\0"
1317 /* 1624 */ "SBCIRdK\0"
1318 /* 1632 */ "LDIRdK\0"
1319 /* 1639 */ "ANDIRdK\0"
1320 /* 1647 */ "CPIRdK\0"
1321 /* 1654 */ "ORIRdK\0"
1322 /* 1661 */ "LDSRdK\0"
1323 /* 1668 */ "SBIWRdK\0"
1324 /* 1676 */ "SUBIWRdK\0"
1325 /* 1685 */ "SBCIWRdK\0"
1326 /* 1694 */ "ADIWRdK\0"
1327 /* 1702 */ "LDIWRdK\0"
1328 /* 1710 */ "ANDIWRdK\0"
1329 /* 1719 */ "ORIWRdK\0"
1330 /* 1727 */ "LDSWRdK\0"
1331 /* 1735 */ "GC_LABEL\0"
1332 /* 1744 */ "DBG_LABEL\0"
1333 /* 1754 */ "EH_LABEL\0"
1334 /* 1763 */ "ANNOTATION_LABEL\0"
1335 /* 1780 */ "ICALL_BRANCH_FUNNEL\0"
1336 /* 1800 */ "G_FSHL\0"
1337 /* 1807 */ "G_SHL\0"
1338 /* 1813 */ "G_FCEIL\0"
1339 /* 1821 */ "EICALL\0"
1340 /* 1828 */ "PATCHABLE_TAIL_CALL\0"
1341 /* 1848 */ "PATCHABLE_TYPED_EVENT_CALL\0"
1342 /* 1875 */ "PATCHABLE_EVENT_CALL\0"
1343 /* 1896 */ "FENTRY_CALL\0"
1344 /* 1908 */ "KILL\0"
1345 /* 1913 */ "G_CONSTANT_POOL\0"
1346 /* 1929 */ "G_ROTL\0"
1347 /* 1936 */ "G_VECREDUCE_FMUL\0"
1348 /* 1953 */ "G_FMUL\0"
1349 /* 1960 */ "G_VECREDUCE_SEQ_FMUL\0"
1350 /* 1981 */ "G_STRICT_FMUL\0"
1351 /* 1995 */ "G_VECREDUCE_MUL\0"
1352 /* 2011 */ "G_MUL\0"
1353 /* 2017 */ "G_FREM\0"
1354 /* 2024 */ "G_STRICT_FREM\0"
1355 /* 2038 */ "G_SREM\0"
1356 /* 2045 */ "G_UREM\0"
1357 /* 2052 */ "G_SDIVREM\0"
1358 /* 2062 */ "G_UDIVREM\0"
1359 /* 2072 */ "ELPM\0"
1360 /* 2077 */ "SPM\0"
1361 /* 2081 */ "INLINEASM\0"
1362 /* 2091 */ "G_VECREDUCE_FMINIMUM\0"
1363 /* 2112 */ "G_FMINIMUM\0"
1364 /* 2123 */ "G_VECREDUCE_FMAXIMUM\0"
1365 /* 2144 */ "G_FMAXIMUM\0"
1366 /* 2155 */ "G_FMINNUM\0"
1367 /* 2165 */ "G_FMAXNUM\0"
1368 /* 2175 */ "G_FATAN\0"
1369 /* 2183 */ "G_FTAN\0"
1370 /* 2190 */ "G_INTRINSIC_ROUNDEVEN\0"
1371 /* 2212 */ "G_ASSERT_ALIGN\0"
1372 /* 2227 */ "G_FCOPYSIGN\0"
1373 /* 2239 */ "G_VECREDUCE_FMIN\0"
1374 /* 2256 */ "G_ATOMICRMW_FMIN\0"
1375 /* 2273 */ "G_VECREDUCE_SMIN\0"
1376 /* 2290 */ "G_SMIN\0"
1377 /* 2297 */ "G_VECREDUCE_UMIN\0"
1378 /* 2314 */ "G_UMIN\0"
1379 /* 2321 */ "G_ATOMICRMW_UMIN\0"
1380 /* 2338 */ "G_ATOMICRMW_MIN\0"
1381 /* 2354 */ "G_FASIN\0"
1382 /* 2362 */ "G_FSIN\0"
1383 /* 2369 */ "CFI_INSTRUCTION\0"
1384 /* 2385 */ "ADJCALLSTACKDOWN\0"
1385 /* 2402 */ "G_SSUBO\0"
1386 /* 2410 */ "G_USUBO\0"
1387 /* 2418 */ "G_SADDO\0"
1388 /* 2426 */ "G_UADDO\0"
1389 /* 2434 */ "JUMP_TABLE_DEBUG_INFO\0"
1390 /* 2456 */ "G_SMULO\0"
1391 /* 2464 */ "G_UMULO\0"
1392 /* 2472 */ "G_BZERO\0"
1393 /* 2480 */ "STACKMAP\0"
1394 /* 2489 */ "G_DEBUGTRAP\0"
1395 /* 2501 */ "G_UBSANTRAP\0"
1396 /* 2513 */ "G_TRAP\0"
1397 /* 2520 */ "G_ATOMICRMW_UDEC_WRAP\0"
1398 /* 2542 */ "G_ATOMICRMW_UINC_WRAP\0"
1399 /* 2564 */ "G_BSWAP\0"
1400 /* 2572 */ "SLEEP\0"
1401 /* 2578 */ "G_SITOFP\0"
1402 /* 2587 */ "G_UITOFP\0"
1403 /* 2596 */ "G_FCMP\0"
1404 /* 2603 */ "G_ICMP\0"
1405 /* 2610 */ "G_SCMP\0"
1406 /* 2617 */ "G_UCMP\0"
1407 /* 2624 */ "EIJMP\0"
1408 /* 2630 */ "NOP\0"
1409 /* 2634 */ "CONVERGENCECTRL_LOOP\0"
1410 /* 2655 */ "G_CTPOP\0"
1411 /* 2663 */ "PATCHABLE_OP\0"
1412 /* 2676 */ "FAULTING_OP\0"
1413 /* 2688 */ "ADJCALLSTACKUP\0"
1414 /* 2703 */ "PREALLOCATED_SETUP\0"
1415 /* 2722 */ "G_FLDEXP\0"
1416 /* 2731 */ "G_STRICT_FLDEXP\0"
1417 /* 2747 */ "G_FEXP\0"
1418 /* 2754 */ "G_FFREXP\0"
1419 /* 2763 */ "LDDWRdYQ\0"
1420 /* 2772 */ "LDDRdPtrQ\0"
1421 /* 2782 */ "LDDWRdPtrQ\0"
1422 /* 2793 */ "G_BR\0"
1423 /* 2798 */ "INLINEASM_BR\0"
1424 /* 2811 */ "G_BLOCK_ADDR\0"
1425 /* 2824 */ "WDR\0"
1426 /* 2828 */ "MEMBARRIER\0"
1427 /* 2839 */ "G_CONSTANT_FOLD_BARRIER\0"
1428 /* 2863 */ "PATCHABLE_FUNCTION_ENTER\0"
1429 /* 2888 */ "G_READCYCLECOUNTER\0"
1430 /* 2907 */ "G_READSTEADYCOUNTER\0"
1431 /* 2927 */ "G_READ_REGISTER\0"
1432 /* 2943 */ "G_WRITE_REGISTER\0"
1433 /* 2960 */ "G_ASHR\0"
1434 /* 2967 */ "G_FSHR\0"
1435 /* 2974 */ "G_LSHR\0"
1436 /* 2981 */ "CONVERGENCECTRL_ANCHOR\0"
1437 /* 3004 */ "G_FFLOOR\0"
1438 /* 3013 */ "G_EXTRACT_SUBVECTOR\0"
1439 /* 3033 */ "G_INSERT_SUBVECTOR\0"
1440 /* 3052 */ "G_BUILD_VECTOR\0"
1441 /* 3067 */ "G_SHUFFLE_VECTOR\0"
1442 /* 3084 */ "G_SPLAT_VECTOR\0"
1443 /* 3099 */ "G_VECREDUCE_XOR\0"
1444 /* 3115 */ "G_XOR\0"
1445 /* 3121 */ "G_ATOMICRMW_XOR\0"
1446 /* 3137 */ "G_VECREDUCE_OR\0"
1447 /* 3152 */ "G_OR\0"
1448 /* 3157 */ "G_ATOMICRMW_OR\0"
1449 /* 3172 */ "G_ROTR\0"
1450 /* 3179 */ "G_INTTOPTR\0"
1451 /* 3190 */ "G_FABS\0"
1452 /* 3197 */ "G_ABS\0"
1453 /* 3203 */ "G_UNMERGE_VALUES\0"
1454 /* 3220 */ "G_MERGE_VALUES\0"
1455 /* 3235 */ "FMULS\0"
1456 /* 3241 */ "G_FACOS\0"
1457 /* 3249 */ "G_FCOS\0"
1458 /* 3256 */ "G_CONCAT_VECTORS\0"
1459 /* 3273 */ "COPY_TO_REGCLASS\0"
1460 /* 3290 */ "G_IS_FPCLASS\0"
1461 /* 3303 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
1462 /* 3333 */ "G_VECTOR_COMPRESS\0"
1463 /* 3351 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
1464 /* 3378 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
1465 /* 3416 */ "G_SSUBSAT\0"
1466 /* 3426 */ "G_USUBSAT\0"
1467 /* 3436 */ "G_SADDSAT\0"
1468 /* 3446 */ "G_UADDSAT\0"
1469 /* 3456 */ "G_SSHLSAT\0"
1470 /* 3466 */ "G_USHLSAT\0"
1471 /* 3476 */ "G_SMULFIXSAT\0"
1472 /* 3489 */ "G_UMULFIXSAT\0"
1473 /* 3502 */ "G_SDIVFIXSAT\0"
1474 /* 3515 */ "G_UDIVFIXSAT\0"
1475 /* 3528 */ "G_EXTRACT\0"
1476 /* 3538 */ "G_SELECT\0"
1477 /* 3547 */ "G_BRINDIRECT\0"
1478 /* 3560 */ "PATCHABLE_RET\0"
1479 /* 3574 */ "G_MEMSET\0"
1480 /* 3583 */ "PATCHABLE_FUNCTION_EXIT\0"
1481 /* 3607 */ "G_BRJT\0"
1482 /* 3614 */ "G_EXTRACT_VECTOR_ELT\0"
1483 /* 3635 */ "G_INSERT_VECTOR_ELT\0"
1484 /* 3655 */ "G_FCONSTANT\0"
1485 /* 3667 */ "G_CONSTANT\0"
1486 /* 3678 */ "G_INTRINSIC_CONVERGENT\0"
1487 /* 3701 */ "STATEPOINT\0"
1488 /* 3712 */ "PATCHPOINT\0"
1489 /* 3723 */ "G_PTRTOINT\0"
1490 /* 3734 */ "G_FRINT\0"
1491 /* 3742 */ "G_INTRINSIC_LLRINT\0"
1492 /* 3761 */ "G_INTRINSIC_LRINT\0"
1493 /* 3779 */ "G_FNEARBYINT\0"
1494 /* 3792 */ "G_VASTART\0"
1495 /* 3802 */ "LIFETIME_START\0"
1496 /* 3817 */ "G_INVOKE_REGION_START\0"
1497 /* 3839 */ "G_INSERT\0"
1498 /* 3848 */ "G_FSQRT\0"
1499 /* 3856 */ "G_STRICT_FSQRT\0"
1500 /* 3871 */ "G_BITCAST\0"
1501 /* 3881 */ "G_ADDRSPACE_CAST\0"
1502 /* 3898 */ "BST\0"
1503 /* 3902 */ "DBG_VALUE_LIST\0"
1504 /* 3917 */ "G_FPEXT\0"
1505 /* 3925 */ "G_SEXT\0"
1506 /* 3932 */ "G_ASSERT_SEXT\0"
1507 /* 3946 */ "G_ANYEXT\0"
1508 /* 3955 */ "G_ZEXT\0"
1509 /* 3962 */ "G_ASSERT_ZEXT\0"
1510 /* 3976 */ "FMULSU\0"
1511 /* 3983 */ "G_FDIV\0"
1512 /* 3990 */ "G_STRICT_FDIV\0"
1513 /* 4004 */ "G_SDIV\0"
1514 /* 4011 */ "G_UDIV\0"
1515 /* 4018 */ "G_GET_FPENV\0"
1516 /* 4030 */ "G_RESET_FPENV\0"
1517 /* 4044 */ "G_SET_FPENV\0"
1518 /* 4056 */ "G_FPOW\0"
1519 /* 4063 */ "G_VECREDUCE_FMAX\0"
1520 /* 4080 */ "G_ATOMICRMW_FMAX\0"
1521 /* 4097 */ "G_VECREDUCE_SMAX\0"
1522 /* 4114 */ "G_SMAX\0"
1523 /* 4121 */ "G_VECREDUCE_UMAX\0"
1524 /* 4138 */ "G_UMAX\0"
1525 /* 4145 */ "G_ATOMICRMW_UMAX\0"
1526 /* 4162 */ "G_ATOMICRMW_MAX\0"
1527 /* 4178 */ "FRMIDX\0"
1528 /* 4185 */ "G_FRAME_INDEX\0"
1529 /* 4199 */ "G_SBFX\0"
1530 /* 4206 */ "G_UBFX\0"
1531 /* 4213 */ "G_SMULFIX\0"
1532 /* 4223 */ "G_UMULFIX\0"
1533 /* 4233 */ "G_SDIVFIX\0"
1534 /* 4243 */ "G_UDIVFIX\0"
1535 /* 4253 */ "G_MEMCPY\0"
1536 /* 4262 */ "COPY\0"
1537 /* 4267 */ "CONVERGENCECTRL_ENTRY\0"
1538 /* 4289 */ "G_CTLZ\0"
1539 /* 4296 */ "G_CTTZ\0"
1540 /* 4303 */ "ELPMBRdZ\0"
1541 /* 4312 */ "ELPMRdZ\0"
1542 /* 4320 */ "ELPMWRdZ\0"
1543 /* 4329 */ "SBICAb\0"
1544 /* 4336 */ "CBIAb\0"
1545 /* 4342 */ "SBIAb\0"
1546 /* 4348 */ "SBISAb\0"
1547 /* 4355 */ "LDRdPtrPd\0"
1548 /* 4365 */ "LDWRdPtrPd\0"
1549 /* 4376 */ "RORBRd\0"
1550 /* 4383 */ "DECRd\0"
1551 /* 4389 */ "INCRd\0"
1552 /* 4395 */ "NEGRd\0"
1553 /* 4401 */ "COMRd\0"
1554 /* 4407 */ "LSLBNRd\0"
1555 /* 4415 */ "ASRBNRd\0"
1556 /* 4423 */ "LSRBNRd\0"
1557 /* 4431 */ "LSLWNRd\0"
1558 /* 4439 */ "ASRWNRd\0"
1559 /* 4447 */ "LSRWNRd\0"
1560 /* 4455 */ "SWAPRd\0"
1561 /* 4462 */ "POPRd\0"
1562 /* 4468 */ "RORRd\0"
1563 /* 4474 */ "ASRRd\0"
1564 /* 4480 */ "LSRRd\0"
1565 /* 4486 */ "NEGWRd\0"
1566 /* 4493 */ "ROLWRd\0"
1567 /* 4500 */ "LSLWRd\0"
1568 /* 4507 */ "COMWRd\0"
1569 /* 4514 */ "POPWRd\0"
1570 /* 4521 */ "RORWRd\0"
1571 /* 4528 */ "ASRWRd\0"
1572 /* 4535 */ "LSRWRd\0"
1573 /* 4542 */ "LACZRd\0"
1574 /* 4549 */ "XCHZRd\0"
1575 /* 4556 */ "LASZRd\0"
1576 /* 4563 */ "LATZRd\0"
1577 /* 4570 */ "LSLWHiRd\0"
1578 /* 4579 */ "ASRWLoRd\0"
1579 /* 4588 */ "LSRWLoRd\0"
1580 /* 4597 */ "AtomicFence\0"
1581 /* 4609 */ "SPMZPi\0"
1582 /* 4616 */ "ELPMBRdZPi\0"
1583 /* 4627 */ "ELPMRdZPi\0"
1584 /* 4637 */ "ELPMWRdZPi\0"
1585 /* 4648 */ "LDRdPtrPi\0"
1586 /* 4658 */ "LDWRdPtrPi\0"
1587 /* 4669 */ "BRGEk\0"
1588 /* 4675 */ "BRNEk\0"
1589 /* 4681 */ "BRSHk\0"
1590 /* 4687 */ "BRMIk\0"
1591 /* 4693 */ "RCALLk\0"
1592 /* 4700 */ "BRPLk\0"
1593 /* 4706 */ "BRLOk\0"
1594 /* 4712 */ "RJMPk\0"
1595 /* 4718 */ "BREQk\0"
1596 /* 4724 */ "BRLTk\0"
1597 /* 4730 */ "BRBCsk\0"
1598 /* 4737 */ "BRBSsk\0"
1599 /* 4744 */ "CopyZero\0"
1600 /* 4753 */ "OUTARr\0"
1601 /* 4760 */ "OUTWARr\0"
1602 /* 4768 */ "PUSHRr\0"
1603 /* 4775 */ "STSKRr\0"
1604 /* 4782 */ "STSWKRr\0"
1605 /* 4790 */ "STDSPQRr\0"
1606 /* 4799 */ "STDWSPQRr\0"
1607 /* 4809 */ "STDPtrQRr\0"
1608 /* 4819 */ "STDWPtrQRr\0"
1609 /* 4830 */ "PUSHWRr\0"
1610 /* 4838 */ "STPtrPdRr\0"
1611 /* 4848 */ "STWPtrPdRr\0"
1612 /* 4859 */ "SUBRdRr\0"
1613 /* 4867 */ "SBCRdRr\0"
1614 /* 4875 */ "ADCRdRr\0"
1615 /* 4883 */ "CPCRdRr\0"
1616 /* 4891 */ "ADDRdRr\0"
1617 /* 4899 */ "ANDRdRr\0"
1618 /* 4907 */ "MULRdRr\0"
1619 /* 4915 */ "CPRdRr\0"
1620 /* 4922 */ "EORRdRr\0"
1621 /* 4930 */ "MULSRdRr\0"
1622 /* 4939 */ "MULSURdRr\0"
1623 /* 4949 */ "MOVRdRr\0"
1624 /* 4957 */ "SUBWRdRr\0"
1625 /* 4966 */ "SBCWRdRr\0"
1626 /* 4975 */ "ADCWRdRr\0"
1627 /* 4984 */ "CPCWRdRr\0"
1628 /* 4993 */ "ADDWRdRr\0"
1629 /* 5002 */ "ANDWRdRr\0"
1630 /* 5011 */ "CPWRdRr\0"
1631 /* 5019 */ "EORWRdRr\0"
1632 /* 5028 */ "MOVWRdRr\0"
1633 /* 5037 */ "STPtrPiRr\0"
1634 /* 5047 */ "STWPtrPiRr\0"
1635 /* 5058 */ "STPtrRr\0"
1636 /* 5066 */ "STWPtrRr\0"
1637 /* 5075 */ "LDRdPtr\0"
1638 /* 5083 */ "LDWRdPtr\0"
1639 /* 5092 */ "BCLRs\0"
1640 /* 5098 */ "BSETs\0"
1641 /* 5104 */ "LDSRdKTiny\0"
1642 /* 5115 */ "STSKRrTiny\0"
1643};
1644#ifdef __GNUC__
1645#pragma GCC diagnostic pop
1646#endif
1647
1648extern const unsigned AVRInstrNameIndices[] = {
1649 1560U, 2081U, 2798U, 2369U, 1754U, 1735U, 1763U, 1908U,
1650 1383U, 1398U, 1349U, 1425U, 3273U, 1195U, 3902U, 1362U,
1651 1556U, 1744U, 972U, 4262U, 1094U, 3802U, 821U, 923U,
1652 960U, 2480U, 1896U, 3712U, 906U, 2703U, 1488U, 3701U,
1653 1117U, 2676U, 2663U, 2863U, 3560U, 3583U, 1828U, 1875U,
1654 1848U, 1780U, 2828U, 2434U, 4267U, 2981U, 2634U, 1243U,
1655 3932U, 3962U, 2212U, 730U, 418U, 2011U, 4004U, 4011U,
1656 2038U, 2045U, 2052U, 2062U, 799U, 3152U, 3115U, 1347U,
1657 1558U, 4185U, 1205U, 1220U, 1913U, 3528U, 3203U, 3839U,
1658 3220U, 3052U, 504U, 3256U, 3723U, 3179U, 3871U, 1286U,
1659 2839U, 880U, 478U, 862U, 3761U, 3742U, 2190U, 2888U,
1660 2907U, 631U, 575U, 605U, 616U, 556U, 586U, 1161U,
1661 1145U, 3303U, 1439U, 1456U, 746U, 424U, 805U, 766U,
1662 3157U, 3121U, 4162U, 2338U, 4145U, 2321U, 697U, 401U,
1663 4080U, 2256U, 2542U, 2520U, 952U, 1505U, 834U, 3547U,
1664 3817U, 456U, 3351U, 3678U, 3378U, 3946U, 496U, 3667U,
1665 3655U, 3792U, 1480U, 3925U, 1412U, 3955U, 1807U, 2974U,
1666 2960U, 1800U, 2967U, 3172U, 1929U, 2603U, 2596U, 2610U,
1667 2617U, 3538U, 2426U, 993U, 2410U, 944U, 2418U, 985U,
1668 2402U, 936U, 2464U, 2456U, 1524U, 1516U, 3446U, 3436U,
1669 3426U, 3416U, 3466U, 3456U, 4213U, 4223U, 3476U, 3489U,
1670 4233U, 4243U, 3502U, 3515U, 655U, 380U, 1953U, 348U,
1671 549U, 3983U, 2017U, 4056U, 1587U, 2747U, 53U, 9U,
1672 1473U, 45U, 0U, 2722U, 2754U, 1376U, 3917U, 468U,
1673 1564U, 1578U, 2578U, 2587U, 3190U, 2227U, 3290U, 1295U,
1674 2155U, 2165U, 1042U, 1057U, 2112U, 2144U, 4018U, 4044U,
1675 4030U, 1001U, 1029U, 1014U, 736U, 1601U, 2290U, 4114U,
1676 2314U, 4138U, 3197U, 853U, 843U, 2793U, 3607U, 1072U,
1677 3033U, 3013U, 3635U, 3614U, 3067U, 3084U, 3333U, 4296U,
1678 1329U, 4289U, 1311U, 2655U, 2564U, 1174U, 1813U, 3249U,
1679 2362U, 2183U, 3241U, 2354U, 2175U, 1548U, 1540U, 1532U,
1680 3848U, 3004U, 3734U, 3779U, 3881U, 2811U, 1081U, 525U,
1681 1264U, 1130U, 683U, 387U, 1981U, 3990U, 2024U, 354U,
1682 3856U, 2731U, 2927U, 2943U, 4253U, 1101U, 1276U, 3574U,
1683 2472U, 2513U, 2489U, 2501U, 662U, 1960U, 638U, 1936U,
1684 4063U, 2239U, 2123U, 2091U, 714U, 1995U, 783U, 3137U,
1685 3099U, 4097U, 2273U, 4121U, 2297U, 4199U, 4206U, 4975U,
1686 4993U, 2385U, 2688U, 1710U, 5002U, 4415U, 4579U, 4439U,
1687 4528U, 185U, 33U, 330U, 4597U, 77U, 231U, 90U,
1688 243U, 106U, 258U, 148U, 296U, 61U, 216U, 169U,
1689 315U, 122U, 273U, 4507U, 4984U, 5011U, 4744U, 4303U,
1690 4616U, 4320U, 4637U, 5019U, 4178U, 373U, 2782U, 2763U,
1691 1702U, 1727U, 5083U, 4365U, 4658U, 4304U, 4321U, 4638U,
1692 4407U, 4570U, 4431U, 4500U, 4423U, 4588U, 4447U, 4535U,
1693 142U, 27U, 291U, 191U, 39U, 335U, 4486U, 1719U,
1694 5020U, 4760U, 4514U, 4830U, 18U, 206U, 4493U, 4376U,
1695 4521U, 136U, 286U, 163U, 310U, 1685U, 4966U, 3927U,
1696 542U, 1187U, 4790U, 4819U, 4799U, 4782U, 4848U, 5047U,
1697 5066U, 1676U, 4957U, 197U, 340U, 3957U, 4875U, 4891U,
1698 1694U, 1639U, 4899U, 4474U, 5092U, 762U, 4730U, 4737U,
1699 1595U, 4718U, 4669U, 4706U, 4724U, 4687U, 4675U, 4700U,
1700 4681U, 5098U, 3898U, 4694U, 4336U, 4401U, 4883U, 1647U,
1701 4915U, 1169U, 4383U, 1611U, 1821U, 2624U, 2072U, 4312U,
1702 4627U, 4922U, 1948U, 3235U, 3976U, 1822U, 2625U, 4389U,
1703 367U, 4713U, 4542U, 4556U, 4563U, 2772U, 1632U, 5075U,
1704 4355U, 4648U, 1661U, 5104U, 2073U, 4313U, 4628U, 4480U,
1705 4949U, 5028U, 4907U, 4930U, 4939U, 4395U, 2630U, 1654U,
1706 4923U, 4753U, 4462U, 4768U, 4693U, 3570U, 1573U, 4712U,
1707 4468U, 1624U, 4867U, 4342U, 4329U, 4348U, 1668U, 440U,
1708 448U, 2572U, 2077U, 4609U, 4809U, 4838U, 5037U, 5058U,
1709 4775U, 5115U, 1616U, 4859U, 4455U, 2824U, 4549U,
1710};
1711
1712static inline void InitAVRMCInstrInfo(MCInstrInfo *II) {
1713 II->InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 487);
1714}
1715
1716} // end namespace llvm
1717#endif // GET_INSTRINFO_MC_DESC
1718
1719#ifdef GET_INSTRINFO_HEADER
1720#undef GET_INSTRINFO_HEADER
1721namespace llvm {
1722struct AVRGenInstrInfo : public TargetInstrInfo {
1723 explicit AVRGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1724 ~AVRGenInstrInfo() override = default;
1725
1726};
1727} // end namespace llvm
1728#endif // GET_INSTRINFO_HEADER
1729
1730#ifdef GET_INSTRINFO_HELPER_DECLS
1731#undef GET_INSTRINFO_HELPER_DECLS
1732
1733
1734#endif // GET_INSTRINFO_HELPER_DECLS
1735
1736#ifdef GET_INSTRINFO_HELPERS
1737#undef GET_INSTRINFO_HELPERS
1738
1739#endif // GET_INSTRINFO_HELPERS
1740
1741#ifdef GET_INSTRINFO_CTOR_DTOR
1742#undef GET_INSTRINFO_CTOR_DTOR
1743namespace llvm {
1744extern const AVRInstrTable AVRDescs;
1745extern const unsigned AVRInstrNameIndices[];
1746extern const char AVRInstrNameData[];
1747AVRGenInstrInfo::AVRGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1748 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1749 InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 487);
1750}
1751} // end namespace llvm
1752#endif // GET_INSTRINFO_CTOR_DTOR
1753
1754#ifdef GET_INSTRINFO_OPERAND_ENUM
1755#undef GET_INSTRINFO_OPERAND_ENUM
1756namespace llvm {
1757namespace AVR {
1758namespace OpName {
1759enum {
1760 OPERAND_LAST
1761};
1762} // end namespace OpName
1763} // end namespace AVR
1764} // end namespace llvm
1765#endif //GET_INSTRINFO_OPERAND_ENUM
1766
1767#ifdef GET_INSTRINFO_NAMED_OPS
1768#undef GET_INSTRINFO_NAMED_OPS
1769namespace llvm {
1770namespace AVR {
1771LLVM_READONLY
1772int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1773 return -1;
1774}
1775} // end namespace AVR
1776} // end namespace llvm
1777#endif //GET_INSTRINFO_NAMED_OPS
1778
1779#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1780#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1781namespace llvm {
1782namespace AVR {
1783namespace OpTypes {
1784enum OperandType {
1785 LDDSTDPtrReg = 0,
1786 LDSTPtrReg = 1,
1787 brtarget_13 = 2,
1788 call_target = 3,
1789 f32imm = 4,
1790 f64imm = 5,
1791 i1imm = 6,
1792 i8imm = 7,
1793 i16imm = 8,
1794 i32imm = 9,
1795 i64imm = 10,
1796 imm7tiny = 11,
1797 imm16 = 12,
1798 imm_arith6 = 13,
1799 imm_com8 = 14,
1800 imm_ldi8 = 15,
1801 imm_port5 = 16,
1802 imm_port6 = 17,
1803 memri = 18,
1804 memspi = 19,
1805 ptype0 = 20,
1806 ptype1 = 21,
1807 ptype2 = 22,
1808 ptype3 = 23,
1809 ptype4 = 24,
1810 ptype5 = 25,
1811 rcalltarget_13 = 26,
1812 relbrtarget_7 = 27,
1813 type0 = 28,
1814 type1 = 29,
1815 type2 = 30,
1816 type3 = 31,
1817 type4 = 32,
1818 type5 = 33,
1819 untyped_imm_0 = 34,
1820 CCR = 35,
1821 DLDREGS = 36,
1822 DREGS = 37,
1823 DREGSLD8lo = 38,
1824 DREGSMOVW = 39,
1825 DREGSlo = 40,
1826 GPR8 = 41,
1827 GPR8lo = 42,
1828 GPRSP = 43,
1829 IWREGS = 44,
1830 LD8 = 45,
1831 LD8lo = 46,
1832 PTRDISPREGS = 47,
1833 PTRREGS = 48,
1834 ZREG = 49,
1835 OPERAND_TYPE_LIST_END
1836};
1837} // end namespace OpTypes
1838} // end namespace AVR
1839} // end namespace llvm
1840#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1841
1842#ifdef GET_INSTRINFO_OPERAND_TYPE
1843#undef GET_INSTRINFO_OPERAND_TYPE
1844namespace llvm {
1845namespace AVR {
1846LLVM_READONLY
1847static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
1848 static const uint16_t Offsets[] = {
1849 /* PHI */
1850 0,
1851 /* INLINEASM */
1852 1,
1853 /* INLINEASM_BR */
1854 1,
1855 /* CFI_INSTRUCTION */
1856 1,
1857 /* EH_LABEL */
1858 2,
1859 /* GC_LABEL */
1860 3,
1861 /* ANNOTATION_LABEL */
1862 4,
1863 /* KILL */
1864 5,
1865 /* EXTRACT_SUBREG */
1866 5,
1867 /* INSERT_SUBREG */
1868 8,
1869 /* IMPLICIT_DEF */
1870 12,
1871 /* SUBREG_TO_REG */
1872 13,
1873 /* COPY_TO_REGCLASS */
1874 17,
1875 /* DBG_VALUE */
1876 20,
1877 /* DBG_VALUE_LIST */
1878 20,
1879 /* DBG_INSTR_REF */
1880 20,
1881 /* DBG_PHI */
1882 20,
1883 /* DBG_LABEL */
1884 20,
1885 /* REG_SEQUENCE */
1886 21,
1887 /* COPY */
1888 23,
1889 /* BUNDLE */
1890 25,
1891 /* LIFETIME_START */
1892 25,
1893 /* LIFETIME_END */
1894 26,
1895 /* PSEUDO_PROBE */
1896 27,
1897 /* ARITH_FENCE */
1898 31,
1899 /* STACKMAP */
1900 33,
1901 /* FENTRY_CALL */
1902 35,
1903 /* PATCHPOINT */
1904 35,
1905 /* LOAD_STACK_GUARD */
1906 41,
1907 /* PREALLOCATED_SETUP */
1908 42,
1909 /* PREALLOCATED_ARG */
1910 43,
1911 /* STATEPOINT */
1912 46,
1913 /* LOCAL_ESCAPE */
1914 46,
1915 /* FAULTING_OP */
1916 48,
1917 /* PATCHABLE_OP */
1918 49,
1919 /* PATCHABLE_FUNCTION_ENTER */
1920 49,
1921 /* PATCHABLE_RET */
1922 49,
1923 /* PATCHABLE_FUNCTION_EXIT */
1924 49,
1925 /* PATCHABLE_TAIL_CALL */
1926 49,
1927 /* PATCHABLE_EVENT_CALL */
1928 49,
1929 /* PATCHABLE_TYPED_EVENT_CALL */
1930 51,
1931 /* ICALL_BRANCH_FUNNEL */
1932 54,
1933 /* MEMBARRIER */
1934 54,
1935 /* JUMP_TABLE_DEBUG_INFO */
1936 54,
1937 /* CONVERGENCECTRL_ENTRY */
1938 55,
1939 /* CONVERGENCECTRL_ANCHOR */
1940 56,
1941 /* CONVERGENCECTRL_LOOP */
1942 57,
1943 /* CONVERGENCECTRL_GLUE */
1944 59,
1945 /* G_ASSERT_SEXT */
1946 60,
1947 /* G_ASSERT_ZEXT */
1948 63,
1949 /* G_ASSERT_ALIGN */
1950 66,
1951 /* G_ADD */
1952 69,
1953 /* G_SUB */
1954 72,
1955 /* G_MUL */
1956 75,
1957 /* G_SDIV */
1958 78,
1959 /* G_UDIV */
1960 81,
1961 /* G_SREM */
1962 84,
1963 /* G_UREM */
1964 87,
1965 /* G_SDIVREM */
1966 90,
1967 /* G_UDIVREM */
1968 94,
1969 /* G_AND */
1970 98,
1971 /* G_OR */
1972 101,
1973 /* G_XOR */
1974 104,
1975 /* G_IMPLICIT_DEF */
1976 107,
1977 /* G_PHI */
1978 108,
1979 /* G_FRAME_INDEX */
1980 109,
1981 /* G_GLOBAL_VALUE */
1982 111,
1983 /* G_PTRAUTH_GLOBAL_VALUE */
1984 113,
1985 /* G_CONSTANT_POOL */
1986 118,
1987 /* G_EXTRACT */
1988 120,
1989 /* G_UNMERGE_VALUES */
1990 123,
1991 /* G_INSERT */
1992 125,
1993 /* G_MERGE_VALUES */
1994 129,
1995 /* G_BUILD_VECTOR */
1996 131,
1997 /* G_BUILD_VECTOR_TRUNC */
1998 133,
1999 /* G_CONCAT_VECTORS */
2000 135,
2001 /* G_PTRTOINT */
2002 137,
2003 /* G_INTTOPTR */
2004 139,
2005 /* G_BITCAST */
2006 141,
2007 /* G_FREEZE */
2008 143,
2009 /* G_CONSTANT_FOLD_BARRIER */
2010 145,
2011 /* G_INTRINSIC_FPTRUNC_ROUND */
2012 147,
2013 /* G_INTRINSIC_TRUNC */
2014 150,
2015 /* G_INTRINSIC_ROUND */
2016 152,
2017 /* G_INTRINSIC_LRINT */
2018 154,
2019 /* G_INTRINSIC_LLRINT */
2020 156,
2021 /* G_INTRINSIC_ROUNDEVEN */
2022 158,
2023 /* G_READCYCLECOUNTER */
2024 160,
2025 /* G_READSTEADYCOUNTER */
2026 161,
2027 /* G_LOAD */
2028 162,
2029 /* G_SEXTLOAD */
2030 164,
2031 /* G_ZEXTLOAD */
2032 166,
2033 /* G_INDEXED_LOAD */
2034 168,
2035 /* G_INDEXED_SEXTLOAD */
2036 173,
2037 /* G_INDEXED_ZEXTLOAD */
2038 178,
2039 /* G_STORE */
2040 183,
2041 /* G_INDEXED_STORE */
2042 185,
2043 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
2044 190,
2045 /* G_ATOMIC_CMPXCHG */
2046 195,
2047 /* G_ATOMICRMW_XCHG */
2048 199,
2049 /* G_ATOMICRMW_ADD */
2050 202,
2051 /* G_ATOMICRMW_SUB */
2052 205,
2053 /* G_ATOMICRMW_AND */
2054 208,
2055 /* G_ATOMICRMW_NAND */
2056 211,
2057 /* G_ATOMICRMW_OR */
2058 214,
2059 /* G_ATOMICRMW_XOR */
2060 217,
2061 /* G_ATOMICRMW_MAX */
2062 220,
2063 /* G_ATOMICRMW_MIN */
2064 223,
2065 /* G_ATOMICRMW_UMAX */
2066 226,
2067 /* G_ATOMICRMW_UMIN */
2068 229,
2069 /* G_ATOMICRMW_FADD */
2070 232,
2071 /* G_ATOMICRMW_FSUB */
2072 235,
2073 /* G_ATOMICRMW_FMAX */
2074 238,
2075 /* G_ATOMICRMW_FMIN */
2076 241,
2077 /* G_ATOMICRMW_UINC_WRAP */
2078 244,
2079 /* G_ATOMICRMW_UDEC_WRAP */
2080 247,
2081 /* G_FENCE */
2082 250,
2083 /* G_PREFETCH */
2084 252,
2085 /* G_BRCOND */
2086 256,
2087 /* G_BRINDIRECT */
2088 258,
2089 /* G_INVOKE_REGION_START */
2090 259,
2091 /* G_INTRINSIC */
2092 259,
2093 /* G_INTRINSIC_W_SIDE_EFFECTS */
2094 260,
2095 /* G_INTRINSIC_CONVERGENT */
2096 261,
2097 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
2098 262,
2099 /* G_ANYEXT */
2100 263,
2101 /* G_TRUNC */
2102 265,
2103 /* G_CONSTANT */
2104 267,
2105 /* G_FCONSTANT */
2106 269,
2107 /* G_VASTART */
2108 271,
2109 /* G_VAARG */
2110 272,
2111 /* G_SEXT */
2112 275,
2113 /* G_SEXT_INREG */
2114 277,
2115 /* G_ZEXT */
2116 280,
2117 /* G_SHL */
2118 282,
2119 /* G_LSHR */
2120 285,
2121 /* G_ASHR */
2122 288,
2123 /* G_FSHL */
2124 291,
2125 /* G_FSHR */
2126 295,
2127 /* G_ROTR */
2128 299,
2129 /* G_ROTL */
2130 302,
2131 /* G_ICMP */
2132 305,
2133 /* G_FCMP */
2134 309,
2135 /* G_SCMP */
2136 313,
2137 /* G_UCMP */
2138 316,
2139 /* G_SELECT */
2140 319,
2141 /* G_UADDO */
2142 323,
2143 /* G_UADDE */
2144 327,
2145 /* G_USUBO */
2146 332,
2147 /* G_USUBE */
2148 336,
2149 /* G_SADDO */
2150 341,
2151 /* G_SADDE */
2152 345,
2153 /* G_SSUBO */
2154 350,
2155 /* G_SSUBE */
2156 354,
2157 /* G_UMULO */
2158 359,
2159 /* G_SMULO */
2160 363,
2161 /* G_UMULH */
2162 367,
2163 /* G_SMULH */
2164 370,
2165 /* G_UADDSAT */
2166 373,
2167 /* G_SADDSAT */
2168 376,
2169 /* G_USUBSAT */
2170 379,
2171 /* G_SSUBSAT */
2172 382,
2173 /* G_USHLSAT */
2174 385,
2175 /* G_SSHLSAT */
2176 388,
2177 /* G_SMULFIX */
2178 391,
2179 /* G_UMULFIX */
2180 395,
2181 /* G_SMULFIXSAT */
2182 399,
2183 /* G_UMULFIXSAT */
2184 403,
2185 /* G_SDIVFIX */
2186 407,
2187 /* G_UDIVFIX */
2188 411,
2189 /* G_SDIVFIXSAT */
2190 415,
2191 /* G_UDIVFIXSAT */
2192 419,
2193 /* G_FADD */
2194 423,
2195 /* G_FSUB */
2196 426,
2197 /* G_FMUL */
2198 429,
2199 /* G_FMA */
2200 432,
2201 /* G_FMAD */
2202 436,
2203 /* G_FDIV */
2204 440,
2205 /* G_FREM */
2206 443,
2207 /* G_FPOW */
2208 446,
2209 /* G_FPOWI */
2210 449,
2211 /* G_FEXP */
2212 452,
2213 /* G_FEXP2 */
2214 454,
2215 /* G_FEXP10 */
2216 456,
2217 /* G_FLOG */
2218 458,
2219 /* G_FLOG2 */
2220 460,
2221 /* G_FLOG10 */
2222 462,
2223 /* G_FLDEXP */
2224 464,
2225 /* G_FFREXP */
2226 467,
2227 /* G_FNEG */
2228 470,
2229 /* G_FPEXT */
2230 472,
2231 /* G_FPTRUNC */
2232 474,
2233 /* G_FPTOSI */
2234 476,
2235 /* G_FPTOUI */
2236 478,
2237 /* G_SITOFP */
2238 480,
2239 /* G_UITOFP */
2240 482,
2241 /* G_FABS */
2242 484,
2243 /* G_FCOPYSIGN */
2244 486,
2245 /* G_IS_FPCLASS */
2246 489,
2247 /* G_FCANONICALIZE */
2248 492,
2249 /* G_FMINNUM */
2250 494,
2251 /* G_FMAXNUM */
2252 497,
2253 /* G_FMINNUM_IEEE */
2254 500,
2255 /* G_FMAXNUM_IEEE */
2256 503,
2257 /* G_FMINIMUM */
2258 506,
2259 /* G_FMAXIMUM */
2260 509,
2261 /* G_GET_FPENV */
2262 512,
2263 /* G_SET_FPENV */
2264 513,
2265 /* G_RESET_FPENV */
2266 514,
2267 /* G_GET_FPMODE */
2268 514,
2269 /* G_SET_FPMODE */
2270 515,
2271 /* G_RESET_FPMODE */
2272 516,
2273 /* G_PTR_ADD */
2274 516,
2275 /* G_PTRMASK */
2276 519,
2277 /* G_SMIN */
2278 522,
2279 /* G_SMAX */
2280 525,
2281 /* G_UMIN */
2282 528,
2283 /* G_UMAX */
2284 531,
2285 /* G_ABS */
2286 534,
2287 /* G_LROUND */
2288 536,
2289 /* G_LLROUND */
2290 538,
2291 /* G_BR */
2292 540,
2293 /* G_BRJT */
2294 541,
2295 /* G_VSCALE */
2296 544,
2297 /* G_INSERT_SUBVECTOR */
2298 546,
2299 /* G_EXTRACT_SUBVECTOR */
2300 550,
2301 /* G_INSERT_VECTOR_ELT */
2302 553,
2303 /* G_EXTRACT_VECTOR_ELT */
2304 557,
2305 /* G_SHUFFLE_VECTOR */
2306 560,
2307 /* G_SPLAT_VECTOR */
2308 564,
2309 /* G_VECTOR_COMPRESS */
2310 566,
2311 /* G_CTTZ */
2312 570,
2313 /* G_CTTZ_ZERO_UNDEF */
2314 572,
2315 /* G_CTLZ */
2316 574,
2317 /* G_CTLZ_ZERO_UNDEF */
2318 576,
2319 /* G_CTPOP */
2320 578,
2321 /* G_BSWAP */
2322 580,
2323 /* G_BITREVERSE */
2324 582,
2325 /* G_FCEIL */
2326 584,
2327 /* G_FCOS */
2328 586,
2329 /* G_FSIN */
2330 588,
2331 /* G_FTAN */
2332 590,
2333 /* G_FACOS */
2334 592,
2335 /* G_FASIN */
2336 594,
2337 /* G_FATAN */
2338 596,
2339 /* G_FCOSH */
2340 598,
2341 /* G_FSINH */
2342 600,
2343 /* G_FTANH */
2344 602,
2345 /* G_FSQRT */
2346 604,
2347 /* G_FFLOOR */
2348 606,
2349 /* G_FRINT */
2350 608,
2351 /* G_FNEARBYINT */
2352 610,
2353 /* G_ADDRSPACE_CAST */
2354 612,
2355 /* G_BLOCK_ADDR */
2356 614,
2357 /* G_JUMP_TABLE */
2358 616,
2359 /* G_DYN_STACKALLOC */
2360 618,
2361 /* G_STACKSAVE */
2362 621,
2363 /* G_STACKRESTORE */
2364 622,
2365 /* G_STRICT_FADD */
2366 623,
2367 /* G_STRICT_FSUB */
2368 626,
2369 /* G_STRICT_FMUL */
2370 629,
2371 /* G_STRICT_FDIV */
2372 632,
2373 /* G_STRICT_FREM */
2374 635,
2375 /* G_STRICT_FMA */
2376 638,
2377 /* G_STRICT_FSQRT */
2378 642,
2379 /* G_STRICT_FLDEXP */
2380 644,
2381 /* G_READ_REGISTER */
2382 647,
2383 /* G_WRITE_REGISTER */
2384 649,
2385 /* G_MEMCPY */
2386 651,
2387 /* G_MEMCPY_INLINE */
2388 655,
2389 /* G_MEMMOVE */
2390 658,
2391 /* G_MEMSET */
2392 662,
2393 /* G_BZERO */
2394 666,
2395 /* G_TRAP */
2396 669,
2397 /* G_DEBUGTRAP */
2398 669,
2399 /* G_UBSANTRAP */
2400 669,
2401 /* G_VECREDUCE_SEQ_FADD */
2402 670,
2403 /* G_VECREDUCE_SEQ_FMUL */
2404 673,
2405 /* G_VECREDUCE_FADD */
2406 676,
2407 /* G_VECREDUCE_FMUL */
2408 678,
2409 /* G_VECREDUCE_FMAX */
2410 680,
2411 /* G_VECREDUCE_FMIN */
2412 682,
2413 /* G_VECREDUCE_FMAXIMUM */
2414 684,
2415 /* G_VECREDUCE_FMINIMUM */
2416 686,
2417 /* G_VECREDUCE_ADD */
2418 688,
2419 /* G_VECREDUCE_MUL */
2420 690,
2421 /* G_VECREDUCE_AND */
2422 692,
2423 /* G_VECREDUCE_OR */
2424 694,
2425 /* G_VECREDUCE_XOR */
2426 696,
2427 /* G_VECREDUCE_SMAX */
2428 698,
2429 /* G_VECREDUCE_SMIN */
2430 700,
2431 /* G_VECREDUCE_UMAX */
2432 702,
2433 /* G_VECREDUCE_UMIN */
2434 704,
2435 /* G_SBFX */
2436 706,
2437 /* G_UBFX */
2438 710,
2439 /* ADCWRdRr */
2440 714,
2441 /* ADDWRdRr */
2442 717,
2443 /* ADJCALLSTACKDOWN */
2444 720,
2445 /* ADJCALLSTACKUP */
2446 722,
2447 /* ANDIWRdK */
2448 724,
2449 /* ANDWRdRr */
2450 727,
2451 /* ASRBNRd */
2452 730,
2453 /* ASRWLoRd */
2454 733,
2455 /* ASRWNRd */
2456 735,
2457 /* ASRWRd */
2458 738,
2459 /* Asr16 */
2460 740,
2461 /* Asr32 */
2462 743,
2463 /* Asr8 */
2464 748,
2465 /* AtomicFence */
2466 751,
2467 /* AtomicLoad16 */
2468 751,
2469 /* AtomicLoad8 */
2470 753,
2471 /* AtomicLoadAdd16 */
2472 755,
2473 /* AtomicLoadAdd8 */
2474 758,
2475 /* AtomicLoadAnd16 */
2476 761,
2477 /* AtomicLoadAnd8 */
2478 764,
2479 /* AtomicLoadOr16 */
2480 767,
2481 /* AtomicLoadOr8 */
2482 770,
2483 /* AtomicLoadSub16 */
2484 773,
2485 /* AtomicLoadSub8 */
2486 776,
2487 /* AtomicLoadXor16 */
2488 779,
2489 /* AtomicLoadXor8 */
2490 782,
2491 /* AtomicStore16 */
2492 785,
2493 /* AtomicStore8 */
2494 787,
2495 /* COMWRd */
2496 789,
2497 /* CPCWRdRr */
2498 791,
2499 /* CPWRdRr */
2500 793,
2501 /* CopyZero */
2502 795,
2503 /* ELPMBRdZ */
2504 796,
2505 /* ELPMBRdZPi */
2506 799,
2507 /* ELPMWRdZ */
2508 802,
2509 /* ELPMWRdZPi */
2510 805,
2511 /* EORWRdRr */
2512 808,
2513 /* FRMIDX */
2514 811,
2515 /* INWRdA */
2516 814,
2517 /* LDDWRdPtrQ */
2518 816,
2519 /* LDDWRdYQ */
2520 819,
2521 /* LDIWRdK */
2522 822,
2523 /* LDSWRdK */
2524 824,
2525 /* LDWRdPtr */
2526 826,
2527 /* LDWRdPtrPd */
2528 828,
2529 /* LDWRdPtrPi */
2530 831,
2531 /* LPMBRdZ */
2532 834,
2533 /* LPMWRdZ */
2534 836,
2535 /* LPMWRdZPi */
2536 838,
2537 /* LSLBNRd */
2538 840,
2539 /* LSLWHiRd */
2540 843,
2541 /* LSLWNRd */
2542 845,
2543 /* LSLWRd */
2544 848,
2545 /* LSRBNRd */
2546 850,
2547 /* LSRWLoRd */
2548 853,
2549 /* LSRWNRd */
2550 855,
2551 /* LSRWRd */
2552 858,
2553 /* Lsl16 */
2554 860,
2555 /* Lsl32 */
2556 863,
2557 /* Lsl8 */
2558 868,
2559 /* Lsr16 */
2560 871,
2561 /* Lsr32 */
2562 874,
2563 /* Lsr8 */
2564 879,
2565 /* NEGWRd */
2566 882,
2567 /* ORIWRdK */
2568 885,
2569 /* ORWRdRr */
2570 888,
2571 /* OUTWARr */
2572 891,
2573 /* POPWRd */
2574 893,
2575 /* PUSHWRr */
2576 894,
2577 /* ROLBRdR1 */
2578 895,
2579 /* ROLBRdR17 */
2580 897,
2581 /* ROLWRd */
2582 899,
2583 /* RORBRd */
2584 901,
2585 /* RORWRd */
2586 903,
2587 /* Rol16 */
2588 905,
2589 /* Rol8 */
2590 908,
2591 /* Ror16 */
2592 911,
2593 /* Ror8 */
2594 914,
2595 /* SBCIWRdK */
2596 917,
2597 /* SBCWRdRr */
2598 920,
2599 /* SEXT */
2600 923,
2601 /* SPREAD */
2602 925,
2603 /* SPWRITE */
2604 927,
2605 /* STDSPQRr */
2606 929,
2607 /* STDWPtrQRr */
2608 932,
2609 /* STDWSPQRr */
2610 935,
2611 /* STSWKRr */
2612 938,
2613 /* STWPtrPdRr */
2614 940,
2615 /* STWPtrPiRr */
2616 944,
2617 /* STWPtrRr */
2618 948,
2619 /* SUBIWRdK */
2620 950,
2621 /* SUBWRdRr */
2622 953,
2623 /* Select16 */
2624 956,
2625 /* Select8 */
2626 960,
2627 /* ZEXT */
2628 964,
2629 /* ADCRdRr */
2630 966,
2631 /* ADDRdRr */
2632 969,
2633 /* ADIWRdK */
2634 972,
2635 /* ANDIRdK */
2636 975,
2637 /* ANDRdRr */
2638 978,
2639 /* ASRRd */
2640 981,
2641 /* BCLRs */
2642 983,
2643 /* BLD */
2644 984,
2645 /* BRBCsk */
2646 987,
2647 /* BRBSsk */
2648 989,
2649 /* BREAK */
2650 991,
2651 /* BREQk */
2652 991,
2653 /* BRGEk */
2654 992,
2655 /* BRLOk */
2656 993,
2657 /* BRLTk */
2658 994,
2659 /* BRMIk */
2660 995,
2661 /* BRNEk */
2662 996,
2663 /* BRPLk */
2664 997,
2665 /* BRSHk */
2666 998,
2667 /* BSETs */
2668 999,
2669 /* BST */
2670 1000,
2671 /* CALLk */
2672 1002,
2673 /* CBIAb */
2674 1003,
2675 /* COMRd */
2676 1005,
2677 /* CPCRdRr */
2678 1007,
2679 /* CPIRdK */
2680 1009,
2681 /* CPRdRr */
2682 1011,
2683 /* CPSE */
2684 1013,
2685 /* DECRd */
2686 1015,
2687 /* DESK */
2688 1017,
2689 /* EICALL */
2690 1018,
2691 /* EIJMP */
2692 1018,
2693 /* ELPM */
2694 1018,
2695 /* ELPMRdZ */
2696 1018,
2697 /* ELPMRdZPi */
2698 1020,
2699 /* EORRdRr */
2700 1022,
2701 /* FMUL */
2702 1025,
2703 /* FMULS */
2704 1027,
2705 /* FMULSU */
2706 1029,
2707 /* ICALL */
2708 1031,
2709 /* IJMP */
2710 1031,
2711 /* INCRd */
2712 1031,
2713 /* INRdA */
2714 1033,
2715 /* JMPk */
2716 1035,
2717 /* LACZRd */
2718 1036,
2719 /* LASZRd */
2720 1038,
2721 /* LATZRd */
2722 1040,
2723 /* LDDRdPtrQ */
2724 1042,
2725 /* LDIRdK */
2726 1045,
2727 /* LDRdPtr */
2728 1047,
2729 /* LDRdPtrPd */
2730 1049,
2731 /* LDRdPtrPi */
2732 1052,
2733 /* LDSRdK */
2734 1055,
2735 /* LDSRdKTiny */
2736 1057,
2737 /* LPM */
2738 1059,
2739 /* LPMRdZ */
2740 1059,
2741 /* LPMRdZPi */
2742 1061,
2743 /* LSRRd */
2744 1063,
2745 /* MOVRdRr */
2746 1065,
2747 /* MOVWRdRr */
2748 1067,
2749 /* MULRdRr */
2750 1069,
2751 /* MULSRdRr */
2752 1071,
2753 /* MULSURdRr */
2754 1073,
2755 /* NEGRd */
2756 1075,
2757 /* NOP */
2758 1077,
2759 /* ORIRdK */
2760 1077,
2761 /* ORRdRr */
2762 1080,
2763 /* OUTARr */
2764 1083,
2765 /* POPRd */
2766 1085,
2767 /* PUSHRr */
2768 1086,
2769 /* RCALLk */
2770 1087,
2771 /* RET */
2772 1088,
2773 /* RETI */
2774 1088,
2775 /* RJMPk */
2776 1088,
2777 /* RORRd */
2778 1089,
2779 /* SBCIRdK */
2780 1091,
2781 /* SBCRdRr */
2782 1094,
2783 /* SBIAb */
2784 1097,
2785 /* SBICAb */
2786 1099,
2787 /* SBISAb */
2788 1101,
2789 /* SBIWRdK */
2790 1103,
2791 /* SBRCRrB */
2792 1106,
2793 /* SBRSRrB */
2794 1108,
2795 /* SLEEP */
2796 1110,
2797 /* SPM */
2798 1110,
2799 /* SPMZPi */
2800 1110,
2801 /* STDPtrQRr */
2802 1111,
2803 /* STPtrPdRr */
2804 1114,
2805 /* STPtrPiRr */
2806 1118,
2807 /* STPtrRr */
2808 1122,
2809 /* STSKRr */
2810 1124,
2811 /* STSKRrTiny */
2812 1126,
2813 /* SUBIRdK */
2814 1128,
2815 /* SUBRdRr */
2816 1131,
2817 /* SWAPRd */
2818 1134,
2819 /* WDR */
2820 1136,
2821 /* XCHZRd */
2822 1136,
2823 };
2824
2825 using namespace OpTypes;
2826 static const int8_t OpcodeOperandTypes[] = {
2827
2828 /* PHI */
2829 -1,
2830 /* INLINEASM */
2831 /* INLINEASM_BR */
2832 /* CFI_INSTRUCTION */
2833 i32imm,
2834 /* EH_LABEL */
2835 i32imm,
2836 /* GC_LABEL */
2837 i32imm,
2838 /* ANNOTATION_LABEL */
2839 i32imm,
2840 /* KILL */
2841 /* EXTRACT_SUBREG */
2842 -1, -1, i32imm,
2843 /* INSERT_SUBREG */
2844 -1, -1, -1, i32imm,
2845 /* IMPLICIT_DEF */
2846 -1,
2847 /* SUBREG_TO_REG */
2848 -1, -1, -1, i32imm,
2849 /* COPY_TO_REGCLASS */
2850 -1, -1, i32imm,
2851 /* DBG_VALUE */
2852 /* DBG_VALUE_LIST */
2853 /* DBG_INSTR_REF */
2854 /* DBG_PHI */
2855 /* DBG_LABEL */
2856 -1,
2857 /* REG_SEQUENCE */
2858 -1, -1,
2859 /* COPY */
2860 -1, -1,
2861 /* BUNDLE */
2862 /* LIFETIME_START */
2863 i32imm,
2864 /* LIFETIME_END */
2865 i32imm,
2866 /* PSEUDO_PROBE */
2867 i64imm, i64imm, i8imm, i32imm,
2868 /* ARITH_FENCE */
2869 -1, -1,
2870 /* STACKMAP */
2871 i64imm, i32imm,
2872 /* FENTRY_CALL */
2873 /* PATCHPOINT */
2874 -1, i64imm, i32imm, -1, i32imm, i32imm,
2875 /* LOAD_STACK_GUARD */
2876 -1,
2877 /* PREALLOCATED_SETUP */
2878 i32imm,
2879 /* PREALLOCATED_ARG */
2880 -1, i32imm, i32imm,
2881 /* STATEPOINT */
2882 /* LOCAL_ESCAPE */
2883 -1, i32imm,
2884 /* FAULTING_OP */
2885 -1,
2886 /* PATCHABLE_OP */
2887 /* PATCHABLE_FUNCTION_ENTER */
2888 /* PATCHABLE_RET */
2889 /* PATCHABLE_FUNCTION_EXIT */
2890 /* PATCHABLE_TAIL_CALL */
2891 /* PATCHABLE_EVENT_CALL */
2892 -1, -1,
2893 /* PATCHABLE_TYPED_EVENT_CALL */
2894 -1, -1, -1,
2895 /* ICALL_BRANCH_FUNNEL */
2896 /* MEMBARRIER */
2897 /* JUMP_TABLE_DEBUG_INFO */
2898 i64imm,
2899 /* CONVERGENCECTRL_ENTRY */
2900 -1,
2901 /* CONVERGENCECTRL_ANCHOR */
2902 -1,
2903 /* CONVERGENCECTRL_LOOP */
2904 -1, -1,
2905 /* CONVERGENCECTRL_GLUE */
2906 -1,
2907 /* G_ASSERT_SEXT */
2908 type0, type0, untyped_imm_0,
2909 /* G_ASSERT_ZEXT */
2910 type0, type0, untyped_imm_0,
2911 /* G_ASSERT_ALIGN */
2912 type0, type0, untyped_imm_0,
2913 /* G_ADD */
2914 type0, type0, type0,
2915 /* G_SUB */
2916 type0, type0, type0,
2917 /* G_MUL */
2918 type0, type0, type0,
2919 /* G_SDIV */
2920 type0, type0, type0,
2921 /* G_UDIV */
2922 type0, type0, type0,
2923 /* G_SREM */
2924 type0, type0, type0,
2925 /* G_UREM */
2926 type0, type0, type0,
2927 /* G_SDIVREM */
2928 type0, type0, type0, type0,
2929 /* G_UDIVREM */
2930 type0, type0, type0, type0,
2931 /* G_AND */
2932 type0, type0, type0,
2933 /* G_OR */
2934 type0, type0, type0,
2935 /* G_XOR */
2936 type0, type0, type0,
2937 /* G_IMPLICIT_DEF */
2938 type0,
2939 /* G_PHI */
2940 type0,
2941 /* G_FRAME_INDEX */
2942 type0, -1,
2943 /* G_GLOBAL_VALUE */
2944 type0, -1,
2945 /* G_PTRAUTH_GLOBAL_VALUE */
2946 type0, -1, i32imm, type1, i64imm,
2947 /* G_CONSTANT_POOL */
2948 type0, -1,
2949 /* G_EXTRACT */
2950 type0, type1, untyped_imm_0,
2951 /* G_UNMERGE_VALUES */
2952 type0, type1,
2953 /* G_INSERT */
2954 type0, type0, type1, untyped_imm_0,
2955 /* G_MERGE_VALUES */
2956 type0, type1,
2957 /* G_BUILD_VECTOR */
2958 type0, type1,
2959 /* G_BUILD_VECTOR_TRUNC */
2960 type0, type1,
2961 /* G_CONCAT_VECTORS */
2962 type0, type1,
2963 /* G_PTRTOINT */
2964 type0, type1,
2965 /* G_INTTOPTR */
2966 type0, type1,
2967 /* G_BITCAST */
2968 type0, type1,
2969 /* G_FREEZE */
2970 type0, type0,
2971 /* G_CONSTANT_FOLD_BARRIER */
2972 type0, type0,
2973 /* G_INTRINSIC_FPTRUNC_ROUND */
2974 type0, type1, i32imm,
2975 /* G_INTRINSIC_TRUNC */
2976 type0, type0,
2977 /* G_INTRINSIC_ROUND */
2978 type0, type0,
2979 /* G_INTRINSIC_LRINT */
2980 type0, type1,
2981 /* G_INTRINSIC_LLRINT */
2982 type0, type1,
2983 /* G_INTRINSIC_ROUNDEVEN */
2984 type0, type0,
2985 /* G_READCYCLECOUNTER */
2986 type0,
2987 /* G_READSTEADYCOUNTER */
2988 type0,
2989 /* G_LOAD */
2990 type0, ptype1,
2991 /* G_SEXTLOAD */
2992 type0, ptype1,
2993 /* G_ZEXTLOAD */
2994 type0, ptype1,
2995 /* G_INDEXED_LOAD */
2996 type0, ptype1, ptype1, type2, -1,
2997 /* G_INDEXED_SEXTLOAD */
2998 type0, ptype1, ptype1, type2, -1,
2999 /* G_INDEXED_ZEXTLOAD */
3000 type0, ptype1, ptype1, type2, -1,
3001 /* G_STORE */
3002 type0, ptype1,
3003 /* G_INDEXED_STORE */
3004 ptype0, type1, ptype0, ptype2, -1,
3005 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
3006 type0, type1, type2, type0, type0,
3007 /* G_ATOMIC_CMPXCHG */
3008 type0, ptype1, type0, type0,
3009 /* G_ATOMICRMW_XCHG */
3010 type0, ptype1, type0,
3011 /* G_ATOMICRMW_ADD */
3012 type0, ptype1, type0,
3013 /* G_ATOMICRMW_SUB */
3014 type0, ptype1, type0,
3015 /* G_ATOMICRMW_AND */
3016 type0, ptype1, type0,
3017 /* G_ATOMICRMW_NAND */
3018 type0, ptype1, type0,
3019 /* G_ATOMICRMW_OR */
3020 type0, ptype1, type0,
3021 /* G_ATOMICRMW_XOR */
3022 type0, ptype1, type0,
3023 /* G_ATOMICRMW_MAX */
3024 type0, ptype1, type0,
3025 /* G_ATOMICRMW_MIN */
3026 type0, ptype1, type0,
3027 /* G_ATOMICRMW_UMAX */
3028 type0, ptype1, type0,
3029 /* G_ATOMICRMW_UMIN */
3030 type0, ptype1, type0,
3031 /* G_ATOMICRMW_FADD */
3032 type0, ptype1, type0,
3033 /* G_ATOMICRMW_FSUB */
3034 type0, ptype1, type0,
3035 /* G_ATOMICRMW_FMAX */
3036 type0, ptype1, type0,
3037 /* G_ATOMICRMW_FMIN */
3038 type0, ptype1, type0,
3039 /* G_ATOMICRMW_UINC_WRAP */
3040 type0, ptype1, type0,
3041 /* G_ATOMICRMW_UDEC_WRAP */
3042 type0, ptype1, type0,
3043 /* G_FENCE */
3044 i32imm, i32imm,
3045 /* G_PREFETCH */
3046 ptype0, i32imm, i32imm, i32imm,
3047 /* G_BRCOND */
3048 type0, -1,
3049 /* G_BRINDIRECT */
3050 type0,
3051 /* G_INVOKE_REGION_START */
3052 /* G_INTRINSIC */
3053 -1,
3054 /* G_INTRINSIC_W_SIDE_EFFECTS */
3055 -1,
3056 /* G_INTRINSIC_CONVERGENT */
3057 -1,
3058 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
3059 -1,
3060 /* G_ANYEXT */
3061 type0, type1,
3062 /* G_TRUNC */
3063 type0, type1,
3064 /* G_CONSTANT */
3065 type0, -1,
3066 /* G_FCONSTANT */
3067 type0, -1,
3068 /* G_VASTART */
3069 type0,
3070 /* G_VAARG */
3071 type0, type1, -1,
3072 /* G_SEXT */
3073 type0, type1,
3074 /* G_SEXT_INREG */
3075 type0, type0, untyped_imm_0,
3076 /* G_ZEXT */
3077 type0, type1,
3078 /* G_SHL */
3079 type0, type0, type1,
3080 /* G_LSHR */
3081 type0, type0, type1,
3082 /* G_ASHR */
3083 type0, type0, type1,
3084 /* G_FSHL */
3085 type0, type0, type0, type1,
3086 /* G_FSHR */
3087 type0, type0, type0, type1,
3088 /* G_ROTR */
3089 type0, type0, type1,
3090 /* G_ROTL */
3091 type0, type0, type1,
3092 /* G_ICMP */
3093 type0, -1, type1, type1,
3094 /* G_FCMP */
3095 type0, -1, type1, type1,
3096 /* G_SCMP */
3097 type0, type1, type1,
3098 /* G_UCMP */
3099 type0, type1, type1,
3100 /* G_SELECT */
3101 type0, type1, type0, type0,
3102 /* G_UADDO */
3103 type0, type1, type0, type0,
3104 /* G_UADDE */
3105 type0, type1, type0, type0, type1,
3106 /* G_USUBO */
3107 type0, type1, type0, type0,
3108 /* G_USUBE */
3109 type0, type1, type0, type0, type1,
3110 /* G_SADDO */
3111 type0, type1, type0, type0,
3112 /* G_SADDE */
3113 type0, type1, type0, type0, type1,
3114 /* G_SSUBO */
3115 type0, type1, type0, type0,
3116 /* G_SSUBE */
3117 type0, type1, type0, type0, type1,
3118 /* G_UMULO */
3119 type0, type1, type0, type0,
3120 /* G_SMULO */
3121 type0, type1, type0, type0,
3122 /* G_UMULH */
3123 type0, type0, type0,
3124 /* G_SMULH */
3125 type0, type0, type0,
3126 /* G_UADDSAT */
3127 type0, type0, type0,
3128 /* G_SADDSAT */
3129 type0, type0, type0,
3130 /* G_USUBSAT */
3131 type0, type0, type0,
3132 /* G_SSUBSAT */
3133 type0, type0, type0,
3134 /* G_USHLSAT */
3135 type0, type0, type1,
3136 /* G_SSHLSAT */
3137 type0, type0, type1,
3138 /* G_SMULFIX */
3139 type0, type0, type0, untyped_imm_0,
3140 /* G_UMULFIX */
3141 type0, type0, type0, untyped_imm_0,
3142 /* G_SMULFIXSAT */
3143 type0, type0, type0, untyped_imm_0,
3144 /* G_UMULFIXSAT */
3145 type0, type0, type0, untyped_imm_0,
3146 /* G_SDIVFIX */
3147 type0, type0, type0, untyped_imm_0,
3148 /* G_UDIVFIX */
3149 type0, type0, type0, untyped_imm_0,
3150 /* G_SDIVFIXSAT */
3151 type0, type0, type0, untyped_imm_0,
3152 /* G_UDIVFIXSAT */
3153 type0, type0, type0, untyped_imm_0,
3154 /* G_FADD */
3155 type0, type0, type0,
3156 /* G_FSUB */
3157 type0, type0, type0,
3158 /* G_FMUL */
3159 type0, type0, type0,
3160 /* G_FMA */
3161 type0, type0, type0, type0,
3162 /* G_FMAD */
3163 type0, type0, type0, type0,
3164 /* G_FDIV */
3165 type0, type0, type0,
3166 /* G_FREM */
3167 type0, type0, type0,
3168 /* G_FPOW */
3169 type0, type0, type0,
3170 /* G_FPOWI */
3171 type0, type0, type1,
3172 /* G_FEXP */
3173 type0, type0,
3174 /* G_FEXP2 */
3175 type0, type0,
3176 /* G_FEXP10 */
3177 type0, type0,
3178 /* G_FLOG */
3179 type0, type0,
3180 /* G_FLOG2 */
3181 type0, type0,
3182 /* G_FLOG10 */
3183 type0, type0,
3184 /* G_FLDEXP */
3185 type0, type0, type1,
3186 /* G_FFREXP */
3187 type0, type1, type0,
3188 /* G_FNEG */
3189 type0, type0,
3190 /* G_FPEXT */
3191 type0, type1,
3192 /* G_FPTRUNC */
3193 type0, type1,
3194 /* G_FPTOSI */
3195 type0, type1,
3196 /* G_FPTOUI */
3197 type0, type1,
3198 /* G_SITOFP */
3199 type0, type1,
3200 /* G_UITOFP */
3201 type0, type1,
3202 /* G_FABS */
3203 type0, type0,
3204 /* G_FCOPYSIGN */
3205 type0, type0, type1,
3206 /* G_IS_FPCLASS */
3207 type0, type1, -1,
3208 /* G_FCANONICALIZE */
3209 type0, type0,
3210 /* G_FMINNUM */
3211 type0, type0, type0,
3212 /* G_FMAXNUM */
3213 type0, type0, type0,
3214 /* G_FMINNUM_IEEE */
3215 type0, type0, type0,
3216 /* G_FMAXNUM_IEEE */
3217 type0, type0, type0,
3218 /* G_FMINIMUM */
3219 type0, type0, type0,
3220 /* G_FMAXIMUM */
3221 type0, type0, type0,
3222 /* G_GET_FPENV */
3223 type0,
3224 /* G_SET_FPENV */
3225 type0,
3226 /* G_RESET_FPENV */
3227 /* G_GET_FPMODE */
3228 type0,
3229 /* G_SET_FPMODE */
3230 type0,
3231 /* G_RESET_FPMODE */
3232 /* G_PTR_ADD */
3233 ptype0, ptype0, type1,
3234 /* G_PTRMASK */
3235 ptype0, ptype0, type1,
3236 /* G_SMIN */
3237 type0, type0, type0,
3238 /* G_SMAX */
3239 type0, type0, type0,
3240 /* G_UMIN */
3241 type0, type0, type0,
3242 /* G_UMAX */
3243 type0, type0, type0,
3244 /* G_ABS */
3245 type0, type0,
3246 /* G_LROUND */
3247 type0, type1,
3248 /* G_LLROUND */
3249 type0, type1,
3250 /* G_BR */
3251 -1,
3252 /* G_BRJT */
3253 ptype0, -1, type1,
3254 /* G_VSCALE */
3255 type0, -1,
3256 /* G_INSERT_SUBVECTOR */
3257 type0, type0, type1, untyped_imm_0,
3258 /* G_EXTRACT_SUBVECTOR */
3259 type0, type0, untyped_imm_0,
3260 /* G_INSERT_VECTOR_ELT */
3261 type0, type0, type1, type2,
3262 /* G_EXTRACT_VECTOR_ELT */
3263 type0, type1, type2,
3264 /* G_SHUFFLE_VECTOR */
3265 type0, type1, type1, -1,
3266 /* G_SPLAT_VECTOR */
3267 type0, type1,
3268 /* G_VECTOR_COMPRESS */
3269 type0, type0, type1, type0,
3270 /* G_CTTZ */
3271 type0, type1,
3272 /* G_CTTZ_ZERO_UNDEF */
3273 type0, type1,
3274 /* G_CTLZ */
3275 type0, type1,
3276 /* G_CTLZ_ZERO_UNDEF */
3277 type0, type1,
3278 /* G_CTPOP */
3279 type0, type1,
3280 /* G_BSWAP */
3281 type0, type0,
3282 /* G_BITREVERSE */
3283 type0, type0,
3284 /* G_FCEIL */
3285 type0, type0,
3286 /* G_FCOS */
3287 type0, type0,
3288 /* G_FSIN */
3289 type0, type0,
3290 /* G_FTAN */
3291 type0, type0,
3292 /* G_FACOS */
3293 type0, type0,
3294 /* G_FASIN */
3295 type0, type0,
3296 /* G_FATAN */
3297 type0, type0,
3298 /* G_FCOSH */
3299 type0, type0,
3300 /* G_FSINH */
3301 type0, type0,
3302 /* G_FTANH */
3303 type0, type0,
3304 /* G_FSQRT */
3305 type0, type0,
3306 /* G_FFLOOR */
3307 type0, type0,
3308 /* G_FRINT */
3309 type0, type0,
3310 /* G_FNEARBYINT */
3311 type0, type0,
3312 /* G_ADDRSPACE_CAST */
3313 type0, type1,
3314 /* G_BLOCK_ADDR */
3315 type0, -1,
3316 /* G_JUMP_TABLE */
3317 type0, -1,
3318 /* G_DYN_STACKALLOC */
3319 ptype0, type1, i32imm,
3320 /* G_STACKSAVE */
3321 ptype0,
3322 /* G_STACKRESTORE */
3323 ptype0,
3324 /* G_STRICT_FADD */
3325 type0, type0, type0,
3326 /* G_STRICT_FSUB */
3327 type0, type0, type0,
3328 /* G_STRICT_FMUL */
3329 type0, type0, type0,
3330 /* G_STRICT_FDIV */
3331 type0, type0, type0,
3332 /* G_STRICT_FREM */
3333 type0, type0, type0,
3334 /* G_STRICT_FMA */
3335 type0, type0, type0, type0,
3336 /* G_STRICT_FSQRT */
3337 type0, type0,
3338 /* G_STRICT_FLDEXP */
3339 type0, type0, type1,
3340 /* G_READ_REGISTER */
3341 type0, -1,
3342 /* G_WRITE_REGISTER */
3343 -1, type0,
3344 /* G_MEMCPY */
3345 ptype0, ptype1, type2, untyped_imm_0,
3346 /* G_MEMCPY_INLINE */
3347 ptype0, ptype1, type2,
3348 /* G_MEMMOVE */
3349 ptype0, ptype1, type2, untyped_imm_0,
3350 /* G_MEMSET */
3351 ptype0, type1, type2, untyped_imm_0,
3352 /* G_BZERO */
3353 ptype0, type1, untyped_imm_0,
3354 /* G_TRAP */
3355 /* G_DEBUGTRAP */
3356 /* G_UBSANTRAP */
3357 i8imm,
3358 /* G_VECREDUCE_SEQ_FADD */
3359 type0, type1, type2,
3360 /* G_VECREDUCE_SEQ_FMUL */
3361 type0, type1, type2,
3362 /* G_VECREDUCE_FADD */
3363 type0, type1,
3364 /* G_VECREDUCE_FMUL */
3365 type0, type1,
3366 /* G_VECREDUCE_FMAX */
3367 type0, type1,
3368 /* G_VECREDUCE_FMIN */
3369 type0, type1,
3370 /* G_VECREDUCE_FMAXIMUM */
3371 type0, type1,
3372 /* G_VECREDUCE_FMINIMUM */
3373 type0, type1,
3374 /* G_VECREDUCE_ADD */
3375 type0, type1,
3376 /* G_VECREDUCE_MUL */
3377 type0, type1,
3378 /* G_VECREDUCE_AND */
3379 type0, type1,
3380 /* G_VECREDUCE_OR */
3381 type0, type1,
3382 /* G_VECREDUCE_XOR */
3383 type0, type1,
3384 /* G_VECREDUCE_SMAX */
3385 type0, type1,
3386 /* G_VECREDUCE_SMIN */
3387 type0, type1,
3388 /* G_VECREDUCE_UMAX */
3389 type0, type1,
3390 /* G_VECREDUCE_UMIN */
3391 type0, type1,
3392 /* G_SBFX */
3393 type0, type0, type1, type1,
3394 /* G_UBFX */
3395 type0, type0, type1, type1,
3396 /* ADCWRdRr */
3397 DREGS, DREGS, DREGS,
3398 /* ADDWRdRr */
3399 DREGS, DREGS, DREGS,
3400 /* ADJCALLSTACKDOWN */
3401 i16imm, i16imm,
3402 /* ADJCALLSTACKUP */
3403 i16imm, i16imm,
3404 /* ANDIWRdK */
3405 DLDREGS, DLDREGS, i16imm,
3406 /* ANDWRdRr */
3407 DREGS, DREGS, DREGS,
3408 /* ASRBNRd */
3409 LD8, GPR8, imm_ldi8,
3410 /* ASRWLoRd */
3411 DREGS, DREGS,
3412 /* ASRWNRd */
3413 DREGS, DREGS, imm16,
3414 /* ASRWRd */
3415 DREGS, DREGS,
3416 /* Asr16 */
3417 DREGS, DREGS, GPR8,
3418 /* Asr32 */
3419 DREGS, DREGS, DREGS, DREGS, i8imm,
3420 /* Asr8 */
3421 GPR8, GPR8, GPR8,
3422 /* AtomicFence */
3423 /* AtomicLoad16 */
3424 DREGS, PTRDISPREGS,
3425 /* AtomicLoad8 */
3426 GPR8, PTRREGS,
3427 /* AtomicLoadAdd16 */
3428 DREGS, PTRDISPREGS, DREGS,
3429 /* AtomicLoadAdd8 */
3430 GPR8, PTRREGS, GPR8,
3431 /* AtomicLoadAnd16 */
3432 DREGS, PTRDISPREGS, DREGS,
3433 /* AtomicLoadAnd8 */
3434 GPR8, PTRREGS, GPR8,
3435 /* AtomicLoadOr16 */
3436 DREGS, PTRDISPREGS, DREGS,
3437 /* AtomicLoadOr8 */
3438 GPR8, PTRREGS, GPR8,
3439 /* AtomicLoadSub16 */
3440 DREGS, PTRDISPREGS, DREGS,
3441 /* AtomicLoadSub8 */
3442 GPR8, PTRREGS, GPR8,
3443 /* AtomicLoadXor16 */
3444 DREGS, PTRDISPREGS, DREGS,
3445 /* AtomicLoadXor8 */
3446 GPR8, PTRREGS, GPR8,
3447 /* AtomicStore16 */
3448 PTRDISPREGS, DREGS,
3449 /* AtomicStore8 */
3450 PTRREGS, GPR8,
3451 /* COMWRd */
3452 DREGS, DREGS,
3453 /* CPCWRdRr */
3454 DREGS, DREGS,
3455 /* CPWRdRr */
3456 DREGS, DREGS,
3457 /* CopyZero */
3458 GPR8,
3459 /* ELPMBRdZ */
3460 GPR8, ZREG, LD8,
3461 /* ELPMBRdZPi */
3462 GPR8, ZREG, LD8,
3463 /* ELPMWRdZ */
3464 DREGS, ZREG, LD8,
3465 /* ELPMWRdZPi */
3466 DREGS, ZREG, LD8,
3467 /* EORWRdRr */
3468 DREGS, DREGS, DREGS,
3469 /* FRMIDX */
3470 DLDREGS, DLDREGS, i16imm,
3471 /* INWRdA */
3472 DREGS, imm_port6,
3473 /* LDDWRdPtrQ */
3474 DREGS, PTRDISPREGS, i16imm,
3475 /* LDDWRdYQ */
3476 DREGS, PTRDISPREGS, i16imm,
3477 /* LDIWRdK */
3478 DLDREGS, i16imm,
3479 /* LDSWRdK */
3480 DREGS, i16imm,
3481 /* LDWRdPtr */
3482 DREGS, PTRDISPREGS,
3483 /* LDWRdPtrPd */
3484 DREGS, PTRREGS, PTRREGS,
3485 /* LDWRdPtrPi */
3486 DREGS, PTRREGS, PTRREGS,
3487 /* LPMBRdZ */
3488 GPR8, ZREG,
3489 /* LPMWRdZ */
3490 DREGS, ZREG,
3491 /* LPMWRdZPi */
3492 DREGS, ZREG,
3493 /* LSLBNRd */
3494 LD8, GPR8, imm_ldi8,
3495 /* LSLWHiRd */
3496 DREGS, DREGS,
3497 /* LSLWNRd */
3498 DLDREGS, DREGS, imm16,
3499 /* LSLWRd */
3500 DREGS, DREGS,
3501 /* LSRBNRd */
3502 LD8, GPR8, imm_ldi8,
3503 /* LSRWLoRd */
3504 DREGS, DREGS,
3505 /* LSRWNRd */
3506 DLDREGS, DREGS, imm16,
3507 /* LSRWRd */
3508 DREGS, DREGS,
3509 /* Lsl16 */
3510 DREGS, DREGS, GPR8,
3511 /* Lsl32 */
3512 DREGS, DREGS, DREGS, DREGS, i8imm,
3513 /* Lsl8 */
3514 GPR8, GPR8, GPR8,
3515 /* Lsr16 */
3516 DREGS, DREGS, GPR8,
3517 /* Lsr32 */
3518 DREGS, DREGS, DREGS, DREGS, i8imm,
3519 /* Lsr8 */
3520 GPR8, GPR8, GPR8,
3521 /* NEGWRd */
3522 DREGS, DREGS, GPR8,
3523 /* ORIWRdK */
3524 DLDREGS, DLDREGS, i16imm,
3525 /* ORWRdRr */
3526 DREGS, DREGS, DREGS,
3527 /* OUTWARr */
3528 imm_port6, DREGS,
3529 /* POPWRd */
3530 DREGS,
3531 /* PUSHWRr */
3532 DREGS,
3533 /* ROLBRdR1 */
3534 GPR8, GPR8,
3535 /* ROLBRdR17 */
3536 GPR8, GPR8,
3537 /* ROLWRd */
3538 DREGS, DREGS,
3539 /* RORBRd */
3540 GPR8, GPR8,
3541 /* RORWRd */
3542 DREGS, DREGS,
3543 /* Rol16 */
3544 DREGS, DREGS, GPR8,
3545 /* Rol8 */
3546 GPR8, GPR8, GPR8,
3547 /* Ror16 */
3548 DREGS, DREGS, GPR8,
3549 /* Ror8 */
3550 GPR8, GPR8, GPR8,
3551 /* SBCIWRdK */
3552 DLDREGS, DLDREGS, i16imm,
3553 /* SBCWRdRr */
3554 DREGS, DREGS, DREGS,
3555 /* SEXT */
3556 DREGS, GPR8,
3557 /* SPREAD */
3558 DREGS, GPRSP,
3559 /* SPWRITE */
3560 GPRSP, DREGS,
3561 /* STDSPQRr */
3562 GPRSP, i16imm, GPR8,
3563 /* STDWPtrQRr */
3564 PTRDISPREGS, i16imm, DREGS,
3565 /* STDWSPQRr */
3566 GPRSP, i16imm, DREGS,
3567 /* STSWKRr */
3568 i16imm, DREGS,
3569 /* STWPtrPdRr */
3570 PTRREGS, PTRREGS, DREGS, i8imm,
3571 /* STWPtrPiRr */
3572 PTRREGS, PTRREGS, DREGS, i8imm,
3573 /* STWPtrRr */
3574 PTRDISPREGS, DREGS,
3575 /* SUBIWRdK */
3576 DLDREGS, DLDREGS, i16imm,
3577 /* SUBWRdRr */
3578 DREGS, DREGS, DREGS,
3579 /* Select16 */
3580 DREGS, DREGS, DREGS, i8imm,
3581 /* Select8 */
3582 GPR8, GPR8, GPR8, i8imm,
3583 /* ZEXT */
3584 DREGS, GPR8,
3585 /* ADCRdRr */
3586 GPR8, GPR8, GPR8,
3587 /* ADDRdRr */
3588 GPR8, GPR8, GPR8,
3589 /* ADIWRdK */
3590 IWREGS, IWREGS, imm_arith6,
3591 /* ANDIRdK */
3592 LD8, LD8, imm_ldi8,
3593 /* ANDRdRr */
3594 GPR8, GPR8, GPR8,
3595 /* ASRRd */
3596 GPR8, GPR8,
3597 /* BCLRs */
3598 i8imm,
3599 /* BLD */
3600 GPR8, GPR8, i8imm,
3601 /* BRBCsk */
3602 i8imm, relbrtarget_7,
3603 /* BRBSsk */
3604 i8imm, relbrtarget_7,
3605 /* BREAK */
3606 /* BREQk */
3607 relbrtarget_7,
3608 /* BRGEk */
3609 relbrtarget_7,
3610 /* BRLOk */
3611 relbrtarget_7,
3612 /* BRLTk */
3613 relbrtarget_7,
3614 /* BRMIk */
3615 relbrtarget_7,
3616 /* BRNEk */
3617 relbrtarget_7,
3618 /* BRPLk */
3619 relbrtarget_7,
3620 /* BRSHk */
3621 relbrtarget_7,
3622 /* BSETs */
3623 i8imm,
3624 /* BST */
3625 GPR8, i8imm,
3626 /* CALLk */
3627 call_target,
3628 /* CBIAb */
3629 imm_port5, i8imm,
3630 /* COMRd */
3631 GPR8, GPR8,
3632 /* CPCRdRr */
3633 GPR8, GPR8,
3634 /* CPIRdK */
3635 LD8, imm_ldi8,
3636 /* CPRdRr */
3637 GPR8, GPR8,
3638 /* CPSE */
3639 GPR8, GPR8,
3640 /* DECRd */
3641 GPR8, GPR8,
3642 /* DESK */
3643 i8imm,
3644 /* EICALL */
3645 /* EIJMP */
3646 /* ELPM */
3647 /* ELPMRdZ */
3648 GPR8, ZREG,
3649 /* ELPMRdZPi */
3650 GPR8, ZREG,
3651 /* EORRdRr */
3652 GPR8, GPR8, GPR8,
3653 /* FMUL */
3654 LD8lo, LD8lo,
3655 /* FMULS */
3656 LD8lo, LD8lo,
3657 /* FMULSU */
3658 LD8lo, LD8lo,
3659 /* ICALL */
3660 /* IJMP */
3661 /* INCRd */
3662 GPR8, GPR8,
3663 /* INRdA */
3664 GPR8, imm_port6,
3665 /* JMPk */
3666 call_target,
3667 /* LACZRd */
3668 GPR8, ZREG,
3669 /* LASZRd */
3670 GPR8, ZREG,
3671 /* LATZRd */
3672 GPR8, ZREG,
3673 /* LDDRdPtrQ */
3674 GPR8, PTRDISPREGS, i16imm,
3675 /* LDIRdK */
3676 LD8, imm_ldi8,
3677 /* LDRdPtr */
3678 GPR8, PTRREGS,
3679 /* LDRdPtrPd */
3680 GPR8, PTRREGS, PTRREGS,
3681 /* LDRdPtrPi */
3682 GPR8, PTRREGS, PTRREGS,
3683 /* LDSRdK */
3684 GPR8, imm16,
3685 /* LDSRdKTiny */
3686 LD8, imm7tiny,
3687 /* LPM */
3688 /* LPMRdZ */
3689 GPR8, ZREG,
3690 /* LPMRdZPi */
3691 GPR8, ZREG,
3692 /* LSRRd */
3693 GPR8, GPR8,
3694 /* MOVRdRr */
3695 GPR8, GPR8,
3696 /* MOVWRdRr */
3697 DREGS, DREGS,
3698 /* MULRdRr */
3699 GPR8, GPR8,
3700 /* MULSRdRr */
3701 LD8, LD8,
3702 /* MULSURdRr */
3703 LD8lo, LD8lo,
3704 /* NEGRd */
3705 GPR8, GPR8,
3706 /* NOP */
3707 /* ORIRdK */
3708 LD8, LD8, imm_ldi8,
3709 /* ORRdRr */
3710 GPR8, GPR8, GPR8,
3711 /* OUTARr */
3712 imm_port6, GPR8,
3713 /* POPRd */
3714 GPR8,
3715 /* PUSHRr */
3716 GPR8,
3717 /* RCALLk */
3718 rcalltarget_13,
3719 /* RET */
3720 /* RETI */
3721 /* RJMPk */
3722 brtarget_13,
3723 /* RORRd */
3724 GPR8, GPR8,
3725 /* SBCIRdK */
3726 LD8, LD8, imm_ldi8,
3727 /* SBCRdRr */
3728 GPR8, GPR8, GPR8,
3729 /* SBIAb */
3730 imm_port5, i8imm,
3731 /* SBICAb */
3732 imm_port5, i8imm,
3733 /* SBISAb */
3734 imm_port5, i8imm,
3735 /* SBIWRdK */
3736 IWREGS, IWREGS, imm_arith6,
3737 /* SBRCRrB */
3738 GPR8, i8imm,
3739 /* SBRSRrB */
3740 GPR8, i8imm,
3741 /* SLEEP */
3742 /* SPM */
3743 /* SPMZPi */
3744 ZREG,
3745 /* STDPtrQRr */
3746 PTRDISPREGS, i16imm, GPR8,
3747 /* STPtrPdRr */
3748 PTRREGS, PTRREGS, GPR8, i8imm,
3749 /* STPtrPiRr */
3750 PTRREGS, PTRREGS, GPR8, i8imm,
3751 /* STPtrRr */
3752 PTRREGS, GPR8,
3753 /* STSKRr */
3754 imm16, GPR8,
3755 /* STSKRrTiny */
3756 imm7tiny, LD8,
3757 /* SUBIRdK */
3758 LD8, LD8, imm_ldi8,
3759 /* SUBRdRr */
3760 GPR8, GPR8, GPR8,
3761 /* SWAPRd */
3762 GPR8, GPR8,
3763 /* WDR */
3764 /* XCHZRd */
3765 GPR8, ZREG,
3766 };
3767 return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
3768}
3769} // end namespace AVR
3770} // end namespace llvm
3771#endif // GET_INSTRINFO_OPERAND_TYPE
3772
3773#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
3774#undef GET_INSTRINFO_MEM_OPERAND_SIZE
3775namespace llvm {
3776namespace AVR {
3777LLVM_READONLY
3778static int getMemOperandSize(int OpType) {
3779 switch (OpType) {
3780 default: return 0;
3781 }
3782}
3783} // end namespace AVR
3784} // end namespace llvm
3785#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
3786
3787#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3788#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3789namespace llvm {
3790namespace AVR {
3791LLVM_READONLY static unsigned
3792getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
3793 return LogicalOpIdx;
3794}
3795LLVM_READONLY static inline unsigned
3796getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
3797 auto S = 0U;
3798 for (auto i = 0U; i < LogicalOpIdx; ++i)
3799 S += getLogicalOperandSize(Opcode, i);
3800 return S;
3801}
3802} // end namespace AVR
3803} // end namespace llvm
3804#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3805
3806#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3807#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3808namespace llvm {
3809namespace AVR {
3810LLVM_READONLY static int
3811getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
3812 return -1;
3813}
3814} // end namespace AVR
3815} // end namespace llvm
3816#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3817
3818#ifdef GET_INSTRINFO_MC_HELPER_DECLS
3819#undef GET_INSTRINFO_MC_HELPER_DECLS
3820
3821namespace llvm {
3822class MCInst;
3823class FeatureBitset;
3824
3825namespace AVR_MC {
3826
3827void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
3828
3829} // end namespace AVR_MC
3830} // end namespace llvm
3831
3832#endif // GET_INSTRINFO_MC_HELPER_DECLS
3833
3834#ifdef GET_INSTRINFO_MC_HELPERS
3835#undef GET_INSTRINFO_MC_HELPERS
3836
3837namespace llvm {
3838namespace AVR_MC {
3839
3840} // end namespace AVR_MC
3841} // end namespace llvm
3842
3843#endif // GET_GENISTRINFO_MC_HELPERS
3844
3845#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
3846 defined(GET_AVAILABLE_OPCODE_CHECKER)
3847#define GET_COMPUTE_FEATURES
3848#endif
3849#ifdef GET_COMPUTE_FEATURES
3850#undef GET_COMPUTE_FEATURES
3851namespace llvm {
3852namespace AVR_MC {
3853
3854// Bits for subtarget features that participate in instruction matching.
3855enum SubtargetFeatureBits : uint8_t {
3856 Feature_HasSRAMBit = 14,
3857 Feature_HasJMPCALLBit = 7,
3858 Feature_HasIJMPCALLBit = 6,
3859 Feature_HasEIJMPCALLBit = 3,
3860 Feature_HasADDSUBIWBit = 0,
3861 Feature_HasSmallStackBit = 15,
3862 Feature_HasMOVWBit = 10,
3863 Feature_HasLPMBit = 8,
3864 Feature_HasLPMXBit = 9,
3865 Feature_HasELPMBit = 4,
3866 Feature_HasELPMXBit = 5,
3867 Feature_HasSPMBit = 12,
3868 Feature_HasSPMXBit = 13,
3869 Feature_HasDESBit = 2,
3870 Feature_SupportsRMWBit = 18,
3871 Feature_SupportsMultiplicationBit = 17,
3872 Feature_HasBREAKBit = 1,
3873 Feature_HasTinyEncodingBit = 16,
3874 Feature_HasNonTinyEncodingBit = 11,
3875};
3876
3877inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
3878 FeatureBitset Features;
3879 if (FB[AVR::FeatureSRAM])
3880 Features.set(Feature_HasSRAMBit);
3881 if (FB[AVR::FeatureJMPCALL])
3882 Features.set(Feature_HasJMPCALLBit);
3883 if (FB[AVR::FeatureIJMPCALL])
3884 Features.set(Feature_HasIJMPCALLBit);
3885 if (FB[AVR::FeatureEIJMPCALL])
3886 Features.set(Feature_HasEIJMPCALLBit);
3887 if (FB[AVR::FeatureADDSUBIW])
3888 Features.set(Feature_HasADDSUBIWBit);
3889 if (FB[AVR::FeatureSmallStack])
3890 Features.set(Feature_HasSmallStackBit);
3891 if (FB[AVR::FeatureMOVW])
3892 Features.set(Feature_HasMOVWBit);
3893 if (FB[AVR::FeatureLPM])
3894 Features.set(Feature_HasLPMBit);
3895 if (FB[AVR::FeatureLPMX])
3896 Features.set(Feature_HasLPMXBit);
3897 if (FB[AVR::FeatureELPM])
3898 Features.set(Feature_HasELPMBit);
3899 if (FB[AVR::FeatureELPMX])
3900 Features.set(Feature_HasELPMXBit);
3901 if (FB[AVR::FeatureSPM])
3902 Features.set(Feature_HasSPMBit);
3903 if (FB[AVR::FeatureSPMX])
3904 Features.set(Feature_HasSPMXBit);
3905 if (FB[AVR::FeatureDES])
3906 Features.set(Feature_HasDESBit);
3907 if (FB[AVR::FeatureRMW])
3908 Features.set(Feature_SupportsRMWBit);
3909 if (FB[AVR::FeatureMultiplication])
3910 Features.set(Feature_SupportsMultiplicationBit);
3911 if (FB[AVR::FeatureBREAK])
3912 Features.set(Feature_HasBREAKBit);
3913 if (FB[AVR::FeatureTinyEncoding])
3914 Features.set(Feature_HasTinyEncodingBit);
3915 if (!FB[AVR::FeatureTinyEncoding])
3916 Features.set(Feature_HasNonTinyEncodingBit);
3917 return Features;
3918}
3919
3920inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
3921 enum : uint8_t {
3922 CEFBS_None,
3923 CEFBS_HasADDSUBIW,
3924 CEFBS_HasBREAK,
3925 CEFBS_HasDES,
3926 CEFBS_HasEIJMPCALL,
3927 CEFBS_HasELPM,
3928 CEFBS_HasELPMX,
3929 CEFBS_HasIJMPCALL,
3930 CEFBS_HasJMPCALL,
3931 CEFBS_HasLPM,
3932 CEFBS_HasLPMX,
3933 CEFBS_HasMOVW,
3934 CEFBS_HasNonTinyEncoding,
3935 CEFBS_HasSPM,
3936 CEFBS_HasSPMX,
3937 CEFBS_HasSRAM,
3938 CEFBS_HasTinyEncoding,
3939 CEFBS_SupportsMultiplication,
3940 CEFBS_SupportsRMW,
3941 CEFBS_HasSRAM_HasNonTinyEncoding,
3942 CEFBS_HasSRAM_HasTinyEncoding,
3943 };
3944
3945 static constexpr FeatureBitset FeatureBitsets[] = {
3946 {}, // CEFBS_None
3947 {Feature_HasADDSUBIWBit, },
3948 {Feature_HasBREAKBit, },
3949 {Feature_HasDESBit, },
3950 {Feature_HasEIJMPCALLBit, },
3951 {Feature_HasELPMBit, },
3952 {Feature_HasELPMXBit, },
3953 {Feature_HasIJMPCALLBit, },
3954 {Feature_HasJMPCALLBit, },
3955 {Feature_HasLPMBit, },
3956 {Feature_HasLPMXBit, },
3957 {Feature_HasMOVWBit, },
3958 {Feature_HasNonTinyEncodingBit, },
3959 {Feature_HasSPMBit, },
3960 {Feature_HasSPMXBit, },
3961 {Feature_HasSRAMBit, },
3962 {Feature_HasTinyEncodingBit, },
3963 {Feature_SupportsMultiplicationBit, },
3964 {Feature_SupportsRMWBit, },
3965 {Feature_HasSRAMBit, Feature_HasNonTinyEncodingBit, },
3966 {Feature_HasSRAMBit, Feature_HasTinyEncodingBit, },
3967 };
3968 static constexpr uint8_t RequiredFeaturesRefs[] = {
3969 CEFBS_None, // PHI = 0
3970 CEFBS_None, // INLINEASM = 1
3971 CEFBS_None, // INLINEASM_BR = 2
3972 CEFBS_None, // CFI_INSTRUCTION = 3
3973 CEFBS_None, // EH_LABEL = 4
3974 CEFBS_None, // GC_LABEL = 5
3975 CEFBS_None, // ANNOTATION_LABEL = 6
3976 CEFBS_None, // KILL = 7
3977 CEFBS_None, // EXTRACT_SUBREG = 8
3978 CEFBS_None, // INSERT_SUBREG = 9
3979 CEFBS_None, // IMPLICIT_DEF = 10
3980 CEFBS_None, // SUBREG_TO_REG = 11
3981 CEFBS_None, // COPY_TO_REGCLASS = 12
3982 CEFBS_None, // DBG_VALUE = 13
3983 CEFBS_None, // DBG_VALUE_LIST = 14
3984 CEFBS_None, // DBG_INSTR_REF = 15
3985 CEFBS_None, // DBG_PHI = 16
3986 CEFBS_None, // DBG_LABEL = 17
3987 CEFBS_None, // REG_SEQUENCE = 18
3988 CEFBS_None, // COPY = 19
3989 CEFBS_None, // BUNDLE = 20
3990 CEFBS_None, // LIFETIME_START = 21
3991 CEFBS_None, // LIFETIME_END = 22
3992 CEFBS_None, // PSEUDO_PROBE = 23
3993 CEFBS_None, // ARITH_FENCE = 24
3994 CEFBS_None, // STACKMAP = 25
3995 CEFBS_None, // FENTRY_CALL = 26
3996 CEFBS_None, // PATCHPOINT = 27
3997 CEFBS_None, // LOAD_STACK_GUARD = 28
3998 CEFBS_None, // PREALLOCATED_SETUP = 29
3999 CEFBS_None, // PREALLOCATED_ARG = 30
4000 CEFBS_None, // STATEPOINT = 31
4001 CEFBS_None, // LOCAL_ESCAPE = 32
4002 CEFBS_None, // FAULTING_OP = 33
4003 CEFBS_None, // PATCHABLE_OP = 34
4004 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
4005 CEFBS_None, // PATCHABLE_RET = 36
4006 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
4007 CEFBS_None, // PATCHABLE_TAIL_CALL = 38
4008 CEFBS_None, // PATCHABLE_EVENT_CALL = 39
4009 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
4010 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
4011 CEFBS_None, // MEMBARRIER = 42
4012 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
4013 CEFBS_None, // CONVERGENCECTRL_ENTRY = 44
4014 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 45
4015 CEFBS_None, // CONVERGENCECTRL_LOOP = 46
4016 CEFBS_None, // CONVERGENCECTRL_GLUE = 47
4017 CEFBS_None, // G_ASSERT_SEXT = 48
4018 CEFBS_None, // G_ASSERT_ZEXT = 49
4019 CEFBS_None, // G_ASSERT_ALIGN = 50
4020 CEFBS_None, // G_ADD = 51
4021 CEFBS_None, // G_SUB = 52
4022 CEFBS_None, // G_MUL = 53
4023 CEFBS_None, // G_SDIV = 54
4024 CEFBS_None, // G_UDIV = 55
4025 CEFBS_None, // G_SREM = 56
4026 CEFBS_None, // G_UREM = 57
4027 CEFBS_None, // G_SDIVREM = 58
4028 CEFBS_None, // G_UDIVREM = 59
4029 CEFBS_None, // G_AND = 60
4030 CEFBS_None, // G_OR = 61
4031 CEFBS_None, // G_XOR = 62
4032 CEFBS_None, // G_IMPLICIT_DEF = 63
4033 CEFBS_None, // G_PHI = 64
4034 CEFBS_None, // G_FRAME_INDEX = 65
4035 CEFBS_None, // G_GLOBAL_VALUE = 66
4036 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 67
4037 CEFBS_None, // G_CONSTANT_POOL = 68
4038 CEFBS_None, // G_EXTRACT = 69
4039 CEFBS_None, // G_UNMERGE_VALUES = 70
4040 CEFBS_None, // G_INSERT = 71
4041 CEFBS_None, // G_MERGE_VALUES = 72
4042 CEFBS_None, // G_BUILD_VECTOR = 73
4043 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 74
4044 CEFBS_None, // G_CONCAT_VECTORS = 75
4045 CEFBS_None, // G_PTRTOINT = 76
4046 CEFBS_None, // G_INTTOPTR = 77
4047 CEFBS_None, // G_BITCAST = 78
4048 CEFBS_None, // G_FREEZE = 79
4049 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 80
4050 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 81
4051 CEFBS_None, // G_INTRINSIC_TRUNC = 82
4052 CEFBS_None, // G_INTRINSIC_ROUND = 83
4053 CEFBS_None, // G_INTRINSIC_LRINT = 84
4054 CEFBS_None, // G_INTRINSIC_LLRINT = 85
4055 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 86
4056 CEFBS_None, // G_READCYCLECOUNTER = 87
4057 CEFBS_None, // G_READSTEADYCOUNTER = 88
4058 CEFBS_None, // G_LOAD = 89
4059 CEFBS_None, // G_SEXTLOAD = 90
4060 CEFBS_None, // G_ZEXTLOAD = 91
4061 CEFBS_None, // G_INDEXED_LOAD = 92
4062 CEFBS_None, // G_INDEXED_SEXTLOAD = 93
4063 CEFBS_None, // G_INDEXED_ZEXTLOAD = 94
4064 CEFBS_None, // G_STORE = 95
4065 CEFBS_None, // G_INDEXED_STORE = 96
4066 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97
4067 CEFBS_None, // G_ATOMIC_CMPXCHG = 98
4068 CEFBS_None, // G_ATOMICRMW_XCHG = 99
4069 CEFBS_None, // G_ATOMICRMW_ADD = 100
4070 CEFBS_None, // G_ATOMICRMW_SUB = 101
4071 CEFBS_None, // G_ATOMICRMW_AND = 102
4072 CEFBS_None, // G_ATOMICRMW_NAND = 103
4073 CEFBS_None, // G_ATOMICRMW_OR = 104
4074 CEFBS_None, // G_ATOMICRMW_XOR = 105
4075 CEFBS_None, // G_ATOMICRMW_MAX = 106
4076 CEFBS_None, // G_ATOMICRMW_MIN = 107
4077 CEFBS_None, // G_ATOMICRMW_UMAX = 108
4078 CEFBS_None, // G_ATOMICRMW_UMIN = 109
4079 CEFBS_None, // G_ATOMICRMW_FADD = 110
4080 CEFBS_None, // G_ATOMICRMW_FSUB = 111
4081 CEFBS_None, // G_ATOMICRMW_FMAX = 112
4082 CEFBS_None, // G_ATOMICRMW_FMIN = 113
4083 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 114
4084 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 115
4085 CEFBS_None, // G_FENCE = 116
4086 CEFBS_None, // G_PREFETCH = 117
4087 CEFBS_None, // G_BRCOND = 118
4088 CEFBS_None, // G_BRINDIRECT = 119
4089 CEFBS_None, // G_INVOKE_REGION_START = 120
4090 CEFBS_None, // G_INTRINSIC = 121
4091 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 122
4092 CEFBS_None, // G_INTRINSIC_CONVERGENT = 123
4093 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124
4094 CEFBS_None, // G_ANYEXT = 125
4095 CEFBS_None, // G_TRUNC = 126
4096 CEFBS_None, // G_CONSTANT = 127
4097 CEFBS_None, // G_FCONSTANT = 128
4098 CEFBS_None, // G_VASTART = 129
4099 CEFBS_None, // G_VAARG = 130
4100 CEFBS_None, // G_SEXT = 131
4101 CEFBS_None, // G_SEXT_INREG = 132
4102 CEFBS_None, // G_ZEXT = 133
4103 CEFBS_None, // G_SHL = 134
4104 CEFBS_None, // G_LSHR = 135
4105 CEFBS_None, // G_ASHR = 136
4106 CEFBS_None, // G_FSHL = 137
4107 CEFBS_None, // G_FSHR = 138
4108 CEFBS_None, // G_ROTR = 139
4109 CEFBS_None, // G_ROTL = 140
4110 CEFBS_None, // G_ICMP = 141
4111 CEFBS_None, // G_FCMP = 142
4112 CEFBS_None, // G_SCMP = 143
4113 CEFBS_None, // G_UCMP = 144
4114 CEFBS_None, // G_SELECT = 145
4115 CEFBS_None, // G_UADDO = 146
4116 CEFBS_None, // G_UADDE = 147
4117 CEFBS_None, // G_USUBO = 148
4118 CEFBS_None, // G_USUBE = 149
4119 CEFBS_None, // G_SADDO = 150
4120 CEFBS_None, // G_SADDE = 151
4121 CEFBS_None, // G_SSUBO = 152
4122 CEFBS_None, // G_SSUBE = 153
4123 CEFBS_None, // G_UMULO = 154
4124 CEFBS_None, // G_SMULO = 155
4125 CEFBS_None, // G_UMULH = 156
4126 CEFBS_None, // G_SMULH = 157
4127 CEFBS_None, // G_UADDSAT = 158
4128 CEFBS_None, // G_SADDSAT = 159
4129 CEFBS_None, // G_USUBSAT = 160
4130 CEFBS_None, // G_SSUBSAT = 161
4131 CEFBS_None, // G_USHLSAT = 162
4132 CEFBS_None, // G_SSHLSAT = 163
4133 CEFBS_None, // G_SMULFIX = 164
4134 CEFBS_None, // G_UMULFIX = 165
4135 CEFBS_None, // G_SMULFIXSAT = 166
4136 CEFBS_None, // G_UMULFIXSAT = 167
4137 CEFBS_None, // G_SDIVFIX = 168
4138 CEFBS_None, // G_UDIVFIX = 169
4139 CEFBS_None, // G_SDIVFIXSAT = 170
4140 CEFBS_None, // G_UDIVFIXSAT = 171
4141 CEFBS_None, // G_FADD = 172
4142 CEFBS_None, // G_FSUB = 173
4143 CEFBS_None, // G_FMUL = 174
4144 CEFBS_None, // G_FMA = 175
4145 CEFBS_None, // G_FMAD = 176
4146 CEFBS_None, // G_FDIV = 177
4147 CEFBS_None, // G_FREM = 178
4148 CEFBS_None, // G_FPOW = 179
4149 CEFBS_None, // G_FPOWI = 180
4150 CEFBS_None, // G_FEXP = 181
4151 CEFBS_None, // G_FEXP2 = 182
4152 CEFBS_None, // G_FEXP10 = 183
4153 CEFBS_None, // G_FLOG = 184
4154 CEFBS_None, // G_FLOG2 = 185
4155 CEFBS_None, // G_FLOG10 = 186
4156 CEFBS_None, // G_FLDEXP = 187
4157 CEFBS_None, // G_FFREXP = 188
4158 CEFBS_None, // G_FNEG = 189
4159 CEFBS_None, // G_FPEXT = 190
4160 CEFBS_None, // G_FPTRUNC = 191
4161 CEFBS_None, // G_FPTOSI = 192
4162 CEFBS_None, // G_FPTOUI = 193
4163 CEFBS_None, // G_SITOFP = 194
4164 CEFBS_None, // G_UITOFP = 195
4165 CEFBS_None, // G_FABS = 196
4166 CEFBS_None, // G_FCOPYSIGN = 197
4167 CEFBS_None, // G_IS_FPCLASS = 198
4168 CEFBS_None, // G_FCANONICALIZE = 199
4169 CEFBS_None, // G_FMINNUM = 200
4170 CEFBS_None, // G_FMAXNUM = 201
4171 CEFBS_None, // G_FMINNUM_IEEE = 202
4172 CEFBS_None, // G_FMAXNUM_IEEE = 203
4173 CEFBS_None, // G_FMINIMUM = 204
4174 CEFBS_None, // G_FMAXIMUM = 205
4175 CEFBS_None, // G_GET_FPENV = 206
4176 CEFBS_None, // G_SET_FPENV = 207
4177 CEFBS_None, // G_RESET_FPENV = 208
4178 CEFBS_None, // G_GET_FPMODE = 209
4179 CEFBS_None, // G_SET_FPMODE = 210
4180 CEFBS_None, // G_RESET_FPMODE = 211
4181 CEFBS_None, // G_PTR_ADD = 212
4182 CEFBS_None, // G_PTRMASK = 213
4183 CEFBS_None, // G_SMIN = 214
4184 CEFBS_None, // G_SMAX = 215
4185 CEFBS_None, // G_UMIN = 216
4186 CEFBS_None, // G_UMAX = 217
4187 CEFBS_None, // G_ABS = 218
4188 CEFBS_None, // G_LROUND = 219
4189 CEFBS_None, // G_LLROUND = 220
4190 CEFBS_None, // G_BR = 221
4191 CEFBS_None, // G_BRJT = 222
4192 CEFBS_None, // G_VSCALE = 223
4193 CEFBS_None, // G_INSERT_SUBVECTOR = 224
4194 CEFBS_None, // G_EXTRACT_SUBVECTOR = 225
4195 CEFBS_None, // G_INSERT_VECTOR_ELT = 226
4196 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 227
4197 CEFBS_None, // G_SHUFFLE_VECTOR = 228
4198 CEFBS_None, // G_SPLAT_VECTOR = 229
4199 CEFBS_None, // G_VECTOR_COMPRESS = 230
4200 CEFBS_None, // G_CTTZ = 231
4201 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 232
4202 CEFBS_None, // G_CTLZ = 233
4203 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 234
4204 CEFBS_None, // G_CTPOP = 235
4205 CEFBS_None, // G_BSWAP = 236
4206 CEFBS_None, // G_BITREVERSE = 237
4207 CEFBS_None, // G_FCEIL = 238
4208 CEFBS_None, // G_FCOS = 239
4209 CEFBS_None, // G_FSIN = 240
4210 CEFBS_None, // G_FTAN = 241
4211 CEFBS_None, // G_FACOS = 242
4212 CEFBS_None, // G_FASIN = 243
4213 CEFBS_None, // G_FATAN = 244
4214 CEFBS_None, // G_FCOSH = 245
4215 CEFBS_None, // G_FSINH = 246
4216 CEFBS_None, // G_FTANH = 247
4217 CEFBS_None, // G_FSQRT = 248
4218 CEFBS_None, // G_FFLOOR = 249
4219 CEFBS_None, // G_FRINT = 250
4220 CEFBS_None, // G_FNEARBYINT = 251
4221 CEFBS_None, // G_ADDRSPACE_CAST = 252
4222 CEFBS_None, // G_BLOCK_ADDR = 253
4223 CEFBS_None, // G_JUMP_TABLE = 254
4224 CEFBS_None, // G_DYN_STACKALLOC = 255
4225 CEFBS_None, // G_STACKSAVE = 256
4226 CEFBS_None, // G_STACKRESTORE = 257
4227 CEFBS_None, // G_STRICT_FADD = 258
4228 CEFBS_None, // G_STRICT_FSUB = 259
4229 CEFBS_None, // G_STRICT_FMUL = 260
4230 CEFBS_None, // G_STRICT_FDIV = 261
4231 CEFBS_None, // G_STRICT_FREM = 262
4232 CEFBS_None, // G_STRICT_FMA = 263
4233 CEFBS_None, // G_STRICT_FSQRT = 264
4234 CEFBS_None, // G_STRICT_FLDEXP = 265
4235 CEFBS_None, // G_READ_REGISTER = 266
4236 CEFBS_None, // G_WRITE_REGISTER = 267
4237 CEFBS_None, // G_MEMCPY = 268
4238 CEFBS_None, // G_MEMCPY_INLINE = 269
4239 CEFBS_None, // G_MEMMOVE = 270
4240 CEFBS_None, // G_MEMSET = 271
4241 CEFBS_None, // G_BZERO = 272
4242 CEFBS_None, // G_TRAP = 273
4243 CEFBS_None, // G_DEBUGTRAP = 274
4244 CEFBS_None, // G_UBSANTRAP = 275
4245 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 276
4246 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 277
4247 CEFBS_None, // G_VECREDUCE_FADD = 278
4248 CEFBS_None, // G_VECREDUCE_FMUL = 279
4249 CEFBS_None, // G_VECREDUCE_FMAX = 280
4250 CEFBS_None, // G_VECREDUCE_FMIN = 281
4251 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 282
4252 CEFBS_None, // G_VECREDUCE_FMINIMUM = 283
4253 CEFBS_None, // G_VECREDUCE_ADD = 284
4254 CEFBS_None, // G_VECREDUCE_MUL = 285
4255 CEFBS_None, // G_VECREDUCE_AND = 286
4256 CEFBS_None, // G_VECREDUCE_OR = 287
4257 CEFBS_None, // G_VECREDUCE_XOR = 288
4258 CEFBS_None, // G_VECREDUCE_SMAX = 289
4259 CEFBS_None, // G_VECREDUCE_SMIN = 290
4260 CEFBS_None, // G_VECREDUCE_UMAX = 291
4261 CEFBS_None, // G_VECREDUCE_UMIN = 292
4262 CEFBS_None, // G_SBFX = 293
4263 CEFBS_None, // G_UBFX = 294
4264 CEFBS_None, // ADCWRdRr = 295
4265 CEFBS_None, // ADDWRdRr = 296
4266 CEFBS_None, // ADJCALLSTACKDOWN = 297
4267 CEFBS_None, // ADJCALLSTACKUP = 298
4268 CEFBS_None, // ANDIWRdK = 299
4269 CEFBS_None, // ANDWRdRr = 300
4270 CEFBS_None, // ASRBNRd = 301
4271 CEFBS_None, // ASRWLoRd = 302
4272 CEFBS_None, // ASRWNRd = 303
4273 CEFBS_None, // ASRWRd = 304
4274 CEFBS_None, // Asr16 = 305
4275 CEFBS_None, // Asr32 = 306
4276 CEFBS_None, // Asr8 = 307
4277 CEFBS_None, // AtomicFence = 308
4278 CEFBS_None, // AtomicLoad16 = 309
4279 CEFBS_None, // AtomicLoad8 = 310
4280 CEFBS_None, // AtomicLoadAdd16 = 311
4281 CEFBS_None, // AtomicLoadAdd8 = 312
4282 CEFBS_None, // AtomicLoadAnd16 = 313
4283 CEFBS_None, // AtomicLoadAnd8 = 314
4284 CEFBS_None, // AtomicLoadOr16 = 315
4285 CEFBS_None, // AtomicLoadOr8 = 316
4286 CEFBS_None, // AtomicLoadSub16 = 317
4287 CEFBS_None, // AtomicLoadSub8 = 318
4288 CEFBS_None, // AtomicLoadXor16 = 319
4289 CEFBS_None, // AtomicLoadXor8 = 320
4290 CEFBS_None, // AtomicStore16 = 321
4291 CEFBS_None, // AtomicStore8 = 322
4292 CEFBS_None, // COMWRd = 323
4293 CEFBS_None, // CPCWRdRr = 324
4294 CEFBS_None, // CPWRdRr = 325
4295 CEFBS_None, // CopyZero = 326
4296 CEFBS_HasELPM, // ELPMBRdZ = 327
4297 CEFBS_HasELPMX, // ELPMBRdZPi = 328
4298 CEFBS_HasELPM, // ELPMWRdZ = 329
4299 CEFBS_HasELPMX, // ELPMWRdZPi = 330
4300 CEFBS_None, // EORWRdRr = 331
4301 CEFBS_None, // FRMIDX = 332
4302 CEFBS_None, // INWRdA = 333
4303 CEFBS_HasSRAM, // LDDWRdPtrQ = 334
4304 CEFBS_HasSRAM, // LDDWRdYQ = 335
4305 CEFBS_None, // LDIWRdK = 336
4306 CEFBS_HasSRAM_HasNonTinyEncoding, // LDSWRdK = 337
4307 CEFBS_HasSRAM, // LDWRdPtr = 338
4308 CEFBS_HasSRAM, // LDWRdPtrPd = 339
4309 CEFBS_HasSRAM, // LDWRdPtrPi = 340
4310 CEFBS_HasLPM, // LPMBRdZ = 341
4311 CEFBS_HasLPM, // LPMWRdZ = 342
4312 CEFBS_HasLPMX, // LPMWRdZPi = 343
4313 CEFBS_None, // LSLBNRd = 344
4314 CEFBS_None, // LSLWHiRd = 345
4315 CEFBS_None, // LSLWNRd = 346
4316 CEFBS_None, // LSLWRd = 347
4317 CEFBS_None, // LSRBNRd = 348
4318 CEFBS_None, // LSRWLoRd = 349
4319 CEFBS_None, // LSRWNRd = 350
4320 CEFBS_None, // LSRWRd = 351
4321 CEFBS_None, // Lsl16 = 352
4322 CEFBS_None, // Lsl32 = 353
4323 CEFBS_None, // Lsl8 = 354
4324 CEFBS_None, // Lsr16 = 355
4325 CEFBS_None, // Lsr32 = 356
4326 CEFBS_None, // Lsr8 = 357
4327 CEFBS_None, // NEGWRd = 358
4328 CEFBS_None, // ORIWRdK = 359
4329 CEFBS_None, // ORWRdRr = 360
4330 CEFBS_None, // OUTWARr = 361
4331 CEFBS_HasSRAM, // POPWRd = 362
4332 CEFBS_HasSRAM, // PUSHWRr = 363
4333 CEFBS_HasNonTinyEncoding, // ROLBRdR1 = 364
4334 CEFBS_HasTinyEncoding, // ROLBRdR17 = 365
4335 CEFBS_None, // ROLWRd = 366
4336 CEFBS_None, // RORBRd = 367
4337 CEFBS_None, // RORWRd = 368
4338 CEFBS_None, // Rol16 = 369
4339 CEFBS_None, // Rol8 = 370
4340 CEFBS_None, // Ror16 = 371
4341 CEFBS_None, // Ror8 = 372
4342 CEFBS_None, // SBCIWRdK = 373
4343 CEFBS_None, // SBCWRdRr = 374
4344 CEFBS_None, // SEXT = 375
4345 CEFBS_None, // SPREAD = 376
4346 CEFBS_None, // SPWRITE = 377
4347 CEFBS_None, // STDSPQRr = 378
4348 CEFBS_HasSRAM, // STDWPtrQRr = 379
4349 CEFBS_None, // STDWSPQRr = 380
4350 CEFBS_HasSRAM_HasNonTinyEncoding, // STSWKRr = 381
4351 CEFBS_HasSRAM, // STWPtrPdRr = 382
4352 CEFBS_HasSRAM, // STWPtrPiRr = 383
4353 CEFBS_HasSRAM, // STWPtrRr = 384
4354 CEFBS_None, // SUBIWRdK = 385
4355 CEFBS_None, // SUBWRdRr = 386
4356 CEFBS_None, // Select16 = 387
4357 CEFBS_None, // Select8 = 388
4358 CEFBS_None, // ZEXT = 389
4359 CEFBS_None, // ADCRdRr = 390
4360 CEFBS_None, // ADDRdRr = 391
4361 CEFBS_HasADDSUBIW, // ADIWRdK = 392
4362 CEFBS_None, // ANDIRdK = 393
4363 CEFBS_None, // ANDRdRr = 394
4364 CEFBS_None, // ASRRd = 395
4365 CEFBS_None, // BCLRs = 396
4366 CEFBS_None, // BLD = 397
4367 CEFBS_None, // BRBCsk = 398
4368 CEFBS_None, // BRBSsk = 399
4369 CEFBS_HasBREAK, // BREAK = 400
4370 CEFBS_None, // BREQk = 401
4371 CEFBS_None, // BRGEk = 402
4372 CEFBS_None, // BRLOk = 403
4373 CEFBS_None, // BRLTk = 404
4374 CEFBS_None, // BRMIk = 405
4375 CEFBS_None, // BRNEk = 406
4376 CEFBS_None, // BRPLk = 407
4377 CEFBS_None, // BRSHk = 408
4378 CEFBS_None, // BSETs = 409
4379 CEFBS_None, // BST = 410
4380 CEFBS_HasJMPCALL, // CALLk = 411
4381 CEFBS_None, // CBIAb = 412
4382 CEFBS_None, // COMRd = 413
4383 CEFBS_None, // CPCRdRr = 414
4384 CEFBS_None, // CPIRdK = 415
4385 CEFBS_None, // CPRdRr = 416
4386 CEFBS_None, // CPSE = 417
4387 CEFBS_None, // DECRd = 418
4388 CEFBS_HasDES, // DESK = 419
4389 CEFBS_HasEIJMPCALL, // EICALL = 420
4390 CEFBS_HasEIJMPCALL, // EIJMP = 421
4391 CEFBS_HasELPM, // ELPM = 422
4392 CEFBS_HasELPMX, // ELPMRdZ = 423
4393 CEFBS_HasELPMX, // ELPMRdZPi = 424
4394 CEFBS_None, // EORRdRr = 425
4395 CEFBS_SupportsMultiplication, // FMUL = 426
4396 CEFBS_SupportsMultiplication, // FMULS = 427
4397 CEFBS_SupportsMultiplication, // FMULSU = 428
4398 CEFBS_HasIJMPCALL, // ICALL = 429
4399 CEFBS_HasIJMPCALL, // IJMP = 430
4400 CEFBS_None, // INCRd = 431
4401 CEFBS_None, // INRdA = 432
4402 CEFBS_HasJMPCALL, // JMPk = 433
4403 CEFBS_SupportsRMW, // LACZRd = 434
4404 CEFBS_SupportsRMW, // LASZRd = 435
4405 CEFBS_SupportsRMW, // LATZRd = 436
4406 CEFBS_HasSRAM_HasNonTinyEncoding, // LDDRdPtrQ = 437
4407 CEFBS_None, // LDIRdK = 438
4408 CEFBS_HasSRAM, // LDRdPtr = 439
4409 CEFBS_HasSRAM, // LDRdPtrPd = 440
4410 CEFBS_HasSRAM, // LDRdPtrPi = 441
4411 CEFBS_HasSRAM_HasNonTinyEncoding, // LDSRdK = 442
4412 CEFBS_HasSRAM_HasTinyEncoding, // LDSRdKTiny = 443
4413 CEFBS_HasLPM, // LPM = 444
4414 CEFBS_HasLPMX, // LPMRdZ = 445
4415 CEFBS_HasLPMX, // LPMRdZPi = 446
4416 CEFBS_None, // LSRRd = 447
4417 CEFBS_None, // MOVRdRr = 448
4418 CEFBS_HasMOVW, // MOVWRdRr = 449
4419 CEFBS_SupportsMultiplication, // MULRdRr = 450
4420 CEFBS_SupportsMultiplication, // MULSRdRr = 451
4421 CEFBS_SupportsMultiplication, // MULSURdRr = 452
4422 CEFBS_None, // NEGRd = 453
4423 CEFBS_None, // NOP = 454
4424 CEFBS_None, // ORIRdK = 455
4425 CEFBS_None, // ORRdRr = 456
4426 CEFBS_None, // OUTARr = 457
4427 CEFBS_HasSRAM, // POPRd = 458
4428 CEFBS_HasSRAM, // PUSHRr = 459
4429 CEFBS_None, // RCALLk = 460
4430 CEFBS_None, // RET = 461
4431 CEFBS_None, // RETI = 462
4432 CEFBS_None, // RJMPk = 463
4433 CEFBS_None, // RORRd = 464
4434 CEFBS_None, // SBCIRdK = 465
4435 CEFBS_None, // SBCRdRr = 466
4436 CEFBS_None, // SBIAb = 467
4437 CEFBS_None, // SBICAb = 468
4438 CEFBS_None, // SBISAb = 469
4439 CEFBS_HasADDSUBIW, // SBIWRdK = 470
4440 CEFBS_None, // SBRCRrB = 471
4441 CEFBS_None, // SBRSRrB = 472
4442 CEFBS_None, // SLEEP = 473
4443 CEFBS_HasSPM, // SPM = 474
4444 CEFBS_HasSPMX, // SPMZPi = 475
4445 CEFBS_HasSRAM_HasNonTinyEncoding, // STDPtrQRr = 476
4446 CEFBS_HasSRAM, // STPtrPdRr = 477
4447 CEFBS_HasSRAM, // STPtrPiRr = 478
4448 CEFBS_HasSRAM, // STPtrRr = 479
4449 CEFBS_HasSRAM_HasNonTinyEncoding, // STSKRr = 480
4450 CEFBS_HasSRAM_HasTinyEncoding, // STSKRrTiny = 481
4451 CEFBS_None, // SUBIRdK = 482
4452 CEFBS_None, // SUBRdRr = 483
4453 CEFBS_None, // SWAPRd = 484
4454 CEFBS_None, // WDR = 485
4455 CEFBS_SupportsRMW, // XCHZRd = 486
4456 };
4457
4458 assert(Opcode < 487);
4459 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
4460}
4461
4462} // end namespace AVR_MC
4463} // end namespace llvm
4464#endif // GET_COMPUTE_FEATURES
4465
4466#ifdef GET_AVAILABLE_OPCODE_CHECKER
4467#undef GET_AVAILABLE_OPCODE_CHECKER
4468namespace llvm {
4469namespace AVR_MC {
4470bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
4471 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4472 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4473 FeatureBitset MissingFeatures =
4474 (AvailableFeatures & RequiredFeatures) ^
4475 RequiredFeatures;
4476 return !MissingFeatures.any();
4477}
4478} // end namespace AVR_MC
4479} // end namespace llvm
4480#endif // GET_AVAILABLE_OPCODE_CHECKER
4481
4482#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
4483#undef ENABLE_INSTR_PREDICATE_VERIFIER
4484#include <sstream>
4485
4486namespace llvm {
4487namespace AVR_MC {
4488
4489#ifndef NDEBUG
4490static const char *SubtargetFeatureNames[] = {
4491 "Feature_HasADDSUBIW",
4492 "Feature_HasBREAK",
4493 "Feature_HasDES",
4494 "Feature_HasEIJMPCALL",
4495 "Feature_HasELPM",
4496 "Feature_HasELPMX",
4497 "Feature_HasIJMPCALL",
4498 "Feature_HasJMPCALL",
4499 "Feature_HasLPM",
4500 "Feature_HasLPMX",
4501 "Feature_HasMOVW",
4502 "Feature_HasNonTinyEncoding",
4503 "Feature_HasSPM",
4504 "Feature_HasSPMX",
4505 "Feature_HasSRAM",
4506 "Feature_HasSmallStack",
4507 "Feature_HasTinyEncoding",
4508 "Feature_SupportsMultiplication",
4509 "Feature_SupportsRMW",
4510 nullptr
4511};
4512
4513#endif // NDEBUG
4514
4515void verifyInstructionPredicates(
4516 unsigned Opcode, const FeatureBitset &Features) {
4517#ifndef NDEBUG
4518 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4519 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4520 FeatureBitset MissingFeatures =
4521 (AvailableFeatures & RequiredFeatures) ^
4522 RequiredFeatures;
4523 if (MissingFeatures.any()) {
4524 std::ostringstream Msg;
4525 Msg << "Attempting to emit " << &AVRInstrNameData[AVRInstrNameIndices[Opcode]]
4526 << " instruction but the ";
4527 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
4528 if (MissingFeatures.test(i))
4529 Msg << SubtargetFeatureNames[i] << " ";
4530 Msg << "predicate(s) are not met";
4531 report_fatal_error(Msg.str().c_str());
4532 }
4533#endif // NDEBUG
4534}
4535} // end namespace AVR_MC
4536} // end namespace llvm
4537#endif // ENABLE_INSTR_PREDICATE_VERIFIER
4538
4539