1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass AVRMCRegisterClasses[];
17
18namespace AVR {
19enum {
20 NoRegister,
21 SP = 1,
22 SPH = 2,
23 SPL = 3,
24 SREG = 4,
25 R0 = 5,
26 R1 = 6,
27 R2 = 7,
28 R3 = 8,
29 R4 = 9,
30 R5 = 10,
31 R6 = 11,
32 R7 = 12,
33 R8 = 13,
34 R9 = 14,
35 R10 = 15,
36 R11 = 16,
37 R12 = 17,
38 R13 = 18,
39 R14 = 19,
40 R15 = 20,
41 R16 = 21,
42 R17 = 22,
43 R18 = 23,
44 R19 = 24,
45 R20 = 25,
46 R21 = 26,
47 R22 = 27,
48 R23 = 28,
49 R24 = 29,
50 R25 = 30,
51 R26 = 31,
52 R27 = 32,
53 R28 = 33,
54 R29 = 34,
55 R30 = 35,
56 R31 = 36,
57 R1R0 = 37,
58 R3R2 = 38,
59 R5R4 = 39,
60 R7R6 = 40,
61 R9R8 = 41,
62 R10R9 = 42,
63 R11R10 = 43,
64 R12R11 = 44,
65 R13R12 = 45,
66 R14R13 = 46,
67 R15R14 = 47,
68 R16R15 = 48,
69 R17R16 = 49,
70 R18R17 = 50,
71 R19R18 = 51,
72 R20R19 = 52,
73 R21R20 = 53,
74 R22R21 = 54,
75 R23R22 = 55,
76 R24R23 = 56,
77 R25R24 = 57,
78 R26R25 = 58,
79 R27R26 = 59,
80 R29R28 = 60,
81 R31R30 = 61,
82 NUM_TARGET_REGS // 62
83};
84} // end namespace AVR
85
86// Register classes
87
88namespace AVR {
89enum {
90 GPR8RegClassID = 0,
91 GPR8loRegClassID = 1,
92 LD8RegClassID = 2,
93 LD8loRegClassID = 3,
94 CCRRegClassID = 4,
95 DREGSRegClassID = 5,
96 DREGSMOVWRegClassID = 6,
97 DREGS_with_sub_hi_in_LD8RegClassID = 7,
98 DREGS_with_sub_lo_in_LD8RegClassID = 8,
99 DREGS_with_sub_lo_in_GPR8loRegClassID = 9,
100 DREGS_with_sub_hi_in_GPR8loRegClassID = 10,
101 DLDREGSRegClassID = 11,
102 DREGS_with_sub_hi_in_LD8loRegClassID = 12,
103 DREGS_with_sub_lo_in_LD8loRegClassID = 13,
104 DREGSloRegClassID = 14,
105 DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID = 15,
106 DREGSLD8loRegClassID = 16,
107 IWREGSRegClassID = 17,
108 PTRREGSRegClassID = 18,
109 PTRDISPREGSRegClassID = 19,
110 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID = 20,
111 GPRSPRegClassID = 21,
112 ZREGRegClassID = 22,
113
114};
115} // end namespace AVR
116
117
118// Register alternate name indices
119
120namespace AVR {
121enum {
122 NoRegAltName, // 0
123 ptr, // 1
124 NUM_TARGET_REG_ALT_NAMES = 2
125};
126} // end namespace AVR
127
128
129// Subregister indices
130
131namespace AVR {
132enum : uint16_t {
133 NoSubRegister,
134 sub_hi, // 1
135 sub_lo, // 2
136 NUM_TARGET_SUBREGS
137};
138} // end namespace AVR
139
140// Register pressure sets enum.
141namespace AVR {
142enum RegisterPressureSets {
143 CCR = 0,
144 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo = 1,
145 GPRSP = 2,
146 IWREGS = 3,
147 LD8lo = 4,
148 LD8 = 5,
149 GPR8lo = 6,
150 GPR8lo_with_LD8lo = 7,
151 GPR8 = 8,
152};
153} // end namespace AVR
154
155} // end namespace llvm
156
157#endif // GET_REGINFO_ENUM
158
159/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
160|* *|
161|* MC Register Information *|
162|* *|
163|* Automatically generated file, do not edit! *|
164|* *|
165\*===----------------------------------------------------------------------===*/
166
167
168#ifdef GET_REGINFO_MC_DESC
169#undef GET_REGINFO_MC_DESC
170
171namespace llvm {
172
173extern const int16_t AVRRegDiffLists[] = {
174 /* 0 */ -2, 0,
175 /* 2 */ 2, -1, 0,
176 /* 5 */ -32, 1, 0,
177 /* 8 */ -31, 1, 0,
178 /* 11 */ -30, 1, 0,
179 /* 14 */ -29, 1, 0,
180 /* 17 */ -28, 1, 0,
181 /* 20 */ -27, 1, 0,
182 /* 23 */ -26, 1, 0,
183 /* 26 */ 27, 1, 0,
184 /* 29 */ 25, 0,
185 /* 31 */ 26, 0,
186 /* 33 */ 27, 0,
187 /* 35 */ 28, 0,
188 /* 37 */ 29, 0,
189 /* 39 */ 30, 0,
190 /* 41 */ 31, 0,
191 /* 43 */ 32, 0,
192};
193
194extern const LaneBitmask AVRLaneMaskLists[] = {
195 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
196 /* 3 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
197};
198
199extern const uint16_t AVRSubRegIdxLists[] = {
200 /* 0 */ 2, 1, 0,
201};
202
203
204#ifdef __GNUC__
205#pragma GCC diagnostic push
206#pragma GCC diagnostic ignored "-Woverlength-strings"
207#endif
208extern const char AVRRegStrings[] = {
209 /* 0 */ "R11R10\0"
210 /* 7 */ "R21R20\0"
211 /* 14 */ "R31R30\0"
212 /* 21 */ "R1R0\0"
213 /* 26 */ "R12R11\0"
214 /* 33 */ "R22R21\0"
215 /* 40 */ "R31\0"
216 /* 44 */ "R1\0"
217 /* 47 */ "R13R12\0"
218 /* 54 */ "R23R22\0"
219 /* 61 */ "R3R2\0"
220 /* 66 */ "R14R13\0"
221 /* 73 */ "R24R23\0"
222 /* 80 */ "R3\0"
223 /* 83 */ "R15R14\0"
224 /* 90 */ "R25R24\0"
225 /* 97 */ "R5R4\0"
226 /* 102 */ "R16R15\0"
227 /* 109 */ "R26R25\0"
228 /* 116 */ "R5\0"
229 /* 119 */ "R17R16\0"
230 /* 126 */ "R27R26\0"
231 /* 133 */ "R7R6\0"
232 /* 138 */ "R18R17\0"
233 /* 145 */ "R27\0"
234 /* 149 */ "R7\0"
235 /* 152 */ "R19R18\0"
236 /* 159 */ "R29R28\0"
237 /* 166 */ "R9R8\0"
238 /* 171 */ "R20R19\0"
239 /* 178 */ "R29\0"
240 /* 182 */ "R10R9\0"
241 /* 188 */ "SREG\0"
242 /* 193 */ "SPH\0"
243 /* 197 */ "SPL\0"
244 /* 201 */ "SP\0"
245};
246#ifdef __GNUC__
247#pragma GCC diagnostic pop
248#endif
249
250extern const MCRegisterDesc AVRRegDesc[] = { // Descriptors
251 { 6, 0, 0, 0, 0, 0, 0 },
252 { 201, 2, 1, 0, 24576, 0, 0 },
253 { 193, 1, 3, 2, 4097, 3, 0 },
254 { 197, 1, 0, 2, 4096, 3, 0 },
255 { 188, 1, 1, 2, 4098, 3, 0 },
256 { 23, 1, 43, 2, 4099, 3, 0 },
257 { 44, 1, 41, 2, 4100, 3, 0 },
258 { 63, 1, 41, 2, 4101, 3, 0 },
259 { 80, 1, 39, 2, 4102, 3, 0 },
260 { 99, 1, 39, 2, 4103, 3, 0 },
261 { 116, 1, 37, 2, 4104, 3, 0 },
262 { 135, 1, 37, 2, 4105, 3, 0 },
263 { 149, 1, 35, 2, 4106, 3, 0 },
264 { 168, 1, 35, 2, 4107, 3, 0 },
265 { 185, 1, 26, 2, 4108, 3, 0 },
266 { 3, 1, 26, 2, 4109, 3, 0 },
267 { 29, 1, 26, 2, 4110, 3, 0 },
268 { 50, 1, 26, 2, 4111, 3, 0 },
269 { 69, 1, 26, 2, 4112, 3, 0 },
270 { 86, 1, 26, 2, 4113, 3, 0 },
271 { 105, 1, 26, 2, 4114, 3, 0 },
272 { 122, 1, 26, 2, 4115, 3, 0 },
273 { 141, 1, 26, 2, 4116, 3, 0 },
274 { 155, 1, 26, 2, 4117, 3, 0 },
275 { 174, 1, 26, 2, 4118, 3, 0 },
276 { 10, 1, 26, 2, 4119, 3, 0 },
277 { 36, 1, 26, 2, 4120, 3, 0 },
278 { 57, 1, 26, 2, 4121, 3, 0 },
279 { 76, 1, 26, 2, 4122, 3, 0 },
280 { 93, 1, 26, 2, 4123, 3, 0 },
281 { 112, 1, 26, 2, 4124, 3, 0 },
282 { 129, 1, 26, 2, 4125, 3, 0 },
283 { 145, 1, 33, 2, 4126, 3, 0 },
284 { 162, 1, 33, 2, 4127, 3, 0 },
285 { 178, 1, 31, 2, 4128, 3, 0 },
286 { 17, 1, 31, 2, 4129, 3, 0 },
287 { 40, 1, 29, 2, 4130, 3, 0 },
288 { 21, 5, 1, 0, 24579, 0, 0 },
289 { 61, 8, 1, 0, 24581, 0, 0 },
290 { 97, 11, 1, 0, 24583, 0, 0 },
291 { 133, 14, 1, 0, 24585, 0, 0 },
292 { 166, 17, 1, 0, 24587, 0, 0 },
293 { 182, 17, 1, 0, 24588, 0, 0 },
294 { 0, 17, 1, 0, 24589, 0, 0 },
295 { 26, 17, 1, 0, 24590, 0, 0 },
296 { 47, 17, 1, 0, 24591, 0, 0 },
297 { 66, 17, 1, 0, 24592, 0, 0 },
298 { 83, 17, 1, 0, 24593, 0, 0 },
299 { 102, 17, 1, 0, 24594, 0, 0 },
300 { 119, 17, 1, 0, 24595, 0, 0 },
301 { 138, 17, 1, 0, 24596, 0, 0 },
302 { 152, 17, 1, 0, 24597, 0, 0 },
303 { 171, 17, 1, 0, 24598, 0, 0 },
304 { 7, 17, 1, 0, 24599, 0, 0 },
305 { 33, 17, 1, 0, 24600, 0, 0 },
306 { 54, 17, 1, 0, 24601, 0, 0 },
307 { 73, 17, 1, 0, 24602, 0, 0 },
308 { 90, 17, 1, 0, 24603, 0, 0 },
309 { 109, 17, 1, 0, 24604, 0, 0 },
310 { 126, 17, 1, 0, 24605, 0, 0 },
311 { 159, 20, 1, 0, 24607, 0, 0 },
312 { 14, 23, 1, 0, 24609, 0, 0 },
313};
314
315extern const MCPhysReg AVRRegUnitRoots[][2] = {
316 { AVR::SPL },
317 { AVR::SPH },
318 { AVR::SREG },
319 { AVR::R0 },
320 { AVR::R1 },
321 { AVR::R2 },
322 { AVR::R3 },
323 { AVR::R4 },
324 { AVR::R5 },
325 { AVR::R6 },
326 { AVR::R7 },
327 { AVR::R8 },
328 { AVR::R9 },
329 { AVR::R10 },
330 { AVR::R11 },
331 { AVR::R12 },
332 { AVR::R13 },
333 { AVR::R14 },
334 { AVR::R15 },
335 { AVR::R16 },
336 { AVR::R17 },
337 { AVR::R18 },
338 { AVR::R19 },
339 { AVR::R20 },
340 { AVR::R21 },
341 { AVR::R22 },
342 { AVR::R23 },
343 { AVR::R24 },
344 { AVR::R25 },
345 { AVR::R26 },
346 { AVR::R27 },
347 { AVR::R28 },
348 { AVR::R29 },
349 { AVR::R30 },
350 { AVR::R31 },
351};
352
353namespace { // Register classes...
354 // GPR8 Register Class...
355 const MCPhysReg GPR8[] = {
356 AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
357 };
358
359 // GPR8 Bit set.
360 const uint8_t GPR8Bits[] = {
361 0xe0, 0xff, 0xff, 0xff, 0x1f,
362 };
363
364 // GPR8lo Register Class...
365 const MCPhysReg GPR8lo[] = {
366 AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1,
367 };
368
369 // GPR8lo Bit set.
370 const uint8_t GPR8loBits[] = {
371 0xe0, 0xff, 0x1f,
372 };
373
374 // LD8 Register Class...
375 const MCPhysReg LD8[] = {
376 AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16,
377 };
378
379 // LD8 Bit set.
380 const uint8_t LD8Bits[] = {
381 0x00, 0x00, 0xe0, 0xff, 0x1f,
382 };
383
384 // LD8lo Register Class...
385 const MCPhysReg LD8lo[] = {
386 AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16,
387 };
388
389 // LD8lo Bit set.
390 const uint8_t LD8loBits[] = {
391 0x00, 0x00, 0xe0, 0x1f,
392 };
393
394 // CCR Register Class...
395 const MCPhysReg CCR[] = {
396 AVR::SREG,
397 };
398
399 // CCR Bit set.
400 const uint8_t CCRBits[] = {
401 0x10,
402 };
403
404 // DREGS Register Class...
405 const MCPhysReg DREGS[] = {
406 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
407 };
408
409 // DREGS Bit set.
410 const uint8_t DREGSBits[] = {
411 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0x3f,
412 };
413
414 // DREGSMOVW Register Class...
415 const MCPhysReg DREGSMOVW[] = {
416 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
417 };
418
419 // DREGSMOVW Bit set.
420 const uint8_t DREGSMOVWBits[] = {
421 0x00, 0x00, 0x00, 0x00, 0xe0, 0xab, 0xaa, 0x3a,
422 };
423
424 // DREGS_with_sub_hi_in_LD8 Register Class...
425 const MCPhysReg DREGS_with_sub_hi_in_LD8[] = {
426 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
427 };
428
429 // DREGS_with_sub_hi_in_LD8 Bit set.
430 const uint8_t DREGS_with_sub_hi_in_LD8Bits[] = {
431 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f,
432 };
433
434 // DREGS_with_sub_lo_in_LD8 Register Class...
435 const MCPhysReg DREGS_with_sub_lo_in_LD8[] = {
436 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
437 };
438
439 // DREGS_with_sub_lo_in_LD8 Bit set.
440 const uint8_t DREGS_with_sub_lo_in_LD8Bits[] = {
441 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
442 };
443
444 // DREGS_with_sub_lo_in_GPR8lo Register Class...
445 const MCPhysReg DREGS_with_sub_lo_in_GPR8lo[] = {
446 AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9,
447 };
448
449 // DREGS_with_sub_lo_in_GPR8lo Bit set.
450 const uint8_t DREGS_with_sub_lo_in_GPR8loBits[] = {
451 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x01,
452 };
453
454 // DREGS_with_sub_hi_in_GPR8lo Register Class...
455 const MCPhysReg DREGS_with_sub_hi_in_GPR8lo[] = {
456 AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R14R13, AVR::R12R11, AVR::R10R9,
457 };
458
459 // DREGS_with_sub_hi_in_GPR8lo Bit set.
460 const uint8_t DREGS_with_sub_hi_in_GPR8loBits[] = {
461 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff,
462 };
463
464 // DLDREGS Register Class...
465 const MCPhysReg DLDREGS[] = {
466 AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16,
467 };
468
469 // DLDREGS Bit set.
470 const uint8_t DLDREGSBits[] = {
471 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x3a,
472 };
473
474 // DREGS_with_sub_hi_in_LD8lo Register Class...
475 const MCPhysReg DREGS_with_sub_hi_in_LD8lo[] = {
476 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15,
477 };
478
479 // DREGS_with_sub_hi_in_LD8lo Bit set.
480 const uint8_t DREGS_with_sub_hi_in_LD8loBits[] = {
481 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
482 };
483
484 // DREGS_with_sub_lo_in_LD8lo Register Class...
485 const MCPhysReg DREGS_with_sub_lo_in_LD8lo[] = {
486 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17,
487 };
488
489 // DREGS_with_sub_lo_in_LD8lo Bit set.
490 const uint8_t DREGS_with_sub_lo_in_LD8loBits[] = {
491 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
492 };
493
494 // DREGSlo Register Class...
495 const MCPhysReg DREGSlo[] = {
496 AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0,
497 };
498
499 // DREGSlo Bit set.
500 const uint8_t DREGSloBits[] = {
501 0x00, 0x00, 0x00, 0x00, 0xe0, 0xab,
502 };
503
504 // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8 Register Class...
505 const MCPhysReg DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8[] = {
506 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17,
507 };
508
509 // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8 Bit set.
510 const uint8_t DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits[] = {
511 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
512 };
513
514 // DREGSLD8lo Register Class...
515 const MCPhysReg DREGSLD8lo[] = {
516 AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16,
517 };
518
519 // DREGSLD8lo Bit set.
520 const uint8_t DREGSLD8loBits[] = {
521 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa,
522 };
523
524 // IWREGS Register Class...
525 const MCPhysReg IWREGS[] = {
526 AVR::R25R24, AVR::R31R30, AVR::R27R26, AVR::R29R28,
527 };
528
529 // IWREGS Bit set.
530 const uint8_t IWREGSBits[] = {
531 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3a,
532 };
533
534 // PTRREGS Register Class...
535 const MCPhysReg PTRREGS[] = {
536 AVR::R27R26, AVR::R29R28, AVR::R31R30,
537 };
538
539 // PTRREGS Bit set.
540 const uint8_t PTRREGSBits[] = {
541 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
542 };
543
544 // PTRDISPREGS Register Class...
545 const MCPhysReg PTRDISPREGS[] = {
546 AVR::R31R30, AVR::R29R28,
547 };
548
549 // PTRDISPREGS Bit set.
550 const uint8_t PTRDISPREGSBits[] = {
551 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
552 };
553
554 // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo Register Class...
555 const MCPhysReg DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo[] = {
556 AVR::R16R15,
557 };
558
559 // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo Bit set.
560 const uint8_t DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits[] = {
561 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
562 };
563
564 // GPRSP Register Class...
565 const MCPhysReg GPRSP[] = {
566 AVR::SP,
567 };
568
569 // GPRSP Bit set.
570 const uint8_t GPRSPBits[] = {
571 0x02,
572 };
573
574 // ZREG Register Class...
575 const MCPhysReg ZREG[] = {
576 AVR::R31R30,
577 };
578
579 // ZREG Bit set.
580 const uint8_t ZREGBits[] = {
581 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
582 };
583
584} // end anonymous namespace
585
586
587#ifdef __GNUC__
588#pragma GCC diagnostic push
589#pragma GCC diagnostic ignored "-Woverlength-strings"
590#endif
591extern const char AVRRegClassStrings[] = {
592 /* 0 */ "DREGS_with_sub_hi_in_LD8\0"
593 /* 25 */ "DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8\0"
594 /* 81 */ "GPR8\0"
595 /* 86 */ "ZREG\0"
596 /* 91 */ "GPRSP\0"
597 /* 97 */ "CCR\0"
598 /* 101 */ "DLDREGS\0"
599 /* 109 */ "PTRDISPREGS\0"
600 /* 121 */ "PTRREGS\0"
601 /* 129 */ "IWREGS\0"
602 /* 136 */ "DREGSMOVW\0"
603 /* 146 */ "DREGSLD8lo\0"
604 /* 157 */ "DREGS_with_sub_hi_in_LD8lo\0"
605 /* 184 */ "DREGS_with_sub_lo_in_LD8lo\0"
606 /* 211 */ "DREGS_with_sub_hi_in_GPR8lo\0"
607 /* 239 */ "DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo\0"
608 /* 296 */ "DREGSlo\0"
609};
610#ifdef __GNUC__
611#pragma GCC diagnostic pop
612#endif
613
614extern const MCRegisterClass AVRMCRegisterClasses[] = {
615 { GPR8, GPR8Bits, 81, 32, sizeof(GPR8Bits), AVR::GPR8RegClassID, 8, 1, true, false },
616 { GPR8lo, GPR8loBits, 232, 16, sizeof(GPR8loBits), AVR::GPR8loRegClassID, 8, 1, true, false },
617 { LD8, LD8Bits, 21, 16, sizeof(LD8Bits), AVR::LD8RegClassID, 8, 1, true, false },
618 { LD8lo, LD8loBits, 151, 8, sizeof(LD8loBits), AVR::LD8loRegClassID, 8, 1, true, false },
619 { CCR, CCRBits, 97, 1, sizeof(CCRBits), AVR::CCRRegClassID, 8, -1, true, false },
620 { DREGS, DREGSBits, 103, 25, sizeof(DREGSBits), AVR::DREGSRegClassID, 16, 1, true, false },
621 { DREGSMOVW, DREGSMOVWBits, 136, 16, sizeof(DREGSMOVWBits), AVR::DREGSMOVWRegClassID, 16, 1, true, false },
622 { DREGS_with_sub_hi_in_LD8, DREGS_with_sub_hi_in_LD8Bits, 0, 14, sizeof(DREGS_with_sub_hi_in_LD8Bits), AVR::DREGS_with_sub_hi_in_LD8RegClassID, 16, 1, true, false },
623 { DREGS_with_sub_lo_in_LD8, DREGS_with_sub_lo_in_LD8Bits, 56, 13, sizeof(DREGS_with_sub_lo_in_LD8Bits), AVR::DREGS_with_sub_lo_in_LD8RegClassID, 16, 1, true, false },
624 { DREGS_with_sub_lo_in_GPR8lo, DREGS_with_sub_lo_in_GPR8loBits, 268, 12, sizeof(DREGS_with_sub_lo_in_GPR8loBits), AVR::DREGS_with_sub_lo_in_GPR8loRegClassID, 16, 1, true, false },
625 { DREGS_with_sub_hi_in_GPR8lo, DREGS_with_sub_hi_in_GPR8loBits, 211, 11, sizeof(DREGS_with_sub_hi_in_GPR8loBits), AVR::DREGS_with_sub_hi_in_GPR8loRegClassID, 16, 1, true, false },
626 { DLDREGS, DLDREGSBits, 101, 8, sizeof(DLDREGSBits), AVR::DLDREGSRegClassID, 16, 1, true, false },
627 { DREGS_with_sub_hi_in_LD8lo, DREGS_with_sub_hi_in_LD8loBits, 157, 8, sizeof(DREGS_with_sub_hi_in_LD8loBits), AVR::DREGS_with_sub_hi_in_LD8loRegClassID, 16, 1, true, false },
628 { DREGS_with_sub_lo_in_LD8lo, DREGS_with_sub_lo_in_LD8loBits, 184, 8, sizeof(DREGS_with_sub_lo_in_LD8loBits), AVR::DREGS_with_sub_lo_in_LD8loRegClassID, 16, 1, true, false },
629 { DREGSlo, DREGSloBits, 296, 8, sizeof(DREGSloBits), AVR::DREGSloRegClassID, 16, 1, true, false },
630 { DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8, DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits, 25, 7, sizeof(DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits), AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID, 16, 1, true, false },
631 { DREGSLD8lo, DREGSLD8loBits, 146, 4, sizeof(DREGSLD8loBits), AVR::DREGSLD8loRegClassID, 16, 1, true, false },
632 { IWREGS, IWREGSBits, 129, 4, sizeof(IWREGSBits), AVR::IWREGSRegClassID, 16, 1, true, false },
633 { PTRREGS, PTRREGSBits, 121, 3, sizeof(PTRREGSBits), AVR::PTRREGSRegClassID, 16, 1, true, false },
634 { PTRDISPREGS, PTRDISPREGSBits, 109, 2, sizeof(PTRDISPREGSBits), AVR::PTRDISPREGSRegClassID, 16, 1, true, false },
635 { DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo, DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits, 239, 1, sizeof(DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits), AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID, 16, 1, true, false },
636 { GPRSP, GPRSPBits, 91, 1, sizeof(GPRSPBits), AVR::GPRSPRegClassID, 16, 1, true, false },
637 { ZREG, ZREGBits, 86, 1, sizeof(ZREGBits), AVR::ZREGRegClassID, 16, 1, true, false },
638};
639
640// AVR Dwarf<->LLVM register mappings.
641extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[] = {
642 { 0U, AVR::R1R0 },
643 { 1U, AVR::R1 },
644 { 2U, AVR::R3R2 },
645 { 3U, AVR::R3 },
646 { 4U, AVR::R5R4 },
647 { 5U, AVR::R5 },
648 { 6U, AVR::R7R6 },
649 { 7U, AVR::R7 },
650 { 8U, AVR::R9R8 },
651 { 9U, AVR::R10R9 },
652 { 10U, AVR::R11R10 },
653 { 11U, AVR::R12R11 },
654 { 12U, AVR::R13R12 },
655 { 13U, AVR::R14R13 },
656 { 14U, AVR::R15R14 },
657 { 15U, AVR::R16R15 },
658 { 16U, AVR::R17R16 },
659 { 17U, AVR::R18R17 },
660 { 18U, AVR::R19R18 },
661 { 19U, AVR::R20R19 },
662 { 20U, AVR::R21R20 },
663 { 21U, AVR::R22R21 },
664 { 22U, AVR::R23R22 },
665 { 23U, AVR::R24R23 },
666 { 24U, AVR::R25R24 },
667 { 25U, AVR::R26R25 },
668 { 26U, AVR::R27R26 },
669 { 27U, AVR::R27 },
670 { 28U, AVR::R29R28 },
671 { 29U, AVR::R29 },
672 { 30U, AVR::R31R30 },
673 { 31U, AVR::R31 },
674 { 32U, AVR::SPL },
675 { 33U, AVR::SPH },
676 { 88U, AVR::SREG },
677};
678extern const unsigned AVRDwarfFlavour0Dwarf2LSize = std::size(AVRDwarfFlavour0Dwarf2L);
679
680extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[] = {
681 { 0U, AVR::R1R0 },
682 { 1U, AVR::R1 },
683 { 2U, AVR::R3R2 },
684 { 3U, AVR::R3 },
685 { 4U, AVR::R5R4 },
686 { 5U, AVR::R5 },
687 { 6U, AVR::R7R6 },
688 { 7U, AVR::R7 },
689 { 8U, AVR::R9R8 },
690 { 9U, AVR::R10R9 },
691 { 10U, AVR::R11R10 },
692 { 11U, AVR::R12R11 },
693 { 12U, AVR::R13R12 },
694 { 13U, AVR::R14R13 },
695 { 14U, AVR::R15R14 },
696 { 15U, AVR::R16R15 },
697 { 16U, AVR::R17R16 },
698 { 17U, AVR::R18R17 },
699 { 18U, AVR::R19R18 },
700 { 19U, AVR::R20R19 },
701 { 20U, AVR::R21R20 },
702 { 21U, AVR::R22R21 },
703 { 22U, AVR::R23R22 },
704 { 23U, AVR::R24R23 },
705 { 24U, AVR::R25R24 },
706 { 25U, AVR::R26R25 },
707 { 26U, AVR::R27R26 },
708 { 27U, AVR::R27 },
709 { 28U, AVR::R29R28 },
710 { 29U, AVR::R29 },
711 { 30U, AVR::R31R30 },
712 { 31U, AVR::R31 },
713 { 32U, AVR::SPL },
714 { 33U, AVR::SPH },
715 { 88U, AVR::SREG },
716};
717extern const unsigned AVREHFlavour0Dwarf2LSize = std::size(AVREHFlavour0Dwarf2L);
718
719extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[] = {
720 { AVR::SP, 32U },
721 { AVR::SPH, 33U },
722 { AVR::SPL, 32U },
723 { AVR::SREG, 88U },
724 { AVR::R0, 0U },
725 { AVR::R1, 1U },
726 { AVR::R2, 2U },
727 { AVR::R3, 3U },
728 { AVR::R4, 4U },
729 { AVR::R5, 5U },
730 { AVR::R6, 6U },
731 { AVR::R7, 7U },
732 { AVR::R8, 8U },
733 { AVR::R9, 9U },
734 { AVR::R10, 10U },
735 { AVR::R11, 11U },
736 { AVR::R12, 12U },
737 { AVR::R13, 13U },
738 { AVR::R14, 14U },
739 { AVR::R15, 15U },
740 { AVR::R16, 16U },
741 { AVR::R17, 17U },
742 { AVR::R18, 18U },
743 { AVR::R19, 19U },
744 { AVR::R20, 20U },
745 { AVR::R21, 21U },
746 { AVR::R22, 22U },
747 { AVR::R23, 23U },
748 { AVR::R24, 24U },
749 { AVR::R25, 25U },
750 { AVR::R26, 26U },
751 { AVR::R27, 27U },
752 { AVR::R28, 28U },
753 { AVR::R29, 29U },
754 { AVR::R30, 30U },
755 { AVR::R31, 31U },
756 { AVR::R1R0, 0U },
757 { AVR::R3R2, 2U },
758 { AVR::R5R4, 4U },
759 { AVR::R7R6, 6U },
760 { AVR::R9R8, 8U },
761 { AVR::R10R9, 9U },
762 { AVR::R11R10, 10U },
763 { AVR::R12R11, 11U },
764 { AVR::R13R12, 12U },
765 { AVR::R14R13, 13U },
766 { AVR::R15R14, 14U },
767 { AVR::R16R15, 15U },
768 { AVR::R17R16, 16U },
769 { AVR::R18R17, 17U },
770 { AVR::R19R18, 18U },
771 { AVR::R20R19, 19U },
772 { AVR::R21R20, 20U },
773 { AVR::R22R21, 21U },
774 { AVR::R23R22, 22U },
775 { AVR::R24R23, 23U },
776 { AVR::R25R24, 24U },
777 { AVR::R26R25, 25U },
778 { AVR::R27R26, 26U },
779 { AVR::R29R28, 28U },
780 { AVR::R31R30, 30U },
781};
782extern const unsigned AVRDwarfFlavour0L2DwarfSize = std::size(AVRDwarfFlavour0L2Dwarf);
783
784extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[] = {
785 { AVR::SP, 32U },
786 { AVR::SPH, 33U },
787 { AVR::SPL, 32U },
788 { AVR::SREG, 88U },
789 { AVR::R0, 0U },
790 { AVR::R1, 1U },
791 { AVR::R2, 2U },
792 { AVR::R3, 3U },
793 { AVR::R4, 4U },
794 { AVR::R5, 5U },
795 { AVR::R6, 6U },
796 { AVR::R7, 7U },
797 { AVR::R8, 8U },
798 { AVR::R9, 9U },
799 { AVR::R10, 10U },
800 { AVR::R11, 11U },
801 { AVR::R12, 12U },
802 { AVR::R13, 13U },
803 { AVR::R14, 14U },
804 { AVR::R15, 15U },
805 { AVR::R16, 16U },
806 { AVR::R17, 17U },
807 { AVR::R18, 18U },
808 { AVR::R19, 19U },
809 { AVR::R20, 20U },
810 { AVR::R21, 21U },
811 { AVR::R22, 22U },
812 { AVR::R23, 23U },
813 { AVR::R24, 24U },
814 { AVR::R25, 25U },
815 { AVR::R26, 26U },
816 { AVR::R27, 27U },
817 { AVR::R28, 28U },
818 { AVR::R29, 29U },
819 { AVR::R30, 30U },
820 { AVR::R31, 31U },
821 { AVR::R1R0, 0U },
822 { AVR::R3R2, 2U },
823 { AVR::R5R4, 4U },
824 { AVR::R7R6, 6U },
825 { AVR::R9R8, 8U },
826 { AVR::R10R9, 9U },
827 { AVR::R11R10, 10U },
828 { AVR::R12R11, 11U },
829 { AVR::R13R12, 12U },
830 { AVR::R14R13, 13U },
831 { AVR::R15R14, 14U },
832 { AVR::R16R15, 15U },
833 { AVR::R17R16, 16U },
834 { AVR::R18R17, 17U },
835 { AVR::R19R18, 18U },
836 { AVR::R20R19, 19U },
837 { AVR::R21R20, 20U },
838 { AVR::R22R21, 21U },
839 { AVR::R23R22, 22U },
840 { AVR::R24R23, 23U },
841 { AVR::R25R24, 24U },
842 { AVR::R26R25, 25U },
843 { AVR::R27R26, 26U },
844 { AVR::R29R28, 28U },
845 { AVR::R31R30, 30U },
846};
847extern const unsigned AVREHFlavour0L2DwarfSize = std::size(AVREHFlavour0L2Dwarf);
848
849extern const uint16_t AVRRegEncodingTable[] = {
850 0,
851 32,
852 33,
853 32,
854 14,
855 0,
856 1,
857 2,
858 3,
859 4,
860 5,
861 6,
862 7,
863 8,
864 9,
865 10,
866 11,
867 12,
868 13,
869 14,
870 15,
871 16,
872 17,
873 18,
874 19,
875 20,
876 21,
877 22,
878 23,
879 24,
880 25,
881 26,
882 27,
883 28,
884 29,
885 30,
886 31,
887 0,
888 2,
889 4,
890 6,
891 8,
892 9,
893 10,
894 11,
895 12,
896 13,
897 14,
898 15,
899 16,
900 17,
901 18,
902 19,
903 20,
904 21,
905 22,
906 23,
907 24,
908 25,
909 26,
910 28,
911 30,
912};
913static inline void InitAVRMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
914 RI->InitMCRegisterInfo(AVRRegDesc, 62, RA, PC, AVRMCRegisterClasses, 23, AVRRegUnitRoots, 35, AVRRegDiffLists, AVRLaneMaskLists, AVRRegStrings, AVRRegClassStrings, AVRSubRegIdxLists, 3,
915AVRRegEncodingTable);
916
917 switch (DwarfFlavour) {
918 default:
919 llvm_unreachable("Unknown DWARF flavour");
920 case 0:
921 RI->mapDwarfRegsToLLVMRegs(AVRDwarfFlavour0Dwarf2L, AVRDwarfFlavour0Dwarf2LSize, false);
922 break;
923 }
924 switch (EHFlavour) {
925 default:
926 llvm_unreachable("Unknown DWARF flavour");
927 case 0:
928 RI->mapDwarfRegsToLLVMRegs(AVREHFlavour0Dwarf2L, AVREHFlavour0Dwarf2LSize, true);
929 break;
930 }
931 switch (DwarfFlavour) {
932 default:
933 llvm_unreachable("Unknown DWARF flavour");
934 case 0:
935 RI->mapLLVMRegsToDwarfRegs(AVRDwarfFlavour0L2Dwarf, AVRDwarfFlavour0L2DwarfSize, false);
936 break;
937 }
938 switch (EHFlavour) {
939 default:
940 llvm_unreachable("Unknown DWARF flavour");
941 case 0:
942 RI->mapLLVMRegsToDwarfRegs(AVREHFlavour0L2Dwarf, AVREHFlavour0L2DwarfSize, true);
943 break;
944 }
945}
946
947} // end namespace llvm
948
949#endif // GET_REGINFO_MC_DESC
950
951/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
952|* *|
953|* Register Information Header Fragment *|
954|* *|
955|* Automatically generated file, do not edit! *|
956|* *|
957\*===----------------------------------------------------------------------===*/
958
959
960#ifdef GET_REGINFO_HEADER
961#undef GET_REGINFO_HEADER
962
963#include "llvm/CodeGen/TargetRegisterInfo.h"
964
965namespace llvm {
966
967class AVRFrameLowering;
968
969struct AVRGenRegisterInfo : public TargetRegisterInfo {
970 explicit AVRGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
971 unsigned PC = 0, unsigned HwMode = 0);
972 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
973 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
974 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
975 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
976 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
977 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
978 unsigned getRegUnitWeight(unsigned RegUnit) const override;
979 unsigned getNumRegPressureSets() const override;
980 const char *getRegPressureSetName(unsigned Idx) const override;
981 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
982 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
983 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
984 ArrayRef<const char *> getRegMaskNames() const override;
985 ArrayRef<const uint32_t *> getRegMasks() const override;
986 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
987 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
988 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
989 bool isConstantPhysReg(MCRegister PhysReg) const override final;
990 /// Devirtualized TargetFrameLowering.
991 static const AVRFrameLowering *getFrameLowering(
992 const MachineFunction &MF);
993};
994
995namespace AVR { // Register classes
996 extern const TargetRegisterClass GPR8RegClass;
997 extern const TargetRegisterClass GPR8loRegClass;
998 extern const TargetRegisterClass LD8RegClass;
999 extern const TargetRegisterClass LD8loRegClass;
1000 extern const TargetRegisterClass CCRRegClass;
1001 extern const TargetRegisterClass DREGSRegClass;
1002 extern const TargetRegisterClass DREGSMOVWRegClass;
1003 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8RegClass;
1004 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8RegClass;
1005 extern const TargetRegisterClass DREGS_with_sub_lo_in_GPR8loRegClass;
1006 extern const TargetRegisterClass DREGS_with_sub_hi_in_GPR8loRegClass;
1007 extern const TargetRegisterClass DLDREGSRegClass;
1008 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8loRegClass;
1009 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8loRegClass;
1010 extern const TargetRegisterClass DREGSloRegClass;
1011 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClass;
1012 extern const TargetRegisterClass DREGSLD8loRegClass;
1013 extern const TargetRegisterClass IWREGSRegClass;
1014 extern const TargetRegisterClass PTRREGSRegClass;
1015 extern const TargetRegisterClass PTRDISPREGSRegClass;
1016 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClass;
1017 extern const TargetRegisterClass GPRSPRegClass;
1018 extern const TargetRegisterClass ZREGRegClass;
1019} // end namespace AVR
1020
1021} // end namespace llvm
1022
1023#endif // GET_REGINFO_HEADER
1024
1025/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1026|* *|
1027|* Target Register and Register Classes Information *|
1028|* *|
1029|* Automatically generated file, do not edit! *|
1030|* *|
1031\*===----------------------------------------------------------------------===*/
1032
1033
1034#ifdef GET_REGINFO_TARGET_DESC
1035#undef GET_REGINFO_TARGET_DESC
1036
1037namespace llvm {
1038
1039extern const MCRegisterClass AVRMCRegisterClasses[];
1040
1041static const MVT::SimpleValueType VTLists[] = {
1042 /* 0 */ MVT::i8, MVT::Other,
1043 /* 2 */ MVT::i16, MVT::Other,
1044};
1045
1046static const char *SubRegIndexNameTable[] = { "sub_hi", "sub_lo", "" };
1047
1048static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
1049 { 65535, 65535 },
1050 { 8, 8 }, // sub_hi
1051 { 0, 8 }, // sub_lo
1052};
1053
1054
1055static const LaneBitmask SubRegIndexLaneMaskTable[] = {
1056 LaneBitmask::getAll(),
1057 LaneBitmask(0x0000000000000001), // sub_hi
1058 LaneBitmask(0x0000000000000002), // sub_lo
1059 };
1060
1061
1062
1063static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
1064 // Mode = 0 (Default)
1065 { 8, 8, 8, /*VTLists+*/0 }, // GPR8
1066 { 8, 8, 8, /*VTLists+*/0 }, // GPR8lo
1067 { 8, 8, 8, /*VTLists+*/0 }, // LD8
1068 { 8, 8, 8, /*VTLists+*/0 }, // LD8lo
1069 { 8, 8, 8, /*VTLists+*/0 }, // CCR
1070 { 16, 16, 8, /*VTLists+*/2 }, // DREGS
1071 { 16, 16, 8, /*VTLists+*/2 }, // DREGSMOVW
1072 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_hi_in_LD8
1073 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_lo_in_LD8
1074 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_lo_in_GPR8lo
1075 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_hi_in_GPR8lo
1076 { 16, 16, 8, /*VTLists+*/2 }, // DLDREGS
1077 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_hi_in_LD8lo
1078 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_lo_in_LD8lo
1079 { 16, 16, 8, /*VTLists+*/2 }, // DREGSlo
1080 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1081 { 16, 16, 8, /*VTLists+*/2 }, // DREGSLD8lo
1082 { 16, 16, 8, /*VTLists+*/2 }, // IWREGS
1083 { 16, 16, 8, /*VTLists+*/2 }, // PTRREGS
1084 { 16, 16, 8, /*VTLists+*/2 }, // PTRDISPREGS
1085 { 16, 16, 8, /*VTLists+*/2 }, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1086 { 16, 16, 8, /*VTLists+*/2 }, // GPRSP
1087 { 16, 16, 8, /*VTLists+*/2 }, // ZREG
1088};
1089
1090static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
1091
1092static const uint32_t GPR8SubClassMask[] = {
1093 0x0000000f,
1094 0x005fffe0, // sub_hi
1095 0x005fffe0, // sub_lo
1096};
1097
1098static const uint32_t GPR8loSubClassMask[] = {
1099 0x00000002,
1100 0x00004400, // sub_hi
1101 0x00104600, // sub_lo
1102};
1103
1104static const uint32_t LD8SubClassMask[] = {
1105 0x0000000c,
1106 0x005fb980, // sub_hi
1107 0x004fa900, // sub_lo
1108};
1109
1110static const uint32_t LD8loSubClassMask[] = {
1111 0x00000008,
1112 0x00119000, // sub_hi
1113 0x0001a000, // sub_lo
1114};
1115
1116static const uint32_t CCRSubClassMask[] = {
1117 0x00000010,
1118};
1119
1120static const uint32_t DREGSSubClassMask[] = {
1121 0x005fffe0,
1122};
1123
1124static const uint32_t DREGSMOVWSubClassMask[] = {
1125 0x004f4840,
1126};
1127
1128static const uint32_t DREGS_with_sub_hi_in_LD8SubClassMask[] = {
1129 0x005fb980,
1130};
1131
1132static const uint32_t DREGS_with_sub_lo_in_LD8SubClassMask[] = {
1133 0x004fa900,
1134};
1135
1136static const uint32_t DREGS_with_sub_lo_in_GPR8loSubClassMask[] = {
1137 0x00104600,
1138};
1139
1140static const uint32_t DREGS_with_sub_hi_in_GPR8loSubClassMask[] = {
1141 0x00004400,
1142};
1143
1144static const uint32_t DLDREGSSubClassMask[] = {
1145 0x004f0800,
1146};
1147
1148static const uint32_t DREGS_with_sub_hi_in_LD8loSubClassMask[] = {
1149 0x00119000,
1150};
1151
1152static const uint32_t DREGS_with_sub_lo_in_LD8loSubClassMask[] = {
1153 0x0001a000,
1154};
1155
1156static const uint32_t DREGSloSubClassMask[] = {
1157 0x00004000,
1158};
1159
1160static const uint32_t DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8SubClassMask[] = {
1161 0x00018000,
1162};
1163
1164static const uint32_t DREGSLD8loSubClassMask[] = {
1165 0x00010000,
1166};
1167
1168static const uint32_t IWREGSSubClassMask[] = {
1169 0x004e0000,
1170};
1171
1172static const uint32_t PTRREGSSubClassMask[] = {
1173 0x004c0000,
1174};
1175
1176static const uint32_t PTRDISPREGSSubClassMask[] = {
1177 0x00480000,
1178};
1179
1180static const uint32_t DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSubClassMask[] = {
1181 0x00100000,
1182};
1183
1184static const uint32_t GPRSPSubClassMask[] = {
1185 0x00200000,
1186};
1187
1188static const uint32_t ZREGSubClassMask[] = {
1189 0x00400000,
1190};
1191
1192static const uint16_t SuperRegIdxSeqs[] = {
1193 /* 0 */ 1, 2, 0,
1194};
1195
1196static const TargetRegisterClass *const GPR8loSuperclasses[] = {
1197 &AVR::GPR8RegClass,
1198 nullptr
1199};
1200
1201static const TargetRegisterClass *const LD8Superclasses[] = {
1202 &AVR::GPR8RegClass,
1203 nullptr
1204};
1205
1206static const TargetRegisterClass *const LD8loSuperclasses[] = {
1207 &AVR::GPR8RegClass,
1208 &AVR::LD8RegClass,
1209 nullptr
1210};
1211
1212static const TargetRegisterClass *const DREGSMOVWSuperclasses[] = {
1213 &AVR::DREGSRegClass,
1214 nullptr
1215};
1216
1217static const TargetRegisterClass *const DREGS_with_sub_hi_in_LD8Superclasses[] = {
1218 &AVR::DREGSRegClass,
1219 nullptr
1220};
1221
1222static const TargetRegisterClass *const DREGS_with_sub_lo_in_LD8Superclasses[] = {
1223 &AVR::DREGSRegClass,
1224 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
1225 nullptr
1226};
1227
1228static const TargetRegisterClass *const DREGS_with_sub_lo_in_GPR8loSuperclasses[] = {
1229 &AVR::DREGSRegClass,
1230 nullptr
1231};
1232
1233static const TargetRegisterClass *const DREGS_with_sub_hi_in_GPR8loSuperclasses[] = {
1234 &AVR::DREGSRegClass,
1235 &AVR::DREGS_with_sub_lo_in_GPR8loRegClass,
1236 nullptr
1237};
1238
1239static const TargetRegisterClass *const DLDREGSSuperclasses[] = {
1240 &AVR::DREGSRegClass,
1241 &AVR::DREGSMOVWRegClass,
1242 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
1243 &AVR::DREGS_with_sub_lo_in_LD8RegClass,
1244 nullptr
1245};
1246
1247static const TargetRegisterClass *const DREGS_with_sub_hi_in_LD8loSuperclasses[] = {
1248 &AVR::DREGSRegClass,
1249 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
1250 nullptr
1251};
1252
1253static const TargetRegisterClass *const DREGS_with_sub_lo_in_LD8loSuperclasses[] = {
1254 &AVR::DREGSRegClass,
1255 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
1256 &AVR::DREGS_with_sub_lo_in_LD8RegClass,
1257 nullptr
1258};
1259
1260static const TargetRegisterClass *const DREGSloSuperclasses[] = {
1261 &AVR::DREGSRegClass,
1262 &AVR::DREGSMOVWRegClass,
1263 &AVR::DREGS_with_sub_lo_in_GPR8loRegClass,
1264 &AVR::DREGS_with_sub_hi_in_GPR8loRegClass,
1265 nullptr
1266};
1267
1268static const TargetRegisterClass *const DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Superclasses[] = {
1269 &AVR::DREGSRegClass,
1270 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
1271 &AVR::DREGS_with_sub_lo_in_LD8RegClass,
1272 &AVR::DREGS_with_sub_hi_in_LD8loRegClass,
1273 &AVR::DREGS_with_sub_lo_in_LD8loRegClass,
1274 nullptr
1275};
1276
1277static const TargetRegisterClass *const DREGSLD8loSuperclasses[] = {
1278 &AVR::DREGSRegClass,
1279 &AVR::DREGSMOVWRegClass,
1280 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
1281 &AVR::DREGS_with_sub_lo_in_LD8RegClass,
1282 &AVR::DLDREGSRegClass,
1283 &AVR::DREGS_with_sub_hi_in_LD8loRegClass,
1284 &AVR::DREGS_with_sub_lo_in_LD8loRegClass,
1285 &AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClass,
1286 nullptr
1287};
1288
1289static const TargetRegisterClass *const IWREGSSuperclasses[] = {
1290 &AVR::DREGSRegClass,
1291 &AVR::DREGSMOVWRegClass,
1292 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
1293 &AVR::DREGS_with_sub_lo_in_LD8RegClass,
1294 &AVR::DLDREGSRegClass,
1295 nullptr
1296};
1297
1298static const TargetRegisterClass *const PTRREGSSuperclasses[] = {
1299 &AVR::DREGSRegClass,
1300 &AVR::DREGSMOVWRegClass,
1301 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
1302 &AVR::DREGS_with_sub_lo_in_LD8RegClass,
1303 &AVR::DLDREGSRegClass,
1304 &AVR::IWREGSRegClass,
1305 nullptr
1306};
1307
1308static const TargetRegisterClass *const PTRDISPREGSSuperclasses[] = {
1309 &AVR::DREGSRegClass,
1310 &AVR::DREGSMOVWRegClass,
1311 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
1312 &AVR::DREGS_with_sub_lo_in_LD8RegClass,
1313 &AVR::DLDREGSRegClass,
1314 &AVR::IWREGSRegClass,
1315 &AVR::PTRREGSRegClass,
1316 nullptr
1317};
1318
1319static const TargetRegisterClass *const DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSuperclasses[] = {
1320 &AVR::DREGSRegClass,
1321 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
1322 &AVR::DREGS_with_sub_lo_in_GPR8loRegClass,
1323 &AVR::DREGS_with_sub_hi_in_LD8loRegClass,
1324 nullptr
1325};
1326
1327static const TargetRegisterClass *const ZREGSuperclasses[] = {
1328 &AVR::DREGSRegClass,
1329 &AVR::DREGSMOVWRegClass,
1330 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
1331 &AVR::DREGS_with_sub_lo_in_LD8RegClass,
1332 &AVR::DLDREGSRegClass,
1333 &AVR::IWREGSRegClass,
1334 &AVR::PTRREGSRegClass,
1335 &AVR::PTRDISPREGSRegClass,
1336 nullptr
1337};
1338
1339
1340namespace AVR { // Register class instances
1341 extern const TargetRegisterClass GPR8RegClass = {
1342 &AVRMCRegisterClasses[GPR8RegClassID],
1343 GPR8SubClassMask,
1344 SuperRegIdxSeqs + 0,
1345 LaneBitmask(0x0000000000000001),
1346 0,
1347 false,
1348 0x00, /* TSFlags */
1349 false, /* HasDisjunctSubRegs */
1350 false, /* CoveredBySubRegs */
1351 NullRegClasses,
1352 nullptr
1353 };
1354
1355 extern const TargetRegisterClass GPR8loRegClass = {
1356 &AVRMCRegisterClasses[GPR8loRegClassID],
1357 GPR8loSubClassMask,
1358 SuperRegIdxSeqs + 0,
1359 LaneBitmask(0x0000000000000001),
1360 0,
1361 false,
1362 0x00, /* TSFlags */
1363 false, /* HasDisjunctSubRegs */
1364 false, /* CoveredBySubRegs */
1365 GPR8loSuperclasses,
1366 nullptr
1367 };
1368
1369 extern const TargetRegisterClass LD8RegClass = {
1370 &AVRMCRegisterClasses[LD8RegClassID],
1371 LD8SubClassMask,
1372 SuperRegIdxSeqs + 0,
1373 LaneBitmask(0x0000000000000001),
1374 0,
1375 false,
1376 0x00, /* TSFlags */
1377 false, /* HasDisjunctSubRegs */
1378 false, /* CoveredBySubRegs */
1379 LD8Superclasses,
1380 nullptr
1381 };
1382
1383 extern const TargetRegisterClass LD8loRegClass = {
1384 &AVRMCRegisterClasses[LD8loRegClassID],
1385 LD8loSubClassMask,
1386 SuperRegIdxSeqs + 0,
1387 LaneBitmask(0x0000000000000001),
1388 0,
1389 false,
1390 0x00, /* TSFlags */
1391 false, /* HasDisjunctSubRegs */
1392 false, /* CoveredBySubRegs */
1393 LD8loSuperclasses,
1394 nullptr
1395 };
1396
1397 extern const TargetRegisterClass CCRRegClass = {
1398 &AVRMCRegisterClasses[CCRRegClassID],
1399 CCRSubClassMask,
1400 SuperRegIdxSeqs + 2,
1401 LaneBitmask(0x0000000000000001),
1402 0,
1403 false,
1404 0x00, /* TSFlags */
1405 false, /* HasDisjunctSubRegs */
1406 false, /* CoveredBySubRegs */
1407 NullRegClasses,
1408 nullptr
1409 };
1410
1411 extern const TargetRegisterClass DREGSRegClass = {
1412 &AVRMCRegisterClasses[DREGSRegClassID],
1413 DREGSSubClassMask,
1414 SuperRegIdxSeqs + 2,
1415 LaneBitmask(0x0000000000000003),
1416 0,
1417 false,
1418 0x00, /* TSFlags */
1419 true, /* HasDisjunctSubRegs */
1420 true, /* CoveredBySubRegs */
1421 NullRegClasses,
1422 nullptr
1423 };
1424
1425 extern const TargetRegisterClass DREGSMOVWRegClass = {
1426 &AVRMCRegisterClasses[DREGSMOVWRegClassID],
1427 DREGSMOVWSubClassMask,
1428 SuperRegIdxSeqs + 2,
1429 LaneBitmask(0x0000000000000003),
1430 0,
1431 false,
1432 0x00, /* TSFlags */
1433 true, /* HasDisjunctSubRegs */
1434 true, /* CoveredBySubRegs */
1435 DREGSMOVWSuperclasses,
1436 nullptr
1437 };
1438
1439 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8RegClass = {
1440 &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8RegClassID],
1441 DREGS_with_sub_hi_in_LD8SubClassMask,
1442 SuperRegIdxSeqs + 2,
1443 LaneBitmask(0x0000000000000003),
1444 0,
1445 false,
1446 0x00, /* TSFlags */
1447 true, /* HasDisjunctSubRegs */
1448 true, /* CoveredBySubRegs */
1449 DREGS_with_sub_hi_in_LD8Superclasses,
1450 nullptr
1451 };
1452
1453 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8RegClass = {
1454 &AVRMCRegisterClasses[DREGS_with_sub_lo_in_LD8RegClassID],
1455 DREGS_with_sub_lo_in_LD8SubClassMask,
1456 SuperRegIdxSeqs + 2,
1457 LaneBitmask(0x0000000000000003),
1458 0,
1459 false,
1460 0x00, /* TSFlags */
1461 true, /* HasDisjunctSubRegs */
1462 true, /* CoveredBySubRegs */
1463 DREGS_with_sub_lo_in_LD8Superclasses,
1464 nullptr
1465 };
1466
1467 extern const TargetRegisterClass DREGS_with_sub_lo_in_GPR8loRegClass = {
1468 &AVRMCRegisterClasses[DREGS_with_sub_lo_in_GPR8loRegClassID],
1469 DREGS_with_sub_lo_in_GPR8loSubClassMask,
1470 SuperRegIdxSeqs + 2,
1471 LaneBitmask(0x0000000000000003),
1472 0,
1473 false,
1474 0x00, /* TSFlags */
1475 true, /* HasDisjunctSubRegs */
1476 true, /* CoveredBySubRegs */
1477 DREGS_with_sub_lo_in_GPR8loSuperclasses,
1478 nullptr
1479 };
1480
1481 extern const TargetRegisterClass DREGS_with_sub_hi_in_GPR8loRegClass = {
1482 &AVRMCRegisterClasses[DREGS_with_sub_hi_in_GPR8loRegClassID],
1483 DREGS_with_sub_hi_in_GPR8loSubClassMask,
1484 SuperRegIdxSeqs + 2,
1485 LaneBitmask(0x0000000000000003),
1486 0,
1487 false,
1488 0x00, /* TSFlags */
1489 true, /* HasDisjunctSubRegs */
1490 true, /* CoveredBySubRegs */
1491 DREGS_with_sub_hi_in_GPR8loSuperclasses,
1492 nullptr
1493 };
1494
1495 extern const TargetRegisterClass DLDREGSRegClass = {
1496 &AVRMCRegisterClasses[DLDREGSRegClassID],
1497 DLDREGSSubClassMask,
1498 SuperRegIdxSeqs + 2,
1499 LaneBitmask(0x0000000000000003),
1500 0,
1501 false,
1502 0x00, /* TSFlags */
1503 true, /* HasDisjunctSubRegs */
1504 true, /* CoveredBySubRegs */
1505 DLDREGSSuperclasses,
1506 nullptr
1507 };
1508
1509 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8loRegClass = {
1510 &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8loRegClassID],
1511 DREGS_with_sub_hi_in_LD8loSubClassMask,
1512 SuperRegIdxSeqs + 2,
1513 LaneBitmask(0x0000000000000003),
1514 0,
1515 false,
1516 0x00, /* TSFlags */
1517 true, /* HasDisjunctSubRegs */
1518 true, /* CoveredBySubRegs */
1519 DREGS_with_sub_hi_in_LD8loSuperclasses,
1520 nullptr
1521 };
1522
1523 extern const TargetRegisterClass DREGS_with_sub_lo_in_LD8loRegClass = {
1524 &AVRMCRegisterClasses[DREGS_with_sub_lo_in_LD8loRegClassID],
1525 DREGS_with_sub_lo_in_LD8loSubClassMask,
1526 SuperRegIdxSeqs + 2,
1527 LaneBitmask(0x0000000000000003),
1528 0,
1529 false,
1530 0x00, /* TSFlags */
1531 true, /* HasDisjunctSubRegs */
1532 true, /* CoveredBySubRegs */
1533 DREGS_with_sub_lo_in_LD8loSuperclasses,
1534 nullptr
1535 };
1536
1537 extern const TargetRegisterClass DREGSloRegClass = {
1538 &AVRMCRegisterClasses[DREGSloRegClassID],
1539 DREGSloSubClassMask,
1540 SuperRegIdxSeqs + 2,
1541 LaneBitmask(0x0000000000000003),
1542 0,
1543 false,
1544 0x00, /* TSFlags */
1545 true, /* HasDisjunctSubRegs */
1546 true, /* CoveredBySubRegs */
1547 DREGSloSuperclasses,
1548 nullptr
1549 };
1550
1551 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClass = {
1552 &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID],
1553 DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8SubClassMask,
1554 SuperRegIdxSeqs + 2,
1555 LaneBitmask(0x0000000000000003),
1556 0,
1557 false,
1558 0x00, /* TSFlags */
1559 true, /* HasDisjunctSubRegs */
1560 true, /* CoveredBySubRegs */
1561 DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Superclasses,
1562 nullptr
1563 };
1564
1565 extern const TargetRegisterClass DREGSLD8loRegClass = {
1566 &AVRMCRegisterClasses[DREGSLD8loRegClassID],
1567 DREGSLD8loSubClassMask,
1568 SuperRegIdxSeqs + 2,
1569 LaneBitmask(0x0000000000000003),
1570 0,
1571 false,
1572 0x00, /* TSFlags */
1573 true, /* HasDisjunctSubRegs */
1574 true, /* CoveredBySubRegs */
1575 DREGSLD8loSuperclasses,
1576 nullptr
1577 };
1578
1579 extern const TargetRegisterClass IWREGSRegClass = {
1580 &AVRMCRegisterClasses[IWREGSRegClassID],
1581 IWREGSSubClassMask,
1582 SuperRegIdxSeqs + 2,
1583 LaneBitmask(0x0000000000000003),
1584 0,
1585 false,
1586 0x00, /* TSFlags */
1587 true, /* HasDisjunctSubRegs */
1588 true, /* CoveredBySubRegs */
1589 IWREGSSuperclasses,
1590 nullptr
1591 };
1592
1593 extern const TargetRegisterClass PTRREGSRegClass = {
1594 &AVRMCRegisterClasses[PTRREGSRegClassID],
1595 PTRREGSSubClassMask,
1596 SuperRegIdxSeqs + 2,
1597 LaneBitmask(0x0000000000000003),
1598 0,
1599 false,
1600 0x00, /* TSFlags */
1601 true, /* HasDisjunctSubRegs */
1602 true, /* CoveredBySubRegs */
1603 PTRREGSSuperclasses,
1604 nullptr
1605 };
1606
1607 extern const TargetRegisterClass PTRDISPREGSRegClass = {
1608 &AVRMCRegisterClasses[PTRDISPREGSRegClassID],
1609 PTRDISPREGSSubClassMask,
1610 SuperRegIdxSeqs + 2,
1611 LaneBitmask(0x0000000000000003),
1612 0,
1613 false,
1614 0x00, /* TSFlags */
1615 true, /* HasDisjunctSubRegs */
1616 true, /* CoveredBySubRegs */
1617 PTRDISPREGSSuperclasses,
1618 nullptr
1619 };
1620
1621 extern const TargetRegisterClass DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClass = {
1622 &AVRMCRegisterClasses[DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID],
1623 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSubClassMask,
1624 SuperRegIdxSeqs + 2,
1625 LaneBitmask(0x0000000000000003),
1626 0,
1627 false,
1628 0x00, /* TSFlags */
1629 true, /* HasDisjunctSubRegs */
1630 true, /* CoveredBySubRegs */
1631 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loSuperclasses,
1632 nullptr
1633 };
1634
1635 extern const TargetRegisterClass GPRSPRegClass = {
1636 &AVRMCRegisterClasses[GPRSPRegClassID],
1637 GPRSPSubClassMask,
1638 SuperRegIdxSeqs + 2,
1639 LaneBitmask(0x0000000000000003),
1640 0,
1641 false,
1642 0x00, /* TSFlags */
1643 true, /* HasDisjunctSubRegs */
1644 true, /* CoveredBySubRegs */
1645 NullRegClasses,
1646 nullptr
1647 };
1648
1649 extern const TargetRegisterClass ZREGRegClass = {
1650 &AVRMCRegisterClasses[ZREGRegClassID],
1651 ZREGSubClassMask,
1652 SuperRegIdxSeqs + 2,
1653 LaneBitmask(0x0000000000000003),
1654 0,
1655 false,
1656 0x00, /* TSFlags */
1657 true, /* HasDisjunctSubRegs */
1658 true, /* CoveredBySubRegs */
1659 ZREGSuperclasses,
1660 nullptr
1661 };
1662
1663} // end namespace AVR
1664
1665namespace {
1666 const TargetRegisterClass *const RegisterClasses[] = {
1667 &AVR::GPR8RegClass,
1668 &AVR::GPR8loRegClass,
1669 &AVR::LD8RegClass,
1670 &AVR::LD8loRegClass,
1671 &AVR::CCRRegClass,
1672 &AVR::DREGSRegClass,
1673 &AVR::DREGSMOVWRegClass,
1674 &AVR::DREGS_with_sub_hi_in_LD8RegClass,
1675 &AVR::DREGS_with_sub_lo_in_LD8RegClass,
1676 &AVR::DREGS_with_sub_lo_in_GPR8loRegClass,
1677 &AVR::DREGS_with_sub_hi_in_GPR8loRegClass,
1678 &AVR::DLDREGSRegClass,
1679 &AVR::DREGS_with_sub_hi_in_LD8loRegClass,
1680 &AVR::DREGS_with_sub_lo_in_LD8loRegClass,
1681 &AVR::DREGSloRegClass,
1682 &AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClass,
1683 &AVR::DREGSLD8loRegClass,
1684 &AVR::IWREGSRegClass,
1685 &AVR::PTRREGSRegClass,
1686 &AVR::PTRDISPREGSRegClass,
1687 &AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClass,
1688 &AVR::GPRSPRegClass,
1689 &AVR::ZREGRegClass,
1690 };
1691} // end anonymous namespace
1692
1693static const uint8_t CostPerUseTable[] = {
16940, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1695
1696
1697static const bool InAllocatableClassTable[] = {
1698false, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
1699
1700
1701static const TargetRegisterInfoDesc AVRRegInfoDesc = { // Extra Descriptors
1702CostPerUseTable, 1, InAllocatableClassTable};
1703
1704unsigned AVRGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1705 static const uint8_t Rows[1][2] = {
1706 { 0, 0, },
1707 };
1708
1709 --IdxA; assert(IdxA < 2); (void) IdxA;
1710 --IdxB; assert(IdxB < 2);
1711 return Rows[0][IdxB];
1712}
1713
1714 struct MaskRolOp {
1715 LaneBitmask Mask;
1716 uint8_t RotateLeft;
1717 };
1718 static const MaskRolOp LaneMaskComposeSequences[] = {
1719 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
1720 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 } // Sequence 2
1721 };
1722 static const uint8_t CompositeSequences[] = {
1723 0, // to sub_hi
1724 2 // to sub_lo
1725 };
1726
1727LaneBitmask AVRGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1728 --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
1729 LaneBitmask Result;
1730 for (const MaskRolOp *Ops =
1731 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1732 Ops->Mask.any(); ++Ops) {
1733 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
1734 if (unsigned S = Ops->RotateLeft)
1735 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
1736 else
1737 Result |= LaneBitmask(M);
1738 }
1739 return Result;
1740}
1741
1742LaneBitmask AVRGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1743 LaneMask &= getSubRegIndexLaneMask(IdxA);
1744 --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
1745 LaneBitmask Result;
1746 for (const MaskRolOp *Ops =
1747 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1748 Ops->Mask.any(); ++Ops) {
1749 LaneBitmask::Type M = LaneMask.getAsInteger();
1750 if (unsigned S = Ops->RotateLeft)
1751 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
1752 else
1753 Result |= LaneBitmask(M);
1754 }
1755 return Result;
1756}
1757
1758const TargetRegisterClass *AVRGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1759 static const uint8_t Table[23][2] = {
1760 { // GPR8
1761 0, // sub_hi
1762 0, // sub_lo
1763 },
1764 { // GPR8lo
1765 0, // sub_hi
1766 0, // sub_lo
1767 },
1768 { // LD8
1769 0, // sub_hi
1770 0, // sub_lo
1771 },
1772 { // LD8lo
1773 0, // sub_hi
1774 0, // sub_lo
1775 },
1776 { // CCR
1777 0, // sub_hi
1778 0, // sub_lo
1779 },
1780 { // DREGS
1781 6, // sub_hi -> DREGS
1782 6, // sub_lo -> DREGS
1783 },
1784 { // DREGSMOVW
1785 7, // sub_hi -> DREGSMOVW
1786 7, // sub_lo -> DREGSMOVW
1787 },
1788 { // DREGS_with_sub_hi_in_LD8
1789 8, // sub_hi -> DREGS_with_sub_hi_in_LD8
1790 8, // sub_lo -> DREGS_with_sub_hi_in_LD8
1791 },
1792 { // DREGS_with_sub_lo_in_LD8
1793 9, // sub_hi -> DREGS_with_sub_lo_in_LD8
1794 9, // sub_lo -> DREGS_with_sub_lo_in_LD8
1795 },
1796 { // DREGS_with_sub_lo_in_GPR8lo
1797 10, // sub_hi -> DREGS_with_sub_lo_in_GPR8lo
1798 10, // sub_lo -> DREGS_with_sub_lo_in_GPR8lo
1799 },
1800 { // DREGS_with_sub_hi_in_GPR8lo
1801 11, // sub_hi -> DREGS_with_sub_hi_in_GPR8lo
1802 11, // sub_lo -> DREGS_with_sub_hi_in_GPR8lo
1803 },
1804 { // DLDREGS
1805 12, // sub_hi -> DLDREGS
1806 12, // sub_lo -> DLDREGS
1807 },
1808 { // DREGS_with_sub_hi_in_LD8lo
1809 13, // sub_hi -> DREGS_with_sub_hi_in_LD8lo
1810 13, // sub_lo -> DREGS_with_sub_hi_in_LD8lo
1811 },
1812 { // DREGS_with_sub_lo_in_LD8lo
1813 14, // sub_hi -> DREGS_with_sub_lo_in_LD8lo
1814 14, // sub_lo -> DREGS_with_sub_lo_in_LD8lo
1815 },
1816 { // DREGSlo
1817 15, // sub_hi -> DREGSlo
1818 15, // sub_lo -> DREGSlo
1819 },
1820 { // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1821 16, // sub_hi -> DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1822 16, // sub_lo -> DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1823 },
1824 { // DREGSLD8lo
1825 17, // sub_hi -> DREGSLD8lo
1826 17, // sub_lo -> DREGSLD8lo
1827 },
1828 { // IWREGS
1829 18, // sub_hi -> IWREGS
1830 18, // sub_lo -> IWREGS
1831 },
1832 { // PTRREGS
1833 19, // sub_hi -> PTRREGS
1834 19, // sub_lo -> PTRREGS
1835 },
1836 { // PTRDISPREGS
1837 20, // sub_hi -> PTRDISPREGS
1838 20, // sub_lo -> PTRDISPREGS
1839 },
1840 { // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1841 21, // sub_hi -> DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1842 21, // sub_lo -> DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1843 },
1844 { // GPRSP
1845 22, // sub_hi -> GPRSP
1846 22, // sub_lo -> GPRSP
1847 },
1848 { // ZREG
1849 23, // sub_hi -> ZREG
1850 23, // sub_lo -> ZREG
1851 },
1852 };
1853 assert(RC && "Missing regclass");
1854 if (!Idx) return RC;
1855 --Idx;
1856 assert(Idx < 2 && "Bad subreg");
1857 unsigned TV = Table[RC->getID()][Idx];
1858 return TV ? getRegClass(TV - 1) : nullptr;
1859}
1860
1861const TargetRegisterClass *AVRGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1862 static const uint8_t Table[23][2] = {
1863 { // GPR8
1864 0, // GPR8:sub_hi
1865 0, // GPR8:sub_lo
1866 },
1867 { // GPR8lo
1868 0, // GPR8lo:sub_hi
1869 0, // GPR8lo:sub_lo
1870 },
1871 { // LD8
1872 0, // LD8:sub_hi
1873 0, // LD8:sub_lo
1874 },
1875 { // LD8lo
1876 0, // LD8lo:sub_hi
1877 0, // LD8lo:sub_lo
1878 },
1879 { // CCR
1880 0, // CCR:sub_hi
1881 0, // CCR:sub_lo
1882 },
1883 { // DREGS
1884 1, // DREGS:sub_hi -> GPR8
1885 1, // DREGS:sub_lo -> GPR8
1886 },
1887 { // DREGSMOVW
1888 1, // DREGSMOVW:sub_hi -> GPR8
1889 1, // DREGSMOVW:sub_lo -> GPR8
1890 },
1891 { // DREGS_with_sub_hi_in_LD8
1892 3, // DREGS_with_sub_hi_in_LD8:sub_hi -> LD8
1893 1, // DREGS_with_sub_hi_in_LD8:sub_lo -> GPR8
1894 },
1895 { // DREGS_with_sub_lo_in_LD8
1896 3, // DREGS_with_sub_lo_in_LD8:sub_hi -> LD8
1897 3, // DREGS_with_sub_lo_in_LD8:sub_lo -> LD8
1898 },
1899 { // DREGS_with_sub_lo_in_GPR8lo
1900 1, // DREGS_with_sub_lo_in_GPR8lo:sub_hi -> GPR8
1901 2, // DREGS_with_sub_lo_in_GPR8lo:sub_lo -> GPR8lo
1902 },
1903 { // DREGS_with_sub_hi_in_GPR8lo
1904 2, // DREGS_with_sub_hi_in_GPR8lo:sub_hi -> GPR8lo
1905 2, // DREGS_with_sub_hi_in_GPR8lo:sub_lo -> GPR8lo
1906 },
1907 { // DLDREGS
1908 3, // DLDREGS:sub_hi -> LD8
1909 3, // DLDREGS:sub_lo -> LD8
1910 },
1911 { // DREGS_with_sub_hi_in_LD8lo
1912 4, // DREGS_with_sub_hi_in_LD8lo:sub_hi -> LD8lo
1913 1, // DREGS_with_sub_hi_in_LD8lo:sub_lo -> GPR8
1914 },
1915 { // DREGS_with_sub_lo_in_LD8lo
1916 3, // DREGS_with_sub_lo_in_LD8lo:sub_hi -> LD8
1917 4, // DREGS_with_sub_lo_in_LD8lo:sub_lo -> LD8lo
1918 },
1919 { // DREGSlo
1920 2, // DREGSlo:sub_hi -> GPR8lo
1921 2, // DREGSlo:sub_lo -> GPR8lo
1922 },
1923 { // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1924 4, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8:sub_hi -> LD8lo
1925 4, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8:sub_lo -> LD8lo
1926 },
1927 { // DREGSLD8lo
1928 4, // DREGSLD8lo:sub_hi -> LD8lo
1929 4, // DREGSLD8lo:sub_lo -> LD8lo
1930 },
1931 { // IWREGS
1932 3, // IWREGS:sub_hi -> LD8
1933 3, // IWREGS:sub_lo -> LD8
1934 },
1935 { // PTRREGS
1936 3, // PTRREGS:sub_hi -> LD8
1937 3, // PTRREGS:sub_lo -> LD8
1938 },
1939 { // PTRDISPREGS
1940 3, // PTRDISPREGS:sub_hi -> LD8
1941 3, // PTRDISPREGS:sub_lo -> LD8
1942 },
1943 { // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1944 4, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo:sub_hi -> LD8lo
1945 2, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo:sub_lo -> GPR8lo
1946 },
1947 { // GPRSP
1948 0, // GPRSP:sub_hi
1949 0, // GPRSP:sub_lo
1950 },
1951 { // ZREG
1952 3, // ZREG:sub_hi -> LD8
1953 3, // ZREG:sub_lo -> LD8
1954 },
1955 };
1956 assert(RC && "Missing regclass");
1957 if (!Idx) return RC;
1958 --Idx;
1959 assert(Idx < 2 && "Bad subreg");
1960 unsigned TV = Table[RC->getID()][Idx];
1961 return TV ? getRegClass(TV - 1) : nullptr;
1962}
1963
1964/// Get the weight in units of pressure for this register class.
1965const RegClassWeight &AVRGenRegisterInfo::
1966getRegClassWeight(const TargetRegisterClass *RC) const {
1967 static const RegClassWeight RCWeightTable[] = {
1968 {1, 32}, // GPR8
1969 {1, 16}, // GPR8lo
1970 {1, 16}, // LD8
1971 {1, 8}, // LD8lo
1972 {1, 1}, // CCR
1973 {2, 32}, // DREGS
1974 {2, 32}, // DREGSMOVW
1975 {2, 17}, // DREGS_with_sub_hi_in_LD8
1976 {2, 16}, // DREGS_with_sub_lo_in_LD8
1977 {2, 17}, // DREGS_with_sub_lo_in_GPR8lo
1978 {2, 16}, // DREGS_with_sub_hi_in_GPR8lo
1979 {2, 16}, // DLDREGS
1980 {2, 9}, // DREGS_with_sub_hi_in_LD8lo
1981 {2, 9}, // DREGS_with_sub_lo_in_LD8lo
1982 {2, 16}, // DREGSlo
1983 {2, 8}, // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8
1984 {2, 8}, // DREGSLD8lo
1985 {2, 8}, // IWREGS
1986 {2, 6}, // PTRREGS
1987 {2, 4}, // PTRDISPREGS
1988 {2, 2}, // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
1989 {2, 2}, // GPRSP
1990 {2, 2}, // ZREG
1991 };
1992 return RCWeightTable[RC->getID()];
1993}
1994
1995/// Get the weight in units of pressure for this register unit.
1996unsigned AVRGenRegisterInfo::
1997getRegUnitWeight(unsigned RegUnit) const {
1998 assert(RegUnit < 35 && "invalid register unit");
1999 // All register units have unit weight.
2000 return 1;
2001}
2002
2003
2004// Get the number of dimensions of register pressure.
2005unsigned AVRGenRegisterInfo::getNumRegPressureSets() const {
2006 return 9;
2007}
2008
2009// Get the name of this register unit pressure set.
2010const char *AVRGenRegisterInfo::
2011getRegPressureSetName(unsigned Idx) const {
2012 static const char *PressureNameTable[] = {
2013 "CCR",
2014 "DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo",
2015 "GPRSP",
2016 "IWREGS",
2017 "LD8lo",
2018 "LD8",
2019 "GPR8lo",
2020 "GPR8lo_with_LD8lo",
2021 "GPR8",
2022 };
2023 return PressureNameTable[Idx];
2024}
2025
2026// Get the register unit pressure limit for this dimension.
2027// This limit must be adjusted dynamically for reserved registers.
2028unsigned AVRGenRegisterInfo::
2029getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
2030 static const uint8_t PressureLimitTable[] = {
2031 1, // 0: CCR
2032 2, // 1: DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo
2033 2, // 2: GPRSP
2034 8, // 3: IWREGS
2035 10, // 4: LD8lo
2036 17, // 5: LD8
2037 17, // 6: GPR8lo
2038 25, // 7: GPR8lo_with_LD8lo
2039 32, // 8: GPR8
2040 };
2041 return PressureLimitTable[Idx];
2042}
2043
2044/// Table of pressure sets per register class or unit.
2045static const int RCSetsTable[] = {
2046 /* 0 */ 0, -1,
2047 /* 2 */ 2, -1,
2048 /* 4 */ 3, 5, 8, -1,
2049 /* 8 */ 3, 4, 5, 7, 8, -1,
2050 /* 14 */ 1, 4, 5, 6, 7, 8, -1,
2051};
2052
2053/// Get the dimensions of register pressure impacted by this register class.
2054/// Returns a -1 terminated array of pressure set IDs
2055const int *AVRGenRegisterInfo::
2056getRegClassPressureSets(const TargetRegisterClass *RC) const {
2057 static const uint8_t RCSetStartTable[] = {
2058 6,17,5,9,0,6,6,5,5,17,17,5,9,9,17,9,9,4,4,4,14,2,4,};
2059 return &RCSetsTable[RCSetStartTable[RC->getID()]];
2060}
2061
2062/// Get the dimensions of register pressure impacted by this register unit.
2063/// Returns a -1 terminated array of pressure set IDs
2064const int *AVRGenRegisterInfo::
2065getRegUnitPressureSets(unsigned RegUnit) const {
2066 assert(RegUnit < 35 && "invalid register unit");
2067 static const uint8_t RUSetStartTable[] = {
2068 2,2,0,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,14,14,9,9,9,9,9,9,9,8,4,4,4,4,4,4,4,};
2069 return &RCSetsTable[RUSetStartTable[RegUnit]];
2070}
2071
2072extern const MCRegisterDesc AVRRegDesc[];
2073extern const int16_t AVRRegDiffLists[];
2074extern const LaneBitmask AVRLaneMaskLists[];
2075extern const char AVRRegStrings[];
2076extern const char AVRRegClassStrings[];
2077extern const MCPhysReg AVRRegUnitRoots[][2];
2078extern const uint16_t AVRSubRegIdxLists[];
2079extern const uint16_t AVRRegEncodingTable[];
2080// AVR Dwarf<->LLVM register mappings.
2081extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[];
2082extern const unsigned AVRDwarfFlavour0Dwarf2LSize;
2083
2084extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[];
2085extern const unsigned AVREHFlavour0Dwarf2LSize;
2086
2087extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[];
2088extern const unsigned AVRDwarfFlavour0L2DwarfSize;
2089
2090extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[];
2091extern const unsigned AVREHFlavour0L2DwarfSize;
2092
2093AVRGenRegisterInfo::
2094AVRGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
2095 unsigned PC, unsigned HwMode)
2096 : TargetRegisterInfo(&AVRRegInfoDesc, RegisterClasses, RegisterClasses+23,
2097 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
2098 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
2099 InitMCRegisterInfo(AVRRegDesc, 62, RA, PC,
2100 AVRMCRegisterClasses, 23,
2101 AVRRegUnitRoots,
2102 35,
2103 AVRRegDiffLists,
2104 AVRLaneMaskLists,
2105 AVRRegStrings,
2106 AVRRegClassStrings,
2107 AVRSubRegIdxLists,
2108 3,
2109 AVRRegEncodingTable);
2110
2111 switch (DwarfFlavour) {
2112 default:
2113 llvm_unreachable("Unknown DWARF flavour");
2114 case 0:
2115 mapDwarfRegsToLLVMRegs(AVRDwarfFlavour0Dwarf2L, AVRDwarfFlavour0Dwarf2LSize, false);
2116 break;
2117 }
2118 switch (EHFlavour) {
2119 default:
2120 llvm_unreachable("Unknown DWARF flavour");
2121 case 0:
2122 mapDwarfRegsToLLVMRegs(AVREHFlavour0Dwarf2L, AVREHFlavour0Dwarf2LSize, true);
2123 break;
2124 }
2125 switch (DwarfFlavour) {
2126 default:
2127 llvm_unreachable("Unknown DWARF flavour");
2128 case 0:
2129 mapLLVMRegsToDwarfRegs(AVRDwarfFlavour0L2Dwarf, AVRDwarfFlavour0L2DwarfSize, false);
2130 break;
2131 }
2132 switch (EHFlavour) {
2133 default:
2134 llvm_unreachable("Unknown DWARF flavour");
2135 case 0:
2136 mapLLVMRegsToDwarfRegs(AVREHFlavour0L2Dwarf, AVREHFlavour0L2DwarfSize, true);
2137 break;
2138 }
2139}
2140
2141static const MCPhysReg CSR_Interrupts_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
2142static const uint32_t CSR_Interrupts_RegMask[] = { 0xffffff80, 0x3fffffdf, };
2143static const MCPhysReg CSR_InterruptsTiny_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, 0 };
2144static const uint32_t CSR_InterruptsTiny_RegMask[] = { 0xff800000, 0x3ff8001f, };
2145static const MCPhysReg CSR_Normal_SaveList[] = { AVR::R29, AVR::R28, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
2146static const uint32_t CSR_Normal_RegMask[] = { 0x007fff80, 0x1003ffc6, };
2147static const MCPhysReg CSR_NormalTiny_SaveList[] = { AVR::R29, AVR::R28, AVR::R19, AVR::R18, 0 };
2148static const uint32_t CSR_NormalTiny_RegMask[] = { 0x01800000, 0x10080006, };
2149
2150
2151ArrayRef<const uint32_t *> AVRGenRegisterInfo::getRegMasks() const {
2152 static const uint32_t *const Masks[] = {
2153 CSR_Interrupts_RegMask,
2154 CSR_InterruptsTiny_RegMask,
2155 CSR_Normal_RegMask,
2156 CSR_NormalTiny_RegMask,
2157 };
2158 return ArrayRef(Masks);
2159}
2160
2161bool AVRGenRegisterInfo::
2162isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2163 return
2164 false;
2165}
2166
2167bool AVRGenRegisterInfo::
2168isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2169 return
2170 false;
2171}
2172
2173bool AVRGenRegisterInfo::
2174isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2175 return
2176 false;
2177}
2178
2179bool AVRGenRegisterInfo::
2180isConstantPhysReg(MCRegister PhysReg) const {
2181 return
2182 false;
2183}
2184
2185ArrayRef<const char *> AVRGenRegisterInfo::getRegMaskNames() const {
2186 static const char *Names[] = {
2187 "CSR_Interrupts",
2188 "CSR_InterruptsTiny",
2189 "CSR_Normal",
2190 "CSR_NormalTiny",
2191 };
2192 return ArrayRef(Names);
2193}
2194
2195const AVRFrameLowering *
2196AVRGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
2197 return static_cast<const AVRFrameLowering *>(
2198 MF.getSubtarget().getFrameLowering());
2199}
2200
2201} // end namespace llvm
2202
2203#endif // GET_REGINFO_TARGET_DESC
2204
2205