1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm {
12
13namespace BPF {
14 enum {
15 PHI = 0,
16 INLINEASM = 1,
17 INLINEASM_BR = 2,
18 CFI_INSTRUCTION = 3,
19 EH_LABEL = 4,
20 GC_LABEL = 5,
21 ANNOTATION_LABEL = 6,
22 KILL = 7,
23 EXTRACT_SUBREG = 8,
24 INSERT_SUBREG = 9,
25 IMPLICIT_DEF = 10,
26 SUBREG_TO_REG = 11,
27 COPY_TO_REGCLASS = 12,
28 DBG_VALUE = 13,
29 DBG_VALUE_LIST = 14,
30 DBG_INSTR_REF = 15,
31 DBG_PHI = 16,
32 DBG_LABEL = 17,
33 REG_SEQUENCE = 18,
34 COPY = 19,
35 BUNDLE = 20,
36 LIFETIME_START = 21,
37 LIFETIME_END = 22,
38 PSEUDO_PROBE = 23,
39 ARITH_FENCE = 24,
40 STACKMAP = 25,
41 FENTRY_CALL = 26,
42 PATCHPOINT = 27,
43 LOAD_STACK_GUARD = 28,
44 PREALLOCATED_SETUP = 29,
45 PREALLOCATED_ARG = 30,
46 STATEPOINT = 31,
47 LOCAL_ESCAPE = 32,
48 FAULTING_OP = 33,
49 PATCHABLE_OP = 34,
50 PATCHABLE_FUNCTION_ENTER = 35,
51 PATCHABLE_RET = 36,
52 PATCHABLE_FUNCTION_EXIT = 37,
53 PATCHABLE_TAIL_CALL = 38,
54 PATCHABLE_EVENT_CALL = 39,
55 PATCHABLE_TYPED_EVENT_CALL = 40,
56 ICALL_BRANCH_FUNNEL = 41,
57 MEMBARRIER = 42,
58 JUMP_TABLE_DEBUG_INFO = 43,
59 CONVERGENCECTRL_ENTRY = 44,
60 CONVERGENCECTRL_ANCHOR = 45,
61 CONVERGENCECTRL_LOOP = 46,
62 CONVERGENCECTRL_GLUE = 47,
63 G_ASSERT_SEXT = 48,
64 G_ASSERT_ZEXT = 49,
65 G_ASSERT_ALIGN = 50,
66 G_ADD = 51,
67 G_SUB = 52,
68 G_MUL = 53,
69 G_SDIV = 54,
70 G_UDIV = 55,
71 G_SREM = 56,
72 G_UREM = 57,
73 G_SDIVREM = 58,
74 G_UDIVREM = 59,
75 G_AND = 60,
76 G_OR = 61,
77 G_XOR = 62,
78 G_IMPLICIT_DEF = 63,
79 G_PHI = 64,
80 G_FRAME_INDEX = 65,
81 G_GLOBAL_VALUE = 66,
82 G_PTRAUTH_GLOBAL_VALUE = 67,
83 G_CONSTANT_POOL = 68,
84 G_EXTRACT = 69,
85 G_UNMERGE_VALUES = 70,
86 G_INSERT = 71,
87 G_MERGE_VALUES = 72,
88 G_BUILD_VECTOR = 73,
89 G_BUILD_VECTOR_TRUNC = 74,
90 G_CONCAT_VECTORS = 75,
91 G_PTRTOINT = 76,
92 G_INTTOPTR = 77,
93 G_BITCAST = 78,
94 G_FREEZE = 79,
95 G_CONSTANT_FOLD_BARRIER = 80,
96 G_INTRINSIC_FPTRUNC_ROUND = 81,
97 G_INTRINSIC_TRUNC = 82,
98 G_INTRINSIC_ROUND = 83,
99 G_INTRINSIC_LRINT = 84,
100 G_INTRINSIC_LLRINT = 85,
101 G_INTRINSIC_ROUNDEVEN = 86,
102 G_READCYCLECOUNTER = 87,
103 G_READSTEADYCOUNTER = 88,
104 G_LOAD = 89,
105 G_SEXTLOAD = 90,
106 G_ZEXTLOAD = 91,
107 G_INDEXED_LOAD = 92,
108 G_INDEXED_SEXTLOAD = 93,
109 G_INDEXED_ZEXTLOAD = 94,
110 G_STORE = 95,
111 G_INDEXED_STORE = 96,
112 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97,
113 G_ATOMIC_CMPXCHG = 98,
114 G_ATOMICRMW_XCHG = 99,
115 G_ATOMICRMW_ADD = 100,
116 G_ATOMICRMW_SUB = 101,
117 G_ATOMICRMW_AND = 102,
118 G_ATOMICRMW_NAND = 103,
119 G_ATOMICRMW_OR = 104,
120 G_ATOMICRMW_XOR = 105,
121 G_ATOMICRMW_MAX = 106,
122 G_ATOMICRMW_MIN = 107,
123 G_ATOMICRMW_UMAX = 108,
124 G_ATOMICRMW_UMIN = 109,
125 G_ATOMICRMW_FADD = 110,
126 G_ATOMICRMW_FSUB = 111,
127 G_ATOMICRMW_FMAX = 112,
128 G_ATOMICRMW_FMIN = 113,
129 G_ATOMICRMW_UINC_WRAP = 114,
130 G_ATOMICRMW_UDEC_WRAP = 115,
131 G_FENCE = 116,
132 G_PREFETCH = 117,
133 G_BRCOND = 118,
134 G_BRINDIRECT = 119,
135 G_INVOKE_REGION_START = 120,
136 G_INTRINSIC = 121,
137 G_INTRINSIC_W_SIDE_EFFECTS = 122,
138 G_INTRINSIC_CONVERGENT = 123,
139 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124,
140 G_ANYEXT = 125,
141 G_TRUNC = 126,
142 G_CONSTANT = 127,
143 G_FCONSTANT = 128,
144 G_VASTART = 129,
145 G_VAARG = 130,
146 G_SEXT = 131,
147 G_SEXT_INREG = 132,
148 G_ZEXT = 133,
149 G_SHL = 134,
150 G_LSHR = 135,
151 G_ASHR = 136,
152 G_FSHL = 137,
153 G_FSHR = 138,
154 G_ROTR = 139,
155 G_ROTL = 140,
156 G_ICMP = 141,
157 G_FCMP = 142,
158 G_SCMP = 143,
159 G_UCMP = 144,
160 G_SELECT = 145,
161 G_UADDO = 146,
162 G_UADDE = 147,
163 G_USUBO = 148,
164 G_USUBE = 149,
165 G_SADDO = 150,
166 G_SADDE = 151,
167 G_SSUBO = 152,
168 G_SSUBE = 153,
169 G_UMULO = 154,
170 G_SMULO = 155,
171 G_UMULH = 156,
172 G_SMULH = 157,
173 G_UADDSAT = 158,
174 G_SADDSAT = 159,
175 G_USUBSAT = 160,
176 G_SSUBSAT = 161,
177 G_USHLSAT = 162,
178 G_SSHLSAT = 163,
179 G_SMULFIX = 164,
180 G_UMULFIX = 165,
181 G_SMULFIXSAT = 166,
182 G_UMULFIXSAT = 167,
183 G_SDIVFIX = 168,
184 G_UDIVFIX = 169,
185 G_SDIVFIXSAT = 170,
186 G_UDIVFIXSAT = 171,
187 G_FADD = 172,
188 G_FSUB = 173,
189 G_FMUL = 174,
190 G_FMA = 175,
191 G_FMAD = 176,
192 G_FDIV = 177,
193 G_FREM = 178,
194 G_FPOW = 179,
195 G_FPOWI = 180,
196 G_FEXP = 181,
197 G_FEXP2 = 182,
198 G_FEXP10 = 183,
199 G_FLOG = 184,
200 G_FLOG2 = 185,
201 G_FLOG10 = 186,
202 G_FLDEXP = 187,
203 G_FFREXP = 188,
204 G_FNEG = 189,
205 G_FPEXT = 190,
206 G_FPTRUNC = 191,
207 G_FPTOSI = 192,
208 G_FPTOUI = 193,
209 G_SITOFP = 194,
210 G_UITOFP = 195,
211 G_FABS = 196,
212 G_FCOPYSIGN = 197,
213 G_IS_FPCLASS = 198,
214 G_FCANONICALIZE = 199,
215 G_FMINNUM = 200,
216 G_FMAXNUM = 201,
217 G_FMINNUM_IEEE = 202,
218 G_FMAXNUM_IEEE = 203,
219 G_FMINIMUM = 204,
220 G_FMAXIMUM = 205,
221 G_GET_FPENV = 206,
222 G_SET_FPENV = 207,
223 G_RESET_FPENV = 208,
224 G_GET_FPMODE = 209,
225 G_SET_FPMODE = 210,
226 G_RESET_FPMODE = 211,
227 G_PTR_ADD = 212,
228 G_PTRMASK = 213,
229 G_SMIN = 214,
230 G_SMAX = 215,
231 G_UMIN = 216,
232 G_UMAX = 217,
233 G_ABS = 218,
234 G_LROUND = 219,
235 G_LLROUND = 220,
236 G_BR = 221,
237 G_BRJT = 222,
238 G_VSCALE = 223,
239 G_INSERT_SUBVECTOR = 224,
240 G_EXTRACT_SUBVECTOR = 225,
241 G_INSERT_VECTOR_ELT = 226,
242 G_EXTRACT_VECTOR_ELT = 227,
243 G_SHUFFLE_VECTOR = 228,
244 G_SPLAT_VECTOR = 229,
245 G_VECTOR_COMPRESS = 230,
246 G_CTTZ = 231,
247 G_CTTZ_ZERO_UNDEF = 232,
248 G_CTLZ = 233,
249 G_CTLZ_ZERO_UNDEF = 234,
250 G_CTPOP = 235,
251 G_BSWAP = 236,
252 G_BITREVERSE = 237,
253 G_FCEIL = 238,
254 G_FCOS = 239,
255 G_FSIN = 240,
256 G_FTAN = 241,
257 G_FACOS = 242,
258 G_FASIN = 243,
259 G_FATAN = 244,
260 G_FCOSH = 245,
261 G_FSINH = 246,
262 G_FTANH = 247,
263 G_FSQRT = 248,
264 G_FFLOOR = 249,
265 G_FRINT = 250,
266 G_FNEARBYINT = 251,
267 G_ADDRSPACE_CAST = 252,
268 G_BLOCK_ADDR = 253,
269 G_JUMP_TABLE = 254,
270 G_DYN_STACKALLOC = 255,
271 G_STACKSAVE = 256,
272 G_STACKRESTORE = 257,
273 G_STRICT_FADD = 258,
274 G_STRICT_FSUB = 259,
275 G_STRICT_FMUL = 260,
276 G_STRICT_FDIV = 261,
277 G_STRICT_FREM = 262,
278 G_STRICT_FMA = 263,
279 G_STRICT_FSQRT = 264,
280 G_STRICT_FLDEXP = 265,
281 G_READ_REGISTER = 266,
282 G_WRITE_REGISTER = 267,
283 G_MEMCPY = 268,
284 G_MEMCPY_INLINE = 269,
285 G_MEMMOVE = 270,
286 G_MEMSET = 271,
287 G_BZERO = 272,
288 G_TRAP = 273,
289 G_DEBUGTRAP = 274,
290 G_UBSANTRAP = 275,
291 G_VECREDUCE_SEQ_FADD = 276,
292 G_VECREDUCE_SEQ_FMUL = 277,
293 G_VECREDUCE_FADD = 278,
294 G_VECREDUCE_FMUL = 279,
295 G_VECREDUCE_FMAX = 280,
296 G_VECREDUCE_FMIN = 281,
297 G_VECREDUCE_FMAXIMUM = 282,
298 G_VECREDUCE_FMINIMUM = 283,
299 G_VECREDUCE_ADD = 284,
300 G_VECREDUCE_MUL = 285,
301 G_VECREDUCE_AND = 286,
302 G_VECREDUCE_OR = 287,
303 G_VECREDUCE_XOR = 288,
304 G_VECREDUCE_SMAX = 289,
305 G_VECREDUCE_SMIN = 290,
306 G_VECREDUCE_UMAX = 291,
307 G_VECREDUCE_UMIN = 292,
308 G_SBFX = 293,
309 G_UBFX = 294,
310 ADJCALLSTACKDOWN = 295,
311 ADJCALLSTACKUP = 296,
312 FI_ri = 297,
313 MEMCPY = 298,
314 Select = 299,
315 Select_32 = 300,
316 Select_32_64 = 301,
317 Select_64_32 = 302,
318 Select_Ri = 303,
319 Select_Ri_32 = 304,
320 Select_Ri_32_64 = 305,
321 Select_Ri_64_32 = 306,
322 ADDR_SPACE_CAST = 307,
323 ADD_ri = 308,
324 ADD_ri_32 = 309,
325 ADD_rr = 310,
326 ADD_rr_32 = 311,
327 AND_ri = 312,
328 AND_ri_32 = 313,
329 AND_rr = 314,
330 AND_rr_32 = 315,
331 BE16 = 316,
332 BE32 = 317,
333 BE64 = 318,
334 BSWAP16 = 319,
335 BSWAP32 = 320,
336 BSWAP64 = 321,
337 CMPXCHGD = 322,
338 CMPXCHGW32 = 323,
339 CORE_LD32 = 324,
340 CORE_LD64 = 325,
341 CORE_SHIFT = 326,
342 CORE_ST = 327,
343 DIV_ri = 328,
344 DIV_ri_32 = 329,
345 DIV_rr = 330,
346 DIV_rr_32 = 331,
347 JAL = 332,
348 JALX = 333,
349 JCOND = 334,
350 JEQ_ri = 335,
351 JEQ_ri_32 = 336,
352 JEQ_rr = 337,
353 JEQ_rr_32 = 338,
354 JMP = 339,
355 JMPL = 340,
356 JNE_ri = 341,
357 JNE_ri_32 = 342,
358 JNE_rr = 343,
359 JNE_rr_32 = 344,
360 JSET_ri = 345,
361 JSET_ri_32 = 346,
362 JSET_rr = 347,
363 JSET_rr_32 = 348,
364 JSGE_ri = 349,
365 JSGE_ri_32 = 350,
366 JSGE_rr = 351,
367 JSGE_rr_32 = 352,
368 JSGT_ri = 353,
369 JSGT_ri_32 = 354,
370 JSGT_rr = 355,
371 JSGT_rr_32 = 356,
372 JSLE_ri = 357,
373 JSLE_ri_32 = 358,
374 JSLE_rr = 359,
375 JSLE_rr_32 = 360,
376 JSLT_ri = 361,
377 JSLT_ri_32 = 362,
378 JSLT_rr = 363,
379 JSLT_rr_32 = 364,
380 JUGE_ri = 365,
381 JUGE_ri_32 = 366,
382 JUGE_rr = 367,
383 JUGE_rr_32 = 368,
384 JUGT_ri = 369,
385 JUGT_ri_32 = 370,
386 JUGT_rr = 371,
387 JUGT_rr_32 = 372,
388 JULE_ri = 373,
389 JULE_ri_32 = 374,
390 JULE_rr = 375,
391 JULE_rr_32 = 376,
392 JULT_ri = 377,
393 JULT_ri_32 = 378,
394 JULT_rr = 379,
395 JULT_rr_32 = 380,
396 LDB = 381,
397 LDB32 = 382,
398 LDBSX = 383,
399 LDD = 384,
400 LDH = 385,
401 LDH32 = 386,
402 LDHSX = 387,
403 LDW = 388,
404 LDW32 = 389,
405 LDWSX = 390,
406 LD_ABS_B = 391,
407 LD_ABS_H = 392,
408 LD_ABS_W = 393,
409 LD_IND_B = 394,
410 LD_IND_H = 395,
411 LD_IND_W = 396,
412 LD_imm64 = 397,
413 LD_pseudo = 398,
414 LE16 = 399,
415 LE32 = 400,
416 LE64 = 401,
417 MOD_ri = 402,
418 MOD_ri_32 = 403,
419 MOD_rr = 404,
420 MOD_rr_32 = 405,
421 MOVSX_rr_16 = 406,
422 MOVSX_rr_32 = 407,
423 MOVSX_rr_32_16 = 408,
424 MOVSX_rr_32_8 = 409,
425 MOVSX_rr_8 = 410,
426 MOV_32_64 = 411,
427 MOV_ri = 412,
428 MOV_ri_32 = 413,
429 MOV_rr = 414,
430 MOV_rr_32 = 415,
431 MUL_ri = 416,
432 MUL_ri_32 = 417,
433 MUL_rr = 418,
434 MUL_rr_32 = 419,
435 NEG_32 = 420,
436 NEG_64 = 421,
437 NOP = 422,
438 OR_ri = 423,
439 OR_ri_32 = 424,
440 OR_rr = 425,
441 OR_rr_32 = 426,
442 RET = 427,
443 SDIV_ri = 428,
444 SDIV_ri_32 = 429,
445 SDIV_rr = 430,
446 SDIV_rr_32 = 431,
447 SLL_ri = 432,
448 SLL_ri_32 = 433,
449 SLL_rr = 434,
450 SLL_rr_32 = 435,
451 SMOD_ri = 436,
452 SMOD_ri_32 = 437,
453 SMOD_rr = 438,
454 SMOD_rr_32 = 439,
455 SRA_ri = 440,
456 SRA_ri_32 = 441,
457 SRA_rr = 442,
458 SRA_rr_32 = 443,
459 SRL_ri = 444,
460 SRL_ri_32 = 445,
461 SRL_rr = 446,
462 SRL_rr_32 = 447,
463 STB = 448,
464 STB32 = 449,
465 STB_imm = 450,
466 STD = 451,
467 STD_imm = 452,
468 STH = 453,
469 STH32 = 454,
470 STH_imm = 455,
471 STW = 456,
472 STW32 = 457,
473 STW_imm = 458,
474 SUB_ri = 459,
475 SUB_ri_32 = 460,
476 SUB_rr = 461,
477 SUB_rr_32 = 462,
478 XADDD = 463,
479 XADDW = 464,
480 XADDW32 = 465,
481 XANDD = 466,
482 XANDW32 = 467,
483 XCHGD = 468,
484 XCHGW32 = 469,
485 XFADDD = 470,
486 XFADDW32 = 471,
487 XFANDD = 472,
488 XFANDW32 = 473,
489 XFORD = 474,
490 XFORW32 = 475,
491 XFXORD = 476,
492 XFXORW32 = 477,
493 XORD = 478,
494 XORW32 = 479,
495 XOR_ri = 480,
496 XOR_ri_32 = 481,
497 XOR_rr = 482,
498 XOR_rr_32 = 483,
499 XXORD = 484,
500 XXORW32 = 485,
501 INSTRUCTION_LIST_END = 486
502 };
503
504} // end namespace BPF
505} // end namespace llvm
506#endif // GET_INSTRINFO_ENUM
507
508#ifdef GET_INSTRINFO_SCHED_ENUM
509#undef GET_INSTRINFO_SCHED_ENUM
510namespace llvm {
511
512namespace BPF {
513namespace Sched {
514 enum {
515 NoInstrModel = 0,
516 SCHED_LIST_END = 1
517 };
518} // end namespace Sched
519} // end namespace BPF
520} // end namespace llvm
521#endif // GET_INSTRINFO_SCHED_ENUM
522
523#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
524namespace llvm {
525
526struct BPFInstrTable {
527 MCInstrDesc Insts[486];
528 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
529 MCOperandInfo OperandInfo[284];
530 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
531 MCPhysReg ImplicitOps[20];
532};
533
534} // end namespace llvm
535#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
536
537#ifdef GET_INSTRINFO_MC_DESC
538#undef GET_INSTRINFO_MC_DESC
539namespace llvm {
540
541static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
542static constexpr unsigned BPFImpOpBase = sizeof BPFInstrTable::OperandInfo / (sizeof(MCPhysReg));
543
544extern const BPFInstrTable BPFDescs = {
545 {
546 { 485, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #485 = XXORW32
547 { 484, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #484 = XXORD
548 { 483, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #483 = XOR_rr_32
549 { 482, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #482 = XOR_rr
550 { 481, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #481 = XOR_ri_32
551 { 480, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #480 = XOR_ri
552 { 479, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #479 = XORW32
553 { 478, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #478 = XORD
554 { 477, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #477 = XFXORW32
555 { 476, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #476 = XFXORD
556 { 475, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #475 = XFORW32
557 { 474, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #474 = XFORD
558 { 473, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #473 = XFANDW32
559 { 472, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #472 = XFANDD
560 { 471, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #471 = XFADDW32
561 { 470, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #470 = XFADDD
562 { 469, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #469 = XCHGW32
563 { 468, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #468 = XCHGD
564 { 467, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #467 = XANDW32
565 { 466, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #466 = XANDD
566 { 465, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #465 = XADDW32
567 { 464, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #464 = XADDW
568 { 463, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #463 = XADDD
569 { 462, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #462 = SUB_rr_32
570 { 461, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #461 = SUB_rr
571 { 460, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #460 = SUB_ri_32
572 { 459, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #459 = SUB_ri
573 { 458, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 273, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #458 = STW_imm
574 { 457, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 256, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #457 = STW32
575 { 456, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #456 = STW
576 { 455, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 273, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #455 = STH_imm
577 { 454, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 256, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #454 = STH32
578 { 453, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = STH
579 { 452, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 273, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = STD_imm
580 { 451, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #451 = STD
581 { 450, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 273, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #450 = STB_imm
582 { 449, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 256, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = STB32
583 { 448, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = STB
584 { 447, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #447 = SRL_rr_32
585 { 446, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #446 = SRL_rr
586 { 445, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = SRL_ri_32
587 { 444, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = SRL_ri
588 { 443, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #443 = SRA_rr_32
589 { 442, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #442 = SRA_rr
590 { 441, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = SRA_ri_32
591 { 440, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = SRA_ri
592 { 439, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #439 = SMOD_rr_32
593 { 438, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #438 = SMOD_rr
594 { 437, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #437 = SMOD_ri_32
595 { 436, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #436 = SMOD_ri
596 { 435, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #435 = SLL_rr_32
597 { 434, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #434 = SLL_rr
598 { 433, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #433 = SLL_ri_32
599 { 432, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #432 = SLL_ri
600 { 431, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #431 = SDIV_rr_32
601 { 430, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #430 = SDIV_rr
602 { 429, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #429 = SDIV_ri_32
603 { 428, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #428 = SDIV_ri
604 { 427, 0, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #427 = RET
605 { 426, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #426 = OR_rr_32
606 { 425, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #425 = OR_rr
607 { 424, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #424 = OR_ri_32
608 { 423, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #423 = OR_ri
609 { 422, 1, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #422 = NOP
610 { 421, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #421 = NEG_64
611 { 420, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 271, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #420 = NEG_32
612 { 419, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #419 = MUL_rr_32
613 { 418, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #418 = MUL_rr
614 { 417, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #417 = MUL_ri_32
615 { 416, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #416 = MUL_ri
616 { 415, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 265, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #415 = MOV_rr_32
617 { 414, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 261, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #414 = MOV_rr
618 { 413, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 269, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #413 = MOV_ri_32
619 { 412, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 259, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #412 = MOV_ri
620 { 411, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 267, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #411 = MOV_32_64
621 { 410, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 261, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #410 = MOVSX_rr_8
622 { 409, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 265, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #409 = MOVSX_rr_32_8
623 { 408, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 265, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #408 = MOVSX_rr_32_16
624 { 407, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 261, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #407 = MOVSX_rr_32
625 { 406, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 261, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #406 = MOVSX_rr_16
626 { 405, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #405 = MOD_rr_32
627 { 404, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #404 = MOD_rr
628 { 403, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #403 = MOD_ri_32
629 { 402, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #402 = MOD_ri
630 { 401, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #401 = LE64
631 { 400, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #400 = LE32
632 { 399, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #399 = LE16
633 { 398, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #398 = LD_pseudo
634 { 397, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 263, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #397 = LD_imm64
635 { 396, 2, 0, 8, 0, 1, 6, BPFImpOpBase + 13, 261, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #396 = LD_IND_W
636 { 395, 2, 0, 8, 0, 1, 6, BPFImpOpBase + 13, 261, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #395 = LD_IND_H
637 { 394, 2, 0, 8, 0, 1, 6, BPFImpOpBase + 13, 261, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #394 = LD_IND_B
638 { 393, 2, 0, 8, 0, 1, 6, BPFImpOpBase + 13, 259, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = LD_ABS_W
639 { 392, 2, 0, 8, 0, 1, 6, BPFImpOpBase + 13, 259, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = LD_ABS_H
640 { 391, 2, 0, 8, 0, 1, 6, BPFImpOpBase + 13, 259, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = LD_ABS_B
641 { 390, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = LDWSX
642 { 389, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 256, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = LDW32
643 { 388, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = LDW
644 { 387, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = LDHSX
645 { 386, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 256, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = LDH32
646 { 385, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = LDH
647 { 384, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = LDD
648 { 383, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = LDBSX
649 { 382, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 256, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = LDB32
650 { 381, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = LDB
651 { 380, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = JULT_rr_32
652 { 379, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = JULT_rr
653 { 378, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = JULT_ri_32
654 { 377, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = JULT_ri
655 { 376, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = JULE_rr_32
656 { 375, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = JULE_rr
657 { 374, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = JULE_ri_32
658 { 373, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = JULE_ri
659 { 372, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = JUGT_rr_32
660 { 371, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = JUGT_rr
661 { 370, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = JUGT_ri_32
662 { 369, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = JUGT_ri
663 { 368, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = JUGE_rr_32
664 { 367, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = JUGE_rr
665 { 366, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = JUGE_ri_32
666 { 365, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = JUGE_ri
667 { 364, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = JSLT_rr_32
668 { 363, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = JSLT_rr
669 { 362, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = JSLT_ri_32
670 { 361, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = JSLT_ri
671 { 360, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = JSLE_rr_32
672 { 359, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = JSLE_rr
673 { 358, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = JSLE_ri_32
674 { 357, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = JSLE_ri
675 { 356, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = JSGT_rr_32
676 { 355, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = JSGT_rr
677 { 354, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = JSGT_ri_32
678 { 353, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = JSGT_ri
679 { 352, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = JSGE_rr_32
680 { 351, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = JSGE_rr
681 { 350, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = JSGE_ri_32
682 { 349, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = JSGE_ri
683 { 348, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = JSET_rr_32
684 { 347, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = JSET_rr
685 { 346, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = JSET_ri_32
686 { 345, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = JSET_ri
687 { 344, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = JNE_rr_32
688 { 343, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = JNE_rr
689 { 342, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = JNE_ri_32
690 { 341, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = JNE_ri
691 { 340, 1, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = JMPL
692 { 339, 1, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = JMP
693 { 338, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = JEQ_rr_32
694 { 337, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = JEQ_rr
695 { 336, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = JEQ_ri_32
696 { 335, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = JEQ_ri
697 { 334, 1, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = JCOND
698 { 333, 1, 0, 8, 0, 1, 6, BPFImpOpBase + 6, 243, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = JALX
699 { 332, 1, 0, 8, 0, 1, 6, BPFImpOpBase + 6, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = JAL
700 { 331, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = DIV_rr_32
701 { 330, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = DIV_rr
702 { 329, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = DIV_ri_32
703 { 328, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = DIV_ri
704 { 327, 4, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = CORE_ST
705 { 326, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 235, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = CORE_SHIFT
706 { 325, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 231, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = CORE_LD64
707 { 324, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 227, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = CORE_LD32
708 { 323, 3, 0, 8, 0, 1, 1, BPFImpOpBase + 4, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = CMPXCHGW32
709 { 322, 3, 0, 8, 0, 1, 1, BPFImpOpBase + 2, 221, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = CMPXCHGD
710 { 321, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #321 = BSWAP64
711 { 320, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #320 = BSWAP32
712 { 319, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = BSWAP16
713 { 318, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = BE64
714 { 317, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = BE32
715 { 316, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = BE16
716 { 315, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = AND_rr_32
717 { 314, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = AND_rr
718 { 313, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #313 = AND_ri_32
719 { 312, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #312 = AND_ri
720 { 311, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #311 = ADD_rr_32
721 { 310, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = ADD_rr
722 { 309, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = ADD_ri_32
723 { 308, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = ADD_ri
724 { 307, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #307 = ADDR_SPACE_CAST
725 { 306, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 201, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #306 = Select_Ri_64_32
726 { 305, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 195, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #305 = Select_Ri_32_64
727 { 304, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 189, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #304 = Select_Ri_32
728 { 303, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 183, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #303 = Select_Ri
729 { 302, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 177, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = Select_64_32
730 { 301, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 171, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = Select_32_64
731 { 300, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 165, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = Select_32
732 { 299, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #299 = Select
733 { 298, 4, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #298 = MEMCPY
734 { 297, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #297 = FI_ri
735 { 296, 2, 0, 8, 0, 1, 1, BPFImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = ADJCALLSTACKUP
736 { 295, 2, 0, 8, 0, 1, 1, BPFImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = ADJCALLSTACKDOWN
737 { 294, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_UBFX
738 { 293, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_SBFX
739 { 292, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMIN
740 { 291, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_UMAX
741 { 290, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMIN
742 { 289, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_VECREDUCE_SMAX
743 { 288, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_VECREDUCE_XOR
744 { 287, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_VECREDUCE_OR
745 { 286, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_VECREDUCE_AND
746 { 285, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_VECREDUCE_MUL
747 { 284, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_VECREDUCE_ADD
748 { 283, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMINIMUM
749 { 282, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMAXIMUM
750 { 281, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMIN
751 { 280, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMAX
752 { 279, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_VECREDUCE_FMUL
753 { 278, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_VECREDUCE_FADD
754 { 277, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FMUL
755 { 276, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_VECREDUCE_SEQ_FADD
756 { 275, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_UBSANTRAP
757 { 274, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #274 = G_DEBUGTRAP
758 { 273, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #273 = G_TRAP
759 { 272, 3, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #272 = G_BZERO
760 { 271, 4, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_MEMSET
761 { 270, 4, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_MEMMOVE
762 { 269, 3, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_MEMCPY_INLINE
763 { 268, 4, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #268 = G_MEMCPY
764 { 267, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_WRITE_REGISTER
765 { 266, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #266 = G_READ_REGISTER
766 { 265, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_STRICT_FLDEXP
767 { 264, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_STRICT_FSQRT
768 { 263, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_STRICT_FMA
769 { 262, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_STRICT_FREM
770 { 261, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_STRICT_FDIV
771 { 260, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_STRICT_FMUL
772 { 259, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_STRICT_FSUB
773 { 258, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_STRICT_FADD
774 { 257, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_STACKRESTORE
775 { 256, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_STACKSAVE
776 { 255, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_DYN_STACKALLOC
777 { 254, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_JUMP_TABLE
778 { 253, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_BLOCK_ADDR
779 { 252, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_ADDRSPACE_CAST
780 { 251, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FNEARBYINT
781 { 250, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_FRINT
782 { 249, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_FFLOOR
783 { 248, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_FSQRT
784 { 247, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_FTANH
785 { 246, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_FSINH
786 { 245, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_FCOSH
787 { 244, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_FATAN
788 { 243, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_FASIN
789 { 242, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_FACOS
790 { 241, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_FTAN
791 { 240, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_FSIN
792 { 239, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_FCOS
793 { 238, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_FCEIL
794 { 237, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_BITREVERSE
795 { 236, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_BSWAP
796 { 235, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_CTPOP
797 { 234, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_CTLZ_ZERO_UNDEF
798 { 233, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_CTLZ
799 { 232, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_CTTZ_ZERO_UNDEF
800 { 231, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_CTTZ
801 { 230, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_VECTOR_COMPRESS
802 { 229, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_SPLAT_VECTOR
803 { 228, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_SHUFFLE_VECTOR
804 { 227, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_EXTRACT_VECTOR_ELT
805 { 226, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_INSERT_VECTOR_ELT
806 { 225, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_EXTRACT_SUBVECTOR
807 { 224, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_INSERT_SUBVECTOR
808 { 223, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_VSCALE
809 { 222, 3, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_BRJT
810 { 221, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_BR
811 { 220, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_LLROUND
812 { 219, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_LROUND
813 { 218, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_ABS
814 { 217, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_UMAX
815 { 216, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_UMIN
816 { 215, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_SMAX
817 { 214, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_SMIN
818 { 213, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_PTRMASK
819 { 212, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_PTR_ADD
820 { 211, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_RESET_FPMODE
821 { 210, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_SET_FPMODE
822 { 209, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_GET_FPMODE
823 { 208, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_RESET_FPENV
824 { 207, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_SET_FPENV
825 { 206, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_GET_FPENV
826 { 205, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FMAXIMUM
827 { 204, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_FMINIMUM
828 { 203, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_FMAXNUM_IEEE
829 { 202, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_FMINNUM_IEEE
830 { 201, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FMAXNUM
831 { 200, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FMINNUM
832 { 199, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_FCANONICALIZE
833 { 198, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_IS_FPCLASS
834 { 197, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FCOPYSIGN
835 { 196, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_FABS
836 { 195, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_UITOFP
837 { 194, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_SITOFP
838 { 193, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FPTOUI
839 { 192, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FPTOSI
840 { 191, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FPTRUNC
841 { 190, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FPEXT
842 { 189, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FNEG
843 { 188, 3, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FFREXP
844 { 187, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FLDEXP
845 { 186, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FLOG10
846 { 185, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FLOG2
847 { 184, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FLOG
848 { 183, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FEXP10
849 { 182, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FEXP2
850 { 181, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FEXP
851 { 180, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FPOWI
852 { 179, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #179 = G_FPOW
853 { 178, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #178 = G_FREM
854 { 177, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #177 = G_FDIV
855 { 176, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #176 = G_FMAD
856 { 175, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #175 = G_FMA
857 { 174, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #174 = G_FMUL
858 { 173, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #173 = G_FSUB
859 { 172, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #172 = G_FADD
860 { 171, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #171 = G_UDIVFIXSAT
861 { 170, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #170 = G_SDIVFIXSAT
862 { 169, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #169 = G_UDIVFIX
863 { 168, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #168 = G_SDIVFIX
864 { 167, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #167 = G_UMULFIXSAT
865 { 166, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #166 = G_SMULFIXSAT
866 { 165, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #165 = G_UMULFIX
867 { 164, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #164 = G_SMULFIX
868 { 163, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #163 = G_SSHLSAT
869 { 162, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #162 = G_USHLSAT
870 { 161, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #161 = G_SSUBSAT
871 { 160, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #160 = G_USUBSAT
872 { 159, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #159 = G_SADDSAT
873 { 158, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #158 = G_UADDSAT
874 { 157, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #157 = G_SMULH
875 { 156, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #156 = G_UMULH
876 { 155, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #155 = G_SMULO
877 { 154, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #154 = G_UMULO
878 { 153, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #153 = G_SSUBE
879 { 152, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #152 = G_SSUBO
880 { 151, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #151 = G_SADDE
881 { 150, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #150 = G_SADDO
882 { 149, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #149 = G_USUBE
883 { 148, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #148 = G_USUBO
884 { 147, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #147 = G_UADDE
885 { 146, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #146 = G_UADDO
886 { 145, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #145 = G_SELECT
887 { 144, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #144 = G_UCMP
888 { 143, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #143 = G_SCMP
889 { 142, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #142 = G_FCMP
890 { 141, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #141 = G_ICMP
891 { 140, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #140 = G_ROTL
892 { 139, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #139 = G_ROTR
893 { 138, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #138 = G_FSHR
894 { 137, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #137 = G_FSHL
895 { 136, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #136 = G_ASHR
896 { 135, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #135 = G_LSHR
897 { 134, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #134 = G_SHL
898 { 133, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #133 = G_ZEXT
899 { 132, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #132 = G_SEXT_INREG
900 { 131, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #131 = G_SEXT
901 { 130, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #130 = G_VAARG
902 { 129, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #129 = G_VASTART
903 { 128, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #128 = G_FCONSTANT
904 { 127, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #127 = G_CONSTANT
905 { 126, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #126 = G_TRUNC
906 { 125, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #125 = G_ANYEXT
907 { 124, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
908 { 123, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #123 = G_INTRINSIC_CONVERGENT
909 { 122, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #122 = G_INTRINSIC_W_SIDE_EFFECTS
910 { 121, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #121 = G_INTRINSIC
911 { 120, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #120 = G_INVOKE_REGION_START
912 { 119, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #119 = G_BRINDIRECT
913 { 118, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #118 = G_BRCOND
914 { 117, 4, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #117 = G_PREFETCH
915 { 116, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #116 = G_FENCE
916 { 115, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UDEC_WRAP
917 { 114, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #114 = G_ATOMICRMW_UINC_WRAP
918 { 113, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMIN
919 { 112, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FMAX
920 { 111, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FSUB
921 { 110, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #110 = G_ATOMICRMW_FADD
922 { 109, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMIN
923 { 108, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #108 = G_ATOMICRMW_UMAX
924 { 107, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MIN
925 { 106, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #106 = G_ATOMICRMW_MAX
926 { 105, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #105 = G_ATOMICRMW_XOR
927 { 104, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #104 = G_ATOMICRMW_OR
928 { 103, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #103 = G_ATOMICRMW_NAND
929 { 102, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #102 = G_ATOMICRMW_AND
930 { 101, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #101 = G_ATOMICRMW_SUB
931 { 100, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #100 = G_ATOMICRMW_ADD
932 { 99, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #99 = G_ATOMICRMW_XCHG
933 { 98, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG
934 { 97, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #97 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
935 { 96, 5, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #96 = G_INDEXED_STORE
936 { 95, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #95 = G_STORE
937 { 94, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #94 = G_INDEXED_ZEXTLOAD
938 { 93, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #93 = G_INDEXED_SEXTLOAD
939 { 92, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #92 = G_INDEXED_LOAD
940 { 91, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #91 = G_ZEXTLOAD
941 { 90, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #90 = G_SEXTLOAD
942 { 89, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #89 = G_LOAD
943 { 88, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #88 = G_READSTEADYCOUNTER
944 { 87, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #87 = G_READCYCLECOUNTER
945 { 86, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #86 = G_INTRINSIC_ROUNDEVEN
946 { 85, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #85 = G_INTRINSIC_LLRINT
947 { 84, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #84 = G_INTRINSIC_LRINT
948 { 83, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #83 = G_INTRINSIC_ROUND
949 { 82, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #82 = G_INTRINSIC_TRUNC
950 { 81, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #81 = G_INTRINSIC_FPTRUNC_ROUND
951 { 80, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #80 = G_CONSTANT_FOLD_BARRIER
952 { 79, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #79 = G_FREEZE
953 { 78, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #78 = G_BITCAST
954 { 77, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #77 = G_INTTOPTR
955 { 76, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #76 = G_PTRTOINT
956 { 75, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #75 = G_CONCAT_VECTORS
957 { 74, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR_TRUNC
958 { 73, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #73 = G_BUILD_VECTOR
959 { 72, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #72 = G_MERGE_VALUES
960 { 71, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #71 = G_INSERT
961 { 70, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #70 = G_UNMERGE_VALUES
962 { 69, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #69 = G_EXTRACT
963 { 68, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #68 = G_CONSTANT_POOL
964 { 67, 5, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #67 = G_PTRAUTH_GLOBAL_VALUE
965 { 66, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #66 = G_GLOBAL_VALUE
966 { 65, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #65 = G_FRAME_INDEX
967 { 64, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #64 = G_PHI
968 { 63, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #63 = G_IMPLICIT_DEF
969 { 62, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #62 = G_XOR
970 { 61, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #61 = G_OR
971 { 60, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #60 = G_AND
972 { 59, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #59 = G_UDIVREM
973 { 58, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #58 = G_SDIVREM
974 { 57, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #57 = G_UREM
975 { 56, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #56 = G_SREM
976 { 55, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #55 = G_UDIV
977 { 54, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #54 = G_SDIV
978 { 53, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #53 = G_MUL
979 { 52, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #52 = G_SUB
980 { 51, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #51 = G_ADD
981 { 50, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #50 = G_ASSERT_ALIGN
982 { 49, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #49 = G_ASSERT_ZEXT
983 { 48, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #48 = G_ASSERT_SEXT
984 { 47, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_GLUE
985 { 46, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_LOOP
986 { 45, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ANCHOR
987 { 44, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #44 = CONVERGENCECTRL_ENTRY
988 { 43, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #43 = JUMP_TABLE_DEBUG_INFO
989 { 42, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #42 = MEMBARRIER
990 { 41, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL
991 { 40, 3, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
992 { 39, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL
993 { 38, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL
994 { 37, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT
995 { 36, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #36 = PATCHABLE_RET
996 { 35, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER
997 { 34, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #34 = PATCHABLE_OP
998 { 33, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #33 = FAULTING_OP
999 { 32, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE
1000 { 31, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #31 = STATEPOINT
1001 { 30, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG
1002 { 29, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP
1003 { 28, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD
1004 { 27, 6, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #27 = PATCHPOINT
1005 { 26, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #26 = FENTRY_CALL
1006 { 25, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #25 = STACKMAP
1007 { 24, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #24 = ARITH_FENCE
1008 { 23, 4, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #23 = PSEUDO_PROBE
1009 { 22, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #22 = LIFETIME_END
1010 { 21, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #21 = LIFETIME_START
1011 { 20, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #20 = BUNDLE
1012 { 19, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #19 = COPY
1013 { 18, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #18 = REG_SEQUENCE
1014 { 17, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #17 = DBG_LABEL
1015 { 16, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #16 = DBG_PHI
1016 { 15, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #15 = DBG_INSTR_REF
1017 { 14, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST
1018 { 13, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #13 = DBG_VALUE
1019 { 12, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS
1020 { 11, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #11 = SUBREG_TO_REG
1021 { 10, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
1022 { 9, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #9 = INSERT_SUBREG
1023 { 8, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
1024 { 7, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #7 = KILL
1025 { 6, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
1026 { 5, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #5 = GC_LABEL
1027 { 4, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #4 = EH_LABEL
1028 { 3, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
1029 { 2, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #2 = INLINEASM_BR
1030 { 1, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1 = INLINEASM
1031 { 0, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #0 = PHI
1032 }, {
1033 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1034 /* 1 */
1035 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1036 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1037 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1038 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1039 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1040 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1041 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1042 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1043 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1044 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1045 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1046 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1047 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1048 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1049 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1050 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1051 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1052 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1053 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1054 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1055 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1056 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1057 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1058 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1059 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1060 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1061 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1062 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1063 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1064 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1065 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1066 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1067 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1068 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1069 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1070 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1071 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1072 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1073 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1074 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1075 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1076 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1077 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1078 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1079 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1080 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1081 /* 152 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1082 /* 155 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1083 /* 159 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1084 /* 165 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1085 /* 171 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1086 /* 177 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1087 /* 183 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1088 /* 189 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1089 /* 195 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1090 /* 201 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1091 /* 207 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1092 /* 210 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1093 /* 213 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1094 /* 216 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1095 /* 219 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1096 /* 221 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1097 /* 224 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1098 /* 227 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1099 /* 231 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1100 /* 235 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1101 /* 239 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1102 /* 243 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1103 /* 244 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1104 /* 247 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1105 /* 250 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1106 /* 253 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1107 /* 256 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1108 /* 259 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1109 /* 261 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1110 /* 263 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1111 /* 265 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1112 /* 267 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1113 /* 269 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1114 /* 271 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1115 /* 273 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1116 /* 276 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1117 /* 280 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1118 }, {
1119 /* 0 */
1120 /* 0 */ BPF::R11, BPF::R11,
1121 /* 2 */ BPF::R0, BPF::R0,
1122 /* 4 */ BPF::W0, BPF::W0,
1123 /* 6 */ BPF::R11, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
1124 /* 13 */ BPF::R6, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
1125 }
1126};
1127
1128
1129#ifdef __GNUC__
1130#pragma GCC diagnostic push
1131#pragma GCC diagnostic ignored "-Woverlength-strings"
1132#endif
1133extern const char BPFInstrNameData[] = {
1134 /* 0 */ "G_FLOG10\0"
1135 /* 9 */ "G_FEXP10\0"
1136 /* 18 */ "LDB32\0"
1137 /* 24 */ "STB32\0"
1138 /* 30 */ "CORE_LD32\0"
1139 /* 40 */ "BE32\0"
1140 /* 45 */ "LE32\0"
1141 /* 50 */ "LDH32\0"
1142 /* 56 */ "STH32\0"
1143 /* 62 */ "BSWAP32\0"
1144 /* 70 */ "XFADDW32\0"
1145 /* 79 */ "XADDW32\0"
1146 /* 87 */ "LDW32\0"
1147 /* 93 */ "XFANDW32\0"
1148 /* 102 */ "XANDW32\0"
1149 /* 110 */ "CMPXCHGW32\0"
1150 /* 121 */ "XFORW32\0"
1151 /* 129 */ "XFXORW32\0"
1152 /* 138 */ "XXORW32\0"
1153 /* 146 */ "STW32\0"
1154 /* 152 */ "Select_Ri_64_32\0"
1155 /* 168 */ "Select_64_32\0"
1156 /* 181 */ "NEG_32\0"
1157 /* 188 */ "Select_Ri_32\0"
1158 /* 201 */ "SRA_ri_32\0"
1159 /* 211 */ "SUB_ri_32\0"
1160 /* 221 */ "ADD_ri_32\0"
1161 /* 231 */ "AND_ri_32\0"
1162 /* 241 */ "SMOD_ri_32\0"
1163 /* 252 */ "JSGE_ri_32\0"
1164 /* 263 */ "JUGE_ri_32\0"
1165 /* 274 */ "JSLE_ri_32\0"
1166 /* 285 */ "JULE_ri_32\0"
1167 /* 296 */ "JNE_ri_32\0"
1168 /* 306 */ "SLL_ri_32\0"
1169 /* 316 */ "SRL_ri_32\0"
1170 /* 326 */ "MUL_ri_32\0"
1171 /* 336 */ "JEQ_ri_32\0"
1172 /* 346 */ "XOR_ri_32\0"
1173 /* 356 */ "JSET_ri_32\0"
1174 /* 367 */ "JSGT_ri_32\0"
1175 /* 378 */ "JUGT_ri_32\0"
1176 /* 389 */ "JSLT_ri_32\0"
1177 /* 400 */ "JULT_ri_32\0"
1178 /* 411 */ "SDIV_ri_32\0"
1179 /* 422 */ "MOV_ri_32\0"
1180 /* 432 */ "SRA_rr_32\0"
1181 /* 442 */ "SUB_rr_32\0"
1182 /* 452 */ "ADD_rr_32\0"
1183 /* 462 */ "AND_rr_32\0"
1184 /* 472 */ "SMOD_rr_32\0"
1185 /* 483 */ "JSGE_rr_32\0"
1186 /* 494 */ "JUGE_rr_32\0"
1187 /* 505 */ "JSLE_rr_32\0"
1188 /* 516 */ "JULE_rr_32\0"
1189 /* 527 */ "JNE_rr_32\0"
1190 /* 537 */ "SLL_rr_32\0"
1191 /* 547 */ "SRL_rr_32\0"
1192 /* 557 */ "MUL_rr_32\0"
1193 /* 567 */ "JEQ_rr_32\0"
1194 /* 577 */ "XOR_rr_32\0"
1195 /* 587 */ "JSET_rr_32\0"
1196 /* 598 */ "JSGT_rr_32\0"
1197 /* 609 */ "JUGT_rr_32\0"
1198 /* 620 */ "JSLT_rr_32\0"
1199 /* 631 */ "JULT_rr_32\0"
1200 /* 642 */ "SDIV_rr_32\0"
1201 /* 653 */ "MOV_rr_32\0"
1202 /* 663 */ "MOVSX_rr_32\0"
1203 /* 675 */ "Select_32\0"
1204 /* 685 */ "G_FLOG2\0"
1205 /* 693 */ "G_FEXP2\0"
1206 /* 701 */ "CORE_LD64\0"
1207 /* 711 */ "BE64\0"
1208 /* 716 */ "LE64\0"
1209 /* 721 */ "BSWAP64\0"
1210 /* 729 */ "MOV_32_64\0"
1211 /* 739 */ "Select_Ri_32_64\0"
1212 /* 755 */ "Select_32_64\0"
1213 /* 768 */ "NEG_64\0"
1214 /* 775 */ "LD_imm64\0"
1215 /* 784 */ "BE16\0"
1216 /* 789 */ "LE16\0"
1217 /* 794 */ "BSWAP16\0"
1218 /* 802 */ "MOVSX_rr_32_16\0"
1219 /* 817 */ "MOVSX_rr_16\0"
1220 /* 829 */ "MOVSX_rr_32_8\0"
1221 /* 843 */ "MOVSX_rr_8\0"
1222 /* 854 */ "G_FMA\0"
1223 /* 860 */ "G_STRICT_FMA\0"
1224 /* 873 */ "LDB\0"
1225 /* 877 */ "STB\0"
1226 /* 881 */ "G_FSUB\0"
1227 /* 888 */ "G_STRICT_FSUB\0"
1228 /* 902 */ "G_ATOMICRMW_FSUB\0"
1229 /* 919 */ "G_SUB\0"
1230 /* 925 */ "G_ATOMICRMW_SUB\0"
1231 /* 941 */ "LD_IND_B\0"
1232 /* 950 */ "LD_ABS_B\0"
1233 /* 959 */ "G_INTRINSIC\0"
1234 /* 971 */ "G_FPTRUNC\0"
1235 /* 981 */ "G_INTRINSIC_TRUNC\0"
1236 /* 999 */ "G_TRUNC\0"
1237 /* 1007 */ "G_BUILD_VECTOR_TRUNC\0"
1238 /* 1028 */ "G_DYN_STACKALLOC\0"
1239 /* 1045 */ "G_FMAD\0"
1240 /* 1052 */ "G_INDEXED_SEXTLOAD\0"
1241 /* 1071 */ "G_SEXTLOAD\0"
1242 /* 1082 */ "G_INDEXED_ZEXTLOAD\0"
1243 /* 1101 */ "G_ZEXTLOAD\0"
1244 /* 1112 */ "G_INDEXED_LOAD\0"
1245 /* 1127 */ "G_LOAD\0"
1246 /* 1134 */ "G_VECREDUCE_FADD\0"
1247 /* 1151 */ "G_FADD\0"
1248 /* 1158 */ "G_VECREDUCE_SEQ_FADD\0"
1249 /* 1179 */ "G_STRICT_FADD\0"
1250 /* 1193 */ "G_ATOMICRMW_FADD\0"
1251 /* 1210 */ "G_VECREDUCE_ADD\0"
1252 /* 1226 */ "G_ADD\0"
1253 /* 1232 */ "G_PTR_ADD\0"
1254 /* 1242 */ "G_ATOMICRMW_ADD\0"
1255 /* 1258 */ "XFADDD\0"
1256 /* 1265 */ "XADDD\0"
1257 /* 1271 */ "LDD\0"
1258 /* 1275 */ "XFANDD\0"
1259 /* 1282 */ "XANDD\0"
1260 /* 1288 */ "CMPXCHGD\0"
1261 /* 1297 */ "G_ATOMICRMW_NAND\0"
1262 /* 1314 */ "G_VECREDUCE_AND\0"
1263 /* 1330 */ "G_AND\0"
1264 /* 1336 */ "G_ATOMICRMW_AND\0"
1265 /* 1352 */ "LIFETIME_END\0"
1266 /* 1365 */ "JCOND\0"
1267 /* 1371 */ "G_BRCOND\0"
1268 /* 1380 */ "G_LLROUND\0"
1269 /* 1390 */ "G_LROUND\0"
1270 /* 1399 */ "G_INTRINSIC_ROUND\0"
1271 /* 1417 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
1272 /* 1443 */ "LOAD_STACK_GUARD\0"
1273 /* 1460 */ "XFORD\0"
1274 /* 1466 */ "XFXORD\0"
1275 /* 1473 */ "XXORD\0"
1276 /* 1479 */ "STD\0"
1277 /* 1483 */ "PSEUDO_PROBE\0"
1278 /* 1496 */ "G_SSUBE\0"
1279 /* 1504 */ "G_USUBE\0"
1280 /* 1512 */ "G_FENCE\0"
1281 /* 1520 */ "ARITH_FENCE\0"
1282 /* 1532 */ "REG_SEQUENCE\0"
1283 /* 1545 */ "G_SADDE\0"
1284 /* 1553 */ "G_UADDE\0"
1285 /* 1561 */ "G_GET_FPMODE\0"
1286 /* 1574 */ "G_RESET_FPMODE\0"
1287 /* 1589 */ "G_SET_FPMODE\0"
1288 /* 1602 */ "G_FMINNUM_IEEE\0"
1289 /* 1617 */ "G_FMAXNUM_IEEE\0"
1290 /* 1632 */ "G_VSCALE\0"
1291 /* 1641 */ "G_JUMP_TABLE\0"
1292 /* 1654 */ "BUNDLE\0"
1293 /* 1661 */ "G_MEMCPY_INLINE\0"
1294 /* 1677 */ "LOCAL_ESCAPE\0"
1295 /* 1690 */ "G_STACKRESTORE\0"
1296 /* 1705 */ "G_INDEXED_STORE\0"
1297 /* 1721 */ "G_STORE\0"
1298 /* 1729 */ "G_BITREVERSE\0"
1299 /* 1742 */ "DBG_VALUE\0"
1300 /* 1752 */ "G_GLOBAL_VALUE\0"
1301 /* 1767 */ "G_PTRAUTH_GLOBAL_VALUE\0"
1302 /* 1790 */ "CONVERGENCECTRL_GLUE\0"
1303 /* 1811 */ "G_STACKSAVE\0"
1304 /* 1823 */ "G_MEMMOVE\0"
1305 /* 1833 */ "G_FREEZE\0"
1306 /* 1842 */ "G_FCANONICALIZE\0"
1307 /* 1858 */ "G_CTLZ_ZERO_UNDEF\0"
1308 /* 1876 */ "G_CTTZ_ZERO_UNDEF\0"
1309 /* 1894 */ "G_IMPLICIT_DEF\0"
1310 /* 1909 */ "DBG_INSTR_REF\0"
1311 /* 1923 */ "G_FNEG\0"
1312 /* 1930 */ "EXTRACT_SUBREG\0"
1313 /* 1945 */ "INSERT_SUBREG\0"
1314 /* 1959 */ "G_SEXT_INREG\0"
1315 /* 1972 */ "SUBREG_TO_REG\0"
1316 /* 1986 */ "G_ATOMIC_CMPXCHG\0"
1317 /* 2003 */ "G_ATOMICRMW_XCHG\0"
1318 /* 2020 */ "G_FLOG\0"
1319 /* 2027 */ "G_VAARG\0"
1320 /* 2035 */ "PREALLOCATED_ARG\0"
1321 /* 2052 */ "G_PREFETCH\0"
1322 /* 2063 */ "LDH\0"
1323 /* 2067 */ "G_SMULH\0"
1324 /* 2075 */ "G_UMULH\0"
1325 /* 2083 */ "G_FTANH\0"
1326 /* 2091 */ "G_FSINH\0"
1327 /* 2099 */ "G_FCOSH\0"
1328 /* 2107 */ "STH\0"
1329 /* 2111 */ "LD_IND_H\0"
1330 /* 2120 */ "LD_ABS_H\0"
1331 /* 2129 */ "DBG_PHI\0"
1332 /* 2137 */ "G_FPTOSI\0"
1333 /* 2146 */ "G_FPTOUI\0"
1334 /* 2155 */ "G_FPOWI\0"
1335 /* 2163 */ "G_PTRMASK\0"
1336 /* 2173 */ "JAL\0"
1337 /* 2177 */ "GC_LABEL\0"
1338 /* 2186 */ "DBG_LABEL\0"
1339 /* 2196 */ "EH_LABEL\0"
1340 /* 2205 */ "ANNOTATION_LABEL\0"
1341 /* 2222 */ "ICALL_BRANCH_FUNNEL\0"
1342 /* 2242 */ "G_FSHL\0"
1343 /* 2249 */ "G_SHL\0"
1344 /* 2255 */ "G_FCEIL\0"
1345 /* 2263 */ "PATCHABLE_TAIL_CALL\0"
1346 /* 2283 */ "PATCHABLE_TYPED_EVENT_CALL\0"
1347 /* 2310 */ "PATCHABLE_EVENT_CALL\0"
1348 /* 2331 */ "FENTRY_CALL\0"
1349 /* 2343 */ "KILL\0"
1350 /* 2348 */ "G_CONSTANT_POOL\0"
1351 /* 2364 */ "JMPL\0"
1352 /* 2369 */ "G_ROTL\0"
1353 /* 2376 */ "G_VECREDUCE_FMUL\0"
1354 /* 2393 */ "G_FMUL\0"
1355 /* 2400 */ "G_VECREDUCE_SEQ_FMUL\0"
1356 /* 2421 */ "G_STRICT_FMUL\0"
1357 /* 2435 */ "G_VECREDUCE_MUL\0"
1358 /* 2451 */ "G_MUL\0"
1359 /* 2457 */ "G_FREM\0"
1360 /* 2464 */ "G_STRICT_FREM\0"
1361 /* 2478 */ "G_SREM\0"
1362 /* 2485 */ "G_UREM\0"
1363 /* 2492 */ "G_SDIVREM\0"
1364 /* 2502 */ "G_UDIVREM\0"
1365 /* 2512 */ "INLINEASM\0"
1366 /* 2522 */ "G_VECREDUCE_FMINIMUM\0"
1367 /* 2543 */ "G_FMINIMUM\0"
1368 /* 2554 */ "G_VECREDUCE_FMAXIMUM\0"
1369 /* 2575 */ "G_FMAXIMUM\0"
1370 /* 2586 */ "G_FMINNUM\0"
1371 /* 2596 */ "G_FMAXNUM\0"
1372 /* 2606 */ "G_FATAN\0"
1373 /* 2614 */ "G_FTAN\0"
1374 /* 2621 */ "G_INTRINSIC_ROUNDEVEN\0"
1375 /* 2643 */ "G_ASSERT_ALIGN\0"
1376 /* 2658 */ "G_FCOPYSIGN\0"
1377 /* 2670 */ "G_VECREDUCE_FMIN\0"
1378 /* 2687 */ "G_ATOMICRMW_FMIN\0"
1379 /* 2704 */ "G_VECREDUCE_SMIN\0"
1380 /* 2721 */ "G_SMIN\0"
1381 /* 2728 */ "G_VECREDUCE_UMIN\0"
1382 /* 2745 */ "G_UMIN\0"
1383 /* 2752 */ "G_ATOMICRMW_UMIN\0"
1384 /* 2769 */ "G_ATOMICRMW_MIN\0"
1385 /* 2785 */ "G_FASIN\0"
1386 /* 2793 */ "G_FSIN\0"
1387 /* 2800 */ "CFI_INSTRUCTION\0"
1388 /* 2816 */ "ADJCALLSTACKDOWN\0"
1389 /* 2833 */ "G_SSUBO\0"
1390 /* 2841 */ "G_USUBO\0"
1391 /* 2849 */ "G_SADDO\0"
1392 /* 2857 */ "G_UADDO\0"
1393 /* 2865 */ "JUMP_TABLE_DEBUG_INFO\0"
1394 /* 2887 */ "G_SMULO\0"
1395 /* 2895 */ "G_UMULO\0"
1396 /* 2903 */ "G_BZERO\0"
1397 /* 2911 */ "STACKMAP\0"
1398 /* 2920 */ "G_DEBUGTRAP\0"
1399 /* 2932 */ "G_UBSANTRAP\0"
1400 /* 2944 */ "G_TRAP\0"
1401 /* 2951 */ "G_ATOMICRMW_UDEC_WRAP\0"
1402 /* 2973 */ "G_ATOMICRMW_UINC_WRAP\0"
1403 /* 2995 */ "G_BSWAP\0"
1404 /* 3003 */ "G_SITOFP\0"
1405 /* 3012 */ "G_UITOFP\0"
1406 /* 3021 */ "G_FCMP\0"
1407 /* 3028 */ "G_ICMP\0"
1408 /* 3035 */ "G_SCMP\0"
1409 /* 3042 */ "G_UCMP\0"
1410 /* 3049 */ "JMP\0"
1411 /* 3053 */ "NOP\0"
1412 /* 3057 */ "CONVERGENCECTRL_LOOP\0"
1413 /* 3078 */ "G_CTPOP\0"
1414 /* 3086 */ "PATCHABLE_OP\0"
1415 /* 3099 */ "FAULTING_OP\0"
1416 /* 3111 */ "ADJCALLSTACKUP\0"
1417 /* 3126 */ "PREALLOCATED_SETUP\0"
1418 /* 3145 */ "G_FLDEXP\0"
1419 /* 3154 */ "G_STRICT_FLDEXP\0"
1420 /* 3170 */ "G_FEXP\0"
1421 /* 3177 */ "G_FFREXP\0"
1422 /* 3186 */ "G_BR\0"
1423 /* 3191 */ "INLINEASM_BR\0"
1424 /* 3204 */ "G_BLOCK_ADDR\0"
1425 /* 3217 */ "MEMBARRIER\0"
1426 /* 3228 */ "G_CONSTANT_FOLD_BARRIER\0"
1427 /* 3252 */ "PATCHABLE_FUNCTION_ENTER\0"
1428 /* 3277 */ "G_READCYCLECOUNTER\0"
1429 /* 3296 */ "G_READSTEADYCOUNTER\0"
1430 /* 3316 */ "G_READ_REGISTER\0"
1431 /* 3332 */ "G_WRITE_REGISTER\0"
1432 /* 3349 */ "G_ASHR\0"
1433 /* 3356 */ "G_FSHR\0"
1434 /* 3363 */ "G_LSHR\0"
1435 /* 3370 */ "CONVERGENCECTRL_ANCHOR\0"
1436 /* 3393 */ "G_FFLOOR\0"
1437 /* 3402 */ "G_EXTRACT_SUBVECTOR\0"
1438 /* 3422 */ "G_INSERT_SUBVECTOR\0"
1439 /* 3441 */ "G_BUILD_VECTOR\0"
1440 /* 3456 */ "G_SHUFFLE_VECTOR\0"
1441 /* 3473 */ "G_SPLAT_VECTOR\0"
1442 /* 3488 */ "G_VECREDUCE_XOR\0"
1443 /* 3504 */ "G_XOR\0"
1444 /* 3510 */ "G_ATOMICRMW_XOR\0"
1445 /* 3526 */ "G_VECREDUCE_OR\0"
1446 /* 3541 */ "G_OR\0"
1447 /* 3546 */ "G_ATOMICRMW_OR\0"
1448 /* 3561 */ "G_ROTR\0"
1449 /* 3568 */ "G_INTTOPTR\0"
1450 /* 3579 */ "G_FABS\0"
1451 /* 3586 */ "G_ABS\0"
1452 /* 3592 */ "G_UNMERGE_VALUES\0"
1453 /* 3609 */ "G_MERGE_VALUES\0"
1454 /* 3624 */ "G_FACOS\0"
1455 /* 3632 */ "G_FCOS\0"
1456 /* 3639 */ "G_CONCAT_VECTORS\0"
1457 /* 3656 */ "COPY_TO_REGCLASS\0"
1458 /* 3673 */ "G_IS_FPCLASS\0"
1459 /* 3686 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
1460 /* 3716 */ "G_VECTOR_COMPRESS\0"
1461 /* 3734 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
1462 /* 3761 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
1463 /* 3799 */ "G_SSUBSAT\0"
1464 /* 3809 */ "G_USUBSAT\0"
1465 /* 3819 */ "G_SADDSAT\0"
1466 /* 3829 */ "G_UADDSAT\0"
1467 /* 3839 */ "G_SSHLSAT\0"
1468 /* 3849 */ "G_USHLSAT\0"
1469 /* 3859 */ "G_SMULFIXSAT\0"
1470 /* 3872 */ "G_UMULFIXSAT\0"
1471 /* 3885 */ "G_SDIVFIXSAT\0"
1472 /* 3898 */ "G_UDIVFIXSAT\0"
1473 /* 3911 */ "G_EXTRACT\0"
1474 /* 3921 */ "G_SELECT\0"
1475 /* 3930 */ "G_BRINDIRECT\0"
1476 /* 3943 */ "PATCHABLE_RET\0"
1477 /* 3957 */ "G_MEMSET\0"
1478 /* 3966 */ "CORE_SHIFT\0"
1479 /* 3977 */ "PATCHABLE_FUNCTION_EXIT\0"
1480 /* 4001 */ "G_BRJT\0"
1481 /* 4008 */ "G_EXTRACT_VECTOR_ELT\0"
1482 /* 4029 */ "G_INSERT_VECTOR_ELT\0"
1483 /* 4049 */ "G_FCONSTANT\0"
1484 /* 4061 */ "G_CONSTANT\0"
1485 /* 4072 */ "G_INTRINSIC_CONVERGENT\0"
1486 /* 4095 */ "STATEPOINT\0"
1487 /* 4106 */ "PATCHPOINT\0"
1488 /* 4117 */ "G_PTRTOINT\0"
1489 /* 4128 */ "G_FRINT\0"
1490 /* 4136 */ "G_INTRINSIC_LLRINT\0"
1491 /* 4155 */ "G_INTRINSIC_LRINT\0"
1492 /* 4173 */ "G_FNEARBYINT\0"
1493 /* 4186 */ "G_VASTART\0"
1494 /* 4196 */ "LIFETIME_START\0"
1495 /* 4211 */ "G_INVOKE_REGION_START\0"
1496 /* 4233 */ "G_INSERT\0"
1497 /* 4242 */ "G_FSQRT\0"
1498 /* 4250 */ "G_STRICT_FSQRT\0"
1499 /* 4265 */ "G_BITCAST\0"
1500 /* 4275 */ "G_ADDRSPACE_CAST\0"
1501 /* 4292 */ "ADDR_SPACE_CAST\0"
1502 /* 4308 */ "DBG_VALUE_LIST\0"
1503 /* 4323 */ "CORE_ST\0"
1504 /* 4331 */ "G_FPEXT\0"
1505 /* 4339 */ "G_SEXT\0"
1506 /* 4346 */ "G_ASSERT_SEXT\0"
1507 /* 4360 */ "G_ANYEXT\0"
1508 /* 4369 */ "G_ZEXT\0"
1509 /* 4376 */ "G_ASSERT_ZEXT\0"
1510 /* 4390 */ "G_FDIV\0"
1511 /* 4397 */ "G_STRICT_FDIV\0"
1512 /* 4411 */ "G_SDIV\0"
1513 /* 4418 */ "G_UDIV\0"
1514 /* 4425 */ "G_GET_FPENV\0"
1515 /* 4437 */ "G_RESET_FPENV\0"
1516 /* 4451 */ "G_SET_FPENV\0"
1517 /* 4463 */ "XADDW\0"
1518 /* 4469 */ "LDW\0"
1519 /* 4473 */ "G_FPOW\0"
1520 /* 4480 */ "STW\0"
1521 /* 4484 */ "LD_IND_W\0"
1522 /* 4493 */ "LD_ABS_W\0"
1523 /* 4502 */ "G_VECREDUCE_FMAX\0"
1524 /* 4519 */ "G_ATOMICRMW_FMAX\0"
1525 /* 4536 */ "G_VECREDUCE_SMAX\0"
1526 /* 4553 */ "G_SMAX\0"
1527 /* 4560 */ "G_VECREDUCE_UMAX\0"
1528 /* 4577 */ "G_UMAX\0"
1529 /* 4584 */ "G_ATOMICRMW_UMAX\0"
1530 /* 4601 */ "G_ATOMICRMW_MAX\0"
1531 /* 4617 */ "G_FRAME_INDEX\0"
1532 /* 4631 */ "G_SBFX\0"
1533 /* 4638 */ "G_UBFX\0"
1534 /* 4645 */ "G_SMULFIX\0"
1535 /* 4655 */ "G_UMULFIX\0"
1536 /* 4665 */ "G_SDIVFIX\0"
1537 /* 4675 */ "G_UDIVFIX\0"
1538 /* 4685 */ "JALX\0"
1539 /* 4690 */ "LDBSX\0"
1540 /* 4696 */ "LDHSX\0"
1541 /* 4702 */ "LDWSX\0"
1542 /* 4708 */ "G_MEMCPY\0"
1543 /* 4717 */ "COPY\0"
1544 /* 4722 */ "CONVERGENCECTRL_ENTRY\0"
1545 /* 4744 */ "G_CTLZ\0"
1546 /* 4751 */ "G_CTTZ\0"
1547 /* 4758 */ "Select_Ri\0"
1548 /* 4768 */ "SRA_ri\0"
1549 /* 4775 */ "SUB_ri\0"
1550 /* 4782 */ "ADD_ri\0"
1551 /* 4789 */ "AND_ri\0"
1552 /* 4796 */ "SMOD_ri\0"
1553 /* 4804 */ "JSGE_ri\0"
1554 /* 4812 */ "JUGE_ri\0"
1555 /* 4820 */ "JSLE_ri\0"
1556 /* 4828 */ "JULE_ri\0"
1557 /* 4836 */ "JNE_ri\0"
1558 /* 4843 */ "FI_ri\0"
1559 /* 4849 */ "SLL_ri\0"
1560 /* 4856 */ "SRL_ri\0"
1561 /* 4863 */ "MUL_ri\0"
1562 /* 4870 */ "JEQ_ri\0"
1563 /* 4877 */ "XOR_ri\0"
1564 /* 4884 */ "JSET_ri\0"
1565 /* 4892 */ "JSGT_ri\0"
1566 /* 4900 */ "JUGT_ri\0"
1567 /* 4908 */ "JSLT_ri\0"
1568 /* 4916 */ "JULT_ri\0"
1569 /* 4924 */ "SDIV_ri\0"
1570 /* 4932 */ "MOV_ri\0"
1571 /* 4939 */ "STB_imm\0"
1572 /* 4947 */ "STD_imm\0"
1573 /* 4955 */ "STH_imm\0"
1574 /* 4963 */ "STW_imm\0"
1575 /* 4971 */ "LD_pseudo\0"
1576 /* 4981 */ "SRA_rr\0"
1577 /* 4988 */ "SUB_rr\0"
1578 /* 4995 */ "ADD_rr\0"
1579 /* 5002 */ "AND_rr\0"
1580 /* 5009 */ "SMOD_rr\0"
1581 /* 5017 */ "JSGE_rr\0"
1582 /* 5025 */ "JUGE_rr\0"
1583 /* 5033 */ "JSLE_rr\0"
1584 /* 5041 */ "JULE_rr\0"
1585 /* 5049 */ "JNE_rr\0"
1586 /* 5056 */ "SLL_rr\0"
1587 /* 5063 */ "SRL_rr\0"
1588 /* 5070 */ "MUL_rr\0"
1589 /* 5077 */ "JEQ_rr\0"
1590 /* 5084 */ "XOR_rr\0"
1591 /* 5091 */ "JSET_rr\0"
1592 /* 5099 */ "JSGT_rr\0"
1593 /* 5107 */ "JUGT_rr\0"
1594 /* 5115 */ "JSLT_rr\0"
1595 /* 5123 */ "JULT_rr\0"
1596 /* 5131 */ "SDIV_rr\0"
1597 /* 5139 */ "MOV_rr\0"
1598 /* 5146 */ "Select\0"
1599};
1600#ifdef __GNUC__
1601#pragma GCC diagnostic pop
1602#endif
1603
1604extern const unsigned BPFInstrNameIndices[] = {
1605 2133U, 2512U, 3191U, 2800U, 2196U, 2177U, 2205U, 2343U,
1606 1930U, 1945U, 1896U, 1972U, 3656U, 1742U, 4308U, 1909U,
1607 2129U, 2186U, 1532U, 4717U, 1654U, 4196U, 1352U, 1483U,
1608 1520U, 2911U, 2331U, 4106U, 1443U, 3126U, 2035U, 4095U,
1609 1677U, 3099U, 3086U, 3252U, 3943U, 3977U, 2263U, 2310U,
1610 2283U, 2222U, 3217U, 2865U, 4722U, 3370U, 3057U, 1790U,
1611 4346U, 4376U, 2643U, 1226U, 919U, 2451U, 4411U, 4418U,
1612 2478U, 2485U, 2492U, 2502U, 1330U, 3541U, 3504U, 1894U,
1613 2131U, 4617U, 1752U, 1767U, 2348U, 3911U, 3592U, 4233U,
1614 3609U, 3441U, 1007U, 3639U, 4117U, 3568U, 4265U, 1833U,
1615 3228U, 1417U, 981U, 1399U, 4155U, 4136U, 2621U, 3277U,
1616 3296U, 1127U, 1071U, 1101U, 1112U, 1052U, 1082U, 1721U,
1617 1705U, 3686U, 1986U, 2003U, 1242U, 925U, 1336U, 1297U,
1618 3546U, 3510U, 4601U, 2769U, 4584U, 2752U, 1193U, 902U,
1619 4519U, 2687U, 2973U, 2951U, 1512U, 2052U, 1371U, 3930U,
1620 4211U, 959U, 3734U, 4072U, 3761U, 4360U, 999U, 4061U,
1621 4049U, 4186U, 2027U, 4339U, 1959U, 4369U, 2249U, 3363U,
1622 3349U, 2242U, 3356U, 3561U, 2369U, 3028U, 3021U, 3035U,
1623 3042U, 3921U, 2857U, 1553U, 2841U, 1504U, 2849U, 1545U,
1624 2833U, 1496U, 2895U, 2887U, 2075U, 2067U, 3829U, 3819U,
1625 3809U, 3799U, 3849U, 3839U, 4645U, 4655U, 3859U, 3872U,
1626 4665U, 4675U, 3885U, 3898U, 1151U, 881U, 2393U, 854U,
1627 1045U, 4390U, 2457U, 4473U, 2155U, 3170U, 693U, 9U,
1628 2020U, 685U, 0U, 3145U, 3177U, 1923U, 4331U, 971U,
1629 2137U, 2146U, 3003U, 3012U, 3579U, 2658U, 3673U, 1842U,
1630 2586U, 2596U, 1602U, 1617U, 2543U, 2575U, 4425U, 4451U,
1631 4437U, 1561U, 1589U, 1574U, 1232U, 2163U, 2721U, 4553U,
1632 2745U, 4577U, 3586U, 1390U, 1380U, 3186U, 4001U, 1632U,
1633 3422U, 3402U, 4029U, 4008U, 3456U, 3473U, 3716U, 4751U,
1634 1876U, 4744U, 1858U, 3078U, 2995U, 1729U, 2255U, 3632U,
1635 2793U, 2614U, 3624U, 2785U, 2606U, 2099U, 2091U, 2083U,
1636 4242U, 3393U, 4128U, 4173U, 4275U, 3204U, 1641U, 1028U,
1637 1811U, 1690U, 1179U, 888U, 2421U, 4397U, 2464U, 860U,
1638 4250U, 3154U, 3316U, 3332U, 4708U, 1661U, 1823U, 3957U,
1639 2903U, 2944U, 2920U, 2932U, 1158U, 2400U, 1134U, 2376U,
1640 4502U, 2670U, 2554U, 2522U, 1210U, 2435U, 1314U, 3526U,
1641 3488U, 4536U, 2704U, 4560U, 2728U, 4631U, 4638U, 2816U,
1642 3111U, 4843U, 4710U, 5146U, 675U, 755U, 168U, 4758U,
1643 188U, 739U, 152U, 4292U, 4782U, 221U, 4995U, 452U,
1644 4789U, 231U, 5002U, 462U, 784U, 40U, 711U, 794U,
1645 62U, 721U, 1288U, 110U, 30U, 701U, 3966U, 4323U,
1646 4925U, 412U, 5132U, 643U, 2173U, 4685U, 1365U, 4870U,
1647 336U, 5077U, 567U, 3049U, 2364U, 4836U, 296U, 5049U,
1648 527U, 4884U, 356U, 5091U, 587U, 4804U, 252U, 5017U,
1649 483U, 4892U, 367U, 5099U, 598U, 4820U, 274U, 5033U,
1650 505U, 4908U, 389U, 5115U, 620U, 4812U, 263U, 5025U,
1651 494U, 4900U, 378U, 5107U, 609U, 4828U, 285U, 5041U,
1652 516U, 4916U, 400U, 5123U, 631U, 873U, 18U, 4690U,
1653 1271U, 2063U, 50U, 4696U, 4469U, 87U, 4702U, 950U,
1654 2120U, 4493U, 941U, 2111U, 4484U, 775U, 4971U, 789U,
1655 45U, 716U, 4797U, 242U, 5010U, 473U, 817U, 663U,
1656 802U, 829U, 843U, 729U, 4932U, 422U, 5139U, 653U,
1657 4863U, 326U, 5070U, 557U, 181U, 768U, 3053U, 4878U,
1658 347U, 5085U, 578U, 3953U, 4924U, 411U, 5131U, 642U,
1659 4849U, 306U, 5056U, 537U, 4796U, 241U, 5009U, 472U,
1660 4768U, 201U, 4981U, 432U, 4856U, 316U, 5063U, 547U,
1661 877U, 24U, 4939U, 1479U, 4947U, 2107U, 56U, 4955U,
1662 4480U, 146U, 4963U, 4775U, 211U, 4988U, 442U, 1265U,
1663 4463U, 79U, 1282U, 102U, 1291U, 113U, 1258U, 70U,
1664 1275U, 93U, 1460U, 121U, 1466U, 129U, 1468U, 131U,
1665 4877U, 346U, 5084U, 577U, 1473U, 138U,
1666};
1667
1668static inline void InitBPFMCInstrInfo(MCInstrInfo *II) {
1669 II->InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 486);
1670}
1671
1672} // end namespace llvm
1673#endif // GET_INSTRINFO_MC_DESC
1674
1675#ifdef GET_INSTRINFO_HEADER
1676#undef GET_INSTRINFO_HEADER
1677namespace llvm {
1678struct BPFGenInstrInfo : public TargetInstrInfo {
1679 explicit BPFGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1680 ~BPFGenInstrInfo() override = default;
1681
1682};
1683} // end namespace llvm
1684#endif // GET_INSTRINFO_HEADER
1685
1686#ifdef GET_INSTRINFO_HELPER_DECLS
1687#undef GET_INSTRINFO_HELPER_DECLS
1688
1689
1690#endif // GET_INSTRINFO_HELPER_DECLS
1691
1692#ifdef GET_INSTRINFO_HELPERS
1693#undef GET_INSTRINFO_HELPERS
1694
1695#endif // GET_INSTRINFO_HELPERS
1696
1697#ifdef GET_INSTRINFO_CTOR_DTOR
1698#undef GET_INSTRINFO_CTOR_DTOR
1699namespace llvm {
1700extern const BPFInstrTable BPFDescs;
1701extern const unsigned BPFInstrNameIndices[];
1702extern const char BPFInstrNameData[];
1703BPFGenInstrInfo::BPFGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1704 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1705 InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 486);
1706}
1707} // end namespace llvm
1708#endif // GET_INSTRINFO_CTOR_DTOR
1709
1710#ifdef GET_INSTRINFO_OPERAND_ENUM
1711#undef GET_INSTRINFO_OPERAND_ENUM
1712namespace llvm {
1713namespace BPF {
1714namespace OpName {
1715enum {
1716 OPERAND_LAST
1717};
1718} // end namespace OpName
1719} // end namespace BPF
1720} // end namespace llvm
1721#endif //GET_INSTRINFO_OPERAND_ENUM
1722
1723#ifdef GET_INSTRINFO_NAMED_OPS
1724#undef GET_INSTRINFO_NAMED_OPS
1725namespace llvm {
1726namespace BPF {
1727LLVM_READONLY
1728int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1729 return -1;
1730}
1731} // end namespace BPF
1732} // end namespace llvm
1733#endif //GET_INSTRINFO_NAMED_OPS
1734
1735#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1736#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1737namespace llvm {
1738namespace BPF {
1739namespace OpTypes {
1740enum OperandType {
1741 MEMri = 0,
1742 brtarget = 1,
1743 calltarget = 2,
1744 f32imm = 3,
1745 f64imm = 4,
1746 gpr_or_imm = 5,
1747 i1imm = 6,
1748 i8imm = 7,
1749 i16imm = 8,
1750 i32imm = 9,
1751 i64imm = 10,
1752 ptype0 = 11,
1753 ptype1 = 12,
1754 ptype2 = 13,
1755 ptype3 = 14,
1756 ptype4 = 15,
1757 ptype5 = 16,
1758 s16imm = 17,
1759 type0 = 18,
1760 type1 = 19,
1761 type2 = 20,
1762 type3 = 21,
1763 type4 = 22,
1764 type5 = 23,
1765 u64imm = 24,
1766 untyped_imm_0 = 25,
1767 GPR = 26,
1768 GPR32 = 27,
1769 OPERAND_TYPE_LIST_END
1770};
1771} // end namespace OpTypes
1772} // end namespace BPF
1773} // end namespace llvm
1774#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1775
1776#ifdef GET_INSTRINFO_OPERAND_TYPE
1777#undef GET_INSTRINFO_OPERAND_TYPE
1778namespace llvm {
1779namespace BPF {
1780LLVM_READONLY
1781static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
1782 static const uint16_t Offsets[] = {
1783 /* PHI */
1784 0,
1785 /* INLINEASM */
1786 1,
1787 /* INLINEASM_BR */
1788 1,
1789 /* CFI_INSTRUCTION */
1790 1,
1791 /* EH_LABEL */
1792 2,
1793 /* GC_LABEL */
1794 3,
1795 /* ANNOTATION_LABEL */
1796 4,
1797 /* KILL */
1798 5,
1799 /* EXTRACT_SUBREG */
1800 5,
1801 /* INSERT_SUBREG */
1802 8,
1803 /* IMPLICIT_DEF */
1804 12,
1805 /* SUBREG_TO_REG */
1806 13,
1807 /* COPY_TO_REGCLASS */
1808 17,
1809 /* DBG_VALUE */
1810 20,
1811 /* DBG_VALUE_LIST */
1812 20,
1813 /* DBG_INSTR_REF */
1814 20,
1815 /* DBG_PHI */
1816 20,
1817 /* DBG_LABEL */
1818 20,
1819 /* REG_SEQUENCE */
1820 21,
1821 /* COPY */
1822 23,
1823 /* BUNDLE */
1824 25,
1825 /* LIFETIME_START */
1826 25,
1827 /* LIFETIME_END */
1828 26,
1829 /* PSEUDO_PROBE */
1830 27,
1831 /* ARITH_FENCE */
1832 31,
1833 /* STACKMAP */
1834 33,
1835 /* FENTRY_CALL */
1836 35,
1837 /* PATCHPOINT */
1838 35,
1839 /* LOAD_STACK_GUARD */
1840 41,
1841 /* PREALLOCATED_SETUP */
1842 42,
1843 /* PREALLOCATED_ARG */
1844 43,
1845 /* STATEPOINT */
1846 46,
1847 /* LOCAL_ESCAPE */
1848 46,
1849 /* FAULTING_OP */
1850 48,
1851 /* PATCHABLE_OP */
1852 49,
1853 /* PATCHABLE_FUNCTION_ENTER */
1854 49,
1855 /* PATCHABLE_RET */
1856 49,
1857 /* PATCHABLE_FUNCTION_EXIT */
1858 49,
1859 /* PATCHABLE_TAIL_CALL */
1860 49,
1861 /* PATCHABLE_EVENT_CALL */
1862 49,
1863 /* PATCHABLE_TYPED_EVENT_CALL */
1864 51,
1865 /* ICALL_BRANCH_FUNNEL */
1866 54,
1867 /* MEMBARRIER */
1868 54,
1869 /* JUMP_TABLE_DEBUG_INFO */
1870 54,
1871 /* CONVERGENCECTRL_ENTRY */
1872 55,
1873 /* CONVERGENCECTRL_ANCHOR */
1874 56,
1875 /* CONVERGENCECTRL_LOOP */
1876 57,
1877 /* CONVERGENCECTRL_GLUE */
1878 59,
1879 /* G_ASSERT_SEXT */
1880 60,
1881 /* G_ASSERT_ZEXT */
1882 63,
1883 /* G_ASSERT_ALIGN */
1884 66,
1885 /* G_ADD */
1886 69,
1887 /* G_SUB */
1888 72,
1889 /* G_MUL */
1890 75,
1891 /* G_SDIV */
1892 78,
1893 /* G_UDIV */
1894 81,
1895 /* G_SREM */
1896 84,
1897 /* G_UREM */
1898 87,
1899 /* G_SDIVREM */
1900 90,
1901 /* G_UDIVREM */
1902 94,
1903 /* G_AND */
1904 98,
1905 /* G_OR */
1906 101,
1907 /* G_XOR */
1908 104,
1909 /* G_IMPLICIT_DEF */
1910 107,
1911 /* G_PHI */
1912 108,
1913 /* G_FRAME_INDEX */
1914 109,
1915 /* G_GLOBAL_VALUE */
1916 111,
1917 /* G_PTRAUTH_GLOBAL_VALUE */
1918 113,
1919 /* G_CONSTANT_POOL */
1920 118,
1921 /* G_EXTRACT */
1922 120,
1923 /* G_UNMERGE_VALUES */
1924 123,
1925 /* G_INSERT */
1926 125,
1927 /* G_MERGE_VALUES */
1928 129,
1929 /* G_BUILD_VECTOR */
1930 131,
1931 /* G_BUILD_VECTOR_TRUNC */
1932 133,
1933 /* G_CONCAT_VECTORS */
1934 135,
1935 /* G_PTRTOINT */
1936 137,
1937 /* G_INTTOPTR */
1938 139,
1939 /* G_BITCAST */
1940 141,
1941 /* G_FREEZE */
1942 143,
1943 /* G_CONSTANT_FOLD_BARRIER */
1944 145,
1945 /* G_INTRINSIC_FPTRUNC_ROUND */
1946 147,
1947 /* G_INTRINSIC_TRUNC */
1948 150,
1949 /* G_INTRINSIC_ROUND */
1950 152,
1951 /* G_INTRINSIC_LRINT */
1952 154,
1953 /* G_INTRINSIC_LLRINT */
1954 156,
1955 /* G_INTRINSIC_ROUNDEVEN */
1956 158,
1957 /* G_READCYCLECOUNTER */
1958 160,
1959 /* G_READSTEADYCOUNTER */
1960 161,
1961 /* G_LOAD */
1962 162,
1963 /* G_SEXTLOAD */
1964 164,
1965 /* G_ZEXTLOAD */
1966 166,
1967 /* G_INDEXED_LOAD */
1968 168,
1969 /* G_INDEXED_SEXTLOAD */
1970 173,
1971 /* G_INDEXED_ZEXTLOAD */
1972 178,
1973 /* G_STORE */
1974 183,
1975 /* G_INDEXED_STORE */
1976 185,
1977 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
1978 190,
1979 /* G_ATOMIC_CMPXCHG */
1980 195,
1981 /* G_ATOMICRMW_XCHG */
1982 199,
1983 /* G_ATOMICRMW_ADD */
1984 202,
1985 /* G_ATOMICRMW_SUB */
1986 205,
1987 /* G_ATOMICRMW_AND */
1988 208,
1989 /* G_ATOMICRMW_NAND */
1990 211,
1991 /* G_ATOMICRMW_OR */
1992 214,
1993 /* G_ATOMICRMW_XOR */
1994 217,
1995 /* G_ATOMICRMW_MAX */
1996 220,
1997 /* G_ATOMICRMW_MIN */
1998 223,
1999 /* G_ATOMICRMW_UMAX */
2000 226,
2001 /* G_ATOMICRMW_UMIN */
2002 229,
2003 /* G_ATOMICRMW_FADD */
2004 232,
2005 /* G_ATOMICRMW_FSUB */
2006 235,
2007 /* G_ATOMICRMW_FMAX */
2008 238,
2009 /* G_ATOMICRMW_FMIN */
2010 241,
2011 /* G_ATOMICRMW_UINC_WRAP */
2012 244,
2013 /* G_ATOMICRMW_UDEC_WRAP */
2014 247,
2015 /* G_FENCE */
2016 250,
2017 /* G_PREFETCH */
2018 252,
2019 /* G_BRCOND */
2020 256,
2021 /* G_BRINDIRECT */
2022 258,
2023 /* G_INVOKE_REGION_START */
2024 259,
2025 /* G_INTRINSIC */
2026 259,
2027 /* G_INTRINSIC_W_SIDE_EFFECTS */
2028 260,
2029 /* G_INTRINSIC_CONVERGENT */
2030 261,
2031 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
2032 262,
2033 /* G_ANYEXT */
2034 263,
2035 /* G_TRUNC */
2036 265,
2037 /* G_CONSTANT */
2038 267,
2039 /* G_FCONSTANT */
2040 269,
2041 /* G_VASTART */
2042 271,
2043 /* G_VAARG */
2044 272,
2045 /* G_SEXT */
2046 275,
2047 /* G_SEXT_INREG */
2048 277,
2049 /* G_ZEXT */
2050 280,
2051 /* G_SHL */
2052 282,
2053 /* G_LSHR */
2054 285,
2055 /* G_ASHR */
2056 288,
2057 /* G_FSHL */
2058 291,
2059 /* G_FSHR */
2060 295,
2061 /* G_ROTR */
2062 299,
2063 /* G_ROTL */
2064 302,
2065 /* G_ICMP */
2066 305,
2067 /* G_FCMP */
2068 309,
2069 /* G_SCMP */
2070 313,
2071 /* G_UCMP */
2072 316,
2073 /* G_SELECT */
2074 319,
2075 /* G_UADDO */
2076 323,
2077 /* G_UADDE */
2078 327,
2079 /* G_USUBO */
2080 332,
2081 /* G_USUBE */
2082 336,
2083 /* G_SADDO */
2084 341,
2085 /* G_SADDE */
2086 345,
2087 /* G_SSUBO */
2088 350,
2089 /* G_SSUBE */
2090 354,
2091 /* G_UMULO */
2092 359,
2093 /* G_SMULO */
2094 363,
2095 /* G_UMULH */
2096 367,
2097 /* G_SMULH */
2098 370,
2099 /* G_UADDSAT */
2100 373,
2101 /* G_SADDSAT */
2102 376,
2103 /* G_USUBSAT */
2104 379,
2105 /* G_SSUBSAT */
2106 382,
2107 /* G_USHLSAT */
2108 385,
2109 /* G_SSHLSAT */
2110 388,
2111 /* G_SMULFIX */
2112 391,
2113 /* G_UMULFIX */
2114 395,
2115 /* G_SMULFIXSAT */
2116 399,
2117 /* G_UMULFIXSAT */
2118 403,
2119 /* G_SDIVFIX */
2120 407,
2121 /* G_UDIVFIX */
2122 411,
2123 /* G_SDIVFIXSAT */
2124 415,
2125 /* G_UDIVFIXSAT */
2126 419,
2127 /* G_FADD */
2128 423,
2129 /* G_FSUB */
2130 426,
2131 /* G_FMUL */
2132 429,
2133 /* G_FMA */
2134 432,
2135 /* G_FMAD */
2136 436,
2137 /* G_FDIV */
2138 440,
2139 /* G_FREM */
2140 443,
2141 /* G_FPOW */
2142 446,
2143 /* G_FPOWI */
2144 449,
2145 /* G_FEXP */
2146 452,
2147 /* G_FEXP2 */
2148 454,
2149 /* G_FEXP10 */
2150 456,
2151 /* G_FLOG */
2152 458,
2153 /* G_FLOG2 */
2154 460,
2155 /* G_FLOG10 */
2156 462,
2157 /* G_FLDEXP */
2158 464,
2159 /* G_FFREXP */
2160 467,
2161 /* G_FNEG */
2162 470,
2163 /* G_FPEXT */
2164 472,
2165 /* G_FPTRUNC */
2166 474,
2167 /* G_FPTOSI */
2168 476,
2169 /* G_FPTOUI */
2170 478,
2171 /* G_SITOFP */
2172 480,
2173 /* G_UITOFP */
2174 482,
2175 /* G_FABS */
2176 484,
2177 /* G_FCOPYSIGN */
2178 486,
2179 /* G_IS_FPCLASS */
2180 489,
2181 /* G_FCANONICALIZE */
2182 492,
2183 /* G_FMINNUM */
2184 494,
2185 /* G_FMAXNUM */
2186 497,
2187 /* G_FMINNUM_IEEE */
2188 500,
2189 /* G_FMAXNUM_IEEE */
2190 503,
2191 /* G_FMINIMUM */
2192 506,
2193 /* G_FMAXIMUM */
2194 509,
2195 /* G_GET_FPENV */
2196 512,
2197 /* G_SET_FPENV */
2198 513,
2199 /* G_RESET_FPENV */
2200 514,
2201 /* G_GET_FPMODE */
2202 514,
2203 /* G_SET_FPMODE */
2204 515,
2205 /* G_RESET_FPMODE */
2206 516,
2207 /* G_PTR_ADD */
2208 516,
2209 /* G_PTRMASK */
2210 519,
2211 /* G_SMIN */
2212 522,
2213 /* G_SMAX */
2214 525,
2215 /* G_UMIN */
2216 528,
2217 /* G_UMAX */
2218 531,
2219 /* G_ABS */
2220 534,
2221 /* G_LROUND */
2222 536,
2223 /* G_LLROUND */
2224 538,
2225 /* G_BR */
2226 540,
2227 /* G_BRJT */
2228 541,
2229 /* G_VSCALE */
2230 544,
2231 /* G_INSERT_SUBVECTOR */
2232 546,
2233 /* G_EXTRACT_SUBVECTOR */
2234 550,
2235 /* G_INSERT_VECTOR_ELT */
2236 553,
2237 /* G_EXTRACT_VECTOR_ELT */
2238 557,
2239 /* G_SHUFFLE_VECTOR */
2240 560,
2241 /* G_SPLAT_VECTOR */
2242 564,
2243 /* G_VECTOR_COMPRESS */
2244 566,
2245 /* G_CTTZ */
2246 570,
2247 /* G_CTTZ_ZERO_UNDEF */
2248 572,
2249 /* G_CTLZ */
2250 574,
2251 /* G_CTLZ_ZERO_UNDEF */
2252 576,
2253 /* G_CTPOP */
2254 578,
2255 /* G_BSWAP */
2256 580,
2257 /* G_BITREVERSE */
2258 582,
2259 /* G_FCEIL */
2260 584,
2261 /* G_FCOS */
2262 586,
2263 /* G_FSIN */
2264 588,
2265 /* G_FTAN */
2266 590,
2267 /* G_FACOS */
2268 592,
2269 /* G_FASIN */
2270 594,
2271 /* G_FATAN */
2272 596,
2273 /* G_FCOSH */
2274 598,
2275 /* G_FSINH */
2276 600,
2277 /* G_FTANH */
2278 602,
2279 /* G_FSQRT */
2280 604,
2281 /* G_FFLOOR */
2282 606,
2283 /* G_FRINT */
2284 608,
2285 /* G_FNEARBYINT */
2286 610,
2287 /* G_ADDRSPACE_CAST */
2288 612,
2289 /* G_BLOCK_ADDR */
2290 614,
2291 /* G_JUMP_TABLE */
2292 616,
2293 /* G_DYN_STACKALLOC */
2294 618,
2295 /* G_STACKSAVE */
2296 621,
2297 /* G_STACKRESTORE */
2298 622,
2299 /* G_STRICT_FADD */
2300 623,
2301 /* G_STRICT_FSUB */
2302 626,
2303 /* G_STRICT_FMUL */
2304 629,
2305 /* G_STRICT_FDIV */
2306 632,
2307 /* G_STRICT_FREM */
2308 635,
2309 /* G_STRICT_FMA */
2310 638,
2311 /* G_STRICT_FSQRT */
2312 642,
2313 /* G_STRICT_FLDEXP */
2314 644,
2315 /* G_READ_REGISTER */
2316 647,
2317 /* G_WRITE_REGISTER */
2318 649,
2319 /* G_MEMCPY */
2320 651,
2321 /* G_MEMCPY_INLINE */
2322 655,
2323 /* G_MEMMOVE */
2324 658,
2325 /* G_MEMSET */
2326 662,
2327 /* G_BZERO */
2328 666,
2329 /* G_TRAP */
2330 669,
2331 /* G_DEBUGTRAP */
2332 669,
2333 /* G_UBSANTRAP */
2334 669,
2335 /* G_VECREDUCE_SEQ_FADD */
2336 670,
2337 /* G_VECREDUCE_SEQ_FMUL */
2338 673,
2339 /* G_VECREDUCE_FADD */
2340 676,
2341 /* G_VECREDUCE_FMUL */
2342 678,
2343 /* G_VECREDUCE_FMAX */
2344 680,
2345 /* G_VECREDUCE_FMIN */
2346 682,
2347 /* G_VECREDUCE_FMAXIMUM */
2348 684,
2349 /* G_VECREDUCE_FMINIMUM */
2350 686,
2351 /* G_VECREDUCE_ADD */
2352 688,
2353 /* G_VECREDUCE_MUL */
2354 690,
2355 /* G_VECREDUCE_AND */
2356 692,
2357 /* G_VECREDUCE_OR */
2358 694,
2359 /* G_VECREDUCE_XOR */
2360 696,
2361 /* G_VECREDUCE_SMAX */
2362 698,
2363 /* G_VECREDUCE_SMIN */
2364 700,
2365 /* G_VECREDUCE_UMAX */
2366 702,
2367 /* G_VECREDUCE_UMIN */
2368 704,
2369 /* G_SBFX */
2370 706,
2371 /* G_UBFX */
2372 710,
2373 /* ADJCALLSTACKDOWN */
2374 714,
2375 /* ADJCALLSTACKUP */
2376 716,
2377 /* FI_ri */
2378 718,
2379 /* MEMCPY */
2380 721,
2381 /* Select */
2382 725,
2383 /* Select_32 */
2384 731,
2385 /* Select_32_64 */
2386 737,
2387 /* Select_64_32 */
2388 743,
2389 /* Select_Ri */
2390 749,
2391 /* Select_Ri_32 */
2392 755,
2393 /* Select_Ri_32_64 */
2394 761,
2395 /* Select_Ri_64_32 */
2396 767,
2397 /* ADDR_SPACE_CAST */
2398 773,
2399 /* ADD_ri */
2400 777,
2401 /* ADD_ri_32 */
2402 780,
2403 /* ADD_rr */
2404 783,
2405 /* ADD_rr_32 */
2406 786,
2407 /* AND_ri */
2408 789,
2409 /* AND_ri_32 */
2410 792,
2411 /* AND_rr */
2412 795,
2413 /* AND_rr_32 */
2414 798,
2415 /* BE16 */
2416 801,
2417 /* BE32 */
2418 803,
2419 /* BE64 */
2420 805,
2421 /* BSWAP16 */
2422 807,
2423 /* BSWAP32 */
2424 809,
2425 /* BSWAP64 */
2426 811,
2427 /* CMPXCHGD */
2428 813,
2429 /* CMPXCHGW32 */
2430 816,
2431 /* CORE_LD32 */
2432 819,
2433 /* CORE_LD64 */
2434 823,
2435 /* CORE_SHIFT */
2436 827,
2437 /* CORE_ST */
2438 831,
2439 /* DIV_ri */
2440 835,
2441 /* DIV_ri_32 */
2442 838,
2443 /* DIV_rr */
2444 841,
2445 /* DIV_rr_32 */
2446 844,
2447 /* JAL */
2448 847,
2449 /* JALX */
2450 848,
2451 /* JCOND */
2452 849,
2453 /* JEQ_ri */
2454 850,
2455 /* JEQ_ri_32 */
2456 853,
2457 /* JEQ_rr */
2458 856,
2459 /* JEQ_rr_32 */
2460 859,
2461 /* JMP */
2462 862,
2463 /* JMPL */
2464 863,
2465 /* JNE_ri */
2466 864,
2467 /* JNE_ri_32 */
2468 867,
2469 /* JNE_rr */
2470 870,
2471 /* JNE_rr_32 */
2472 873,
2473 /* JSET_ri */
2474 876,
2475 /* JSET_ri_32 */
2476 879,
2477 /* JSET_rr */
2478 882,
2479 /* JSET_rr_32 */
2480 885,
2481 /* JSGE_ri */
2482 888,
2483 /* JSGE_ri_32 */
2484 891,
2485 /* JSGE_rr */
2486 894,
2487 /* JSGE_rr_32 */
2488 897,
2489 /* JSGT_ri */
2490 900,
2491 /* JSGT_ri_32 */
2492 903,
2493 /* JSGT_rr */
2494 906,
2495 /* JSGT_rr_32 */
2496 909,
2497 /* JSLE_ri */
2498 912,
2499 /* JSLE_ri_32 */
2500 915,
2501 /* JSLE_rr */
2502 918,
2503 /* JSLE_rr_32 */
2504 921,
2505 /* JSLT_ri */
2506 924,
2507 /* JSLT_ri_32 */
2508 927,
2509 /* JSLT_rr */
2510 930,
2511 /* JSLT_rr_32 */
2512 933,
2513 /* JUGE_ri */
2514 936,
2515 /* JUGE_ri_32 */
2516 939,
2517 /* JUGE_rr */
2518 942,
2519 /* JUGE_rr_32 */
2520 945,
2521 /* JUGT_ri */
2522 948,
2523 /* JUGT_ri_32 */
2524 951,
2525 /* JUGT_rr */
2526 954,
2527 /* JUGT_rr_32 */
2528 957,
2529 /* JULE_ri */
2530 960,
2531 /* JULE_ri_32 */
2532 963,
2533 /* JULE_rr */
2534 966,
2535 /* JULE_rr_32 */
2536 969,
2537 /* JULT_ri */
2538 972,
2539 /* JULT_ri_32 */
2540 975,
2541 /* JULT_rr */
2542 978,
2543 /* JULT_rr_32 */
2544 981,
2545 /* LDB */
2546 984,
2547 /* LDB32 */
2548 987,
2549 /* LDBSX */
2550 990,
2551 /* LDD */
2552 993,
2553 /* LDH */
2554 996,
2555 /* LDH32 */
2556 999,
2557 /* LDHSX */
2558 1002,
2559 /* LDW */
2560 1005,
2561 /* LDW32 */
2562 1008,
2563 /* LDWSX */
2564 1011,
2565 /* LD_ABS_B */
2566 1014,
2567 /* LD_ABS_H */
2568 1016,
2569 /* LD_ABS_W */
2570 1018,
2571 /* LD_IND_B */
2572 1020,
2573 /* LD_IND_H */
2574 1022,
2575 /* LD_IND_W */
2576 1024,
2577 /* LD_imm64 */
2578 1026,
2579 /* LD_pseudo */
2580 1028,
2581 /* LE16 */
2582 1031,
2583 /* LE32 */
2584 1033,
2585 /* LE64 */
2586 1035,
2587 /* MOD_ri */
2588 1037,
2589 /* MOD_ri_32 */
2590 1040,
2591 /* MOD_rr */
2592 1043,
2593 /* MOD_rr_32 */
2594 1046,
2595 /* MOVSX_rr_16 */
2596 1049,
2597 /* MOVSX_rr_32 */
2598 1051,
2599 /* MOVSX_rr_32_16 */
2600 1053,
2601 /* MOVSX_rr_32_8 */
2602 1055,
2603 /* MOVSX_rr_8 */
2604 1057,
2605 /* MOV_32_64 */
2606 1059,
2607 /* MOV_ri */
2608 1061,
2609 /* MOV_ri_32 */
2610 1063,
2611 /* MOV_rr */
2612 1065,
2613 /* MOV_rr_32 */
2614 1067,
2615 /* MUL_ri */
2616 1069,
2617 /* MUL_ri_32 */
2618 1072,
2619 /* MUL_rr */
2620 1075,
2621 /* MUL_rr_32 */
2622 1078,
2623 /* NEG_32 */
2624 1081,
2625 /* NEG_64 */
2626 1083,
2627 /* NOP */
2628 1085,
2629 /* OR_ri */
2630 1086,
2631 /* OR_ri_32 */
2632 1089,
2633 /* OR_rr */
2634 1092,
2635 /* OR_rr_32 */
2636 1095,
2637 /* RET */
2638 1098,
2639 /* SDIV_ri */
2640 1098,
2641 /* SDIV_ri_32 */
2642 1101,
2643 /* SDIV_rr */
2644 1104,
2645 /* SDIV_rr_32 */
2646 1107,
2647 /* SLL_ri */
2648 1110,
2649 /* SLL_ri_32 */
2650 1113,
2651 /* SLL_rr */
2652 1116,
2653 /* SLL_rr_32 */
2654 1119,
2655 /* SMOD_ri */
2656 1122,
2657 /* SMOD_ri_32 */
2658 1125,
2659 /* SMOD_rr */
2660 1128,
2661 /* SMOD_rr_32 */
2662 1131,
2663 /* SRA_ri */
2664 1134,
2665 /* SRA_ri_32 */
2666 1137,
2667 /* SRA_rr */
2668 1140,
2669 /* SRA_rr_32 */
2670 1143,
2671 /* SRL_ri */
2672 1146,
2673 /* SRL_ri_32 */
2674 1149,
2675 /* SRL_rr */
2676 1152,
2677 /* SRL_rr_32 */
2678 1155,
2679 /* STB */
2680 1158,
2681 /* STB32 */
2682 1161,
2683 /* STB_imm */
2684 1164,
2685 /* STD */
2686 1167,
2687 /* STD_imm */
2688 1170,
2689 /* STH */
2690 1173,
2691 /* STH32 */
2692 1176,
2693 /* STH_imm */
2694 1179,
2695 /* STW */
2696 1182,
2697 /* STW32 */
2698 1185,
2699 /* STW_imm */
2700 1188,
2701 /* SUB_ri */
2702 1191,
2703 /* SUB_ri_32 */
2704 1194,
2705 /* SUB_rr */
2706 1197,
2707 /* SUB_rr_32 */
2708 1200,
2709 /* XADDD */
2710 1203,
2711 /* XADDW */
2712 1207,
2713 /* XADDW32 */
2714 1211,
2715 /* XANDD */
2716 1215,
2717 /* XANDW32 */
2718 1219,
2719 /* XCHGD */
2720 1223,
2721 /* XCHGW32 */
2722 1227,
2723 /* XFADDD */
2724 1231,
2725 /* XFADDW32 */
2726 1235,
2727 /* XFANDD */
2728 1239,
2729 /* XFANDW32 */
2730 1243,
2731 /* XFORD */
2732 1247,
2733 /* XFORW32 */
2734 1251,
2735 /* XFXORD */
2736 1255,
2737 /* XFXORW32 */
2738 1259,
2739 /* XORD */
2740 1263,
2741 /* XORW32 */
2742 1267,
2743 /* XOR_ri */
2744 1271,
2745 /* XOR_ri_32 */
2746 1274,
2747 /* XOR_rr */
2748 1277,
2749 /* XOR_rr_32 */
2750 1280,
2751 /* XXORD */
2752 1283,
2753 /* XXORW32 */
2754 1287,
2755 };
2756
2757 using namespace OpTypes;
2758 static const int8_t OpcodeOperandTypes[] = {
2759
2760 /* PHI */
2761 -1,
2762 /* INLINEASM */
2763 /* INLINEASM_BR */
2764 /* CFI_INSTRUCTION */
2765 i32imm,
2766 /* EH_LABEL */
2767 i32imm,
2768 /* GC_LABEL */
2769 i32imm,
2770 /* ANNOTATION_LABEL */
2771 i32imm,
2772 /* KILL */
2773 /* EXTRACT_SUBREG */
2774 -1, -1, i32imm,
2775 /* INSERT_SUBREG */
2776 -1, -1, -1, i32imm,
2777 /* IMPLICIT_DEF */
2778 -1,
2779 /* SUBREG_TO_REG */
2780 -1, -1, -1, i32imm,
2781 /* COPY_TO_REGCLASS */
2782 -1, -1, i32imm,
2783 /* DBG_VALUE */
2784 /* DBG_VALUE_LIST */
2785 /* DBG_INSTR_REF */
2786 /* DBG_PHI */
2787 /* DBG_LABEL */
2788 -1,
2789 /* REG_SEQUENCE */
2790 -1, -1,
2791 /* COPY */
2792 -1, -1,
2793 /* BUNDLE */
2794 /* LIFETIME_START */
2795 i32imm,
2796 /* LIFETIME_END */
2797 i32imm,
2798 /* PSEUDO_PROBE */
2799 i64imm, i64imm, i8imm, i32imm,
2800 /* ARITH_FENCE */
2801 -1, -1,
2802 /* STACKMAP */
2803 i64imm, i32imm,
2804 /* FENTRY_CALL */
2805 /* PATCHPOINT */
2806 -1, i64imm, i32imm, -1, i32imm, i32imm,
2807 /* LOAD_STACK_GUARD */
2808 -1,
2809 /* PREALLOCATED_SETUP */
2810 i32imm,
2811 /* PREALLOCATED_ARG */
2812 -1, i32imm, i32imm,
2813 /* STATEPOINT */
2814 /* LOCAL_ESCAPE */
2815 -1, i32imm,
2816 /* FAULTING_OP */
2817 -1,
2818 /* PATCHABLE_OP */
2819 /* PATCHABLE_FUNCTION_ENTER */
2820 /* PATCHABLE_RET */
2821 /* PATCHABLE_FUNCTION_EXIT */
2822 /* PATCHABLE_TAIL_CALL */
2823 /* PATCHABLE_EVENT_CALL */
2824 -1, -1,
2825 /* PATCHABLE_TYPED_EVENT_CALL */
2826 -1, -1, -1,
2827 /* ICALL_BRANCH_FUNNEL */
2828 /* MEMBARRIER */
2829 /* JUMP_TABLE_DEBUG_INFO */
2830 i64imm,
2831 /* CONVERGENCECTRL_ENTRY */
2832 -1,
2833 /* CONVERGENCECTRL_ANCHOR */
2834 -1,
2835 /* CONVERGENCECTRL_LOOP */
2836 -1, -1,
2837 /* CONVERGENCECTRL_GLUE */
2838 -1,
2839 /* G_ASSERT_SEXT */
2840 type0, type0, untyped_imm_0,
2841 /* G_ASSERT_ZEXT */
2842 type0, type0, untyped_imm_0,
2843 /* G_ASSERT_ALIGN */
2844 type0, type0, untyped_imm_0,
2845 /* G_ADD */
2846 type0, type0, type0,
2847 /* G_SUB */
2848 type0, type0, type0,
2849 /* G_MUL */
2850 type0, type0, type0,
2851 /* G_SDIV */
2852 type0, type0, type0,
2853 /* G_UDIV */
2854 type0, type0, type0,
2855 /* G_SREM */
2856 type0, type0, type0,
2857 /* G_UREM */
2858 type0, type0, type0,
2859 /* G_SDIVREM */
2860 type0, type0, type0, type0,
2861 /* G_UDIVREM */
2862 type0, type0, type0, type0,
2863 /* G_AND */
2864 type0, type0, type0,
2865 /* G_OR */
2866 type0, type0, type0,
2867 /* G_XOR */
2868 type0, type0, type0,
2869 /* G_IMPLICIT_DEF */
2870 type0,
2871 /* G_PHI */
2872 type0,
2873 /* G_FRAME_INDEX */
2874 type0, -1,
2875 /* G_GLOBAL_VALUE */
2876 type0, -1,
2877 /* G_PTRAUTH_GLOBAL_VALUE */
2878 type0, -1, i32imm, type1, i64imm,
2879 /* G_CONSTANT_POOL */
2880 type0, -1,
2881 /* G_EXTRACT */
2882 type0, type1, untyped_imm_0,
2883 /* G_UNMERGE_VALUES */
2884 type0, type1,
2885 /* G_INSERT */
2886 type0, type0, type1, untyped_imm_0,
2887 /* G_MERGE_VALUES */
2888 type0, type1,
2889 /* G_BUILD_VECTOR */
2890 type0, type1,
2891 /* G_BUILD_VECTOR_TRUNC */
2892 type0, type1,
2893 /* G_CONCAT_VECTORS */
2894 type0, type1,
2895 /* G_PTRTOINT */
2896 type0, type1,
2897 /* G_INTTOPTR */
2898 type0, type1,
2899 /* G_BITCAST */
2900 type0, type1,
2901 /* G_FREEZE */
2902 type0, type0,
2903 /* G_CONSTANT_FOLD_BARRIER */
2904 type0, type0,
2905 /* G_INTRINSIC_FPTRUNC_ROUND */
2906 type0, type1, i32imm,
2907 /* G_INTRINSIC_TRUNC */
2908 type0, type0,
2909 /* G_INTRINSIC_ROUND */
2910 type0, type0,
2911 /* G_INTRINSIC_LRINT */
2912 type0, type1,
2913 /* G_INTRINSIC_LLRINT */
2914 type0, type1,
2915 /* G_INTRINSIC_ROUNDEVEN */
2916 type0, type0,
2917 /* G_READCYCLECOUNTER */
2918 type0,
2919 /* G_READSTEADYCOUNTER */
2920 type0,
2921 /* G_LOAD */
2922 type0, ptype1,
2923 /* G_SEXTLOAD */
2924 type0, ptype1,
2925 /* G_ZEXTLOAD */
2926 type0, ptype1,
2927 /* G_INDEXED_LOAD */
2928 type0, ptype1, ptype1, type2, -1,
2929 /* G_INDEXED_SEXTLOAD */
2930 type0, ptype1, ptype1, type2, -1,
2931 /* G_INDEXED_ZEXTLOAD */
2932 type0, ptype1, ptype1, type2, -1,
2933 /* G_STORE */
2934 type0, ptype1,
2935 /* G_INDEXED_STORE */
2936 ptype0, type1, ptype0, ptype2, -1,
2937 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
2938 type0, type1, type2, type0, type0,
2939 /* G_ATOMIC_CMPXCHG */
2940 type0, ptype1, type0, type0,
2941 /* G_ATOMICRMW_XCHG */
2942 type0, ptype1, type0,
2943 /* G_ATOMICRMW_ADD */
2944 type0, ptype1, type0,
2945 /* G_ATOMICRMW_SUB */
2946 type0, ptype1, type0,
2947 /* G_ATOMICRMW_AND */
2948 type0, ptype1, type0,
2949 /* G_ATOMICRMW_NAND */
2950 type0, ptype1, type0,
2951 /* G_ATOMICRMW_OR */
2952 type0, ptype1, type0,
2953 /* G_ATOMICRMW_XOR */
2954 type0, ptype1, type0,
2955 /* G_ATOMICRMW_MAX */
2956 type0, ptype1, type0,
2957 /* G_ATOMICRMW_MIN */
2958 type0, ptype1, type0,
2959 /* G_ATOMICRMW_UMAX */
2960 type0, ptype1, type0,
2961 /* G_ATOMICRMW_UMIN */
2962 type0, ptype1, type0,
2963 /* G_ATOMICRMW_FADD */
2964 type0, ptype1, type0,
2965 /* G_ATOMICRMW_FSUB */
2966 type0, ptype1, type0,
2967 /* G_ATOMICRMW_FMAX */
2968 type0, ptype1, type0,
2969 /* G_ATOMICRMW_FMIN */
2970 type0, ptype1, type0,
2971 /* G_ATOMICRMW_UINC_WRAP */
2972 type0, ptype1, type0,
2973 /* G_ATOMICRMW_UDEC_WRAP */
2974 type0, ptype1, type0,
2975 /* G_FENCE */
2976 i32imm, i32imm,
2977 /* G_PREFETCH */
2978 ptype0, i32imm, i32imm, i32imm,
2979 /* G_BRCOND */
2980 type0, -1,
2981 /* G_BRINDIRECT */
2982 type0,
2983 /* G_INVOKE_REGION_START */
2984 /* G_INTRINSIC */
2985 -1,
2986 /* G_INTRINSIC_W_SIDE_EFFECTS */
2987 -1,
2988 /* G_INTRINSIC_CONVERGENT */
2989 -1,
2990 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
2991 -1,
2992 /* G_ANYEXT */
2993 type0, type1,
2994 /* G_TRUNC */
2995 type0, type1,
2996 /* G_CONSTANT */
2997 type0, -1,
2998 /* G_FCONSTANT */
2999 type0, -1,
3000 /* G_VASTART */
3001 type0,
3002 /* G_VAARG */
3003 type0, type1, -1,
3004 /* G_SEXT */
3005 type0, type1,
3006 /* G_SEXT_INREG */
3007 type0, type0, untyped_imm_0,
3008 /* G_ZEXT */
3009 type0, type1,
3010 /* G_SHL */
3011 type0, type0, type1,
3012 /* G_LSHR */
3013 type0, type0, type1,
3014 /* G_ASHR */
3015 type0, type0, type1,
3016 /* G_FSHL */
3017 type0, type0, type0, type1,
3018 /* G_FSHR */
3019 type0, type0, type0, type1,
3020 /* G_ROTR */
3021 type0, type0, type1,
3022 /* G_ROTL */
3023 type0, type0, type1,
3024 /* G_ICMP */
3025 type0, -1, type1, type1,
3026 /* G_FCMP */
3027 type0, -1, type1, type1,
3028 /* G_SCMP */
3029 type0, type1, type1,
3030 /* G_UCMP */
3031 type0, type1, type1,
3032 /* G_SELECT */
3033 type0, type1, type0, type0,
3034 /* G_UADDO */
3035 type0, type1, type0, type0,
3036 /* G_UADDE */
3037 type0, type1, type0, type0, type1,
3038 /* G_USUBO */
3039 type0, type1, type0, type0,
3040 /* G_USUBE */
3041 type0, type1, type0, type0, type1,
3042 /* G_SADDO */
3043 type0, type1, type0, type0,
3044 /* G_SADDE */
3045 type0, type1, type0, type0, type1,
3046 /* G_SSUBO */
3047 type0, type1, type0, type0,
3048 /* G_SSUBE */
3049 type0, type1, type0, type0, type1,
3050 /* G_UMULO */
3051 type0, type1, type0, type0,
3052 /* G_SMULO */
3053 type0, type1, type0, type0,
3054 /* G_UMULH */
3055 type0, type0, type0,
3056 /* G_SMULH */
3057 type0, type0, type0,
3058 /* G_UADDSAT */
3059 type0, type0, type0,
3060 /* G_SADDSAT */
3061 type0, type0, type0,
3062 /* G_USUBSAT */
3063 type0, type0, type0,
3064 /* G_SSUBSAT */
3065 type0, type0, type0,
3066 /* G_USHLSAT */
3067 type0, type0, type1,
3068 /* G_SSHLSAT */
3069 type0, type0, type1,
3070 /* G_SMULFIX */
3071 type0, type0, type0, untyped_imm_0,
3072 /* G_UMULFIX */
3073 type0, type0, type0, untyped_imm_0,
3074 /* G_SMULFIXSAT */
3075 type0, type0, type0, untyped_imm_0,
3076 /* G_UMULFIXSAT */
3077 type0, type0, type0, untyped_imm_0,
3078 /* G_SDIVFIX */
3079 type0, type0, type0, untyped_imm_0,
3080 /* G_UDIVFIX */
3081 type0, type0, type0, untyped_imm_0,
3082 /* G_SDIVFIXSAT */
3083 type0, type0, type0, untyped_imm_0,
3084 /* G_UDIVFIXSAT */
3085 type0, type0, type0, untyped_imm_0,
3086 /* G_FADD */
3087 type0, type0, type0,
3088 /* G_FSUB */
3089 type0, type0, type0,
3090 /* G_FMUL */
3091 type0, type0, type0,
3092 /* G_FMA */
3093 type0, type0, type0, type0,
3094 /* G_FMAD */
3095 type0, type0, type0, type0,
3096 /* G_FDIV */
3097 type0, type0, type0,
3098 /* G_FREM */
3099 type0, type0, type0,
3100 /* G_FPOW */
3101 type0, type0, type0,
3102 /* G_FPOWI */
3103 type0, type0, type1,
3104 /* G_FEXP */
3105 type0, type0,
3106 /* G_FEXP2 */
3107 type0, type0,
3108 /* G_FEXP10 */
3109 type0, type0,
3110 /* G_FLOG */
3111 type0, type0,
3112 /* G_FLOG2 */
3113 type0, type0,
3114 /* G_FLOG10 */
3115 type0, type0,
3116 /* G_FLDEXP */
3117 type0, type0, type1,
3118 /* G_FFREXP */
3119 type0, type1, type0,
3120 /* G_FNEG */
3121 type0, type0,
3122 /* G_FPEXT */
3123 type0, type1,
3124 /* G_FPTRUNC */
3125 type0, type1,
3126 /* G_FPTOSI */
3127 type0, type1,
3128 /* G_FPTOUI */
3129 type0, type1,
3130 /* G_SITOFP */
3131 type0, type1,
3132 /* G_UITOFP */
3133 type0, type1,
3134 /* G_FABS */
3135 type0, type0,
3136 /* G_FCOPYSIGN */
3137 type0, type0, type1,
3138 /* G_IS_FPCLASS */
3139 type0, type1, -1,
3140 /* G_FCANONICALIZE */
3141 type0, type0,
3142 /* G_FMINNUM */
3143 type0, type0, type0,
3144 /* G_FMAXNUM */
3145 type0, type0, type0,
3146 /* G_FMINNUM_IEEE */
3147 type0, type0, type0,
3148 /* G_FMAXNUM_IEEE */
3149 type0, type0, type0,
3150 /* G_FMINIMUM */
3151 type0, type0, type0,
3152 /* G_FMAXIMUM */
3153 type0, type0, type0,
3154 /* G_GET_FPENV */
3155 type0,
3156 /* G_SET_FPENV */
3157 type0,
3158 /* G_RESET_FPENV */
3159 /* G_GET_FPMODE */
3160 type0,
3161 /* G_SET_FPMODE */
3162 type0,
3163 /* G_RESET_FPMODE */
3164 /* G_PTR_ADD */
3165 ptype0, ptype0, type1,
3166 /* G_PTRMASK */
3167 ptype0, ptype0, type1,
3168 /* G_SMIN */
3169 type0, type0, type0,
3170 /* G_SMAX */
3171 type0, type0, type0,
3172 /* G_UMIN */
3173 type0, type0, type0,
3174 /* G_UMAX */
3175 type0, type0, type0,
3176 /* G_ABS */
3177 type0, type0,
3178 /* G_LROUND */
3179 type0, type1,
3180 /* G_LLROUND */
3181 type0, type1,
3182 /* G_BR */
3183 -1,
3184 /* G_BRJT */
3185 ptype0, -1, type1,
3186 /* G_VSCALE */
3187 type0, -1,
3188 /* G_INSERT_SUBVECTOR */
3189 type0, type0, type1, untyped_imm_0,
3190 /* G_EXTRACT_SUBVECTOR */
3191 type0, type0, untyped_imm_0,
3192 /* G_INSERT_VECTOR_ELT */
3193 type0, type0, type1, type2,
3194 /* G_EXTRACT_VECTOR_ELT */
3195 type0, type1, type2,
3196 /* G_SHUFFLE_VECTOR */
3197 type0, type1, type1, -1,
3198 /* G_SPLAT_VECTOR */
3199 type0, type1,
3200 /* G_VECTOR_COMPRESS */
3201 type0, type0, type1, type0,
3202 /* G_CTTZ */
3203 type0, type1,
3204 /* G_CTTZ_ZERO_UNDEF */
3205 type0, type1,
3206 /* G_CTLZ */
3207 type0, type1,
3208 /* G_CTLZ_ZERO_UNDEF */
3209 type0, type1,
3210 /* G_CTPOP */
3211 type0, type1,
3212 /* G_BSWAP */
3213 type0, type0,
3214 /* G_BITREVERSE */
3215 type0, type0,
3216 /* G_FCEIL */
3217 type0, type0,
3218 /* G_FCOS */
3219 type0, type0,
3220 /* G_FSIN */
3221 type0, type0,
3222 /* G_FTAN */
3223 type0, type0,
3224 /* G_FACOS */
3225 type0, type0,
3226 /* G_FASIN */
3227 type0, type0,
3228 /* G_FATAN */
3229 type0, type0,
3230 /* G_FCOSH */
3231 type0, type0,
3232 /* G_FSINH */
3233 type0, type0,
3234 /* G_FTANH */
3235 type0, type0,
3236 /* G_FSQRT */
3237 type0, type0,
3238 /* G_FFLOOR */
3239 type0, type0,
3240 /* G_FRINT */
3241 type0, type0,
3242 /* G_FNEARBYINT */
3243 type0, type0,
3244 /* G_ADDRSPACE_CAST */
3245 type0, type1,
3246 /* G_BLOCK_ADDR */
3247 type0, -1,
3248 /* G_JUMP_TABLE */
3249 type0, -1,
3250 /* G_DYN_STACKALLOC */
3251 ptype0, type1, i32imm,
3252 /* G_STACKSAVE */
3253 ptype0,
3254 /* G_STACKRESTORE */
3255 ptype0,
3256 /* G_STRICT_FADD */
3257 type0, type0, type0,
3258 /* G_STRICT_FSUB */
3259 type0, type0, type0,
3260 /* G_STRICT_FMUL */
3261 type0, type0, type0,
3262 /* G_STRICT_FDIV */
3263 type0, type0, type0,
3264 /* G_STRICT_FREM */
3265 type0, type0, type0,
3266 /* G_STRICT_FMA */
3267 type0, type0, type0, type0,
3268 /* G_STRICT_FSQRT */
3269 type0, type0,
3270 /* G_STRICT_FLDEXP */
3271 type0, type0, type1,
3272 /* G_READ_REGISTER */
3273 type0, -1,
3274 /* G_WRITE_REGISTER */
3275 -1, type0,
3276 /* G_MEMCPY */
3277 ptype0, ptype1, type2, untyped_imm_0,
3278 /* G_MEMCPY_INLINE */
3279 ptype0, ptype1, type2,
3280 /* G_MEMMOVE */
3281 ptype0, ptype1, type2, untyped_imm_0,
3282 /* G_MEMSET */
3283 ptype0, type1, type2, untyped_imm_0,
3284 /* G_BZERO */
3285 ptype0, type1, untyped_imm_0,
3286 /* G_TRAP */
3287 /* G_DEBUGTRAP */
3288 /* G_UBSANTRAP */
3289 i8imm,
3290 /* G_VECREDUCE_SEQ_FADD */
3291 type0, type1, type2,
3292 /* G_VECREDUCE_SEQ_FMUL */
3293 type0, type1, type2,
3294 /* G_VECREDUCE_FADD */
3295 type0, type1,
3296 /* G_VECREDUCE_FMUL */
3297 type0, type1,
3298 /* G_VECREDUCE_FMAX */
3299 type0, type1,
3300 /* G_VECREDUCE_FMIN */
3301 type0, type1,
3302 /* G_VECREDUCE_FMAXIMUM */
3303 type0, type1,
3304 /* G_VECREDUCE_FMINIMUM */
3305 type0, type1,
3306 /* G_VECREDUCE_ADD */
3307 type0, type1,
3308 /* G_VECREDUCE_MUL */
3309 type0, type1,
3310 /* G_VECREDUCE_AND */
3311 type0, type1,
3312 /* G_VECREDUCE_OR */
3313 type0, type1,
3314 /* G_VECREDUCE_XOR */
3315 type0, type1,
3316 /* G_VECREDUCE_SMAX */
3317 type0, type1,
3318 /* G_VECREDUCE_SMIN */
3319 type0, type1,
3320 /* G_VECREDUCE_UMAX */
3321 type0, type1,
3322 /* G_VECREDUCE_UMIN */
3323 type0, type1,
3324 /* G_SBFX */
3325 type0, type0, type1, type1,
3326 /* G_UBFX */
3327 type0, type0, type1, type1,
3328 /* ADJCALLSTACKDOWN */
3329 i64imm, i64imm,
3330 /* ADJCALLSTACKUP */
3331 i64imm, i64imm,
3332 /* FI_ri */
3333 GPR, GPR, s16imm,
3334 /* MEMCPY */
3335 GPR, GPR, i64imm, i64imm,
3336 /* Select */
3337 GPR, GPR, GPR, i64imm, GPR, GPR,
3338 /* Select_32 */
3339 GPR32, GPR32, GPR32, i32imm, GPR32, GPR32,
3340 /* Select_32_64 */
3341 GPR, GPR32, GPR32, i32imm, GPR, GPR,
3342 /* Select_64_32 */
3343 GPR32, GPR, GPR, i64imm, GPR32, GPR32,
3344 /* Select_Ri */
3345 GPR, GPR, i64imm, i64imm, GPR, GPR,
3346 /* Select_Ri_32 */
3347 GPR32, GPR32, i32imm, i32imm, GPR32, GPR32,
3348 /* Select_Ri_32_64 */
3349 GPR, GPR32, i32imm, i32imm, GPR, GPR,
3350 /* Select_Ri_64_32 */
3351 GPR32, GPR, i64imm, i64imm, GPR32, GPR32,
3352 /* ADDR_SPACE_CAST */
3353 GPR, GPR, i64imm, i64imm,
3354 /* ADD_ri */
3355 GPR, GPR, i64imm,
3356 /* ADD_ri_32 */
3357 GPR32, GPR32, i32imm,
3358 /* ADD_rr */
3359 GPR, GPR, GPR,
3360 /* ADD_rr_32 */
3361 GPR32, GPR32, GPR32,
3362 /* AND_ri */
3363 GPR, GPR, i64imm,
3364 /* AND_ri_32 */
3365 GPR32, GPR32, i32imm,
3366 /* AND_rr */
3367 GPR, GPR, GPR,
3368 /* AND_rr_32 */
3369 GPR32, GPR32, GPR32,
3370 /* BE16 */
3371 GPR, GPR,
3372 /* BE32 */
3373 GPR, GPR,
3374 /* BE64 */
3375 GPR, GPR,
3376 /* BSWAP16 */
3377 GPR, GPR,
3378 /* BSWAP32 */
3379 GPR, GPR,
3380 /* BSWAP64 */
3381 GPR, GPR,
3382 /* CMPXCHGD */
3383 GPR, s16imm, GPR,
3384 /* CMPXCHGW32 */
3385 GPR, s16imm, GPR32,
3386 /* CORE_LD32 */
3387 GPR32, u64imm, GPR, u64imm,
3388 /* CORE_LD64 */
3389 GPR, u64imm, GPR, u64imm,
3390 /* CORE_SHIFT */
3391 GPR, u64imm, GPR, u64imm,
3392 /* CORE_ST */
3393 gpr_or_imm, u64imm, GPR, u64imm,
3394 /* DIV_ri */
3395 GPR, GPR, i64imm,
3396 /* DIV_ri_32 */
3397 GPR32, GPR32, i32imm,
3398 /* DIV_rr */
3399 GPR, GPR, GPR,
3400 /* DIV_rr_32 */
3401 GPR32, GPR32, GPR32,
3402 /* JAL */
3403 calltarget,
3404 /* JALX */
3405 GPR,
3406 /* JCOND */
3407 brtarget,
3408 /* JEQ_ri */
3409 GPR, i64imm, brtarget,
3410 /* JEQ_ri_32 */
3411 GPR32, i32imm, brtarget,
3412 /* JEQ_rr */
3413 GPR, GPR, brtarget,
3414 /* JEQ_rr_32 */
3415 GPR32, GPR32, brtarget,
3416 /* JMP */
3417 brtarget,
3418 /* JMPL */
3419 brtarget,
3420 /* JNE_ri */
3421 GPR, i64imm, brtarget,
3422 /* JNE_ri_32 */
3423 GPR32, i32imm, brtarget,
3424 /* JNE_rr */
3425 GPR, GPR, brtarget,
3426 /* JNE_rr_32 */
3427 GPR32, GPR32, brtarget,
3428 /* JSET_ri */
3429 GPR, i64imm, brtarget,
3430 /* JSET_ri_32 */
3431 GPR32, i32imm, brtarget,
3432 /* JSET_rr */
3433 GPR, GPR, brtarget,
3434 /* JSET_rr_32 */
3435 GPR32, GPR32, brtarget,
3436 /* JSGE_ri */
3437 GPR, i64imm, brtarget,
3438 /* JSGE_ri_32 */
3439 GPR32, i32imm, brtarget,
3440 /* JSGE_rr */
3441 GPR, GPR, brtarget,
3442 /* JSGE_rr_32 */
3443 GPR32, GPR32, brtarget,
3444 /* JSGT_ri */
3445 GPR, i64imm, brtarget,
3446 /* JSGT_ri_32 */
3447 GPR32, i32imm, brtarget,
3448 /* JSGT_rr */
3449 GPR, GPR, brtarget,
3450 /* JSGT_rr_32 */
3451 GPR32, GPR32, brtarget,
3452 /* JSLE_ri */
3453 GPR, i64imm, brtarget,
3454 /* JSLE_ri_32 */
3455 GPR32, i32imm, brtarget,
3456 /* JSLE_rr */
3457 GPR, GPR, brtarget,
3458 /* JSLE_rr_32 */
3459 GPR32, GPR32, brtarget,
3460 /* JSLT_ri */
3461 GPR, i64imm, brtarget,
3462 /* JSLT_ri_32 */
3463 GPR32, i32imm, brtarget,
3464 /* JSLT_rr */
3465 GPR, GPR, brtarget,
3466 /* JSLT_rr_32 */
3467 GPR32, GPR32, brtarget,
3468 /* JUGE_ri */
3469 GPR, i64imm, brtarget,
3470 /* JUGE_ri_32 */
3471 GPR32, i32imm, brtarget,
3472 /* JUGE_rr */
3473 GPR, GPR, brtarget,
3474 /* JUGE_rr_32 */
3475 GPR32, GPR32, brtarget,
3476 /* JUGT_ri */
3477 GPR, i64imm, brtarget,
3478 /* JUGT_ri_32 */
3479 GPR32, i32imm, brtarget,
3480 /* JUGT_rr */
3481 GPR, GPR, brtarget,
3482 /* JUGT_rr_32 */
3483 GPR32, GPR32, brtarget,
3484 /* JULE_ri */
3485 GPR, i64imm, brtarget,
3486 /* JULE_ri_32 */
3487 GPR32, i32imm, brtarget,
3488 /* JULE_rr */
3489 GPR, GPR, brtarget,
3490 /* JULE_rr_32 */
3491 GPR32, GPR32, brtarget,
3492 /* JULT_ri */
3493 GPR, i64imm, brtarget,
3494 /* JULT_ri_32 */
3495 GPR32, i32imm, brtarget,
3496 /* JULT_rr */
3497 GPR, GPR, brtarget,
3498 /* JULT_rr_32 */
3499 GPR32, GPR32, brtarget,
3500 /* LDB */
3501 GPR, GPR, s16imm,
3502 /* LDB32 */
3503 GPR32, GPR, s16imm,
3504 /* LDBSX */
3505 GPR, GPR, s16imm,
3506 /* LDD */
3507 GPR, GPR, s16imm,
3508 /* LDH */
3509 GPR, GPR, s16imm,
3510 /* LDH32 */
3511 GPR32, GPR, s16imm,
3512 /* LDHSX */
3513 GPR, GPR, s16imm,
3514 /* LDW */
3515 GPR, GPR, s16imm,
3516 /* LDW32 */
3517 GPR32, GPR, s16imm,
3518 /* LDWSX */
3519 GPR, GPR, s16imm,
3520 /* LD_ABS_B */
3521 GPR, i64imm,
3522 /* LD_ABS_H */
3523 GPR, i64imm,
3524 /* LD_ABS_W */
3525 GPR, i64imm,
3526 /* LD_IND_B */
3527 GPR, GPR,
3528 /* LD_IND_H */
3529 GPR, GPR,
3530 /* LD_IND_W */
3531 GPR, GPR,
3532 /* LD_imm64 */
3533 GPR, u64imm,
3534 /* LD_pseudo */
3535 GPR, i64imm, u64imm,
3536 /* LE16 */
3537 GPR, GPR,
3538 /* LE32 */
3539 GPR, GPR,
3540 /* LE64 */
3541 GPR, GPR,
3542 /* MOD_ri */
3543 GPR, GPR, i64imm,
3544 /* MOD_ri_32 */
3545 GPR32, GPR32, i32imm,
3546 /* MOD_rr */
3547 GPR, GPR, GPR,
3548 /* MOD_rr_32 */
3549 GPR32, GPR32, GPR32,
3550 /* MOVSX_rr_16 */
3551 GPR, GPR,
3552 /* MOVSX_rr_32 */
3553 GPR, GPR,
3554 /* MOVSX_rr_32_16 */
3555 GPR32, GPR32,
3556 /* MOVSX_rr_32_8 */
3557 GPR32, GPR32,
3558 /* MOVSX_rr_8 */
3559 GPR, GPR,
3560 /* MOV_32_64 */
3561 GPR, GPR32,
3562 /* MOV_ri */
3563 GPR, i64imm,
3564 /* MOV_ri_32 */
3565 GPR32, i32imm,
3566 /* MOV_rr */
3567 GPR, GPR,
3568 /* MOV_rr_32 */
3569 GPR32, GPR32,
3570 /* MUL_ri */
3571 GPR, GPR, i64imm,
3572 /* MUL_ri_32 */
3573 GPR32, GPR32, i32imm,
3574 /* MUL_rr */
3575 GPR, GPR, GPR,
3576 /* MUL_rr_32 */
3577 GPR32, GPR32, GPR32,
3578 /* NEG_32 */
3579 GPR32, GPR32,
3580 /* NEG_64 */
3581 GPR, GPR,
3582 /* NOP */
3583 i32imm,
3584 /* OR_ri */
3585 GPR, GPR, i64imm,
3586 /* OR_ri_32 */
3587 GPR32, GPR32, i32imm,
3588 /* OR_rr */
3589 GPR, GPR, GPR,
3590 /* OR_rr_32 */
3591 GPR32, GPR32, GPR32,
3592 /* RET */
3593 /* SDIV_ri */
3594 GPR, GPR, i64imm,
3595 /* SDIV_ri_32 */
3596 GPR32, GPR32, i32imm,
3597 /* SDIV_rr */
3598 GPR, GPR, GPR,
3599 /* SDIV_rr_32 */
3600 GPR32, GPR32, GPR32,
3601 /* SLL_ri */
3602 GPR, GPR, i64imm,
3603 /* SLL_ri_32 */
3604 GPR32, GPR32, i32imm,
3605 /* SLL_rr */
3606 GPR, GPR, GPR,
3607 /* SLL_rr_32 */
3608 GPR32, GPR32, GPR32,
3609 /* SMOD_ri */
3610 GPR, GPR, i64imm,
3611 /* SMOD_ri_32 */
3612 GPR32, GPR32, i32imm,
3613 /* SMOD_rr */
3614 GPR, GPR, GPR,
3615 /* SMOD_rr_32 */
3616 GPR32, GPR32, GPR32,
3617 /* SRA_ri */
3618 GPR, GPR, i64imm,
3619 /* SRA_ri_32 */
3620 GPR32, GPR32, i32imm,
3621 /* SRA_rr */
3622 GPR, GPR, GPR,
3623 /* SRA_rr_32 */
3624 GPR32, GPR32, GPR32,
3625 /* SRL_ri */
3626 GPR, GPR, i64imm,
3627 /* SRL_ri_32 */
3628 GPR32, GPR32, i32imm,
3629 /* SRL_rr */
3630 GPR, GPR, GPR,
3631 /* SRL_rr_32 */
3632 GPR32, GPR32, GPR32,
3633 /* STB */
3634 GPR, GPR, s16imm,
3635 /* STB32 */
3636 GPR32, GPR, s16imm,
3637 /* STB_imm */
3638 i64imm, GPR, s16imm,
3639 /* STD */
3640 GPR, GPR, s16imm,
3641 /* STD_imm */
3642 i64imm, GPR, s16imm,
3643 /* STH */
3644 GPR, GPR, s16imm,
3645 /* STH32 */
3646 GPR32, GPR, s16imm,
3647 /* STH_imm */
3648 i64imm, GPR, s16imm,
3649 /* STW */
3650 GPR, GPR, s16imm,
3651 /* STW32 */
3652 GPR32, GPR, s16imm,
3653 /* STW_imm */
3654 i64imm, GPR, s16imm,
3655 /* SUB_ri */
3656 GPR, GPR, i64imm,
3657 /* SUB_ri_32 */
3658 GPR32, GPR32, i32imm,
3659 /* SUB_rr */
3660 GPR, GPR, GPR,
3661 /* SUB_rr_32 */
3662 GPR32, GPR32, GPR32,
3663 /* XADDD */
3664 GPR, GPR, s16imm, GPR,
3665 /* XADDW */
3666 GPR, GPR, s16imm, GPR,
3667 /* XADDW32 */
3668 GPR32, GPR, s16imm, GPR32,
3669 /* XANDD */
3670 GPR, GPR, s16imm, GPR,
3671 /* XANDW32 */
3672 GPR32, GPR, s16imm, GPR32,
3673 /* XCHGD */
3674 GPR, GPR, s16imm, GPR,
3675 /* XCHGW32 */
3676 GPR32, GPR, s16imm, GPR32,
3677 /* XFADDD */
3678 GPR, GPR, s16imm, GPR,
3679 /* XFADDW32 */
3680 GPR32, GPR, s16imm, GPR32,
3681 /* XFANDD */
3682 GPR, GPR, s16imm, GPR,
3683 /* XFANDW32 */
3684 GPR32, GPR, s16imm, GPR32,
3685 /* XFORD */
3686 GPR, GPR, s16imm, GPR,
3687 /* XFORW32 */
3688 GPR32, GPR, s16imm, GPR32,
3689 /* XFXORD */
3690 GPR, GPR, s16imm, GPR,
3691 /* XFXORW32 */
3692 GPR32, GPR, s16imm, GPR32,
3693 /* XORD */
3694 GPR, GPR, s16imm, GPR,
3695 /* XORW32 */
3696 GPR32, GPR, s16imm, GPR32,
3697 /* XOR_ri */
3698 GPR, GPR, i64imm,
3699 /* XOR_ri_32 */
3700 GPR32, GPR32, i32imm,
3701 /* XOR_rr */
3702 GPR, GPR, GPR,
3703 /* XOR_rr_32 */
3704 GPR32, GPR32, GPR32,
3705 /* XXORD */
3706 GPR, GPR, s16imm, GPR,
3707 /* XXORW32 */
3708 GPR32, GPR, s16imm, GPR32,
3709 };
3710 return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
3711}
3712} // end namespace BPF
3713} // end namespace llvm
3714#endif // GET_INSTRINFO_OPERAND_TYPE
3715
3716#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
3717#undef GET_INSTRINFO_MEM_OPERAND_SIZE
3718namespace llvm {
3719namespace BPF {
3720LLVM_READONLY
3721static int getMemOperandSize(int OpType) {
3722 switch (OpType) {
3723 default: return 0;
3724 }
3725}
3726} // end namespace BPF
3727} // end namespace llvm
3728#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
3729
3730#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3731#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3732namespace llvm {
3733namespace BPF {
3734LLVM_READONLY static unsigned
3735getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
3736 return LogicalOpIdx;
3737}
3738LLVM_READONLY static inline unsigned
3739getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
3740 auto S = 0U;
3741 for (auto i = 0U; i < LogicalOpIdx; ++i)
3742 S += getLogicalOperandSize(Opcode, i);
3743 return S;
3744}
3745} // end namespace BPF
3746} // end namespace llvm
3747#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3748
3749#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3750#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3751namespace llvm {
3752namespace BPF {
3753LLVM_READONLY static int
3754getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
3755 return -1;
3756}
3757} // end namespace BPF
3758} // end namespace llvm
3759#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3760
3761#ifdef GET_INSTRINFO_MC_HELPER_DECLS
3762#undef GET_INSTRINFO_MC_HELPER_DECLS
3763
3764namespace llvm {
3765class MCInst;
3766class FeatureBitset;
3767
3768namespace BPF_MC {
3769
3770void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
3771
3772} // end namespace BPF_MC
3773} // end namespace llvm
3774
3775#endif // GET_INSTRINFO_MC_HELPER_DECLS
3776
3777#ifdef GET_INSTRINFO_MC_HELPERS
3778#undef GET_INSTRINFO_MC_HELPERS
3779
3780namespace llvm {
3781namespace BPF_MC {
3782
3783} // end namespace BPF_MC
3784} // end namespace llvm
3785
3786#endif // GET_GENISTRINFO_MC_HELPERS
3787
3788#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
3789 defined(GET_AVAILABLE_OPCODE_CHECKER)
3790#define GET_COMPUTE_FEATURES
3791#endif
3792#ifdef GET_COMPUTE_FEATURES
3793#undef GET_COMPUTE_FEATURES
3794namespace llvm {
3795namespace BPF_MC {
3796
3797// Bits for subtarget features that participate in instruction matching.
3798enum SubtargetFeatureBits : uint8_t {
3799};
3800
3801inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
3802 FeatureBitset Features;
3803 return Features;
3804}
3805
3806inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
3807 enum : uint8_t {
3808 CEFBS_None,
3809 };
3810
3811 static constexpr FeatureBitset FeatureBitsets[] = {
3812 {}, // CEFBS_None
3813 };
3814 static constexpr uint8_t RequiredFeaturesRefs[] = {
3815 CEFBS_None, // PHI = 0
3816 CEFBS_None, // INLINEASM = 1
3817 CEFBS_None, // INLINEASM_BR = 2
3818 CEFBS_None, // CFI_INSTRUCTION = 3
3819 CEFBS_None, // EH_LABEL = 4
3820 CEFBS_None, // GC_LABEL = 5
3821 CEFBS_None, // ANNOTATION_LABEL = 6
3822 CEFBS_None, // KILL = 7
3823 CEFBS_None, // EXTRACT_SUBREG = 8
3824 CEFBS_None, // INSERT_SUBREG = 9
3825 CEFBS_None, // IMPLICIT_DEF = 10
3826 CEFBS_None, // SUBREG_TO_REG = 11
3827 CEFBS_None, // COPY_TO_REGCLASS = 12
3828 CEFBS_None, // DBG_VALUE = 13
3829 CEFBS_None, // DBG_VALUE_LIST = 14
3830 CEFBS_None, // DBG_INSTR_REF = 15
3831 CEFBS_None, // DBG_PHI = 16
3832 CEFBS_None, // DBG_LABEL = 17
3833 CEFBS_None, // REG_SEQUENCE = 18
3834 CEFBS_None, // COPY = 19
3835 CEFBS_None, // BUNDLE = 20
3836 CEFBS_None, // LIFETIME_START = 21
3837 CEFBS_None, // LIFETIME_END = 22
3838 CEFBS_None, // PSEUDO_PROBE = 23
3839 CEFBS_None, // ARITH_FENCE = 24
3840 CEFBS_None, // STACKMAP = 25
3841 CEFBS_None, // FENTRY_CALL = 26
3842 CEFBS_None, // PATCHPOINT = 27
3843 CEFBS_None, // LOAD_STACK_GUARD = 28
3844 CEFBS_None, // PREALLOCATED_SETUP = 29
3845 CEFBS_None, // PREALLOCATED_ARG = 30
3846 CEFBS_None, // STATEPOINT = 31
3847 CEFBS_None, // LOCAL_ESCAPE = 32
3848 CEFBS_None, // FAULTING_OP = 33
3849 CEFBS_None, // PATCHABLE_OP = 34
3850 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
3851 CEFBS_None, // PATCHABLE_RET = 36
3852 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
3853 CEFBS_None, // PATCHABLE_TAIL_CALL = 38
3854 CEFBS_None, // PATCHABLE_EVENT_CALL = 39
3855 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
3856 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
3857 CEFBS_None, // MEMBARRIER = 42
3858 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
3859 CEFBS_None, // CONVERGENCECTRL_ENTRY = 44
3860 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 45
3861 CEFBS_None, // CONVERGENCECTRL_LOOP = 46
3862 CEFBS_None, // CONVERGENCECTRL_GLUE = 47
3863 CEFBS_None, // G_ASSERT_SEXT = 48
3864 CEFBS_None, // G_ASSERT_ZEXT = 49
3865 CEFBS_None, // G_ASSERT_ALIGN = 50
3866 CEFBS_None, // G_ADD = 51
3867 CEFBS_None, // G_SUB = 52
3868 CEFBS_None, // G_MUL = 53
3869 CEFBS_None, // G_SDIV = 54
3870 CEFBS_None, // G_UDIV = 55
3871 CEFBS_None, // G_SREM = 56
3872 CEFBS_None, // G_UREM = 57
3873 CEFBS_None, // G_SDIVREM = 58
3874 CEFBS_None, // G_UDIVREM = 59
3875 CEFBS_None, // G_AND = 60
3876 CEFBS_None, // G_OR = 61
3877 CEFBS_None, // G_XOR = 62
3878 CEFBS_None, // G_IMPLICIT_DEF = 63
3879 CEFBS_None, // G_PHI = 64
3880 CEFBS_None, // G_FRAME_INDEX = 65
3881 CEFBS_None, // G_GLOBAL_VALUE = 66
3882 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 67
3883 CEFBS_None, // G_CONSTANT_POOL = 68
3884 CEFBS_None, // G_EXTRACT = 69
3885 CEFBS_None, // G_UNMERGE_VALUES = 70
3886 CEFBS_None, // G_INSERT = 71
3887 CEFBS_None, // G_MERGE_VALUES = 72
3888 CEFBS_None, // G_BUILD_VECTOR = 73
3889 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 74
3890 CEFBS_None, // G_CONCAT_VECTORS = 75
3891 CEFBS_None, // G_PTRTOINT = 76
3892 CEFBS_None, // G_INTTOPTR = 77
3893 CEFBS_None, // G_BITCAST = 78
3894 CEFBS_None, // G_FREEZE = 79
3895 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 80
3896 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 81
3897 CEFBS_None, // G_INTRINSIC_TRUNC = 82
3898 CEFBS_None, // G_INTRINSIC_ROUND = 83
3899 CEFBS_None, // G_INTRINSIC_LRINT = 84
3900 CEFBS_None, // G_INTRINSIC_LLRINT = 85
3901 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 86
3902 CEFBS_None, // G_READCYCLECOUNTER = 87
3903 CEFBS_None, // G_READSTEADYCOUNTER = 88
3904 CEFBS_None, // G_LOAD = 89
3905 CEFBS_None, // G_SEXTLOAD = 90
3906 CEFBS_None, // G_ZEXTLOAD = 91
3907 CEFBS_None, // G_INDEXED_LOAD = 92
3908 CEFBS_None, // G_INDEXED_SEXTLOAD = 93
3909 CEFBS_None, // G_INDEXED_ZEXTLOAD = 94
3910 CEFBS_None, // G_STORE = 95
3911 CEFBS_None, // G_INDEXED_STORE = 96
3912 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97
3913 CEFBS_None, // G_ATOMIC_CMPXCHG = 98
3914 CEFBS_None, // G_ATOMICRMW_XCHG = 99
3915 CEFBS_None, // G_ATOMICRMW_ADD = 100
3916 CEFBS_None, // G_ATOMICRMW_SUB = 101
3917 CEFBS_None, // G_ATOMICRMW_AND = 102
3918 CEFBS_None, // G_ATOMICRMW_NAND = 103
3919 CEFBS_None, // G_ATOMICRMW_OR = 104
3920 CEFBS_None, // G_ATOMICRMW_XOR = 105
3921 CEFBS_None, // G_ATOMICRMW_MAX = 106
3922 CEFBS_None, // G_ATOMICRMW_MIN = 107
3923 CEFBS_None, // G_ATOMICRMW_UMAX = 108
3924 CEFBS_None, // G_ATOMICRMW_UMIN = 109
3925 CEFBS_None, // G_ATOMICRMW_FADD = 110
3926 CEFBS_None, // G_ATOMICRMW_FSUB = 111
3927 CEFBS_None, // G_ATOMICRMW_FMAX = 112
3928 CEFBS_None, // G_ATOMICRMW_FMIN = 113
3929 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 114
3930 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 115
3931 CEFBS_None, // G_FENCE = 116
3932 CEFBS_None, // G_PREFETCH = 117
3933 CEFBS_None, // G_BRCOND = 118
3934 CEFBS_None, // G_BRINDIRECT = 119
3935 CEFBS_None, // G_INVOKE_REGION_START = 120
3936 CEFBS_None, // G_INTRINSIC = 121
3937 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 122
3938 CEFBS_None, // G_INTRINSIC_CONVERGENT = 123
3939 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124
3940 CEFBS_None, // G_ANYEXT = 125
3941 CEFBS_None, // G_TRUNC = 126
3942 CEFBS_None, // G_CONSTANT = 127
3943 CEFBS_None, // G_FCONSTANT = 128
3944 CEFBS_None, // G_VASTART = 129
3945 CEFBS_None, // G_VAARG = 130
3946 CEFBS_None, // G_SEXT = 131
3947 CEFBS_None, // G_SEXT_INREG = 132
3948 CEFBS_None, // G_ZEXT = 133
3949 CEFBS_None, // G_SHL = 134
3950 CEFBS_None, // G_LSHR = 135
3951 CEFBS_None, // G_ASHR = 136
3952 CEFBS_None, // G_FSHL = 137
3953 CEFBS_None, // G_FSHR = 138
3954 CEFBS_None, // G_ROTR = 139
3955 CEFBS_None, // G_ROTL = 140
3956 CEFBS_None, // G_ICMP = 141
3957 CEFBS_None, // G_FCMP = 142
3958 CEFBS_None, // G_SCMP = 143
3959 CEFBS_None, // G_UCMP = 144
3960 CEFBS_None, // G_SELECT = 145
3961 CEFBS_None, // G_UADDO = 146
3962 CEFBS_None, // G_UADDE = 147
3963 CEFBS_None, // G_USUBO = 148
3964 CEFBS_None, // G_USUBE = 149
3965 CEFBS_None, // G_SADDO = 150
3966 CEFBS_None, // G_SADDE = 151
3967 CEFBS_None, // G_SSUBO = 152
3968 CEFBS_None, // G_SSUBE = 153
3969 CEFBS_None, // G_UMULO = 154
3970 CEFBS_None, // G_SMULO = 155
3971 CEFBS_None, // G_UMULH = 156
3972 CEFBS_None, // G_SMULH = 157
3973 CEFBS_None, // G_UADDSAT = 158
3974 CEFBS_None, // G_SADDSAT = 159
3975 CEFBS_None, // G_USUBSAT = 160
3976 CEFBS_None, // G_SSUBSAT = 161
3977 CEFBS_None, // G_USHLSAT = 162
3978 CEFBS_None, // G_SSHLSAT = 163
3979 CEFBS_None, // G_SMULFIX = 164
3980 CEFBS_None, // G_UMULFIX = 165
3981 CEFBS_None, // G_SMULFIXSAT = 166
3982 CEFBS_None, // G_UMULFIXSAT = 167
3983 CEFBS_None, // G_SDIVFIX = 168
3984 CEFBS_None, // G_UDIVFIX = 169
3985 CEFBS_None, // G_SDIVFIXSAT = 170
3986 CEFBS_None, // G_UDIVFIXSAT = 171
3987 CEFBS_None, // G_FADD = 172
3988 CEFBS_None, // G_FSUB = 173
3989 CEFBS_None, // G_FMUL = 174
3990 CEFBS_None, // G_FMA = 175
3991 CEFBS_None, // G_FMAD = 176
3992 CEFBS_None, // G_FDIV = 177
3993 CEFBS_None, // G_FREM = 178
3994 CEFBS_None, // G_FPOW = 179
3995 CEFBS_None, // G_FPOWI = 180
3996 CEFBS_None, // G_FEXP = 181
3997 CEFBS_None, // G_FEXP2 = 182
3998 CEFBS_None, // G_FEXP10 = 183
3999 CEFBS_None, // G_FLOG = 184
4000 CEFBS_None, // G_FLOG2 = 185
4001 CEFBS_None, // G_FLOG10 = 186
4002 CEFBS_None, // G_FLDEXP = 187
4003 CEFBS_None, // G_FFREXP = 188
4004 CEFBS_None, // G_FNEG = 189
4005 CEFBS_None, // G_FPEXT = 190
4006 CEFBS_None, // G_FPTRUNC = 191
4007 CEFBS_None, // G_FPTOSI = 192
4008 CEFBS_None, // G_FPTOUI = 193
4009 CEFBS_None, // G_SITOFP = 194
4010 CEFBS_None, // G_UITOFP = 195
4011 CEFBS_None, // G_FABS = 196
4012 CEFBS_None, // G_FCOPYSIGN = 197
4013 CEFBS_None, // G_IS_FPCLASS = 198
4014 CEFBS_None, // G_FCANONICALIZE = 199
4015 CEFBS_None, // G_FMINNUM = 200
4016 CEFBS_None, // G_FMAXNUM = 201
4017 CEFBS_None, // G_FMINNUM_IEEE = 202
4018 CEFBS_None, // G_FMAXNUM_IEEE = 203
4019 CEFBS_None, // G_FMINIMUM = 204
4020 CEFBS_None, // G_FMAXIMUM = 205
4021 CEFBS_None, // G_GET_FPENV = 206
4022 CEFBS_None, // G_SET_FPENV = 207
4023 CEFBS_None, // G_RESET_FPENV = 208
4024 CEFBS_None, // G_GET_FPMODE = 209
4025 CEFBS_None, // G_SET_FPMODE = 210
4026 CEFBS_None, // G_RESET_FPMODE = 211
4027 CEFBS_None, // G_PTR_ADD = 212
4028 CEFBS_None, // G_PTRMASK = 213
4029 CEFBS_None, // G_SMIN = 214
4030 CEFBS_None, // G_SMAX = 215
4031 CEFBS_None, // G_UMIN = 216
4032 CEFBS_None, // G_UMAX = 217
4033 CEFBS_None, // G_ABS = 218
4034 CEFBS_None, // G_LROUND = 219
4035 CEFBS_None, // G_LLROUND = 220
4036 CEFBS_None, // G_BR = 221
4037 CEFBS_None, // G_BRJT = 222
4038 CEFBS_None, // G_VSCALE = 223
4039 CEFBS_None, // G_INSERT_SUBVECTOR = 224
4040 CEFBS_None, // G_EXTRACT_SUBVECTOR = 225
4041 CEFBS_None, // G_INSERT_VECTOR_ELT = 226
4042 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 227
4043 CEFBS_None, // G_SHUFFLE_VECTOR = 228
4044 CEFBS_None, // G_SPLAT_VECTOR = 229
4045 CEFBS_None, // G_VECTOR_COMPRESS = 230
4046 CEFBS_None, // G_CTTZ = 231
4047 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 232
4048 CEFBS_None, // G_CTLZ = 233
4049 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 234
4050 CEFBS_None, // G_CTPOP = 235
4051 CEFBS_None, // G_BSWAP = 236
4052 CEFBS_None, // G_BITREVERSE = 237
4053 CEFBS_None, // G_FCEIL = 238
4054 CEFBS_None, // G_FCOS = 239
4055 CEFBS_None, // G_FSIN = 240
4056 CEFBS_None, // G_FTAN = 241
4057 CEFBS_None, // G_FACOS = 242
4058 CEFBS_None, // G_FASIN = 243
4059 CEFBS_None, // G_FATAN = 244
4060 CEFBS_None, // G_FCOSH = 245
4061 CEFBS_None, // G_FSINH = 246
4062 CEFBS_None, // G_FTANH = 247
4063 CEFBS_None, // G_FSQRT = 248
4064 CEFBS_None, // G_FFLOOR = 249
4065 CEFBS_None, // G_FRINT = 250
4066 CEFBS_None, // G_FNEARBYINT = 251
4067 CEFBS_None, // G_ADDRSPACE_CAST = 252
4068 CEFBS_None, // G_BLOCK_ADDR = 253
4069 CEFBS_None, // G_JUMP_TABLE = 254
4070 CEFBS_None, // G_DYN_STACKALLOC = 255
4071 CEFBS_None, // G_STACKSAVE = 256
4072 CEFBS_None, // G_STACKRESTORE = 257
4073 CEFBS_None, // G_STRICT_FADD = 258
4074 CEFBS_None, // G_STRICT_FSUB = 259
4075 CEFBS_None, // G_STRICT_FMUL = 260
4076 CEFBS_None, // G_STRICT_FDIV = 261
4077 CEFBS_None, // G_STRICT_FREM = 262
4078 CEFBS_None, // G_STRICT_FMA = 263
4079 CEFBS_None, // G_STRICT_FSQRT = 264
4080 CEFBS_None, // G_STRICT_FLDEXP = 265
4081 CEFBS_None, // G_READ_REGISTER = 266
4082 CEFBS_None, // G_WRITE_REGISTER = 267
4083 CEFBS_None, // G_MEMCPY = 268
4084 CEFBS_None, // G_MEMCPY_INLINE = 269
4085 CEFBS_None, // G_MEMMOVE = 270
4086 CEFBS_None, // G_MEMSET = 271
4087 CEFBS_None, // G_BZERO = 272
4088 CEFBS_None, // G_TRAP = 273
4089 CEFBS_None, // G_DEBUGTRAP = 274
4090 CEFBS_None, // G_UBSANTRAP = 275
4091 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 276
4092 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 277
4093 CEFBS_None, // G_VECREDUCE_FADD = 278
4094 CEFBS_None, // G_VECREDUCE_FMUL = 279
4095 CEFBS_None, // G_VECREDUCE_FMAX = 280
4096 CEFBS_None, // G_VECREDUCE_FMIN = 281
4097 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 282
4098 CEFBS_None, // G_VECREDUCE_FMINIMUM = 283
4099 CEFBS_None, // G_VECREDUCE_ADD = 284
4100 CEFBS_None, // G_VECREDUCE_MUL = 285
4101 CEFBS_None, // G_VECREDUCE_AND = 286
4102 CEFBS_None, // G_VECREDUCE_OR = 287
4103 CEFBS_None, // G_VECREDUCE_XOR = 288
4104 CEFBS_None, // G_VECREDUCE_SMAX = 289
4105 CEFBS_None, // G_VECREDUCE_SMIN = 290
4106 CEFBS_None, // G_VECREDUCE_UMAX = 291
4107 CEFBS_None, // G_VECREDUCE_UMIN = 292
4108 CEFBS_None, // G_SBFX = 293
4109 CEFBS_None, // G_UBFX = 294
4110 CEFBS_None, // ADJCALLSTACKDOWN = 295
4111 CEFBS_None, // ADJCALLSTACKUP = 296
4112 CEFBS_None, // FI_ri = 297
4113 CEFBS_None, // MEMCPY = 298
4114 CEFBS_None, // Select = 299
4115 CEFBS_None, // Select_32 = 300
4116 CEFBS_None, // Select_32_64 = 301
4117 CEFBS_None, // Select_64_32 = 302
4118 CEFBS_None, // Select_Ri = 303
4119 CEFBS_None, // Select_Ri_32 = 304
4120 CEFBS_None, // Select_Ri_32_64 = 305
4121 CEFBS_None, // Select_Ri_64_32 = 306
4122 CEFBS_None, // ADDR_SPACE_CAST = 307
4123 CEFBS_None, // ADD_ri = 308
4124 CEFBS_None, // ADD_ri_32 = 309
4125 CEFBS_None, // ADD_rr = 310
4126 CEFBS_None, // ADD_rr_32 = 311
4127 CEFBS_None, // AND_ri = 312
4128 CEFBS_None, // AND_ri_32 = 313
4129 CEFBS_None, // AND_rr = 314
4130 CEFBS_None, // AND_rr_32 = 315
4131 CEFBS_None, // BE16 = 316
4132 CEFBS_None, // BE32 = 317
4133 CEFBS_None, // BE64 = 318
4134 CEFBS_None, // BSWAP16 = 319
4135 CEFBS_None, // BSWAP32 = 320
4136 CEFBS_None, // BSWAP64 = 321
4137 CEFBS_None, // CMPXCHGD = 322
4138 CEFBS_None, // CMPXCHGW32 = 323
4139 CEFBS_None, // CORE_LD32 = 324
4140 CEFBS_None, // CORE_LD64 = 325
4141 CEFBS_None, // CORE_SHIFT = 326
4142 CEFBS_None, // CORE_ST = 327
4143 CEFBS_None, // DIV_ri = 328
4144 CEFBS_None, // DIV_ri_32 = 329
4145 CEFBS_None, // DIV_rr = 330
4146 CEFBS_None, // DIV_rr_32 = 331
4147 CEFBS_None, // JAL = 332
4148 CEFBS_None, // JALX = 333
4149 CEFBS_None, // JCOND = 334
4150 CEFBS_None, // JEQ_ri = 335
4151 CEFBS_None, // JEQ_ri_32 = 336
4152 CEFBS_None, // JEQ_rr = 337
4153 CEFBS_None, // JEQ_rr_32 = 338
4154 CEFBS_None, // JMP = 339
4155 CEFBS_None, // JMPL = 340
4156 CEFBS_None, // JNE_ri = 341
4157 CEFBS_None, // JNE_ri_32 = 342
4158 CEFBS_None, // JNE_rr = 343
4159 CEFBS_None, // JNE_rr_32 = 344
4160 CEFBS_None, // JSET_ri = 345
4161 CEFBS_None, // JSET_ri_32 = 346
4162 CEFBS_None, // JSET_rr = 347
4163 CEFBS_None, // JSET_rr_32 = 348
4164 CEFBS_None, // JSGE_ri = 349
4165 CEFBS_None, // JSGE_ri_32 = 350
4166 CEFBS_None, // JSGE_rr = 351
4167 CEFBS_None, // JSGE_rr_32 = 352
4168 CEFBS_None, // JSGT_ri = 353
4169 CEFBS_None, // JSGT_ri_32 = 354
4170 CEFBS_None, // JSGT_rr = 355
4171 CEFBS_None, // JSGT_rr_32 = 356
4172 CEFBS_None, // JSLE_ri = 357
4173 CEFBS_None, // JSLE_ri_32 = 358
4174 CEFBS_None, // JSLE_rr = 359
4175 CEFBS_None, // JSLE_rr_32 = 360
4176 CEFBS_None, // JSLT_ri = 361
4177 CEFBS_None, // JSLT_ri_32 = 362
4178 CEFBS_None, // JSLT_rr = 363
4179 CEFBS_None, // JSLT_rr_32 = 364
4180 CEFBS_None, // JUGE_ri = 365
4181 CEFBS_None, // JUGE_ri_32 = 366
4182 CEFBS_None, // JUGE_rr = 367
4183 CEFBS_None, // JUGE_rr_32 = 368
4184 CEFBS_None, // JUGT_ri = 369
4185 CEFBS_None, // JUGT_ri_32 = 370
4186 CEFBS_None, // JUGT_rr = 371
4187 CEFBS_None, // JUGT_rr_32 = 372
4188 CEFBS_None, // JULE_ri = 373
4189 CEFBS_None, // JULE_ri_32 = 374
4190 CEFBS_None, // JULE_rr = 375
4191 CEFBS_None, // JULE_rr_32 = 376
4192 CEFBS_None, // JULT_ri = 377
4193 CEFBS_None, // JULT_ri_32 = 378
4194 CEFBS_None, // JULT_rr = 379
4195 CEFBS_None, // JULT_rr_32 = 380
4196 CEFBS_None, // LDB = 381
4197 CEFBS_None, // LDB32 = 382
4198 CEFBS_None, // LDBSX = 383
4199 CEFBS_None, // LDD = 384
4200 CEFBS_None, // LDH = 385
4201 CEFBS_None, // LDH32 = 386
4202 CEFBS_None, // LDHSX = 387
4203 CEFBS_None, // LDW = 388
4204 CEFBS_None, // LDW32 = 389
4205 CEFBS_None, // LDWSX = 390
4206 CEFBS_None, // LD_ABS_B = 391
4207 CEFBS_None, // LD_ABS_H = 392
4208 CEFBS_None, // LD_ABS_W = 393
4209 CEFBS_None, // LD_IND_B = 394
4210 CEFBS_None, // LD_IND_H = 395
4211 CEFBS_None, // LD_IND_W = 396
4212 CEFBS_None, // LD_imm64 = 397
4213 CEFBS_None, // LD_pseudo = 398
4214 CEFBS_None, // LE16 = 399
4215 CEFBS_None, // LE32 = 400
4216 CEFBS_None, // LE64 = 401
4217 CEFBS_None, // MOD_ri = 402
4218 CEFBS_None, // MOD_ri_32 = 403
4219 CEFBS_None, // MOD_rr = 404
4220 CEFBS_None, // MOD_rr_32 = 405
4221 CEFBS_None, // MOVSX_rr_16 = 406
4222 CEFBS_None, // MOVSX_rr_32 = 407
4223 CEFBS_None, // MOVSX_rr_32_16 = 408
4224 CEFBS_None, // MOVSX_rr_32_8 = 409
4225 CEFBS_None, // MOVSX_rr_8 = 410
4226 CEFBS_None, // MOV_32_64 = 411
4227 CEFBS_None, // MOV_ri = 412
4228 CEFBS_None, // MOV_ri_32 = 413
4229 CEFBS_None, // MOV_rr = 414
4230 CEFBS_None, // MOV_rr_32 = 415
4231 CEFBS_None, // MUL_ri = 416
4232 CEFBS_None, // MUL_ri_32 = 417
4233 CEFBS_None, // MUL_rr = 418
4234 CEFBS_None, // MUL_rr_32 = 419
4235 CEFBS_None, // NEG_32 = 420
4236 CEFBS_None, // NEG_64 = 421
4237 CEFBS_None, // NOP = 422
4238 CEFBS_None, // OR_ri = 423
4239 CEFBS_None, // OR_ri_32 = 424
4240 CEFBS_None, // OR_rr = 425
4241 CEFBS_None, // OR_rr_32 = 426
4242 CEFBS_None, // RET = 427
4243 CEFBS_None, // SDIV_ri = 428
4244 CEFBS_None, // SDIV_ri_32 = 429
4245 CEFBS_None, // SDIV_rr = 430
4246 CEFBS_None, // SDIV_rr_32 = 431
4247 CEFBS_None, // SLL_ri = 432
4248 CEFBS_None, // SLL_ri_32 = 433
4249 CEFBS_None, // SLL_rr = 434
4250 CEFBS_None, // SLL_rr_32 = 435
4251 CEFBS_None, // SMOD_ri = 436
4252 CEFBS_None, // SMOD_ri_32 = 437
4253 CEFBS_None, // SMOD_rr = 438
4254 CEFBS_None, // SMOD_rr_32 = 439
4255 CEFBS_None, // SRA_ri = 440
4256 CEFBS_None, // SRA_ri_32 = 441
4257 CEFBS_None, // SRA_rr = 442
4258 CEFBS_None, // SRA_rr_32 = 443
4259 CEFBS_None, // SRL_ri = 444
4260 CEFBS_None, // SRL_ri_32 = 445
4261 CEFBS_None, // SRL_rr = 446
4262 CEFBS_None, // SRL_rr_32 = 447
4263 CEFBS_None, // STB = 448
4264 CEFBS_None, // STB32 = 449
4265 CEFBS_None, // STB_imm = 450
4266 CEFBS_None, // STD = 451
4267 CEFBS_None, // STD_imm = 452
4268 CEFBS_None, // STH = 453
4269 CEFBS_None, // STH32 = 454
4270 CEFBS_None, // STH_imm = 455
4271 CEFBS_None, // STW = 456
4272 CEFBS_None, // STW32 = 457
4273 CEFBS_None, // STW_imm = 458
4274 CEFBS_None, // SUB_ri = 459
4275 CEFBS_None, // SUB_ri_32 = 460
4276 CEFBS_None, // SUB_rr = 461
4277 CEFBS_None, // SUB_rr_32 = 462
4278 CEFBS_None, // XADDD = 463
4279 CEFBS_None, // XADDW = 464
4280 CEFBS_None, // XADDW32 = 465
4281 CEFBS_None, // XANDD = 466
4282 CEFBS_None, // XANDW32 = 467
4283 CEFBS_None, // XCHGD = 468
4284 CEFBS_None, // XCHGW32 = 469
4285 CEFBS_None, // XFADDD = 470
4286 CEFBS_None, // XFADDW32 = 471
4287 CEFBS_None, // XFANDD = 472
4288 CEFBS_None, // XFANDW32 = 473
4289 CEFBS_None, // XFORD = 474
4290 CEFBS_None, // XFORW32 = 475
4291 CEFBS_None, // XFXORD = 476
4292 CEFBS_None, // XFXORW32 = 477
4293 CEFBS_None, // XORD = 478
4294 CEFBS_None, // XORW32 = 479
4295 CEFBS_None, // XOR_ri = 480
4296 CEFBS_None, // XOR_ri_32 = 481
4297 CEFBS_None, // XOR_rr = 482
4298 CEFBS_None, // XOR_rr_32 = 483
4299 CEFBS_None, // XXORD = 484
4300 CEFBS_None, // XXORW32 = 485
4301 };
4302
4303 assert(Opcode < 486);
4304 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
4305}
4306
4307} // end namespace BPF_MC
4308} // end namespace llvm
4309#endif // GET_COMPUTE_FEATURES
4310
4311#ifdef GET_AVAILABLE_OPCODE_CHECKER
4312#undef GET_AVAILABLE_OPCODE_CHECKER
4313namespace llvm {
4314namespace BPF_MC {
4315bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
4316 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4317 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4318 FeatureBitset MissingFeatures =
4319 (AvailableFeatures & RequiredFeatures) ^
4320 RequiredFeatures;
4321 return !MissingFeatures.any();
4322}
4323} // end namespace BPF_MC
4324} // end namespace llvm
4325#endif // GET_AVAILABLE_OPCODE_CHECKER
4326
4327#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
4328#undef ENABLE_INSTR_PREDICATE_VERIFIER
4329#include <sstream>
4330
4331namespace llvm {
4332namespace BPF_MC {
4333
4334#ifndef NDEBUG
4335static const char *SubtargetFeatureNames[] = {
4336 nullptr
4337};
4338
4339#endif // NDEBUG
4340
4341void verifyInstructionPredicates(
4342 unsigned Opcode, const FeatureBitset &Features) {
4343#ifndef NDEBUG
4344 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4345 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4346 FeatureBitset MissingFeatures =
4347 (AvailableFeatures & RequiredFeatures) ^
4348 RequiredFeatures;
4349 if (MissingFeatures.any()) {
4350 std::ostringstream Msg;
4351 Msg << "Attempting to emit " << &BPFInstrNameData[BPFInstrNameIndices[Opcode]]
4352 << " instruction but the ";
4353 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
4354 if (MissingFeatures.test(i))
4355 Msg << SubtargetFeatureNames[i] << " ";
4356 Msg << "predicate(s) are not met";
4357 report_fatal_error(Msg.str().c_str());
4358 }
4359#endif // NDEBUG
4360}
4361} // end namespace BPF_MC
4362} // end namespace llvm
4363#endif // ENABLE_INSTR_PREDICATE_VERIFIER
4364
4365