1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass BPFMCRegisterClasses[];
17
18namespace BPF {
19enum {
20 NoRegister,
21 R0 = 1,
22 R1 = 2,
23 R2 = 3,
24 R3 = 4,
25 R4 = 5,
26 R5 = 6,
27 R6 = 7,
28 R7 = 8,
29 R8 = 9,
30 R9 = 10,
31 R10 = 11,
32 R11 = 12,
33 W0 = 13,
34 W1 = 14,
35 W2 = 15,
36 W3 = 16,
37 W4 = 17,
38 W5 = 18,
39 W6 = 19,
40 W7 = 20,
41 W8 = 21,
42 W9 = 22,
43 W10 = 23,
44 W11 = 24,
45 NUM_TARGET_REGS // 25
46};
47} // end namespace BPF
48
49// Register classes
50
51namespace BPF {
52enum {
53 GPR32RegClassID = 0,
54 GPRRegClassID = 1,
55
56};
57} // end namespace BPF
58
59
60// Subregister indices
61
62namespace BPF {
63enum : uint16_t {
64 NoSubRegister,
65 sub_32, // 1
66 NUM_TARGET_SUBREGS
67};
68} // end namespace BPF
69
70// Register pressure sets enum.
71namespace BPF {
72enum RegisterPressureSets {
73 GPR32 = 0,
74};
75} // end namespace BPF
76
77} // end namespace llvm
78
79#endif // GET_REGINFO_ENUM
80
81/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
82|* *|
83|* MC Register Information *|
84|* *|
85|* Automatically generated file, do not edit! *|
86|* *|
87\*===----------------------------------------------------------------------===*/
88
89
90#ifdef GET_REGINFO_MC_DESC
91#undef GET_REGINFO_MC_DESC
92
93namespace llvm {
94
95extern const int16_t BPFRegDiffLists[] = {
96 /* 0 */ -12, 0,
97 /* 2 */ 12, 0,
98};
99
100extern const LaneBitmask BPFLaneMaskLists[] = {
101 /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
102 /* 2 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
103};
104
105extern const uint16_t BPFSubRegIdxLists[] = {
106 /* 0 */ 1, 0,
107};
108
109
110#ifdef __GNUC__
111#pragma GCC diagnostic push
112#pragma GCC diagnostic ignored "-Woverlength-strings"
113#endif
114extern const char BPFRegStrings[] = {
115 /* 0 */ "R10\0"
116 /* 4 */ "W10\0"
117 /* 8 */ "R0\0"
118 /* 11 */ "W0\0"
119 /* 14 */ "R11\0"
120 /* 18 */ "W11\0"
121 /* 22 */ "R1\0"
122 /* 25 */ "W1\0"
123 /* 28 */ "R2\0"
124 /* 31 */ "W2\0"
125 /* 34 */ "R3\0"
126 /* 37 */ "W3\0"
127 /* 40 */ "R4\0"
128 /* 43 */ "W4\0"
129 /* 46 */ "R5\0"
130 /* 49 */ "W5\0"
131 /* 52 */ "R6\0"
132 /* 55 */ "W6\0"
133 /* 58 */ "R7\0"
134 /* 61 */ "W7\0"
135 /* 64 */ "R8\0"
136 /* 67 */ "W8\0"
137 /* 70 */ "R9\0"
138 /* 73 */ "W9\0"
139};
140#ifdef __GNUC__
141#pragma GCC diagnostic pop
142#endif
143
144extern const MCRegisterDesc BPFRegDesc[] = { // Descriptors
145 { 3, 0, 0, 0, 0, 0, 0 },
146 { 8, 2, 1, 0, 4096, 0, 0 },
147 { 22, 2, 1, 0, 4097, 0, 0 },
148 { 28, 2, 1, 0, 4098, 0, 0 },
149 { 34, 2, 1, 0, 4099, 0, 0 },
150 { 40, 2, 1, 0, 4100, 0, 0 },
151 { 46, 2, 1, 0, 4101, 0, 0 },
152 { 52, 2, 1, 0, 4102, 0, 0 },
153 { 58, 2, 1, 0, 4103, 0, 0 },
154 { 64, 2, 1, 0, 4104, 0, 0 },
155 { 70, 2, 1, 0, 4105, 0, 0 },
156 { 0, 2, 1, 0, 4106, 0, 0 },
157 { 14, 2, 1, 0, 4107, 0, 0 },
158 { 11, 1, 0, 1, 4096, 2, 0 },
159 { 25, 1, 0, 1, 4097, 2, 0 },
160 { 31, 1, 0, 1, 4098, 2, 0 },
161 { 37, 1, 0, 1, 4099, 2, 0 },
162 { 43, 1, 0, 1, 4100, 2, 0 },
163 { 49, 1, 0, 1, 4101, 2, 0 },
164 { 55, 1, 0, 1, 4102, 2, 0 },
165 { 61, 1, 0, 1, 4103, 2, 0 },
166 { 67, 1, 0, 1, 4104, 2, 0 },
167 { 73, 1, 0, 1, 4105, 2, 0 },
168 { 4, 1, 0, 1, 4106, 2, 0 },
169 { 18, 1, 0, 1, 4107, 2, 0 },
170};
171
172extern const MCPhysReg BPFRegUnitRoots[][2] = {
173 { BPF::W0 },
174 { BPF::W1 },
175 { BPF::W2 },
176 { BPF::W3 },
177 { BPF::W4 },
178 { BPF::W5 },
179 { BPF::W6 },
180 { BPF::W7 },
181 { BPF::W8 },
182 { BPF::W9 },
183 { BPF::W10 },
184 { BPF::W11 },
185};
186
187namespace { // Register classes...
188 // GPR32 Register Class...
189 const MCPhysReg GPR32[] = {
190 BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5, BPF::W6, BPF::W7, BPF::W8, BPF::W9, BPF::W0, BPF::W11, BPF::W10,
191 };
192
193 // GPR32 Bit set.
194 const uint8_t GPR32Bits[] = {
195 0x00, 0xe0, 0xff, 0x01,
196 };
197
198 // GPR Register Class...
199 const MCPhysReg GPR[] = {
200 BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R0, BPF::R11, BPF::R10,
201 };
202
203 // GPR Bit set.
204 const uint8_t GPRBits[] = {
205 0xfe, 0x1f,
206 };
207
208} // end anonymous namespace
209
210
211#ifdef __GNUC__
212#pragma GCC diagnostic push
213#pragma GCC diagnostic ignored "-Woverlength-strings"
214#endif
215extern const char BPFRegClassStrings[] = {
216 /* 0 */ "GPR32\0"
217 /* 6 */ "GPR\0"
218};
219#ifdef __GNUC__
220#pragma GCC diagnostic pop
221#endif
222
223extern const MCRegisterClass BPFMCRegisterClasses[] = {
224 { GPR32, GPR32Bits, 0, 12, sizeof(GPR32Bits), BPF::GPR32RegClassID, 32, 1, true, false },
225 { GPR, GPRBits, 6, 12, sizeof(GPRBits), BPF::GPRRegClassID, 64, 1, true, false },
226};
227
228// BPF Dwarf<->LLVM register mappings.
229extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[] = {
230 { 0U, BPF::W0 },
231 { 1U, BPF::W1 },
232 { 2U, BPF::W2 },
233 { 3U, BPF::W3 },
234 { 4U, BPF::W4 },
235 { 5U, BPF::W5 },
236 { 6U, BPF::W6 },
237 { 7U, BPF::W7 },
238 { 8U, BPF::W8 },
239 { 9U, BPF::W9 },
240 { 10U, BPF::W10 },
241 { 11U, BPF::W11 },
242};
243extern const unsigned BPFDwarfFlavour0Dwarf2LSize = std::size(BPFDwarfFlavour0Dwarf2L);
244
245extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[] = {
246 { 0U, BPF::W0 },
247 { 1U, BPF::W1 },
248 { 2U, BPF::W2 },
249 { 3U, BPF::W3 },
250 { 4U, BPF::W4 },
251 { 5U, BPF::W5 },
252 { 6U, BPF::W6 },
253 { 7U, BPF::W7 },
254 { 8U, BPF::W8 },
255 { 9U, BPF::W9 },
256 { 10U, BPF::W10 },
257 { 11U, BPF::W11 },
258};
259extern const unsigned BPFEHFlavour0Dwarf2LSize = std::size(BPFEHFlavour0Dwarf2L);
260
261extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[] = {
262 { BPF::R0, 0U },
263 { BPF::R1, 1U },
264 { BPF::R2, 2U },
265 { BPF::R3, 3U },
266 { BPF::R4, 4U },
267 { BPF::R5, 5U },
268 { BPF::R6, 6U },
269 { BPF::R7, 7U },
270 { BPF::R8, 8U },
271 { BPF::R9, 9U },
272 { BPF::R10, 10U },
273 { BPF::R11, 11U },
274 { BPF::W0, 0U },
275 { BPF::W1, 1U },
276 { BPF::W2, 2U },
277 { BPF::W3, 3U },
278 { BPF::W4, 4U },
279 { BPF::W5, 5U },
280 { BPF::W6, 6U },
281 { BPF::W7, 7U },
282 { BPF::W8, 8U },
283 { BPF::W9, 9U },
284 { BPF::W10, 10U },
285 { BPF::W11, 11U },
286};
287extern const unsigned BPFDwarfFlavour0L2DwarfSize = std::size(BPFDwarfFlavour0L2Dwarf);
288
289extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[] = {
290 { BPF::R0, 0U },
291 { BPF::R1, 1U },
292 { BPF::R2, 2U },
293 { BPF::R3, 3U },
294 { BPF::R4, 4U },
295 { BPF::R5, 5U },
296 { BPF::R6, 6U },
297 { BPF::R7, 7U },
298 { BPF::R8, 8U },
299 { BPF::R9, 9U },
300 { BPF::R10, 10U },
301 { BPF::R11, 11U },
302 { BPF::W0, 0U },
303 { BPF::W1, 1U },
304 { BPF::W2, 2U },
305 { BPF::W3, 3U },
306 { BPF::W4, 4U },
307 { BPF::W5, 5U },
308 { BPF::W6, 6U },
309 { BPF::W7, 7U },
310 { BPF::W8, 8U },
311 { BPF::W9, 9U },
312 { BPF::W10, 10U },
313 { BPF::W11, 11U },
314};
315extern const unsigned BPFEHFlavour0L2DwarfSize = std::size(BPFEHFlavour0L2Dwarf);
316
317extern const uint16_t BPFRegEncodingTable[] = {
318 0,
319 0,
320 1,
321 2,
322 3,
323 4,
324 5,
325 6,
326 7,
327 8,
328 9,
329 10,
330 11,
331 0,
332 1,
333 2,
334 3,
335 4,
336 5,
337 6,
338 7,
339 8,
340 9,
341 10,
342 11,
343};
344static inline void InitBPFMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
345 RI->InitMCRegisterInfo(BPFRegDesc, 25, RA, PC, BPFMCRegisterClasses, 2, BPFRegUnitRoots, 12, BPFRegDiffLists, BPFLaneMaskLists, BPFRegStrings, BPFRegClassStrings, BPFSubRegIdxLists, 2,
346BPFRegEncodingTable);
347
348 switch (DwarfFlavour) {
349 default:
350 llvm_unreachable("Unknown DWARF flavour");
351 case 0:
352 RI->mapDwarfRegsToLLVMRegs(BPFDwarfFlavour0Dwarf2L, BPFDwarfFlavour0Dwarf2LSize, false);
353 break;
354 }
355 switch (EHFlavour) {
356 default:
357 llvm_unreachable("Unknown DWARF flavour");
358 case 0:
359 RI->mapDwarfRegsToLLVMRegs(BPFEHFlavour0Dwarf2L, BPFEHFlavour0Dwarf2LSize, true);
360 break;
361 }
362 switch (DwarfFlavour) {
363 default:
364 llvm_unreachable("Unknown DWARF flavour");
365 case 0:
366 RI->mapLLVMRegsToDwarfRegs(BPFDwarfFlavour0L2Dwarf, BPFDwarfFlavour0L2DwarfSize, false);
367 break;
368 }
369 switch (EHFlavour) {
370 default:
371 llvm_unreachable("Unknown DWARF flavour");
372 case 0:
373 RI->mapLLVMRegsToDwarfRegs(BPFEHFlavour0L2Dwarf, BPFEHFlavour0L2DwarfSize, true);
374 break;
375 }
376}
377
378} // end namespace llvm
379
380#endif // GET_REGINFO_MC_DESC
381
382/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
383|* *|
384|* Register Information Header Fragment *|
385|* *|
386|* Automatically generated file, do not edit! *|
387|* *|
388\*===----------------------------------------------------------------------===*/
389
390
391#ifdef GET_REGINFO_HEADER
392#undef GET_REGINFO_HEADER
393
394#include "llvm/CodeGen/TargetRegisterInfo.h"
395
396namespace llvm {
397
398class BPFFrameLowering;
399
400struct BPFGenRegisterInfo : public TargetRegisterInfo {
401 explicit BPFGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
402 unsigned PC = 0, unsigned HwMode = 0);
403 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
404 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
405 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
406 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
407 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
408 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
409 unsigned getRegUnitWeight(unsigned RegUnit) const override;
410 unsigned getNumRegPressureSets() const override;
411 const char *getRegPressureSetName(unsigned Idx) const override;
412 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
413 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
414 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
415 ArrayRef<const char *> getRegMaskNames() const override;
416 ArrayRef<const uint32_t *> getRegMasks() const override;
417 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
418 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
419 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
420 bool isConstantPhysReg(MCRegister PhysReg) const override final;
421 /// Devirtualized TargetFrameLowering.
422 static const BPFFrameLowering *getFrameLowering(
423 const MachineFunction &MF);
424};
425
426namespace BPF { // Register classes
427 extern const TargetRegisterClass GPR32RegClass;
428 extern const TargetRegisterClass GPRRegClass;
429} // end namespace BPF
430
431} // end namespace llvm
432
433#endif // GET_REGINFO_HEADER
434
435/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
436|* *|
437|* Target Register and Register Classes Information *|
438|* *|
439|* Automatically generated file, do not edit! *|
440|* *|
441\*===----------------------------------------------------------------------===*/
442
443
444#ifdef GET_REGINFO_TARGET_DESC
445#undef GET_REGINFO_TARGET_DESC
446
447namespace llvm {
448
449extern const MCRegisterClass BPFMCRegisterClasses[];
450
451static const MVT::SimpleValueType VTLists[] = {
452 /* 0 */ MVT::i32, MVT::Other,
453 /* 2 */ MVT::i64, MVT::Other,
454};
455
456static const char *SubRegIndexNameTable[] = { "sub_32", "" };
457
458static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
459 { 65535, 65535 },
460 { 0, 32 }, // sub_32
461};
462
463
464static const LaneBitmask SubRegIndexLaneMaskTable[] = {
465 LaneBitmask::getAll(),
466 LaneBitmask(0x0000000000000001), // sub_32
467 };
468
469
470
471static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
472 // Mode = 0 (Default)
473 { 32, 32, 64, /*VTLists+*/0 }, // GPR32
474 { 64, 64, 64, /*VTLists+*/2 }, // GPR
475};
476
477static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
478
479static const uint32_t GPR32SubClassMask[] = {
480 0x00000001,
481 0x00000002, // sub_32
482};
483
484static const uint32_t GPRSubClassMask[] = {
485 0x00000002,
486};
487
488static const uint16_t SuperRegIdxSeqs[] = {
489 /* 0 */ 1, 0,
490};
491
492
493namespace BPF { // Register class instances
494 extern const TargetRegisterClass GPR32RegClass = {
495 &BPFMCRegisterClasses[GPR32RegClassID],
496 GPR32SubClassMask,
497 SuperRegIdxSeqs + 0,
498 LaneBitmask(0x0000000000000001),
499 0,
500 false,
501 0x00, /* TSFlags */
502 false, /* HasDisjunctSubRegs */
503 false, /* CoveredBySubRegs */
504 NullRegClasses,
505 nullptr
506 };
507
508 extern const TargetRegisterClass GPRRegClass = {
509 &BPFMCRegisterClasses[GPRRegClassID],
510 GPRSubClassMask,
511 SuperRegIdxSeqs + 1,
512 LaneBitmask(0x0000000000000001),
513 0,
514 false,
515 0x00, /* TSFlags */
516 false, /* HasDisjunctSubRegs */
517 false, /* CoveredBySubRegs */
518 NullRegClasses,
519 nullptr
520 };
521
522} // end namespace BPF
523
524namespace {
525 const TargetRegisterClass *const RegisterClasses[] = {
526 &BPF::GPR32RegClass,
527 &BPF::GPRRegClass,
528 };
529} // end anonymous namespace
530
531static const uint8_t CostPerUseTable[] = {
5320, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
533
534
535static const bool InAllocatableClassTable[] = {
536false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
537
538
539static const TargetRegisterInfoDesc BPFRegInfoDesc = { // Extra Descriptors
540CostPerUseTable, 1, InAllocatableClassTable};
541
542unsigned BPFGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
543 static const uint8_t Rows[1][1] = {
544 { 0, },
545 };
546
547 --IdxA; assert(IdxA < 1); (void) IdxA;
548 --IdxB; assert(IdxB < 1);
549 return Rows[0][IdxB];
550}
551
552 struct MaskRolOp {
553 LaneBitmask Mask;
554 uint8_t RotateLeft;
555 };
556 static const MaskRolOp LaneMaskComposeSequences[] = {
557 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 } // Sequence 0
558 };
559 static const uint8_t CompositeSequences[] = {
560 0 // to sub_32
561 };
562
563LaneBitmask BPFGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
564 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
565 LaneBitmask Result;
566 for (const MaskRolOp *Ops =
567 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
568 Ops->Mask.any(); ++Ops) {
569 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
570 if (unsigned S = Ops->RotateLeft)
571 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
572 else
573 Result |= LaneBitmask(M);
574 }
575 return Result;
576}
577
578LaneBitmask BPFGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
579 LaneMask &= getSubRegIndexLaneMask(IdxA);
580 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
581 LaneBitmask Result;
582 for (const MaskRolOp *Ops =
583 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
584 Ops->Mask.any(); ++Ops) {
585 LaneBitmask::Type M = LaneMask.getAsInteger();
586 if (unsigned S = Ops->RotateLeft)
587 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
588 else
589 Result |= LaneBitmask(M);
590 }
591 return Result;
592}
593
594const TargetRegisterClass *BPFGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
595 static const uint8_t Table[2][1] = {
596 { // GPR32
597 0, // sub_32
598 },
599 { // GPR
600 2, // sub_32 -> GPR
601 },
602 };
603 assert(RC && "Missing regclass");
604 if (!Idx) return RC;
605 --Idx;
606 assert(Idx < 1 && "Bad subreg");
607 unsigned TV = Table[RC->getID()][Idx];
608 return TV ? getRegClass(TV - 1) : nullptr;
609}
610
611const TargetRegisterClass *BPFGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
612 static const uint8_t Table[2][1] = {
613 { // GPR32
614 0, // GPR32:sub_32
615 },
616 { // GPR
617 1, // GPR:sub_32 -> GPR32
618 },
619 };
620 assert(RC && "Missing regclass");
621 if (!Idx) return RC;
622 --Idx;
623 assert(Idx < 1 && "Bad subreg");
624 unsigned TV = Table[RC->getID()][Idx];
625 return TV ? getRegClass(TV - 1) : nullptr;
626}
627
628/// Get the weight in units of pressure for this register class.
629const RegClassWeight &BPFGenRegisterInfo::
630getRegClassWeight(const TargetRegisterClass *RC) const {
631 static const RegClassWeight RCWeightTable[] = {
632 {1, 12}, // GPR32
633 {1, 12}, // GPR
634 };
635 return RCWeightTable[RC->getID()];
636}
637
638/// Get the weight in units of pressure for this register unit.
639unsigned BPFGenRegisterInfo::
640getRegUnitWeight(unsigned RegUnit) const {
641 assert(RegUnit < 12 && "invalid register unit");
642 // All register units have unit weight.
643 return 1;
644}
645
646
647// Get the number of dimensions of register pressure.
648unsigned BPFGenRegisterInfo::getNumRegPressureSets() const {
649 return 1;
650}
651
652// Get the name of this register unit pressure set.
653const char *BPFGenRegisterInfo::
654getRegPressureSetName(unsigned Idx) const {
655 static const char *PressureNameTable[] = {
656 "GPR32",
657 };
658 return PressureNameTable[Idx];
659}
660
661// Get the register unit pressure limit for this dimension.
662// This limit must be adjusted dynamically for reserved registers.
663unsigned BPFGenRegisterInfo::
664getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
665 static const uint8_t PressureLimitTable[] = {
666 12, // 0: GPR32
667 };
668 return PressureLimitTable[Idx];
669}
670
671/// Table of pressure sets per register class or unit.
672static const int RCSetsTable[] = {
673 /* 0 */ 0, -1,
674};
675
676/// Get the dimensions of register pressure impacted by this register class.
677/// Returns a -1 terminated array of pressure set IDs
678const int *BPFGenRegisterInfo::
679getRegClassPressureSets(const TargetRegisterClass *RC) const {
680 static const uint8_t RCSetStartTable[] = {
681 0,0,};
682 return &RCSetsTable[RCSetStartTable[RC->getID()]];
683}
684
685/// Get the dimensions of register pressure impacted by this register unit.
686/// Returns a -1 terminated array of pressure set IDs
687const int *BPFGenRegisterInfo::
688getRegUnitPressureSets(unsigned RegUnit) const {
689 assert(RegUnit < 12 && "invalid register unit");
690 static const uint8_t RUSetStartTable[] = {
691 0,0,0,0,0,0,0,0,0,0,0,0,};
692 return &RCSetsTable[RUSetStartTable[RegUnit]];
693}
694
695extern const MCRegisterDesc BPFRegDesc[];
696extern const int16_t BPFRegDiffLists[];
697extern const LaneBitmask BPFLaneMaskLists[];
698extern const char BPFRegStrings[];
699extern const char BPFRegClassStrings[];
700extern const MCPhysReg BPFRegUnitRoots[][2];
701extern const uint16_t BPFSubRegIdxLists[];
702extern const uint16_t BPFRegEncodingTable[];
703// BPF Dwarf<->LLVM register mappings.
704extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[];
705extern const unsigned BPFDwarfFlavour0Dwarf2LSize;
706
707extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[];
708extern const unsigned BPFEHFlavour0Dwarf2LSize;
709
710extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[];
711extern const unsigned BPFDwarfFlavour0L2DwarfSize;
712
713extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[];
714extern const unsigned BPFEHFlavour0L2DwarfSize;
715
716BPFGenRegisterInfo::
717BPFGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
718 unsigned PC, unsigned HwMode)
719 : TargetRegisterInfo(&BPFRegInfoDesc, RegisterClasses, RegisterClasses+2,
720 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
721 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
722 InitMCRegisterInfo(BPFRegDesc, 25, RA, PC,
723 BPFMCRegisterClasses, 2,
724 BPFRegUnitRoots,
725 12,
726 BPFRegDiffLists,
727 BPFLaneMaskLists,
728 BPFRegStrings,
729 BPFRegClassStrings,
730 BPFSubRegIdxLists,
731 2,
732 BPFRegEncodingTable);
733
734 switch (DwarfFlavour) {
735 default:
736 llvm_unreachable("Unknown DWARF flavour");
737 case 0:
738 mapDwarfRegsToLLVMRegs(BPFDwarfFlavour0Dwarf2L, BPFDwarfFlavour0Dwarf2LSize, false);
739 break;
740 }
741 switch (EHFlavour) {
742 default:
743 llvm_unreachable("Unknown DWARF flavour");
744 case 0:
745 mapDwarfRegsToLLVMRegs(BPFEHFlavour0Dwarf2L, BPFEHFlavour0Dwarf2LSize, true);
746 break;
747 }
748 switch (DwarfFlavour) {
749 default:
750 llvm_unreachable("Unknown DWARF flavour");
751 case 0:
752 mapLLVMRegsToDwarfRegs(BPFDwarfFlavour0L2Dwarf, BPFDwarfFlavour0L2DwarfSize, false);
753 break;
754 }
755 switch (EHFlavour) {
756 default:
757 llvm_unreachable("Unknown DWARF flavour");
758 case 0:
759 mapLLVMRegsToDwarfRegs(BPFEHFlavour0L2Dwarf, BPFEHFlavour0L2DwarfSize, true);
760 break;
761 }
762}
763
764static const MCPhysReg CSR_SaveList[] = { BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
765static const uint32_t CSR_RegMask[] = { 0x00f80f80, };
766
767
768ArrayRef<const uint32_t *> BPFGenRegisterInfo::getRegMasks() const {
769 static const uint32_t *const Masks[] = {
770 CSR_RegMask,
771 };
772 return ArrayRef(Masks);
773}
774
775bool BPFGenRegisterInfo::
776isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
777 return
778 false;
779}
780
781bool BPFGenRegisterInfo::
782isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
783 return
784 false;
785}
786
787bool BPFGenRegisterInfo::
788isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
789 return
790 false;
791}
792
793bool BPFGenRegisterInfo::
794isConstantPhysReg(MCRegister PhysReg) const {
795 return
796 false;
797}
798
799ArrayRef<const char *> BPFGenRegisterInfo::getRegMaskNames() const {
800 static const char *Names[] = {
801 "CSR",
802 };
803 return ArrayRef(Names);
804}
805
806const BPFFrameLowering *
807BPFGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
808 return static_cast<const BPFFrameLowering *>(
809 MF.getSubtarget().getFrameLowering());
810}
811
812} // end namespace llvm
813
814#endif // GET_REGINFO_TARGET_DESC
815
816