1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace BPF {
15enum {
16 ALU32 = 0,
17 DummyFeature = 1,
18 DwarfRIS = 2,
19 NumSubtargetFeatures = 3
20};
21} // end namespace BPF
22} // end namespace llvm
23
24#endif // GET_SUBTARGETINFO_ENUM
25
26
27#ifdef GET_SUBTARGETINFO_MACRO
28GET_SUBTARGETINFO_MACRO(HasAlu32, false, hasAlu32)
29GET_SUBTARGETINFO_MACRO(UseDwarfRIS, false, useDwarfRIS)
30GET_SUBTARGETINFO_MACRO(isDummyMode, false, isDummyMode)
31#undef GET_SUBTARGETINFO_MACRO
32#endif // GET_SUBTARGETINFO_MACRO
33
34
35#ifdef GET_SUBTARGETINFO_MC_DESC
36#undef GET_SUBTARGETINFO_MC_DESC
37
38namespace llvm {
39// Sorted (by key) array of values for CPU features.
40extern const llvm::SubtargetFeatureKV BPFFeatureKV[] = {
41 { "alu32", "Enable ALU32 instructions", BPF::ALU32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
42 { "dummy", "unused feature", BPF::DummyFeature, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
43 { "dwarfris", "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections", BPF::DwarfRIS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
44};
45
46#ifdef DBGFIELD
47#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
48#endif
49#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
50#define DBGFIELD(x) x,
51#else
52#define DBGFIELD(x)
53#endif
54
55// ===============================================================
56// Data tables for the new per-operand machine model.
57
58// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
59extern const llvm::MCWriteProcResEntry BPFWriteProcResTable[] = {
60 { 0, 0, 0 }, // Invalid
61}; // BPFWriteProcResTable
62
63// {Cycles, WriteResourceID}
64extern const llvm::MCWriteLatencyEntry BPFWriteLatencyTable[] = {
65 { 0, 0}, // Invalid
66}; // BPFWriteLatencyTable
67
68// {UseIdx, WriteResourceID, Cycles}
69extern const llvm::MCReadAdvanceEntry BPFReadAdvanceTable[] = {
70 {0, 0, 0}, // Invalid
71}; // BPFReadAdvanceTable
72
73#undef DBGFIELD
74
75static const llvm::MCSchedModel NoSchedModel = {
76 MCSchedModel::DefaultIssueWidth,
77 MCSchedModel::DefaultMicroOpBufferSize,
78 MCSchedModel::DefaultLoopMicroOpBufferSize,
79 MCSchedModel::DefaultLoadLatency,
80 MCSchedModel::DefaultHighLatency,
81 MCSchedModel::DefaultMispredictPenalty,
82 false, // PostRAScheduler
83 false, // CompleteModel
84 false, // EnableIntervals
85 0, // Processor ID
86 nullptr, nullptr, 0, 0, // No instruction-level machine model.
87 nullptr, // No Itinerary
88 nullptr // No extra processor descriptor
89};
90
91// Sorted (by key) array of values for CPU subtype.
92extern const llvm::SubtargetSubTypeKV BPFSubTypeKV[] = {
93 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
94 { "probe", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
95 { "v1", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
96 { "v2", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
97 { "v3", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
98 { "v4", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
99};
100
101namespace BPF_MC {
102unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
103 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
104 // Don't know how to resolve this scheduling class.
105 return 0;
106}
107} // end namespace BPF_MC
108
109struct BPFGenMCSubtargetInfo : public MCSubtargetInfo {
110 BPFGenMCSubtargetInfo(const Triple &TT,
111 StringRef CPU, StringRef TuneCPU, StringRef FS,
112 ArrayRef<SubtargetFeatureKV> PF,
113 ArrayRef<SubtargetSubTypeKV> PD,
114 const MCWriteProcResEntry *WPR,
115 const MCWriteLatencyEntry *WL,
116 const MCReadAdvanceEntry *RA, const InstrStage *IS,
117 const unsigned *OC, const unsigned *FP) :
118 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
119 WPR, WL, RA, IS, OC, FP) { }
120
121 unsigned resolveVariantSchedClass(unsigned SchedClass,
122 const MCInst *MI, const MCInstrInfo *MCII,
123 unsigned CPUID) const override {
124 return BPF_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
125 }
126};
127
128static inline MCSubtargetInfo *createBPFMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
129 return new BPFGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, BPFFeatureKV, BPFSubTypeKV,
130 BPFWriteProcResTable, BPFWriteLatencyTable, BPFReadAdvanceTable,
131 nullptr, nullptr, nullptr);
132}
133
134} // end namespace llvm
135
136#endif // GET_SUBTARGETINFO_MC_DESC
137
138
139#ifdef GET_SUBTARGETINFO_TARGET_DESC
140#undef GET_SUBTARGETINFO_TARGET_DESC
141
142#include "llvm/Support/Debug.h"
143#include "llvm/Support/raw_ostream.h"
144
145// ParseSubtargetFeatures - Parses features string setting specified
146// subtarget options.
147void llvm::BPFSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
148 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
149 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
150 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
151 InitMCProcessorInfo(CPU, TuneCPU, FS);
152 const FeatureBitset &Bits = getFeatureBits();
153 if (Bits[BPF::ALU32]) HasAlu32 = true;
154 if (Bits[BPF::DummyFeature]) isDummyMode = true;
155 if (Bits[BPF::DwarfRIS]) UseDwarfRIS = true;
156}
157#endif // GET_SUBTARGETINFO_TARGET_DESC
158
159
160#ifdef GET_SUBTARGETINFO_HEADER
161#undef GET_SUBTARGETINFO_HEADER
162
163namespace llvm {
164class DFAPacketizer;
165namespace BPF_MC {
166unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
167} // end namespace BPF_MC
168
169struct BPFGenSubtargetInfo : public TargetSubtargetInfo {
170 explicit BPFGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
171public:
172 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
173 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
174 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
175};
176} // end namespace llvm
177
178#endif // GET_SUBTARGETINFO_HEADER
179
180
181#ifdef GET_SUBTARGETINFO_CTOR
182#undef GET_SUBTARGETINFO_CTOR
183
184#include "llvm/CodeGen/TargetSchedule.h"
185
186namespace llvm {
187extern const llvm::SubtargetFeatureKV BPFFeatureKV[];
188extern const llvm::SubtargetSubTypeKV BPFSubTypeKV[];
189extern const llvm::MCWriteProcResEntry BPFWriteProcResTable[];
190extern const llvm::MCWriteLatencyEntry BPFWriteLatencyTable[];
191extern const llvm::MCReadAdvanceEntry BPFReadAdvanceTable[];
192BPFGenSubtargetInfo::BPFGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
193 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(BPFFeatureKV, 3), ArrayRef(BPFSubTypeKV, 6),
194 BPFWriteProcResTable, BPFWriteLatencyTable, BPFReadAdvanceTable,
195 nullptr, nullptr, nullptr) {}
196
197unsigned BPFGenSubtargetInfo
198::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
199 report_fatal_error("Expected a variant SchedClass");
200} // BPFGenSubtargetInfo::resolveSchedClass
201
202unsigned BPFGenSubtargetInfo
203::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
204 return BPF_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
205} // BPFGenSubtargetInfo::resolveVariantSchedClass
206
207} // end namespace llvm
208
209#endif // GET_SUBTARGETINFO_CTOR
210
211
212#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
213#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
214
215#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
216
217
218#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
219#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
220
221#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
222
223