1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm {
12
13namespace Hexagon {
14 enum {
15 PHI = 0,
16 INLINEASM = 1,
17 INLINEASM_BR = 2,
18 CFI_INSTRUCTION = 3,
19 EH_LABEL = 4,
20 GC_LABEL = 5,
21 ANNOTATION_LABEL = 6,
22 KILL = 7,
23 EXTRACT_SUBREG = 8,
24 INSERT_SUBREG = 9,
25 IMPLICIT_DEF = 10,
26 SUBREG_TO_REG = 11,
27 COPY_TO_REGCLASS = 12,
28 DBG_VALUE = 13,
29 DBG_VALUE_LIST = 14,
30 DBG_INSTR_REF = 15,
31 DBG_PHI = 16,
32 DBG_LABEL = 17,
33 REG_SEQUENCE = 18,
34 COPY = 19,
35 BUNDLE = 20,
36 LIFETIME_START = 21,
37 LIFETIME_END = 22,
38 PSEUDO_PROBE = 23,
39 ARITH_FENCE = 24,
40 STACKMAP = 25,
41 FENTRY_CALL = 26,
42 PATCHPOINT = 27,
43 LOAD_STACK_GUARD = 28,
44 PREALLOCATED_SETUP = 29,
45 PREALLOCATED_ARG = 30,
46 STATEPOINT = 31,
47 LOCAL_ESCAPE = 32,
48 FAULTING_OP = 33,
49 PATCHABLE_OP = 34,
50 PATCHABLE_FUNCTION_ENTER = 35,
51 PATCHABLE_RET = 36,
52 PATCHABLE_FUNCTION_EXIT = 37,
53 PATCHABLE_TAIL_CALL = 38,
54 PATCHABLE_EVENT_CALL = 39,
55 PATCHABLE_TYPED_EVENT_CALL = 40,
56 ICALL_BRANCH_FUNNEL = 41,
57 MEMBARRIER = 42,
58 JUMP_TABLE_DEBUG_INFO = 43,
59 CONVERGENCECTRL_ENTRY = 44,
60 CONVERGENCECTRL_ANCHOR = 45,
61 CONVERGENCECTRL_LOOP = 46,
62 CONVERGENCECTRL_GLUE = 47,
63 G_ASSERT_SEXT = 48,
64 G_ASSERT_ZEXT = 49,
65 G_ASSERT_ALIGN = 50,
66 G_ADD = 51,
67 G_SUB = 52,
68 G_MUL = 53,
69 G_SDIV = 54,
70 G_UDIV = 55,
71 G_SREM = 56,
72 G_UREM = 57,
73 G_SDIVREM = 58,
74 G_UDIVREM = 59,
75 G_AND = 60,
76 G_OR = 61,
77 G_XOR = 62,
78 G_IMPLICIT_DEF = 63,
79 G_PHI = 64,
80 G_FRAME_INDEX = 65,
81 G_GLOBAL_VALUE = 66,
82 G_PTRAUTH_GLOBAL_VALUE = 67,
83 G_CONSTANT_POOL = 68,
84 G_EXTRACT = 69,
85 G_UNMERGE_VALUES = 70,
86 G_INSERT = 71,
87 G_MERGE_VALUES = 72,
88 G_BUILD_VECTOR = 73,
89 G_BUILD_VECTOR_TRUNC = 74,
90 G_CONCAT_VECTORS = 75,
91 G_PTRTOINT = 76,
92 G_INTTOPTR = 77,
93 G_BITCAST = 78,
94 G_FREEZE = 79,
95 G_CONSTANT_FOLD_BARRIER = 80,
96 G_INTRINSIC_FPTRUNC_ROUND = 81,
97 G_INTRINSIC_TRUNC = 82,
98 G_INTRINSIC_ROUND = 83,
99 G_INTRINSIC_LRINT = 84,
100 G_INTRINSIC_LLRINT = 85,
101 G_INTRINSIC_ROUNDEVEN = 86,
102 G_READCYCLECOUNTER = 87,
103 G_READSTEADYCOUNTER = 88,
104 G_LOAD = 89,
105 G_SEXTLOAD = 90,
106 G_ZEXTLOAD = 91,
107 G_INDEXED_LOAD = 92,
108 G_INDEXED_SEXTLOAD = 93,
109 G_INDEXED_ZEXTLOAD = 94,
110 G_STORE = 95,
111 G_INDEXED_STORE = 96,
112 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97,
113 G_ATOMIC_CMPXCHG = 98,
114 G_ATOMICRMW_XCHG = 99,
115 G_ATOMICRMW_ADD = 100,
116 G_ATOMICRMW_SUB = 101,
117 G_ATOMICRMW_AND = 102,
118 G_ATOMICRMW_NAND = 103,
119 G_ATOMICRMW_OR = 104,
120 G_ATOMICRMW_XOR = 105,
121 G_ATOMICRMW_MAX = 106,
122 G_ATOMICRMW_MIN = 107,
123 G_ATOMICRMW_UMAX = 108,
124 G_ATOMICRMW_UMIN = 109,
125 G_ATOMICRMW_FADD = 110,
126 G_ATOMICRMW_FSUB = 111,
127 G_ATOMICRMW_FMAX = 112,
128 G_ATOMICRMW_FMIN = 113,
129 G_ATOMICRMW_UINC_WRAP = 114,
130 G_ATOMICRMW_UDEC_WRAP = 115,
131 G_FENCE = 116,
132 G_PREFETCH = 117,
133 G_BRCOND = 118,
134 G_BRINDIRECT = 119,
135 G_INVOKE_REGION_START = 120,
136 G_INTRINSIC = 121,
137 G_INTRINSIC_W_SIDE_EFFECTS = 122,
138 G_INTRINSIC_CONVERGENT = 123,
139 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124,
140 G_ANYEXT = 125,
141 G_TRUNC = 126,
142 G_CONSTANT = 127,
143 G_FCONSTANT = 128,
144 G_VASTART = 129,
145 G_VAARG = 130,
146 G_SEXT = 131,
147 G_SEXT_INREG = 132,
148 G_ZEXT = 133,
149 G_SHL = 134,
150 G_LSHR = 135,
151 G_ASHR = 136,
152 G_FSHL = 137,
153 G_FSHR = 138,
154 G_ROTR = 139,
155 G_ROTL = 140,
156 G_ICMP = 141,
157 G_FCMP = 142,
158 G_SCMP = 143,
159 G_UCMP = 144,
160 G_SELECT = 145,
161 G_UADDO = 146,
162 G_UADDE = 147,
163 G_USUBO = 148,
164 G_USUBE = 149,
165 G_SADDO = 150,
166 G_SADDE = 151,
167 G_SSUBO = 152,
168 G_SSUBE = 153,
169 G_UMULO = 154,
170 G_SMULO = 155,
171 G_UMULH = 156,
172 G_SMULH = 157,
173 G_UADDSAT = 158,
174 G_SADDSAT = 159,
175 G_USUBSAT = 160,
176 G_SSUBSAT = 161,
177 G_USHLSAT = 162,
178 G_SSHLSAT = 163,
179 G_SMULFIX = 164,
180 G_UMULFIX = 165,
181 G_SMULFIXSAT = 166,
182 G_UMULFIXSAT = 167,
183 G_SDIVFIX = 168,
184 G_UDIVFIX = 169,
185 G_SDIVFIXSAT = 170,
186 G_UDIVFIXSAT = 171,
187 G_FADD = 172,
188 G_FSUB = 173,
189 G_FMUL = 174,
190 G_FMA = 175,
191 G_FMAD = 176,
192 G_FDIV = 177,
193 G_FREM = 178,
194 G_FPOW = 179,
195 G_FPOWI = 180,
196 G_FEXP = 181,
197 G_FEXP2 = 182,
198 G_FEXP10 = 183,
199 G_FLOG = 184,
200 G_FLOG2 = 185,
201 G_FLOG10 = 186,
202 G_FLDEXP = 187,
203 G_FFREXP = 188,
204 G_FNEG = 189,
205 G_FPEXT = 190,
206 G_FPTRUNC = 191,
207 G_FPTOSI = 192,
208 G_FPTOUI = 193,
209 G_SITOFP = 194,
210 G_UITOFP = 195,
211 G_FABS = 196,
212 G_FCOPYSIGN = 197,
213 G_IS_FPCLASS = 198,
214 G_FCANONICALIZE = 199,
215 G_FMINNUM = 200,
216 G_FMAXNUM = 201,
217 G_FMINNUM_IEEE = 202,
218 G_FMAXNUM_IEEE = 203,
219 G_FMINIMUM = 204,
220 G_FMAXIMUM = 205,
221 G_GET_FPENV = 206,
222 G_SET_FPENV = 207,
223 G_RESET_FPENV = 208,
224 G_GET_FPMODE = 209,
225 G_SET_FPMODE = 210,
226 G_RESET_FPMODE = 211,
227 G_PTR_ADD = 212,
228 G_PTRMASK = 213,
229 G_SMIN = 214,
230 G_SMAX = 215,
231 G_UMIN = 216,
232 G_UMAX = 217,
233 G_ABS = 218,
234 G_LROUND = 219,
235 G_LLROUND = 220,
236 G_BR = 221,
237 G_BRJT = 222,
238 G_VSCALE = 223,
239 G_INSERT_SUBVECTOR = 224,
240 G_EXTRACT_SUBVECTOR = 225,
241 G_INSERT_VECTOR_ELT = 226,
242 G_EXTRACT_VECTOR_ELT = 227,
243 G_SHUFFLE_VECTOR = 228,
244 G_SPLAT_VECTOR = 229,
245 G_VECTOR_COMPRESS = 230,
246 G_CTTZ = 231,
247 G_CTTZ_ZERO_UNDEF = 232,
248 G_CTLZ = 233,
249 G_CTLZ_ZERO_UNDEF = 234,
250 G_CTPOP = 235,
251 G_BSWAP = 236,
252 G_BITREVERSE = 237,
253 G_FCEIL = 238,
254 G_FCOS = 239,
255 G_FSIN = 240,
256 G_FTAN = 241,
257 G_FACOS = 242,
258 G_FASIN = 243,
259 G_FATAN = 244,
260 G_FCOSH = 245,
261 G_FSINH = 246,
262 G_FTANH = 247,
263 G_FSQRT = 248,
264 G_FFLOOR = 249,
265 G_FRINT = 250,
266 G_FNEARBYINT = 251,
267 G_ADDRSPACE_CAST = 252,
268 G_BLOCK_ADDR = 253,
269 G_JUMP_TABLE = 254,
270 G_DYN_STACKALLOC = 255,
271 G_STACKSAVE = 256,
272 G_STACKRESTORE = 257,
273 G_STRICT_FADD = 258,
274 G_STRICT_FSUB = 259,
275 G_STRICT_FMUL = 260,
276 G_STRICT_FDIV = 261,
277 G_STRICT_FREM = 262,
278 G_STRICT_FMA = 263,
279 G_STRICT_FSQRT = 264,
280 G_STRICT_FLDEXP = 265,
281 G_READ_REGISTER = 266,
282 G_WRITE_REGISTER = 267,
283 G_MEMCPY = 268,
284 G_MEMCPY_INLINE = 269,
285 G_MEMMOVE = 270,
286 G_MEMSET = 271,
287 G_BZERO = 272,
288 G_TRAP = 273,
289 G_DEBUGTRAP = 274,
290 G_UBSANTRAP = 275,
291 G_VECREDUCE_SEQ_FADD = 276,
292 G_VECREDUCE_SEQ_FMUL = 277,
293 G_VECREDUCE_FADD = 278,
294 G_VECREDUCE_FMUL = 279,
295 G_VECREDUCE_FMAX = 280,
296 G_VECREDUCE_FMIN = 281,
297 G_VECREDUCE_FMAXIMUM = 282,
298 G_VECREDUCE_FMINIMUM = 283,
299 G_VECREDUCE_ADD = 284,
300 G_VECREDUCE_MUL = 285,
301 G_VECREDUCE_AND = 286,
302 G_VECREDUCE_OR = 287,
303 G_VECREDUCE_XOR = 288,
304 G_VECREDUCE_SMAX = 289,
305 G_VECREDUCE_SMIN = 290,
306 G_VECREDUCE_UMAX = 291,
307 G_VECREDUCE_UMIN = 292,
308 G_SBFX = 293,
309 G_UBFX = 294,
310 A2_addsp = 295,
311 A2_iconst = 296,
312 A2_neg = 297,
313 A2_not = 298,
314 A2_tfrf = 299,
315 A2_tfrfnew = 300,
316 A2_tfrp = 301,
317 A2_tfrpf = 302,
318 A2_tfrpfnew = 303,
319 A2_tfrpi = 304,
320 A2_tfrpt = 305,
321 A2_tfrptnew = 306,
322 A2_tfrt = 307,
323 A2_tfrtnew = 308,
324 A2_vaddb_map = 309,
325 A2_vsubb_map = 310,
326 A2_zxtb = 311,
327 A4_boundscheck = 312,
328 ADJCALLSTACKDOWN = 313,
329 ADJCALLSTACKUP = 314,
330 C2_cmpgei = 315,
331 C2_cmpgeui = 316,
332 C2_cmplt = 317,
333 C2_cmpltu = 318,
334 C2_pxfer_map = 319,
335 DUPLEX_Pseudo = 320,
336 ENDLOOP0 = 321,
337 ENDLOOP01 = 322,
338 ENDLOOP1 = 323,
339 J2_endloop0 = 324,
340 J2_endloop01 = 325,
341 J2_endloop1 = 326,
342 J2_jumpf_nopred_map = 327,
343 J2_jumprf_nopred_map = 328,
344 J2_jumprt_nopred_map = 329,
345 J2_jumpt_nopred_map = 330,
346 J2_trap1_noregmap = 331,
347 L2_loadalignb_zomap = 332,
348 L2_loadalignh_zomap = 333,
349 L2_loadbsw2_zomap = 334,
350 L2_loadbsw4_zomap = 335,
351 L2_loadbzw2_zomap = 336,
352 L2_loadbzw4_zomap = 337,
353 L2_loadrb_zomap = 338,
354 L2_loadrd_zomap = 339,
355 L2_loadrh_zomap = 340,
356 L2_loadri_zomap = 341,
357 L2_loadrub_zomap = 342,
358 L2_loadruh_zomap = 343,
359 L2_ploadrbf_zomap = 344,
360 L2_ploadrbfnew_zomap = 345,
361 L2_ploadrbt_zomap = 346,
362 L2_ploadrbtnew_zomap = 347,
363 L2_ploadrdf_zomap = 348,
364 L2_ploadrdfnew_zomap = 349,
365 L2_ploadrdt_zomap = 350,
366 L2_ploadrdtnew_zomap = 351,
367 L2_ploadrhf_zomap = 352,
368 L2_ploadrhfnew_zomap = 353,
369 L2_ploadrht_zomap = 354,
370 L2_ploadrhtnew_zomap = 355,
371 L2_ploadrif_zomap = 356,
372 L2_ploadrifnew_zomap = 357,
373 L2_ploadrit_zomap = 358,
374 L2_ploadritnew_zomap = 359,
375 L2_ploadrubf_zomap = 360,
376 L2_ploadrubfnew_zomap = 361,
377 L2_ploadrubt_zomap = 362,
378 L2_ploadrubtnew_zomap = 363,
379 L2_ploadruhf_zomap = 364,
380 L2_ploadruhfnew_zomap = 365,
381 L2_ploadruht_zomap = 366,
382 L2_ploadruhtnew_zomap = 367,
383 L4_add_memopb_zomap = 368,
384 L4_add_memoph_zomap = 369,
385 L4_add_memopw_zomap = 370,
386 L4_and_memopb_zomap = 371,
387 L4_and_memoph_zomap = 372,
388 L4_and_memopw_zomap = 373,
389 L4_iadd_memopb_zomap = 374,
390 L4_iadd_memoph_zomap = 375,
391 L4_iadd_memopw_zomap = 376,
392 L4_iand_memopb_zomap = 377,
393 L4_iand_memoph_zomap = 378,
394 L4_iand_memopw_zomap = 379,
395 L4_ior_memopb_zomap = 380,
396 L4_ior_memoph_zomap = 381,
397 L4_ior_memopw_zomap = 382,
398 L4_isub_memopb_zomap = 383,
399 L4_isub_memoph_zomap = 384,
400 L4_isub_memopw_zomap = 385,
401 L4_or_memopb_zomap = 386,
402 L4_or_memoph_zomap = 387,
403 L4_or_memopw_zomap = 388,
404 L4_return_map_to_raw_f = 389,
405 L4_return_map_to_raw_fnew_pnt = 390,
406 L4_return_map_to_raw_fnew_pt = 391,
407 L4_return_map_to_raw_t = 392,
408 L4_return_map_to_raw_tnew_pnt = 393,
409 L4_return_map_to_raw_tnew_pt = 394,
410 L4_sub_memopb_zomap = 395,
411 L4_sub_memoph_zomap = 396,
412 L4_sub_memopw_zomap = 397,
413 L6_deallocframe_map_to_raw = 398,
414 L6_return_map_to_raw = 399,
415 LDriw_ctr = 400,
416 LDriw_pred = 401,
417 M2_mpysmi = 402,
418 M2_mpyui = 403,
419 M2_vrcmpys_acc_s1 = 404,
420 M2_vrcmpys_s1 = 405,
421 M2_vrcmpys_s1rp = 406,
422 M7_vdmpy = 407,
423 M7_vdmpy_acc = 408,
424 PS_aligna = 409,
425 PS_alloca = 410,
426 PS_call_instrprof_custom = 411,
427 PS_call_nr = 412,
428 PS_crash = 413,
429 PS_false = 414,
430 PS_fi = 415,
431 PS_fia = 416,
432 PS_loadrb_pci = 417,
433 PS_loadrb_pcr = 418,
434 PS_loadrd_pci = 419,
435 PS_loadrd_pcr = 420,
436 PS_loadrh_pci = 421,
437 PS_loadrh_pcr = 422,
438 PS_loadri_pci = 423,
439 PS_loadri_pcr = 424,
440 PS_loadrub_pci = 425,
441 PS_loadrub_pcr = 426,
442 PS_loadruh_pci = 427,
443 PS_loadruh_pcr = 428,
444 PS_pselect = 429,
445 PS_qfalse = 430,
446 PS_qtrue = 431,
447 PS_storerb_pci = 432,
448 PS_storerb_pcr = 433,
449 PS_storerd_pci = 434,
450 PS_storerd_pcr = 435,
451 PS_storerf_pci = 436,
452 PS_storerf_pcr = 437,
453 PS_storerh_pci = 438,
454 PS_storerh_pcr = 439,
455 PS_storeri_pci = 440,
456 PS_storeri_pcr = 441,
457 PS_tailcall_i = 442,
458 PS_tailcall_r = 443,
459 PS_true = 444,
460 PS_vdd0 = 445,
461 PS_vloadrq_ai = 446,
462 PS_vloadrv_ai = 447,
463 PS_vloadrv_nt_ai = 448,
464 PS_vloadrw_ai = 449,
465 PS_vloadrw_nt_ai = 450,
466 PS_vmulw = 451,
467 PS_vmulw_acc = 452,
468 PS_vselect = 453,
469 PS_vsplatib = 454,
470 PS_vsplatih = 455,
471 PS_vsplatiw = 456,
472 PS_vsplatrb = 457,
473 PS_vsplatrh = 458,
474 PS_vsplatrw = 459,
475 PS_vstorerq_ai = 460,
476 PS_vstorerv_ai = 461,
477 PS_vstorerv_nt_ai = 462,
478 PS_vstorerw_ai = 463,
479 PS_vstorerw_nt_ai = 464,
480 PS_wselect = 465,
481 S2_asr_i_p_rnd_goodsyntax = 466,
482 S2_asr_i_r_rnd_goodsyntax = 467,
483 S2_pstorerbf_zomap = 468,
484 S2_pstorerbnewf_zomap = 469,
485 S2_pstorerbnewt_zomap = 470,
486 S2_pstorerbt_zomap = 471,
487 S2_pstorerdf_zomap = 472,
488 S2_pstorerdt_zomap = 473,
489 S2_pstorerff_zomap = 474,
490 S2_pstorerft_zomap = 475,
491 S2_pstorerhf_zomap = 476,
492 S2_pstorerhnewf_zomap = 477,
493 S2_pstorerhnewt_zomap = 478,
494 S2_pstorerht_zomap = 479,
495 S2_pstorerif_zomap = 480,
496 S2_pstorerinewf_zomap = 481,
497 S2_pstorerinewt_zomap = 482,
498 S2_pstorerit_zomap = 483,
499 S2_storerb_zomap = 484,
500 S2_storerbnew_zomap = 485,
501 S2_storerd_zomap = 486,
502 S2_storerf_zomap = 487,
503 S2_storerh_zomap = 488,
504 S2_storerhnew_zomap = 489,
505 S2_storeri_zomap = 490,
506 S2_storerinew_zomap = 491,
507 S2_tableidxb_goodsyntax = 492,
508 S2_tableidxd_goodsyntax = 493,
509 S2_tableidxh_goodsyntax = 494,
510 S2_tableidxw_goodsyntax = 495,
511 S4_pstorerbfnew_zomap = 496,
512 S4_pstorerbnewfnew_zomap = 497,
513 S4_pstorerbnewtnew_zomap = 498,
514 S4_pstorerbtnew_zomap = 499,
515 S4_pstorerdfnew_zomap = 500,
516 S4_pstorerdtnew_zomap = 501,
517 S4_pstorerffnew_zomap = 502,
518 S4_pstorerftnew_zomap = 503,
519 S4_pstorerhfnew_zomap = 504,
520 S4_pstorerhnewfnew_zomap = 505,
521 S4_pstorerhnewtnew_zomap = 506,
522 S4_pstorerhtnew_zomap = 507,
523 S4_pstorerifnew_zomap = 508,
524 S4_pstorerinewfnew_zomap = 509,
525 S4_pstorerinewtnew_zomap = 510,
526 S4_pstoreritnew_zomap = 511,
527 S4_storeirb_zomap = 512,
528 S4_storeirbf_zomap = 513,
529 S4_storeirbfnew_zomap = 514,
530 S4_storeirbt_zomap = 515,
531 S4_storeirbtnew_zomap = 516,
532 S4_storeirh_zomap = 517,
533 S4_storeirhf_zomap = 518,
534 S4_storeirhfnew_zomap = 519,
535 S4_storeirht_zomap = 520,
536 S4_storeirhtnew_zomap = 521,
537 S4_storeiri_zomap = 522,
538 S4_storeirif_zomap = 523,
539 S4_storeirifnew_zomap = 524,
540 S4_storeirit_zomap = 525,
541 S4_storeiritnew_zomap = 526,
542 S5_asrhub_rnd_sat_goodsyntax = 527,
543 S5_vasrhrnd_goodsyntax = 528,
544 S6_allocframe_to_raw = 529,
545 STriw_ctr = 530,
546 STriw_pred = 531,
547 V6_MAP_equb = 532,
548 V6_MAP_equb_and = 533,
549 V6_MAP_equb_ior = 534,
550 V6_MAP_equb_xor = 535,
551 V6_MAP_equh = 536,
552 V6_MAP_equh_and = 537,
553 V6_MAP_equh_ior = 538,
554 V6_MAP_equh_xor = 539,
555 V6_MAP_equw = 540,
556 V6_MAP_equw_and = 541,
557 V6_MAP_equw_ior = 542,
558 V6_MAP_equw_xor = 543,
559 V6_dbl_ld0 = 544,
560 V6_dbl_st0 = 545,
561 V6_extractw_alt = 546,
562 V6_hi = 547,
563 V6_ld0 = 548,
564 V6_ldcnp0 = 549,
565 V6_ldcnpnt0 = 550,
566 V6_ldcp0 = 551,
567 V6_ldcpnt0 = 552,
568 V6_ldnp0 = 553,
569 V6_ldnpnt0 = 554,
570 V6_ldnt0 = 555,
571 V6_ldp0 = 556,
572 V6_ldpnt0 = 557,
573 V6_ldtnp0 = 558,
574 V6_ldtnpnt0 = 559,
575 V6_ldtp0 = 560,
576 V6_ldtpnt0 = 561,
577 V6_ldu0 = 562,
578 V6_lo = 563,
579 V6_st0 = 564,
580 V6_stn0 = 565,
581 V6_stnnt0 = 566,
582 V6_stnp0 = 567,
583 V6_stnpnt0 = 568,
584 V6_stnq0 = 569,
585 V6_stnqnt0 = 570,
586 V6_stnt0 = 571,
587 V6_stp0 = 572,
588 V6_stpnt0 = 573,
589 V6_stq0 = 574,
590 V6_stqnt0 = 575,
591 V6_stu0 = 576,
592 V6_stunp0 = 577,
593 V6_stup0 = 578,
594 V6_v10mpyubs10 = 579,
595 V6_v10mpyubs10_vxx = 580,
596 V6_v6mpyhubs10_alt = 581,
597 V6_v6mpyvubs10_alt = 582,
598 V6_vabsb_alt = 583,
599 V6_vabsb_sat_alt = 584,
600 V6_vabsdiffh_alt = 585,
601 V6_vabsdiffub_alt = 586,
602 V6_vabsdiffuh_alt = 587,
603 V6_vabsdiffw_alt = 588,
604 V6_vabsh_alt = 589,
605 V6_vabsh_sat_alt = 590,
606 V6_vabsub_alt = 591,
607 V6_vabsuh_alt = 592,
608 V6_vabsuw_alt = 593,
609 V6_vabsw_alt = 594,
610 V6_vabsw_sat_alt = 595,
611 V6_vaddb_alt = 596,
612 V6_vaddb_dv_alt = 597,
613 V6_vaddbnq_alt = 598,
614 V6_vaddbq_alt = 599,
615 V6_vaddbsat_alt = 600,
616 V6_vaddbsat_dv_alt = 601,
617 V6_vaddh_alt = 602,
618 V6_vaddh_dv_alt = 603,
619 V6_vaddhnq_alt = 604,
620 V6_vaddhq_alt = 605,
621 V6_vaddhsat_alt = 606,
622 V6_vaddhsat_dv_alt = 607,
623 V6_vaddhw_acc_alt = 608,
624 V6_vaddhw_alt = 609,
625 V6_vaddubh_acc_alt = 610,
626 V6_vaddubh_alt = 611,
627 V6_vaddubsat_alt = 612,
628 V6_vaddubsat_dv_alt = 613,
629 V6_vadduhsat_alt = 614,
630 V6_vadduhsat_dv_alt = 615,
631 V6_vadduhw_acc_alt = 616,
632 V6_vadduhw_alt = 617,
633 V6_vadduwsat_alt = 618,
634 V6_vadduwsat_dv_alt = 619,
635 V6_vaddw_alt = 620,
636 V6_vaddw_dv_alt = 621,
637 V6_vaddwnq_alt = 622,
638 V6_vaddwq_alt = 623,
639 V6_vaddwsat_alt = 624,
640 V6_vaddwsat_dv_alt = 625,
641 V6_vandnqrt_acc_alt = 626,
642 V6_vandnqrt_alt = 627,
643 V6_vandqrt_acc_alt = 628,
644 V6_vandqrt_alt = 629,
645 V6_vandvrt_acc_alt = 630,
646 V6_vandvrt_alt = 631,
647 V6_vaslh_acc_alt = 632,
648 V6_vaslh_alt = 633,
649 V6_vaslhv_alt = 634,
650 V6_vaslw_acc_alt = 635,
651 V6_vaslw_alt = 636,
652 V6_vaslwv_alt = 637,
653 V6_vasr_into_alt = 638,
654 V6_vasrh_acc_alt = 639,
655 V6_vasrh_alt = 640,
656 V6_vasrhv_alt = 641,
657 V6_vasrw_acc_alt = 642,
658 V6_vasrw_alt = 643,
659 V6_vasrwv_alt = 644,
660 V6_vassignp = 645,
661 V6_vavgb_alt = 646,
662 V6_vavgbrnd_alt = 647,
663 V6_vavgh_alt = 648,
664 V6_vavghrnd_alt = 649,
665 V6_vavgub_alt = 650,
666 V6_vavgubrnd_alt = 651,
667 V6_vavguh_alt = 652,
668 V6_vavguhrnd_alt = 653,
669 V6_vavguw_alt = 654,
670 V6_vavguwrnd_alt = 655,
671 V6_vavgw_alt = 656,
672 V6_vavgwrnd_alt = 657,
673 V6_vcl0h_alt = 658,
674 V6_vcl0w_alt = 659,
675 V6_vd0 = 660,
676 V6_vdd0 = 661,
677 V6_vdealb4w_alt = 662,
678 V6_vdealb_alt = 663,
679 V6_vdealh_alt = 664,
680 V6_vdmpybus_acc_alt = 665,
681 V6_vdmpybus_alt = 666,
682 V6_vdmpybus_dv_acc_alt = 667,
683 V6_vdmpybus_dv_alt = 668,
684 V6_vdmpyhb_acc_alt = 669,
685 V6_vdmpyhb_alt = 670,
686 V6_vdmpyhb_dv_acc_alt = 671,
687 V6_vdmpyhb_dv_alt = 672,
688 V6_vdmpyhisat_acc_alt = 673,
689 V6_vdmpyhisat_alt = 674,
690 V6_vdmpyhsat_acc_alt = 675,
691 V6_vdmpyhsat_alt = 676,
692 V6_vdmpyhsuisat_acc_alt = 677,
693 V6_vdmpyhsuisat_alt = 678,
694 V6_vdmpyhsusat_acc_alt = 679,
695 V6_vdmpyhsusat_alt = 680,
696 V6_vdmpyhvsat_acc_alt = 681,
697 V6_vdmpyhvsat_alt = 682,
698 V6_vdsaduh_acc_alt = 683,
699 V6_vdsaduh_alt = 684,
700 V6_vgathermh_pseudo = 685,
701 V6_vgathermhq_pseudo = 686,
702 V6_vgathermhw_pseudo = 687,
703 V6_vgathermhwq_pseudo = 688,
704 V6_vgathermw_pseudo = 689,
705 V6_vgathermwq_pseudo = 690,
706 V6_vlsrh_alt = 691,
707 V6_vlsrhv_alt = 692,
708 V6_vlsrw_alt = 693,
709 V6_vlsrwv_alt = 694,
710 V6_vmaxb_alt = 695,
711 V6_vmaxh_alt = 696,
712 V6_vmaxub_alt = 697,
713 V6_vmaxuh_alt = 698,
714 V6_vmaxw_alt = 699,
715 V6_vminb_alt = 700,
716 V6_vminh_alt = 701,
717 V6_vminub_alt = 702,
718 V6_vminuh_alt = 703,
719 V6_vminw_alt = 704,
720 V6_vmpabus_acc_alt = 705,
721 V6_vmpabus_alt = 706,
722 V6_vmpabusv_alt = 707,
723 V6_vmpabuu_acc_alt = 708,
724 V6_vmpabuu_alt = 709,
725 V6_vmpabuuv_alt = 710,
726 V6_vmpahb_acc_alt = 711,
727 V6_vmpahb_alt = 712,
728 V6_vmpauhb_acc_alt = 713,
729 V6_vmpauhb_alt = 714,
730 V6_vmpybus_acc_alt = 715,
731 V6_vmpybus_alt = 716,
732 V6_vmpybusv_acc_alt = 717,
733 V6_vmpybusv_alt = 718,
734 V6_vmpybv_acc_alt = 719,
735 V6_vmpybv_alt = 720,
736 V6_vmpyewuh_alt = 721,
737 V6_vmpyh_acc_alt = 722,
738 V6_vmpyh_alt = 723,
739 V6_vmpyhsat_acc_alt = 724,
740 V6_vmpyhsrs_alt = 725,
741 V6_vmpyhss_alt = 726,
742 V6_vmpyhus_acc_alt = 727,
743 V6_vmpyhus_alt = 728,
744 V6_vmpyhv_acc_alt = 729,
745 V6_vmpyhv_alt = 730,
746 V6_vmpyhvsrs_alt = 731,
747 V6_vmpyiewh_acc_alt = 732,
748 V6_vmpyiewuh_acc_alt = 733,
749 V6_vmpyiewuh_alt = 734,
750 V6_vmpyih_acc_alt = 735,
751 V6_vmpyih_alt = 736,
752 V6_vmpyihb_acc_alt = 737,
753 V6_vmpyihb_alt = 738,
754 V6_vmpyiowh_alt = 739,
755 V6_vmpyiwb_acc_alt = 740,
756 V6_vmpyiwb_alt = 741,
757 V6_vmpyiwh_acc_alt = 742,
758 V6_vmpyiwh_alt = 743,
759 V6_vmpyiwub_acc_alt = 744,
760 V6_vmpyiwub_alt = 745,
761 V6_vmpyowh_alt = 746,
762 V6_vmpyowh_rnd_alt = 747,
763 V6_vmpyowh_rnd_sacc_alt = 748,
764 V6_vmpyowh_sacc_alt = 749,
765 V6_vmpyub_acc_alt = 750,
766 V6_vmpyub_alt = 751,
767 V6_vmpyubv_acc_alt = 752,
768 V6_vmpyubv_alt = 753,
769 V6_vmpyuh_acc_alt = 754,
770 V6_vmpyuh_alt = 755,
771 V6_vmpyuhv_acc_alt = 756,
772 V6_vmpyuhv_alt = 757,
773 V6_vnavgb_alt = 758,
774 V6_vnavgh_alt = 759,
775 V6_vnavgub_alt = 760,
776 V6_vnavgw_alt = 761,
777 V6_vnormamth_alt = 762,
778 V6_vnormamtw_alt = 763,
779 V6_vpackeb_alt = 764,
780 V6_vpackeh_alt = 765,
781 V6_vpackhb_sat_alt = 766,
782 V6_vpackhub_sat_alt = 767,
783 V6_vpackob_alt = 768,
784 V6_vpackoh_alt = 769,
785 V6_vpackwh_sat_alt = 770,
786 V6_vpackwuh_sat_alt = 771,
787 V6_vpopcounth_alt = 772,
788 V6_vrmpybub_rtt_acc_alt = 773,
789 V6_vrmpybub_rtt_alt = 774,
790 V6_vrmpybus_acc_alt = 775,
791 V6_vrmpybus_alt = 776,
792 V6_vrmpybusi_acc_alt = 777,
793 V6_vrmpybusi_alt = 778,
794 V6_vrmpybusv_acc_alt = 779,
795 V6_vrmpybusv_alt = 780,
796 V6_vrmpybv_acc_alt = 781,
797 V6_vrmpybv_alt = 782,
798 V6_vrmpyub_acc_alt = 783,
799 V6_vrmpyub_alt = 784,
800 V6_vrmpyub_rtt_acc_alt = 785,
801 V6_vrmpyub_rtt_alt = 786,
802 V6_vrmpyubi_acc_alt = 787,
803 V6_vrmpyubi_alt = 788,
804 V6_vrmpyubv_acc_alt = 789,
805 V6_vrmpyubv_alt = 790,
806 V6_vrotr_alt = 791,
807 V6_vroundhb_alt = 792,
808 V6_vroundhub_alt = 793,
809 V6_vrounduhub_alt = 794,
810 V6_vrounduwuh_alt = 795,
811 V6_vroundwh_alt = 796,
812 V6_vroundwuh_alt = 797,
813 V6_vrsadubi_acc_alt = 798,
814 V6_vrsadubi_alt = 799,
815 V6_vsathub_alt = 800,
816 V6_vsatuwuh_alt = 801,
817 V6_vsatwh_alt = 802,
818 V6_vsb_alt = 803,
819 V6_vscattermh_add_alt = 804,
820 V6_vscattermh_alt = 805,
821 V6_vscattermhq_alt = 806,
822 V6_vscattermw_add_alt = 807,
823 V6_vscattermw_alt = 808,
824 V6_vscattermwh_add_alt = 809,
825 V6_vscattermwh_alt = 810,
826 V6_vscattermwhq_alt = 811,
827 V6_vscattermwq_alt = 812,
828 V6_vsh_alt = 813,
829 V6_vshufeh_alt = 814,
830 V6_vshuffb_alt = 815,
831 V6_vshuffeb_alt = 816,
832 V6_vshuffh_alt = 817,
833 V6_vshuffob_alt = 818,
834 V6_vshufoeb_alt = 819,
835 V6_vshufoeh_alt = 820,
836 V6_vshufoh_alt = 821,
837 V6_vsubb_alt = 822,
838 V6_vsubb_dv_alt = 823,
839 V6_vsubbnq_alt = 824,
840 V6_vsubbq_alt = 825,
841 V6_vsubbsat_alt = 826,
842 V6_vsubbsat_dv_alt = 827,
843 V6_vsubh_alt = 828,
844 V6_vsubh_dv_alt = 829,
845 V6_vsubhnq_alt = 830,
846 V6_vsubhq_alt = 831,
847 V6_vsubhsat_alt = 832,
848 V6_vsubhsat_dv_alt = 833,
849 V6_vsubhw_alt = 834,
850 V6_vsububh_alt = 835,
851 V6_vsububsat_alt = 836,
852 V6_vsububsat_dv_alt = 837,
853 V6_vsubuhsat_alt = 838,
854 V6_vsubuhsat_dv_alt = 839,
855 V6_vsubuhw_alt = 840,
856 V6_vsubuwsat_alt = 841,
857 V6_vsubuwsat_dv_alt = 842,
858 V6_vsubw_alt = 843,
859 V6_vsubw_dv_alt = 844,
860 V6_vsubwnq_alt = 845,
861 V6_vsubwq_alt = 846,
862 V6_vsubwsat_alt = 847,
863 V6_vsubwsat_dv_alt = 848,
864 V6_vtmpyb_acc_alt = 849,
865 V6_vtmpyb_alt = 850,
866 V6_vtmpybus_acc_alt = 851,
867 V6_vtmpybus_alt = 852,
868 V6_vtmpyhb_acc_alt = 853,
869 V6_vtmpyhb_alt = 854,
870 V6_vtran2x2_map = 855,
871 V6_vunpackb_alt = 856,
872 V6_vunpackh_alt = 857,
873 V6_vunpackob_alt = 858,
874 V6_vunpackoh_alt = 859,
875 V6_vunpackub_alt = 860,
876 V6_vunpackuh_alt = 861,
877 V6_vzb_alt = 862,
878 V6_vzh_alt = 863,
879 V6_zld0 = 864,
880 V6_zldp0 = 865,
881 Y2_crswap_old = 866,
882 Y2_dcfetch = 867,
883 Y2_k1lock_map = 868,
884 Y2_k1unlock_map = 869,
885 dup_A2_add = 870,
886 dup_A2_addi = 871,
887 dup_A2_andir = 872,
888 dup_A2_combineii = 873,
889 dup_A2_sxtb = 874,
890 dup_A2_sxth = 875,
891 dup_A2_tfr = 876,
892 dup_A2_tfrsi = 877,
893 dup_A2_zxtb = 878,
894 dup_A2_zxth = 879,
895 dup_A4_combineii = 880,
896 dup_A4_combineir = 881,
897 dup_A4_combineri = 882,
898 dup_C2_cmoveif = 883,
899 dup_C2_cmoveit = 884,
900 dup_C2_cmovenewif = 885,
901 dup_C2_cmovenewit = 886,
902 dup_C2_cmpeqi = 887,
903 dup_L2_deallocframe = 888,
904 dup_L2_loadrb_io = 889,
905 dup_L2_loadrd_io = 890,
906 dup_L2_loadrh_io = 891,
907 dup_L2_loadri_io = 892,
908 dup_L2_loadrub_io = 893,
909 dup_L2_loadruh_io = 894,
910 dup_S2_allocframe = 895,
911 dup_S2_storerb_io = 896,
912 dup_S2_storerd_io = 897,
913 dup_S2_storerh_io = 898,
914 dup_S2_storeri_io = 899,
915 dup_S4_storeirb_io = 900,
916 dup_S4_storeiri_io = 901,
917 A2_abs = 902,
918 A2_absp = 903,
919 A2_abssat = 904,
920 A2_add = 905,
921 A2_addh_h16_hh = 906,
922 A2_addh_h16_hl = 907,
923 A2_addh_h16_lh = 908,
924 A2_addh_h16_ll = 909,
925 A2_addh_h16_sat_hh = 910,
926 A2_addh_h16_sat_hl = 911,
927 A2_addh_h16_sat_lh = 912,
928 A2_addh_h16_sat_ll = 913,
929 A2_addh_l16_hl = 914,
930 A2_addh_l16_ll = 915,
931 A2_addh_l16_sat_hl = 916,
932 A2_addh_l16_sat_ll = 917,
933 A2_addi = 918,
934 A2_addp = 919,
935 A2_addpsat = 920,
936 A2_addsat = 921,
937 A2_addsph = 922,
938 A2_addspl = 923,
939 A2_and = 924,
940 A2_andir = 925,
941 A2_andp = 926,
942 A2_aslh = 927,
943 A2_asrh = 928,
944 A2_combine_hh = 929,
945 A2_combine_hl = 930,
946 A2_combine_lh = 931,
947 A2_combine_ll = 932,
948 A2_combineii = 933,
949 A2_combinew = 934,
950 A2_max = 935,
951 A2_maxp = 936,
952 A2_maxu = 937,
953 A2_maxup = 938,
954 A2_min = 939,
955 A2_minp = 940,
956 A2_minu = 941,
957 A2_minup = 942,
958 A2_negp = 943,
959 A2_negsat = 944,
960 A2_nop = 945,
961 A2_notp = 946,
962 A2_or = 947,
963 A2_orir = 948,
964 A2_orp = 949,
965 A2_paddf = 950,
966 A2_paddfnew = 951,
967 A2_paddif = 952,
968 A2_paddifnew = 953,
969 A2_paddit = 954,
970 A2_padditnew = 955,
971 A2_paddt = 956,
972 A2_paddtnew = 957,
973 A2_pandf = 958,
974 A2_pandfnew = 959,
975 A2_pandt = 960,
976 A2_pandtnew = 961,
977 A2_porf = 962,
978 A2_porfnew = 963,
979 A2_port = 964,
980 A2_portnew = 965,
981 A2_psubf = 966,
982 A2_psubfnew = 967,
983 A2_psubt = 968,
984 A2_psubtnew = 969,
985 A2_pxorf = 970,
986 A2_pxorfnew = 971,
987 A2_pxort = 972,
988 A2_pxortnew = 973,
989 A2_roundsat = 974,
990 A2_sat = 975,
991 A2_satb = 976,
992 A2_sath = 977,
993 A2_satub = 978,
994 A2_satuh = 979,
995 A2_sub = 980,
996 A2_subh_h16_hh = 981,
997 A2_subh_h16_hl = 982,
998 A2_subh_h16_lh = 983,
999 A2_subh_h16_ll = 984,
1000 A2_subh_h16_sat_hh = 985,
1001 A2_subh_h16_sat_hl = 986,
1002 A2_subh_h16_sat_lh = 987,
1003 A2_subh_h16_sat_ll = 988,
1004 A2_subh_l16_hl = 989,
1005 A2_subh_l16_ll = 990,
1006 A2_subh_l16_sat_hl = 991,
1007 A2_subh_l16_sat_ll = 992,
1008 A2_subp = 993,
1009 A2_subri = 994,
1010 A2_subsat = 995,
1011 A2_svaddh = 996,
1012 A2_svaddhs = 997,
1013 A2_svadduhs = 998,
1014 A2_svavgh = 999,
1015 A2_svavghs = 1000,
1016 A2_svnavgh = 1001,
1017 A2_svsubh = 1002,
1018 A2_svsubhs = 1003,
1019 A2_svsubuhs = 1004,
1020 A2_swiz = 1005,
1021 A2_sxtb = 1006,
1022 A2_sxth = 1007,
1023 A2_sxtw = 1008,
1024 A2_tfr = 1009,
1025 A2_tfrcrr = 1010,
1026 A2_tfrih = 1011,
1027 A2_tfril = 1012,
1028 A2_tfrrcr = 1013,
1029 A2_tfrsi = 1014,
1030 A2_vabsh = 1015,
1031 A2_vabshsat = 1016,
1032 A2_vabsw = 1017,
1033 A2_vabswsat = 1018,
1034 A2_vaddh = 1019,
1035 A2_vaddhs = 1020,
1036 A2_vaddub = 1021,
1037 A2_vaddubs = 1022,
1038 A2_vadduhs = 1023,
1039 A2_vaddw = 1024,
1040 A2_vaddws = 1025,
1041 A2_vavgh = 1026,
1042 A2_vavghcr = 1027,
1043 A2_vavghr = 1028,
1044 A2_vavgub = 1029,
1045 A2_vavgubr = 1030,
1046 A2_vavguh = 1031,
1047 A2_vavguhr = 1032,
1048 A2_vavguw = 1033,
1049 A2_vavguwr = 1034,
1050 A2_vavgw = 1035,
1051 A2_vavgwcr = 1036,
1052 A2_vavgwr = 1037,
1053 A2_vcmpbeq = 1038,
1054 A2_vcmpbgtu = 1039,
1055 A2_vcmpheq = 1040,
1056 A2_vcmphgt = 1041,
1057 A2_vcmphgtu = 1042,
1058 A2_vcmpweq = 1043,
1059 A2_vcmpwgt = 1044,
1060 A2_vcmpwgtu = 1045,
1061 A2_vconj = 1046,
1062 A2_vmaxb = 1047,
1063 A2_vmaxh = 1048,
1064 A2_vmaxub = 1049,
1065 A2_vmaxuh = 1050,
1066 A2_vmaxuw = 1051,
1067 A2_vmaxw = 1052,
1068 A2_vminb = 1053,
1069 A2_vminh = 1054,
1070 A2_vminub = 1055,
1071 A2_vminuh = 1056,
1072 A2_vminuw = 1057,
1073 A2_vminw = 1058,
1074 A2_vnavgh = 1059,
1075 A2_vnavghcr = 1060,
1076 A2_vnavghr = 1061,
1077 A2_vnavgw = 1062,
1078 A2_vnavgwcr = 1063,
1079 A2_vnavgwr = 1064,
1080 A2_vraddub = 1065,
1081 A2_vraddub_acc = 1066,
1082 A2_vrsadub = 1067,
1083 A2_vrsadub_acc = 1068,
1084 A2_vsubh = 1069,
1085 A2_vsubhs = 1070,
1086 A2_vsubub = 1071,
1087 A2_vsububs = 1072,
1088 A2_vsubuhs = 1073,
1089 A2_vsubw = 1074,
1090 A2_vsubws = 1075,
1091 A2_xor = 1076,
1092 A2_xorp = 1077,
1093 A2_zxth = 1078,
1094 A4_addp_c = 1079,
1095 A4_andn = 1080,
1096 A4_andnp = 1081,
1097 A4_bitsplit = 1082,
1098 A4_bitspliti = 1083,
1099 A4_boundscheck_hi = 1084,
1100 A4_boundscheck_lo = 1085,
1101 A4_cmpbeq = 1086,
1102 A4_cmpbeqi = 1087,
1103 A4_cmpbgt = 1088,
1104 A4_cmpbgti = 1089,
1105 A4_cmpbgtu = 1090,
1106 A4_cmpbgtui = 1091,
1107 A4_cmpheq = 1092,
1108 A4_cmpheqi = 1093,
1109 A4_cmphgt = 1094,
1110 A4_cmphgti = 1095,
1111 A4_cmphgtu = 1096,
1112 A4_cmphgtui = 1097,
1113 A4_combineii = 1098,
1114 A4_combineir = 1099,
1115 A4_combineri = 1100,
1116 A4_cround_ri = 1101,
1117 A4_cround_rr = 1102,
1118 A4_ext = 1103,
1119 A4_modwrapu = 1104,
1120 A4_orn = 1105,
1121 A4_ornp = 1106,
1122 A4_paslhf = 1107,
1123 A4_paslhfnew = 1108,
1124 A4_paslht = 1109,
1125 A4_paslhtnew = 1110,
1126 A4_pasrhf = 1111,
1127 A4_pasrhfnew = 1112,
1128 A4_pasrht = 1113,
1129 A4_pasrhtnew = 1114,
1130 A4_psxtbf = 1115,
1131 A4_psxtbfnew = 1116,
1132 A4_psxtbt = 1117,
1133 A4_psxtbtnew = 1118,
1134 A4_psxthf = 1119,
1135 A4_psxthfnew = 1120,
1136 A4_psxtht = 1121,
1137 A4_psxthtnew = 1122,
1138 A4_pzxtbf = 1123,
1139 A4_pzxtbfnew = 1124,
1140 A4_pzxtbt = 1125,
1141 A4_pzxtbtnew = 1126,
1142 A4_pzxthf = 1127,
1143 A4_pzxthfnew = 1128,
1144 A4_pzxtht = 1129,
1145 A4_pzxthtnew = 1130,
1146 A4_rcmpeq = 1131,
1147 A4_rcmpeqi = 1132,
1148 A4_rcmpneq = 1133,
1149 A4_rcmpneqi = 1134,
1150 A4_round_ri = 1135,
1151 A4_round_ri_sat = 1136,
1152 A4_round_rr = 1137,
1153 A4_round_rr_sat = 1138,
1154 A4_subp_c = 1139,
1155 A4_tfrcpp = 1140,
1156 A4_tfrpcp = 1141,
1157 A4_tlbmatch = 1142,
1158 A4_vcmpbeq_any = 1143,
1159 A4_vcmpbeqi = 1144,
1160 A4_vcmpbgt = 1145,
1161 A4_vcmpbgti = 1146,
1162 A4_vcmpbgtui = 1147,
1163 A4_vcmpheqi = 1148,
1164 A4_vcmphgti = 1149,
1165 A4_vcmphgtui = 1150,
1166 A4_vcmpweqi = 1151,
1167 A4_vcmpwgti = 1152,
1168 A4_vcmpwgtui = 1153,
1169 A4_vrmaxh = 1154,
1170 A4_vrmaxuh = 1155,
1171 A4_vrmaxuw = 1156,
1172 A4_vrmaxw = 1157,
1173 A4_vrminh = 1158,
1174 A4_vrminuh = 1159,
1175 A4_vrminuw = 1160,
1176 A4_vrminw = 1161,
1177 A5_ACS = 1162,
1178 A5_vaddhubs = 1163,
1179 A6_vcmpbeq_notany = 1164,
1180 A6_vminub_RdP = 1165,
1181 A7_clip = 1166,
1182 A7_croundd_ri = 1167,
1183 A7_croundd_rr = 1168,
1184 A7_vclip = 1169,
1185 C2_all8 = 1170,
1186 C2_and = 1171,
1187 C2_andn = 1172,
1188 C2_any8 = 1173,
1189 C2_bitsclr = 1174,
1190 C2_bitsclri = 1175,
1191 C2_bitsset = 1176,
1192 C2_ccombinewf = 1177,
1193 C2_ccombinewnewf = 1178,
1194 C2_ccombinewnewt = 1179,
1195 C2_ccombinewt = 1180,
1196 C2_cmoveif = 1181,
1197 C2_cmoveit = 1182,
1198 C2_cmovenewif = 1183,
1199 C2_cmovenewit = 1184,
1200 C2_cmpeq = 1185,
1201 C2_cmpeqi = 1186,
1202 C2_cmpeqp = 1187,
1203 C2_cmpgt = 1188,
1204 C2_cmpgti = 1189,
1205 C2_cmpgtp = 1190,
1206 C2_cmpgtu = 1191,
1207 C2_cmpgtui = 1192,
1208 C2_cmpgtup = 1193,
1209 C2_mask = 1194,
1210 C2_mux = 1195,
1211 C2_muxii = 1196,
1212 C2_muxir = 1197,
1213 C2_muxri = 1198,
1214 C2_not = 1199,
1215 C2_or = 1200,
1216 C2_orn = 1201,
1217 C2_tfrpr = 1202,
1218 C2_tfrrp = 1203,
1219 C2_vitpack = 1204,
1220 C2_vmux = 1205,
1221 C2_xor = 1206,
1222 C4_addipc = 1207,
1223 C4_and_and = 1208,
1224 C4_and_andn = 1209,
1225 C4_and_or = 1210,
1226 C4_and_orn = 1211,
1227 C4_cmplte = 1212,
1228 C4_cmpltei = 1213,
1229 C4_cmplteu = 1214,
1230 C4_cmplteui = 1215,
1231 C4_cmpneq = 1216,
1232 C4_cmpneqi = 1217,
1233 C4_fastcorner9 = 1218,
1234 C4_fastcorner9_not = 1219,
1235 C4_nbitsclr = 1220,
1236 C4_nbitsclri = 1221,
1237 C4_nbitsset = 1222,
1238 C4_or_and = 1223,
1239 C4_or_andn = 1224,
1240 C4_or_or = 1225,
1241 C4_or_orn = 1226,
1242 CALLProfile = 1227,
1243 CONST32 = 1228,
1244 CONST64 = 1229,
1245 DuplexIClass0 = 1230,
1246 DuplexIClass1 = 1231,
1247 DuplexIClass2 = 1232,
1248 DuplexIClass3 = 1233,
1249 DuplexIClass4 = 1234,
1250 DuplexIClass5 = 1235,
1251 DuplexIClass6 = 1236,
1252 DuplexIClass7 = 1237,
1253 DuplexIClass8 = 1238,
1254 DuplexIClass9 = 1239,
1255 DuplexIClassA = 1240,
1256 DuplexIClassB = 1241,
1257 DuplexIClassC = 1242,
1258 DuplexIClassD = 1243,
1259 DuplexIClassE = 1244,
1260 DuplexIClassF = 1245,
1261 EH_RETURN_JMPR = 1246,
1262 F2_conv_d2df = 1247,
1263 F2_conv_d2sf = 1248,
1264 F2_conv_df2d = 1249,
1265 F2_conv_df2d_chop = 1250,
1266 F2_conv_df2sf = 1251,
1267 F2_conv_df2ud = 1252,
1268 F2_conv_df2ud_chop = 1253,
1269 F2_conv_df2uw = 1254,
1270 F2_conv_df2uw_chop = 1255,
1271 F2_conv_df2w = 1256,
1272 F2_conv_df2w_chop = 1257,
1273 F2_conv_sf2d = 1258,
1274 F2_conv_sf2d_chop = 1259,
1275 F2_conv_sf2df = 1260,
1276 F2_conv_sf2ud = 1261,
1277 F2_conv_sf2ud_chop = 1262,
1278 F2_conv_sf2uw = 1263,
1279 F2_conv_sf2uw_chop = 1264,
1280 F2_conv_sf2w = 1265,
1281 F2_conv_sf2w_chop = 1266,
1282 F2_conv_ud2df = 1267,
1283 F2_conv_ud2sf = 1268,
1284 F2_conv_uw2df = 1269,
1285 F2_conv_uw2sf = 1270,
1286 F2_conv_w2df = 1271,
1287 F2_conv_w2sf = 1272,
1288 F2_dfadd = 1273,
1289 F2_dfclass = 1274,
1290 F2_dfcmpeq = 1275,
1291 F2_dfcmpge = 1276,
1292 F2_dfcmpgt = 1277,
1293 F2_dfcmpuo = 1278,
1294 F2_dfimm_n = 1279,
1295 F2_dfimm_p = 1280,
1296 F2_dfmax = 1281,
1297 F2_dfmin = 1282,
1298 F2_dfmpyfix = 1283,
1299 F2_dfmpyhh = 1284,
1300 F2_dfmpylh = 1285,
1301 F2_dfmpyll = 1286,
1302 F2_dfsub = 1287,
1303 F2_sfadd = 1288,
1304 F2_sfclass = 1289,
1305 F2_sfcmpeq = 1290,
1306 F2_sfcmpge = 1291,
1307 F2_sfcmpgt = 1292,
1308 F2_sfcmpuo = 1293,
1309 F2_sffixupd = 1294,
1310 F2_sffixupn = 1295,
1311 F2_sffixupr = 1296,
1312 F2_sffma = 1297,
1313 F2_sffma_lib = 1298,
1314 F2_sffma_sc = 1299,
1315 F2_sffms = 1300,
1316 F2_sffms_lib = 1301,
1317 F2_sfimm_n = 1302,
1318 F2_sfimm_p = 1303,
1319 F2_sfinvsqrta = 1304,
1320 F2_sfmax = 1305,
1321 F2_sfmin = 1306,
1322 F2_sfmpy = 1307,
1323 F2_sfrecipa = 1308,
1324 F2_sfsub = 1309,
1325 G4_tfrgcpp = 1310,
1326 G4_tfrgcrr = 1311,
1327 G4_tfrgpcp = 1312,
1328 G4_tfrgrcr = 1313,
1329 HI = 1314,
1330 J2_call = 1315,
1331 J2_callf = 1316,
1332 J2_callr = 1317,
1333 J2_callrf = 1318,
1334 J2_callrh = 1319,
1335 J2_callrt = 1320,
1336 J2_callt = 1321,
1337 J2_jump = 1322,
1338 J2_jumpf = 1323,
1339 J2_jumpfnew = 1324,
1340 J2_jumpfnewpt = 1325,
1341 J2_jumpfpt = 1326,
1342 J2_jumpr = 1327,
1343 J2_jumprf = 1328,
1344 J2_jumprfnew = 1329,
1345 J2_jumprfnewpt = 1330,
1346 J2_jumprfpt = 1331,
1347 J2_jumprgtez = 1332,
1348 J2_jumprgtezpt = 1333,
1349 J2_jumprh = 1334,
1350 J2_jumprltez = 1335,
1351 J2_jumprltezpt = 1336,
1352 J2_jumprnz = 1337,
1353 J2_jumprnzpt = 1338,
1354 J2_jumprt = 1339,
1355 J2_jumprtnew = 1340,
1356 J2_jumprtnewpt = 1341,
1357 J2_jumprtpt = 1342,
1358 J2_jumprz = 1343,
1359 J2_jumprzpt = 1344,
1360 J2_jumpt = 1345,
1361 J2_jumptnew = 1346,
1362 J2_jumptnewpt = 1347,
1363 J2_jumptpt = 1348,
1364 J2_loop0i = 1349,
1365 J2_loop0iext = 1350,
1366 J2_loop0r = 1351,
1367 J2_loop0rext = 1352,
1368 J2_loop1i = 1353,
1369 J2_loop1iext = 1354,
1370 J2_loop1r = 1355,
1371 J2_loop1rext = 1356,
1372 J2_pause = 1357,
1373 J2_ploop1si = 1358,
1374 J2_ploop1sr = 1359,
1375 J2_ploop2si = 1360,
1376 J2_ploop2sr = 1361,
1377 J2_ploop3si = 1362,
1378 J2_ploop3sr = 1363,
1379 J2_rte = 1364,
1380 J2_trap0 = 1365,
1381 J2_trap1 = 1366,
1382 J2_unpause = 1367,
1383 J4_cmpeq_f_jumpnv_nt = 1368,
1384 J4_cmpeq_f_jumpnv_t = 1369,
1385 J4_cmpeq_fp0_jump_nt = 1370,
1386 J4_cmpeq_fp0_jump_t = 1371,
1387 J4_cmpeq_fp1_jump_nt = 1372,
1388 J4_cmpeq_fp1_jump_t = 1373,
1389 J4_cmpeq_t_jumpnv_nt = 1374,
1390 J4_cmpeq_t_jumpnv_t = 1375,
1391 J4_cmpeq_tp0_jump_nt = 1376,
1392 J4_cmpeq_tp0_jump_t = 1377,
1393 J4_cmpeq_tp1_jump_nt = 1378,
1394 J4_cmpeq_tp1_jump_t = 1379,
1395 J4_cmpeqi_f_jumpnv_nt = 1380,
1396 J4_cmpeqi_f_jumpnv_t = 1381,
1397 J4_cmpeqi_fp0_jump_nt = 1382,
1398 J4_cmpeqi_fp0_jump_t = 1383,
1399 J4_cmpeqi_fp1_jump_nt = 1384,
1400 J4_cmpeqi_fp1_jump_t = 1385,
1401 J4_cmpeqi_t_jumpnv_nt = 1386,
1402 J4_cmpeqi_t_jumpnv_t = 1387,
1403 J4_cmpeqi_tp0_jump_nt = 1388,
1404 J4_cmpeqi_tp0_jump_t = 1389,
1405 J4_cmpeqi_tp1_jump_nt = 1390,
1406 J4_cmpeqi_tp1_jump_t = 1391,
1407 J4_cmpeqn1_f_jumpnv_nt = 1392,
1408 J4_cmpeqn1_f_jumpnv_t = 1393,
1409 J4_cmpeqn1_fp0_jump_nt = 1394,
1410 J4_cmpeqn1_fp0_jump_t = 1395,
1411 J4_cmpeqn1_fp1_jump_nt = 1396,
1412 J4_cmpeqn1_fp1_jump_t = 1397,
1413 J4_cmpeqn1_t_jumpnv_nt = 1398,
1414 J4_cmpeqn1_t_jumpnv_t = 1399,
1415 J4_cmpeqn1_tp0_jump_nt = 1400,
1416 J4_cmpeqn1_tp0_jump_t = 1401,
1417 J4_cmpeqn1_tp1_jump_nt = 1402,
1418 J4_cmpeqn1_tp1_jump_t = 1403,
1419 J4_cmpgt_f_jumpnv_nt = 1404,
1420 J4_cmpgt_f_jumpnv_t = 1405,
1421 J4_cmpgt_fp0_jump_nt = 1406,
1422 J4_cmpgt_fp0_jump_t = 1407,
1423 J4_cmpgt_fp1_jump_nt = 1408,
1424 J4_cmpgt_fp1_jump_t = 1409,
1425 J4_cmpgt_t_jumpnv_nt = 1410,
1426 J4_cmpgt_t_jumpnv_t = 1411,
1427 J4_cmpgt_tp0_jump_nt = 1412,
1428 J4_cmpgt_tp0_jump_t = 1413,
1429 J4_cmpgt_tp1_jump_nt = 1414,
1430 J4_cmpgt_tp1_jump_t = 1415,
1431 J4_cmpgti_f_jumpnv_nt = 1416,
1432 J4_cmpgti_f_jumpnv_t = 1417,
1433 J4_cmpgti_fp0_jump_nt = 1418,
1434 J4_cmpgti_fp0_jump_t = 1419,
1435 J4_cmpgti_fp1_jump_nt = 1420,
1436 J4_cmpgti_fp1_jump_t = 1421,
1437 J4_cmpgti_t_jumpnv_nt = 1422,
1438 J4_cmpgti_t_jumpnv_t = 1423,
1439 J4_cmpgti_tp0_jump_nt = 1424,
1440 J4_cmpgti_tp0_jump_t = 1425,
1441 J4_cmpgti_tp1_jump_nt = 1426,
1442 J4_cmpgti_tp1_jump_t = 1427,
1443 J4_cmpgtn1_f_jumpnv_nt = 1428,
1444 J4_cmpgtn1_f_jumpnv_t = 1429,
1445 J4_cmpgtn1_fp0_jump_nt = 1430,
1446 J4_cmpgtn1_fp0_jump_t = 1431,
1447 J4_cmpgtn1_fp1_jump_nt = 1432,
1448 J4_cmpgtn1_fp1_jump_t = 1433,
1449 J4_cmpgtn1_t_jumpnv_nt = 1434,
1450 J4_cmpgtn1_t_jumpnv_t = 1435,
1451 J4_cmpgtn1_tp0_jump_nt = 1436,
1452 J4_cmpgtn1_tp0_jump_t = 1437,
1453 J4_cmpgtn1_tp1_jump_nt = 1438,
1454 J4_cmpgtn1_tp1_jump_t = 1439,
1455 J4_cmpgtu_f_jumpnv_nt = 1440,
1456 J4_cmpgtu_f_jumpnv_t = 1441,
1457 J4_cmpgtu_fp0_jump_nt = 1442,
1458 J4_cmpgtu_fp0_jump_t = 1443,
1459 J4_cmpgtu_fp1_jump_nt = 1444,
1460 J4_cmpgtu_fp1_jump_t = 1445,
1461 J4_cmpgtu_t_jumpnv_nt = 1446,
1462 J4_cmpgtu_t_jumpnv_t = 1447,
1463 J4_cmpgtu_tp0_jump_nt = 1448,
1464 J4_cmpgtu_tp0_jump_t = 1449,
1465 J4_cmpgtu_tp1_jump_nt = 1450,
1466 J4_cmpgtu_tp1_jump_t = 1451,
1467 J4_cmpgtui_f_jumpnv_nt = 1452,
1468 J4_cmpgtui_f_jumpnv_t = 1453,
1469 J4_cmpgtui_fp0_jump_nt = 1454,
1470 J4_cmpgtui_fp0_jump_t = 1455,
1471 J4_cmpgtui_fp1_jump_nt = 1456,
1472 J4_cmpgtui_fp1_jump_t = 1457,
1473 J4_cmpgtui_t_jumpnv_nt = 1458,
1474 J4_cmpgtui_t_jumpnv_t = 1459,
1475 J4_cmpgtui_tp0_jump_nt = 1460,
1476 J4_cmpgtui_tp0_jump_t = 1461,
1477 J4_cmpgtui_tp1_jump_nt = 1462,
1478 J4_cmpgtui_tp1_jump_t = 1463,
1479 J4_cmplt_f_jumpnv_nt = 1464,
1480 J4_cmplt_f_jumpnv_t = 1465,
1481 J4_cmplt_t_jumpnv_nt = 1466,
1482 J4_cmplt_t_jumpnv_t = 1467,
1483 J4_cmpltu_f_jumpnv_nt = 1468,
1484 J4_cmpltu_f_jumpnv_t = 1469,
1485 J4_cmpltu_t_jumpnv_nt = 1470,
1486 J4_cmpltu_t_jumpnv_t = 1471,
1487 J4_hintjumpr = 1472,
1488 J4_jumpseti = 1473,
1489 J4_jumpsetr = 1474,
1490 J4_tstbit0_f_jumpnv_nt = 1475,
1491 J4_tstbit0_f_jumpnv_t = 1476,
1492 J4_tstbit0_fp0_jump_nt = 1477,
1493 J4_tstbit0_fp0_jump_t = 1478,
1494 J4_tstbit0_fp1_jump_nt = 1479,
1495 J4_tstbit0_fp1_jump_t = 1480,
1496 J4_tstbit0_t_jumpnv_nt = 1481,
1497 J4_tstbit0_t_jumpnv_t = 1482,
1498 J4_tstbit0_tp0_jump_nt = 1483,
1499 J4_tstbit0_tp0_jump_t = 1484,
1500 J4_tstbit0_tp1_jump_nt = 1485,
1501 J4_tstbit0_tp1_jump_t = 1486,
1502 L2_deallocframe = 1487,
1503 L2_loadalignb_io = 1488,
1504 L2_loadalignb_pbr = 1489,
1505 L2_loadalignb_pci = 1490,
1506 L2_loadalignb_pcr = 1491,
1507 L2_loadalignb_pi = 1492,
1508 L2_loadalignb_pr = 1493,
1509 L2_loadalignh_io = 1494,
1510 L2_loadalignh_pbr = 1495,
1511 L2_loadalignh_pci = 1496,
1512 L2_loadalignh_pcr = 1497,
1513 L2_loadalignh_pi = 1498,
1514 L2_loadalignh_pr = 1499,
1515 L2_loadbsw2_io = 1500,
1516 L2_loadbsw2_pbr = 1501,
1517 L2_loadbsw2_pci = 1502,
1518 L2_loadbsw2_pcr = 1503,
1519 L2_loadbsw2_pi = 1504,
1520 L2_loadbsw2_pr = 1505,
1521 L2_loadbsw4_io = 1506,
1522 L2_loadbsw4_pbr = 1507,
1523 L2_loadbsw4_pci = 1508,
1524 L2_loadbsw4_pcr = 1509,
1525 L2_loadbsw4_pi = 1510,
1526 L2_loadbsw4_pr = 1511,
1527 L2_loadbzw2_io = 1512,
1528 L2_loadbzw2_pbr = 1513,
1529 L2_loadbzw2_pci = 1514,
1530 L2_loadbzw2_pcr = 1515,
1531 L2_loadbzw2_pi = 1516,
1532 L2_loadbzw2_pr = 1517,
1533 L2_loadbzw4_io = 1518,
1534 L2_loadbzw4_pbr = 1519,
1535 L2_loadbzw4_pci = 1520,
1536 L2_loadbzw4_pcr = 1521,
1537 L2_loadbzw4_pi = 1522,
1538 L2_loadbzw4_pr = 1523,
1539 L2_loadrb_io = 1524,
1540 L2_loadrb_pbr = 1525,
1541 L2_loadrb_pci = 1526,
1542 L2_loadrb_pcr = 1527,
1543 L2_loadrb_pi = 1528,
1544 L2_loadrb_pr = 1529,
1545 L2_loadrbgp = 1530,
1546 L2_loadrd_io = 1531,
1547 L2_loadrd_pbr = 1532,
1548 L2_loadrd_pci = 1533,
1549 L2_loadrd_pcr = 1534,
1550 L2_loadrd_pi = 1535,
1551 L2_loadrd_pr = 1536,
1552 L2_loadrdgp = 1537,
1553 L2_loadrh_io = 1538,
1554 L2_loadrh_pbr = 1539,
1555 L2_loadrh_pci = 1540,
1556 L2_loadrh_pcr = 1541,
1557 L2_loadrh_pi = 1542,
1558 L2_loadrh_pr = 1543,
1559 L2_loadrhgp = 1544,
1560 L2_loadri_io = 1545,
1561 L2_loadri_pbr = 1546,
1562 L2_loadri_pci = 1547,
1563 L2_loadri_pcr = 1548,
1564 L2_loadri_pi = 1549,
1565 L2_loadri_pr = 1550,
1566 L2_loadrigp = 1551,
1567 L2_loadrub_io = 1552,
1568 L2_loadrub_pbr = 1553,
1569 L2_loadrub_pci = 1554,
1570 L2_loadrub_pcr = 1555,
1571 L2_loadrub_pi = 1556,
1572 L2_loadrub_pr = 1557,
1573 L2_loadrubgp = 1558,
1574 L2_loadruh_io = 1559,
1575 L2_loadruh_pbr = 1560,
1576 L2_loadruh_pci = 1561,
1577 L2_loadruh_pcr = 1562,
1578 L2_loadruh_pi = 1563,
1579 L2_loadruh_pr = 1564,
1580 L2_loadruhgp = 1565,
1581 L2_loadw_aq = 1566,
1582 L2_loadw_locked = 1567,
1583 L2_ploadrbf_io = 1568,
1584 L2_ploadrbf_pi = 1569,
1585 L2_ploadrbfnew_io = 1570,
1586 L2_ploadrbfnew_pi = 1571,
1587 L2_ploadrbt_io = 1572,
1588 L2_ploadrbt_pi = 1573,
1589 L2_ploadrbtnew_io = 1574,
1590 L2_ploadrbtnew_pi = 1575,
1591 L2_ploadrdf_io = 1576,
1592 L2_ploadrdf_pi = 1577,
1593 L2_ploadrdfnew_io = 1578,
1594 L2_ploadrdfnew_pi = 1579,
1595 L2_ploadrdt_io = 1580,
1596 L2_ploadrdt_pi = 1581,
1597 L2_ploadrdtnew_io = 1582,
1598 L2_ploadrdtnew_pi = 1583,
1599 L2_ploadrhf_io = 1584,
1600 L2_ploadrhf_pi = 1585,
1601 L2_ploadrhfnew_io = 1586,
1602 L2_ploadrhfnew_pi = 1587,
1603 L2_ploadrht_io = 1588,
1604 L2_ploadrht_pi = 1589,
1605 L2_ploadrhtnew_io = 1590,
1606 L2_ploadrhtnew_pi = 1591,
1607 L2_ploadrif_io = 1592,
1608 L2_ploadrif_pi = 1593,
1609 L2_ploadrifnew_io = 1594,
1610 L2_ploadrifnew_pi = 1595,
1611 L2_ploadrit_io = 1596,
1612 L2_ploadrit_pi = 1597,
1613 L2_ploadritnew_io = 1598,
1614 L2_ploadritnew_pi = 1599,
1615 L2_ploadrubf_io = 1600,
1616 L2_ploadrubf_pi = 1601,
1617 L2_ploadrubfnew_io = 1602,
1618 L2_ploadrubfnew_pi = 1603,
1619 L2_ploadrubt_io = 1604,
1620 L2_ploadrubt_pi = 1605,
1621 L2_ploadrubtnew_io = 1606,
1622 L2_ploadrubtnew_pi = 1607,
1623 L2_ploadruhf_io = 1608,
1624 L2_ploadruhf_pi = 1609,
1625 L2_ploadruhfnew_io = 1610,
1626 L2_ploadruhfnew_pi = 1611,
1627 L2_ploadruht_io = 1612,
1628 L2_ploadruht_pi = 1613,
1629 L2_ploadruhtnew_io = 1614,
1630 L2_ploadruhtnew_pi = 1615,
1631 L4_add_memopb_io = 1616,
1632 L4_add_memoph_io = 1617,
1633 L4_add_memopw_io = 1618,
1634 L4_and_memopb_io = 1619,
1635 L4_and_memoph_io = 1620,
1636 L4_and_memopw_io = 1621,
1637 L4_iadd_memopb_io = 1622,
1638 L4_iadd_memoph_io = 1623,
1639 L4_iadd_memopw_io = 1624,
1640 L4_iand_memopb_io = 1625,
1641 L4_iand_memoph_io = 1626,
1642 L4_iand_memopw_io = 1627,
1643 L4_ior_memopb_io = 1628,
1644 L4_ior_memoph_io = 1629,
1645 L4_ior_memopw_io = 1630,
1646 L4_isub_memopb_io = 1631,
1647 L4_isub_memoph_io = 1632,
1648 L4_isub_memopw_io = 1633,
1649 L4_loadalignb_ap = 1634,
1650 L4_loadalignb_ur = 1635,
1651 L4_loadalignh_ap = 1636,
1652 L4_loadalignh_ur = 1637,
1653 L4_loadbsw2_ap = 1638,
1654 L4_loadbsw2_ur = 1639,
1655 L4_loadbsw4_ap = 1640,
1656 L4_loadbsw4_ur = 1641,
1657 L4_loadbzw2_ap = 1642,
1658 L4_loadbzw2_ur = 1643,
1659 L4_loadbzw4_ap = 1644,
1660 L4_loadbzw4_ur = 1645,
1661 L4_loadd_aq = 1646,
1662 L4_loadd_locked = 1647,
1663 L4_loadrb_ap = 1648,
1664 L4_loadrb_rr = 1649,
1665 L4_loadrb_ur = 1650,
1666 L4_loadrd_ap = 1651,
1667 L4_loadrd_rr = 1652,
1668 L4_loadrd_ur = 1653,
1669 L4_loadrh_ap = 1654,
1670 L4_loadrh_rr = 1655,
1671 L4_loadrh_ur = 1656,
1672 L4_loadri_ap = 1657,
1673 L4_loadri_rr = 1658,
1674 L4_loadri_ur = 1659,
1675 L4_loadrub_ap = 1660,
1676 L4_loadrub_rr = 1661,
1677 L4_loadrub_ur = 1662,
1678 L4_loadruh_ap = 1663,
1679 L4_loadruh_rr = 1664,
1680 L4_loadruh_ur = 1665,
1681 L4_loadw_phys = 1666,
1682 L4_or_memopb_io = 1667,
1683 L4_or_memoph_io = 1668,
1684 L4_or_memopw_io = 1669,
1685 L4_ploadrbf_abs = 1670,
1686 L4_ploadrbf_rr = 1671,
1687 L4_ploadrbfnew_abs = 1672,
1688 L4_ploadrbfnew_rr = 1673,
1689 L4_ploadrbt_abs = 1674,
1690 L4_ploadrbt_rr = 1675,
1691 L4_ploadrbtnew_abs = 1676,
1692 L4_ploadrbtnew_rr = 1677,
1693 L4_ploadrdf_abs = 1678,
1694 L4_ploadrdf_rr = 1679,
1695 L4_ploadrdfnew_abs = 1680,
1696 L4_ploadrdfnew_rr = 1681,
1697 L4_ploadrdt_abs = 1682,
1698 L4_ploadrdt_rr = 1683,
1699 L4_ploadrdtnew_abs = 1684,
1700 L4_ploadrdtnew_rr = 1685,
1701 L4_ploadrhf_abs = 1686,
1702 L4_ploadrhf_rr = 1687,
1703 L4_ploadrhfnew_abs = 1688,
1704 L4_ploadrhfnew_rr = 1689,
1705 L4_ploadrht_abs = 1690,
1706 L4_ploadrht_rr = 1691,
1707 L4_ploadrhtnew_abs = 1692,
1708 L4_ploadrhtnew_rr = 1693,
1709 L4_ploadrif_abs = 1694,
1710 L4_ploadrif_rr = 1695,
1711 L4_ploadrifnew_abs = 1696,
1712 L4_ploadrifnew_rr = 1697,
1713 L4_ploadrit_abs = 1698,
1714 L4_ploadrit_rr = 1699,
1715 L4_ploadritnew_abs = 1700,
1716 L4_ploadritnew_rr = 1701,
1717 L4_ploadrubf_abs = 1702,
1718 L4_ploadrubf_rr = 1703,
1719 L4_ploadrubfnew_abs = 1704,
1720 L4_ploadrubfnew_rr = 1705,
1721 L4_ploadrubt_abs = 1706,
1722 L4_ploadrubt_rr = 1707,
1723 L4_ploadrubtnew_abs = 1708,
1724 L4_ploadrubtnew_rr = 1709,
1725 L4_ploadruhf_abs = 1710,
1726 L4_ploadruhf_rr = 1711,
1727 L4_ploadruhfnew_abs = 1712,
1728 L4_ploadruhfnew_rr = 1713,
1729 L4_ploadruht_abs = 1714,
1730 L4_ploadruht_rr = 1715,
1731 L4_ploadruhtnew_abs = 1716,
1732 L4_ploadruhtnew_rr = 1717,
1733 L4_return = 1718,
1734 L4_return_f = 1719,
1735 L4_return_fnew_pnt = 1720,
1736 L4_return_fnew_pt = 1721,
1737 L4_return_t = 1722,
1738 L4_return_tnew_pnt = 1723,
1739 L4_return_tnew_pt = 1724,
1740 L4_sub_memopb_io = 1725,
1741 L4_sub_memoph_io = 1726,
1742 L4_sub_memopw_io = 1727,
1743 L6_memcpy = 1728,
1744 LO = 1729,
1745 M2_acci = 1730,
1746 M2_accii = 1731,
1747 M2_cmaci_s0 = 1732,
1748 M2_cmacr_s0 = 1733,
1749 M2_cmacs_s0 = 1734,
1750 M2_cmacs_s1 = 1735,
1751 M2_cmacsc_s0 = 1736,
1752 M2_cmacsc_s1 = 1737,
1753 M2_cmpyi_s0 = 1738,
1754 M2_cmpyr_s0 = 1739,
1755 M2_cmpyrs_s0 = 1740,
1756 M2_cmpyrs_s1 = 1741,
1757 M2_cmpyrsc_s0 = 1742,
1758 M2_cmpyrsc_s1 = 1743,
1759 M2_cmpys_s0 = 1744,
1760 M2_cmpys_s1 = 1745,
1761 M2_cmpysc_s0 = 1746,
1762 M2_cmpysc_s1 = 1747,
1763 M2_cnacs_s0 = 1748,
1764 M2_cnacs_s1 = 1749,
1765 M2_cnacsc_s0 = 1750,
1766 M2_cnacsc_s1 = 1751,
1767 M2_dpmpyss_acc_s0 = 1752,
1768 M2_dpmpyss_nac_s0 = 1753,
1769 M2_dpmpyss_rnd_s0 = 1754,
1770 M2_dpmpyss_s0 = 1755,
1771 M2_dpmpyuu_acc_s0 = 1756,
1772 M2_dpmpyuu_nac_s0 = 1757,
1773 M2_dpmpyuu_s0 = 1758,
1774 M2_hmmpyh_rs1 = 1759,
1775 M2_hmmpyh_s1 = 1760,
1776 M2_hmmpyl_rs1 = 1761,
1777 M2_hmmpyl_s1 = 1762,
1778 M2_maci = 1763,
1779 M2_macsin = 1764,
1780 M2_macsip = 1765,
1781 M2_mmachs_rs0 = 1766,
1782 M2_mmachs_rs1 = 1767,
1783 M2_mmachs_s0 = 1768,
1784 M2_mmachs_s1 = 1769,
1785 M2_mmacls_rs0 = 1770,
1786 M2_mmacls_rs1 = 1771,
1787 M2_mmacls_s0 = 1772,
1788 M2_mmacls_s1 = 1773,
1789 M2_mmacuhs_rs0 = 1774,
1790 M2_mmacuhs_rs1 = 1775,
1791 M2_mmacuhs_s0 = 1776,
1792 M2_mmacuhs_s1 = 1777,
1793 M2_mmaculs_rs0 = 1778,
1794 M2_mmaculs_rs1 = 1779,
1795 M2_mmaculs_s0 = 1780,
1796 M2_mmaculs_s1 = 1781,
1797 M2_mmpyh_rs0 = 1782,
1798 M2_mmpyh_rs1 = 1783,
1799 M2_mmpyh_s0 = 1784,
1800 M2_mmpyh_s1 = 1785,
1801 M2_mmpyl_rs0 = 1786,
1802 M2_mmpyl_rs1 = 1787,
1803 M2_mmpyl_s0 = 1788,
1804 M2_mmpyl_s1 = 1789,
1805 M2_mmpyuh_rs0 = 1790,
1806 M2_mmpyuh_rs1 = 1791,
1807 M2_mmpyuh_s0 = 1792,
1808 M2_mmpyuh_s1 = 1793,
1809 M2_mmpyul_rs0 = 1794,
1810 M2_mmpyul_rs1 = 1795,
1811 M2_mmpyul_s0 = 1796,
1812 M2_mmpyul_s1 = 1797,
1813 M2_mnaci = 1798,
1814 M2_mpy_acc_hh_s0 = 1799,
1815 M2_mpy_acc_hh_s1 = 1800,
1816 M2_mpy_acc_hl_s0 = 1801,
1817 M2_mpy_acc_hl_s1 = 1802,
1818 M2_mpy_acc_lh_s0 = 1803,
1819 M2_mpy_acc_lh_s1 = 1804,
1820 M2_mpy_acc_ll_s0 = 1805,
1821 M2_mpy_acc_ll_s1 = 1806,
1822 M2_mpy_acc_sat_hh_s0 = 1807,
1823 M2_mpy_acc_sat_hh_s1 = 1808,
1824 M2_mpy_acc_sat_hl_s0 = 1809,
1825 M2_mpy_acc_sat_hl_s1 = 1810,
1826 M2_mpy_acc_sat_lh_s0 = 1811,
1827 M2_mpy_acc_sat_lh_s1 = 1812,
1828 M2_mpy_acc_sat_ll_s0 = 1813,
1829 M2_mpy_acc_sat_ll_s1 = 1814,
1830 M2_mpy_hh_s0 = 1815,
1831 M2_mpy_hh_s1 = 1816,
1832 M2_mpy_hl_s0 = 1817,
1833 M2_mpy_hl_s1 = 1818,
1834 M2_mpy_lh_s0 = 1819,
1835 M2_mpy_lh_s1 = 1820,
1836 M2_mpy_ll_s0 = 1821,
1837 M2_mpy_ll_s1 = 1822,
1838 M2_mpy_nac_hh_s0 = 1823,
1839 M2_mpy_nac_hh_s1 = 1824,
1840 M2_mpy_nac_hl_s0 = 1825,
1841 M2_mpy_nac_hl_s1 = 1826,
1842 M2_mpy_nac_lh_s0 = 1827,
1843 M2_mpy_nac_lh_s1 = 1828,
1844 M2_mpy_nac_ll_s0 = 1829,
1845 M2_mpy_nac_ll_s1 = 1830,
1846 M2_mpy_nac_sat_hh_s0 = 1831,
1847 M2_mpy_nac_sat_hh_s1 = 1832,
1848 M2_mpy_nac_sat_hl_s0 = 1833,
1849 M2_mpy_nac_sat_hl_s1 = 1834,
1850 M2_mpy_nac_sat_lh_s0 = 1835,
1851 M2_mpy_nac_sat_lh_s1 = 1836,
1852 M2_mpy_nac_sat_ll_s0 = 1837,
1853 M2_mpy_nac_sat_ll_s1 = 1838,
1854 M2_mpy_rnd_hh_s0 = 1839,
1855 M2_mpy_rnd_hh_s1 = 1840,
1856 M2_mpy_rnd_hl_s0 = 1841,
1857 M2_mpy_rnd_hl_s1 = 1842,
1858 M2_mpy_rnd_lh_s0 = 1843,
1859 M2_mpy_rnd_lh_s1 = 1844,
1860 M2_mpy_rnd_ll_s0 = 1845,
1861 M2_mpy_rnd_ll_s1 = 1846,
1862 M2_mpy_sat_hh_s0 = 1847,
1863 M2_mpy_sat_hh_s1 = 1848,
1864 M2_mpy_sat_hl_s0 = 1849,
1865 M2_mpy_sat_hl_s1 = 1850,
1866 M2_mpy_sat_lh_s0 = 1851,
1867 M2_mpy_sat_lh_s1 = 1852,
1868 M2_mpy_sat_ll_s0 = 1853,
1869 M2_mpy_sat_ll_s1 = 1854,
1870 M2_mpy_sat_rnd_hh_s0 = 1855,
1871 M2_mpy_sat_rnd_hh_s1 = 1856,
1872 M2_mpy_sat_rnd_hl_s0 = 1857,
1873 M2_mpy_sat_rnd_hl_s1 = 1858,
1874 M2_mpy_sat_rnd_lh_s0 = 1859,
1875 M2_mpy_sat_rnd_lh_s1 = 1860,
1876 M2_mpy_sat_rnd_ll_s0 = 1861,
1877 M2_mpy_sat_rnd_ll_s1 = 1862,
1878 M2_mpy_up = 1863,
1879 M2_mpy_up_s1 = 1864,
1880 M2_mpy_up_s1_sat = 1865,
1881 M2_mpyd_acc_hh_s0 = 1866,
1882 M2_mpyd_acc_hh_s1 = 1867,
1883 M2_mpyd_acc_hl_s0 = 1868,
1884 M2_mpyd_acc_hl_s1 = 1869,
1885 M2_mpyd_acc_lh_s0 = 1870,
1886 M2_mpyd_acc_lh_s1 = 1871,
1887 M2_mpyd_acc_ll_s0 = 1872,
1888 M2_mpyd_acc_ll_s1 = 1873,
1889 M2_mpyd_hh_s0 = 1874,
1890 M2_mpyd_hh_s1 = 1875,
1891 M2_mpyd_hl_s0 = 1876,
1892 M2_mpyd_hl_s1 = 1877,
1893 M2_mpyd_lh_s0 = 1878,
1894 M2_mpyd_lh_s1 = 1879,
1895 M2_mpyd_ll_s0 = 1880,
1896 M2_mpyd_ll_s1 = 1881,
1897 M2_mpyd_nac_hh_s0 = 1882,
1898 M2_mpyd_nac_hh_s1 = 1883,
1899 M2_mpyd_nac_hl_s0 = 1884,
1900 M2_mpyd_nac_hl_s1 = 1885,
1901 M2_mpyd_nac_lh_s0 = 1886,
1902 M2_mpyd_nac_lh_s1 = 1887,
1903 M2_mpyd_nac_ll_s0 = 1888,
1904 M2_mpyd_nac_ll_s1 = 1889,
1905 M2_mpyd_rnd_hh_s0 = 1890,
1906 M2_mpyd_rnd_hh_s1 = 1891,
1907 M2_mpyd_rnd_hl_s0 = 1892,
1908 M2_mpyd_rnd_hl_s1 = 1893,
1909 M2_mpyd_rnd_lh_s0 = 1894,
1910 M2_mpyd_rnd_lh_s1 = 1895,
1911 M2_mpyd_rnd_ll_s0 = 1896,
1912 M2_mpyd_rnd_ll_s1 = 1897,
1913 M2_mpyi = 1898,
1914 M2_mpysin = 1899,
1915 M2_mpysip = 1900,
1916 M2_mpysu_up = 1901,
1917 M2_mpyu_acc_hh_s0 = 1902,
1918 M2_mpyu_acc_hh_s1 = 1903,
1919 M2_mpyu_acc_hl_s0 = 1904,
1920 M2_mpyu_acc_hl_s1 = 1905,
1921 M2_mpyu_acc_lh_s0 = 1906,
1922 M2_mpyu_acc_lh_s1 = 1907,
1923 M2_mpyu_acc_ll_s0 = 1908,
1924 M2_mpyu_acc_ll_s1 = 1909,
1925 M2_mpyu_hh_s0 = 1910,
1926 M2_mpyu_hh_s1 = 1911,
1927 M2_mpyu_hl_s0 = 1912,
1928 M2_mpyu_hl_s1 = 1913,
1929 M2_mpyu_lh_s0 = 1914,
1930 M2_mpyu_lh_s1 = 1915,
1931 M2_mpyu_ll_s0 = 1916,
1932 M2_mpyu_ll_s1 = 1917,
1933 M2_mpyu_nac_hh_s0 = 1918,
1934 M2_mpyu_nac_hh_s1 = 1919,
1935 M2_mpyu_nac_hl_s0 = 1920,
1936 M2_mpyu_nac_hl_s1 = 1921,
1937 M2_mpyu_nac_lh_s0 = 1922,
1938 M2_mpyu_nac_lh_s1 = 1923,
1939 M2_mpyu_nac_ll_s0 = 1924,
1940 M2_mpyu_nac_ll_s1 = 1925,
1941 M2_mpyu_up = 1926,
1942 M2_mpyud_acc_hh_s0 = 1927,
1943 M2_mpyud_acc_hh_s1 = 1928,
1944 M2_mpyud_acc_hl_s0 = 1929,
1945 M2_mpyud_acc_hl_s1 = 1930,
1946 M2_mpyud_acc_lh_s0 = 1931,
1947 M2_mpyud_acc_lh_s1 = 1932,
1948 M2_mpyud_acc_ll_s0 = 1933,
1949 M2_mpyud_acc_ll_s1 = 1934,
1950 M2_mpyud_hh_s0 = 1935,
1951 M2_mpyud_hh_s1 = 1936,
1952 M2_mpyud_hl_s0 = 1937,
1953 M2_mpyud_hl_s1 = 1938,
1954 M2_mpyud_lh_s0 = 1939,
1955 M2_mpyud_lh_s1 = 1940,
1956 M2_mpyud_ll_s0 = 1941,
1957 M2_mpyud_ll_s1 = 1942,
1958 M2_mpyud_nac_hh_s0 = 1943,
1959 M2_mpyud_nac_hh_s1 = 1944,
1960 M2_mpyud_nac_hl_s0 = 1945,
1961 M2_mpyud_nac_hl_s1 = 1946,
1962 M2_mpyud_nac_lh_s0 = 1947,
1963 M2_mpyud_nac_lh_s1 = 1948,
1964 M2_mpyud_nac_ll_s0 = 1949,
1965 M2_mpyud_nac_ll_s1 = 1950,
1966 M2_nacci = 1951,
1967 M2_naccii = 1952,
1968 M2_subacc = 1953,
1969 M2_vabsdiffh = 1954,
1970 M2_vabsdiffw = 1955,
1971 M2_vcmac_s0_sat_i = 1956,
1972 M2_vcmac_s0_sat_r = 1957,
1973 M2_vcmpy_s0_sat_i = 1958,
1974 M2_vcmpy_s0_sat_r = 1959,
1975 M2_vcmpy_s1_sat_i = 1960,
1976 M2_vcmpy_s1_sat_r = 1961,
1977 M2_vdmacs_s0 = 1962,
1978 M2_vdmacs_s1 = 1963,
1979 M2_vdmpyrs_s0 = 1964,
1980 M2_vdmpyrs_s1 = 1965,
1981 M2_vdmpys_s0 = 1966,
1982 M2_vdmpys_s1 = 1967,
1983 M2_vmac2 = 1968,
1984 M2_vmac2es = 1969,
1985 M2_vmac2es_s0 = 1970,
1986 M2_vmac2es_s1 = 1971,
1987 M2_vmac2s_s0 = 1972,
1988 M2_vmac2s_s1 = 1973,
1989 M2_vmac2su_s0 = 1974,
1990 M2_vmac2su_s1 = 1975,
1991 M2_vmpy2es_s0 = 1976,
1992 M2_vmpy2es_s1 = 1977,
1993 M2_vmpy2s_s0 = 1978,
1994 M2_vmpy2s_s0pack = 1979,
1995 M2_vmpy2s_s1 = 1980,
1996 M2_vmpy2s_s1pack = 1981,
1997 M2_vmpy2su_s0 = 1982,
1998 M2_vmpy2su_s1 = 1983,
1999 M2_vraddh = 1984,
2000 M2_vradduh = 1985,
2001 M2_vrcmaci_s0 = 1986,
2002 M2_vrcmaci_s0c = 1987,
2003 M2_vrcmacr_s0 = 1988,
2004 M2_vrcmacr_s0c = 1989,
2005 M2_vrcmpyi_s0 = 1990,
2006 M2_vrcmpyi_s0c = 1991,
2007 M2_vrcmpyr_s0 = 1992,
2008 M2_vrcmpyr_s0c = 1993,
2009 M2_vrcmpys_acc_s1_h = 1994,
2010 M2_vrcmpys_acc_s1_l = 1995,
2011 M2_vrcmpys_s1_h = 1996,
2012 M2_vrcmpys_s1_l = 1997,
2013 M2_vrcmpys_s1rp_h = 1998,
2014 M2_vrcmpys_s1rp_l = 1999,
2015 M2_vrmac_s0 = 2000,
2016 M2_vrmpy_s0 = 2001,
2017 M2_xor_xacc = 2002,
2018 M4_and_and = 2003,
2019 M4_and_andn = 2004,
2020 M4_and_or = 2005,
2021 M4_and_xor = 2006,
2022 M4_cmpyi_wh = 2007,
2023 M4_cmpyi_whc = 2008,
2024 M4_cmpyr_wh = 2009,
2025 M4_cmpyr_whc = 2010,
2026 M4_mac_up_s1_sat = 2011,
2027 M4_mpyri_addi = 2012,
2028 M4_mpyri_addr = 2013,
2029 M4_mpyri_addr_u2 = 2014,
2030 M4_mpyrr_addi = 2015,
2031 M4_mpyrr_addr = 2016,
2032 M4_nac_up_s1_sat = 2017,
2033 M4_or_and = 2018,
2034 M4_or_andn = 2019,
2035 M4_or_or = 2020,
2036 M4_or_xor = 2021,
2037 M4_pmpyw = 2022,
2038 M4_pmpyw_acc = 2023,
2039 M4_vpmpyh = 2024,
2040 M4_vpmpyh_acc = 2025,
2041 M4_vrmpyeh_acc_s0 = 2026,
2042 M4_vrmpyeh_acc_s1 = 2027,
2043 M4_vrmpyeh_s0 = 2028,
2044 M4_vrmpyeh_s1 = 2029,
2045 M4_vrmpyoh_acc_s0 = 2030,
2046 M4_vrmpyoh_acc_s1 = 2031,
2047 M4_vrmpyoh_s0 = 2032,
2048 M4_vrmpyoh_s1 = 2033,
2049 M4_xor_and = 2034,
2050 M4_xor_andn = 2035,
2051 M4_xor_or = 2036,
2052 M4_xor_xacc = 2037,
2053 M5_vdmacbsu = 2038,
2054 M5_vdmpybsu = 2039,
2055 M5_vmacbsu = 2040,
2056 M5_vmacbuu = 2041,
2057 M5_vmpybsu = 2042,
2058 M5_vmpybuu = 2043,
2059 M5_vrmacbsu = 2044,
2060 M5_vrmacbuu = 2045,
2061 M5_vrmpybsu = 2046,
2062 M5_vrmpybuu = 2047,
2063 M6_vabsdiffb = 2048,
2064 M6_vabsdiffub = 2049,
2065 M7_dcmpyiw = 2050,
2066 M7_dcmpyiw_acc = 2051,
2067 M7_dcmpyiwc = 2052,
2068 M7_dcmpyiwc_acc = 2053,
2069 M7_dcmpyrw = 2054,
2070 M7_dcmpyrw_acc = 2055,
2071 M7_dcmpyrwc = 2056,
2072 M7_dcmpyrwc_acc = 2057,
2073 M7_wcmpyiw = 2058,
2074 M7_wcmpyiw_rnd = 2059,
2075 M7_wcmpyiwc = 2060,
2076 M7_wcmpyiwc_rnd = 2061,
2077 M7_wcmpyrw = 2062,
2078 M7_wcmpyrw_rnd = 2063,
2079 M7_wcmpyrwc = 2064,
2080 M7_wcmpyrwc_rnd = 2065,
2081 PS_call_stk = 2066,
2082 PS_callr_nr = 2067,
2083 PS_jmpret = 2068,
2084 PS_jmpretf = 2069,
2085 PS_jmpretfnew = 2070,
2086 PS_jmpretfnewpt = 2071,
2087 PS_jmprett = 2072,
2088 PS_jmprettnew = 2073,
2089 PS_jmprettnewpt = 2074,
2090 PS_loadrbabs = 2075,
2091 PS_loadrdabs = 2076,
2092 PS_loadrhabs = 2077,
2093 PS_loadriabs = 2078,
2094 PS_loadrubabs = 2079,
2095 PS_loadruhabs = 2080,
2096 PS_storerbabs = 2081,
2097 PS_storerbnewabs = 2082,
2098 PS_storerdabs = 2083,
2099 PS_storerfabs = 2084,
2100 PS_storerhabs = 2085,
2101 PS_storerhnewabs = 2086,
2102 PS_storeriabs = 2087,
2103 PS_storerinewabs = 2088,
2104 PS_trap1 = 2089,
2105 R6_release_at_vi = 2090,
2106 R6_release_st_vi = 2091,
2107 RESTORE_DEALLOC_BEFORE_TAILCALL_V4 = 2092,
2108 RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT = 2093,
2109 RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC = 2094,
2110 RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC = 2095,
2111 RESTORE_DEALLOC_RET_JMP_V4 = 2096,
2112 RESTORE_DEALLOC_RET_JMP_V4_EXT = 2097,
2113 RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC = 2098,
2114 RESTORE_DEALLOC_RET_JMP_V4_PIC = 2099,
2115 S2_addasl_rrri = 2100,
2116 S2_allocframe = 2101,
2117 S2_asl_i_p = 2102,
2118 S2_asl_i_p_acc = 2103,
2119 S2_asl_i_p_and = 2104,
2120 S2_asl_i_p_nac = 2105,
2121 S2_asl_i_p_or = 2106,
2122 S2_asl_i_p_xacc = 2107,
2123 S2_asl_i_r = 2108,
2124 S2_asl_i_r_acc = 2109,
2125 S2_asl_i_r_and = 2110,
2126 S2_asl_i_r_nac = 2111,
2127 S2_asl_i_r_or = 2112,
2128 S2_asl_i_r_sat = 2113,
2129 S2_asl_i_r_xacc = 2114,
2130 S2_asl_i_vh = 2115,
2131 S2_asl_i_vw = 2116,
2132 S2_asl_r_p = 2117,
2133 S2_asl_r_p_acc = 2118,
2134 S2_asl_r_p_and = 2119,
2135 S2_asl_r_p_nac = 2120,
2136 S2_asl_r_p_or = 2121,
2137 S2_asl_r_p_xor = 2122,
2138 S2_asl_r_r = 2123,
2139 S2_asl_r_r_acc = 2124,
2140 S2_asl_r_r_and = 2125,
2141 S2_asl_r_r_nac = 2126,
2142 S2_asl_r_r_or = 2127,
2143 S2_asl_r_r_sat = 2128,
2144 S2_asl_r_vh = 2129,
2145 S2_asl_r_vw = 2130,
2146 S2_asr_i_p = 2131,
2147 S2_asr_i_p_acc = 2132,
2148 S2_asr_i_p_and = 2133,
2149 S2_asr_i_p_nac = 2134,
2150 S2_asr_i_p_or = 2135,
2151 S2_asr_i_p_rnd = 2136,
2152 S2_asr_i_r = 2137,
2153 S2_asr_i_r_acc = 2138,
2154 S2_asr_i_r_and = 2139,
2155 S2_asr_i_r_nac = 2140,
2156 S2_asr_i_r_or = 2141,
2157 S2_asr_i_r_rnd = 2142,
2158 S2_asr_i_svw_trun = 2143,
2159 S2_asr_i_vh = 2144,
2160 S2_asr_i_vw = 2145,
2161 S2_asr_r_p = 2146,
2162 S2_asr_r_p_acc = 2147,
2163 S2_asr_r_p_and = 2148,
2164 S2_asr_r_p_nac = 2149,
2165 S2_asr_r_p_or = 2150,
2166 S2_asr_r_p_xor = 2151,
2167 S2_asr_r_r = 2152,
2168 S2_asr_r_r_acc = 2153,
2169 S2_asr_r_r_and = 2154,
2170 S2_asr_r_r_nac = 2155,
2171 S2_asr_r_r_or = 2156,
2172 S2_asr_r_r_sat = 2157,
2173 S2_asr_r_svw_trun = 2158,
2174 S2_asr_r_vh = 2159,
2175 S2_asr_r_vw = 2160,
2176 S2_brev = 2161,
2177 S2_brevp = 2162,
2178 S2_cabacdecbin = 2163,
2179 S2_cl0 = 2164,
2180 S2_cl0p = 2165,
2181 S2_cl1 = 2166,
2182 S2_cl1p = 2167,
2183 S2_clb = 2168,
2184 S2_clbnorm = 2169,
2185 S2_clbp = 2170,
2186 S2_clrbit_i = 2171,
2187 S2_clrbit_r = 2172,
2188 S2_ct0 = 2173,
2189 S2_ct0p = 2174,
2190 S2_ct1 = 2175,
2191 S2_ct1p = 2176,
2192 S2_deinterleave = 2177,
2193 S2_extractu = 2178,
2194 S2_extractu_rp = 2179,
2195 S2_extractup = 2180,
2196 S2_extractup_rp = 2181,
2197 S2_insert = 2182,
2198 S2_insert_rp = 2183,
2199 S2_insertp = 2184,
2200 S2_insertp_rp = 2185,
2201 S2_interleave = 2186,
2202 S2_lfsp = 2187,
2203 S2_lsl_r_p = 2188,
2204 S2_lsl_r_p_acc = 2189,
2205 S2_lsl_r_p_and = 2190,
2206 S2_lsl_r_p_nac = 2191,
2207 S2_lsl_r_p_or = 2192,
2208 S2_lsl_r_p_xor = 2193,
2209 S2_lsl_r_r = 2194,
2210 S2_lsl_r_r_acc = 2195,
2211 S2_lsl_r_r_and = 2196,
2212 S2_lsl_r_r_nac = 2197,
2213 S2_lsl_r_r_or = 2198,
2214 S2_lsl_r_vh = 2199,
2215 S2_lsl_r_vw = 2200,
2216 S2_lsr_i_p = 2201,
2217 S2_lsr_i_p_acc = 2202,
2218 S2_lsr_i_p_and = 2203,
2219 S2_lsr_i_p_nac = 2204,
2220 S2_lsr_i_p_or = 2205,
2221 S2_lsr_i_p_xacc = 2206,
2222 S2_lsr_i_r = 2207,
2223 S2_lsr_i_r_acc = 2208,
2224 S2_lsr_i_r_and = 2209,
2225 S2_lsr_i_r_nac = 2210,
2226 S2_lsr_i_r_or = 2211,
2227 S2_lsr_i_r_xacc = 2212,
2228 S2_lsr_i_vh = 2213,
2229 S2_lsr_i_vw = 2214,
2230 S2_lsr_r_p = 2215,
2231 S2_lsr_r_p_acc = 2216,
2232 S2_lsr_r_p_and = 2217,
2233 S2_lsr_r_p_nac = 2218,
2234 S2_lsr_r_p_or = 2219,
2235 S2_lsr_r_p_xor = 2220,
2236 S2_lsr_r_r = 2221,
2237 S2_lsr_r_r_acc = 2222,
2238 S2_lsr_r_r_and = 2223,
2239 S2_lsr_r_r_nac = 2224,
2240 S2_lsr_r_r_or = 2225,
2241 S2_lsr_r_vh = 2226,
2242 S2_lsr_r_vw = 2227,
2243 S2_mask = 2228,
2244 S2_packhl = 2229,
2245 S2_parityp = 2230,
2246 S2_pstorerbf_io = 2231,
2247 S2_pstorerbf_pi = 2232,
2248 S2_pstorerbfnew_pi = 2233,
2249 S2_pstorerbnewf_io = 2234,
2250 S2_pstorerbnewf_pi = 2235,
2251 S2_pstorerbnewfnew_pi = 2236,
2252 S2_pstorerbnewt_io = 2237,
2253 S2_pstorerbnewt_pi = 2238,
2254 S2_pstorerbnewtnew_pi = 2239,
2255 S2_pstorerbt_io = 2240,
2256 S2_pstorerbt_pi = 2241,
2257 S2_pstorerbtnew_pi = 2242,
2258 S2_pstorerdf_io = 2243,
2259 S2_pstorerdf_pi = 2244,
2260 S2_pstorerdfnew_pi = 2245,
2261 S2_pstorerdt_io = 2246,
2262 S2_pstorerdt_pi = 2247,
2263 S2_pstorerdtnew_pi = 2248,
2264 S2_pstorerff_io = 2249,
2265 S2_pstorerff_pi = 2250,
2266 S2_pstorerffnew_pi = 2251,
2267 S2_pstorerft_io = 2252,
2268 S2_pstorerft_pi = 2253,
2269 S2_pstorerftnew_pi = 2254,
2270 S2_pstorerhf_io = 2255,
2271 S2_pstorerhf_pi = 2256,
2272 S2_pstorerhfnew_pi = 2257,
2273 S2_pstorerhnewf_io = 2258,
2274 S2_pstorerhnewf_pi = 2259,
2275 S2_pstorerhnewfnew_pi = 2260,
2276 S2_pstorerhnewt_io = 2261,
2277 S2_pstorerhnewt_pi = 2262,
2278 S2_pstorerhnewtnew_pi = 2263,
2279 S2_pstorerht_io = 2264,
2280 S2_pstorerht_pi = 2265,
2281 S2_pstorerhtnew_pi = 2266,
2282 S2_pstorerif_io = 2267,
2283 S2_pstorerif_pi = 2268,
2284 S2_pstorerifnew_pi = 2269,
2285 S2_pstorerinewf_io = 2270,
2286 S2_pstorerinewf_pi = 2271,
2287 S2_pstorerinewfnew_pi = 2272,
2288 S2_pstorerinewt_io = 2273,
2289 S2_pstorerinewt_pi = 2274,
2290 S2_pstorerinewtnew_pi = 2275,
2291 S2_pstorerit_io = 2276,
2292 S2_pstorerit_pi = 2277,
2293 S2_pstoreritnew_pi = 2278,
2294 S2_setbit_i = 2279,
2295 S2_setbit_r = 2280,
2296 S2_shuffeb = 2281,
2297 S2_shuffeh = 2282,
2298 S2_shuffob = 2283,
2299 S2_shuffoh = 2284,
2300 S2_storerb_io = 2285,
2301 S2_storerb_pbr = 2286,
2302 S2_storerb_pci = 2287,
2303 S2_storerb_pcr = 2288,
2304 S2_storerb_pi = 2289,
2305 S2_storerb_pr = 2290,
2306 S2_storerbgp = 2291,
2307 S2_storerbnew_io = 2292,
2308 S2_storerbnew_pbr = 2293,
2309 S2_storerbnew_pci = 2294,
2310 S2_storerbnew_pcr = 2295,
2311 S2_storerbnew_pi = 2296,
2312 S2_storerbnew_pr = 2297,
2313 S2_storerbnewgp = 2298,
2314 S2_storerd_io = 2299,
2315 S2_storerd_pbr = 2300,
2316 S2_storerd_pci = 2301,
2317 S2_storerd_pcr = 2302,
2318 S2_storerd_pi = 2303,
2319 S2_storerd_pr = 2304,
2320 S2_storerdgp = 2305,
2321 S2_storerf_io = 2306,
2322 S2_storerf_pbr = 2307,
2323 S2_storerf_pci = 2308,
2324 S2_storerf_pcr = 2309,
2325 S2_storerf_pi = 2310,
2326 S2_storerf_pr = 2311,
2327 S2_storerfgp = 2312,
2328 S2_storerh_io = 2313,
2329 S2_storerh_pbr = 2314,
2330 S2_storerh_pci = 2315,
2331 S2_storerh_pcr = 2316,
2332 S2_storerh_pi = 2317,
2333 S2_storerh_pr = 2318,
2334 S2_storerhgp = 2319,
2335 S2_storerhnew_io = 2320,
2336 S2_storerhnew_pbr = 2321,
2337 S2_storerhnew_pci = 2322,
2338 S2_storerhnew_pcr = 2323,
2339 S2_storerhnew_pi = 2324,
2340 S2_storerhnew_pr = 2325,
2341 S2_storerhnewgp = 2326,
2342 S2_storeri_io = 2327,
2343 S2_storeri_pbr = 2328,
2344 S2_storeri_pci = 2329,
2345 S2_storeri_pcr = 2330,
2346 S2_storeri_pi = 2331,
2347 S2_storeri_pr = 2332,
2348 S2_storerigp = 2333,
2349 S2_storerinew_io = 2334,
2350 S2_storerinew_pbr = 2335,
2351 S2_storerinew_pci = 2336,
2352 S2_storerinew_pcr = 2337,
2353 S2_storerinew_pi = 2338,
2354 S2_storerinew_pr = 2339,
2355 S2_storerinewgp = 2340,
2356 S2_storew_locked = 2341,
2357 S2_storew_rl_at_vi = 2342,
2358 S2_storew_rl_st_vi = 2343,
2359 S2_svsathb = 2344,
2360 S2_svsathub = 2345,
2361 S2_tableidxb = 2346,
2362 S2_tableidxd = 2347,
2363 S2_tableidxh = 2348,
2364 S2_tableidxw = 2349,
2365 S2_togglebit_i = 2350,
2366 S2_togglebit_r = 2351,
2367 S2_tstbit_i = 2352,
2368 S2_tstbit_r = 2353,
2369 S2_valignib = 2354,
2370 S2_valignrb = 2355,
2371 S2_vcnegh = 2356,
2372 S2_vcrotate = 2357,
2373 S2_vrcnegh = 2358,
2374 S2_vrndpackwh = 2359,
2375 S2_vrndpackwhs = 2360,
2376 S2_vsathb = 2361,
2377 S2_vsathb_nopack = 2362,
2378 S2_vsathub = 2363,
2379 S2_vsathub_nopack = 2364,
2380 S2_vsatwh = 2365,
2381 S2_vsatwh_nopack = 2366,
2382 S2_vsatwuh = 2367,
2383 S2_vsatwuh_nopack = 2368,
2384 S2_vsplatrb = 2369,
2385 S2_vsplatrh = 2370,
2386 S2_vspliceib = 2371,
2387 S2_vsplicerb = 2372,
2388 S2_vsxtbh = 2373,
2389 S2_vsxthw = 2374,
2390 S2_vtrunehb = 2375,
2391 S2_vtrunewh = 2376,
2392 S2_vtrunohb = 2377,
2393 S2_vtrunowh = 2378,
2394 S2_vzxtbh = 2379,
2395 S2_vzxthw = 2380,
2396 S4_addaddi = 2381,
2397 S4_addi_asl_ri = 2382,
2398 S4_addi_lsr_ri = 2383,
2399 S4_andi_asl_ri = 2384,
2400 S4_andi_lsr_ri = 2385,
2401 S4_clbaddi = 2386,
2402 S4_clbpaddi = 2387,
2403 S4_clbpnorm = 2388,
2404 S4_extract = 2389,
2405 S4_extract_rp = 2390,
2406 S4_extractp = 2391,
2407 S4_extractp_rp = 2392,
2408 S4_lsli = 2393,
2409 S4_ntstbit_i = 2394,
2410 S4_ntstbit_r = 2395,
2411 S4_or_andi = 2396,
2412 S4_or_andix = 2397,
2413 S4_or_ori = 2398,
2414 S4_ori_asl_ri = 2399,
2415 S4_ori_lsr_ri = 2400,
2416 S4_parity = 2401,
2417 S4_pstorerbf_abs = 2402,
2418 S4_pstorerbf_rr = 2403,
2419 S4_pstorerbfnew_abs = 2404,
2420 S4_pstorerbfnew_io = 2405,
2421 S4_pstorerbfnew_rr = 2406,
2422 S4_pstorerbnewf_abs = 2407,
2423 S4_pstorerbnewf_rr = 2408,
2424 S4_pstorerbnewfnew_abs = 2409,
2425 S4_pstorerbnewfnew_io = 2410,
2426 S4_pstorerbnewfnew_rr = 2411,
2427 S4_pstorerbnewt_abs = 2412,
2428 S4_pstorerbnewt_rr = 2413,
2429 S4_pstorerbnewtnew_abs = 2414,
2430 S4_pstorerbnewtnew_io = 2415,
2431 S4_pstorerbnewtnew_rr = 2416,
2432 S4_pstorerbt_abs = 2417,
2433 S4_pstorerbt_rr = 2418,
2434 S4_pstorerbtnew_abs = 2419,
2435 S4_pstorerbtnew_io = 2420,
2436 S4_pstorerbtnew_rr = 2421,
2437 S4_pstorerdf_abs = 2422,
2438 S4_pstorerdf_rr = 2423,
2439 S4_pstorerdfnew_abs = 2424,
2440 S4_pstorerdfnew_io = 2425,
2441 S4_pstorerdfnew_rr = 2426,
2442 S4_pstorerdt_abs = 2427,
2443 S4_pstorerdt_rr = 2428,
2444 S4_pstorerdtnew_abs = 2429,
2445 S4_pstorerdtnew_io = 2430,
2446 S4_pstorerdtnew_rr = 2431,
2447 S4_pstorerff_abs = 2432,
2448 S4_pstorerff_rr = 2433,
2449 S4_pstorerffnew_abs = 2434,
2450 S4_pstorerffnew_io = 2435,
2451 S4_pstorerffnew_rr = 2436,
2452 S4_pstorerft_abs = 2437,
2453 S4_pstorerft_rr = 2438,
2454 S4_pstorerftnew_abs = 2439,
2455 S4_pstorerftnew_io = 2440,
2456 S4_pstorerftnew_rr = 2441,
2457 S4_pstorerhf_abs = 2442,
2458 S4_pstorerhf_rr = 2443,
2459 S4_pstorerhfnew_abs = 2444,
2460 S4_pstorerhfnew_io = 2445,
2461 S4_pstorerhfnew_rr = 2446,
2462 S4_pstorerhnewf_abs = 2447,
2463 S4_pstorerhnewf_rr = 2448,
2464 S4_pstorerhnewfnew_abs = 2449,
2465 S4_pstorerhnewfnew_io = 2450,
2466 S4_pstorerhnewfnew_rr = 2451,
2467 S4_pstorerhnewt_abs = 2452,
2468 S4_pstorerhnewt_rr = 2453,
2469 S4_pstorerhnewtnew_abs = 2454,
2470 S4_pstorerhnewtnew_io = 2455,
2471 S4_pstorerhnewtnew_rr = 2456,
2472 S4_pstorerht_abs = 2457,
2473 S4_pstorerht_rr = 2458,
2474 S4_pstorerhtnew_abs = 2459,
2475 S4_pstorerhtnew_io = 2460,
2476 S4_pstorerhtnew_rr = 2461,
2477 S4_pstorerif_abs = 2462,
2478 S4_pstorerif_rr = 2463,
2479 S4_pstorerifnew_abs = 2464,
2480 S4_pstorerifnew_io = 2465,
2481 S4_pstorerifnew_rr = 2466,
2482 S4_pstorerinewf_abs = 2467,
2483 S4_pstorerinewf_rr = 2468,
2484 S4_pstorerinewfnew_abs = 2469,
2485 S4_pstorerinewfnew_io = 2470,
2486 S4_pstorerinewfnew_rr = 2471,
2487 S4_pstorerinewt_abs = 2472,
2488 S4_pstorerinewt_rr = 2473,
2489 S4_pstorerinewtnew_abs = 2474,
2490 S4_pstorerinewtnew_io = 2475,
2491 S4_pstorerinewtnew_rr = 2476,
2492 S4_pstorerit_abs = 2477,
2493 S4_pstorerit_rr = 2478,
2494 S4_pstoreritnew_abs = 2479,
2495 S4_pstoreritnew_io = 2480,
2496 S4_pstoreritnew_rr = 2481,
2497 S4_stored_locked = 2482,
2498 S4_stored_rl_at_vi = 2483,
2499 S4_stored_rl_st_vi = 2484,
2500 S4_storeirb_io = 2485,
2501 S4_storeirbf_io = 2486,
2502 S4_storeirbfnew_io = 2487,
2503 S4_storeirbt_io = 2488,
2504 S4_storeirbtnew_io = 2489,
2505 S4_storeirh_io = 2490,
2506 S4_storeirhf_io = 2491,
2507 S4_storeirhfnew_io = 2492,
2508 S4_storeirht_io = 2493,
2509 S4_storeirhtnew_io = 2494,
2510 S4_storeiri_io = 2495,
2511 S4_storeirif_io = 2496,
2512 S4_storeirifnew_io = 2497,
2513 S4_storeirit_io = 2498,
2514 S4_storeiritnew_io = 2499,
2515 S4_storerb_ap = 2500,
2516 S4_storerb_rr = 2501,
2517 S4_storerb_ur = 2502,
2518 S4_storerbnew_ap = 2503,
2519 S4_storerbnew_rr = 2504,
2520 S4_storerbnew_ur = 2505,
2521 S4_storerd_ap = 2506,
2522 S4_storerd_rr = 2507,
2523 S4_storerd_ur = 2508,
2524 S4_storerf_ap = 2509,
2525 S4_storerf_rr = 2510,
2526 S4_storerf_ur = 2511,
2527 S4_storerh_ap = 2512,
2528 S4_storerh_rr = 2513,
2529 S4_storerh_ur = 2514,
2530 S4_storerhnew_ap = 2515,
2531 S4_storerhnew_rr = 2516,
2532 S4_storerhnew_ur = 2517,
2533 S4_storeri_ap = 2518,
2534 S4_storeri_rr = 2519,
2535 S4_storeri_ur = 2520,
2536 S4_storerinew_ap = 2521,
2537 S4_storerinew_rr = 2522,
2538 S4_storerinew_ur = 2523,
2539 S4_subaddi = 2524,
2540 S4_subi_asl_ri = 2525,
2541 S4_subi_lsr_ri = 2526,
2542 S4_vrcrotate = 2527,
2543 S4_vrcrotate_acc = 2528,
2544 S4_vxaddsubh = 2529,
2545 S4_vxaddsubhr = 2530,
2546 S4_vxaddsubw = 2531,
2547 S4_vxsubaddh = 2532,
2548 S4_vxsubaddhr = 2533,
2549 S4_vxsubaddw = 2534,
2550 S5_asrhub_rnd_sat = 2535,
2551 S5_asrhub_sat = 2536,
2552 S5_popcountp = 2537,
2553 S5_vasrhrnd = 2538,
2554 S6_rol_i_p = 2539,
2555 S6_rol_i_p_acc = 2540,
2556 S6_rol_i_p_and = 2541,
2557 S6_rol_i_p_nac = 2542,
2558 S6_rol_i_p_or = 2543,
2559 S6_rol_i_p_xacc = 2544,
2560 S6_rol_i_r = 2545,
2561 S6_rol_i_r_acc = 2546,
2562 S6_rol_i_r_and = 2547,
2563 S6_rol_i_r_nac = 2548,
2564 S6_rol_i_r_or = 2549,
2565 S6_rol_i_r_xacc = 2550,
2566 S6_vsplatrbp = 2551,
2567 S6_vtrunehb_ppp = 2552,
2568 S6_vtrunohb_ppp = 2553,
2569 SA1_addi = 2554,
2570 SA1_addrx = 2555,
2571 SA1_addsp = 2556,
2572 SA1_and1 = 2557,
2573 SA1_clrf = 2558,
2574 SA1_clrfnew = 2559,
2575 SA1_clrt = 2560,
2576 SA1_clrtnew = 2561,
2577 SA1_cmpeqi = 2562,
2578 SA1_combine0i = 2563,
2579 SA1_combine1i = 2564,
2580 SA1_combine2i = 2565,
2581 SA1_combine3i = 2566,
2582 SA1_combinerz = 2567,
2583 SA1_combinezr = 2568,
2584 SA1_dec = 2569,
2585 SA1_inc = 2570,
2586 SA1_seti = 2571,
2587 SA1_setin1 = 2572,
2588 SA1_sxtb = 2573,
2589 SA1_sxth = 2574,
2590 SA1_tfr = 2575,
2591 SA1_zxtb = 2576,
2592 SA1_zxth = 2577,
2593 SAVE_REGISTERS_CALL_V4 = 2578,
2594 SAVE_REGISTERS_CALL_V4STK = 2579,
2595 SAVE_REGISTERS_CALL_V4STK_EXT = 2580,
2596 SAVE_REGISTERS_CALL_V4STK_EXT_PIC = 2581,
2597 SAVE_REGISTERS_CALL_V4STK_PIC = 2582,
2598 SAVE_REGISTERS_CALL_V4_EXT = 2583,
2599 SAVE_REGISTERS_CALL_V4_EXT_PIC = 2584,
2600 SAVE_REGISTERS_CALL_V4_PIC = 2585,
2601 SL1_loadri_io = 2586,
2602 SL1_loadrub_io = 2587,
2603 SL2_deallocframe = 2588,
2604 SL2_jumpr31 = 2589,
2605 SL2_jumpr31_f = 2590,
2606 SL2_jumpr31_fnew = 2591,
2607 SL2_jumpr31_t = 2592,
2608 SL2_jumpr31_tnew = 2593,
2609 SL2_loadrb_io = 2594,
2610 SL2_loadrd_sp = 2595,
2611 SL2_loadrh_io = 2596,
2612 SL2_loadri_sp = 2597,
2613 SL2_loadruh_io = 2598,
2614 SL2_return = 2599,
2615 SL2_return_f = 2600,
2616 SL2_return_fnew = 2601,
2617 SL2_return_t = 2602,
2618 SL2_return_tnew = 2603,
2619 SS1_storeb_io = 2604,
2620 SS1_storew_io = 2605,
2621 SS2_allocframe = 2606,
2622 SS2_storebi0 = 2607,
2623 SS2_storebi1 = 2608,
2624 SS2_stored_sp = 2609,
2625 SS2_storeh_io = 2610,
2626 SS2_storew_sp = 2611,
2627 SS2_storewi0 = 2612,
2628 SS2_storewi1 = 2613,
2629 TFRI64_V2_ext = 2614,
2630 TFRI64_V4 = 2615,
2631 V6_extractw = 2616,
2632 V6_lvsplatb = 2617,
2633 V6_lvsplath = 2618,
2634 V6_lvsplatw = 2619,
2635 V6_pred_and = 2620,
2636 V6_pred_and_n = 2621,
2637 V6_pred_not = 2622,
2638 V6_pred_or = 2623,
2639 V6_pred_or_n = 2624,
2640 V6_pred_scalar2 = 2625,
2641 V6_pred_scalar2v2 = 2626,
2642 V6_pred_xor = 2627,
2643 V6_shuffeqh = 2628,
2644 V6_shuffeqw = 2629,
2645 V6_v6mpyhubs10 = 2630,
2646 V6_v6mpyhubs10_vxx = 2631,
2647 V6_v6mpyvubs10 = 2632,
2648 V6_v6mpyvubs10_vxx = 2633,
2649 V6_vL32Ub_ai = 2634,
2650 V6_vL32Ub_pi = 2635,
2651 V6_vL32Ub_ppu = 2636,
2652 V6_vL32b_ai = 2637,
2653 V6_vL32b_cur_ai = 2638,
2654 V6_vL32b_cur_npred_ai = 2639,
2655 V6_vL32b_cur_npred_pi = 2640,
2656 V6_vL32b_cur_npred_ppu = 2641,
2657 V6_vL32b_cur_pi = 2642,
2658 V6_vL32b_cur_ppu = 2643,
2659 V6_vL32b_cur_pred_ai = 2644,
2660 V6_vL32b_cur_pred_pi = 2645,
2661 V6_vL32b_cur_pred_ppu = 2646,
2662 V6_vL32b_npred_ai = 2647,
2663 V6_vL32b_npred_pi = 2648,
2664 V6_vL32b_npred_ppu = 2649,
2665 V6_vL32b_nt_ai = 2650,
2666 V6_vL32b_nt_cur_ai = 2651,
2667 V6_vL32b_nt_cur_npred_ai = 2652,
2668 V6_vL32b_nt_cur_npred_pi = 2653,
2669 V6_vL32b_nt_cur_npred_ppu = 2654,
2670 V6_vL32b_nt_cur_pi = 2655,
2671 V6_vL32b_nt_cur_ppu = 2656,
2672 V6_vL32b_nt_cur_pred_ai = 2657,
2673 V6_vL32b_nt_cur_pred_pi = 2658,
2674 V6_vL32b_nt_cur_pred_ppu = 2659,
2675 V6_vL32b_nt_npred_ai = 2660,
2676 V6_vL32b_nt_npred_pi = 2661,
2677 V6_vL32b_nt_npred_ppu = 2662,
2678 V6_vL32b_nt_pi = 2663,
2679 V6_vL32b_nt_ppu = 2664,
2680 V6_vL32b_nt_pred_ai = 2665,
2681 V6_vL32b_nt_pred_pi = 2666,
2682 V6_vL32b_nt_pred_ppu = 2667,
2683 V6_vL32b_nt_tmp_ai = 2668,
2684 V6_vL32b_nt_tmp_npred_ai = 2669,
2685 V6_vL32b_nt_tmp_npred_pi = 2670,
2686 V6_vL32b_nt_tmp_npred_ppu = 2671,
2687 V6_vL32b_nt_tmp_pi = 2672,
2688 V6_vL32b_nt_tmp_ppu = 2673,
2689 V6_vL32b_nt_tmp_pred_ai = 2674,
2690 V6_vL32b_nt_tmp_pred_pi = 2675,
2691 V6_vL32b_nt_tmp_pred_ppu = 2676,
2692 V6_vL32b_pi = 2677,
2693 V6_vL32b_ppu = 2678,
2694 V6_vL32b_pred_ai = 2679,
2695 V6_vL32b_pred_pi = 2680,
2696 V6_vL32b_pred_ppu = 2681,
2697 V6_vL32b_tmp_ai = 2682,
2698 V6_vL32b_tmp_npred_ai = 2683,
2699 V6_vL32b_tmp_npred_pi = 2684,
2700 V6_vL32b_tmp_npred_ppu = 2685,
2701 V6_vL32b_tmp_pi = 2686,
2702 V6_vL32b_tmp_ppu = 2687,
2703 V6_vL32b_tmp_pred_ai = 2688,
2704 V6_vL32b_tmp_pred_pi = 2689,
2705 V6_vL32b_tmp_pred_ppu = 2690,
2706 V6_vS32Ub_ai = 2691,
2707 V6_vS32Ub_npred_ai = 2692,
2708 V6_vS32Ub_npred_pi = 2693,
2709 V6_vS32Ub_npred_ppu = 2694,
2710 V6_vS32Ub_pi = 2695,
2711 V6_vS32Ub_ppu = 2696,
2712 V6_vS32Ub_pred_ai = 2697,
2713 V6_vS32Ub_pred_pi = 2698,
2714 V6_vS32Ub_pred_ppu = 2699,
2715 V6_vS32b_ai = 2700,
2716 V6_vS32b_new_ai = 2701,
2717 V6_vS32b_new_npred_ai = 2702,
2718 V6_vS32b_new_npred_pi = 2703,
2719 V6_vS32b_new_npred_ppu = 2704,
2720 V6_vS32b_new_pi = 2705,
2721 V6_vS32b_new_ppu = 2706,
2722 V6_vS32b_new_pred_ai = 2707,
2723 V6_vS32b_new_pred_pi = 2708,
2724 V6_vS32b_new_pred_ppu = 2709,
2725 V6_vS32b_npred_ai = 2710,
2726 V6_vS32b_npred_pi = 2711,
2727 V6_vS32b_npred_ppu = 2712,
2728 V6_vS32b_nqpred_ai = 2713,
2729 V6_vS32b_nqpred_pi = 2714,
2730 V6_vS32b_nqpred_ppu = 2715,
2731 V6_vS32b_nt_ai = 2716,
2732 V6_vS32b_nt_new_ai = 2717,
2733 V6_vS32b_nt_new_npred_ai = 2718,
2734 V6_vS32b_nt_new_npred_pi = 2719,
2735 V6_vS32b_nt_new_npred_ppu = 2720,
2736 V6_vS32b_nt_new_pi = 2721,
2737 V6_vS32b_nt_new_ppu = 2722,
2738 V6_vS32b_nt_new_pred_ai = 2723,
2739 V6_vS32b_nt_new_pred_pi = 2724,
2740 V6_vS32b_nt_new_pred_ppu = 2725,
2741 V6_vS32b_nt_npred_ai = 2726,
2742 V6_vS32b_nt_npred_pi = 2727,
2743 V6_vS32b_nt_npred_ppu = 2728,
2744 V6_vS32b_nt_nqpred_ai = 2729,
2745 V6_vS32b_nt_nqpred_pi = 2730,
2746 V6_vS32b_nt_nqpred_ppu = 2731,
2747 V6_vS32b_nt_pi = 2732,
2748 V6_vS32b_nt_ppu = 2733,
2749 V6_vS32b_nt_pred_ai = 2734,
2750 V6_vS32b_nt_pred_pi = 2735,
2751 V6_vS32b_nt_pred_ppu = 2736,
2752 V6_vS32b_nt_qpred_ai = 2737,
2753 V6_vS32b_nt_qpred_pi = 2738,
2754 V6_vS32b_nt_qpred_ppu = 2739,
2755 V6_vS32b_pi = 2740,
2756 V6_vS32b_ppu = 2741,
2757 V6_vS32b_pred_ai = 2742,
2758 V6_vS32b_pred_pi = 2743,
2759 V6_vS32b_pred_ppu = 2744,
2760 V6_vS32b_qpred_ai = 2745,
2761 V6_vS32b_qpred_pi = 2746,
2762 V6_vS32b_qpred_ppu = 2747,
2763 V6_vS32b_srls_ai = 2748,
2764 V6_vS32b_srls_pi = 2749,
2765 V6_vS32b_srls_ppu = 2750,
2766 V6_vabs_hf = 2751,
2767 V6_vabs_sf = 2752,
2768 V6_vabsb = 2753,
2769 V6_vabsb_sat = 2754,
2770 V6_vabsdiffh = 2755,
2771 V6_vabsdiffub = 2756,
2772 V6_vabsdiffuh = 2757,
2773 V6_vabsdiffw = 2758,
2774 V6_vabsh = 2759,
2775 V6_vabsh_sat = 2760,
2776 V6_vabsw = 2761,
2777 V6_vabsw_sat = 2762,
2778 V6_vadd_hf = 2763,
2779 V6_vadd_hf_hf = 2764,
2780 V6_vadd_qf16 = 2765,
2781 V6_vadd_qf16_mix = 2766,
2782 V6_vadd_qf32 = 2767,
2783 V6_vadd_qf32_mix = 2768,
2784 V6_vadd_sf = 2769,
2785 V6_vadd_sf_bf = 2770,
2786 V6_vadd_sf_hf = 2771,
2787 V6_vadd_sf_sf = 2772,
2788 V6_vaddb = 2773,
2789 V6_vaddb_dv = 2774,
2790 V6_vaddbnq = 2775,
2791 V6_vaddbq = 2776,
2792 V6_vaddbsat = 2777,
2793 V6_vaddbsat_dv = 2778,
2794 V6_vaddcarry = 2779,
2795 V6_vaddcarryo = 2780,
2796 V6_vaddcarrysat = 2781,
2797 V6_vaddclbh = 2782,
2798 V6_vaddclbw = 2783,
2799 V6_vaddh = 2784,
2800 V6_vaddh_dv = 2785,
2801 V6_vaddhnq = 2786,
2802 V6_vaddhq = 2787,
2803 V6_vaddhsat = 2788,
2804 V6_vaddhsat_dv = 2789,
2805 V6_vaddhw = 2790,
2806 V6_vaddhw_acc = 2791,
2807 V6_vaddubh = 2792,
2808 V6_vaddubh_acc = 2793,
2809 V6_vaddubsat = 2794,
2810 V6_vaddubsat_dv = 2795,
2811 V6_vaddububb_sat = 2796,
2812 V6_vadduhsat = 2797,
2813 V6_vadduhsat_dv = 2798,
2814 V6_vadduhw = 2799,
2815 V6_vadduhw_acc = 2800,
2816 V6_vadduwsat = 2801,
2817 V6_vadduwsat_dv = 2802,
2818 V6_vaddw = 2803,
2819 V6_vaddw_dv = 2804,
2820 V6_vaddwnq = 2805,
2821 V6_vaddwq = 2806,
2822 V6_vaddwsat = 2807,
2823 V6_vaddwsat_dv = 2808,
2824 V6_valignb = 2809,
2825 V6_valignbi = 2810,
2826 V6_vand = 2811,
2827 V6_vandnqrt = 2812,
2828 V6_vandnqrt_acc = 2813,
2829 V6_vandqrt = 2814,
2830 V6_vandqrt_acc = 2815,
2831 V6_vandvnqv = 2816,
2832 V6_vandvqv = 2817,
2833 V6_vandvrt = 2818,
2834 V6_vandvrt_acc = 2819,
2835 V6_vaslh = 2820,
2836 V6_vaslh_acc = 2821,
2837 V6_vaslhv = 2822,
2838 V6_vaslw = 2823,
2839 V6_vaslw_acc = 2824,
2840 V6_vaslwv = 2825,
2841 V6_vasr_into = 2826,
2842 V6_vasrh = 2827,
2843 V6_vasrh_acc = 2828,
2844 V6_vasrhbrndsat = 2829,
2845 V6_vasrhbsat = 2830,
2846 V6_vasrhubrndsat = 2831,
2847 V6_vasrhubsat = 2832,
2848 V6_vasrhv = 2833,
2849 V6_vasruhubrndsat = 2834,
2850 V6_vasruhubsat = 2835,
2851 V6_vasruwuhrndsat = 2836,
2852 V6_vasruwuhsat = 2837,
2853 V6_vasrvuhubrndsat = 2838,
2854 V6_vasrvuhubsat = 2839,
2855 V6_vasrvwuhrndsat = 2840,
2856 V6_vasrvwuhsat = 2841,
2857 V6_vasrw = 2842,
2858 V6_vasrw_acc = 2843,
2859 V6_vasrwh = 2844,
2860 V6_vasrwhrndsat = 2845,
2861 V6_vasrwhsat = 2846,
2862 V6_vasrwuhrndsat = 2847,
2863 V6_vasrwuhsat = 2848,
2864 V6_vasrwv = 2849,
2865 V6_vassign = 2850,
2866 V6_vassign_fp = 2851,
2867 V6_vassign_tmp = 2852,
2868 V6_vavgb = 2853,
2869 V6_vavgbrnd = 2854,
2870 V6_vavgh = 2855,
2871 V6_vavghrnd = 2856,
2872 V6_vavgub = 2857,
2873 V6_vavgubrnd = 2858,
2874 V6_vavguh = 2859,
2875 V6_vavguhrnd = 2860,
2876 V6_vavguw = 2861,
2877 V6_vavguwrnd = 2862,
2878 V6_vavgw = 2863,
2879 V6_vavgwrnd = 2864,
2880 V6_vccombine = 2865,
2881 V6_vcl0h = 2866,
2882 V6_vcl0w = 2867,
2883 V6_vcmov = 2868,
2884 V6_vcombine = 2869,
2885 V6_vcombine_tmp = 2870,
2886 V6_vconv_h_hf = 2871,
2887 V6_vconv_hf_h = 2872,
2888 V6_vconv_hf_qf16 = 2873,
2889 V6_vconv_hf_qf32 = 2874,
2890 V6_vconv_sf_qf32 = 2875,
2891 V6_vconv_sf_w = 2876,
2892 V6_vconv_w_sf = 2877,
2893 V6_vcvt_b_hf = 2878,
2894 V6_vcvt_bf_sf = 2879,
2895 V6_vcvt_h_hf = 2880,
2896 V6_vcvt_hf_b = 2881,
2897 V6_vcvt_hf_h = 2882,
2898 V6_vcvt_hf_sf = 2883,
2899 V6_vcvt_hf_ub = 2884,
2900 V6_vcvt_hf_uh = 2885,
2901 V6_vcvt_sf_hf = 2886,
2902 V6_vcvt_ub_hf = 2887,
2903 V6_vcvt_uh_hf = 2888,
2904 V6_vdeal = 2889,
2905 V6_vdealb = 2890,
2906 V6_vdealb4w = 2891,
2907 V6_vdealh = 2892,
2908 V6_vdealvdd = 2893,
2909 V6_vdelta = 2894,
2910 V6_vdmpy_sf_hf = 2895,
2911 V6_vdmpy_sf_hf_acc = 2896,
2912 V6_vdmpybus = 2897,
2913 V6_vdmpybus_acc = 2898,
2914 V6_vdmpybus_dv = 2899,
2915 V6_vdmpybus_dv_acc = 2900,
2916 V6_vdmpyhb = 2901,
2917 V6_vdmpyhb_acc = 2902,
2918 V6_vdmpyhb_dv = 2903,
2919 V6_vdmpyhb_dv_acc = 2904,
2920 V6_vdmpyhisat = 2905,
2921 V6_vdmpyhisat_acc = 2906,
2922 V6_vdmpyhsat = 2907,
2923 V6_vdmpyhsat_acc = 2908,
2924 V6_vdmpyhsuisat = 2909,
2925 V6_vdmpyhsuisat_acc = 2910,
2926 V6_vdmpyhsusat = 2911,
2927 V6_vdmpyhsusat_acc = 2912,
2928 V6_vdmpyhvsat = 2913,
2929 V6_vdmpyhvsat_acc = 2914,
2930 V6_vdsaduh = 2915,
2931 V6_vdsaduh_acc = 2916,
2932 V6_veqb = 2917,
2933 V6_veqb_and = 2918,
2934 V6_veqb_or = 2919,
2935 V6_veqb_xor = 2920,
2936 V6_veqh = 2921,
2937 V6_veqh_and = 2922,
2938 V6_veqh_or = 2923,
2939 V6_veqh_xor = 2924,
2940 V6_veqw = 2925,
2941 V6_veqw_and = 2926,
2942 V6_veqw_or = 2927,
2943 V6_veqw_xor = 2928,
2944 V6_vfmax_hf = 2929,
2945 V6_vfmax_sf = 2930,
2946 V6_vfmin_hf = 2931,
2947 V6_vfmin_sf = 2932,
2948 V6_vfneg_hf = 2933,
2949 V6_vfneg_sf = 2934,
2950 V6_vgathermh = 2935,
2951 V6_vgathermhq = 2936,
2952 V6_vgathermhw = 2937,
2953 V6_vgathermhwq = 2938,
2954 V6_vgathermw = 2939,
2955 V6_vgathermwq = 2940,
2956 V6_vgtb = 2941,
2957 V6_vgtb_and = 2942,
2958 V6_vgtb_or = 2943,
2959 V6_vgtb_xor = 2944,
2960 V6_vgtbf = 2945,
2961 V6_vgtbf_and = 2946,
2962 V6_vgtbf_or = 2947,
2963 V6_vgtbf_xor = 2948,
2964 V6_vgth = 2949,
2965 V6_vgth_and = 2950,
2966 V6_vgth_or = 2951,
2967 V6_vgth_xor = 2952,
2968 V6_vgthf = 2953,
2969 V6_vgthf_and = 2954,
2970 V6_vgthf_or = 2955,
2971 V6_vgthf_xor = 2956,
2972 V6_vgtsf = 2957,
2973 V6_vgtsf_and = 2958,
2974 V6_vgtsf_or = 2959,
2975 V6_vgtsf_xor = 2960,
2976 V6_vgtub = 2961,
2977 V6_vgtub_and = 2962,
2978 V6_vgtub_or = 2963,
2979 V6_vgtub_xor = 2964,
2980 V6_vgtuh = 2965,
2981 V6_vgtuh_and = 2966,
2982 V6_vgtuh_or = 2967,
2983 V6_vgtuh_xor = 2968,
2984 V6_vgtuw = 2969,
2985 V6_vgtuw_and = 2970,
2986 V6_vgtuw_or = 2971,
2987 V6_vgtuw_xor = 2972,
2988 V6_vgtw = 2973,
2989 V6_vgtw_and = 2974,
2990 V6_vgtw_or = 2975,
2991 V6_vgtw_xor = 2976,
2992 V6_vhist = 2977,
2993 V6_vhistq = 2978,
2994 V6_vinsertwr = 2979,
2995 V6_vlalignb = 2980,
2996 V6_vlalignbi = 2981,
2997 V6_vlsrb = 2982,
2998 V6_vlsrh = 2983,
2999 V6_vlsrhv = 2984,
3000 V6_vlsrw = 2985,
3001 V6_vlsrwv = 2986,
3002 V6_vlut4 = 2987,
3003 V6_vlutvvb = 2988,
3004 V6_vlutvvb_nm = 2989,
3005 V6_vlutvvb_oracc = 2990,
3006 V6_vlutvvb_oracci = 2991,
3007 V6_vlutvvbi = 2992,
3008 V6_vlutvwh = 2993,
3009 V6_vlutvwh_nm = 2994,
3010 V6_vlutvwh_oracc = 2995,
3011 V6_vlutvwh_oracci = 2996,
3012 V6_vlutvwhi = 2997,
3013 V6_vmax_bf = 2998,
3014 V6_vmax_hf = 2999,
3015 V6_vmax_sf = 3000,
3016 V6_vmaxb = 3001,
3017 V6_vmaxh = 3002,
3018 V6_vmaxub = 3003,
3019 V6_vmaxuh = 3004,
3020 V6_vmaxw = 3005,
3021 V6_vmin_bf = 3006,
3022 V6_vmin_hf = 3007,
3023 V6_vmin_sf = 3008,
3024 V6_vminb = 3009,
3025 V6_vminh = 3010,
3026 V6_vminub = 3011,
3027 V6_vminuh = 3012,
3028 V6_vminw = 3013,
3029 V6_vmpabus = 3014,
3030 V6_vmpabus_acc = 3015,
3031 V6_vmpabusv = 3016,
3032 V6_vmpabuu = 3017,
3033 V6_vmpabuu_acc = 3018,
3034 V6_vmpabuuv = 3019,
3035 V6_vmpahb = 3020,
3036 V6_vmpahb_acc = 3021,
3037 V6_vmpahhsat = 3022,
3038 V6_vmpauhb = 3023,
3039 V6_vmpauhb_acc = 3024,
3040 V6_vmpauhuhsat = 3025,
3041 V6_vmpsuhuhsat = 3026,
3042 V6_vmpy_hf_hf = 3027,
3043 V6_vmpy_hf_hf_acc = 3028,
3044 V6_vmpy_qf16 = 3029,
3045 V6_vmpy_qf16_hf = 3030,
3046 V6_vmpy_qf16_mix_hf = 3031,
3047 V6_vmpy_qf32 = 3032,
3048 V6_vmpy_qf32_hf = 3033,
3049 V6_vmpy_qf32_mix_hf = 3034,
3050 V6_vmpy_qf32_qf16 = 3035,
3051 V6_vmpy_qf32_sf = 3036,
3052 V6_vmpy_sf_bf = 3037,
3053 V6_vmpy_sf_bf_acc = 3038,
3054 V6_vmpy_sf_hf = 3039,
3055 V6_vmpy_sf_hf_acc = 3040,
3056 V6_vmpy_sf_sf = 3041,
3057 V6_vmpybus = 3042,
3058 V6_vmpybus_acc = 3043,
3059 V6_vmpybusv = 3044,
3060 V6_vmpybusv_acc = 3045,
3061 V6_vmpybv = 3046,
3062 V6_vmpybv_acc = 3047,
3063 V6_vmpyewuh = 3048,
3064 V6_vmpyewuh_64 = 3049,
3065 V6_vmpyh = 3050,
3066 V6_vmpyh_acc = 3051,
3067 V6_vmpyhsat_acc = 3052,
3068 V6_vmpyhsrs = 3053,
3069 V6_vmpyhss = 3054,
3070 V6_vmpyhus = 3055,
3071 V6_vmpyhus_acc = 3056,
3072 V6_vmpyhv = 3057,
3073 V6_vmpyhv_acc = 3058,
3074 V6_vmpyhvsrs = 3059,
3075 V6_vmpyieoh = 3060,
3076 V6_vmpyiewh_acc = 3061,
3077 V6_vmpyiewuh = 3062,
3078 V6_vmpyiewuh_acc = 3063,
3079 V6_vmpyih = 3064,
3080 V6_vmpyih_acc = 3065,
3081 V6_vmpyihb = 3066,
3082 V6_vmpyihb_acc = 3067,
3083 V6_vmpyiowh = 3068,
3084 V6_vmpyiwb = 3069,
3085 V6_vmpyiwb_acc = 3070,
3086 V6_vmpyiwh = 3071,
3087 V6_vmpyiwh_acc = 3072,
3088 V6_vmpyiwub = 3073,
3089 V6_vmpyiwub_acc = 3074,
3090 V6_vmpyowh = 3075,
3091 V6_vmpyowh_64_acc = 3076,
3092 V6_vmpyowh_rnd = 3077,
3093 V6_vmpyowh_rnd_sacc = 3078,
3094 V6_vmpyowh_sacc = 3079,
3095 V6_vmpyub = 3080,
3096 V6_vmpyub_acc = 3081,
3097 V6_vmpyubv = 3082,
3098 V6_vmpyubv_acc = 3083,
3099 V6_vmpyuh = 3084,
3100 V6_vmpyuh_acc = 3085,
3101 V6_vmpyuhe = 3086,
3102 V6_vmpyuhe_acc = 3087,
3103 V6_vmpyuhv = 3088,
3104 V6_vmpyuhv_acc = 3089,
3105 V6_vmpyuhvs = 3090,
3106 V6_vmux = 3091,
3107 V6_vnavgb = 3092,
3108 V6_vnavgh = 3093,
3109 V6_vnavgub = 3094,
3110 V6_vnavgw = 3095,
3111 V6_vnccombine = 3096,
3112 V6_vncmov = 3097,
3113 V6_vnormamth = 3098,
3114 V6_vnormamtw = 3099,
3115 V6_vnot = 3100,
3116 V6_vor = 3101,
3117 V6_vpackeb = 3102,
3118 V6_vpackeh = 3103,
3119 V6_vpackhb_sat = 3104,
3120 V6_vpackhub_sat = 3105,
3121 V6_vpackob = 3106,
3122 V6_vpackoh = 3107,
3123 V6_vpackwh_sat = 3108,
3124 V6_vpackwuh_sat = 3109,
3125 V6_vpopcounth = 3110,
3126 V6_vprefixqb = 3111,
3127 V6_vprefixqh = 3112,
3128 V6_vprefixqw = 3113,
3129 V6_vrdelta = 3114,
3130 V6_vrmpybub_rtt = 3115,
3131 V6_vrmpybub_rtt_acc = 3116,
3132 V6_vrmpybus = 3117,
3133 V6_vrmpybus_acc = 3118,
3134 V6_vrmpybusi = 3119,
3135 V6_vrmpybusi_acc = 3120,
3136 V6_vrmpybusv = 3121,
3137 V6_vrmpybusv_acc = 3122,
3138 V6_vrmpybv = 3123,
3139 V6_vrmpybv_acc = 3124,
3140 V6_vrmpyub = 3125,
3141 V6_vrmpyub_acc = 3126,
3142 V6_vrmpyub_rtt = 3127,
3143 V6_vrmpyub_rtt_acc = 3128,
3144 V6_vrmpyubi = 3129,
3145 V6_vrmpyubi_acc = 3130,
3146 V6_vrmpyubv = 3131,
3147 V6_vrmpyubv_acc = 3132,
3148 V6_vrmpyzbb_rt = 3133,
3149 V6_vrmpyzbb_rt_acc = 3134,
3150 V6_vrmpyzbb_rx = 3135,
3151 V6_vrmpyzbb_rx_acc = 3136,
3152 V6_vrmpyzbub_rt = 3137,
3153 V6_vrmpyzbub_rt_acc = 3138,
3154 V6_vrmpyzbub_rx = 3139,
3155 V6_vrmpyzbub_rx_acc = 3140,
3156 V6_vrmpyzcb_rt = 3141,
3157 V6_vrmpyzcb_rt_acc = 3142,
3158 V6_vrmpyzcb_rx = 3143,
3159 V6_vrmpyzcb_rx_acc = 3144,
3160 V6_vrmpyzcbs_rt = 3145,
3161 V6_vrmpyzcbs_rt_acc = 3146,
3162 V6_vrmpyzcbs_rx = 3147,
3163 V6_vrmpyzcbs_rx_acc = 3148,
3164 V6_vrmpyznb_rt = 3149,
3165 V6_vrmpyznb_rt_acc = 3150,
3166 V6_vrmpyznb_rx = 3151,
3167 V6_vrmpyznb_rx_acc = 3152,
3168 V6_vror = 3153,
3169 V6_vrotr = 3154,
3170 V6_vroundhb = 3155,
3171 V6_vroundhub = 3156,
3172 V6_vrounduhub = 3157,
3173 V6_vrounduwuh = 3158,
3174 V6_vroundwh = 3159,
3175 V6_vroundwuh = 3160,
3176 V6_vrsadubi = 3161,
3177 V6_vrsadubi_acc = 3162,
3178 V6_vsatdw = 3163,
3179 V6_vsathub = 3164,
3180 V6_vsatuwuh = 3165,
3181 V6_vsatwh = 3166,
3182 V6_vsb = 3167,
3183 V6_vscattermh = 3168,
3184 V6_vscattermh_add = 3169,
3185 V6_vscattermhq = 3170,
3186 V6_vscattermhw = 3171,
3187 V6_vscattermhw_add = 3172,
3188 V6_vscattermhwq = 3173,
3189 V6_vscattermw = 3174,
3190 V6_vscattermw_add = 3175,
3191 V6_vscattermwq = 3176,
3192 V6_vsh = 3177,
3193 V6_vshufeh = 3178,
3194 V6_vshuff = 3179,
3195 V6_vshuffb = 3180,
3196 V6_vshuffeb = 3181,
3197 V6_vshuffh = 3182,
3198 V6_vshuffob = 3183,
3199 V6_vshuffvdd = 3184,
3200 V6_vshufoeb = 3185,
3201 V6_vshufoeh = 3186,
3202 V6_vshufoh = 3187,
3203 V6_vsub_hf = 3188,
3204 V6_vsub_hf_hf = 3189,
3205 V6_vsub_qf16 = 3190,
3206 V6_vsub_qf16_mix = 3191,
3207 V6_vsub_qf32 = 3192,
3208 V6_vsub_qf32_mix = 3193,
3209 V6_vsub_sf = 3194,
3210 V6_vsub_sf_bf = 3195,
3211 V6_vsub_sf_hf = 3196,
3212 V6_vsub_sf_sf = 3197,
3213 V6_vsubb = 3198,
3214 V6_vsubb_dv = 3199,
3215 V6_vsubbnq = 3200,
3216 V6_vsubbq = 3201,
3217 V6_vsubbsat = 3202,
3218 V6_vsubbsat_dv = 3203,
3219 V6_vsubcarry = 3204,
3220 V6_vsubcarryo = 3205,
3221 V6_vsubh = 3206,
3222 V6_vsubh_dv = 3207,
3223 V6_vsubhnq = 3208,
3224 V6_vsubhq = 3209,
3225 V6_vsubhsat = 3210,
3226 V6_vsubhsat_dv = 3211,
3227 V6_vsubhw = 3212,
3228 V6_vsububh = 3213,
3229 V6_vsububsat = 3214,
3230 V6_vsububsat_dv = 3215,
3231 V6_vsubububb_sat = 3216,
3232 V6_vsubuhsat = 3217,
3233 V6_vsubuhsat_dv = 3218,
3234 V6_vsubuhw = 3219,
3235 V6_vsubuwsat = 3220,
3236 V6_vsubuwsat_dv = 3221,
3237 V6_vsubw = 3222,
3238 V6_vsubw_dv = 3223,
3239 V6_vsubwnq = 3224,
3240 V6_vsubwq = 3225,
3241 V6_vsubwsat = 3226,
3242 V6_vsubwsat_dv = 3227,
3243 V6_vswap = 3228,
3244 V6_vtmpyb = 3229,
3245 V6_vtmpyb_acc = 3230,
3246 V6_vtmpybus = 3231,
3247 V6_vtmpybus_acc = 3232,
3248 V6_vtmpyhb = 3233,
3249 V6_vtmpyhb_acc = 3234,
3250 V6_vunpackb = 3235,
3251 V6_vunpackh = 3236,
3252 V6_vunpackob = 3237,
3253 V6_vunpackoh = 3238,
3254 V6_vunpackub = 3239,
3255 V6_vunpackuh = 3240,
3256 V6_vwhist128 = 3241,
3257 V6_vwhist128m = 3242,
3258 V6_vwhist128q = 3243,
3259 V6_vwhist128qm = 3244,
3260 V6_vwhist256 = 3245,
3261 V6_vwhist256_sat = 3246,
3262 V6_vwhist256q = 3247,
3263 V6_vwhist256q_sat = 3248,
3264 V6_vxor = 3249,
3265 V6_vzb = 3250,
3266 V6_vzh = 3251,
3267 V6_zLd_ai = 3252,
3268 V6_zLd_pi = 3253,
3269 V6_zLd_ppu = 3254,
3270 V6_zLd_pred_ai = 3255,
3271 V6_zLd_pred_pi = 3256,
3272 V6_zLd_pred_ppu = 3257,
3273 V6_zextract = 3258,
3274 Y2_barrier = 3259,
3275 Y2_break = 3260,
3276 Y2_ciad = 3261,
3277 Y2_crswap0 = 3262,
3278 Y2_cswi = 3263,
3279 Y2_dccleana = 3264,
3280 Y2_dccleanidx = 3265,
3281 Y2_dccleaninva = 3266,
3282 Y2_dccleaninvidx = 3267,
3283 Y2_dcfetchbo = 3268,
3284 Y2_dcinva = 3269,
3285 Y2_dcinvidx = 3270,
3286 Y2_dckill = 3271,
3287 Y2_dctagr = 3272,
3288 Y2_dctagw = 3273,
3289 Y2_dczeroa = 3274,
3290 Y2_getimask = 3275,
3291 Y2_iassignr = 3276,
3292 Y2_iassignw = 3277,
3293 Y2_icdatar = 3278,
3294 Y2_icdataw = 3279,
3295 Y2_icinva = 3280,
3296 Y2_icinvidx = 3281,
3297 Y2_ickill = 3282,
3298 Y2_ictagr = 3283,
3299 Y2_ictagw = 3284,
3300 Y2_isync = 3285,
3301 Y2_k0lock = 3286,
3302 Y2_k0unlock = 3287,
3303 Y2_l2cleaninvidx = 3288,
3304 Y2_l2kill = 3289,
3305 Y2_resume = 3290,
3306 Y2_setimask = 3291,
3307 Y2_setprio = 3292,
3308 Y2_start = 3293,
3309 Y2_stop = 3294,
3310 Y2_swi = 3295,
3311 Y2_syncht = 3296,
3312 Y2_tfrscrr = 3297,
3313 Y2_tfrsrcr = 3298,
3314 Y2_tlblock = 3299,
3315 Y2_tlbp = 3300,
3316 Y2_tlbr = 3301,
3317 Y2_tlbunlock = 3302,
3318 Y2_tlbw = 3303,
3319 Y2_wait = 3304,
3320 Y4_crswap1 = 3305,
3321 Y4_crswap10 = 3306,
3322 Y4_l2fetch = 3307,
3323 Y4_l2tagr = 3308,
3324 Y4_l2tagw = 3309,
3325 Y4_nmi = 3310,
3326 Y4_siad = 3311,
3327 Y4_tfrscpp = 3312,
3328 Y4_tfrspcp = 3313,
3329 Y4_trace = 3314,
3330 Y5_ctlbw = 3315,
3331 Y5_l2cleanidx = 3316,
3332 Y5_l2fetch = 3317,
3333 Y5_l2gclean = 3318,
3334 Y5_l2gcleaninv = 3319,
3335 Y5_l2gunlock = 3320,
3336 Y5_l2invidx = 3321,
3337 Y5_l2locka = 3322,
3338 Y5_l2unlocka = 3323,
3339 Y5_tlbasidi = 3324,
3340 Y5_tlboc = 3325,
3341 Y6_diag = 3326,
3342 Y6_diag0 = 3327,
3343 Y6_diag1 = 3328,
3344 Y6_dmlink = 3329,
3345 Y6_dmpause = 3330,
3346 Y6_dmpoll = 3331,
3347 Y6_dmresume = 3332,
3348 Y6_dmstart = 3333,
3349 Y6_dmwait = 3334,
3350 Y6_l2gcleaninvpa = 3335,
3351 Y6_l2gcleanpa = 3336,
3352 dep_A2_addsat = 3337,
3353 dep_A2_subsat = 3338,
3354 dep_S2_packhl = 3339,
3355 invalid_decode = 3340,
3356 INSTRUCTION_LIST_END = 3341
3357 };
3358
3359} // end namespace Hexagon
3360} // end namespace llvm
3361#endif // GET_INSTRINFO_ENUM
3362
3363#ifdef GET_INSTRINFO_SCHED_ENUM
3364#undef GET_INSTRINFO_SCHED_ENUM
3365namespace llvm {
3366
3367namespace Hexagon {
3368namespace Sched {
3369 enum {
3370 NoInstrModel = 0,
3371 tc_01d44cb2 = 1,
3372 PSEUDO = 2,
3373 tc_c57d9f39 = 3,
3374 tc_1c2c7a4a = 4,
3375 tc_442395f3 = 5,
3376 tc_713b66bf = 6,
3377 tc_86173609 = 7,
3378 tc_5da50c4b = 8,
3379 tc_4a55d03c = 9,
3380 tc_d33e5eee = 10,
3381 tc_651cbe02 = 11,
3382 DUPLEX = 12,
3383 tc_ENDLOOP = 13,
3384 tc_23708a21 = 14,
3385 tc_56a124a7 = 15,
3386 tc_2f573607 = 16,
3387 tc_53c851ab = 17,
3388 tc_fedb7e19 = 18,
3389 tc_4222e6bf = 19,
3390 tc_075c8dd8 = 20,
3391 tc_9bcfb2ee = 21,
3392 tc_158aa3f7 = 22,
3393 tc_df5d53f9 = 23,
3394 tc_14ab4f41 = 24,
3395 tc_f38f92e1 = 25,
3396 tc_1981450d = 26,
3397 tc_e9170fb7 = 27,
3398 tc_40d64c94 = 28,
3399 LD_tc_ld_SLOT01 = 29,
3400 tc_38382228 = 30,
3401 tc_c21d7447 = 31,
3402 tc_7f8ae742 = 32,
3403 tc_5a4b5e58 = 33,
3404 tc_197dce51 = 34,
3405 tc_44fffc58 = 35,
3406 tc_5ceb2f9e = 36,
3407 tc_56c4f9fe = 37,
3408 tc_b4dc7630 = 38,
3409 tc_a2b365d2 = 39,
3410 tc_60e324ff = 40,
3411 tc_db5555f3 = 41,
3412 tc_c0749f3c = 42,
3413 PSEUDOM = 43,
3414 tc_3aacf4a8 = 44,
3415 tc_c4edf264 = 45,
3416 tc_c5dba46e = 46,
3417 tc_af25efd9 = 47,
3418 tc_0dfac0a7 = 48,
3419 tc_8035e91f = 49,
3420 tc_011e0e9d = 50,
3421 tc_ae5babd7 = 51,
3422 tc_5deb5e47 = 52,
3423 tc_bb831a7c = 53,
3424 tc_92240447 = 54,
3425 tc_7c31e19a = 55,
3426 tc_d03278fd = 56,
3427 tc_65cbd974 = 57,
3428 tc_934753bb = 58,
3429 ST_tc_st_SLOT01 = 59,
3430 CVI_VA = 60,
3431 tc_f175e046 = 61,
3432 tc_4942646a = 62,
3433 tc_0ec46cf9 = 63,
3434 tc_718b5c53 = 64,
3435 CVI_GATHER_PSEUDO = 65,
3436 tc_7dc63b5c = 66,
3437 tc_d45ba9cd = 67,
3438 tc_388f9897 = 68,
3439 tc_9124c04f = 69,
3440 tc_4ac61d92 = 70,
3441 tc_aee6250c = 71,
3442 tc_eed07714 = 72,
3443 tc_74a42bda = 73,
3444 tc_a9edeffa = 74,
3445 tc_838c4d7a = 75,
3446 tc_d61dfdc3 = 76,
3447 tc_8a825db2 = 77,
3448 tc_f34c1c21 = 78,
3449 tc_95a33176 = 79,
3450 tc_9f6cd987 = 80,
3451 tc_b837298f = 81,
3452 tc_8b5bd4f5 = 82,
3453 tc_84a7500d = 83,
3454 tc_7476d766 = 84,
3455 tc_49fdfd4b = 85,
3456 tc_f098b237 = 86,
3457 tc_20131976 = 87,
3458 tc_1d41f8b7 = 88,
3459 tc_a1297125 = 89,
3460 tc_112d30d6 = 90,
3461 tc_d68dca5c = 91,
3462 tc_788b1d09 = 92,
3463 tc_38e0bae9 = 93,
3464 tc_407e96f9 = 94,
3465 tc_7401744f = 95,
3466 tc_9b3c0462 = 96,
3467 tc_151bf368 = 97,
3468 tc_9c52f549 = 98,
3469 tc_55b33fda = 99,
3470 tc_6fc5dbea = 100,
3471 tc_3edca78f = 101,
3472 tc_a7a13fac = 102,
3473 tc_9783714b = 103,
3474 tc_f0e8e832 = 104,
3475 tc_65279839 = 105,
3476 tc_0a195f2c = 106,
3477 tc_01e1be3b = 107,
3478 tc_556f6577 = 108,
3479 tc_02fe1c65 = 109,
3480 tc_9e72dc89 = 110,
3481 tc_9edb7c77 = 111,
3482 tc_7f7f45f5 = 112,
3483 tc_c20701f0 = 113,
3484 tc_f7569068 = 114,
3485 tc_fae9dfa5 = 115,
3486 tc_6ae3426b = 116,
3487 tc_69bfb303 = 117,
3488 tc_362b0be2 = 118,
3489 tc_dc51281d = 119,
3490 tc_95f43c5e = 120,
3491 tc_decdde8a = 121,
3492 tc_eeda4109 = 122,
3493 tc_711c805f = 123,
3494 tc_ed03645c = 124,
3495 tc_42ff66ba = 125,
3496 tc_57a55b54 = 126,
3497 tc_f97707c1 = 127,
3498 tc_1248597c = 128,
3499 tc_9406230a = 129,
3500 tc_d57d649c = 130,
3501 tc_4abdbdc6 = 131,
3502 tc_6d861a95 = 132,
3503 tc_b9bec29e = 133,
3504 tc_45f9d1be = 134,
3505 tc_33e7e673 = 135,
3506 tc_24e109c7 = 136,
3507 tc_9e27f2f9 = 137,
3508 tc_f6e2aff9 = 138,
3509 tc_24f426ab = 139,
3510 tc_975a4e54 = 140,
3511 tc_e60def48 = 141,
3512 tc_5502c366 = 142,
3513 tc_7b9187d3 = 143,
3514 tc_f999c66e = 144,
3515 tc_1c7522a8 = 145,
3516 tc_76bb5435 = 146,
3517 tc_8a6d0d94 = 147,
3518 tc_2471c1c8 = 148,
3519 tc_64b00d8a = 149,
3520 tc_5f2afaf7 = 150,
3521 tc_ac65613f = 151,
3522 tc_a32e03e7 = 152,
3523 tc_822c3c68 = 153,
3524 tc_abfd9a6d = 154,
3525 tc_bf2ffc0f = 155,
3526 tc_ed3f8d2a = 156,
3527 tc_7c6d32e4 = 157,
3528 tc_45791fb8 = 158,
3529 tc_b7c4062a = 159,
3530 tc_5944960d = 160,
3531 tc_2c13e7f5 = 161,
3532 tc_a154b476 = 162,
3533 tc_a4e22bbd = 163,
3534 tc_503ce0f3 = 164,
3535 tc_0655b949 = 165,
3536 tc_6e20402a = 166,
3537 tc_db96aa6b = 167,
3538 tc_a7bdb22c = 168,
3539 tc_db596beb = 169,
3540 tc_a08b630b = 170,
3541 tc_1fcb8495 = 171,
3542 tc_9edefe01 = 172,
3543 tc_449acf79 = 173,
3544 tc_ce59038e = 174,
3545 tc_f529831b = 175,
3546 tc_addc37a8 = 176,
3547 tc_6f42bc60 = 177,
3548 tc_7af3a37e = 178,
3549 tc_e3d699e3 = 179,
3550 tc_ba9255a6 = 180,
3551 tc_1fe4ab69 = 181,
3552 tc_bb07f2c5 = 182,
3553 tc_8e82e8ca = 183,
3554 tc_cfa0e29b = 184,
3555 tc_0a6c20ae = 185,
3556 tc_0fac1eb8 = 186,
3557 tc_829d8a86 = 187,
3558 tc_280f7fe1 = 188,
3559 tc_887d1bb7 = 189,
3560 tc_96ef76ef = 190,
3561 tc_55a9a350 = 191,
3562 tc_f0cdeccf = 192,
3563 tc_a38c45dc = 193,
3564 tc_d3632d88 = 194,
3565 tc_5e4cf0e8 = 195,
3566 tc_ef921005 = 196,
3567 tc_5b347363 = 197,
3568 tc_3d14a17b = 198,
3569 tc_3fbf1042 = 199,
3570 tc_63567288 = 200,
3571 tc_59a7822c = 201,
3572 tc_937dd41c = 202,
3573 tc_a4ee89db = 203,
3574 tc_c818ff7f = 204,
3575 tc_1242dc2a = 205,
3576 tc_44d5a428 = 206,
3577 tc_540c3da3 = 207,
3578 tc_5bf8afbb = 208,
3579 tc_2b4c548e = 209,
3580 tc_bb599486 = 210,
3581 tc_a7e6707d = 211,
3582 tc_3c56e5ce = 212,
3583 tc_abe8c3b2 = 213,
3584 tc_453fe68d = 214,
3585 tc_1ba8a0cd = 215,
3586 tc_52447ecc = 216,
3587 tc_3904b926 = 217,
3588 tc_b9db8205 = 218,
3589 tc_663c80a7 = 219,
3590 tc_f21e8abb = 220,
3591 tc_131f1c81 = 221,
3592 tc_c7039829 = 222,
3593 tc_e2d2e9e5 = 223,
3594 tc_ab23f776 = 224,
3595 tc_7177e272 = 225,
3596 tc_e99d4c2e = 226,
3597 tc_6942b6e0 = 227,
3598 tc_a02a10a8 = 228,
3599 tc_54a0dc47 = 229,
3600 tc_447d9895 = 230,
3601 tc_191381c1 = 231,
3602 tc_3e2aaafc = 232,
3603 tc_3ce09744 = 233,
3604 tc_20a4bbec = 234,
3605 tc_5cdf8c84 = 235,
3606 tc_c127de3a = 236,
3607 tc_05ca8cfd = 237,
3608 tc_d8287c14 = 238,
3609 tc_257f6f7c = 239,
3610 tc_7e6a3e89 = 240,
3611 tc_e35c1e93 = 241,
3612 tc_08a4f1b6 = 242,
3613 tc_56e64202 = 243,
3614 tc_ac4046bc = 244,
3615 tc_2e8f5f6e = 245,
3616 tc_7417e785 = 246,
3617 tc_309dbb4f = 247,
3618 tc_df80eeb0 = 248,
3619 tc_16ff9ef8 = 249,
3620 tc_e2fdd6e6 = 250,
3621 tc_51d0ecc3 = 251,
3622 tc_531b383c = 252,
3623 tc_3c8c15d0 = 253,
3624 tc_0afc8be9 = 254,
3625 tc_561aaa58 = 255,
3626 tc_946013d8 = 256,
3627 tc_46d6c3e0 = 257,
3628 tc_87adc037 = 258,
3629 tc_a19b9305 = 259,
3630 tc_649072c2 = 260,
3631 tc_b091f1c6 = 261,
3632 tc_0b04c6c7 = 262,
3633 tc_660769f1 = 263,
3634 tc_dcca380f = 264,
3635 tc_72e2b393 = 265,
3636 tc_73efe966 = 266,
3637 tc_cda936da = 267,
3638 tc_a28f32b5 = 268,
3639 tc_7d68d5c2 = 269,
3640 tc_7095ecba = 270,
3641 tc_a69eeee1 = 271,
3642 tc_1381a97c = 272,
3643 tc_e3f68a46 = 273,
3644 tc_f1de44ef = 274,
3645 tc_9d1dc972 = 275,
3646 tc_90bcc1db = 276,
3647 tc_cd94bfe0 = 277,
3648 tc_15fdf750 = 278,
3649 tc_1ad8a370 = 279,
3650 tc_e675c45a = 280,
3651 tc_37820f4c = 281,
3652 tc_61bf7c03 = 282,
3653 tc_933f2b39 = 283,
3654 tc_26a377fe = 284,
3655 tc_2d4051cd = 285,
3656 tc_6e7fa133 = 286,
3657 tc_8772086c = 287,
3658 tc_b4416217 = 288,
3659 tc_9f363d21 = 289,
3660 tc_8e420e4d = 290,
3661 tc_7273323b = 291,
3662 tc_58d21193 = 292,
3663 tc_71646d06 = 293,
3664 tc_04da405a = 294,
3665 tc_2c745bb8 = 295,
3666 tc_b28e51aa = 296,
3667 tc_767c4e9d = 297,
3668 tc_e699ae41 = 298,
3669 tc_a0dbea28 = 299,
3670 tc_dd5b0695 = 300,
3671 tc_3ad719fb = 301,
3672 tc_77f94a5e = 302,
3673 tc_55255f2b = 303,
3674 tc_0a43be35 = 304,
3675 tc_b1ae5f67 = 305,
3676 tc_d234b61a = 306,
3677 tc_2237d952 = 307,
3678 tc_78f87ed3 = 308,
3679 tc_a724463d = 309,
3680 tc_6fb52018 = 310,
3681 tc_46c18ecf = 311,
3682 tc_9b20a062 = 312,
3683 tc_5a222e89 = 313,
3684 tc_0ba0d5da = 314,
3685 tc_7d6a2568 = 315,
3686 tc_759e57be = 316,
3687 tc_139ef484 = 317,
3688 tc_9b34f5e0 = 318,
3689 tc_7f58404a = 319,
3690 tc_b3d46584 = 320,
3691 tc_d71ea8fa = 321,
3692 tc_6aa823ab = 322,
3693 tc_b2196a3f = 323,
3694 tc_2c3e17fc = 324,
3695 tc_27106296 = 325,
3696 tc_a3070909 = 326,
3697 tc_512b1653 = 327,
3698 tc_d7718fbe = 328,
3699 tc_bb78483e = 329,
3700 tc_54f0cee2 = 330,
3701 tc_28e55c6f = 331,
3702 tc_4bf903b0 = 332,
3703 tc_7c28bd7e = 333,
3704 tc_invalid = 334,
3705 SCHED_LIST_END = 335
3706 };
3707} // end namespace Sched
3708} // end namespace Hexagon
3709} // end namespace llvm
3710#endif // GET_INSTRINFO_SCHED_ENUM
3711
3712#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
3713namespace llvm {
3714
3715struct HexagonInstrTable {
3716 MCInstrDesc Insts[3341];
3717 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
3718 MCOperandInfo OperandInfo[1079];
3719 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
3720 MCPhysReg ImplicitOps[177];
3721};
3722
3723} // end namespace llvm
3724#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
3725
3726#ifdef GET_INSTRINFO_MC_DESC
3727#undef GET_INSTRINFO_MC_DESC
3728namespace llvm {
3729
3730static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
3731static constexpr unsigned HexagonImpOpBase = sizeof HexagonInstrTable::OperandInfo / (sizeof(MCPhysReg));
3732
3733extern const HexagonInstrTable HexagonDescs = {
3734 {
3735 { 3340, 0, 0, 4, 334, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #3340 = invalid_decode
3736 { 3339, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x3ULL }, // Inst #3339 = dep_S2_packhl
3737 { 3338, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #3338 = dep_A2_subsat
3738 { 3337, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #3337 = dep_A2_addsat
3739 { 3336, 1, 0, 4, 333, 0, 0, HexagonImpOpBase + 0, 1078, 0, 0xa9ULL }, // Inst #3336 = Y6_l2gcleanpa
3740 { 3335, 1, 0, 4, 333, 0, 0, HexagonImpOpBase + 0, 1078, 0, 0xa9ULL }, // Inst #3335 = Y6_l2gcleaninvpa
3741 { 3334, 1, 1, 4, 332, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80a9ULL }, // Inst #3334 = Y6_dmwait
3742 { 3333, 1, 0, 4, 167, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xa9ULL }, // Inst #3333 = Y6_dmstart
3743 { 3332, 1, 0, 4, 167, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xa9ULL }, // Inst #3332 = Y6_dmresume
3744 { 3331, 1, 1, 4, 332, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80a9ULL }, // Inst #3331 = Y6_dmpoll
3745 { 3330, 1, 1, 4, 332, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80a9ULL }, // Inst #3330 = Y6_dmpause
3746 { 3329, 2, 0, 4, 178, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xa9ULL }, // Inst #3329 = Y6_dmlink
3747 { 3328, 2, 0, 4, 331, 0, 0, HexagonImpOpBase + 0, 162, 0, 0x5ULL }, // Inst #3328 = Y6_diag1
3748 { 3327, 2, 0, 4, 331, 0, 0, HexagonImpOpBase + 0, 162, 0, 0x5ULL }, // Inst #3327 = Y6_diag0
3749 { 3326, 1, 0, 4, 324, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x5ULL }, // Inst #3326 = Y6_diag
3750 { 3325, 2, 1, 4, 322, 0, 0, HexagonImpOpBase + 0, 307, 0, 0x8085ULL }, // Inst #3325 = Y5_tlboc
3751 { 3324, 1, 0, 4, 330, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x85ULL }, // Inst #3324 = Y5_tlbasidi
3752 { 3323, 1, 0, 4, 306, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x129ULL }, // Inst #3323 = Y5_l2unlocka
3753 { 3322, 2, 1, 4, 309, 0, 0, HexagonImpOpBase + 0, 185, 0, 0x2129ULL }, // Inst #3322 = Y5_l2locka
3754 { 3321, 1, 0, 4, 306, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x129ULL }, // Inst #3321 = Y5_l2invidx
3755 { 3320, 0, 0, 4, 320, 0, 0, HexagonImpOpBase + 0, 1, 0, 0xa9ULL }, // Inst #3320 = Y5_l2gunlock
3756 { 3319, 0, 0, 4, 320, 0, 0, HexagonImpOpBase + 0, 1, 0, 0xa9ULL }, // Inst #3319 = Y5_l2gcleaninv
3757 { 3318, 0, 0, 4, 320, 0, 0, HexagonImpOpBase + 0, 1, 0, 0xa9ULL }, // Inst #3318 = Y5_l2gclean
3758 { 3317, 2, 0, 4, 326, 0, 0, HexagonImpOpBase + 0, 307, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x129ULL }, // Inst #3317 = Y5_l2fetch
3759 { 3316, 1, 0, 4, 306, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x129ULL }, // Inst #3316 = Y5_l2cleanidx
3760 { 3315, 3, 1, 4, 329, 0, 0, HexagonImpOpBase + 0, 212, 0, 0x8085ULL }, // Inst #3315 = Y5_ctlbw
3761 { 3314, 1, 0, 4, 328, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x105ULL }, // Inst #3314 = Y4_trace
3762 { 3313, 2, 1, 4, 116, 0, 0, HexagonImpOpBase + 0, 1076, 0, 0x8005ULL }, // Inst #3313 = Y4_tfrspcp
3763 { 3312, 2, 1, 4, 115, 0, 0, HexagonImpOpBase + 0, 1074, 0, 0x5ULL }, // Inst #3312 = Y4_tfrscpp
3764 { 3311, 1, 0, 4, 304, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x105ULL }, // Inst #3311 = Y4_siad
3765 { 3310, 1, 0, 4, 304, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x85ULL }, // Inst #3310 = Y4_nmi
3766 { 3309, 2, 0, 4, 327, 0, 0, HexagonImpOpBase + 0, 157, 0, 0xa9ULL }, // Inst #3309 = Y4_l2tagw
3767 { 3308, 2, 1, 4, 309, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x8129ULL }, // Inst #3308 = Y4_l2tagr
3768 { 3307, 2, 0, 4, 326, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x129ULL }, // Inst #3307 = Y4_l2fetch
3769 { 3306, 3, 1, 4, 325, 2, 2, HexagonImpOpBase + 173, 1071, 0, 0x5ULL }, // Inst #3306 = Y4_crswap10
3770 { 3305, 2, 1, 4, 66, 1, 1, HexagonImpOpBase + 171, 493, 0, 0x8005ULL }, // Inst #3305 = Y4_crswap1
3771 { 3304, 1, 0, 4, 324, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x85ULL }, // Inst #3304 = Y2_wait
3772 { 3303, 2, 0, 4, 323, 0, 0, HexagonImpOpBase + 0, 190, 0, 0x85ULL }, // Inst #3303 = Y2_tlbw
3773 { 3302, 0, 0, 4, 319, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x85ULL }, // Inst #3302 = Y2_tlbunlock
3774 { 3301, 2, 1, 4, 322, 0, 0, HexagonImpOpBase + 0, 190, 0, 0x85ULL }, // Inst #3301 = Y2_tlbr
3775 { 3300, 2, 1, 4, 322, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x8085ULL }, // Inst #3300 = Y2_tlbp
3776 { 3299, 0, 0, 4, 319, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x85ULL }, // Inst #3299 = Y2_tlblock
3777 { 3298, 2, 1, 4, 116, 0, 0, HexagonImpOpBase + 0, 1069, 0, 0x8005ULL }, // Inst #3298 = Y2_tfrsrcr
3778 { 3297, 2, 1, 4, 115, 0, 0, HexagonImpOpBase + 0, 1067, 0, 0x8005ULL }, // Inst #3297 = Y2_tfrscrr
3779 { 3296, 0, 0, 4, 302, 0, 0, HexagonImpOpBase + 0, 1, 0, 0xa9ULL }, // Inst #3296 = Y2_syncht
3780 { 3295, 1, 0, 4, 304, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x105ULL }, // Inst #3295 = Y2_swi
3781 { 3294, 1, 0, 4, 304, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x85ULL }, // Inst #3294 = Y2_stop
3782 { 3293, 1, 0, 4, 304, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x85ULL }, // Inst #3293 = Y2_start
3783 { 3292, 2, 0, 4, 321, 0, 0, HexagonImpOpBase + 0, 185, 0, 0x5ULL }, // Inst #3292 = Y2_setprio
3784 { 3291, 2, 0, 4, 321, 0, 0, HexagonImpOpBase + 0, 185, 0, 0x105ULL }, // Inst #3291 = Y2_setimask
3785 { 3290, 1, 0, 4, 304, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x85ULL }, // Inst #3290 = Y2_resume
3786 { 3289, 0, 0, 4, 320, 0, 0, HexagonImpOpBase + 0, 1, 0, 0xa9ULL }, // Inst #3289 = Y2_l2kill
3787 { 3288, 1, 0, 4, 306, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x129ULL }, // Inst #3288 = Y2_l2cleaninvidx
3788 { 3287, 0, 0, 4, 319, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x85ULL }, // Inst #3287 = Y2_k0unlock
3789 { 3286, 0, 0, 4, 319, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x85ULL }, // Inst #3286 = Y2_k0lock
3790 { 3285, 0, 0, 4, 318, 0, 0, HexagonImpOpBase + 0, 1, 0, 0xa3ULL }, // Inst #3285 = Y2_isync
3791 { 3284, 2, 0, 4, 317, 0, 0, HexagonImpOpBase + 0, 157, 0, 0xa3ULL }, // Inst #3284 = Y2_ictagw
3792 { 3283, 2, 1, 4, 316, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x80a3ULL }, // Inst #3283 = Y2_ictagr
3793 { 3282, 0, 0, 4, 133, 0, 0, HexagonImpOpBase + 0, 1, 0, 0xa3ULL }, // Inst #3282 = Y2_ickill
3794 { 3281, 1, 0, 4, 315, 0, 0, HexagonImpOpBase + 0, 272, 0, 0xa3ULL }, // Inst #3281 = Y2_icinvidx
3795 { 3280, 1, 0, 4, 314, 0, 0, HexagonImpOpBase + 0, 272, 0, 0xa3ULL }, // Inst #3280 = Y2_icinva
3796 { 3279, 2, 0, 4, 313, 0, 0, HexagonImpOpBase + 0, 157, 0, 0xa3ULL }, // Inst #3279 = Y2_icdataw
3797 { 3278, 2, 1, 4, 312, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x80a3ULL }, // Inst #3278 = Y2_icdatar
3798 { 3277, 1, 0, 4, 304, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x105ULL }, // Inst #3277 = Y2_iassignw
3799 { 3276, 2, 1, 4, 311, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x8105ULL }, // Inst #3276 = Y2_iassignr
3800 { 3275, 2, 1, 4, 311, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x8105ULL }, // Inst #3275 = Y2_getimask
3801 { 3274, 1, 0, 4, 305, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x229ULL }, // Inst #3274 = Y2_dczeroa
3802 { 3273, 2, 0, 4, 310, 0, 0, HexagonImpOpBase + 0, 157, 0, 0xa9ULL }, // Inst #3273 = Y2_dctagw
3803 { 3272, 2, 1, 4, 309, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x8129ULL }, // Inst #3272 = Y2_dctagr
3804 { 3271, 0, 0, 4, 308, 0, 0, HexagonImpOpBase + 0, 1, 0, 0xa9ULL }, // Inst #3271 = Y2_dckill
3805 { 3270, 1, 0, 4, 306, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x129ULL }, // Inst #3270 = Y2_dcinvidx
3806 { 3269, 1, 0, 4, 305, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x229ULL }, // Inst #3269 = Y2_dcinva
3807 { 3268, 2, 0, 4, 307, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38000000024ULL }, // Inst #3268 = Y2_dcfetchbo
3808 { 3267, 1, 0, 4, 306, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x129ULL }, // Inst #3267 = Y2_dccleaninvidx
3809 { 3266, 1, 0, 4, 305, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x229ULL }, // Inst #3266 = Y2_dccleaninva
3810 { 3265, 1, 0, 4, 306, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x129ULL }, // Inst #3265 = Y2_dccleanidx
3811 { 3264, 1, 0, 4, 305, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x229ULL }, // Inst #3264 = Y2_dccleana
3812 { 3263, 1, 0, 4, 304, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x105ULL }, // Inst #3263 = Y2_cswi
3813 { 3262, 2, 1, 4, 66, 1, 1, HexagonImpOpBase + 169, 493, 0, 0x8005ULL }, // Inst #3262 = Y2_crswap0
3814 { 3261, 1, 0, 4, 304, 0, 0, HexagonImpOpBase + 0, 272, 0, 0x105ULL }, // Inst #3261 = Y2_ciad
3815 { 3260, 0, 0, 4, 303, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x85ULL }, // Inst #3260 = Y2_break
3816 { 3259, 0, 0, 4, 302, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x129ULL }, // Inst #3259 = Y2_barrier
3817 { 3258, 2, 1, 4, 208, 0, 0, HexagonImpOpBase + 0, 289, 0, 0x800000000008018ULL }, // Inst #3258 = V6_zextract
3818 { 3257, 4, 1, 4, 301, 0, 0, HexagonImpOpBase + 0, 1063, 0|(1ULL<<MCID::MayLoad), 0x80006800000041fULL }, // Inst #3257 = V6_zLd_pred_ppu
3819 { 3256, 4, 1, 4, 301, 0, 0, HexagonImpOpBase + 0, 1059, 0|(1ULL<<MCID::MayLoad), 0x80006800000041fULL }, // Inst #3256 = V6_zLd_pred_pi
3820 { 3255, 3, 0, 4, 300, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x80003800000041fULL }, // Inst #3255 = V6_zLd_pred_ai
3821 { 3254, 3, 1, 4, 299, 0, 0, HexagonImpOpBase + 0, 946, 0|(1ULL<<MCID::MayLoad), 0x80006800000001fULL }, // Inst #3254 = V6_zLd_ppu
3822 { 3253, 3, 1, 4, 299, 0, 0, HexagonImpOpBase + 0, 507, 0|(1ULL<<MCID::MayLoad), 0x80006800000001fULL }, // Inst #3253 = V6_zLd_pi
3823 { 3252, 2, 0, 4, 298, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad), 0x80003800000001fULL }, // Inst #3252 = V6_zLd_ai
3824 { 3251, 2, 1, 4, 288, 0, 0, HexagonImpOpBase + 0, 465, 0, 0x800000000008011ULL }, // Inst #3251 = V6_vzh
3825 { 3250, 2, 1, 4, 288, 0, 0, HexagonImpOpBase + 0, 465, 0, 0x800000000008011ULL }, // Inst #3250 = V6_vzb
3826 { 3249, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3249 = V6_vxor
3827 { 3248, 1, 0, 4, 273, 0, 0, HexagonImpOpBase + 0, 249, 0, 0x80000000000000aULL }, // Inst #3248 = V6_vwhist256q_sat
3828 { 3247, 1, 0, 4, 273, 0, 0, HexagonImpOpBase + 0, 249, 0, 0x80000000000000aULL }, // Inst #3247 = V6_vwhist256q
3829 { 3246, 0, 0, 4, 272, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x80000000000000aULL }, // Inst #3246 = V6_vwhist256_sat
3830 { 3245, 0, 0, 4, 272, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x80000000000000aULL }, // Inst #3245 = V6_vwhist256
3831 { 3244, 2, 0, 4, 297, 0, 0, HexagonImpOpBase + 0, 1057, 0, 0x80000000000000aULL }, // Inst #3244 = V6_vwhist128qm
3832 { 3243, 1, 0, 4, 273, 0, 0, HexagonImpOpBase + 0, 249, 0, 0x80000000000000aULL }, // Inst #3243 = V6_vwhist128q
3833 { 3242, 1, 0, 4, 296, 0, 0, HexagonImpOpBase + 0, 0, 0, 0x80000000000000aULL }, // Inst #3242 = V6_vwhist128m
3834 { 3241, 0, 0, 4, 272, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x80000000000000aULL }, // Inst #3241 = V6_vwhist128
3835 { 3240, 2, 1, 4, 294, 0, 0, HexagonImpOpBase + 0, 465, 0, 0x800000000008019ULL }, // Inst #3240 = V6_vunpackuh
3836 { 3239, 2, 1, 4, 294, 0, 0, HexagonImpOpBase + 0, 465, 0, 0x800000000008019ULL }, // Inst #3239 = V6_vunpackub
3837 { 3238, 3, 1, 4, 295, 0, 0, HexagonImpOpBase + 0, 490, 0, 0x840000000008019ULL }, // Inst #3238 = V6_vunpackoh
3838 { 3237, 3, 1, 4, 295, 0, 0, HexagonImpOpBase + 0, 490, 0, 0x840000000008019ULL }, // Inst #3237 = V6_vunpackob
3839 { 3236, 2, 1, 4, 294, 0, 0, HexagonImpOpBase + 0, 465, 0, 0x800000000008019ULL }, // Inst #3236 = V6_vunpackh
3840 { 3235, 2, 1, 4, 294, 0, 0, HexagonImpOpBase + 0, 465, 0, 0x800000000008019ULL }, // Inst #3235 = V6_vunpackb
3841 { 3234, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 402, 0, 0x84000000000801dULL }, // Inst #3234 = V6_vtmpyhb_acc
3842 { 3233, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 406, 0, 0x80000000000801dULL }, // Inst #3233 = V6_vtmpyhb
3843 { 3232, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 402, 0, 0x84000000000801dULL }, // Inst #3232 = V6_vtmpybus_acc
3844 { 3231, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 406, 0, 0x80000000000801dULL }, // Inst #3231 = V6_vtmpybus
3845 { 3230, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 402, 0, 0x84000000000801dULL }, // Inst #3230 = V6_vtmpyb_acc
3846 { 3229, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 406, 0, 0x80000000000801dULL }, // Inst #3229 = V6_vtmpyb
3847 { 3228, 4, 1, 4, 293, 0, 0, HexagonImpOpBase + 0, 1053, 0, 0x800000000008011ULL }, // Inst #3228 = V6_vswap
3848 { 3227, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #3227 = V6_vsubwsat_dv
3849 { 3226, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3226 = V6_vsubwsat
3850 { 3225, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 367, 0, 0x3800000000008010ULL }, // Inst #3225 = V6_vsubwq
3851 { 3224, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 367, 0, 0x3800000000008010ULL }, // Inst #3224 = V6_vsubwnq
3852 { 3223, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #3223 = V6_vsubw_dv
3853 { 3222, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3222 = V6_vsubw
3854 { 3221, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #3221 = V6_vsubuwsat_dv
3855 { 3220, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3220 = V6_vsubuwsat
3856 { 3219, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3219 = V6_vsubuhw
3857 { 3218, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #3218 = V6_vsubuhsat_dv
3858 { 3217, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3217 = V6_vsubuhsat
3859 { 3216, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3216 = V6_vsubububb_sat
3860 { 3215, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #3215 = V6_vsububsat_dv
3861 { 3214, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3214 = V6_vsububsat
3862 { 3213, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3213 = V6_vsububh
3863 { 3212, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3212 = V6_vsubhw
3864 { 3211, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #3211 = V6_vsubhsat_dv
3865 { 3210, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3210 = V6_vsubhsat
3866 { 3209, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 367, 0, 0x3800000000008010ULL }, // Inst #3209 = V6_vsubhq
3867 { 3208, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 367, 0, 0x3800000000008010ULL }, // Inst #3208 = V6_vsubhnq
3868 { 3207, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #3207 = V6_vsubh_dv
3869 { 3206, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3206 = V6_vsubh
3870 { 3205, 4, 2, 4, 241, 0, 0, HexagonImpOpBase + 0, 954, 0, 0x3800000000008010ULL }, // Inst #3205 = V6_vsubcarryo
3871 { 3204, 5, 2, 4, 240, 0, 0, HexagonImpOpBase + 0, 949, 0, 0x3800000000008010ULL }, // Inst #3204 = V6_vsubcarry
3872 { 3203, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #3203 = V6_vsubbsat_dv
3873 { 3202, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3202 = V6_vsubbsat
3874 { 3201, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 367, 0, 0x3800000000008010ULL }, // Inst #3201 = V6_vsubbq
3875 { 3200, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 367, 0, 0x3800000000008010ULL }, // Inst #3200 = V6_vsubbnq
3876 { 3199, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #3199 = V6_vsubb_dv
3877 { 3198, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3198 = V6_vsubb
3878 { 3197, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #3197 = V6_vsub_sf_sf
3879 { 3196, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3196 = V6_vsub_sf_hf
3880 { 3195, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3195 = V6_vsub_sf_bf
3881 { 3194, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #3194 = V6_vsub_sf
3882 { 3193, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #3193 = V6_vsub_qf32_mix
3883 { 3192, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #3192 = V6_vsub_qf32
3884 { 3191, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #3191 = V6_vsub_qf16_mix
3885 { 3190, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #3190 = V6_vsub_qf16
3886 { 3189, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #3189 = V6_vsub_hf_hf
3887 { 3188, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #3188 = V6_vsub_hf
3888 { 3187, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3187 = V6_vshufoh
3889 { 3186, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x800000000008011ULL }, // Inst #3186 = V6_vshufoeh
3890 { 3185, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x800000000008011ULL }, // Inst #3185 = V6_vshufoeb
3891 { 3184, 4, 1, 4, 258, 0, 0, HexagonImpOpBase + 0, 983, 0, 0x800000000008019ULL }, // Inst #3184 = V6_vshuffvdd
3892 { 3183, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3183 = V6_vshuffob
3893 { 3182, 2, 1, 4, 256, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x800000000008018ULL }, // Inst #3182 = V6_vshuffh
3894 { 3181, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3181 = V6_vshuffeb
3895 { 3180, 2, 1, 4, 256, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x800000000008018ULL }, // Inst #3180 = V6_vshuffb
3896 { 3179, 5, 2, 4, 255, 0, 0, HexagonImpOpBase + 0, 485, 0, 0x80c000000008019ULL }, // Inst #3179 = V6_vshuff
3897 { 3178, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3178 = V6_vshufeh
3898 { 3177, 2, 1, 4, 288, 0, 0, HexagonImpOpBase + 0, 465, 0, 0x800000000008011ULL }, // Inst #3177 = V6_vsh
3899 { 3176, 5, 0, 4, 290, 0, 0, HexagonImpOpBase + 0, 471, 0|(1ULL<<MCID::MayStore), 0x380018000000000bULL }, // Inst #3176 = V6_vscattermwq
3900 { 3175, 4, 0, 4, 289, 0, 0, HexagonImpOpBase + 0, 467, 0|(1ULL<<MCID::MayStore), 0x384018000000000bULL }, // Inst #3175 = V6_vscattermw_add
3901 { 3174, 4, 0, 4, 289, 0, 0, HexagonImpOpBase + 0, 467, 0|(1ULL<<MCID::MayStore), 0x380018000000000bULL }, // Inst #3174 = V6_vscattermw
3902 { 3173, 5, 0, 4, 292, 0, 0, HexagonImpOpBase + 0, 480, 0|(1ULL<<MCID::MayStore), 0x80010000000000cULL }, // Inst #3173 = V6_vscattermhwq
3903 { 3172, 4, 0, 4, 291, 0, 0, HexagonImpOpBase + 0, 476, 0|(1ULL<<MCID::MayStore), 0x84010000000000cULL }, // Inst #3172 = V6_vscattermhw_add
3904 { 3171, 4, 0, 4, 291, 0, 0, HexagonImpOpBase + 0, 476, 0|(1ULL<<MCID::MayStore), 0x80010000000000cULL }, // Inst #3171 = V6_vscattermhw
3905 { 3170, 5, 0, 4, 290, 0, 0, HexagonImpOpBase + 0, 471, 0|(1ULL<<MCID::MayStore), 0x380010000000000bULL }, // Inst #3170 = V6_vscattermhq
3906 { 3169, 4, 0, 4, 289, 0, 0, HexagonImpOpBase + 0, 467, 0|(1ULL<<MCID::MayStore), 0x384010000000000bULL }, // Inst #3169 = V6_vscattermh_add
3907 { 3168, 4, 0, 4, 289, 0, 0, HexagonImpOpBase + 0, 467, 0|(1ULL<<MCID::MayStore), 0x380010000000000bULL }, // Inst #3168 = V6_vscattermh
3908 { 3167, 2, 1, 4, 288, 0, 0, HexagonImpOpBase + 0, 465, 0, 0x800000000008011ULL }, // Inst #3167 = V6_vsb
3909 { 3166, 3, 1, 4, 287, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3166 = V6_vsatwh
3910 { 3165, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3165 = V6_vsatuwuh
3911 { 3164, 3, 1, 4, 287, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3164 = V6_vsathub
3912 { 3163, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3163 = V6_vsatdw
3913 { 3162, 5, 1, 4, 280, 0, 0, HexagonImpOpBase + 0, 456, 0, 0x84000000000801dULL }, // Inst #3162 = V6_vrsadubi_acc
3914 { 3161, 4, 1, 4, 279, 0, 0, HexagonImpOpBase + 0, 461, 0, 0x80000000000801dULL }, // Inst #3161 = V6_vrsadubi
3915 { 3160, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #3160 = V6_vroundwuh
3916 { 3159, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #3159 = V6_vroundwh
3917 { 3158, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #3158 = V6_vrounduwuh
3918 { 3157, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #3157 = V6_vrounduhub
3919 { 3156, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #3156 = V6_vroundhub
3920 { 3155, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #3155 = V6_vroundhb
3921 { 3154, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #3154 = V6_vrotr
3922 { 3153, 3, 1, 4, 286, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x800000000008018ULL }, // Inst #3153 = V6_vror
3923 { 3152, 5, 2, 4, 285, 0, 0, HexagonImpOpBase + 0, 1048, 0, 0x840000000008006ULL }, // Inst #3152 = V6_vrmpyznb_rx_acc
3924 { 3151, 4, 2, 4, 284, 0, 0, HexagonImpOpBase + 0, 1044, 0, 0x800000000008006ULL }, // Inst #3151 = V6_vrmpyznb_rx
3925 { 3150, 4, 1, 4, 283, 0, 0, HexagonImpOpBase + 0, 1040, 0, 0x840000000008006ULL }, // Inst #3150 = V6_vrmpyznb_rt_acc
3926 { 3149, 3, 1, 4, 282, 0, 0, HexagonImpOpBase + 0, 1037, 0, 0x800000000008006ULL }, // Inst #3149 = V6_vrmpyznb_rt
3927 { 3148, 5, 2, 4, 285, 0, 0, HexagonImpOpBase + 0, 1048, 0, 0x840000000008006ULL }, // Inst #3148 = V6_vrmpyzcbs_rx_acc
3928 { 3147, 4, 2, 4, 284, 0, 0, HexagonImpOpBase + 0, 1044, 0, 0x800000000008006ULL }, // Inst #3147 = V6_vrmpyzcbs_rx
3929 { 3146, 4, 1, 4, 283, 0, 0, HexagonImpOpBase + 0, 1040, 0, 0x840000000008006ULL }, // Inst #3146 = V6_vrmpyzcbs_rt_acc
3930 { 3145, 3, 1, 4, 282, 0, 0, HexagonImpOpBase + 0, 1037, 0, 0x800000000008006ULL }, // Inst #3145 = V6_vrmpyzcbs_rt
3931 { 3144, 5, 2, 4, 285, 0, 0, HexagonImpOpBase + 0, 1048, 0, 0x840000000008006ULL }, // Inst #3144 = V6_vrmpyzcb_rx_acc
3932 { 3143, 4, 2, 4, 284, 0, 0, HexagonImpOpBase + 0, 1044, 0, 0x800000000008006ULL }, // Inst #3143 = V6_vrmpyzcb_rx
3933 { 3142, 4, 1, 4, 283, 0, 0, HexagonImpOpBase + 0, 1040, 0, 0x840000000008006ULL }, // Inst #3142 = V6_vrmpyzcb_rt_acc
3934 { 3141, 3, 1, 4, 282, 0, 0, HexagonImpOpBase + 0, 1037, 0, 0x800000000008006ULL }, // Inst #3141 = V6_vrmpyzcb_rt
3935 { 3140, 5, 2, 4, 285, 0, 0, HexagonImpOpBase + 0, 1048, 0, 0x840000000008006ULL }, // Inst #3140 = V6_vrmpyzbub_rx_acc
3936 { 3139, 4, 2, 4, 284, 0, 0, HexagonImpOpBase + 0, 1044, 0, 0x800000000008006ULL }, // Inst #3139 = V6_vrmpyzbub_rx
3937 { 3138, 4, 1, 4, 283, 0, 0, HexagonImpOpBase + 0, 1040, 0, 0x840000000008006ULL }, // Inst #3138 = V6_vrmpyzbub_rt_acc
3938 { 3137, 3, 1, 4, 282, 0, 0, HexagonImpOpBase + 0, 1037, 0, 0x800000000008006ULL }, // Inst #3137 = V6_vrmpyzbub_rt
3939 { 3136, 5, 2, 4, 285, 0, 0, HexagonImpOpBase + 0, 1048, 0, 0x840000000008006ULL }, // Inst #3136 = V6_vrmpyzbb_rx_acc
3940 { 3135, 4, 2, 4, 284, 0, 0, HexagonImpOpBase + 0, 1044, 0, 0x800000000008006ULL }, // Inst #3135 = V6_vrmpyzbb_rx
3941 { 3134, 4, 1, 4, 283, 0, 0, HexagonImpOpBase + 0, 1040, 0, 0x840000000008006ULL }, // Inst #3134 = V6_vrmpyzbb_rt_acc
3942 { 3133, 3, 1, 4, 282, 0, 0, HexagonImpOpBase + 0, 1037, 0, 0x800000000008006ULL }, // Inst #3133 = V6_vrmpyzbb_rt
3943 { 3132, 4, 1, 4, 281, 0, 0, HexagonImpOpBase + 0, 416, 0, 0x84000000000801cULL }, // Inst #3132 = V6_vrmpyubv_acc
3944 { 3131, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #3131 = V6_vrmpyubv
3945 { 3130, 5, 1, 4, 280, 0, 0, HexagonImpOpBase + 0, 456, 0, 0x84000000000801dULL }, // Inst #3130 = V6_vrmpyubi_acc
3946 { 3129, 4, 1, 4, 279, 0, 0, HexagonImpOpBase + 0, 461, 0, 0x80000000000801dULL }, // Inst #3129 = V6_vrmpyubi
3947 { 3128, 4, 1, 4, 278, 0, 0, HexagonImpOpBase + 0, 449, 0, 0x84000000000801bULL }, // Inst #3128 = V6_vrmpyub_rtt_acc
3948 { 3127, 3, 1, 4, 277, 0, 0, HexagonImpOpBase + 0, 453, 0, 0x80000000000801bULL }, // Inst #3127 = V6_vrmpyub_rtt
3949 { 3126, 4, 1, 4, 261, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801cULL }, // Inst #3126 = V6_vrmpyub_acc
3950 { 3125, 3, 1, 4, 260, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801cULL }, // Inst #3125 = V6_vrmpyub
3951 { 3124, 4, 1, 4, 281, 0, 0, HexagonImpOpBase + 0, 416, 0, 0x84000000000801cULL }, // Inst #3124 = V6_vrmpybv_acc
3952 { 3123, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #3123 = V6_vrmpybv
3953 { 3122, 4, 1, 4, 281, 0, 0, HexagonImpOpBase + 0, 416, 0, 0x84000000000801cULL }, // Inst #3122 = V6_vrmpybusv_acc
3954 { 3121, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #3121 = V6_vrmpybusv
3955 { 3120, 5, 1, 4, 280, 0, 0, HexagonImpOpBase + 0, 456, 0, 0x84000000000801dULL }, // Inst #3120 = V6_vrmpybusi_acc
3956 { 3119, 4, 1, 4, 279, 0, 0, HexagonImpOpBase + 0, 461, 0, 0x80000000000801dULL }, // Inst #3119 = V6_vrmpybusi
3957 { 3118, 4, 1, 4, 261, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801cULL }, // Inst #3118 = V6_vrmpybus_acc
3958 { 3117, 3, 1, 4, 260, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801cULL }, // Inst #3117 = V6_vrmpybus
3959 { 3116, 4, 1, 4, 278, 0, 0, HexagonImpOpBase + 0, 449, 0, 0x84000000000801bULL }, // Inst #3116 = V6_vrmpybub_rtt_acc
3960 { 3115, 3, 1, 4, 277, 0, 0, HexagonImpOpBase + 0, 453, 0, 0x80000000000801bULL }, // Inst #3115 = V6_vrmpybub_rtt
3961 { 3114, 3, 1, 4, 257, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x800000000008018ULL }, // Inst #3114 = V6_vrdelta
3962 { 3113, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 1035, 0, 0x80000000000801aULL }, // Inst #3113 = V6_vprefixqw
3963 { 3112, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 1035, 0, 0x80000000000801aULL }, // Inst #3112 = V6_vprefixqh
3964 { 3111, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 1035, 0, 0x80000000000801aULL }, // Inst #3111 = V6_vprefixqb
3965 { 3110, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801aULL }, // Inst #3110 = V6_vpopcounth
3966 { 3109, 3, 1, 4, 257, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x800000000008018ULL }, // Inst #3109 = V6_vpackwuh_sat
3967 { 3108, 3, 1, 4, 257, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x800000000008018ULL }, // Inst #3108 = V6_vpackwh_sat
3968 { 3107, 3, 1, 4, 257, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x800000000008018ULL }, // Inst #3107 = V6_vpackoh
3969 { 3106, 3, 1, 4, 257, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x800000000008018ULL }, // Inst #3106 = V6_vpackob
3970 { 3105, 3, 1, 4, 257, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x800000000008018ULL }, // Inst #3105 = V6_vpackhub_sat
3971 { 3104, 3, 1, 4, 257, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x800000000008018ULL }, // Inst #3104 = V6_vpackhb_sat
3972 { 3103, 3, 1, 4, 257, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x800000000008018ULL }, // Inst #3103 = V6_vpackeh
3973 { 3102, 3, 1, 4, 257, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x800000000008018ULL }, // Inst #3102 = V6_vpackeb
3974 { 3101, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3101 = V6_vor
3975 { 3100, 2, 1, 4, 63, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x3800000000008010ULL }, // Inst #3100 = V6_vnot
3976 { 3099, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801aULL }, // Inst #3099 = V6_vnormamtw
3977 { 3098, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801aULL }, // Inst #3098 = V6_vnormamth
3978 { 3097, 3, 1, 4, 44, 0, 0, HexagonImpOpBase + 0, 980, 0, 0x1800000000008c10ULL }, // Inst #3097 = V6_vncmov
3979 { 3096, 4, 1, 4, 47, 0, 0, HexagonImpOpBase + 0, 976, 0, 0x800000000008c11ULL }, // Inst #3096 = V6_vnccombine
3980 { 3095, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3095 = V6_vnavgw
3981 { 3094, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3094 = V6_vnavgub
3982 { 3093, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3093 = V6_vnavgh
3983 { 3092, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3092 = V6_vnavgb
3984 { 3091, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 954, 0, 0x3800000000008010ULL }, // Inst #3091 = V6_vmux
3985 { 3090, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #3090 = V6_vmpyuhvs
3986 { 3089, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 371, 0, 0x84000000000801dULL }, // Inst #3089 = V6_vmpyuhv_acc
3987 { 3088, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3088 = V6_vmpyuhv
3988 { 3087, 4, 1, 4, 261, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801cULL }, // Inst #3087 = V6_vmpyuhe_acc
3989 { 3086, 3, 1, 4, 260, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801cULL }, // Inst #3086 = V6_vmpyuhe
3990 { 3085, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 442, 0, 0x84000000000801dULL }, // Inst #3085 = V6_vmpyuh_acc
3991 { 3084, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 446, 0, 0x80000000000801dULL }, // Inst #3084 = V6_vmpyuh
3992 { 3083, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 371, 0, 0x84000000000801dULL }, // Inst #3083 = V6_vmpyubv_acc
3993 { 3082, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3082 = V6_vmpyubv
3994 { 3081, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 442, 0, 0x84000000000801dULL }, // Inst #3081 = V6_vmpyub_acc
3995 { 3080, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 446, 0, 0x80000000000801dULL }, // Inst #3080 = V6_vmpyub
3996 { 3079, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 416, 0, 0x84000000000801dULL }, // Inst #3079 = V6_vmpyowh_sacc
3997 { 3078, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 416, 0, 0x84000000000801dULL }, // Inst #3078 = V6_vmpyowh_rnd_sacc
3998 { 3077, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801dULL }, // Inst #3077 = V6_vmpyowh_rnd
3999 { 3076, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 371, 0, 0x84000000000801dULL }, // Inst #3076 = V6_vmpyowh_64_acc
4000 { 3075, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801dULL }, // Inst #3075 = V6_vmpyowh
4001 { 3074, 4, 1, 4, 261, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801cULL }, // Inst #3074 = V6_vmpyiwub_acc
4002 { 3073, 3, 1, 4, 260, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801cULL }, // Inst #3073 = V6_vmpyiwub
4003 { 3072, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801dULL }, // Inst #3072 = V6_vmpyiwh_acc
4004 { 3071, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801dULL }, // Inst #3071 = V6_vmpyiwh
4005 { 3070, 4, 1, 4, 261, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801cULL }, // Inst #3070 = V6_vmpyiwb_acc
4006 { 3069, 3, 1, 4, 260, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801cULL }, // Inst #3069 = V6_vmpyiwb
4007 { 3068, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801dULL }, // Inst #3068 = V6_vmpyiowh
4008 { 3067, 4, 1, 4, 261, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801cULL }, // Inst #3067 = V6_vmpyihb_acc
4009 { 3066, 3, 1, 4, 260, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801cULL }, // Inst #3066 = V6_vmpyihb
4010 { 3065, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 416, 0, 0x84000000000801dULL }, // Inst #3065 = V6_vmpyih_acc
4011 { 3064, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801dULL }, // Inst #3064 = V6_vmpyih
4012 { 3063, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 416, 0, 0x84000000000801dULL }, // Inst #3063 = V6_vmpyiewuh_acc
4013 { 3062, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801dULL }, // Inst #3062 = V6_vmpyiewuh
4014 { 3061, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 416, 0, 0x84000000000801dULL }, // Inst #3061 = V6_vmpyiewh_acc
4015 { 3060, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #3060 = V6_vmpyieoh
4016 { 3059, 3, 1, 4, 266, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #3059 = V6_vmpyhvsrs
4017 { 3058, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 371, 0, 0x84000000000801dULL }, // Inst #3058 = V6_vmpyhv_acc
4018 { 3057, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3057 = V6_vmpyhv
4019 { 3056, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 371, 0, 0x84000000000801dULL }, // Inst #3056 = V6_vmpyhus_acc
4020 { 3055, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3055 = V6_vmpyhus
4021 { 3054, 3, 1, 4, 264, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801cULL }, // Inst #3054 = V6_vmpyhss
4022 { 3053, 3, 1, 4, 264, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801cULL }, // Inst #3053 = V6_vmpyhsrs
4023 { 3052, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 442, 0, 0x84000000000801dULL }, // Inst #3052 = V6_vmpyhsat_acc
4024 { 3051, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 442, 0, 0x84000000000801dULL }, // Inst #3051 = V6_vmpyh_acc
4025 { 3050, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 446, 0, 0x80000000000801dULL }, // Inst #3050 = V6_vmpyh
4026 { 3049, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3049 = V6_vmpyewuh_64
4027 { 3048, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801dULL }, // Inst #3048 = V6_vmpyewuh
4028 { 3047, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 371, 0, 0x84000000000801dULL }, // Inst #3047 = V6_vmpybv_acc
4029 { 3046, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3046 = V6_vmpybv
4030 { 3045, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 371, 0, 0x84000000000801dULL }, // Inst #3045 = V6_vmpybusv_acc
4031 { 3044, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3044 = V6_vmpybusv
4032 { 3043, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 442, 0, 0x84000000000801dULL }, // Inst #3043 = V6_vmpybus_acc
4033 { 3042, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 446, 0, 0x80000000000801dULL }, // Inst #3042 = V6_vmpybus
4034 { 3041, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801dULL }, // Inst #3041 = V6_vmpy_sf_sf
4035 { 3040, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 371, 0, 0x84000000000801dULL }, // Inst #3040 = V6_vmpy_sf_hf_acc
4036 { 3039, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3039 = V6_vmpy_sf_hf
4037 { 3038, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 371, 0, 0x84000000000801dULL }, // Inst #3038 = V6_vmpy_sf_bf_acc
4038 { 3037, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3037 = V6_vmpy_sf_bf
4039 { 3036, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801dULL }, // Inst #3036 = V6_vmpy_qf32_sf
4040 { 3035, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3035 = V6_vmpy_qf32_qf16
4041 { 3034, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3034 = V6_vmpy_qf32_mix_hf
4042 { 3033, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #3033 = V6_vmpy_qf32_hf
4043 { 3032, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801dULL }, // Inst #3032 = V6_vmpy_qf32
4044 { 3031, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801dULL }, // Inst #3031 = V6_vmpy_qf16_mix_hf
4045 { 3030, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801dULL }, // Inst #3030 = V6_vmpy_qf16_hf
4046 { 3029, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801dULL }, // Inst #3029 = V6_vmpy_qf16
4047 { 3028, 4, 1, 4, 259, 0, 0, HexagonImpOpBase + 0, 416, 0, 0x84000000000801cULL }, // Inst #3028 = V6_vmpy_hf_hf_acc
4048 { 3027, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #3027 = V6_vmpy_hf_hf
4049 { 3026, 4, 1, 4, 276, 0, 0, HexagonImpOpBase + 0, 1031, 0, 0x80000000000801dULL }, // Inst #3026 = V6_vmpsuhuhsat
4050 { 3025, 4, 1, 4, 276, 0, 0, HexagonImpOpBase + 0, 1031, 0, 0x80000000000801dULL }, // Inst #3025 = V6_vmpauhuhsat
4051 { 3024, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 402, 0, 0x84000000000801dULL }, // Inst #3024 = V6_vmpauhb_acc
4052 { 3023, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 406, 0, 0x80000000000801dULL }, // Inst #3023 = V6_vmpauhb
4053 { 3022, 4, 1, 4, 276, 0, 0, HexagonImpOpBase + 0, 1031, 0, 0x80000000000801dULL }, // Inst #3022 = V6_vmpahhsat
4054 { 3021, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 402, 0, 0x84000000000801dULL }, // Inst #3021 = V6_vmpahb_acc
4055 { 3020, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 406, 0, 0x80000000000801dULL }, // Inst #3020 = V6_vmpahb
4056 { 3019, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x80000000000801dULL }, // Inst #3019 = V6_vmpabuuv
4057 { 3018, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 402, 0, 0x84000000000801dULL }, // Inst #3018 = V6_vmpabuu_acc
4058 { 3017, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 406, 0, 0x80000000000801dULL }, // Inst #3017 = V6_vmpabuu
4059 { 3016, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x80000000000801dULL }, // Inst #3016 = V6_vmpabusv
4060 { 3015, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 402, 0, 0x84000000000801dULL }, // Inst #3015 = V6_vmpabus_acc
4061 { 3014, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 406, 0, 0x80000000000801dULL }, // Inst #3014 = V6_vmpabus
4062 { 3013, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3013 = V6_vminw
4063 { 3012, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3012 = V6_vminuh
4064 { 3011, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3011 = V6_vminub
4065 { 3010, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3010 = V6_vminh
4066 { 3009, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3009 = V6_vminb
4067 { 3008, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3008 = V6_vmin_sf
4068 { 3007, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3007 = V6_vmin_hf
4069 { 3006, 3, 1, 4, 267, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801eULL }, // Inst #3006 = V6_vmin_bf
4070 { 3005, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3005 = V6_vmaxw
4071 { 3004, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3004 = V6_vmaxuh
4072 { 3003, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3003 = V6_vmaxub
4073 { 3002, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3002 = V6_vmaxh
4074 { 3001, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3001 = V6_vmaxb
4075 { 3000, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #3000 = V6_vmax_sf
4076 { 2999, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2999 = V6_vmax_hf
4077 { 2998, 3, 1, 4, 267, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801eULL }, // Inst #2998 = V6_vmax_bf
4078 { 2997, 4, 1, 4, 258, 0, 0, HexagonImpOpBase + 0, 1027, 0, 0x800000000008019ULL }, // Inst #2997 = V6_vlutvwhi
4079 { 2996, 5, 1, 4, 275, 0, 0, HexagonImpOpBase + 0, 1022, 0, 0x840000000008019ULL }, // Inst #2996 = V6_vlutvwh_oracci
4080 { 2995, 5, 1, 4, 275, 0, 0, HexagonImpOpBase + 0, 1017, 0, 0x840000000008019ULL }, // Inst #2995 = V6_vlutvwh_oracc
4081 { 2994, 4, 1, 4, 258, 0, 0, HexagonImpOpBase + 0, 983, 0, 0x800000000008019ULL }, // Inst #2994 = V6_vlutvwh_nm
4082 { 2993, 4, 1, 4, 258, 0, 0, HexagonImpOpBase + 0, 983, 0, 0x800000000008019ULL }, // Inst #2993 = V6_vlutvwh
4083 { 2992, 4, 1, 4, 243, 0, 0, HexagonImpOpBase + 0, 966, 0, 0x800000000008018ULL }, // Inst #2992 = V6_vlutvvbi
4084 { 2991, 5, 1, 4, 275, 0, 0, HexagonImpOpBase + 0, 1012, 0, 0x840000000008019ULL }, // Inst #2991 = V6_vlutvvb_oracci
4085 { 2990, 5, 1, 4, 275, 0, 0, HexagonImpOpBase + 0, 1007, 0, 0x840000000008019ULL }, // Inst #2990 = V6_vlutvvb_oracc
4086 { 2989, 4, 1, 4, 243, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x800000000008018ULL }, // Inst #2989 = V6_vlutvvb_nm
4087 { 2988, 4, 1, 4, 243, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x800000000008018ULL }, // Inst #2988 = V6_vlutvvb
4088 { 2987, 3, 1, 4, 274, 0, 0, HexagonImpOpBase + 0, 1004, 0, 0x80000000000801dULL }, // Inst #2987 = V6_vlut4
4089 { 2986, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2986 = V6_vlsrwv
4090 { 2985, 3, 1, 4, 246, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801aULL }, // Inst #2985 = V6_vlsrw
4091 { 2984, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2984 = V6_vlsrhv
4092 { 2983, 3, 1, 4, 246, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801aULL }, // Inst #2983 = V6_vlsrh
4093 { 2982, 3, 1, 4, 246, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801aULL }, // Inst #2982 = V6_vlsrb
4094 { 2981, 4, 1, 4, 243, 0, 0, HexagonImpOpBase + 0, 966, 0, 0x800000000008018ULL }, // Inst #2981 = V6_vlalignbi
4095 { 2980, 4, 1, 4, 243, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x800000000008018ULL }, // Inst #2980 = V6_vlalignb
4096 { 2979, 3, 1, 4, 244, 0, 0, HexagonImpOpBase + 0, 1001, 0, 0x80000000000801eULL }, // Inst #2979 = V6_vinsertwr
4097 { 2978, 1, 0, 4, 273, 0, 0, HexagonImpOpBase + 0, 249, 0, 0x80000000000000aULL }, // Inst #2978 = V6_vhistq
4098 { 2977, 0, 0, 4, 272, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x80000000000000aULL }, // Inst #2977 = V6_vhist
4099 { 2976, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2976 = V6_vgtw_xor
4100 { 2975, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3840000000000010ULL }, // Inst #2975 = V6_vgtw_or
4101 { 2974, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2974 = V6_vgtw_and
4102 { 2973, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 323, 0, 0x3800000000008010ULL }, // Inst #2973 = V6_vgtw
4103 { 2972, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2972 = V6_vgtuw_xor
4104 { 2971, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3840000000000010ULL }, // Inst #2971 = V6_vgtuw_or
4105 { 2970, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2970 = V6_vgtuw_and
4106 { 2969, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 323, 0, 0x3800000000008010ULL }, // Inst #2969 = V6_vgtuw
4107 { 2968, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2968 = V6_vgtuh_xor
4108 { 2967, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3840000000000010ULL }, // Inst #2967 = V6_vgtuh_or
4109 { 2966, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2966 = V6_vgtuh_and
4110 { 2965, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 323, 0, 0x3800000000008010ULL }, // Inst #2965 = V6_vgtuh
4111 { 2964, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2964 = V6_vgtub_xor
4112 { 2963, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3840000000000010ULL }, // Inst #2963 = V6_vgtub_or
4113 { 2962, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2962 = V6_vgtub_and
4114 { 2961, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 323, 0, 0x3800000000008010ULL }, // Inst #2961 = V6_vgtub
4115 { 2960, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2960 = V6_vgtsf_xor
4116 { 2959, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3840000000000010ULL }, // Inst #2959 = V6_vgtsf_or
4117 { 2958, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2958 = V6_vgtsf_and
4118 { 2957, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 323, 0, 0x3800000000008010ULL }, // Inst #2957 = V6_vgtsf
4119 { 2956, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2956 = V6_vgthf_xor
4120 { 2955, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3840000000000010ULL }, // Inst #2955 = V6_vgthf_or
4121 { 2954, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2954 = V6_vgthf_and
4122 { 2953, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 323, 0, 0x3800000000008010ULL }, // Inst #2953 = V6_vgthf
4123 { 2952, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2952 = V6_vgth_xor
4124 { 2951, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3840000000000010ULL }, // Inst #2951 = V6_vgth_or
4125 { 2950, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2950 = V6_vgth_and
4126 { 2949, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 323, 0, 0x3800000000008010ULL }, // Inst #2949 = V6_vgth
4127 { 2948, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2948 = V6_vgtbf_xor
4128 { 2947, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3840000000000010ULL }, // Inst #2947 = V6_vgtbf_or
4129 { 2946, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2946 = V6_vgtbf_and
4130 { 2945, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 323, 0, 0x3800000000008010ULL }, // Inst #2945 = V6_vgtbf
4131 { 2944, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2944 = V6_vgtb_xor
4132 { 2943, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3840000000000010ULL }, // Inst #2943 = V6_vgtb_or
4133 { 2942, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2942 = V6_vgtb_and
4134 { 2941, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 323, 0, 0x3800000000008010ULL }, // Inst #2941 = V6_vgtb
4135 { 2940, 4, 0, 4, 269, 0, 1, HexagonImpOpBase + 168, 990, 0|(1ULL<<MCID::MayLoad), 0x1800180000408007ULL }, // Inst #2940 = V6_vgathermwq
4136 { 2939, 3, 0, 4, 268, 0, 1, HexagonImpOpBase + 168, 987, 0|(1ULL<<MCID::MayLoad), 0x1800180000408007ULL }, // Inst #2939 = V6_vgathermw
4137 { 2938, 4, 0, 4, 271, 0, 1, HexagonImpOpBase + 168, 997, 0|(1ULL<<MCID::MayLoad), 0x800100000408008ULL }, // Inst #2938 = V6_vgathermhwq
4138 { 2937, 3, 0, 4, 270, 0, 1, HexagonImpOpBase + 168, 994, 0|(1ULL<<MCID::MayLoad), 0x800100000408008ULL }, // Inst #2937 = V6_vgathermhw
4139 { 2936, 4, 0, 4, 269, 0, 1, HexagonImpOpBase + 168, 990, 0|(1ULL<<MCID::MayLoad), 0x1800100000408007ULL }, // Inst #2936 = V6_vgathermhq
4140 { 2935, 3, 0, 4, 268, 0, 1, HexagonImpOpBase + 168, 987, 0|(1ULL<<MCID::MayLoad), 0x1800100000408007ULL }, // Inst #2935 = V6_vgathermh
4141 { 2934, 2, 1, 4, 235, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801eULL }, // Inst #2934 = V6_vfneg_sf
4142 { 2933, 2, 1, 4, 235, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801eULL }, // Inst #2933 = V6_vfneg_hf
4143 { 2932, 3, 1, 4, 267, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801eULL }, // Inst #2932 = V6_vfmin_sf
4144 { 2931, 3, 1, 4, 267, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801eULL }, // Inst #2931 = V6_vfmin_hf
4145 { 2930, 3, 1, 4, 267, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801eULL }, // Inst #2930 = V6_vfmax_sf
4146 { 2929, 3, 1, 4, 267, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801eULL }, // Inst #2929 = V6_vfmax_hf
4147 { 2928, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2928 = V6_veqw_xor
4148 { 2927, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3840000000000010ULL }, // Inst #2927 = V6_veqw_or
4149 { 2926, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2926 = V6_veqw_and
4150 { 2925, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 323, 0, 0x3800000000008010ULL }, // Inst #2925 = V6_veqw
4151 { 2924, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2924 = V6_veqh_xor
4152 { 2923, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3840000000000010ULL }, // Inst #2923 = V6_veqh_or
4153 { 2922, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2922 = V6_veqh_and
4154 { 2921, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 323, 0, 0x3800000000008010ULL }, // Inst #2921 = V6_veqh
4155 { 2920, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2920 = V6_veqb_xor
4156 { 2919, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3840000000000010ULL }, // Inst #2919 = V6_veqb_or
4157 { 2918, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 326, 0, 0x3800000000000010ULL }, // Inst #2918 = V6_veqb_and
4158 { 2917, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 323, 0, 0x3800000000008010ULL }, // Inst #2917 = V6_veqb
4159 { 2916, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 402, 0, 0x84000000000801dULL }, // Inst #2916 = V6_vdsaduh_acc
4160 { 2915, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 406, 0, 0x80000000000801dULL }, // Inst #2915 = V6_vdsaduh
4161 { 2914, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 416, 0, 0x84000000000801dULL }, // Inst #2914 = V6_vdmpyhvsat_acc
4162 { 2913, 3, 1, 4, 266, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #2913 = V6_vdmpyhvsat
4163 { 2912, 4, 1, 4, 265, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801cULL }, // Inst #2912 = V6_vdmpyhsusat_acc
4164 { 2911, 3, 1, 4, 264, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801cULL }, // Inst #2911 = V6_vdmpyhsusat
4165 { 2910, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 409, 0, 0x84000000000801dULL }, // Inst #2910 = V6_vdmpyhsuisat_acc
4166 { 2909, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 413, 0, 0x80000000000801dULL }, // Inst #2909 = V6_vdmpyhsuisat
4167 { 2908, 4, 1, 4, 265, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801cULL }, // Inst #2908 = V6_vdmpyhsat_acc
4168 { 2907, 3, 1, 4, 264, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801cULL }, // Inst #2907 = V6_vdmpyhsat
4169 { 2906, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 409, 0, 0x84000000000801dULL }, // Inst #2906 = V6_vdmpyhisat_acc
4170 { 2905, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 413, 0, 0x80000000000801dULL }, // Inst #2905 = V6_vdmpyhisat
4171 { 2904, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 402, 0, 0x84000000000801dULL }, // Inst #2904 = V6_vdmpyhb_dv_acc
4172 { 2903, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 406, 0, 0x80000000000801dULL }, // Inst #2903 = V6_vdmpyhb_dv
4173 { 2902, 4, 1, 4, 261, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801cULL }, // Inst #2902 = V6_vdmpyhb_acc
4174 { 2901, 3, 1, 4, 260, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801cULL }, // Inst #2901 = V6_vdmpyhb
4175 { 2900, 4, 1, 4, 263, 0, 0, HexagonImpOpBase + 0, 402, 0, 0x84000000000801dULL }, // Inst #2900 = V6_vdmpybus_dv_acc
4176 { 2899, 3, 1, 4, 262, 0, 0, HexagonImpOpBase + 0, 406, 0, 0x80000000000801dULL }, // Inst #2899 = V6_vdmpybus_dv
4177 { 2898, 4, 1, 4, 261, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801cULL }, // Inst #2898 = V6_vdmpybus_acc
4178 { 2897, 3, 1, 4, 260, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801cULL }, // Inst #2897 = V6_vdmpybus
4179 { 2896, 4, 1, 4, 259, 0, 0, HexagonImpOpBase + 0, 416, 0, 0x84000000000801cULL }, // Inst #2896 = V6_vdmpy_sf_hf_acc
4180 { 2895, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #2895 = V6_vdmpy_sf_hf
4181 { 2894, 3, 1, 4, 257, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x800000000008018ULL }, // Inst #2894 = V6_vdelta
4182 { 2893, 4, 1, 4, 258, 0, 0, HexagonImpOpBase + 0, 983, 0, 0x800000000008019ULL }, // Inst #2893 = V6_vdealvdd
4183 { 2892, 2, 1, 4, 256, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x800000000008018ULL }, // Inst #2892 = V6_vdealh
4184 { 2891, 3, 1, 4, 257, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x800000000008018ULL }, // Inst #2891 = V6_vdealb4w
4185 { 2890, 2, 1, 4, 256, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x800000000008018ULL }, // Inst #2890 = V6_vdealb
4186 { 2889, 5, 2, 4, 255, 0, 0, HexagonImpOpBase + 0, 485, 0, 0x80c000000008019ULL }, // Inst #2889 = V6_vdeal
4187 { 2888, 2, 1, 4, 253, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801cULL }, // Inst #2888 = V6_vcvt_uh_hf
4188 { 2887, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #2887 = V6_vcvt_ub_hf
4189 { 2886, 2, 1, 4, 254, 0, 0, HexagonImpOpBase + 0, 465, 0, 0x80000000000801dULL }, // Inst #2886 = V6_vcvt_sf_hf
4190 { 2885, 2, 1, 4, 253, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801cULL }, // Inst #2885 = V6_vcvt_hf_uh
4191 { 2884, 2, 1, 4, 254, 0, 0, HexagonImpOpBase + 0, 465, 0, 0x80000000000801dULL }, // Inst #2884 = V6_vcvt_hf_ub
4192 { 2883, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #2883 = V6_vcvt_hf_sf
4193 { 2882, 2, 1, 4, 253, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801cULL }, // Inst #2882 = V6_vcvt_hf_h
4194 { 2881, 2, 1, 4, 254, 0, 0, HexagonImpOpBase + 0, 465, 0, 0x80000000000801dULL }, // Inst #2881 = V6_vcvt_hf_b
4195 { 2880, 2, 1, 4, 253, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801cULL }, // Inst #2880 = V6_vcvt_h_hf
4196 { 2879, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #2879 = V6_vcvt_bf_sf
4197 { 2878, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #2878 = V6_vcvt_b_hf
4198 { 2877, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801aULL }, // Inst #2877 = V6_vconv_w_sf
4199 { 2876, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801aULL }, // Inst #2876 = V6_vconv_sf_w
4200 { 2875, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801aULL }, // Inst #2875 = V6_vconv_sf_qf32
4201 { 2874, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 337, 0, 0x80000000000801aULL }, // Inst #2874 = V6_vconv_hf_qf32
4202 { 2873, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801aULL }, // Inst #2873 = V6_vconv_hf_qf16
4203 { 2872, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801aULL }, // Inst #2872 = V6_vconv_hf_h
4204 { 2871, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801aULL }, // Inst #2871 = V6_vconv_h_hf
4205 { 2870, 3, 1, 4, 252, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x90000000000801cULL }, // Inst #2870 = V6_vcombine_tmp
4206 { 2869, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::RegSequence), 0x800000000008011ULL }, // Inst #2869 = V6_vcombine
4207 { 2868, 3, 1, 4, 44, 0, 0, HexagonImpOpBase + 0, 980, 0, 0x1800000000008410ULL }, // Inst #2868 = V6_vcmov
4208 { 2867, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801aULL }, // Inst #2867 = V6_vcl0w
4209 { 2866, 2, 1, 4, 251, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801aULL }, // Inst #2866 = V6_vcl0h
4210 { 2865, 4, 1, 4, 47, 0, 0, HexagonImpOpBase + 0, 976, 0, 0x800000000008411ULL }, // Inst #2865 = V6_vccombine
4211 { 2864, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2864 = V6_vavgwrnd
4212 { 2863, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2863 = V6_vavgw
4213 { 2862, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2862 = V6_vavguwrnd
4214 { 2861, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2861 = V6_vavguw
4215 { 2860, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2860 = V6_vavguhrnd
4216 { 2859, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2859 = V6_vavguh
4217 { 2858, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2858 = V6_vavgubrnd
4218 { 2857, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2857 = V6_vavgub
4219 { 2856, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2856 = V6_vavghrnd
4220 { 2855, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2855 = V6_vavgh
4221 { 2854, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2854 = V6_vavgbrnd
4222 { 2853, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2853 = V6_vavgb
4223 { 2852, 2, 1, 4, 250, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x90000000000801cULL }, // Inst #2852 = V6_vassign_tmp
4224 { 2851, 2, 1, 4, 235, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801eULL }, // Inst #2851 = V6_vassign_fp
4225 { 2850, 2, 1, 4, 63, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x1800000000008010ULL }, // Inst #2850 = V6_vassign
4226 { 2849, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2849 = V6_vasrwv
4227 { 2848, 4, 1, 4, 249, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x80000000000801aULL }, // Inst #2848 = V6_vasrwuhsat
4228 { 2847, 4, 1, 4, 249, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x80000000000801aULL }, // Inst #2847 = V6_vasrwuhrndsat
4229 { 2846, 4, 1, 4, 249, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x80000000000801aULL }, // Inst #2846 = V6_vasrwhsat
4230 { 2845, 4, 1, 4, 249, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x80000000000801aULL }, // Inst #2845 = V6_vasrwhrndsat
4231 { 2844, 4, 1, 4, 249, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x80000000000801aULL }, // Inst #2844 = V6_vasrwh
4232 { 2843, 4, 1, 4, 247, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801aULL }, // Inst #2843 = V6_vasrw_acc
4233 { 2842, 3, 1, 4, 246, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801aULL }, // Inst #2842 = V6_vasrw
4234 { 2841, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 973, 0, 0x480000000000801aULL }, // Inst #2841 = V6_vasrvwuhsat
4235 { 2840, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 973, 0, 0x480000000000801aULL }, // Inst #2840 = V6_vasrvwuhrndsat
4236 { 2839, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 973, 0, 0x480000000000801aULL }, // Inst #2839 = V6_vasrvuhubsat
4237 { 2838, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 973, 0, 0x480000000000801aULL }, // Inst #2838 = V6_vasrvuhubrndsat
4238 { 2837, 4, 1, 4, 249, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x80000000000801aULL }, // Inst #2837 = V6_vasruwuhsat
4239 { 2836, 4, 1, 4, 249, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x80000000000801aULL }, // Inst #2836 = V6_vasruwuhrndsat
4240 { 2835, 4, 1, 4, 249, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x80000000000801aULL }, // Inst #2835 = V6_vasruhubsat
4241 { 2834, 4, 1, 4, 249, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x80000000000801aULL }, // Inst #2834 = V6_vasruhubrndsat
4242 { 2833, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2833 = V6_vasrhv
4243 { 2832, 4, 1, 4, 249, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x80000000000801aULL }, // Inst #2832 = V6_vasrhubsat
4244 { 2831, 4, 1, 4, 249, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x80000000000801aULL }, // Inst #2831 = V6_vasrhubrndsat
4245 { 2830, 4, 1, 4, 249, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x80000000000801aULL }, // Inst #2830 = V6_vasrhbsat
4246 { 2829, 4, 1, 4, 249, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x80000000000801aULL }, // Inst #2829 = V6_vasrhbrndsat
4247 { 2828, 4, 1, 4, 247, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801aULL }, // Inst #2828 = V6_vasrh_acc
4248 { 2827, 3, 1, 4, 246, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801aULL }, // Inst #2827 = V6_vasrh
4249 { 2826, 4, 1, 4, 248, 0, 0, HexagonImpOpBase + 0, 371, 0, 0x800000000008019ULL }, // Inst #2826 = V6_vasr_into
4250 { 2825, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2825 = V6_vaslwv
4251 { 2824, 4, 1, 4, 247, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801aULL }, // Inst #2824 = V6_vaslw_acc
4252 { 2823, 3, 1, 4, 246, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801aULL }, // Inst #2823 = V6_vaslw
4253 { 2822, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2822 = V6_vaslhv
4254 { 2821, 4, 1, 4, 247, 0, 0, HexagonImpOpBase + 0, 392, 0, 0x84000000000801aULL }, // Inst #2821 = V6_vaslh_acc
4255 { 2820, 3, 1, 4, 246, 0, 0, HexagonImpOpBase + 0, 396, 0, 0x80000000000801aULL }, // Inst #2820 = V6_vaslh
4256 { 2819, 4, 1, 4, 245, 0, 0, HexagonImpOpBase + 0, 385, 0, 0x84000000000001eULL }, // Inst #2819 = V6_vandvrt_acc
4257 { 2818, 3, 1, 4, 244, 0, 0, HexagonImpOpBase + 0, 389, 0, 0x80000000000801eULL }, // Inst #2818 = V6_vandvrt
4258 { 2817, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 970, 0, 0x3800000000008010ULL }, // Inst #2817 = V6_vandvqv
4259 { 2816, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 970, 0, 0x3800000000008010ULL }, // Inst #2816 = V6_vandvnqv
4260 { 2815, 4, 1, 4, 245, 0, 0, HexagonImpOpBase + 0, 378, 0, 0x84000000000801eULL }, // Inst #2815 = V6_vandqrt_acc
4261 { 2814, 3, 1, 4, 244, 0, 0, HexagonImpOpBase + 0, 382, 0, 0x80000000000801eULL }, // Inst #2814 = V6_vandqrt
4262 { 2813, 4, 1, 4, 245, 0, 0, HexagonImpOpBase + 0, 378, 0, 0x84000000000801eULL }, // Inst #2813 = V6_vandnqrt_acc
4263 { 2812, 3, 1, 4, 244, 0, 0, HexagonImpOpBase + 0, 382, 0, 0x80000000000801eULL }, // Inst #2812 = V6_vandnqrt
4264 { 2811, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2811 = V6_vand
4265 { 2810, 4, 1, 4, 243, 0, 0, HexagonImpOpBase + 0, 966, 0, 0x800000000008018ULL }, // Inst #2810 = V6_valignbi
4266 { 2809, 4, 1, 4, 243, 0, 0, HexagonImpOpBase + 0, 962, 0, 0x800000000008018ULL }, // Inst #2809 = V6_valignb
4267 { 2808, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #2808 = V6_vaddwsat_dv
4268 { 2807, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2807 = V6_vaddwsat
4269 { 2806, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 367, 0, 0x3840000000008010ULL }, // Inst #2806 = V6_vaddwq
4270 { 2805, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 367, 0, 0x3840000000008010ULL }, // Inst #2805 = V6_vaddwnq
4271 { 2804, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #2804 = V6_vaddw_dv
4272 { 2803, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2803 = V6_vaddw
4273 { 2802, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #2802 = V6_vadduwsat_dv
4274 { 2801, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2801 = V6_vadduwsat
4275 { 2800, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 371, 0, 0x84000000000801dULL }, // Inst #2800 = V6_vadduhw_acc
4276 { 2799, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #2799 = V6_vadduhw
4277 { 2798, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #2798 = V6_vadduhsat_dv
4278 { 2797, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2797 = V6_vadduhsat
4279 { 2796, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2796 = V6_vaddububb_sat
4280 { 2795, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #2795 = V6_vaddubsat_dv
4281 { 2794, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2794 = V6_vaddubsat
4282 { 2793, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 371, 0, 0x84000000000801dULL }, // Inst #2793 = V6_vaddubh_acc
4283 { 2792, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #2792 = V6_vaddubh
4284 { 2791, 4, 1, 4, 242, 0, 0, HexagonImpOpBase + 0, 371, 0, 0x84000000000801dULL }, // Inst #2791 = V6_vaddhw_acc
4285 { 2790, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #2790 = V6_vaddhw
4286 { 2789, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #2789 = V6_vaddhsat_dv
4287 { 2788, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2788 = V6_vaddhsat
4288 { 2787, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 367, 0, 0x3840000000008010ULL }, // Inst #2787 = V6_vaddhq
4289 { 2786, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 367, 0, 0x3840000000008010ULL }, // Inst #2786 = V6_vaddhnq
4290 { 2785, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #2785 = V6_vaddh_dv
4291 { 2784, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2784 = V6_vaddh
4292 { 2783, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2783 = V6_vaddclbw
4293 { 2782, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2782 = V6_vaddclbh
4294 { 2781, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 958, 0, 0x3800000000008010ULL }, // Inst #2781 = V6_vaddcarrysat
4295 { 2780, 4, 2, 4, 241, 0, 0, HexagonImpOpBase + 0, 954, 0, 0x3800000000008010ULL }, // Inst #2780 = V6_vaddcarryo
4296 { 2779, 5, 2, 4, 240, 0, 0, HexagonImpOpBase + 0, 949, 0, 0x3800000000008010ULL }, // Inst #2779 = V6_vaddcarry
4297 { 2778, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #2778 = V6_vaddbsat_dv
4298 { 2777, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2777 = V6_vaddbsat
4299 { 2776, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 367, 0, 0x3840000000008010ULL }, // Inst #2776 = V6_vaddbq
4300 { 2775, 4, 1, 4, 239, 0, 0, HexagonImpOpBase + 0, 367, 0, 0x3840000000008010ULL }, // Inst #2775 = V6_vaddbnq
4301 { 2774, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 364, 0, 0x800000000008011ULL }, // Inst #2774 = V6_vaddb_dv
4302 { 2773, 3, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x3800000000008010ULL }, // Inst #2773 = V6_vaddb
4303 { 2772, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #2772 = V6_vadd_sf_sf
4304 { 2771, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #2771 = V6_vadd_sf_hf
4305 { 2770, 3, 1, 4, 238, 0, 0, HexagonImpOpBase + 0, 375, 0, 0x80000000000801dULL }, // Inst #2770 = V6_vadd_sf_bf
4306 { 2769, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2769 = V6_vadd_sf
4307 { 2768, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2768 = V6_vadd_qf32_mix
4308 { 2767, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2767 = V6_vadd_qf32
4309 { 2766, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2766 = V6_vadd_qf16_mix
4310 { 2765, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2765 = V6_vadd_qf16
4311 { 2764, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #2764 = V6_vadd_hf_hf
4312 { 2763, 3, 1, 4, 237, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801aULL }, // Inst #2763 = V6_vadd_hf
4313 { 2762, 2, 1, 4, 63, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x3800000000008010ULL }, // Inst #2762 = V6_vabsw_sat
4314 { 2761, 2, 1, 4, 63, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x3800000000008010ULL }, // Inst #2761 = V6_vabsw
4315 { 2760, 2, 1, 4, 63, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x3800000000008010ULL }, // Inst #2760 = V6_vabsh_sat
4316 { 2759, 2, 1, 4, 63, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x3800000000008010ULL }, // Inst #2759 = V6_vabsh
4317 { 2758, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #2758 = V6_vabsdiffw
4318 { 2757, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #2757 = V6_vabsdiffuh
4319 { 2756, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #2756 = V6_vabsdiffub
4320 { 2755, 3, 1, 4, 236, 0, 0, HexagonImpOpBase + 0, 361, 0, 0x80000000000801cULL }, // Inst #2755 = V6_vabsdiffh
4321 { 2754, 2, 1, 4, 63, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x3800000000008010ULL }, // Inst #2754 = V6_vabsb_sat
4322 { 2753, 2, 1, 4, 63, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x3800000000008010ULL }, // Inst #2753 = V6_vabsb
4323 { 2752, 2, 1, 4, 235, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801eULL }, // Inst #2752 = V6_vabs_sf
4324 { 2751, 2, 1, 4, 235, 0, 0, HexagonImpOpBase + 0, 359, 0, 0x80000000000801eULL }, // Inst #2751 = V6_vabs_hf
4325 { 2750, 3, 1, 4, 234, 0, 0, HexagonImpOpBase + 0, 946, 0|(1ULL<<MCID::MayStore), 0xc002e000000000dULL }, // Inst #2750 = V6_vS32b_srls_ppu
4326 { 2749, 3, 1, 4, 234, 0, 0, HexagonImpOpBase + 0, 507, 0|(1ULL<<MCID::MayStore), 0xc002e000000000dULL }, // Inst #2749 = V6_vS32b_srls_pi
4327 { 2748, 2, 0, 4, 233, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::MayStore), 0xc002b000000000dULL }, // Inst #2748 = V6_vS32b_srls_ai
4328 { 2747, 5, 1, 4, 231, 0, 0, HexagonImpOpBase + 0, 941, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2747 = V6_vS32b_qpred_ppu
4329 { 2746, 5, 1, 4, 231, 0, 0, HexagonImpOpBase + 0, 936, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2746 = V6_vS32b_qpred_pi
4330 { 2745, 4, 0, 4, 230, 0, 0, HexagonImpOpBase + 0, 932, 0|(1ULL<<MCID::MayStore), 0x18002b0000000014ULL }, // Inst #2745 = V6_vS32b_qpred_ai
4331 { 2744, 5, 1, 4, 229, 0, 0, HexagonImpOpBase + 0, 919, 0|(1ULL<<MCID::MayStore), 0x18002e0000080414ULL }, // Inst #2744 = V6_vS32b_pred_ppu
4332 { 2743, 5, 1, 4, 229, 0, 0, HexagonImpOpBase + 0, 914, 0|(1ULL<<MCID::MayStore), 0x18002e0000080414ULL }, // Inst #2743 = V6_vS32b_pred_pi
4333 { 2742, 4, 0, 4, 228, 0, 0, HexagonImpOpBase + 0, 910, 0|(1ULL<<MCID::MayStore), 0x18002b0000080414ULL }, // Inst #2742 = V6_vS32b_pred_ai
4334 { 2741, 4, 1, 4, 232, 0, 0, HexagonImpOpBase + 0, 928, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18002e0000080014ULL }, // Inst #2741 = V6_vS32b_ppu
4335 { 2740, 4, 1, 4, 232, 0, 0, HexagonImpOpBase + 0, 924, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18002e0000080014ULL }, // Inst #2740 = V6_vS32b_pi
4336 { 2739, 5, 1, 4, 231, 0, 0, HexagonImpOpBase + 0, 941, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2739 = V6_vS32b_nt_qpred_ppu
4337 { 2738, 5, 1, 4, 231, 0, 0, HexagonImpOpBase + 0, 936, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2738 = V6_vS32b_nt_qpred_pi
4338 { 2737, 4, 0, 4, 230, 0, 0, HexagonImpOpBase + 0, 932, 0|(1ULL<<MCID::MayStore), 0x18002b0000000014ULL }, // Inst #2737 = V6_vS32b_nt_qpred_ai
4339 { 2736, 5, 1, 4, 229, 0, 0, HexagonImpOpBase + 0, 919, 0|(1ULL<<MCID::MayStore), 0x18002e0000080414ULL }, // Inst #2736 = V6_vS32b_nt_pred_ppu
4340 { 2735, 5, 1, 4, 229, 0, 0, HexagonImpOpBase + 0, 914, 0|(1ULL<<MCID::MayStore), 0x18002e0000080414ULL }, // Inst #2735 = V6_vS32b_nt_pred_pi
4341 { 2734, 4, 0, 4, 228, 0, 0, HexagonImpOpBase + 0, 910, 0|(1ULL<<MCID::MayStore), 0x18002b0000080414ULL }, // Inst #2734 = V6_vS32b_nt_pred_ai
4342 { 2733, 4, 1, 4, 232, 0, 0, HexagonImpOpBase + 0, 928, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18002e0000080014ULL }, // Inst #2733 = V6_vS32b_nt_ppu
4343 { 2732, 4, 1, 4, 232, 0, 0, HexagonImpOpBase + 0, 924, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18002e0000080014ULL }, // Inst #2732 = V6_vS32b_nt_pi
4344 { 2731, 5, 1, 4, 231, 0, 0, HexagonImpOpBase + 0, 941, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2731 = V6_vS32b_nt_nqpred_ppu
4345 { 2730, 5, 1, 4, 231, 0, 0, HexagonImpOpBase + 0, 936, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2730 = V6_vS32b_nt_nqpred_pi
4346 { 2729, 4, 0, 4, 230, 0, 0, HexagonImpOpBase + 0, 932, 0|(1ULL<<MCID::MayStore), 0x18002b0000000014ULL }, // Inst #2729 = V6_vS32b_nt_nqpred_ai
4347 { 2728, 5, 1, 4, 229, 0, 0, HexagonImpOpBase + 0, 919, 0|(1ULL<<MCID::MayStore), 0x18002e0000080c14ULL }, // Inst #2728 = V6_vS32b_nt_npred_ppu
4348 { 2727, 5, 1, 4, 229, 0, 0, HexagonImpOpBase + 0, 914, 0|(1ULL<<MCID::MayStore), 0x18002e0000080c14ULL }, // Inst #2727 = V6_vS32b_nt_npred_pi
4349 { 2726, 4, 0, 4, 228, 0, 0, HexagonImpOpBase + 0, 910, 0|(1ULL<<MCID::MayStore), 0x18002b0000080c14ULL }, // Inst #2726 = V6_vS32b_nt_npred_ai
4350 { 2725, 5, 1, 4, 226, 0, 0, HexagonImpOpBase + 0, 919, 0|(1ULL<<MCID::MayStore), 0xc002e0000144413ULL }, // Inst #2725 = V6_vS32b_nt_new_pred_ppu
4351 { 2724, 5, 1, 4, 226, 0, 0, HexagonImpOpBase + 0, 914, 0|(1ULL<<MCID::MayStore), 0xc002e0000144413ULL }, // Inst #2724 = V6_vS32b_nt_new_pred_pi
4352 { 2723, 4, 0, 4, 225, 0, 0, HexagonImpOpBase + 0, 910, 0|(1ULL<<MCID::MayStore), 0xc002b0000134413ULL }, // Inst #2723 = V6_vS32b_nt_new_pred_ai
4353 { 2722, 4, 1, 4, 227, 0, 0, HexagonImpOpBase + 0, 928, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc002e0000134013ULL }, // Inst #2722 = V6_vS32b_nt_new_ppu
4354 { 2721, 4, 1, 4, 227, 0, 0, HexagonImpOpBase + 0, 924, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc002e0000134013ULL }, // Inst #2721 = V6_vS32b_nt_new_pi
4355 { 2720, 5, 1, 4, 226, 0, 0, HexagonImpOpBase + 0, 919, 0|(1ULL<<MCID::MayStore), 0xc002e0000144c13ULL }, // Inst #2720 = V6_vS32b_nt_new_npred_ppu
4356 { 2719, 5, 1, 4, 226, 0, 0, HexagonImpOpBase + 0, 914, 0|(1ULL<<MCID::MayStore), 0xc002e0000144c13ULL }, // Inst #2719 = V6_vS32b_nt_new_npred_pi
4357 { 2718, 4, 0, 4, 225, 0, 0, HexagonImpOpBase + 0, 910, 0|(1ULL<<MCID::MayStore), 0xc002b0000134c13ULL }, // Inst #2718 = V6_vS32b_nt_new_npred_ai
4358 { 2717, 3, 0, 4, 224, 0, 0, HexagonImpOpBase + 0, 294, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc002b0000124013ULL }, // Inst #2717 = V6_vS32b_nt_new_ai
4359 { 2716, 3, 0, 4, 46, 0, 0, HexagonImpOpBase + 0, 294, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18002b0000080014ULL }, // Inst #2716 = V6_vS32b_nt_ai
4360 { 2715, 5, 1, 4, 231, 0, 0, HexagonImpOpBase + 0, 941, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2715 = V6_vS32b_nqpred_ppu
4361 { 2714, 5, 1, 4, 231, 0, 0, HexagonImpOpBase + 0, 936, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2714 = V6_vS32b_nqpred_pi
4362 { 2713, 4, 0, 4, 230, 0, 0, HexagonImpOpBase + 0, 932, 0|(1ULL<<MCID::MayStore), 0x18002b0000000014ULL }, // Inst #2713 = V6_vS32b_nqpred_ai
4363 { 2712, 5, 1, 4, 229, 0, 0, HexagonImpOpBase + 0, 919, 0|(1ULL<<MCID::MayStore), 0x18002e0000080c14ULL }, // Inst #2712 = V6_vS32b_npred_ppu
4364 { 2711, 5, 1, 4, 229, 0, 0, HexagonImpOpBase + 0, 914, 0|(1ULL<<MCID::MayStore), 0x18002e0000080c14ULL }, // Inst #2711 = V6_vS32b_npred_pi
4365 { 2710, 4, 0, 4, 228, 0, 0, HexagonImpOpBase + 0, 910, 0|(1ULL<<MCID::MayStore), 0x18002b0000080c14ULL }, // Inst #2710 = V6_vS32b_npred_ai
4366 { 2709, 5, 1, 4, 226, 0, 0, HexagonImpOpBase + 0, 919, 0|(1ULL<<MCID::MayStore), 0xc002e0000144413ULL }, // Inst #2709 = V6_vS32b_new_pred_ppu
4367 { 2708, 5, 1, 4, 226, 0, 0, HexagonImpOpBase + 0, 914, 0|(1ULL<<MCID::MayStore), 0xc002e0000144413ULL }, // Inst #2708 = V6_vS32b_new_pred_pi
4368 { 2707, 4, 0, 4, 225, 0, 0, HexagonImpOpBase + 0, 910, 0|(1ULL<<MCID::MayStore), 0xc002b0000134413ULL }, // Inst #2707 = V6_vS32b_new_pred_ai
4369 { 2706, 4, 1, 4, 227, 0, 0, HexagonImpOpBase + 0, 928, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc002e0000134013ULL }, // Inst #2706 = V6_vS32b_new_ppu
4370 { 2705, 4, 1, 4, 227, 0, 0, HexagonImpOpBase + 0, 924, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc002e0000134013ULL }, // Inst #2705 = V6_vS32b_new_pi
4371 { 2704, 5, 1, 4, 226, 0, 0, HexagonImpOpBase + 0, 919, 0|(1ULL<<MCID::MayStore), 0xc002e0000144c13ULL }, // Inst #2704 = V6_vS32b_new_npred_ppu
4372 { 2703, 5, 1, 4, 226, 0, 0, HexagonImpOpBase + 0, 914, 0|(1ULL<<MCID::MayStore), 0xc002e0000144c13ULL }, // Inst #2703 = V6_vS32b_new_npred_pi
4373 { 2702, 4, 0, 4, 225, 0, 0, HexagonImpOpBase + 0, 910, 0|(1ULL<<MCID::MayStore), 0xc002b0000134c13ULL }, // Inst #2702 = V6_vS32b_new_npred_ai
4374 { 2701, 3, 0, 4, 224, 0, 0, HexagonImpOpBase + 0, 294, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc002b0000124013ULL }, // Inst #2701 = V6_vS32b_new_ai
4375 { 2700, 3, 0, 4, 46, 0, 0, HexagonImpOpBase + 0, 294, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18002b0000080014ULL }, // Inst #2700 = V6_vS32b_ai
4376 { 2699, 5, 1, 4, 222, 0, 0, HexagonImpOpBase + 0, 919, 0|(1ULL<<MCID::MayStore), 0x8002e0000000415ULL }, // Inst #2699 = V6_vS32Ub_pred_ppu
4377 { 2698, 5, 1, 4, 222, 0, 0, HexagonImpOpBase + 0, 914, 0|(1ULL<<MCID::MayStore), 0x8002e0000000415ULL }, // Inst #2698 = V6_vS32Ub_pred_pi
4378 { 2697, 4, 0, 4, 221, 0, 0, HexagonImpOpBase + 0, 910, 0|(1ULL<<MCID::MayStore), 0x8002b0000000415ULL }, // Inst #2697 = V6_vS32Ub_pred_ai
4379 { 2696, 4, 1, 4, 223, 0, 0, HexagonImpOpBase + 0, 928, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x8002e0000000015ULL }, // Inst #2696 = V6_vS32Ub_ppu
4380 { 2695, 4, 1, 4, 223, 0, 0, HexagonImpOpBase + 0, 924, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x8002e0000000015ULL }, // Inst #2695 = V6_vS32Ub_pi
4381 { 2694, 5, 1, 4, 222, 0, 0, HexagonImpOpBase + 0, 919, 0|(1ULL<<MCID::MayStore), 0x8002e0000000c15ULL }, // Inst #2694 = V6_vS32Ub_npred_ppu
4382 { 2693, 5, 1, 4, 222, 0, 0, HexagonImpOpBase + 0, 914, 0|(1ULL<<MCID::MayStore), 0x8002e0000000c15ULL }, // Inst #2693 = V6_vS32Ub_npred_pi
4383 { 2692, 4, 0, 4, 221, 0, 0, HexagonImpOpBase + 0, 910, 0|(1ULL<<MCID::MayStore), 0x8002b0000000c15ULL }, // Inst #2692 = V6_vS32Ub_npred_ai
4384 { 2691, 3, 0, 4, 220, 0, 0, HexagonImpOpBase + 0, 294, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x8002b0000000015ULL }, // Inst #2691 = V6_vS32Ub_ai
4385 { 2690, 5, 2, 4, 218, 0, 0, HexagonImpOpBase + 0, 905, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408416ULL }, // Inst #2690 = V6_vL32b_tmp_pred_ppu
4386 { 2689, 5, 2, 4, 218, 0, 0, HexagonImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408416ULL }, // Inst #2689 = V6_vL32b_tmp_pred_pi
4387 { 2688, 4, 1, 4, 217, 0, 0, HexagonImpOpBase + 0, 896, 0|(1ULL<<MCID::MayLoad), 0x9002b8000408416ULL }, // Inst #2688 = V6_vL32b_tmp_pred_ai
4388 { 2687, 4, 2, 4, 219, 0, 0, HexagonImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9002e8000408016ULL }, // Inst #2687 = V6_vL32b_tmp_ppu
4389 { 2686, 4, 2, 4, 219, 0, 0, HexagonImpOpBase + 0, 888, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9002e8000408016ULL }, // Inst #2686 = V6_vL32b_tmp_pi
4390 { 2685, 5, 2, 4, 218, 0, 0, HexagonImpOpBase + 0, 905, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408c16ULL }, // Inst #2685 = V6_vL32b_tmp_npred_ppu
4391 { 2684, 5, 2, 4, 218, 0, 0, HexagonImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408c16ULL }, // Inst #2684 = V6_vL32b_tmp_npred_pi
4392 { 2683, 4, 1, 4, 217, 0, 0, HexagonImpOpBase + 0, 896, 0|(1ULL<<MCID::MayLoad), 0x9002b8000408c16ULL }, // Inst #2683 = V6_vL32b_tmp_npred_ai
4393 { 2682, 3, 1, 4, 216, 0, 0, HexagonImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9002b8000408016ULL }, // Inst #2682 = V6_vL32b_tmp_ai
4394 { 2681, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 905, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408412ULL }, // Inst #2681 = V6_vL32b_pred_ppu
4395 { 2680, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408412ULL }, // Inst #2680 = V6_vL32b_pred_pi
4396 { 2679, 4, 1, 4, 213, 0, 0, HexagonImpOpBase + 0, 896, 0|(1ULL<<MCID::MayLoad), 0x18002b8000408412ULL }, // Inst #2679 = V6_vL32b_pred_ai
4397 { 2678, 4, 2, 4, 215, 0, 0, HexagonImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18002e8000608012ULL }, // Inst #2678 = V6_vL32b_ppu
4398 { 2677, 4, 2, 4, 215, 0, 0, HexagonImpOpBase + 0, 888, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18002e8000608012ULL }, // Inst #2677 = V6_vL32b_pi
4399 { 2676, 5, 2, 4, 218, 0, 0, HexagonImpOpBase + 0, 905, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408416ULL }, // Inst #2676 = V6_vL32b_nt_tmp_pred_ppu
4400 { 2675, 5, 2, 4, 218, 0, 0, HexagonImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408416ULL }, // Inst #2675 = V6_vL32b_nt_tmp_pred_pi
4401 { 2674, 4, 1, 4, 217, 0, 0, HexagonImpOpBase + 0, 896, 0|(1ULL<<MCID::MayLoad), 0x9002b8000408416ULL }, // Inst #2674 = V6_vL32b_nt_tmp_pred_ai
4402 { 2673, 4, 2, 4, 219, 0, 0, HexagonImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9002e8000408016ULL }, // Inst #2673 = V6_vL32b_nt_tmp_ppu
4403 { 2672, 4, 2, 4, 219, 0, 0, HexagonImpOpBase + 0, 888, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9002e8000408016ULL }, // Inst #2672 = V6_vL32b_nt_tmp_pi
4404 { 2671, 5, 2, 4, 218, 0, 0, HexagonImpOpBase + 0, 905, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408c16ULL }, // Inst #2671 = V6_vL32b_nt_tmp_npred_ppu
4405 { 2670, 5, 2, 4, 218, 0, 0, HexagonImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408c16ULL }, // Inst #2670 = V6_vL32b_nt_tmp_npred_pi
4406 { 2669, 4, 1, 4, 217, 0, 0, HexagonImpOpBase + 0, 896, 0|(1ULL<<MCID::MayLoad), 0x9002b8000408c16ULL }, // Inst #2669 = V6_vL32b_nt_tmp_npred_ai
4407 { 2668, 3, 1, 4, 216, 0, 0, HexagonImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9002b8000408016ULL }, // Inst #2668 = V6_vL32b_nt_tmp_ai
4408 { 2667, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 905, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408412ULL }, // Inst #2667 = V6_vL32b_nt_pred_ppu
4409 { 2666, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408412ULL }, // Inst #2666 = V6_vL32b_nt_pred_pi
4410 { 2665, 4, 1, 4, 213, 0, 0, HexagonImpOpBase + 0, 896, 0|(1ULL<<MCID::MayLoad), 0x18002b8000408412ULL }, // Inst #2665 = V6_vL32b_nt_pred_ai
4411 { 2664, 4, 2, 4, 215, 0, 0, HexagonImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18002e8000608012ULL }, // Inst #2664 = V6_vL32b_nt_ppu
4412 { 2663, 4, 2, 4, 215, 0, 0, HexagonImpOpBase + 0, 888, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18002e8000608012ULL }, // Inst #2663 = V6_vL32b_nt_pi
4413 { 2662, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 905, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408c12ULL }, // Inst #2662 = V6_vL32b_nt_npred_ppu
4414 { 2661, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408c12ULL }, // Inst #2661 = V6_vL32b_nt_npred_pi
4415 { 2660, 4, 1, 4, 213, 0, 0, HexagonImpOpBase + 0, 896, 0|(1ULL<<MCID::MayLoad), 0x18002b8000408c12ULL }, // Inst #2660 = V6_vL32b_nt_npred_ai
4416 { 2659, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 905, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408412ULL }, // Inst #2659 = V6_vL32b_nt_cur_pred_ppu
4417 { 2658, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408412ULL }, // Inst #2658 = V6_vL32b_nt_cur_pred_pi
4418 { 2657, 4, 1, 4, 213, 0, 0, HexagonImpOpBase + 0, 896, 0|(1ULL<<MCID::MayLoad), 0x1c002b8000408412ULL }, // Inst #2657 = V6_vL32b_nt_cur_pred_ai
4419 { 2656, 4, 2, 4, 215, 0, 0, HexagonImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1c002e8000408012ULL }, // Inst #2656 = V6_vL32b_nt_cur_ppu
4420 { 2655, 4, 2, 4, 215, 0, 0, HexagonImpOpBase + 0, 888, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1c002e8000408012ULL }, // Inst #2655 = V6_vL32b_nt_cur_pi
4421 { 2654, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 905, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408c12ULL }, // Inst #2654 = V6_vL32b_nt_cur_npred_ppu
4422 { 2653, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408c12ULL }, // Inst #2653 = V6_vL32b_nt_cur_npred_pi
4423 { 2652, 4, 1, 4, 213, 0, 0, HexagonImpOpBase + 0, 896, 0|(1ULL<<MCID::MayLoad), 0x1c002b8000408c12ULL }, // Inst #2652 = V6_vL32b_nt_cur_npred_ai
4424 { 2651, 3, 1, 4, 42, 0, 0, HexagonImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1c002b8000408012ULL }, // Inst #2651 = V6_vL32b_nt_cur_ai
4425 { 2650, 3, 1, 4, 42, 0, 0, HexagonImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18002b8000608012ULL }, // Inst #2650 = V6_vL32b_nt_ai
4426 { 2649, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 905, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408c12ULL }, // Inst #2649 = V6_vL32b_npred_ppu
4427 { 2648, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408c12ULL }, // Inst #2648 = V6_vL32b_npred_pi
4428 { 2647, 4, 1, 4, 213, 0, 0, HexagonImpOpBase + 0, 896, 0|(1ULL<<MCID::MayLoad), 0x18002b8000408c12ULL }, // Inst #2647 = V6_vL32b_npred_ai
4429 { 2646, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 905, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408412ULL }, // Inst #2646 = V6_vL32b_cur_pred_ppu
4430 { 2645, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408412ULL }, // Inst #2645 = V6_vL32b_cur_pred_pi
4431 { 2644, 4, 1, 4, 213, 0, 0, HexagonImpOpBase + 0, 896, 0|(1ULL<<MCID::MayLoad), 0x1c002b8000408412ULL }, // Inst #2644 = V6_vL32b_cur_pred_ai
4432 { 2643, 4, 2, 4, 215, 0, 0, HexagonImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1c002e8000408012ULL }, // Inst #2643 = V6_vL32b_cur_ppu
4433 { 2642, 4, 2, 4, 215, 0, 0, HexagonImpOpBase + 0, 888, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1c002e8000408012ULL }, // Inst #2642 = V6_vL32b_cur_pi
4434 { 2641, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 905, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408c12ULL }, // Inst #2641 = V6_vL32b_cur_npred_ppu
4435 { 2640, 5, 2, 4, 214, 0, 0, HexagonImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408c12ULL }, // Inst #2640 = V6_vL32b_cur_npred_pi
4436 { 2639, 4, 1, 4, 213, 0, 0, HexagonImpOpBase + 0, 896, 0|(1ULL<<MCID::MayLoad), 0x1c002b8000408c12ULL }, // Inst #2639 = V6_vL32b_cur_npred_ai
4437 { 2638, 3, 1, 4, 42, 0, 0, HexagonImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1c002b8000408012ULL }, // Inst #2638 = V6_vL32b_cur_ai
4438 { 2637, 3, 1, 4, 42, 0, 0, HexagonImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18002b8000608012ULL }, // Inst #2637 = V6_vL32b_ai
4439 { 2636, 4, 2, 4, 212, 0, 0, HexagonImpOpBase + 0, 892, 0|(1ULL<<MCID::MayLoad), 0x8002e8000408017ULL }, // Inst #2636 = V6_vL32Ub_ppu
4440 { 2635, 4, 2, 4, 212, 0, 0, HexagonImpOpBase + 0, 888, 0|(1ULL<<MCID::MayLoad), 0x8002e8000408017ULL }, // Inst #2635 = V6_vL32Ub_pi
4441 { 2634, 3, 1, 4, 211, 0, 0, HexagonImpOpBase + 0, 277, 0|(1ULL<<MCID::MayLoad), 0x8002b8000408017ULL }, // Inst #2634 = V6_vL32Ub_ai
4442 { 2633, 5, 1, 4, 210, 0, 0, HexagonImpOpBase + 0, 354, 0, 0x84000000000801dULL }, // Inst #2633 = V6_v6mpyvubs10_vxx
4443 { 2632, 4, 1, 4, 209, 0, 0, HexagonImpOpBase + 0, 350, 0, 0x80000000000801dULL }, // Inst #2632 = V6_v6mpyvubs10
4444 { 2631, 5, 1, 4, 210, 0, 0, HexagonImpOpBase + 0, 354, 0, 0x84000000000801dULL }, // Inst #2631 = V6_v6mpyhubs10_vxx
4445 { 2630, 4, 1, 4, 209, 0, 0, HexagonImpOpBase + 0, 350, 0, 0x80000000000801dULL }, // Inst #2630 = V6_v6mpyhubs10
4446 { 2629, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 881, 0, 0x800000000008011ULL }, // Inst #2629 = V6_shuffeqw
4447 { 2628, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 881, 0, 0x800000000008011ULL }, // Inst #2628 = V6_shuffeqh
4448 { 2627, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 881, 0, 0x800000000008011ULL }, // Inst #2627 = V6_pred_xor
4449 { 2626, 2, 1, 4, 208, 0, 0, HexagonImpOpBase + 0, 886, 0, 0x800000000008018ULL }, // Inst #2626 = V6_pred_scalar2v2
4450 { 2625, 2, 1, 4, 208, 0, 0, HexagonImpOpBase + 0, 886, 0, 0x800000000008018ULL }, // Inst #2625 = V6_pred_scalar2
4451 { 2624, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 881, 0, 0x800000000008011ULL }, // Inst #2624 = V6_pred_or_n
4452 { 2623, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 881, 0, 0x800000000008011ULL }, // Inst #2623 = V6_pred_or
4453 { 2622, 2, 1, 4, 63, 0, 0, HexagonImpOpBase + 0, 884, 0, 0x3800000000008010ULL }, // Inst #2622 = V6_pred_not
4454 { 2621, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 881, 0, 0x800000000008011ULL }, // Inst #2621 = V6_pred_and_n
4455 { 2620, 3, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 881, 0, 0x800000000008011ULL }, // Inst #2620 = V6_pred_and
4456 { 2619, 2, 1, 4, 45, 0, 0, HexagonImpOpBase + 0, 289, 0, 0x80000000000801eULL }, // Inst #2619 = V6_lvsplatw
4457 { 2618, 2, 1, 4, 45, 0, 0, HexagonImpOpBase + 0, 289, 0, 0x80000000000801eULL }, // Inst #2618 = V6_lvsplath
4458 { 2617, 2, 1, 4, 45, 0, 0, HexagonImpOpBase + 0, 289, 0, 0x80000000000801eULL }, // Inst #2617 = V6_lvsplatb
4459 { 2616, 3, 1, 4, 207, 0, 0, HexagonImpOpBase + 0, 334, 0|(1ULL<<MCID::MayLoad), 0x38000000000080a4ULL }, // Inst #2616 = V6_extractw
4460 { 2615, 2, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 167, 0, 0xc2800000ULL }, // Inst #2615 = TFRI64_V4
4461 { 2614, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 495, 0, 0xc2800000ULL }, // Inst #2614 = TFRI64_V2_ext
4462 { 2613, 2, 0, 4, 206, 0, 0, HexagonImpOpBase + 0, 615, 0|(1ULL<<MCID::MayStore), 0x1b000000002aULL }, // Inst #2613 = SS2_storewi1
4463 { 2612, 2, 0, 4, 206, 0, 0, HexagonImpOpBase + 0, 615, 0|(1ULL<<MCID::MayStore), 0x1b000000002aULL }, // Inst #2612 = SS2_storewi0
4464 { 2611, 2, 0, 4, 165, 1, 0, HexagonImpOpBase + 44, 879, 0|(1ULL<<MCID::MayStore), 0x1b000000002aULL }, // Inst #2611 = SS2_storew_sp
4465 { 2610, 3, 0, 4, 51, 0, 0, HexagonImpOpBase + 0, 874, 0|(1ULL<<MCID::MayStore), 0x13000000002aULL }, // Inst #2610 = SS2_storeh_io
4466 { 2609, 2, 0, 4, 165, 1, 0, HexagonImpOpBase + 44, 877, 0|(1ULL<<MCID::MayStore), 0x23000000002aULL }, // Inst #2609 = SS2_stored_sp
4467 { 2608, 2, 0, 4, 206, 0, 0, HexagonImpOpBase + 0, 615, 0|(1ULL<<MCID::MayStore), 0xb000000002aULL }, // Inst #2608 = SS2_storebi1
4468 { 2607, 2, 0, 4, 206, 0, 0, HexagonImpOpBase + 0, 615, 0|(1ULL<<MCID::MayStore), 0xb000000002aULL }, // Inst #2607 = SS2_storebi0
4469 { 2606, 1, 0, 4, 205, 5, 2, HexagonImpOpBase + 161, 0, 0|(1ULL<<MCID::MayStore), 0x23000000002aULL }, // Inst #2606 = SS2_allocframe
4470 { 2605, 3, 0, 4, 51, 0, 0, HexagonImpOpBase + 0, 874, 0|(1ULL<<MCID::MayStore), 0x1b000000002aULL }, // Inst #2605 = SS1_storew_io
4471 { 2604, 3, 0, 4, 51, 0, 0, HexagonImpOpBase + 0, 874, 0|(1ULL<<MCID::MayStore), 0xb000000002aULL }, // Inst #2604 = SS1_storeb_io
4472 { 2603, 0, 0, 4, 204, 3, 4, HexagonImpOpBase + 154, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20900000142aULL }, // Inst #2603 = SL2_return_tnew
4473 { 2602, 0, 0, 4, 204, 3, 4, HexagonImpOpBase + 154, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20900000042aULL }, // Inst #2602 = SL2_return_t
4474 { 2601, 0, 0, 4, 204, 3, 4, HexagonImpOpBase + 154, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x209000001c2aULL }, // Inst #2601 = SL2_return_fnew
4475 { 2600, 0, 0, 4, 204, 3, 4, HexagonImpOpBase + 154, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x209000000c2aULL }, // Inst #2600 = SL2_return_f
4476 { 2599, 0, 0, 4, 204, 2, 4, HexagonImpOpBase + 148, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20900000002aULL }, // Inst #2599 = SL2_return
4477 { 2598, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 609, 0|(1ULL<<MCID::MayLoad), 0x13000000802aULL }, // Inst #2598 = SL2_loadruh_io
4478 { 2597, 2, 1, 4, 147, 1, 0, HexagonImpOpBase + 44, 615, 0|(1ULL<<MCID::MayLoad), 0x1b000000802aULL }, // Inst #2597 = SL2_loadri_sp
4479 { 2596, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 609, 0|(1ULL<<MCID::MayLoad), 0x13000000802aULL }, // Inst #2596 = SL2_loadrh_io
4480 { 2595, 2, 1, 4, 147, 1, 0, HexagonImpOpBase + 44, 870, 0|(1ULL<<MCID::MayLoad), 0x23000000802aULL }, // Inst #2595 = SL2_loadrd_sp
4481 { 2594, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 609, 0|(1ULL<<MCID::MayLoad), 0xb000000802aULL }, // Inst #2594 = SL2_loadrb_io
4482 { 2593, 0, 0, 4, 203, 2, 1, HexagonImpOpBase + 145, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000142aULL }, // Inst #2593 = SL2_jumpr31_tnew
4483 { 2592, 0, 0, 4, 203, 2, 1, HexagonImpOpBase + 145, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000042aULL }, // Inst #2592 = SL2_jumpr31_t
4484 { 2591, 0, 0, 4, 203, 2, 1, HexagonImpOpBase + 145, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000001c2aULL }, // Inst #2591 = SL2_jumpr31_fnew
4485 { 2590, 0, 0, 4, 203, 2, 1, HexagonImpOpBase + 145, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000c2aULL }, // Inst #2590 = SL2_jumpr31_f
4486 { 2589, 0, 0, 4, 203, 1, 1, HexagonImpOpBase + 143, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000002aULL }, // Inst #2589 = SL2_jumpr31
4487 { 2588, 0, 0, 4, 202, 2, 3, HexagonImpOpBase + 138, 1, 0|(1ULL<<MCID::MayLoad), 0x20000000002aULL }, // Inst #2588 = SL2_deallocframe
4488 { 2587, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 609, 0|(1ULL<<MCID::MayLoad), 0xb000000802aULL }, // Inst #2587 = SL1_loadrub_io
4489 { 2586, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 609, 0|(1ULL<<MCID::MayLoad), 0x1b000000802aULL }, // Inst #2586 = SL1_loadri_io
4490 { 2585, 1, 0, 4, 35, 2, 3, HexagonImpOpBase + 133, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2585 = SAVE_REGISTERS_CALL_V4_PIC
4491 { 2584, 1, 0, 4, 35, 2, 3, HexagonImpOpBase + 133, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800023ULL }, // Inst #2584 = SAVE_REGISTERS_CALL_V4_EXT_PIC
4492 { 2583, 1, 0, 4, 35, 2, 0, HexagonImpOpBase + 122, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800023ULL }, // Inst #2583 = SAVE_REGISTERS_CALL_V4_EXT
4493 { 2582, 1, 0, 4, 35, 2, 4, HexagonImpOpBase + 127, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2582 = SAVE_REGISTERS_CALL_V4STK_PIC
4494 { 2581, 1, 0, 4, 35, 2, 4, HexagonImpOpBase + 127, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800023ULL }, // Inst #2581 = SAVE_REGISTERS_CALL_V4STK_EXT_PIC
4495 { 2580, 1, 0, 4, 35, 2, 1, HexagonImpOpBase + 124, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800023ULL }, // Inst #2580 = SAVE_REGISTERS_CALL_V4STK_EXT
4496 { 2579, 1, 0, 4, 35, 2, 1, HexagonImpOpBase + 124, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2579 = SAVE_REGISTERS_CALL_V4STK
4497 { 2578, 1, 0, 4, 35, 2, 0, HexagonImpOpBase + 122, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2578 = SAVE_REGISTERS_CALL_V4
4498 { 2577, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 867, 0, 0x802aULL }, // Inst #2577 = SA1_zxth
4499 { 2576, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 867, 0, 0x802aULL }, // Inst #2576 = SA1_zxtb
4500 { 2575, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 867, 0, 0x802aULL }, // Inst #2575 = SA1_tfr
4501 { 2574, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 867, 0, 0x802aULL }, // Inst #2574 = SA1_sxth
4502 { 2573, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 867, 0, 0x802aULL }, // Inst #2573 = SA1_sxtb
4503 { 2572, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 615, 0, 0x802aULL }, // Inst #2572 = SA1_setin1
4504 { 2571, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 615, 0, 0xc280802aULL }, // Inst #2571 = SA1_seti
4505 { 2570, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 867, 0, 0x802aULL }, // Inst #2570 = SA1_inc
4506 { 2569, 3, 1, 4, 197, 0, 0, HexagonImpOpBase + 0, 609, 0, 0x802aULL }, // Inst #2569 = SA1_dec
4507 { 2568, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 872, 0, 0x802aULL }, // Inst #2568 = SA1_combinezr
4508 { 2567, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 872, 0, 0x802aULL }, // Inst #2567 = SA1_combinerz
4509 { 2566, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 870, 0, 0x802aULL }, // Inst #2566 = SA1_combine3i
4510 { 2565, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 870, 0, 0x802aULL }, // Inst #2565 = SA1_combine2i
4511 { 2564, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 870, 0, 0x802aULL }, // Inst #2564 = SA1_combine1i
4512 { 2563, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 870, 0, 0x802aULL }, // Inst #2563 = SA1_combine0i
4513 { 2562, 2, 0, 4, 201, 0, 1, HexagonImpOpBase + 121, 615, 0, 0x2aULL }, // Inst #2562 = SA1_cmpeqi
4514 { 2561, 1, 1, 4, 200, 1, 0, HexagonImpOpBase + 121, 869, 0, 0x942aULL }, // Inst #2561 = SA1_clrtnew
4515 { 2560, 1, 1, 4, 199, 1, 0, HexagonImpOpBase + 121, 869, 0, 0x842aULL }, // Inst #2560 = SA1_clrt
4516 { 2559, 1, 1, 4, 200, 1, 0, HexagonImpOpBase + 121, 869, 0, 0x9c2aULL }, // Inst #2559 = SA1_clrfnew
4517 { 2558, 1, 1, 4, 199, 1, 0, HexagonImpOpBase + 121, 869, 0, 0x8c2aULL }, // Inst #2558 = SA1_clrf
4518 { 2557, 2, 1, 4, 198, 0, 0, HexagonImpOpBase + 0, 867, 0, 0x802aULL }, // Inst #2557 = SA1_and1
4519 { 2556, 2, 1, 4, 198, 1, 0, HexagonImpOpBase + 44, 615, 0, 0x802aULL }, // Inst #2556 = SA1_addsp
4520 { 2555, 3, 1, 4, 197, 0, 0, HexagonImpOpBase + 0, 864, 0, 0x802aULL }, // Inst #2555 = SA1_addrx
4521 { 2554, 3, 1, 4, 197, 0, 0, HexagonImpOpBase + 0, 861, 0, 0xf480802aULL }, // Inst #2554 = SA1_addi
4522 { 2553, 3, 1, 4, 94, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x2cULL }, // Inst #2553 = S6_vtrunohb_ppp
4523 { 2552, 3, 1, 4, 94, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x2cULL }, // Inst #2552 = S6_vtrunehb_ppp
4524 { 2551, 2, 1, 4, 196, 0, 0, HexagonImpOpBase + 0, 190, 0, 0x2bULL }, // Inst #2551 = S6_vsplatrbp
4525 { 2550, 4, 1, 4, 195, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2550 = S6_rol_i_r_xacc
4526 { 2549, 4, 1, 4, 195, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2549 = S6_rol_i_r_or
4527 { 2548, 4, 1, 4, 195, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2548 = S6_rol_i_r_nac
4528 { 2547, 4, 1, 4, 195, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2547 = S6_rol_i_r_and
4529 { 2546, 4, 1, 4, 195, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2546 = S6_rol_i_r_acc
4530 { 2545, 3, 1, 4, 94, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x802bULL }, // Inst #2545 = S6_rol_i_r
4531 { 2544, 4, 1, 4, 195, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2544 = S6_rol_i_p_xacc
4532 { 2543, 4, 1, 4, 195, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2543 = S6_rol_i_p_or
4533 { 2542, 4, 1, 4, 195, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2542 = S6_rol_i_p_nac
4534 { 2541, 4, 1, 4, 195, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2541 = S6_rol_i_p_and
4535 { 2540, 4, 1, 4, 195, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2540 = S6_rol_i_p_acc
4536 { 2539, 3, 1, 4, 94, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x2bULL }, // Inst #2539 = S6_rol_i_p
4537 { 2538, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x8000000000002bULL }, // Inst #2538 = S5_vasrhrnd
4538 { 2537, 2, 1, 4, 194, 0, 0, HexagonImpOpBase + 0, 307, 0, 0x8000000000802bULL }, // Inst #2537 = S5_popcountp
4539 { 2536, 3, 1, 4, 48, 0, 1, HexagonImpOpBase + 63, 314, 0, 0x8000000000802bULL }, // Inst #2536 = S5_asrhub_sat
4540 { 2535, 3, 1, 4, 48, 0, 1, HexagonImpOpBase + 63, 314, 0, 0x8000000000802bULL }, // Inst #2535 = S5_asrhub_rnd_sat
4541 { 2534, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x8000000000002cULL }, // Inst #2534 = S4_vxsubaddw
4542 { 2533, 3, 1, 4, 48, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x8000000000002cULL }, // Inst #2533 = S4_vxsubaddhr
4543 { 2532, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x8000000000002cULL }, // Inst #2532 = S4_vxsubaddh
4544 { 2531, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x8000000000002cULL }, // Inst #2531 = S4_vxaddsubw
4545 { 2530, 3, 1, 4, 48, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x8000000000002cULL }, // Inst #2530 = S4_vxaddsubhr
4546 { 2529, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x8000000000002cULL }, // Inst #2529 = S4_vxaddsubh
4547 { 2528, 5, 1, 4, 193, 0, 0, HexagonImpOpBase + 0, 856, 0, 0x8000000000002cULL }, // Inst #2528 = S4_vrcrotate_acc
4548 { 2527, 4, 1, 4, 192, 0, 0, HexagonImpOpBase + 0, 852, 0, 0x8000000000002cULL }, // Inst #2527 = S4_vrcrotate
4549 { 2526, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 812, 0, 0x80000102808003ULL }, // Inst #2526 = S4_subi_lsr_ri
4550 { 2525, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 812, 0, 0x80000102808003ULL }, // Inst #2525 = S4_subi_asl_ri
4551 { 2524, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 726, 0, 0x800000d4808003ULL }, // Inst #2524 = S4_subaddi
4552 { 2523, 4, 0, 4, 191, 0, 0, HexagonImpOpBase + 0, 840, 0|(1ULL<<MCID::MayStore), 0x1c80c5934029ULL }, // Inst #2523 = S4_storerinew_ur
4553 { 2522, 4, 0, 4, 190, 0, 0, HexagonImpOpBase + 0, 726, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1d8000134029ULL }, // Inst #2522 = S4_storerinew_rr
4554 { 2521, 3, 1, 4, 186, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore), 0x1a80c3924029ULL }, // Inst #2521 = S4_storerinew_ap
4555 { 2520, 4, 0, 4, 189, 0, 0, HexagonImpOpBase + 0, 840, 0|(1ULL<<MCID::MayStore), 0x1c00c5880029ULL }, // Inst #2520 = S4_storeri_ur
4556 { 2519, 4, 0, 4, 188, 0, 0, HexagonImpOpBase + 0, 726, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1d0000080029ULL }, // Inst #2519 = S4_storeri_rr
4557 { 2518, 3, 1, 4, 182, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore), 0x1a00c3880029ULL }, // Inst #2518 = S4_storeri_ap
4558 { 2517, 4, 0, 4, 191, 0, 0, HexagonImpOpBase + 0, 840, 0|(1ULL<<MCID::MayStore), 0x1480c5934029ULL }, // Inst #2517 = S4_storerhnew_ur
4559 { 2516, 4, 0, 4, 190, 0, 0, HexagonImpOpBase + 0, 726, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x158000134029ULL }, // Inst #2516 = S4_storerhnew_rr
4560 { 2515, 3, 1, 4, 186, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore), 0x1280c3924029ULL }, // Inst #2515 = S4_storerhnew_ap
4561 { 2514, 4, 0, 4, 189, 0, 0, HexagonImpOpBase + 0, 840, 0|(1ULL<<MCID::MayStore), 0x1400c5880029ULL }, // Inst #2514 = S4_storerh_ur
4562 { 2513, 4, 0, 4, 188, 0, 0, HexagonImpOpBase + 0, 726, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x150000080029ULL }, // Inst #2513 = S4_storerh_rr
4563 { 2512, 3, 1, 4, 182, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore), 0x1200c3880029ULL }, // Inst #2512 = S4_storerh_ap
4564 { 2511, 4, 0, 4, 189, 0, 0, HexagonImpOpBase + 0, 840, 0|(1ULL<<MCID::MayStore), 0x1400c5800029ULL }, // Inst #2511 = S4_storerf_ur
4565 { 2510, 4, 0, 4, 188, 0, 0, HexagonImpOpBase + 0, 726, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x150000000029ULL }, // Inst #2510 = S4_storerf_rr
4566 { 2509, 3, 1, 4, 182, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore), 0x1200c3800029ULL }, // Inst #2509 = S4_storerf_ap
4567 { 2508, 4, 0, 4, 189, 0, 0, HexagonImpOpBase + 0, 848, 0|(1ULL<<MCID::MayStore), 0x2400c5800029ULL }, // Inst #2508 = S4_storerd_ur
4568 { 2507, 4, 0, 4, 188, 0, 0, HexagonImpOpBase + 0, 844, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x250000000029ULL }, // Inst #2507 = S4_storerd_rr
4569 { 2506, 3, 1, 4, 182, 0, 0, HexagonImpOpBase + 0, 513, 0|(1ULL<<MCID::MayStore), 0x2200c3800029ULL }, // Inst #2506 = S4_storerd_ap
4570 { 2505, 4, 0, 4, 191, 0, 0, HexagonImpOpBase + 0, 840, 0|(1ULL<<MCID::MayStore), 0xc80c5934029ULL }, // Inst #2505 = S4_storerbnew_ur
4571 { 2504, 4, 0, 4, 190, 0, 0, HexagonImpOpBase + 0, 726, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xd8000134029ULL }, // Inst #2504 = S4_storerbnew_rr
4572 { 2503, 3, 1, 4, 186, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore), 0xa80c3924029ULL }, // Inst #2503 = S4_storerbnew_ap
4573 { 2502, 4, 0, 4, 189, 0, 0, HexagonImpOpBase + 0, 840, 0|(1ULL<<MCID::MayStore), 0xc00c5880029ULL }, // Inst #2502 = S4_storerb_ur
4574 { 2501, 4, 0, 4, 188, 0, 0, HexagonImpOpBase + 0, 726, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xd0000080029ULL }, // Inst #2501 = S4_storerb_rr
4575 { 2500, 3, 1, 4, 182, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore), 0xa00c3880029ULL }, // Inst #2500 = S4_storerb_ap
4576 { 2499, 4, 0, 4, 57, 0, 0, HexagonImpOpBase + 0, 836, 0|(1ULL<<MCID::MayStore), 0x1b00d6801429ULL }, // Inst #2499 = S4_storeiritnew_io
4577 { 2498, 4, 0, 4, 56, 0, 0, HexagonImpOpBase + 0, 836, 0|(1ULL<<MCID::MayStore), 0x1b00d6800429ULL }, // Inst #2498 = S4_storeirit_io
4578 { 2497, 4, 0, 4, 57, 0, 0, HexagonImpOpBase + 0, 836, 0|(1ULL<<MCID::MayStore), 0x1b00d6801c29ULL }, // Inst #2497 = S4_storeirifnew_io
4579 { 2496, 4, 0, 4, 56, 0, 0, HexagonImpOpBase + 0, 836, 0|(1ULL<<MCID::MayStore), 0x1b00d6800c29ULL }, // Inst #2496 = S4_storeirif_io
4580 { 2495, 3, 0, 4, 55, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1b0114800029ULL }, // Inst #2495 = S4_storeiri_io
4581 { 2494, 4, 0, 4, 57, 0, 0, HexagonImpOpBase + 0, 836, 0|(1ULL<<MCID::MayStore), 0x1300d6801429ULL }, // Inst #2494 = S4_storeirhtnew_io
4582 { 2493, 4, 0, 4, 56, 0, 0, HexagonImpOpBase + 0, 836, 0|(1ULL<<MCID::MayStore), 0x1300d6800429ULL }, // Inst #2493 = S4_storeirht_io
4583 { 2492, 4, 0, 4, 57, 0, 0, HexagonImpOpBase + 0, 836, 0|(1ULL<<MCID::MayStore), 0x1300d6801c29ULL }, // Inst #2492 = S4_storeirhfnew_io
4584 { 2491, 4, 0, 4, 56, 0, 0, HexagonImpOpBase + 0, 836, 0|(1ULL<<MCID::MayStore), 0x1300d6800c29ULL }, // Inst #2491 = S4_storeirhf_io
4585 { 2490, 3, 0, 4, 55, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x130114800029ULL }, // Inst #2490 = S4_storeirh_io
4586 { 2489, 4, 0, 4, 57, 0, 0, HexagonImpOpBase + 0, 836, 0|(1ULL<<MCID::MayStore), 0xb00d6801429ULL }, // Inst #2489 = S4_storeirbtnew_io
4587 { 2488, 4, 0, 4, 56, 0, 0, HexagonImpOpBase + 0, 836, 0|(1ULL<<MCID::MayStore), 0xb00d6800429ULL }, // Inst #2488 = S4_storeirbt_io
4588 { 2487, 4, 0, 4, 57, 0, 0, HexagonImpOpBase + 0, 836, 0|(1ULL<<MCID::MayStore), 0xb00d6801c29ULL }, // Inst #2487 = S4_storeirbfnew_io
4589 { 2486, 4, 0, 4, 56, 0, 0, HexagonImpOpBase + 0, 836, 0|(1ULL<<MCID::MayStore), 0xb00d6800c29ULL }, // Inst #2486 = S4_storeirbf_io
4590 { 2485, 3, 0, 4, 55, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xb0114800029ULL }, // Inst #2485 = S4_storeirb_io
4591 { 2484, 2, 0, 4, 178, 0, 0, HexagonImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2000000000a9ULL }, // Inst #2484 = S4_stored_rl_st_vi
4592 { 2483, 2, 0, 4, 178, 0, 0, HexagonImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2000000000a9ULL }, // Inst #2483 = S4_stored_rl_at_vi
4593 { 2482, 3, 1, 4, 177, 0, 0, HexagonImpOpBase + 0, 172, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200000002129ULL }, // Inst #2482 = S4_stored_locked
4594 { 2481, 5, 0, 4, 183, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x1d0000081429ULL }, // Inst #2481 = S4_pstoreritnew_rr
4595 { 2480, 4, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1b090488142fULL }, // Inst #2480 = S4_pstoreritnew_io
4596 { 2479, 3, 0, 4, 182, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1900c3881429ULL }, // Inst #2479 = S4_pstoreritnew_abs
4597 { 2478, 5, 0, 4, 181, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x1d0000080429ULL }, // Inst #2478 = S4_pstorerit_rr
4598 { 2477, 3, 0, 4, 180, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1900c3880429ULL }, // Inst #2477 = S4_pstorerit_abs
4599 { 2476, 5, 0, 4, 187, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x1d8000145429ULL }, // Inst #2476 = S4_pstorerinewtnew_rr
4600 { 2475, 4, 0, 4, 54, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1b890493542fULL }, // Inst #2475 = S4_pstorerinewtnew_io
4601 { 2474, 3, 0, 4, 186, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1980c3925429ULL }, // Inst #2474 = S4_pstorerinewtnew_abs
4602 { 2473, 5, 0, 4, 185, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x1d8000144429ULL }, // Inst #2473 = S4_pstorerinewt_rr
4603 { 2472, 3, 0, 4, 184, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1980c3924429ULL }, // Inst #2472 = S4_pstorerinewt_abs
4604 { 2471, 5, 0, 4, 187, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x1d8000145c29ULL }, // Inst #2471 = S4_pstorerinewfnew_rr
4605 { 2470, 4, 0, 4, 54, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1b8904935c2fULL }, // Inst #2470 = S4_pstorerinewfnew_io
4606 { 2469, 3, 0, 4, 186, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1980c3925c29ULL }, // Inst #2469 = S4_pstorerinewfnew_abs
4607 { 2468, 5, 0, 4, 185, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x1d8000144c29ULL }, // Inst #2468 = S4_pstorerinewf_rr
4608 { 2467, 3, 0, 4, 184, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1980c3924c29ULL }, // Inst #2467 = S4_pstorerinewf_abs
4609 { 2466, 5, 0, 4, 183, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x1d0000081c29ULL }, // Inst #2466 = S4_pstorerifnew_rr
4610 { 2465, 4, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1b0904881c2fULL }, // Inst #2465 = S4_pstorerifnew_io
4611 { 2464, 3, 0, 4, 182, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1900c3881c29ULL }, // Inst #2464 = S4_pstorerifnew_abs
4612 { 2463, 5, 0, 4, 181, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x1d0000080c29ULL }, // Inst #2463 = S4_pstorerif_rr
4613 { 2462, 3, 0, 4, 180, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1900c3880c29ULL }, // Inst #2462 = S4_pstorerif_abs
4614 { 2461, 5, 0, 4, 183, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x150000081429ULL }, // Inst #2461 = S4_pstorerhtnew_rr
4615 { 2460, 4, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1304e488142fULL }, // Inst #2460 = S4_pstorerhtnew_io
4616 { 2459, 3, 0, 4, 182, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1100c3881429ULL }, // Inst #2459 = S4_pstorerhtnew_abs
4617 { 2458, 5, 0, 4, 181, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x150000080429ULL }, // Inst #2458 = S4_pstorerht_rr
4618 { 2457, 3, 0, 4, 180, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1100c3880429ULL }, // Inst #2457 = S4_pstorerht_abs
4619 { 2456, 5, 0, 4, 187, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x158000145429ULL }, // Inst #2456 = S4_pstorerhnewtnew_rr
4620 { 2455, 4, 0, 4, 54, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1384e493542fULL }, // Inst #2455 = S4_pstorerhnewtnew_io
4621 { 2454, 3, 0, 4, 186, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1180c3925429ULL }, // Inst #2454 = S4_pstorerhnewtnew_abs
4622 { 2453, 5, 0, 4, 185, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x158000144429ULL }, // Inst #2453 = S4_pstorerhnewt_rr
4623 { 2452, 3, 0, 4, 184, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1180c3924429ULL }, // Inst #2452 = S4_pstorerhnewt_abs
4624 { 2451, 5, 0, 4, 187, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x158000145c29ULL }, // Inst #2451 = S4_pstorerhnewfnew_rr
4625 { 2450, 4, 0, 4, 54, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1384e4935c2fULL }, // Inst #2450 = S4_pstorerhnewfnew_io
4626 { 2449, 3, 0, 4, 186, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1180c3925c29ULL }, // Inst #2449 = S4_pstorerhnewfnew_abs
4627 { 2448, 5, 0, 4, 185, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x158000144c29ULL }, // Inst #2448 = S4_pstorerhnewf_rr
4628 { 2447, 3, 0, 4, 184, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1180c3924c29ULL }, // Inst #2447 = S4_pstorerhnewf_abs
4629 { 2446, 5, 0, 4, 183, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x150000081c29ULL }, // Inst #2446 = S4_pstorerhfnew_rr
4630 { 2445, 4, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1304e4881c2fULL }, // Inst #2445 = S4_pstorerhfnew_io
4631 { 2444, 3, 0, 4, 182, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1100c3881c29ULL }, // Inst #2444 = S4_pstorerhfnew_abs
4632 { 2443, 5, 0, 4, 181, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x150000080c29ULL }, // Inst #2443 = S4_pstorerhf_rr
4633 { 2442, 3, 0, 4, 180, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1100c3880c29ULL }, // Inst #2442 = S4_pstorerhf_abs
4634 { 2441, 5, 0, 4, 183, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x150000001429ULL }, // Inst #2441 = S4_pstorerftnew_rr
4635 { 2440, 4, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1304e480142fULL }, // Inst #2440 = S4_pstorerftnew_io
4636 { 2439, 3, 0, 4, 182, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1100c3801429ULL }, // Inst #2439 = S4_pstorerftnew_abs
4637 { 2438, 5, 0, 4, 181, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x150000000429ULL }, // Inst #2438 = S4_pstorerft_rr
4638 { 2437, 3, 0, 4, 180, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1100c3800429ULL }, // Inst #2437 = S4_pstorerft_abs
4639 { 2436, 5, 0, 4, 183, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x150000001c29ULL }, // Inst #2436 = S4_pstorerffnew_rr
4640 { 2435, 4, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1304e4801c2fULL }, // Inst #2435 = S4_pstorerffnew_io
4641 { 2434, 3, 0, 4, 182, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1100c3801c29ULL }, // Inst #2434 = S4_pstorerffnew_abs
4642 { 2433, 5, 0, 4, 181, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0x150000000c29ULL }, // Inst #2433 = S4_pstorerff_rr
4643 { 2432, 3, 0, 4, 180, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x1100c3800c29ULL }, // Inst #2432 = S4_pstorerff_abs
4644 { 2431, 5, 0, 4, 183, 0, 0, HexagonImpOpBase + 0, 831, 0|(1ULL<<MCID::MayStore), 0x250000001429ULL }, // Inst #2431 = S4_pstorerdtnew_rr
4645 { 2430, 4, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 769, 0|(1ULL<<MCID::MayStore), 0x230d2480142fULL }, // Inst #2430 = S4_pstorerdtnew_io
4646 { 2429, 3, 0, 4, 182, 0, 0, HexagonImpOpBase + 0, 828, 0|(1ULL<<MCID::MayStore), 0x2100c3801429ULL }, // Inst #2429 = S4_pstorerdtnew_abs
4647 { 2428, 5, 0, 4, 181, 0, 0, HexagonImpOpBase + 0, 831, 0|(1ULL<<MCID::MayStore), 0x250000000429ULL }, // Inst #2428 = S4_pstorerdt_rr
4648 { 2427, 3, 0, 4, 180, 0, 0, HexagonImpOpBase + 0, 828, 0|(1ULL<<MCID::MayStore), 0x2100c3800429ULL }, // Inst #2427 = S4_pstorerdt_abs
4649 { 2426, 5, 0, 4, 183, 0, 0, HexagonImpOpBase + 0, 831, 0|(1ULL<<MCID::MayStore), 0x250000001c29ULL }, // Inst #2426 = S4_pstorerdfnew_rr
4650 { 2425, 4, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 769, 0|(1ULL<<MCID::MayStore), 0x230d24801c2fULL }, // Inst #2425 = S4_pstorerdfnew_io
4651 { 2424, 3, 0, 4, 182, 0, 0, HexagonImpOpBase + 0, 828, 0|(1ULL<<MCID::MayStore), 0x2100c3801c29ULL }, // Inst #2424 = S4_pstorerdfnew_abs
4652 { 2423, 5, 0, 4, 181, 0, 0, HexagonImpOpBase + 0, 831, 0|(1ULL<<MCID::MayStore), 0x250000000c29ULL }, // Inst #2423 = S4_pstorerdf_rr
4653 { 2422, 3, 0, 4, 180, 0, 0, HexagonImpOpBase + 0, 828, 0|(1ULL<<MCID::MayStore), 0x2100c3800c29ULL }, // Inst #2422 = S4_pstorerdf_abs
4654 { 2421, 5, 0, 4, 183, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0xd0000081429ULL }, // Inst #2421 = S4_pstorerbtnew_rr
4655 { 2420, 4, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0xb00c488142fULL }, // Inst #2420 = S4_pstorerbtnew_io
4656 { 2419, 3, 0, 4, 182, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x900c3881429ULL }, // Inst #2419 = S4_pstorerbtnew_abs
4657 { 2418, 5, 0, 4, 181, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0xd0000080429ULL }, // Inst #2418 = S4_pstorerbt_rr
4658 { 2417, 3, 0, 4, 180, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x900c3880429ULL }, // Inst #2417 = S4_pstorerbt_abs
4659 { 2416, 5, 0, 4, 187, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0xd8000145429ULL }, // Inst #2416 = S4_pstorerbnewtnew_rr
4660 { 2415, 4, 0, 4, 54, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0xb80c493542fULL }, // Inst #2415 = S4_pstorerbnewtnew_io
4661 { 2414, 3, 0, 4, 186, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x980c3925429ULL }, // Inst #2414 = S4_pstorerbnewtnew_abs
4662 { 2413, 5, 0, 4, 185, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0xd8000144429ULL }, // Inst #2413 = S4_pstorerbnewt_rr
4663 { 2412, 3, 0, 4, 184, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x980c3924429ULL }, // Inst #2412 = S4_pstorerbnewt_abs
4664 { 2411, 5, 0, 4, 187, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0xd8000145c29ULL }, // Inst #2411 = S4_pstorerbnewfnew_rr
4665 { 2410, 4, 0, 4, 54, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0xb80c4935c2fULL }, // Inst #2410 = S4_pstorerbnewfnew_io
4666 { 2409, 3, 0, 4, 186, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x980c3925c29ULL }, // Inst #2409 = S4_pstorerbnewfnew_abs
4667 { 2408, 5, 0, 4, 185, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0xd8000144c29ULL }, // Inst #2408 = S4_pstorerbnewf_rr
4668 { 2407, 3, 0, 4, 184, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x980c3924c29ULL }, // Inst #2407 = S4_pstorerbnewf_abs
4669 { 2406, 5, 0, 4, 183, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0xd0000081c29ULL }, // Inst #2406 = S4_pstorerbfnew_rr
4670 { 2405, 4, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0xb00c4881c2fULL }, // Inst #2405 = S4_pstorerbfnew_io
4671 { 2404, 3, 0, 4, 182, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x900c3881c29ULL }, // Inst #2404 = S4_pstorerbfnew_abs
4672 { 2403, 5, 0, 4, 181, 0, 0, HexagonImpOpBase + 0, 823, 0|(1ULL<<MCID::MayStore), 0xd0000080c29ULL }, // Inst #2403 = S4_pstorerbf_rr
4673 { 2402, 3, 0, 4, 180, 0, 0, HexagonImpOpBase + 0, 820, 0|(1ULL<<MCID::MayStore), 0x900c3880c29ULL }, // Inst #2402 = S4_pstorerbf_abs
4674 { 2401, 3, 1, 4, 170, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #2401 = S4_parity
4675 { 2400, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 812, 0, 0x80000102808003ULL }, // Inst #2400 = S4_ori_lsr_ri
4676 { 2399, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 812, 0, 0x80000102808003ULL }, // Inst #2399 = S4_ori_asl_ri
4677 { 2398, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x80000156808003ULL }, // Inst #2398 = S4_or_ori
4678 { 2397, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 816, 0, 0x80000156808003ULL }, // Inst #2397 = S4_or_andix
4679 { 2396, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x80000156808003ULL }, // Inst #2396 = S4_or_andi
4680 { 2395, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 178, 0, 0x2cULL }, // Inst #2395 = S4_ntstbit_r
4681 { 2394, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 175, 0, 0x2bULL }, // Inst #2394 = S4_ntstbit_i
4682 { 2393, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 510, 0, 0x802cULL }, // Inst #2393 = S4_lsli
4683 { 2392, 3, 1, 4, 170, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x8000000000002cULL }, // Inst #2392 = S4_extractp_rp
4684 { 2391, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 747, 0, 0x8000000000002bULL }, // Inst #2391 = S4_extractp
4685 { 2390, 3, 1, 4, 170, 0, 0, HexagonImpOpBase + 0, 744, 0, 0x8000000000802cULL }, // Inst #2390 = S4_extract_rp
4686 { 2389, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 686, 0, 0x8000000000802bULL }, // Inst #2389 = S4_extract
4687 { 2388, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 307, 0, 0x8000000000802bULL }, // Inst #2388 = S4_clbpnorm
4688 { 2387, 3, 1, 4, 170, 0, 0, HexagonImpOpBase + 0, 314, 0, 0x8000000000802bULL }, // Inst #2387 = S4_clbpaddi
4689 { 2386, 3, 1, 4, 170, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x8000000000802bULL }, // Inst #2386 = S4_clbaddi
4690 { 2385, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 812, 0, 0x80000102808003ULL }, // Inst #2385 = S4_andi_lsr_ri
4691 { 2384, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 812, 0, 0x80000102808003ULL }, // Inst #2384 = S4_andi_asl_ri
4692 { 2383, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 812, 0, 0x80000102808003ULL }, // Inst #2383 = S4_addi_lsr_ri
4693 { 2382, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 812, 0, 0x80000102808003ULL }, // Inst #2382 = S4_addi_asl_ri
4694 { 2381, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 219, 0, 0x800000d6808003ULL }, // Inst #2381 = S4_addaddi
4695 { 2380, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 190, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2bULL }, // Inst #2380 = S2_vzxthw
4696 { 2379, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 190, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2bULL }, // Inst #2379 = S2_vzxtbh
4697 { 2378, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x2cULL }, // Inst #2378 = S2_vtrunowh
4698 { 2377, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 307, 0, 0x802bULL }, // Inst #2377 = S2_vtrunohb
4699 { 2376, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x2cULL }, // Inst #2376 = S2_vtrunewh
4700 { 2375, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 307, 0, 0x802bULL }, // Inst #2375 = S2_vtrunehb
4701 { 2374, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 190, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2bULL }, // Inst #2374 = S2_vsxthw
4702 { 2373, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 190, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2bULL }, // Inst #2373 = S2_vsxtbh
4703 { 2372, 4, 1, 4, 100, 0, 0, HexagonImpOpBase + 0, 808, 0, 0x2cULL }, // Inst #2372 = S2_vsplicerb
4704 { 2371, 4, 1, 4, 100, 0, 0, HexagonImpOpBase + 0, 804, 0, 0x2cULL }, // Inst #2371 = S2_vspliceib
4705 { 2370, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 190, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2bULL }, // Inst #2370 = S2_vsplatrh
4706 { 2369, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x802bULL }, // Inst #2369 = S2_vsplatrb
4707 { 2368, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 162, 0, 0x2bULL }, // Inst #2368 = S2_vsatwuh_nopack
4708 { 2367, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 307, 0, 0x802bULL }, // Inst #2367 = S2_vsatwuh
4709 { 2366, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 162, 0, 0x2bULL }, // Inst #2366 = S2_vsatwh_nopack
4710 { 2365, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 307, 0, 0x802bULL }, // Inst #2365 = S2_vsatwh
4711 { 2364, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 162, 0, 0x2bULL }, // Inst #2364 = S2_vsathub_nopack
4712 { 2363, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 307, 0, 0x802bULL }, // Inst #2363 = S2_vsathub
4713 { 2362, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 162, 0, 0x2bULL }, // Inst #2362 = S2_vsathb_nopack
4714 { 2361, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 307, 0, 0x802bULL }, // Inst #2361 = S2_vsathb
4715 { 2360, 2, 1, 4, 76, 0, 1, HexagonImpOpBase + 63, 307, 0, 0x8000000000802bULL }, // Inst #2360 = S2_vrndpackwhs
4716 { 2359, 2, 1, 4, 179, 0, 0, HexagonImpOpBase + 0, 307, 0, 0x8000000000802bULL }, // Inst #2359 = S2_vrndpackwh
4717 { 2358, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2358 = S2_vrcnegh
4718 { 2357, 3, 1, 4, 48, 0, 1, HexagonImpOpBase + 63, 209, 0, 0x8000000000002cULL }, // Inst #2357 = S2_vcrotate
4719 { 2356, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 209, 0, 0x8000000000002cULL }, // Inst #2356 = S2_vcnegh
4720 { 2355, 4, 1, 4, 100, 0, 0, HexagonImpOpBase + 0, 808, 0, 0x2cULL }, // Inst #2355 = S2_valignrb
4721 { 2354, 4, 1, 4, 100, 0, 0, HexagonImpOpBase + 0, 804, 0, 0x2cULL }, // Inst #2354 = S2_valignib
4722 { 2353, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 178, 0, 0x2cULL }, // Inst #2353 = S2_tstbit_r
4723 { 2352, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 175, 0, 0x2bULL }, // Inst #2352 = S2_tstbit_i
4724 { 2351, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x802cULL }, // Inst #2351 = S2_togglebit_r
4725 { 2350, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x802bULL }, // Inst #2350 = S2_togglebit_i
4726 { 2349, 5, 1, 4, 53, 0, 0, HexagonImpOpBase + 0, 309, 0, 0x8000000000802bULL }, // Inst #2349 = S2_tableidxw
4727 { 2348, 5, 1, 4, 53, 0, 0, HexagonImpOpBase + 0, 309, 0, 0x8000000000802bULL }, // Inst #2348 = S2_tableidxh
4728 { 2347, 5, 1, 4, 53, 0, 0, HexagonImpOpBase + 0, 309, 0, 0x8000000000802bULL }, // Inst #2347 = S2_tableidxd
4729 { 2346, 5, 1, 4, 53, 0, 0, HexagonImpOpBase + 0, 309, 0, 0x8000000000802bULL }, // Inst #2346 = S2_tableidxb
4730 { 2345, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 157, 0, 0x802bULL }, // Inst #2345 = S2_svsathub
4731 { 2344, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 157, 0, 0x802bULL }, // Inst #2344 = S2_svsathb
4732 { 2343, 2, 0, 4, 178, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::MayStore), 0x1800000000a9ULL }, // Inst #2343 = S2_storew_rl_st_vi
4733 { 2342, 2, 0, 4, 178, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::MayStore), 0x1800000000a9ULL }, // Inst #2342 = S2_storew_rl_at_vi
4734 { 2341, 3, 1, 4, 177, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x180000002129ULL }, // Inst #2341 = S2_storew_locked
4735 { 2340, 2, 0, 4, 166, 1, 0, HexagonImpOpBase + 101, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x188a4011402fULL }, // Inst #2340 = S2_storerinewgp
4736 { 2339, 4, 1, 4, 54, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0x1e8000134029ULL }, // Inst #2339 = S2_storerinew_pr
4737 { 2338, 4, 1, 4, 54, 0, 0, HexagonImpOpBase + 0, 787, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1e8000134029ULL }, // Inst #2338 = S2_storerinew_pi
4738 { 2337, 4, 1, 4, 54, 1, 0, HexagonImpOpBase + 100, 778, 0|(1ULL<<MCID::MayStore), 0x1e8000134029ULL }, // Inst #2337 = S2_storerinew_pcr
4739 { 2336, 5, 1, 4, 176, 1, 0, HexagonImpOpBase + 100, 782, 0|(1ULL<<MCID::MayStore), 0x1e8000144029ULL }, // Inst #2336 = S2_storerinew_pci
4740 { 2335, 4, 1, 4, 54, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0x1e8000134029ULL }, // Inst #2335 = S2_storerinew_pbr
4741 { 2334, 3, 0, 4, 52, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1b89b2924029ULL }, // Inst #2334 = S2_storerinew_io
4742 { 2333, 2, 0, 4, 165, 1, 0, HexagonImpOpBase + 101, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x180a4008002fULL }, // Inst #2333 = S2_storerigp
4743 { 2332, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0x1e0000080029ULL }, // Inst #2332 = S2_storeri_pr
4744 { 2331, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 787, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1e0000080029ULL }, // Inst #2331 = S2_storeri_pi
4745 { 2330, 4, 1, 4, 39, 1, 0, HexagonImpOpBase + 100, 778, 0|(1ULL<<MCID::MayStore), 0x1e0000080029ULL }, // Inst #2330 = S2_storeri_pcr
4746 { 2329, 5, 1, 4, 38, 1, 0, HexagonImpOpBase + 100, 782, 0|(1ULL<<MCID::MayStore), 0x1e0000080029ULL }, // Inst #2329 = S2_storeri_pci
4747 { 2328, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0x1e0000080029ULL }, // Inst #2328 = S2_storeri_pbr
4748 { 2327, 3, 0, 4, 51, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1b09b2880029ULL }, // Inst #2327 = S2_storeri_io
4749 { 2326, 2, 0, 4, 166, 1, 0, HexagonImpOpBase + 101, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10862011402fULL }, // Inst #2326 = S2_storerhnewgp
4750 { 2325, 4, 1, 4, 54, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0x168000134029ULL }, // Inst #2325 = S2_storerhnew_pr
4751 { 2324, 4, 1, 4, 54, 0, 0, HexagonImpOpBase + 0, 787, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1680001b4029ULL }, // Inst #2324 = S2_storerhnew_pi
4752 { 2323, 4, 1, 4, 54, 1, 0, HexagonImpOpBase + 100, 778, 0|(1ULL<<MCID::MayStore), 0x168000134029ULL }, // Inst #2323 = S2_storerhnew_pcr
4753 { 2322, 5, 1, 4, 176, 1, 0, HexagonImpOpBase + 100, 782, 0|(1ULL<<MCID::MayStore), 0x168000144029ULL }, // Inst #2322 = S2_storerhnew_pci
4754 { 2321, 4, 1, 4, 54, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0x168000134029ULL }, // Inst #2321 = S2_storerhnew_pbr
4755 { 2320, 3, 0, 4, 52, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x138592924029ULL }, // Inst #2320 = S2_storerhnew_io
4756 { 2319, 2, 0, 4, 165, 1, 0, HexagonImpOpBase + 101, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10062008002fULL }, // Inst #2319 = S2_storerhgp
4757 { 2318, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0x160000080029ULL }, // Inst #2318 = S2_storerh_pr
4758 { 2317, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 787, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x160000080029ULL }, // Inst #2317 = S2_storerh_pi
4759 { 2316, 4, 1, 4, 39, 1, 0, HexagonImpOpBase + 100, 778, 0|(1ULL<<MCID::MayStore), 0x160000080029ULL }, // Inst #2316 = S2_storerh_pcr
4760 { 2315, 5, 1, 4, 38, 1, 0, HexagonImpOpBase + 100, 782, 0|(1ULL<<MCID::MayStore), 0x160000080029ULL }, // Inst #2315 = S2_storerh_pci
4761 { 2314, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0x160000080029ULL }, // Inst #2314 = S2_storerh_pbr
4762 { 2313, 3, 0, 4, 51, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x130592880029ULL }, // Inst #2313 = S2_storerh_io
4763 { 2312, 2, 0, 4, 165, 1, 0, HexagonImpOpBase + 101, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10062000002fULL }, // Inst #2312 = S2_storerfgp
4764 { 2311, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #2311 = S2_storerf_pr
4765 { 2310, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 787, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x160000000029ULL }, // Inst #2310 = S2_storerf_pi
4766 { 2309, 4, 1, 4, 39, 1, 0, HexagonImpOpBase + 100, 778, 0|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #2309 = S2_storerf_pcr
4767 { 2308, 5, 1, 4, 38, 1, 0, HexagonImpOpBase + 100, 782, 0|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #2308 = S2_storerf_pci
4768 { 2307, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #2307 = S2_storerf_pbr
4769 { 2306, 3, 0, 4, 51, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x130592800029ULL }, // Inst #2306 = S2_storerf_io
4770 { 2305, 2, 0, 4, 165, 1, 0, HexagonImpOpBase + 101, 738, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x200e6000002fULL }, // Inst #2305 = S2_storerdgp
4771 { 2304, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 791, 0|(1ULL<<MCID::MayStore), 0x260000000029ULL }, // Inst #2304 = S2_storerd_pr
4772 { 2303, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 800, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x260000000029ULL }, // Inst #2303 = S2_storerd_pi
4773 { 2302, 4, 1, 4, 39, 1, 0, HexagonImpOpBase + 100, 791, 0|(1ULL<<MCID::MayStore), 0x260000000029ULL }, // Inst #2302 = S2_storerd_pcr
4774 { 2301, 5, 1, 4, 38, 1, 0, HexagonImpOpBase + 100, 795, 0|(1ULL<<MCID::MayStore), 0x260000000029ULL }, // Inst #2301 = S2_storerd_pci
4775 { 2300, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 791, 0|(1ULL<<MCID::MayStore), 0x260000000029ULL }, // Inst #2300 = S2_storerd_pbr
4776 { 2299, 3, 0, 4, 51, 0, 0, HexagonImpOpBase + 0, 513, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x230dd2800029ULL }, // Inst #2299 = S2_storerd_io
4777 { 2298, 2, 0, 4, 166, 1, 0, HexagonImpOpBase + 101, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x8820011402fULL }, // Inst #2298 = S2_storerbnewgp
4778 { 2297, 4, 1, 4, 54, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0xe8000134029ULL }, // Inst #2297 = S2_storerbnew_pr
4779 { 2296, 4, 1, 4, 54, 0, 0, HexagonImpOpBase + 0, 787, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xe80001b4029ULL }, // Inst #2296 = S2_storerbnew_pi
4780 { 2295, 4, 1, 4, 54, 1, 0, HexagonImpOpBase + 100, 778, 0|(1ULL<<MCID::MayStore), 0xe8000134029ULL }, // Inst #2295 = S2_storerbnew_pcr
4781 { 2294, 5, 1, 4, 176, 1, 0, HexagonImpOpBase + 100, 782, 0|(1ULL<<MCID::MayStore), 0xe8000144029ULL }, // Inst #2294 = S2_storerbnew_pci
4782 { 2293, 4, 1, 4, 54, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0xe8000134029ULL }, // Inst #2293 = S2_storerbnew_pbr
4783 { 2292, 3, 0, 4, 52, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xb8172924029ULL }, // Inst #2292 = S2_storerbnew_io
4784 { 2291, 2, 0, 4, 165, 1, 0, HexagonImpOpBase + 101, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x8020008002fULL }, // Inst #2291 = S2_storerbgp
4785 { 2290, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0xe0000080029ULL }, // Inst #2290 = S2_storerb_pr
4786 { 2289, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 787, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xe0000080029ULL }, // Inst #2289 = S2_storerb_pi
4787 { 2288, 4, 1, 4, 39, 1, 0, HexagonImpOpBase + 100, 778, 0|(1ULL<<MCID::MayStore), 0xe0000080029ULL }, // Inst #2288 = S2_storerb_pcr
4788 { 2287, 5, 1, 4, 38, 1, 0, HexagonImpOpBase + 100, 782, 0|(1ULL<<MCID::MayStore), 0xe0000080029ULL }, // Inst #2287 = S2_storerb_pci
4789 { 2286, 4, 1, 4, 39, 0, 0, HexagonImpOpBase + 0, 778, 0|(1ULL<<MCID::MayStore), 0xe0000080029ULL }, // Inst #2286 = S2_storerb_pbr
4790 { 2285, 3, 0, 4, 51, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xb0172880029ULL }, // Inst #2285 = S2_storerb_io
4791 { 2284, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x2cULL }, // Inst #2284 = S2_shuffoh
4792 { 2283, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x2cULL }, // Inst #2283 = S2_shuffob
4793 { 2282, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x2cULL }, // Inst #2282 = S2_shuffeh
4794 { 2281, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x2cULL }, // Inst #2281 = S2_shuffeb
4795 { 2280, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x802cULL }, // Inst #2280 = S2_setbit_r
4796 { 2279, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x802bULL }, // Inst #2279 = S2_setbit_i
4797 { 2278, 5, 1, 4, 173, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x1e0000081429ULL }, // Inst #2278 = S2_pstoreritnew_pi
4798 { 2277, 5, 1, 4, 172, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x1e0000080429ULL }, // Inst #2277 = S2_pstorerit_pi
4799 { 2276, 4, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1b090488042fULL }, // Inst #2276 = S2_pstorerit_io
4800 { 2275, 5, 1, 4, 175, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x1e8000145429ULL }, // Inst #2275 = S2_pstorerinewtnew_pi
4801 { 2274, 5, 1, 4, 174, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x1e8000144429ULL }, // Inst #2274 = S2_pstorerinewt_pi
4802 { 2273, 4, 0, 4, 50, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1b890493442fULL }, // Inst #2273 = S2_pstorerinewt_io
4803 { 2272, 5, 1, 4, 175, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x1e8000145c29ULL }, // Inst #2272 = S2_pstorerinewfnew_pi
4804 { 2271, 5, 1, 4, 174, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x1e8000144c29ULL }, // Inst #2271 = S2_pstorerinewf_pi
4805 { 2270, 4, 0, 4, 50, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1b8904934c2fULL }, // Inst #2270 = S2_pstorerinewf_io
4806 { 2269, 5, 1, 4, 173, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x1e0000081c29ULL }, // Inst #2269 = S2_pstorerifnew_pi
4807 { 2268, 5, 1, 4, 172, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x1e0000080c29ULL }, // Inst #2268 = S2_pstorerif_pi
4808 { 2267, 4, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1b0904880c2fULL }, // Inst #2267 = S2_pstorerif_io
4809 { 2266, 5, 1, 4, 173, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x160000081429ULL }, // Inst #2266 = S2_pstorerhtnew_pi
4810 { 2265, 5, 1, 4, 172, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x160000080429ULL }, // Inst #2265 = S2_pstorerht_pi
4811 { 2264, 4, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1304e488042fULL }, // Inst #2264 = S2_pstorerht_io
4812 { 2263, 5, 1, 4, 175, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x168000145429ULL }, // Inst #2263 = S2_pstorerhnewtnew_pi
4813 { 2262, 5, 1, 4, 174, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x168000144429ULL }, // Inst #2262 = S2_pstorerhnewt_pi
4814 { 2261, 4, 0, 4, 50, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1384e493442fULL }, // Inst #2261 = S2_pstorerhnewt_io
4815 { 2260, 5, 1, 4, 175, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x168000145c29ULL }, // Inst #2260 = S2_pstorerhnewfnew_pi
4816 { 2259, 5, 1, 4, 174, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x168000144c29ULL }, // Inst #2259 = S2_pstorerhnewf_pi
4817 { 2258, 4, 0, 4, 50, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1384e4934c2fULL }, // Inst #2258 = S2_pstorerhnewf_io
4818 { 2257, 5, 1, 4, 173, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x160000081c29ULL }, // Inst #2257 = S2_pstorerhfnew_pi
4819 { 2256, 5, 1, 4, 172, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x160000080c29ULL }, // Inst #2256 = S2_pstorerhf_pi
4820 { 2255, 4, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1304e4880c2fULL }, // Inst #2255 = S2_pstorerhf_io
4821 { 2254, 5, 1, 4, 173, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x160000001429ULL }, // Inst #2254 = S2_pstorerftnew_pi
4822 { 2253, 5, 1, 4, 172, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x160000000429ULL }, // Inst #2253 = S2_pstorerft_pi
4823 { 2252, 4, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1304e480042fULL }, // Inst #2252 = S2_pstorerft_io
4824 { 2251, 5, 1, 4, 173, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x160000001c29ULL }, // Inst #2251 = S2_pstorerffnew_pi
4825 { 2250, 5, 1, 4, 172, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0x160000000c29ULL }, // Inst #2250 = S2_pstorerff_pi
4826 { 2249, 4, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0x1304e4800c2fULL }, // Inst #2249 = S2_pstorerff_io
4827 { 2248, 5, 1, 4, 173, 0, 0, HexagonImpOpBase + 0, 773, 0|(1ULL<<MCID::MayStore), 0x260000001429ULL }, // Inst #2248 = S2_pstorerdtnew_pi
4828 { 2247, 5, 1, 4, 172, 0, 0, HexagonImpOpBase + 0, 773, 0|(1ULL<<MCID::MayStore), 0x260000000429ULL }, // Inst #2247 = S2_pstorerdt_pi
4829 { 2246, 4, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 769, 0|(1ULL<<MCID::MayStore), 0x230d2480042fULL }, // Inst #2246 = S2_pstorerdt_io
4830 { 2245, 5, 1, 4, 173, 0, 0, HexagonImpOpBase + 0, 773, 0|(1ULL<<MCID::MayStore), 0x260000001c29ULL }, // Inst #2245 = S2_pstorerdfnew_pi
4831 { 2244, 5, 1, 4, 172, 0, 0, HexagonImpOpBase + 0, 773, 0|(1ULL<<MCID::MayStore), 0x260000000c29ULL }, // Inst #2244 = S2_pstorerdf_pi
4832 { 2243, 4, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 769, 0|(1ULL<<MCID::MayStore), 0x230d24800c2fULL }, // Inst #2243 = S2_pstorerdf_io
4833 { 2242, 5, 1, 4, 173, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0xe0000081429ULL }, // Inst #2242 = S2_pstorerbtnew_pi
4834 { 2241, 5, 1, 4, 172, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0xe0000080429ULL }, // Inst #2241 = S2_pstorerbt_pi
4835 { 2240, 4, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0xb00c488042fULL }, // Inst #2240 = S2_pstorerbt_io
4836 { 2239, 5, 1, 4, 175, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0xe8000145429ULL }, // Inst #2239 = S2_pstorerbnewtnew_pi
4837 { 2238, 5, 1, 4, 174, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0xe8000144429ULL }, // Inst #2238 = S2_pstorerbnewt_pi
4838 { 2237, 4, 0, 4, 50, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0xb80c493442fULL }, // Inst #2237 = S2_pstorerbnewt_io
4839 { 2236, 5, 1, 4, 175, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0xe8000145c29ULL }, // Inst #2236 = S2_pstorerbnewfnew_pi
4840 { 2235, 5, 1, 4, 174, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0xe8000144c29ULL }, // Inst #2235 = S2_pstorerbnewf_pi
4841 { 2234, 4, 0, 4, 50, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0xb80c4934c2fULL }, // Inst #2234 = S2_pstorerbnewf_io
4842 { 2233, 5, 1, 4, 173, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0xe0000081c29ULL }, // Inst #2233 = S2_pstorerbfnew_pi
4843 { 2232, 5, 1, 4, 172, 0, 0, HexagonImpOpBase + 0, 764, 0|(1ULL<<MCID::MayStore), 0xe0000080c29ULL }, // Inst #2232 = S2_pstorerbf_pi
4844 { 2231, 4, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 760, 0|(1ULL<<MCID::MayStore), 0xb00c4880c2fULL }, // Inst #2231 = S2_pstorerbf_io
4845 { 2230, 3, 1, 4, 170, 0, 0, HexagonImpOpBase + 0, 557, 0, 0x80000000008003ULL }, // Inst #2230 = S2_parityp
4846 { 2229, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x1ULL }, // Inst #2229 = S2_packhl
4847 { 2228, 3, 1, 4, 171, 0, 0, HexagonImpOpBase + 0, 516, 0, 0x8000000000802bULL }, // Inst #2228 = S2_mask
4848 { 2227, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 209, 0, 0x2cULL }, // Inst #2227 = S2_lsr_r_vw
4849 { 2226, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 209, 0, 0x2cULL }, // Inst #2226 = S2_lsr_r_vh
4850 { 2225, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2225 = S2_lsr_r_r_or
4851 { 2224, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2224 = S2_lsr_r_r_nac
4852 { 2223, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2223 = S2_lsr_r_r_and
4853 { 2222, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2222 = S2_lsr_r_r_acc
4854 { 2221, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x802cULL }, // Inst #2221 = S2_lsr_r_r
4855 { 2220, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2220 = S2_lsr_r_p_xor
4856 { 2219, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2219 = S2_lsr_r_p_or
4857 { 2218, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2218 = S2_lsr_r_p_nac
4858 { 2217, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2217 = S2_lsr_r_p_and
4859 { 2216, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2216 = S2_lsr_r_p_acc
4860 { 2215, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 209, 0, 0x2cULL }, // Inst #2215 = S2_lsr_r_p
4861 { 2214, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x2bULL }, // Inst #2214 = S2_lsr_i_vw
4862 { 2213, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x2bULL }, // Inst #2213 = S2_lsr_i_vh
4863 { 2212, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2212 = S2_lsr_i_r_xacc
4864 { 2211, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2211 = S2_lsr_i_r_or
4865 { 2210, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2210 = S2_lsr_i_r_nac
4866 { 2209, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2209 = S2_lsr_i_r_and
4867 { 2208, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2208 = S2_lsr_i_r_acc
4868 { 2207, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x802bULL }, // Inst #2207 = S2_lsr_i_r
4869 { 2206, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2206 = S2_lsr_i_p_xacc
4870 { 2205, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2205 = S2_lsr_i_p_or
4871 { 2204, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2204 = S2_lsr_i_p_nac
4872 { 2203, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2203 = S2_lsr_i_p_and
4873 { 2202, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2202 = S2_lsr_i_p_acc
4874 { 2201, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x2bULL }, // Inst #2201 = S2_lsr_i_p
4875 { 2200, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 209, 0, 0x2cULL }, // Inst #2200 = S2_lsl_r_vw
4876 { 2199, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 209, 0, 0x2cULL }, // Inst #2199 = S2_lsl_r_vh
4877 { 2198, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2198 = S2_lsl_r_r_or
4878 { 2197, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2197 = S2_lsl_r_r_nac
4879 { 2196, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2196 = S2_lsl_r_r_and
4880 { 2195, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2195 = S2_lsl_r_r_acc
4881 { 2194, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x802cULL }, // Inst #2194 = S2_lsl_r_r
4882 { 2193, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2193 = S2_lsl_r_p_xor
4883 { 2192, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2192 = S2_lsl_r_p_or
4884 { 2191, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2191 = S2_lsl_r_p_nac
4885 { 2190, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2190 = S2_lsl_r_p_and
4886 { 2189, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2189 = S2_lsl_r_p_acc
4887 { 2188, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 209, 0, 0x2cULL }, // Inst #2188 = S2_lsl_r_p
4888 { 2187, 3, 1, 4, 170, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x8000000000002cULL }, // Inst #2187 = S2_lfsp
4889 { 2186, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 162, 0, 0x8000000000002bULL }, // Inst #2186 = S2_interleave
4890 { 2185, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x8000000000002cULL }, // Inst #2185 = S2_insertp_rp
4891 { 2184, 5, 1, 4, 53, 0, 0, HexagonImpOpBase + 0, 755, 0, 0x8000000000002bULL }, // Inst #2184 = S2_insertp
4892 { 2183, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 751, 0, 0x8000000000802cULL }, // Inst #2183 = S2_insert_rp
4893 { 2182, 5, 1, 4, 53, 0, 0, HexagonImpOpBase + 0, 309, 0, 0x8000000000802bULL }, // Inst #2182 = S2_insert
4894 { 2181, 3, 1, 4, 170, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x8000000000002cULL }, // Inst #2181 = S2_extractup_rp
4895 { 2180, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 747, 0, 0x8000000000002bULL }, // Inst #2180 = S2_extractup
4896 { 2179, 3, 1, 4, 170, 0, 0, HexagonImpOpBase + 0, 744, 0, 0x8000000000802cULL }, // Inst #2179 = S2_extractu_rp
4897 { 2178, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 686, 0, 0x8000000000802bULL }, // Inst #2178 = S2_extractu
4898 { 2177, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 162, 0, 0x8000000000002bULL }, // Inst #2177 = S2_deinterleave
4899 { 2176, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 307, 0, 0x8000000000802bULL }, // Inst #2176 = S2_ct1p
4900 { 2175, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x8000000000802bULL }, // Inst #2175 = S2_ct1
4901 { 2174, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 307, 0, 0x8000000000802bULL }, // Inst #2174 = S2_ct0p
4902 { 2173, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x8000000000802bULL }, // Inst #2173 = S2_ct0
4903 { 2172, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x802cULL }, // Inst #2172 = S2_clrbit_r
4904 { 2171, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x802bULL }, // Inst #2171 = S2_clrbit_i
4905 { 2170, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 307, 0, 0x8000000000802bULL }, // Inst #2170 = S2_clbp
4906 { 2169, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x8000000000802bULL }, // Inst #2169 = S2_clbnorm
4907 { 2168, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x8000000000802bULL }, // Inst #2168 = S2_clb
4908 { 2167, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 307, 0, 0x8000000000802bULL }, // Inst #2167 = S2_cl1p
4909 { 2166, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x8000000000802bULL }, // Inst #2166 = S2_cl1
4910 { 2165, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 307, 0, 0x8000000000802bULL }, // Inst #2165 = S2_cl0p
4911 { 2164, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x8000000000802bULL }, // Inst #2164 = S2_cl0
4912 { 2163, 3, 1, 4, 169, 0, 1, HexagonImpOpBase + 121, 169, 0, 0x8000000000202cULL }, // Inst #2163 = S2_cabacdecbin
4913 { 2162, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 162, 0, 0x8000000000002bULL }, // Inst #2162 = S2_brevp
4914 { 2161, 2, 1, 4, 168, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x8000000000802bULL }, // Inst #2161 = S2_brev
4915 { 2160, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 209, 0, 0x2cULL }, // Inst #2160 = S2_asr_r_vw
4916 { 2159, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 209, 0, 0x2cULL }, // Inst #2159 = S2_asr_r_vh
4917 { 2158, 3, 1, 4, 78, 0, 0, HexagonImpOpBase + 0, 212, 0, 0x8000000000802cULL }, // Inst #2158 = S2_asr_r_svw_trun
4918 { 2157, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x8000000000802cULL }, // Inst #2157 = S2_asr_r_r_sat
4919 { 2156, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2156 = S2_asr_r_r_or
4920 { 2155, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2155 = S2_asr_r_r_nac
4921 { 2154, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2154 = S2_asr_r_r_and
4922 { 2153, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2153 = S2_asr_r_r_acc
4923 { 2152, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x802cULL }, // Inst #2152 = S2_asr_r_r
4924 { 2151, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2151 = S2_asr_r_p_xor
4925 { 2150, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2150 = S2_asr_r_p_or
4926 { 2149, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2149 = S2_asr_r_p_nac
4927 { 2148, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2148 = S2_asr_r_p_and
4928 { 2147, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2147 = S2_asr_r_p_acc
4929 { 2146, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 209, 0, 0x2cULL }, // Inst #2146 = S2_asr_r_p
4930 { 2145, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x2bULL }, // Inst #2145 = S2_asr_i_vw
4931 { 2144, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x2bULL }, // Inst #2144 = S2_asr_i_vh
4932 { 2143, 3, 1, 4, 78, 0, 0, HexagonImpOpBase + 0, 314, 0, 0x8000000000802bULL }, // Inst #2143 = S2_asr_i_svw_trun
4933 { 2142, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x8000000000802bULL }, // Inst #2142 = S2_asr_i_r_rnd
4934 { 2141, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2141 = S2_asr_i_r_or
4935 { 2140, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2140 = S2_asr_i_r_nac
4936 { 2139, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2139 = S2_asr_i_r_and
4937 { 2138, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2138 = S2_asr_i_r_acc
4938 { 2137, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x802bULL }, // Inst #2137 = S2_asr_i_r
4939 { 2136, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x8000000000002bULL }, // Inst #2136 = S2_asr_i_p_rnd
4940 { 2135, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2135 = S2_asr_i_p_or
4941 { 2134, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2134 = S2_asr_i_p_nac
4942 { 2133, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2133 = S2_asr_i_p_and
4943 { 2132, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2132 = S2_asr_i_p_acc
4944 { 2131, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x2bULL }, // Inst #2131 = S2_asr_i_p
4945 { 2130, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 209, 0, 0x2cULL }, // Inst #2130 = S2_asl_r_vw
4946 { 2129, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 209, 0, 0x2cULL }, // Inst #2129 = S2_asl_r_vh
4947 { 2128, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x8000000000802cULL }, // Inst #2128 = S2_asl_r_r_sat
4948 { 2127, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2127 = S2_asl_r_r_or
4949 { 2126, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2126 = S2_asl_r_r_nac
4950 { 2125, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2125 = S2_asl_r_r_and
4951 { 2124, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x8000000000802cULL }, // Inst #2124 = S2_asl_r_r_acc
4952 { 2123, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x802cULL }, // Inst #2123 = S2_asl_r_r
4953 { 2122, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2122 = S2_asl_r_p_xor
4954 { 2121, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2121 = S2_asl_r_p_or
4955 { 2120, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2120 = S2_asl_r_p_nac
4956 { 2119, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2119 = S2_asl_r_p_and
4957 { 2118, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #2118 = S2_asl_r_p_acc
4958 { 2117, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 209, 0, 0x2cULL }, // Inst #2117 = S2_asl_r_p
4959 { 2116, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x2bULL }, // Inst #2116 = S2_asl_i_vw
4960 { 2115, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x2bULL }, // Inst #2115 = S2_asl_i_vh
4961 { 2114, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2114 = S2_asl_i_r_xacc
4962 { 2113, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 199, 0, 0x8000000000802bULL }, // Inst #2113 = S2_asl_i_r_sat
4963 { 2112, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2112 = S2_asl_i_r_or
4964 { 2111, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2111 = S2_asl_i_r_nac
4965 { 2110, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2110 = S2_asl_i_r_and
4966 { 2109, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x8000000000802bULL }, // Inst #2109 = S2_asl_i_r_acc
4967 { 2108, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x802bULL }, // Inst #2108 = S2_asl_i_r
4968 { 2107, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2107 = S2_asl_i_p_xacc
4969 { 2106, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2106 = S2_asl_i_p_or
4970 { 2105, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2105 = S2_asl_i_p_nac
4971 { 2104, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2104 = S2_asl_i_p_and
4972 { 2103, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 740, 0, 0x8000000000002bULL }, // Inst #2103 = S2_asl_i_p_acc
4973 { 2102, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x2bULL }, // Inst #2102 = S2_asl_i_p
4974 { 2101, 3, 1, 4, 58, 4, 1, HexagonImpOpBase + 58, 507, 0|(1ULL<<MCID::MayStore), 0x230000008029ULL }, // Inst #2101 = S2_allocframe
4975 { 2100, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 219, 0, 0x8000000000802cULL }, // Inst #2100 = S2_addasl_rrri
4976 { 2099, 1, 0, 4, 121, 0, 7, HexagonImpOpBase + 114, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb10800023ULL }, // Inst #2099 = RESTORE_DEALLOC_RET_JMP_V4_PIC
4977 { 2098, 1, 0, 4, 121, 0, 7, HexagonImpOpBase + 114, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb11800023ULL }, // Inst #2098 = RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
4978 { 2097, 1, 0, 4, 121, 0, 4, HexagonImpOpBase + 110, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb11800023ULL }, // Inst #2097 = RESTORE_DEALLOC_RET_JMP_V4_EXT
4979 { 2096, 1, 0, 4, 121, 0, 4, HexagonImpOpBase + 110, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb10800023ULL }, // Inst #2096 = RESTORE_DEALLOC_RET_JMP_V4
4980 { 2095, 1, 0, 4, 35, 0, 7, HexagonImpOpBase + 114, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2095 = RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
4981 { 2094, 1, 0, 4, 35, 0, 7, HexagonImpOpBase + 114, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800023ULL }, // Inst #2094 = RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
4982 { 2093, 1, 0, 4, 35, 0, 4, HexagonImpOpBase + 110, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800023ULL }, // Inst #2093 = RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT
4983 { 2092, 1, 0, 4, 35, 0, 4, HexagonImpOpBase + 110, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2092 = RESTORE_DEALLOC_BEFORE_TAILCALL_V4
4984 { 2091, 1, 0, 4, 167, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::MayStore), 0xa9ULL }, // Inst #2091 = R6_release_st_vi
4985 { 2090, 1, 0, 4, 167, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::MayStore), 0xa9ULL }, // Inst #2090 = R6_release_at_vi
4986 { 2089, 1, 0, 4, 17, 0, 0, HexagonImpOpBase + 0, 0, 0, 0x23ULL }, // Inst #2089 = PS_trap1
4987 { 2088, 2, 0, 4, 166, 0, 0, HexagonImpOpBase + 0, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x198a4111402fULL }, // Inst #2088 = PS_storerinewabs
4988 { 2087, 2, 0, 4, 165, 0, 0, HexagonImpOpBase + 0, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x190a4108002fULL }, // Inst #2087 = PS_storeriabs
4989 { 2086, 2, 0, 4, 166, 0, 0, HexagonImpOpBase + 0, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x11862111402fULL }, // Inst #2086 = PS_storerhnewabs
4990 { 2085, 2, 0, 4, 165, 0, 0, HexagonImpOpBase + 0, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x11062108002fULL }, // Inst #2085 = PS_storerhabs
4991 { 2084, 2, 0, 4, 165, 0, 0, HexagonImpOpBase + 0, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x11062100002fULL }, // Inst #2084 = PS_storerfabs
4992 { 2083, 2, 0, 4, 165, 0, 0, HexagonImpOpBase + 0, 738, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x210e6100002fULL }, // Inst #2083 = PS_storerdabs
4993 { 2082, 2, 0, 4, 166, 0, 0, HexagonImpOpBase + 0, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x9820111402fULL }, // Inst #2082 = PS_storerbnewabs
4994 { 2081, 2, 0, 4, 165, 0, 0, HexagonImpOpBase + 0, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x9020108002fULL }, // Inst #2081 = PS_storerbabs
4995 { 2080, 2, 1, 4, 147, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x11062300802fULL }, // Inst #2080 = PS_loadruhabs
4996 { 2079, 2, 1, 4, 147, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9020300802fULL }, // Inst #2079 = PS_loadrubabs
4997 { 2078, 2, 1, 4, 147, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x190a4300802fULL }, // Inst #2078 = PS_loadriabs
4998 { 2077, 2, 1, 4, 147, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x11062300802fULL }, // Inst #2077 = PS_loadrhabs
4999 { 2076, 2, 1, 4, 147, 0, 0, HexagonImpOpBase + 0, 167, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x210e6300002fULL }, // Inst #2076 = PS_loadrdabs
5000 { 2075, 2, 1, 4, 147, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9020300802fULL }, // Inst #2075 = PS_loadrbabs
5001 { 2074, 2, 0, 4, 124, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x801000001423ULL }, // Inst #2074 = PS_jmprettnewpt
5002 { 2073, 2, 0, 4, 124, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000001423ULL }, // Inst #2073 = PS_jmprettnew
5003 { 2072, 2, 0, 4, 16, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000423ULL }, // Inst #2072 = PS_jmprett
5004 { 2071, 2, 0, 4, 124, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x801000001c23ULL }, // Inst #2071 = PS_jmpretfnewpt
5005 { 2070, 2, 0, 4, 124, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000001c23ULL }, // Inst #2070 = PS_jmpretfnew
5006 { 2069, 2, 0, 4, 16, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000c23ULL }, // Inst #2069 = PS_jmpretf
5007 { 2068, 1, 0, 4, 40, 0, 1, HexagonImpOpBase + 55, 272, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x1000000023ULL }, // Inst #2068 = PS_jmpret
5008 { 2067, 1, 0, 4, 118, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000823ULL }, // Inst #2067 = PS_callr_nr
5009 { 2066, 1, 0, 4, 35, 0, 5, HexagonImpOpBase + 105, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2066 = PS_call_stk
5010 { 2065, 3, 1, 4, 33, 0, 1, HexagonImpOpBase + 63, 557, 0, 0x80000000008025ULL }, // Inst #2065 = M7_wcmpyrwc_rnd
5011 { 2064, 3, 1, 4, 33, 0, 1, HexagonImpOpBase + 63, 557, 0, 0x80000000008025ULL }, // Inst #2064 = M7_wcmpyrwc
5012 { 2063, 3, 1, 4, 33, 0, 1, HexagonImpOpBase + 63, 557, 0, 0x80000000008025ULL }, // Inst #2063 = M7_wcmpyrw_rnd
5013 { 2062, 3, 1, 4, 33, 0, 1, HexagonImpOpBase + 63, 557, 0, 0x80000000008025ULL }, // Inst #2062 = M7_wcmpyrw
5014 { 2061, 3, 1, 4, 33, 0, 1, HexagonImpOpBase + 63, 557, 0, 0x80000000008025ULL }, // Inst #2061 = M7_wcmpyiwc_rnd
5015 { 2060, 3, 1, 4, 33, 0, 1, HexagonImpOpBase + 63, 557, 0, 0x80000000008025ULL }, // Inst #2060 = M7_wcmpyiwc
5016 { 2059, 3, 1, 4, 33, 0, 1, HexagonImpOpBase + 63, 557, 0, 0x80000000008025ULL }, // Inst #2059 = M7_wcmpyiw_rnd
5017 { 2058, 3, 1, 4, 33, 0, 1, HexagonImpOpBase + 63, 557, 0, 0x80000000008025ULL }, // Inst #2058 = M7_wcmpyiw
5018 { 2057, 4, 1, 4, 34, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #2057 = M7_dcmpyrwc_acc
5019 { 2056, 3, 1, 4, 33, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #2056 = M7_dcmpyrwc
5020 { 2055, 4, 1, 4, 34, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #2055 = M7_dcmpyrw_acc
5021 { 2054, 3, 1, 4, 33, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #2054 = M7_dcmpyrw
5022 { 2053, 4, 1, 4, 34, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #2053 = M7_dcmpyiwc_acc
5023 { 2052, 3, 1, 4, 33, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #2052 = M7_dcmpyiwc
5024 { 2051, 4, 1, 4, 34, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #2051 = M7_dcmpyiw_acc
5025 { 2050, 3, 1, 4, 33, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #2050 = M7_dcmpyiw
5026 { 2049, 3, 1, 4, 96, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #2049 = M6_vabsdiffub
5027 { 2048, 3, 1, 4, 96, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #2048 = M6_vabsdiffb
5028 { 2047, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #2047 = M5_vrmpybuu
5029 { 2046, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #2046 = M5_vrmpybsu
5030 { 2045, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #2045 = M5_vrmacbuu
5031 { 2044, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #2044 = M5_vrmacbsu
5032 { 2043, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #2043 = M5_vmpybuu
5033 { 2042, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #2042 = M5_vmpybsu
5034 { 2041, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #2041 = M5_vmacbuu
5035 { 2040, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #2040 = M5_vmacbsu
5036 { 2039, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #2039 = M5_vdmpybsu
5037 { 2038, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #2038 = M5_vdmacbsu
5038 { 2037, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x8000000000002cULL }, // Inst #2037 = M4_xor_xacc
5039 { 2036, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #2036 = M4_xor_or
5040 { 2035, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #2035 = M4_xor_andn
5041 { 2034, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #2034 = M4_xor_and
5042 { 2033, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #2033 = M4_vrmpyoh_s1
5043 { 2032, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #2032 = M4_vrmpyoh_s0
5044 { 2031, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #2031 = M4_vrmpyoh_acc_s1
5045 { 2030, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #2030 = M4_vrmpyoh_acc_s0
5046 { 2029, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #2029 = M4_vrmpyeh_s1
5047 { 2028, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #2028 = M4_vrmpyeh_s0
5048 { 2027, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #2027 = M4_vrmpyeh_acc_s1
5049 { 2026, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #2026 = M4_vrmpyeh_acc_s0
5050 { 2025, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #2025 = M4_vpmpyh_acc
5051 { 2024, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #2024 = M4_vpmpyh
5052 { 2023, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #2023 = M4_pmpyw_acc
5053 { 2022, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #2022 = M4_pmpyw
5054 { 2021, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #2021 = M4_or_xor
5055 { 2020, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #2020 = M4_or_or
5056 { 2019, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #2019 = M4_or_andn
5057 { 2018, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #2018 = M4_or_and
5058 { 2017, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #2017 = M4_nac_up_s1_sat
5059 { 2016, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 734, 0, 0x80000000008025ULL }, // Inst #2016 = M4_mpyrr_addr
5060 { 2015, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 730, 0, 0x800000c2808003ULL }, // Inst #2015 = M4_mpyrr_addi
5061 { 2014, 4, 1, 4, 164, 0, 0, HexagonImpOpBase + 0, 726, 0, 0x80000000008003ULL }, // Inst #2014 = M4_mpyri_addr_u2
5062 { 2013, 4, 1, 4, 162, 0, 0, HexagonImpOpBase + 0, 219, 0, 0x800000c6808003ULL }, // Inst #2013 = M4_mpyri_addr
5063 { 2012, 4, 1, 4, 162, 0, 0, HexagonImpOpBase + 0, 722, 0, 0x800000c2808003ULL }, // Inst #2012 = M4_mpyri_addi
5064 { 2011, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #2011 = M4_mac_up_s1_sat
5065 { 2010, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 212, 0, 0x8000000000802cULL }, // Inst #2010 = M4_cmpyr_whc
5066 { 2009, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 212, 0, 0x8000000000802cULL }, // Inst #2009 = M4_cmpyr_wh
5067 { 2008, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 212, 0, 0x8000000000802cULL }, // Inst #2008 = M4_cmpyi_whc
5068 { 2007, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 212, 0, 0x8000000000802cULL }, // Inst #2007 = M4_cmpyi_wh
5069 { 2006, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #2006 = M4_and_xor
5070 { 2005, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #2005 = M4_and_or
5071 { 2004, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #2004 = M4_and_andn
5072 { 2003, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #2003 = M4_and_and
5073 { 2002, 4, 1, 4, 163, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #2002 = M2_xor_xacc
5074 { 2001, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #2001 = M2_vrmpy_s0
5075 { 2000, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #2000 = M2_vrmac_s0
5076 { 1999, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 557, 0, 0x80000000008025ULL }, // Inst #1999 = M2_vrcmpys_s1rp_l
5077 { 1998, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 557, 0, 0x80000000008025ULL }, // Inst #1998 = M2_vrcmpys_s1rp_h
5078 { 1997, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1997 = M2_vrcmpys_s1_l
5079 { 1996, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1996 = M2_vrcmpys_s1_h
5080 { 1995, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1995 = M2_vrcmpys_acc_s1_l
5081 { 1994, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1994 = M2_vrcmpys_acc_s1_h
5082 { 1993, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #1993 = M2_vrcmpyr_s0c
5083 { 1992, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #1992 = M2_vrcmpyr_s0
5084 { 1991, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #1991 = M2_vrcmpyi_s0c
5085 { 1990, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #1990 = M2_vrcmpyi_s0
5086 { 1989, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #1989 = M2_vrcmacr_s0c
5087 { 1988, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #1988 = M2_vrcmacr_s0
5088 { 1987, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #1987 = M2_vrcmaci_s0c
5089 { 1986, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #1986 = M2_vrcmaci_s0
5090 { 1985, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 557, 0, 0x80000000008025ULL }, // Inst #1985 = M2_vradduh
5091 { 1984, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 557, 0, 0x80000000008025ULL }, // Inst #1984 = M2_vraddh
5092 { 1983, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 519, 0, 0x80000000000025ULL }, // Inst #1983 = M2_vmpy2su_s1
5093 { 1982, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 519, 0, 0x80000000000025ULL }, // Inst #1982 = M2_vmpy2su_s0
5094 { 1981, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1981 = M2_vmpy2s_s1pack
5095 { 1980, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 519, 0, 0x80000000000025ULL }, // Inst #1980 = M2_vmpy2s_s1
5096 { 1979, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1979 = M2_vmpy2s_s0pack
5097 { 1978, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 519, 0, 0x80000000000025ULL }, // Inst #1978 = M2_vmpy2s_s0
5098 { 1977, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1977 = M2_vmpy2es_s1
5099 { 1976, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1976 = M2_vmpy2es_s0
5100 { 1975, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 718, 0, 0x80000000000025ULL }, // Inst #1975 = M2_vmac2su_s1
5101 { 1974, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 718, 0, 0x80000000000025ULL }, // Inst #1974 = M2_vmac2su_s0
5102 { 1973, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 718, 0, 0x80000000000025ULL }, // Inst #1973 = M2_vmac2s_s1
5103 { 1972, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 718, 0, 0x80000000000025ULL }, // Inst #1972 = M2_vmac2s_s0
5104 { 1971, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1971 = M2_vmac2es_s1
5105 { 1970, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1970 = M2_vmac2es_s0
5106 { 1969, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #1969 = M2_vmac2es
5107 { 1968, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1968 = M2_vmac2
5108 { 1967, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1967 = M2_vdmpys_s1
5109 { 1966, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1966 = M2_vdmpys_s0
5110 { 1965, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 557, 0, 0x80000000008025ULL }, // Inst #1965 = M2_vdmpyrs_s1
5111 { 1964, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 557, 0, 0x80000000008025ULL }, // Inst #1964 = M2_vdmpyrs_s0
5112 { 1963, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1963 = M2_vdmacs_s1
5113 { 1962, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1962 = M2_vdmacs_s0
5114 { 1961, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1961 = M2_vcmpy_s1_sat_r
5115 { 1960, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1960 = M2_vcmpy_s1_sat_i
5116 { 1959, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1959 = M2_vcmpy_s0_sat_r
5117 { 1958, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1958 = M2_vcmpy_s0_sat_i
5118 { 1957, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1957 = M2_vcmac_s0_sat_r
5119 { 1956, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1956 = M2_vcmac_s0_sat_i
5120 { 1955, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #1955 = M2_vabsdiffw
5121 { 1954, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #1954 = M2_vabsdiffh
5122 { 1953, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1953 = M2_subacc
5123 { 1952, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x80000116808025ULL }, // Inst #1952 = M2_naccii
5124 { 1951, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1951 = M2_nacci
5125 { 1950, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1950 = M2_mpyud_nac_ll_s1
5126 { 1949, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1949 = M2_mpyud_nac_ll_s0
5127 { 1948, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1948 = M2_mpyud_nac_lh_s1
5128 { 1947, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1947 = M2_mpyud_nac_lh_s0
5129 { 1946, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1946 = M2_mpyud_nac_hl_s1
5130 { 1945, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1945 = M2_mpyud_nac_hl_s0
5131 { 1944, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1944 = M2_mpyud_nac_hh_s1
5132 { 1943, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1943 = M2_mpyud_nac_hh_s0
5133 { 1942, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1942 = M2_mpyud_ll_s1
5134 { 1941, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1941 = M2_mpyud_ll_s0
5135 { 1940, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1940 = M2_mpyud_lh_s1
5136 { 1939, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1939 = M2_mpyud_lh_s0
5137 { 1938, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1938 = M2_mpyud_hl_s1
5138 { 1937, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1937 = M2_mpyud_hl_s0
5139 { 1936, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1936 = M2_mpyud_hh_s1
5140 { 1935, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1935 = M2_mpyud_hh_s0
5141 { 1934, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1934 = M2_mpyud_acc_ll_s1
5142 { 1933, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1933 = M2_mpyud_acc_ll_s0
5143 { 1932, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1932 = M2_mpyud_acc_lh_s1
5144 { 1931, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1931 = M2_mpyud_acc_lh_s0
5145 { 1930, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1930 = M2_mpyud_acc_hl_s1
5146 { 1929, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1929 = M2_mpyud_acc_hl_s0
5147 { 1928, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1928 = M2_mpyud_acc_hh_s1
5148 { 1927, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1927 = M2_mpyud_acc_hh_s0
5149 { 1926, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1926 = M2_mpyu_up
5150 { 1925, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1925 = M2_mpyu_nac_ll_s1
5151 { 1924, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1924 = M2_mpyu_nac_ll_s0
5152 { 1923, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1923 = M2_mpyu_nac_lh_s1
5153 { 1922, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1922 = M2_mpyu_nac_lh_s0
5154 { 1921, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1921 = M2_mpyu_nac_hl_s1
5155 { 1920, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1920 = M2_mpyu_nac_hl_s0
5156 { 1919, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1919 = M2_mpyu_nac_hh_s1
5157 { 1918, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1918 = M2_mpyu_nac_hh_s0
5158 { 1917, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1917 = M2_mpyu_ll_s1
5159 { 1916, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1916 = M2_mpyu_ll_s0
5160 { 1915, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1915 = M2_mpyu_lh_s1
5161 { 1914, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1914 = M2_mpyu_lh_s0
5162 { 1913, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1913 = M2_mpyu_hl_s1
5163 { 1912, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1912 = M2_mpyu_hl_s0
5164 { 1911, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1911 = M2_mpyu_hh_s1
5165 { 1910, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1910 = M2_mpyu_hh_s0
5166 { 1909, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1909 = M2_mpyu_acc_ll_s1
5167 { 1908, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1908 = M2_mpyu_acc_ll_s0
5168 { 1907, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1907 = M2_mpyu_acc_lh_s1
5169 { 1906, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1906 = M2_mpyu_acc_lh_s0
5170 { 1905, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1905 = M2_mpyu_acc_hl_s1
5171 { 1904, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1904 = M2_mpyu_acc_hl_s0
5172 { 1903, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1903 = M2_mpyu_acc_hh_s1
5173 { 1902, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1902 = M2_mpyu_acc_hh_s0
5174 { 1901, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1901 = M2_mpysu_up
5175 { 1900, 3, 1, 4, 30, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x80000104808025ULL }, // Inst #1900 = M2_mpysip
5176 { 1899, 3, 1, 4, 30, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x80000000008025ULL }, // Inst #1899 = M2_mpysin
5177 { 1898, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1898 = M2_mpyi
5178 { 1897, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1897 = M2_mpyd_rnd_ll_s1
5179 { 1896, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1896 = M2_mpyd_rnd_ll_s0
5180 { 1895, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1895 = M2_mpyd_rnd_lh_s1
5181 { 1894, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1894 = M2_mpyd_rnd_lh_s0
5182 { 1893, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1893 = M2_mpyd_rnd_hl_s1
5183 { 1892, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1892 = M2_mpyd_rnd_hl_s0
5184 { 1891, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1891 = M2_mpyd_rnd_hh_s1
5185 { 1890, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1890 = M2_mpyd_rnd_hh_s0
5186 { 1889, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1889 = M2_mpyd_nac_ll_s1
5187 { 1888, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1888 = M2_mpyd_nac_ll_s0
5188 { 1887, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1887 = M2_mpyd_nac_lh_s1
5189 { 1886, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1886 = M2_mpyd_nac_lh_s0
5190 { 1885, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1885 = M2_mpyd_nac_hl_s1
5191 { 1884, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1884 = M2_mpyd_nac_hl_s0
5192 { 1883, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1883 = M2_mpyd_nac_hh_s1
5193 { 1882, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1882 = M2_mpyd_nac_hh_s0
5194 { 1881, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1881 = M2_mpyd_ll_s1
5195 { 1880, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1880 = M2_mpyd_ll_s0
5196 { 1879, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1879 = M2_mpyd_lh_s1
5197 { 1878, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1878 = M2_mpyd_lh_s0
5198 { 1877, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1877 = M2_mpyd_hl_s1
5199 { 1876, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1876 = M2_mpyd_hl_s0
5200 { 1875, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1875 = M2_mpyd_hh_s1
5201 { 1874, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1874 = M2_mpyd_hh_s0
5202 { 1873, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1873 = M2_mpyd_acc_ll_s1
5203 { 1872, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1872 = M2_mpyd_acc_ll_s0
5204 { 1871, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1871 = M2_mpyd_acc_lh_s1
5205 { 1870, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1870 = M2_mpyd_acc_lh_s0
5206 { 1869, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1869 = M2_mpyd_acc_hl_s1
5207 { 1868, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1868 = M2_mpyd_acc_hl_s0
5208 { 1867, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1867 = M2_mpyd_acc_hh_s1
5209 { 1866, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1866 = M2_mpyd_acc_hh_s0
5210 { 1865, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1865 = M2_mpy_up_s1_sat
5211 { 1864, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1864 = M2_mpy_up_s1
5212 { 1863, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1863 = M2_mpy_up
5213 { 1862, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1862 = M2_mpy_sat_rnd_ll_s1
5214 { 1861, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1861 = M2_mpy_sat_rnd_ll_s0
5215 { 1860, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1860 = M2_mpy_sat_rnd_lh_s1
5216 { 1859, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1859 = M2_mpy_sat_rnd_lh_s0
5217 { 1858, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1858 = M2_mpy_sat_rnd_hl_s1
5218 { 1857, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1857 = M2_mpy_sat_rnd_hl_s0
5219 { 1856, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1856 = M2_mpy_sat_rnd_hh_s1
5220 { 1855, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1855 = M2_mpy_sat_rnd_hh_s0
5221 { 1854, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1854 = M2_mpy_sat_ll_s1
5222 { 1853, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1853 = M2_mpy_sat_ll_s0
5223 { 1852, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1852 = M2_mpy_sat_lh_s1
5224 { 1851, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1851 = M2_mpy_sat_lh_s0
5225 { 1850, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1850 = M2_mpy_sat_hl_s1
5226 { 1849, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1849 = M2_mpy_sat_hl_s0
5227 { 1848, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1848 = M2_mpy_sat_hh_s1
5228 { 1847, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1847 = M2_mpy_sat_hh_s0
5229 { 1846, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1846 = M2_mpy_rnd_ll_s1
5230 { 1845, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1845 = M2_mpy_rnd_ll_s0
5231 { 1844, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1844 = M2_mpy_rnd_lh_s1
5232 { 1843, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1843 = M2_mpy_rnd_lh_s0
5233 { 1842, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1842 = M2_mpy_rnd_hl_s1
5234 { 1841, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1841 = M2_mpy_rnd_hl_s0
5235 { 1840, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1840 = M2_mpy_rnd_hh_s1
5236 { 1839, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1839 = M2_mpy_rnd_hh_s0
5237 { 1838, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1838 = M2_mpy_nac_sat_ll_s1
5238 { 1837, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1837 = M2_mpy_nac_sat_ll_s0
5239 { 1836, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1836 = M2_mpy_nac_sat_lh_s1
5240 { 1835, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1835 = M2_mpy_nac_sat_lh_s0
5241 { 1834, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1834 = M2_mpy_nac_sat_hl_s1
5242 { 1833, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1833 = M2_mpy_nac_sat_hl_s0
5243 { 1832, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1832 = M2_mpy_nac_sat_hh_s1
5244 { 1831, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1831 = M2_mpy_nac_sat_hh_s0
5245 { 1830, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1830 = M2_mpy_nac_ll_s1
5246 { 1829, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1829 = M2_mpy_nac_ll_s0
5247 { 1828, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1828 = M2_mpy_nac_lh_s1
5248 { 1827, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1827 = M2_mpy_nac_lh_s0
5249 { 1826, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1826 = M2_mpy_nac_hl_s1
5250 { 1825, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1825 = M2_mpy_nac_hl_s0
5251 { 1824, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1824 = M2_mpy_nac_hh_s1
5252 { 1823, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1823 = M2_mpy_nac_hh_s0
5253 { 1822, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1822 = M2_mpy_ll_s1
5254 { 1821, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1821 = M2_mpy_ll_s0
5255 { 1820, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1820 = M2_mpy_lh_s1
5256 { 1819, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1819 = M2_mpy_lh_s0
5257 { 1818, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1818 = M2_mpy_hl_s1
5258 { 1817, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1817 = M2_mpy_hl_s0
5259 { 1816, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1816 = M2_mpy_hh_s1
5260 { 1815, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1815 = M2_mpy_hh_s0
5261 { 1814, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1814 = M2_mpy_acc_sat_ll_s1
5262 { 1813, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1813 = M2_mpy_acc_sat_ll_s0
5263 { 1812, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1812 = M2_mpy_acc_sat_lh_s1
5264 { 1811, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1811 = M2_mpy_acc_sat_lh_s0
5265 { 1810, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1810 = M2_mpy_acc_sat_hl_s1
5266 { 1809, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1809 = M2_mpy_acc_sat_hl_s0
5267 { 1808, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1808 = M2_mpy_acc_sat_hh_s1
5268 { 1807, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 590, 0, 0x80000000008025ULL }, // Inst #1807 = M2_mpy_acc_sat_hh_s0
5269 { 1806, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1806 = M2_mpy_acc_ll_s1
5270 { 1805, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1805 = M2_mpy_acc_ll_s0
5271 { 1804, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1804 = M2_mpy_acc_lh_s1
5272 { 1803, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1803 = M2_mpy_acc_lh_s0
5273 { 1802, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1802 = M2_mpy_acc_hl_s1
5274 { 1801, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1801 = M2_mpy_acc_hl_s0
5275 { 1800, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1800 = M2_mpy_acc_hh_s1
5276 { 1799, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1799 = M2_mpy_acc_hh_s0
5277 { 1798, 4, 1, 4, 107, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1798 = M2_mnaci
5278 { 1797, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1797 = M2_mmpyul_s1
5279 { 1796, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1796 = M2_mmpyul_s0
5280 { 1795, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1795 = M2_mmpyul_rs1
5281 { 1794, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1794 = M2_mmpyul_rs0
5282 { 1793, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1793 = M2_mmpyuh_s1
5283 { 1792, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1792 = M2_mmpyuh_s0
5284 { 1791, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1791 = M2_mmpyuh_rs1
5285 { 1790, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1790 = M2_mmpyuh_rs0
5286 { 1789, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1789 = M2_mmpyl_s1
5287 { 1788, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1788 = M2_mmpyl_s0
5288 { 1787, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1787 = M2_mmpyl_rs1
5289 { 1786, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1786 = M2_mmpyl_rs0
5290 { 1785, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1785 = M2_mmpyh_s1
5291 { 1784, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1784 = M2_mmpyh_s0
5292 { 1783, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1783 = M2_mmpyh_rs1
5293 { 1782, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000025ULL }, // Inst #1782 = M2_mmpyh_rs0
5294 { 1781, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1781 = M2_mmaculs_s1
5295 { 1780, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1780 = M2_mmaculs_s0
5296 { 1779, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1779 = M2_mmaculs_rs1
5297 { 1778, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1778 = M2_mmaculs_rs0
5298 { 1777, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1777 = M2_mmacuhs_s1
5299 { 1776, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1776 = M2_mmacuhs_s0
5300 { 1775, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1775 = M2_mmacuhs_rs1
5301 { 1774, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1774 = M2_mmacuhs_rs0
5302 { 1773, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1773 = M2_mmacls_s1
5303 { 1772, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1772 = M2_mmacls_s0
5304 { 1771, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1771 = M2_mmacls_rs1
5305 { 1770, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1770 = M2_mmacls_rs0
5306 { 1769, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1769 = M2_mmachs_s1
5307 { 1768, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1768 = M2_mmachs_s0
5308 { 1767, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1767 = M2_mmachs_rs1
5309 { 1766, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 215, 0, 0x80000000000025ULL }, // Inst #1766 = M2_mmachs_rs0
5310 { 1765, 4, 1, 4, 162, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x80000106808025ULL }, // Inst #1765 = M2_macsip
5311 { 1764, 4, 1, 4, 162, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x80000106808025ULL }, // Inst #1764 = M2_macsin
5312 { 1763, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1763 = M2_maci
5313 { 1762, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1762 = M2_hmmpyl_s1
5314 { 1761, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1761 = M2_hmmpyl_rs1
5315 { 1760, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1760 = M2_hmmpyh_s1
5316 { 1759, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1759 = M2_hmmpyh_rs1
5317 { 1758, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1758 = M2_dpmpyuu_s0
5318 { 1757, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1757 = M2_dpmpyuu_nac_s0
5319 { 1756, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1756 = M2_dpmpyuu_acc_s0
5320 { 1755, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1755 = M2_dpmpyss_s0
5321 { 1754, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008025ULL }, // Inst #1754 = M2_dpmpyss_rnd_s0
5322 { 1753, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1753 = M2_dpmpyss_nac_s0
5323 { 1752, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1752 = M2_dpmpyss_acc_s0
5324 { 1751, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 718, 0, 0x80000000000025ULL }, // Inst #1751 = M2_cnacsc_s1
5325 { 1750, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 718, 0, 0x80000000000025ULL }, // Inst #1750 = M2_cnacsc_s0
5326 { 1749, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 718, 0, 0x80000000000025ULL }, // Inst #1749 = M2_cnacs_s1
5327 { 1748, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 718, 0, 0x80000000000025ULL }, // Inst #1748 = M2_cnacs_s0
5328 { 1747, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 519, 0, 0x80000000000025ULL }, // Inst #1747 = M2_cmpysc_s1
5329 { 1746, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 519, 0, 0x80000000000025ULL }, // Inst #1746 = M2_cmpysc_s0
5330 { 1745, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 519, 0, 0x80000000000025ULL }, // Inst #1745 = M2_cmpys_s1
5331 { 1744, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 519, 0, 0x80000000000025ULL }, // Inst #1744 = M2_cmpys_s0
5332 { 1743, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1743 = M2_cmpyrsc_s1
5333 { 1742, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1742 = M2_cmpyrsc_s0
5334 { 1741, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1741 = M2_cmpyrs_s1
5335 { 1740, 3, 1, 4, 31, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008025ULL }, // Inst #1740 = M2_cmpyrs_s0
5336 { 1739, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1739 = M2_cmpyr_s0
5337 { 1738, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000025ULL }, // Inst #1738 = M2_cmpyi_s0
5338 { 1737, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 718, 0, 0x80000000000025ULL }, // Inst #1737 = M2_cmacsc_s1
5339 { 1736, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 718, 0, 0x80000000000025ULL }, // Inst #1736 = M2_cmacsc_s0
5340 { 1735, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 718, 0, 0x80000000000025ULL }, // Inst #1735 = M2_cmacs_s1
5341 { 1734, 4, 1, 4, 32, 0, 1, HexagonImpOpBase + 63, 718, 0, 0x80000000000025ULL }, // Inst #1734 = M2_cmacs_s0
5342 { 1733, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1733 = M2_cmacr_s0
5343 { 1732, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 718, 0, 0x80000000000025ULL }, // Inst #1732 = M2_cmaci_s0
5344 { 1731, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 714, 0, 0x80000116808025ULL }, // Inst #1731 = M2_accii
5345 { 1730, 4, 1, 4, 161, 0, 0, HexagonImpOpBase + 0, 590, 0, 0x80000000008025ULL }, // Inst #1730 = M2_acci
5346 { 1729, 2, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x8000ULL }, // Inst #1729 = LO
5347 { 1728, 3, 0, 4, 160, 0, 0, HexagonImpOpBase + 0, 711, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa4ULL }, // Inst #1728 = L6_memcpy
5348 { 1727, 3, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1727 = L4_sub_memopw_io
5349 { 1726, 3, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1726 = L4_sub_memoph_io
5350 { 1725, 3, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1725 = L4_sub_memopb_io
5351 { 1724, 3, 1, 4, 24, 1, 2, HexagonImpOpBase + 102, 192, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xa09000001424ULL }, // Inst #1724 = L4_return_tnew_pt
5352 { 1723, 3, 1, 4, 24, 1, 2, HexagonImpOpBase + 102, 192, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x209000001424ULL }, // Inst #1723 = L4_return_tnew_pnt
5353 { 1722, 3, 1, 4, 23, 1, 2, HexagonImpOpBase + 102, 192, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xa09000000424ULL }, // Inst #1722 = L4_return_t
5354 { 1721, 3, 1, 4, 24, 1, 2, HexagonImpOpBase + 102, 192, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xa09000001c24ULL }, // Inst #1721 = L4_return_fnew_pt
5355 { 1720, 3, 1, 4, 24, 1, 2, HexagonImpOpBase + 102, 192, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x209000001c24ULL }, // Inst #1720 = L4_return_fnew_pnt
5356 { 1719, 3, 1, 4, 23, 1, 2, HexagonImpOpBase + 102, 192, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xa09000000c24ULL }, // Inst #1719 = L4_return_f
5357 { 1718, 2, 1, 4, 28, 1, 2, HexagonImpOpBase + 102, 190, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xa09000000024ULL }, // Inst #1718 = L4_return
5358 { 1717, 5, 1, 4, 159, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0x150000009424ULL }, // Inst #1717 = L4_ploadruhtnew_rr
5359 { 1716, 3, 1, 4, 153, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x1100c5809424ULL }, // Inst #1716 = L4_ploadruhtnew_abs
5360 { 1715, 5, 1, 4, 158, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0x150000008424ULL }, // Inst #1715 = L4_ploadruht_rr
5361 { 1714, 3, 1, 4, 157, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x1100c5808424ULL }, // Inst #1714 = L4_ploadruht_abs
5362 { 1713, 5, 1, 4, 159, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0x150000009c24ULL }, // Inst #1713 = L4_ploadruhfnew_rr
5363 { 1712, 3, 1, 4, 153, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x1100c5809c24ULL }, // Inst #1712 = L4_ploadruhfnew_abs
5364 { 1711, 5, 1, 4, 158, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0x150000008c24ULL }, // Inst #1711 = L4_ploadruhf_rr
5365 { 1710, 3, 1, 4, 157, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x1100c5808c24ULL }, // Inst #1710 = L4_ploadruhf_abs
5366 { 1709, 5, 1, 4, 159, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0xd0000009424ULL }, // Inst #1709 = L4_ploadrubtnew_rr
5367 { 1708, 3, 1, 4, 153, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x900c5809424ULL }, // Inst #1708 = L4_ploadrubtnew_abs
5368 { 1707, 5, 1, 4, 158, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0xd0000008424ULL }, // Inst #1707 = L4_ploadrubt_rr
5369 { 1706, 3, 1, 4, 157, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x900c5808424ULL }, // Inst #1706 = L4_ploadrubt_abs
5370 { 1705, 5, 1, 4, 159, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0xd0000009c24ULL }, // Inst #1705 = L4_ploadrubfnew_rr
5371 { 1704, 3, 1, 4, 153, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x900c5809c24ULL }, // Inst #1704 = L4_ploadrubfnew_abs
5372 { 1703, 5, 1, 4, 158, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0xd0000008c24ULL }, // Inst #1703 = L4_ploadrubf_rr
5373 { 1702, 3, 1, 4, 157, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x900c5808c24ULL }, // Inst #1702 = L4_ploadrubf_abs
5374 { 1701, 5, 1, 4, 159, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0x1d0000009424ULL }, // Inst #1701 = L4_ploadritnew_rr
5375 { 1700, 3, 1, 4, 153, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x1900c5809424ULL }, // Inst #1700 = L4_ploadritnew_abs
5376 { 1699, 5, 1, 4, 158, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0x1d0000008424ULL }, // Inst #1699 = L4_ploadrit_rr
5377 { 1698, 3, 1, 4, 157, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x1900c5808424ULL }, // Inst #1698 = L4_ploadrit_abs
5378 { 1697, 5, 1, 4, 159, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0x1d0000009c24ULL }, // Inst #1697 = L4_ploadrifnew_rr
5379 { 1696, 3, 1, 4, 153, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x1900c5809c24ULL }, // Inst #1696 = L4_ploadrifnew_abs
5380 { 1695, 5, 1, 4, 158, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0x1d0000008c24ULL }, // Inst #1695 = L4_ploadrif_rr
5381 { 1694, 3, 1, 4, 157, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x1900c5808c24ULL }, // Inst #1694 = L4_ploadrif_abs
5382 { 1693, 5, 1, 4, 159, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0x150000009424ULL }, // Inst #1693 = L4_ploadrhtnew_rr
5383 { 1692, 3, 1, 4, 153, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x1100c5809424ULL }, // Inst #1692 = L4_ploadrhtnew_abs
5384 { 1691, 5, 1, 4, 158, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0x150000008424ULL }, // Inst #1691 = L4_ploadrht_rr
5385 { 1690, 3, 1, 4, 157, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x1100c5808424ULL }, // Inst #1690 = L4_ploadrht_abs
5386 { 1689, 5, 1, 4, 159, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0x150000009c24ULL }, // Inst #1689 = L4_ploadrhfnew_rr
5387 { 1688, 3, 1, 4, 153, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x1100c5809c24ULL }, // Inst #1688 = L4_ploadrhfnew_abs
5388 { 1687, 5, 1, 4, 158, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0x150000008c24ULL }, // Inst #1687 = L4_ploadrhf_rr
5389 { 1686, 3, 1, 4, 157, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x1100c5808c24ULL }, // Inst #1686 = L4_ploadrhf_abs
5390 { 1685, 5, 1, 4, 159, 0, 0, HexagonImpOpBase + 0, 706, 0|(1ULL<<MCID::MayLoad), 0x250000001424ULL }, // Inst #1685 = L4_ploadrdtnew_rr
5391 { 1684, 3, 1, 4, 153, 0, 0, HexagonImpOpBase + 0, 703, 0|(1ULL<<MCID::MayLoad), 0x2100c5801424ULL }, // Inst #1684 = L4_ploadrdtnew_abs
5392 { 1683, 5, 1, 4, 158, 0, 0, HexagonImpOpBase + 0, 706, 0|(1ULL<<MCID::MayLoad), 0x250000000424ULL }, // Inst #1683 = L4_ploadrdt_rr
5393 { 1682, 3, 1, 4, 157, 0, 0, HexagonImpOpBase + 0, 703, 0|(1ULL<<MCID::MayLoad), 0x2100c5800424ULL }, // Inst #1682 = L4_ploadrdt_abs
5394 { 1681, 5, 1, 4, 159, 0, 0, HexagonImpOpBase + 0, 706, 0|(1ULL<<MCID::MayLoad), 0x250000001c24ULL }, // Inst #1681 = L4_ploadrdfnew_rr
5395 { 1680, 3, 1, 4, 153, 0, 0, HexagonImpOpBase + 0, 703, 0|(1ULL<<MCID::MayLoad), 0x2100c5801c24ULL }, // Inst #1680 = L4_ploadrdfnew_abs
5396 { 1679, 5, 1, 4, 158, 0, 0, HexagonImpOpBase + 0, 706, 0|(1ULL<<MCID::MayLoad), 0x250000000c24ULL }, // Inst #1679 = L4_ploadrdf_rr
5397 { 1678, 3, 1, 4, 157, 0, 0, HexagonImpOpBase + 0, 703, 0|(1ULL<<MCID::MayLoad), 0x2100c5800c24ULL }, // Inst #1678 = L4_ploadrdf_abs
5398 { 1677, 5, 1, 4, 159, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0xd0000009424ULL }, // Inst #1677 = L4_ploadrbtnew_rr
5399 { 1676, 3, 1, 4, 153, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x900c5809424ULL }, // Inst #1676 = L4_ploadrbtnew_abs
5400 { 1675, 5, 1, 4, 158, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0xd0000008424ULL }, // Inst #1675 = L4_ploadrbt_rr
5401 { 1674, 3, 1, 4, 157, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x900c5808424ULL }, // Inst #1674 = L4_ploadrbt_abs
5402 { 1673, 5, 1, 4, 159, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0xd0000009c24ULL }, // Inst #1673 = L4_ploadrbfnew_rr
5403 { 1672, 3, 1, 4, 153, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x900c5809c24ULL }, // Inst #1672 = L4_ploadrbfnew_abs
5404 { 1671, 5, 1, 4, 158, 0, 0, HexagonImpOpBase + 0, 698, 0|(1ULL<<MCID::MayLoad), 0xd0000008c24ULL }, // Inst #1671 = L4_ploadrbf_rr
5405 { 1670, 3, 1, 4, 157, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x900c5808c24ULL }, // Inst #1670 = L4_ploadrbf_abs
5406 { 1669, 3, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1669 = L4_or_memopw_io
5407 { 1668, 3, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1668 = L4_or_memoph_io
5408 { 1667, 3, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1667 = L4_or_memopb_io
5409 { 1666, 3, 1, 4, 156, 0, 0, HexagonImpOpBase + 0, 202, 0|(1ULL<<MCID::MayLoad), 0x1800000080a4ULL }, // Inst #1666 = L4_loadw_phys
5410 { 1665, 4, 1, 4, 154, 0, 0, HexagonImpOpBase + 0, 686, 0|(1ULL<<MCID::MayLoad), 0x1400c7808024ULL }, // Inst #1665 = L4_loadruh_ur
5411 { 1664, 4, 1, 4, 155, 0, 0, HexagonImpOpBase + 0, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x150000008024ULL }, // Inst #1664 = L4_loadruh_rr
5412 { 1663, 3, 2, 4, 153, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad), 0x1200c5808024ULL }, // Inst #1663 = L4_loadruh_ap
5413 { 1662, 4, 1, 4, 154, 0, 0, HexagonImpOpBase + 0, 686, 0|(1ULL<<MCID::MayLoad), 0xc00c7808024ULL }, // Inst #1662 = L4_loadrub_ur
5414 { 1661, 4, 1, 4, 155, 0, 0, HexagonImpOpBase + 0, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xd0000008024ULL }, // Inst #1661 = L4_loadrub_rr
5415 { 1660, 3, 2, 4, 153, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad), 0xa00c5808024ULL }, // Inst #1660 = L4_loadrub_ap
5416 { 1659, 4, 1, 4, 154, 0, 0, HexagonImpOpBase + 0, 686, 0|(1ULL<<MCID::MayLoad), 0x1c00c7808024ULL }, // Inst #1659 = L4_loadri_ur
5417 { 1658, 4, 1, 4, 155, 0, 0, HexagonImpOpBase + 0, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1d0000008024ULL }, // Inst #1658 = L4_loadri_rr
5418 { 1657, 3, 2, 4, 153, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad), 0x1a00c5808024ULL }, // Inst #1657 = L4_loadri_ap
5419 { 1656, 4, 1, 4, 154, 0, 0, HexagonImpOpBase + 0, 686, 0|(1ULL<<MCID::MayLoad), 0x1400c7808024ULL }, // Inst #1656 = L4_loadrh_ur
5420 { 1655, 4, 1, 4, 155, 0, 0, HexagonImpOpBase + 0, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x150000008024ULL }, // Inst #1655 = L4_loadrh_rr
5421 { 1654, 3, 2, 4, 153, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad), 0x1200c5808024ULL }, // Inst #1654 = L4_loadrh_ap
5422 { 1653, 4, 1, 4, 154, 0, 0, HexagonImpOpBase + 0, 690, 0|(1ULL<<MCID::MayLoad), 0x2400c7800024ULL }, // Inst #1653 = L4_loadrd_ur
5423 { 1652, 4, 1, 4, 155, 0, 0, HexagonImpOpBase + 0, 694, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x250000000024ULL }, // Inst #1652 = L4_loadrd_rr
5424 { 1651, 3, 2, 4, 153, 0, 0, HexagonImpOpBase + 0, 501, 0|(1ULL<<MCID::MayLoad), 0x2200c5800024ULL }, // Inst #1651 = L4_loadrd_ap
5425 { 1650, 4, 1, 4, 154, 0, 0, HexagonImpOpBase + 0, 686, 0|(1ULL<<MCID::MayLoad), 0xc00c7808024ULL }, // Inst #1650 = L4_loadrb_ur
5426 { 1649, 4, 1, 4, 155, 0, 0, HexagonImpOpBase + 0, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xd0000008024ULL }, // Inst #1649 = L4_loadrb_rr
5427 { 1648, 3, 2, 4, 153, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad), 0xa00c5808024ULL }, // Inst #1648 = L4_loadrb_ap
5428 { 1647, 2, 1, 4, 149, 0, 0, HexagonImpOpBase + 0, 190, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200000000124ULL }, // Inst #1647 = L4_loadd_locked
5429 { 1646, 2, 1, 4, 148, 0, 0, HexagonImpOpBase + 0, 190, 0|(1ULL<<MCID::MayLoad), 0x200000000024ULL }, // Inst #1646 = L4_loadd_aq
5430 { 1645, 4, 1, 4, 154, 0, 0, HexagonImpOpBase + 0, 690, 0|(1ULL<<MCID::MayLoad), 0x1c00c7800024ULL }, // Inst #1645 = L4_loadbzw4_ur
5431 { 1644, 3, 2, 4, 153, 0, 0, HexagonImpOpBase + 0, 501, 0|(1ULL<<MCID::MayLoad), 0x1a00c5800024ULL }, // Inst #1644 = L4_loadbzw4_ap
5432 { 1643, 4, 1, 4, 154, 0, 0, HexagonImpOpBase + 0, 686, 0|(1ULL<<MCID::MayLoad), 0x1400c7808024ULL }, // Inst #1643 = L4_loadbzw2_ur
5433 { 1642, 3, 2, 4, 153, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad), 0x1200c5808024ULL }, // Inst #1642 = L4_loadbzw2_ap
5434 { 1641, 4, 1, 4, 154, 0, 0, HexagonImpOpBase + 0, 690, 0|(1ULL<<MCID::MayLoad), 0x1c00c7800024ULL }, // Inst #1641 = L4_loadbsw4_ur
5435 { 1640, 3, 2, 4, 153, 0, 0, HexagonImpOpBase + 0, 501, 0|(1ULL<<MCID::MayLoad), 0x1a00c5800024ULL }, // Inst #1640 = L4_loadbsw4_ap
5436 { 1639, 4, 1, 4, 154, 0, 0, HexagonImpOpBase + 0, 686, 0|(1ULL<<MCID::MayLoad), 0x1400c7808024ULL }, // Inst #1639 = L4_loadbsw2_ur
5437 { 1638, 3, 2, 4, 153, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad), 0x1200c5808024ULL }, // Inst #1638 = L4_loadbsw2_ap
5438 { 1637, 5, 1, 4, 152, 0, 0, HexagonImpOpBase + 0, 681, 0|(1ULL<<MCID::MayLoad), 0x1400c9800024ULL }, // Inst #1637 = L4_loadalignh_ur
5439 { 1636, 4, 2, 4, 151, 0, 0, HexagonImpOpBase + 0, 677, 0|(1ULL<<MCID::MayLoad), 0x1200c7800024ULL }, // Inst #1636 = L4_loadalignh_ap
5440 { 1635, 5, 1, 4, 152, 0, 0, HexagonImpOpBase + 0, 681, 0|(1ULL<<MCID::MayLoad), 0xc00c9800024ULL }, // Inst #1635 = L4_loadalignb_ur
5441 { 1634, 4, 2, 4, 151, 0, 0, HexagonImpOpBase + 0, 677, 0|(1ULL<<MCID::MayLoad), 0xa00c7800024ULL }, // Inst #1634 = L4_loadalignb_ap
5442 { 1633, 3, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1633 = L4_isub_memopw_io
5443 { 1632, 3, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1632 = L4_isub_memoph_io
5444 { 1631, 3, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1631 = L4_isub_memopb_io
5445 { 1630, 3, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1630 = L4_ior_memopw_io
5446 { 1629, 3, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1629 = L4_ior_memoph_io
5447 { 1628, 3, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1628 = L4_ior_memopb_io
5448 { 1627, 3, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1627 = L4_iand_memopw_io
5449 { 1626, 3, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1626 = L4_iand_memoph_io
5450 { 1625, 3, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1625 = L4_iand_memopb_io
5451 { 1624, 3, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1624 = L4_iadd_memopw_io
5452 { 1623, 3, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1623 = L4_iadd_memoph_io
5453 { 1622, 3, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1622 = L4_iadd_memopb_io
5454 { 1621, 3, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1621 = L4_and_memopw_io
5455 { 1620, 3, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1620 = L4_and_memoph_io
5456 { 1619, 3, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1619 = L4_and_memopb_io
5457 { 1618, 3, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1618 = L4_add_memopw_io
5458 { 1617, 3, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1617 = L4_add_memoph_io
5459 { 1616, 3, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1616 = L4_add_memopb_io
5460 { 1615, 5, 2, 4, 150, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0x160000009424ULL }, // Inst #1615 = L2_ploadruhtnew_pi
5461 { 1614, 4, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0x1304e680942fULL }, // Inst #1614 = L2_ploadruhtnew_io
5462 { 1613, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0x160000008424ULL }, // Inst #1613 = L2_ploadruht_pi
5463 { 1612, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0x1304e680842fULL }, // Inst #1612 = L2_ploadruht_io
5464 { 1611, 5, 2, 4, 150, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0x160000009c24ULL }, // Inst #1611 = L2_ploadruhfnew_pi
5465 { 1610, 4, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0x1304e6809c2fULL }, // Inst #1610 = L2_ploadruhfnew_io
5466 { 1609, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0x160000008c24ULL }, // Inst #1609 = L2_ploadruhf_pi
5467 { 1608, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0x1304e6808c2fULL }, // Inst #1608 = L2_ploadruhf_io
5468 { 1607, 5, 2, 4, 150, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0xe0000009424ULL }, // Inst #1607 = L2_ploadrubtnew_pi
5469 { 1606, 4, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0xb00c680942fULL }, // Inst #1606 = L2_ploadrubtnew_io
5470 { 1605, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0xe0000008424ULL }, // Inst #1605 = L2_ploadrubt_pi
5471 { 1604, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0xb00c680842fULL }, // Inst #1604 = L2_ploadrubt_io
5472 { 1603, 5, 2, 4, 150, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0xe0000009c24ULL }, // Inst #1603 = L2_ploadrubfnew_pi
5473 { 1602, 4, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0xb00c6809c2fULL }, // Inst #1602 = L2_ploadrubfnew_io
5474 { 1601, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0xe0000008c24ULL }, // Inst #1601 = L2_ploadrubf_pi
5475 { 1600, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0xb00c6808c2fULL }, // Inst #1600 = L2_ploadrubf_io
5476 { 1599, 5, 2, 4, 150, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0x1e0000009424ULL }, // Inst #1599 = L2_ploadritnew_pi
5477 { 1598, 4, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0x1b090680942fULL }, // Inst #1598 = L2_ploadritnew_io
5478 { 1597, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0x1e0000008424ULL }, // Inst #1597 = L2_ploadrit_pi
5479 { 1596, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0x1b090680842fULL }, // Inst #1596 = L2_ploadrit_io
5480 { 1595, 5, 2, 4, 150, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0x1e0000009c24ULL }, // Inst #1595 = L2_ploadrifnew_pi
5481 { 1594, 4, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0x1b0906809c2fULL }, // Inst #1594 = L2_ploadrifnew_io
5482 { 1593, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0x1e0000008c24ULL }, // Inst #1593 = L2_ploadrif_pi
5483 { 1592, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0x1b0906808c2fULL }, // Inst #1592 = L2_ploadrif_io
5484 { 1591, 5, 2, 4, 150, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0x160000009424ULL }, // Inst #1591 = L2_ploadrhtnew_pi
5485 { 1590, 4, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0x1304e680942fULL }, // Inst #1590 = L2_ploadrhtnew_io
5486 { 1589, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0x160000008424ULL }, // Inst #1589 = L2_ploadrht_pi
5487 { 1588, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0x1304e680842fULL }, // Inst #1588 = L2_ploadrht_io
5488 { 1587, 5, 2, 4, 150, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0x160000009c24ULL }, // Inst #1587 = L2_ploadrhfnew_pi
5489 { 1586, 4, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0x1304e6809c2fULL }, // Inst #1586 = L2_ploadrhfnew_io
5490 { 1585, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0x160000008c24ULL }, // Inst #1585 = L2_ploadrhf_pi
5491 { 1584, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0x1304e6808c2fULL }, // Inst #1584 = L2_ploadrhf_io
5492 { 1583, 5, 2, 4, 150, 0, 0, HexagonImpOpBase + 0, 672, 0|(1ULL<<MCID::MayLoad), 0x260000001424ULL }, // Inst #1583 = L2_ploadrdtnew_pi
5493 { 1582, 4, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 668, 0|(1ULL<<MCID::MayLoad), 0x230d2680142fULL }, // Inst #1582 = L2_ploadrdtnew_io
5494 { 1581, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 672, 0|(1ULL<<MCID::MayLoad), 0x260000000424ULL }, // Inst #1581 = L2_ploadrdt_pi
5495 { 1580, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 668, 0|(1ULL<<MCID::MayLoad), 0x230d2680042fULL }, // Inst #1580 = L2_ploadrdt_io
5496 { 1579, 5, 2, 4, 150, 0, 0, HexagonImpOpBase + 0, 672, 0|(1ULL<<MCID::MayLoad), 0x260000001c24ULL }, // Inst #1579 = L2_ploadrdfnew_pi
5497 { 1578, 4, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 668, 0|(1ULL<<MCID::MayLoad), 0x230d26801c2fULL }, // Inst #1578 = L2_ploadrdfnew_io
5498 { 1577, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 672, 0|(1ULL<<MCID::MayLoad), 0x260000000c24ULL }, // Inst #1577 = L2_ploadrdf_pi
5499 { 1576, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 668, 0|(1ULL<<MCID::MayLoad), 0x230d26800c2fULL }, // Inst #1576 = L2_ploadrdf_io
5500 { 1575, 5, 2, 4, 150, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0xe0000009424ULL }, // Inst #1575 = L2_ploadrbtnew_pi
5501 { 1574, 4, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0xb00c680942fULL }, // Inst #1574 = L2_ploadrbtnew_io
5502 { 1573, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0xe0000008424ULL }, // Inst #1573 = L2_ploadrbt_pi
5503 { 1572, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0xb00c680842fULL }, // Inst #1572 = L2_ploadrbt_io
5504 { 1571, 5, 2, 4, 150, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0xe0000009c24ULL }, // Inst #1571 = L2_ploadrbfnew_pi
5505 { 1570, 4, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0xb00c6809c2fULL }, // Inst #1570 = L2_ploadrbfnew_io
5506 { 1569, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad), 0xe0000008c24ULL }, // Inst #1569 = L2_ploadrbf_pi
5507 { 1568, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 526, 0|(1ULL<<MCID::MayLoad), 0xb00c6808c2fULL }, // Inst #1568 = L2_ploadrbf_io
5508 { 1567, 2, 1, 4, 149, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x180000008124ULL }, // Inst #1567 = L2_loadw_locked
5509 { 1566, 2, 1, 4, 148, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::MayLoad), 0x180000008024ULL }, // Inst #1566 = L2_loadw_aq
5510 { 1565, 2, 1, 4, 147, 1, 0, HexagonImpOpBase + 101, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10062200802fULL }, // Inst #1565 = L2_loadruhgp
5511 { 1564, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1564 = L2_loadruh_pr
5512 { 1563, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 646, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x160000008024ULL }, // Inst #1563 = L2_loadruh_pi
5513 { 1562, 4, 2, 4, 20, 1, 0, HexagonImpOpBase + 100, 637, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1562 = L2_loadruh_pcr
5514 { 1561, 5, 2, 4, 36, 1, 0, HexagonImpOpBase + 100, 641, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1561 = L2_loadruh_pci
5515 { 1560, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1560 = L2_loadruh_pbr
5516 { 1559, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x130594808024ULL }, // Inst #1559 = L2_loadruh_io
5517 { 1558, 2, 1, 4, 147, 1, 0, HexagonImpOpBase + 101, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x8020200802fULL }, // Inst #1558 = L2_loadrubgp
5518 { 1557, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1557 = L2_loadrub_pr
5519 { 1556, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 646, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xe0000008024ULL }, // Inst #1556 = L2_loadrub_pi
5520 { 1555, 4, 2, 4, 20, 1, 0, HexagonImpOpBase + 100, 637, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1555 = L2_loadrub_pcr
5521 { 1554, 5, 2, 4, 36, 1, 0, HexagonImpOpBase + 100, 641, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1554 = L2_loadrub_pci
5522 { 1553, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1553 = L2_loadrub_pbr
5523 { 1552, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xb0174808024ULL }, // Inst #1552 = L2_loadrub_io
5524 { 1551, 2, 1, 4, 147, 1, 0, HexagonImpOpBase + 101, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x180a4200802fULL }, // Inst #1551 = L2_loadrigp
5525 { 1550, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0x1e0000008024ULL }, // Inst #1550 = L2_loadri_pr
5526 { 1549, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 646, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1e0000008024ULL }, // Inst #1549 = L2_loadri_pi
5527 { 1548, 4, 2, 4, 20, 1, 0, HexagonImpOpBase + 100, 637, 0|(1ULL<<MCID::MayLoad), 0x1e0000008024ULL }, // Inst #1548 = L2_loadri_pcr
5528 { 1547, 5, 2, 4, 36, 1, 0, HexagonImpOpBase + 100, 641, 0|(1ULL<<MCID::MayLoad), 0x1e0000008024ULL }, // Inst #1547 = L2_loadri_pci
5529 { 1546, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0x1e0000008024ULL }, // Inst #1546 = L2_loadri_pbr
5530 { 1545, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1b09b4808024ULL }, // Inst #1545 = L2_loadri_io
5531 { 1544, 2, 1, 4, 147, 1, 0, HexagonImpOpBase + 101, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10062200802fULL }, // Inst #1544 = L2_loadrhgp
5532 { 1543, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1543 = L2_loadrh_pr
5533 { 1542, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 646, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x160000008024ULL }, // Inst #1542 = L2_loadrh_pi
5534 { 1541, 4, 2, 4, 20, 1, 0, HexagonImpOpBase + 100, 637, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1541 = L2_loadrh_pcr
5535 { 1540, 5, 2, 4, 36, 1, 0, HexagonImpOpBase + 100, 641, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1540 = L2_loadrh_pci
5536 { 1539, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1539 = L2_loadrh_pbr
5537 { 1538, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x130594808024ULL }, // Inst #1538 = L2_loadrh_io
5538 { 1537, 2, 1, 4, 147, 1, 0, HexagonImpOpBase + 101, 167, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x200e6200002fULL }, // Inst #1537 = L2_loadrdgp
5539 { 1536, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 650, 0|(1ULL<<MCID::MayLoad), 0x260000000024ULL }, // Inst #1536 = L2_loadrd_pr
5540 { 1535, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 659, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x260000000024ULL }, // Inst #1535 = L2_loadrd_pi
5541 { 1534, 4, 2, 4, 20, 1, 0, HexagonImpOpBase + 100, 650, 0|(1ULL<<MCID::MayLoad), 0x260000000024ULL }, // Inst #1534 = L2_loadrd_pcr
5542 { 1533, 5, 2, 4, 36, 1, 0, HexagonImpOpBase + 100, 654, 0|(1ULL<<MCID::MayLoad), 0x260000000024ULL }, // Inst #1533 = L2_loadrd_pci
5543 { 1532, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 650, 0|(1ULL<<MCID::MayLoad), 0x260000000024ULL }, // Inst #1532 = L2_loadrd_pbr
5544 { 1531, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 501, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x230dd4800024ULL }, // Inst #1531 = L2_loadrd_io
5545 { 1530, 2, 1, 4, 147, 1, 0, HexagonImpOpBase + 101, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x8020200802fULL }, // Inst #1530 = L2_loadrbgp
5546 { 1529, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1529 = L2_loadrb_pr
5547 { 1528, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 646, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xe0000008024ULL }, // Inst #1528 = L2_loadrb_pi
5548 { 1527, 4, 2, 4, 20, 1, 0, HexagonImpOpBase + 100, 637, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1527 = L2_loadrb_pcr
5549 { 1526, 5, 2, 4, 36, 1, 0, HexagonImpOpBase + 100, 641, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1526 = L2_loadrb_pci
5550 { 1525, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1525 = L2_loadrb_pbr
5551 { 1524, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xb0174808024ULL }, // Inst #1524 = L2_loadrb_io
5552 { 1523, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 650, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1523 = L2_loadbzw4_pr
5553 { 1522, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 659, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1522 = L2_loadbzw4_pi
5554 { 1521, 4, 2, 4, 20, 1, 0, HexagonImpOpBase + 100, 650, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1521 = L2_loadbzw4_pcr
5555 { 1520, 5, 2, 4, 36, 1, 0, HexagonImpOpBase + 100, 654, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1520 = L2_loadbzw4_pci
5556 { 1519, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 650, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1519 = L2_loadbzw4_pbr
5557 { 1518, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 501, 0|(1ULL<<MCID::MayLoad), 0x1b09b4800024ULL }, // Inst #1518 = L2_loadbzw4_io
5558 { 1517, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1517 = L2_loadbzw2_pr
5559 { 1516, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 646, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1516 = L2_loadbzw2_pi
5560 { 1515, 4, 2, 4, 20, 1, 0, HexagonImpOpBase + 100, 637, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1515 = L2_loadbzw2_pcr
5561 { 1514, 5, 2, 4, 36, 1, 0, HexagonImpOpBase + 100, 641, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1514 = L2_loadbzw2_pci
5562 { 1513, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1513 = L2_loadbzw2_pbr
5563 { 1512, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad), 0x130594808024ULL }, // Inst #1512 = L2_loadbzw2_io
5564 { 1511, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 650, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1511 = L2_loadbsw4_pr
5565 { 1510, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 659, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1510 = L2_loadbsw4_pi
5566 { 1509, 4, 2, 4, 20, 1, 0, HexagonImpOpBase + 100, 650, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1509 = L2_loadbsw4_pcr
5567 { 1508, 5, 2, 4, 36, 1, 0, HexagonImpOpBase + 100, 654, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1508 = L2_loadbsw4_pci
5568 { 1507, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 650, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1507 = L2_loadbsw4_pbr
5569 { 1506, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 501, 0|(1ULL<<MCID::MayLoad), 0x1b09b4800024ULL }, // Inst #1506 = L2_loadbsw4_io
5570 { 1505, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1505 = L2_loadbsw2_pr
5571 { 1504, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 646, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1504 = L2_loadbsw2_pi
5572 { 1503, 4, 2, 4, 20, 1, 0, HexagonImpOpBase + 100, 637, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1503 = L2_loadbsw2_pcr
5573 { 1502, 5, 2, 4, 36, 1, 0, HexagonImpOpBase + 100, 641, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1502 = L2_loadbsw2_pci
5574 { 1501, 4, 2, 4, 20, 0, 0, HexagonImpOpBase + 0, 637, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1501 = L2_loadbsw2_pbr
5575 { 1500, 3, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::MayLoad), 0x130594808024ULL }, // Inst #1500 = L2_loadbsw2_io
5576 { 1499, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 621, 0|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #1499 = L2_loadalignh_pr
5577 { 1498, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 632, 0|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #1498 = L2_loadalignh_pi
5578 { 1497, 5, 2, 4, 145, 1, 0, HexagonImpOpBase + 100, 621, 0|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #1497 = L2_loadalignh_pcr
5579 { 1496, 6, 2, 4, 146, 1, 0, HexagonImpOpBase + 100, 626, 0|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #1496 = L2_loadalignh_pci
5580 { 1495, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 621, 0|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #1495 = L2_loadalignh_pbr
5581 { 1494, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 617, 0|(1ULL<<MCID::MayLoad), 0x130596800024ULL }, // Inst #1494 = L2_loadalignh_io
5582 { 1493, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 621, 0|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #1493 = L2_loadalignb_pr
5583 { 1492, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 632, 0|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #1492 = L2_loadalignb_pi
5584 { 1491, 5, 2, 4, 145, 1, 0, HexagonImpOpBase + 100, 621, 0|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #1491 = L2_loadalignb_pcr
5585 { 1490, 6, 2, 4, 146, 1, 0, HexagonImpOpBase + 100, 626, 0|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #1490 = L2_loadalignb_pci
5586 { 1489, 5, 2, 4, 145, 0, 0, HexagonImpOpBase + 0, 621, 0|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #1489 = L2_loadalignb_pbr
5587 { 1488, 4, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 617, 0|(1ULL<<MCID::MayLoad), 0xb0176800024ULL }, // Inst #1488 = L2_loadalignb_io
5588 { 1487, 2, 1, 4, 27, 1, 1, HexagonImpOpBase + 56, 190, 0|(1ULL<<MCID::MayLoad), 0x200000000024ULL }, // Inst #1487 = L2_deallocframe
5589 { 1486, 2, 0, 4, 144, 1, 2, HexagonImpOpBase + 97, 615, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807972801404ULL }, // Inst #1486 = J4_tstbit0_tp1_jump_t
5590 { 1485, 2, 0, 4, 144, 1, 2, HexagonImpOpBase + 97, 615, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801404ULL }, // Inst #1485 = J4_tstbit0_tp1_jump_nt
5591 { 1484, 2, 0, 4, 144, 1, 2, HexagonImpOpBase + 94, 615, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807972801404ULL }, // Inst #1484 = J4_tstbit0_tp0_jump_t
5592 { 1483, 2, 0, 4, 144, 1, 2, HexagonImpOpBase + 94, 615, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801404ULL }, // Inst #1483 = J4_tstbit0_tp0_jump_nt
5593 { 1482, 2, 0, 4, 143, 0, 1, HexagonImpOpBase + 55, 155, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809972804427ULL }, // Inst #1482 = J4_tstbit0_t_jumpnv_t
5594 { 1481, 2, 0, 4, 143, 0, 1, HexagonImpOpBase + 55, 155, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9972804427ULL }, // Inst #1481 = J4_tstbit0_t_jumpnv_nt
5595 { 1480, 2, 0, 4, 144, 1, 2, HexagonImpOpBase + 97, 615, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807972801c04ULL }, // Inst #1480 = J4_tstbit0_fp1_jump_t
5596 { 1479, 2, 0, 4, 144, 1, 2, HexagonImpOpBase + 97, 615, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801c04ULL }, // Inst #1479 = J4_tstbit0_fp1_jump_nt
5597 { 1478, 2, 0, 4, 144, 1, 2, HexagonImpOpBase + 94, 615, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807972801c04ULL }, // Inst #1478 = J4_tstbit0_fp0_jump_t
5598 { 1477, 2, 0, 4, 144, 1, 2, HexagonImpOpBase + 94, 615, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801c04ULL }, // Inst #1477 = J4_tstbit0_fp0_jump_nt
5599 { 1476, 2, 0, 4, 143, 0, 1, HexagonImpOpBase + 55, 155, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809972804c27ULL }, // Inst #1476 = J4_tstbit0_f_jumpnv_t
5600 { 1475, 2, 0, 4, 143, 0, 1, HexagonImpOpBase + 55, 155, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9972804c27ULL }, // Inst #1475 = J4_tstbit0_f_jumpnv_nt
5601 { 1474, 3, 1, 4, 142, 0, 1, HexagonImpOpBase + 55, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5974808004ULL }, // Inst #1474 = J4_jumpsetr
5602 { 1473, 3, 1, 4, 142, 0, 1, HexagonImpOpBase + 55, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5974808004ULL }, // Inst #1473 = J4_jumpseti
5603 { 1472, 1, 0, 4, 141, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x7000000023ULL }, // Inst #1472 = J4_hintjumpr
5604 { 1471, 3, 0, 4, 140, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974814427ULL }, // Inst #1471 = J4_cmpltu_t_jumpnv_t
5605 { 1470, 3, 0, 4, 140, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974814427ULL }, // Inst #1470 = J4_cmpltu_t_jumpnv_nt
5606 { 1469, 3, 0, 4, 140, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974814c27ULL }, // Inst #1469 = J4_cmpltu_f_jumpnv_t
5607 { 1468, 3, 0, 4, 140, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974814c27ULL }, // Inst #1468 = J4_cmpltu_f_jumpnv_nt
5608 { 1467, 3, 0, 4, 140, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974814427ULL }, // Inst #1467 = J4_cmplt_t_jumpnv_t
5609 { 1466, 3, 0, 4, 140, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974814427ULL }, // Inst #1466 = J4_cmplt_t_jumpnv_nt
5610 { 1465, 3, 0, 4, 140, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974814c27ULL }, // Inst #1465 = J4_cmplt_f_jumpnv_t
5611 { 1464, 3, 0, 4, 140, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974814c27ULL }, // Inst #1464 = J4_cmplt_f_jumpnv_nt
5612 { 1463, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1463 = J4_cmpgtui_tp1_jump_t
5613 { 1462, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1462 = J4_cmpgtui_tp1_jump_nt
5614 { 1461, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1461 = J4_cmpgtui_tp0_jump_t
5615 { 1460, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1460 = J4_cmpgtui_tp0_jump_nt
5616 { 1459, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1459 = J4_cmpgtui_t_jumpnv_t
5617 { 1458, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1458 = J4_cmpgtui_t_jumpnv_nt
5618 { 1457, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1457 = J4_cmpgtui_fp1_jump_t
5619 { 1456, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1456 = J4_cmpgtui_fp1_jump_nt
5620 { 1455, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1455 = J4_cmpgtui_fp0_jump_t
5621 { 1454, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1454 = J4_cmpgtui_fp0_jump_nt
5622 { 1453, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1453 = J4_cmpgtui_f_jumpnv_t
5623 { 1452, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1452 = J4_cmpgtui_f_jumpnv_nt
5624 { 1451, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 97, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1451 = J4_cmpgtu_tp1_jump_t
5625 { 1450, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 97, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1450 = J4_cmpgtu_tp1_jump_nt
5626 { 1449, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 94, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1449 = J4_cmpgtu_tp0_jump_t
5627 { 1448, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 94, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1448 = J4_cmpgtu_tp0_jump_nt
5628 { 1447, 3, 0, 4, 136, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1447 = J4_cmpgtu_t_jumpnv_t
5629 { 1446, 3, 0, 4, 136, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1446 = J4_cmpgtu_t_jumpnv_nt
5630 { 1445, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 97, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1445 = J4_cmpgtu_fp1_jump_t
5631 { 1444, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 97, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1444 = J4_cmpgtu_fp1_jump_nt
5632 { 1443, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 94, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1443 = J4_cmpgtu_fp0_jump_t
5633 { 1442, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 94, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1442 = J4_cmpgtu_fp0_jump_nt
5634 { 1441, 3, 0, 4, 136, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1441 = J4_cmpgtu_f_jumpnv_t
5635 { 1440, 3, 0, 4, 136, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1440 = J4_cmpgtu_f_jumpnv_nt
5636 { 1439, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1439 = J4_cmpgtn1_tp1_jump_t
5637 { 1438, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1438 = J4_cmpgtn1_tp1_jump_nt
5638 { 1437, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1437 = J4_cmpgtn1_tp0_jump_t
5639 { 1436, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1436 = J4_cmpgtn1_tp0_jump_nt
5640 { 1435, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1435 = J4_cmpgtn1_t_jumpnv_t
5641 { 1434, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1434 = J4_cmpgtn1_t_jumpnv_nt
5642 { 1433, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1433 = J4_cmpgtn1_fp1_jump_t
5643 { 1432, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1432 = J4_cmpgtn1_fp1_jump_nt
5644 { 1431, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1431 = J4_cmpgtn1_fp0_jump_t
5645 { 1430, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1430 = J4_cmpgtn1_fp0_jump_nt
5646 { 1429, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1429 = J4_cmpgtn1_f_jumpnv_t
5647 { 1428, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1428 = J4_cmpgtn1_f_jumpnv_nt
5648 { 1427, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1427 = J4_cmpgti_tp1_jump_t
5649 { 1426, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1426 = J4_cmpgti_tp1_jump_nt
5650 { 1425, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1425 = J4_cmpgti_tp0_jump_t
5651 { 1424, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1424 = J4_cmpgti_tp0_jump_nt
5652 { 1423, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1423 = J4_cmpgti_t_jumpnv_t
5653 { 1422, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1422 = J4_cmpgti_t_jumpnv_nt
5654 { 1421, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1421 = J4_cmpgti_fp1_jump_t
5655 { 1420, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1420 = J4_cmpgti_fp1_jump_nt
5656 { 1419, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1419 = J4_cmpgti_fp0_jump_t
5657 { 1418, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1418 = J4_cmpgti_fp0_jump_nt
5658 { 1417, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1417 = J4_cmpgti_f_jumpnv_t
5659 { 1416, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1416 = J4_cmpgti_f_jumpnv_nt
5660 { 1415, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 97, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1415 = J4_cmpgt_tp1_jump_t
5661 { 1414, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 97, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1414 = J4_cmpgt_tp1_jump_nt
5662 { 1413, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 94, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1413 = J4_cmpgt_tp0_jump_t
5663 { 1412, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 94, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1412 = J4_cmpgt_tp0_jump_nt
5664 { 1411, 3, 0, 4, 136, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1411 = J4_cmpgt_t_jumpnv_t
5665 { 1410, 3, 0, 4, 136, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1410 = J4_cmpgt_t_jumpnv_nt
5666 { 1409, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 97, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1409 = J4_cmpgt_fp1_jump_t
5667 { 1408, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 97, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1408 = J4_cmpgt_fp1_jump_nt
5668 { 1407, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 94, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1407 = J4_cmpgt_fp0_jump_t
5669 { 1406, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 94, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1406 = J4_cmpgt_fp0_jump_nt
5670 { 1405, 3, 0, 4, 136, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1405 = J4_cmpgt_f_jumpnv_t
5671 { 1404, 3, 0, 4, 136, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1404 = J4_cmpgt_f_jumpnv_nt
5672 { 1403, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1403 = J4_cmpeqn1_tp1_jump_t
5673 { 1402, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1402 = J4_cmpeqn1_tp1_jump_nt
5674 { 1401, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1401 = J4_cmpeqn1_tp0_jump_t
5675 { 1400, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1400 = J4_cmpeqn1_tp0_jump_nt
5676 { 1399, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1399 = J4_cmpeqn1_t_jumpnv_t
5677 { 1398, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1398 = J4_cmpeqn1_t_jumpnv_nt
5678 { 1397, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1397 = J4_cmpeqn1_fp1_jump_t
5679 { 1396, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1396 = J4_cmpeqn1_fp1_jump_nt
5680 { 1395, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1395 = J4_cmpeqn1_fp0_jump_t
5681 { 1394, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1394 = J4_cmpeqn1_fp0_jump_nt
5682 { 1393, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1393 = J4_cmpeqn1_f_jumpnv_t
5683 { 1392, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1392 = J4_cmpeqn1_f_jumpnv_nt
5684 { 1391, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1391 = J4_cmpeqi_tp1_jump_t
5685 { 1390, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1390 = J4_cmpeqi_tp1_jump_nt
5686 { 1389, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1389 = J4_cmpeqi_tp0_jump_t
5687 { 1388, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1388 = J4_cmpeqi_tp0_jump_nt
5688 { 1387, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1387 = J4_cmpeqi_t_jumpnv_t
5689 { 1386, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1386 = J4_cmpeqi_t_jumpnv_nt
5690 { 1385, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1385 = J4_cmpeqi_fp1_jump_t
5691 { 1384, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 97, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1384 = J4_cmpeqi_fp1_jump_nt
5692 { 1383, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1383 = J4_cmpeqi_fp0_jump_t
5693 { 1382, 3, 0, 4, 139, 1, 2, HexagonImpOpBase + 94, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1382 = J4_cmpeqi_fp0_jump_nt
5694 { 1381, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1381 = J4_cmpeqi_f_jumpnv_t
5695 { 1380, 3, 0, 4, 138, 0, 1, HexagonImpOpBase + 55, 516, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1380 = J4_cmpeqi_f_jumpnv_nt
5696 { 1379, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 97, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1379 = J4_cmpeq_tp1_jump_t
5697 { 1378, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 97, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1378 = J4_cmpeq_tp1_jump_nt
5698 { 1377, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 94, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1377 = J4_cmpeq_tp0_jump_t
5699 { 1376, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 94, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1376 = J4_cmpeq_tp0_jump_nt
5700 { 1375, 3, 0, 4, 136, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1375 = J4_cmpeq_t_jumpnv_t
5701 { 1374, 3, 0, 4, 136, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1374 = J4_cmpeq_t_jumpnv_nt
5702 { 1373, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 97, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1373 = J4_cmpeq_fp1_jump_t
5703 { 1372, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 97, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1372 = J4_cmpeq_fp1_jump_nt
5704 { 1371, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 94, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1371 = J4_cmpeq_fp0_jump_t
5705 { 1370, 3, 0, 4, 137, 1, 2, HexagonImpOpBase + 94, 609, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1370 = J4_cmpeq_fp0_jump_nt
5706 { 1369, 3, 0, 4, 136, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1369 = J4_cmpeq_f_jumpnv_t
5707 { 1368, 3, 0, 4, 136, 0, 1, HexagonImpOpBase + 55, 199, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1368 = J4_cmpeq_f_jumpnv_nt
5708 { 1367, 0, 0, 4, 135, 0, 0, HexagonImpOpBase + 0, 1, 0, 0xa3ULL }, // Inst #1367 = J2_unpause
5709 { 1366, 3, 1, 4, 17, 2, 3, HexagonImpOpBase + 89, 507, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80a3ULL }, // Inst #1366 = J2_trap1
5710 { 1365, 1, 0, 4, 134, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa3ULL }, // Inst #1365 = J2_trap0
5711 { 1364, 0, 0, 4, 133, 1, 1, HexagonImpOpBase + 87, 1, 0, 0x23ULL }, // Inst #1364 = J2_rte
5712 { 1363, 2, 0, 4, 132, 0, 4, HexagonImpOpBase + 83, 607, 0, 0x6930802005ULL }, // Inst #1363 = J2_ploop3sr
5713 { 1362, 2, 0, 4, 131, 0, 4, HexagonImpOpBase + 83, 13, 0, 0x6930802005ULL }, // Inst #1362 = J2_ploop3si
5714 { 1361, 2, 0, 4, 132, 0, 4, HexagonImpOpBase + 83, 607, 0, 0x6930802005ULL }, // Inst #1361 = J2_ploop2sr
5715 { 1360, 2, 0, 4, 131, 0, 4, HexagonImpOpBase + 83, 13, 0, 0x6930802005ULL }, // Inst #1360 = J2_ploop2si
5716 { 1359, 2, 0, 4, 132, 0, 4, HexagonImpOpBase + 83, 607, 0, 0x6930802005ULL }, // Inst #1359 = J2_ploop1sr
5717 { 1358, 2, 0, 4, 131, 0, 4, HexagonImpOpBase + 83, 13, 0, 0x6930802005ULL }, // Inst #1358 = J2_ploop1si
5718 { 1357, 1, 0, 4, 130, 0, 0, HexagonImpOpBase + 0, 0, 0, 0xa3ULL }, // Inst #1357 = J2_pause
5719 { 1356, 2, 0, 4, 129, 0, 2, HexagonImpOpBase + 79, 607, 0, 0x931800005ULL }, // Inst #1356 = J2_loop1rext
5720 { 1355, 2, 0, 4, 129, 0, 2, HexagonImpOpBase + 81, 607, 0, 0x6930800005ULL }, // Inst #1355 = J2_loop1r
5721 { 1354, 2, 0, 4, 128, 0, 3, HexagonImpOpBase + 76, 13, 0, 0x931800005ULL }, // Inst #1354 = J2_loop1iext
5722 { 1353, 2, 0, 4, 128, 0, 2, HexagonImpOpBase + 81, 13, 0, 0x6930800005ULL }, // Inst #1353 = J2_loop1i
5723 { 1352, 2, 0, 4, 129, 0, 2, HexagonImpOpBase + 79, 607, 0, 0x931800005ULL }, // Inst #1352 = J2_loop0rext
5724 { 1351, 2, 0, 4, 129, 0, 3, HexagonImpOpBase + 73, 607, 0, 0x6930800005ULL }, // Inst #1351 = J2_loop0r
5725 { 1350, 2, 0, 4, 128, 0, 3, HexagonImpOpBase + 76, 13, 0, 0x931800005ULL }, // Inst #1350 = J2_loop0iext
5726 { 1349, 2, 0, 4, 128, 0, 3, HexagonImpOpBase + 73, 13, 0, 0x6930800005ULL }, // Inst #1349 = J2_loop0i
5727 { 1348, 2, 0, 4, 123, 0, 1, HexagonImpOpBase + 55, 183, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807a32800423ULL }, // Inst #1348 = J2_jumptpt
5728 { 1347, 2, 0, 4, 122, 0, 1, HexagonImpOpBase + 55, 183, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807a32801423ULL }, // Inst #1347 = J2_jumptnewpt
5729 { 1346, 2, 0, 4, 122, 0, 1, HexagonImpOpBase + 55, 183, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7a32801423ULL }, // Inst #1346 = J2_jumptnew
5730 { 1345, 2, 0, 4, 15, 0, 1, HexagonImpOpBase + 55, 183, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7a32800423ULL }, // Inst #1345 = J2_jumpt
5731 { 1344, 2, 0, 4, 126, 0, 1, HexagonImpOpBase + 55, 155, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807000001405ULL }, // Inst #1344 = J2_jumprzpt
5732 { 1343, 2, 0, 4, 126, 0, 1, HexagonImpOpBase + 55, 155, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7000001405ULL }, // Inst #1343 = J2_jumprz
5733 { 1342, 2, 0, 4, 125, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x801000000423ULL }, // Inst #1342 = J2_jumprtpt
5734 { 1341, 2, 0, 4, 124, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x801000001423ULL }, // Inst #1341 = J2_jumprtnewpt
5735 { 1340, 2, 0, 4, 124, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000001423ULL }, // Inst #1340 = J2_jumprtnew
5736 { 1339, 2, 0, 4, 16, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000423ULL }, // Inst #1339 = J2_jumprt
5737 { 1338, 2, 0, 4, 126, 0, 1, HexagonImpOpBase + 55, 155, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807000001405ULL }, // Inst #1338 = J2_jumprnzpt
5738 { 1337, 2, 0, 4, 126, 0, 1, HexagonImpOpBase + 55, 155, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7000001405ULL }, // Inst #1337 = J2_jumprnz
5739 { 1336, 2, 0, 4, 126, 0, 1, HexagonImpOpBase + 55, 155, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807000001405ULL }, // Inst #1336 = J2_jumprltezpt
5740 { 1335, 2, 0, 4, 126, 0, 1, HexagonImpOpBase + 55, 155, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7000001405ULL }, // Inst #1335 = J2_jumprltez
5741 { 1334, 1, 0, 4, 127, 0, 1, HexagonImpOpBase + 55, 272, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000023ULL }, // Inst #1334 = J2_jumprh
5742 { 1333, 2, 0, 4, 126, 0, 1, HexagonImpOpBase + 55, 155, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807000001405ULL }, // Inst #1333 = J2_jumprgtezpt
5743 { 1332, 2, 0, 4, 126, 0, 1, HexagonImpOpBase + 55, 155, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7000001405ULL }, // Inst #1332 = J2_jumprgtez
5744 { 1331, 2, 0, 4, 125, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x801000000c23ULL }, // Inst #1331 = J2_jumprfpt
5745 { 1330, 2, 0, 4, 124, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x801000001c23ULL }, // Inst #1330 = J2_jumprfnewpt
5746 { 1329, 2, 0, 4, 124, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000001c23ULL }, // Inst #1329 = J2_jumprfnew
5747 { 1328, 2, 0, 4, 16, 0, 1, HexagonImpOpBase + 55, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000c23ULL }, // Inst #1328 = J2_jumprf
5748 { 1327, 1, 0, 4, 40, 0, 1, HexagonImpOpBase + 55, 272, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x1000000023ULL }, // Inst #1327 = J2_jumpr
5749 { 1326, 2, 0, 4, 123, 0, 1, HexagonImpOpBase + 55, 183, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807a32800c23ULL }, // Inst #1326 = J2_jumpfpt
5750 { 1325, 2, 0, 4, 122, 0, 1, HexagonImpOpBase + 55, 183, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807a32801c23ULL }, // Inst #1325 = J2_jumpfnewpt
5751 { 1324, 2, 0, 4, 122, 0, 1, HexagonImpOpBase + 55, 183, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7a32801c23ULL }, // Inst #1324 = J2_jumpfnew
5752 { 1323, 2, 0, 4, 15, 0, 1, HexagonImpOpBase + 55, 183, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7a32800c23ULL }, // Inst #1323 = J2_jumpf
5753 { 1322, 1, 0, 4, 121, 0, 1, HexagonImpOpBase + 55, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x5b10800023ULL }, // Inst #1322 = J2_jump
5754 { 1321, 2, 0, 4, 117, 1, 2, HexagonImpOpBase + 68, 183, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x80007a32800423ULL }, // Inst #1321 = J2_callt
5755 { 1320, 2, 0, 4, 119, 1, 2, HexagonImpOpBase + 68, 185, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x80001000000423ULL }, // Inst #1320 = J2_callrt
5756 { 1319, 1, 0, 4, 120, 0, 2, HexagonImpOpBase + 71, 272, 0|(1ULL<<MCID::Call), 0x80001000000023ULL }, // Inst #1319 = J2_callrh
5757 { 1318, 2, 0, 4, 119, 1, 2, HexagonImpOpBase + 68, 185, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x80001000000c23ULL }, // Inst #1318 = J2_callrf
5758 { 1317, 1, 0, 4, 118, 1, 2, HexagonImpOpBase + 68, 272, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x80001000000023ULL }, // Inst #1317 = J2_callr
5759 { 1316, 2, 0, 4, 117, 1, 2, HexagonImpOpBase + 68, 183, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x80007a32800c23ULL }, // Inst #1316 = J2_callf
5760 { 1315, 1, 0, 4, 35, 1, 2, HexagonImpOpBase + 68, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80005b10800023ULL }, // Inst #1315 = J2_call
5761 { 1314, 2, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x8000ULL }, // Inst #1314 = HI
5762 { 1313, 2, 1, 4, 116, 0, 0, HexagonImpOpBase + 0, 605, 0, 0x8005ULL }, // Inst #1313 = G4_tfrgrcr
5763 { 1312, 2, 1, 4, 116, 0, 0, HexagonImpOpBase + 0, 603, 0, 0x8005ULL }, // Inst #1312 = G4_tfrgpcp
5764 { 1311, 2, 1, 4, 115, 0, 0, HexagonImpOpBase + 0, 601, 0, 0x8005ULL }, // Inst #1311 = G4_tfrgcrr
5765 { 1310, 2, 1, 4, 115, 0, 0, HexagonImpOpBase + 0, 599, 0, 0x5ULL }, // Inst #1310 = G4_tfrgcpp
5766 { 1309, 3, 1, 4, 109, 1, 0, HexagonImpOpBase + 67, 202, 0, 0x1000000008025ULL }, // Inst #1309 = F2_sfsub
5767 { 1308, 4, 2, 4, 114, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x100000000a025ULL }, // Inst #1308 = F2_sfrecipa
5768 { 1307, 3, 1, 4, 109, 1, 0, HexagonImpOpBase + 67, 202, 0|(1ULL<<MCID::Commutable), 0x1000000008025ULL }, // Inst #1307 = F2_sfmpy
5769 { 1306, 3, 1, 4, 113, 1, 0, HexagonImpOpBase + 67, 202, 0, 0x81000000008025ULL }, // Inst #1306 = F2_sfmin
5770 { 1305, 3, 1, 4, 113, 1, 0, HexagonImpOpBase + 67, 202, 0, 0x81000000008025ULL }, // Inst #1305 = F2_sfmax
5771 { 1304, 3, 2, 4, 112, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x100000000a02bULL }, // Inst #1304 = F2_sfinvsqrta
5772 { 1303, 2, 1, 4, 105, 0, 0, HexagonImpOpBase + 0, 155, 0, 0x80000000008003ULL }, // Inst #1303 = F2_sfimm_p
5773 { 1302, 2, 1, 4, 105, 0, 0, HexagonImpOpBase + 0, 155, 0, 0x80000000008003ULL }, // Inst #1302 = F2_sfimm_n
5774 { 1301, 4, 1, 4, 110, 1, 0, HexagonImpOpBase + 67, 590, 0, 0x1000000008025ULL }, // Inst #1301 = F2_sffms_lib
5775 { 1300, 4, 1, 4, 110, 1, 0, HexagonImpOpBase + 67, 590, 0, 0x1000000008025ULL }, // Inst #1300 = F2_sffms
5776 { 1299, 5, 1, 4, 111, 1, 0, HexagonImpOpBase + 67, 594, 0, 0x1000000008025ULL }, // Inst #1299 = F2_sffma_sc
5777 { 1298, 4, 1, 4, 110, 1, 0, HexagonImpOpBase + 67, 590, 0, 0x1000000008025ULL }, // Inst #1298 = F2_sffma_lib
5778 { 1297, 4, 1, 4, 110, 1, 0, HexagonImpOpBase + 67, 590, 0, 0x1000000008025ULL }, // Inst #1297 = F2_sffma
5779 { 1296, 2, 1, 4, 103, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x100000000802bULL }, // Inst #1296 = F2_sffixupr
5780 { 1295, 3, 1, 4, 109, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x1000000008025ULL }, // Inst #1295 = F2_sffixupn
5781 { 1294, 3, 1, 4, 109, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x1000000008025ULL }, // Inst #1294 = F2_sffixupd
5782 { 1293, 3, 1, 4, 9, 1, 0, HexagonImpOpBase + 67, 178, 0|(1ULL<<MCID::Compare), 0x100000000002cULL }, // Inst #1293 = F2_sfcmpuo
5783 { 1292, 3, 1, 4, 9, 1, 0, HexagonImpOpBase + 67, 178, 0|(1ULL<<MCID::Compare), 0x100000000002cULL }, // Inst #1292 = F2_sfcmpgt
5784 { 1291, 3, 1, 4, 9, 1, 0, HexagonImpOpBase + 67, 178, 0|(1ULL<<MCID::Compare), 0x100000000002cULL }, // Inst #1291 = F2_sfcmpge
5785 { 1290, 3, 1, 4, 9, 1, 0, HexagonImpOpBase + 67, 178, 0|(1ULL<<MCID::Compare), 0x100000000002cULL }, // Inst #1290 = F2_sfcmpeq
5786 { 1289, 3, 1, 4, 89, 1, 0, HexagonImpOpBase + 67, 175, 0, 0x100000000002bULL }, // Inst #1289 = F2_sfclass
5787 { 1288, 3, 1, 4, 109, 1, 0, HexagonImpOpBase + 67, 202, 0|(1ULL<<MCID::Commutable), 0x1000000008025ULL }, // Inst #1288 = F2_sfadd
5788 { 1287, 3, 1, 4, 104, 1, 0, HexagonImpOpBase + 67, 169, 0, 0x1000000000025ULL }, // Inst #1287 = F2_dfsub
5789 { 1286, 3, 1, 4, 108, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #1286 = F2_dfmpyll
5790 { 1285, 4, 1, 4, 107, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #1285 = F2_dfmpylh
5791 { 1284, 4, 1, 4, 106, 1, 0, HexagonImpOpBase + 67, 215, 0, 0x1000000000025ULL }, // Inst #1284 = F2_dfmpyhh
5792 { 1283, 3, 1, 4, 104, 1, 0, HexagonImpOpBase + 67, 169, 0, 0x1000000000025ULL }, // Inst #1283 = F2_dfmpyfix
5793 { 1282, 3, 1, 4, 96, 1, 0, HexagonImpOpBase + 67, 169, 0, 0x81000000000025ULL }, // Inst #1282 = F2_dfmin
5794 { 1281, 3, 1, 4, 96, 1, 0, HexagonImpOpBase + 67, 169, 0, 0x81000000000025ULL }, // Inst #1281 = F2_dfmax
5795 { 1280, 2, 1, 4, 105, 0, 0, HexagonImpOpBase + 0, 167, 0, 0x80000000000003ULL }, // Inst #1280 = F2_dfimm_p
5796 { 1279, 2, 1, 4, 105, 0, 0, HexagonImpOpBase + 0, 167, 0, 0x80000000000003ULL }, // Inst #1279 = F2_dfimm_n
5797 { 1278, 3, 1, 4, 9, 1, 0, HexagonImpOpBase + 67, 534, 0|(1ULL<<MCID::Compare), 0x1000000000003ULL }, // Inst #1278 = F2_dfcmpuo
5798 { 1277, 3, 1, 4, 9, 1, 0, HexagonImpOpBase + 67, 534, 0|(1ULL<<MCID::Compare), 0x1000000000003ULL }, // Inst #1277 = F2_dfcmpgt
5799 { 1276, 3, 1, 4, 9, 1, 0, HexagonImpOpBase + 67, 534, 0|(1ULL<<MCID::Compare), 0x1000000000003ULL }, // Inst #1276 = F2_dfcmpge
5800 { 1275, 3, 1, 4, 9, 1, 0, HexagonImpOpBase + 67, 534, 0|(1ULL<<MCID::Compare), 0x1000000000003ULL }, // Inst #1275 = F2_dfcmpeq
5801 { 1274, 3, 1, 4, 89, 1, 0, HexagonImpOpBase + 67, 549, 0, 0x1000000000003ULL }, // Inst #1274 = F2_dfclass
5802 { 1273, 3, 1, 4, 104, 1, 0, HexagonImpOpBase + 67, 169, 0, 0x1000000000025ULL }, // Inst #1273 = F2_dfadd
5803 { 1272, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 157, 0, 0x100000000802bULL }, // Inst #1272 = F2_conv_w2sf
5804 { 1271, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 190, 0, 0x100000000002bULL }, // Inst #1271 = F2_conv_w2df
5805 { 1270, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 157, 0, 0x100000000802bULL }, // Inst #1270 = F2_conv_uw2sf
5806 { 1269, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 190, 0, 0x100000000002bULL }, // Inst #1269 = F2_conv_uw2df
5807 { 1268, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 307, 0, 0x100000000802bULL }, // Inst #1268 = F2_conv_ud2sf
5808 { 1267, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 162, 0, 0x100000000002bULL }, // Inst #1267 = F2_conv_ud2df
5809 { 1266, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 157, 0, 0x100000000802bULL }, // Inst #1266 = F2_conv_sf2w_chop
5810 { 1265, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 157, 0, 0x100000000802bULL }, // Inst #1265 = F2_conv_sf2w
5811 { 1264, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 157, 0, 0x100000000802bULL }, // Inst #1264 = F2_conv_sf2uw_chop
5812 { 1263, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 157, 0, 0x100000000802bULL }, // Inst #1263 = F2_conv_sf2uw
5813 { 1262, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 190, 0, 0x100000000002bULL }, // Inst #1262 = F2_conv_sf2ud_chop
5814 { 1261, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 190, 0, 0x100000000002bULL }, // Inst #1261 = F2_conv_sf2ud
5815 { 1260, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 190, 0, 0x100000000002bULL }, // Inst #1260 = F2_conv_sf2df
5816 { 1259, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 190, 0, 0x100000000002bULL }, // Inst #1259 = F2_conv_sf2d_chop
5817 { 1258, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 190, 0, 0x100000000002bULL }, // Inst #1258 = F2_conv_sf2d
5818 { 1257, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 307, 0, 0x100000000802bULL }, // Inst #1257 = F2_conv_df2w_chop
5819 { 1256, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 307, 0, 0x100000000802bULL }, // Inst #1256 = F2_conv_df2w
5820 { 1255, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 307, 0, 0x100000000802bULL }, // Inst #1255 = F2_conv_df2uw_chop
5821 { 1254, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 307, 0, 0x100000000802bULL }, // Inst #1254 = F2_conv_df2uw
5822 { 1253, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 162, 0, 0x100000000002bULL }, // Inst #1253 = F2_conv_df2ud_chop
5823 { 1252, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 162, 0, 0x100000000002bULL }, // Inst #1252 = F2_conv_df2ud
5824 { 1251, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 307, 0, 0x100000000802bULL }, // Inst #1251 = F2_conv_df2sf
5825 { 1250, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 162, 0, 0x100000000002bULL }, // Inst #1250 = F2_conv_df2d_chop
5826 { 1249, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 162, 0, 0x100000000002bULL }, // Inst #1249 = F2_conv_df2d
5827 { 1248, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 307, 0, 0x100000000802bULL }, // Inst #1248 = F2_conv_d2sf
5828 { 1247, 2, 1, 4, 103, 1, 0, HexagonImpOpBase + 67, 162, 0, 0x100000000002bULL }, // Inst #1247 = F2_conv_d2df
5829 { 1246, 1, 0, 4, 40, 1, 1, HexagonImpOpBase + 65, 272, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000023ULL }, // Inst #1246 = EH_RETURN_JMPR
5830 { 1245, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20ULL }, // Inst #1245 = DuplexIClassF
5831 { 1244, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20ULL }, // Inst #1244 = DuplexIClassE
5832 { 1243, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20ULL }, // Inst #1243 = DuplexIClassD
5833 { 1242, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20ULL }, // Inst #1242 = DuplexIClassC
5834 { 1241, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20ULL }, // Inst #1241 = DuplexIClassB
5835 { 1240, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20ULL }, // Inst #1240 = DuplexIClassA
5836 { 1239, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20ULL }, // Inst #1239 = DuplexIClass9
5837 { 1238, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20ULL }, // Inst #1238 = DuplexIClass8
5838 { 1237, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20020ULL }, // Inst #1237 = DuplexIClass7
5839 { 1236, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20020ULL }, // Inst #1236 = DuplexIClass6
5840 { 1235, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20020ULL }, // Inst #1235 = DuplexIClass5
5841 { 1234, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20020ULL }, // Inst #1234 = DuplexIClass4
5842 { 1233, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20020ULL }, // Inst #1233 = DuplexIClass3
5843 { 1232, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20ULL }, // Inst #1232 = DuplexIClass2
5844 { 1231, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20ULL }, // Inst #1231 = DuplexIClass1
5845 { 1230, 0, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x20ULL }, // Inst #1230 = DuplexIClass0
5846 { 1229, 2, 1, 4, 29, 0, 0, HexagonImpOpBase + 0, 588, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x24ULL }, // Inst #1229 = CONST64
5847 { 1228, 2, 1, 4, 29, 0, 0, HexagonImpOpBase + 0, 586, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x24ULL }, // Inst #1228 = CONST32
5848 { 1227, 1, 0, 4, 35, 0, 1, HexagonImpOpBase + 64, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #1227 = CALLProfile
5849 { 1226, 4, 1, 4, 102, 0, 0, HexagonImpOpBase + 0, 582, 0, 0x5ULL }, // Inst #1226 = C4_or_orn
5850 { 1225, 4, 1, 4, 102, 0, 0, HexagonImpOpBase + 0, 582, 0, 0x5ULL }, // Inst #1225 = C4_or_or
5851 { 1224, 4, 1, 4, 102, 0, 0, HexagonImpOpBase + 0, 582, 0, 0x5ULL }, // Inst #1224 = C4_or_andn
5852 { 1223, 4, 1, 4, 102, 0, 0, HexagonImpOpBase + 0, 582, 0, 0x5ULL }, // Inst #1223 = C4_or_and
5853 { 1222, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 178, 0, 0x2cULL }, // Inst #1222 = C4_nbitsset
5854 { 1221, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 175, 0, 0x2bULL }, // Inst #1221 = C4_nbitsclri
5855 { 1220, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 178, 0, 0x2cULL }, // Inst #1220 = C4_nbitsclr
5856 { 1219, 3, 1, 4, 11, 0, 0, HexagonImpOpBase + 0, 560, 0, 0x5ULL }, // Inst #1219 = C4_fastcorner9_not
5857 { 1218, 3, 1, 4, 11, 0, 0, HexagonImpOpBase + 0, 560, 0, 0x5ULL }, // Inst #1218 = C4_fastcorner9
5858 { 1217, 3, 1, 4, 10, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Compare), 0x154800000ULL }, // Inst #1217 = C4_cmpneqi
5859 { 1216, 3, 1, 4, 98, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #1216 = C4_cmpneq
5860 { 1215, 3, 1, 4, 10, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Compare), 0x124800000ULL }, // Inst #1215 = C4_cmplteui
5861 { 1214, 3, 1, 4, 98, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Compare), 0x1ULL }, // Inst #1214 = C4_cmplteu
5862 { 1213, 3, 1, 4, 10, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Compare), 0x154800000ULL }, // Inst #1213 = C4_cmpltei
5863 { 1212, 3, 1, 4, 98, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Compare), 0x1ULL }, // Inst #1212 = C4_cmplte
5864 { 1211, 4, 1, 4, 102, 0, 0, HexagonImpOpBase + 0, 582, 0, 0x5ULL }, // Inst #1211 = C4_and_orn
5865 { 1210, 4, 1, 4, 102, 0, 0, HexagonImpOpBase + 0, 582, 0, 0x5ULL }, // Inst #1210 = C4_and_or
5866 { 1209, 4, 1, 4, 102, 0, 0, HexagonImpOpBase + 0, 582, 0, 0x5ULL }, // Inst #1209 = C4_and_andn
5867 { 1208, 4, 1, 4, 102, 0, 0, HexagonImpOpBase + 0, 582, 0, 0x5ULL }, // Inst #1208 = C4_and_and
5868 { 1207, 2, 1, 4, 101, 0, 0, HexagonImpOpBase + 0, 155, 0, 0xc2808005ULL }, // Inst #1207 = C4_addipc
5869 { 1206, 3, 1, 4, 11, 0, 0, HexagonImpOpBase + 0, 560, 0, 0x5ULL }, // Inst #1206 = C2_xor
5870 { 1205, 4, 1, 4, 100, 0, 0, HexagonImpOpBase + 0, 245, 0, 0x3ULL }, // Inst #1205 = C2_vmux
5871 { 1204, 3, 1, 4, 78, 0, 0, HexagonImpOpBase + 0, 579, 0, 0x8000000000802bULL }, // Inst #1204 = C2_vitpack
5872 { 1203, 2, 1, 4, 99, 0, 0, HexagonImpOpBase + 0, 185, 0, 0x2bULL }, // Inst #1203 = C2_tfrrp
5873 { 1202, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 577, 0, 0x802bULL }, // Inst #1202 = C2_tfrpr
5874 { 1201, 3, 1, 4, 11, 0, 0, HexagonImpOpBase + 0, 560, 0, 0x5ULL }, // Inst #1201 = C2_orn
5875 { 1200, 3, 1, 4, 11, 0, 0, HexagonImpOpBase + 0, 560, 0, 0x5ULL }, // Inst #1200 = C2_or
5876 { 1199, 2, 1, 4, 97, 0, 0, HexagonImpOpBase + 0, 181, 0, 0x5ULL }, // Inst #1199 = C2_not
5877 { 1198, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 573, 0, 0x114808000ULL }, // Inst #1198 = C2_muxri
5878 { 1197, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 526, 0, 0x116808000ULL }, // Inst #1197 = C2_muxir
5879 { 1196, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 569, 0, 0x114808000ULL }, // Inst #1196 = C2_muxii
5880 { 1195, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x8001ULL }, // Inst #1195 = C2_mux
5881 { 1194, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 567, 0, 0x2bULL }, // Inst #1194 = C2_mask
5882 { 1193, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0|(1ULL<<MCID::Compare), 0x3ULL }, // Inst #1193 = C2_cmpgtup
5883 { 1192, 3, 1, 4, 10, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Compare), 0x124800000ULL }, // Inst #1192 = C2_cmpgtui
5884 { 1191, 3, 1, 4, 98, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Compare), 0x1ULL }, // Inst #1191 = C2_cmpgtu
5885 { 1190, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0|(1ULL<<MCID::Compare), 0x3ULL }, // Inst #1190 = C2_cmpgtp
5886 { 1189, 3, 1, 4, 10, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Compare), 0x154800000ULL }, // Inst #1189 = C2_cmpgti
5887 { 1188, 3, 1, 4, 98, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Compare), 0x1ULL }, // Inst #1188 = C2_cmpgt
5888 { 1187, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x3ULL }, // Inst #1187 = C2_cmpeqp
5889 { 1186, 3, 1, 4, 10, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Compare), 0x154800000ULL }, // Inst #1186 = C2_cmpeqi
5890 { 1185, 3, 1, 4, 98, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #1185 = C2_cmpeq
5891 { 1184, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MoveImm), 0x194809400ULL }, // Inst #1184 = C2_cmovenewit
5892 { 1183, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MoveImm), 0x194809c00ULL }, // Inst #1183 = C2_cmovenewif
5893 { 1182, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MoveImm), 0x194808400ULL }, // Inst #1182 = C2_cmoveit
5894 { 1181, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::MoveImm), 0x194808c00ULL }, // Inst #1181 = C2_cmoveif
5895 { 1180, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 563, 0, 0x401ULL }, // Inst #1180 = C2_ccombinewt
5896 { 1179, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 563, 0, 0x1401ULL }, // Inst #1179 = C2_ccombinewnewt
5897 { 1178, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 563, 0, 0x1c01ULL }, // Inst #1178 = C2_ccombinewnewf
5898 { 1177, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 563, 0, 0xc01ULL }, // Inst #1177 = C2_ccombinewf
5899 { 1176, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 178, 0, 0x2cULL }, // Inst #1176 = C2_bitsset
5900 { 1175, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 175, 0, 0x2bULL }, // Inst #1175 = C2_bitsclri
5901 { 1174, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 178, 0, 0x2cULL }, // Inst #1174 = C2_bitsclr
5902 { 1173, 2, 1, 4, 97, 0, 0, HexagonImpOpBase + 0, 181, 0, 0x5ULL }, // Inst #1173 = C2_any8
5903 { 1172, 3, 1, 4, 11, 0, 0, HexagonImpOpBase + 0, 560, 0, 0x5ULL }, // Inst #1172 = C2_andn
5904 { 1171, 3, 1, 4, 11, 0, 0, HexagonImpOpBase + 0, 560, 0, 0x5ULL }, // Inst #1171 = C2_and
5905 { 1170, 2, 1, 4, 97, 0, 0, HexagonImpOpBase + 0, 181, 0, 0x5ULL }, // Inst #1170 = C2_all8
5906 { 1169, 3, 1, 4, 94, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x2bULL }, // Inst #1169 = A7_vclip
5907 { 1168, 3, 1, 4, 96, 0, 0, HexagonImpOpBase + 0, 209, 0, 0x8000000000002cULL }, // Inst #1168 = A7_croundd_rr
5908 { 1167, 3, 1, 4, 96, 0, 0, HexagonImpOpBase + 0, 304, 0, 0x8000000000002bULL }, // Inst #1167 = A7_croundd_ri
5909 { 1166, 3, 1, 4, 94, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x802bULL }, // Inst #1166 = A7_clip
5910 { 1165, 4, 2, 4, 95, 0, 0, HexagonImpOpBase + 0, 245, 0, 0x80000000002025ULL }, // Inst #1165 = A6_vminub_RdP
5911 { 1164, 3, 1, 4, 94, 0, 0, HexagonImpOpBase + 0, 534, 0, 0x3ULL }, // Inst #1164 = A6_vcmpbeq_notany
5912 { 1163, 3, 1, 4, 48, 0, 1, HexagonImpOpBase + 63, 557, 0, 0x8000000000802cULL }, // Inst #1163 = A5_vaddhubs
5913 { 1162, 5, 2, 4, 93, 0, 1, HexagonImpOpBase + 63, 552, 0, 0x80000000002025ULL }, // Inst #1162 = A5_ACS
5914 { 1161, 4, 1, 4, 92, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #1161 = A4_vrminw
5915 { 1160, 4, 1, 4, 92, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #1160 = A4_vrminuw
5916 { 1159, 4, 1, 4, 92, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #1159 = A4_vrminuh
5917 { 1158, 4, 1, 4, 92, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #1158 = A4_vrminh
5918 { 1157, 4, 1, 4, 92, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #1157 = A4_vrmaxw
5919 { 1156, 4, 1, 4, 92, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #1156 = A4_vrmaxuw
5920 { 1155, 4, 1, 4, 92, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #1155 = A4_vrmaxuh
5921 { 1154, 4, 1, 4, 92, 0, 0, HexagonImpOpBase + 0, 205, 0, 0x8000000000002cULL }, // Inst #1154 = A4_vrmaxh
5922 { 1153, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 549, 0, 0x3ULL }, // Inst #1153 = A4_vcmpwgtui
5923 { 1152, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 549, 0, 0x3ULL }, // Inst #1152 = A4_vcmpwgti
5924 { 1151, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 549, 0, 0x3ULL }, // Inst #1151 = A4_vcmpweqi
5925 { 1150, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 549, 0, 0x3ULL }, // Inst #1150 = A4_vcmphgtui
5926 { 1149, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 549, 0, 0x3ULL }, // Inst #1149 = A4_vcmphgti
5927 { 1148, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 549, 0, 0x3ULL }, // Inst #1148 = A4_vcmpheqi
5928 { 1147, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 549, 0, 0x3ULL }, // Inst #1147 = A4_vcmpbgtui
5929 { 1146, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 549, 0, 0x3ULL }, // Inst #1146 = A4_vcmpbgti
5930 { 1145, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0, 0x3ULL }, // Inst #1145 = A4_vcmpbgt
5931 { 1144, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 549, 0, 0x3ULL }, // Inst #1144 = A4_vcmpbeqi
5932 { 1143, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0, 0x3ULL }, // Inst #1143 = A4_vcmpbeq_any
5933 { 1142, 3, 1, 4, 91, 0, 0, HexagonImpOpBase + 0, 546, 0, 0x2003ULL }, // Inst #1142 = A4_tlbmatch
5934 { 1141, 2, 1, 4, 85, 0, 0, HexagonImpOpBase + 0, 544, 0, 0x5ULL }, // Inst #1141 = A4_tfrpcp
5935 { 1140, 2, 1, 4, 84, 0, 0, HexagonImpOpBase + 0, 542, 0, 0x5ULL }, // Inst #1140 = A4_tfrcpp
5936 { 1139, 5, 2, 4, 88, 0, 0, HexagonImpOpBase + 0, 537, 0, 0x202cULL }, // Inst #1139 = A4_subp_c
5937 { 1138, 3, 1, 4, 48, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x8000000000802cULL }, // Inst #1138 = A4_round_rr_sat
5938 { 1137, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x8000000000802cULL }, // Inst #1137 = A4_round_rr
5939 { 1136, 3, 1, 4, 48, 0, 1, HexagonImpOpBase + 63, 199, 0, 0x8000000000802bULL }, // Inst #1136 = A4_round_ri_sat
5940 { 1135, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x8000000000802bULL }, // Inst #1135 = A4_round_ri
5941 { 1134, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x114808000ULL }, // Inst #1134 = A4_rcmpneqi
5942 { 1133, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #1133 = A4_rcmpneq
5943 { 1132, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x114808000ULL }, // Inst #1132 = A4_rcmpeqi
5944 { 1131, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #1131 = A4_rcmpeq
5945 { 1130, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x9400ULL }, // Inst #1130 = A4_pzxthtnew
5946 { 1129, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x8400ULL }, // Inst #1129 = A4_pzxtht
5947 { 1128, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x9c00ULL }, // Inst #1128 = A4_pzxthfnew
5948 { 1127, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x8c00ULL }, // Inst #1127 = A4_pzxthf
5949 { 1126, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x9400ULL }, // Inst #1126 = A4_pzxtbtnew
5950 { 1125, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x8400ULL }, // Inst #1125 = A4_pzxtbt
5951 { 1124, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x9c00ULL }, // Inst #1124 = A4_pzxtbfnew
5952 { 1123, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x8c00ULL }, // Inst #1123 = A4_pzxtbf
5953 { 1122, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x9400ULL }, // Inst #1122 = A4_psxthtnew
5954 { 1121, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x8400ULL }, // Inst #1121 = A4_psxtht
5955 { 1120, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x9c00ULL }, // Inst #1120 = A4_psxthfnew
5956 { 1119, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x8c00ULL }, // Inst #1119 = A4_psxthf
5957 { 1118, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x9400ULL }, // Inst #1118 = A4_psxtbtnew
5958 { 1117, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x8400ULL }, // Inst #1117 = A4_psxtbt
5959 { 1116, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x9c00ULL }, // Inst #1116 = A4_psxtbfnew
5960 { 1115, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x8c00ULL }, // Inst #1115 = A4_psxtbf
5961 { 1114, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x9400ULL }, // Inst #1114 = A4_pasrhtnew
5962 { 1113, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x8400ULL }, // Inst #1113 = A4_pasrht
5963 { 1112, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x9c00ULL }, // Inst #1112 = A4_pasrhfnew
5964 { 1111, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x8c00ULL }, // Inst #1111 = A4_pasrhf
5965 { 1110, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x9400ULL }, // Inst #1110 = A4_paslhtnew
5966 { 1109, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x8400ULL }, // Inst #1109 = A4_paslht
5967 { 1108, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x9c00ULL }, // Inst #1108 = A4_paslhfnew
5968 { 1107, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 159, 0, 0x8c00ULL }, // Inst #1107 = A4_paslhf
5969 { 1106, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x3ULL }, // Inst #1106 = A4_ornp
5970 { 1105, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x8001ULL }, // Inst #1105 = A4_orn
5971 { 1104, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #1104 = A4_modwrapu
5972 { 1103, 1, 0, 4, 90, 0, 0, HexagonImpOpBase + 0, 0, 0, 0x22ULL }, // Inst #1103 = A4_ext
5973 { 1102, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x8000000000802cULL }, // Inst #1102 = A4_cround_rr
5974 { 1101, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x8000000000802bULL }, // Inst #1101 = A4_cround_ri
5975 { 1100, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 501, 0, 0x114800000ULL }, // Inst #1100 = A4_combineri
5976 { 1099, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 498, 0, 0x112800000ULL }, // Inst #1099 = A4_combineir
5977 { 1098, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 495, 0, 0xc4800000ULL }, // Inst #1098 = A4_combineii
5978 { 1097, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Compare), 0xe4800003ULL }, // Inst #1097 = A4_cmphgtui
5979 { 1096, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Compare), 0x2cULL }, // Inst #1096 = A4_cmphgtu
5980 { 1095, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Compare), 0x114800003ULL }, // Inst #1095 = A4_cmphgti
5981 { 1094, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Compare), 0x2cULL }, // Inst #1094 = A4_cmphgt
5982 { 1093, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x114800003ULL }, // Inst #1093 = A4_cmpheqi
5983 { 1092, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x2cULL }, // Inst #1092 = A4_cmpheq
5984 { 1091, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Compare), 0xe4800003ULL }, // Inst #1091 = A4_cmpbgtui
5985 { 1090, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Compare), 0x2cULL }, // Inst #1090 = A4_cmpbgtu
5986 { 1089, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Compare), 0x3ULL }, // Inst #1089 = A4_cmpbgti
5987 { 1088, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Compare), 0x2cULL }, // Inst #1088 = A4_cmpbgt
5988 { 1087, 3, 1, 4, 89, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x3ULL }, // Inst #1087 = A4_cmpbeqi
5989 { 1086, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x2cULL }, // Inst #1086 = A4_cmpbeq
5990 { 1085, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0, 0x3ULL }, // Inst #1085 = A4_boundscheck_lo
5991 { 1084, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0, 0x3ULL }, // Inst #1084 = A4_boundscheck_hi
5992 { 1083, 3, 1, 4, 78, 0, 0, HexagonImpOpBase + 0, 501, 0, 0x8000000000002bULL }, // Inst #1083 = A4_bitspliti
5993 { 1082, 3, 1, 4, 78, 0, 0, HexagonImpOpBase + 0, 519, 0, 0x80000000000003ULL }, // Inst #1082 = A4_bitsplit
5994 { 1081, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x3ULL }, // Inst #1081 = A4_andnp
5995 { 1080, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x8001ULL }, // Inst #1080 = A4_andn
5996 { 1079, 5, 2, 4, 88, 0, 0, HexagonImpOpBase + 0, 537, 0, 0x202cULL }, // Inst #1079 = A4_addp_c
5997 { 1078, 2, 1, 4, 3, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #1078 = A2_zxth
5998 { 1077, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0|(1ULL<<MCID::Commutable), 0x3ULL }, // Inst #1077 = A2_xorp
5999 { 1076, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #1076 = A2_xor
6000 { 1075, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000003ULL }, // Inst #1075 = A2_vsubws
6001 { 1074, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x3ULL }, // Inst #1074 = A2_vsubw
6002 { 1073, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000003ULL }, // Inst #1073 = A2_vsubuhs
6003 { 1072, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000003ULL }, // Inst #1072 = A2_vsububs
6004 { 1071, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x3ULL }, // Inst #1071 = A2_vsubub
6005 { 1070, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000003ULL }, // Inst #1070 = A2_vsubhs
6006 { 1069, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x3ULL }, // Inst #1069 = A2_vsubh
6007 { 1068, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #1068 = A2_vrsadub_acc
6008 { 1067, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #1067 = A2_vrsadub
6009 { 1066, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 215, 0, 0x80000000000025ULL }, // Inst #1066 = A2_vraddub_acc
6010 { 1065, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000025ULL }, // Inst #1065 = A2_vraddub
6011 { 1064, 3, 1, 4, 48, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000003ULL }, // Inst #1064 = A2_vnavgwr
6012 { 1063, 3, 1, 4, 48, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000003ULL }, // Inst #1063 = A2_vnavgwcr
6013 { 1062, 3, 1, 4, 86, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1062 = A2_vnavgw
6014 { 1061, 3, 1, 4, 48, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000003ULL }, // Inst #1061 = A2_vnavghr
6015 { 1060, 3, 1, 4, 48, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000003ULL }, // Inst #1060 = A2_vnavghcr
6016 { 1059, 3, 1, 4, 86, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1059 = A2_vnavgh
6017 { 1058, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1058 = A2_vminw
6018 { 1057, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1057 = A2_vminuw
6019 { 1056, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1056 = A2_vminuh
6020 { 1055, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1055 = A2_vminub
6021 { 1054, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1054 = A2_vminh
6022 { 1053, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1053 = A2_vminb
6023 { 1052, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1052 = A2_vmaxw
6024 { 1051, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1051 = A2_vmaxuw
6025 { 1050, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1050 = A2_vmaxuh
6026 { 1049, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1049 = A2_vmaxub
6027 { 1048, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1048 = A2_vmaxh
6028 { 1047, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1047 = A2_vmaxb
6029 { 1046, 2, 1, 4, 76, 0, 1, HexagonImpOpBase + 63, 162, 0, 0x8000000000002bULL }, // Inst #1046 = A2_vconj
6030 { 1045, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0, 0x3ULL }, // Inst #1045 = A2_vcmpwgtu
6031 { 1044, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0, 0x3ULL }, // Inst #1044 = A2_vcmpwgt
6032 { 1043, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0, 0x3ULL }, // Inst #1043 = A2_vcmpweq
6033 { 1042, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0, 0x3ULL }, // Inst #1042 = A2_vcmphgtu
6034 { 1041, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0, 0x3ULL }, // Inst #1041 = A2_vcmphgt
6035 { 1040, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0, 0x3ULL }, // Inst #1040 = A2_vcmpheq
6036 { 1039, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0, 0x3ULL }, // Inst #1039 = A2_vcmpbgtu
6037 { 1038, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 534, 0, 0x3ULL }, // Inst #1038 = A2_vcmpbeq
6038 { 1037, 3, 1, 4, 87, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1037 = A2_vavgwr
6039 { 1036, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1036 = A2_vavgwcr
6040 { 1035, 3, 1, 4, 86, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1035 = A2_vavgw
6041 { 1034, 3, 1, 4, 87, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1034 = A2_vavguwr
6042 { 1033, 3, 1, 4, 86, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1033 = A2_vavguw
6043 { 1032, 3, 1, 4, 87, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1032 = A2_vavguhr
6044 { 1031, 3, 1, 4, 86, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1031 = A2_vavguh
6045 { 1030, 3, 1, 4, 87, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1030 = A2_vavgubr
6046 { 1029, 3, 1, 4, 86, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1029 = A2_vavgub
6047 { 1028, 3, 1, 4, 87, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1028 = A2_vavghr
6048 { 1027, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1027 = A2_vavghcr
6049 { 1026, 3, 1, 4, 86, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #1026 = A2_vavgh
6050 { 1025, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000003ULL }, // Inst #1025 = A2_vaddws
6051 { 1024, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x3ULL }, // Inst #1024 = A2_vaddw
6052 { 1023, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000003ULL }, // Inst #1023 = A2_vadduhs
6053 { 1022, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000003ULL }, // Inst #1022 = A2_vaddubs
6054 { 1021, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x3ULL }, // Inst #1021 = A2_vaddub
6055 { 1020, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 169, 0, 0x80000000000003ULL }, // Inst #1020 = A2_vaddhs
6056 { 1019, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x3ULL }, // Inst #1019 = A2_vaddh
6057 { 1018, 2, 1, 4, 76, 0, 1, HexagonImpOpBase + 63, 162, 0, 0x8000000000002bULL }, // Inst #1018 = A2_vabswsat
6058 { 1017, 2, 1, 4, 76, 0, 0, HexagonImpOpBase + 0, 162, 0, 0x8000000000002bULL }, // Inst #1017 = A2_vabsw
6059 { 1016, 2, 1, 4, 76, 0, 1, HexagonImpOpBase + 63, 162, 0, 0x8000000000002bULL }, // Inst #1016 = A2_vabshsat
6060 { 1015, 2, 1, 4, 76, 0, 0, HexagonImpOpBase + 0, 162, 0, 0x8000000000002bULL }, // Inst #1015 = A2_vabsh
6061 { 1014, 2, 1, 4, 3, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x212808000ULL }, // Inst #1014 = A2_tfrsi
6062 { 1013, 2, 1, 4, 85, 0, 0, HexagonImpOpBase + 0, 532, 0, 0x8005ULL }, // Inst #1013 = A2_tfrrcr
6063 { 1012, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 507, 0, 0x8000ULL }, // Inst #1012 = A2_tfril
6064 { 1011, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 507, 0, 0x8000ULL }, // Inst #1011 = A2_tfrih
6065 { 1010, 2, 1, 4, 84, 0, 0, HexagonImpOpBase + 0, 530, 0, 0x8005ULL }, // Inst #1010 = A2_tfrcrr
6066 { 1009, 2, 1, 4, 3, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #1009 = A2_tfr
6067 { 1008, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 190, 0, 0x2bULL }, // Inst #1008 = A2_sxtw
6068 { 1007, 2, 1, 4, 3, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #1007 = A2_sxth
6069 { 1006, 2, 1, 4, 3, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #1006 = A2_sxtb
6070 { 1005, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x802bULL }, // Inst #1005 = A2_swiz
6071 { 1004, 3, 1, 4, 79, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008001ULL }, // Inst #1004 = A2_svsubuhs
6072 { 1003, 3, 1, 4, 79, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008001ULL }, // Inst #1003 = A2_svsubhs
6073 { 1002, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x8001ULL }, // Inst #1002 = A2_svsubh
6074 { 1001, 3, 1, 4, 82, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008001ULL }, // Inst #1001 = A2_svnavgh
6075 { 1000, 3, 1, 4, 83, 0, 0, HexagonImpOpBase + 0, 202, 0|(1ULL<<MCID::Commutable), 0x80000000008001ULL }, // Inst #1000 = A2_svavghs
6076 { 999, 3, 1, 4, 82, 0, 0, HexagonImpOpBase + 0, 202, 0|(1ULL<<MCID::Commutable), 0x80000000008001ULL }, // Inst #999 = A2_svavgh
6077 { 998, 3, 1, 4, 79, 0, 1, HexagonImpOpBase + 63, 202, 0|(1ULL<<MCID::Commutable), 0x80000000008001ULL }, // Inst #998 = A2_svadduhs
6078 { 997, 3, 1, 4, 79, 0, 1, HexagonImpOpBase + 63, 202, 0|(1ULL<<MCID::Commutable), 0x80000000008001ULL }, // Inst #997 = A2_svaddhs
6079 { 996, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #996 = A2_svaddh
6080 { 995, 3, 1, 4, 79, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008001ULL }, // Inst #995 = A2_subsat
6081 { 994, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 510, 0, 0x152808000ULL }, // Inst #994 = A2_subri
6082 { 993, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x3ULL }, // Inst #993 = A2_subp
6083 { 992, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #992 = A2_subh_l16_sat_ll
6084 { 991, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #991 = A2_subh_l16_sat_hl
6085 { 990, 3, 1, 4, 78, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #990 = A2_subh_l16_ll
6086 { 989, 3, 1, 4, 78, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #989 = A2_subh_l16_hl
6087 { 988, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #988 = A2_subh_h16_sat_ll
6088 { 987, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #987 = A2_subh_h16_sat_lh
6089 { 986, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #986 = A2_subh_h16_sat_hl
6090 { 985, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #985 = A2_subh_h16_sat_hh
6091 { 984, 3, 1, 4, 1, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #984 = A2_subh_h16_ll
6092 { 983, 3, 1, 4, 1, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #983 = A2_subh_h16_lh
6093 { 982, 3, 1, 4, 1, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #982 = A2_subh_h16_hl
6094 { 981, 3, 1, 4, 1, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #981 = A2_subh_h16_hh
6095 { 980, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0|(1ULL<<MCID::Predicable), 0x8001ULL }, // Inst #980 = A2_sub
6096 { 979, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 157, 0, 0x802bULL }, // Inst #979 = A2_satuh
6097 { 978, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 157, 0, 0x802bULL }, // Inst #978 = A2_satub
6098 { 977, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 157, 0, 0x802bULL }, // Inst #977 = A2_sath
6099 { 976, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 157, 0, 0x802bULL }, // Inst #976 = A2_satb
6100 { 975, 2, 1, 4, 80, 0, 1, HexagonImpOpBase + 63, 307, 0, 0x802bULL }, // Inst #975 = A2_sat
6101 { 974, 2, 1, 4, 76, 0, 1, HexagonImpOpBase + 63, 307, 0, 0x8000000000802bULL }, // Inst #974 = A2_roundsat
6102 { 973, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x9401ULL }, // Inst #973 = A2_pxortnew
6103 { 972, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x8401ULL }, // Inst #972 = A2_pxort
6104 { 971, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x9c01ULL }, // Inst #971 = A2_pxorfnew
6105 { 970, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x8c01ULL }, // Inst #970 = A2_pxorf
6106 { 969, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x9401ULL }, // Inst #969 = A2_psubtnew
6107 { 968, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x8401ULL }, // Inst #968 = A2_psubt
6108 { 967, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x9c01ULL }, // Inst #967 = A2_psubfnew
6109 { 966, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x8c01ULL }, // Inst #966 = A2_psubf
6110 { 965, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x9401ULL }, // Inst #965 = A2_portnew
6111 { 964, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x8401ULL }, // Inst #964 = A2_port
6112 { 963, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x9c01ULL }, // Inst #963 = A2_porfnew
6113 { 962, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x8c01ULL }, // Inst #962 = A2_porf
6114 { 961, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x9401ULL }, // Inst #961 = A2_pandtnew
6115 { 960, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x8401ULL }, // Inst #960 = A2_pandt
6116 { 959, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x9c01ULL }, // Inst #959 = A2_pandfnew
6117 { 958, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x8c01ULL }, // Inst #958 = A2_pandf
6118 { 957, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x9401ULL }, // Inst #957 = A2_paddtnew
6119 { 956, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x8401ULL }, // Inst #956 = A2_paddt
6120 { 955, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 526, 0, 0x116809400ULL }, // Inst #955 = A2_padditnew
6121 { 954, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 526, 0, 0x116808400ULL }, // Inst #954 = A2_paddit
6122 { 953, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 526, 0, 0x116809c00ULL }, // Inst #953 = A2_paddifnew
6123 { 952, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 526, 0, 0x116808c00ULL }, // Inst #952 = A2_paddif
6124 { 951, 4, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x9c01ULL }, // Inst #951 = A2_paddfnew
6125 { 950, 4, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 522, 0, 0x8c01ULL }, // Inst #950 = A2_paddf
6126 { 949, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0|(1ULL<<MCID::Commutable), 0x3ULL }, // Inst #949 = A2_orp
6127 { 948, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x154808000ULL }, // Inst #948 = A2_orir
6128 { 947, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #947 = A2_or
6129 { 946, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 162, 0, 0x2bULL }, // Inst #946 = A2_notp
6130 { 945, 0, 0, 4, 81, 0, 0, HexagonImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #945 = A2_nop
6131 { 944, 2, 1, 4, 76, 0, 1, HexagonImpOpBase + 63, 157, 0, 0x8000000000802bULL }, // Inst #944 = A2_negsat
6132 { 943, 2, 1, 4, 80, 0, 0, HexagonImpOpBase + 0, 162, 0, 0x2bULL }, // Inst #943 = A2_negp
6133 { 942, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #942 = A2_minup
6134 { 941, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #941 = A2_minu
6135 { 940, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #940 = A2_minp
6136 { 939, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #939 = A2_min
6137 { 938, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #938 = A2_maxup
6138 { 937, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #937 = A2_maxu
6139 { 936, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #936 = A2_maxp
6140 { 935, 3, 1, 4, 77, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #935 = A2_max
6141 { 934, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 519, 0|(1ULL<<MCID::Predicable), 0x1ULL }, // Inst #934 = A2_combinew
6142 { 933, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 495, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x112800000ULL }, // Inst #933 = A2_combineii
6143 { 932, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x8001ULL }, // Inst #932 = A2_combine_ll
6144 { 931, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x8001ULL }, // Inst #931 = A2_combine_lh
6145 { 930, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x8001ULL }, // Inst #930 = A2_combine_hl
6146 { 929, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x8001ULL }, // Inst #929 = A2_combine_hh
6147 { 928, 2, 1, 4, 3, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #928 = A2_asrh
6148 { 927, 2, 1, 4, 3, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #927 = A2_aslh
6149 { 926, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0|(1ULL<<MCID::Commutable), 0x3ULL }, // Inst #926 = A2_andp
6150 { 925, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 199, 0, 0x154808000ULL }, // Inst #925 = A2_andir
6151 { 924, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #924 = A2_and
6152 { 923, 3, 1, 4, 1, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #923 = A2_addspl
6153 { 922, 3, 1, 4, 1, 0, 0, HexagonImpOpBase + 0, 169, 0, 0x80000000000003ULL }, // Inst #922 = A2_addsph
6154 { 921, 3, 1, 4, 79, 0, 1, HexagonImpOpBase + 63, 202, 0|(1ULL<<MCID::Commutable), 0x80000000008001ULL }, // Inst #921 = A2_addsat
6155 { 920, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 169, 0|(1ULL<<MCID::Commutable), 0x80000000000003ULL }, // Inst #920 = A2_addpsat
6156 { 919, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable), 0x3ULL }, // Inst #919 = A2_addp
6157 { 918, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0x214808002ULL }, // Inst #918 = A2_addi
6158 { 917, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #917 = A2_addh_l16_sat_ll
6159 { 916, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #916 = A2_addh_l16_sat_hl
6160 { 915, 3, 1, 4, 78, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #915 = A2_addh_l16_ll
6161 { 914, 3, 1, 4, 78, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #914 = A2_addh_l16_hl
6162 { 913, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #913 = A2_addh_h16_sat_ll
6163 { 912, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #912 = A2_addh_h16_sat_lh
6164 { 911, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #911 = A2_addh_h16_sat_hl
6165 { 910, 3, 1, 4, 77, 0, 1, HexagonImpOpBase + 63, 202, 0, 0x80000000008003ULL }, // Inst #910 = A2_addh_h16_sat_hh
6166 { 909, 3, 1, 4, 1, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #909 = A2_addh_h16_ll
6167 { 908, 3, 1, 4, 1, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #908 = A2_addh_h16_lh
6168 { 907, 3, 1, 4, 1, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #907 = A2_addh_h16_hl
6169 { 906, 3, 1, 4, 1, 0, 0, HexagonImpOpBase + 0, 202, 0, 0x80000000008003ULL }, // Inst #906 = A2_addh_h16_hh
6170 { 905, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 202, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #905 = A2_add
6171 { 904, 2, 1, 4, 76, 0, 1, HexagonImpOpBase + 63, 157, 0, 0x8000000000802bULL }, // Inst #904 = A2_abssat
6172 { 903, 2, 1, 4, 76, 0, 0, HexagonImpOpBase + 0, 162, 0, 0x8000000000002bULL }, // Inst #903 = A2_absp
6173 { 902, 2, 1, 4, 76, 0, 0, HexagonImpOpBase + 0, 157, 0, 0x8000000000802bULL }, // Inst #902 = A2_abs
6174 { 901, 3, 0, 4, 75, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1b0114800030ULL }, // Inst #901 = dup_S4_storeiri_io
6175 { 900, 3, 0, 4, 75, 0, 0, HexagonImpOpBase + 0, 516, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0xb0114800030ULL }, // Inst #900 = dup_S4_storeirb_io
6176 { 899, 3, 0, 4, 74, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1b09b2800029ULL }, // Inst #899 = dup_S2_storeri_io
6177 { 898, 3, 0, 4, 74, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x130592800029ULL }, // Inst #898 = dup_S2_storerh_io
6178 { 897, 3, 0, 4, 74, 0, 0, HexagonImpOpBase + 0, 513, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x230dd2800029ULL }, // Inst #897 = dup_S2_storerd_io
6179 { 896, 3, 0, 4, 74, 0, 0, HexagonImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0xb0172800029ULL }, // Inst #896 = dup_S2_storerb_io
6180 { 895, 3, 1, 4, 73, 4, 1, HexagonImpOpBase + 58, 507, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x230000008029ULL }, // Inst #895 = dup_S2_allocframe
6181 { 894, 3, 1, 4, 72, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x130594808024ULL }, // Inst #894 = dup_L2_loadruh_io
6182 { 893, 3, 1, 4, 72, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xb0174808024ULL }, // Inst #893 = dup_L2_loadrub_io
6183 { 892, 3, 1, 4, 72, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1b09b4808024ULL }, // Inst #892 = dup_L2_loadri_io
6184 { 891, 3, 1, 4, 72, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x130594808024ULL }, // Inst #891 = dup_L2_loadrh_io
6185 { 890, 3, 1, 4, 72, 0, 0, HexagonImpOpBase + 0, 501, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x230dd4800024ULL }, // Inst #890 = dup_L2_loadrd_io
6186 { 889, 3, 1, 4, 72, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xb0174808024ULL }, // Inst #889 = dup_L2_loadrb_io
6187 { 888, 2, 1, 4, 71, 1, 1, HexagonImpOpBase + 56, 190, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x200000000024ULL }, // Inst #888 = dup_L2_deallocframe
6188 { 887, 3, 1, 4, 68, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x154800000ULL }, // Inst #887 = dup_C2_cmpeqi
6189 { 886, 3, 1, 4, 70, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::Pseudo), 0x194809400ULL }, // Inst #886 = dup_C2_cmovenewit
6190 { 885, 3, 1, 4, 70, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::Pseudo), 0x194809c00ULL }, // Inst #885 = dup_C2_cmovenewif
6191 { 884, 3, 1, 4, 68, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::Pseudo), 0x194808400ULL }, // Inst #884 = dup_C2_cmoveit
6192 { 883, 3, 1, 4, 68, 0, 0, HexagonImpOpBase + 0, 504, 0|(1ULL<<MCID::Pseudo), 0x194808c00ULL }, // Inst #883 = dup_C2_cmoveif
6193 { 882, 3, 1, 4, 68, 0, 0, HexagonImpOpBase + 0, 501, 0|(1ULL<<MCID::Pseudo), 0x114800000ULL }, // Inst #882 = dup_A4_combineri
6194 { 881, 3, 1, 4, 68, 0, 0, HexagonImpOpBase + 0, 498, 0|(1ULL<<MCID::Pseudo), 0x112800000ULL }, // Inst #881 = dup_A4_combineir
6195 { 880, 3, 1, 4, 68, 0, 0, HexagonImpOpBase + 0, 495, 0|(1ULL<<MCID::Pseudo), 0xc4800000ULL }, // Inst #880 = dup_A4_combineii
6196 { 879, 2, 1, 4, 69, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8000ULL }, // Inst #879 = dup_A2_zxth
6197 { 878, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #878 = dup_A2_zxtb
6198 { 877, 2, 1, 4, 69, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x212808000ULL }, // Inst #877 = dup_A2_tfrsi
6199 { 876, 2, 1, 4, 69, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8000ULL }, // Inst #876 = dup_A2_tfr
6200 { 875, 2, 1, 4, 69, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8000ULL }, // Inst #875 = dup_A2_sxth
6201 { 874, 2, 1, 4, 69, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8000ULL }, // Inst #874 = dup_A2_sxtb
6202 { 873, 3, 1, 4, 68, 0, 0, HexagonImpOpBase + 0, 495, 0|(1ULL<<MCID::Pseudo), 0x112800000ULL }, // Inst #873 = dup_A2_combineii
6203 { 872, 3, 1, 4, 68, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::Pseudo), 0x154808000ULL }, // Inst #872 = dup_A2_andir
6204 { 871, 3, 1, 4, 68, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::Pseudo), 0x214808002ULL }, // Inst #871 = dup_A2_addi
6205 { 870, 3, 1, 4, 68, 0, 0, HexagonImpOpBase + 0, 202, 0|(1ULL<<MCID::Pseudo), 0x8001ULL }, // Inst #870 = dup_A2_add
6206 { 869, 0, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #869 = Y2_k1unlock_map
6207 { 868, 0, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #868 = Y2_k1lock_map
6208 { 867, 1, 0, 4, 67, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x26ULL }, // Inst #867 = Y2_dcfetch
6209 { 866, 2, 1, 4, 66, 0, 0, HexagonImpOpBase + 0, 493, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #866 = Y2_crswap_old
6210 { 865, 2, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 185, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #865 = V6_zldp0
6211 { 864, 1, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 272, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #864 = V6_zld0
6212 { 863, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 465, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #863 = V6_vzh_alt
6213 { 862, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 465, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #862 = V6_vzb_alt
6214 { 861, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 465, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #861 = V6_vunpackuh_alt
6215 { 860, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 465, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #860 = V6_vunpackub_alt
6216 { 859, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 490, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #859 = V6_vunpackoh_alt
6217 { 858, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 490, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #858 = V6_vunpackob_alt
6218 { 857, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 465, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #857 = V6_vunpackh_alt
6219 { 856, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 465, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #856 = V6_vunpackb_alt
6220 { 855, 5, 2, 4, 2, 0, 0, HexagonImpOpBase + 0, 485, 0|(1ULL<<MCID::Pseudo), 0x80c000000008026ULL }, // Inst #855 = V6_vtran2x2_map
6221 { 854, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 406, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #854 = V6_vtmpyhb_alt
6222 { 853, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 402, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #853 = V6_vtmpyhb_acc_alt
6223 { 852, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 406, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #852 = V6_vtmpybus_alt
6224 { 851, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 402, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #851 = V6_vtmpybus_acc_alt
6225 { 850, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 406, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #850 = V6_vtmpyb_alt
6226 { 849, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 402, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #849 = V6_vtmpyb_acc_alt
6227 { 848, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #848 = V6_vsubwsat_dv_alt
6228 { 847, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #847 = V6_vsubwsat_alt
6229 { 846, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #846 = V6_vsubwq_alt
6230 { 845, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #845 = V6_vsubwnq_alt
6231 { 844, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #844 = V6_vsubw_dv_alt
6232 { 843, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #843 = V6_vsubw_alt
6233 { 842, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #842 = V6_vsubuwsat_dv_alt
6234 { 841, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #841 = V6_vsubuwsat_alt
6235 { 840, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #840 = V6_vsubuhw_alt
6236 { 839, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #839 = V6_vsubuhsat_dv_alt
6237 { 838, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #838 = V6_vsubuhsat_alt
6238 { 837, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #837 = V6_vsububsat_dv_alt
6239 { 836, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #836 = V6_vsububsat_alt
6240 { 835, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #835 = V6_vsububh_alt
6241 { 834, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #834 = V6_vsubhw_alt
6242 { 833, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #833 = V6_vsubhsat_dv_alt
6243 { 832, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #832 = V6_vsubhsat_alt
6244 { 831, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #831 = V6_vsubhq_alt
6245 { 830, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #830 = V6_vsubhnq_alt
6246 { 829, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #829 = V6_vsubh_dv_alt
6247 { 828, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #828 = V6_vsubh_alt
6248 { 827, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #827 = V6_vsubbsat_dv_alt
6249 { 826, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #826 = V6_vsubbsat_alt
6250 { 825, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #825 = V6_vsubbq_alt
6251 { 824, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #824 = V6_vsubbnq_alt
6252 { 823, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #823 = V6_vsubb_dv_alt
6253 { 822, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #822 = V6_vsubb_alt
6254 { 821, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #821 = V6_vshufoh_alt
6255 { 820, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #820 = V6_vshufoeh_alt
6256 { 819, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #819 = V6_vshufoeb_alt
6257 { 818, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #818 = V6_vshuffob_alt
6258 { 817, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #817 = V6_vshuffh_alt
6259 { 816, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #816 = V6_vshuffeb_alt
6260 { 815, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #815 = V6_vshuffb_alt
6261 { 814, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #814 = V6_vshufeh_alt
6262 { 813, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 465, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #813 = V6_vsh_alt
6263 { 812, 5, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 471, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #812 = V6_vscattermwq_alt
6264 { 811, 5, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 480, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #811 = V6_vscattermwhq_alt
6265 { 810, 4, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 476, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #810 = V6_vscattermwh_alt
6266 { 809, 4, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 476, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #809 = V6_vscattermwh_add_alt
6267 { 808, 4, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 467, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #808 = V6_vscattermw_alt
6268 { 807, 4, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 467, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #807 = V6_vscattermw_add_alt
6269 { 806, 5, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 471, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #806 = V6_vscattermhq_alt
6270 { 805, 4, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 467, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #805 = V6_vscattermh_alt
6271 { 804, 4, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 467, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #804 = V6_vscattermh_add_alt
6272 { 803, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 465, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #803 = V6_vsb_alt
6273 { 802, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #802 = V6_vsatwh_alt
6274 { 801, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #801 = V6_vsatuwuh_alt
6275 { 800, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #800 = V6_vsathub_alt
6276 { 799, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 461, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #799 = V6_vrsadubi_alt
6277 { 798, 5, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 456, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #798 = V6_vrsadubi_acc_alt
6278 { 797, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #797 = V6_vroundwuh_alt
6279 { 796, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #796 = V6_vroundwh_alt
6280 { 795, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #795 = V6_vrounduwuh_alt
6281 { 794, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #794 = V6_vrounduhub_alt
6282 { 793, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #793 = V6_vroundhub_alt
6283 { 792, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #792 = V6_vroundhb_alt
6284 { 791, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #791 = V6_vrotr_alt
6285 { 790, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #790 = V6_vrmpyubv_alt
6286 { 789, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 416, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #789 = V6_vrmpyubv_acc_alt
6287 { 788, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 461, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #788 = V6_vrmpyubi_alt
6288 { 787, 5, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 456, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #787 = V6_vrmpyubi_acc_alt
6289 { 786, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 453, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #786 = V6_vrmpyub_rtt_alt
6290 { 785, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 449, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #785 = V6_vrmpyub_rtt_acc_alt
6291 { 784, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #784 = V6_vrmpyub_alt
6292 { 783, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #783 = V6_vrmpyub_acc_alt
6293 { 782, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #782 = V6_vrmpybv_alt
6294 { 781, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 416, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #781 = V6_vrmpybv_acc_alt
6295 { 780, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #780 = V6_vrmpybusv_alt
6296 { 779, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 416, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #779 = V6_vrmpybusv_acc_alt
6297 { 778, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 461, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #778 = V6_vrmpybusi_alt
6298 { 777, 5, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 456, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #777 = V6_vrmpybusi_acc_alt
6299 { 776, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #776 = V6_vrmpybus_alt
6300 { 775, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #775 = V6_vrmpybus_acc_alt
6301 { 774, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 453, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #774 = V6_vrmpybub_rtt_alt
6302 { 773, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 449, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #773 = V6_vrmpybub_rtt_acc_alt
6303 { 772, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #772 = V6_vpopcounth_alt
6304 { 771, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #771 = V6_vpackwuh_sat_alt
6305 { 770, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #770 = V6_vpackwh_sat_alt
6306 { 769, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #769 = V6_vpackoh_alt
6307 { 768, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #768 = V6_vpackob_alt
6308 { 767, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #767 = V6_vpackhub_sat_alt
6309 { 766, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #766 = V6_vpackhb_sat_alt
6310 { 765, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #765 = V6_vpackeh_alt
6311 { 764, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #764 = V6_vpackeb_alt
6312 { 763, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #763 = V6_vnormamtw_alt
6313 { 762, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #762 = V6_vnormamth_alt
6314 { 761, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #761 = V6_vnavgw_alt
6315 { 760, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #760 = V6_vnavgub_alt
6316 { 759, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #759 = V6_vnavgh_alt
6317 { 758, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #758 = V6_vnavgb_alt
6318 { 757, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #757 = V6_vmpyuhv_alt
6319 { 756, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 371, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #756 = V6_vmpyuhv_acc_alt
6320 { 755, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 446, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #755 = V6_vmpyuh_alt
6321 { 754, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 442, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #754 = V6_vmpyuh_acc_alt
6322 { 753, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #753 = V6_vmpyubv_alt
6323 { 752, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 371, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #752 = V6_vmpyubv_acc_alt
6324 { 751, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 446, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #751 = V6_vmpyub_alt
6325 { 750, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 442, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #750 = V6_vmpyub_acc_alt
6326 { 749, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 416, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #749 = V6_vmpyowh_sacc_alt
6327 { 748, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 416, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #748 = V6_vmpyowh_rnd_sacc_alt
6328 { 747, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #747 = V6_vmpyowh_rnd_alt
6329 { 746, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #746 = V6_vmpyowh_alt
6330 { 745, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #745 = V6_vmpyiwub_alt
6331 { 744, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #744 = V6_vmpyiwub_acc_alt
6332 { 743, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #743 = V6_vmpyiwh_alt
6333 { 742, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #742 = V6_vmpyiwh_acc_alt
6334 { 741, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #741 = V6_vmpyiwb_alt
6335 { 740, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #740 = V6_vmpyiwb_acc_alt
6336 { 739, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #739 = V6_vmpyiowh_alt
6337 { 738, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #738 = V6_vmpyihb_alt
6338 { 737, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #737 = V6_vmpyihb_acc_alt
6339 { 736, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #736 = V6_vmpyih_alt
6340 { 735, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 416, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #735 = V6_vmpyih_acc_alt
6341 { 734, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #734 = V6_vmpyiewuh_alt
6342 { 733, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 416, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #733 = V6_vmpyiewuh_acc_alt
6343 { 732, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 416, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #732 = V6_vmpyiewh_acc_alt
6344 { 731, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #731 = V6_vmpyhvsrs_alt
6345 { 730, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #730 = V6_vmpyhv_alt
6346 { 729, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 371, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #729 = V6_vmpyhv_acc_alt
6347 { 728, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #728 = V6_vmpyhus_alt
6348 { 727, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 371, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #727 = V6_vmpyhus_acc_alt
6349 { 726, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #726 = V6_vmpyhss_alt
6350 { 725, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #725 = V6_vmpyhsrs_alt
6351 { 724, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 442, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #724 = V6_vmpyhsat_acc_alt
6352 { 723, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 446, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #723 = V6_vmpyh_alt
6353 { 722, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 442, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #722 = V6_vmpyh_acc_alt
6354 { 721, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #721 = V6_vmpyewuh_alt
6355 { 720, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #720 = V6_vmpybv_alt
6356 { 719, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 371, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #719 = V6_vmpybv_acc_alt
6357 { 718, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #718 = V6_vmpybusv_alt
6358 { 717, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 371, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #717 = V6_vmpybusv_acc_alt
6359 { 716, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 446, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #716 = V6_vmpybus_alt
6360 { 715, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 442, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #715 = V6_vmpybus_acc_alt
6361 { 714, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 406, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #714 = V6_vmpauhb_alt
6362 { 713, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 402, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #713 = V6_vmpauhb_acc_alt
6363 { 712, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 406, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #712 = V6_vmpahb_alt
6364 { 711, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 402, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #711 = V6_vmpahb_acc_alt
6365 { 710, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #710 = V6_vmpabuuv_alt
6366 { 709, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 406, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #709 = V6_vmpabuu_alt
6367 { 708, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 402, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #708 = V6_vmpabuu_acc_alt
6368 { 707, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #707 = V6_vmpabusv_alt
6369 { 706, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 406, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #706 = V6_vmpabus_alt
6370 { 705, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 402, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #705 = V6_vmpabus_acc_alt
6371 { 704, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #704 = V6_vminw_alt
6372 { 703, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #703 = V6_vminuh_alt
6373 { 702, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #702 = V6_vminub_alt
6374 { 701, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #701 = V6_vminh_alt
6375 { 700, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #700 = V6_vminb_alt
6376 { 699, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #699 = V6_vmaxw_alt
6377 { 698, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #698 = V6_vmaxuh_alt
6378 { 697, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #697 = V6_vmaxub_alt
6379 { 696, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #696 = V6_vmaxh_alt
6380 { 695, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #695 = V6_vmaxb_alt
6381 { 694, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #694 = V6_vlsrwv_alt
6382 { 693, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #693 = V6_vlsrw_alt
6383 { 692, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #692 = V6_vlsrhv_alt
6384 { 691, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #691 = V6_vlsrh_alt
6385 { 690, 6, 0, 4, 65, 0, 0, HexagonImpOpBase + 0, 425, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b0000000007ULL }, // Inst #690 = V6_vgathermwq_pseudo
6386 { 689, 5, 0, 4, 65, 0, 0, HexagonImpOpBase + 0, 420, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b0000000007ULL }, // Inst #689 = V6_vgathermw_pseudo
6387 { 688, 6, 0, 4, 65, 0, 0, HexagonImpOpBase + 0, 436, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x130000000007ULL }, // Inst #688 = V6_vgathermhwq_pseudo
6388 { 687, 5, 0, 4, 65, 0, 0, HexagonImpOpBase + 0, 431, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x130000000007ULL }, // Inst #687 = V6_vgathermhw_pseudo
6389 { 686, 6, 0, 4, 65, 0, 0, HexagonImpOpBase + 0, 425, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x130000000007ULL }, // Inst #686 = V6_vgathermhq_pseudo
6390 { 685, 5, 0, 4, 65, 0, 0, HexagonImpOpBase + 0, 420, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x130000000007ULL }, // Inst #685 = V6_vgathermh_pseudo
6391 { 684, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 406, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #684 = V6_vdsaduh_alt
6392 { 683, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 402, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #683 = V6_vdsaduh_acc_alt
6393 { 682, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #682 = V6_vdmpyhvsat_alt
6394 { 681, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 416, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #681 = V6_vdmpyhvsat_acc_alt
6395 { 680, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #680 = V6_vdmpyhsusat_alt
6396 { 679, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #679 = V6_vdmpyhsusat_acc_alt
6397 { 678, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 413, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #678 = V6_vdmpyhsuisat_alt
6398 { 677, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 409, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #677 = V6_vdmpyhsuisat_acc_alt
6399 { 676, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #676 = V6_vdmpyhsat_alt
6400 { 675, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #675 = V6_vdmpyhsat_acc_alt
6401 { 674, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 413, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #674 = V6_vdmpyhisat_alt
6402 { 673, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 409, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #673 = V6_vdmpyhisat_acc_alt
6403 { 672, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 406, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #672 = V6_vdmpyhb_dv_alt
6404 { 671, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 402, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #671 = V6_vdmpyhb_dv_acc_alt
6405 { 670, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #670 = V6_vdmpyhb_alt
6406 { 669, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #669 = V6_vdmpyhb_acc_alt
6407 { 668, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 406, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #668 = V6_vdmpybus_dv_alt
6408 { 667, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 402, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #667 = V6_vdmpybus_dv_acc_alt
6409 { 666, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #666 = V6_vdmpybus_alt
6410 { 665, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #665 = V6_vdmpybus_acc_alt
6411 { 664, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #664 = V6_vdealh_alt
6412 { 663, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #663 = V6_vdealb_alt
6413 { 662, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #662 = V6_vdealb4w_alt
6414 { 661, 1, 1, 4, 64, 0, 0, HexagonImpOpBase + 0, 273, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #661 = V6_vdd0
6415 { 660, 1, 1, 4, 60, 0, 0, HexagonImpOpBase + 0, 401, 0|(1ULL<<MCID::Pseudo), 0x800000000008010ULL }, // Inst #660 = V6_vd0
6416 { 659, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #659 = V6_vcl0w_alt
6417 { 658, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #658 = V6_vcl0h_alt
6418 { 657, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #657 = V6_vavgwrnd_alt
6419 { 656, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #656 = V6_vavgw_alt
6420 { 655, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #655 = V6_vavguwrnd_alt
6421 { 654, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #654 = V6_vavguw_alt
6422 { 653, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #653 = V6_vavguhrnd_alt
6423 { 652, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #652 = V6_vavguh_alt
6424 { 651, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #651 = V6_vavgubrnd_alt
6425 { 650, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #650 = V6_vavgub_alt
6426 { 649, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #649 = V6_vavghrnd_alt
6427 { 648, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #648 = V6_vavgh_alt
6428 { 647, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #647 = V6_vavgbrnd_alt
6429 { 646, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #646 = V6_vavgb_alt
6430 { 645, 2, 1, 4, 60, 0, 0, HexagonImpOpBase + 0, 399, 0|(1ULL<<MCID::Pseudo), 0x800000000008011ULL }, // Inst #645 = V6_vassignp
6431 { 644, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #644 = V6_vasrwv_alt
6432 { 643, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #643 = V6_vasrw_alt
6433 { 642, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #642 = V6_vasrw_acc_alt
6434 { 641, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #641 = V6_vasrhv_alt
6435 { 640, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #640 = V6_vasrh_alt
6436 { 639, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #639 = V6_vasrh_acc_alt
6437 { 638, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 371, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #638 = V6_vasr_into_alt
6438 { 637, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #637 = V6_vaslwv_alt
6439 { 636, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #636 = V6_vaslw_alt
6440 { 635, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #635 = V6_vaslw_acc_alt
6441 { 634, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #634 = V6_vaslhv_alt
6442 { 633, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #633 = V6_vaslh_alt
6443 { 632, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #632 = V6_vaslh_acc_alt
6444 { 631, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 389, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #631 = V6_vandvrt_alt
6445 { 630, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 385, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #630 = V6_vandvrt_acc_alt
6446 { 629, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 382, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #629 = V6_vandqrt_alt
6447 { 628, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 378, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #628 = V6_vandqrt_acc_alt
6448 { 627, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 382, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #627 = V6_vandnqrt_alt
6449 { 626, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 378, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #626 = V6_vandnqrt_acc_alt
6450 { 625, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #625 = V6_vaddwsat_dv_alt
6451 { 624, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #624 = V6_vaddwsat_alt
6452 { 623, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #623 = V6_vaddwq_alt
6453 { 622, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #622 = V6_vaddwnq_alt
6454 { 621, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #621 = V6_vaddw_dv_alt
6455 { 620, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #620 = V6_vaddw_alt
6456 { 619, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #619 = V6_vadduwsat_dv_alt
6457 { 618, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #618 = V6_vadduwsat_alt
6458 { 617, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #617 = V6_vadduhw_alt
6459 { 616, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 371, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #616 = V6_vadduhw_acc_alt
6460 { 615, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #615 = V6_vadduhsat_dv_alt
6461 { 614, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #614 = V6_vadduhsat_alt
6462 { 613, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #613 = V6_vaddubsat_dv_alt
6463 { 612, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #612 = V6_vaddubsat_alt
6464 { 611, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #611 = V6_vaddubh_alt
6465 { 610, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 371, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #610 = V6_vaddubh_acc_alt
6466 { 609, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #609 = V6_vaddhw_alt
6467 { 608, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 371, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #608 = V6_vaddhw_acc_alt
6468 { 607, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #607 = V6_vaddhsat_dv_alt
6469 { 606, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #606 = V6_vaddhsat_alt
6470 { 605, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #605 = V6_vaddhq_alt
6471 { 604, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #604 = V6_vaddhnq_alt
6472 { 603, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #603 = V6_vaddh_dv_alt
6473 { 602, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #602 = V6_vaddh_alt
6474 { 601, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #601 = V6_vaddbsat_dv_alt
6475 { 600, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #600 = V6_vaddbsat_alt
6476 { 599, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #599 = V6_vaddbq_alt
6477 { 598, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #598 = V6_vaddbnq_alt
6478 { 597, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 364, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #597 = V6_vaddb_dv_alt
6479 { 596, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #596 = V6_vaddb_alt
6480 { 595, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #595 = V6_vabsw_sat_alt
6481 { 594, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #594 = V6_vabsw_alt
6482 { 593, 2, 1, 4, 63, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #593 = V6_vabsuw_alt
6483 { 592, 2, 1, 4, 63, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #592 = V6_vabsuh_alt
6484 { 591, 2, 1, 4, 63, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #591 = V6_vabsub_alt
6485 { 590, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #590 = V6_vabsh_sat_alt
6486 { 589, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #589 = V6_vabsh_alt
6487 { 588, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #588 = V6_vabsdiffw_alt
6488 { 587, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #587 = V6_vabsdiffuh_alt
6489 { 586, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #586 = V6_vabsdiffub_alt
6490 { 585, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #585 = V6_vabsdiffh_alt
6491 { 584, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #584 = V6_vabsb_sat_alt
6492 { 583, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #583 = V6_vabsb_alt
6493 { 582, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 350, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #582 = V6_v6mpyvubs10_alt
6494 { 581, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 350, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #581 = V6_v6mpyhubs10_alt
6495 { 580, 5, 1, 4, 62, 0, 0, HexagonImpOpBase + 0, 354, 0|(1ULL<<MCID::Pseudo), 0x84000000000801cULL }, // Inst #580 = V6_v10mpyubs10_vxx
6496 { 579, 4, 1, 4, 61, 0, 0, HexagonImpOpBase + 0, 350, 0|(1ULL<<MCID::Pseudo), 0x80000000000801cULL }, // Inst #579 = V6_v10mpyubs10
6497 { 578, 3, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 344, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #578 = V6_stup0
6498 { 577, 3, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 344, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #577 = V6_stunp0
6499 { 576, 2, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 342, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #576 = V6_stu0
6500 { 575, 3, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 347, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #575 = V6_stqnt0
6501 { 574, 3, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 347, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #574 = V6_stq0
6502 { 573, 3, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 344, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #573 = V6_stpnt0
6503 { 572, 3, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 344, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #572 = V6_stp0
6504 { 571, 2, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 342, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #571 = V6_stnt0
6505 { 570, 3, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 347, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #570 = V6_stnqnt0
6506 { 569, 3, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 347, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #569 = V6_stnq0
6507 { 568, 3, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 344, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #568 = V6_stnpnt0
6508 { 567, 3, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 344, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #567 = V6_stnp0
6509 { 566, 2, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 342, 0|(1ULL<<MCID::Pseudo), 0x800000000010014ULL }, // Inst #566 = V6_stnnt0
6510 { 565, 2, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 342, 0|(1ULL<<MCID::Pseudo), 0x800000000010014ULL }, // Inst #565 = V6_stn0
6511 { 564, 2, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 342, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #564 = V6_st0
6512 { 563, 2, 1, 4, 60, 0, 0, HexagonImpOpBase + 0, 337, 0|(1ULL<<MCID::Pseudo), 0x800000000008010ULL }, // Inst #563 = V6_lo
6513 { 562, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 289, 0|(1ULL<<MCID::Pseudo), 0x800000000008012ULL }, // Inst #562 = V6_ldu0
6514 { 561, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 339, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #561 = V6_ldtpnt0
6515 { 560, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 339, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #560 = V6_ldtp0
6516 { 559, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 339, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #559 = V6_ldtnpnt0
6517 { 558, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 339, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #558 = V6_ldtnp0
6518 { 557, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 339, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #557 = V6_ldpnt0
6519 { 556, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 339, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #556 = V6_ldp0
6520 { 555, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 289, 0|(1ULL<<MCID::Pseudo), 0x800000000008012ULL }, // Inst #555 = V6_ldnt0
6521 { 554, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 339, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #554 = V6_ldnpnt0
6522 { 553, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 339, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #553 = V6_ldnp0
6523 { 552, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 339, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #552 = V6_ldcpnt0
6524 { 551, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 339, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #551 = V6_ldcp0
6525 { 550, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 339, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #550 = V6_ldcnpnt0
6526 { 549, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 339, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #549 = V6_ldcnp0
6527 { 548, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 289, 0|(1ULL<<MCID::Pseudo), 0x800000000008012ULL }, // Inst #548 = V6_ld0
6528 { 547, 2, 1, 4, 60, 0, 0, HexagonImpOpBase + 0, 337, 0|(1ULL<<MCID::Pseudo), 0x800000000008010ULL }, // Inst #547 = V6_hi
6529 { 546, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 334, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #546 = V6_extractw_alt
6530 { 545, 2, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 332, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x800000000000026ULL }, // Inst #545 = V6_dbl_st0
6531 { 544, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 330, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x800000000408026ULL }, // Inst #544 = V6_dbl_ld0
6532 { 543, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 326, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #543 = V6_MAP_equw_xor
6533 { 542, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 326, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #542 = V6_MAP_equw_ior
6534 { 541, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 326, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #541 = V6_MAP_equw_and
6535 { 540, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 323, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #540 = V6_MAP_equw
6536 { 539, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 326, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #539 = V6_MAP_equh_xor
6537 { 538, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 326, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #538 = V6_MAP_equh_ior
6538 { 537, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 326, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #537 = V6_MAP_equh_and
6539 { 536, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 323, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #536 = V6_MAP_equh
6540 { 535, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 326, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #535 = V6_MAP_equb_xor
6541 { 534, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 326, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #534 = V6_MAP_equb_ior
6542 { 533, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 326, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #533 = V6_MAP_equb_and
6543 { 532, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 323, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #532 = V6_MAP_equb
6544 { 531, 3, 0, 4, 59, 0, 0, HexagonImpOpBase + 0, 320, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1b2800029ULL }, // Inst #531 = STriw_pred
6545 { 530, 3, 0, 4, 59, 0, 0, HexagonImpOpBase + 0, 317, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1b2800029ULL }, // Inst #530 = STriw_ctr
6546 { 529, 1, 0, 4, 58, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #529 = S6_allocframe_to_raw
6547 { 528, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 304, 0|(1ULL<<MCID::Pseudo), 0x2bULL }, // Inst #528 = S5_vasrhrnd_goodsyntax
6548 { 527, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 314, 0|(1ULL<<MCID::Pseudo), 0x802bULL }, // Inst #527 = S5_asrhub_rnd_sat_goodsyntax
6549 { 526, 3, 0, 4, 57, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #526 = S4_storeiritnew_zomap
6550 { 525, 3, 0, 4, 56, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #525 = S4_storeirit_zomap
6551 { 524, 3, 0, 4, 57, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #524 = S4_storeirifnew_zomap
6552 { 523, 3, 0, 4, 56, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #523 = S4_storeirif_zomap
6553 { 522, 2, 0, 4, 55, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #522 = S4_storeiri_zomap
6554 { 521, 3, 0, 4, 57, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #521 = S4_storeirhtnew_zomap
6555 { 520, 3, 0, 4, 56, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #520 = S4_storeirht_zomap
6556 { 519, 3, 0, 4, 57, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #519 = S4_storeirhfnew_zomap
6557 { 518, 3, 0, 4, 56, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #518 = S4_storeirhf_zomap
6558 { 517, 2, 0, 4, 55, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #517 = S4_storeirh_zomap
6559 { 516, 3, 0, 4, 57, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #516 = S4_storeirbtnew_zomap
6560 { 515, 3, 0, 4, 56, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #515 = S4_storeirbt_zomap
6561 { 514, 3, 0, 4, 57, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #514 = S4_storeirbfnew_zomap
6562 { 513, 3, 0, 4, 56, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #513 = S4_storeirbf_zomap
6563 { 512, 2, 0, 4, 55, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #512 = S4_storeirb_zomap
6564 { 511, 3, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #511 = S4_pstoreritnew_zomap
6565 { 510, 3, 0, 4, 54, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #510 = S4_pstorerinewtnew_zomap
6566 { 509, 3, 0, 4, 54, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #509 = S4_pstorerinewfnew_zomap
6567 { 508, 3, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #508 = S4_pstorerifnew_zomap
6568 { 507, 3, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #507 = S4_pstorerhtnew_zomap
6569 { 506, 3, 0, 4, 54, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #506 = S4_pstorerhnewtnew_zomap
6570 { 505, 3, 0, 4, 54, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #505 = S4_pstorerhnewfnew_zomap
6571 { 504, 3, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #504 = S4_pstorerhfnew_zomap
6572 { 503, 3, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #503 = S4_pstorerftnew_zomap
6573 { 502, 3, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #502 = S4_pstorerffnew_zomap
6574 { 501, 3, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 172, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #501 = S4_pstorerdtnew_zomap
6575 { 500, 3, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 172, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #500 = S4_pstorerdfnew_zomap
6576 { 499, 3, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #499 = S4_pstorerbtnew_zomap
6577 { 498, 3, 0, 4, 54, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #498 = S4_pstorerbnewtnew_zomap
6578 { 497, 3, 0, 4, 54, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #497 = S4_pstorerbnewfnew_zomap
6579 { 496, 3, 0, 4, 39, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #496 = S4_pstorerbfnew_zomap
6580 { 495, 5, 1, 4, 53, 0, 0, HexagonImpOpBase + 0, 309, 0|(1ULL<<MCID::Pseudo), 0x802bULL }, // Inst #495 = S2_tableidxw_goodsyntax
6581 { 494, 5, 1, 4, 53, 0, 0, HexagonImpOpBase + 0, 309, 0|(1ULL<<MCID::Pseudo), 0x802bULL }, // Inst #494 = S2_tableidxh_goodsyntax
6582 { 493, 5, 1, 4, 53, 0, 0, HexagonImpOpBase + 0, 309, 0|(1ULL<<MCID::Pseudo), 0x802bULL }, // Inst #493 = S2_tableidxd_goodsyntax
6583 { 492, 5, 1, 4, 53, 0, 0, HexagonImpOpBase + 0, 309, 0|(1ULL<<MCID::Pseudo), 0x802bULL }, // Inst #492 = S2_tableidxb_goodsyntax
6584 { 491, 2, 0, 4, 52, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x10026ULL }, // Inst #491 = S2_storerinew_zomap
6585 { 490, 2, 0, 4, 51, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #490 = S2_storeri_zomap
6586 { 489, 2, 0, 4, 52, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x10026ULL }, // Inst #489 = S2_storerhnew_zomap
6587 { 488, 2, 0, 4, 51, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #488 = S2_storerh_zomap
6588 { 487, 2, 0, 4, 51, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #487 = S2_storerf_zomap
6589 { 486, 2, 0, 4, 51, 0, 0, HexagonImpOpBase + 0, 307, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #486 = S2_storerd_zomap
6590 { 485, 2, 0, 4, 52, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x10026ULL }, // Inst #485 = S2_storerbnew_zomap
6591 { 484, 2, 0, 4, 51, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #484 = S2_storerb_zomap
6592 { 483, 3, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #483 = S2_pstorerit_zomap
6593 { 482, 3, 0, 4, 50, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #482 = S2_pstorerinewt_zomap
6594 { 481, 3, 0, 4, 50, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #481 = S2_pstorerinewf_zomap
6595 { 480, 3, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #480 = S2_pstorerif_zomap
6596 { 479, 3, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #479 = S2_pstorerht_zomap
6597 { 478, 3, 0, 4, 50, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #478 = S2_pstorerhnewt_zomap
6598 { 477, 3, 0, 4, 50, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #477 = S2_pstorerhnewf_zomap
6599 { 476, 3, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #476 = S2_pstorerhf_zomap
6600 { 475, 3, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #475 = S2_pstorerft_zomap
6601 { 474, 3, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #474 = S2_pstorerff_zomap
6602 { 473, 3, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 172, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #473 = S2_pstorerdt_zomap
6603 { 472, 3, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 172, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #472 = S2_pstorerdf_zomap
6604 { 471, 3, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #471 = S2_pstorerbt_zomap
6605 { 470, 3, 0, 4, 50, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #470 = S2_pstorerbnewt_zomap
6606 { 469, 3, 0, 4, 50, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #469 = S2_pstorerbnewf_zomap
6607 { 468, 3, 0, 4, 49, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #468 = S2_pstorerbf_zomap
6608 { 467, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::Pseudo), 0x802bULL }, // Inst #467 = S2_asr_i_r_rnd_goodsyntax
6609 { 466, 3, 1, 4, 48, 0, 0, HexagonImpOpBase + 0, 304, 0|(1ULL<<MCID::Pseudo), 0x2bULL }, // Inst #466 = S2_asr_i_p_rnd_goodsyntax
6610 { 465, 4, 1, 4, 47, 0, 0, HexagonImpOpBase + 0, 300, 0|(1ULL<<MCID::Pseudo), 0x11ULL }, // Inst #465 = PS_wselect
6611 { 464, 3, 0, 4, 46, 0, 0, HexagonImpOpBase + 0, 297, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x280000000014ULL }, // Inst #464 = PS_vstorerw_nt_ai
6612 { 463, 3, 0, 4, 46, 0, 0, HexagonImpOpBase + 0, 297, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x280000000014ULL }, // Inst #463 = PS_vstorerw_ai
6613 { 462, 3, 0, 4, 46, 0, 0, HexagonImpOpBase + 0, 294, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x280000000014ULL }, // Inst #462 = PS_vstorerv_nt_ai
6614 { 461, 3, 0, 4, 46, 0, 0, HexagonImpOpBase + 0, 294, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x280000000014ULL }, // Inst #461 = PS_vstorerv_ai
6615 { 460, 3, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 291, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x28ULL }, // Inst #460 = PS_vstorerq_ai
6616 { 459, 2, 1, 4, 45, 0, 0, HexagonImpOpBase + 0, 289, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x1eULL }, // Inst #459 = PS_vsplatrw
6617 { 458, 2, 1, 4, 45, 0, 0, HexagonImpOpBase + 0, 289, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x1eULL }, // Inst #458 = PS_vsplatrh
6618 { 457, 2, 1, 4, 45, 0, 0, HexagonImpOpBase + 0, 289, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x1eULL }, // Inst #457 = PS_vsplatrb
6619 { 456, 2, 1, 4, 45, 0, 0, HexagonImpOpBase + 0, 287, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x1eULL }, // Inst #456 = PS_vsplatiw
6620 { 455, 2, 1, 4, 45, 0, 0, HexagonImpOpBase + 0, 287, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x1eULL }, // Inst #455 = PS_vsplatih
6621 { 454, 2, 1, 4, 45, 0, 0, HexagonImpOpBase + 0, 287, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x1eULL }, // Inst #454 = PS_vsplatib
6622 { 453, 4, 1, 4, 44, 0, 0, HexagonImpOpBase + 0, 283, 0|(1ULL<<MCID::Pseudo), 0x10ULL }, // Inst #453 = PS_vselect
6623 { 452, 4, 1, 4, 43, 0, 0, HexagonImpOpBase + 0, 215, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #452 = PS_vmulw_acc
6624 { 451, 3, 1, 4, 43, 0, 0, HexagonImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #451 = PS_vmulw
6625 { 450, 3, 1, 4, 42, 0, 0, HexagonImpOpBase + 0, 280, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x280000000012ULL }, // Inst #450 = PS_vloadrw_nt_ai
6626 { 449, 3, 1, 4, 42, 0, 0, HexagonImpOpBase + 0, 280, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x280000000012ULL }, // Inst #449 = PS_vloadrw_ai
6627 { 448, 3, 1, 4, 42, 0, 0, HexagonImpOpBase + 0, 277, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x280000000012ULL }, // Inst #448 = PS_vloadrv_nt_ai
6628 { 447, 3, 1, 4, 42, 0, 0, HexagonImpOpBase + 0, 277, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x280000000012ULL }, // Inst #447 = PS_vloadrv_ai
6629 { 446, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 274, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x28ULL }, // Inst #446 = PS_vloadrq_ai
6630 { 445, 1, 1, 4, 41, 0, 0, HexagonImpOpBase + 0, 273, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x11ULL }, // Inst #445 = PS_vdd0
6631 { 444, 1, 1, 4, 11, 0, 0, HexagonImpOpBase + 0, 195, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x5ULL }, // Inst #444 = PS_true
6632 { 443, 1, 0, 4, 40, 0, 1, HexagonImpOpBase + 55, 272, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x1000000023ULL }, // Inst #443 = PS_tailcall_r
6633 { 442, 1, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x28ULL }, // Inst #442 = PS_tailcall_i
6634 { 441, 5, 1, 4, 39, 1, 1, HexagonImpOpBase + 53, 256, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1e0000000029ULL }, // Inst #441 = PS_storeri_pcr
6635 { 440, 6, 1, 4, 38, 1, 1, HexagonImpOpBase + 53, 250, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1e0000000029ULL }, // Inst #440 = PS_storeri_pci
6636 { 439, 5, 1, 4, 39, 1, 1, HexagonImpOpBase + 53, 256, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #439 = PS_storerh_pcr
6637 { 438, 6, 1, 4, 38, 1, 1, HexagonImpOpBase + 53, 250, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #438 = PS_storerh_pci
6638 { 437, 5, 1, 4, 39, 1, 1, HexagonImpOpBase + 53, 256, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #437 = PS_storerf_pcr
6639 { 436, 6, 1, 4, 38, 1, 1, HexagonImpOpBase + 53, 250, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #436 = PS_storerf_pci
6640 { 435, 5, 1, 4, 39, 1, 1, HexagonImpOpBase + 53, 267, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1e0000000029ULL }, // Inst #435 = PS_storerd_pcr
6641 { 434, 6, 1, 4, 38, 1, 1, HexagonImpOpBase + 53, 261, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1e0000000029ULL }, // Inst #434 = PS_storerd_pci
6642 { 433, 5, 1, 4, 39, 1, 1, HexagonImpOpBase + 53, 256, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0xe0000000029ULL }, // Inst #433 = PS_storerb_pcr
6643 { 432, 6, 1, 4, 38, 1, 1, HexagonImpOpBase + 53, 250, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0xe0000000029ULL }, // Inst #432 = PS_storerb_pci
6644 { 431, 1, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 249, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x10ULL }, // Inst #431 = PS_qtrue
6645 { 430, 1, 1, 4, 37, 0, 0, HexagonImpOpBase + 0, 249, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x10ULL }, // Inst #430 = PS_qfalse
6646 { 429, 4, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 245, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #429 = PS_pselect
6647 { 428, 5, 2, 4, 20, 1, 1, HexagonImpOpBase + 53, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #428 = PS_loadruh_pcr
6648 { 427, 6, 2, 4, 36, 1, 1, HexagonImpOpBase + 53, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #427 = PS_loadruh_pci
6649 { 426, 5, 2, 4, 20, 1, 1, HexagonImpOpBase + 53, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #426 = PS_loadrub_pcr
6650 { 425, 6, 2, 4, 36, 1, 1, HexagonImpOpBase + 53, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #425 = PS_loadrub_pci
6651 { 424, 5, 2, 4, 20, 1, 1, HexagonImpOpBase + 53, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #424 = PS_loadri_pcr
6652 { 423, 6, 2, 4, 36, 1, 1, HexagonImpOpBase + 53, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #423 = PS_loadri_pci
6653 { 422, 5, 2, 4, 20, 1, 1, HexagonImpOpBase + 53, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #422 = PS_loadrh_pcr
6654 { 421, 6, 2, 4, 36, 1, 1, HexagonImpOpBase + 53, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #421 = PS_loadrh_pci
6655 { 420, 5, 2, 4, 20, 1, 1, HexagonImpOpBase + 53, 240, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x260000000024ULL }, // Inst #420 = PS_loadrd_pcr
6656 { 419, 6, 2, 4, 36, 1, 1, HexagonImpOpBase + 53, 234, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x260000000024ULL }, // Inst #419 = PS_loadrd_pci
6657 { 418, 5, 2, 4, 20, 1, 1, HexagonImpOpBase + 53, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #418 = PS_loadrb_pcr
6658 { 417, 6, 2, 4, 36, 1, 1, HexagonImpOpBase + 53, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #417 = PS_loadrb_pci
6659 { 416, 4, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 219, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x216800028ULL }, // Inst #416 = PS_fia
6660 { 415, 3, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x214800028ULL }, // Inst #415 = PS_fi
6661 { 414, 1, 1, 4, 11, 0, 0, HexagonImpOpBase + 0, 195, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x5ULL }, // Inst #414 = PS_false
6662 { 413, 0, 0, 4, 2, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0xa8ULL }, // Inst #413 = PS_crash
6663 { 412, 1, 0, 4, 35, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800028ULL }, // Inst #412 = PS_call_nr
6664 { 411, 2, 0, 4, 2, 0, 8, HexagonImpOpBase + 45, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #411 = PS_call_instrprof_custom
6665 { 410, 3, 1, 4, 2, 0, 1, HexagonImpOpBase + 44, 199, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #410 = PS_alloca
6666 { 409, 2, 1, 4, 2, 1, 0, HexagonImpOpBase + 43, 155, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #409 = PS_aligna
6667 { 408, 4, 1, 4, 34, 0, 0, HexagonImpOpBase + 0, 215, 0|(1ULL<<MCID::Pseudo), 0x25ULL }, // Inst #408 = M7_vdmpy_acc
6668 { 407, 3, 1, 4, 33, 0, 0, HexagonImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo), 0x25ULL }, // Inst #407 = M7_vdmpy
6669 { 406, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 212, 0|(1ULL<<MCID::Pseudo), 0x8025ULL }, // Inst #406 = M2_vrcmpys_s1rp
6670 { 405, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 209, 0|(1ULL<<MCID::Pseudo), 0x25ULL }, // Inst #405 = M2_vrcmpys_s1
6671 { 404, 4, 1, 4, 32, 0, 0, HexagonImpOpBase + 0, 205, 0|(1ULL<<MCID::Pseudo), 0x25ULL }, // Inst #404 = M2_vrcmpys_acc_s1
6672 { 403, 3, 1, 4, 31, 0, 0, HexagonImpOpBase + 0, 202, 0|(1ULL<<MCID::Pseudo), 0x8025ULL }, // Inst #403 = M2_mpyui
6673 { 402, 3, 1, 4, 30, 0, 0, HexagonImpOpBase + 0, 199, 0|(1ULL<<MCID::Pseudo), 0x134808025ULL }, // Inst #402 = M2_mpysmi
6674 { 401, 3, 1, 4, 29, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1b4800024ULL }, // Inst #401 = LDriw_pred
6675 { 400, 3, 1, 4, 29, 0, 0, HexagonImpOpBase + 0, 196, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1b4800024ULL }, // Inst #400 = LDriw_ctr
6676 { 399, 0, 0, 4, 28, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #399 = L6_return_map_to_raw
6677 { 398, 0, 0, 4, 27, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #398 = L6_deallocframe_map_to_raw
6678 { 397, 2, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #397 = L4_sub_memopw_zomap
6679 { 396, 2, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #396 = L4_sub_memoph_zomap
6680 { 395, 2, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #395 = L4_sub_memopb_zomap
6681 { 394, 1, 0, 4, 26, 0, 0, HexagonImpOpBase + 0, 195, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #394 = L4_return_map_to_raw_tnew_pt
6682 { 393, 1, 0, 4, 26, 0, 0, HexagonImpOpBase + 0, 195, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #393 = L4_return_map_to_raw_tnew_pnt
6683 { 392, 1, 0, 4, 25, 0, 0, HexagonImpOpBase + 0, 195, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #392 = L4_return_map_to_raw_t
6684 { 391, 1, 0, 4, 24, 0, 0, HexagonImpOpBase + 0, 195, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #391 = L4_return_map_to_raw_fnew_pt
6685 { 390, 1, 0, 4, 24, 0, 0, HexagonImpOpBase + 0, 195, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #390 = L4_return_map_to_raw_fnew_pnt
6686 { 389, 1, 0, 4, 23, 0, 0, HexagonImpOpBase + 0, 195, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #389 = L4_return_map_to_raw_f
6687 { 388, 2, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #388 = L4_or_memopw_zomap
6688 { 387, 2, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #387 = L4_or_memoph_zomap
6689 { 386, 2, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #386 = L4_or_memopb_zomap
6690 { 385, 2, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #385 = L4_isub_memopw_zomap
6691 { 384, 2, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #384 = L4_isub_memoph_zomap
6692 { 383, 2, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #383 = L4_isub_memopb_zomap
6693 { 382, 2, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #382 = L4_ior_memopw_zomap
6694 { 381, 2, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #381 = L4_ior_memoph_zomap
6695 { 380, 2, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #380 = L4_ior_memopb_zomap
6696 { 379, 2, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #379 = L4_iand_memopw_zomap
6697 { 378, 2, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #378 = L4_iand_memoph_zomap
6698 { 377, 2, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #377 = L4_iand_memopb_zomap
6699 { 376, 2, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #376 = L4_iadd_memopw_zomap
6700 { 375, 2, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #375 = L4_iadd_memoph_zomap
6701 { 374, 2, 0, 4, 22, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #374 = L4_iadd_memopb_zomap
6702 { 373, 2, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #373 = L4_and_memopw_zomap
6703 { 372, 2, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #372 = L4_and_memoph_zomap
6704 { 371, 2, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #371 = L4_and_memopb_zomap
6705 { 370, 2, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #370 = L4_add_memopw_zomap
6706 { 369, 2, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #369 = L4_add_memoph_zomap
6707 { 368, 2, 0, 4, 21, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #368 = L4_add_memopb_zomap
6708 { 367, 3, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #367 = L2_ploadruhtnew_zomap
6709 { 366, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #366 = L2_ploadruht_zomap
6710 { 365, 3, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #365 = L2_ploadruhfnew_zomap
6711 { 364, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #364 = L2_ploadruhf_zomap
6712 { 363, 3, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #363 = L2_ploadrubtnew_zomap
6713 { 362, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #362 = L2_ploadrubt_zomap
6714 { 361, 3, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #361 = L2_ploadrubfnew_zomap
6715 { 360, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #360 = L2_ploadrubf_zomap
6716 { 359, 3, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #359 = L2_ploadritnew_zomap
6717 { 358, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #358 = L2_ploadrit_zomap
6718 { 357, 3, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #357 = L2_ploadrifnew_zomap
6719 { 356, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #356 = L2_ploadrif_zomap
6720 { 355, 3, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #355 = L2_ploadrhtnew_zomap
6721 { 354, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #354 = L2_ploadrht_zomap
6722 { 353, 3, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #353 = L2_ploadrhfnew_zomap
6723 { 352, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #352 = L2_ploadrhf_zomap
6724 { 351, 3, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 192, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #351 = L2_ploadrdtnew_zomap
6725 { 350, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 192, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #350 = L2_ploadrdt_zomap
6726 { 349, 3, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 192, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #349 = L2_ploadrdfnew_zomap
6727 { 348, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 192, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #348 = L2_ploadrdf_zomap
6728 { 347, 3, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #347 = L2_ploadrbtnew_zomap
6729 { 346, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #346 = L2_ploadrbt_zomap
6730 { 345, 3, 1, 4, 20, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #345 = L2_ploadrbfnew_zomap
6731 { 344, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #344 = L2_ploadrbf_zomap
6732 { 343, 2, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #343 = L2_loadruh_zomap
6733 { 342, 2, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #342 = L2_loadrub_zomap
6734 { 341, 2, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #341 = L2_loadri_zomap
6735 { 340, 2, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #340 = L2_loadrh_zomap
6736 { 339, 2, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 190, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #339 = L2_loadrd_zomap
6737 { 338, 2, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #338 = L2_loadrb_zomap
6738 { 337, 2, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 190, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #337 = L2_loadbzw4_zomap
6739 { 336, 2, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #336 = L2_loadbzw2_zomap
6740 { 335, 2, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 190, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #335 = L2_loadbsw4_zomap
6741 { 334, 2, 1, 4, 19, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #334 = L2_loadbsw2_zomap
6742 { 333, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #333 = L2_loadalignh_zomap
6743 { 332, 3, 1, 4, 18, 0, 0, HexagonImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #332 = L2_loadalignb_zomap
6744 { 331, 1, 0, 4, 17, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x26ULL }, // Inst #331 = J2_trap1_noregmap
6745 { 330, 2, 0, 4, 15, 0, 0, HexagonImpOpBase + 0, 183, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #330 = J2_jumpt_nopred_map
6746 { 329, 2, 0, 4, 16, 0, 0, HexagonImpOpBase + 0, 185, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #329 = J2_jumprt_nopred_map
6747 { 328, 2, 0, 4, 16, 0, 0, HexagonImpOpBase + 0, 185, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #328 = J2_jumprf_nopred_map
6748 { 327, 2, 0, 4, 15, 0, 0, HexagonImpOpBase + 0, 183, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #327 = J2_jumpf_nopred_map
6749 { 326, 0, 0, 4, 14, 2, 2, HexagonImpOpBase + 39, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x23ULL }, // Inst #326 = J2_endloop1
6750 { 325, 0, 0, 4, 14, 4, 5, HexagonImpOpBase + 30, 1, 0|(1ULL<<MCID::Pseudo), 0x23ULL }, // Inst #325 = J2_endloop01
6751 { 324, 0, 0, 4, 14, 2, 4, HexagonImpOpBase + 24, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x23ULL }, // Inst #324 = J2_endloop0
6752 { 323, 1, 0, 4, 13, 2, 2, HexagonImpOpBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x21ULL }, // Inst #323 = ENDLOOP1
6753 { 322, 1, 0, 4, 13, 4, 3, HexagonImpOpBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x21ULL }, // Inst #322 = ENDLOOP01
6754 { 321, 1, 0, 4, 13, 2, 2, HexagonImpOpBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x21ULL }, // Inst #321 = ENDLOOP0
6755 { 320, 1, 0, 4, 12, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #320 = DUPLEX_Pseudo
6756 { 319, 2, 1, 4, 11, 0, 0, HexagonImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #319 = C2_pxfer_map
6757 { 318, 3, 1, 4, 10, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x1ULL }, // Inst #318 = C2_cmpltu
6758 { 317, 3, 1, 4, 10, 0, 0, HexagonImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x1ULL }, // Inst #317 = C2_cmplt
6759 { 316, 3, 1, 4, 10, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #316 = C2_cmpgeui
6760 { 315, 3, 1, 4, 10, 0, 0, HexagonImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #315 = C2_cmpgei
6761 { 314, 2, 0, 4, 2, 1, 3, HexagonImpOpBase + 5, 21, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #314 = ADJCALLSTACKUP
6762 { 313, 2, 0, 4, 2, 3, 2, HexagonImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #313 = ADJCALLSTACKDOWN
6763 { 312, 3, 1, 4, 9, 0, 0, HexagonImpOpBase + 0, 172, 0|(1ULL<<MCID::Pseudo), 0x3ULL }, // Inst #312 = A4_boundscheck
6764 { 311, 2, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #311 = A2_zxtb
6765 { 310, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #310 = A2_vsubb_map
6766 { 309, 3, 1, 4, 8, 0, 0, HexagonImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #309 = A2_vaddb_map
6767 { 308, 3, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x9400ULL }, // Inst #308 = A2_tfrtnew
6768 { 307, 3, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8400ULL }, // Inst #307 = A2_tfrt
6769 { 306, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x1400ULL }, // Inst #306 = A2_tfrptnew
6770 { 305, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x400ULL }, // Inst #305 = A2_tfrpt
6771 { 304, 2, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3ULL }, // Inst #304 = A2_tfrpi
6772 { 303, 3, 1, 4, 7, 0, 0, HexagonImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x1c00ULL }, // Inst #303 = A2_tfrpfnew
6773 { 302, 3, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0xc00ULL }, // Inst #302 = A2_tfrpf
6774 { 301, 2, 1, 4, 6, 0, 0, HexagonImpOpBase + 0, 162, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #301 = A2_tfrp
6775 { 300, 3, 1, 4, 5, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x9c00ULL }, // Inst #300 = A2_tfrfnew
6776 { 299, 3, 1, 4, 4, 0, 0, HexagonImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x8c00ULL }, // Inst #299 = A2_tfrf
6777 { 298, 2, 1, 4, 3, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8000ULL }, // Inst #298 = A2_not
6778 { 297, 2, 1, 4, 3, 0, 0, HexagonImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x8000ULL }, // Inst #297 = A2_neg
6779 { 296, 2, 1, 4, 2, 0, 0, HexagonImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #296 = A2_iconst
6780 { 295, 3, 1, 4, 1, 0, 0, HexagonImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo), 0x3ULL }, // Inst #295 = A2_addsp
6781 { 294, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_UBFX
6782 { 293, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_SBFX
6783 { 292, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMIN
6784 { 291, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_UMAX
6785 { 290, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMIN
6786 { 289, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #289 = G_VECREDUCE_SMAX
6787 { 288, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #288 = G_VECREDUCE_XOR
6788 { 287, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #287 = G_VECREDUCE_OR
6789 { 286, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #286 = G_VECREDUCE_AND
6790 { 285, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #285 = G_VECREDUCE_MUL
6791 { 284, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #284 = G_VECREDUCE_ADD
6792 { 283, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMINIMUM
6793 { 282, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMAXIMUM
6794 { 281, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMIN
6795 { 280, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMAX
6796 { 279, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #279 = G_VECREDUCE_FMUL
6797 { 278, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #278 = G_VECREDUCE_FADD
6798 { 277, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FMUL
6799 { 276, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #276 = G_VECREDUCE_SEQ_FADD
6800 { 275, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_UBSANTRAP
6801 { 274, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_DEBUGTRAP
6802 { 273, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = G_TRAP
6803 { 272, 3, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #272 = G_BZERO
6804 { 271, 4, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #271 = G_MEMSET
6805 { 270, 4, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #270 = G_MEMMOVE
6806 { 269, 3, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #269 = G_MEMCPY_INLINE
6807 { 268, 4, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #268 = G_MEMCPY
6808 { 267, 2, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_WRITE_REGISTER
6809 { 266, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #266 = G_READ_REGISTER
6810 { 265, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #265 = G_STRICT_FLDEXP
6811 { 264, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #264 = G_STRICT_FSQRT
6812 { 263, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #263 = G_STRICT_FMA
6813 { 262, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #262 = G_STRICT_FREM
6814 { 261, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #261 = G_STRICT_FDIV
6815 { 260, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #260 = G_STRICT_FMUL
6816 { 259, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #259 = G_STRICT_FSUB
6817 { 258, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #258 = G_STRICT_FADD
6818 { 257, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #257 = G_STACKRESTORE
6819 { 256, 1, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #256 = G_STACKSAVE
6820 { 255, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #255 = G_DYN_STACKALLOC
6821 { 254, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_JUMP_TABLE
6822 { 253, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_BLOCK_ADDR
6823 { 252, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_ADDRSPACE_CAST
6824 { 251, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FNEARBYINT
6825 { 250, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_FRINT
6826 { 249, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_FFLOOR
6827 { 248, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_FSQRT
6828 { 247, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_FTANH
6829 { 246, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_FSINH
6830 { 245, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_FCOSH
6831 { 244, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_FATAN
6832 { 243, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_FASIN
6833 { 242, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_FACOS
6834 { 241, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_FTAN
6835 { 240, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_FSIN
6836 { 239, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_FCOS
6837 { 238, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_FCEIL
6838 { 237, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_BITREVERSE
6839 { 236, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_BSWAP
6840 { 235, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_CTPOP
6841 { 234, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #234 = G_CTLZ_ZERO_UNDEF
6842 { 233, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #233 = G_CTLZ
6843 { 232, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_CTTZ_ZERO_UNDEF
6844 { 231, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_CTTZ
6845 { 230, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_VECTOR_COMPRESS
6846 { 229, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #229 = G_SPLAT_VECTOR
6847 { 228, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #228 = G_SHUFFLE_VECTOR
6848 { 227, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #227 = G_EXTRACT_VECTOR_ELT
6849 { 226, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #226 = G_INSERT_VECTOR_ELT
6850 { 225, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_EXTRACT_SUBVECTOR
6851 { 224, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_INSERT_SUBVECTOR
6852 { 223, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #223 = G_VSCALE
6853 { 222, 3, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #222 = G_BRJT
6854 { 221, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #221 = G_BR
6855 { 220, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #220 = G_LLROUND
6856 { 219, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #219 = G_LROUND
6857 { 218, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #218 = G_ABS
6858 { 217, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_UMAX
6859 { 216, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_UMIN
6860 { 215, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_SMAX
6861 { 214, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #214 = G_SMIN
6862 { 213, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #213 = G_PTRMASK
6863 { 212, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #212 = G_PTR_ADD
6864 { 211, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #211 = G_RESET_FPMODE
6865 { 210, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #210 = G_SET_FPMODE
6866 { 209, 1, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #209 = G_GET_FPMODE
6867 { 208, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #208 = G_RESET_FPENV
6868 { 207, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #207 = G_SET_FPENV
6869 { 206, 1, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #206 = G_GET_FPENV
6870 { 205, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #205 = G_FMAXIMUM
6871 { 204, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #204 = G_FMINIMUM
6872 { 203, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #203 = G_FMAXNUM_IEEE
6873 { 202, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #202 = G_FMINNUM_IEEE
6874 { 201, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #201 = G_FMAXNUM
6875 { 200, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #200 = G_FMINNUM
6876 { 199, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_FCANONICALIZE
6877 { 198, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_IS_FPCLASS
6878 { 197, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FCOPYSIGN
6879 { 196, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FABS
6880 { 195, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_UITOFP
6881 { 194, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_SITOFP
6882 { 193, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FPTOUI
6883 { 192, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FPTOSI
6884 { 191, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FPTRUNC
6885 { 190, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FPEXT
6886 { 189, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FNEG
6887 { 188, 3, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FFREXP
6888 { 187, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FLDEXP
6889 { 186, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FLOG10
6890 { 185, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FLOG2
6891 { 184, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FLOG
6892 { 183, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FEXP10
6893 { 182, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #182 = G_FEXP2
6894 { 181, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FEXP
6895 { 180, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #180 = G_FPOWI
6896 { 179, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_FPOW
6897 { 178, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_FREM
6898 { 177, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_FDIV
6899 { 176, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_FMAD
6900 { 175, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #175 = G_FMA
6901 { 174, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #174 = G_FMUL
6902 { 173, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #173 = G_FSUB
6903 { 172, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #172 = G_FADD
6904 { 171, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_UDIVFIXSAT
6905 { 170, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_SDIVFIXSAT
6906 { 169, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_UDIVFIX
6907 { 168, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_SDIVFIX
6908 { 167, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_UMULFIXSAT
6909 { 166, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_SMULFIXSAT
6910 { 165, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_UMULFIX
6911 { 164, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #164 = G_SMULFIX
6912 { 163, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #163 = G_SSHLSAT
6913 { 162, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #162 = G_USHLSAT
6914 { 161, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SSUBSAT
6915 { 160, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_USUBSAT
6916 { 159, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #159 = G_SADDSAT
6917 { 158, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_UADDSAT
6918 { 157, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #157 = G_SMULH
6919 { 156, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #156 = G_UMULH
6920 { 155, 4, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #155 = G_SMULO
6921 { 154, 4, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_UMULO
6922 { 153, 5, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SSUBE
6923 { 152, 4, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_SSUBO
6924 { 151, 5, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_SADDE
6925 { 150, 4, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #150 = G_SADDO
6926 { 149, 5, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_USUBE
6927 { 148, 4, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_USUBO
6928 { 147, 5, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_UADDE
6929 { 146, 4, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #146 = G_UADDO
6930 { 145, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_SELECT
6931 { 144, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_UCMP
6932 { 143, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_SCMP
6933 { 142, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_FCMP
6934 { 141, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ICMP
6935 { 140, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_ROTL
6936 { 139, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_ROTR
6937 { 138, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #138 = G_FSHR
6938 { 137, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #137 = G_FSHL
6939 { 136, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_ASHR
6940 { 135, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_LSHR
6941 { 134, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_SHL
6942 { 133, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ZEXT
6943 { 132, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #132 = G_SEXT_INREG
6944 { 131, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #131 = G_SEXT
6945 { 130, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #130 = G_VAARG
6946 { 129, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #129 = G_VASTART
6947 { 128, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #128 = G_FCONSTANT
6948 { 127, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #127 = G_CONSTANT
6949 { 126, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #126 = G_TRUNC
6950 { 125, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #125 = G_ANYEXT
6951 { 124, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
6952 { 123, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #123 = G_INTRINSIC_CONVERGENT
6953 { 122, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #122 = G_INTRINSIC_W_SIDE_EFFECTS
6954 { 121, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #121 = G_INTRINSIC
6955 { 120, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #120 = G_INVOKE_REGION_START
6956 { 119, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #119 = G_BRINDIRECT
6957 { 118, 2, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #118 = G_BRCOND
6958 { 117, 4, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #117 = G_PREFETCH
6959 { 116, 2, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #116 = G_FENCE
6960 { 115, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UDEC_WRAP
6961 { 114, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_UINC_WRAP
6962 { 113, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMIN
6963 { 112, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FMAX
6964 { 111, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FSUB
6965 { 110, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_FADD
6966 { 109, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMIN
6967 { 108, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_UMAX
6968 { 107, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MIN
6969 { 106, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_MAX
6970 { 105, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_XOR
6971 { 104, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_OR
6972 { 103, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_NAND
6973 { 102, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMICRMW_AND
6974 { 101, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMICRMW_SUB
6975 { 100, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_ATOMICRMW_ADD
6976 { 99, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_ATOMICRMW_XCHG
6977 { 98, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG
6978 { 97, 5, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #97 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
6979 { 96, 5, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #96 = G_INDEXED_STORE
6980 { 95, 2, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #95 = G_STORE
6981 { 94, 5, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_INDEXED_ZEXTLOAD
6982 { 93, 5, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_INDEXED_SEXTLOAD
6983 { 92, 5, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #92 = G_INDEXED_LOAD
6984 { 91, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #91 = G_ZEXTLOAD
6985 { 90, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #90 = G_SEXTLOAD
6986 { 89, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #89 = G_LOAD
6987 { 88, 1, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #88 = G_READSTEADYCOUNTER
6988 { 87, 1, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #87 = G_READCYCLECOUNTER
6989 { 86, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_ROUNDEVEN
6990 { 85, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_LLRINT
6991 { 84, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_INTRINSIC_LRINT
6992 { 83, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_INTRINSIC_ROUND
6993 { 82, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_INTRINSIC_TRUNC
6994 { 81, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_INTRINSIC_FPTRUNC_ROUND
6995 { 80, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_CONSTANT_FOLD_BARRIER
6996 { 79, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #79 = G_FREEZE
6997 { 78, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #78 = G_BITCAST
6998 { 77, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #77 = G_INTTOPTR
6999 { 76, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #76 = G_PTRTOINT
7000 { 75, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #75 = G_CONCAT_VECTORS
7001 { 74, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR_TRUNC
7002 { 73, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #73 = G_BUILD_VECTOR
7003 { 72, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #72 = G_MERGE_VALUES
7004 { 71, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_INSERT
7005 { 70, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #70 = G_UNMERGE_VALUES
7006 { 69, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_EXTRACT
7007 { 68, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #68 = G_CONSTANT_POOL
7008 { 67, 5, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_PTRAUTH_GLOBAL_VALUE
7009 { 66, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #66 = G_GLOBAL_VALUE
7010 { 65, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #65 = G_FRAME_INDEX
7011 { 64, 1, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #64 = G_PHI
7012 { 63, 1, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #63 = G_IMPLICIT_DEF
7013 { 62, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_XOR
7014 { 61, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #61 = G_OR
7015 { 60, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #60 = G_AND
7016 { 59, 4, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UDIVREM
7017 { 58, 4, 2, 0, 0, 0, 0, HexagonImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SDIVREM
7018 { 57, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UREM
7019 { 56, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SREM
7020 { 55, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #55 = G_UDIV
7021 { 54, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SDIV
7022 { 53, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_MUL
7023 { 52, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_SUB
7024 { 51, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #51 = G_ADD
7025 { 50, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_ALIGN
7026 { 49, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #49 = G_ASSERT_ZEXT
7027 { 48, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #48 = G_ASSERT_SEXT
7028 { 47, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_GLUE
7029 { 46, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_LOOP
7030 { 45, 1, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ANCHOR
7031 { 44, 1, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #44 = CONVERGENCECTRL_ENTRY
7032 { 43, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #43 = JUMP_TABLE_DEBUG_INFO
7033 { 42, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = MEMBARRIER
7034 { 41, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL
7035 { 40, 3, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
7036 { 39, 2, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL
7037 { 38, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL
7038 { 37, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT
7039 { 36, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_RET
7040 { 35, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER
7041 { 34, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = PATCHABLE_OP
7042 { 33, 1, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #33 = FAULTING_OP
7043 { 32, 2, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE
7044 { 31, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = STATEPOINT
7045 { 30, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG
7046 { 29, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP
7047 { 28, 1, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD
7048 { 27, 6, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = PATCHPOINT
7049 { 26, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = FENTRY_CALL
7050 { 25, 2, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #25 = STACKMAP
7051 { 24, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #24 = ARITH_FENCE
7052 { 23, 4, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #23 = PSEUDO_PROBE
7053 { 22, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_END
7054 { 21, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #21 = LIFETIME_START
7055 { 20, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #20 = BUNDLE
7056 { 19, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = COPY
7057 { 18, 2, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #18 = REG_SEQUENCE
7058 { 17, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #17 = DBG_LABEL
7059 { 16, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_PHI
7060 { 15, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_INSTR_REF
7061 { 14, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST
7062 { 13, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #13 = DBG_VALUE
7063 { 12, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS
7064 { 11, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = SUBREG_TO_REG
7065 { 10, 1, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
7066 { 9, 4, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG
7067 { 8, 3, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
7068 { 7, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL
7069 { 6, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
7070 { 5, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL
7071 { 4, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL
7072 { 3, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
7073 { 2, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR
7074 { 1, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM
7075 { 0, 1, 1, 0, 0, 0, 0, HexagonImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI
7076 }, {
7077 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7078 /* 1 */
7079 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7080 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7081 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7082 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7083 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7084 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7085 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
7086 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7087 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7088 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
7089 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7090 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7091 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7092 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7093 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7094 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7095 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7096 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7097 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7098 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7099 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7100 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7101 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7102 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7103 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7104 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7105 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7106 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7107 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7108 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7109 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7110 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7111 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7112 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7113 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7114 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7115 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7116 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7117 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7118 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
7119 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
7120 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7121 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7122 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7123 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7124 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7125 /* 152 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7126 /* 155 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7127 /* 157 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7128 /* 159 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7129 /* 162 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7130 /* 164 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7131 /* 167 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7132 /* 169 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7133 /* 172 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7134 /* 175 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7135 /* 178 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7136 /* 181 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7137 /* 183 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7138 /* 185 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7139 /* 187 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7140 /* 190 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7141 /* 192 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7142 /* 195 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7143 /* 196 */ { Hexagon::CtrRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7144 /* 199 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7145 /* 202 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7146 /* 205 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7147 /* 209 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7148 /* 212 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7149 /* 215 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7150 /* 219 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7151 /* 223 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7152 /* 229 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7153 /* 234 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7154 /* 240 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7155 /* 245 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7156 /* 249 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7157 /* 250 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7158 /* 256 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7159 /* 261 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7160 /* 267 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7161 /* 272 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7162 /* 273 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7163 /* 274 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7164 /* 277 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7165 /* 280 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7166 /* 283 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7167 /* 287 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7168 /* 289 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7169 /* 291 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7170 /* 294 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7171 /* 297 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7172 /* 300 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7173 /* 304 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7174 /* 307 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7175 /* 309 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7176 /* 314 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7177 /* 317 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::CtrRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7178 /* 320 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7179 /* 323 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7180 /* 326 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7181 /* 330 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7182 /* 332 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7183 /* 334 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7184 /* 337 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7185 /* 339 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7186 /* 342 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7187 /* 344 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7188 /* 347 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7189 /* 350 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7190 /* 354 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7191 /* 359 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7192 /* 361 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7193 /* 364 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7194 /* 367 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7195 /* 371 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7196 /* 375 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7197 /* 378 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7198 /* 382 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7199 /* 385 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7200 /* 389 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7201 /* 392 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7202 /* 396 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7203 /* 399 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7204 /* 401 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7205 /* 402 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7206 /* 406 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7207 /* 409 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7208 /* 413 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7209 /* 416 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7210 /* 420 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7211 /* 425 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7212 /* 431 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7213 /* 436 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7214 /* 442 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7215 /* 446 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7216 /* 449 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7217 /* 453 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7218 /* 456 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7219 /* 461 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7220 /* 465 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7221 /* 467 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7222 /* 471 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7223 /* 476 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7224 /* 480 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7225 /* 485 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7226 /* 490 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7227 /* 493 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7228 /* 495 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7229 /* 498 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7230 /* 501 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7231 /* 504 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7232 /* 507 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7233 /* 510 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7234 /* 513 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7235 /* 516 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7236 /* 519 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7237 /* 522 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7238 /* 526 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7239 /* 530 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::CtrRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7240 /* 532 */ { Hexagon::CtrRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7241 /* 534 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7242 /* 537 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
7243 /* 542 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::CtrRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7244 /* 544 */ { Hexagon::CtrRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7245 /* 546 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7246 /* 549 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7247 /* 552 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7248 /* 557 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7249 /* 560 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7250 /* 563 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7251 /* 567 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7252 /* 569 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7253 /* 573 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7254 /* 577 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7255 /* 579 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7256 /* 582 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7257 /* 586 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7258 /* 588 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7259 /* 590 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7260 /* 594 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7261 /* 599 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GuestRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7262 /* 601 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GuestRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7263 /* 603 */ { Hexagon::GuestRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7264 /* 605 */ { Hexagon::GuestRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7265 /* 607 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7266 /* 609 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7267 /* 612 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7268 /* 615 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7269 /* 617 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7270 /* 621 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7271 /* 626 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7272 /* 632 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7273 /* 637 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7274 /* 641 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7275 /* 646 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7276 /* 650 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7277 /* 654 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7278 /* 659 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7279 /* 663 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7280 /* 668 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7281 /* 672 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7282 /* 677 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7283 /* 681 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7284 /* 686 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7285 /* 690 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7286 /* 694 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7287 /* 698 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7288 /* 703 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7289 /* 706 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7290 /* 711 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7291 /* 714 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7292 /* 718 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7293 /* 722 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7294 /* 726 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7295 /* 730 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7296 /* 734 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7297 /* 738 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7298 /* 740 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7299 /* 744 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7300 /* 747 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7301 /* 751 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7302 /* 755 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7303 /* 760 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7304 /* 764 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7305 /* 769 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7306 /* 773 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7307 /* 778 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7308 /* 782 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7309 /* 787 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7310 /* 791 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7311 /* 795 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7312 /* 800 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7313 /* 804 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7314 /* 808 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7315 /* 812 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7316 /* 816 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7317 /* 820 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7318 /* 823 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7319 /* 828 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7320 /* 831 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7321 /* 836 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7322 /* 840 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7323 /* 844 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7324 /* 848 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7325 /* 852 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7326 /* 856 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7327 /* 861 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7328 /* 864 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7329 /* 867 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7330 /* 869 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7331 /* 870 */ { Hexagon::GeneralDoubleLow8RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7332 /* 872 */ { Hexagon::GeneralDoubleLow8RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7333 /* 874 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7334 /* 877 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::GeneralDoubleLow8RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7335 /* 879 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7336 /* 881 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7337 /* 884 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7338 /* 886 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7339 /* 888 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7340 /* 892 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7341 /* 896 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7342 /* 900 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7343 /* 905 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7344 /* 910 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7345 /* 914 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7346 /* 919 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7347 /* 924 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7348 /* 928 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7349 /* 932 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7350 /* 936 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7351 /* 941 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7352 /* 946 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7353 /* 949 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
7354 /* 954 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7355 /* 958 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7356 /* 962 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7357 /* 966 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7358 /* 970 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7359 /* 973 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7360 /* 976 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7361 /* 980 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7362 /* 983 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7363 /* 987 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7364 /* 990 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7365 /* 994 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7366 /* 997 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7367 /* 1001 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7368 /* 1004 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7369 /* 1007 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7370 /* 1012 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7371 /* 1017 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7372 /* 1022 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7373 /* 1027 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7374 /* 1031 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7375 /* 1035 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7376 /* 1037 */ { Hexagon::HvxVQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7377 /* 1040 */ { Hexagon::HvxVQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVQRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7378 /* 1044 */ { Hexagon::HvxVQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
7379 /* 1048 */ { Hexagon::HvxVQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVQRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
7380 /* 1053 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7381 /* 1057 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7382 /* 1059 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7383 /* 1063 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7384 /* 1067 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::SysRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7385 /* 1069 */ { Hexagon::SysRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7386 /* 1071 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7387 /* 1074 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::SysRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7388 /* 1076 */ { Hexagon::SysRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7389 /* 1078 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7390 }, {
7391 /* 0 */
7392 /* 0 */ Hexagon::R31, Hexagon::R30, Hexagon::R29, Hexagon::R29, Hexagon::R30,
7393 /* 5 */ Hexagon::R29, Hexagon::R29, Hexagon::R30, Hexagon::R31,
7394 /* 9 */ Hexagon::SA0, Hexagon::LC0, Hexagon::PC, Hexagon::LC0,
7395 /* 13 */ Hexagon::SA0, Hexagon::SA1, Hexagon::LC0, Hexagon::LC1, Hexagon::PC, Hexagon::LC0, Hexagon::LC1,
7396 /* 20 */ Hexagon::SA1, Hexagon::LC1, Hexagon::PC, Hexagon::LC1,
7397 /* 24 */ Hexagon::LC0, Hexagon::SA0, Hexagon::LC0, Hexagon::P3, Hexagon::PC, Hexagon::USR,
7398 /* 30 */ Hexagon::LC0, Hexagon::LC1, Hexagon::SA0, Hexagon::SA1, Hexagon::LC0, Hexagon::LC1, Hexagon::P3, Hexagon::PC, Hexagon::USR,
7399 /* 39 */ Hexagon::LC1, Hexagon::SA1, Hexagon::LC1, Hexagon::PC,
7400 /* 43 */ Hexagon::R30,
7401 /* 44 */ Hexagon::R29,
7402 /* 45 */ Hexagon::R0, Hexagon::R14, Hexagon::R15, Hexagon::R28, Hexagon::R29, Hexagon::R30, Hexagon::R31, Hexagon::PC,
7403 /* 53 */ Hexagon::CS, Hexagon::CS,
7404 /* 55 */ Hexagon::PC,
7405 /* 56 */ Hexagon::FRAMEKEY, Hexagon::R29,
7406 /* 58 */ Hexagon::FRAMEKEY, Hexagon::FRAMELIMIT, Hexagon::R30, Hexagon::R31, Hexagon::R30,
7407 /* 63 */ Hexagon::USR_OVF,
7408 /* 64 */ Hexagon::R16,
7409 /* 65 */ Hexagon::R28, Hexagon::PC,
7410 /* 67 */ Hexagon::USR,
7411 /* 68 */ Hexagon::R29, Hexagon::PC, Hexagon::R31,
7412 /* 71 */ Hexagon::PC, Hexagon::R31,
7413 /* 73 */ Hexagon::LC0, Hexagon::SA0, Hexagon::USR,
7414 /* 76 */ Hexagon::SA0, Hexagon::LC0, Hexagon::USR,
7415 /* 79 */ Hexagon::SA1, Hexagon::LC1,
7416 /* 81 */ Hexagon::LC1, Hexagon::SA1,
7417 /* 83 */ Hexagon::LC0, Hexagon::P3, Hexagon::SA0, Hexagon::USR,
7418 /* 87 */ Hexagon::ELR, Hexagon::PC,
7419 /* 89 */ Hexagon::CCR, Hexagon::GOSP, Hexagon::CCR, Hexagon::GOSP, Hexagon::PC,
7420 /* 94 */ Hexagon::P0, Hexagon::P0, Hexagon::PC,
7421 /* 97 */ Hexagon::P1, Hexagon::P1, Hexagon::PC,
7422 /* 100 */ Hexagon::CS,
7423 /* 101 */ Hexagon::GP,
7424 /* 102 */ Hexagon::FRAMEKEY, Hexagon::PC, Hexagon::R29,
7425 /* 105 */ Hexagon::PC, Hexagon::R31, Hexagon::R6, Hexagon::R7, Hexagon::P0,
7426 /* 110 */ Hexagon::R29, Hexagon::R30, Hexagon::R31, Hexagon::PC,
7427 /* 114 */ Hexagon::R14, Hexagon::R15, Hexagon::R28, Hexagon::R29, Hexagon::R30, Hexagon::R31, Hexagon::PC,
7428 /* 121 */ Hexagon::P0,
7429 /* 122 */ Hexagon::R29, Hexagon::R31,
7430 /* 124 */ Hexagon::R29, Hexagon::R31, Hexagon::P0,
7431 /* 127 */ Hexagon::R29, Hexagon::R31, Hexagon::R14, Hexagon::R15, Hexagon::R28, Hexagon::P0,
7432 /* 133 */ Hexagon::R29, Hexagon::R31, Hexagon::R14, Hexagon::R15, Hexagon::R28,
7433 /* 138 */ Hexagon::FRAMEKEY, Hexagon::R30, Hexagon::R29, Hexagon::R30, Hexagon::R31,
7434 /* 143 */ Hexagon::R31, Hexagon::PC,
7435 /* 145 */ Hexagon::P0, Hexagon::R31, Hexagon::PC,
7436 /* 148 */ Hexagon::FRAMEKEY, Hexagon::R30, Hexagon::PC, Hexagon::R29, Hexagon::R30, Hexagon::R31,
7437 /* 154 */ Hexagon::FRAMEKEY, Hexagon::P0, Hexagon::R30, Hexagon::PC, Hexagon::R29, Hexagon::R30, Hexagon::R31,
7438 /* 161 */ Hexagon::FRAMEKEY, Hexagon::FRAMELIMIT, Hexagon::R29, Hexagon::R30, Hexagon::R31, Hexagon::R29, Hexagon::R30,
7439 /* 168 */ Hexagon::VTMP,
7440 /* 169 */ Hexagon::SGP0, Hexagon::SGP0,
7441 /* 171 */ Hexagon::SGP1, Hexagon::SGP1,
7442 /* 173 */ Hexagon::SGP0, Hexagon::SGP1, Hexagon::SGP0, Hexagon::SGP1,
7443 }
7444};
7445
7446
7447#ifdef __GNUC__
7448#pragma GCC diagnostic push
7449#pragma GCC diagnostic ignored "-Woverlength-strings"
7450#endif
7451extern const char HexagonInstrNameData[] = {
7452 /* 0 */ "G_FLOG10\0"
7453 /* 9 */ "G_FEXP10\0"
7454 /* 18 */ "Y4_crswap10\0"
7455 /* 30 */ "V6_v6mpyhubs10\0"
7456 /* 45 */ "V6_v6mpyvubs10\0"
7457 /* 60 */ "V6_v10mpyubs10\0"
7458 /* 75 */ "ENDLOOP0\0"
7459 /* 84 */ "V6_vdd0\0"
7460 /* 92 */ "PS_vdd0\0"
7461 /* 100 */ "V6_ld0\0"
7462 /* 107 */ "V6_dbl_ld0\0"
7463 /* 118 */ "V6_zld0\0"
7464 /* 126 */ "V6_vd0\0"
7465 /* 133 */ "Y6_diag0\0"
7466 /* 142 */ "SS2_storebi0\0"
7467 /* 155 */ "SS2_storewi0\0"
7468 /* 168 */ "S2_cl0\0"
7469 /* 175 */ "V6_stn0\0"
7470 /* 183 */ "J2_trap0\0"
7471 /* 192 */ "Y2_crswap0\0"
7472 /* 203 */ "V6_ldcp0\0"
7473 /* 212 */ "V6_ldp0\0"
7474 /* 220 */ "V6_zldp0\0"
7475 /* 229 */ "V6_ldcnp0\0"
7476 /* 239 */ "V6_ldnp0\0"
7477 /* 248 */ "V6_ldtnp0\0"
7478 /* 258 */ "V6_stnp0\0"
7479 /* 267 */ "V6_stunp0\0"
7480 /* 277 */ "J2_endloop0\0"
7481 /* 289 */ "V6_ldtp0\0"
7482 /* 298 */ "V6_stp0\0"
7483 /* 306 */ "V6_stup0\0"
7484 /* 315 */ "V6_stnq0\0"
7485 /* 324 */ "V6_stq0\0"
7486 /* 332 */ "M2_vrmac_s0\0"
7487 /* 344 */ "M2_dpmpyss_nac_s0\0"
7488 /* 362 */ "M2_dpmpyuu_nac_s0\0"
7489 /* 380 */ "M4_vrmpyeh_acc_s0\0"
7490 /* 398 */ "M4_vrmpyoh_acc_s0\0"
7491 /* 416 */ "M2_dpmpyss_acc_s0\0"
7492 /* 434 */ "M2_dpmpyuu_acc_s0\0"
7493 /* 452 */ "M2_cmacsc_s0\0"
7494 /* 465 */ "M2_cnacsc_s0\0"
7495 /* 478 */ "M2_cmpyrsc_s0\0"
7496 /* 492 */ "M2_cmpysc_s0\0"
7497 /* 505 */ "M2_dpmpyss_rnd_s0\0"
7498 /* 523 */ "M4_vrmpyeh_s0\0"
7499 /* 537 */ "M2_mpyud_nac_hh_s0\0"
7500 /* 556 */ "M2_mpyd_nac_hh_s0\0"
7501 /* 574 */ "M2_mpyu_nac_hh_s0\0"
7502 /* 592 */ "M2_mpy_nac_hh_s0\0"
7503 /* 609 */ "M2_mpyud_acc_hh_s0\0"
7504 /* 628 */ "M2_mpyd_acc_hh_s0\0"
7505 /* 646 */ "M2_mpyu_acc_hh_s0\0"
7506 /* 664 */ "M2_mpy_acc_hh_s0\0"
7507 /* 681 */ "M2_mpyd_rnd_hh_s0\0"
7508 /* 699 */ "M2_mpy_sat_rnd_hh_s0\0"
7509 /* 720 */ "M2_mpy_rnd_hh_s0\0"
7510 /* 737 */ "M2_mpyud_hh_s0\0"
7511 /* 752 */ "M2_mpyd_hh_s0\0"
7512 /* 766 */ "M2_mpy_nac_sat_hh_s0\0"
7513 /* 787 */ "M2_mpy_acc_sat_hh_s0\0"
7514 /* 808 */ "M2_mpy_sat_hh_s0\0"
7515 /* 825 */ "M2_mpyu_hh_s0\0"
7516 /* 839 */ "M2_mpy_hh_s0\0"
7517 /* 852 */ "M2_mpyud_nac_lh_s0\0"
7518 /* 871 */ "M2_mpyd_nac_lh_s0\0"
7519 /* 889 */ "M2_mpyu_nac_lh_s0\0"
7520 /* 907 */ "M2_mpy_nac_lh_s0\0"
7521 /* 924 */ "M2_mpyud_acc_lh_s0\0"
7522 /* 943 */ "M2_mpyd_acc_lh_s0\0"
7523 /* 961 */ "M2_mpyu_acc_lh_s0\0"
7524 /* 979 */ "M2_mpy_acc_lh_s0\0"
7525 /* 996 */ "M2_mpyd_rnd_lh_s0\0"
7526 /* 1014 */ "M2_mpy_sat_rnd_lh_s0\0"
7527 /* 1035 */ "M2_mpy_rnd_lh_s0\0"
7528 /* 1052 */ "M2_mpyud_lh_s0\0"
7529 /* 1067 */ "M2_mpyd_lh_s0\0"
7530 /* 1081 */ "M2_mpy_nac_sat_lh_s0\0"
7531 /* 1102 */ "M2_mpy_acc_sat_lh_s0\0"
7532 /* 1123 */ "M2_mpy_sat_lh_s0\0"
7533 /* 1140 */ "M2_mpyu_lh_s0\0"
7534 /* 1154 */ "M2_mpy_lh_s0\0"
7535 /* 1167 */ "M4_vrmpyoh_s0\0"
7536 /* 1181 */ "M2_mmpyuh_s0\0"
7537 /* 1194 */ "M2_mmpyh_s0\0"
7538 /* 1206 */ "M2_cmaci_s0\0"
7539 /* 1218 */ "M2_vrcmaci_s0\0"
7540 /* 1232 */ "M2_cmpyi_s0\0"
7541 /* 1244 */ "M2_vrcmpyi_s0\0"
7542 /* 1258 */ "M2_mpyud_nac_hl_s0\0"
7543 /* 1277 */ "M2_mpyd_nac_hl_s0\0"
7544 /* 1295 */ "M2_mpyu_nac_hl_s0\0"
7545 /* 1313 */ "M2_mpy_nac_hl_s0\0"
7546 /* 1330 */ "M2_mpyud_acc_hl_s0\0"
7547 /* 1349 */ "M2_mpyd_acc_hl_s0\0"
7548 /* 1367 */ "M2_mpyu_acc_hl_s0\0"
7549 /* 1385 */ "M2_mpy_acc_hl_s0\0"
7550 /* 1402 */ "M2_mpyd_rnd_hl_s0\0"
7551 /* 1420 */ "M2_mpy_sat_rnd_hl_s0\0"
7552 /* 1441 */ "M2_mpy_rnd_hl_s0\0"
7553 /* 1458 */ "M2_mpyud_hl_s0\0"
7554 /* 1473 */ "M2_mpyd_hl_s0\0"
7555 /* 1487 */ "M2_mpy_nac_sat_hl_s0\0"
7556 /* 1508 */ "M2_mpy_acc_sat_hl_s0\0"
7557 /* 1529 */ "M2_mpy_sat_hl_s0\0"
7558 /* 1546 */ "M2_mpyu_hl_s0\0"
7559 /* 1560 */ "M2_mpy_hl_s0\0"
7560 /* 1573 */ "M2_mpyud_nac_ll_s0\0"
7561 /* 1592 */ "M2_mpyd_nac_ll_s0\0"
7562 /* 1610 */ "M2_mpyu_nac_ll_s0\0"
7563 /* 1628 */ "M2_mpy_nac_ll_s0\0"
7564 /* 1645 */ "M2_mpyud_acc_ll_s0\0"
7565 /* 1664 */ "M2_mpyd_acc_ll_s0\0"
7566 /* 1682 */ "M2_mpyu_acc_ll_s0\0"
7567 /* 1700 */ "M2_mpy_acc_ll_s0\0"
7568 /* 1717 */ "M2_mpyd_rnd_ll_s0\0"
7569 /* 1735 */ "M2_mpy_sat_rnd_ll_s0\0"
7570 /* 1756 */ "M2_mpy_rnd_ll_s0\0"
7571 /* 1773 */ "M2_mpyud_ll_s0\0"
7572 /* 1788 */ "M2_mpyd_ll_s0\0"
7573 /* 1802 */ "M2_mpy_nac_sat_ll_s0\0"
7574 /* 1823 */ "M2_mpy_acc_sat_ll_s0\0"
7575 /* 1844 */ "M2_mpy_sat_ll_s0\0"
7576 /* 1861 */ "M2_mpyu_ll_s0\0"
7577 /* 1875 */ "M2_mpy_ll_s0\0"
7578 /* 1888 */ "M2_mmpyul_s0\0"
7579 /* 1901 */ "M2_mmpyl_s0\0"
7580 /* 1913 */ "M2_cmacr_s0\0"
7581 /* 1925 */ "M2_vrcmacr_s0\0"
7582 /* 1939 */ "M2_cmpyr_s0\0"
7583 /* 1951 */ "M2_vrcmpyr_s0\0"
7584 /* 1965 */ "M2_vmac2s_s0\0"
7585 /* 1978 */ "M2_vmpy2s_s0\0"
7586 /* 1991 */ "M2_cmacs_s0\0"
7587 /* 2003 */ "M2_vdmacs_s0\0"
7588 /* 2016 */ "M2_cnacs_s0\0"
7589 /* 2028 */ "M2_vmac2es_s0\0"
7590 /* 2042 */ "M2_vmpy2es_s0\0"
7591 /* 2056 */ "M2_mmachs_s0\0"
7592 /* 2069 */ "M2_mmacuhs_s0\0"
7593 /* 2083 */ "M2_mmacls_s0\0"
7594 /* 2096 */ "M2_mmaculs_s0\0"
7595 /* 2110 */ "M2_cmpyrs_s0\0"
7596 /* 2123 */ "M2_vdmpyrs_s0\0"
7597 /* 2137 */ "M2_dpmpyss_s0\0"
7598 /* 2151 */ "M2_cmpys_s0\0"
7599 /* 2163 */ "M2_vdmpys_s0\0"
7600 /* 2176 */ "M2_vmac2su_s0\0"
7601 /* 2190 */ "M2_vmpy2su_s0\0"
7602 /* 2204 */ "M2_dpmpyuu_s0\0"
7603 /* 2218 */ "M2_vrmpy_s0\0"
7604 /* 2230 */ "M2_mmpyuh_rs0\0"
7605 /* 2244 */ "M2_mmpyh_rs0\0"
7606 /* 2257 */ "M2_mmpyul_rs0\0"
7607 /* 2271 */ "M2_mmpyl_rs0\0"
7608 /* 2284 */ "M2_mmachs_rs0\0"
7609 /* 2298 */ "M2_mmacuhs_rs0\0"
7610 /* 2313 */ "M2_mmacls_rs0\0"
7611 /* 2327 */ "M2_mmaculs_rs0\0"
7612 /* 2342 */ "DuplexIClass0\0"
7613 /* 2356 */ "S2_ct0\0"
7614 /* 2363 */ "V6_ldnt0\0"
7615 /* 2372 */ "V6_stnnt0\0"
7616 /* 2382 */ "V6_ldcpnt0\0"
7617 /* 2393 */ "V6_ldpnt0\0"
7618 /* 2403 */ "V6_ldcnpnt0\0"
7619 /* 2415 */ "V6_ldnpnt0\0"
7620 /* 2426 */ "V6_ldtnpnt0\0"
7621 /* 2438 */ "V6_stnpnt0\0"
7622 /* 2449 */ "V6_ldtpnt0\0"
7623 /* 2460 */ "V6_stpnt0\0"
7624 /* 2470 */ "V6_stnqnt0\0"
7625 /* 2481 */ "V6_stqnt0\0"
7626 /* 2491 */ "V6_stnt0\0"
7627 /* 2500 */ "V6_st0\0"
7628 /* 2507 */ "V6_dbl_st0\0"
7629 /* 2518 */ "V6_ldu0\0"
7630 /* 2526 */ "V6_stu0\0"
7631 /* 2534 */ "ENDLOOP01\0"
7632 /* 2544 */ "J2_endloop01\0"
7633 /* 2557 */ "SL2_jumpr31\0"
7634 /* 2569 */ "ENDLOOP1\0"
7635 /* 2578 */ "SA1_and1\0"
7636 /* 2587 */ "Y6_diag1\0"
7637 /* 2596 */ "SS2_storebi1\0"
7638 /* 2609 */ "SS2_storewi1\0"
7639 /* 2622 */ "S2_cl1\0"
7640 /* 2629 */ "SA1_setin1\0"
7641 /* 2640 */ "J2_trap1\0"
7642 /* 2649 */ "PS_trap1\0"
7643 /* 2658 */ "Y4_crswap1\0"
7644 /* 2669 */ "J2_endloop1\0"
7645 /* 2681 */ "M4_vrmpyeh_acc_s1\0"
7646 /* 2699 */ "M4_vrmpyoh_acc_s1\0"
7647 /* 2717 */ "M2_vrcmpys_acc_s1\0"
7648 /* 2735 */ "M2_cmacsc_s1\0"
7649 /* 2748 */ "M2_cnacsc_s1\0"
7650 /* 2761 */ "M2_cmpyrsc_s1\0"
7651 /* 2775 */ "M2_cmpysc_s1\0"
7652 /* 2788 */ "M4_vrmpyeh_s1\0"
7653 /* 2802 */ "M2_mpyud_nac_hh_s1\0"
7654 /* 2821 */ "M2_mpyd_nac_hh_s1\0"
7655 /* 2839 */ "M2_mpyu_nac_hh_s1\0"
7656 /* 2857 */ "M2_mpy_nac_hh_s1\0"
7657 /* 2874 */ "M2_mpyud_acc_hh_s1\0"
7658 /* 2893 */ "M2_mpyd_acc_hh_s1\0"
7659 /* 2911 */ "M2_mpyu_acc_hh_s1\0"
7660 /* 2929 */ "M2_mpy_acc_hh_s1\0"
7661 /* 2946 */ "M2_mpyd_rnd_hh_s1\0"
7662 /* 2964 */ "M2_mpy_sat_rnd_hh_s1\0"
7663 /* 2985 */ "M2_mpy_rnd_hh_s1\0"
7664 /* 3002 */ "M2_mpyud_hh_s1\0"
7665 /* 3017 */ "M2_mpyd_hh_s1\0"
7666 /* 3031 */ "M2_mpy_nac_sat_hh_s1\0"
7667 /* 3052 */ "M2_mpy_acc_sat_hh_s1\0"
7668 /* 3073 */ "M2_mpy_sat_hh_s1\0"
7669 /* 3090 */ "M2_mpyu_hh_s1\0"
7670 /* 3104 */ "M2_mpy_hh_s1\0"
7671 /* 3117 */ "M2_mpyud_nac_lh_s1\0"
7672 /* 3136 */ "M2_mpyd_nac_lh_s1\0"
7673 /* 3154 */ "M2_mpyu_nac_lh_s1\0"
7674 /* 3172 */ "M2_mpy_nac_lh_s1\0"
7675 /* 3189 */ "M2_mpyud_acc_lh_s1\0"
7676 /* 3208 */ "M2_mpyd_acc_lh_s1\0"
7677 /* 3226 */ "M2_mpyu_acc_lh_s1\0"
7678 /* 3244 */ "M2_mpy_acc_lh_s1\0"
7679 /* 3261 */ "M2_mpyd_rnd_lh_s1\0"
7680 /* 3279 */ "M2_mpy_sat_rnd_lh_s1\0"
7681 /* 3300 */ "M2_mpy_rnd_lh_s1\0"
7682 /* 3317 */ "M2_mpyud_lh_s1\0"
7683 /* 3332 */ "M2_mpyd_lh_s1\0"
7684 /* 3346 */ "M2_mpy_nac_sat_lh_s1\0"
7685 /* 3367 */ "M2_mpy_acc_sat_lh_s1\0"
7686 /* 3388 */ "M2_mpy_sat_lh_s1\0"
7687 /* 3405 */ "M2_mpyu_lh_s1\0"
7688 /* 3419 */ "M2_mpy_lh_s1\0"
7689 /* 3432 */ "M4_vrmpyoh_s1\0"
7690 /* 3446 */ "M2_mmpyuh_s1\0"
7691 /* 3459 */ "M2_mmpyh_s1\0"
7692 /* 3471 */ "M2_hmmpyh_s1\0"
7693 /* 3484 */ "M2_mpyud_nac_hl_s1\0"
7694 /* 3503 */ "M2_mpyd_nac_hl_s1\0"
7695 /* 3521 */ "M2_mpyu_nac_hl_s1\0"
7696 /* 3539 */ "M2_mpy_nac_hl_s1\0"
7697 /* 3556 */ "M2_mpyud_acc_hl_s1\0"
7698 /* 3575 */ "M2_mpyd_acc_hl_s1\0"
7699 /* 3593 */ "M2_mpyu_acc_hl_s1\0"
7700 /* 3611 */ "M2_mpy_acc_hl_s1\0"
7701 /* 3628 */ "M2_mpyd_rnd_hl_s1\0"
7702 /* 3646 */ "M2_mpy_sat_rnd_hl_s1\0"
7703 /* 3667 */ "M2_mpy_rnd_hl_s1\0"
7704 /* 3684 */ "M2_mpyud_hl_s1\0"
7705 /* 3699 */ "M2_mpyd_hl_s1\0"
7706 /* 3713 */ "M2_mpy_nac_sat_hl_s1\0"
7707 /* 3734 */ "M2_mpy_acc_sat_hl_s1\0"
7708 /* 3755 */ "M2_mpy_sat_hl_s1\0"
7709 /* 3772 */ "M2_mpyu_hl_s1\0"
7710 /* 3786 */ "M2_mpy_hl_s1\0"
7711 /* 3799 */ "M2_mpyud_nac_ll_s1\0"
7712 /* 3818 */ "M2_mpyd_nac_ll_s1\0"
7713 /* 3836 */ "M2_mpyu_nac_ll_s1\0"
7714 /* 3854 */ "M2_mpy_nac_ll_s1\0"
7715 /* 3871 */ "M2_mpyud_acc_ll_s1\0"
7716 /* 3890 */ "M2_mpyd_acc_ll_s1\0"
7717 /* 3908 */ "M2_mpyu_acc_ll_s1\0"
7718 /* 3926 */ "M2_mpy_acc_ll_s1\0"
7719 /* 3943 */ "M2_mpyd_rnd_ll_s1\0"
7720 /* 3961 */ "M2_mpy_sat_rnd_ll_s1\0"
7721 /* 3982 */ "M2_mpy_rnd_ll_s1\0"
7722 /* 3999 */ "M2_mpyud_ll_s1\0"
7723 /* 4014 */ "M2_mpyd_ll_s1\0"
7724 /* 4028 */ "M2_mpy_nac_sat_ll_s1\0"
7725 /* 4049 */ "M2_mpy_acc_sat_ll_s1\0"
7726 /* 4070 */ "M2_mpy_sat_ll_s1\0"
7727 /* 4087 */ "M2_mpyu_ll_s1\0"
7728 /* 4101 */ "M2_mpy_ll_s1\0"
7729 /* 4114 */ "M2_mmpyul_s1\0"
7730 /* 4127 */ "M2_mmpyl_s1\0"
7731 /* 4139 */ "M2_hmmpyl_s1\0"
7732 /* 4152 */ "M2_mpy_up_s1\0"
7733 /* 4165 */ "M2_vmac2s_s1\0"
7734 /* 4178 */ "M2_vmpy2s_s1\0"
7735 /* 4191 */ "M2_cmacs_s1\0"
7736 /* 4203 */ "M2_vdmacs_s1\0"
7737 /* 4216 */ "M2_cnacs_s1\0"
7738 /* 4228 */ "M2_vmac2es_s1\0"
7739 /* 4242 */ "M2_vmpy2es_s1\0"
7740 /* 4256 */ "M2_mmachs_s1\0"
7741 /* 4269 */ "M2_mmacuhs_s1\0"
7742 /* 4283 */ "M2_mmacls_s1\0"
7743 /* 4296 */ "M2_mmaculs_s1\0"
7744 /* 4310 */ "M2_cmpyrs_s1\0"
7745 /* 4323 */ "M2_vdmpyrs_s1\0"
7746 /* 4337 */ "M2_cmpys_s1\0"
7747 /* 4349 */ "M2_vrcmpys_s1\0"
7748 /* 4363 */ "M2_vdmpys_s1\0"
7749 /* 4376 */ "M2_vmac2su_s1\0"
7750 /* 4390 */ "M2_vmpy2su_s1\0"
7751 /* 4404 */ "M2_mmpyuh_rs1\0"
7752 /* 4418 */ "M2_mmpyh_rs1\0"
7753 /* 4431 */ "M2_hmmpyh_rs1\0"
7754 /* 4445 */ "M2_mmpyul_rs1\0"
7755 /* 4459 */ "M2_mmpyl_rs1\0"
7756 /* 4472 */ "M2_hmmpyl_rs1\0"
7757 /* 4486 */ "M2_mmachs_rs1\0"
7758 /* 4500 */ "M2_mmacuhs_rs1\0"
7759 /* 4515 */ "M2_mmacls_rs1\0"
7760 /* 4529 */ "M2_mmaculs_rs1\0"
7761 /* 4544 */ "DuplexIClass1\0"
7762 /* 4558 */ "S2_ct1\0"
7763 /* 4565 */ "CONST32\0"
7764 /* 4573 */ "V6_vsub_qf32\0"
7765 /* 4586 */ "V6_vadd_qf32\0"
7766 /* 4599 */ "V6_vconv_hf_qf32\0"
7767 /* 4616 */ "V6_vconv_sf_qf32\0"
7768 /* 4633 */ "V6_vmpy_qf32\0"
7769 /* 4646 */ "G_FLOG2\0"
7770 /* 4654 */ "G_FEXP2\0"
7771 /* 4662 */ "M2_vmac2\0"
7772 /* 4671 */ "V6_pred_scalar2\0"
7773 /* 4687 */ "DuplexIClass2\0"
7774 /* 4701 */ "M4_mpyri_addr_u2\0"
7775 /* 4718 */ "V6_pred_scalar2v2\0"
7776 /* 4736 */ "DuplexIClass3\0"
7777 /* 4750 */ "CONST64\0"
7778 /* 4758 */ "V6_vmpyewuh_64\0"
7779 /* 4773 */ "TFRI64_V4\0"
7780 /* 4783 */ "RESTORE_DEALLOC_BEFORE_TAILCALL_V4\0"
7781 /* 4818 */ "SAVE_REGISTERS_CALL_V4\0"
7782 /* 4841 */ "RESTORE_DEALLOC_RET_JMP_V4\0"
7783 /* 4868 */ "DuplexIClass4\0"
7784 /* 4882 */ "V6_vlut4\0"
7785 /* 4891 */ "DuplexIClass5\0"
7786 /* 4905 */ "V6_vmpy_qf32_qf16\0"
7787 /* 4923 */ "V6_vsub_qf16\0"
7788 /* 4936 */ "V6_vadd_qf16\0"
7789 /* 4949 */ "V6_vconv_hf_qf16\0"
7790 /* 4966 */ "V6_vmpy_qf16\0"
7791 /* 4979 */ "V6_vwhist256\0"
7792 /* 4992 */ "DuplexIClass6\0"
7793 /* 5006 */ "DuplexIClass7\0"
7794 /* 5020 */ "V6_vwhist128\0"
7795 /* 5033 */ "C2_all8\0"
7796 /* 5041 */ "DuplexIClass8\0"
7797 /* 5055 */ "C2_any8\0"
7798 /* 5063 */ "C4_fastcorner9\0"
7799 /* 5078 */ "DuplexIClass9\0"
7800 /* 5092 */ "G_FMA\0"
7801 /* 5098 */ "G_STRICT_FMA\0"
7802 /* 5111 */ "DuplexIClassA\0"
7803 /* 5125 */ "G_FSUB\0"
7804 /* 5132 */ "G_STRICT_FSUB\0"
7805 /* 5146 */ "G_ATOMICRMW_FSUB\0"
7806 /* 5163 */ "G_SUB\0"
7807 /* 5169 */ "G_ATOMICRMW_SUB\0"
7808 /* 5185 */ "DuplexIClassB\0"
7809 /* 5199 */ "RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC\0"
7810 /* 5238 */ "SAVE_REGISTERS_CALL_V4_PIC\0"
7811 /* 5265 */ "RESTORE_DEALLOC_RET_JMP_V4_PIC\0"
7812 /* 5296 */ "SAVE_REGISTERS_CALL_V4STK_PIC\0"
7813 /* 5326 */ "RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC\0"
7814 /* 5369 */ "SAVE_REGISTERS_CALL_V4_EXT_PIC\0"
7815 /* 5400 */ "RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC\0"
7816 /* 5435 */ "SAVE_REGISTERS_CALL_V4STK_EXT_PIC\0"
7817 /* 5469 */ "G_INTRINSIC\0"
7818 /* 5481 */ "G_FPTRUNC\0"
7819 /* 5491 */ "G_INTRINSIC_TRUNC\0"
7820 /* 5509 */ "G_TRUNC\0"
7821 /* 5517 */ "G_BUILD_VECTOR_TRUNC\0"
7822 /* 5538 */ "G_DYN_STACKALLOC\0"
7823 /* 5555 */ "DuplexIClassC\0"
7824 /* 5569 */ "G_FMAD\0"
7825 /* 5576 */ "G_INDEXED_SEXTLOAD\0"
7826 /* 5595 */ "G_SEXTLOAD\0"
7827 /* 5606 */ "G_INDEXED_ZEXTLOAD\0"
7828 /* 5625 */ "G_ZEXTLOAD\0"
7829 /* 5636 */ "G_INDEXED_LOAD\0"
7830 /* 5651 */ "G_LOAD\0"
7831 /* 5658 */ "G_VECREDUCE_FADD\0"
7832 /* 5675 */ "G_FADD\0"
7833 /* 5682 */ "G_VECREDUCE_SEQ_FADD\0"
7834 /* 5703 */ "G_STRICT_FADD\0"
7835 /* 5717 */ "G_ATOMICRMW_FADD\0"
7836 /* 5734 */ "G_VECREDUCE_ADD\0"
7837 /* 5750 */ "G_ADD\0"
7838 /* 5756 */ "G_PTR_ADD\0"
7839 /* 5766 */ "G_ATOMICRMW_ADD\0"
7840 /* 5782 */ "G_ATOMICRMW_NAND\0"
7841 /* 5799 */ "G_VECREDUCE_AND\0"
7842 /* 5815 */ "G_AND\0"
7843 /* 5821 */ "G_ATOMICRMW_AND\0"
7844 /* 5837 */ "LIFETIME_END\0"
7845 /* 5850 */ "G_BRCOND\0"
7846 /* 5859 */ "G_LLROUND\0"
7847 /* 5869 */ "G_LROUND\0"
7848 /* 5878 */ "G_INTRINSIC_ROUND\0"
7849 /* 5896 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
7850 /* 5922 */ "LOAD_STACK_GUARD\0"
7851 /* 5939 */ "DuplexIClassD\0"
7852 /* 5953 */ "PSEUDO_PROBE\0"
7853 /* 5966 */ "G_SSUBE\0"
7854 /* 5974 */ "G_USUBE\0"
7855 /* 5982 */ "G_FENCE\0"
7856 /* 5990 */ "ARITH_FENCE\0"
7857 /* 6002 */ "REG_SEQUENCE\0"
7858 /* 6015 */ "G_SADDE\0"
7859 /* 6023 */ "G_UADDE\0"
7860 /* 6031 */ "G_GET_FPMODE\0"
7861 /* 6044 */ "G_RESET_FPMODE\0"
7862 /* 6059 */ "G_SET_FPMODE\0"
7863 /* 6072 */ "G_FMINNUM_IEEE\0"
7864 /* 6087 */ "G_FMAXNUM_IEEE\0"
7865 /* 6102 */ "G_VSCALE\0"
7866 /* 6111 */ "G_JUMP_TABLE\0"
7867 /* 6124 */ "BUNDLE\0"
7868 /* 6131 */ "G_MEMCPY_INLINE\0"
7869 /* 6147 */ "LOCAL_ESCAPE\0"
7870 /* 6160 */ "G_STACKRESTORE\0"
7871 /* 6175 */ "G_INDEXED_STORE\0"
7872 /* 6191 */ "G_STORE\0"
7873 /* 6199 */ "G_BITREVERSE\0"
7874 /* 6212 */ "DBG_VALUE\0"
7875 /* 6222 */ "G_GLOBAL_VALUE\0"
7876 /* 6237 */ "G_PTRAUTH_GLOBAL_VALUE\0"
7877 /* 6260 */ "CONVERGENCECTRL_GLUE\0"
7878 /* 6281 */ "G_STACKSAVE\0"
7879 /* 6293 */ "G_MEMMOVE\0"
7880 /* 6303 */ "G_FREEZE\0"
7881 /* 6312 */ "G_FCANONICALIZE\0"
7882 /* 6328 */ "DuplexIClassE\0"
7883 /* 6342 */ "G_CTLZ_ZERO_UNDEF\0"
7884 /* 6360 */ "G_CTTZ_ZERO_UNDEF\0"
7885 /* 6378 */ "G_IMPLICIT_DEF\0"
7886 /* 6393 */ "DBG_INSTR_REF\0"
7887 /* 6407 */ "DuplexIClassF\0"
7888 /* 6421 */ "G_FNEG\0"
7889 /* 6428 */ "EXTRACT_SUBREG\0"
7890 /* 6443 */ "INSERT_SUBREG\0"
7891 /* 6457 */ "G_SEXT_INREG\0"
7892 /* 6470 */ "SUBREG_TO_REG\0"
7893 /* 6484 */ "G_ATOMIC_CMPXCHG\0"
7894 /* 6501 */ "G_ATOMICRMW_XCHG\0"
7895 /* 6518 */ "G_FLOG\0"
7896 /* 6525 */ "G_VAARG\0"
7897 /* 6533 */ "PREALLOCATED_ARG\0"
7898 /* 6550 */ "G_PREFETCH\0"
7899 /* 6561 */ "G_SMULH\0"
7900 /* 6569 */ "G_UMULH\0"
7901 /* 6577 */ "G_FTANH\0"
7902 /* 6585 */ "G_FSINH\0"
7903 /* 6593 */ "G_FCOSH\0"
7904 /* 6601 */ "DBG_PHI\0"
7905 /* 6609 */ "G_FPTOSI\0"
7906 /* 6618 */ "G_FPTOUI\0"
7907 /* 6627 */ "G_FPOWI\0"
7908 /* 6635 */ "G_PTRMASK\0"
7909 /* 6645 */ "SAVE_REGISTERS_CALL_V4STK\0"
7910 /* 6671 */ "GC_LABEL\0"
7911 /* 6680 */ "DBG_LABEL\0"
7912 /* 6690 */ "EH_LABEL\0"
7913 /* 6699 */ "ANNOTATION_LABEL\0"
7914 /* 6716 */ "ICALL_BRANCH_FUNNEL\0"
7915 /* 6736 */ "G_FSHL\0"
7916 /* 6743 */ "G_SHL\0"
7917 /* 6749 */ "G_FCEIL\0"
7918 /* 6757 */ "PATCHABLE_TAIL_CALL\0"
7919 /* 6777 */ "PATCHABLE_TYPED_EVENT_CALL\0"
7920 /* 6804 */ "PATCHABLE_EVENT_CALL\0"
7921 /* 6825 */ "FENTRY_CALL\0"
7922 /* 6837 */ "KILL\0"
7923 /* 6842 */ "G_CONSTANT_POOL\0"
7924 /* 6858 */ "G_ROTL\0"
7925 /* 6865 */ "G_VECREDUCE_FMUL\0"
7926 /* 6882 */ "G_FMUL\0"
7927 /* 6889 */ "G_VECREDUCE_SEQ_FMUL\0"
7928 /* 6910 */ "G_STRICT_FMUL\0"
7929 /* 6924 */ "G_VECREDUCE_MUL\0"
7930 /* 6940 */ "G_MUL\0"
7931 /* 6946 */ "G_FREM\0"
7932 /* 6953 */ "G_STRICT_FREM\0"
7933 /* 6967 */ "G_SREM\0"
7934 /* 6974 */ "G_UREM\0"
7935 /* 6981 */ "G_SDIVREM\0"
7936 /* 6991 */ "G_UDIVREM\0"
7937 /* 7001 */ "INLINEASM\0"
7938 /* 7011 */ "G_VECREDUCE_FMINIMUM\0"
7939 /* 7032 */ "G_FMINIMUM\0"
7940 /* 7043 */ "G_VECREDUCE_FMAXIMUM\0"
7941 /* 7064 */ "G_FMAXIMUM\0"
7942 /* 7075 */ "G_FMINNUM\0"
7943 /* 7085 */ "G_FMAXNUM\0"
7944 /* 7095 */ "G_FATAN\0"
7945 /* 7103 */ "G_FTAN\0"
7946 /* 7110 */ "G_INTRINSIC_ROUNDEVEN\0"
7947 /* 7132 */ "G_ASSERT_ALIGN\0"
7948 /* 7147 */ "G_FCOPYSIGN\0"
7949 /* 7159 */ "G_VECREDUCE_FMIN\0"
7950 /* 7176 */ "G_ATOMICRMW_FMIN\0"
7951 /* 7193 */ "G_VECREDUCE_SMIN\0"
7952 /* 7210 */ "G_SMIN\0"
7953 /* 7217 */ "G_VECREDUCE_UMIN\0"
7954 /* 7234 */ "G_UMIN\0"
7955 /* 7241 */ "G_ATOMICRMW_UMIN\0"
7956 /* 7258 */ "G_ATOMICRMW_MIN\0"
7957 /* 7274 */ "G_FASIN\0"
7958 /* 7282 */ "G_FSIN\0"
7959 /* 7289 */ "CFI_INSTRUCTION\0"
7960 /* 7305 */ "ADJCALLSTACKDOWN\0"
7961 /* 7322 */ "G_SSUBO\0"
7962 /* 7330 */ "G_USUBO\0"
7963 /* 7338 */ "G_SADDO\0"
7964 /* 7346 */ "G_UADDO\0"
7965 /* 7354 */ "JUMP_TABLE_DEBUG_INFO\0"
7966 /* 7376 */ "G_SMULO\0"
7967 /* 7384 */ "G_UMULO\0"
7968 /* 7392 */ "G_BZERO\0"
7969 /* 7400 */ "STACKMAP\0"
7970 /* 7409 */ "G_DEBUGTRAP\0"
7971 /* 7421 */ "G_UBSANTRAP\0"
7972 /* 7433 */ "G_TRAP\0"
7973 /* 7440 */ "G_ATOMICRMW_UDEC_WRAP\0"
7974 /* 7462 */ "G_ATOMICRMW_UINC_WRAP\0"
7975 /* 7484 */ "G_BSWAP\0"
7976 /* 7492 */ "G_SITOFP\0"
7977 /* 7501 */ "G_UITOFP\0"
7978 /* 7510 */ "G_FCMP\0"
7979 /* 7517 */ "G_ICMP\0"
7980 /* 7524 */ "G_SCMP\0"
7981 /* 7531 */ "G_UCMP\0"
7982 /* 7538 */ "CONVERGENCECTRL_LOOP\0"
7983 /* 7559 */ "G_CTPOP\0"
7984 /* 7567 */ "PATCHABLE_OP\0"
7985 /* 7580 */ "FAULTING_OP\0"
7986 /* 7592 */ "ADJCALLSTACKUP\0"
7987 /* 7607 */ "PREALLOCATED_SETUP\0"
7988 /* 7626 */ "G_FLDEXP\0"
7989 /* 7635 */ "G_STRICT_FLDEXP\0"
7990 /* 7651 */ "G_FEXP\0"
7991 /* 7658 */ "G_FFREXP\0"
7992 /* 7667 */ "A6_vminub_RdP\0"
7993 /* 7681 */ "G_BR\0"
7994 /* 7686 */ "INLINEASM_BR\0"
7995 /* 7699 */ "G_BLOCK_ADDR\0"
7996 /* 7712 */ "MEMBARRIER\0"
7997 /* 7723 */ "G_CONSTANT_FOLD_BARRIER\0"
7998 /* 7747 */ "PATCHABLE_FUNCTION_ENTER\0"
7999 /* 7772 */ "G_READCYCLECOUNTER\0"
8000 /* 7791 */ "G_READSTEADYCOUNTER\0"
8001 /* 7811 */ "G_READ_REGISTER\0"
8002 /* 7827 */ "G_WRITE_REGISTER\0"
8003 /* 7844 */ "G_ASHR\0"
8004 /* 7851 */ "G_FSHR\0"
8005 /* 7858 */ "G_LSHR\0"
8006 /* 7865 */ "CONVERGENCECTRL_ANCHOR\0"
8007 /* 7888 */ "G_FFLOOR\0"
8008 /* 7897 */ "G_EXTRACT_SUBVECTOR\0"
8009 /* 7917 */ "G_INSERT_SUBVECTOR\0"
8010 /* 7936 */ "G_BUILD_VECTOR\0"
8011 /* 7951 */ "G_SHUFFLE_VECTOR\0"
8012 /* 7968 */ "G_SPLAT_VECTOR\0"
8013 /* 7983 */ "G_VECREDUCE_XOR\0"
8014 /* 7999 */ "G_XOR\0"
8015 /* 8005 */ "G_ATOMICRMW_XOR\0"
8016 /* 8021 */ "G_VECREDUCE_OR\0"
8017 /* 8036 */ "G_OR\0"
8018 /* 8041 */ "G_ATOMICRMW_OR\0"
8019 /* 8056 */ "EH_RETURN_JMPR\0"
8020 /* 8071 */ "G_ROTR\0"
8021 /* 8078 */ "G_INTTOPTR\0"
8022 /* 8089 */ "G_FABS\0"
8023 /* 8096 */ "G_ABS\0"
8024 /* 8102 */ "A5_ACS\0"
8025 /* 8109 */ "G_UNMERGE_VALUES\0"
8026 /* 8126 */ "G_MERGE_VALUES\0"
8027 /* 8141 */ "G_FACOS\0"
8028 /* 8149 */ "G_FCOS\0"
8029 /* 8156 */ "G_CONCAT_VECTORS\0"
8030 /* 8173 */ "COPY_TO_REGCLASS\0"
8031 /* 8190 */ "G_IS_FPCLASS\0"
8032 /* 8203 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
8033 /* 8233 */ "G_VECTOR_COMPRESS\0"
8034 /* 8251 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
8035 /* 8278 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
8036 /* 8316 */ "G_SSUBSAT\0"
8037 /* 8326 */ "G_USUBSAT\0"
8038 /* 8336 */ "G_SADDSAT\0"
8039 /* 8346 */ "G_UADDSAT\0"
8040 /* 8356 */ "G_SSHLSAT\0"
8041 /* 8366 */ "G_USHLSAT\0"
8042 /* 8376 */ "G_SMULFIXSAT\0"
8043 /* 8389 */ "G_UMULFIXSAT\0"
8044 /* 8402 */ "G_SDIVFIXSAT\0"
8045 /* 8415 */ "G_UDIVFIXSAT\0"
8046 /* 8428 */ "G_EXTRACT\0"
8047 /* 8438 */ "G_SELECT\0"
8048 /* 8447 */ "G_BRINDIRECT\0"
8049 /* 8460 */ "PATCHABLE_RET\0"
8050 /* 8474 */ "G_MEMSET\0"
8051 /* 8483 */ "PATCHABLE_FUNCTION_EXIT\0"
8052 /* 8507 */ "G_BRJT\0"
8053 /* 8514 */ "G_EXTRACT_VECTOR_ELT\0"
8054 /* 8535 */ "G_INSERT_VECTOR_ELT\0"
8055 /* 8555 */ "G_FCONSTANT\0"
8056 /* 8567 */ "G_CONSTANT\0"
8057 /* 8578 */ "G_INTRINSIC_CONVERGENT\0"
8058 /* 8601 */ "STATEPOINT\0"
8059 /* 8612 */ "PATCHPOINT\0"
8060 /* 8623 */ "G_PTRTOINT\0"
8061 /* 8634 */ "G_FRINT\0"
8062 /* 8642 */ "G_INTRINSIC_LLRINT\0"
8063 /* 8661 */ "G_INTRINSIC_LRINT\0"
8064 /* 8679 */ "G_FNEARBYINT\0"
8065 /* 8692 */ "G_VASTART\0"
8066 /* 8702 */ "LIFETIME_START\0"
8067 /* 8717 */ "G_INVOKE_REGION_START\0"
8068 /* 8739 */ "G_INSERT\0"
8069 /* 8748 */ "G_FSQRT\0"
8070 /* 8756 */ "G_STRICT_FSQRT\0"
8071 /* 8771 */ "G_BITCAST\0"
8072 /* 8781 */ "G_ADDRSPACE_CAST\0"
8073 /* 8798 */ "DBG_VALUE_LIST\0"
8074 /* 8813 */ "G_FPEXT\0"
8075 /* 8821 */ "G_SEXT\0"
8076 /* 8828 */ "G_ASSERT_SEXT\0"
8077 /* 8842 */ "G_ANYEXT\0"
8078 /* 8851 */ "G_ZEXT\0"
8079 /* 8858 */ "G_ASSERT_ZEXT\0"
8080 /* 8872 */ "RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT\0"
8081 /* 8911 */ "SAVE_REGISTERS_CALL_V4_EXT\0"
8082 /* 8938 */ "RESTORE_DEALLOC_RET_JMP_V4_EXT\0"
8083 /* 8969 */ "SAVE_REGISTERS_CALL_V4STK_EXT\0"
8084 /* 8999 */ "G_FDIV\0"
8085 /* 9006 */ "G_STRICT_FDIV\0"
8086 /* 9020 */ "G_SDIV\0"
8087 /* 9027 */ "G_UDIV\0"
8088 /* 9034 */ "G_GET_FPENV\0"
8089 /* 9046 */ "G_RESET_FPENV\0"
8090 /* 9060 */ "G_SET_FPENV\0"
8091 /* 9072 */ "G_FPOW\0"
8092 /* 9079 */ "G_VECREDUCE_FMAX\0"
8093 /* 9096 */ "G_ATOMICRMW_FMAX\0"
8094 /* 9113 */ "G_VECREDUCE_SMAX\0"
8095 /* 9130 */ "G_SMAX\0"
8096 /* 9137 */ "G_VECREDUCE_UMAX\0"
8097 /* 9154 */ "G_UMAX\0"
8098 /* 9161 */ "G_ATOMICRMW_UMAX\0"
8099 /* 9178 */ "G_ATOMICRMW_MAX\0"
8100 /* 9194 */ "G_FRAME_INDEX\0"
8101 /* 9208 */ "G_SBFX\0"
8102 /* 9215 */ "G_UBFX\0"
8103 /* 9222 */ "G_SMULFIX\0"
8104 /* 9232 */ "G_UMULFIX\0"
8105 /* 9242 */ "G_SDIVFIX\0"
8106 /* 9252 */ "G_UDIVFIX\0"
8107 /* 9262 */ "G_MEMCPY\0"
8108 /* 9271 */ "COPY\0"
8109 /* 9276 */ "CONVERGENCECTRL_ENTRY\0"
8110 /* 9298 */ "G_CTLZ\0"
8111 /* 9305 */ "G_CTTZ\0"
8112 /* 9312 */ "PS_alloca\0"
8113 /* 9322 */ "PS_fia\0"
8114 /* 9329 */ "Y5_l2locka\0"
8115 /* 9340 */ "Y5_l2unlocka\0"
8116 /* 9353 */ "F2_sffma\0"
8117 /* 9362 */ "Y2_dccleana\0"
8118 /* 9374 */ "PS_aligna\0"
8119 /* 9384 */ "Y2_dczeroa\0"
8120 /* 9395 */ "F2_sfrecipa\0"
8121 /* 9407 */ "Y6_l2gcleanpa\0"
8122 /* 9421 */ "Y6_l2gcleaninvpa\0"
8123 /* 9438 */ "V6_vrdelta\0"
8124 /* 9449 */ "V6_vdelta\0"
8125 /* 9459 */ "F2_sfinvsqrta\0"
8126 /* 9473 */ "Y2_dcinva\0"
8127 /* 9483 */ "Y2_icinva\0"
8128 /* 9493 */ "Y2_dccleaninva\0"
8129 /* 9508 */ "V6_vcvt_hf_b\0"
8130 /* 9521 */ "V6_vsubb\0"
8131 /* 9530 */ "V6_vaddb\0"
8132 /* 9539 */ "S2_shuffeb\0"
8133 /* 9550 */ "V6_vshuffeb\0"
8134 /* 9562 */ "V6_vpackeb\0"
8135 /* 9573 */ "V6_vshufoeb\0"
8136 /* 9585 */ "M6_vabsdiffb\0"
8137 /* 9598 */ "V6_vshuffb\0"
8138 /* 9609 */ "V6_vnavgb\0"
8139 /* 9619 */ "V6_vavgb\0"
8140 /* 9628 */ "V6_vmpahb\0"
8141 /* 9638 */ "V6_vroundhb\0"
8142 /* 9650 */ "S2_vtrunehb\0"
8143 /* 9662 */ "V6_vmpyihb\0"
8144 /* 9673 */ "S2_vtrunohb\0"
8145 /* 9685 */ "S2_vsathb\0"
8146 /* 9695 */ "S2_svsathb\0"
8147 /* 9706 */ "V6_vmpauhb\0"
8148 /* 9717 */ "V6_vdmpyhb\0"
8149 /* 9728 */ "V6_vtmpyhb\0"
8150 /* 9739 */ "S2_vspliceib\0"
8151 /* 9752 */ "F2_sffma_lib\0"
8152 /* 9765 */ "F2_sffms_lib\0"
8153 /* 9778 */ "S2_valignib\0"
8154 /* 9790 */ "PS_vsplatib\0"
8155 /* 9802 */ "V6_vunpackb\0"
8156 /* 9814 */ "V6_vdealb\0"
8157 /* 9824 */ "S2_clb\0"
8158 /* 9831 */ "V6_vlalignb\0"
8159 /* 9843 */ "V6_valignb\0"
8160 /* 9854 */ "A2_vminb\0"
8161 /* 9863 */ "V6_vminb\0"
8162 /* 9872 */ "S2_shuffob\0"
8163 /* 9883 */ "V6_vshuffob\0"
8164 /* 9895 */ "V6_vunpackob\0"
8165 /* 9908 */ "V6_vpackob\0"
8166 /* 9919 */ "V6_veqb\0"
8167 /* 9927 */ "V6_vprefixqb\0"
8168 /* 9940 */ "S2_vsplicerb\0"
8169 /* 9953 */ "S2_valignrb\0"
8170 /* 9965 */ "V6_vlsrb\0"
8171 /* 9974 */ "S2_vsplatrb\0"
8172 /* 9986 */ "PS_vsplatrb\0"
8173 /* 9998 */ "V6_vabsb\0"
8174 /* 10007 */ "V6_vsb\0"
8175 /* 10014 */ "V6_lvsplatb\0"
8176 /* 10026 */ "A2_satb\0"
8177 /* 10034 */ "V6_vgtb\0"
8178 /* 10042 */ "SA1_sxtb\0"
8179 /* 10051 */ "dup_A2_sxtb\0"
8180 /* 10063 */ "SA1_zxtb\0"
8181 /* 10072 */ "dup_A2_zxtb\0"
8182 /* 10084 */ "V6_vcvt_hf_ub\0"
8183 /* 10098 */ "A2_vsubub\0"
8184 /* 10108 */ "A2_vrsadub\0"
8185 /* 10119 */ "A2_vraddub\0"
8186 /* 10130 */ "A2_vaddub\0"
8187 /* 10140 */ "M6_vabsdiffub\0"
8188 /* 10154 */ "V6_vabsdiffub\0"
8189 /* 10168 */ "V6_vnavgub\0"
8190 /* 10179 */ "A2_vavgub\0"
8191 /* 10189 */ "V6_vavgub\0"
8192 /* 10199 */ "V6_vroundhub\0"
8193 /* 10212 */ "S2_vsathub\0"
8194 /* 10223 */ "V6_vsathub\0"
8195 /* 10234 */ "S2_svsathub\0"
8196 /* 10246 */ "V6_vrounduhub\0"
8197 /* 10260 */ "V6_vunpackub\0"
8198 /* 10273 */ "A2_vminub\0"
8199 /* 10283 */ "V6_vminub\0"
8200 /* 10293 */ "V6_MAP_equb\0"
8201 /* 10305 */ "A2_sub\0"
8202 /* 10312 */ "F2_dfsub\0"
8203 /* 10321 */ "F2_sfsub\0"
8204 /* 10330 */ "A2_satub\0"
8205 /* 10339 */ "V6_vgtub\0"
8206 /* 10348 */ "V6_vmpyiwub\0"
8207 /* 10360 */ "A2_vmaxub\0"
8208 /* 10370 */ "V6_vmaxub\0"
8209 /* 10380 */ "V6_vrmpyub\0"
8210 /* 10391 */ "V6_vmpyub\0"
8211 /* 10401 */ "V6_vlutvvb\0"
8212 /* 10412 */ "V6_vmpyiwb\0"
8213 /* 10423 */ "A2_vmaxb\0"
8214 /* 10432 */ "V6_vmaxb\0"
8215 /* 10441 */ "S2_tableidxb\0"
8216 /* 10454 */ "V6_vtmpyb\0"
8217 /* 10464 */ "V6_vzb\0"
8218 /* 10471 */ "M2_vrcmaci_s0c\0"
8219 /* 10486 */ "M2_vrcmpyi_s0c\0"
8220 /* 10501 */ "M2_vrcmacr_s0c\0"
8221 /* 10516 */ "M2_vrcmpyr_s0c\0"
8222 /* 10531 */ "A4_subp_c\0"
8223 /* 10541 */ "A4_addp_c\0"
8224 /* 10551 */ "S6_rol_i_p_nac\0"
8225 /* 10566 */ "S2_asl_i_p_nac\0"
8226 /* 10581 */ "S2_asr_i_p_nac\0"
8227 /* 10596 */ "S2_lsr_i_p_nac\0"
8228 /* 10611 */ "S2_asl_r_p_nac\0"
8229 /* 10626 */ "S2_lsl_r_p_nac\0"
8230 /* 10641 */ "S2_asr_r_p_nac\0"
8231 /* 10656 */ "S2_lsr_r_p_nac\0"
8232 /* 10671 */ "S6_rol_i_r_nac\0"
8233 /* 10686 */ "S2_asl_i_r_nac\0"
8234 /* 10701 */ "S2_asr_i_r_nac\0"
8235 /* 10716 */ "S2_lsr_i_r_nac\0"
8236 /* 10731 */ "S2_asl_r_r_nac\0"
8237 /* 10746 */ "S2_lsl_r_r_nac\0"
8238 /* 10761 */ "S2_asr_r_r_nac\0"
8239 /* 10776 */ "S2_lsr_r_r_nac\0"
8240 /* 10791 */ "V6_vmpyowh_64_acc\0"
8241 /* 10809 */ "V6_vmpahb_acc\0"
8242 /* 10823 */ "V6_vmpyihb_acc\0"
8243 /* 10838 */ "V6_vmpauhb_acc\0"
8244 /* 10853 */ "V6_vdmpyhb_acc\0"
8245 /* 10868 */ "V6_vtmpyhb_acc\0"
8246 /* 10883 */ "A2_vrsadub_acc\0"
8247 /* 10898 */ "A2_vraddub_acc\0"
8248 /* 10913 */ "V6_vmpyiwub_acc\0"
8249 /* 10929 */ "V6_vrmpyub_acc\0"
8250 /* 10944 */ "V6_vmpyub_acc\0"
8251 /* 10958 */ "V6_vmpyiwb_acc\0"
8252 /* 10973 */ "V6_vtmpyb_acc\0"
8253 /* 10987 */ "M7_dcmpyiwc_acc\0"
8254 /* 11003 */ "M7_dcmpyrwc_acc\0"
8255 /* 11019 */ "V6_vmpyuhe_acc\0"
8256 /* 11034 */ "S4_vrcrotate_acc\0"
8257 /* 11051 */ "V6_vmpy_sf_bf_acc\0"
8258 /* 11069 */ "V6_vmpy_hf_hf_acc\0"
8259 /* 11087 */ "V6_vdmpy_sf_hf_acc\0"
8260 /* 11106 */ "V6_vmpy_sf_hf_acc\0"
8261 /* 11124 */ "V6_vaddubh_acc\0"
8262 /* 11139 */ "V6_vmpyih_acc\0"
8263 /* 11153 */ "V6_vaslh_acc\0"
8264 /* 11166 */ "V6_vasrh_acc\0"
8265 /* 11179 */ "V6_vdsaduh_acc\0"
8266 /* 11194 */ "V6_vmpyiewuh_acc\0"
8267 /* 11211 */ "V6_vmpyuh_acc\0"
8268 /* 11225 */ "V6_vmpyiewh_acc\0"
8269 /* 11241 */ "V6_vmpyiwh_acc\0"
8270 /* 11256 */ "M4_vpmpyh_acc\0"
8271 /* 11270 */ "V6_vmpyh_acc\0"
8272 /* 11283 */ "V6_vrsadubi_acc\0"
8273 /* 11299 */ "V6_vrmpyubi_acc\0"
8274 /* 11315 */ "V6_vrmpybusi_acc\0"
8275 /* 11332 */ "S6_rol_i_p_acc\0"
8276 /* 11347 */ "S2_asl_i_p_acc\0"
8277 /* 11362 */ "S2_asr_i_p_acc\0"
8278 /* 11377 */ "S2_lsr_i_p_acc\0"
8279 /* 11392 */ "S2_asl_r_p_acc\0"
8280 /* 11407 */ "S2_lsl_r_p_acc\0"
8281 /* 11422 */ "S2_asr_r_p_acc\0"
8282 /* 11437 */ "S2_lsr_r_p_acc\0"
8283 /* 11452 */ "S6_rol_i_r_acc\0"
8284 /* 11467 */ "S2_asl_i_r_acc\0"
8285 /* 11482 */ "S2_asr_i_r_acc\0"
8286 /* 11497 */ "S2_lsr_i_r_acc\0"
8287 /* 11512 */ "S2_asl_r_r_acc\0"
8288 /* 11527 */ "S2_lsl_r_r_acc\0"
8289 /* 11542 */ "S2_asr_r_r_acc\0"
8290 /* 11557 */ "S2_lsr_r_r_acc\0"
8291 /* 11572 */ "V6_vmpabus_acc\0"
8292 /* 11587 */ "V6_vdmpybus_acc\0"
8293 /* 11603 */ "V6_vrmpybus_acc\0"
8294 /* 11619 */ "V6_vtmpybus_acc\0"
8295 /* 11635 */ "V6_vmpybus_acc\0"
8296 /* 11650 */ "V6_vmpyhus_acc\0"
8297 /* 11665 */ "V6_vdmpyhsat_acc\0"
8298 /* 11682 */ "V6_vmpyhsat_acc\0"
8299 /* 11698 */ "V6_vdmpyhisat_acc\0"
8300 /* 11716 */ "V6_vdmpyhsuisat_acc\0"
8301 /* 11736 */ "V6_vdmpyhsusat_acc\0"
8302 /* 11755 */ "V6_vdmpyhvsat_acc\0"
8303 /* 11773 */ "V6_vrmpyzbb_rt_acc\0"
8304 /* 11792 */ "V6_vrmpyzcb_rt_acc\0"
8305 /* 11811 */ "V6_vrmpyznb_rt_acc\0"
8306 /* 11830 */ "V6_vrmpyzbub_rt_acc\0"
8307 /* 11850 */ "V6_vrmpyzcbs_rt_acc\0"
8308 /* 11870 */ "V6_vandqrt_acc\0"
8309 /* 11885 */ "V6_vandnqrt_acc\0"
8310 /* 11901 */ "V6_vandvrt_acc\0"
8311 /* 11916 */ "V6_vrmpybub_rtt_acc\0"
8312 /* 11936 */ "V6_vrmpyub_rtt_acc\0"
8313 /* 11955 */ "V6_vmpabuu_acc\0"
8314 /* 11970 */ "V6_vrmpyubv_acc\0"
8315 /* 11986 */ "V6_vmpyubv_acc\0"
8316 /* 12001 */ "V6_vrmpybv_acc\0"
8317 /* 12016 */ "V6_vmpybv_acc\0"
8318 /* 12030 */ "V6_vdmpyhb_dv_acc\0"
8319 /* 12048 */ "V6_vdmpybus_dv_acc\0"
8320 /* 12067 */ "V6_vmpyuhv_acc\0"
8321 /* 12082 */ "V6_vmpyhv_acc\0"
8322 /* 12096 */ "V6_vrmpybusv_acc\0"
8323 /* 12113 */ "V6_vmpybusv_acc\0"
8324 /* 12129 */ "V6_vaddhw_acc\0"
8325 /* 12143 */ "V6_vadduhw_acc\0"
8326 /* 12158 */ "M7_dcmpyiw_acc\0"
8327 /* 12173 */ "V6_vaslw_acc\0"
8328 /* 12186 */ "PS_vmulw_acc\0"
8329 /* 12199 */ "V6_vasrw_acc\0"
8330 /* 12212 */ "M7_dcmpyrw_acc\0"
8331 /* 12227 */ "M4_pmpyw_acc\0"
8332 /* 12240 */ "V6_vrmpyzbb_rx_acc\0"
8333 /* 12259 */ "V6_vrmpyzcb_rx_acc\0"
8334 /* 12278 */ "V6_vrmpyznb_rx_acc\0"
8335 /* 12297 */ "V6_vrmpyzbub_rx_acc\0"
8336 /* 12317 */ "V6_vrmpyzcbs_rx_acc\0"
8337 /* 12337 */ "M7_vdmpy_acc\0"
8338 /* 12350 */ "M2_subacc\0"
8339 /* 12360 */ "V6_vlutvvb_oracc\0"
8340 /* 12377 */ "V6_vlutvwh_oracc\0"
8341 /* 12394 */ "V6_vmpyowh_rnd_sacc\0"
8342 /* 12414 */ "V6_vmpyowh_sacc\0"
8343 /* 12430 */ "S6_rol_i_p_xacc\0"
8344 /* 12446 */ "S2_asl_i_p_xacc\0"
8345 /* 12462 */ "S2_lsr_i_p_xacc\0"
8346 /* 12478 */ "S6_rol_i_r_xacc\0"
8347 /* 12494 */ "S2_asl_i_r_xacc\0"
8348 /* 12510 */ "S2_lsr_i_r_xacc\0"
8349 /* 12526 */ "M2_xor_xacc\0"
8350 /* 12538 */ "M4_xor_xacc\0"
8351 /* 12550 */ "SA1_dec\0"
8352 /* 12558 */ "M4_cmpyi_whc\0"
8353 /* 12571 */ "M4_cmpyr_whc\0"
8354 /* 12584 */ "SA1_inc\0"
8355 /* 12592 */ "Y2_isync\0"
8356 /* 12601 */ "Y5_tlboc\0"
8357 /* 12610 */ "C4_addipc\0"
8358 /* 12620 */ "F2_sffma_sc\0"
8359 /* 12632 */ "M7_dcmpyiwc\0"
8360 /* 12644 */ "M7_wcmpyiwc\0"
8361 /* 12656 */ "M7_dcmpyrwc\0"
8362 /* 12668 */ "M7_wcmpyrwc\0"
8363 /* 12680 */ "F2_conv_df2d\0"
8364 /* 12693 */ "F2_conv_sf2d\0"
8365 /* 12706 */ "Y2_ciad\0"
8366 /* 12714 */ "Y4_siad\0"
8367 /* 12722 */ "dup_A2_add\0"
8368 /* 12733 */ "V6_vscattermh_add\0"
8369 /* 12751 */ "V6_vscattermhw_add\0"
8370 /* 12770 */ "V6_vscattermw_add\0"
8371 /* 12788 */ "F2_dfadd\0"
8372 /* 12797 */ "F2_sfadd\0"
8373 /* 12806 */ "V6_vshuffvdd\0"
8374 /* 12819 */ "V6_vdealvdd\0"
8375 /* 12831 */ "L4_loadd_locked\0"
8376 /* 12847 */ "S4_stored_locked\0"
8377 /* 12864 */ "L2_loadw_locked\0"
8378 /* 12880 */ "S2_storew_locked\0"
8379 /* 12897 */ "LDriw_pred\0"
8380 /* 12908 */ "STriw_pred\0"
8381 /* 12919 */ "Y2_crswap_old\0"
8382 /* 12933 */ "A2_and\0"
8383 /* 12940 */ "C2_and\0"
8384 /* 12947 */ "V6_veqb_and\0"
8385 /* 12959 */ "V6_vgtb_and\0"
8386 /* 12971 */ "V6_MAP_equb_and\0"
8387 /* 12987 */ "V6_vgtub_and\0"
8388 /* 13000 */ "V6_pred_and\0"
8389 /* 13012 */ "C4_and_and\0"
8390 /* 13023 */ "M4_and_and\0"
8391 /* 13034 */ "V6_vgtbf_and\0"
8392 /* 13047 */ "V6_vgthf_and\0"
8393 /* 13060 */ "V6_vgtsf_and\0"
8394 /* 13073 */ "V6_veqh_and\0"
8395 /* 13085 */ "V6_vgth_and\0"
8396 /* 13097 */ "V6_MAP_equh_and\0"
8397 /* 13113 */ "V6_vgtuh_and\0"
8398 /* 13126 */ "S6_rol_i_p_and\0"
8399 /* 13141 */ "S2_asl_i_p_and\0"
8400 /* 13156 */ "S2_asr_i_p_and\0"
8401 /* 13171 */ "S2_lsr_i_p_and\0"
8402 /* 13186 */ "S2_asl_r_p_and\0"
8403 /* 13201 */ "S2_lsl_r_p_and\0"
8404 /* 13216 */ "S2_asr_r_p_and\0"
8405 /* 13231 */ "S2_lsr_r_p_and\0"
8406 /* 13246 */ "S6_rol_i_r_and\0"
8407 /* 13261 */ "S2_asl_i_r_and\0"
8408 /* 13276 */ "S2_asr_i_r_and\0"
8409 /* 13291 */ "S2_lsr_i_r_and\0"
8410 /* 13306 */ "S2_asl_r_r_and\0"
8411 /* 13321 */ "S2_lsl_r_r_and\0"
8412 /* 13336 */ "S2_asr_r_r_and\0"
8413 /* 13351 */ "S2_lsr_r_r_and\0"
8414 /* 13366 */ "C4_or_and\0"
8415 /* 13376 */ "M4_or_and\0"
8416 /* 13386 */ "M4_xor_and\0"
8417 /* 13397 */ "V6_veqw_and\0"
8418 /* 13409 */ "V6_vgtw_and\0"
8419 /* 13421 */ "V6_MAP_equw_and\0"
8420 /* 13437 */ "V6_vgtuw_and\0"
8421 /* 13450 */ "V6_vand\0"
8422 /* 13458 */ "M7_wcmpyiwc_rnd\0"
8423 /* 13474 */ "M7_wcmpyrwc_rnd\0"
8424 /* 13490 */ "V6_vmpyowh_rnd\0"
8425 /* 13505 */ "S2_asr_i_p_rnd\0"
8426 /* 13520 */ "S2_asr_i_r_rnd\0"
8427 /* 13535 */ "M7_wcmpyiw_rnd\0"
8428 /* 13550 */ "M7_wcmpyrw_rnd\0"
8429 /* 13565 */ "V6_vavgbrnd\0"
8430 /* 13577 */ "V6_vavgubrnd\0"
8431 /* 13590 */ "V6_vavghrnd\0"
8432 /* 13602 */ "S5_vasrhrnd\0"
8433 /* 13614 */ "V6_vavguhrnd\0"
8434 /* 13627 */ "V6_vavgwrnd\0"
8435 /* 13639 */ "V6_vavguwrnd\0"
8436 /* 13652 */ "F2_sffixupd\0"
8437 /* 13664 */ "F2_conv_df2ud\0"
8438 /* 13678 */ "F2_conv_sf2ud\0"
8439 /* 13692 */ "S2_tableidxd\0"
8440 /* 13705 */ "Y4_trace\0"
8441 /* 13714 */ "invalid_decode\0"
8442 /* 13729 */ "F2_dfcmpge\0"
8443 /* 13740 */ "F2_sfcmpge\0"
8444 /* 13751 */ "V6_vmpyuhe\0"
8445 /* 13762 */ "CALLProfile\0"
8446 /* 13774 */ "SS2_allocframe\0"
8447 /* 13789 */ "dup_S2_allocframe\0"
8448 /* 13807 */ "SL2_deallocframe\0"
8449 /* 13824 */ "dup_L2_deallocframe\0"
8450 /* 13844 */ "Y2_resume\0"
8451 /* 13854 */ "Y6_dmresume\0"
8452 /* 13866 */ "V6_vnccombine\0"
8453 /* 13880 */ "V6_vccombine\0"
8454 /* 13893 */ "V6_vcombine\0"
8455 /* 13905 */ "PS_false\0"
8456 /* 13914 */ "PS_qfalse\0"
8457 /* 13924 */ "J2_pause\0"
8458 /* 13933 */ "Y6_dmpause\0"
8459 /* 13944 */ "J2_unpause\0"
8460 /* 13955 */ "S4_vrcrotate\0"
8461 /* 13968 */ "S2_vcrotate\0"
8462 /* 13980 */ "C4_cmplte\0"
8463 /* 13990 */ "J2_rte\0"
8464 /* 13997 */ "PS_true\0"
8465 /* 14005 */ "PS_qtrue\0"
8466 /* 14014 */ "S2_interleave\0"
8467 /* 14028 */ "S2_deinterleave\0"
8468 /* 14044 */ "SL2_jumpr31_f\0"
8469 /* 14058 */ "SL2_return_f\0"
8470 /* 14071 */ "L4_return_f\0"
8471 /* 14083 */ "L4_return_map_to_raw_f\0"
8472 /* 14106 */ "V6_vsub_sf_bf\0"
8473 /* 14120 */ "V6_vadd_sf_bf\0"
8474 /* 14134 */ "V6_vmpy_sf_bf\0"
8475 /* 14148 */ "V6_vmin_bf\0"
8476 /* 14159 */ "V6_vmax_bf\0"
8477 /* 14170 */ "V6_vgtbf\0"
8478 /* 14179 */ "A4_psxtbf\0"
8479 /* 14189 */ "A4_pzxtbf\0"
8480 /* 14199 */ "A2_psubf\0"
8481 /* 14208 */ "F2_conv_d2df\0"
8482 /* 14221 */ "F2_conv_ud2df\0"
8483 /* 14235 */ "F2_conv_sf2df\0"
8484 /* 14249 */ "F2_conv_w2df\0"
8485 /* 14262 */ "F2_conv_uw2df\0"
8486 /* 14276 */ "A2_paddf\0"
8487 /* 14285 */ "A2_pandf\0"
8488 /* 14294 */ "V6_vshuff\0"
8489 /* 14304 */ "V6_vmpy_qf32_hf\0"
8490 /* 14320 */ "V6_vmpy_qf16_hf\0"
8491 /* 14336 */ "V6_vcvt_b_hf\0"
8492 /* 14349 */ "V6_vcvt_ub_hf\0"
8493 /* 14363 */ "V6_vsub_hf\0"
8494 /* 14374 */ "V6_vadd_hf\0"
8495 /* 14385 */ "V6_vsub_hf_hf\0"
8496 /* 14399 */ "V6_vadd_hf_hf\0"
8497 /* 14413 */ "V6_vmpy_hf_hf\0"
8498 /* 14427 */ "V6_vsub_sf_hf\0"
8499 /* 14441 */ "V6_vadd_sf_hf\0"
8500 /* 14455 */ "V6_vcvt_sf_hf\0"
8501 /* 14469 */ "V6_vdmpy_sf_hf\0"
8502 /* 14484 */ "V6_vmpy_sf_hf\0"
8503 /* 14498 */ "V6_vfneg_hf\0"
8504 /* 14510 */ "V6_vcvt_h_hf\0"
8505 /* 14523 */ "V6_vconv_h_hf\0"
8506 /* 14537 */ "V6_vcvt_uh_hf\0"
8507 /* 14551 */ "V6_vfmin_hf\0"
8508 /* 14563 */ "V6_vmin_hf\0"
8509 /* 14574 */ "V6_vabs_hf\0"
8510 /* 14585 */ "V6_vfmax_hf\0"
8511 /* 14597 */ "V6_vmax_hf\0"
8512 /* 14608 */ "V6_vmpy_qf32_mix_hf\0"
8513 /* 14628 */ "V6_vmpy_qf16_mix_hf\0"
8514 /* 14648 */ "A4_paslhf\0"
8515 /* 14658 */ "A4_pasrhf\0"
8516 /* 14668 */ "V6_vgthf\0"
8517 /* 14677 */ "A4_psxthf\0"
8518 /* 14687 */ "A4_pzxthf\0"
8519 /* 14697 */ "A2_paddif\0"
8520 /* 14707 */ "dup_C2_cmoveif\0"
8521 /* 14722 */ "dup_C2_cmovenewif\0"
8522 /* 14740 */ "J2_callf\0"
8523 /* 14749 */ "J2_jumpf\0"
8524 /* 14758 */ "A2_tfrpf\0"
8525 /* 14767 */ "A2_tfrf\0"
8526 /* 14775 */ "SA1_clrf\0"
8527 /* 14784 */ "J2_callrf\0"
8528 /* 14794 */ "A2_porf\0"
8529 /* 14802 */ "A2_pxorf\0"
8530 /* 14811 */ "J2_jumprf\0"
8531 /* 14821 */ "F2_conv_d2sf\0"
8532 /* 14834 */ "F2_conv_ud2sf\0"
8533 /* 14848 */ "F2_conv_df2sf\0"
8534 /* 14862 */ "F2_conv_w2sf\0"
8535 /* 14875 */ "F2_conv_uw2sf\0"
8536 /* 14889 */ "V6_vmpy_qf32_sf\0"
8537 /* 14905 */ "V6_vsub_sf\0"
8538 /* 14916 */ "V6_vadd_sf\0"
8539 /* 14927 */ "V6_vcvt_bf_sf\0"
8540 /* 14941 */ "V6_vcvt_hf_sf\0"
8541 /* 14955 */ "V6_vsub_sf_sf\0"
8542 /* 14969 */ "V6_vadd_sf_sf\0"
8543 /* 14983 */ "V6_vmpy_sf_sf\0"
8544 /* 14997 */ "V6_vfneg_sf\0"
8545 /* 15009 */ "V6_vfmin_sf\0"
8546 /* 15021 */ "V6_vmin_sf\0"
8547 /* 15032 */ "V6_vabs_sf\0"
8548 /* 15043 */ "V6_vconv_w_sf\0"
8549 /* 15057 */ "V6_vfmax_sf\0"
8550 /* 15069 */ "V6_vmax_sf\0"
8551 /* 15080 */ "V6_vgtsf\0"
8552 /* 15089 */ "PS_jmpretf\0"
8553 /* 15100 */ "C2_ccombinewf\0"
8554 /* 15114 */ "C2_ccombinewnewf\0"
8555 /* 15131 */ "Y6_diag\0"
8556 /* 15139 */ "A2_neg\0"
8557 /* 15146 */ "V6_vcl0h\0"
8558 /* 15155 */ "M2_vrcmpys_acc_s1_h\0"
8559 /* 15175 */ "M2_vrcmpys_s1_h\0"
8560 /* 15191 */ "V6_vcvt_hf_h\0"
8561 /* 15204 */ "V6_vconv_hf_h\0"
8562 /* 15218 */ "M2_vrcmpys_s1rp_h\0"
8563 /* 15236 */ "V6_vaddclbh\0"
8564 /* 15248 */ "S2_vsxtbh\0"
8565 /* 15258 */ "S2_vzxtbh\0"
8566 /* 15268 */ "V6_vsububh\0"
8567 /* 15279 */ "V6_vaddubh\0"
8568 /* 15290 */ "S4_vxaddsubh\0"
8569 /* 15303 */ "A2_vsubh\0"
8570 /* 15312 */ "V6_vsubh\0"
8571 /* 15321 */ "A2_svsubh\0"
8572 /* 15331 */ "A4_tlbmatch\0"
8573 /* 15343 */ "Y4_l2fetch\0"
8574 /* 15354 */ "Y5_l2fetch\0"
8575 /* 15365 */ "Y2_dcfetch\0"
8576 /* 15376 */ "S4_vxsubaddh\0"
8577 /* 15389 */ "M2_vraddh\0"
8578 /* 15399 */ "A2_vaddh\0"
8579 /* 15408 */ "V6_vaddh\0"
8580 /* 15417 */ "A2_svaddh\0"
8581 /* 15427 */ "S2_shuffeh\0"
8582 /* 15438 */ "V6_vshufeh\0"
8583 /* 15449 */ "V6_vpackeh\0"
8584 /* 15460 */ "V6_vshufoeh\0"
8585 /* 15472 */ "M2_vabsdiffh\0"
8586 /* 15485 */ "V6_vabsdiffh\0"
8587 /* 15498 */ "V6_vshuffh\0"
8588 /* 15509 */ "S2_vrcnegh\0"
8589 /* 15520 */ "S2_vcnegh\0"
8590 /* 15530 */ "A2_vnavgh\0"
8591 /* 15540 */ "V6_vnavgh\0"
8592 /* 15550 */ "A2_svnavgh\0"
8593 /* 15561 */ "A2_vavgh\0"
8594 /* 15570 */ "V6_vavgh\0"
8595 /* 15579 */ "A2_svavgh\0"
8596 /* 15589 */ "A2_subh_h16_hh\0"
8597 /* 15604 */ "A2_addh_h16_hh\0"
8598 /* 15619 */ "A2_combine_hh\0"
8599 /* 15633 */ "A2_subh_h16_sat_hh\0"
8600 /* 15652 */ "A2_addh_h16_sat_hh\0"
8601 /* 15671 */ "F2_dfmpyhh\0"
8602 /* 15682 */ "A2_tfrih\0"
8603 /* 15691 */ "PS_vsplatih\0"
8604 /* 15703 */ "V6_vmpyih\0"
8605 /* 15713 */ "V6_vunpackh\0"
8606 /* 15725 */ "A2_subh_h16_lh\0"
8607 /* 15740 */ "A2_addh_h16_lh\0"
8608 /* 15755 */ "A2_combine_lh\0"
8609 /* 15769 */ "A2_subh_h16_sat_lh\0"
8610 /* 15788 */ "A2_addh_h16_sat_lh\0"
8611 /* 15807 */ "V6_vdealh\0"
8612 /* 15817 */ "A2_aslh\0"
8613 /* 15825 */ "V6_vaslh\0"
8614 /* 15834 */ "F2_dfmpylh\0"
8615 /* 15845 */ "V6_vgathermh\0"
8616 /* 15858 */ "V6_vscattermh\0"
8617 /* 15872 */ "A4_vrminh\0"
8618 /* 15882 */ "A2_vminh\0"
8619 /* 15891 */ "V6_vminh\0"
8620 /* 15900 */ "V6_vmpyieoh\0"
8621 /* 15912 */ "S2_shuffoh\0"
8622 /* 15923 */ "V6_vshufoh\0"
8623 /* 15934 */ "V6_vunpackoh\0"
8624 /* 15947 */ "V6_vpackoh\0"
8625 /* 15958 */ "A2_addsph\0"
8626 /* 15968 */ "V6_shuffeqh\0"
8627 /* 15980 */ "V6_veqh\0"
8628 /* 15988 */ "V6_vprefixqh\0"
8629 /* 16001 */ "J2_callrh\0"
8630 /* 16011 */ "J2_jumprh\0"
8631 /* 16021 */ "A2_asrh\0"
8632 /* 16029 */ "V6_vasrh\0"
8633 /* 16038 */ "V6_vlsrh\0"
8634 /* 16047 */ "S2_vsplatrh\0"
8635 /* 16059 */ "PS_vsplatrh\0"
8636 /* 16071 */ "PS_crash\0"
8637 /* 16080 */ "A2_vabsh\0"
8638 /* 16089 */ "V6_vabsh\0"
8639 /* 16098 */ "V6_vsh\0"
8640 /* 16105 */ "V6_lvsplath\0"
8641 /* 16117 */ "A2_sath\0"
8642 /* 16125 */ "V6_vgth\0"
8643 /* 16133 */ "V6_vnormamth\0"
8644 /* 16146 */ "V6_vpopcounth\0"
8645 /* 16160 */ "SA1_sxth\0"
8646 /* 16169 */ "dup_A2_sxth\0"
8647 /* 16181 */ "SA1_zxth\0"
8648 /* 16190 */ "dup_A2_zxth\0"
8649 /* 16202 */ "V6_vcvt_hf_uh\0"
8650 /* 16216 */ "V6_vdsaduh\0"
8651 /* 16227 */ "M2_vradduh\0"
8652 /* 16238 */ "V6_vabsdiffuh\0"
8653 /* 16252 */ "A2_vavguh\0"
8654 /* 16262 */ "V6_vavguh\0"
8655 /* 16272 */ "V6_vunpackuh\0"
8656 /* 16285 */ "A4_vrminuh\0"
8657 /* 16296 */ "A2_vminuh\0"
8658 /* 16306 */ "V6_vminuh\0"
8659 /* 16316 */ "V6_MAP_equh\0"
8660 /* 16328 */ "A2_satuh\0"
8661 /* 16337 */ "V6_vgtuh\0"
8662 /* 16346 */ "V6_vroundwuh\0"
8663 /* 16359 */ "V6_vmpyiewuh\0"
8664 /* 16372 */ "V6_vmpyewuh\0"
8665 /* 16384 */ "S2_vsatwuh\0"
8666 /* 16395 */ "V6_vrounduwuh\0"
8667 /* 16409 */ "V6_vsatuwuh\0"
8668 /* 16421 */ "A4_vrmaxuh\0"
8669 /* 16432 */ "A2_vmaxuh\0"
8670 /* 16442 */ "V6_vmaxuh\0"
8671 /* 16452 */ "V6_vmpyuh\0"
8672 /* 16462 */ "S2_asl_i_vh\0"
8673 /* 16474 */ "S2_asr_i_vh\0"
8674 /* 16486 */ "S2_lsr_i_vh\0"
8675 /* 16498 */ "S2_asl_r_vh\0"
8676 /* 16510 */ "S2_lsl_r_vh\0"
8677 /* 16522 */ "S2_asr_r_vh\0"
8678 /* 16534 */ "S2_lsr_r_vh\0"
8679 /* 16546 */ "M4_cmpyi_wh\0"
8680 /* 16558 */ "M4_cmpyr_wh\0"
8681 /* 16570 */ "V6_vroundwh\0"
8682 /* 16582 */ "S2_vtrunewh\0"
8683 /* 16594 */ "V6_vmpyiwh\0"
8684 /* 16605 */ "S2_vrndpackwh\0"
8685 /* 16619 */ "V6_vmpyiowh\0"
8686 /* 16631 */ "S2_vtrunowh\0"
8687 /* 16643 */ "V6_vmpyowh\0"
8688 /* 16654 */ "V6_vasrwh\0"
8689 /* 16664 */ "S2_vsatwh\0"
8690 /* 16674 */ "V6_vsatwh\0"
8691 /* 16684 */ "V6_vlutvwh\0"
8692 /* 16695 */ "A4_vrmaxh\0"
8693 /* 16705 */ "A2_vmaxh\0"
8694 /* 16714 */ "V6_vmaxh\0"
8695 /* 16723 */ "S2_tableidxh\0"
8696 /* 16736 */ "M4_vpmpyh\0"
8697 /* 16746 */ "V6_vmpyh\0"
8698 /* 16755 */ "V6_vzh\0"
8699 /* 16762 */ "SA1_combine0i\0"
8700 /* 16776 */ "J2_loop0i\0"
8701 /* 16786 */ "SA1_combine1i\0"
8702 /* 16800 */ "J2_loop1i\0"
8703 /* 16810 */ "SA1_combine2i\0"
8704 /* 16824 */ "SA1_combine3i\0"
8705 /* 16838 */ "PS_tailcall_i\0"
8706 /* 16852 */ "M2_vcmac_s0_sat_i\0"
8707 /* 16870 */ "M2_vcmpy_s0_sat_i\0"
8708 /* 16888 */ "M2_vcmpy_s1_sat_i\0"
8709 /* 16906 */ "S2_togglebit_i\0"
8710 /* 16921 */ "S2_clrbit_i\0"
8711 /* 16933 */ "S2_setbit_i\0"
8712 /* 16945 */ "S2_tstbit_i\0"
8713 /* 16957 */ "S4_ntstbit_i\0"
8714 /* 16970 */ "V6_vL32b_ai\0"
8715 /* 16982 */ "V6_vS32b_ai\0"
8716 /* 16994 */ "V6_vL32Ub_ai\0"
8717 /* 17007 */ "V6_vS32Ub_ai\0"
8718 /* 17020 */ "V6_zLd_ai\0"
8719 /* 17030 */ "V6_vL32b_pred_ai\0"
8720 /* 17047 */ "V6_vS32b_pred_ai\0"
8721 /* 17064 */ "V6_vS32Ub_pred_ai\0"
8722 /* 17082 */ "V6_zLd_pred_ai\0"
8723 /* 17097 */ "V6_vL32b_tmp_pred_ai\0"
8724 /* 17118 */ "V6_vL32b_nt_tmp_pred_ai\0"
8725 /* 17142 */ "V6_vL32b_cur_pred_ai\0"
8726 /* 17163 */ "V6_vL32b_nt_cur_pred_ai\0"
8727 /* 17187 */ "V6_vL32b_nt_pred_ai\0"
8728 /* 17207 */ "V6_vS32b_nt_pred_ai\0"
8729 /* 17227 */ "V6_vS32b_new_pred_ai\0"
8730 /* 17248 */ "V6_vS32b_nt_new_pred_ai\0"
8731 /* 17272 */ "V6_vL32b_npred_ai\0"
8732 /* 17290 */ "V6_vS32b_npred_ai\0"
8733 /* 17308 */ "V6_vS32Ub_npred_ai\0"
8734 /* 17327 */ "V6_vL32b_tmp_npred_ai\0"
8735 /* 17349 */ "V6_vL32b_nt_tmp_npred_ai\0"
8736 /* 17374 */ "V6_vL32b_cur_npred_ai\0"
8737 /* 17396 */ "V6_vL32b_nt_cur_npred_ai\0"
8738 /* 17421 */ "V6_vL32b_nt_npred_ai\0"
8739 /* 17442 */ "V6_vS32b_nt_npred_ai\0"
8740 /* 17463 */ "V6_vS32b_new_npred_ai\0"
8741 /* 17485 */ "V6_vS32b_nt_new_npred_ai\0"
8742 /* 17510 */ "V6_vS32b_qpred_ai\0"
8743 /* 17528 */ "V6_vS32b_nt_qpred_ai\0"
8744 /* 17549 */ "V6_vS32b_nqpred_ai\0"
8745 /* 17568 */ "V6_vS32b_nt_nqpred_ai\0"
8746 /* 17590 */ "V6_vL32b_tmp_ai\0"
8747 /* 17606 */ "V6_vL32b_nt_tmp_ai\0"
8748 /* 17625 */ "PS_vloadrq_ai\0"
8749 /* 17639 */ "PS_vstorerq_ai\0"
8750 /* 17654 */ "V6_vL32b_cur_ai\0"
8751 /* 17670 */ "V6_vL32b_nt_cur_ai\0"
8752 /* 17689 */ "V6_vS32b_srls_ai\0"
8753 /* 17706 */ "V6_vL32b_nt_ai\0"
8754 /* 17721 */ "V6_vS32b_nt_ai\0"
8755 /* 17736 */ "PS_vloadrv_nt_ai\0"
8756 /* 17753 */ "PS_vstorerv_nt_ai\0"
8757 /* 17771 */ "PS_vloadrw_nt_ai\0"
8758 /* 17788 */ "PS_vstorerw_nt_ai\0"
8759 /* 17806 */ "PS_vloadrv_ai\0"
8760 /* 17820 */ "PS_vstorerv_ai\0"
8761 /* 17835 */ "V6_vS32b_new_ai\0"
8762 /* 17851 */ "V6_vS32b_nt_new_ai\0"
8763 /* 17870 */ "PS_vloadrw_ai\0"
8764 /* 17884 */ "PS_vstorerw_ai\0"
8765 /* 17899 */ "V6_vlalignbi\0"
8766 /* 17912 */ "V6_valignbi\0"
8767 /* 17924 */ "V6_vrsadubi\0"
8768 /* 17936 */ "V6_vrmpyubi\0"
8769 /* 17948 */ "V6_vlutvvbi\0"
8770 /* 17960 */ "M2_maci\0"
8771 /* 17968 */ "M2_mnaci\0"
8772 /* 17977 */ "M2_acci\0"
8773 /* 17985 */ "M2_nacci\0"
8774 /* 17994 */ "V6_vlutvvb_oracci\0"
8775 /* 18012 */ "V6_vlutvwh_oracci\0"
8776 /* 18030 */ "L2_loadbsw2_pci\0"
8777 /* 18046 */ "L2_loadbzw2_pci\0"
8778 /* 18062 */ "L2_loadbsw4_pci\0"
8779 /* 18078 */ "L2_loadbzw4_pci\0"
8780 /* 18094 */ "L2_loadalignb_pci\0"
8781 /* 18112 */ "L2_loadrb_pci\0"
8782 /* 18126 */ "PS_loadrb_pci\0"
8783 /* 18140 */ "S2_storerb_pci\0"
8784 /* 18155 */ "PS_storerb_pci\0"
8785 /* 18170 */ "L2_loadrub_pci\0"
8786 /* 18185 */ "PS_loadrub_pci\0"
8787 /* 18200 */ "L2_loadrd_pci\0"
8788 /* 18214 */ "PS_loadrd_pci\0"
8789 /* 18228 */ "S2_storerd_pci\0"
8790 /* 18243 */ "PS_storerd_pci\0"
8791 /* 18258 */ "S2_storerf_pci\0"
8792 /* 18273 */ "PS_storerf_pci\0"
8793 /* 18288 */ "L2_loadalignh_pci\0"
8794 /* 18306 */ "L2_loadrh_pci\0"
8795 /* 18320 */ "PS_loadrh_pci\0"
8796 /* 18334 */ "S2_storerh_pci\0"
8797 /* 18349 */ "PS_storerh_pci\0"
8798 /* 18364 */ "L2_loadruh_pci\0"
8799 /* 18379 */ "PS_loadruh_pci\0"
8800 /* 18394 */ "L2_loadri_pci\0"
8801 /* 18408 */ "PS_loadri_pci\0"
8802 /* 18422 */ "S2_storeri_pci\0"
8803 /* 18437 */ "PS_storeri_pci\0"
8804 /* 18452 */ "S2_storerbnew_pci\0"
8805 /* 18470 */ "S2_storerhnew_pci\0"
8806 /* 18488 */ "S2_storerinew_pci\0"
8807 /* 18506 */ "SA1_addi\0"
8808 /* 18515 */ "dup_A2_addi\0"
8809 /* 18527 */ "M4_mpyri_addi\0"
8810 /* 18541 */ "M4_mpyrr_addi\0"
8811 /* 18555 */ "S4_clbaddi\0"
8812 /* 18566 */ "S4_subaddi\0"
8813 /* 18577 */ "S4_addaddi\0"
8814 /* 18588 */ "S4_clbpaddi\0"
8815 /* 18600 */ "Y5_tlbasidi\0"
8816 /* 18612 */ "S4_or_andi\0"
8817 /* 18623 */ "C2_cmpgei\0"
8818 /* 18633 */ "C4_cmpltei\0"
8819 /* 18644 */ "PS_fi\0"
8820 /* 18650 */ "V6_hi\0"
8821 /* 18656 */ "A4_boundscheck_hi\0"
8822 /* 18674 */ "V6_vlutvwhi\0"
8823 /* 18686 */ "M2_accii\0"
8824 /* 18695 */ "M2_naccii\0"
8825 /* 18705 */ "dup_A2_combineii\0"
8826 /* 18722 */ "dup_A4_combineii\0"
8827 /* 18739 */ "C2_muxii\0"
8828 /* 18748 */ "S4_lsli\0"
8829 /* 18756 */ "Y4_nmi\0"
8830 /* 18763 */ "M2_mpysmi\0"
8831 /* 18773 */ "L2_loadbsw2_pi\0"
8832 /* 18788 */ "L2_loadbzw2_pi\0"
8833 /* 18803 */ "L2_loadbsw4_pi\0"
8834 /* 18818 */ "L2_loadbzw4_pi\0"
8835 /* 18833 */ "V6_vL32b_pi\0"
8836 /* 18845 */ "V6_vS32b_pi\0"
8837 /* 18857 */ "V6_vL32Ub_pi\0"
8838 /* 18870 */ "V6_vS32Ub_pi\0"
8839 /* 18883 */ "L2_loadalignb_pi\0"
8840 /* 18900 */ "L2_loadrb_pi\0"
8841 /* 18913 */ "S2_storerb_pi\0"
8842 /* 18927 */ "L2_loadrub_pi\0"
8843 /* 18941 */ "V6_zLd_pi\0"
8844 /* 18951 */ "V6_vL32b_pred_pi\0"
8845 /* 18968 */ "V6_vS32b_pred_pi\0"
8846 /* 18985 */ "V6_vS32Ub_pred_pi\0"
8847 /* 19003 */ "V6_zLd_pred_pi\0"
8848 /* 19018 */ "V6_vL32b_tmp_pred_pi\0"
8849 /* 19039 */ "V6_vL32b_nt_tmp_pred_pi\0"
8850 /* 19063 */ "V6_vL32b_cur_pred_pi\0"
8851 /* 19084 */ "V6_vL32b_nt_cur_pred_pi\0"
8852 /* 19108 */ "V6_vL32b_nt_pred_pi\0"
8853 /* 19128 */ "V6_vS32b_nt_pred_pi\0"
8854 /* 19148 */ "V6_vS32b_new_pred_pi\0"
8855 /* 19169 */ "V6_vS32b_nt_new_pred_pi\0"
8856 /* 19193 */ "V6_vL32b_npred_pi\0"
8857 /* 19211 */ "V6_vS32b_npred_pi\0"
8858 /* 19229 */ "V6_vS32Ub_npred_pi\0"
8859 /* 19248 */ "V6_vL32b_tmp_npred_pi\0"
8860 /* 19270 */ "V6_vL32b_nt_tmp_npred_pi\0"
8861 /* 19295 */ "V6_vL32b_cur_npred_pi\0"
8862 /* 19317 */ "V6_vL32b_nt_cur_npred_pi\0"
8863 /* 19342 */ "V6_vL32b_nt_npred_pi\0"
8864 /* 19363 */ "V6_vS32b_nt_npred_pi\0"
8865 /* 19384 */ "V6_vS32b_new_npred_pi\0"
8866 /* 19406 */ "V6_vS32b_nt_new_npred_pi\0"
8867 /* 19431 */ "V6_vS32b_qpred_pi\0"
8868 /* 19449 */ "V6_vS32b_nt_qpred_pi\0"
8869 /* 19470 */ "V6_vS32b_nqpred_pi\0"
8870 /* 19489 */ "V6_vS32b_nt_nqpred_pi\0"
8871 /* 19511 */ "L2_loadrd_pi\0"
8872 /* 19524 */ "S2_storerd_pi\0"
8873 /* 19538 */ "L2_ploadrbf_pi\0"
8874 /* 19553 */ "S2_pstorerbf_pi\0"
8875 /* 19569 */ "L2_ploadrubf_pi\0"
8876 /* 19585 */ "L2_ploadrdf_pi\0"
8877 /* 19600 */ "S2_pstorerdf_pi\0"
8878 /* 19616 */ "S2_pstorerff_pi\0"
8879 /* 19632 */ "L2_ploadrhf_pi\0"
8880 /* 19647 */ "S2_pstorerhf_pi\0"
8881 /* 19663 */ "L2_ploadruhf_pi\0"
8882 /* 19679 */ "L2_ploadrif_pi\0"
8883 /* 19694 */ "S2_pstorerif_pi\0"
8884 /* 19710 */ "S2_storerf_pi\0"
8885 /* 19724 */ "S2_pstorerbnewf_pi\0"
8886 /* 19743 */ "S2_pstorerhnewf_pi\0"
8887 /* 19762 */ "S2_pstorerinewf_pi\0"
8888 /* 19781 */ "L2_loadalignh_pi\0"
8889 /* 19798 */ "L2_loadrh_pi\0"
8890 /* 19811 */ "S2_storerh_pi\0"
8891 /* 19825 */ "L2_loadruh_pi\0"
8892 /* 19839 */ "L2_loadri_pi\0"
8893 /* 19852 */ "S2_storeri_pi\0"
8894 /* 19866 */ "V6_vL32b_tmp_pi\0"
8895 /* 19882 */ "V6_vL32b_nt_tmp_pi\0"
8896 /* 19901 */ "V6_vL32b_cur_pi\0"
8897 /* 19917 */ "V6_vL32b_nt_cur_pi\0"
8898 /* 19936 */ "V6_vS32b_srls_pi\0"
8899 /* 19953 */ "L2_ploadrbt_pi\0"
8900 /* 19968 */ "S2_pstorerbt_pi\0"
8901 /* 19984 */ "L2_ploadrubt_pi\0"
8902 /* 20000 */ "L2_ploadrdt_pi\0"
8903 /* 20015 */ "S2_pstorerdt_pi\0"
8904 /* 20031 */ "S2_pstorerft_pi\0"
8905 /* 20047 */ "L2_ploadrht_pi\0"
8906 /* 20062 */ "S2_pstorerht_pi\0"
8907 /* 20078 */ "L2_ploadruht_pi\0"
8908 /* 20094 */ "L2_ploadrit_pi\0"
8909 /* 20109 */ "S2_pstorerit_pi\0"
8910 /* 20125 */ "V6_vL32b_nt_pi\0"
8911 /* 20140 */ "V6_vS32b_nt_pi\0"
8912 /* 20155 */ "S2_pstorerbnewt_pi\0"
8913 /* 20174 */ "S2_pstorerhnewt_pi\0"
8914 /* 20193 */ "S2_pstorerinewt_pi\0"
8915 /* 20212 */ "V6_vS32b_new_pi\0"
8916 /* 20228 */ "V6_vS32b_nt_new_pi\0"
8917 /* 20247 */ "S2_storerbnew_pi\0"
8918 /* 20264 */ "L2_ploadrbfnew_pi\0"
8919 /* 20282 */ "S2_pstorerbfnew_pi\0"
8920 /* 20301 */ "L2_ploadrubfnew_pi\0"
8921 /* 20320 */ "L2_ploadrdfnew_pi\0"
8922 /* 20338 */ "S2_pstorerdfnew_pi\0"
8923 /* 20357 */ "S2_pstorerffnew_pi\0"
8924 /* 20376 */ "L2_ploadrhfnew_pi\0"
8925 /* 20394 */ "S2_pstorerhfnew_pi\0"
8926 /* 20413 */ "L2_ploadruhfnew_pi\0"
8927 /* 20432 */ "L2_ploadrifnew_pi\0"
8928 /* 20450 */ "S2_pstorerifnew_pi\0"
8929 /* 20469 */ "S2_pstorerbnewfnew_pi\0"
8930 /* 20491 */ "S2_pstorerhnewfnew_pi\0"
8931 /* 20513 */ "S2_pstorerinewfnew_pi\0"
8932 /* 20535 */ "S2_storerhnew_pi\0"
8933 /* 20552 */ "S2_storerinew_pi\0"
8934 /* 20569 */ "L2_ploadrbtnew_pi\0"
8935 /* 20587 */ "S2_pstorerbtnew_pi\0"
8936 /* 20606 */ "L2_ploadrubtnew_pi\0"
8937 /* 20625 */ "L2_ploadrdtnew_pi\0"
8938 /* 20643 */ "S2_pstorerdtnew_pi\0"
8939 /* 20662 */ "S2_pstorerftnew_pi\0"
8940 /* 20681 */ "L2_ploadrhtnew_pi\0"
8941 /* 20699 */ "S2_pstorerhtnew_pi\0"
8942 /* 20718 */ "L2_ploadruhtnew_pi\0"
8943 /* 20737 */ "L2_ploadritnew_pi\0"
8944 /* 20755 */ "S2_pstoreritnew_pi\0"
8945 /* 20774 */ "S2_pstorerbnewtnew_pi\0"
8946 /* 20796 */ "S2_pstorerhnewtnew_pi\0"
8947 /* 20818 */ "S2_pstorerinewtnew_pi\0"
8948 /* 20840 */ "A2_tfrpi\0"
8949 /* 20849 */ "A4_cmpbeqi\0"
8950 /* 20860 */ "A4_vcmpbeqi\0"
8951 /* 20872 */ "A4_cmpheqi\0"
8952 /* 20883 */ "A4_vcmpheqi\0"
8953 /* 20895 */ "C4_cmpneqi\0"
8954 /* 20906 */ "A4_rcmpneqi\0"
8955 /* 20918 */ "SA1_cmpeqi\0"
8956 /* 20929 */ "dup_C2_cmpeqi\0"
8957 /* 20943 */ "A4_rcmpeqi\0"
8958 /* 20954 */ "A4_vcmpweqi\0"
8959 /* 20966 */ "A7_croundd_ri\0"
8960 /* 20980 */ "A4_round_ri\0"
8961 /* 20992 */ "A4_cround_ri\0"
8962 /* 21005 */ "S4_subi_asl_ri\0"
8963 /* 21020 */ "S4_addi_asl_ri\0"
8964 /* 21035 */ "S4_andi_asl_ri\0"
8965 /* 21050 */ "S4_ori_asl_ri\0"
8966 /* 21064 */ "S4_subi_lsr_ri\0"
8967 /* 21079 */ "S4_addi_lsr_ri\0"
8968 /* 21094 */ "S4_andi_lsr_ri\0"
8969 /* 21109 */ "S4_ori_lsr_ri\0"
8970 /* 21123 */ "A2_subri\0"
8971 /* 21132 */ "dup_A4_combineri\0"
8972 /* 21149 */ "C2_bitsclri\0"
8973 /* 21161 */ "C4_nbitsclri\0"
8974 /* 21174 */ "S4_or_ori\0"
8975 /* 21184 */ "S2_addasl_rrri\0"
8976 /* 21199 */ "C2_muxri\0"
8977 /* 21208 */ "J2_ploop1si\0"
8978 /* 21220 */ "J2_ploop2si\0"
8979 /* 21232 */ "J2_ploop3si\0"
8980 /* 21244 */ "dup_A2_tfrsi\0"
8981 /* 21257 */ "V6_vrmpybusi\0"
8982 /* 21270 */ "SA1_seti\0"
8983 /* 21279 */ "J4_jumpseti\0"
8984 /* 21291 */ "A4_cmpbgti\0"
8985 /* 21302 */ "A4_vcmpbgti\0"
8986 /* 21314 */ "A4_cmphgti\0"
8987 /* 21325 */ "A4_vcmphgti\0"
8988 /* 21337 */ "C2_cmpgti\0"
8989 /* 21347 */ "A4_vcmpwgti\0"
8990 /* 21359 */ "A4_bitspliti\0"
8991 /* 21372 */ "C2_cmpgeui\0"
8992 /* 21383 */ "C4_cmplteui\0"
8993 /* 21395 */ "A4_cmpbgtui\0"
8994 /* 21407 */ "A4_vcmpbgtui\0"
8995 /* 21420 */ "A4_cmphgtui\0"
8996 /* 21432 */ "A4_vcmphgtui\0"
8997 /* 21445 */ "C2_cmpgtui\0"
8998 /* 21456 */ "A4_vcmpwgtui\0"
8999 /* 21469 */ "M2_mpyui\0"
9000 /* 21478 */ "R6_release_at_vi\0"
9001 /* 21495 */ "S4_stored_rl_at_vi\0"
9002 /* 21514 */ "S2_storew_rl_at_vi\0"
9003 /* 21533 */ "R6_release_st_vi\0"
9004 /* 21550 */ "S4_stored_rl_st_vi\0"
9005 /* 21569 */ "S2_storew_rl_st_vi\0"
9006 /* 21588 */ "Y2_swi\0"
9007 /* 21595 */ "Y2_cswi\0"
9008 /* 21603 */ "M2_mpyi\0"
9009 /* 21611 */ "A2_vconj\0"
9010 /* 21620 */ "Y2_break\0"
9011 /* 21629 */ "M2_vmpy2s_s0pack\0"
9012 /* 21646 */ "M2_vmpy2s_s1pack\0"
9013 /* 21663 */ "S2_vsathb_nopack\0"
9014 /* 21680 */ "S2_vsathub_nopack\0"
9015 /* 21698 */ "S2_vsatwuh_nopack\0"
9016 /* 21716 */ "S2_vsatwh_nopack\0"
9017 /* 21733 */ "C2_vitpack\0"
9018 /* 21744 */ "A4_boundscheck\0"
9019 /* 21759 */ "Y2_k0lock\0"
9020 /* 21769 */ "Y2_tlblock\0"
9021 /* 21780 */ "Y2_k0unlock\0"
9022 /* 21792 */ "Y2_tlbunlock\0"
9023 /* 21805 */ "Y5_l2gunlock\0"
9024 /* 21818 */ "Y6_dmlink\0"
9025 /* 21828 */ "C2_mask\0"
9026 /* 21836 */ "S2_mask\0"
9027 /* 21844 */ "Y2_getimask\0"
9028 /* 21856 */ "Y2_setimask\0"
9029 /* 21868 */ "PS_call_stk\0"
9030 /* 21880 */ "M2_vrcmpys_acc_s1_l\0"
9031 /* 21900 */ "M2_vrcmpys_s1_l\0"
9032 /* 21916 */ "M2_vrcmpys_s1rp_l\0"
9033 /* 21934 */ "V6_vdeal\0"
9034 /* 21943 */ "A2_subh_h16_hl\0"
9035 /* 21958 */ "A2_addh_h16_hl\0"
9036 /* 21973 */ "A2_subh_l16_hl\0"
9037 /* 21988 */ "A2_addh_l16_hl\0"
9038 /* 22003 */ "A2_combine_hl\0"
9039 /* 22017 */ "A2_subh_h16_sat_hl\0"
9040 /* 22036 */ "A2_addh_h16_sat_hl\0"
9041 /* 22055 */ "A2_subh_l16_sat_hl\0"
9042 /* 22074 */ "A2_addh_l16_sat_hl\0"
9043 /* 22093 */ "dep_S2_packhl\0"
9044 /* 22107 */ "A2_tfril\0"
9045 /* 22116 */ "A2_subh_h16_ll\0"
9046 /* 22131 */ "A2_addh_h16_ll\0"
9047 /* 22146 */ "A2_subh_l16_ll\0"
9048 /* 22161 */ "A2_addh_l16_ll\0"
9049 /* 22176 */ "A2_combine_ll\0"
9050 /* 22190 */ "A2_subh_h16_sat_ll\0"
9051 /* 22209 */ "A2_addh_h16_sat_ll\0"
9052 /* 22228 */ "A2_subh_l16_sat_ll\0"
9053 /* 22247 */ "A2_addh_l16_sat_ll\0"
9054 /* 22266 */ "J2_call\0"
9055 /* 22274 */ "Y2_l2kill\0"
9056 /* 22284 */ "Y2_dckill\0"
9057 /* 22294 */ "Y2_ickill\0"
9058 /* 22304 */ "Y6_dmpoll\0"
9059 /* 22314 */ "F2_dfmpyll\0"
9060 /* 22325 */ "A2_addspl\0"
9061 /* 22335 */ "V6_vwhist128m\0"
9062 /* 22349 */ "V6_vlutvvb_nm\0"
9063 /* 22363 */ "V6_vlutvwh_nm\0"
9064 /* 22377 */ "PS_call_instrprof_custom\0"
9065 /* 22402 */ "V6_vwhist128qm\0"
9066 /* 22417 */ "S2_clbnorm\0"
9067 /* 22428 */ "S4_clbpnorm\0"
9068 /* 22440 */ "V6_pred_and_n\0"
9069 /* 22454 */ "F2_dfimm_n\0"
9070 /* 22465 */ "F2_sfimm_n\0"
9071 /* 22476 */ "V6_pred_or_n\0"
9072 /* 22489 */ "Y5_l2gclean\0"
9073 /* 22501 */ "C2_andn\0"
9074 /* 22509 */ "A4_andn\0"
9075 /* 22517 */ "C4_and_andn\0"
9076 /* 22529 */ "M4_and_andn\0"
9077 /* 22541 */ "C4_or_andn\0"
9078 /* 22552 */ "M4_or_andn\0"
9079 /* 22563 */ "M4_xor_andn\0"
9080 /* 22575 */ "V6_vassign\0"
9081 /* 22586 */ "S2_cabacdecbin\0"
9082 /* 22601 */ "A2_min\0"
9083 /* 22608 */ "F2_dfmin\0"
9084 /* 22617 */ "F2_sfmin\0"
9085 /* 22626 */ "M2_macsin\0"
9086 /* 22636 */ "M2_mpysin\0"
9087 /* 22646 */ "F2_sffixupn\0"
9088 /* 22658 */ "C2_orn\0"
9089 /* 22665 */ "A4_orn\0"
9090 /* 22672 */ "C4_and_orn\0"
9091 /* 22683 */ "C4_or_orn\0"
9092 /* 22693 */ "SL2_return\0"
9093 /* 22704 */ "L4_return\0"
9094 /* 22714 */ "S2_asr_i_svw_trun\0"
9095 /* 22732 */ "S2_asr_r_svw_trun\0"
9096 /* 22750 */ "Y2_dcfetchbo\0"
9097 /* 22763 */ "DUPLEX_Pseudo\0"
9098 /* 22777 */ "V6_vgathermh_pseudo\0"
9099 /* 22797 */ "V6_vgathermhq_pseudo\0"
9100 /* 22818 */ "V6_vgathermhwq_pseudo\0"
9101 /* 22840 */ "V6_vgathermwq_pseudo\0"
9102 /* 22861 */ "V6_vgathermhw_pseudo\0"
9103 /* 22882 */ "V6_vgathermw_pseudo\0"
9104 /* 22902 */ "L2_loadbsw2_io\0"
9105 /* 22917 */ "L2_loadbzw2_io\0"
9106 /* 22932 */ "L2_loadbsw4_io\0"
9107 /* 22947 */ "L2_loadbzw4_io\0"
9108 /* 22962 */ "SS1_storeb_io\0"
9109 /* 22976 */ "L2_loadalignb_io\0"
9110 /* 22993 */ "L4_sub_memopb_io\0"
9111 /* 23010 */ "L4_isub_memopb_io\0"
9112 /* 23028 */ "L4_add_memopb_io\0"
9113 /* 23045 */ "L4_iadd_memopb_io\0"
9114 /* 23063 */ "L4_and_memopb_io\0"
9115 /* 23080 */ "L4_iand_memopb_io\0"
9116 /* 23098 */ "L4_or_memopb_io\0"
9117 /* 23114 */ "L4_ior_memopb_io\0"
9118 /* 23131 */ "SL2_loadrb_io\0"
9119 /* 23145 */ "dup_L2_loadrb_io\0"
9120 /* 23162 */ "dup_S2_storerb_io\0"
9121 /* 23180 */ "dup_S4_storeirb_io\0"
9122 /* 23199 */ "SL1_loadrub_io\0"
9123 /* 23214 */ "dup_L2_loadrub_io\0"
9124 /* 23232 */ "dup_L2_loadrd_io\0"
9125 /* 23249 */ "dup_S2_storerd_io\0"
9126 /* 23267 */ "L2_ploadrbf_io\0"
9127 /* 23282 */ "S2_pstorerbf_io\0"
9128 /* 23298 */ "S4_storeirbf_io\0"
9129 /* 23314 */ "L2_ploadrubf_io\0"
9130 /* 23330 */ "L2_ploadrdf_io\0"
9131 /* 23345 */ "S2_pstorerdf_io\0"
9132 /* 23361 */ "S2_pstorerff_io\0"
9133 /* 23377 */ "L2_ploadrhf_io\0"
9134 /* 23392 */ "S2_pstorerhf_io\0"
9135 /* 23408 */ "S4_storeirhf_io\0"
9136 /* 23424 */ "L2_ploadruhf_io\0"
9137 /* 23440 */ "L2_ploadrif_io\0"
9138 /* 23455 */ "S2_pstorerif_io\0"
9139 /* 23471 */ "S4_storeirif_io\0"
9140 /* 23487 */ "S2_storerf_io\0"
9141 /* 23501 */ "S2_pstorerbnewf_io\0"
9142 /* 23520 */ "S2_pstorerhnewf_io\0"
9143 /* 23539 */ "S2_pstorerinewf_io\0"
9144 /* 23558 */ "SS2_storeh_io\0"
9145 /* 23572 */ "L2_loadalignh_io\0"
9146 /* 23589 */ "L4_sub_memoph_io\0"
9147 /* 23606 */ "L4_isub_memoph_io\0"
9148 /* 23624 */ "L4_add_memoph_io\0"
9149 /* 23641 */ "L4_iadd_memoph_io\0"
9150 /* 23659 */ "L4_and_memoph_io\0"
9151 /* 23676 */ "L4_iand_memoph_io\0"
9152 /* 23694 */ "L4_or_memoph_io\0"
9153 /* 23710 */ "L4_ior_memoph_io\0"
9154 /* 23727 */ "SL2_loadrh_io\0"
9155 /* 23741 */ "dup_L2_loadrh_io\0"
9156 /* 23758 */ "dup_S2_storerh_io\0"
9157 /* 23776 */ "S4_storeirh_io\0"
9158 /* 23791 */ "SL2_loadruh_io\0"
9159 /* 23806 */ "dup_L2_loadruh_io\0"
9160 /* 23824 */ "SL1_loadri_io\0"
9161 /* 23838 */ "dup_L2_loadri_io\0"
9162 /* 23855 */ "dup_S2_storeri_io\0"
9163 /* 23873 */ "dup_S4_storeiri_io\0"
9164 /* 23892 */ "L2_ploadrbt_io\0"
9165 /* 23907 */ "S2_pstorerbt_io\0"
9166 /* 23923 */ "S4_storeirbt_io\0"
9167 /* 23939 */ "L2_ploadrubt_io\0"
9168 /* 23955 */ "L2_ploadrdt_io\0"
9169 /* 23970 */ "S2_pstorerdt_io\0"
9170 /* 23986 */ "S2_pstorerft_io\0"
9171 /* 24002 */ "L2_ploadrht_io\0"
9172 /* 24017 */ "S2_pstorerht_io\0"
9173 /* 24033 */ "S4_storeirht_io\0"
9174 /* 24049 */ "L2_ploadruht_io\0"
9175 /* 24065 */ "L2_ploadrit_io\0"
9176 /* 24080 */ "S2_pstorerit_io\0"
9177 /* 24096 */ "S4_storeirit_io\0"
9178 /* 24112 */ "S2_pstorerbnewt_io\0"
9179 /* 24131 */ "S2_pstorerhnewt_io\0"
9180 /* 24150 */ "S2_pstorerinewt_io\0"
9181 /* 24169 */ "S2_storerbnew_io\0"
9182 /* 24186 */ "L2_ploadrbfnew_io\0"
9183 /* 24204 */ "S4_pstorerbfnew_io\0"
9184 /* 24223 */ "S4_storeirbfnew_io\0"
9185 /* 24242 */ "L2_ploadrubfnew_io\0"
9186 /* 24261 */ "L2_ploadrdfnew_io\0"
9187 /* 24279 */ "S4_pstorerdfnew_io\0"
9188 /* 24298 */ "S4_pstorerffnew_io\0"
9189 /* 24317 */ "L2_ploadrhfnew_io\0"
9190 /* 24335 */ "S4_pstorerhfnew_io\0"
9191 /* 24354 */ "S4_storeirhfnew_io\0"
9192 /* 24373 */ "L2_ploadruhfnew_io\0"
9193 /* 24392 */ "L2_ploadrifnew_io\0"
9194 /* 24410 */ "S4_pstorerifnew_io\0"
9195 /* 24429 */ "S4_storeirifnew_io\0"
9196 /* 24448 */ "S4_pstorerbnewfnew_io\0"
9197 /* 24470 */ "S4_pstorerhnewfnew_io\0"
9198 /* 24492 */ "S4_pstorerinewfnew_io\0"
9199 /* 24514 */ "S2_storerhnew_io\0"
9200 /* 24531 */ "S2_storerinew_io\0"
9201 /* 24548 */ "L2_ploadrbtnew_io\0"
9202 /* 24566 */ "S4_pstorerbtnew_io\0"
9203 /* 24585 */ "S4_storeirbtnew_io\0"
9204 /* 24604 */ "L2_ploadrubtnew_io\0"
9205 /* 24623 */ "L2_ploadrdtnew_io\0"
9206 /* 24641 */ "S4_pstorerdtnew_io\0"
9207 /* 24660 */ "S4_pstorerftnew_io\0"
9208 /* 24679 */ "L2_ploadrhtnew_io\0"
9209 /* 24697 */ "S4_pstorerhtnew_io\0"
9210 /* 24716 */ "S4_storeirhtnew_io\0"
9211 /* 24735 */ "L2_ploadruhtnew_io\0"
9212 /* 24754 */ "L2_ploadritnew_io\0"
9213 /* 24772 */ "S4_pstoreritnew_io\0"
9214 /* 24791 */ "S4_storeiritnew_io\0"
9215 /* 24810 */ "S4_pstorerbnewtnew_io\0"
9216 /* 24832 */ "S4_pstorerhnewtnew_io\0"
9217 /* 24854 */ "S4_pstorerinewtnew_io\0"
9218 /* 24876 */ "SS1_storew_io\0"
9219 /* 24890 */ "L4_sub_memopw_io\0"
9220 /* 24907 */ "L4_isub_memopw_io\0"
9221 /* 24925 */ "L4_add_memopw_io\0"
9222 /* 24942 */ "L4_iadd_memopw_io\0"
9223 /* 24960 */ "L4_and_memopw_io\0"
9224 /* 24977 */ "L4_iand_memopw_io\0"
9225 /* 24995 */ "L4_or_memopw_io\0"
9226 /* 25011 */ "L4_ior_memopw_io\0"
9227 /* 25028 */ "Y2_setprio\0"
9228 /* 25039 */ "V6_lo\0"
9229 /* 25045 */ "A4_boundscheck_lo\0"
9230 /* 25063 */ "V6_vasr_into\0"
9231 /* 25076 */ "F2_dfcmpuo\0"
9232 /* 25087 */ "F2_sfcmpuo\0"
9233 /* 25098 */ "V6_vsubcarryo\0"
9234 /* 25112 */ "V6_vaddcarryo\0"
9235 /* 25126 */ "S2_cl0p\0"
9236 /* 25134 */ "S2_ct0p\0"
9237 /* 25142 */ "S2_cl1p\0"
9238 /* 25150 */ "S2_ct1p\0"
9239 /* 25158 */ "S6_rol_i_p\0"
9240 /* 25169 */ "S2_asl_i_p\0"
9241 /* 25180 */ "S2_asr_i_p\0"
9242 /* 25191 */ "S2_lsr_i_p\0"
9243 /* 25202 */ "F2_dfimm_p\0"
9244 /* 25213 */ "F2_sfimm_p\0"
9245 /* 25224 */ "S2_asl_r_p\0"
9246 /* 25235 */ "S2_lsl_r_p\0"
9247 /* 25246 */ "S2_asr_r_p\0"
9248 /* 25257 */ "S2_lsr_r_p\0"
9249 /* 25268 */ "L4_loadbsw2_ap\0"
9250 /* 25283 */ "L4_loadbzw2_ap\0"
9251 /* 25298 */ "L4_loadbsw4_ap\0"
9252 /* 25313 */ "L4_loadbzw4_ap\0"
9253 /* 25328 */ "L4_loadalignb_ap\0"
9254 /* 25345 */ "L4_loadrb_ap\0"
9255 /* 25358 */ "S4_storerb_ap\0"
9256 /* 25372 */ "L4_loadrub_ap\0"
9257 /* 25386 */ "L4_loadrd_ap\0"
9258 /* 25399 */ "S4_storerd_ap\0"
9259 /* 25413 */ "S4_storerf_ap\0"
9260 /* 25427 */ "L4_loadalignh_ap\0"
9261 /* 25444 */ "L4_loadrh_ap\0"
9262 /* 25457 */ "S4_storerh_ap\0"
9263 /* 25471 */ "L4_loadruh_ap\0"
9264 /* 25485 */ "L4_loadri_ap\0"
9265 /* 25498 */ "S4_storeri_ap\0"
9266 /* 25512 */ "S4_storerbnew_ap\0"
9267 /* 25529 */ "S4_storerhnew_ap\0"
9268 /* 25546 */ "S4_storerinew_ap\0"
9269 /* 25563 */ "V6_vtran2x2_map\0"
9270 /* 25579 */ "A2_vsubb_map\0"
9271 /* 25592 */ "A2_vaddb_map\0"
9272 /* 25605 */ "J2_jumpf_nopred_map\0"
9273 /* 25625 */ "J2_jumprf_nopred_map\0"
9274 /* 25646 */ "J2_jumpt_nopred_map\0"
9275 /* 25666 */ "J2_jumprt_nopred_map\0"
9276 /* 25687 */ "Y2_k1lock_map\0"
9277 /* 25701 */ "Y2_k1unlock_map\0"
9278 /* 25717 */ "C2_pxfer_map\0"
9279 /* 25730 */ "J2_trap1_noregmap\0"
9280 /* 25748 */ "L2_loadbsw2_zomap\0"
9281 /* 25766 */ "L2_loadbzw2_zomap\0"
9282 /* 25784 */ "L2_loadbsw4_zomap\0"
9283 /* 25802 */ "L2_loadbzw4_zomap\0"
9284 /* 25820 */ "L2_loadalignb_zomap\0"
9285 /* 25840 */ "L4_sub_memopb_zomap\0"
9286 /* 25860 */ "L4_isub_memopb_zomap\0"
9287 /* 25881 */ "L4_add_memopb_zomap\0"
9288 /* 25901 */ "L4_iadd_memopb_zomap\0"
9289 /* 25922 */ "L4_and_memopb_zomap\0"
9290 /* 25942 */ "L4_iand_memopb_zomap\0"
9291 /* 25963 */ "L4_or_memopb_zomap\0"
9292 /* 25982 */ "L4_ior_memopb_zomap\0"
9293 /* 26002 */ "L2_loadrb_zomap\0"
9294 /* 26018 */ "S2_storerb_zomap\0"
9295 /* 26035 */ "S4_storeirb_zomap\0"
9296 /* 26053 */ "L2_loadrub_zomap\0"
9297 /* 26070 */ "L2_loadrd_zomap\0"
9298 /* 26086 */ "S2_storerd_zomap\0"
9299 /* 26103 */ "L2_ploadrbf_zomap\0"
9300 /* 26121 */ "S2_pstorerbf_zomap\0"
9301 /* 26140 */ "S4_storeirbf_zomap\0"
9302 /* 26159 */ "L2_ploadrubf_zomap\0"
9303 /* 26178 */ "L2_ploadrdf_zomap\0"
9304 /* 26196 */ "S2_pstorerdf_zomap\0"
9305 /* 26215 */ "S2_pstorerff_zomap\0"
9306 /* 26234 */ "L2_ploadrhf_zomap\0"
9307 /* 26252 */ "S2_pstorerhf_zomap\0"
9308 /* 26271 */ "S4_storeirhf_zomap\0"
9309 /* 26290 */ "L2_ploadruhf_zomap\0"
9310 /* 26309 */ "L2_ploadrif_zomap\0"
9311 /* 26327 */ "S2_pstorerif_zomap\0"
9312 /* 26346 */ "S4_storeirif_zomap\0"
9313 /* 26365 */ "S2_storerf_zomap\0"
9314 /* 26382 */ "S2_pstorerbnewf_zomap\0"
9315 /* 26404 */ "S2_pstorerhnewf_zomap\0"
9316 /* 26426 */ "S2_pstorerinewf_zomap\0"
9317 /* 26448 */ "L2_loadalignh_zomap\0"
9318 /* 26468 */ "L4_sub_memoph_zomap\0"
9319 /* 26488 */ "L4_isub_memoph_zomap\0"
9320 /* 26509 */ "L4_add_memoph_zomap\0"
9321 /* 26529 */ "L4_iadd_memoph_zomap\0"
9322 /* 26550 */ "L4_and_memoph_zomap\0"
9323 /* 26570 */ "L4_iand_memoph_zomap\0"
9324 /* 26591 */ "L4_or_memoph_zomap\0"
9325 /* 26610 */ "L4_ior_memoph_zomap\0"
9326 /* 26630 */ "L2_loadrh_zomap\0"
9327 /* 26646 */ "S2_storerh_zomap\0"
9328 /* 26663 */ "S4_storeirh_zomap\0"
9329 /* 26681 */ "L2_loadruh_zomap\0"
9330 /* 26698 */ "L2_loadri_zomap\0"
9331 /* 26714 */ "S2_storeri_zomap\0"
9332 /* 26731 */ "S4_storeiri_zomap\0"
9333 /* 26749 */ "L2_ploadrbt_zomap\0"
9334 /* 26767 */ "S2_pstorerbt_zomap\0"
9335 /* 26786 */ "S4_storeirbt_zomap\0"
9336 /* 26805 */ "L2_ploadrubt_zomap\0"
9337 /* 26824 */ "L2_ploadrdt_zomap\0"
9338 /* 26842 */ "S2_pstorerdt_zomap\0"
9339 /* 26861 */ "S2_pstorerft_zomap\0"
9340 /* 26880 */ "L2_ploadrht_zomap\0"
9341 /* 26898 */ "S2_pstorerht_zomap\0"
9342 /* 26917 */ "S4_storeirht_zomap\0"
9343 /* 26936 */ "L2_ploadruht_zomap\0"
9344 /* 26955 */ "L2_ploadrit_zomap\0"
9345 /* 26973 */ "S2_pstorerit_zomap\0"
9346 /* 26992 */ "S4_storeirit_zomap\0"
9347 /* 27011 */ "S2_pstorerbnewt_zomap\0"
9348 /* 27033 */ "S2_pstorerhnewt_zomap\0"
9349 /* 27055 */ "S2_pstorerinewt_zomap\0"
9350 /* 27077 */ "S2_storerbnew_zomap\0"
9351 /* 27097 */ "L2_ploadrbfnew_zomap\0"
9352 /* 27118 */ "S4_pstorerbfnew_zomap\0"
9353 /* 27140 */ "S4_storeirbfnew_zomap\0"
9354 /* 27162 */ "L2_ploadrubfnew_zomap\0"
9355 /* 27184 */ "L2_ploadrdfnew_zomap\0"
9356 /* 27205 */ "S4_pstorerdfnew_zomap\0"
9357 /* 27227 */ "S4_pstorerffnew_zomap\0"
9358 /* 27249 */ "L2_ploadrhfnew_zomap\0"
9359 /* 27270 */ "S4_pstorerhfnew_zomap\0"
9360 /* 27292 */ "S4_storeirhfnew_zomap\0"
9361 /* 27314 */ "L2_ploadruhfnew_zomap\0"
9362 /* 27336 */ "L2_ploadrifnew_zomap\0"
9363 /* 27357 */ "S4_pstorerifnew_zomap\0"
9364 /* 27379 */ "S4_storeirifnew_zomap\0"
9365 /* 27401 */ "S4_pstorerbnewfnew_zomap\0"
9366 /* 27426 */ "S4_pstorerhnewfnew_zomap\0"
9367 /* 27451 */ "S4_pstorerinewfnew_zomap\0"
9368 /* 27476 */ "S2_storerhnew_zomap\0"
9369 /* 27496 */ "S2_storerinew_zomap\0"
9370 /* 27516 */ "L2_ploadrbtnew_zomap\0"
9371 /* 27537 */ "S4_pstorerbtnew_zomap\0"
9372 /* 27559 */ "S4_storeirbtnew_zomap\0"
9373 /* 27581 */ "L2_ploadrubtnew_zomap\0"
9374 /* 27603 */ "L2_ploadrdtnew_zomap\0"
9375 /* 27624 */ "S4_pstorerdtnew_zomap\0"
9376 /* 27646 */ "S4_pstorerftnew_zomap\0"
9377 /* 27668 */ "L2_ploadrhtnew_zomap\0"
9378 /* 27689 */ "S4_pstorerhtnew_zomap\0"
9379 /* 27711 */ "S4_storeirhtnew_zomap\0"
9380 /* 27733 */ "L2_ploadruhtnew_zomap\0"
9381 /* 27755 */ "L2_ploadritnew_zomap\0"
9382 /* 27776 */ "S4_pstoreritnew_zomap\0"
9383 /* 27798 */ "S4_storeiritnew_zomap\0"
9384 /* 27820 */ "S4_pstorerbnewtnew_zomap\0"
9385 /* 27845 */ "S4_pstorerhnewtnew_zomap\0"
9386 /* 27870 */ "S4_pstorerinewtnew_zomap\0"
9387 /* 27895 */ "L4_sub_memopw_zomap\0"
9388 /* 27915 */ "L4_isub_memopw_zomap\0"
9389 /* 27936 */ "L4_add_memopw_zomap\0"
9390 /* 27956 */ "L4_iadd_memopw_zomap\0"
9391 /* 27977 */ "L4_and_memopw_zomap\0"
9392 /* 27997 */ "L4_iand_memopw_zomap\0"
9393 /* 28018 */ "L4_or_memopw_zomap\0"
9394 /* 28037 */ "L4_ior_memopw_zomap\0"
9395 /* 28057 */ "V6_vswap\0"
9396 /* 28066 */ "S2_clbp\0"
9397 /* 28074 */ "Y2_tlbp\0"
9398 /* 28082 */ "S6_vsplatrbp\0"
9399 /* 28095 */ "A2_subp\0"
9400 /* 28103 */ "G4_tfrgpcp\0"
9401 /* 28114 */ "A4_tfrpcp\0"
9402 /* 28124 */ "Y4_tfrspcp\0"
9403 /* 28135 */ "A2_addp\0"
9404 /* 28143 */ "A2_andp\0"
9405 /* 28151 */ "V6_vassign_fp\0"
9406 /* 28165 */ "L2_loadrbgp\0"
9407 /* 28177 */ "S2_storerbgp\0"
9408 /* 28190 */ "L2_loadrubgp\0"
9409 /* 28203 */ "L2_loadrdgp\0"
9410 /* 28215 */ "S2_storerdgp\0"
9411 /* 28228 */ "A2_negp\0"
9412 /* 28236 */ "S2_storerfgp\0"
9413 /* 28249 */ "L2_loadrhgp\0"
9414 /* 28261 */ "S2_storerhgp\0"
9415 /* 28274 */ "L2_loadruhgp\0"
9416 /* 28287 */ "L2_loadrigp\0"
9417 /* 28299 */ "S2_storerigp\0"
9418 /* 28312 */ "S2_storerbnewgp\0"
9419 /* 28328 */ "S2_storerhnewgp\0"
9420 /* 28344 */ "S2_storerinewgp\0"
9421 /* 28360 */ "A7_clip\0"
9422 /* 28368 */ "A7_vclip\0"
9423 /* 28377 */ "M2_macsip\0"
9424 /* 28387 */ "M2_mpysip\0"
9425 /* 28397 */ "V6_vcombine_tmp\0"
9426 /* 28413 */ "V6_vassign_tmp\0"
9427 /* 28428 */ "J2_jump\0"
9428 /* 28436 */ "A4_andnp\0"
9429 /* 28445 */ "V6_vassignp\0"
9430 /* 28457 */ "A2_minp\0"
9431 /* 28465 */ "A4_ornp\0"
9432 /* 28473 */ "F2_conv_df2d_chop\0"
9433 /* 28491 */ "F2_conv_sf2d_chop\0"
9434 /* 28509 */ "F2_conv_df2ud_chop\0"
9435 /* 28528 */ "F2_conv_sf2ud_chop\0"
9436 /* 28547 */ "F2_conv_df2w_chop\0"
9437 /* 28565 */ "F2_conv_sf2w_chop\0"
9438 /* 28583 */ "F2_conv_df2uw_chop\0"
9439 /* 28602 */ "F2_conv_sf2uw_chop\0"
9440 /* 28621 */ "A2_nop\0"
9441 /* 28628 */ "Y2_stop\0"
9442 /* 28636 */ "G4_tfrgcpp\0"
9443 /* 28647 */ "A4_tfrcpp\0"
9444 /* 28657 */ "Y4_tfrscpp\0"
9445 /* 28668 */ "S6_vtrunehb_ppp\0"
9446 /* 28684 */ "S6_vtrunohb_ppp\0"
9447 /* 28700 */ "C2_cmpeqp\0"
9448 /* 28710 */ "M2_vrcmpys_s1rp\0"
9449 /* 28726 */ "S4_extractp_rp\0"
9450 /* 28741 */ "S2_insertp_rp\0"
9451 /* 28755 */ "S2_extractup_rp\0"
9452 /* 28771 */ "S4_extract_rp\0"
9453 /* 28785 */ "S2_insert_rp\0"
9454 /* 28798 */ "S2_extractu_rp\0"
9455 /* 28813 */ "A2_tfrp\0"
9456 /* 28821 */ "A2_orp\0"
9457 /* 28828 */ "A2_xorp\0"
9458 /* 28836 */ "C2_tfrrp\0"
9459 /* 28845 */ "SS2_stored_sp\0"
9460 /* 28859 */ "SL2_loadrd_sp\0"
9461 /* 28873 */ "SL2_loadri_sp\0"
9462 /* 28887 */ "SS2_storew_sp\0"
9463 /* 28901 */ "A2_absp\0"
9464 /* 28909 */ "SA1_addsp\0"
9465 /* 28919 */ "A2_addsp\0"
9466 /* 28928 */ "S2_lfsp\0"
9467 /* 28936 */ "S4_extractp\0"
9468 /* 28948 */ "C2_cmpgtp\0"
9469 /* 28958 */ "S5_popcountp\0"
9470 /* 28971 */ "A2_notp\0"
9471 /* 28979 */ "S2_insertp\0"
9472 /* 28990 */ "M2_mpysu_up\0"
9473 /* 29002 */ "M2_mpyu_up\0"
9474 /* 29013 */ "M2_mpy_up\0"
9475 /* 29023 */ "A2_minup\0"
9476 /* 29032 */ "S2_extractup\0"
9477 /* 29045 */ "C2_cmpgtup\0"
9478 /* 29056 */ "A2_maxup\0"
9479 /* 29065 */ "S2_brevp\0"
9480 /* 29074 */ "A2_maxp\0"
9481 /* 29082 */ "S2_parityp\0"
9482 /* 29093 */ "V6_vwhist256q\0"
9483 /* 29107 */ "V6_vwhist128q\0"
9484 /* 29121 */ "L4_loadd_aq\0"
9485 /* 29133 */ "L2_loadw_aq\0"
9486 /* 29145 */ "V6_vsubbq\0"
9487 /* 29155 */ "V6_vaddbq\0"
9488 /* 29165 */ "A4_cmpbeq\0"
9489 /* 29175 */ "A2_vcmpbeq\0"
9490 /* 29186 */ "A4_cmpheq\0"
9491 /* 29196 */ "A2_vcmpheq\0"
9492 /* 29207 */ "C4_cmpneq\0"
9493 /* 29217 */ "A4_rcmpneq\0"
9494 /* 29228 */ "C2_cmpeq\0"
9495 /* 29237 */ "F2_dfcmpeq\0"
9496 /* 29248 */ "F2_sfcmpeq\0"
9497 /* 29259 */ "A4_rcmpeq\0"
9498 /* 29269 */ "A2_vcmpweq\0"
9499 /* 29280 */ "V6_vsubhq\0"
9500 /* 29290 */ "V6_vaddhq\0"
9501 /* 29300 */ "V6_vgathermhq\0"
9502 /* 29314 */ "V6_vscattermhq\0"
9503 /* 29329 */ "V6_vsubbnq\0"
9504 /* 29340 */ "V6_vaddbnq\0"
9505 /* 29351 */ "V6_vsubhnq\0"
9506 /* 29362 */ "V6_vaddhnq\0"
9507 /* 29373 */ "V6_vsubwnq\0"
9508 /* 29384 */ "V6_vaddwnq\0"
9509 /* 29395 */ "V6_vhistq\0"
9510 /* 29405 */ "V6_vsubwq\0"
9511 /* 29415 */ "V6_vaddwq\0"
9512 /* 29425 */ "V6_vgathermhwq\0"
9513 /* 29440 */ "V6_vscattermhwq\0"
9514 /* 29456 */ "V6_vgathermwq\0"
9515 /* 29470 */ "V6_vscattermwq\0"
9516 /* 29485 */ "J2_loop0r\0"
9517 /* 29495 */ "J2_loop1r\0"
9518 /* 29505 */ "S6_rol_i_r\0"
9519 /* 29516 */ "S2_asl_i_r\0"
9520 /* 29527 */ "S2_asr_i_r\0"
9521 /* 29538 */ "S2_lsr_i_r\0"
9522 /* 29549 */ "PS_tailcall_r\0"
9523 /* 29563 */ "S2_asl_r_r\0"
9524 /* 29574 */ "S2_lsl_r_r\0"
9525 /* 29585 */ "S2_asr_r_r\0"
9526 /* 29596 */ "S2_lsr_r_r\0"
9527 /* 29607 */ "M2_vcmac_s0_sat_r\0"
9528 /* 29625 */ "M2_vcmpy_s0_sat_r\0"
9529 /* 29643 */ "M2_vcmpy_s1_sat_r\0"
9530 /* 29661 */ "S2_togglebit_r\0"
9531 /* 29676 */ "S2_clrbit_r\0"
9532 /* 29688 */ "S2_setbit_r\0"
9533 /* 29700 */ "S2_tstbit_r\0"
9534 /* 29712 */ "S4_ntstbit_r\0"
9535 /* 29725 */ "Y2_icdatar\0"
9536 /* 29736 */ "Y2_tlbr\0"
9537 /* 29744 */ "L2_loadbsw2_pbr\0"
9538 /* 29760 */ "L2_loadbzw2_pbr\0"
9539 /* 29776 */ "L2_loadbsw4_pbr\0"
9540 /* 29792 */ "L2_loadbzw4_pbr\0"
9541 /* 29808 */ "L2_loadalignb_pbr\0"
9542 /* 29826 */ "L2_loadrb_pbr\0"
9543 /* 29840 */ "S2_storerb_pbr\0"
9544 /* 29855 */ "L2_loadrub_pbr\0"
9545 /* 29870 */ "L2_loadrd_pbr\0"
9546 /* 29884 */ "S2_storerd_pbr\0"
9547 /* 29899 */ "S2_storerf_pbr\0"
9548 /* 29914 */ "L2_loadalignh_pbr\0"
9549 /* 29932 */ "L2_loadrh_pbr\0"
9550 /* 29946 */ "S2_storerh_pbr\0"
9551 /* 29961 */ "L2_loadruh_pbr\0"
9552 /* 29976 */ "L2_loadri_pbr\0"
9553 /* 29990 */ "S2_storeri_pbr\0"
9554 /* 30005 */ "S2_storerbnew_pbr\0"
9555 /* 30023 */ "S2_storerhnew_pbr\0"
9556 /* 30041 */ "S2_storerinew_pbr\0"
9557 /* 30059 */ "A2_vavgubr\0"
9558 /* 30070 */ "A2_vnavghcr\0"
9559 /* 30082 */ "A2_vavghcr\0"
9560 /* 30093 */ "L2_loadbsw2_pcr\0"
9561 /* 30109 */ "L2_loadbzw2_pcr\0"
9562 /* 30125 */ "L2_loadbsw4_pcr\0"
9563 /* 30141 */ "L2_loadbzw4_pcr\0"
9564 /* 30157 */ "L2_loadalignb_pcr\0"
9565 /* 30175 */ "L2_loadrb_pcr\0"
9566 /* 30189 */ "PS_loadrb_pcr\0"
9567 /* 30203 */ "S2_storerb_pcr\0"
9568 /* 30218 */ "PS_storerb_pcr\0"
9569 /* 30233 */ "L2_loadrub_pcr\0"
9570 /* 30248 */ "PS_loadrub_pcr\0"
9571 /* 30263 */ "L2_loadrd_pcr\0"
9572 /* 30277 */ "PS_loadrd_pcr\0"
9573 /* 30291 */ "S2_storerd_pcr\0"
9574 /* 30306 */ "PS_storerd_pcr\0"
9575 /* 30321 */ "S2_storerf_pcr\0"
9576 /* 30336 */ "PS_storerf_pcr\0"
9577 /* 30351 */ "L2_loadalignh_pcr\0"
9578 /* 30369 */ "L2_loadrh_pcr\0"
9579 /* 30383 */ "PS_loadrh_pcr\0"
9580 /* 30397 */ "S2_storerh_pcr\0"
9581 /* 30412 */ "PS_storerh_pcr\0"
9582 /* 30427 */ "L2_loadruh_pcr\0"
9583 /* 30442 */ "PS_loadruh_pcr\0"
9584 /* 30457 */ "L2_loadri_pcr\0"
9585 /* 30471 */ "PS_loadri_pcr\0"
9586 /* 30485 */ "S2_storeri_pcr\0"
9587 /* 30500 */ "PS_storeri_pcr\0"
9588 /* 30515 */ "S2_storerbnew_pcr\0"
9589 /* 30533 */ "S2_storerhnew_pcr\0"
9590 /* 30551 */ "S2_storerinew_pcr\0"
9591 /* 30569 */ "G4_tfrgrcr\0"
9592 /* 30580 */ "A2_tfrrcr\0"
9593 /* 30590 */ "Y2_tfrsrcr\0"
9594 /* 30601 */ "A2_vnavgwcr\0"
9595 /* 30613 */ "A2_vavgwcr\0"
9596 /* 30624 */ "M4_mpyri_addr\0"
9597 /* 30638 */ "M4_mpyrr_addr\0"
9598 /* 30652 */ "Y2_barrier\0"
9599 /* 30663 */ "SA1_tfr\0"
9600 /* 30671 */ "dup_A2_tfr\0"
9601 /* 30682 */ "Y4_l2tagr\0"
9602 /* 30692 */ "Y2_dctagr\0"
9603 /* 30702 */ "Y2_ictagr\0"
9604 /* 30712 */ "S4_vxaddsubhr\0"
9605 /* 30726 */ "S4_vxsubaddhr\0"
9606 /* 30740 */ "A2_vnavghr\0"
9607 /* 30751 */ "A2_vavghr\0"
9608 /* 30761 */ "A2_vavguhr\0"
9609 /* 30772 */ "dup_A2_andir\0"
9610 /* 30785 */ "dup_A4_combineir\0"
9611 /* 30802 */ "A2_orir\0"
9612 /* 30810 */ "C2_muxir\0"
9613 /* 30819 */ "C2_bitsclr\0"
9614 /* 30830 */ "C4_nbitsclr\0"
9615 /* 30842 */ "J2_callr\0"
9616 /* 30851 */ "PS_call_nr\0"
9617 /* 30862 */ "PS_callr_nr\0"
9618 /* 30874 */ "Y2_iassignr\0"
9619 /* 30886 */ "A2_or\0"
9620 /* 30892 */ "C2_or\0"
9621 /* 30898 */ "V6_veqb_or\0"
9622 /* 30909 */ "V6_vgtb_or\0"
9623 /* 30920 */ "V6_vgtub_or\0"
9624 /* 30932 */ "V6_pred_or\0"
9625 /* 30943 */ "C4_and_or\0"
9626 /* 30953 */ "M4_and_or\0"
9627 /* 30963 */ "V6_vgtbf_or\0"
9628 /* 30975 */ "V6_vgthf_or\0"
9629 /* 30987 */ "V6_vgtsf_or\0"
9630 /* 30999 */ "V6_veqh_or\0"
9631 /* 31010 */ "V6_vgth_or\0"
9632 /* 31021 */ "V6_vgtuh_or\0"
9633 /* 31033 */ "S6_rol_i_p_or\0"
9634 /* 31047 */ "S2_asl_i_p_or\0"
9635 /* 31061 */ "S2_asr_i_p_or\0"
9636 /* 31075 */ "S2_lsr_i_p_or\0"
9637 /* 31089 */ "S2_asl_r_p_or\0"
9638 /* 31103 */ "S2_lsl_r_p_or\0"
9639 /* 31117 */ "S2_asr_r_p_or\0"
9640 /* 31131 */ "S2_lsr_r_p_or\0"
9641 /* 31145 */ "S6_rol_i_r_or\0"
9642 /* 31159 */ "S2_asl_i_r_or\0"
9643 /* 31173 */ "S2_asr_i_r_or\0"
9644 /* 31187 */ "S2_lsr_i_r_or\0"
9645 /* 31201 */ "S2_asl_r_r_or\0"
9646 /* 31215 */ "S2_lsl_r_r_or\0"
9647 /* 31229 */ "S2_asr_r_r_or\0"
9648 /* 31243 */ "S2_lsr_r_r_or\0"
9649 /* 31257 */ "C4_or_or\0"
9650 /* 31266 */ "M4_or_or\0"
9651 /* 31275 */ "M4_xor_or\0"
9652 /* 31285 */ "V6_veqw_or\0"
9653 /* 31296 */ "V6_vgtw_or\0"
9654 /* 31307 */ "V6_vgtuw_or\0"
9655 /* 31319 */ "V6_MAP_equb_ior\0"
9656 /* 31335 */ "V6_MAP_equh_ior\0"
9657 /* 31351 */ "V6_MAP_equw_ior\0"
9658 /* 31367 */ "V6_vror\0"
9659 /* 31375 */ "V6_vor\0"
9660 /* 31382 */ "A2_xor\0"
9661 /* 31389 */ "C2_xor\0"
9662 /* 31396 */ "V6_veqb_xor\0"
9663 /* 31408 */ "V6_vgtb_xor\0"
9664 /* 31420 */ "V6_MAP_equb_xor\0"
9665 /* 31436 */ "V6_vgtub_xor\0"
9666 /* 31449 */ "V6_pred_xor\0"
9667 /* 31461 */ "M4_and_xor\0"
9668 /* 31472 */ "V6_vgtbf_xor\0"
9669 /* 31485 */ "V6_vgthf_xor\0"
9670 /* 31498 */ "V6_vgtsf_xor\0"
9671 /* 31511 */ "V6_veqh_xor\0"
9672 /* 31523 */ "V6_vgth_xor\0"
9673 /* 31535 */ "V6_MAP_equh_xor\0"
9674 /* 31551 */ "V6_vgtuh_xor\0"
9675 /* 31564 */ "S2_asl_r_p_xor\0"
9676 /* 31579 */ "S2_lsl_r_p_xor\0"
9677 /* 31594 */ "S2_asr_r_p_xor\0"
9678 /* 31609 */ "S2_lsr_r_p_xor\0"
9679 /* 31624 */ "M4_or_xor\0"
9680 /* 31634 */ "V6_veqw_xor\0"
9681 /* 31646 */ "V6_vgtw_xor\0"
9682 /* 31658 */ "V6_MAP_equw_xor\0"
9683 /* 31674 */ "V6_vgtuw_xor\0"
9684 /* 31687 */ "V6_vxor\0"
9685 /* 31695 */ "L2_loadbsw2_pr\0"
9686 /* 31710 */ "L2_loadbzw2_pr\0"
9687 /* 31725 */ "L2_loadbsw4_pr\0"
9688 /* 31740 */ "L2_loadbzw4_pr\0"
9689 /* 31755 */ "L2_loadalignb_pr\0"
9690 /* 31772 */ "L2_loadrb_pr\0"
9691 /* 31785 */ "S2_storerb_pr\0"
9692 /* 31799 */ "L2_loadrub_pr\0"
9693 /* 31813 */ "L2_loadrd_pr\0"
9694 /* 31826 */ "S2_storerd_pr\0"
9695 /* 31840 */ "S2_storerf_pr\0"
9696 /* 31854 */ "L2_loadalignh_pr\0"
9697 /* 31871 */ "L2_loadrh_pr\0"
9698 /* 31884 */ "S2_storerh_pr\0"
9699 /* 31898 */ "L2_loadruh_pr\0"
9700 /* 31912 */ "L2_loadri_pr\0"
9701 /* 31925 */ "S2_storeri_pr\0"
9702 /* 31939 */ "S2_storerbnew_pr\0"
9703 /* 31956 */ "S2_storerhnew_pr\0"
9704 /* 31973 */ "S2_storerinew_pr\0"
9705 /* 31990 */ "J2_jumpr\0"
9706 /* 31999 */ "J4_hintjumpr\0"
9707 /* 32012 */ "C2_tfrpr\0"
9708 /* 32021 */ "F2_sffixupr\0"
9709 /* 32033 */ "L4_loadrb_rr\0"
9710 /* 32046 */ "S4_storerb_rr\0"
9711 /* 32060 */ "L4_loadrub_rr\0"
9712 /* 32074 */ "A7_croundd_rr\0"
9713 /* 32088 */ "A4_round_rr\0"
9714 /* 32100 */ "A4_cround_rr\0"
9715 /* 32113 */ "L4_loadrd_rr\0"
9716 /* 32126 */ "S4_storerd_rr\0"
9717 /* 32140 */ "L4_ploadrbf_rr\0"
9718 /* 32155 */ "S4_pstorerbf_rr\0"
9719 /* 32171 */ "L4_ploadrubf_rr\0"
9720 /* 32187 */ "L4_ploadrdf_rr\0"
9721 /* 32202 */ "S4_pstorerdf_rr\0"
9722 /* 32218 */ "S4_pstorerff_rr\0"
9723 /* 32234 */ "L4_ploadrhf_rr\0"
9724 /* 32249 */ "S4_pstorerhf_rr\0"
9725 /* 32265 */ "L4_ploadruhf_rr\0"
9726 /* 32281 */ "L4_ploadrif_rr\0"
9727 /* 32296 */ "S4_pstorerif_rr\0"
9728 /* 32312 */ "S4_storerf_rr\0"
9729 /* 32326 */ "S4_pstorerbnewf_rr\0"
9730 /* 32345 */ "S4_pstorerhnewf_rr\0"
9731 /* 32364 */ "S4_pstorerinewf_rr\0"
9732 /* 32383 */ "L4_loadrh_rr\0"
9733 /* 32396 */ "S4_storerh_rr\0"
9734 /* 32410 */ "L4_loadruh_rr\0"
9735 /* 32424 */ "L4_loadri_rr\0"
9736 /* 32437 */ "S4_storeri_rr\0"
9737 /* 32451 */ "L4_ploadrbt_rr\0"
9738 /* 32466 */ "S4_pstorerbt_rr\0"
9739 /* 32482 */ "L4_ploadrubt_rr\0"
9740 /* 32498 */ "L4_ploadrdt_rr\0"
9741 /* 32513 */ "S4_pstorerdt_rr\0"
9742 /* 32529 */ "S4_pstorerft_rr\0"
9743 /* 32545 */ "L4_ploadrht_rr\0"
9744 /* 32560 */ "S4_pstorerht_rr\0"
9745 /* 32576 */ "L4_ploadruht_rr\0"
9746 /* 32592 */ "L4_ploadrit_rr\0"
9747 /* 32607 */ "S4_pstorerit_rr\0"
9748 /* 32623 */ "S4_pstorerbnewt_rr\0"
9749 /* 32642 */ "S4_pstorerhnewt_rr\0"
9750 /* 32661 */ "S4_pstorerinewt_rr\0"
9751 /* 32680 */ "S4_storerbnew_rr\0"
9752 /* 32697 */ "L4_ploadrbfnew_rr\0"
9753 /* 32715 */ "S4_pstorerbfnew_rr\0"
9754 /* 32734 */ "L4_ploadrubfnew_rr\0"
9755 /* 32753 */ "L4_ploadrdfnew_rr\0"
9756 /* 32771 */ "S4_pstorerdfnew_rr\0"
9757 /* 32790 */ "S4_pstorerffnew_rr\0"
9758 /* 32809 */ "L4_ploadrhfnew_rr\0"
9759 /* 32827 */ "S4_pstorerhfnew_rr\0"
9760 /* 32846 */ "L4_ploadruhfnew_rr\0"
9761 /* 32865 */ "L4_ploadrifnew_rr\0"
9762 /* 32883 */ "S4_pstorerifnew_rr\0"
9763 /* 32902 */ "S4_pstorerbnewfnew_rr\0"
9764 /* 32924 */ "S4_pstorerhnewfnew_rr\0"
9765 /* 32946 */ "S4_pstorerinewfnew_rr\0"
9766 /* 32968 */ "S4_storerhnew_rr\0"
9767 /* 32985 */ "S4_storerinew_rr\0"
9768 /* 33002 */ "L4_ploadrbtnew_rr\0"
9769 /* 33020 */ "S4_pstorerbtnew_rr\0"
9770 /* 33039 */ "L4_ploadrubtnew_rr\0"
9771 /* 33058 */ "L4_ploadrdtnew_rr\0"
9772 /* 33076 */ "S4_pstorerdtnew_rr\0"
9773 /* 33095 */ "S4_pstorerftnew_rr\0"
9774 /* 33114 */ "L4_ploadrhtnew_rr\0"
9775 /* 33132 */ "S4_pstorerhtnew_rr\0"
9776 /* 33151 */ "L4_ploadruhtnew_rr\0"
9777 /* 33170 */ "L4_ploadritnew_rr\0"
9778 /* 33188 */ "S4_pstoreritnew_rr\0"
9779 /* 33207 */ "S4_pstorerbnewtnew_rr\0"
9780 /* 33229 */ "S4_pstorerhnewtnew_rr\0"
9781 /* 33251 */ "S4_pstorerinewtnew_rr\0"
9782 /* 33273 */ "G4_tfrgcrr\0"
9783 /* 33284 */ "A2_tfrcrr\0"
9784 /* 33294 */ "Y2_tfrscrr\0"
9785 /* 33305 */ "J2_ploop1sr\0"
9786 /* 33317 */ "J2_ploop2sr\0"
9787 /* 33329 */ "J2_ploop3sr\0"
9788 /* 33341 */ "LDriw_ctr\0"
9789 /* 33351 */ "STriw_ctr\0"
9790 /* 33361 */ "J4_jumpsetr\0"
9791 /* 33373 */ "V6_vrotr\0"
9792 /* 33382 */ "L4_loadbsw2_ur\0"
9793 /* 33397 */ "L4_loadbzw2_ur\0"
9794 /* 33412 */ "L4_loadbsw4_ur\0"
9795 /* 33427 */ "L4_loadbzw4_ur\0"
9796 /* 33442 */ "L4_loadalignb_ur\0"
9797 /* 33459 */ "L4_loadrb_ur\0"
9798 /* 33472 */ "S4_storerb_ur\0"
9799 /* 33486 */ "L4_loadrub_ur\0"
9800 /* 33500 */ "L4_loadrd_ur\0"
9801 /* 33513 */ "S4_storerd_ur\0"
9802 /* 33527 */ "S4_storerf_ur\0"
9803 /* 33541 */ "L4_loadalignh_ur\0"
9804 /* 33558 */ "L4_loadrh_ur\0"
9805 /* 33571 */ "S4_storerh_ur\0"
9806 /* 33585 */ "L4_loadruh_ur\0"
9807 /* 33599 */ "L4_loadri_ur\0"
9808 /* 33612 */ "S4_storeri_ur\0"
9809 /* 33626 */ "S4_storerbnew_ur\0"
9810 /* 33643 */ "S4_storerhnew_ur\0"
9811 /* 33660 */ "S4_storerinew_ur\0"
9812 /* 33677 */ "A2_vnavgwr\0"
9813 /* 33688 */ "A2_vavgwr\0"
9814 /* 33698 */ "V6_vinsertwr\0"
9815 /* 33711 */ "A2_vavguwr\0"
9816 /* 33722 */ "SA1_combinezr\0"
9817 /* 33736 */ "A2_abs\0"
9818 /* 33743 */ "L4_ploadrbf_abs\0"
9819 /* 33759 */ "S4_pstorerbf_abs\0"
9820 /* 33776 */ "L4_ploadrubf_abs\0"
9821 /* 33793 */ "L4_ploadrdf_abs\0"
9822 /* 33809 */ "S4_pstorerdf_abs\0"
9823 /* 33826 */ "S4_pstorerff_abs\0"
9824 /* 33843 */ "L4_ploadrhf_abs\0"
9825 /* 33859 */ "S4_pstorerhf_abs\0"
9826 /* 33876 */ "L4_ploadruhf_abs\0"
9827 /* 33893 */ "L4_ploadrif_abs\0"
9828 /* 33909 */ "S4_pstorerif_abs\0"
9829 /* 33926 */ "S4_pstorerbnewf_abs\0"
9830 /* 33946 */ "S4_pstorerhnewf_abs\0"
9831 /* 33966 */ "S4_pstorerinewf_abs\0"
9832 /* 33986 */ "L4_ploadrbt_abs\0"
9833 /* 34002 */ "S4_pstorerbt_abs\0"
9834 /* 34019 */ "L4_ploadrubt_abs\0"
9835 /* 34036 */ "L4_ploadrdt_abs\0"
9836 /* 34052 */ "S4_pstorerdt_abs\0"
9837 /* 34069 */ "S4_pstorerft_abs\0"
9838 /* 34086 */ "L4_ploadrht_abs\0"
9839 /* 34102 */ "S4_pstorerht_abs\0"
9840 /* 34119 */ "L4_ploadruht_abs\0"
9841 /* 34136 */ "L4_ploadrit_abs\0"
9842 /* 34152 */ "S4_pstorerit_abs\0"
9843 /* 34169 */ "S4_pstorerbnewt_abs\0"
9844 /* 34189 */ "S4_pstorerhnewt_abs\0"
9845 /* 34209 */ "S4_pstorerinewt_abs\0"
9846 /* 34229 */ "L4_ploadrbfnew_abs\0"
9847 /* 34248 */ "S4_pstorerbfnew_abs\0"
9848 /* 34268 */ "L4_ploadrubfnew_abs\0"
9849 /* 34288 */ "L4_ploadrdfnew_abs\0"
9850 /* 34307 */ "S4_pstorerdfnew_abs\0"
9851 /* 34327 */ "S4_pstorerffnew_abs\0"
9852 /* 34347 */ "L4_ploadrhfnew_abs\0"
9853 /* 34366 */ "S4_pstorerhfnew_abs\0"
9854 /* 34386 */ "L4_ploadruhfnew_abs\0"
9855 /* 34406 */ "L4_ploadrifnew_abs\0"
9856 /* 34425 */ "S4_pstorerifnew_abs\0"
9857 /* 34445 */ "S4_pstorerbnewfnew_abs\0"
9858 /* 34468 */ "S4_pstorerhnewfnew_abs\0"
9859 /* 34491 */ "S4_pstorerinewfnew_abs\0"
9860 /* 34514 */ "L4_ploadrbtnew_abs\0"
9861 /* 34533 */ "S4_pstorerbtnew_abs\0"
9862 /* 34553 */ "L4_ploadrubtnew_abs\0"
9863 /* 34573 */ "L4_ploadrdtnew_abs\0"
9864 /* 34592 */ "S4_pstorerdtnew_abs\0"
9865 /* 34612 */ "S4_pstorerftnew_abs\0"
9866 /* 34632 */ "L4_ploadrhtnew_abs\0"
9867 /* 34651 */ "S4_pstorerhtnew_abs\0"
9868 /* 34671 */ "L4_ploadruhtnew_abs\0"
9869 /* 34691 */ "L4_ploadritnew_abs\0"
9870 /* 34710 */ "S4_pstoreritnew_abs\0"
9871 /* 34730 */ "S4_pstorerbnewtnew_abs\0"
9872 /* 34753 */ "S4_pstorerhnewtnew_abs\0"
9873 /* 34776 */ "S4_pstorerinewtnew_abs\0"
9874 /* 34799 */ "PS_loadrbabs\0"
9875 /* 34812 */ "PS_storerbabs\0"
9876 /* 34826 */ "PS_loadrubabs\0"
9877 /* 34840 */ "PS_loadrdabs\0"
9878 /* 34853 */ "PS_storerdabs\0"
9879 /* 34867 */ "PS_storerfabs\0"
9880 /* 34881 */ "PS_loadrhabs\0"
9881 /* 34894 */ "PS_storerhabs\0"
9882 /* 34908 */ "PS_loadruhabs\0"
9883 /* 34922 */ "PS_loadriabs\0"
9884 /* 34935 */ "PS_storeriabs\0"
9885 /* 34949 */ "PS_storerbnewabs\0"
9886 /* 34966 */ "PS_storerhnewabs\0"
9887 /* 34983 */ "PS_storerinewabs\0"
9888 /* 35000 */ "A2_vsububs\0"
9889 /* 35011 */ "A2_vaddubs\0"
9890 /* 35022 */ "A5_vaddhubs\0"
9891 /* 35034 */ "M2_vmac2es\0"
9892 /* 35045 */ "A2_vsubhs\0"
9893 /* 35055 */ "A2_svsubhs\0"
9894 /* 35066 */ "A2_vaddhs\0"
9895 /* 35076 */ "A2_svaddhs\0"
9896 /* 35087 */ "A2_svavghs\0"
9897 /* 35098 */ "A2_vsubuhs\0"
9898 /* 35109 */ "A2_svsubuhs\0"
9899 /* 35121 */ "A2_vadduhs\0"
9900 /* 35132 */ "A2_svadduhs\0"
9901 /* 35144 */ "S2_vrndpackwhs\0"
9902 /* 35159 */ "F2_sffms\0"
9903 /* 35168 */ "V6_vmpyhsrs\0"
9904 /* 35180 */ "V6_vmpyhvsrs\0"
9905 /* 35193 */ "F2_dfclass\0"
9906 /* 35204 */ "F2_sfclass\0"
9907 /* 35215 */ "V6_vmpyhss\0"
9908 /* 35226 */ "V6_vmpabus\0"
9909 /* 35237 */ "V6_vdmpybus\0"
9910 /* 35249 */ "V6_vrmpybus\0"
9911 /* 35261 */ "V6_vtmpybus\0"
9912 /* 35273 */ "V6_vmpybus\0"
9913 /* 35284 */ "V6_vmpyhus\0"
9914 /* 35295 */ "V6_vmpyuhvs\0"
9915 /* 35307 */ "A2_vsubws\0"
9916 /* 35317 */ "A2_vaddws\0"
9917 /* 35327 */ "L4_loadw_phys\0"
9918 /* 35341 */ "SL2_jumpr31_t\0"
9919 /* 35355 */ "SL2_return_t\0"
9920 /* 35368 */ "L4_return_t\0"
9921 /* 35380 */ "J4_tstbit0_fp0_jump_t\0"
9922 /* 35402 */ "J4_cmpeqn1_fp0_jump_t\0"
9923 /* 35424 */ "J4_cmpgtn1_fp0_jump_t\0"
9924 /* 35446 */ "J4_cmpeqi_fp0_jump_t\0"
9925 /* 35467 */ "J4_cmpgti_fp0_jump_t\0"
9926 /* 35488 */ "J4_cmpgtui_fp0_jump_t\0"
9927 /* 35510 */ "J4_cmpeq_fp0_jump_t\0"
9928 /* 35530 */ "J4_cmpgt_fp0_jump_t\0"
9929 /* 35550 */ "J4_cmpgtu_fp0_jump_t\0"
9930 /* 35571 */ "J4_tstbit0_tp0_jump_t\0"
9931 /* 35593 */ "J4_cmpeqn1_tp0_jump_t\0"
9932 /* 35615 */ "J4_cmpgtn1_tp0_jump_t\0"
9933 /* 35637 */ "J4_cmpeqi_tp0_jump_t\0"
9934 /* 35658 */ "J4_cmpgti_tp0_jump_t\0"
9935 /* 35679 */ "J4_cmpgtui_tp0_jump_t\0"
9936 /* 35701 */ "J4_cmpeq_tp0_jump_t\0"
9937 /* 35721 */ "J4_cmpgt_tp0_jump_t\0"
9938 /* 35741 */ "J4_cmpgtu_tp0_jump_t\0"
9939 /* 35762 */ "J4_tstbit0_fp1_jump_t\0"
9940 /* 35784 */ "J4_cmpeqn1_fp1_jump_t\0"
9941 /* 35806 */ "J4_cmpgtn1_fp1_jump_t\0"
9942 /* 35828 */ "J4_cmpeqi_fp1_jump_t\0"
9943 /* 35849 */ "J4_cmpgti_fp1_jump_t\0"
9944 /* 35870 */ "J4_cmpgtui_fp1_jump_t\0"
9945 /* 35892 */ "J4_cmpeq_fp1_jump_t\0"
9946 /* 35912 */ "J4_cmpgt_fp1_jump_t\0"
9947 /* 35932 */ "J4_cmpgtu_fp1_jump_t\0"
9948 /* 35953 */ "J4_tstbit0_tp1_jump_t\0"
9949 /* 35975 */ "J4_cmpeqn1_tp1_jump_t\0"
9950 /* 35997 */ "J4_cmpgtn1_tp1_jump_t\0"
9951 /* 36019 */ "J4_cmpeqi_tp1_jump_t\0"
9952 /* 36040 */ "J4_cmpgti_tp1_jump_t\0"
9953 /* 36061 */ "J4_cmpgtui_tp1_jump_t\0"
9954 /* 36083 */ "J4_cmpeq_tp1_jump_t\0"
9955 /* 36103 */ "J4_cmpgt_tp1_jump_t\0"
9956 /* 36123 */ "J4_cmpgtu_tp1_jump_t\0"
9957 /* 36144 */ "J4_tstbit0_f_jumpnv_t\0"
9958 /* 36166 */ "J4_cmpeqn1_f_jumpnv_t\0"
9959 /* 36188 */ "J4_cmpgtn1_f_jumpnv_t\0"
9960 /* 36210 */ "J4_cmpeqi_f_jumpnv_t\0"
9961 /* 36231 */ "J4_cmpgti_f_jumpnv_t\0"
9962 /* 36252 */ "J4_cmpgtui_f_jumpnv_t\0"
9963 /* 36274 */ "J4_cmpeq_f_jumpnv_t\0"
9964 /* 36294 */ "J4_cmpgt_f_jumpnv_t\0"
9965 /* 36314 */ "J4_cmplt_f_jumpnv_t\0"
9966 /* 36334 */ "J4_cmpgtu_f_jumpnv_t\0"
9967 /* 36355 */ "J4_cmpltu_f_jumpnv_t\0"
9968 /* 36376 */ "J4_tstbit0_t_jumpnv_t\0"
9969 /* 36398 */ "J4_cmpeqn1_t_jumpnv_t\0"
9970 /* 36420 */ "J4_cmpgtn1_t_jumpnv_t\0"
9971 /* 36442 */ "J4_cmpeqi_t_jumpnv_t\0"
9972 /* 36463 */ "J4_cmpgti_t_jumpnv_t\0"
9973 /* 36484 */ "J4_cmpgtui_t_jumpnv_t\0"
9974 /* 36506 */ "J4_cmpeq_t_jumpnv_t\0"
9975 /* 36526 */ "J4_cmpgt_t_jumpnv_t\0"
9976 /* 36546 */ "J4_cmplt_t_jumpnv_t\0"
9977 /* 36566 */ "J4_cmpgtu_t_jumpnv_t\0"
9978 /* 36587 */ "J4_cmpltu_t_jumpnv_t\0"
9979 /* 36608 */ "L4_return_map_to_raw_t\0"
9980 /* 36631 */ "M4_mac_up_s1_sat\0"
9981 /* 36648 */ "M4_nac_up_s1_sat\0"
9982 /* 36665 */ "M2_mpy_up_s1_sat\0"
9983 /* 36682 */ "A2_sat\0"
9984 /* 36689 */ "V6_vwhist256_sat\0"
9985 /* 36706 */ "V6_vsubububb_sat\0"
9986 /* 36723 */ "V6_vaddububb_sat\0"
9987 /* 36740 */ "V6_vpackhb_sat\0"
9988 /* 36755 */ "V6_vabsb_sat\0"
9989 /* 36768 */ "V6_vpackhub_sat\0"
9990 /* 36784 */ "S5_asrhub_sat\0"
9991 /* 36798 */ "S5_asrhub_rnd_sat\0"
9992 /* 36816 */ "V6_vabsh_sat\0"
9993 /* 36829 */ "V6_vpackwuh_sat\0"
9994 /* 36845 */ "V6_vpackwh_sat\0"
9995 /* 36860 */ "A4_round_ri_sat\0"
9996 /* 36876 */ "V6_vwhist256q_sat\0"
9997 /* 36894 */ "S2_asl_i_r_sat\0"
9998 /* 36909 */ "S2_asl_r_r_sat\0"
9999 /* 36924 */ "S2_asr_r_r_sat\0"
10000 /* 36939 */ "A4_round_rr_sat\0"
10001 /* 36955 */ "V6_vabsw_sat\0"
10002 /* 36968 */ "V6_vsubbsat\0"
10003 /* 36980 */ "V6_vaddbsat\0"
10004 /* 36992 */ "V6_vasrhbsat\0"
10005 /* 37005 */ "V6_vsububsat\0"
10006 /* 37018 */ "V6_vaddubsat\0"
10007 /* 37031 */ "V6_vasrhubsat\0"
10008 /* 37045 */ "V6_vasruhubsat\0"
10009 /* 37060 */ "V6_vasrvuhubsat\0"
10010 /* 37076 */ "dep_A2_subsat\0"
10011 /* 37090 */ "dep_A2_addsat\0"
10012 /* 37104 */ "V6_vasrhbrndsat\0"
10013 /* 37120 */ "V6_vasrhubrndsat\0"
10014 /* 37137 */ "V6_vasruhubrndsat\0"
10015 /* 37155 */ "V6_vasrvuhubrndsat\0"
10016 /* 37174 */ "V6_vasrwuhrndsat\0"
10017 /* 37191 */ "V6_vasruwuhrndsat\0"
10018 /* 37209 */ "V6_vasrvwuhrndsat\0"
10019 /* 37227 */ "V6_vasrwhrndsat\0"
10020 /* 37243 */ "A2_roundsat\0"
10021 /* 37255 */ "A2_negsat\0"
10022 /* 37265 */ "V6_vsubhsat\0"
10023 /* 37277 */ "V6_vaddhsat\0"
10024 /* 37289 */ "V6_vmpahhsat\0"
10025 /* 37302 */ "A2_vabshsat\0"
10026 /* 37314 */ "V6_vsubuhsat\0"
10027 /* 37327 */ "V6_vadduhsat\0"
10028 /* 37340 */ "V6_vmpauhuhsat\0"
10029 /* 37355 */ "V6_vmpsuhuhsat\0"
10030 /* 37370 */ "V6_vasrwuhsat\0"
10031 /* 37384 */ "V6_vasruwuhsat\0"
10032 /* 37399 */ "V6_vasrvwuhsat\0"
10033 /* 37414 */ "V6_vasrwhsat\0"
10034 /* 37427 */ "V6_vdmpyhsat\0"
10035 /* 37440 */ "V6_vdmpyhisat\0"
10036 /* 37454 */ "V6_vdmpyhsuisat\0"
10037 /* 37470 */ "A2_addpsat\0"
10038 /* 37481 */ "A2_abssat\0"
10039 /* 37491 */ "V6_vdmpyhsusat\0"
10040 /* 37506 */ "V6_vdmpyhvsat\0"
10041 /* 37520 */ "V6_vsubwsat\0"
10042 /* 37532 */ "V6_vaddwsat\0"
10043 /* 37544 */ "A2_vabswsat\0"
10044 /* 37556 */ "V6_vsubuwsat\0"
10045 /* 37569 */ "V6_vadduwsat\0"
10046 /* 37582 */ "V6_vaddcarrysat\0"
10047 /* 37598 */ "A4_psxtbt\0"
10048 /* 37608 */ "A4_pzxtbt\0"
10049 /* 37618 */ "A2_psubt\0"
10050 /* 37627 */ "S4_extract\0"
10051 /* 37638 */ "V6_zextract\0"
10052 /* 37650 */ "PS_pselect\0"
10053 /* 37661 */ "PS_vselect\0"
10054 /* 37672 */ "PS_wselect\0"
10055 /* 37683 */ "A2_paddt\0"
10056 /* 37692 */ "A2_pandt\0"
10057 /* 37701 */ "PS_jmpret\0"
10058 /* 37711 */ "C2_bitsset\0"
10059 /* 37722 */ "C4_nbitsset\0"
10060 /* 37734 */ "A4_cmpbgt\0"
10061 /* 37744 */ "A4_vcmpbgt\0"
10062 /* 37755 */ "A4_cmphgt\0"
10063 /* 37765 */ "A2_vcmphgt\0"
10064 /* 37776 */ "C2_cmpgt\0"
10065 /* 37785 */ "F2_dfcmpgt\0"
10066 /* 37796 */ "F2_sfcmpgt\0"
10067 /* 37807 */ "A2_vcmpwgt\0"
10068 /* 37818 */ "Y2_syncht\0"
10069 /* 37828 */ "A4_paslht\0"
10070 /* 37838 */ "A4_pasrht\0"
10071 /* 37848 */ "A4_psxtht\0"
10072 /* 37858 */ "A4_pzxtht\0"
10073 /* 37868 */ "Y2_wait\0"
10074 /* 37876 */ "Y6_dmwait\0"
10075 /* 37886 */ "A2_paddit\0"
10076 /* 37896 */ "dup_C2_cmoveit\0"
10077 /* 37911 */ "A4_bitsplit\0"
10078 /* 37923 */ "dup_C2_cmovenewit\0"
10079 /* 37941 */ "V6_v6mpyhubs10_alt\0"
10080 /* 37960 */ "V6_v6mpyvubs10_alt\0"
10081 /* 37979 */ "V6_vsubb_alt\0"
10082 /* 37992 */ "V6_vaddb_alt\0"
10083 /* 38005 */ "V6_vshuffeb_alt\0"
10084 /* 38021 */ "V6_vpackeb_alt\0"
10085 /* 38036 */ "V6_vshufoeb_alt\0"
10086 /* 38052 */ "V6_vshuffb_alt\0"
10087 /* 38067 */ "V6_vnavgb_alt\0"
10088 /* 38081 */ "V6_vavgb_alt\0"
10089 /* 38094 */ "V6_vmpahb_alt\0"
10090 /* 38108 */ "V6_vroundhb_alt\0"
10091 /* 38124 */ "V6_vmpyihb_alt\0"
10092 /* 38139 */ "V6_vmpauhb_alt\0"
10093 /* 38154 */ "V6_vdmpyhb_alt\0"
10094 /* 38169 */ "V6_vtmpyhb_alt\0"
10095 /* 38184 */ "V6_vunpackb_alt\0"
10096 /* 38200 */ "V6_vdealb_alt\0"
10097 /* 38214 */ "V6_vminb_alt\0"
10098 /* 38227 */ "V6_vshuffob_alt\0"
10099 /* 38243 */ "V6_vunpackob_alt\0"
10100 /* 38260 */ "V6_vpackob_alt\0"
10101 /* 38275 */ "V6_vabsb_alt\0"
10102 /* 38288 */ "V6_vsb_alt\0"
10103 /* 38299 */ "V6_vabsdiffub_alt\0"
10104 /* 38317 */ "V6_vnavgub_alt\0"
10105 /* 38332 */ "V6_vavgub_alt\0"
10106 /* 38346 */ "V6_vroundhub_alt\0"
10107 /* 38363 */ "V6_vsathub_alt\0"
10108 /* 38378 */ "V6_vrounduhub_alt\0"
10109 /* 38396 */ "V6_vunpackub_alt\0"
10110 /* 38413 */ "V6_vminub_alt\0"
10111 /* 38427 */ "V6_vabsub_alt\0"
10112 /* 38441 */ "V6_vmpyiwub_alt\0"
10113 /* 38457 */ "V6_vmaxub_alt\0"
10114 /* 38471 */ "V6_vrmpyub_alt\0"
10115 /* 38486 */ "V6_vmpyub_alt\0"
10116 /* 38500 */ "V6_vmpyiwb_alt\0"
10117 /* 38515 */ "V6_vmaxb_alt\0"
10118 /* 38528 */ "V6_vtmpyb_alt\0"
10119 /* 38542 */ "V6_vzb_alt\0"
10120 /* 38553 */ "V6_vmpahb_acc_alt\0"
10121 /* 38571 */ "V6_vmpyihb_acc_alt\0"
10122 /* 38590 */ "V6_vmpauhb_acc_alt\0"
10123 /* 38609 */ "V6_vdmpyhb_acc_alt\0"
10124 /* 38628 */ "V6_vtmpyhb_acc_alt\0"
10125 /* 38647 */ "V6_vmpyiwub_acc_alt\0"
10126 /* 38667 */ "V6_vrmpyub_acc_alt\0"
10127 /* 38686 */ "V6_vmpyub_acc_alt\0"
10128 /* 38704 */ "V6_vmpyiwb_acc_alt\0"
10129 /* 38723 */ "V6_vtmpyb_acc_alt\0"
10130 /* 38741 */ "V6_vaddubh_acc_alt\0"
10131 /* 38760 */ "V6_vmpyih_acc_alt\0"
10132 /* 38778 */ "V6_vaslh_acc_alt\0"
10133 /* 38795 */ "V6_vasrh_acc_alt\0"
10134 /* 38812 */ "V6_vdsaduh_acc_alt\0"
10135 /* 38831 */ "V6_vmpyiewuh_acc_alt\0"
10136 /* 38852 */ "V6_vmpyuh_acc_alt\0"
10137 /* 38870 */ "V6_vmpyiewh_acc_alt\0"
10138 /* 38890 */ "V6_vmpyiwh_acc_alt\0"
10139 /* 38909 */ "V6_vmpyh_acc_alt\0"
10140 /* 38926 */ "V6_vrsadubi_acc_alt\0"
10141 /* 38946 */ "V6_vrmpyubi_acc_alt\0"
10142 /* 38966 */ "V6_vrmpybusi_acc_alt\0"
10143 /* 38987 */ "V6_vmpabus_acc_alt\0"
10144 /* 39006 */ "V6_vdmpybus_acc_alt\0"
10145 /* 39026 */ "V6_vrmpybus_acc_alt\0"
10146 /* 39046 */ "V6_vtmpybus_acc_alt\0"
10147 /* 39066 */ "V6_vmpybus_acc_alt\0"
10148 /* 39085 */ "V6_vmpyhus_acc_alt\0"
10149 /* 39104 */ "V6_vdmpyhsat_acc_alt\0"
10150 /* 39125 */ "V6_vmpyhsat_acc_alt\0"
10151 /* 39145 */ "V6_vdmpyhisat_acc_alt\0"
10152 /* 39167 */ "V6_vdmpyhsuisat_acc_alt\0"
10153 /* 39191 */ "V6_vdmpyhsusat_acc_alt\0"
10154 /* 39214 */ "V6_vdmpyhvsat_acc_alt\0"
10155 /* 39236 */ "V6_vandqrt_acc_alt\0"
10156 /* 39255 */ "V6_vandnqrt_acc_alt\0"
10157 /* 39275 */ "V6_vandvrt_acc_alt\0"
10158 /* 39294 */ "V6_vrmpybub_rtt_acc_alt\0"
10159 /* 39318 */ "V6_vrmpyub_rtt_acc_alt\0"
10160 /* 39341 */ "V6_vmpabuu_acc_alt\0"
10161 /* 39360 */ "V6_vrmpyubv_acc_alt\0"
10162 /* 39380 */ "V6_vmpyubv_acc_alt\0"
10163 /* 39399 */ "V6_vrmpybv_acc_alt\0"
10164 /* 39418 */ "V6_vmpybv_acc_alt\0"
10165 /* 39436 */ "V6_vdmpyhb_dv_acc_alt\0"
10166 /* 39458 */ "V6_vdmpybus_dv_acc_alt\0"
10167 /* 39481 */ "V6_vmpyuhv_acc_alt\0"
10168 /* 39500 */ "V6_vmpyhv_acc_alt\0"
10169 /* 39518 */ "V6_vrmpybusv_acc_alt\0"
10170 /* 39539 */ "V6_vmpybusv_acc_alt\0"
10171 /* 39559 */ "V6_vaddhw_acc_alt\0"
10172 /* 39577 */ "V6_vadduhw_acc_alt\0"
10173 /* 39596 */ "V6_vaslw_acc_alt\0"
10174 /* 39613 */ "V6_vasrw_acc_alt\0"
10175 /* 39630 */ "V6_vmpyowh_rnd_sacc_alt\0"
10176 /* 39654 */ "V6_vmpyowh_sacc_alt\0"
10177 /* 39674 */ "V6_vscattermh_add_alt\0"
10178 /* 39696 */ "V6_vscattermwh_add_alt\0"
10179 /* 39719 */ "V6_vscattermw_add_alt\0"
10180 /* 39741 */ "V6_vmpyowh_rnd_alt\0"
10181 /* 39760 */ "V6_vavgbrnd_alt\0"
10182 /* 39776 */ "V6_vavgubrnd_alt\0"
10183 /* 39793 */ "V6_vavghrnd_alt\0"
10184 /* 39809 */ "V6_vavguhrnd_alt\0"
10185 /* 39826 */ "V6_vavgwrnd_alt\0"
10186 /* 39842 */ "V6_vavguwrnd_alt\0"
10187 /* 39859 */ "V6_vcl0h_alt\0"
10188 /* 39872 */ "V6_vsububh_alt\0"
10189 /* 39887 */ "V6_vaddubh_alt\0"
10190 /* 39902 */ "V6_vsubh_alt\0"
10191 /* 39915 */ "V6_vaddh_alt\0"
10192 /* 39928 */ "V6_vshufeh_alt\0"
10193 /* 39943 */ "V6_vpackeh_alt\0"
10194 /* 39958 */ "V6_vshufoeh_alt\0"
10195 /* 39974 */ "V6_vabsdiffh_alt\0"
10196 /* 39991 */ "V6_vshuffh_alt\0"
10197 /* 40006 */ "V6_vnavgh_alt\0"
10198 /* 40020 */ "V6_vavgh_alt\0"
10199 /* 40033 */ "V6_vmpyih_alt\0"
10200 /* 40047 */ "V6_vunpackh_alt\0"
10201 /* 40063 */ "V6_vdealh_alt\0"
10202 /* 40077 */ "V6_vaslh_alt\0"
10203 /* 40090 */ "V6_vscattermh_alt\0"
10204 /* 40108 */ "V6_vminh_alt\0"
10205 /* 40121 */ "V6_vshufoh_alt\0"
10206 /* 40136 */ "V6_vunpackoh_alt\0"
10207 /* 40153 */ "V6_vpackoh_alt\0"
10208 /* 40168 */ "V6_vasrh_alt\0"
10209 /* 40181 */ "V6_vlsrh_alt\0"
10210 /* 40194 */ "V6_vabsh_alt\0"
10211 /* 40207 */ "V6_vsh_alt\0"
10212 /* 40218 */ "V6_vnormamth_alt\0"
10213 /* 40235 */ "V6_vpopcounth_alt\0"
10214 /* 40253 */ "V6_vdsaduh_alt\0"
10215 /* 40268 */ "V6_vabsdiffuh_alt\0"
10216 /* 40286 */ "V6_vavguh_alt\0"
10217 /* 40300 */ "V6_vunpackuh_alt\0"
10218 /* 40317 */ "V6_vminuh_alt\0"
10219 /* 40331 */ "V6_vabsuh_alt\0"
10220 /* 40345 */ "V6_vroundwuh_alt\0"
10221 /* 40362 */ "V6_vmpyiewuh_alt\0"
10222 /* 40379 */ "V6_vmpyewuh_alt\0"
10223 /* 40395 */ "V6_vrounduwuh_alt\0"
10224 /* 40413 */ "V6_vsatuwuh_alt\0"
10225 /* 40429 */ "V6_vmaxuh_alt\0"
10226 /* 40443 */ "V6_vmpyuh_alt\0"
10227 /* 40457 */ "V6_vroundwh_alt\0"
10228 /* 40473 */ "V6_vmpyiwh_alt\0"
10229 /* 40488 */ "V6_vscattermwh_alt\0"
10230 /* 40507 */ "V6_vmpyiowh_alt\0"
10231 /* 40523 */ "V6_vmpyowh_alt\0"
10232 /* 40538 */ "V6_vsatwh_alt\0"
10233 /* 40552 */ "V6_vmaxh_alt\0"
10234 /* 40565 */ "V6_vmpyh_alt\0"
10235 /* 40578 */ "V6_vzh_alt\0"
10236 /* 40589 */ "V6_vrsadubi_alt\0"
10237 /* 40605 */ "V6_vrmpyubi_alt\0"
10238 /* 40621 */ "V6_vrmpybusi_alt\0"
10239 /* 40638 */ "V6_vasr_into_alt\0"
10240 /* 40655 */ "V6_vsubbq_alt\0"
10241 /* 40669 */ "V6_vaddbq_alt\0"
10242 /* 40683 */ "V6_vsubhq_alt\0"
10243 /* 40697 */ "V6_vaddhq_alt\0"
10244 /* 40711 */ "V6_vscattermhq_alt\0"
10245 /* 40730 */ "V6_vscattermwhq_alt\0"
10246 /* 40750 */ "V6_vsubbnq_alt\0"
10247 /* 40765 */ "V6_vaddbnq_alt\0"
10248 /* 40780 */ "V6_vsubhnq_alt\0"
10249 /* 40795 */ "V6_vaddhnq_alt\0"
10250 /* 40810 */ "V6_vsubwnq_alt\0"
10251 /* 40825 */ "V6_vaddwnq_alt\0"
10252 /* 40840 */ "V6_vsubwq_alt\0"
10253 /* 40854 */ "V6_vaddwq_alt\0"
10254 /* 40868 */ "V6_vscattermwq_alt\0"
10255 /* 40887 */ "V6_vrotr_alt\0"
10256 /* 40900 */ "V6_vmpyhsrs_alt\0"
10257 /* 40916 */ "V6_vmpyhvsrs_alt\0"
10258 /* 40933 */ "V6_vmpyhss_alt\0"
10259 /* 40948 */ "V6_vmpabus_alt\0"
10260 /* 40963 */ "V6_vdmpybus_alt\0"
10261 /* 40979 */ "V6_vrmpybus_alt\0"
10262 /* 40995 */ "V6_vtmpybus_alt\0"
10263 /* 41011 */ "V6_vmpybus_alt\0"
10264 /* 41026 */ "V6_vmpyhus_alt\0"
10265 /* 41041 */ "V6_vpackhb_sat_alt\0"
10266 /* 41060 */ "V6_vabsb_sat_alt\0"
10267 /* 41077 */ "V6_vpackhub_sat_alt\0"
10268 /* 41097 */ "V6_vabsh_sat_alt\0"
10269 /* 41114 */ "V6_vpackwuh_sat_alt\0"
10270 /* 41134 */ "V6_vpackwh_sat_alt\0"
10271 /* 41153 */ "V6_vabsw_sat_alt\0"
10272 /* 41170 */ "V6_vsubbsat_alt\0"
10273 /* 41186 */ "V6_vaddbsat_alt\0"
10274 /* 41202 */ "V6_vsububsat_alt\0"
10275 /* 41219 */ "V6_vaddubsat_alt\0"
10276 /* 41236 */ "V6_vsubhsat_alt\0"
10277 /* 41252 */ "V6_vaddhsat_alt\0"
10278 /* 41268 */ "V6_vsubuhsat_alt\0"
10279 /* 41285 */ "V6_vadduhsat_alt\0"
10280 /* 41302 */ "V6_vdmpyhsat_alt\0"
10281 /* 41319 */ "V6_vdmpyhisat_alt\0"
10282 /* 41337 */ "V6_vdmpyhsuisat_alt\0"
10283 /* 41357 */ "V6_vdmpyhsusat_alt\0"
10284 /* 41376 */ "V6_vdmpyhvsat_alt\0"
10285 /* 41394 */ "V6_vsubwsat_alt\0"
10286 /* 41410 */ "V6_vaddwsat_alt\0"
10287 /* 41426 */ "V6_vsubuwsat_alt\0"
10288 /* 41443 */ "V6_vadduwsat_alt\0"
10289 /* 41460 */ "V6_vandqrt_alt\0"
10290 /* 41475 */ "V6_vandnqrt_alt\0"
10291 /* 41491 */ "V6_vandvrt_alt\0"
10292 /* 41506 */ "V6_vrmpybub_rtt_alt\0"
10293 /* 41526 */ "V6_vrmpyub_rtt_alt\0"
10294 /* 41545 */ "V6_vmpabuu_alt\0"
10295 /* 41560 */ "V6_vrmpyubv_alt\0"
10296 /* 41576 */ "V6_vmpyubv_alt\0"
10297 /* 41591 */ "V6_vrmpybv_alt\0"
10298 /* 41606 */ "V6_vmpybv_alt\0"
10299 /* 41620 */ "V6_vsubb_dv_alt\0"
10300 /* 41636 */ "V6_vaddb_dv_alt\0"
10301 /* 41652 */ "V6_vdmpyhb_dv_alt\0"
10302 /* 41670 */ "V6_vsubh_dv_alt\0"
10303 /* 41686 */ "V6_vaddh_dv_alt\0"
10304 /* 41702 */ "V6_vdmpybus_dv_alt\0"
10305 /* 41721 */ "V6_vsubbsat_dv_alt\0"
10306 /* 41740 */ "V6_vaddbsat_dv_alt\0"
10307 /* 41759 */ "V6_vsububsat_dv_alt\0"
10308 /* 41779 */ "V6_vaddubsat_dv_alt\0"
10309 /* 41799 */ "V6_vsubhsat_dv_alt\0"
10310 /* 41818 */ "V6_vaddhsat_dv_alt\0"
10311 /* 41837 */ "V6_vsubuhsat_dv_alt\0"
10312 /* 41857 */ "V6_vadduhsat_dv_alt\0"
10313 /* 41877 */ "V6_vsubwsat_dv_alt\0"
10314 /* 41896 */ "V6_vaddwsat_dv_alt\0"
10315 /* 41915 */ "V6_vsubuwsat_dv_alt\0"
10316 /* 41935 */ "V6_vadduwsat_dv_alt\0"
10317 /* 41955 */ "V6_vsubw_dv_alt\0"
10318 /* 41971 */ "V6_vaddw_dv_alt\0"
10319 /* 41987 */ "V6_vaslhv_alt\0"
10320 /* 42001 */ "V6_vasrhv_alt\0"
10321 /* 42015 */ "V6_vlsrhv_alt\0"
10322 /* 42029 */ "V6_vmpyuhv_alt\0"
10323 /* 42044 */ "V6_vmpyhv_alt\0"
10324 /* 42058 */ "V6_vmpabusv_alt\0"
10325 /* 42074 */ "V6_vrmpybusv_alt\0"
10326 /* 42091 */ "V6_vmpybusv_alt\0"
10327 /* 42107 */ "V6_vmpabuuv_alt\0"
10328 /* 42123 */ "V6_vaslwv_alt\0"
10329 /* 42137 */ "V6_vasrwv_alt\0"
10330 /* 42151 */ "V6_vlsrwv_alt\0"
10331 /* 42165 */ "V6_vcl0w_alt\0"
10332 /* 42178 */ "V6_vdealb4w_alt\0"
10333 /* 42194 */ "V6_vsubw_alt\0"
10334 /* 42207 */ "V6_vaddw_alt\0"
10335 /* 42220 */ "V6_vabsdiffw_alt\0"
10336 /* 42237 */ "V6_vnavgw_alt\0"
10337 /* 42251 */ "V6_vavgw_alt\0"
10338 /* 42264 */ "V6_vsubhw_alt\0"
10339 /* 42278 */ "V6_vaddhw_alt\0"
10340 /* 42292 */ "V6_vsubuhw_alt\0"
10341 /* 42307 */ "V6_vadduhw_alt\0"
10342 /* 42322 */ "V6_vaslw_alt\0"
10343 /* 42335 */ "V6_vscattermw_alt\0"
10344 /* 42353 */ "V6_vminw_alt\0"
10345 /* 42366 */ "V6_vasrw_alt\0"
10346 /* 42379 */ "V6_vlsrw_alt\0"
10347 /* 42392 */ "V6_vabsw_alt\0"
10348 /* 42405 */ "V6_extractw_alt\0"
10349 /* 42421 */ "V6_vnormamtw_alt\0"
10350 /* 42438 */ "V6_vavguw_alt\0"
10351 /* 42452 */ "V6_vabsuw_alt\0"
10352 /* 42466 */ "V6_vmaxw_alt\0"
10353 /* 42479 */ "J2_callt\0"
10354 /* 42488 */ "C2_cmplt\0"
10355 /* 42497 */ "J4_tstbit0_fp0_jump_nt\0"
10356 /* 42520 */ "J4_cmpeqn1_fp0_jump_nt\0"
10357 /* 42543 */ "J4_cmpgtn1_fp0_jump_nt\0"
10358 /* 42566 */ "J4_cmpeqi_fp0_jump_nt\0"
10359 /* 42588 */ "J4_cmpgti_fp0_jump_nt\0"
10360 /* 42610 */ "J4_cmpgtui_fp0_jump_nt\0"
10361 /* 42633 */ "J4_cmpeq_fp0_jump_nt\0"
10362 /* 42654 */ "J4_cmpgt_fp0_jump_nt\0"
10363 /* 42675 */ "J4_cmpgtu_fp0_jump_nt\0"
10364 /* 42697 */ "J4_tstbit0_tp0_jump_nt\0"
10365 /* 42720 */ "J4_cmpeqn1_tp0_jump_nt\0"
10366 /* 42743 */ "J4_cmpgtn1_tp0_jump_nt\0"
10367 /* 42766 */ "J4_cmpeqi_tp0_jump_nt\0"
10368 /* 42788 */ "J4_cmpgti_tp0_jump_nt\0"
10369 /* 42810 */ "J4_cmpgtui_tp0_jump_nt\0"
10370 /* 42833 */ "J4_cmpeq_tp0_jump_nt\0"
10371 /* 42854 */ "J4_cmpgt_tp0_jump_nt\0"
10372 /* 42875 */ "J4_cmpgtu_tp0_jump_nt\0"
10373 /* 42897 */ "J4_tstbit0_fp1_jump_nt\0"
10374 /* 42920 */ "J4_cmpeqn1_fp1_jump_nt\0"
10375 /* 42943 */ "J4_cmpgtn1_fp1_jump_nt\0"
10376 /* 42966 */ "J4_cmpeqi_fp1_jump_nt\0"
10377 /* 42988 */ "J4_cmpgti_fp1_jump_nt\0"
10378 /* 43010 */ "J4_cmpgtui_fp1_jump_nt\0"
10379 /* 43033 */ "J4_cmpeq_fp1_jump_nt\0"
10380 /* 43054 */ "J4_cmpgt_fp1_jump_nt\0"
10381 /* 43075 */ "J4_cmpgtu_fp1_jump_nt\0"
10382 /* 43097 */ "J4_tstbit0_tp1_jump_nt\0"
10383 /* 43120 */ "J4_cmpeqn1_tp1_jump_nt\0"
10384 /* 43143 */ "J4_cmpgtn1_tp1_jump_nt\0"
10385 /* 43166 */ "J4_cmpeqi_tp1_jump_nt\0"
10386 /* 43188 */ "J4_cmpgti_tp1_jump_nt\0"
10387 /* 43210 */ "J4_cmpgtui_tp1_jump_nt\0"
10388 /* 43233 */ "J4_cmpeq_tp1_jump_nt\0"
10389 /* 43254 */ "J4_cmpgt_tp1_jump_nt\0"
10390 /* 43275 */ "J4_cmpgtu_tp1_jump_nt\0"
10391 /* 43297 */ "J4_tstbit0_f_jumpnv_nt\0"
10392 /* 43320 */ "J4_cmpeqn1_f_jumpnv_nt\0"
10393 /* 43343 */ "J4_cmpgtn1_f_jumpnv_nt\0"
10394 /* 43366 */ "J4_cmpeqi_f_jumpnv_nt\0"
10395 /* 43388 */ "J4_cmpgti_f_jumpnv_nt\0"
10396 /* 43410 */ "J4_cmpgtui_f_jumpnv_nt\0"
10397 /* 43433 */ "J4_cmpeq_f_jumpnv_nt\0"
10398 /* 43454 */ "J4_cmpgt_f_jumpnv_nt\0"
10399 /* 43475 */ "J4_cmplt_f_jumpnv_nt\0"
10400 /* 43496 */ "J4_cmpgtu_f_jumpnv_nt\0"
10401 /* 43518 */ "J4_cmpltu_f_jumpnv_nt\0"
10402 /* 43540 */ "J4_tstbit0_t_jumpnv_nt\0"
10403 /* 43563 */ "J4_cmpeqn1_t_jumpnv_nt\0"
10404 /* 43586 */ "J4_cmpgtn1_t_jumpnv_nt\0"
10405 /* 43609 */ "J4_cmpeqi_t_jumpnv_nt\0"
10406 /* 43631 */ "J4_cmpgti_t_jumpnv_nt\0"
10407 /* 43653 */ "J4_cmpgtui_t_jumpnv_nt\0"
10408 /* 43676 */ "J4_cmpeq_t_jumpnv_nt\0"
10409 /* 43697 */ "J4_cmpgt_t_jumpnv_nt\0"
10410 /* 43718 */ "J4_cmplt_t_jumpnv_nt\0"
10411 /* 43739 */ "J4_cmpgtu_t_jumpnv_nt\0"
10412 /* 43761 */ "J4_cmpltu_t_jumpnv_nt\0"
10413 /* 43783 */ "L4_return_fnew_pnt\0"
10414 /* 43802 */ "L4_return_map_to_raw_fnew_pnt\0"
10415 /* 43832 */ "L4_return_tnew_pnt\0"
10416 /* 43851 */ "L4_return_map_to_raw_tnew_pnt\0"
10417 /* 43881 */ "A2_not\0"
10418 /* 43888 */ "C2_not\0"
10419 /* 43895 */ "C4_fastcorner9_not\0"
10420 /* 43914 */ "V6_pred_not\0"
10421 /* 43926 */ "V6_vnot\0"
10422 /* 43934 */ "L4_return_fnew_pt\0"
10423 /* 43952 */ "L4_return_map_to_raw_fnew_pt\0"
10424 /* 43981 */ "L4_return_tnew_pt\0"
10425 /* 43999 */ "L4_return_map_to_raw_tnew_pt\0"
10426 /* 44028 */ "J2_jumpfpt\0"
10427 /* 44039 */ "J2_jumprfpt\0"
10428 /* 44051 */ "J2_jumpt\0"
10429 /* 44060 */ "A2_tfrpt\0"
10430 /* 44069 */ "J2_jumptpt\0"
10431 /* 44080 */ "J2_jumprtpt\0"
10432 /* 44092 */ "J2_jumpfnewpt\0"
10433 /* 44106 */ "J2_jumprfnewpt\0"
10434 /* 44121 */ "PS_jmpretfnewpt\0"
10435 /* 44137 */ "J2_jumptnewpt\0"
10436 /* 44151 */ "J2_jumprtnewpt\0"
10437 /* 44166 */ "PS_jmprettnewpt\0"
10438 /* 44182 */ "J2_jumprgtezpt\0"
10439 /* 44197 */ "J2_jumprltezpt\0"
10440 /* 44212 */ "J2_jumprnzpt\0"
10441 /* 44225 */ "J2_jumprzpt\0"
10442 /* 44237 */ "V6_vrmpyzbb_rt\0"
10443 /* 44252 */ "V6_vrmpyzcb_rt\0"
10444 /* 44267 */ "V6_vrmpyznb_rt\0"
10445 /* 44282 */ "V6_vrmpyzbub_rt\0"
10446 /* 44298 */ "V6_vrmpyzcbs_rt\0"
10447 /* 44314 */ "Y2_start\0"
10448 /* 44323 */ "Y6_dmstart\0"
10449 /* 44334 */ "S2_insert\0"
10450 /* 44344 */ "A2_tfrt\0"
10451 /* 44352 */ "SA1_clrt\0"
10452 /* 44361 */ "J2_callrt\0"
10453 /* 44371 */ "A2_port\0"
10454 /* 44379 */ "A2_pxort\0"
10455 /* 44388 */ "J2_jumprt\0"
10456 /* 44398 */ "V6_vandqrt\0"
10457 /* 44409 */ "V6_vandnqrt\0"
10458 /* 44421 */ "V6_vandvrt\0"
10459 /* 44432 */ "V6_vhist\0"
10460 /* 44441 */ "A2_iconst\0"
10461 /* 44451 */ "PS_jmprett\0"
10462 /* 44462 */ "V6_vrmpybub_rtt\0"
10463 /* 44478 */ "V6_vrmpyub_rtt\0"
10464 /* 44493 */ "C2_ccombinewt\0"
10465 /* 44507 */ "C2_ccombinewnewt\0"
10466 /* 44524 */ "TFRI64_V2_ext\0"
10467 /* 44538 */ "A4_ext\0"
10468 /* 44545 */ "J2_loop0iext\0"
10469 /* 44558 */ "J2_loop1iext\0"
10470 /* 44571 */ "J2_loop0rext\0"
10471 /* 44584 */ "J2_loop1rext\0"
10472 /* 44597 */ "C4_cmplteu\0"
10473 /* 44608 */ "A2_minu\0"
10474 /* 44616 */ "A4_modwrapu\0"
10475 /* 44628 */ "V6_vL32b_ppu\0"
10476 /* 44641 */ "V6_vS32b_ppu\0"
10477 /* 44654 */ "V6_vL32Ub_ppu\0"
10478 /* 44668 */ "V6_vS32Ub_ppu\0"
10479 /* 44682 */ "V6_zLd_ppu\0"
10480 /* 44693 */ "V6_vL32b_pred_ppu\0"
10481 /* 44711 */ "V6_vS32b_pred_ppu\0"
10482 /* 44729 */ "V6_vS32Ub_pred_ppu\0"
10483 /* 44748 */ "V6_zLd_pred_ppu\0"
10484 /* 44764 */ "V6_vL32b_tmp_pred_ppu\0"
10485 /* 44786 */ "V6_vL32b_nt_tmp_pred_ppu\0"
10486 /* 44811 */ "V6_vL32b_cur_pred_ppu\0"
10487 /* 44833 */ "V6_vL32b_nt_cur_pred_ppu\0"
10488 /* 44858 */ "V6_vL32b_nt_pred_ppu\0"
10489 /* 44879 */ "V6_vS32b_nt_pred_ppu\0"
10490 /* 44900 */ "V6_vS32b_new_pred_ppu\0"
10491 /* 44922 */ "V6_vS32b_nt_new_pred_ppu\0"
10492 /* 44947 */ "V6_vL32b_npred_ppu\0"
10493 /* 44966 */ "V6_vS32b_npred_ppu\0"
10494 /* 44985 */ "V6_vS32Ub_npred_ppu\0"
10495 /* 45005 */ "V6_vL32b_tmp_npred_ppu\0"
10496 /* 45028 */ "V6_vL32b_nt_tmp_npred_ppu\0"
10497 /* 45054 */ "V6_vL32b_cur_npred_ppu\0"
10498 /* 45077 */ "V6_vL32b_nt_cur_npred_ppu\0"
10499 /* 45103 */ "V6_vL32b_nt_npred_ppu\0"
10500 /* 45125 */ "V6_vS32b_nt_npred_ppu\0"
10501 /* 45147 */ "V6_vS32b_new_npred_ppu\0"
10502 /* 45170 */ "V6_vS32b_nt_new_npred_ppu\0"
10503 /* 45196 */ "V6_vS32b_qpred_ppu\0"
10504 /* 45215 */ "V6_vS32b_nt_qpred_ppu\0"
10505 /* 45237 */ "V6_vS32b_nqpred_ppu\0"
10506 /* 45257 */ "V6_vS32b_nt_nqpred_ppu\0"
10507 /* 45280 */ "V6_vL32b_tmp_ppu\0"
10508 /* 45297 */ "V6_vL32b_nt_tmp_ppu\0"
10509 /* 45317 */ "V6_vL32b_cur_ppu\0"
10510 /* 45334 */ "V6_vL32b_nt_cur_ppu\0"
10511 /* 45354 */ "V6_vS32b_srls_ppu\0"
10512 /* 45372 */ "V6_vL32b_nt_ppu\0"
10513 /* 45388 */ "V6_vS32b_nt_ppu\0"
10514 /* 45404 */ "V6_vS32b_new_ppu\0"
10515 /* 45421 */ "V6_vS32b_nt_new_ppu\0"
10516 /* 45441 */ "M5_vdmacbsu\0"
10517 /* 45453 */ "M5_vrmacbsu\0"
10518 /* 45465 */ "M5_vmacbsu\0"
10519 /* 45476 */ "M5_vdmpybsu\0"
10520 /* 45488 */ "M5_vrmpybsu\0"
10521 /* 45500 */ "M5_vmpybsu\0"
10522 /* 45511 */ "S2_extractu\0"
10523 /* 45523 */ "A4_cmpbgtu\0"
10524 /* 45534 */ "A2_vcmpbgtu\0"
10525 /* 45546 */ "A4_cmphgtu\0"
10526 /* 45557 */ "A2_vcmphgtu\0"
10527 /* 45569 */ "C2_cmpgtu\0"
10528 /* 45579 */ "A2_vcmpwgtu\0"
10529 /* 45591 */ "C2_cmpltu\0"
10530 /* 45601 */ "V6_vmpabuu\0"
10531 /* 45612 */ "M5_vrmacbuu\0"
10532 /* 45624 */ "M5_vmacbuu\0"
10533 /* 45635 */ "M5_vrmpybuu\0"
10534 /* 45647 */ "M5_vmpybuu\0"
10535 /* 45658 */ "A2_maxu\0"
10536 /* 45666 */ "V6_vrmpyubv\0"
10537 /* 45678 */ "V6_vmpyubv\0"
10538 /* 45689 */ "V6_vrmpybv\0"
10539 /* 45700 */ "V6_vmpybv\0"
10540 /* 45710 */ "V6_vsubb_dv\0"
10541 /* 45722 */ "V6_vaddb_dv\0"
10542 /* 45734 */ "V6_vdmpyhb_dv\0"
10543 /* 45748 */ "V6_vsubh_dv\0"
10544 /* 45760 */ "V6_vaddh_dv\0"
10545 /* 45772 */ "V6_vdmpybus_dv\0"
10546 /* 45787 */ "V6_vsubbsat_dv\0"
10547 /* 45802 */ "V6_vaddbsat_dv\0"
10548 /* 45817 */ "V6_vsububsat_dv\0"
10549 /* 45833 */ "V6_vaddubsat_dv\0"
10550 /* 45849 */ "V6_vsubhsat_dv\0"
10551 /* 45864 */ "V6_vaddhsat_dv\0"
10552 /* 45879 */ "V6_vsubuhsat_dv\0"
10553 /* 45895 */ "V6_vadduhsat_dv\0"
10554 /* 45911 */ "V6_vsubwsat_dv\0"
10555 /* 45926 */ "V6_vaddwsat_dv\0"
10556 /* 45941 */ "V6_vsubuwsat_dv\0"
10557 /* 45957 */ "V6_vadduwsat_dv\0"
10558 /* 45973 */ "V6_vsubw_dv\0"
10559 /* 45985 */ "V6_vaddw_dv\0"
10560 /* 45997 */ "S2_brev\0"
10561 /* 46005 */ "V6_vaslhv\0"
10562 /* 46015 */ "V6_vasrhv\0"
10563 /* 46025 */ "V6_vlsrhv\0"
10564 /* 46035 */ "V6_vmpyuhv\0"
10565 /* 46046 */ "V6_vmpyhv\0"
10566 /* 46056 */ "Y5_l2gcleaninv\0"
10567 /* 46071 */ "V6_vncmov\0"
10568 /* 46081 */ "V6_vcmov\0"
10569 /* 46090 */ "V6_vandvnqv\0"
10570 /* 46102 */ "V6_vandvqv\0"
10571 /* 46113 */ "V6_vmpabusv\0"
10572 /* 46125 */ "V6_vrmpybusv\0"
10573 /* 46138 */ "V6_vmpybusv\0"
10574 /* 46150 */ "V6_vmpabuuv\0"
10575 /* 46162 */ "V6_vaslwv\0"
10576 /* 46172 */ "V6_vasrwv\0"
10577 /* 46182 */ "V6_vlsrwv\0"
10578 /* 46192 */ "V6_vcl0w\0"
10579 /* 46201 */ "F2_conv_df2w\0"
10580 /* 46214 */ "F2_conv_sf2w\0"
10581 /* 46227 */ "V6_vdealb4w\0"
10582 /* 46239 */ "V6_vconv_sf_w\0"
10583 /* 46253 */ "S6_allocframe_to_raw\0"
10584 /* 46274 */ "L6_deallocframe_map_to_raw\0"
10585 /* 46301 */ "L6_return_map_to_raw\0"
10586 /* 46322 */ "Y2_icdataw\0"
10587 /* 46333 */ "V6_vaddclbw\0"
10588 /* 46345 */ "Y2_tlbw\0"
10589 /* 46353 */ "Y5_ctlbw\0"
10590 /* 46362 */ "S4_vxaddsubw\0"
10591 /* 46375 */ "A2_vsubw\0"
10592 /* 46384 */ "V6_vsubw\0"
10593 /* 46393 */ "S4_vxsubaddw\0"
10594 /* 46406 */ "A2_vaddw\0"
10595 /* 46415 */ "V6_vaddw\0"
10596 /* 46424 */ "V6_vsatdw\0"
10597 /* 46434 */ "SL2_jumpr31_fnew\0"
10598 /* 46451 */ "SL2_return_fnew\0"
10599 /* 46467 */ "A4_psxtbfnew\0"
10600 /* 46480 */ "A4_pzxtbfnew\0"
10601 /* 46493 */ "A2_psubfnew\0"
10602 /* 46505 */ "A2_paddfnew\0"
10603 /* 46517 */ "A2_pandfnew\0"
10604 /* 46529 */ "A4_paslhfnew\0"
10605 /* 46542 */ "A4_pasrhfnew\0"
10606 /* 46555 */ "A4_psxthfnew\0"
10607 /* 46568 */ "A4_pzxthfnew\0"
10608 /* 46581 */ "A2_paddifnew\0"
10609 /* 46594 */ "J2_jumpfnew\0"
10610 /* 46606 */ "A2_tfrpfnew\0"
10611 /* 46618 */ "A2_tfrfnew\0"
10612 /* 46629 */ "SA1_clrfnew\0"
10613 /* 46641 */ "A2_porfnew\0"
10614 /* 46652 */ "A2_pxorfnew\0"
10615 /* 46664 */ "J2_jumprfnew\0"
10616 /* 46677 */ "PS_jmpretfnew\0"
10617 /* 46691 */ "A2_combinew\0"
10618 /* 46703 */ "SL2_jumpr31_tnew\0"
10619 /* 46720 */ "SL2_return_tnew\0"
10620 /* 46736 */ "A4_psxtbtnew\0"
10621 /* 46749 */ "A4_pzxtbtnew\0"
10622 /* 46762 */ "A2_psubtnew\0"
10623 /* 46774 */ "A2_paddtnew\0"
10624 /* 46786 */ "A2_pandtnew\0"
10625 /* 46798 */ "A4_paslhtnew\0"
10626 /* 46811 */ "A4_pasrhtnew\0"
10627 /* 46824 */ "A4_psxthtnew\0"
10628 /* 46837 */ "A4_pzxthtnew\0"
10629 /* 46850 */ "A2_padditnew\0"
10630 /* 46863 */ "J2_jumptnew\0"
10631 /* 46875 */ "A2_tfrptnew\0"
10632 /* 46887 */ "A2_tfrtnew\0"
10633 /* 46898 */ "SA1_clrtnew\0"
10634 /* 46910 */ "A2_portnew\0"
10635 /* 46921 */ "A2_pxortnew\0"
10636 /* 46933 */ "J2_jumprtnew\0"
10637 /* 46946 */ "PS_jmprettnew\0"
10638 /* 46960 */ "M2_vabsdiffw\0"
10639 /* 46973 */ "V6_vabsdiffw\0"
10640 /* 46986 */ "Y4_l2tagw\0"
10641 /* 46996 */ "Y2_dctagw\0"
10642 /* 47006 */ "Y2_ictagw\0"
10643 /* 47016 */ "A2_vnavgw\0"
10644 /* 47026 */ "V6_vnavgw\0"
10645 /* 47036 */ "A2_vavgw\0"
10646 /* 47045 */ "V6_vavgw\0"
10647 /* 47054 */ "V6_vsubhw\0"
10648 /* 47064 */ "V6_vaddhw\0"
10649 /* 47074 */ "V6_vgathermhw\0"
10650 /* 47088 */ "V6_vscattermhw\0"
10651 /* 47103 */ "S2_vsxthw\0"
10652 /* 47113 */ "S2_vzxthw\0"
10653 /* 47123 */ "V6_vsubuhw\0"
10654 /* 47134 */ "V6_vadduhw\0"
10655 /* 47145 */ "PS_vsplatiw\0"
10656 /* 47157 */ "M7_dcmpyiw\0"
10657 /* 47168 */ "M7_wcmpyiw\0"
10658 /* 47179 */ "V6_vaslw\0"
10659 /* 47188 */ "PS_vmulw\0"
10660 /* 47197 */ "V6_vgathermw\0"
10661 /* 47210 */ "V6_vscattermw\0"
10662 /* 47224 */ "Y2_iassignw\0"
10663 /* 47236 */ "A4_vrminw\0"
10664 /* 47246 */ "A2_vminw\0"
10665 /* 47255 */ "V6_vminw\0"
10666 /* 47264 */ "V6_shuffeqw\0"
10667 /* 47276 */ "V6_veqw\0"
10668 /* 47284 */ "V6_vprefixqw\0"
10669 /* 47297 */ "V6_vasrw\0"
10670 /* 47306 */ "V6_vlsrw\0"
10671 /* 47315 */ "PS_vsplatrw\0"
10672 /* 47327 */ "M7_dcmpyrw\0"
10673 /* 47338 */ "M7_wcmpyrw\0"
10674 /* 47349 */ "A2_vabsw\0"
10675 /* 47358 */ "V6_vabsw\0"
10676 /* 47367 */ "V6_lvsplatw\0"
10677 /* 47379 */ "V6_extractw\0"
10678 /* 47391 */ "V6_vgtw\0"
10679 /* 47399 */ "V6_vnormamtw\0"
10680 /* 47412 */ "A2_sxtw\0"
10681 /* 47420 */ "F2_conv_df2uw\0"
10682 /* 47434 */ "F2_conv_sf2uw\0"
10683 /* 47448 */ "A2_vavguw\0"
10684 /* 47458 */ "V6_vavguw\0"
10685 /* 47468 */ "A4_vrminuw\0"
10686 /* 47479 */ "A2_vminuw\0"
10687 /* 47489 */ "V6_MAP_equw\0"
10688 /* 47501 */ "V6_vgtuw\0"
10689 /* 47510 */ "A4_vrmaxuw\0"
10690 /* 47521 */ "A2_vmaxuw\0"
10691 /* 47531 */ "S2_asl_i_vw\0"
10692 /* 47543 */ "S2_asr_i_vw\0"
10693 /* 47555 */ "S2_lsr_i_vw\0"
10694 /* 47567 */ "S2_asl_r_vw\0"
10695 /* 47579 */ "S2_lsl_r_vw\0"
10696 /* 47591 */ "S2_asr_r_vw\0"
10697 /* 47603 */ "S2_lsr_r_vw\0"
10698 /* 47615 */ "A4_vrmaxw\0"
10699 /* 47625 */ "A2_vmaxw\0"
10700 /* 47634 */ "V6_vmaxw\0"
10701 /* 47643 */ "S2_tableidxw\0"
10702 /* 47656 */ "M4_pmpyw\0"
10703 /* 47665 */ "A2_max\0"
10704 /* 47672 */ "F2_dfmax\0"
10705 /* 47681 */ "F2_sfmax\0"
10706 /* 47690 */ "S2_tableidxb_goodsyntax\0"
10707 /* 47714 */ "S2_asr_i_p_rnd_goodsyntax\0"
10708 /* 47740 */ "S2_asr_i_r_rnd_goodsyntax\0"
10709 /* 47766 */ "S5_vasrhrnd_goodsyntax\0"
10710 /* 47789 */ "S2_tableidxd_goodsyntax\0"
10711 /* 47813 */ "S2_tableidxh_goodsyntax\0"
10712 /* 47837 */ "S5_asrhub_rnd_sat_goodsyntax\0"
10713 /* 47866 */ "S2_tableidxw_goodsyntax\0"
10714 /* 47890 */ "Y5_l2cleanidx\0"
10715 /* 47904 */ "Y2_dccleanidx\0"
10716 /* 47918 */ "Y5_l2invidx\0"
10717 /* 47930 */ "Y2_dcinvidx\0"
10718 /* 47942 */ "Y2_icinvidx\0"
10719 /* 47954 */ "Y2_l2cleaninvidx\0"
10720 /* 47971 */ "Y2_dccleaninvidx\0"
10721 /* 47988 */ "S4_or_andix\0"
10722 /* 48000 */ "F2_dfmpyfix\0"
10723 /* 48012 */ "V6_vsub_qf32_mix\0"
10724 /* 48029 */ "V6_vadd_qf32_mix\0"
10725 /* 48046 */ "V6_vsub_qf16_mix\0"
10726 /* 48063 */ "V6_vadd_qf16_mix\0"
10727 /* 48080 */ "V6_vrmpyzbb_rx\0"
10728 /* 48095 */ "V6_vrmpyzcb_rx\0"
10729 /* 48110 */ "V6_vrmpyznb_rx\0"
10730 /* 48125 */ "V6_vrmpyzbub_rx\0"
10731 /* 48141 */ "V6_vrmpyzcbs_rx\0"
10732 /* 48157 */ "SA1_addrx\0"
10733 /* 48167 */ "C2_mux\0"
10734 /* 48174 */ "C2_vmux\0"
10735 /* 48182 */ "V6_vmux\0"
10736 /* 48190 */ "V6_v6mpyhubs10_vxx\0"
10737 /* 48209 */ "V6_v6mpyvubs10_vxx\0"
10738 /* 48228 */ "V6_v10mpyubs10_vxx\0"
10739 /* 48247 */ "A4_vcmpbeq_any\0"
10740 /* 48262 */ "A6_vcmpbeq_notany\0"
10741 /* 48280 */ "L6_memcpy\0"
10742 /* 48290 */ "M7_vdmpy\0"
10743 /* 48299 */ "F2_sfmpy\0"
10744 /* 48308 */ "V6_vsubcarry\0"
10745 /* 48321 */ "V6_vaddcarry\0"
10746 /* 48334 */ "S4_parity\0"
10747 /* 48344 */ "J2_jumprgtez\0"
10748 /* 48357 */ "J2_jumprltez\0"
10749 /* 48370 */ "A2_swiz\0"
10750 /* 48378 */ "J2_jumprnz\0"
10751 /* 48389 */ "SA1_combinerz\0"
10752 /* 48403 */ "J2_jumprz\0"
10753};
10754#ifdef __GNUC__
10755#pragma GCC diagnostic pop
10756#endif
10757
10758extern const unsigned HexagonInstrNameIndices[] = {
10759 6605U, 7001U, 7686U, 7289U, 6690U, 6671U, 6699U, 6837U,
10760 6428U, 6443U, 6380U, 6470U, 8173U, 6212U, 8798U, 6393U,
10761 6601U, 6680U, 6002U, 9271U, 6124U, 8702U, 5837U, 5953U,
10762 5990U, 7400U, 6825U, 8612U, 5922U, 7607U, 6533U, 8601U,
10763 6147U, 7580U, 7567U, 7747U, 8460U, 8483U, 6757U, 6804U,
10764 6777U, 6716U, 7712U, 7354U, 9276U, 7865U, 7538U, 6260U,
10765 8828U, 8858U, 7132U, 5750U, 5163U, 6940U, 9020U, 9027U,
10766 6967U, 6974U, 6981U, 6991U, 5815U, 8036U, 7999U, 6378U,
10767 6603U, 9194U, 6222U, 6237U, 6842U, 8428U, 8109U, 8739U,
10768 8126U, 7936U, 5517U, 8156U, 8623U, 8078U, 8771U, 6303U,
10769 7723U, 5896U, 5491U, 5878U, 8661U, 8642U, 7110U, 7772U,
10770 7791U, 5651U, 5595U, 5625U, 5636U, 5576U, 5606U, 6191U,
10771 6175U, 8203U, 6484U, 6501U, 5766U, 5169U, 5821U, 5782U,
10772 8041U, 8005U, 9178U, 7258U, 9161U, 7241U, 5717U, 5146U,
10773 9096U, 7176U, 7462U, 7440U, 5982U, 6550U, 5850U, 8447U,
10774 8717U, 5469U, 8251U, 8578U, 8278U, 8842U, 5509U, 8567U,
10775 8555U, 8692U, 6525U, 8821U, 6457U, 8851U, 6743U, 7858U,
10776 7844U, 6736U, 7851U, 8071U, 6858U, 7517U, 7510U, 7524U,
10777 7531U, 8438U, 7346U, 6023U, 7330U, 5974U, 7338U, 6015U,
10778 7322U, 5966U, 7384U, 7376U, 6569U, 6561U, 8346U, 8336U,
10779 8326U, 8316U, 8366U, 8356U, 9222U, 9232U, 8376U, 8389U,
10780 9242U, 9252U, 8402U, 8415U, 5675U, 5125U, 6882U, 5092U,
10781 5569U, 8999U, 6946U, 9072U, 6627U, 7651U, 4654U, 9U,
10782 6518U, 4646U, 0U, 7626U, 7658U, 6421U, 8813U, 5481U,
10783 6609U, 6618U, 7492U, 7501U, 8089U, 7147U, 8190U, 6312U,
10784 7075U, 7085U, 6072U, 6087U, 7032U, 7064U, 9034U, 9060U,
10785 9046U, 6031U, 6059U, 6044U, 5756U, 6635U, 7210U, 9130U,
10786 7234U, 9154U, 8096U, 5869U, 5859U, 7681U, 8507U, 6102U,
10787 7917U, 7897U, 8535U, 8514U, 7951U, 7968U, 8233U, 9305U,
10788 6360U, 9298U, 6342U, 7559U, 7484U, 6199U, 6749U, 8149U,
10789 7282U, 7103U, 8141U, 7274U, 7095U, 6593U, 6585U, 6577U,
10790 8748U, 7888U, 8634U, 8679U, 8781U, 7699U, 6111U, 5538U,
10791 6281U, 6160U, 5703U, 5132U, 6910U, 9006U, 6953U, 5098U,
10792 8756U, 7635U, 7811U, 7827U, 9262U, 6131U, 6293U, 8474U,
10793 7392U, 7433U, 7409U, 7421U, 5682U, 6889U, 5658U, 6865U,
10794 9079U, 7159U, 7043U, 7011U, 5734U, 6924U, 5799U, 8021U,
10795 7983U, 9113U, 7193U, 9137U, 7217U, 9208U, 9215U, 28919U,
10796 44441U, 15139U, 43881U, 14767U, 46618U, 28813U, 14758U, 46606U,
10797 20840U, 44060U, 46875U, 44344U, 46887U, 25592U, 25579U, 10076U,
10798 21744U, 7305U, 7592U, 18623U, 21372U, 42488U, 45591U, 25717U,
10799 22763U, 75U, 2534U, 2569U, 277U, 2544U, 2669U, 25605U,
10800 25625U, 25666U, 25646U, 25730U, 25820U, 26448U, 25748U, 25784U,
10801 25766U, 25802U, 26002U, 26070U, 26630U, 26698U, 26053U, 26681U,
10802 26103U, 27097U, 26749U, 27516U, 26178U, 27184U, 26824U, 27603U,
10803 26234U, 27249U, 26880U, 27668U, 26309U, 27336U, 26955U, 27755U,
10804 26159U, 27162U, 26805U, 27581U, 26290U, 27314U, 26936U, 27733U,
10805 25881U, 26509U, 27936U, 25922U, 26550U, 27977U, 25901U, 26529U,
10806 27956U, 25942U, 26570U, 27997U, 25982U, 26610U, 28037U, 25860U,
10807 26488U, 27915U, 25963U, 26591U, 28018U, 14083U, 43802U, 43952U,
10808 36608U, 43851U, 43999U, 25840U, 26468U, 27895U, 46274U, 46301U,
10809 33341U, 12897U, 18763U, 21469U, 2717U, 4349U, 28710U, 48290U,
10810 12337U, 9374U, 9312U, 22377U, 30851U, 16071U, 13905U, 18644U,
10811 9322U, 18126U, 30189U, 18214U, 30277U, 18320U, 30383U, 18408U,
10812 30471U, 18185U, 30248U, 18379U, 30442U, 37650U, 13914U, 14005U,
10813 18155U, 30218U, 18243U, 30306U, 18273U, 30336U, 18349U, 30412U,
10814 18437U, 30500U, 16838U, 29549U, 13997U, 92U, 17625U, 17806U,
10815 17736U, 17870U, 17771U, 47188U, 12186U, 37661U, 9790U, 15691U,
10816 47145U, 9986U, 16059U, 47315U, 17639U, 17820U, 17753U, 17884U,
10817 17788U, 37672U, 47714U, 47740U, 26121U, 26382U, 27011U, 26767U,
10818 26196U, 26842U, 26215U, 26861U, 26252U, 26404U, 27033U, 26898U,
10819 26327U, 26426U, 27055U, 26973U, 26018U, 27077U, 26086U, 26365U,
10820 26646U, 27476U, 26714U, 27496U, 47690U, 47789U, 47813U, 47866U,
10821 27118U, 27401U, 27820U, 27537U, 27205U, 27624U, 27227U, 27646U,
10822 27270U, 27426U, 27845U, 27689U, 27357U, 27451U, 27870U, 27776U,
10823 26035U, 26140U, 27140U, 26786U, 27559U, 26663U, 26271U, 27292U,
10824 26917U, 27711U, 26731U, 26346U, 27379U, 26992U, 27798U, 47837U,
10825 47766U, 46253U, 33351U, 12908U, 10293U, 12971U, 31319U, 31420U,
10826 16316U, 13097U, 31335U, 31535U, 47489U, 13421U, 31351U, 31658U,
10827 107U, 2507U, 42405U, 18650U, 100U, 229U, 2403U, 203U,
10828 2382U, 239U, 2415U, 2363U, 212U, 2393U, 248U, 2426U,
10829 289U, 2449U, 2518U, 25039U, 2500U, 175U, 2372U, 258U,
10830 2438U, 315U, 2470U, 2491U, 298U, 2460U, 324U, 2481U,
10831 2526U, 267U, 306U, 60U, 48228U, 37941U, 37960U, 38275U,
10832 41060U, 39974U, 38299U, 40268U, 42220U, 40194U, 41097U, 38427U,
10833 40331U, 42452U, 42392U, 41153U, 37992U, 41636U, 40765U, 40669U,
10834 41186U, 41740U, 39915U, 41686U, 40795U, 40697U, 41252U, 41818U,
10835 39559U, 42278U, 38741U, 39887U, 41219U, 41779U, 41285U, 41857U,
10836 39577U, 42307U, 41443U, 41935U, 42207U, 41971U, 40825U, 40854U,
10837 41410U, 41896U, 39255U, 41475U, 39236U, 41460U, 39275U, 41491U,
10838 38778U, 40077U, 41987U, 39596U, 42322U, 42123U, 40638U, 38795U,
10839 40168U, 42001U, 39613U, 42366U, 42137U, 28445U, 38081U, 39760U,
10840 40020U, 39793U, 38332U, 39776U, 40286U, 39809U, 42438U, 39842U,
10841 42251U, 39826U, 39859U, 42165U, 126U, 84U, 42178U, 38200U,
10842 40063U, 39006U, 40963U, 39458U, 41702U, 38609U, 38154U, 39436U,
10843 41652U, 39145U, 41319U, 39104U, 41302U, 39167U, 41337U, 39191U,
10844 41357U, 39214U, 41376U, 38812U, 40253U, 22777U, 22797U, 22861U,
10845 22818U, 22882U, 22840U, 40181U, 42015U, 42379U, 42151U, 38515U,
10846 40552U, 38457U, 40429U, 42466U, 38214U, 40108U, 38413U, 40317U,
10847 42353U, 38987U, 40948U, 42058U, 39341U, 41545U, 42107U, 38553U,
10848 38094U, 38590U, 38139U, 39066U, 41011U, 39539U, 42091U, 39418U,
10849 41606U, 40379U, 38909U, 40565U, 39125U, 40900U, 40933U, 39085U,
10850 41026U, 39500U, 42044U, 40916U, 38870U, 38831U, 40362U, 38760U,
10851 40033U, 38571U, 38124U, 40507U, 38704U, 38500U, 38890U, 40473U,
10852 38647U, 38441U, 40523U, 39741U, 39630U, 39654U, 38686U, 38486U,
10853 39380U, 41576U, 38852U, 40443U, 39481U, 42029U, 38067U, 40006U,
10854 38317U, 42237U, 40218U, 42421U, 38021U, 39943U, 41041U, 41077U,
10855 38260U, 40153U, 41134U, 41114U, 40235U, 39294U, 41506U, 39026U,
10856 40979U, 38966U, 40621U, 39518U, 42074U, 39399U, 41591U, 38667U,
10857 38471U, 39318U, 41526U, 38946U, 40605U, 39360U, 41560U, 40887U,
10858 38108U, 38346U, 38378U, 40395U, 40457U, 40345U, 38926U, 40589U,
10859 38363U, 40413U, 40538U, 38288U, 39674U, 40090U, 40711U, 39719U,
10860 42335U, 39696U, 40488U, 40730U, 40868U, 40207U, 39928U, 38052U,
10861 38005U, 39991U, 38227U, 38036U, 39958U, 40121U, 37979U, 41620U,
10862 40750U, 40655U, 41170U, 41721U, 39902U, 41670U, 40780U, 40683U,
10863 41236U, 41799U, 42264U, 39872U, 41202U, 41759U, 41268U, 41837U,
10864 42292U, 41426U, 41915U, 42194U, 41955U, 40810U, 40840U, 41394U,
10865 41877U, 38723U, 38528U, 39046U, 40995U, 38628U, 38169U, 25563U,
10866 38184U, 40047U, 38243U, 40136U, 38396U, 40300U, 38542U, 40578U,
10867 118U, 220U, 12919U, 15365U, 25687U, 25701U, 12722U, 18515U,
10868 30772U, 18705U, 10051U, 16169U, 30671U, 21244U, 10072U, 16190U,
10869 18722U, 30785U, 21132U, 14707U, 37896U, 14722U, 37923U, 20929U,
10870 13824U, 23145U, 23232U, 23741U, 23838U, 23214U, 23806U, 13789U,
10871 23162U, 23249U, 23758U, 23855U, 23180U, 23873U, 33736U, 28901U,
10872 37481U, 12726U, 15604U, 21958U, 15740U, 22131U, 15652U, 22036U,
10873 15788U, 22209U, 21988U, 22161U, 22074U, 22247U, 18519U, 28135U,
10874 37470U, 37094U, 15958U, 22325U, 12933U, 30776U, 28143U, 15817U,
10875 16021U, 15619U, 22003U, 15755U, 22176U, 18709U, 46691U, 47665U,
10876 29074U, 45658U, 29056U, 22601U, 28457U, 44608U, 29023U, 28228U,
10877 37255U, 28621U, 28971U, 30886U, 30802U, 28821U, 14276U, 46505U,
10878 14697U, 46581U, 37886U, 46850U, 37683U, 46774U, 14285U, 46517U,
10879 37692U, 46786U, 14794U, 46641U, 44371U, 46910U, 14199U, 46493U,
10880 37618U, 46762U, 14802U, 46652U, 44379U, 46921U, 37243U, 36682U,
10881 10026U, 16117U, 10330U, 16328U, 10305U, 15589U, 21943U, 15725U,
10882 22116U, 15633U, 22017U, 15769U, 22190U, 21973U, 22146U, 22055U,
10883 22228U, 28095U, 21123U, 37080U, 15417U, 35076U, 35132U, 15579U,
10884 35087U, 15550U, 15321U, 35055U, 35109U, 48370U, 10055U, 16173U,
10885 47412U, 30675U, 33284U, 15682U, 22107U, 30580U, 21248U, 16080U,
10886 37302U, 47349U, 37544U, 15399U, 35066U, 10130U, 35011U, 35121U,
10887 46406U, 35317U, 15561U, 30082U, 30751U, 10179U, 30059U, 16252U,
10888 30761U, 47448U, 33711U, 47036U, 30613U, 33688U, 29175U, 45534U,
10889 29196U, 37765U, 45557U, 29269U, 37807U, 45579U, 21611U, 10423U,
10890 16705U, 10360U, 16432U, 47521U, 47625U, 9854U, 15882U, 10273U,
10891 16296U, 47479U, 47246U, 15530U, 30070U, 30740U, 47016U, 30601U,
10892 33677U, 10119U, 10898U, 10108U, 10883U, 15303U, 35045U, 10098U,
10893 35000U, 35098U, 46375U, 35307U, 31382U, 28828U, 16194U, 10541U,
10894 22509U, 28436U, 37911U, 21359U, 18656U, 25045U, 29165U, 20849U,
10895 37734U, 21291U, 45523U, 21395U, 29186U, 20872U, 37755U, 21314U,
10896 45546U, 21420U, 18726U, 30789U, 21136U, 20992U, 32100U, 44538U,
10897 44616U, 22665U, 28465U, 14648U, 46529U, 37828U, 46798U, 14658U,
10898 46542U, 37838U, 46811U, 14179U, 46467U, 37598U, 46736U, 14677U,
10899 46555U, 37848U, 46824U, 14189U, 46480U, 37608U, 46749U, 14687U,
10900 46568U, 37858U, 46837U, 29259U, 20943U, 29217U, 20906U, 20980U,
10901 36860U, 32088U, 36939U, 10531U, 28647U, 28114U, 15331U, 48247U,
10902 20860U, 37744U, 21302U, 21407U, 20883U, 21325U, 21432U, 20954U,
10903 21347U, 21456U, 16695U, 16421U, 47510U, 47615U, 15872U, 16285U,
10904 47468U, 47236U, 8102U, 35022U, 48262U, 7667U, 28360U, 20966U,
10905 32074U, 28368U, 5033U, 12940U, 22501U, 5055U, 30819U, 21149U,
10906 37711U, 15100U, 15114U, 44507U, 44493U, 14711U, 37900U, 14726U,
10907 37927U, 29228U, 20933U, 28700U, 37776U, 21337U, 28948U, 45569U,
10908 21445U, 29045U, 21828U, 48167U, 18739U, 30810U, 21199U, 43888U,
10909 30892U, 22658U, 32012U, 28836U, 21733U, 48174U, 31389U, 12610U,
10910 13012U, 22517U, 30943U, 22672U, 13980U, 18633U, 44597U, 21383U,
10911 29207U, 20895U, 5063U, 43895U, 30830U, 21161U, 37722U, 13366U,
10912 22541U, 31257U, 22683U, 13762U, 4565U, 4750U, 2342U, 4544U,
10913 4687U, 4736U, 4868U, 4891U, 4992U, 5006U, 5041U, 5078U,
10914 5111U, 5185U, 5555U, 5939U, 6328U, 6407U, 8056U, 14208U,
10915 14821U, 12680U, 28473U, 14848U, 13664U, 28509U, 47420U, 28583U,
10916 46201U, 28547U, 12693U, 28491U, 14235U, 13678U, 28528U, 47434U,
10917 28602U, 46214U, 28565U, 14221U, 14834U, 14262U, 14875U, 14249U,
10918 14862U, 12788U, 35193U, 29237U, 13729U, 37785U, 25076U, 22454U,
10919 25202U, 47672U, 22608U, 48000U, 15671U, 15834U, 22314U, 10312U,
10920 12797U, 35204U, 29248U, 13740U, 37796U, 25087U, 13652U, 22646U,
10921 32021U, 9353U, 9752U, 12620U, 35159U, 9765U, 22465U, 25213U,
10922 9459U, 47681U, 22617U, 48299U, 9395U, 10321U, 28636U, 33273U,
10923 28103U, 30569U, 6606U, 22266U, 14740U, 30842U, 14784U, 16001U,
10924 44361U, 42479U, 28428U, 14749U, 46594U, 44092U, 44028U, 31990U,
10925 14811U, 46664U, 44106U, 44039U, 48344U, 44182U, 16011U, 48357U,
10926 44197U, 48378U, 44212U, 44388U, 46933U, 44151U, 44080U, 48403U,
10927 44225U, 44051U, 46863U, 44137U, 44069U, 16776U, 44545U, 29485U,
10928 44571U, 16800U, 44558U, 29495U, 44584U, 13924U, 21208U, 33305U,
10929 21220U, 33317U, 21232U, 33329U, 13990U, 183U, 2640U, 13944U,
10930 43433U, 36274U, 42633U, 35510U, 43033U, 35892U, 43676U, 36506U,
10931 42833U, 35701U, 43233U, 36083U, 43366U, 36210U, 42566U, 35446U,
10932 42966U, 35828U, 43609U, 36442U, 42766U, 35637U, 43166U, 36019U,
10933 43320U, 36166U, 42520U, 35402U, 42920U, 35784U, 43563U, 36398U,
10934 42720U, 35593U, 43120U, 35975U, 43454U, 36294U, 42654U, 35530U,
10935 43054U, 35912U, 43697U, 36526U, 42854U, 35721U, 43254U, 36103U,
10936 43388U, 36231U, 42588U, 35467U, 42988U, 35849U, 43631U, 36463U,
10937 42788U, 35658U, 43188U, 36040U, 43343U, 36188U, 42543U, 35424U,
10938 42943U, 35806U, 43586U, 36420U, 42743U, 35615U, 43143U, 35997U,
10939 43496U, 36334U, 42675U, 35550U, 43075U, 35932U, 43739U, 36566U,
10940 42875U, 35741U, 43275U, 36123U, 43410U, 36252U, 42610U, 35488U,
10941 43010U, 35870U, 43653U, 36484U, 42810U, 35679U, 43210U, 36061U,
10942 43475U, 36314U, 43718U, 36546U, 43518U, 36355U, 43761U, 36587U,
10943 31999U, 21279U, 33361U, 43297U, 36144U, 42497U, 35380U, 42897U,
10944 35762U, 43540U, 36376U, 42697U, 35571U, 43097U, 35953U, 13808U,
10945 22976U, 29808U, 18094U, 30157U, 18883U, 31755U, 23572U, 29914U,
10946 18288U, 30351U, 19781U, 31854U, 22902U, 29744U, 18030U, 30093U,
10947 18773U, 31695U, 22932U, 29776U, 18062U, 30125U, 18803U, 31725U,
10948 22917U, 29760U, 18046U, 30109U, 18788U, 31710U, 22947U, 29792U,
10949 18078U, 30141U, 18818U, 31740U, 23132U, 29826U, 18112U, 30175U,
10950 18900U, 31772U, 28165U, 23236U, 29870U, 18200U, 30263U, 19511U,
10951 31813U, 28203U, 23728U, 29932U, 18306U, 30369U, 19798U, 31871U,
10952 28249U, 23842U, 29976U, 18394U, 30457U, 19839U, 31912U, 28287U,
10953 23218U, 29855U, 18170U, 30233U, 18927U, 31799U, 28190U, 23792U,
10954 29961U, 18364U, 30427U, 19825U, 31898U, 28274U, 29133U, 12864U,
10955 23267U, 19538U, 24186U, 20264U, 23892U, 19953U, 24548U, 20569U,
10956 23330U, 19585U, 24261U, 20320U, 23955U, 20000U, 24623U, 20625U,
10957 23377U, 19632U, 24317U, 20376U, 24002U, 20047U, 24679U, 20681U,
10958 23440U, 19679U, 24392U, 20432U, 24065U, 20094U, 24754U, 20737U,
10959 23314U, 19569U, 24242U, 20301U, 23939U, 19984U, 24604U, 20606U,
10960 23424U, 19663U, 24373U, 20413U, 24049U, 20078U, 24735U, 20718U,
10961 23028U, 23624U, 24925U, 23063U, 23659U, 24960U, 23045U, 23641U,
10962 24942U, 23080U, 23676U, 24977U, 23114U, 23710U, 25011U, 23010U,
10963 23606U, 24907U, 25328U, 33442U, 25427U, 33541U, 25268U, 33382U,
10964 25298U, 33412U, 25283U, 33397U, 25313U, 33427U, 29121U, 12831U,
10965 25345U, 32033U, 33459U, 25386U, 32113U, 33500U, 25444U, 32383U,
10966 33558U, 25485U, 32424U, 33599U, 25372U, 32060U, 33486U, 25471U,
10967 32410U, 33585U, 35327U, 23098U, 23694U, 24995U, 33743U, 32140U,
10968 34229U, 32697U, 33986U, 32451U, 34514U, 33002U, 33793U, 32187U,
10969 34288U, 32753U, 34036U, 32498U, 34573U, 33058U, 33843U, 32234U,
10970 34347U, 32809U, 34086U, 32545U, 34632U, 33114U, 33893U, 32281U,
10971 34406U, 32865U, 34136U, 32592U, 34691U, 33170U, 33776U, 32171U,
10972 34268U, 32734U, 34019U, 32482U, 34553U, 33039U, 33876U, 32265U,
10973 34386U, 32846U, 34119U, 32576U, 34671U, 33151U, 22704U, 14071U,
10974 43783U, 43934U, 35368U, 43832U, 43981U, 22993U, 23589U, 24890U,
10975 48280U, 7381U, 17977U, 18686U, 1206U, 1913U, 1991U, 4191U,
10976 452U, 2735U, 1232U, 1939U, 2110U, 4310U, 478U, 2761U,
10977 2151U, 4337U, 492U, 2775U, 2016U, 4216U, 465U, 2748U,
10978 416U, 344U, 505U, 2137U, 434U, 362U, 2204U, 4431U,
10979 3471U, 4472U, 4139U, 17960U, 22626U, 28377U, 2284U, 4486U,
10980 2056U, 4256U, 2313U, 4515U, 2083U, 4283U, 2298U, 4500U,
10981 2069U, 4269U, 2327U, 4529U, 2096U, 4296U, 2244U, 4418U,
10982 1194U, 3459U, 2271U, 4459U, 1901U, 4127U, 2230U, 4404U,
10983 1181U, 3446U, 2257U, 4445U, 1888U, 4114U, 17968U, 664U,
10984 2929U, 1385U, 3611U, 979U, 3244U, 1700U, 3926U, 787U,
10985 3052U, 1508U, 3734U, 1102U, 3367U, 1823U, 4049U, 839U,
10986 3104U, 1560U, 3786U, 1154U, 3419U, 1875U, 4101U, 592U,
10987 2857U, 1313U, 3539U, 907U, 3172U, 1628U, 3854U, 766U,
10988 3031U, 1487U, 3713U, 1081U, 3346U, 1802U, 4028U, 720U,
10989 2985U, 1441U, 3667U, 1035U, 3300U, 1756U, 3982U, 808U,
10990 3073U, 1529U, 3755U, 1123U, 3388U, 1844U, 4070U, 699U,
10991 2964U, 1420U, 3646U, 1014U, 3279U, 1735U, 3961U, 29013U,
10992 4152U, 36665U, 628U, 2893U, 1349U, 3575U, 943U, 3208U,
10993 1664U, 3890U, 752U, 3017U, 1473U, 3699U, 1067U, 3332U,
10994 1788U, 4014U, 556U, 2821U, 1277U, 3503U, 871U, 3136U,
10995 1592U, 3818U, 681U, 2946U, 1402U, 3628U, 996U, 3261U,
10996 1717U, 3943U, 21603U, 22636U, 28387U, 28990U, 646U, 2911U,
10997 1367U, 3593U, 961U, 3226U, 1682U, 3908U, 825U, 3090U,
10998 1546U, 3772U, 1140U, 3405U, 1861U, 4087U, 574U, 2839U,
10999 1295U, 3521U, 889U, 3154U, 1610U, 3836U, 29002U, 609U,
11000 2874U, 1330U, 3556U, 924U, 3189U, 1645U, 3871U, 737U,
11001 3002U, 1458U, 3684U, 1052U, 3317U, 1773U, 3999U, 537U,
11002 2802U, 1258U, 3484U, 852U, 3117U, 1573U, 3799U, 17985U,
11003 18695U, 12350U, 15472U, 46960U, 16852U, 29607U, 16870U, 29625U,
11004 16888U, 29643U, 2003U, 4203U, 2123U, 4323U, 2163U, 4363U,
11005 4662U, 35034U, 2028U, 4228U, 1965U, 4165U, 2176U, 4376U,
11006 2042U, 4242U, 1978U, 21629U, 4178U, 21646U, 2190U, 4390U,
11007 15389U, 16227U, 1218U, 10471U, 1925U, 10501U, 1244U, 10486U,
11008 1951U, 10516U, 15155U, 21880U, 15175U, 21900U, 15218U, 21916U,
11009 332U, 2218U, 12526U, 13023U, 22529U, 30953U, 31461U, 16546U,
11010 12558U, 16558U, 12571U, 36631U, 18527U, 30624U, 4701U, 18541U,
11011 30638U, 36648U, 13376U, 22552U, 31266U, 31624U, 47656U, 12227U,
11012 16736U, 11256U, 380U, 2681U, 523U, 2788U, 398U, 2699U,
11013 1167U, 3432U, 13386U, 22563U, 31275U, 12538U, 45441U, 45476U,
11014 45465U, 45624U, 45500U, 45647U, 45453U, 45612U, 45488U, 45635U,
11015 9585U, 10140U, 47157U, 12158U, 12632U, 10987U, 47327U, 12212U,
11016 12656U, 11003U, 47168U, 13535U, 12644U, 13458U, 47338U, 13550U,
11017 12668U, 13474U, 21868U, 30862U, 37701U, 15089U, 46677U, 44121U,
11018 44451U, 46946U, 44166U, 34799U, 34840U, 34881U, 34922U, 34826U,
11019 34908U, 34812U, 34949U, 34853U, 34867U, 34894U, 34966U, 34935U,
11020 34983U, 2649U, 21478U, 21533U, 4783U, 8872U, 5326U, 5199U,
11021 4841U, 8938U, 5400U, 5265U, 21184U, 13775U, 25169U, 11347U,
11022 13141U, 10566U, 31047U, 12446U, 29516U, 11467U, 13261U, 10686U,
11023 31159U, 36894U, 12494U, 16462U, 47531U, 25224U, 11392U, 13186U,
11024 10611U, 31089U, 31564U, 29563U, 11512U, 13306U, 10731U, 31201U,
11025 36909U, 16498U, 47567U, 25180U, 11362U, 13156U, 10581U, 31061U,
11026 13505U, 29527U, 11482U, 13276U, 10701U, 31173U, 13520U, 22714U,
11027 16474U, 47543U, 25246U, 11422U, 13216U, 10641U, 31117U, 31594U,
11028 29585U, 11542U, 13336U, 10761U, 31229U, 36924U, 22732U, 16522U,
11029 47591U, 45997U, 29065U, 22586U, 168U, 25126U, 2622U, 25142U,
11030 9824U, 22417U, 28066U, 16921U, 29676U, 2356U, 25134U, 4558U,
11031 25150U, 14028U, 45511U, 28798U, 29032U, 28755U, 44334U, 28785U,
11032 28979U, 28741U, 14014U, 28928U, 25235U, 11407U, 13201U, 10626U,
11033 31103U, 31579U, 29574U, 11527U, 13321U, 10746U, 31215U, 16510U,
11034 47579U, 25191U, 11377U, 13171U, 10596U, 31075U, 12462U, 29538U,
11035 11497U, 13291U, 10716U, 31187U, 12510U, 16486U, 47555U, 25257U,
11036 11437U, 13231U, 10656U, 31131U, 31609U, 29596U, 11557U, 13351U,
11037 10776U, 31243U, 16534U, 47603U, 21836U, 22097U, 29082U, 23282U,
11038 19553U, 20282U, 23501U, 19724U, 20469U, 24112U, 20155U, 20774U,
11039 23907U, 19968U, 20587U, 23345U, 19600U, 20338U, 23970U, 20015U,
11040 20643U, 23361U, 19616U, 20357U, 23986U, 20031U, 20662U, 23392U,
11041 19647U, 20394U, 23520U, 19743U, 20491U, 24131U, 20174U, 20796U,
11042 24017U, 20062U, 20699U, 23455U, 19694U, 20450U, 23539U, 19762U,
11043 20513U, 24150U, 20193U, 20818U, 24080U, 20109U, 20755U, 16933U,
11044 29688U, 9539U, 15427U, 9872U, 15912U, 23166U, 29840U, 18140U,
11045 30203U, 18913U, 31785U, 28177U, 24169U, 30005U, 18452U, 30515U,
11046 20247U, 31939U, 28312U, 23253U, 29884U, 18228U, 30291U, 19524U,
11047 31826U, 28215U, 23487U, 29899U, 18258U, 30321U, 19710U, 31840U,
11048 28236U, 23762U, 29946U, 18334U, 30397U, 19811U, 31884U, 28261U,
11049 24514U, 30023U, 18470U, 30533U, 20535U, 31956U, 28328U, 23859U,
11050 29990U, 18422U, 30485U, 19852U, 31925U, 28299U, 24531U, 30041U,
11051 18488U, 30551U, 20552U, 31973U, 28344U, 12880U, 21514U, 21569U,
11052 9695U, 10234U, 10441U, 13692U, 16723U, 47643U, 16906U, 29661U,
11053 16945U, 29700U, 9778U, 9953U, 15520U, 13968U, 15509U, 16605U,
11054 35144U, 9685U, 21663U, 10212U, 21680U, 16664U, 21716U, 16384U,
11055 21698U, 9974U, 16047U, 9739U, 9940U, 15248U, 47103U, 9650U,
11056 16582U, 9673U, 16631U, 15258U, 47113U, 18577U, 21020U, 21079U,
11057 21035U, 21094U, 18555U, 18588U, 22428U, 37627U, 28771U, 28936U,
11058 28726U, 18748U, 16957U, 29712U, 18612U, 47988U, 21174U, 21050U,
11059 21109U, 48334U, 33759U, 32155U, 34248U, 24204U, 32715U, 33926U,
11060 32326U, 34445U, 24448U, 32902U, 34169U, 32623U, 34730U, 24810U,
11061 33207U, 34002U, 32466U, 34533U, 24566U, 33020U, 33809U, 32202U,
11062 34307U, 24279U, 32771U, 34052U, 32513U, 34592U, 24641U, 33076U,
11063 33826U, 32218U, 34327U, 24298U, 32790U, 34069U, 32529U, 34612U,
11064 24660U, 33095U, 33859U, 32249U, 34366U, 24335U, 32827U, 33946U,
11065 32345U, 34468U, 24470U, 32924U, 34189U, 32642U, 34753U, 24832U,
11066 33229U, 34102U, 32560U, 34651U, 24697U, 33132U, 33909U, 32296U,
11067 34425U, 24410U, 32883U, 33966U, 32364U, 34491U, 24492U, 32946U,
11068 34209U, 32661U, 34776U, 24854U, 33251U, 34152U, 32607U, 34710U,
11069 24772U, 33188U, 12847U, 21495U, 21550U, 23184U, 23298U, 24223U,
11070 23923U, 24585U, 23776U, 23408U, 24354U, 24033U, 24716U, 23877U,
11071 23471U, 24429U, 24096U, 24791U, 25358U, 32046U, 33472U, 25512U,
11072 32680U, 33626U, 25399U, 32126U, 33513U, 25413U, 32312U, 33527U,
11073 25457U, 32396U, 33571U, 25529U, 32968U, 33643U, 25498U, 32437U,
11074 33612U, 25546U, 32985U, 33660U, 18566U, 21005U, 21064U, 13955U,
11075 11034U, 15290U, 30712U, 46362U, 15376U, 30726U, 46393U, 36798U,
11076 36784U, 28958U, 13602U, 25158U, 11332U, 13126U, 10551U, 31033U,
11077 12430U, 29505U, 11452U, 13246U, 10671U, 31145U, 12478U, 28082U,
11078 28668U, 28684U, 18506U, 48157U, 28909U, 2578U, 14775U, 46629U,
11079 44352U, 46898U, 20918U, 16762U, 16786U, 16810U, 16824U, 48389U,
11080 33722U, 12550U, 12584U, 21270U, 2629U, 10042U, 16160U, 30663U,
11081 10063U, 16181U, 4818U, 6645U, 8969U, 5435U, 5296U, 8911U,
11082 5369U, 5238U, 23824U, 23199U, 13807U, 2557U, 14044U, 46434U,
11083 35341U, 46703U, 23131U, 28859U, 23727U, 28873U, 23791U, 22693U,
11084 14058U, 46451U, 35355U, 46720U, 22962U, 24876U, 13774U, 142U,
11085 2596U, 28845U, 23558U, 28887U, 155U, 2609U, 44524U, 4773U,
11086 47379U, 10014U, 16105U, 47367U, 13000U, 22440U, 43914U, 30932U,
11087 22476U, 4671U, 4718U, 31449U, 15968U, 47264U, 30U, 48190U,
11088 45U, 48209U, 16994U, 18857U, 44654U, 16970U, 17654U, 17374U,
11089 19295U, 45054U, 19901U, 45317U, 17142U, 19063U, 44811U, 17272U,
11090 19193U, 44947U, 17706U, 17670U, 17396U, 19317U, 45077U, 19917U,
11091 45334U, 17163U, 19084U, 44833U, 17421U, 19342U, 45103U, 20125U,
11092 45372U, 17187U, 19108U, 44858U, 17606U, 17349U, 19270U, 45028U,
11093 19882U, 45297U, 17118U, 19039U, 44786U, 18833U, 44628U, 17030U,
11094 18951U, 44693U, 17590U, 17327U, 19248U, 45005U, 19866U, 45280U,
11095 17097U, 19018U, 44764U, 17007U, 17308U, 19229U, 44985U, 18870U,
11096 44668U, 17064U, 18985U, 44729U, 16982U, 17835U, 17463U, 19384U,
11097 45147U, 20212U, 45404U, 17227U, 19148U, 44900U, 17290U, 19211U,
11098 44966U, 17549U, 19470U, 45237U, 17721U, 17851U, 17485U, 19406U,
11099 45170U, 20228U, 45421U, 17248U, 19169U, 44922U, 17442U, 19363U,
11100 45125U, 17568U, 19489U, 45257U, 20140U, 45388U, 17207U, 19128U,
11101 44879U, 17528U, 19449U, 45215U, 18845U, 44641U, 17047U, 18968U,
11102 44711U, 17510U, 19431U, 45196U, 17689U, 19936U, 45354U, 14574U,
11103 15032U, 9998U, 36755U, 15485U, 10154U, 16238U, 46973U, 16089U,
11104 36816U, 47358U, 36955U, 14374U, 14399U, 4936U, 48063U, 4586U,
11105 48029U, 14916U, 14120U, 14441U, 14969U, 9530U, 45722U, 29340U,
11106 29155U, 36980U, 45802U, 48321U, 25112U, 37582U, 15236U, 46333U,
11107 15408U, 45760U, 29362U, 29290U, 37277U, 45864U, 47064U, 12129U,
11108 15279U, 11124U, 37018U, 45833U, 36723U, 37327U, 45895U, 47134U,
11109 12143U, 37569U, 45957U, 46415U, 45985U, 29384U, 29415U, 37532U,
11110 45926U, 9843U, 17912U, 13450U, 44409U, 11885U, 44398U, 11870U,
11111 46090U, 46102U, 44421U, 11901U, 15825U, 11153U, 46005U, 47179U,
11112 12173U, 46162U, 25063U, 16029U, 11166U, 37104U, 36992U, 37120U,
11113 37031U, 46015U, 37137U, 37045U, 37191U, 37384U, 37155U, 37060U,
11114 37209U, 37399U, 47297U, 12199U, 16654U, 37227U, 37414U, 37174U,
11115 37370U, 46172U, 22575U, 28151U, 28413U, 9619U, 13565U, 15570U,
11116 13590U, 10189U, 13577U, 16262U, 13614U, 47458U, 13639U, 47045U,
11117 13627U, 13880U, 15146U, 46192U, 46081U, 13893U, 28397U, 14523U,
11118 15204U, 4949U, 4599U, 4616U, 46239U, 15043U, 14336U, 14927U,
11119 14510U, 9508U, 15191U, 14941U, 10084U, 16202U, 14455U, 14349U,
11120 14537U, 21934U, 9814U, 46227U, 15807U, 12819U, 9449U, 14469U,
11121 11087U, 35237U, 11587U, 45772U, 12048U, 9717U, 10853U, 45734U,
11122 12030U, 37440U, 11698U, 37427U, 11665U, 37454U, 11716U, 37491U,
11123 11736U, 37506U, 11755U, 16216U, 11179U, 9919U, 12947U, 30898U,
11124 31396U, 15980U, 13073U, 30999U, 31511U, 47276U, 13397U, 31285U,
11125 31634U, 14585U, 15057U, 14551U, 15009U, 14498U, 14997U, 15845U,
11126 29300U, 47074U, 29425U, 47197U, 29456U, 10034U, 12959U, 30909U,
11127 31408U, 14170U, 13034U, 30963U, 31472U, 16125U, 13085U, 31010U,
11128 31523U, 14668U, 13047U, 30975U, 31485U, 15080U, 13060U, 30987U,
11129 31498U, 10339U, 12987U, 30920U, 31436U, 16337U, 13113U, 31021U,
11130 31551U, 47501U, 13437U, 31307U, 31674U, 47391U, 13409U, 31296U,
11131 31646U, 44432U, 29395U, 33698U, 9831U, 17899U, 9965U, 16038U,
11132 46025U, 47306U, 46182U, 4882U, 10401U, 22349U, 12360U, 17994U,
11133 17948U, 16684U, 22363U, 12377U, 18012U, 18674U, 14159U, 14597U,
11134 15069U, 10432U, 16714U, 10370U, 16442U, 47634U, 14148U, 14563U,
11135 15021U, 9863U, 15891U, 10283U, 16306U, 47255U, 35226U, 11572U,
11136 46113U, 45601U, 11955U, 46150U, 9628U, 10809U, 37289U, 9706U,
11137 10838U, 37340U, 37355U, 14413U, 11069U, 4966U, 14320U, 14628U,
11138 4633U, 14304U, 14608U, 4905U, 14889U, 14134U, 11051U, 14484U,
11139 11106U, 14983U, 35273U, 11635U, 46138U, 12113U, 45700U, 12016U,
11140 16372U, 4758U, 16746U, 11270U, 11682U, 35168U, 35215U, 35284U,
11141 11650U, 46046U, 12082U, 35180U, 15900U, 11225U, 16359U, 11194U,
11142 15703U, 11139U, 9662U, 10823U, 16619U, 10412U, 10958U, 16594U,
11143 11241U, 10348U, 10913U, 16643U, 10791U, 13490U, 12394U, 12414U,
11144 10391U, 10944U, 45678U, 11986U, 16452U, 11211U, 13751U, 11019U,
11145 46035U, 12067U, 35295U, 48182U, 9609U, 15540U, 10168U, 47026U,
11146 13866U, 46071U, 16133U, 47399U, 43926U, 31375U, 9562U, 15449U,
11147 36740U, 36768U, 9908U, 15947U, 36845U, 36829U, 16146U, 9927U,
11148 15988U, 47284U, 9438U, 44462U, 11916U, 35249U, 11603U, 21257U,
11149 11315U, 46125U, 12096U, 45689U, 12001U, 10380U, 10929U, 44478U,
11150 11936U, 17936U, 11299U, 45666U, 11970U, 44237U, 11773U, 48080U,
11151 12240U, 44282U, 11830U, 48125U, 12297U, 44252U, 11792U, 48095U,
11152 12259U, 44298U, 11850U, 48141U, 12317U, 44267U, 11811U, 48110U,
11153 12278U, 31367U, 33373U, 9638U, 10199U, 10246U, 16395U, 16570U,
11154 16346U, 17924U, 11283U, 46424U, 10223U, 16409U, 16674U, 10007U,
11155 15858U, 12733U, 29314U, 47088U, 12751U, 29440U, 47210U, 12770U,
11156 29470U, 16098U, 15438U, 14294U, 9598U, 9550U, 15498U, 9883U,
11157 12806U, 9573U, 15460U, 15923U, 14363U, 14385U, 4923U, 48046U,
11158 4573U, 48012U, 14905U, 14106U, 14427U, 14955U, 9521U, 45710U,
11159 29329U, 29145U, 36968U, 45787U, 48308U, 25098U, 15312U, 45748U,
11160 29351U, 29280U, 37265U, 45849U, 47054U, 15268U, 37005U, 45817U,
11161 36706U, 37314U, 45879U, 47123U, 37556U, 45941U, 46384U, 45973U,
11162 29373U, 29405U, 37520U, 45911U, 28057U, 10454U, 10973U, 35261U,
11163 11619U, 9728U, 10868U, 9802U, 15713U, 9895U, 15934U, 10260U,
11164 16272U, 5020U, 22335U, 29107U, 22402U, 4979U, 36689U, 29093U,
11165 36876U, 31687U, 10464U, 16755U, 17020U, 18941U, 44682U, 17082U,
11166 19003U, 44748U, 37638U, 30652U, 21620U, 12706U, 192U, 21595U,
11167 9362U, 47904U, 9493U, 47971U, 22750U, 9473U, 47930U, 22284U,
11168 30692U, 46996U, 9384U, 21844U, 30874U, 47224U, 29725U, 46322U,
11169 9483U, 47942U, 22294U, 30702U, 47006U, 12592U, 21759U, 21780U,
11170 47954U, 22274U, 13844U, 21856U, 25028U, 44314U, 28628U, 21588U,
11171 37818U, 33294U, 30590U, 21769U, 28074U, 29736U, 21792U, 46345U,
11172 37868U, 2658U, 18U, 15343U, 30682U, 46986U, 18756U, 12714U,
11173 28657U, 28124U, 13705U, 46353U, 47890U, 15354U, 22489U, 46056U,
11174 21805U, 47918U, 9329U, 9340U, 18600U, 12601U, 15131U, 133U,
11175 2587U, 21818U, 13933U, 22304U, 13854U, 44323U, 37876U, 9421U,
11176 9407U, 37090U, 37076U, 22093U, 13714U,
11177};
11178
11179static inline void InitHexagonMCInstrInfo(MCInstrInfo *II) {
11180 II->InitMCInstrInfo(HexagonDescs.Insts, HexagonInstrNameIndices, HexagonInstrNameData, nullptr, nullptr, 3341);
11181}
11182
11183} // end namespace llvm
11184#endif // GET_INSTRINFO_MC_DESC
11185
11186#ifdef GET_INSTRINFO_HEADER
11187#undef GET_INSTRINFO_HEADER
11188namespace llvm {
11189struct HexagonGenInstrInfo : public TargetInstrInfo {
11190 explicit HexagonGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
11191 ~HexagonGenInstrInfo() override = default;
11192
11193};
11194} // end namespace llvm
11195#endif // GET_INSTRINFO_HEADER
11196
11197#ifdef GET_INSTRINFO_HELPER_DECLS
11198#undef GET_INSTRINFO_HELPER_DECLS
11199
11200
11201#endif // GET_INSTRINFO_HELPER_DECLS
11202
11203#ifdef GET_INSTRINFO_HELPERS
11204#undef GET_INSTRINFO_HELPERS
11205
11206#endif // GET_INSTRINFO_HELPERS
11207
11208#ifdef GET_INSTRINFO_CTOR_DTOR
11209#undef GET_INSTRINFO_CTOR_DTOR
11210namespace llvm {
11211extern const HexagonInstrTable HexagonDescs;
11212extern const unsigned HexagonInstrNameIndices[];
11213extern const char HexagonInstrNameData[];
11214HexagonGenInstrInfo::HexagonGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
11215 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
11216 InitMCInstrInfo(HexagonDescs.Insts, HexagonInstrNameIndices, HexagonInstrNameData, nullptr, nullptr, 3341);
11217}
11218} // end namespace llvm
11219#endif // GET_INSTRINFO_CTOR_DTOR
11220
11221#ifdef GET_INSTRINFO_OPERAND_ENUM
11222#undef GET_INSTRINFO_OPERAND_ENUM
11223namespace llvm {
11224namespace Hexagon {
11225namespace OpName {
11226enum {
11227 OPERAND_LAST
11228};
11229} // end namespace OpName
11230} // end namespace Hexagon
11231} // end namespace llvm
11232#endif //GET_INSTRINFO_OPERAND_ENUM
11233
11234#ifdef GET_INSTRINFO_NAMED_OPS
11235#undef GET_INSTRINFO_NAMED_OPS
11236namespace llvm {
11237namespace Hexagon {
11238LLVM_READONLY
11239int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
11240 return -1;
11241}
11242} // end namespace Hexagon
11243} // end namespace llvm
11244#endif //GET_INSTRINFO_NAMED_OPS
11245
11246#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
11247#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
11248namespace llvm {
11249namespace Hexagon {
11250namespace OpTypes {
11251enum OperandType {
11252 a30_2Imm = 0,
11253 b13_2Imm = 1,
11254 b15_2Imm = 2,
11255 b30_2Imm = 3,
11256 bblabel = 4,
11257 f32Imm = 5,
11258 f32imm = 6,
11259 f64Imm = 7,
11260 f64imm = 8,
11261 globaladdress = 9,
11262 globaladdressExt = 10,
11263 i1imm = 11,
11264 i8imm = 12,
11265 i16imm = 13,
11266 i32imm = 14,
11267 i64imm = 15,
11268 m32_0Imm = 16,
11269 n1Const = 17,
11270 ptype0 = 18,
11271 ptype1 = 19,
11272 ptype2 = 20,
11273 ptype3 = 21,
11274 ptype4 = 22,
11275 ptype5 = 23,
11276 s3_0Imm = 24,
11277 s4_0Imm = 25,
11278 s4_1Imm = 26,
11279 s4_2Imm = 27,
11280 s4_3Imm = 28,
11281 s6_0Imm = 29,
11282 s6_3Imm = 30,
11283 s8_0Imm = 31,
11284 s9_0Imm = 32,
11285 s27_2Imm = 33,
11286 s29_3Imm = 34,
11287 s30_2Imm = 35,
11288 s31_1Imm = 36,
11289 s32_0Imm = 37,
11290 sgp10Const = 38,
11291 type0 = 39,
11292 type1 = 40,
11293 type2 = 41,
11294 type3 = 42,
11295 type4 = 43,
11296 type5 = 44,
11297 u1_0Imm = 45,
11298 u2_0Imm = 46,
11299 u3_0Imm = 47,
11300 u3_1Imm = 48,
11301 u4_0Imm = 49,
11302 u4_2Imm = 50,
11303 u5_0Imm = 51,
11304 u5_2Imm = 52,
11305 u5_3Imm = 53,
11306 u6_0Imm = 54,
11307 u6_1Imm = 55,
11308 u6_2Imm = 56,
11309 u7_0Imm = 57,
11310 u8_0Imm = 58,
11311 u10_0Imm = 59,
11312 u11_3Imm = 60,
11313 u16_0Imm = 61,
11314 u26_6Imm = 62,
11315 u29_3Imm = 63,
11316 u30_2Imm = 64,
11317 u31_1Imm = 65,
11318 u32_0Imm = 66,
11319 u64_0Imm = 67,
11320 untyped_imm_0 = 68,
11321 CtrRegs = 69,
11322 CtrRegs64 = 70,
11323 DoubleRegs = 71,
11324 GeneralDoubleLow8Regs = 72,
11325 GeneralSubRegs = 73,
11326 GuestRegs = 74,
11327 GuestRegs64 = 75,
11328 HvxQR = 76,
11329 HvxVQR = 77,
11330 HvxVR = 78,
11331 HvxWR = 79,
11332 IntRegs = 80,
11333 IntRegsLow8 = 81,
11334 ModRegs = 82,
11335 PredRegs = 83,
11336 SysRegs = 84,
11337 SysRegs64 = 85,
11338 UsrBits = 86,
11339 V62Regs = 87,
11340 V65Regs = 88,
11341 VectRegRev = 89,
11342 OPERAND_TYPE_LIST_END
11343};
11344} // end namespace OpTypes
11345} // end namespace Hexagon
11346} // end namespace llvm
11347#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
11348
11349#ifdef GET_INSTRINFO_OPERAND_TYPE
11350#undef GET_INSTRINFO_OPERAND_TYPE
11351namespace llvm {
11352namespace Hexagon {
11353LLVM_READONLY
11354static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
11355 static const uint16_t Offsets[] = {
11356 /* PHI */
11357 0,
11358 /* INLINEASM */
11359 1,
11360 /* INLINEASM_BR */
11361 1,
11362 /* CFI_INSTRUCTION */
11363 1,
11364 /* EH_LABEL */
11365 2,
11366 /* GC_LABEL */
11367 3,
11368 /* ANNOTATION_LABEL */
11369 4,
11370 /* KILL */
11371 5,
11372 /* EXTRACT_SUBREG */
11373 5,
11374 /* INSERT_SUBREG */
11375 8,
11376 /* IMPLICIT_DEF */
11377 12,
11378 /* SUBREG_TO_REG */
11379 13,
11380 /* COPY_TO_REGCLASS */
11381 17,
11382 /* DBG_VALUE */
11383 20,
11384 /* DBG_VALUE_LIST */
11385 20,
11386 /* DBG_INSTR_REF */
11387 20,
11388 /* DBG_PHI */
11389 20,
11390 /* DBG_LABEL */
11391 20,
11392 /* REG_SEQUENCE */
11393 21,
11394 /* COPY */
11395 23,
11396 /* BUNDLE */
11397 25,
11398 /* LIFETIME_START */
11399 25,
11400 /* LIFETIME_END */
11401 26,
11402 /* PSEUDO_PROBE */
11403 27,
11404 /* ARITH_FENCE */
11405 31,
11406 /* STACKMAP */
11407 33,
11408 /* FENTRY_CALL */
11409 35,
11410 /* PATCHPOINT */
11411 35,
11412 /* LOAD_STACK_GUARD */
11413 41,
11414 /* PREALLOCATED_SETUP */
11415 42,
11416 /* PREALLOCATED_ARG */
11417 43,
11418 /* STATEPOINT */
11419 46,
11420 /* LOCAL_ESCAPE */
11421 46,
11422 /* FAULTING_OP */
11423 48,
11424 /* PATCHABLE_OP */
11425 49,
11426 /* PATCHABLE_FUNCTION_ENTER */
11427 49,
11428 /* PATCHABLE_RET */
11429 49,
11430 /* PATCHABLE_FUNCTION_EXIT */
11431 49,
11432 /* PATCHABLE_TAIL_CALL */
11433 49,
11434 /* PATCHABLE_EVENT_CALL */
11435 49,
11436 /* PATCHABLE_TYPED_EVENT_CALL */
11437 51,
11438 /* ICALL_BRANCH_FUNNEL */
11439 54,
11440 /* MEMBARRIER */
11441 54,
11442 /* JUMP_TABLE_DEBUG_INFO */
11443 54,
11444 /* CONVERGENCECTRL_ENTRY */
11445 55,
11446 /* CONVERGENCECTRL_ANCHOR */
11447 56,
11448 /* CONVERGENCECTRL_LOOP */
11449 57,
11450 /* CONVERGENCECTRL_GLUE */
11451 59,
11452 /* G_ASSERT_SEXT */
11453 60,
11454 /* G_ASSERT_ZEXT */
11455 63,
11456 /* G_ASSERT_ALIGN */
11457 66,
11458 /* G_ADD */
11459 69,
11460 /* G_SUB */
11461 72,
11462 /* G_MUL */
11463 75,
11464 /* G_SDIV */
11465 78,
11466 /* G_UDIV */
11467 81,
11468 /* G_SREM */
11469 84,
11470 /* G_UREM */
11471 87,
11472 /* G_SDIVREM */
11473 90,
11474 /* G_UDIVREM */
11475 94,
11476 /* G_AND */
11477 98,
11478 /* G_OR */
11479 101,
11480 /* G_XOR */
11481 104,
11482 /* G_IMPLICIT_DEF */
11483 107,
11484 /* G_PHI */
11485 108,
11486 /* G_FRAME_INDEX */
11487 109,
11488 /* G_GLOBAL_VALUE */
11489 111,
11490 /* G_PTRAUTH_GLOBAL_VALUE */
11491 113,
11492 /* G_CONSTANT_POOL */
11493 118,
11494 /* G_EXTRACT */
11495 120,
11496 /* G_UNMERGE_VALUES */
11497 123,
11498 /* G_INSERT */
11499 125,
11500 /* G_MERGE_VALUES */
11501 129,
11502 /* G_BUILD_VECTOR */
11503 131,
11504 /* G_BUILD_VECTOR_TRUNC */
11505 133,
11506 /* G_CONCAT_VECTORS */
11507 135,
11508 /* G_PTRTOINT */
11509 137,
11510 /* G_INTTOPTR */
11511 139,
11512 /* G_BITCAST */
11513 141,
11514 /* G_FREEZE */
11515 143,
11516 /* G_CONSTANT_FOLD_BARRIER */
11517 145,
11518 /* G_INTRINSIC_FPTRUNC_ROUND */
11519 147,
11520 /* G_INTRINSIC_TRUNC */
11521 150,
11522 /* G_INTRINSIC_ROUND */
11523 152,
11524 /* G_INTRINSIC_LRINT */
11525 154,
11526 /* G_INTRINSIC_LLRINT */
11527 156,
11528 /* G_INTRINSIC_ROUNDEVEN */
11529 158,
11530 /* G_READCYCLECOUNTER */
11531 160,
11532 /* G_READSTEADYCOUNTER */
11533 161,
11534 /* G_LOAD */
11535 162,
11536 /* G_SEXTLOAD */
11537 164,
11538 /* G_ZEXTLOAD */
11539 166,
11540 /* G_INDEXED_LOAD */
11541 168,
11542 /* G_INDEXED_SEXTLOAD */
11543 173,
11544 /* G_INDEXED_ZEXTLOAD */
11545 178,
11546 /* G_STORE */
11547 183,
11548 /* G_INDEXED_STORE */
11549 185,
11550 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
11551 190,
11552 /* G_ATOMIC_CMPXCHG */
11553 195,
11554 /* G_ATOMICRMW_XCHG */
11555 199,
11556 /* G_ATOMICRMW_ADD */
11557 202,
11558 /* G_ATOMICRMW_SUB */
11559 205,
11560 /* G_ATOMICRMW_AND */
11561 208,
11562 /* G_ATOMICRMW_NAND */
11563 211,
11564 /* G_ATOMICRMW_OR */
11565 214,
11566 /* G_ATOMICRMW_XOR */
11567 217,
11568 /* G_ATOMICRMW_MAX */
11569 220,
11570 /* G_ATOMICRMW_MIN */
11571 223,
11572 /* G_ATOMICRMW_UMAX */
11573 226,
11574 /* G_ATOMICRMW_UMIN */
11575 229,
11576 /* G_ATOMICRMW_FADD */
11577 232,
11578 /* G_ATOMICRMW_FSUB */
11579 235,
11580 /* G_ATOMICRMW_FMAX */
11581 238,
11582 /* G_ATOMICRMW_FMIN */
11583 241,
11584 /* G_ATOMICRMW_UINC_WRAP */
11585 244,
11586 /* G_ATOMICRMW_UDEC_WRAP */
11587 247,
11588 /* G_FENCE */
11589 250,
11590 /* G_PREFETCH */
11591 252,
11592 /* G_BRCOND */
11593 256,
11594 /* G_BRINDIRECT */
11595 258,
11596 /* G_INVOKE_REGION_START */
11597 259,
11598 /* G_INTRINSIC */
11599 259,
11600 /* G_INTRINSIC_W_SIDE_EFFECTS */
11601 260,
11602 /* G_INTRINSIC_CONVERGENT */
11603 261,
11604 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
11605 262,
11606 /* G_ANYEXT */
11607 263,
11608 /* G_TRUNC */
11609 265,
11610 /* G_CONSTANT */
11611 267,
11612 /* G_FCONSTANT */
11613 269,
11614 /* G_VASTART */
11615 271,
11616 /* G_VAARG */
11617 272,
11618 /* G_SEXT */
11619 275,
11620 /* G_SEXT_INREG */
11621 277,
11622 /* G_ZEXT */
11623 280,
11624 /* G_SHL */
11625 282,
11626 /* G_LSHR */
11627 285,
11628 /* G_ASHR */
11629 288,
11630 /* G_FSHL */
11631 291,
11632 /* G_FSHR */
11633 295,
11634 /* G_ROTR */
11635 299,
11636 /* G_ROTL */
11637 302,
11638 /* G_ICMP */
11639 305,
11640 /* G_FCMP */
11641 309,
11642 /* G_SCMP */
11643 313,
11644 /* G_UCMP */
11645 316,
11646 /* G_SELECT */
11647 319,
11648 /* G_UADDO */
11649 323,
11650 /* G_UADDE */
11651 327,
11652 /* G_USUBO */
11653 332,
11654 /* G_USUBE */
11655 336,
11656 /* G_SADDO */
11657 341,
11658 /* G_SADDE */
11659 345,
11660 /* G_SSUBO */
11661 350,
11662 /* G_SSUBE */
11663 354,
11664 /* G_UMULO */
11665 359,
11666 /* G_SMULO */
11667 363,
11668 /* G_UMULH */
11669 367,
11670 /* G_SMULH */
11671 370,
11672 /* G_UADDSAT */
11673 373,
11674 /* G_SADDSAT */
11675 376,
11676 /* G_USUBSAT */
11677 379,
11678 /* G_SSUBSAT */
11679 382,
11680 /* G_USHLSAT */
11681 385,
11682 /* G_SSHLSAT */
11683 388,
11684 /* G_SMULFIX */
11685 391,
11686 /* G_UMULFIX */
11687 395,
11688 /* G_SMULFIXSAT */
11689 399,
11690 /* G_UMULFIXSAT */
11691 403,
11692 /* G_SDIVFIX */
11693 407,
11694 /* G_UDIVFIX */
11695 411,
11696 /* G_SDIVFIXSAT */
11697 415,
11698 /* G_UDIVFIXSAT */
11699 419,
11700 /* G_FADD */
11701 423,
11702 /* G_FSUB */
11703 426,
11704 /* G_FMUL */
11705 429,
11706 /* G_FMA */
11707 432,
11708 /* G_FMAD */
11709 436,
11710 /* G_FDIV */
11711 440,
11712 /* G_FREM */
11713 443,
11714 /* G_FPOW */
11715 446,
11716 /* G_FPOWI */
11717 449,
11718 /* G_FEXP */
11719 452,
11720 /* G_FEXP2 */
11721 454,
11722 /* G_FEXP10 */
11723 456,
11724 /* G_FLOG */
11725 458,
11726 /* G_FLOG2 */
11727 460,
11728 /* G_FLOG10 */
11729 462,
11730 /* G_FLDEXP */
11731 464,
11732 /* G_FFREXP */
11733 467,
11734 /* G_FNEG */
11735 470,
11736 /* G_FPEXT */
11737 472,
11738 /* G_FPTRUNC */
11739 474,
11740 /* G_FPTOSI */
11741 476,
11742 /* G_FPTOUI */
11743 478,
11744 /* G_SITOFP */
11745 480,
11746 /* G_UITOFP */
11747 482,
11748 /* G_FABS */
11749 484,
11750 /* G_FCOPYSIGN */
11751 486,
11752 /* G_IS_FPCLASS */
11753 489,
11754 /* G_FCANONICALIZE */
11755 492,
11756 /* G_FMINNUM */
11757 494,
11758 /* G_FMAXNUM */
11759 497,
11760 /* G_FMINNUM_IEEE */
11761 500,
11762 /* G_FMAXNUM_IEEE */
11763 503,
11764 /* G_FMINIMUM */
11765 506,
11766 /* G_FMAXIMUM */
11767 509,
11768 /* G_GET_FPENV */
11769 512,
11770 /* G_SET_FPENV */
11771 513,
11772 /* G_RESET_FPENV */
11773 514,
11774 /* G_GET_FPMODE */
11775 514,
11776 /* G_SET_FPMODE */
11777 515,
11778 /* G_RESET_FPMODE */
11779 516,
11780 /* G_PTR_ADD */
11781 516,
11782 /* G_PTRMASK */
11783 519,
11784 /* G_SMIN */
11785 522,
11786 /* G_SMAX */
11787 525,
11788 /* G_UMIN */
11789 528,
11790 /* G_UMAX */
11791 531,
11792 /* G_ABS */
11793 534,
11794 /* G_LROUND */
11795 536,
11796 /* G_LLROUND */
11797 538,
11798 /* G_BR */
11799 540,
11800 /* G_BRJT */
11801 541,
11802 /* G_VSCALE */
11803 544,
11804 /* G_INSERT_SUBVECTOR */
11805 546,
11806 /* G_EXTRACT_SUBVECTOR */
11807 550,
11808 /* G_INSERT_VECTOR_ELT */
11809 553,
11810 /* G_EXTRACT_VECTOR_ELT */
11811 557,
11812 /* G_SHUFFLE_VECTOR */
11813 560,
11814 /* G_SPLAT_VECTOR */
11815 564,
11816 /* G_VECTOR_COMPRESS */
11817 566,
11818 /* G_CTTZ */
11819 570,
11820 /* G_CTTZ_ZERO_UNDEF */
11821 572,
11822 /* G_CTLZ */
11823 574,
11824 /* G_CTLZ_ZERO_UNDEF */
11825 576,
11826 /* G_CTPOP */
11827 578,
11828 /* G_BSWAP */
11829 580,
11830 /* G_BITREVERSE */
11831 582,
11832 /* G_FCEIL */
11833 584,
11834 /* G_FCOS */
11835 586,
11836 /* G_FSIN */
11837 588,
11838 /* G_FTAN */
11839 590,
11840 /* G_FACOS */
11841 592,
11842 /* G_FASIN */
11843 594,
11844 /* G_FATAN */
11845 596,
11846 /* G_FCOSH */
11847 598,
11848 /* G_FSINH */
11849 600,
11850 /* G_FTANH */
11851 602,
11852 /* G_FSQRT */
11853 604,
11854 /* G_FFLOOR */
11855 606,
11856 /* G_FRINT */
11857 608,
11858 /* G_FNEARBYINT */
11859 610,
11860 /* G_ADDRSPACE_CAST */
11861 612,
11862 /* G_BLOCK_ADDR */
11863 614,
11864 /* G_JUMP_TABLE */
11865 616,
11866 /* G_DYN_STACKALLOC */
11867 618,
11868 /* G_STACKSAVE */
11869 621,
11870 /* G_STACKRESTORE */
11871 622,
11872 /* G_STRICT_FADD */
11873 623,
11874 /* G_STRICT_FSUB */
11875 626,
11876 /* G_STRICT_FMUL */
11877 629,
11878 /* G_STRICT_FDIV */
11879 632,
11880 /* G_STRICT_FREM */
11881 635,
11882 /* G_STRICT_FMA */
11883 638,
11884 /* G_STRICT_FSQRT */
11885 642,
11886 /* G_STRICT_FLDEXP */
11887 644,
11888 /* G_READ_REGISTER */
11889 647,
11890 /* G_WRITE_REGISTER */
11891 649,
11892 /* G_MEMCPY */
11893 651,
11894 /* G_MEMCPY_INLINE */
11895 655,
11896 /* G_MEMMOVE */
11897 658,
11898 /* G_MEMSET */
11899 662,
11900 /* G_BZERO */
11901 666,
11902 /* G_TRAP */
11903 669,
11904 /* G_DEBUGTRAP */
11905 669,
11906 /* G_UBSANTRAP */
11907 669,
11908 /* G_VECREDUCE_SEQ_FADD */
11909 670,
11910 /* G_VECREDUCE_SEQ_FMUL */
11911 673,
11912 /* G_VECREDUCE_FADD */
11913 676,
11914 /* G_VECREDUCE_FMUL */
11915 678,
11916 /* G_VECREDUCE_FMAX */
11917 680,
11918 /* G_VECREDUCE_FMIN */
11919 682,
11920 /* G_VECREDUCE_FMAXIMUM */
11921 684,
11922 /* G_VECREDUCE_FMINIMUM */
11923 686,
11924 /* G_VECREDUCE_ADD */
11925 688,
11926 /* G_VECREDUCE_MUL */
11927 690,
11928 /* G_VECREDUCE_AND */
11929 692,
11930 /* G_VECREDUCE_OR */
11931 694,
11932 /* G_VECREDUCE_XOR */
11933 696,
11934 /* G_VECREDUCE_SMAX */
11935 698,
11936 /* G_VECREDUCE_SMIN */
11937 700,
11938 /* G_VECREDUCE_UMAX */
11939 702,
11940 /* G_VECREDUCE_UMIN */
11941 704,
11942 /* G_SBFX */
11943 706,
11944 /* G_UBFX */
11945 710,
11946 /* A2_addsp */
11947 714,
11948 /* A2_iconst */
11949 717,
11950 /* A2_neg */
11951 719,
11952 /* A2_not */
11953 721,
11954 /* A2_tfrf */
11955 723,
11956 /* A2_tfrfnew */
11957 726,
11958 /* A2_tfrp */
11959 729,
11960 /* A2_tfrpf */
11961 731,
11962 /* A2_tfrpfnew */
11963 734,
11964 /* A2_tfrpi */
11965 737,
11966 /* A2_tfrpt */
11967 739,
11968 /* A2_tfrptnew */
11969 742,
11970 /* A2_tfrt */
11971 745,
11972 /* A2_tfrtnew */
11973 748,
11974 /* A2_vaddb_map */
11975 751,
11976 /* A2_vsubb_map */
11977 754,
11978 /* A2_zxtb */
11979 757,
11980 /* A4_boundscheck */
11981 759,
11982 /* ADJCALLSTACKDOWN */
11983 762,
11984 /* ADJCALLSTACKUP */
11985 764,
11986 /* C2_cmpgei */
11987 766,
11988 /* C2_cmpgeui */
11989 769,
11990 /* C2_cmplt */
11991 772,
11992 /* C2_cmpltu */
11993 775,
11994 /* C2_pxfer_map */
11995 778,
11996 /* DUPLEX_Pseudo */
11997 780,
11998 /* ENDLOOP0 */
11999 781,
12000 /* ENDLOOP01 */
12001 782,
12002 /* ENDLOOP1 */
12003 783,
12004 /* J2_endloop0 */
12005 784,
12006 /* J2_endloop01 */
12007 784,
12008 /* J2_endloop1 */
12009 784,
12010 /* J2_jumpf_nopred_map */
12011 784,
12012 /* J2_jumprf_nopred_map */
12013 786,
12014 /* J2_jumprt_nopred_map */
12015 788,
12016 /* J2_jumpt_nopred_map */
12017 790,
12018 /* J2_trap1_noregmap */
12019 792,
12020 /* L2_loadalignb_zomap */
12021 793,
12022 /* L2_loadalignh_zomap */
12023 796,
12024 /* L2_loadbsw2_zomap */
12025 799,
12026 /* L2_loadbsw4_zomap */
12027 801,
12028 /* L2_loadbzw2_zomap */
12029 803,
12030 /* L2_loadbzw4_zomap */
12031 805,
12032 /* L2_loadrb_zomap */
12033 807,
12034 /* L2_loadrd_zomap */
12035 809,
12036 /* L2_loadrh_zomap */
12037 811,
12038 /* L2_loadri_zomap */
12039 813,
12040 /* L2_loadrub_zomap */
12041 815,
12042 /* L2_loadruh_zomap */
12043 817,
12044 /* L2_ploadrbf_zomap */
12045 819,
12046 /* L2_ploadrbfnew_zomap */
12047 822,
12048 /* L2_ploadrbt_zomap */
12049 825,
12050 /* L2_ploadrbtnew_zomap */
12051 828,
12052 /* L2_ploadrdf_zomap */
12053 831,
12054 /* L2_ploadrdfnew_zomap */
12055 834,
12056 /* L2_ploadrdt_zomap */
12057 837,
12058 /* L2_ploadrdtnew_zomap */
12059 840,
12060 /* L2_ploadrhf_zomap */
12061 843,
12062 /* L2_ploadrhfnew_zomap */
12063 846,
12064 /* L2_ploadrht_zomap */
12065 849,
12066 /* L2_ploadrhtnew_zomap */
12067 852,
12068 /* L2_ploadrif_zomap */
12069 855,
12070 /* L2_ploadrifnew_zomap */
12071 858,
12072 /* L2_ploadrit_zomap */
12073 861,
12074 /* L2_ploadritnew_zomap */
12075 864,
12076 /* L2_ploadrubf_zomap */
12077 867,
12078 /* L2_ploadrubfnew_zomap */
12079 870,
12080 /* L2_ploadrubt_zomap */
12081 873,
12082 /* L2_ploadrubtnew_zomap */
12083 876,
12084 /* L2_ploadruhf_zomap */
12085 879,
12086 /* L2_ploadruhfnew_zomap */
12087 882,
12088 /* L2_ploadruht_zomap */
12089 885,
12090 /* L2_ploadruhtnew_zomap */
12091 888,
12092 /* L4_add_memopb_zomap */
12093 891,
12094 /* L4_add_memoph_zomap */
12095 893,
12096 /* L4_add_memopw_zomap */
12097 895,
12098 /* L4_and_memopb_zomap */
12099 897,
12100 /* L4_and_memoph_zomap */
12101 899,
12102 /* L4_and_memopw_zomap */
12103 901,
12104 /* L4_iadd_memopb_zomap */
12105 903,
12106 /* L4_iadd_memoph_zomap */
12107 905,
12108 /* L4_iadd_memopw_zomap */
12109 907,
12110 /* L4_iand_memopb_zomap */
12111 909,
12112 /* L4_iand_memoph_zomap */
12113 911,
12114 /* L4_iand_memopw_zomap */
12115 913,
12116 /* L4_ior_memopb_zomap */
12117 915,
12118 /* L4_ior_memoph_zomap */
12119 917,
12120 /* L4_ior_memopw_zomap */
12121 919,
12122 /* L4_isub_memopb_zomap */
12123 921,
12124 /* L4_isub_memoph_zomap */
12125 923,
12126 /* L4_isub_memopw_zomap */
12127 925,
12128 /* L4_or_memopb_zomap */
12129 927,
12130 /* L4_or_memoph_zomap */
12131 929,
12132 /* L4_or_memopw_zomap */
12133 931,
12134 /* L4_return_map_to_raw_f */
12135 933,
12136 /* L4_return_map_to_raw_fnew_pnt */
12137 934,
12138 /* L4_return_map_to_raw_fnew_pt */
12139 935,
12140 /* L4_return_map_to_raw_t */
12141 936,
12142 /* L4_return_map_to_raw_tnew_pnt */
12143 937,
12144 /* L4_return_map_to_raw_tnew_pt */
12145 938,
12146 /* L4_sub_memopb_zomap */
12147 939,
12148 /* L4_sub_memoph_zomap */
12149 941,
12150 /* L4_sub_memopw_zomap */
12151 943,
12152 /* L6_deallocframe_map_to_raw */
12153 945,
12154 /* L6_return_map_to_raw */
12155 945,
12156 /* LDriw_ctr */
12157 945,
12158 /* LDriw_pred */
12159 948,
12160 /* M2_mpysmi */
12161 951,
12162 /* M2_mpyui */
12163 954,
12164 /* M2_vrcmpys_acc_s1 */
12165 957,
12166 /* M2_vrcmpys_s1 */
12167 961,
12168 /* M2_vrcmpys_s1rp */
12169 964,
12170 /* M7_vdmpy */
12171 967,
12172 /* M7_vdmpy_acc */
12173 970,
12174 /* PS_aligna */
12175 974,
12176 /* PS_alloca */
12177 976,
12178 /* PS_call_instrprof_custom */
12179 979,
12180 /* PS_call_nr */
12181 981,
12182 /* PS_crash */
12183 982,
12184 /* PS_false */
12185 982,
12186 /* PS_fi */
12187 983,
12188 /* PS_fia */
12189 986,
12190 /* PS_loadrb_pci */
12191 990,
12192 /* PS_loadrb_pcr */
12193 996,
12194 /* PS_loadrd_pci */
12195 1001,
12196 /* PS_loadrd_pcr */
12197 1007,
12198 /* PS_loadrh_pci */
12199 1012,
12200 /* PS_loadrh_pcr */
12201 1018,
12202 /* PS_loadri_pci */
12203 1023,
12204 /* PS_loadri_pcr */
12205 1029,
12206 /* PS_loadrub_pci */
12207 1034,
12208 /* PS_loadrub_pcr */
12209 1040,
12210 /* PS_loadruh_pci */
12211 1045,
12212 /* PS_loadruh_pcr */
12213 1051,
12214 /* PS_pselect */
12215 1056,
12216 /* PS_qfalse */
12217 1060,
12218 /* PS_qtrue */
12219 1061,
12220 /* PS_storerb_pci */
12221 1062,
12222 /* PS_storerb_pcr */
12223 1068,
12224 /* PS_storerd_pci */
12225 1073,
12226 /* PS_storerd_pcr */
12227 1079,
12228 /* PS_storerf_pci */
12229 1084,
12230 /* PS_storerf_pcr */
12231 1090,
12232 /* PS_storerh_pci */
12233 1095,
12234 /* PS_storerh_pcr */
12235 1101,
12236 /* PS_storeri_pci */
12237 1106,
12238 /* PS_storeri_pcr */
12239 1112,
12240 /* PS_tailcall_i */
12241 1117,
12242 /* PS_tailcall_r */
12243 1118,
12244 /* PS_true */
12245 1119,
12246 /* PS_vdd0 */
12247 1120,
12248 /* PS_vloadrq_ai */
12249 1121,
12250 /* PS_vloadrv_ai */
12251 1124,
12252 /* PS_vloadrv_nt_ai */
12253 1127,
12254 /* PS_vloadrw_ai */
12255 1130,
12256 /* PS_vloadrw_nt_ai */
12257 1133,
12258 /* PS_vmulw */
12259 1136,
12260 /* PS_vmulw_acc */
12261 1139,
12262 /* PS_vselect */
12263 1143,
12264 /* PS_vsplatib */
12265 1147,
12266 /* PS_vsplatih */
12267 1149,
12268 /* PS_vsplatiw */
12269 1151,
12270 /* PS_vsplatrb */
12271 1153,
12272 /* PS_vsplatrh */
12273 1155,
12274 /* PS_vsplatrw */
12275 1157,
12276 /* PS_vstorerq_ai */
12277 1159,
12278 /* PS_vstorerv_ai */
12279 1162,
12280 /* PS_vstorerv_nt_ai */
12281 1165,
12282 /* PS_vstorerw_ai */
12283 1168,
12284 /* PS_vstorerw_nt_ai */
12285 1171,
12286 /* PS_wselect */
12287 1174,
12288 /* S2_asr_i_p_rnd_goodsyntax */
12289 1178,
12290 /* S2_asr_i_r_rnd_goodsyntax */
12291 1181,
12292 /* S2_pstorerbf_zomap */
12293 1184,
12294 /* S2_pstorerbnewf_zomap */
12295 1187,
12296 /* S2_pstorerbnewt_zomap */
12297 1190,
12298 /* S2_pstorerbt_zomap */
12299 1193,
12300 /* S2_pstorerdf_zomap */
12301 1196,
12302 /* S2_pstorerdt_zomap */
12303 1199,
12304 /* S2_pstorerff_zomap */
12305 1202,
12306 /* S2_pstorerft_zomap */
12307 1205,
12308 /* S2_pstorerhf_zomap */
12309 1208,
12310 /* S2_pstorerhnewf_zomap */
12311 1211,
12312 /* S2_pstorerhnewt_zomap */
12313 1214,
12314 /* S2_pstorerht_zomap */
12315 1217,
12316 /* S2_pstorerif_zomap */
12317 1220,
12318 /* S2_pstorerinewf_zomap */
12319 1223,
12320 /* S2_pstorerinewt_zomap */
12321 1226,
12322 /* S2_pstorerit_zomap */
12323 1229,
12324 /* S2_storerb_zomap */
12325 1232,
12326 /* S2_storerbnew_zomap */
12327 1234,
12328 /* S2_storerd_zomap */
12329 1236,
12330 /* S2_storerf_zomap */
12331 1238,
12332 /* S2_storerh_zomap */
12333 1240,
12334 /* S2_storerhnew_zomap */
12335 1242,
12336 /* S2_storeri_zomap */
12337 1244,
12338 /* S2_storerinew_zomap */
12339 1246,
12340 /* S2_tableidxb_goodsyntax */
12341 1248,
12342 /* S2_tableidxd_goodsyntax */
12343 1253,
12344 /* S2_tableidxh_goodsyntax */
12345 1258,
12346 /* S2_tableidxw_goodsyntax */
12347 1263,
12348 /* S4_pstorerbfnew_zomap */
12349 1268,
12350 /* S4_pstorerbnewfnew_zomap */
12351 1271,
12352 /* S4_pstorerbnewtnew_zomap */
12353 1274,
12354 /* S4_pstorerbtnew_zomap */
12355 1277,
12356 /* S4_pstorerdfnew_zomap */
12357 1280,
12358 /* S4_pstorerdtnew_zomap */
12359 1283,
12360 /* S4_pstorerffnew_zomap */
12361 1286,
12362 /* S4_pstorerftnew_zomap */
12363 1289,
12364 /* S4_pstorerhfnew_zomap */
12365 1292,
12366 /* S4_pstorerhnewfnew_zomap */
12367 1295,
12368 /* S4_pstorerhnewtnew_zomap */
12369 1298,
12370 /* S4_pstorerhtnew_zomap */
12371 1301,
12372 /* S4_pstorerifnew_zomap */
12373 1304,
12374 /* S4_pstorerinewfnew_zomap */
12375 1307,
12376 /* S4_pstorerinewtnew_zomap */
12377 1310,
12378 /* S4_pstoreritnew_zomap */
12379 1313,
12380 /* S4_storeirb_zomap */
12381 1316,
12382 /* S4_storeirbf_zomap */
12383 1318,
12384 /* S4_storeirbfnew_zomap */
12385 1321,
12386 /* S4_storeirbt_zomap */
12387 1324,
12388 /* S4_storeirbtnew_zomap */
12389 1327,
12390 /* S4_storeirh_zomap */
12391 1330,
12392 /* S4_storeirhf_zomap */
12393 1332,
12394 /* S4_storeirhfnew_zomap */
12395 1335,
12396 /* S4_storeirht_zomap */
12397 1338,
12398 /* S4_storeirhtnew_zomap */
12399 1341,
12400 /* S4_storeiri_zomap */
12401 1344,
12402 /* S4_storeirif_zomap */
12403 1346,
12404 /* S4_storeirifnew_zomap */
12405 1349,
12406 /* S4_storeirit_zomap */
12407 1352,
12408 /* S4_storeiritnew_zomap */
12409 1355,
12410 /* S5_asrhub_rnd_sat_goodsyntax */
12411 1358,
12412 /* S5_vasrhrnd_goodsyntax */
12413 1361,
12414 /* S6_allocframe_to_raw */
12415 1364,
12416 /* STriw_ctr */
12417 1365,
12418 /* STriw_pred */
12419 1368,
12420 /* V6_MAP_equb */
12421 1371,
12422 /* V6_MAP_equb_and */
12423 1374,
12424 /* V6_MAP_equb_ior */
12425 1378,
12426 /* V6_MAP_equb_xor */
12427 1382,
12428 /* V6_MAP_equh */
12429 1386,
12430 /* V6_MAP_equh_and */
12431 1389,
12432 /* V6_MAP_equh_ior */
12433 1393,
12434 /* V6_MAP_equh_xor */
12435 1397,
12436 /* V6_MAP_equw */
12437 1401,
12438 /* V6_MAP_equw_and */
12439 1404,
12440 /* V6_MAP_equw_ior */
12441 1408,
12442 /* V6_MAP_equw_xor */
12443 1412,
12444 /* V6_dbl_ld0 */
12445 1416,
12446 /* V6_dbl_st0 */
12447 1418,
12448 /* V6_extractw_alt */
12449 1420,
12450 /* V6_hi */
12451 1423,
12452 /* V6_ld0 */
12453 1425,
12454 /* V6_ldcnp0 */
12455 1427,
12456 /* V6_ldcnpnt0 */
12457 1430,
12458 /* V6_ldcp0 */
12459 1433,
12460 /* V6_ldcpnt0 */
12461 1436,
12462 /* V6_ldnp0 */
12463 1439,
12464 /* V6_ldnpnt0 */
12465 1442,
12466 /* V6_ldnt0 */
12467 1445,
12468 /* V6_ldp0 */
12469 1447,
12470 /* V6_ldpnt0 */
12471 1450,
12472 /* V6_ldtnp0 */
12473 1453,
12474 /* V6_ldtnpnt0 */
12475 1456,
12476 /* V6_ldtp0 */
12477 1459,
12478 /* V6_ldtpnt0 */
12479 1462,
12480 /* V6_ldu0 */
12481 1465,
12482 /* V6_lo */
12483 1467,
12484 /* V6_st0 */
12485 1469,
12486 /* V6_stn0 */
12487 1471,
12488 /* V6_stnnt0 */
12489 1473,
12490 /* V6_stnp0 */
12491 1475,
12492 /* V6_stnpnt0 */
12493 1478,
12494 /* V6_stnq0 */
12495 1481,
12496 /* V6_stnqnt0 */
12497 1484,
12498 /* V6_stnt0 */
12499 1487,
12500 /* V6_stp0 */
12501 1489,
12502 /* V6_stpnt0 */
12503 1492,
12504 /* V6_stq0 */
12505 1495,
12506 /* V6_stqnt0 */
12507 1498,
12508 /* V6_stu0 */
12509 1501,
12510 /* V6_stunp0 */
12511 1503,
12512 /* V6_stup0 */
12513 1506,
12514 /* V6_v10mpyubs10 */
12515 1509,
12516 /* V6_v10mpyubs10_vxx */
12517 1513,
12518 /* V6_v6mpyhubs10_alt */
12519 1518,
12520 /* V6_v6mpyvubs10_alt */
12521 1522,
12522 /* V6_vabsb_alt */
12523 1526,
12524 /* V6_vabsb_sat_alt */
12525 1528,
12526 /* V6_vabsdiffh_alt */
12527 1530,
12528 /* V6_vabsdiffub_alt */
12529 1533,
12530 /* V6_vabsdiffuh_alt */
12531 1536,
12532 /* V6_vabsdiffw_alt */
12533 1539,
12534 /* V6_vabsh_alt */
12535 1542,
12536 /* V6_vabsh_sat_alt */
12537 1544,
12538 /* V6_vabsub_alt */
12539 1546,
12540 /* V6_vabsuh_alt */
12541 1548,
12542 /* V6_vabsuw_alt */
12543 1550,
12544 /* V6_vabsw_alt */
12545 1552,
12546 /* V6_vabsw_sat_alt */
12547 1554,
12548 /* V6_vaddb_alt */
12549 1556,
12550 /* V6_vaddb_dv_alt */
12551 1559,
12552 /* V6_vaddbnq_alt */
12553 1562,
12554 /* V6_vaddbq_alt */
12555 1566,
12556 /* V6_vaddbsat_alt */
12557 1570,
12558 /* V6_vaddbsat_dv_alt */
12559 1573,
12560 /* V6_vaddh_alt */
12561 1576,
12562 /* V6_vaddh_dv_alt */
12563 1579,
12564 /* V6_vaddhnq_alt */
12565 1582,
12566 /* V6_vaddhq_alt */
12567 1586,
12568 /* V6_vaddhsat_alt */
12569 1590,
12570 /* V6_vaddhsat_dv_alt */
12571 1593,
12572 /* V6_vaddhw_acc_alt */
12573 1596,
12574 /* V6_vaddhw_alt */
12575 1600,
12576 /* V6_vaddubh_acc_alt */
12577 1603,
12578 /* V6_vaddubh_alt */
12579 1607,
12580 /* V6_vaddubsat_alt */
12581 1610,
12582 /* V6_vaddubsat_dv_alt */
12583 1613,
12584 /* V6_vadduhsat_alt */
12585 1616,
12586 /* V6_vadduhsat_dv_alt */
12587 1619,
12588 /* V6_vadduhw_acc_alt */
12589 1622,
12590 /* V6_vadduhw_alt */
12591 1626,
12592 /* V6_vadduwsat_alt */
12593 1629,
12594 /* V6_vadduwsat_dv_alt */
12595 1632,
12596 /* V6_vaddw_alt */
12597 1635,
12598 /* V6_vaddw_dv_alt */
12599 1638,
12600 /* V6_vaddwnq_alt */
12601 1641,
12602 /* V6_vaddwq_alt */
12603 1645,
12604 /* V6_vaddwsat_alt */
12605 1649,
12606 /* V6_vaddwsat_dv_alt */
12607 1652,
12608 /* V6_vandnqrt_acc_alt */
12609 1655,
12610 /* V6_vandnqrt_alt */
12611 1659,
12612 /* V6_vandqrt_acc_alt */
12613 1662,
12614 /* V6_vandqrt_alt */
12615 1666,
12616 /* V6_vandvrt_acc_alt */
12617 1669,
12618 /* V6_vandvrt_alt */
12619 1673,
12620 /* V6_vaslh_acc_alt */
12621 1676,
12622 /* V6_vaslh_alt */
12623 1680,
12624 /* V6_vaslhv_alt */
12625 1683,
12626 /* V6_vaslw_acc_alt */
12627 1686,
12628 /* V6_vaslw_alt */
12629 1690,
12630 /* V6_vaslwv_alt */
12631 1693,
12632 /* V6_vasr_into_alt */
12633 1696,
12634 /* V6_vasrh_acc_alt */
12635 1700,
12636 /* V6_vasrh_alt */
12637 1704,
12638 /* V6_vasrhv_alt */
12639 1707,
12640 /* V6_vasrw_acc_alt */
12641 1710,
12642 /* V6_vasrw_alt */
12643 1714,
12644 /* V6_vasrwv_alt */
12645 1717,
12646 /* V6_vassignp */
12647 1720,
12648 /* V6_vavgb_alt */
12649 1722,
12650 /* V6_vavgbrnd_alt */
12651 1725,
12652 /* V6_vavgh_alt */
12653 1728,
12654 /* V6_vavghrnd_alt */
12655 1731,
12656 /* V6_vavgub_alt */
12657 1734,
12658 /* V6_vavgubrnd_alt */
12659 1737,
12660 /* V6_vavguh_alt */
12661 1740,
12662 /* V6_vavguhrnd_alt */
12663 1743,
12664 /* V6_vavguw_alt */
12665 1746,
12666 /* V6_vavguwrnd_alt */
12667 1749,
12668 /* V6_vavgw_alt */
12669 1752,
12670 /* V6_vavgwrnd_alt */
12671 1755,
12672 /* V6_vcl0h_alt */
12673 1758,
12674 /* V6_vcl0w_alt */
12675 1760,
12676 /* V6_vd0 */
12677 1762,
12678 /* V6_vdd0 */
12679 1763,
12680 /* V6_vdealb4w_alt */
12681 1764,
12682 /* V6_vdealb_alt */
12683 1767,
12684 /* V6_vdealh_alt */
12685 1769,
12686 /* V6_vdmpybus_acc_alt */
12687 1771,
12688 /* V6_vdmpybus_alt */
12689 1775,
12690 /* V6_vdmpybus_dv_acc_alt */
12691 1778,
12692 /* V6_vdmpybus_dv_alt */
12693 1782,
12694 /* V6_vdmpyhb_acc_alt */
12695 1785,
12696 /* V6_vdmpyhb_alt */
12697 1789,
12698 /* V6_vdmpyhb_dv_acc_alt */
12699 1792,
12700 /* V6_vdmpyhb_dv_alt */
12701 1796,
12702 /* V6_vdmpyhisat_acc_alt */
12703 1799,
12704 /* V6_vdmpyhisat_alt */
12705 1803,
12706 /* V6_vdmpyhsat_acc_alt */
12707 1806,
12708 /* V6_vdmpyhsat_alt */
12709 1810,
12710 /* V6_vdmpyhsuisat_acc_alt */
12711 1813,
12712 /* V6_vdmpyhsuisat_alt */
12713 1817,
12714 /* V6_vdmpyhsusat_acc_alt */
12715 1820,
12716 /* V6_vdmpyhsusat_alt */
12717 1824,
12718 /* V6_vdmpyhvsat_acc_alt */
12719 1827,
12720 /* V6_vdmpyhvsat_alt */
12721 1831,
12722 /* V6_vdsaduh_acc_alt */
12723 1834,
12724 /* V6_vdsaduh_alt */
12725 1838,
12726 /* V6_vgathermh_pseudo */
12727 1841,
12728 /* V6_vgathermhq_pseudo */
12729 1846,
12730 /* V6_vgathermhw_pseudo */
12731 1852,
12732 /* V6_vgathermhwq_pseudo */
12733 1857,
12734 /* V6_vgathermw_pseudo */
12735 1863,
12736 /* V6_vgathermwq_pseudo */
12737 1868,
12738 /* V6_vlsrh_alt */
12739 1874,
12740 /* V6_vlsrhv_alt */
12741 1877,
12742 /* V6_vlsrw_alt */
12743 1880,
12744 /* V6_vlsrwv_alt */
12745 1883,
12746 /* V6_vmaxb_alt */
12747 1886,
12748 /* V6_vmaxh_alt */
12749 1889,
12750 /* V6_vmaxub_alt */
12751 1892,
12752 /* V6_vmaxuh_alt */
12753 1895,
12754 /* V6_vmaxw_alt */
12755 1898,
12756 /* V6_vminb_alt */
12757 1901,
12758 /* V6_vminh_alt */
12759 1904,
12760 /* V6_vminub_alt */
12761 1907,
12762 /* V6_vminuh_alt */
12763 1910,
12764 /* V6_vminw_alt */
12765 1913,
12766 /* V6_vmpabus_acc_alt */
12767 1916,
12768 /* V6_vmpabus_alt */
12769 1920,
12770 /* V6_vmpabusv_alt */
12771 1923,
12772 /* V6_vmpabuu_acc_alt */
12773 1926,
12774 /* V6_vmpabuu_alt */
12775 1930,
12776 /* V6_vmpabuuv_alt */
12777 1933,
12778 /* V6_vmpahb_acc_alt */
12779 1936,
12780 /* V6_vmpahb_alt */
12781 1940,
12782 /* V6_vmpauhb_acc_alt */
12783 1943,
12784 /* V6_vmpauhb_alt */
12785 1947,
12786 /* V6_vmpybus_acc_alt */
12787 1950,
12788 /* V6_vmpybus_alt */
12789 1954,
12790 /* V6_vmpybusv_acc_alt */
12791 1957,
12792 /* V6_vmpybusv_alt */
12793 1961,
12794 /* V6_vmpybv_acc_alt */
12795 1964,
12796 /* V6_vmpybv_alt */
12797 1968,
12798 /* V6_vmpyewuh_alt */
12799 1971,
12800 /* V6_vmpyh_acc_alt */
12801 1974,
12802 /* V6_vmpyh_alt */
12803 1978,
12804 /* V6_vmpyhsat_acc_alt */
12805 1981,
12806 /* V6_vmpyhsrs_alt */
12807 1985,
12808 /* V6_vmpyhss_alt */
12809 1988,
12810 /* V6_vmpyhus_acc_alt */
12811 1991,
12812 /* V6_vmpyhus_alt */
12813 1995,
12814 /* V6_vmpyhv_acc_alt */
12815 1998,
12816 /* V6_vmpyhv_alt */
12817 2002,
12818 /* V6_vmpyhvsrs_alt */
12819 2005,
12820 /* V6_vmpyiewh_acc_alt */
12821 2008,
12822 /* V6_vmpyiewuh_acc_alt */
12823 2012,
12824 /* V6_vmpyiewuh_alt */
12825 2016,
12826 /* V6_vmpyih_acc_alt */
12827 2019,
12828 /* V6_vmpyih_alt */
12829 2023,
12830 /* V6_vmpyihb_acc_alt */
12831 2026,
12832 /* V6_vmpyihb_alt */
12833 2030,
12834 /* V6_vmpyiowh_alt */
12835 2033,
12836 /* V6_vmpyiwb_acc_alt */
12837 2036,
12838 /* V6_vmpyiwb_alt */
12839 2040,
12840 /* V6_vmpyiwh_acc_alt */
12841 2043,
12842 /* V6_vmpyiwh_alt */
12843 2047,
12844 /* V6_vmpyiwub_acc_alt */
12845 2050,
12846 /* V6_vmpyiwub_alt */
12847 2054,
12848 /* V6_vmpyowh_alt */
12849 2057,
12850 /* V6_vmpyowh_rnd_alt */
12851 2060,
12852 /* V6_vmpyowh_rnd_sacc_alt */
12853 2063,
12854 /* V6_vmpyowh_sacc_alt */
12855 2067,
12856 /* V6_vmpyub_acc_alt */
12857 2071,
12858 /* V6_vmpyub_alt */
12859 2075,
12860 /* V6_vmpyubv_acc_alt */
12861 2078,
12862 /* V6_vmpyubv_alt */
12863 2082,
12864 /* V6_vmpyuh_acc_alt */
12865 2085,
12866 /* V6_vmpyuh_alt */
12867 2089,
12868 /* V6_vmpyuhv_acc_alt */
12869 2092,
12870 /* V6_vmpyuhv_alt */
12871 2096,
12872 /* V6_vnavgb_alt */
12873 2099,
12874 /* V6_vnavgh_alt */
12875 2102,
12876 /* V6_vnavgub_alt */
12877 2105,
12878 /* V6_vnavgw_alt */
12879 2108,
12880 /* V6_vnormamth_alt */
12881 2111,
12882 /* V6_vnormamtw_alt */
12883 2113,
12884 /* V6_vpackeb_alt */
12885 2115,
12886 /* V6_vpackeh_alt */
12887 2118,
12888 /* V6_vpackhb_sat_alt */
12889 2121,
12890 /* V6_vpackhub_sat_alt */
12891 2124,
12892 /* V6_vpackob_alt */
12893 2127,
12894 /* V6_vpackoh_alt */
12895 2130,
12896 /* V6_vpackwh_sat_alt */
12897 2133,
12898 /* V6_vpackwuh_sat_alt */
12899 2136,
12900 /* V6_vpopcounth_alt */
12901 2139,
12902 /* V6_vrmpybub_rtt_acc_alt */
12903 2141,
12904 /* V6_vrmpybub_rtt_alt */
12905 2145,
12906 /* V6_vrmpybus_acc_alt */
12907 2148,
12908 /* V6_vrmpybus_alt */
12909 2152,
12910 /* V6_vrmpybusi_acc_alt */
12911 2155,
12912 /* V6_vrmpybusi_alt */
12913 2160,
12914 /* V6_vrmpybusv_acc_alt */
12915 2164,
12916 /* V6_vrmpybusv_alt */
12917 2168,
12918 /* V6_vrmpybv_acc_alt */
12919 2171,
12920 /* V6_vrmpybv_alt */
12921 2175,
12922 /* V6_vrmpyub_acc_alt */
12923 2178,
12924 /* V6_vrmpyub_alt */
12925 2182,
12926 /* V6_vrmpyub_rtt_acc_alt */
12927 2185,
12928 /* V6_vrmpyub_rtt_alt */
12929 2189,
12930 /* V6_vrmpyubi_acc_alt */
12931 2192,
12932 /* V6_vrmpyubi_alt */
12933 2197,
12934 /* V6_vrmpyubv_acc_alt */
12935 2201,
12936 /* V6_vrmpyubv_alt */
12937 2205,
12938 /* V6_vrotr_alt */
12939 2208,
12940 /* V6_vroundhb_alt */
12941 2211,
12942 /* V6_vroundhub_alt */
12943 2214,
12944 /* V6_vrounduhub_alt */
12945 2217,
12946 /* V6_vrounduwuh_alt */
12947 2220,
12948 /* V6_vroundwh_alt */
12949 2223,
12950 /* V6_vroundwuh_alt */
12951 2226,
12952 /* V6_vrsadubi_acc_alt */
12953 2229,
12954 /* V6_vrsadubi_alt */
12955 2234,
12956 /* V6_vsathub_alt */
12957 2238,
12958 /* V6_vsatuwuh_alt */
12959 2241,
12960 /* V6_vsatwh_alt */
12961 2244,
12962 /* V6_vsb_alt */
12963 2247,
12964 /* V6_vscattermh_add_alt */
12965 2249,
12966 /* V6_vscattermh_alt */
12967 2253,
12968 /* V6_vscattermhq_alt */
12969 2257,
12970 /* V6_vscattermw_add_alt */
12971 2262,
12972 /* V6_vscattermw_alt */
12973 2266,
12974 /* V6_vscattermwh_add_alt */
12975 2270,
12976 /* V6_vscattermwh_alt */
12977 2274,
12978 /* V6_vscattermwhq_alt */
12979 2278,
12980 /* V6_vscattermwq_alt */
12981 2283,
12982 /* V6_vsh_alt */
12983 2288,
12984 /* V6_vshufeh_alt */
12985 2290,
12986 /* V6_vshuffb_alt */
12987 2293,
12988 /* V6_vshuffeb_alt */
12989 2295,
12990 /* V6_vshuffh_alt */
12991 2298,
12992 /* V6_vshuffob_alt */
12993 2300,
12994 /* V6_vshufoeb_alt */
12995 2303,
12996 /* V6_vshufoeh_alt */
12997 2306,
12998 /* V6_vshufoh_alt */
12999 2309,
13000 /* V6_vsubb_alt */
13001 2312,
13002 /* V6_vsubb_dv_alt */
13003 2315,
13004 /* V6_vsubbnq_alt */
13005 2318,
13006 /* V6_vsubbq_alt */
13007 2322,
13008 /* V6_vsubbsat_alt */
13009 2326,
13010 /* V6_vsubbsat_dv_alt */
13011 2329,
13012 /* V6_vsubh_alt */
13013 2332,
13014 /* V6_vsubh_dv_alt */
13015 2335,
13016 /* V6_vsubhnq_alt */
13017 2338,
13018 /* V6_vsubhq_alt */
13019 2342,
13020 /* V6_vsubhsat_alt */
13021 2346,
13022 /* V6_vsubhsat_dv_alt */
13023 2349,
13024 /* V6_vsubhw_alt */
13025 2352,
13026 /* V6_vsububh_alt */
13027 2355,
13028 /* V6_vsububsat_alt */
13029 2358,
13030 /* V6_vsububsat_dv_alt */
13031 2361,
13032 /* V6_vsubuhsat_alt */
13033 2364,
13034 /* V6_vsubuhsat_dv_alt */
13035 2367,
13036 /* V6_vsubuhw_alt */
13037 2370,
13038 /* V6_vsubuwsat_alt */
13039 2373,
13040 /* V6_vsubuwsat_dv_alt */
13041 2376,
13042 /* V6_vsubw_alt */
13043 2379,
13044 /* V6_vsubw_dv_alt */
13045 2382,
13046 /* V6_vsubwnq_alt */
13047 2385,
13048 /* V6_vsubwq_alt */
13049 2389,
13050 /* V6_vsubwsat_alt */
13051 2393,
13052 /* V6_vsubwsat_dv_alt */
13053 2396,
13054 /* V6_vtmpyb_acc_alt */
13055 2399,
13056 /* V6_vtmpyb_alt */
13057 2403,
13058 /* V6_vtmpybus_acc_alt */
13059 2406,
13060 /* V6_vtmpybus_alt */
13061 2410,
13062 /* V6_vtmpyhb_acc_alt */
13063 2413,
13064 /* V6_vtmpyhb_alt */
13065 2417,
13066 /* V6_vtran2x2_map */
13067 2420,
13068 /* V6_vunpackb_alt */
13069 2425,
13070 /* V6_vunpackh_alt */
13071 2427,
13072 /* V6_vunpackob_alt */
13073 2429,
13074 /* V6_vunpackoh_alt */
13075 2432,
13076 /* V6_vunpackub_alt */
13077 2435,
13078 /* V6_vunpackuh_alt */
13079 2437,
13080 /* V6_vzb_alt */
13081 2439,
13082 /* V6_vzh_alt */
13083 2441,
13084 /* V6_zld0 */
13085 2443,
13086 /* V6_zldp0 */
13087 2444,
13088 /* Y2_crswap_old */
13089 2446,
13090 /* Y2_dcfetch */
13091 2448,
13092 /* Y2_k1lock_map */
13093 2449,
13094 /* Y2_k1unlock_map */
13095 2449,
13096 /* dup_A2_add */
13097 2449,
13098 /* dup_A2_addi */
13099 2452,
13100 /* dup_A2_andir */
13101 2455,
13102 /* dup_A2_combineii */
13103 2458,
13104 /* dup_A2_sxtb */
13105 2461,
13106 /* dup_A2_sxth */
13107 2463,
13108 /* dup_A2_tfr */
13109 2465,
13110 /* dup_A2_tfrsi */
13111 2467,
13112 /* dup_A2_zxtb */
13113 2469,
13114 /* dup_A2_zxth */
13115 2471,
13116 /* dup_A4_combineii */
13117 2473,
13118 /* dup_A4_combineir */
13119 2476,
13120 /* dup_A4_combineri */
13121 2479,
13122 /* dup_C2_cmoveif */
13123 2482,
13124 /* dup_C2_cmoveit */
13125 2485,
13126 /* dup_C2_cmovenewif */
13127 2488,
13128 /* dup_C2_cmovenewit */
13129 2491,
13130 /* dup_C2_cmpeqi */
13131 2494,
13132 /* dup_L2_deallocframe */
13133 2497,
13134 /* dup_L2_loadrb_io */
13135 2499,
13136 /* dup_L2_loadrd_io */
13137 2502,
13138 /* dup_L2_loadrh_io */
13139 2505,
13140 /* dup_L2_loadri_io */
13141 2508,
13142 /* dup_L2_loadrub_io */
13143 2511,
13144 /* dup_L2_loadruh_io */
13145 2514,
13146 /* dup_S2_allocframe */
13147 2517,
13148 /* dup_S2_storerb_io */
13149 2520,
13150 /* dup_S2_storerd_io */
13151 2523,
13152 /* dup_S2_storerh_io */
13153 2526,
13154 /* dup_S2_storeri_io */
13155 2529,
13156 /* dup_S4_storeirb_io */
13157 2532,
13158 /* dup_S4_storeiri_io */
13159 2535,
13160 /* A2_abs */
13161 2538,
13162 /* A2_absp */
13163 2540,
13164 /* A2_abssat */
13165 2542,
13166 /* A2_add */
13167 2544,
13168 /* A2_addh_h16_hh */
13169 2547,
13170 /* A2_addh_h16_hl */
13171 2550,
13172 /* A2_addh_h16_lh */
13173 2553,
13174 /* A2_addh_h16_ll */
13175 2556,
13176 /* A2_addh_h16_sat_hh */
13177 2559,
13178 /* A2_addh_h16_sat_hl */
13179 2562,
13180 /* A2_addh_h16_sat_lh */
13181 2565,
13182 /* A2_addh_h16_sat_ll */
13183 2568,
13184 /* A2_addh_l16_hl */
13185 2571,
13186 /* A2_addh_l16_ll */
13187 2574,
13188 /* A2_addh_l16_sat_hl */
13189 2577,
13190 /* A2_addh_l16_sat_ll */
13191 2580,
13192 /* A2_addi */
13193 2583,
13194 /* A2_addp */
13195 2586,
13196 /* A2_addpsat */
13197 2589,
13198 /* A2_addsat */
13199 2592,
13200 /* A2_addsph */
13201 2595,
13202 /* A2_addspl */
13203 2598,
13204 /* A2_and */
13205 2601,
13206 /* A2_andir */
13207 2604,
13208 /* A2_andp */
13209 2607,
13210 /* A2_aslh */
13211 2610,
13212 /* A2_asrh */
13213 2612,
13214 /* A2_combine_hh */
13215 2614,
13216 /* A2_combine_hl */
13217 2617,
13218 /* A2_combine_lh */
13219 2620,
13220 /* A2_combine_ll */
13221 2623,
13222 /* A2_combineii */
13223 2626,
13224 /* A2_combinew */
13225 2629,
13226 /* A2_max */
13227 2632,
13228 /* A2_maxp */
13229 2635,
13230 /* A2_maxu */
13231 2638,
13232 /* A2_maxup */
13233 2641,
13234 /* A2_min */
13235 2644,
13236 /* A2_minp */
13237 2647,
13238 /* A2_minu */
13239 2650,
13240 /* A2_minup */
13241 2653,
13242 /* A2_negp */
13243 2656,
13244 /* A2_negsat */
13245 2658,
13246 /* A2_nop */
13247 2660,
13248 /* A2_notp */
13249 2660,
13250 /* A2_or */
13251 2662,
13252 /* A2_orir */
13253 2665,
13254 /* A2_orp */
13255 2668,
13256 /* A2_paddf */
13257 2671,
13258 /* A2_paddfnew */
13259 2675,
13260 /* A2_paddif */
13261 2679,
13262 /* A2_paddifnew */
13263 2683,
13264 /* A2_paddit */
13265 2687,
13266 /* A2_padditnew */
13267 2691,
13268 /* A2_paddt */
13269 2695,
13270 /* A2_paddtnew */
13271 2699,
13272 /* A2_pandf */
13273 2703,
13274 /* A2_pandfnew */
13275 2707,
13276 /* A2_pandt */
13277 2711,
13278 /* A2_pandtnew */
13279 2715,
13280 /* A2_porf */
13281 2719,
13282 /* A2_porfnew */
13283 2723,
13284 /* A2_port */
13285 2727,
13286 /* A2_portnew */
13287 2731,
13288 /* A2_psubf */
13289 2735,
13290 /* A2_psubfnew */
13291 2739,
13292 /* A2_psubt */
13293 2743,
13294 /* A2_psubtnew */
13295 2747,
13296 /* A2_pxorf */
13297 2751,
13298 /* A2_pxorfnew */
13299 2755,
13300 /* A2_pxort */
13301 2759,
13302 /* A2_pxortnew */
13303 2763,
13304 /* A2_roundsat */
13305 2767,
13306 /* A2_sat */
13307 2769,
13308 /* A2_satb */
13309 2771,
13310 /* A2_sath */
13311 2773,
13312 /* A2_satub */
13313 2775,
13314 /* A2_satuh */
13315 2777,
13316 /* A2_sub */
13317 2779,
13318 /* A2_subh_h16_hh */
13319 2782,
13320 /* A2_subh_h16_hl */
13321 2785,
13322 /* A2_subh_h16_lh */
13323 2788,
13324 /* A2_subh_h16_ll */
13325 2791,
13326 /* A2_subh_h16_sat_hh */
13327 2794,
13328 /* A2_subh_h16_sat_hl */
13329 2797,
13330 /* A2_subh_h16_sat_lh */
13331 2800,
13332 /* A2_subh_h16_sat_ll */
13333 2803,
13334 /* A2_subh_l16_hl */
13335 2806,
13336 /* A2_subh_l16_ll */
13337 2809,
13338 /* A2_subh_l16_sat_hl */
13339 2812,
13340 /* A2_subh_l16_sat_ll */
13341 2815,
13342 /* A2_subp */
13343 2818,
13344 /* A2_subri */
13345 2821,
13346 /* A2_subsat */
13347 2824,
13348 /* A2_svaddh */
13349 2827,
13350 /* A2_svaddhs */
13351 2830,
13352 /* A2_svadduhs */
13353 2833,
13354 /* A2_svavgh */
13355 2836,
13356 /* A2_svavghs */
13357 2839,
13358 /* A2_svnavgh */
13359 2842,
13360 /* A2_svsubh */
13361 2845,
13362 /* A2_svsubhs */
13363 2848,
13364 /* A2_svsubuhs */
13365 2851,
13366 /* A2_swiz */
13367 2854,
13368 /* A2_sxtb */
13369 2856,
13370 /* A2_sxth */
13371 2858,
13372 /* A2_sxtw */
13373 2860,
13374 /* A2_tfr */
13375 2862,
13376 /* A2_tfrcrr */
13377 2864,
13378 /* A2_tfrih */
13379 2866,
13380 /* A2_tfril */
13381 2869,
13382 /* A2_tfrrcr */
13383 2872,
13384 /* A2_tfrsi */
13385 2874,
13386 /* A2_vabsh */
13387 2876,
13388 /* A2_vabshsat */
13389 2878,
13390 /* A2_vabsw */
13391 2880,
13392 /* A2_vabswsat */
13393 2882,
13394 /* A2_vaddh */
13395 2884,
13396 /* A2_vaddhs */
13397 2887,
13398 /* A2_vaddub */
13399 2890,
13400 /* A2_vaddubs */
13401 2893,
13402 /* A2_vadduhs */
13403 2896,
13404 /* A2_vaddw */
13405 2899,
13406 /* A2_vaddws */
13407 2902,
13408 /* A2_vavgh */
13409 2905,
13410 /* A2_vavghcr */
13411 2908,
13412 /* A2_vavghr */
13413 2911,
13414 /* A2_vavgub */
13415 2914,
13416 /* A2_vavgubr */
13417 2917,
13418 /* A2_vavguh */
13419 2920,
13420 /* A2_vavguhr */
13421 2923,
13422 /* A2_vavguw */
13423 2926,
13424 /* A2_vavguwr */
13425 2929,
13426 /* A2_vavgw */
13427 2932,
13428 /* A2_vavgwcr */
13429 2935,
13430 /* A2_vavgwr */
13431 2938,
13432 /* A2_vcmpbeq */
13433 2941,
13434 /* A2_vcmpbgtu */
13435 2944,
13436 /* A2_vcmpheq */
13437 2947,
13438 /* A2_vcmphgt */
13439 2950,
13440 /* A2_vcmphgtu */
13441 2953,
13442 /* A2_vcmpweq */
13443 2956,
13444 /* A2_vcmpwgt */
13445 2959,
13446 /* A2_vcmpwgtu */
13447 2962,
13448 /* A2_vconj */
13449 2965,
13450 /* A2_vmaxb */
13451 2967,
13452 /* A2_vmaxh */
13453 2970,
13454 /* A2_vmaxub */
13455 2973,
13456 /* A2_vmaxuh */
13457 2976,
13458 /* A2_vmaxuw */
13459 2979,
13460 /* A2_vmaxw */
13461 2982,
13462 /* A2_vminb */
13463 2985,
13464 /* A2_vminh */
13465 2988,
13466 /* A2_vminub */
13467 2991,
13468 /* A2_vminuh */
13469 2994,
13470 /* A2_vminuw */
13471 2997,
13472 /* A2_vminw */
13473 3000,
13474 /* A2_vnavgh */
13475 3003,
13476 /* A2_vnavghcr */
13477 3006,
13478 /* A2_vnavghr */
13479 3009,
13480 /* A2_vnavgw */
13481 3012,
13482 /* A2_vnavgwcr */
13483 3015,
13484 /* A2_vnavgwr */
13485 3018,
13486 /* A2_vraddub */
13487 3021,
13488 /* A2_vraddub_acc */
13489 3024,
13490 /* A2_vrsadub */
13491 3028,
13492 /* A2_vrsadub_acc */
13493 3031,
13494 /* A2_vsubh */
13495 3035,
13496 /* A2_vsubhs */
13497 3038,
13498 /* A2_vsubub */
13499 3041,
13500 /* A2_vsububs */
13501 3044,
13502 /* A2_vsubuhs */
13503 3047,
13504 /* A2_vsubw */
13505 3050,
13506 /* A2_vsubws */
13507 3053,
13508 /* A2_xor */
13509 3056,
13510 /* A2_xorp */
13511 3059,
13512 /* A2_zxth */
13513 3062,
13514 /* A4_addp_c */
13515 3064,
13516 /* A4_andn */
13517 3069,
13518 /* A4_andnp */
13519 3072,
13520 /* A4_bitsplit */
13521 3075,
13522 /* A4_bitspliti */
13523 3078,
13524 /* A4_boundscheck_hi */
13525 3081,
13526 /* A4_boundscheck_lo */
13527 3084,
13528 /* A4_cmpbeq */
13529 3087,
13530 /* A4_cmpbeqi */
13531 3090,
13532 /* A4_cmpbgt */
13533 3093,
13534 /* A4_cmpbgti */
13535 3096,
13536 /* A4_cmpbgtu */
13537 3099,
13538 /* A4_cmpbgtui */
13539 3102,
13540 /* A4_cmpheq */
13541 3105,
13542 /* A4_cmpheqi */
13543 3108,
13544 /* A4_cmphgt */
13545 3111,
13546 /* A4_cmphgti */
13547 3114,
13548 /* A4_cmphgtu */
13549 3117,
13550 /* A4_cmphgtui */
13551 3120,
13552 /* A4_combineii */
13553 3123,
13554 /* A4_combineir */
13555 3126,
13556 /* A4_combineri */
13557 3129,
13558 /* A4_cround_ri */
13559 3132,
13560 /* A4_cround_rr */
13561 3135,
13562 /* A4_ext */
13563 3138,
13564 /* A4_modwrapu */
13565 3139,
13566 /* A4_orn */
13567 3142,
13568 /* A4_ornp */
13569 3145,
13570 /* A4_paslhf */
13571 3148,
13572 /* A4_paslhfnew */
13573 3151,
13574 /* A4_paslht */
13575 3154,
13576 /* A4_paslhtnew */
13577 3157,
13578 /* A4_pasrhf */
13579 3160,
13580 /* A4_pasrhfnew */
13581 3163,
13582 /* A4_pasrht */
13583 3166,
13584 /* A4_pasrhtnew */
13585 3169,
13586 /* A4_psxtbf */
13587 3172,
13588 /* A4_psxtbfnew */
13589 3175,
13590 /* A4_psxtbt */
13591 3178,
13592 /* A4_psxtbtnew */
13593 3181,
13594 /* A4_psxthf */
13595 3184,
13596 /* A4_psxthfnew */
13597 3187,
13598 /* A4_psxtht */
13599 3190,
13600 /* A4_psxthtnew */
13601 3193,
13602 /* A4_pzxtbf */
13603 3196,
13604 /* A4_pzxtbfnew */
13605 3199,
13606 /* A4_pzxtbt */
13607 3202,
13608 /* A4_pzxtbtnew */
13609 3205,
13610 /* A4_pzxthf */
13611 3208,
13612 /* A4_pzxthfnew */
13613 3211,
13614 /* A4_pzxtht */
13615 3214,
13616 /* A4_pzxthtnew */
13617 3217,
13618 /* A4_rcmpeq */
13619 3220,
13620 /* A4_rcmpeqi */
13621 3223,
13622 /* A4_rcmpneq */
13623 3226,
13624 /* A4_rcmpneqi */
13625 3229,
13626 /* A4_round_ri */
13627 3232,
13628 /* A4_round_ri_sat */
13629 3235,
13630 /* A4_round_rr */
13631 3238,
13632 /* A4_round_rr_sat */
13633 3241,
13634 /* A4_subp_c */
13635 3244,
13636 /* A4_tfrcpp */
13637 3249,
13638 /* A4_tfrpcp */
13639 3251,
13640 /* A4_tlbmatch */
13641 3253,
13642 /* A4_vcmpbeq_any */
13643 3256,
13644 /* A4_vcmpbeqi */
13645 3259,
13646 /* A4_vcmpbgt */
13647 3262,
13648 /* A4_vcmpbgti */
13649 3265,
13650 /* A4_vcmpbgtui */
13651 3268,
13652 /* A4_vcmpheqi */
13653 3271,
13654 /* A4_vcmphgti */
13655 3274,
13656 /* A4_vcmphgtui */
13657 3277,
13658 /* A4_vcmpweqi */
13659 3280,
13660 /* A4_vcmpwgti */
13661 3283,
13662 /* A4_vcmpwgtui */
13663 3286,
13664 /* A4_vrmaxh */
13665 3289,
13666 /* A4_vrmaxuh */
13667 3293,
13668 /* A4_vrmaxuw */
13669 3297,
13670 /* A4_vrmaxw */
13671 3301,
13672 /* A4_vrminh */
13673 3305,
13674 /* A4_vrminuh */
13675 3309,
13676 /* A4_vrminuw */
13677 3313,
13678 /* A4_vrminw */
13679 3317,
13680 /* A5_ACS */
13681 3321,
13682 /* A5_vaddhubs */
13683 3326,
13684 /* A6_vcmpbeq_notany */
13685 3329,
13686 /* A6_vminub_RdP */
13687 3332,
13688 /* A7_clip */
13689 3336,
13690 /* A7_croundd_ri */
13691 3339,
13692 /* A7_croundd_rr */
13693 3342,
13694 /* A7_vclip */
13695 3345,
13696 /* C2_all8 */
13697 3348,
13698 /* C2_and */
13699 3350,
13700 /* C2_andn */
13701 3353,
13702 /* C2_any8 */
13703 3356,
13704 /* C2_bitsclr */
13705 3358,
13706 /* C2_bitsclri */
13707 3361,
13708 /* C2_bitsset */
13709 3364,
13710 /* C2_ccombinewf */
13711 3367,
13712 /* C2_ccombinewnewf */
13713 3371,
13714 /* C2_ccombinewnewt */
13715 3375,
13716 /* C2_ccombinewt */
13717 3379,
13718 /* C2_cmoveif */
13719 3383,
13720 /* C2_cmoveit */
13721 3386,
13722 /* C2_cmovenewif */
13723 3389,
13724 /* C2_cmovenewit */
13725 3392,
13726 /* C2_cmpeq */
13727 3395,
13728 /* C2_cmpeqi */
13729 3398,
13730 /* C2_cmpeqp */
13731 3401,
13732 /* C2_cmpgt */
13733 3404,
13734 /* C2_cmpgti */
13735 3407,
13736 /* C2_cmpgtp */
13737 3410,
13738 /* C2_cmpgtu */
13739 3413,
13740 /* C2_cmpgtui */
13741 3416,
13742 /* C2_cmpgtup */
13743 3419,
13744 /* C2_mask */
13745 3422,
13746 /* C2_mux */
13747 3424,
13748 /* C2_muxii */
13749 3428,
13750 /* C2_muxir */
13751 3432,
13752 /* C2_muxri */
13753 3436,
13754 /* C2_not */
13755 3440,
13756 /* C2_or */
13757 3442,
13758 /* C2_orn */
13759 3445,
13760 /* C2_tfrpr */
13761 3448,
13762 /* C2_tfrrp */
13763 3450,
13764 /* C2_vitpack */
13765 3452,
13766 /* C2_vmux */
13767 3455,
13768 /* C2_xor */
13769 3459,
13770 /* C4_addipc */
13771 3462,
13772 /* C4_and_and */
13773 3464,
13774 /* C4_and_andn */
13775 3468,
13776 /* C4_and_or */
13777 3472,
13778 /* C4_and_orn */
13779 3476,
13780 /* C4_cmplte */
13781 3480,
13782 /* C4_cmpltei */
13783 3483,
13784 /* C4_cmplteu */
13785 3486,
13786 /* C4_cmplteui */
13787 3489,
13788 /* C4_cmpneq */
13789 3492,
13790 /* C4_cmpneqi */
13791 3495,
13792 /* C4_fastcorner9 */
13793 3498,
13794 /* C4_fastcorner9_not */
13795 3501,
13796 /* C4_nbitsclr */
13797 3504,
13798 /* C4_nbitsclri */
13799 3507,
13800 /* C4_nbitsset */
13801 3510,
13802 /* C4_or_and */
13803 3513,
13804 /* C4_or_andn */
13805 3517,
13806 /* C4_or_or */
13807 3521,
13808 /* C4_or_orn */
13809 3525,
13810 /* CALLProfile */
13811 3529,
13812 /* CONST32 */
13813 3530,
13814 /* CONST64 */
13815 3532,
13816 /* DuplexIClass0 */
13817 3534,
13818 /* DuplexIClass1 */
13819 3534,
13820 /* DuplexIClass2 */
13821 3534,
13822 /* DuplexIClass3 */
13823 3534,
13824 /* DuplexIClass4 */
13825 3534,
13826 /* DuplexIClass5 */
13827 3534,
13828 /* DuplexIClass6 */
13829 3534,
13830 /* DuplexIClass7 */
13831 3534,
13832 /* DuplexIClass8 */
13833 3534,
13834 /* DuplexIClass9 */
13835 3534,
13836 /* DuplexIClassA */
13837 3534,
13838 /* DuplexIClassB */
13839 3534,
13840 /* DuplexIClassC */
13841 3534,
13842 /* DuplexIClassD */
13843 3534,
13844 /* DuplexIClassE */
13845 3534,
13846 /* DuplexIClassF */
13847 3534,
13848 /* EH_RETURN_JMPR */
13849 3534,
13850 /* F2_conv_d2df */
13851 3535,
13852 /* F2_conv_d2sf */
13853 3537,
13854 /* F2_conv_df2d */
13855 3539,
13856 /* F2_conv_df2d_chop */
13857 3541,
13858 /* F2_conv_df2sf */
13859 3543,
13860 /* F2_conv_df2ud */
13861 3545,
13862 /* F2_conv_df2ud_chop */
13863 3547,
13864 /* F2_conv_df2uw */
13865 3549,
13866 /* F2_conv_df2uw_chop */
13867 3551,
13868 /* F2_conv_df2w */
13869 3553,
13870 /* F2_conv_df2w_chop */
13871 3555,
13872 /* F2_conv_sf2d */
13873 3557,
13874 /* F2_conv_sf2d_chop */
13875 3559,
13876 /* F2_conv_sf2df */
13877 3561,
13878 /* F2_conv_sf2ud */
13879 3563,
13880 /* F2_conv_sf2ud_chop */
13881 3565,
13882 /* F2_conv_sf2uw */
13883 3567,
13884 /* F2_conv_sf2uw_chop */
13885 3569,
13886 /* F2_conv_sf2w */
13887 3571,
13888 /* F2_conv_sf2w_chop */
13889 3573,
13890 /* F2_conv_ud2df */
13891 3575,
13892 /* F2_conv_ud2sf */
13893 3577,
13894 /* F2_conv_uw2df */
13895 3579,
13896 /* F2_conv_uw2sf */
13897 3581,
13898 /* F2_conv_w2df */
13899 3583,
13900 /* F2_conv_w2sf */
13901 3585,
13902 /* F2_dfadd */
13903 3587,
13904 /* F2_dfclass */
13905 3590,
13906 /* F2_dfcmpeq */
13907 3593,
13908 /* F2_dfcmpge */
13909 3596,
13910 /* F2_dfcmpgt */
13911 3599,
13912 /* F2_dfcmpuo */
13913 3602,
13914 /* F2_dfimm_n */
13915 3605,
13916 /* F2_dfimm_p */
13917 3607,
13918 /* F2_dfmax */
13919 3609,
13920 /* F2_dfmin */
13921 3612,
13922 /* F2_dfmpyfix */
13923 3615,
13924 /* F2_dfmpyhh */
13925 3618,
13926 /* F2_dfmpylh */
13927 3622,
13928 /* F2_dfmpyll */
13929 3626,
13930 /* F2_dfsub */
13931 3629,
13932 /* F2_sfadd */
13933 3632,
13934 /* F2_sfclass */
13935 3635,
13936 /* F2_sfcmpeq */
13937 3638,
13938 /* F2_sfcmpge */
13939 3641,
13940 /* F2_sfcmpgt */
13941 3644,
13942 /* F2_sfcmpuo */
13943 3647,
13944 /* F2_sffixupd */
13945 3650,
13946 /* F2_sffixupn */
13947 3653,
13948 /* F2_sffixupr */
13949 3656,
13950 /* F2_sffma */
13951 3658,
13952 /* F2_sffma_lib */
13953 3662,
13954 /* F2_sffma_sc */
13955 3666,
13956 /* F2_sffms */
13957 3671,
13958 /* F2_sffms_lib */
13959 3675,
13960 /* F2_sfimm_n */
13961 3679,
13962 /* F2_sfimm_p */
13963 3681,
13964 /* F2_sfinvsqrta */
13965 3683,
13966 /* F2_sfmax */
13967 3686,
13968 /* F2_sfmin */
13969 3689,
13970 /* F2_sfmpy */
13971 3692,
13972 /* F2_sfrecipa */
13973 3695,
13974 /* F2_sfsub */
13975 3699,
13976 /* G4_tfrgcpp */
13977 3702,
13978 /* G4_tfrgcrr */
13979 3704,
13980 /* G4_tfrgpcp */
13981 3706,
13982 /* G4_tfrgrcr */
13983 3708,
13984 /* HI */
13985 3710,
13986 /* J2_call */
13987 3712,
13988 /* J2_callf */
13989 3713,
13990 /* J2_callr */
13991 3715,
13992 /* J2_callrf */
13993 3716,
13994 /* J2_callrh */
13995 3718,
13996 /* J2_callrt */
13997 3719,
13998 /* J2_callt */
13999 3721,
14000 /* J2_jump */
14001 3723,
14002 /* J2_jumpf */
14003 3724,
14004 /* J2_jumpfnew */
14005 3726,
14006 /* J2_jumpfnewpt */
14007 3728,
14008 /* J2_jumpfpt */
14009 3730,
14010 /* J2_jumpr */
14011 3732,
14012 /* J2_jumprf */
14013 3733,
14014 /* J2_jumprfnew */
14015 3735,
14016 /* J2_jumprfnewpt */
14017 3737,
14018 /* J2_jumprfpt */
14019 3739,
14020 /* J2_jumprgtez */
14021 3741,
14022 /* J2_jumprgtezpt */
14023 3743,
14024 /* J2_jumprh */
14025 3745,
14026 /* J2_jumprltez */
14027 3746,
14028 /* J2_jumprltezpt */
14029 3748,
14030 /* J2_jumprnz */
14031 3750,
14032 /* J2_jumprnzpt */
14033 3752,
14034 /* J2_jumprt */
14035 3754,
14036 /* J2_jumprtnew */
14037 3756,
14038 /* J2_jumprtnewpt */
14039 3758,
14040 /* J2_jumprtpt */
14041 3760,
14042 /* J2_jumprz */
14043 3762,
14044 /* J2_jumprzpt */
14045 3764,
14046 /* J2_jumpt */
14047 3766,
14048 /* J2_jumptnew */
14049 3768,
14050 /* J2_jumptnewpt */
14051 3770,
14052 /* J2_jumptpt */
14053 3772,
14054 /* J2_loop0i */
14055 3774,
14056 /* J2_loop0iext */
14057 3776,
14058 /* J2_loop0r */
14059 3778,
14060 /* J2_loop0rext */
14061 3780,
14062 /* J2_loop1i */
14063 3782,
14064 /* J2_loop1iext */
14065 3784,
14066 /* J2_loop1r */
14067 3786,
14068 /* J2_loop1rext */
14069 3788,
14070 /* J2_pause */
14071 3790,
14072 /* J2_ploop1si */
14073 3791,
14074 /* J2_ploop1sr */
14075 3793,
14076 /* J2_ploop2si */
14077 3795,
14078 /* J2_ploop2sr */
14079 3797,
14080 /* J2_ploop3si */
14081 3799,
14082 /* J2_ploop3sr */
14083 3801,
14084 /* J2_rte */
14085 3803,
14086 /* J2_trap0 */
14087 3803,
14088 /* J2_trap1 */
14089 3804,
14090 /* J2_unpause */
14091 3807,
14092 /* J4_cmpeq_f_jumpnv_nt */
14093 3807,
14094 /* J4_cmpeq_f_jumpnv_t */
14095 3810,
14096 /* J4_cmpeq_fp0_jump_nt */
14097 3813,
14098 /* J4_cmpeq_fp0_jump_t */
14099 3816,
14100 /* J4_cmpeq_fp1_jump_nt */
14101 3819,
14102 /* J4_cmpeq_fp1_jump_t */
14103 3822,
14104 /* J4_cmpeq_t_jumpnv_nt */
14105 3825,
14106 /* J4_cmpeq_t_jumpnv_t */
14107 3828,
14108 /* J4_cmpeq_tp0_jump_nt */
14109 3831,
14110 /* J4_cmpeq_tp0_jump_t */
14111 3834,
14112 /* J4_cmpeq_tp1_jump_nt */
14113 3837,
14114 /* J4_cmpeq_tp1_jump_t */
14115 3840,
14116 /* J4_cmpeqi_f_jumpnv_nt */
14117 3843,
14118 /* J4_cmpeqi_f_jumpnv_t */
14119 3846,
14120 /* J4_cmpeqi_fp0_jump_nt */
14121 3849,
14122 /* J4_cmpeqi_fp0_jump_t */
14123 3852,
14124 /* J4_cmpeqi_fp1_jump_nt */
14125 3855,
14126 /* J4_cmpeqi_fp1_jump_t */
14127 3858,
14128 /* J4_cmpeqi_t_jumpnv_nt */
14129 3861,
14130 /* J4_cmpeqi_t_jumpnv_t */
14131 3864,
14132 /* J4_cmpeqi_tp0_jump_nt */
14133 3867,
14134 /* J4_cmpeqi_tp0_jump_t */
14135 3870,
14136 /* J4_cmpeqi_tp1_jump_nt */
14137 3873,
14138 /* J4_cmpeqi_tp1_jump_t */
14139 3876,
14140 /* J4_cmpeqn1_f_jumpnv_nt */
14141 3879,
14142 /* J4_cmpeqn1_f_jumpnv_t */
14143 3882,
14144 /* J4_cmpeqn1_fp0_jump_nt */
14145 3885,
14146 /* J4_cmpeqn1_fp0_jump_t */
14147 3888,
14148 /* J4_cmpeqn1_fp1_jump_nt */
14149 3891,
14150 /* J4_cmpeqn1_fp1_jump_t */
14151 3894,
14152 /* J4_cmpeqn1_t_jumpnv_nt */
14153 3897,
14154 /* J4_cmpeqn1_t_jumpnv_t */
14155 3900,
14156 /* J4_cmpeqn1_tp0_jump_nt */
14157 3903,
14158 /* J4_cmpeqn1_tp0_jump_t */
14159 3906,
14160 /* J4_cmpeqn1_tp1_jump_nt */
14161 3909,
14162 /* J4_cmpeqn1_tp1_jump_t */
14163 3912,
14164 /* J4_cmpgt_f_jumpnv_nt */
14165 3915,
14166 /* J4_cmpgt_f_jumpnv_t */
14167 3918,
14168 /* J4_cmpgt_fp0_jump_nt */
14169 3921,
14170 /* J4_cmpgt_fp0_jump_t */
14171 3924,
14172 /* J4_cmpgt_fp1_jump_nt */
14173 3927,
14174 /* J4_cmpgt_fp1_jump_t */
14175 3930,
14176 /* J4_cmpgt_t_jumpnv_nt */
14177 3933,
14178 /* J4_cmpgt_t_jumpnv_t */
14179 3936,
14180 /* J4_cmpgt_tp0_jump_nt */
14181 3939,
14182 /* J4_cmpgt_tp0_jump_t */
14183 3942,
14184 /* J4_cmpgt_tp1_jump_nt */
14185 3945,
14186 /* J4_cmpgt_tp1_jump_t */
14187 3948,
14188 /* J4_cmpgti_f_jumpnv_nt */
14189 3951,
14190 /* J4_cmpgti_f_jumpnv_t */
14191 3954,
14192 /* J4_cmpgti_fp0_jump_nt */
14193 3957,
14194 /* J4_cmpgti_fp0_jump_t */
14195 3960,
14196 /* J4_cmpgti_fp1_jump_nt */
14197 3963,
14198 /* J4_cmpgti_fp1_jump_t */
14199 3966,
14200 /* J4_cmpgti_t_jumpnv_nt */
14201 3969,
14202 /* J4_cmpgti_t_jumpnv_t */
14203 3972,
14204 /* J4_cmpgti_tp0_jump_nt */
14205 3975,
14206 /* J4_cmpgti_tp0_jump_t */
14207 3978,
14208 /* J4_cmpgti_tp1_jump_nt */
14209 3981,
14210 /* J4_cmpgti_tp1_jump_t */
14211 3984,
14212 /* J4_cmpgtn1_f_jumpnv_nt */
14213 3987,
14214 /* J4_cmpgtn1_f_jumpnv_t */
14215 3990,
14216 /* J4_cmpgtn1_fp0_jump_nt */
14217 3993,
14218 /* J4_cmpgtn1_fp0_jump_t */
14219 3996,
14220 /* J4_cmpgtn1_fp1_jump_nt */
14221 3999,
14222 /* J4_cmpgtn1_fp1_jump_t */
14223 4002,
14224 /* J4_cmpgtn1_t_jumpnv_nt */
14225 4005,
14226 /* J4_cmpgtn1_t_jumpnv_t */
14227 4008,
14228 /* J4_cmpgtn1_tp0_jump_nt */
14229 4011,
14230 /* J4_cmpgtn1_tp0_jump_t */
14231 4014,
14232 /* J4_cmpgtn1_tp1_jump_nt */
14233 4017,
14234 /* J4_cmpgtn1_tp1_jump_t */
14235 4020,
14236 /* J4_cmpgtu_f_jumpnv_nt */
14237 4023,
14238 /* J4_cmpgtu_f_jumpnv_t */
14239 4026,
14240 /* J4_cmpgtu_fp0_jump_nt */
14241 4029,
14242 /* J4_cmpgtu_fp0_jump_t */
14243 4032,
14244 /* J4_cmpgtu_fp1_jump_nt */
14245 4035,
14246 /* J4_cmpgtu_fp1_jump_t */
14247 4038,
14248 /* J4_cmpgtu_t_jumpnv_nt */
14249 4041,
14250 /* J4_cmpgtu_t_jumpnv_t */
14251 4044,
14252 /* J4_cmpgtu_tp0_jump_nt */
14253 4047,
14254 /* J4_cmpgtu_tp0_jump_t */
14255 4050,
14256 /* J4_cmpgtu_tp1_jump_nt */
14257 4053,
14258 /* J4_cmpgtu_tp1_jump_t */
14259 4056,
14260 /* J4_cmpgtui_f_jumpnv_nt */
14261 4059,
14262 /* J4_cmpgtui_f_jumpnv_t */
14263 4062,
14264 /* J4_cmpgtui_fp0_jump_nt */
14265 4065,
14266 /* J4_cmpgtui_fp0_jump_t */
14267 4068,
14268 /* J4_cmpgtui_fp1_jump_nt */
14269 4071,
14270 /* J4_cmpgtui_fp1_jump_t */
14271 4074,
14272 /* J4_cmpgtui_t_jumpnv_nt */
14273 4077,
14274 /* J4_cmpgtui_t_jumpnv_t */
14275 4080,
14276 /* J4_cmpgtui_tp0_jump_nt */
14277 4083,
14278 /* J4_cmpgtui_tp0_jump_t */
14279 4086,
14280 /* J4_cmpgtui_tp1_jump_nt */
14281 4089,
14282 /* J4_cmpgtui_tp1_jump_t */
14283 4092,
14284 /* J4_cmplt_f_jumpnv_nt */
14285 4095,
14286 /* J4_cmplt_f_jumpnv_t */
14287 4098,
14288 /* J4_cmplt_t_jumpnv_nt */
14289 4101,
14290 /* J4_cmplt_t_jumpnv_t */
14291 4104,
14292 /* J4_cmpltu_f_jumpnv_nt */
14293 4107,
14294 /* J4_cmpltu_f_jumpnv_t */
14295 4110,
14296 /* J4_cmpltu_t_jumpnv_nt */
14297 4113,
14298 /* J4_cmpltu_t_jumpnv_t */
14299 4116,
14300 /* J4_hintjumpr */
14301 4119,
14302 /* J4_jumpseti */
14303 4120,
14304 /* J4_jumpsetr */
14305 4123,
14306 /* J4_tstbit0_f_jumpnv_nt */
14307 4126,
14308 /* J4_tstbit0_f_jumpnv_t */
14309 4128,
14310 /* J4_tstbit0_fp0_jump_nt */
14311 4130,
14312 /* J4_tstbit0_fp0_jump_t */
14313 4132,
14314 /* J4_tstbit0_fp1_jump_nt */
14315 4134,
14316 /* J4_tstbit0_fp1_jump_t */
14317 4136,
14318 /* J4_tstbit0_t_jumpnv_nt */
14319 4138,
14320 /* J4_tstbit0_t_jumpnv_t */
14321 4140,
14322 /* J4_tstbit0_tp0_jump_nt */
14323 4142,
14324 /* J4_tstbit0_tp0_jump_t */
14325 4144,
14326 /* J4_tstbit0_tp1_jump_nt */
14327 4146,
14328 /* J4_tstbit0_tp1_jump_t */
14329 4148,
14330 /* L2_deallocframe */
14331 4150,
14332 /* L2_loadalignb_io */
14333 4152,
14334 /* L2_loadalignb_pbr */
14335 4156,
14336 /* L2_loadalignb_pci */
14337 4161,
14338 /* L2_loadalignb_pcr */
14339 4167,
14340 /* L2_loadalignb_pi */
14341 4172,
14342 /* L2_loadalignb_pr */
14343 4177,
14344 /* L2_loadalignh_io */
14345 4182,
14346 /* L2_loadalignh_pbr */
14347 4186,
14348 /* L2_loadalignh_pci */
14349 4191,
14350 /* L2_loadalignh_pcr */
14351 4197,
14352 /* L2_loadalignh_pi */
14353 4202,
14354 /* L2_loadalignh_pr */
14355 4207,
14356 /* L2_loadbsw2_io */
14357 4212,
14358 /* L2_loadbsw2_pbr */
14359 4215,
14360 /* L2_loadbsw2_pci */
14361 4219,
14362 /* L2_loadbsw2_pcr */
14363 4224,
14364 /* L2_loadbsw2_pi */
14365 4228,
14366 /* L2_loadbsw2_pr */
14367 4232,
14368 /* L2_loadbsw4_io */
14369 4236,
14370 /* L2_loadbsw4_pbr */
14371 4239,
14372 /* L2_loadbsw4_pci */
14373 4243,
14374 /* L2_loadbsw4_pcr */
14375 4248,
14376 /* L2_loadbsw4_pi */
14377 4252,
14378 /* L2_loadbsw4_pr */
14379 4256,
14380 /* L2_loadbzw2_io */
14381 4260,
14382 /* L2_loadbzw2_pbr */
14383 4263,
14384 /* L2_loadbzw2_pci */
14385 4267,
14386 /* L2_loadbzw2_pcr */
14387 4272,
14388 /* L2_loadbzw2_pi */
14389 4276,
14390 /* L2_loadbzw2_pr */
14391 4280,
14392 /* L2_loadbzw4_io */
14393 4284,
14394 /* L2_loadbzw4_pbr */
14395 4287,
14396 /* L2_loadbzw4_pci */
14397 4291,
14398 /* L2_loadbzw4_pcr */
14399 4296,
14400 /* L2_loadbzw4_pi */
14401 4300,
14402 /* L2_loadbzw4_pr */
14403 4304,
14404 /* L2_loadrb_io */
14405 4308,
14406 /* L2_loadrb_pbr */
14407 4311,
14408 /* L2_loadrb_pci */
14409 4315,
14410 /* L2_loadrb_pcr */
14411 4320,
14412 /* L2_loadrb_pi */
14413 4324,
14414 /* L2_loadrb_pr */
14415 4328,
14416 /* L2_loadrbgp */
14417 4332,
14418 /* L2_loadrd_io */
14419 4334,
14420 /* L2_loadrd_pbr */
14421 4337,
14422 /* L2_loadrd_pci */
14423 4341,
14424 /* L2_loadrd_pcr */
14425 4346,
14426 /* L2_loadrd_pi */
14427 4350,
14428 /* L2_loadrd_pr */
14429 4354,
14430 /* L2_loadrdgp */
14431 4358,
14432 /* L2_loadrh_io */
14433 4360,
14434 /* L2_loadrh_pbr */
14435 4363,
14436 /* L2_loadrh_pci */
14437 4367,
14438 /* L2_loadrh_pcr */
14439 4372,
14440 /* L2_loadrh_pi */
14441 4376,
14442 /* L2_loadrh_pr */
14443 4380,
14444 /* L2_loadrhgp */
14445 4384,
14446 /* L2_loadri_io */
14447 4386,
14448 /* L2_loadri_pbr */
14449 4389,
14450 /* L2_loadri_pci */
14451 4393,
14452 /* L2_loadri_pcr */
14453 4398,
14454 /* L2_loadri_pi */
14455 4402,
14456 /* L2_loadri_pr */
14457 4406,
14458 /* L2_loadrigp */
14459 4410,
14460 /* L2_loadrub_io */
14461 4412,
14462 /* L2_loadrub_pbr */
14463 4415,
14464 /* L2_loadrub_pci */
14465 4419,
14466 /* L2_loadrub_pcr */
14467 4424,
14468 /* L2_loadrub_pi */
14469 4428,
14470 /* L2_loadrub_pr */
14471 4432,
14472 /* L2_loadrubgp */
14473 4436,
14474 /* L2_loadruh_io */
14475 4438,
14476 /* L2_loadruh_pbr */
14477 4441,
14478 /* L2_loadruh_pci */
14479 4445,
14480 /* L2_loadruh_pcr */
14481 4450,
14482 /* L2_loadruh_pi */
14483 4454,
14484 /* L2_loadruh_pr */
14485 4458,
14486 /* L2_loadruhgp */
14487 4462,
14488 /* L2_loadw_aq */
14489 4464,
14490 /* L2_loadw_locked */
14491 4466,
14492 /* L2_ploadrbf_io */
14493 4468,
14494 /* L2_ploadrbf_pi */
14495 4472,
14496 /* L2_ploadrbfnew_io */
14497 4477,
14498 /* L2_ploadrbfnew_pi */
14499 4481,
14500 /* L2_ploadrbt_io */
14501 4486,
14502 /* L2_ploadrbt_pi */
14503 4490,
14504 /* L2_ploadrbtnew_io */
14505 4495,
14506 /* L2_ploadrbtnew_pi */
14507 4499,
14508 /* L2_ploadrdf_io */
14509 4504,
14510 /* L2_ploadrdf_pi */
14511 4508,
14512 /* L2_ploadrdfnew_io */
14513 4513,
14514 /* L2_ploadrdfnew_pi */
14515 4517,
14516 /* L2_ploadrdt_io */
14517 4522,
14518 /* L2_ploadrdt_pi */
14519 4526,
14520 /* L2_ploadrdtnew_io */
14521 4531,
14522 /* L2_ploadrdtnew_pi */
14523 4535,
14524 /* L2_ploadrhf_io */
14525 4540,
14526 /* L2_ploadrhf_pi */
14527 4544,
14528 /* L2_ploadrhfnew_io */
14529 4549,
14530 /* L2_ploadrhfnew_pi */
14531 4553,
14532 /* L2_ploadrht_io */
14533 4558,
14534 /* L2_ploadrht_pi */
14535 4562,
14536 /* L2_ploadrhtnew_io */
14537 4567,
14538 /* L2_ploadrhtnew_pi */
14539 4571,
14540 /* L2_ploadrif_io */
14541 4576,
14542 /* L2_ploadrif_pi */
14543 4580,
14544 /* L2_ploadrifnew_io */
14545 4585,
14546 /* L2_ploadrifnew_pi */
14547 4589,
14548 /* L2_ploadrit_io */
14549 4594,
14550 /* L2_ploadrit_pi */
14551 4598,
14552 /* L2_ploadritnew_io */
14553 4603,
14554 /* L2_ploadritnew_pi */
14555 4607,
14556 /* L2_ploadrubf_io */
14557 4612,
14558 /* L2_ploadrubf_pi */
14559 4616,
14560 /* L2_ploadrubfnew_io */
14561 4621,
14562 /* L2_ploadrubfnew_pi */
14563 4625,
14564 /* L2_ploadrubt_io */
14565 4630,
14566 /* L2_ploadrubt_pi */
14567 4634,
14568 /* L2_ploadrubtnew_io */
14569 4639,
14570 /* L2_ploadrubtnew_pi */
14571 4643,
14572 /* L2_ploadruhf_io */
14573 4648,
14574 /* L2_ploadruhf_pi */
14575 4652,
14576 /* L2_ploadruhfnew_io */
14577 4657,
14578 /* L2_ploadruhfnew_pi */
14579 4661,
14580 /* L2_ploadruht_io */
14581 4666,
14582 /* L2_ploadruht_pi */
14583 4670,
14584 /* L2_ploadruhtnew_io */
14585 4675,
14586 /* L2_ploadruhtnew_pi */
14587 4679,
14588 /* L4_add_memopb_io */
14589 4684,
14590 /* L4_add_memoph_io */
14591 4687,
14592 /* L4_add_memopw_io */
14593 4690,
14594 /* L4_and_memopb_io */
14595 4693,
14596 /* L4_and_memoph_io */
14597 4696,
14598 /* L4_and_memopw_io */
14599 4699,
14600 /* L4_iadd_memopb_io */
14601 4702,
14602 /* L4_iadd_memoph_io */
14603 4705,
14604 /* L4_iadd_memopw_io */
14605 4708,
14606 /* L4_iand_memopb_io */
14607 4711,
14608 /* L4_iand_memoph_io */
14609 4714,
14610 /* L4_iand_memopw_io */
14611 4717,
14612 /* L4_ior_memopb_io */
14613 4720,
14614 /* L4_ior_memoph_io */
14615 4723,
14616 /* L4_ior_memopw_io */
14617 4726,
14618 /* L4_isub_memopb_io */
14619 4729,
14620 /* L4_isub_memoph_io */
14621 4732,
14622 /* L4_isub_memopw_io */
14623 4735,
14624 /* L4_loadalignb_ap */
14625 4738,
14626 /* L4_loadalignb_ur */
14627 4742,
14628 /* L4_loadalignh_ap */
14629 4747,
14630 /* L4_loadalignh_ur */
14631 4751,
14632 /* L4_loadbsw2_ap */
14633 4756,
14634 /* L4_loadbsw2_ur */
14635 4759,
14636 /* L4_loadbsw4_ap */
14637 4763,
14638 /* L4_loadbsw4_ur */
14639 4766,
14640 /* L4_loadbzw2_ap */
14641 4770,
14642 /* L4_loadbzw2_ur */
14643 4773,
14644 /* L4_loadbzw4_ap */
14645 4777,
14646 /* L4_loadbzw4_ur */
14647 4780,
14648 /* L4_loadd_aq */
14649 4784,
14650 /* L4_loadd_locked */
14651 4786,
14652 /* L4_loadrb_ap */
14653 4788,
14654 /* L4_loadrb_rr */
14655 4791,
14656 /* L4_loadrb_ur */
14657 4795,
14658 /* L4_loadrd_ap */
14659 4799,
14660 /* L4_loadrd_rr */
14661 4802,
14662 /* L4_loadrd_ur */
14663 4806,
14664 /* L4_loadrh_ap */
14665 4810,
14666 /* L4_loadrh_rr */
14667 4813,
14668 /* L4_loadrh_ur */
14669 4817,
14670 /* L4_loadri_ap */
14671 4821,
14672 /* L4_loadri_rr */
14673 4824,
14674 /* L4_loadri_ur */
14675 4828,
14676 /* L4_loadrub_ap */
14677 4832,
14678 /* L4_loadrub_rr */
14679 4835,
14680 /* L4_loadrub_ur */
14681 4839,
14682 /* L4_loadruh_ap */
14683 4843,
14684 /* L4_loadruh_rr */
14685 4846,
14686 /* L4_loadruh_ur */
14687 4850,
14688 /* L4_loadw_phys */
14689 4854,
14690 /* L4_or_memopb_io */
14691 4857,
14692 /* L4_or_memoph_io */
14693 4860,
14694 /* L4_or_memopw_io */
14695 4863,
14696 /* L4_ploadrbf_abs */
14697 4866,
14698 /* L4_ploadrbf_rr */
14699 4869,
14700 /* L4_ploadrbfnew_abs */
14701 4874,
14702 /* L4_ploadrbfnew_rr */
14703 4877,
14704 /* L4_ploadrbt_abs */
14705 4882,
14706 /* L4_ploadrbt_rr */
14707 4885,
14708 /* L4_ploadrbtnew_abs */
14709 4890,
14710 /* L4_ploadrbtnew_rr */
14711 4893,
14712 /* L4_ploadrdf_abs */
14713 4898,
14714 /* L4_ploadrdf_rr */
14715 4901,
14716 /* L4_ploadrdfnew_abs */
14717 4906,
14718 /* L4_ploadrdfnew_rr */
14719 4909,
14720 /* L4_ploadrdt_abs */
14721 4914,
14722 /* L4_ploadrdt_rr */
14723 4917,
14724 /* L4_ploadrdtnew_abs */
14725 4922,
14726 /* L4_ploadrdtnew_rr */
14727 4925,
14728 /* L4_ploadrhf_abs */
14729 4930,
14730 /* L4_ploadrhf_rr */
14731 4933,
14732 /* L4_ploadrhfnew_abs */
14733 4938,
14734 /* L4_ploadrhfnew_rr */
14735 4941,
14736 /* L4_ploadrht_abs */
14737 4946,
14738 /* L4_ploadrht_rr */
14739 4949,
14740 /* L4_ploadrhtnew_abs */
14741 4954,
14742 /* L4_ploadrhtnew_rr */
14743 4957,
14744 /* L4_ploadrif_abs */
14745 4962,
14746 /* L4_ploadrif_rr */
14747 4965,
14748 /* L4_ploadrifnew_abs */
14749 4970,
14750 /* L4_ploadrifnew_rr */
14751 4973,
14752 /* L4_ploadrit_abs */
14753 4978,
14754 /* L4_ploadrit_rr */
14755 4981,
14756 /* L4_ploadritnew_abs */
14757 4986,
14758 /* L4_ploadritnew_rr */
14759 4989,
14760 /* L4_ploadrubf_abs */
14761 4994,
14762 /* L4_ploadrubf_rr */
14763 4997,
14764 /* L4_ploadrubfnew_abs */
14765 5002,
14766 /* L4_ploadrubfnew_rr */
14767 5005,
14768 /* L4_ploadrubt_abs */
14769 5010,
14770 /* L4_ploadrubt_rr */
14771 5013,
14772 /* L4_ploadrubtnew_abs */
14773 5018,
14774 /* L4_ploadrubtnew_rr */
14775 5021,
14776 /* L4_ploadruhf_abs */
14777 5026,
14778 /* L4_ploadruhf_rr */
14779 5029,
14780 /* L4_ploadruhfnew_abs */
14781 5034,
14782 /* L4_ploadruhfnew_rr */
14783 5037,
14784 /* L4_ploadruht_abs */
14785 5042,
14786 /* L4_ploadruht_rr */
14787 5045,
14788 /* L4_ploadruhtnew_abs */
14789 5050,
14790 /* L4_ploadruhtnew_rr */
14791 5053,
14792 /* L4_return */
14793 5058,
14794 /* L4_return_f */
14795 5060,
14796 /* L4_return_fnew_pnt */
14797 5063,
14798 /* L4_return_fnew_pt */
14799 5066,
14800 /* L4_return_t */
14801 5069,
14802 /* L4_return_tnew_pnt */
14803 5072,
14804 /* L4_return_tnew_pt */
14805 5075,
14806 /* L4_sub_memopb_io */
14807 5078,
14808 /* L4_sub_memoph_io */
14809 5081,
14810 /* L4_sub_memopw_io */
14811 5084,
14812 /* L6_memcpy */
14813 5087,
14814 /* LO */
14815 5090,
14816 /* M2_acci */
14817 5092,
14818 /* M2_accii */
14819 5096,
14820 /* M2_cmaci_s0 */
14821 5100,
14822 /* M2_cmacr_s0 */
14823 5104,
14824 /* M2_cmacs_s0 */
14825 5108,
14826 /* M2_cmacs_s1 */
14827 5112,
14828 /* M2_cmacsc_s0 */
14829 5116,
14830 /* M2_cmacsc_s1 */
14831 5120,
14832 /* M2_cmpyi_s0 */
14833 5124,
14834 /* M2_cmpyr_s0 */
14835 5127,
14836 /* M2_cmpyrs_s0 */
14837 5130,
14838 /* M2_cmpyrs_s1 */
14839 5133,
14840 /* M2_cmpyrsc_s0 */
14841 5136,
14842 /* M2_cmpyrsc_s1 */
14843 5139,
14844 /* M2_cmpys_s0 */
14845 5142,
14846 /* M2_cmpys_s1 */
14847 5145,
14848 /* M2_cmpysc_s0 */
14849 5148,
14850 /* M2_cmpysc_s1 */
14851 5151,
14852 /* M2_cnacs_s0 */
14853 5154,
14854 /* M2_cnacs_s1 */
14855 5158,
14856 /* M2_cnacsc_s0 */
14857 5162,
14858 /* M2_cnacsc_s1 */
14859 5166,
14860 /* M2_dpmpyss_acc_s0 */
14861 5170,
14862 /* M2_dpmpyss_nac_s0 */
14863 5174,
14864 /* M2_dpmpyss_rnd_s0 */
14865 5178,
14866 /* M2_dpmpyss_s0 */
14867 5181,
14868 /* M2_dpmpyuu_acc_s0 */
14869 5184,
14870 /* M2_dpmpyuu_nac_s0 */
14871 5188,
14872 /* M2_dpmpyuu_s0 */
14873 5192,
14874 /* M2_hmmpyh_rs1 */
14875 5195,
14876 /* M2_hmmpyh_s1 */
14877 5198,
14878 /* M2_hmmpyl_rs1 */
14879 5201,
14880 /* M2_hmmpyl_s1 */
14881 5204,
14882 /* M2_maci */
14883 5207,
14884 /* M2_macsin */
14885 5211,
14886 /* M2_macsip */
14887 5215,
14888 /* M2_mmachs_rs0 */
14889 5219,
14890 /* M2_mmachs_rs1 */
14891 5223,
14892 /* M2_mmachs_s0 */
14893 5227,
14894 /* M2_mmachs_s1 */
14895 5231,
14896 /* M2_mmacls_rs0 */
14897 5235,
14898 /* M2_mmacls_rs1 */
14899 5239,
14900 /* M2_mmacls_s0 */
14901 5243,
14902 /* M2_mmacls_s1 */
14903 5247,
14904 /* M2_mmacuhs_rs0 */
14905 5251,
14906 /* M2_mmacuhs_rs1 */
14907 5255,
14908 /* M2_mmacuhs_s0 */
14909 5259,
14910 /* M2_mmacuhs_s1 */
14911 5263,
14912 /* M2_mmaculs_rs0 */
14913 5267,
14914 /* M2_mmaculs_rs1 */
14915 5271,
14916 /* M2_mmaculs_s0 */
14917 5275,
14918 /* M2_mmaculs_s1 */
14919 5279,
14920 /* M2_mmpyh_rs0 */
14921 5283,
14922 /* M2_mmpyh_rs1 */
14923 5286,
14924 /* M2_mmpyh_s0 */
14925 5289,
14926 /* M2_mmpyh_s1 */
14927 5292,
14928 /* M2_mmpyl_rs0 */
14929 5295,
14930 /* M2_mmpyl_rs1 */
14931 5298,
14932 /* M2_mmpyl_s0 */
14933 5301,
14934 /* M2_mmpyl_s1 */
14935 5304,
14936 /* M2_mmpyuh_rs0 */
14937 5307,
14938 /* M2_mmpyuh_rs1 */
14939 5310,
14940 /* M2_mmpyuh_s0 */
14941 5313,
14942 /* M2_mmpyuh_s1 */
14943 5316,
14944 /* M2_mmpyul_rs0 */
14945 5319,
14946 /* M2_mmpyul_rs1 */
14947 5322,
14948 /* M2_mmpyul_s0 */
14949 5325,
14950 /* M2_mmpyul_s1 */
14951 5328,
14952 /* M2_mnaci */
14953 5331,
14954 /* M2_mpy_acc_hh_s0 */
14955 5335,
14956 /* M2_mpy_acc_hh_s1 */
14957 5339,
14958 /* M2_mpy_acc_hl_s0 */
14959 5343,
14960 /* M2_mpy_acc_hl_s1 */
14961 5347,
14962 /* M2_mpy_acc_lh_s0 */
14963 5351,
14964 /* M2_mpy_acc_lh_s1 */
14965 5355,
14966 /* M2_mpy_acc_ll_s0 */
14967 5359,
14968 /* M2_mpy_acc_ll_s1 */
14969 5363,
14970 /* M2_mpy_acc_sat_hh_s0 */
14971 5367,
14972 /* M2_mpy_acc_sat_hh_s1 */
14973 5371,
14974 /* M2_mpy_acc_sat_hl_s0 */
14975 5375,
14976 /* M2_mpy_acc_sat_hl_s1 */
14977 5379,
14978 /* M2_mpy_acc_sat_lh_s0 */
14979 5383,
14980 /* M2_mpy_acc_sat_lh_s1 */
14981 5387,
14982 /* M2_mpy_acc_sat_ll_s0 */
14983 5391,
14984 /* M2_mpy_acc_sat_ll_s1 */
14985 5395,
14986 /* M2_mpy_hh_s0 */
14987 5399,
14988 /* M2_mpy_hh_s1 */
14989 5402,
14990 /* M2_mpy_hl_s0 */
14991 5405,
14992 /* M2_mpy_hl_s1 */
14993 5408,
14994 /* M2_mpy_lh_s0 */
14995 5411,
14996 /* M2_mpy_lh_s1 */
14997 5414,
14998 /* M2_mpy_ll_s0 */
14999 5417,
15000 /* M2_mpy_ll_s1 */
15001 5420,
15002 /* M2_mpy_nac_hh_s0 */
15003 5423,
15004 /* M2_mpy_nac_hh_s1 */
15005 5427,
15006 /* M2_mpy_nac_hl_s0 */
15007 5431,
15008 /* M2_mpy_nac_hl_s1 */
15009 5435,
15010 /* M2_mpy_nac_lh_s0 */
15011 5439,
15012 /* M2_mpy_nac_lh_s1 */
15013 5443,
15014 /* M2_mpy_nac_ll_s0 */
15015 5447,
15016 /* M2_mpy_nac_ll_s1 */
15017 5451,
15018 /* M2_mpy_nac_sat_hh_s0 */
15019 5455,
15020 /* M2_mpy_nac_sat_hh_s1 */
15021 5459,
15022 /* M2_mpy_nac_sat_hl_s0 */
15023 5463,
15024 /* M2_mpy_nac_sat_hl_s1 */
15025 5467,
15026 /* M2_mpy_nac_sat_lh_s0 */
15027 5471,
15028 /* M2_mpy_nac_sat_lh_s1 */
15029 5475,
15030 /* M2_mpy_nac_sat_ll_s0 */
15031 5479,
15032 /* M2_mpy_nac_sat_ll_s1 */
15033 5483,
15034 /* M2_mpy_rnd_hh_s0 */
15035 5487,
15036 /* M2_mpy_rnd_hh_s1 */
15037 5490,
15038 /* M2_mpy_rnd_hl_s0 */
15039 5493,
15040 /* M2_mpy_rnd_hl_s1 */
15041 5496,
15042 /* M2_mpy_rnd_lh_s0 */
15043 5499,
15044 /* M2_mpy_rnd_lh_s1 */
15045 5502,
15046 /* M2_mpy_rnd_ll_s0 */
15047 5505,
15048 /* M2_mpy_rnd_ll_s1 */
15049 5508,
15050 /* M2_mpy_sat_hh_s0 */
15051 5511,
15052 /* M2_mpy_sat_hh_s1 */
15053 5514,
15054 /* M2_mpy_sat_hl_s0 */
15055 5517,
15056 /* M2_mpy_sat_hl_s1 */
15057 5520,
15058 /* M2_mpy_sat_lh_s0 */
15059 5523,
15060 /* M2_mpy_sat_lh_s1 */
15061 5526,
15062 /* M2_mpy_sat_ll_s0 */
15063 5529,
15064 /* M2_mpy_sat_ll_s1 */
15065 5532,
15066 /* M2_mpy_sat_rnd_hh_s0 */
15067 5535,
15068 /* M2_mpy_sat_rnd_hh_s1 */
15069 5538,
15070 /* M2_mpy_sat_rnd_hl_s0 */
15071 5541,
15072 /* M2_mpy_sat_rnd_hl_s1 */
15073 5544,
15074 /* M2_mpy_sat_rnd_lh_s0 */
15075 5547,
15076 /* M2_mpy_sat_rnd_lh_s1 */
15077 5550,
15078 /* M2_mpy_sat_rnd_ll_s0 */
15079 5553,
15080 /* M2_mpy_sat_rnd_ll_s1 */
15081 5556,
15082 /* M2_mpy_up */
15083 5559,
15084 /* M2_mpy_up_s1 */
15085 5562,
15086 /* M2_mpy_up_s1_sat */
15087 5565,
15088 /* M2_mpyd_acc_hh_s0 */
15089 5568,
15090 /* M2_mpyd_acc_hh_s1 */
15091 5572,
15092 /* M2_mpyd_acc_hl_s0 */
15093 5576,
15094 /* M2_mpyd_acc_hl_s1 */
15095 5580,
15096 /* M2_mpyd_acc_lh_s0 */
15097 5584,
15098 /* M2_mpyd_acc_lh_s1 */
15099 5588,
15100 /* M2_mpyd_acc_ll_s0 */
15101 5592,
15102 /* M2_mpyd_acc_ll_s1 */
15103 5596,
15104 /* M2_mpyd_hh_s0 */
15105 5600,
15106 /* M2_mpyd_hh_s1 */
15107 5603,
15108 /* M2_mpyd_hl_s0 */
15109 5606,
15110 /* M2_mpyd_hl_s1 */
15111 5609,
15112 /* M2_mpyd_lh_s0 */
15113 5612,
15114 /* M2_mpyd_lh_s1 */
15115 5615,
15116 /* M2_mpyd_ll_s0 */
15117 5618,
15118 /* M2_mpyd_ll_s1 */
15119 5621,
15120 /* M2_mpyd_nac_hh_s0 */
15121 5624,
15122 /* M2_mpyd_nac_hh_s1 */
15123 5628,
15124 /* M2_mpyd_nac_hl_s0 */
15125 5632,
15126 /* M2_mpyd_nac_hl_s1 */
15127 5636,
15128 /* M2_mpyd_nac_lh_s0 */
15129 5640,
15130 /* M2_mpyd_nac_lh_s1 */
15131 5644,
15132 /* M2_mpyd_nac_ll_s0 */
15133 5648,
15134 /* M2_mpyd_nac_ll_s1 */
15135 5652,
15136 /* M2_mpyd_rnd_hh_s0 */
15137 5656,
15138 /* M2_mpyd_rnd_hh_s1 */
15139 5659,
15140 /* M2_mpyd_rnd_hl_s0 */
15141 5662,
15142 /* M2_mpyd_rnd_hl_s1 */
15143 5665,
15144 /* M2_mpyd_rnd_lh_s0 */
15145 5668,
15146 /* M2_mpyd_rnd_lh_s1 */
15147 5671,
15148 /* M2_mpyd_rnd_ll_s0 */
15149 5674,
15150 /* M2_mpyd_rnd_ll_s1 */
15151 5677,
15152 /* M2_mpyi */
15153 5680,
15154 /* M2_mpysin */
15155 5683,
15156 /* M2_mpysip */
15157 5686,
15158 /* M2_mpysu_up */
15159 5689,
15160 /* M2_mpyu_acc_hh_s0 */
15161 5692,
15162 /* M2_mpyu_acc_hh_s1 */
15163 5696,
15164 /* M2_mpyu_acc_hl_s0 */
15165 5700,
15166 /* M2_mpyu_acc_hl_s1 */
15167 5704,
15168 /* M2_mpyu_acc_lh_s0 */
15169 5708,
15170 /* M2_mpyu_acc_lh_s1 */
15171 5712,
15172 /* M2_mpyu_acc_ll_s0 */
15173 5716,
15174 /* M2_mpyu_acc_ll_s1 */
15175 5720,
15176 /* M2_mpyu_hh_s0 */
15177 5724,
15178 /* M2_mpyu_hh_s1 */
15179 5727,
15180 /* M2_mpyu_hl_s0 */
15181 5730,
15182 /* M2_mpyu_hl_s1 */
15183 5733,
15184 /* M2_mpyu_lh_s0 */
15185 5736,
15186 /* M2_mpyu_lh_s1 */
15187 5739,
15188 /* M2_mpyu_ll_s0 */
15189 5742,
15190 /* M2_mpyu_ll_s1 */
15191 5745,
15192 /* M2_mpyu_nac_hh_s0 */
15193 5748,
15194 /* M2_mpyu_nac_hh_s1 */
15195 5752,
15196 /* M2_mpyu_nac_hl_s0 */
15197 5756,
15198 /* M2_mpyu_nac_hl_s1 */
15199 5760,
15200 /* M2_mpyu_nac_lh_s0 */
15201 5764,
15202 /* M2_mpyu_nac_lh_s1 */
15203 5768,
15204 /* M2_mpyu_nac_ll_s0 */
15205 5772,
15206 /* M2_mpyu_nac_ll_s1 */
15207 5776,
15208 /* M2_mpyu_up */
15209 5780,
15210 /* M2_mpyud_acc_hh_s0 */
15211 5783,
15212 /* M2_mpyud_acc_hh_s1 */
15213 5787,
15214 /* M2_mpyud_acc_hl_s0 */
15215 5791,
15216 /* M2_mpyud_acc_hl_s1 */
15217 5795,
15218 /* M2_mpyud_acc_lh_s0 */
15219 5799,
15220 /* M2_mpyud_acc_lh_s1 */
15221 5803,
15222 /* M2_mpyud_acc_ll_s0 */
15223 5807,
15224 /* M2_mpyud_acc_ll_s1 */
15225 5811,
15226 /* M2_mpyud_hh_s0 */
15227 5815,
15228 /* M2_mpyud_hh_s1 */
15229 5818,
15230 /* M2_mpyud_hl_s0 */
15231 5821,
15232 /* M2_mpyud_hl_s1 */
15233 5824,
15234 /* M2_mpyud_lh_s0 */
15235 5827,
15236 /* M2_mpyud_lh_s1 */
15237 5830,
15238 /* M2_mpyud_ll_s0 */
15239 5833,
15240 /* M2_mpyud_ll_s1 */
15241 5836,
15242 /* M2_mpyud_nac_hh_s0 */
15243 5839,
15244 /* M2_mpyud_nac_hh_s1 */
15245 5843,
15246 /* M2_mpyud_nac_hl_s0 */
15247 5847,
15248 /* M2_mpyud_nac_hl_s1 */
15249 5851,
15250 /* M2_mpyud_nac_lh_s0 */
15251 5855,
15252 /* M2_mpyud_nac_lh_s1 */
15253 5859,
15254 /* M2_mpyud_nac_ll_s0 */
15255 5863,
15256 /* M2_mpyud_nac_ll_s1 */
15257 5867,
15258 /* M2_nacci */
15259 5871,
15260 /* M2_naccii */
15261 5875,
15262 /* M2_subacc */
15263 5879,
15264 /* M2_vabsdiffh */
15265 5883,
15266 /* M2_vabsdiffw */
15267 5886,
15268 /* M2_vcmac_s0_sat_i */
15269 5889,
15270 /* M2_vcmac_s0_sat_r */
15271 5893,
15272 /* M2_vcmpy_s0_sat_i */
15273 5897,
15274 /* M2_vcmpy_s0_sat_r */
15275 5900,
15276 /* M2_vcmpy_s1_sat_i */
15277 5903,
15278 /* M2_vcmpy_s1_sat_r */
15279 5906,
15280 /* M2_vdmacs_s0 */
15281 5909,
15282 /* M2_vdmacs_s1 */
15283 5913,
15284 /* M2_vdmpyrs_s0 */
15285 5917,
15286 /* M2_vdmpyrs_s1 */
15287 5920,
15288 /* M2_vdmpys_s0 */
15289 5923,
15290 /* M2_vdmpys_s1 */
15291 5926,
15292 /* M2_vmac2 */
15293 5929,
15294 /* M2_vmac2es */
15295 5933,
15296 /* M2_vmac2es_s0 */
15297 5937,
15298 /* M2_vmac2es_s1 */
15299 5941,
15300 /* M2_vmac2s_s0 */
15301 5945,
15302 /* M2_vmac2s_s1 */
15303 5949,
15304 /* M2_vmac2su_s0 */
15305 5953,
15306 /* M2_vmac2su_s1 */
15307 5957,
15308 /* M2_vmpy2es_s0 */
15309 5961,
15310 /* M2_vmpy2es_s1 */
15311 5964,
15312 /* M2_vmpy2s_s0 */
15313 5967,
15314 /* M2_vmpy2s_s0pack */
15315 5970,
15316 /* M2_vmpy2s_s1 */
15317 5973,
15318 /* M2_vmpy2s_s1pack */
15319 5976,
15320 /* M2_vmpy2su_s0 */
15321 5979,
15322 /* M2_vmpy2su_s1 */
15323 5982,
15324 /* M2_vraddh */
15325 5985,
15326 /* M2_vradduh */
15327 5988,
15328 /* M2_vrcmaci_s0 */
15329 5991,
15330 /* M2_vrcmaci_s0c */
15331 5995,
15332 /* M2_vrcmacr_s0 */
15333 5999,
15334 /* M2_vrcmacr_s0c */
15335 6003,
15336 /* M2_vrcmpyi_s0 */
15337 6007,
15338 /* M2_vrcmpyi_s0c */
15339 6010,
15340 /* M2_vrcmpyr_s0 */
15341 6013,
15342 /* M2_vrcmpyr_s0c */
15343 6016,
15344 /* M2_vrcmpys_acc_s1_h */
15345 6019,
15346 /* M2_vrcmpys_acc_s1_l */
15347 6023,
15348 /* M2_vrcmpys_s1_h */
15349 6027,
15350 /* M2_vrcmpys_s1_l */
15351 6030,
15352 /* M2_vrcmpys_s1rp_h */
15353 6033,
15354 /* M2_vrcmpys_s1rp_l */
15355 6036,
15356 /* M2_vrmac_s0 */
15357 6039,
15358 /* M2_vrmpy_s0 */
15359 6043,
15360 /* M2_xor_xacc */
15361 6046,
15362 /* M4_and_and */
15363 6050,
15364 /* M4_and_andn */
15365 6054,
15366 /* M4_and_or */
15367 6058,
15368 /* M4_and_xor */
15369 6062,
15370 /* M4_cmpyi_wh */
15371 6066,
15372 /* M4_cmpyi_whc */
15373 6069,
15374 /* M4_cmpyr_wh */
15375 6072,
15376 /* M4_cmpyr_whc */
15377 6075,
15378 /* M4_mac_up_s1_sat */
15379 6078,
15380 /* M4_mpyri_addi */
15381 6082,
15382 /* M4_mpyri_addr */
15383 6086,
15384 /* M4_mpyri_addr_u2 */
15385 6090,
15386 /* M4_mpyrr_addi */
15387 6094,
15388 /* M4_mpyrr_addr */
15389 6098,
15390 /* M4_nac_up_s1_sat */
15391 6102,
15392 /* M4_or_and */
15393 6106,
15394 /* M4_or_andn */
15395 6110,
15396 /* M4_or_or */
15397 6114,
15398 /* M4_or_xor */
15399 6118,
15400 /* M4_pmpyw */
15401 6122,
15402 /* M4_pmpyw_acc */
15403 6125,
15404 /* M4_vpmpyh */
15405 6129,
15406 /* M4_vpmpyh_acc */
15407 6132,
15408 /* M4_vrmpyeh_acc_s0 */
15409 6136,
15410 /* M4_vrmpyeh_acc_s1 */
15411 6140,
15412 /* M4_vrmpyeh_s0 */
15413 6144,
15414 /* M4_vrmpyeh_s1 */
15415 6147,
15416 /* M4_vrmpyoh_acc_s0 */
15417 6150,
15418 /* M4_vrmpyoh_acc_s1 */
15419 6154,
15420 /* M4_vrmpyoh_s0 */
15421 6158,
15422 /* M4_vrmpyoh_s1 */
15423 6161,
15424 /* M4_xor_and */
15425 6164,
15426 /* M4_xor_andn */
15427 6168,
15428 /* M4_xor_or */
15429 6172,
15430 /* M4_xor_xacc */
15431 6176,
15432 /* M5_vdmacbsu */
15433 6180,
15434 /* M5_vdmpybsu */
15435 6184,
15436 /* M5_vmacbsu */
15437 6187,
15438 /* M5_vmacbuu */
15439 6191,
15440 /* M5_vmpybsu */
15441 6195,
15442 /* M5_vmpybuu */
15443 6198,
15444 /* M5_vrmacbsu */
15445 6201,
15446 /* M5_vrmacbuu */
15447 6205,
15448 /* M5_vrmpybsu */
15449 6209,
15450 /* M5_vrmpybuu */
15451 6212,
15452 /* M6_vabsdiffb */
15453 6215,
15454 /* M6_vabsdiffub */
15455 6218,
15456 /* M7_dcmpyiw */
15457 6221,
15458 /* M7_dcmpyiw_acc */
15459 6224,
15460 /* M7_dcmpyiwc */
15461 6228,
15462 /* M7_dcmpyiwc_acc */
15463 6231,
15464 /* M7_dcmpyrw */
15465 6235,
15466 /* M7_dcmpyrw_acc */
15467 6238,
15468 /* M7_dcmpyrwc */
15469 6242,
15470 /* M7_dcmpyrwc_acc */
15471 6245,
15472 /* M7_wcmpyiw */
15473 6249,
15474 /* M7_wcmpyiw_rnd */
15475 6252,
15476 /* M7_wcmpyiwc */
15477 6255,
15478 /* M7_wcmpyiwc_rnd */
15479 6258,
15480 /* M7_wcmpyrw */
15481 6261,
15482 /* M7_wcmpyrw_rnd */
15483 6264,
15484 /* M7_wcmpyrwc */
15485 6267,
15486 /* M7_wcmpyrwc_rnd */
15487 6270,
15488 /* PS_call_stk */
15489 6273,
15490 /* PS_callr_nr */
15491 6274,
15492 /* PS_jmpret */
15493 6275,
15494 /* PS_jmpretf */
15495 6276,
15496 /* PS_jmpretfnew */
15497 6278,
15498 /* PS_jmpretfnewpt */
15499 6280,
15500 /* PS_jmprett */
15501 6282,
15502 /* PS_jmprettnew */
15503 6284,
15504 /* PS_jmprettnewpt */
15505 6286,
15506 /* PS_loadrbabs */
15507 6288,
15508 /* PS_loadrdabs */
15509 6290,
15510 /* PS_loadrhabs */
15511 6292,
15512 /* PS_loadriabs */
15513 6294,
15514 /* PS_loadrubabs */
15515 6296,
15516 /* PS_loadruhabs */
15517 6298,
15518 /* PS_storerbabs */
15519 6300,
15520 /* PS_storerbnewabs */
15521 6302,
15522 /* PS_storerdabs */
15523 6304,
15524 /* PS_storerfabs */
15525 6306,
15526 /* PS_storerhabs */
15527 6308,
15528 /* PS_storerhnewabs */
15529 6310,
15530 /* PS_storeriabs */
15531 6312,
15532 /* PS_storerinewabs */
15533 6314,
15534 /* PS_trap1 */
15535 6316,
15536 /* R6_release_at_vi */
15537 6317,
15538 /* R6_release_st_vi */
15539 6318,
15540 /* RESTORE_DEALLOC_BEFORE_TAILCALL_V4 */
15541 6319,
15542 /* RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT */
15543 6320,
15544 /* RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC */
15545 6321,
15546 /* RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC */
15547 6322,
15548 /* RESTORE_DEALLOC_RET_JMP_V4 */
15549 6323,
15550 /* RESTORE_DEALLOC_RET_JMP_V4_EXT */
15551 6324,
15552 /* RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC */
15553 6325,
15554 /* RESTORE_DEALLOC_RET_JMP_V4_PIC */
15555 6326,
15556 /* S2_addasl_rrri */
15557 6327,
15558 /* S2_allocframe */
15559 6331,
15560 /* S2_asl_i_p */
15561 6334,
15562 /* S2_asl_i_p_acc */
15563 6337,
15564 /* S2_asl_i_p_and */
15565 6341,
15566 /* S2_asl_i_p_nac */
15567 6345,
15568 /* S2_asl_i_p_or */
15569 6349,
15570 /* S2_asl_i_p_xacc */
15571 6353,
15572 /* S2_asl_i_r */
15573 6357,
15574 /* S2_asl_i_r_acc */
15575 6360,
15576 /* S2_asl_i_r_and */
15577 6364,
15578 /* S2_asl_i_r_nac */
15579 6368,
15580 /* S2_asl_i_r_or */
15581 6372,
15582 /* S2_asl_i_r_sat */
15583 6376,
15584 /* S2_asl_i_r_xacc */
15585 6379,
15586 /* S2_asl_i_vh */
15587 6383,
15588 /* S2_asl_i_vw */
15589 6386,
15590 /* S2_asl_r_p */
15591 6389,
15592 /* S2_asl_r_p_acc */
15593 6392,
15594 /* S2_asl_r_p_and */
15595 6396,
15596 /* S2_asl_r_p_nac */
15597 6400,
15598 /* S2_asl_r_p_or */
15599 6404,
15600 /* S2_asl_r_p_xor */
15601 6408,
15602 /* S2_asl_r_r */
15603 6412,
15604 /* S2_asl_r_r_acc */
15605 6415,
15606 /* S2_asl_r_r_and */
15607 6419,
15608 /* S2_asl_r_r_nac */
15609 6423,
15610 /* S2_asl_r_r_or */
15611 6427,
15612 /* S2_asl_r_r_sat */
15613 6431,
15614 /* S2_asl_r_vh */
15615 6434,
15616 /* S2_asl_r_vw */
15617 6437,
15618 /* S2_asr_i_p */
15619 6440,
15620 /* S2_asr_i_p_acc */
15621 6443,
15622 /* S2_asr_i_p_and */
15623 6447,
15624 /* S2_asr_i_p_nac */
15625 6451,
15626 /* S2_asr_i_p_or */
15627 6455,
15628 /* S2_asr_i_p_rnd */
15629 6459,
15630 /* S2_asr_i_r */
15631 6462,
15632 /* S2_asr_i_r_acc */
15633 6465,
15634 /* S2_asr_i_r_and */
15635 6469,
15636 /* S2_asr_i_r_nac */
15637 6473,
15638 /* S2_asr_i_r_or */
15639 6477,
15640 /* S2_asr_i_r_rnd */
15641 6481,
15642 /* S2_asr_i_svw_trun */
15643 6484,
15644 /* S2_asr_i_vh */
15645 6487,
15646 /* S2_asr_i_vw */
15647 6490,
15648 /* S2_asr_r_p */
15649 6493,
15650 /* S2_asr_r_p_acc */
15651 6496,
15652 /* S2_asr_r_p_and */
15653 6500,
15654 /* S2_asr_r_p_nac */
15655 6504,
15656 /* S2_asr_r_p_or */
15657 6508,
15658 /* S2_asr_r_p_xor */
15659 6512,
15660 /* S2_asr_r_r */
15661 6516,
15662 /* S2_asr_r_r_acc */
15663 6519,
15664 /* S2_asr_r_r_and */
15665 6523,
15666 /* S2_asr_r_r_nac */
15667 6527,
15668 /* S2_asr_r_r_or */
15669 6531,
15670 /* S2_asr_r_r_sat */
15671 6535,
15672 /* S2_asr_r_svw_trun */
15673 6538,
15674 /* S2_asr_r_vh */
15675 6541,
15676 /* S2_asr_r_vw */
15677 6544,
15678 /* S2_brev */
15679 6547,
15680 /* S2_brevp */
15681 6549,
15682 /* S2_cabacdecbin */
15683 6551,
15684 /* S2_cl0 */
15685 6554,
15686 /* S2_cl0p */
15687 6556,
15688 /* S2_cl1 */
15689 6558,
15690 /* S2_cl1p */
15691 6560,
15692 /* S2_clb */
15693 6562,
15694 /* S2_clbnorm */
15695 6564,
15696 /* S2_clbp */
15697 6566,
15698 /* S2_clrbit_i */
15699 6568,
15700 /* S2_clrbit_r */
15701 6571,
15702 /* S2_ct0 */
15703 6574,
15704 /* S2_ct0p */
15705 6576,
15706 /* S2_ct1 */
15707 6578,
15708 /* S2_ct1p */
15709 6580,
15710 /* S2_deinterleave */
15711 6582,
15712 /* S2_extractu */
15713 6584,
15714 /* S2_extractu_rp */
15715 6588,
15716 /* S2_extractup */
15717 6591,
15718 /* S2_extractup_rp */
15719 6595,
15720 /* S2_insert */
15721 6598,
15722 /* S2_insert_rp */
15723 6603,
15724 /* S2_insertp */
15725 6607,
15726 /* S2_insertp_rp */
15727 6612,
15728 /* S2_interleave */
15729 6616,
15730 /* S2_lfsp */
15731 6618,
15732 /* S2_lsl_r_p */
15733 6621,
15734 /* S2_lsl_r_p_acc */
15735 6624,
15736 /* S2_lsl_r_p_and */
15737 6628,
15738 /* S2_lsl_r_p_nac */
15739 6632,
15740 /* S2_lsl_r_p_or */
15741 6636,
15742 /* S2_lsl_r_p_xor */
15743 6640,
15744 /* S2_lsl_r_r */
15745 6644,
15746 /* S2_lsl_r_r_acc */
15747 6647,
15748 /* S2_lsl_r_r_and */
15749 6651,
15750 /* S2_lsl_r_r_nac */
15751 6655,
15752 /* S2_lsl_r_r_or */
15753 6659,
15754 /* S2_lsl_r_vh */
15755 6663,
15756 /* S2_lsl_r_vw */
15757 6666,
15758 /* S2_lsr_i_p */
15759 6669,
15760 /* S2_lsr_i_p_acc */
15761 6672,
15762 /* S2_lsr_i_p_and */
15763 6676,
15764 /* S2_lsr_i_p_nac */
15765 6680,
15766 /* S2_lsr_i_p_or */
15767 6684,
15768 /* S2_lsr_i_p_xacc */
15769 6688,
15770 /* S2_lsr_i_r */
15771 6692,
15772 /* S2_lsr_i_r_acc */
15773 6695,
15774 /* S2_lsr_i_r_and */
15775 6699,
15776 /* S2_lsr_i_r_nac */
15777 6703,
15778 /* S2_lsr_i_r_or */
15779 6707,
15780 /* S2_lsr_i_r_xacc */
15781 6711,
15782 /* S2_lsr_i_vh */
15783 6715,
15784 /* S2_lsr_i_vw */
15785 6718,
15786 /* S2_lsr_r_p */
15787 6721,
15788 /* S2_lsr_r_p_acc */
15789 6724,
15790 /* S2_lsr_r_p_and */
15791 6728,
15792 /* S2_lsr_r_p_nac */
15793 6732,
15794 /* S2_lsr_r_p_or */
15795 6736,
15796 /* S2_lsr_r_p_xor */
15797 6740,
15798 /* S2_lsr_r_r */
15799 6744,
15800 /* S2_lsr_r_r_acc */
15801 6747,
15802 /* S2_lsr_r_r_and */
15803 6751,
15804 /* S2_lsr_r_r_nac */
15805 6755,
15806 /* S2_lsr_r_r_or */
15807 6759,
15808 /* S2_lsr_r_vh */
15809 6763,
15810 /* S2_lsr_r_vw */
15811 6766,
15812 /* S2_mask */
15813 6769,
15814 /* S2_packhl */
15815 6772,
15816 /* S2_parityp */
15817 6775,
15818 /* S2_pstorerbf_io */
15819 6778,
15820 /* S2_pstorerbf_pi */
15821 6782,
15822 /* S2_pstorerbfnew_pi */
15823 6787,
15824 /* S2_pstorerbnewf_io */
15825 6792,
15826 /* S2_pstorerbnewf_pi */
15827 6796,
15828 /* S2_pstorerbnewfnew_pi */
15829 6801,
15830 /* S2_pstorerbnewt_io */
15831 6806,
15832 /* S2_pstorerbnewt_pi */
15833 6810,
15834 /* S2_pstorerbnewtnew_pi */
15835 6815,
15836 /* S2_pstorerbt_io */
15837 6820,
15838 /* S2_pstorerbt_pi */
15839 6824,
15840 /* S2_pstorerbtnew_pi */
15841 6829,
15842 /* S2_pstorerdf_io */
15843 6834,
15844 /* S2_pstorerdf_pi */
15845 6838,
15846 /* S2_pstorerdfnew_pi */
15847 6843,
15848 /* S2_pstorerdt_io */
15849 6848,
15850 /* S2_pstorerdt_pi */
15851 6852,
15852 /* S2_pstorerdtnew_pi */
15853 6857,
15854 /* S2_pstorerff_io */
15855 6862,
15856 /* S2_pstorerff_pi */
15857 6866,
15858 /* S2_pstorerffnew_pi */
15859 6871,
15860 /* S2_pstorerft_io */
15861 6876,
15862 /* S2_pstorerft_pi */
15863 6880,
15864 /* S2_pstorerftnew_pi */
15865 6885,
15866 /* S2_pstorerhf_io */
15867 6890,
15868 /* S2_pstorerhf_pi */
15869 6894,
15870 /* S2_pstorerhfnew_pi */
15871 6899,
15872 /* S2_pstorerhnewf_io */
15873 6904,
15874 /* S2_pstorerhnewf_pi */
15875 6908,
15876 /* S2_pstorerhnewfnew_pi */
15877 6913,
15878 /* S2_pstorerhnewt_io */
15879 6918,
15880 /* S2_pstorerhnewt_pi */
15881 6922,
15882 /* S2_pstorerhnewtnew_pi */
15883 6927,
15884 /* S2_pstorerht_io */
15885 6932,
15886 /* S2_pstorerht_pi */
15887 6936,
15888 /* S2_pstorerhtnew_pi */
15889 6941,
15890 /* S2_pstorerif_io */
15891 6946,
15892 /* S2_pstorerif_pi */
15893 6950,
15894 /* S2_pstorerifnew_pi */
15895 6955,
15896 /* S2_pstorerinewf_io */
15897 6960,
15898 /* S2_pstorerinewf_pi */
15899 6964,
15900 /* S2_pstorerinewfnew_pi */
15901 6969,
15902 /* S2_pstorerinewt_io */
15903 6974,
15904 /* S2_pstorerinewt_pi */
15905 6978,
15906 /* S2_pstorerinewtnew_pi */
15907 6983,
15908 /* S2_pstorerit_io */
15909 6988,
15910 /* S2_pstorerit_pi */
15911 6992,
15912 /* S2_pstoreritnew_pi */
15913 6997,
15914 /* S2_setbit_i */
15915 7002,
15916 /* S2_setbit_r */
15917 7005,
15918 /* S2_shuffeb */
15919 7008,
15920 /* S2_shuffeh */
15921 7011,
15922 /* S2_shuffob */
15923 7014,
15924 /* S2_shuffoh */
15925 7017,
15926 /* S2_storerb_io */
15927 7020,
15928 /* S2_storerb_pbr */
15929 7023,
15930 /* S2_storerb_pci */
15931 7027,
15932 /* S2_storerb_pcr */
15933 7032,
15934 /* S2_storerb_pi */
15935 7036,
15936 /* S2_storerb_pr */
15937 7040,
15938 /* S2_storerbgp */
15939 7044,
15940 /* S2_storerbnew_io */
15941 7046,
15942 /* S2_storerbnew_pbr */
15943 7049,
15944 /* S2_storerbnew_pci */
15945 7053,
15946 /* S2_storerbnew_pcr */
15947 7058,
15948 /* S2_storerbnew_pi */
15949 7062,
15950 /* S2_storerbnew_pr */
15951 7066,
15952 /* S2_storerbnewgp */
15953 7070,
15954 /* S2_storerd_io */
15955 7072,
15956 /* S2_storerd_pbr */
15957 7075,
15958 /* S2_storerd_pci */
15959 7079,
15960 /* S2_storerd_pcr */
15961 7084,
15962 /* S2_storerd_pi */
15963 7088,
15964 /* S2_storerd_pr */
15965 7092,
15966 /* S2_storerdgp */
15967 7096,
15968 /* S2_storerf_io */
15969 7098,
15970 /* S2_storerf_pbr */
15971 7101,
15972 /* S2_storerf_pci */
15973 7105,
15974 /* S2_storerf_pcr */
15975 7110,
15976 /* S2_storerf_pi */
15977 7114,
15978 /* S2_storerf_pr */
15979 7118,
15980 /* S2_storerfgp */
15981 7122,
15982 /* S2_storerh_io */
15983 7124,
15984 /* S2_storerh_pbr */
15985 7127,
15986 /* S2_storerh_pci */
15987 7131,
15988 /* S2_storerh_pcr */
15989 7136,
15990 /* S2_storerh_pi */
15991 7140,
15992 /* S2_storerh_pr */
15993 7144,
15994 /* S2_storerhgp */
15995 7148,
15996 /* S2_storerhnew_io */
15997 7150,
15998 /* S2_storerhnew_pbr */
15999 7153,
16000 /* S2_storerhnew_pci */
16001 7157,
16002 /* S2_storerhnew_pcr */
16003 7162,
16004 /* S2_storerhnew_pi */
16005 7166,
16006 /* S2_storerhnew_pr */
16007 7170,
16008 /* S2_storerhnewgp */
16009 7174,
16010 /* S2_storeri_io */
16011 7176,
16012 /* S2_storeri_pbr */
16013 7179,
16014 /* S2_storeri_pci */
16015 7183,
16016 /* S2_storeri_pcr */
16017 7188,
16018 /* S2_storeri_pi */
16019 7192,
16020 /* S2_storeri_pr */
16021 7196,
16022 /* S2_storerigp */
16023 7200,
16024 /* S2_storerinew_io */
16025 7202,
16026 /* S2_storerinew_pbr */
16027 7205,
16028 /* S2_storerinew_pci */
16029 7209,
16030 /* S2_storerinew_pcr */
16031 7214,
16032 /* S2_storerinew_pi */
16033 7218,
16034 /* S2_storerinew_pr */
16035 7222,
16036 /* S2_storerinewgp */
16037 7226,
16038 /* S2_storew_locked */
16039 7228,
16040 /* S2_storew_rl_at_vi */
16041 7231,
16042 /* S2_storew_rl_st_vi */
16043 7233,
16044 /* S2_svsathb */
16045 7235,
16046 /* S2_svsathub */
16047 7237,
16048 /* S2_tableidxb */
16049 7239,
16050 /* S2_tableidxd */
16051 7244,
16052 /* S2_tableidxh */
16053 7249,
16054 /* S2_tableidxw */
16055 7254,
16056 /* S2_togglebit_i */
16057 7259,
16058 /* S2_togglebit_r */
16059 7262,
16060 /* S2_tstbit_i */
16061 7265,
16062 /* S2_tstbit_r */
16063 7268,
16064 /* S2_valignib */
16065 7271,
16066 /* S2_valignrb */
16067 7275,
16068 /* S2_vcnegh */
16069 7279,
16070 /* S2_vcrotate */
16071 7282,
16072 /* S2_vrcnegh */
16073 7285,
16074 /* S2_vrndpackwh */
16075 7289,
16076 /* S2_vrndpackwhs */
16077 7291,
16078 /* S2_vsathb */
16079 7293,
16080 /* S2_vsathb_nopack */
16081 7295,
16082 /* S2_vsathub */
16083 7297,
16084 /* S2_vsathub_nopack */
16085 7299,
16086 /* S2_vsatwh */
16087 7301,
16088 /* S2_vsatwh_nopack */
16089 7303,
16090 /* S2_vsatwuh */
16091 7305,
16092 /* S2_vsatwuh_nopack */
16093 7307,
16094 /* S2_vsplatrb */
16095 7309,
16096 /* S2_vsplatrh */
16097 7311,
16098 /* S2_vspliceib */
16099 7313,
16100 /* S2_vsplicerb */
16101 7317,
16102 /* S2_vsxtbh */
16103 7321,
16104 /* S2_vsxthw */
16105 7323,
16106 /* S2_vtrunehb */
16107 7325,
16108 /* S2_vtrunewh */
16109 7327,
16110 /* S2_vtrunohb */
16111 7330,
16112 /* S2_vtrunowh */
16113 7332,
16114 /* S2_vzxtbh */
16115 7335,
16116 /* S2_vzxthw */
16117 7337,
16118 /* S4_addaddi */
16119 7339,
16120 /* S4_addi_asl_ri */
16121 7343,
16122 /* S4_addi_lsr_ri */
16123 7347,
16124 /* S4_andi_asl_ri */
16125 7351,
16126 /* S4_andi_lsr_ri */
16127 7355,
16128 /* S4_clbaddi */
16129 7359,
16130 /* S4_clbpaddi */
16131 7362,
16132 /* S4_clbpnorm */
16133 7365,
16134 /* S4_extract */
16135 7367,
16136 /* S4_extract_rp */
16137 7371,
16138 /* S4_extractp */
16139 7374,
16140 /* S4_extractp_rp */
16141 7378,
16142 /* S4_lsli */
16143 7381,
16144 /* S4_ntstbit_i */
16145 7384,
16146 /* S4_ntstbit_r */
16147 7387,
16148 /* S4_or_andi */
16149 7390,
16150 /* S4_or_andix */
16151 7394,
16152 /* S4_or_ori */
16153 7398,
16154 /* S4_ori_asl_ri */
16155 7402,
16156 /* S4_ori_lsr_ri */
16157 7406,
16158 /* S4_parity */
16159 7410,
16160 /* S4_pstorerbf_abs */
16161 7413,
16162 /* S4_pstorerbf_rr */
16163 7416,
16164 /* S4_pstorerbfnew_abs */
16165 7421,
16166 /* S4_pstorerbfnew_io */
16167 7424,
16168 /* S4_pstorerbfnew_rr */
16169 7428,
16170 /* S4_pstorerbnewf_abs */
16171 7433,
16172 /* S4_pstorerbnewf_rr */
16173 7436,
16174 /* S4_pstorerbnewfnew_abs */
16175 7441,
16176 /* S4_pstorerbnewfnew_io */
16177 7444,
16178 /* S4_pstorerbnewfnew_rr */
16179 7448,
16180 /* S4_pstorerbnewt_abs */
16181 7453,
16182 /* S4_pstorerbnewt_rr */
16183 7456,
16184 /* S4_pstorerbnewtnew_abs */
16185 7461,
16186 /* S4_pstorerbnewtnew_io */
16187 7464,
16188 /* S4_pstorerbnewtnew_rr */
16189 7468,
16190 /* S4_pstorerbt_abs */
16191 7473,
16192 /* S4_pstorerbt_rr */
16193 7476,
16194 /* S4_pstorerbtnew_abs */
16195 7481,
16196 /* S4_pstorerbtnew_io */
16197 7484,
16198 /* S4_pstorerbtnew_rr */
16199 7488,
16200 /* S4_pstorerdf_abs */
16201 7493,
16202 /* S4_pstorerdf_rr */
16203 7496,
16204 /* S4_pstorerdfnew_abs */
16205 7501,
16206 /* S4_pstorerdfnew_io */
16207 7504,
16208 /* S4_pstorerdfnew_rr */
16209 7508,
16210 /* S4_pstorerdt_abs */
16211 7513,
16212 /* S4_pstorerdt_rr */
16213 7516,
16214 /* S4_pstorerdtnew_abs */
16215 7521,
16216 /* S4_pstorerdtnew_io */
16217 7524,
16218 /* S4_pstorerdtnew_rr */
16219 7528,
16220 /* S4_pstorerff_abs */
16221 7533,
16222 /* S4_pstorerff_rr */
16223 7536,
16224 /* S4_pstorerffnew_abs */
16225 7541,
16226 /* S4_pstorerffnew_io */
16227 7544,
16228 /* S4_pstorerffnew_rr */
16229 7548,
16230 /* S4_pstorerft_abs */
16231 7553,
16232 /* S4_pstorerft_rr */
16233 7556,
16234 /* S4_pstorerftnew_abs */
16235 7561,
16236 /* S4_pstorerftnew_io */
16237 7564,
16238 /* S4_pstorerftnew_rr */
16239 7568,
16240 /* S4_pstorerhf_abs */
16241 7573,
16242 /* S4_pstorerhf_rr */
16243 7576,
16244 /* S4_pstorerhfnew_abs */
16245 7581,
16246 /* S4_pstorerhfnew_io */
16247 7584,
16248 /* S4_pstorerhfnew_rr */
16249 7588,
16250 /* S4_pstorerhnewf_abs */
16251 7593,
16252 /* S4_pstorerhnewf_rr */
16253 7596,
16254 /* S4_pstorerhnewfnew_abs */
16255 7601,
16256 /* S4_pstorerhnewfnew_io */
16257 7604,
16258 /* S4_pstorerhnewfnew_rr */
16259 7608,
16260 /* S4_pstorerhnewt_abs */
16261 7613,
16262 /* S4_pstorerhnewt_rr */
16263 7616,
16264 /* S4_pstorerhnewtnew_abs */
16265 7621,
16266 /* S4_pstorerhnewtnew_io */
16267 7624,
16268 /* S4_pstorerhnewtnew_rr */
16269 7628,
16270 /* S4_pstorerht_abs */
16271 7633,
16272 /* S4_pstorerht_rr */
16273 7636,
16274 /* S4_pstorerhtnew_abs */
16275 7641,
16276 /* S4_pstorerhtnew_io */
16277 7644,
16278 /* S4_pstorerhtnew_rr */
16279 7648,
16280 /* S4_pstorerif_abs */
16281 7653,
16282 /* S4_pstorerif_rr */
16283 7656,
16284 /* S4_pstorerifnew_abs */
16285 7661,
16286 /* S4_pstorerifnew_io */
16287 7664,
16288 /* S4_pstorerifnew_rr */
16289 7668,
16290 /* S4_pstorerinewf_abs */
16291 7673,
16292 /* S4_pstorerinewf_rr */
16293 7676,
16294 /* S4_pstorerinewfnew_abs */
16295 7681,
16296 /* S4_pstorerinewfnew_io */
16297 7684,
16298 /* S4_pstorerinewfnew_rr */
16299 7688,
16300 /* S4_pstorerinewt_abs */
16301 7693,
16302 /* S4_pstorerinewt_rr */
16303 7696,
16304 /* S4_pstorerinewtnew_abs */
16305 7701,
16306 /* S4_pstorerinewtnew_io */
16307 7704,
16308 /* S4_pstorerinewtnew_rr */
16309 7708,
16310 /* S4_pstorerit_abs */
16311 7713,
16312 /* S4_pstorerit_rr */
16313 7716,
16314 /* S4_pstoreritnew_abs */
16315 7721,
16316 /* S4_pstoreritnew_io */
16317 7724,
16318 /* S4_pstoreritnew_rr */
16319 7728,
16320 /* S4_stored_locked */
16321 7733,
16322 /* S4_stored_rl_at_vi */
16323 7736,
16324 /* S4_stored_rl_st_vi */
16325 7738,
16326 /* S4_storeirb_io */
16327 7740,
16328 /* S4_storeirbf_io */
16329 7743,
16330 /* S4_storeirbfnew_io */
16331 7747,
16332 /* S4_storeirbt_io */
16333 7751,
16334 /* S4_storeirbtnew_io */
16335 7755,
16336 /* S4_storeirh_io */
16337 7759,
16338 /* S4_storeirhf_io */
16339 7762,
16340 /* S4_storeirhfnew_io */
16341 7766,
16342 /* S4_storeirht_io */
16343 7770,
16344 /* S4_storeirhtnew_io */
16345 7774,
16346 /* S4_storeiri_io */
16347 7778,
16348 /* S4_storeirif_io */
16349 7781,
16350 /* S4_storeirifnew_io */
16351 7785,
16352 /* S4_storeirit_io */
16353 7789,
16354 /* S4_storeiritnew_io */
16355 7793,
16356 /* S4_storerb_ap */
16357 7797,
16358 /* S4_storerb_rr */
16359 7800,
16360 /* S4_storerb_ur */
16361 7804,
16362 /* S4_storerbnew_ap */
16363 7808,
16364 /* S4_storerbnew_rr */
16365 7811,
16366 /* S4_storerbnew_ur */
16367 7815,
16368 /* S4_storerd_ap */
16369 7819,
16370 /* S4_storerd_rr */
16371 7822,
16372 /* S4_storerd_ur */
16373 7826,
16374 /* S4_storerf_ap */
16375 7830,
16376 /* S4_storerf_rr */
16377 7833,
16378 /* S4_storerf_ur */
16379 7837,
16380 /* S4_storerh_ap */
16381 7841,
16382 /* S4_storerh_rr */
16383 7844,
16384 /* S4_storerh_ur */
16385 7848,
16386 /* S4_storerhnew_ap */
16387 7852,
16388 /* S4_storerhnew_rr */
16389 7855,
16390 /* S4_storerhnew_ur */
16391 7859,
16392 /* S4_storeri_ap */
16393 7863,
16394 /* S4_storeri_rr */
16395 7866,
16396 /* S4_storeri_ur */
16397 7870,
16398 /* S4_storerinew_ap */
16399 7874,
16400 /* S4_storerinew_rr */
16401 7877,
16402 /* S4_storerinew_ur */
16403 7881,
16404 /* S4_subaddi */
16405 7885,
16406 /* S4_subi_asl_ri */
16407 7889,
16408 /* S4_subi_lsr_ri */
16409 7893,
16410 /* S4_vrcrotate */
16411 7897,
16412 /* S4_vrcrotate_acc */
16413 7901,
16414 /* S4_vxaddsubh */
16415 7906,
16416 /* S4_vxaddsubhr */
16417 7909,
16418 /* S4_vxaddsubw */
16419 7912,
16420 /* S4_vxsubaddh */
16421 7915,
16422 /* S4_vxsubaddhr */
16423 7918,
16424 /* S4_vxsubaddw */
16425 7921,
16426 /* S5_asrhub_rnd_sat */
16427 7924,
16428 /* S5_asrhub_sat */
16429 7927,
16430 /* S5_popcountp */
16431 7930,
16432 /* S5_vasrhrnd */
16433 7932,
16434 /* S6_rol_i_p */
16435 7935,
16436 /* S6_rol_i_p_acc */
16437 7938,
16438 /* S6_rol_i_p_and */
16439 7942,
16440 /* S6_rol_i_p_nac */
16441 7946,
16442 /* S6_rol_i_p_or */
16443 7950,
16444 /* S6_rol_i_p_xacc */
16445 7954,
16446 /* S6_rol_i_r */
16447 7958,
16448 /* S6_rol_i_r_acc */
16449 7961,
16450 /* S6_rol_i_r_and */
16451 7965,
16452 /* S6_rol_i_r_nac */
16453 7969,
16454 /* S6_rol_i_r_or */
16455 7973,
16456 /* S6_rol_i_r_xacc */
16457 7977,
16458 /* S6_vsplatrbp */
16459 7981,
16460 /* S6_vtrunehb_ppp */
16461 7983,
16462 /* S6_vtrunohb_ppp */
16463 7986,
16464 /* SA1_addi */
16465 7989,
16466 /* SA1_addrx */
16467 7992,
16468 /* SA1_addsp */
16469 7995,
16470 /* SA1_and1 */
16471 7997,
16472 /* SA1_clrf */
16473 7999,
16474 /* SA1_clrfnew */
16475 8000,
16476 /* SA1_clrt */
16477 8001,
16478 /* SA1_clrtnew */
16479 8002,
16480 /* SA1_cmpeqi */
16481 8003,
16482 /* SA1_combine0i */
16483 8005,
16484 /* SA1_combine1i */
16485 8007,
16486 /* SA1_combine2i */
16487 8009,
16488 /* SA1_combine3i */
16489 8011,
16490 /* SA1_combinerz */
16491 8013,
16492 /* SA1_combinezr */
16493 8015,
16494 /* SA1_dec */
16495 8017,
16496 /* SA1_inc */
16497 8020,
16498 /* SA1_seti */
16499 8022,
16500 /* SA1_setin1 */
16501 8024,
16502 /* SA1_sxtb */
16503 8026,
16504 /* SA1_sxth */
16505 8028,
16506 /* SA1_tfr */
16507 8030,
16508 /* SA1_zxtb */
16509 8032,
16510 /* SA1_zxth */
16511 8034,
16512 /* SAVE_REGISTERS_CALL_V4 */
16513 8036,
16514 /* SAVE_REGISTERS_CALL_V4STK */
16515 8037,
16516 /* SAVE_REGISTERS_CALL_V4STK_EXT */
16517 8038,
16518 /* SAVE_REGISTERS_CALL_V4STK_EXT_PIC */
16519 8039,
16520 /* SAVE_REGISTERS_CALL_V4STK_PIC */
16521 8040,
16522 /* SAVE_REGISTERS_CALL_V4_EXT */
16523 8041,
16524 /* SAVE_REGISTERS_CALL_V4_EXT_PIC */
16525 8042,
16526 /* SAVE_REGISTERS_CALL_V4_PIC */
16527 8043,
16528 /* SL1_loadri_io */
16529 8044,
16530 /* SL1_loadrub_io */
16531 8047,
16532 /* SL2_deallocframe */
16533 8050,
16534 /* SL2_jumpr31 */
16535 8050,
16536 /* SL2_jumpr31_f */
16537 8050,
16538 /* SL2_jumpr31_fnew */
16539 8050,
16540 /* SL2_jumpr31_t */
16541 8050,
16542 /* SL2_jumpr31_tnew */
16543 8050,
16544 /* SL2_loadrb_io */
16545 8050,
16546 /* SL2_loadrd_sp */
16547 8053,
16548 /* SL2_loadrh_io */
16549 8055,
16550 /* SL2_loadri_sp */
16551 8058,
16552 /* SL2_loadruh_io */
16553 8060,
16554 /* SL2_return */
16555 8063,
16556 /* SL2_return_f */
16557 8063,
16558 /* SL2_return_fnew */
16559 8063,
16560 /* SL2_return_t */
16561 8063,
16562 /* SL2_return_tnew */
16563 8063,
16564 /* SS1_storeb_io */
16565 8063,
16566 /* SS1_storew_io */
16567 8066,
16568 /* SS2_allocframe */
16569 8069,
16570 /* SS2_storebi0 */
16571 8070,
16572 /* SS2_storebi1 */
16573 8072,
16574 /* SS2_stored_sp */
16575 8074,
16576 /* SS2_storeh_io */
16577 8076,
16578 /* SS2_storew_sp */
16579 8079,
16580 /* SS2_storewi0 */
16581 8081,
16582 /* SS2_storewi1 */
16583 8083,
16584 /* TFRI64_V2_ext */
16585 8085,
16586 /* TFRI64_V4 */
16587 8088,
16588 /* V6_extractw */
16589 8090,
16590 /* V6_lvsplatb */
16591 8093,
16592 /* V6_lvsplath */
16593 8095,
16594 /* V6_lvsplatw */
16595 8097,
16596 /* V6_pred_and */
16597 8099,
16598 /* V6_pred_and_n */
16599 8102,
16600 /* V6_pred_not */
16601 8105,
16602 /* V6_pred_or */
16603 8107,
16604 /* V6_pred_or_n */
16605 8110,
16606 /* V6_pred_scalar2 */
16607 8113,
16608 /* V6_pred_scalar2v2 */
16609 8115,
16610 /* V6_pred_xor */
16611 8117,
16612 /* V6_shuffeqh */
16613 8120,
16614 /* V6_shuffeqw */
16615 8123,
16616 /* V6_v6mpyhubs10 */
16617 8126,
16618 /* V6_v6mpyhubs10_vxx */
16619 8130,
16620 /* V6_v6mpyvubs10 */
16621 8135,
16622 /* V6_v6mpyvubs10_vxx */
16623 8139,
16624 /* V6_vL32Ub_ai */
16625 8144,
16626 /* V6_vL32Ub_pi */
16627 8147,
16628 /* V6_vL32Ub_ppu */
16629 8151,
16630 /* V6_vL32b_ai */
16631 8155,
16632 /* V6_vL32b_cur_ai */
16633 8158,
16634 /* V6_vL32b_cur_npred_ai */
16635 8161,
16636 /* V6_vL32b_cur_npred_pi */
16637 8165,
16638 /* V6_vL32b_cur_npred_ppu */
16639 8170,
16640 /* V6_vL32b_cur_pi */
16641 8175,
16642 /* V6_vL32b_cur_ppu */
16643 8179,
16644 /* V6_vL32b_cur_pred_ai */
16645 8183,
16646 /* V6_vL32b_cur_pred_pi */
16647 8187,
16648 /* V6_vL32b_cur_pred_ppu */
16649 8192,
16650 /* V6_vL32b_npred_ai */
16651 8197,
16652 /* V6_vL32b_npred_pi */
16653 8201,
16654 /* V6_vL32b_npred_ppu */
16655 8206,
16656 /* V6_vL32b_nt_ai */
16657 8211,
16658 /* V6_vL32b_nt_cur_ai */
16659 8214,
16660 /* V6_vL32b_nt_cur_npred_ai */
16661 8217,
16662 /* V6_vL32b_nt_cur_npred_pi */
16663 8221,
16664 /* V6_vL32b_nt_cur_npred_ppu */
16665 8226,
16666 /* V6_vL32b_nt_cur_pi */
16667 8231,
16668 /* V6_vL32b_nt_cur_ppu */
16669 8235,
16670 /* V6_vL32b_nt_cur_pred_ai */
16671 8239,
16672 /* V6_vL32b_nt_cur_pred_pi */
16673 8243,
16674 /* V6_vL32b_nt_cur_pred_ppu */
16675 8248,
16676 /* V6_vL32b_nt_npred_ai */
16677 8253,
16678 /* V6_vL32b_nt_npred_pi */
16679 8257,
16680 /* V6_vL32b_nt_npred_ppu */
16681 8262,
16682 /* V6_vL32b_nt_pi */
16683 8267,
16684 /* V6_vL32b_nt_ppu */
16685 8271,
16686 /* V6_vL32b_nt_pred_ai */
16687 8275,
16688 /* V6_vL32b_nt_pred_pi */
16689 8279,
16690 /* V6_vL32b_nt_pred_ppu */
16691 8284,
16692 /* V6_vL32b_nt_tmp_ai */
16693 8289,
16694 /* V6_vL32b_nt_tmp_npred_ai */
16695 8292,
16696 /* V6_vL32b_nt_tmp_npred_pi */
16697 8296,
16698 /* V6_vL32b_nt_tmp_npred_ppu */
16699 8301,
16700 /* V6_vL32b_nt_tmp_pi */
16701 8306,
16702 /* V6_vL32b_nt_tmp_ppu */
16703 8310,
16704 /* V6_vL32b_nt_tmp_pred_ai */
16705 8314,
16706 /* V6_vL32b_nt_tmp_pred_pi */
16707 8318,
16708 /* V6_vL32b_nt_tmp_pred_ppu */
16709 8323,
16710 /* V6_vL32b_pi */
16711 8328,
16712 /* V6_vL32b_ppu */
16713 8332,
16714 /* V6_vL32b_pred_ai */
16715 8336,
16716 /* V6_vL32b_pred_pi */
16717 8340,
16718 /* V6_vL32b_pred_ppu */
16719 8345,
16720 /* V6_vL32b_tmp_ai */
16721 8350,
16722 /* V6_vL32b_tmp_npred_ai */
16723 8353,
16724 /* V6_vL32b_tmp_npred_pi */
16725 8357,
16726 /* V6_vL32b_tmp_npred_ppu */
16727 8362,
16728 /* V6_vL32b_tmp_pi */
16729 8367,
16730 /* V6_vL32b_tmp_ppu */
16731 8371,
16732 /* V6_vL32b_tmp_pred_ai */
16733 8375,
16734 /* V6_vL32b_tmp_pred_pi */
16735 8379,
16736 /* V6_vL32b_tmp_pred_ppu */
16737 8384,
16738 /* V6_vS32Ub_ai */
16739 8389,
16740 /* V6_vS32Ub_npred_ai */
16741 8392,
16742 /* V6_vS32Ub_npred_pi */
16743 8396,
16744 /* V6_vS32Ub_npred_ppu */
16745 8401,
16746 /* V6_vS32Ub_pi */
16747 8406,
16748 /* V6_vS32Ub_ppu */
16749 8410,
16750 /* V6_vS32Ub_pred_ai */
16751 8414,
16752 /* V6_vS32Ub_pred_pi */
16753 8418,
16754 /* V6_vS32Ub_pred_ppu */
16755 8423,
16756 /* V6_vS32b_ai */
16757 8428,
16758 /* V6_vS32b_new_ai */
16759 8431,
16760 /* V6_vS32b_new_npred_ai */
16761 8434,
16762 /* V6_vS32b_new_npred_pi */
16763 8438,
16764 /* V6_vS32b_new_npred_ppu */
16765 8443,
16766 /* V6_vS32b_new_pi */
16767 8448,
16768 /* V6_vS32b_new_ppu */
16769 8452,
16770 /* V6_vS32b_new_pred_ai */
16771 8456,
16772 /* V6_vS32b_new_pred_pi */
16773 8460,
16774 /* V6_vS32b_new_pred_ppu */
16775 8465,
16776 /* V6_vS32b_npred_ai */
16777 8470,
16778 /* V6_vS32b_npred_pi */
16779 8474,
16780 /* V6_vS32b_npred_ppu */
16781 8479,
16782 /* V6_vS32b_nqpred_ai */
16783 8484,
16784 /* V6_vS32b_nqpred_pi */
16785 8488,
16786 /* V6_vS32b_nqpred_ppu */
16787 8493,
16788 /* V6_vS32b_nt_ai */
16789 8498,
16790 /* V6_vS32b_nt_new_ai */
16791 8501,
16792 /* V6_vS32b_nt_new_npred_ai */
16793 8504,
16794 /* V6_vS32b_nt_new_npred_pi */
16795 8508,
16796 /* V6_vS32b_nt_new_npred_ppu */
16797 8513,
16798 /* V6_vS32b_nt_new_pi */
16799 8518,
16800 /* V6_vS32b_nt_new_ppu */
16801 8522,
16802 /* V6_vS32b_nt_new_pred_ai */
16803 8526,
16804 /* V6_vS32b_nt_new_pred_pi */
16805 8530,
16806 /* V6_vS32b_nt_new_pred_ppu */
16807 8535,
16808 /* V6_vS32b_nt_npred_ai */
16809 8540,
16810 /* V6_vS32b_nt_npred_pi */
16811 8544,
16812 /* V6_vS32b_nt_npred_ppu */
16813 8549,
16814 /* V6_vS32b_nt_nqpred_ai */
16815 8554,
16816 /* V6_vS32b_nt_nqpred_pi */
16817 8558,
16818 /* V6_vS32b_nt_nqpred_ppu */
16819 8563,
16820 /* V6_vS32b_nt_pi */
16821 8568,
16822 /* V6_vS32b_nt_ppu */
16823 8572,
16824 /* V6_vS32b_nt_pred_ai */
16825 8576,
16826 /* V6_vS32b_nt_pred_pi */
16827 8580,
16828 /* V6_vS32b_nt_pred_ppu */
16829 8585,
16830 /* V6_vS32b_nt_qpred_ai */
16831 8590,
16832 /* V6_vS32b_nt_qpred_pi */
16833 8594,
16834 /* V6_vS32b_nt_qpred_ppu */
16835 8599,
16836 /* V6_vS32b_pi */
16837 8604,
16838 /* V6_vS32b_ppu */
16839 8608,
16840 /* V6_vS32b_pred_ai */
16841 8612,
16842 /* V6_vS32b_pred_pi */
16843 8616,
16844 /* V6_vS32b_pred_ppu */
16845 8621,
16846 /* V6_vS32b_qpred_ai */
16847 8626,
16848 /* V6_vS32b_qpred_pi */
16849 8630,
16850 /* V6_vS32b_qpred_ppu */
16851 8635,
16852 /* V6_vS32b_srls_ai */
16853 8640,
16854 /* V6_vS32b_srls_pi */
16855 8642,
16856 /* V6_vS32b_srls_ppu */
16857 8645,
16858 /* V6_vabs_hf */
16859 8648,
16860 /* V6_vabs_sf */
16861 8650,
16862 /* V6_vabsb */
16863 8652,
16864 /* V6_vabsb_sat */
16865 8654,
16866 /* V6_vabsdiffh */
16867 8656,
16868 /* V6_vabsdiffub */
16869 8659,
16870 /* V6_vabsdiffuh */
16871 8662,
16872 /* V6_vabsdiffw */
16873 8665,
16874 /* V6_vabsh */
16875 8668,
16876 /* V6_vabsh_sat */
16877 8670,
16878 /* V6_vabsw */
16879 8672,
16880 /* V6_vabsw_sat */
16881 8674,
16882 /* V6_vadd_hf */
16883 8676,
16884 /* V6_vadd_hf_hf */
16885 8679,
16886 /* V6_vadd_qf16 */
16887 8682,
16888 /* V6_vadd_qf16_mix */
16889 8685,
16890 /* V6_vadd_qf32 */
16891 8688,
16892 /* V6_vadd_qf32_mix */
16893 8691,
16894 /* V6_vadd_sf */
16895 8694,
16896 /* V6_vadd_sf_bf */
16897 8697,
16898 /* V6_vadd_sf_hf */
16899 8700,
16900 /* V6_vadd_sf_sf */
16901 8703,
16902 /* V6_vaddb */
16903 8706,
16904 /* V6_vaddb_dv */
16905 8709,
16906 /* V6_vaddbnq */
16907 8712,
16908 /* V6_vaddbq */
16909 8716,
16910 /* V6_vaddbsat */
16911 8720,
16912 /* V6_vaddbsat_dv */
16913 8723,
16914 /* V6_vaddcarry */
16915 8726,
16916 /* V6_vaddcarryo */
16917 8731,
16918 /* V6_vaddcarrysat */
16919 8735,
16920 /* V6_vaddclbh */
16921 8739,
16922 /* V6_vaddclbw */
16923 8742,
16924 /* V6_vaddh */
16925 8745,
16926 /* V6_vaddh_dv */
16927 8748,
16928 /* V6_vaddhnq */
16929 8751,
16930 /* V6_vaddhq */
16931 8755,
16932 /* V6_vaddhsat */
16933 8759,
16934 /* V6_vaddhsat_dv */
16935 8762,
16936 /* V6_vaddhw */
16937 8765,
16938 /* V6_vaddhw_acc */
16939 8768,
16940 /* V6_vaddubh */
16941 8772,
16942 /* V6_vaddubh_acc */
16943 8775,
16944 /* V6_vaddubsat */
16945 8779,
16946 /* V6_vaddubsat_dv */
16947 8782,
16948 /* V6_vaddububb_sat */
16949 8785,
16950 /* V6_vadduhsat */
16951 8788,
16952 /* V6_vadduhsat_dv */
16953 8791,
16954 /* V6_vadduhw */
16955 8794,
16956 /* V6_vadduhw_acc */
16957 8797,
16958 /* V6_vadduwsat */
16959 8801,
16960 /* V6_vadduwsat_dv */
16961 8804,
16962 /* V6_vaddw */
16963 8807,
16964 /* V6_vaddw_dv */
16965 8810,
16966 /* V6_vaddwnq */
16967 8813,
16968 /* V6_vaddwq */
16969 8817,
16970 /* V6_vaddwsat */
16971 8821,
16972 /* V6_vaddwsat_dv */
16973 8824,
16974 /* V6_valignb */
16975 8827,
16976 /* V6_valignbi */
16977 8831,
16978 /* V6_vand */
16979 8835,
16980 /* V6_vandnqrt */
16981 8838,
16982 /* V6_vandnqrt_acc */
16983 8841,
16984 /* V6_vandqrt */
16985 8845,
16986 /* V6_vandqrt_acc */
16987 8848,
16988 /* V6_vandvnqv */
16989 8852,
16990 /* V6_vandvqv */
16991 8855,
16992 /* V6_vandvrt */
16993 8858,
16994 /* V6_vandvrt_acc */
16995 8861,
16996 /* V6_vaslh */
16997 8865,
16998 /* V6_vaslh_acc */
16999 8868,
17000 /* V6_vaslhv */
17001 8872,
17002 /* V6_vaslw */
17003 8875,
17004 /* V6_vaslw_acc */
17005 8878,
17006 /* V6_vaslwv */
17007 8882,
17008 /* V6_vasr_into */
17009 8885,
17010 /* V6_vasrh */
17011 8889,
17012 /* V6_vasrh_acc */
17013 8892,
17014 /* V6_vasrhbrndsat */
17015 8896,
17016 /* V6_vasrhbsat */
17017 8900,
17018 /* V6_vasrhubrndsat */
17019 8904,
17020 /* V6_vasrhubsat */
17021 8908,
17022 /* V6_vasrhv */
17023 8912,
17024 /* V6_vasruhubrndsat */
17025 8915,
17026 /* V6_vasruhubsat */
17027 8919,
17028 /* V6_vasruwuhrndsat */
17029 8923,
17030 /* V6_vasruwuhsat */
17031 8927,
17032 /* V6_vasrvuhubrndsat */
17033 8931,
17034 /* V6_vasrvuhubsat */
17035 8934,
17036 /* V6_vasrvwuhrndsat */
17037 8937,
17038 /* V6_vasrvwuhsat */
17039 8940,
17040 /* V6_vasrw */
17041 8943,
17042 /* V6_vasrw_acc */
17043 8946,
17044 /* V6_vasrwh */
17045 8950,
17046 /* V6_vasrwhrndsat */
17047 8954,
17048 /* V6_vasrwhsat */
17049 8958,
17050 /* V6_vasrwuhrndsat */
17051 8962,
17052 /* V6_vasrwuhsat */
17053 8966,
17054 /* V6_vasrwv */
17055 8970,
17056 /* V6_vassign */
17057 8973,
17058 /* V6_vassign_fp */
17059 8975,
17060 /* V6_vassign_tmp */
17061 8977,
17062 /* V6_vavgb */
17063 8979,
17064 /* V6_vavgbrnd */
17065 8982,
17066 /* V6_vavgh */
17067 8985,
17068 /* V6_vavghrnd */
17069 8988,
17070 /* V6_vavgub */
17071 8991,
17072 /* V6_vavgubrnd */
17073 8994,
17074 /* V6_vavguh */
17075 8997,
17076 /* V6_vavguhrnd */
17077 9000,
17078 /* V6_vavguw */
17079 9003,
17080 /* V6_vavguwrnd */
17081 9006,
17082 /* V6_vavgw */
17083 9009,
17084 /* V6_vavgwrnd */
17085 9012,
17086 /* V6_vccombine */
17087 9015,
17088 /* V6_vcl0h */
17089 9019,
17090 /* V6_vcl0w */
17091 9021,
17092 /* V6_vcmov */
17093 9023,
17094 /* V6_vcombine */
17095 9026,
17096 /* V6_vcombine_tmp */
17097 9029,
17098 /* V6_vconv_h_hf */
17099 9032,
17100 /* V6_vconv_hf_h */
17101 9034,
17102 /* V6_vconv_hf_qf16 */
17103 9036,
17104 /* V6_vconv_hf_qf32 */
17105 9038,
17106 /* V6_vconv_sf_qf32 */
17107 9040,
17108 /* V6_vconv_sf_w */
17109 9042,
17110 /* V6_vconv_w_sf */
17111 9044,
17112 /* V6_vcvt_b_hf */
17113 9046,
17114 /* V6_vcvt_bf_sf */
17115 9049,
17116 /* V6_vcvt_h_hf */
17117 9052,
17118 /* V6_vcvt_hf_b */
17119 9054,
17120 /* V6_vcvt_hf_h */
17121 9056,
17122 /* V6_vcvt_hf_sf */
17123 9058,
17124 /* V6_vcvt_hf_ub */
17125 9061,
17126 /* V6_vcvt_hf_uh */
17127 9063,
17128 /* V6_vcvt_sf_hf */
17129 9065,
17130 /* V6_vcvt_ub_hf */
17131 9067,
17132 /* V6_vcvt_uh_hf */
17133 9070,
17134 /* V6_vdeal */
17135 9072,
17136 /* V6_vdealb */
17137 9077,
17138 /* V6_vdealb4w */
17139 9079,
17140 /* V6_vdealh */
17141 9082,
17142 /* V6_vdealvdd */
17143 9084,
17144 /* V6_vdelta */
17145 9088,
17146 /* V6_vdmpy_sf_hf */
17147 9091,
17148 /* V6_vdmpy_sf_hf_acc */
17149 9094,
17150 /* V6_vdmpybus */
17151 9098,
17152 /* V6_vdmpybus_acc */
17153 9101,
17154 /* V6_vdmpybus_dv */
17155 9105,
17156 /* V6_vdmpybus_dv_acc */
17157 9108,
17158 /* V6_vdmpyhb */
17159 9112,
17160 /* V6_vdmpyhb_acc */
17161 9115,
17162 /* V6_vdmpyhb_dv */
17163 9119,
17164 /* V6_vdmpyhb_dv_acc */
17165 9122,
17166 /* V6_vdmpyhisat */
17167 9126,
17168 /* V6_vdmpyhisat_acc */
17169 9129,
17170 /* V6_vdmpyhsat */
17171 9133,
17172 /* V6_vdmpyhsat_acc */
17173 9136,
17174 /* V6_vdmpyhsuisat */
17175 9140,
17176 /* V6_vdmpyhsuisat_acc */
17177 9143,
17178 /* V6_vdmpyhsusat */
17179 9147,
17180 /* V6_vdmpyhsusat_acc */
17181 9150,
17182 /* V6_vdmpyhvsat */
17183 9154,
17184 /* V6_vdmpyhvsat_acc */
17185 9157,
17186 /* V6_vdsaduh */
17187 9161,
17188 /* V6_vdsaduh_acc */
17189 9164,
17190 /* V6_veqb */
17191 9168,
17192 /* V6_veqb_and */
17193 9171,
17194 /* V6_veqb_or */
17195 9175,
17196 /* V6_veqb_xor */
17197 9179,
17198 /* V6_veqh */
17199 9183,
17200 /* V6_veqh_and */
17201 9186,
17202 /* V6_veqh_or */
17203 9190,
17204 /* V6_veqh_xor */
17205 9194,
17206 /* V6_veqw */
17207 9198,
17208 /* V6_veqw_and */
17209 9201,
17210 /* V6_veqw_or */
17211 9205,
17212 /* V6_veqw_xor */
17213 9209,
17214 /* V6_vfmax_hf */
17215 9213,
17216 /* V6_vfmax_sf */
17217 9216,
17218 /* V6_vfmin_hf */
17219 9219,
17220 /* V6_vfmin_sf */
17221 9222,
17222 /* V6_vfneg_hf */
17223 9225,
17224 /* V6_vfneg_sf */
17225 9227,
17226 /* V6_vgathermh */
17227 9229,
17228 /* V6_vgathermhq */
17229 9232,
17230 /* V6_vgathermhw */
17231 9236,
17232 /* V6_vgathermhwq */
17233 9239,
17234 /* V6_vgathermw */
17235 9243,
17236 /* V6_vgathermwq */
17237 9246,
17238 /* V6_vgtb */
17239 9250,
17240 /* V6_vgtb_and */
17241 9253,
17242 /* V6_vgtb_or */
17243 9257,
17244 /* V6_vgtb_xor */
17245 9261,
17246 /* V6_vgtbf */
17247 9265,
17248 /* V6_vgtbf_and */
17249 9268,
17250 /* V6_vgtbf_or */
17251 9272,
17252 /* V6_vgtbf_xor */
17253 9276,
17254 /* V6_vgth */
17255 9280,
17256 /* V6_vgth_and */
17257 9283,
17258 /* V6_vgth_or */
17259 9287,
17260 /* V6_vgth_xor */
17261 9291,
17262 /* V6_vgthf */
17263 9295,
17264 /* V6_vgthf_and */
17265 9298,
17266 /* V6_vgthf_or */
17267 9302,
17268 /* V6_vgthf_xor */
17269 9306,
17270 /* V6_vgtsf */
17271 9310,
17272 /* V6_vgtsf_and */
17273 9313,
17274 /* V6_vgtsf_or */
17275 9317,
17276 /* V6_vgtsf_xor */
17277 9321,
17278 /* V6_vgtub */
17279 9325,
17280 /* V6_vgtub_and */
17281 9328,
17282 /* V6_vgtub_or */
17283 9332,
17284 /* V6_vgtub_xor */
17285 9336,
17286 /* V6_vgtuh */
17287 9340,
17288 /* V6_vgtuh_and */
17289 9343,
17290 /* V6_vgtuh_or */
17291 9347,
17292 /* V6_vgtuh_xor */
17293 9351,
17294 /* V6_vgtuw */
17295 9355,
17296 /* V6_vgtuw_and */
17297 9358,
17298 /* V6_vgtuw_or */
17299 9362,
17300 /* V6_vgtuw_xor */
17301 9366,
17302 /* V6_vgtw */
17303 9370,
17304 /* V6_vgtw_and */
17305 9373,
17306 /* V6_vgtw_or */
17307 9377,
17308 /* V6_vgtw_xor */
17309 9381,
17310 /* V6_vhist */
17311 9385,
17312 /* V6_vhistq */
17313 9385,
17314 /* V6_vinsertwr */
17315 9386,
17316 /* V6_vlalignb */
17317 9389,
17318 /* V6_vlalignbi */
17319 9393,
17320 /* V6_vlsrb */
17321 9397,
17322 /* V6_vlsrh */
17323 9400,
17324 /* V6_vlsrhv */
17325 9403,
17326 /* V6_vlsrw */
17327 9406,
17328 /* V6_vlsrwv */
17329 9409,
17330 /* V6_vlut4 */
17331 9412,
17332 /* V6_vlutvvb */
17333 9415,
17334 /* V6_vlutvvb_nm */
17335 9419,
17336 /* V6_vlutvvb_oracc */
17337 9423,
17338 /* V6_vlutvvb_oracci */
17339 9428,
17340 /* V6_vlutvvbi */
17341 9433,
17342 /* V6_vlutvwh */
17343 9437,
17344 /* V6_vlutvwh_nm */
17345 9441,
17346 /* V6_vlutvwh_oracc */
17347 9445,
17348 /* V6_vlutvwh_oracci */
17349 9450,
17350 /* V6_vlutvwhi */
17351 9455,
17352 /* V6_vmax_bf */
17353 9459,
17354 /* V6_vmax_hf */
17355 9462,
17356 /* V6_vmax_sf */
17357 9465,
17358 /* V6_vmaxb */
17359 9468,
17360 /* V6_vmaxh */
17361 9471,
17362 /* V6_vmaxub */
17363 9474,
17364 /* V6_vmaxuh */
17365 9477,
17366 /* V6_vmaxw */
17367 9480,
17368 /* V6_vmin_bf */
17369 9483,
17370 /* V6_vmin_hf */
17371 9486,
17372 /* V6_vmin_sf */
17373 9489,
17374 /* V6_vminb */
17375 9492,
17376 /* V6_vminh */
17377 9495,
17378 /* V6_vminub */
17379 9498,
17380 /* V6_vminuh */
17381 9501,
17382 /* V6_vminw */
17383 9504,
17384 /* V6_vmpabus */
17385 9507,
17386 /* V6_vmpabus_acc */
17387 9510,
17388 /* V6_vmpabusv */
17389 9514,
17390 /* V6_vmpabuu */
17391 9517,
17392 /* V6_vmpabuu_acc */
17393 9520,
17394 /* V6_vmpabuuv */
17395 9524,
17396 /* V6_vmpahb */
17397 9527,
17398 /* V6_vmpahb_acc */
17399 9530,
17400 /* V6_vmpahhsat */
17401 9534,
17402 /* V6_vmpauhb */
17403 9538,
17404 /* V6_vmpauhb_acc */
17405 9541,
17406 /* V6_vmpauhuhsat */
17407 9545,
17408 /* V6_vmpsuhuhsat */
17409 9549,
17410 /* V6_vmpy_hf_hf */
17411 9553,
17412 /* V6_vmpy_hf_hf_acc */
17413 9556,
17414 /* V6_vmpy_qf16 */
17415 9560,
17416 /* V6_vmpy_qf16_hf */
17417 9563,
17418 /* V6_vmpy_qf16_mix_hf */
17419 9566,
17420 /* V6_vmpy_qf32 */
17421 9569,
17422 /* V6_vmpy_qf32_hf */
17423 9572,
17424 /* V6_vmpy_qf32_mix_hf */
17425 9575,
17426 /* V6_vmpy_qf32_qf16 */
17427 9578,
17428 /* V6_vmpy_qf32_sf */
17429 9581,
17430 /* V6_vmpy_sf_bf */
17431 9584,
17432 /* V6_vmpy_sf_bf_acc */
17433 9587,
17434 /* V6_vmpy_sf_hf */
17435 9591,
17436 /* V6_vmpy_sf_hf_acc */
17437 9594,
17438 /* V6_vmpy_sf_sf */
17439 9598,
17440 /* V6_vmpybus */
17441 9601,
17442 /* V6_vmpybus_acc */
17443 9604,
17444 /* V6_vmpybusv */
17445 9608,
17446 /* V6_vmpybusv_acc */
17447 9611,
17448 /* V6_vmpybv */
17449 9615,
17450 /* V6_vmpybv_acc */
17451 9618,
17452 /* V6_vmpyewuh */
17453 9622,
17454 /* V6_vmpyewuh_64 */
17455 9625,
17456 /* V6_vmpyh */
17457 9628,
17458 /* V6_vmpyh_acc */
17459 9631,
17460 /* V6_vmpyhsat_acc */
17461 9635,
17462 /* V6_vmpyhsrs */
17463 9639,
17464 /* V6_vmpyhss */
17465 9642,
17466 /* V6_vmpyhus */
17467 9645,
17468 /* V6_vmpyhus_acc */
17469 9648,
17470 /* V6_vmpyhv */
17471 9652,
17472 /* V6_vmpyhv_acc */
17473 9655,
17474 /* V6_vmpyhvsrs */
17475 9659,
17476 /* V6_vmpyieoh */
17477 9662,
17478 /* V6_vmpyiewh_acc */
17479 9665,
17480 /* V6_vmpyiewuh */
17481 9669,
17482 /* V6_vmpyiewuh_acc */
17483 9672,
17484 /* V6_vmpyih */
17485 9676,
17486 /* V6_vmpyih_acc */
17487 9679,
17488 /* V6_vmpyihb */
17489 9683,
17490 /* V6_vmpyihb_acc */
17491 9686,
17492 /* V6_vmpyiowh */
17493 9690,
17494 /* V6_vmpyiwb */
17495 9693,
17496 /* V6_vmpyiwb_acc */
17497 9696,
17498 /* V6_vmpyiwh */
17499 9700,
17500 /* V6_vmpyiwh_acc */
17501 9703,
17502 /* V6_vmpyiwub */
17503 9707,
17504 /* V6_vmpyiwub_acc */
17505 9710,
17506 /* V6_vmpyowh */
17507 9714,
17508 /* V6_vmpyowh_64_acc */
17509 9717,
17510 /* V6_vmpyowh_rnd */
17511 9721,
17512 /* V6_vmpyowh_rnd_sacc */
17513 9724,
17514 /* V6_vmpyowh_sacc */
17515 9728,
17516 /* V6_vmpyub */
17517 9732,
17518 /* V6_vmpyub_acc */
17519 9735,
17520 /* V6_vmpyubv */
17521 9739,
17522 /* V6_vmpyubv_acc */
17523 9742,
17524 /* V6_vmpyuh */
17525 9746,
17526 /* V6_vmpyuh_acc */
17527 9749,
17528 /* V6_vmpyuhe */
17529 9753,
17530 /* V6_vmpyuhe_acc */
17531 9756,
17532 /* V6_vmpyuhv */
17533 9760,
17534 /* V6_vmpyuhv_acc */
17535 9763,
17536 /* V6_vmpyuhvs */
17537 9767,
17538 /* V6_vmux */
17539 9770,
17540 /* V6_vnavgb */
17541 9774,
17542 /* V6_vnavgh */
17543 9777,
17544 /* V6_vnavgub */
17545 9780,
17546 /* V6_vnavgw */
17547 9783,
17548 /* V6_vnccombine */
17549 9786,
17550 /* V6_vncmov */
17551 9790,
17552 /* V6_vnormamth */
17553 9793,
17554 /* V6_vnormamtw */
17555 9795,
17556 /* V6_vnot */
17557 9797,
17558 /* V6_vor */
17559 9799,
17560 /* V6_vpackeb */
17561 9802,
17562 /* V6_vpackeh */
17563 9805,
17564 /* V6_vpackhb_sat */
17565 9808,
17566 /* V6_vpackhub_sat */
17567 9811,
17568 /* V6_vpackob */
17569 9814,
17570 /* V6_vpackoh */
17571 9817,
17572 /* V6_vpackwh_sat */
17573 9820,
17574 /* V6_vpackwuh_sat */
17575 9823,
17576 /* V6_vpopcounth */
17577 9826,
17578 /* V6_vprefixqb */
17579 9828,
17580 /* V6_vprefixqh */
17581 9830,
17582 /* V6_vprefixqw */
17583 9832,
17584 /* V6_vrdelta */
17585 9834,
17586 /* V6_vrmpybub_rtt */
17587 9837,
17588 /* V6_vrmpybub_rtt_acc */
17589 9840,
17590 /* V6_vrmpybus */
17591 9844,
17592 /* V6_vrmpybus_acc */
17593 9847,
17594 /* V6_vrmpybusi */
17595 9851,
17596 /* V6_vrmpybusi_acc */
17597 9855,
17598 /* V6_vrmpybusv */
17599 9860,
17600 /* V6_vrmpybusv_acc */
17601 9863,
17602 /* V6_vrmpybv */
17603 9867,
17604 /* V6_vrmpybv_acc */
17605 9870,
17606 /* V6_vrmpyub */
17607 9874,
17608 /* V6_vrmpyub_acc */
17609 9877,
17610 /* V6_vrmpyub_rtt */
17611 9881,
17612 /* V6_vrmpyub_rtt_acc */
17613 9884,
17614 /* V6_vrmpyubi */
17615 9888,
17616 /* V6_vrmpyubi_acc */
17617 9892,
17618 /* V6_vrmpyubv */
17619 9897,
17620 /* V6_vrmpyubv_acc */
17621 9900,
17622 /* V6_vrmpyzbb_rt */
17623 9904,
17624 /* V6_vrmpyzbb_rt_acc */
17625 9907,
17626 /* V6_vrmpyzbb_rx */
17627 9911,
17628 /* V6_vrmpyzbb_rx_acc */
17629 9915,
17630 /* V6_vrmpyzbub_rt */
17631 9920,
17632 /* V6_vrmpyzbub_rt_acc */
17633 9923,
17634 /* V6_vrmpyzbub_rx */
17635 9927,
17636 /* V6_vrmpyzbub_rx_acc */
17637 9931,
17638 /* V6_vrmpyzcb_rt */
17639 9936,
17640 /* V6_vrmpyzcb_rt_acc */
17641 9939,
17642 /* V6_vrmpyzcb_rx */
17643 9943,
17644 /* V6_vrmpyzcb_rx_acc */
17645 9947,
17646 /* V6_vrmpyzcbs_rt */
17647 9952,
17648 /* V6_vrmpyzcbs_rt_acc */
17649 9955,
17650 /* V6_vrmpyzcbs_rx */
17651 9959,
17652 /* V6_vrmpyzcbs_rx_acc */
17653 9963,
17654 /* V6_vrmpyznb_rt */
17655 9968,
17656 /* V6_vrmpyznb_rt_acc */
17657 9971,
17658 /* V6_vrmpyznb_rx */
17659 9975,
17660 /* V6_vrmpyznb_rx_acc */
17661 9979,
17662 /* V6_vror */
17663 9984,
17664 /* V6_vrotr */
17665 9987,
17666 /* V6_vroundhb */
17667 9990,
17668 /* V6_vroundhub */
17669 9993,
17670 /* V6_vrounduhub */
17671 9996,
17672 /* V6_vrounduwuh */
17673 9999,
17674 /* V6_vroundwh */
17675 10002,
17676 /* V6_vroundwuh */
17677 10005,
17678 /* V6_vrsadubi */
17679 10008,
17680 /* V6_vrsadubi_acc */
17681 10012,
17682 /* V6_vsatdw */
17683 10017,
17684 /* V6_vsathub */
17685 10020,
17686 /* V6_vsatuwuh */
17687 10023,
17688 /* V6_vsatwh */
17689 10026,
17690 /* V6_vsb */
17691 10029,
17692 /* V6_vscattermh */
17693 10031,
17694 /* V6_vscattermh_add */
17695 10035,
17696 /* V6_vscattermhq */
17697 10039,
17698 /* V6_vscattermhw */
17699 10044,
17700 /* V6_vscattermhw_add */
17701 10048,
17702 /* V6_vscattermhwq */
17703 10052,
17704 /* V6_vscattermw */
17705 10057,
17706 /* V6_vscattermw_add */
17707 10061,
17708 /* V6_vscattermwq */
17709 10065,
17710 /* V6_vsh */
17711 10070,
17712 /* V6_vshufeh */
17713 10072,
17714 /* V6_vshuff */
17715 10075,
17716 /* V6_vshuffb */
17717 10080,
17718 /* V6_vshuffeb */
17719 10082,
17720 /* V6_vshuffh */
17721 10085,
17722 /* V6_vshuffob */
17723 10087,
17724 /* V6_vshuffvdd */
17725 10090,
17726 /* V6_vshufoeb */
17727 10094,
17728 /* V6_vshufoeh */
17729 10097,
17730 /* V6_vshufoh */
17731 10100,
17732 /* V6_vsub_hf */
17733 10103,
17734 /* V6_vsub_hf_hf */
17735 10106,
17736 /* V6_vsub_qf16 */
17737 10109,
17738 /* V6_vsub_qf16_mix */
17739 10112,
17740 /* V6_vsub_qf32 */
17741 10115,
17742 /* V6_vsub_qf32_mix */
17743 10118,
17744 /* V6_vsub_sf */
17745 10121,
17746 /* V6_vsub_sf_bf */
17747 10124,
17748 /* V6_vsub_sf_hf */
17749 10127,
17750 /* V6_vsub_sf_sf */
17751 10130,
17752 /* V6_vsubb */
17753 10133,
17754 /* V6_vsubb_dv */
17755 10136,
17756 /* V6_vsubbnq */
17757 10139,
17758 /* V6_vsubbq */
17759 10143,
17760 /* V6_vsubbsat */
17761 10147,
17762 /* V6_vsubbsat_dv */
17763 10150,
17764 /* V6_vsubcarry */
17765 10153,
17766 /* V6_vsubcarryo */
17767 10158,
17768 /* V6_vsubh */
17769 10162,
17770 /* V6_vsubh_dv */
17771 10165,
17772 /* V6_vsubhnq */
17773 10168,
17774 /* V6_vsubhq */
17775 10172,
17776 /* V6_vsubhsat */
17777 10176,
17778 /* V6_vsubhsat_dv */
17779 10179,
17780 /* V6_vsubhw */
17781 10182,
17782 /* V6_vsububh */
17783 10185,
17784 /* V6_vsububsat */
17785 10188,
17786 /* V6_vsububsat_dv */
17787 10191,
17788 /* V6_vsubububb_sat */
17789 10194,
17790 /* V6_vsubuhsat */
17791 10197,
17792 /* V6_vsubuhsat_dv */
17793 10200,
17794 /* V6_vsubuhw */
17795 10203,
17796 /* V6_vsubuwsat */
17797 10206,
17798 /* V6_vsubuwsat_dv */
17799 10209,
17800 /* V6_vsubw */
17801 10212,
17802 /* V6_vsubw_dv */
17803 10215,
17804 /* V6_vsubwnq */
17805 10218,
17806 /* V6_vsubwq */
17807 10222,
17808 /* V6_vsubwsat */
17809 10226,
17810 /* V6_vsubwsat_dv */
17811 10229,
17812 /* V6_vswap */
17813 10232,
17814 /* V6_vtmpyb */
17815 10236,
17816 /* V6_vtmpyb_acc */
17817 10239,
17818 /* V6_vtmpybus */
17819 10243,
17820 /* V6_vtmpybus_acc */
17821 10246,
17822 /* V6_vtmpyhb */
17823 10250,
17824 /* V6_vtmpyhb_acc */
17825 10253,
17826 /* V6_vunpackb */
17827 10257,
17828 /* V6_vunpackh */
17829 10259,
17830 /* V6_vunpackob */
17831 10261,
17832 /* V6_vunpackoh */
17833 10264,
17834 /* V6_vunpackub */
17835 10267,
17836 /* V6_vunpackuh */
17837 10269,
17838 /* V6_vwhist128 */
17839 10271,
17840 /* V6_vwhist128m */
17841 10271,
17842 /* V6_vwhist128q */
17843 10272,
17844 /* V6_vwhist128qm */
17845 10273,
17846 /* V6_vwhist256 */
17847 10275,
17848 /* V6_vwhist256_sat */
17849 10275,
17850 /* V6_vwhist256q */
17851 10275,
17852 /* V6_vwhist256q_sat */
17853 10276,
17854 /* V6_vxor */
17855 10277,
17856 /* V6_vzb */
17857 10280,
17858 /* V6_vzh */
17859 10282,
17860 /* V6_zLd_ai */
17861 10284,
17862 /* V6_zLd_pi */
17863 10286,
17864 /* V6_zLd_ppu */
17865 10289,
17866 /* V6_zLd_pred_ai */
17867 10292,
17868 /* V6_zLd_pred_pi */
17869 10295,
17870 /* V6_zLd_pred_ppu */
17871 10299,
17872 /* V6_zextract */
17873 10303,
17874 /* Y2_barrier */
17875 10305,
17876 /* Y2_break */
17877 10305,
17878 /* Y2_ciad */
17879 10305,
17880 /* Y2_crswap0 */
17881 10306,
17882 /* Y2_cswi */
17883 10308,
17884 /* Y2_dccleana */
17885 10309,
17886 /* Y2_dccleanidx */
17887 10310,
17888 /* Y2_dccleaninva */
17889 10311,
17890 /* Y2_dccleaninvidx */
17891 10312,
17892 /* Y2_dcfetchbo */
17893 10313,
17894 /* Y2_dcinva */
17895 10315,
17896 /* Y2_dcinvidx */
17897 10316,
17898 /* Y2_dckill */
17899 10317,
17900 /* Y2_dctagr */
17901 10317,
17902 /* Y2_dctagw */
17903 10319,
17904 /* Y2_dczeroa */
17905 10321,
17906 /* Y2_getimask */
17907 10322,
17908 /* Y2_iassignr */
17909 10324,
17910 /* Y2_iassignw */
17911 10326,
17912 /* Y2_icdatar */
17913 10327,
17914 /* Y2_icdataw */
17915 10329,
17916 /* Y2_icinva */
17917 10331,
17918 /* Y2_icinvidx */
17919 10332,
17920 /* Y2_ickill */
17921 10333,
17922 /* Y2_ictagr */
17923 10333,
17924 /* Y2_ictagw */
17925 10335,
17926 /* Y2_isync */
17927 10337,
17928 /* Y2_k0lock */
17929 10337,
17930 /* Y2_k0unlock */
17931 10337,
17932 /* Y2_l2cleaninvidx */
17933 10337,
17934 /* Y2_l2kill */
17935 10338,
17936 /* Y2_resume */
17937 10338,
17938 /* Y2_setimask */
17939 10339,
17940 /* Y2_setprio */
17941 10341,
17942 /* Y2_start */
17943 10343,
17944 /* Y2_stop */
17945 10344,
17946 /* Y2_swi */
17947 10345,
17948 /* Y2_syncht */
17949 10346,
17950 /* Y2_tfrscrr */
17951 10346,
17952 /* Y2_tfrsrcr */
17953 10348,
17954 /* Y2_tlblock */
17955 10350,
17956 /* Y2_tlbp */
17957 10350,
17958 /* Y2_tlbr */
17959 10352,
17960 /* Y2_tlbunlock */
17961 10354,
17962 /* Y2_tlbw */
17963 10354,
17964 /* Y2_wait */
17965 10356,
17966 /* Y4_crswap1 */
17967 10357,
17968 /* Y4_crswap10 */
17969 10359,
17970 /* Y4_l2fetch */
17971 10362,
17972 /* Y4_l2tagr */
17973 10364,
17974 /* Y4_l2tagw */
17975 10366,
17976 /* Y4_nmi */
17977 10368,
17978 /* Y4_siad */
17979 10369,
17980 /* Y4_tfrscpp */
17981 10370,
17982 /* Y4_tfrspcp */
17983 10372,
17984 /* Y4_trace */
17985 10374,
17986 /* Y5_ctlbw */
17987 10375,
17988 /* Y5_l2cleanidx */
17989 10378,
17990 /* Y5_l2fetch */
17991 10379,
17992 /* Y5_l2gclean */
17993 10381,
17994 /* Y5_l2gcleaninv */
17995 10381,
17996 /* Y5_l2gunlock */
17997 10381,
17998 /* Y5_l2invidx */
17999 10381,
18000 /* Y5_l2locka */
18001 10382,
18002 /* Y5_l2unlocka */
18003 10384,
18004 /* Y5_tlbasidi */
18005 10385,
18006 /* Y5_tlboc */
18007 10386,
18008 /* Y6_diag */
18009 10388,
18010 /* Y6_diag0 */
18011 10389,
18012 /* Y6_diag1 */
18013 10391,
18014 /* Y6_dmlink */
18015 10393,
18016 /* Y6_dmpause */
18017 10395,
18018 /* Y6_dmpoll */
18019 10396,
18020 /* Y6_dmresume */
18021 10397,
18022 /* Y6_dmstart */
18023 10398,
18024 /* Y6_dmwait */
18025 10399,
18026 /* Y6_l2gcleaninvpa */
18027 10400,
18028 /* Y6_l2gcleanpa */
18029 10401,
18030 /* dep_A2_addsat */
18031 10402,
18032 /* dep_A2_subsat */
18033 10405,
18034 /* dep_S2_packhl */
18035 10408,
18036 /* invalid_decode */
18037 10411,
18038 };
18039
18040 using namespace OpTypes;
18041 static const int8_t OpcodeOperandTypes[] = {
18042
18043 /* PHI */
18044 -1,
18045 /* INLINEASM */
18046 /* INLINEASM_BR */
18047 /* CFI_INSTRUCTION */
18048 i32imm,
18049 /* EH_LABEL */
18050 i32imm,
18051 /* GC_LABEL */
18052 i32imm,
18053 /* ANNOTATION_LABEL */
18054 i32imm,
18055 /* KILL */
18056 /* EXTRACT_SUBREG */
18057 -1, -1, i32imm,
18058 /* INSERT_SUBREG */
18059 -1, -1, -1, i32imm,
18060 /* IMPLICIT_DEF */
18061 -1,
18062 /* SUBREG_TO_REG */
18063 -1, -1, -1, i32imm,
18064 /* COPY_TO_REGCLASS */
18065 -1, -1, i32imm,
18066 /* DBG_VALUE */
18067 /* DBG_VALUE_LIST */
18068 /* DBG_INSTR_REF */
18069 /* DBG_PHI */
18070 /* DBG_LABEL */
18071 -1,
18072 /* REG_SEQUENCE */
18073 -1, -1,
18074 /* COPY */
18075 -1, -1,
18076 /* BUNDLE */
18077 /* LIFETIME_START */
18078 i32imm,
18079 /* LIFETIME_END */
18080 i32imm,
18081 /* PSEUDO_PROBE */
18082 i64imm, i64imm, i8imm, i32imm,
18083 /* ARITH_FENCE */
18084 -1, -1,
18085 /* STACKMAP */
18086 i64imm, i32imm,
18087 /* FENTRY_CALL */
18088 /* PATCHPOINT */
18089 -1, i64imm, i32imm, -1, i32imm, i32imm,
18090 /* LOAD_STACK_GUARD */
18091 -1,
18092 /* PREALLOCATED_SETUP */
18093 i32imm,
18094 /* PREALLOCATED_ARG */
18095 -1, i32imm, i32imm,
18096 /* STATEPOINT */
18097 /* LOCAL_ESCAPE */
18098 -1, i32imm,
18099 /* FAULTING_OP */
18100 -1,
18101 /* PATCHABLE_OP */
18102 /* PATCHABLE_FUNCTION_ENTER */
18103 /* PATCHABLE_RET */
18104 /* PATCHABLE_FUNCTION_EXIT */
18105 /* PATCHABLE_TAIL_CALL */
18106 /* PATCHABLE_EVENT_CALL */
18107 -1, -1,
18108 /* PATCHABLE_TYPED_EVENT_CALL */
18109 -1, -1, -1,
18110 /* ICALL_BRANCH_FUNNEL */
18111 /* MEMBARRIER */
18112 /* JUMP_TABLE_DEBUG_INFO */
18113 i64imm,
18114 /* CONVERGENCECTRL_ENTRY */
18115 -1,
18116 /* CONVERGENCECTRL_ANCHOR */
18117 -1,
18118 /* CONVERGENCECTRL_LOOP */
18119 -1, -1,
18120 /* CONVERGENCECTRL_GLUE */
18121 -1,
18122 /* G_ASSERT_SEXT */
18123 type0, type0, untyped_imm_0,
18124 /* G_ASSERT_ZEXT */
18125 type0, type0, untyped_imm_0,
18126 /* G_ASSERT_ALIGN */
18127 type0, type0, untyped_imm_0,
18128 /* G_ADD */
18129 type0, type0, type0,
18130 /* G_SUB */
18131 type0, type0, type0,
18132 /* G_MUL */
18133 type0, type0, type0,
18134 /* G_SDIV */
18135 type0, type0, type0,
18136 /* G_UDIV */
18137 type0, type0, type0,
18138 /* G_SREM */
18139 type0, type0, type0,
18140 /* G_UREM */
18141 type0, type0, type0,
18142 /* G_SDIVREM */
18143 type0, type0, type0, type0,
18144 /* G_UDIVREM */
18145 type0, type0, type0, type0,
18146 /* G_AND */
18147 type0, type0, type0,
18148 /* G_OR */
18149 type0, type0, type0,
18150 /* G_XOR */
18151 type0, type0, type0,
18152 /* G_IMPLICIT_DEF */
18153 type0,
18154 /* G_PHI */
18155 type0,
18156 /* G_FRAME_INDEX */
18157 type0, -1,
18158 /* G_GLOBAL_VALUE */
18159 type0, -1,
18160 /* G_PTRAUTH_GLOBAL_VALUE */
18161 type0, -1, i32imm, type1, i64imm,
18162 /* G_CONSTANT_POOL */
18163 type0, -1,
18164 /* G_EXTRACT */
18165 type0, type1, untyped_imm_0,
18166 /* G_UNMERGE_VALUES */
18167 type0, type1,
18168 /* G_INSERT */
18169 type0, type0, type1, untyped_imm_0,
18170 /* G_MERGE_VALUES */
18171 type0, type1,
18172 /* G_BUILD_VECTOR */
18173 type0, type1,
18174 /* G_BUILD_VECTOR_TRUNC */
18175 type0, type1,
18176 /* G_CONCAT_VECTORS */
18177 type0, type1,
18178 /* G_PTRTOINT */
18179 type0, type1,
18180 /* G_INTTOPTR */
18181 type0, type1,
18182 /* G_BITCAST */
18183 type0, type1,
18184 /* G_FREEZE */
18185 type0, type0,
18186 /* G_CONSTANT_FOLD_BARRIER */
18187 type0, type0,
18188 /* G_INTRINSIC_FPTRUNC_ROUND */
18189 type0, type1, i32imm,
18190 /* G_INTRINSIC_TRUNC */
18191 type0, type0,
18192 /* G_INTRINSIC_ROUND */
18193 type0, type0,
18194 /* G_INTRINSIC_LRINT */
18195 type0, type1,
18196 /* G_INTRINSIC_LLRINT */
18197 type0, type1,
18198 /* G_INTRINSIC_ROUNDEVEN */
18199 type0, type0,
18200 /* G_READCYCLECOUNTER */
18201 type0,
18202 /* G_READSTEADYCOUNTER */
18203 type0,
18204 /* G_LOAD */
18205 type0, ptype1,
18206 /* G_SEXTLOAD */
18207 type0, ptype1,
18208 /* G_ZEXTLOAD */
18209 type0, ptype1,
18210 /* G_INDEXED_LOAD */
18211 type0, ptype1, ptype1, type2, -1,
18212 /* G_INDEXED_SEXTLOAD */
18213 type0, ptype1, ptype1, type2, -1,
18214 /* G_INDEXED_ZEXTLOAD */
18215 type0, ptype1, ptype1, type2, -1,
18216 /* G_STORE */
18217 type0, ptype1,
18218 /* G_INDEXED_STORE */
18219 ptype0, type1, ptype0, ptype2, -1,
18220 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
18221 type0, type1, type2, type0, type0,
18222 /* G_ATOMIC_CMPXCHG */
18223 type0, ptype1, type0, type0,
18224 /* G_ATOMICRMW_XCHG */
18225 type0, ptype1, type0,
18226 /* G_ATOMICRMW_ADD */
18227 type0, ptype1, type0,
18228 /* G_ATOMICRMW_SUB */
18229 type0, ptype1, type0,
18230 /* G_ATOMICRMW_AND */
18231 type0, ptype1, type0,
18232 /* G_ATOMICRMW_NAND */
18233 type0, ptype1, type0,
18234 /* G_ATOMICRMW_OR */
18235 type0, ptype1, type0,
18236 /* G_ATOMICRMW_XOR */
18237 type0, ptype1, type0,
18238 /* G_ATOMICRMW_MAX */
18239 type0, ptype1, type0,
18240 /* G_ATOMICRMW_MIN */
18241 type0, ptype1, type0,
18242 /* G_ATOMICRMW_UMAX */
18243 type0, ptype1, type0,
18244 /* G_ATOMICRMW_UMIN */
18245 type0, ptype1, type0,
18246 /* G_ATOMICRMW_FADD */
18247 type0, ptype1, type0,
18248 /* G_ATOMICRMW_FSUB */
18249 type0, ptype1, type0,
18250 /* G_ATOMICRMW_FMAX */
18251 type0, ptype1, type0,
18252 /* G_ATOMICRMW_FMIN */
18253 type0, ptype1, type0,
18254 /* G_ATOMICRMW_UINC_WRAP */
18255 type0, ptype1, type0,
18256 /* G_ATOMICRMW_UDEC_WRAP */
18257 type0, ptype1, type0,
18258 /* G_FENCE */
18259 i32imm, i32imm,
18260 /* G_PREFETCH */
18261 ptype0, i32imm, i32imm, i32imm,
18262 /* G_BRCOND */
18263 type0, -1,
18264 /* G_BRINDIRECT */
18265 type0,
18266 /* G_INVOKE_REGION_START */
18267 /* G_INTRINSIC */
18268 -1,
18269 /* G_INTRINSIC_W_SIDE_EFFECTS */
18270 -1,
18271 /* G_INTRINSIC_CONVERGENT */
18272 -1,
18273 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
18274 -1,
18275 /* G_ANYEXT */
18276 type0, type1,
18277 /* G_TRUNC */
18278 type0, type1,
18279 /* G_CONSTANT */
18280 type0, -1,
18281 /* G_FCONSTANT */
18282 type0, -1,
18283 /* G_VASTART */
18284 type0,
18285 /* G_VAARG */
18286 type0, type1, -1,
18287 /* G_SEXT */
18288 type0, type1,
18289 /* G_SEXT_INREG */
18290 type0, type0, untyped_imm_0,
18291 /* G_ZEXT */
18292 type0, type1,
18293 /* G_SHL */
18294 type0, type0, type1,
18295 /* G_LSHR */
18296 type0, type0, type1,
18297 /* G_ASHR */
18298 type0, type0, type1,
18299 /* G_FSHL */
18300 type0, type0, type0, type1,
18301 /* G_FSHR */
18302 type0, type0, type0, type1,
18303 /* G_ROTR */
18304 type0, type0, type1,
18305 /* G_ROTL */
18306 type0, type0, type1,
18307 /* G_ICMP */
18308 type0, -1, type1, type1,
18309 /* G_FCMP */
18310 type0, -1, type1, type1,
18311 /* G_SCMP */
18312 type0, type1, type1,
18313 /* G_UCMP */
18314 type0, type1, type1,
18315 /* G_SELECT */
18316 type0, type1, type0, type0,
18317 /* G_UADDO */
18318 type0, type1, type0, type0,
18319 /* G_UADDE */
18320 type0, type1, type0, type0, type1,
18321 /* G_USUBO */
18322 type0, type1, type0, type0,
18323 /* G_USUBE */
18324 type0, type1, type0, type0, type1,
18325 /* G_SADDO */
18326 type0, type1, type0, type0,
18327 /* G_SADDE */
18328 type0, type1, type0, type0, type1,
18329 /* G_SSUBO */
18330 type0, type1, type0, type0,
18331 /* G_SSUBE */
18332 type0, type1, type0, type0, type1,
18333 /* G_UMULO */
18334 type0, type1, type0, type0,
18335 /* G_SMULO */
18336 type0, type1, type0, type0,
18337 /* G_UMULH */
18338 type0, type0, type0,
18339 /* G_SMULH */
18340 type0, type0, type0,
18341 /* G_UADDSAT */
18342 type0, type0, type0,
18343 /* G_SADDSAT */
18344 type0, type0, type0,
18345 /* G_USUBSAT */
18346 type0, type0, type0,
18347 /* G_SSUBSAT */
18348 type0, type0, type0,
18349 /* G_USHLSAT */
18350 type0, type0, type1,
18351 /* G_SSHLSAT */
18352 type0, type0, type1,
18353 /* G_SMULFIX */
18354 type0, type0, type0, untyped_imm_0,
18355 /* G_UMULFIX */
18356 type0, type0, type0, untyped_imm_0,
18357 /* G_SMULFIXSAT */
18358 type0, type0, type0, untyped_imm_0,
18359 /* G_UMULFIXSAT */
18360 type0, type0, type0, untyped_imm_0,
18361 /* G_SDIVFIX */
18362 type0, type0, type0, untyped_imm_0,
18363 /* G_UDIVFIX */
18364 type0, type0, type0, untyped_imm_0,
18365 /* G_SDIVFIXSAT */
18366 type0, type0, type0, untyped_imm_0,
18367 /* G_UDIVFIXSAT */
18368 type0, type0, type0, untyped_imm_0,
18369 /* G_FADD */
18370 type0, type0, type0,
18371 /* G_FSUB */
18372 type0, type0, type0,
18373 /* G_FMUL */
18374 type0, type0, type0,
18375 /* G_FMA */
18376 type0, type0, type0, type0,
18377 /* G_FMAD */
18378 type0, type0, type0, type0,
18379 /* G_FDIV */
18380 type0, type0, type0,
18381 /* G_FREM */
18382 type0, type0, type0,
18383 /* G_FPOW */
18384 type0, type0, type0,
18385 /* G_FPOWI */
18386 type0, type0, type1,
18387 /* G_FEXP */
18388 type0, type0,
18389 /* G_FEXP2 */
18390 type0, type0,
18391 /* G_FEXP10 */
18392 type0, type0,
18393 /* G_FLOG */
18394 type0, type0,
18395 /* G_FLOG2 */
18396 type0, type0,
18397 /* G_FLOG10 */
18398 type0, type0,
18399 /* G_FLDEXP */
18400 type0, type0, type1,
18401 /* G_FFREXP */
18402 type0, type1, type0,
18403 /* G_FNEG */
18404 type0, type0,
18405 /* G_FPEXT */
18406 type0, type1,
18407 /* G_FPTRUNC */
18408 type0, type1,
18409 /* G_FPTOSI */
18410 type0, type1,
18411 /* G_FPTOUI */
18412 type0, type1,
18413 /* G_SITOFP */
18414 type0, type1,
18415 /* G_UITOFP */
18416 type0, type1,
18417 /* G_FABS */
18418 type0, type0,
18419 /* G_FCOPYSIGN */
18420 type0, type0, type1,
18421 /* G_IS_FPCLASS */
18422 type0, type1, -1,
18423 /* G_FCANONICALIZE */
18424 type0, type0,
18425 /* G_FMINNUM */
18426 type0, type0, type0,
18427 /* G_FMAXNUM */
18428 type0, type0, type0,
18429 /* G_FMINNUM_IEEE */
18430 type0, type0, type0,
18431 /* G_FMAXNUM_IEEE */
18432 type0, type0, type0,
18433 /* G_FMINIMUM */
18434 type0, type0, type0,
18435 /* G_FMAXIMUM */
18436 type0, type0, type0,
18437 /* G_GET_FPENV */
18438 type0,
18439 /* G_SET_FPENV */
18440 type0,
18441 /* G_RESET_FPENV */
18442 /* G_GET_FPMODE */
18443 type0,
18444 /* G_SET_FPMODE */
18445 type0,
18446 /* G_RESET_FPMODE */
18447 /* G_PTR_ADD */
18448 ptype0, ptype0, type1,
18449 /* G_PTRMASK */
18450 ptype0, ptype0, type1,
18451 /* G_SMIN */
18452 type0, type0, type0,
18453 /* G_SMAX */
18454 type0, type0, type0,
18455 /* G_UMIN */
18456 type0, type0, type0,
18457 /* G_UMAX */
18458 type0, type0, type0,
18459 /* G_ABS */
18460 type0, type0,
18461 /* G_LROUND */
18462 type0, type1,
18463 /* G_LLROUND */
18464 type0, type1,
18465 /* G_BR */
18466 -1,
18467 /* G_BRJT */
18468 ptype0, -1, type1,
18469 /* G_VSCALE */
18470 type0, -1,
18471 /* G_INSERT_SUBVECTOR */
18472 type0, type0, type1, untyped_imm_0,
18473 /* G_EXTRACT_SUBVECTOR */
18474 type0, type0, untyped_imm_0,
18475 /* G_INSERT_VECTOR_ELT */
18476 type0, type0, type1, type2,
18477 /* G_EXTRACT_VECTOR_ELT */
18478 type0, type1, type2,
18479 /* G_SHUFFLE_VECTOR */
18480 type0, type1, type1, -1,
18481 /* G_SPLAT_VECTOR */
18482 type0, type1,
18483 /* G_VECTOR_COMPRESS */
18484 type0, type0, type1, type0,
18485 /* G_CTTZ */
18486 type0, type1,
18487 /* G_CTTZ_ZERO_UNDEF */
18488 type0, type1,
18489 /* G_CTLZ */
18490 type0, type1,
18491 /* G_CTLZ_ZERO_UNDEF */
18492 type0, type1,
18493 /* G_CTPOP */
18494 type0, type1,
18495 /* G_BSWAP */
18496 type0, type0,
18497 /* G_BITREVERSE */
18498 type0, type0,
18499 /* G_FCEIL */
18500 type0, type0,
18501 /* G_FCOS */
18502 type0, type0,
18503 /* G_FSIN */
18504 type0, type0,
18505 /* G_FTAN */
18506 type0, type0,
18507 /* G_FACOS */
18508 type0, type0,
18509 /* G_FASIN */
18510 type0, type0,
18511 /* G_FATAN */
18512 type0, type0,
18513 /* G_FCOSH */
18514 type0, type0,
18515 /* G_FSINH */
18516 type0, type0,
18517 /* G_FTANH */
18518 type0, type0,
18519 /* G_FSQRT */
18520 type0, type0,
18521 /* G_FFLOOR */
18522 type0, type0,
18523 /* G_FRINT */
18524 type0, type0,
18525 /* G_FNEARBYINT */
18526 type0, type0,
18527 /* G_ADDRSPACE_CAST */
18528 type0, type1,
18529 /* G_BLOCK_ADDR */
18530 type0, -1,
18531 /* G_JUMP_TABLE */
18532 type0, -1,
18533 /* G_DYN_STACKALLOC */
18534 ptype0, type1, i32imm,
18535 /* G_STACKSAVE */
18536 ptype0,
18537 /* G_STACKRESTORE */
18538 ptype0,
18539 /* G_STRICT_FADD */
18540 type0, type0, type0,
18541 /* G_STRICT_FSUB */
18542 type0, type0, type0,
18543 /* G_STRICT_FMUL */
18544 type0, type0, type0,
18545 /* G_STRICT_FDIV */
18546 type0, type0, type0,
18547 /* G_STRICT_FREM */
18548 type0, type0, type0,
18549 /* G_STRICT_FMA */
18550 type0, type0, type0, type0,
18551 /* G_STRICT_FSQRT */
18552 type0, type0,
18553 /* G_STRICT_FLDEXP */
18554 type0, type0, type1,
18555 /* G_READ_REGISTER */
18556 type0, -1,
18557 /* G_WRITE_REGISTER */
18558 -1, type0,
18559 /* G_MEMCPY */
18560 ptype0, ptype1, type2, untyped_imm_0,
18561 /* G_MEMCPY_INLINE */
18562 ptype0, ptype1, type2,
18563 /* G_MEMMOVE */
18564 ptype0, ptype1, type2, untyped_imm_0,
18565 /* G_MEMSET */
18566 ptype0, type1, type2, untyped_imm_0,
18567 /* G_BZERO */
18568 ptype0, type1, untyped_imm_0,
18569 /* G_TRAP */
18570 /* G_DEBUGTRAP */
18571 /* G_UBSANTRAP */
18572 i8imm,
18573 /* G_VECREDUCE_SEQ_FADD */
18574 type0, type1, type2,
18575 /* G_VECREDUCE_SEQ_FMUL */
18576 type0, type1, type2,
18577 /* G_VECREDUCE_FADD */
18578 type0, type1,
18579 /* G_VECREDUCE_FMUL */
18580 type0, type1,
18581 /* G_VECREDUCE_FMAX */
18582 type0, type1,
18583 /* G_VECREDUCE_FMIN */
18584 type0, type1,
18585 /* G_VECREDUCE_FMAXIMUM */
18586 type0, type1,
18587 /* G_VECREDUCE_FMINIMUM */
18588 type0, type1,
18589 /* G_VECREDUCE_ADD */
18590 type0, type1,
18591 /* G_VECREDUCE_MUL */
18592 type0, type1,
18593 /* G_VECREDUCE_AND */
18594 type0, type1,
18595 /* G_VECREDUCE_OR */
18596 type0, type1,
18597 /* G_VECREDUCE_XOR */
18598 type0, type1,
18599 /* G_VECREDUCE_SMAX */
18600 type0, type1,
18601 /* G_VECREDUCE_SMIN */
18602 type0, type1,
18603 /* G_VECREDUCE_UMAX */
18604 type0, type1,
18605 /* G_VECREDUCE_UMIN */
18606 type0, type1,
18607 /* G_SBFX */
18608 type0, type0, type1, type1,
18609 /* G_UBFX */
18610 type0, type0, type1, type1,
18611 /* A2_addsp */
18612 DoubleRegs, IntRegs, DoubleRegs,
18613 /* A2_iconst */
18614 IntRegs, s27_2Imm,
18615 /* A2_neg */
18616 IntRegs, IntRegs,
18617 /* A2_not */
18618 IntRegs, IntRegs,
18619 /* A2_tfrf */
18620 IntRegs, PredRegs, IntRegs,
18621 /* A2_tfrfnew */
18622 IntRegs, PredRegs, IntRegs,
18623 /* A2_tfrp */
18624 DoubleRegs, DoubleRegs,
18625 /* A2_tfrpf */
18626 DoubleRegs, PredRegs, DoubleRegs,
18627 /* A2_tfrpfnew */
18628 DoubleRegs, PredRegs, DoubleRegs,
18629 /* A2_tfrpi */
18630 DoubleRegs, s8_0Imm,
18631 /* A2_tfrpt */
18632 DoubleRegs, PredRegs, DoubleRegs,
18633 /* A2_tfrptnew */
18634 DoubleRegs, PredRegs, DoubleRegs,
18635 /* A2_tfrt */
18636 IntRegs, PredRegs, IntRegs,
18637 /* A2_tfrtnew */
18638 IntRegs, PredRegs, IntRegs,
18639 /* A2_vaddb_map */
18640 DoubleRegs, DoubleRegs, DoubleRegs,
18641 /* A2_vsubb_map */
18642 DoubleRegs, DoubleRegs, DoubleRegs,
18643 /* A2_zxtb */
18644 IntRegs, IntRegs,
18645 /* A4_boundscheck */
18646 PredRegs, IntRegs, DoubleRegs,
18647 /* ADJCALLSTACKDOWN */
18648 i32imm, i32imm,
18649 /* ADJCALLSTACKUP */
18650 i32imm, i32imm,
18651 /* C2_cmpgei */
18652 PredRegs, IntRegs, s8_0Imm,
18653 /* C2_cmpgeui */
18654 PredRegs, IntRegs, u8_0Imm,
18655 /* C2_cmplt */
18656 PredRegs, IntRegs, IntRegs,
18657 /* C2_cmpltu */
18658 PredRegs, IntRegs, IntRegs,
18659 /* C2_pxfer_map */
18660 PredRegs, PredRegs,
18661 /* DUPLEX_Pseudo */
18662 s32_0Imm,
18663 /* ENDLOOP0 */
18664 b30_2Imm,
18665 /* ENDLOOP01 */
18666 b30_2Imm,
18667 /* ENDLOOP1 */
18668 b30_2Imm,
18669 /* J2_endloop0 */
18670 /* J2_endloop01 */
18671 /* J2_endloop1 */
18672 /* J2_jumpf_nopred_map */
18673 PredRegs, b15_2Imm,
18674 /* J2_jumprf_nopred_map */
18675 PredRegs, IntRegs,
18676 /* J2_jumprt_nopred_map */
18677 PredRegs, IntRegs,
18678 /* J2_jumpt_nopred_map */
18679 PredRegs, b15_2Imm,
18680 /* J2_trap1_noregmap */
18681 u8_0Imm,
18682 /* L2_loadalignb_zomap */
18683 DoubleRegs, DoubleRegs, IntRegs,
18684 /* L2_loadalignh_zomap */
18685 DoubleRegs, DoubleRegs, IntRegs,
18686 /* L2_loadbsw2_zomap */
18687 IntRegs, IntRegs,
18688 /* L2_loadbsw4_zomap */
18689 DoubleRegs, IntRegs,
18690 /* L2_loadbzw2_zomap */
18691 IntRegs, IntRegs,
18692 /* L2_loadbzw4_zomap */
18693 DoubleRegs, IntRegs,
18694 /* L2_loadrb_zomap */
18695 IntRegs, IntRegs,
18696 /* L2_loadrd_zomap */
18697 DoubleRegs, IntRegs,
18698 /* L2_loadrh_zomap */
18699 IntRegs, IntRegs,
18700 /* L2_loadri_zomap */
18701 IntRegs, IntRegs,
18702 /* L2_loadrub_zomap */
18703 IntRegs, IntRegs,
18704 /* L2_loadruh_zomap */
18705 IntRegs, IntRegs,
18706 /* L2_ploadrbf_zomap */
18707 IntRegs, PredRegs, IntRegs,
18708 /* L2_ploadrbfnew_zomap */
18709 IntRegs, PredRegs, IntRegs,
18710 /* L2_ploadrbt_zomap */
18711 IntRegs, PredRegs, IntRegs,
18712 /* L2_ploadrbtnew_zomap */
18713 IntRegs, PredRegs, IntRegs,
18714 /* L2_ploadrdf_zomap */
18715 DoubleRegs, PredRegs, IntRegs,
18716 /* L2_ploadrdfnew_zomap */
18717 DoubleRegs, PredRegs, IntRegs,
18718 /* L2_ploadrdt_zomap */
18719 DoubleRegs, PredRegs, IntRegs,
18720 /* L2_ploadrdtnew_zomap */
18721 DoubleRegs, PredRegs, IntRegs,
18722 /* L2_ploadrhf_zomap */
18723 IntRegs, PredRegs, IntRegs,
18724 /* L2_ploadrhfnew_zomap */
18725 IntRegs, PredRegs, IntRegs,
18726 /* L2_ploadrht_zomap */
18727 IntRegs, PredRegs, IntRegs,
18728 /* L2_ploadrhtnew_zomap */
18729 IntRegs, PredRegs, IntRegs,
18730 /* L2_ploadrif_zomap */
18731 IntRegs, PredRegs, IntRegs,
18732 /* L2_ploadrifnew_zomap */
18733 IntRegs, PredRegs, IntRegs,
18734 /* L2_ploadrit_zomap */
18735 IntRegs, PredRegs, IntRegs,
18736 /* L2_ploadritnew_zomap */
18737 IntRegs, PredRegs, IntRegs,
18738 /* L2_ploadrubf_zomap */
18739 IntRegs, PredRegs, IntRegs,
18740 /* L2_ploadrubfnew_zomap */
18741 IntRegs, PredRegs, IntRegs,
18742 /* L2_ploadrubt_zomap */
18743 IntRegs, PredRegs, IntRegs,
18744 /* L2_ploadrubtnew_zomap */
18745 IntRegs, PredRegs, IntRegs,
18746 /* L2_ploadruhf_zomap */
18747 IntRegs, PredRegs, IntRegs,
18748 /* L2_ploadruhfnew_zomap */
18749 IntRegs, PredRegs, IntRegs,
18750 /* L2_ploadruht_zomap */
18751 IntRegs, PredRegs, IntRegs,
18752 /* L2_ploadruhtnew_zomap */
18753 IntRegs, PredRegs, IntRegs,
18754 /* L4_add_memopb_zomap */
18755 IntRegs, IntRegs,
18756 /* L4_add_memoph_zomap */
18757 IntRegs, IntRegs,
18758 /* L4_add_memopw_zomap */
18759 IntRegs, IntRegs,
18760 /* L4_and_memopb_zomap */
18761 IntRegs, IntRegs,
18762 /* L4_and_memoph_zomap */
18763 IntRegs, IntRegs,
18764 /* L4_and_memopw_zomap */
18765 IntRegs, IntRegs,
18766 /* L4_iadd_memopb_zomap */
18767 IntRegs, u5_0Imm,
18768 /* L4_iadd_memoph_zomap */
18769 IntRegs, u5_0Imm,
18770 /* L4_iadd_memopw_zomap */
18771 IntRegs, u5_0Imm,
18772 /* L4_iand_memopb_zomap */
18773 IntRegs, u5_0Imm,
18774 /* L4_iand_memoph_zomap */
18775 IntRegs, u5_0Imm,
18776 /* L4_iand_memopw_zomap */
18777 IntRegs, u5_0Imm,
18778 /* L4_ior_memopb_zomap */
18779 IntRegs, u5_0Imm,
18780 /* L4_ior_memoph_zomap */
18781 IntRegs, u5_0Imm,
18782 /* L4_ior_memopw_zomap */
18783 IntRegs, u5_0Imm,
18784 /* L4_isub_memopb_zomap */
18785 IntRegs, u5_0Imm,
18786 /* L4_isub_memoph_zomap */
18787 IntRegs, u5_0Imm,
18788 /* L4_isub_memopw_zomap */
18789 IntRegs, u5_0Imm,
18790 /* L4_or_memopb_zomap */
18791 IntRegs, IntRegs,
18792 /* L4_or_memoph_zomap */
18793 IntRegs, IntRegs,
18794 /* L4_or_memopw_zomap */
18795 IntRegs, IntRegs,
18796 /* L4_return_map_to_raw_f */
18797 PredRegs,
18798 /* L4_return_map_to_raw_fnew_pnt */
18799 PredRegs,
18800 /* L4_return_map_to_raw_fnew_pt */
18801 PredRegs,
18802 /* L4_return_map_to_raw_t */
18803 PredRegs,
18804 /* L4_return_map_to_raw_tnew_pnt */
18805 PredRegs,
18806 /* L4_return_map_to_raw_tnew_pt */
18807 PredRegs,
18808 /* L4_sub_memopb_zomap */
18809 IntRegs, IntRegs,
18810 /* L4_sub_memoph_zomap */
18811 IntRegs, IntRegs,
18812 /* L4_sub_memopw_zomap */
18813 IntRegs, IntRegs,
18814 /* L6_deallocframe_map_to_raw */
18815 /* L6_return_map_to_raw */
18816 /* LDriw_ctr */
18817 CtrRegs, IntRegs, s32_0Imm,
18818 /* LDriw_pred */
18819 PredRegs, IntRegs, s32_0Imm,
18820 /* M2_mpysmi */
18821 IntRegs, IntRegs, m32_0Imm,
18822 /* M2_mpyui */
18823 IntRegs, IntRegs, IntRegs,
18824 /* M2_vrcmpys_acc_s1 */
18825 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
18826 /* M2_vrcmpys_s1 */
18827 DoubleRegs, DoubleRegs, IntRegs,
18828 /* M2_vrcmpys_s1rp */
18829 IntRegs, DoubleRegs, IntRegs,
18830 /* M7_vdmpy */
18831 DoubleRegs, DoubleRegs, DoubleRegs,
18832 /* M7_vdmpy_acc */
18833 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
18834 /* PS_aligna */
18835 IntRegs, u32_0Imm,
18836 /* PS_alloca */
18837 IntRegs, IntRegs, u32_0Imm,
18838 /* PS_call_instrprof_custom */
18839 s32_0Imm, u32_0Imm,
18840 /* PS_call_nr */
18841 s32_0Imm,
18842 /* PS_crash */
18843 /* PS_false */
18844 PredRegs,
18845 /* PS_fi */
18846 IntRegs, IntRegs, s32_0Imm,
18847 /* PS_fia */
18848 IntRegs, IntRegs, IntRegs, s32_0Imm,
18849 /* PS_loadrb_pci */
18850 IntRegs, IntRegs, IntRegs, s4_0Imm, ModRegs, IntRegs,
18851 /* PS_loadrb_pcr */
18852 IntRegs, IntRegs, IntRegs, ModRegs, IntRegs,
18853 /* PS_loadrd_pci */
18854 DoubleRegs, IntRegs, IntRegs, s4_0Imm, ModRegs, IntRegs,
18855 /* PS_loadrd_pcr */
18856 DoubleRegs, IntRegs, IntRegs, ModRegs, IntRegs,
18857 /* PS_loadrh_pci */
18858 IntRegs, IntRegs, IntRegs, s4_0Imm, ModRegs, IntRegs,
18859 /* PS_loadrh_pcr */
18860 IntRegs, IntRegs, IntRegs, ModRegs, IntRegs,
18861 /* PS_loadri_pci */
18862 IntRegs, IntRegs, IntRegs, s4_0Imm, ModRegs, IntRegs,
18863 /* PS_loadri_pcr */
18864 IntRegs, IntRegs, IntRegs, ModRegs, IntRegs,
18865 /* PS_loadrub_pci */
18866 IntRegs, IntRegs, IntRegs, s4_0Imm, ModRegs, IntRegs,
18867 /* PS_loadrub_pcr */
18868 IntRegs, IntRegs, IntRegs, ModRegs, IntRegs,
18869 /* PS_loadruh_pci */
18870 IntRegs, IntRegs, IntRegs, s4_0Imm, ModRegs, IntRegs,
18871 /* PS_loadruh_pcr */
18872 IntRegs, IntRegs, IntRegs, ModRegs, IntRegs,
18873 /* PS_pselect */
18874 DoubleRegs, PredRegs, DoubleRegs, DoubleRegs,
18875 /* PS_qfalse */
18876 HvxQR,
18877 /* PS_qtrue */
18878 HvxQR,
18879 /* PS_storerb_pci */
18880 IntRegs, IntRegs, s4_0Imm, ModRegs, IntRegs, IntRegs,
18881 /* PS_storerb_pcr */
18882 IntRegs, IntRegs, ModRegs, IntRegs, IntRegs,
18883 /* PS_storerd_pci */
18884 IntRegs, IntRegs, s4_0Imm, ModRegs, DoubleRegs, IntRegs,
18885 /* PS_storerd_pcr */
18886 IntRegs, IntRegs, ModRegs, DoubleRegs, IntRegs,
18887 /* PS_storerf_pci */
18888 IntRegs, IntRegs, s4_0Imm, ModRegs, IntRegs, IntRegs,
18889 /* PS_storerf_pcr */
18890 IntRegs, IntRegs, ModRegs, IntRegs, IntRegs,
18891 /* PS_storerh_pci */
18892 IntRegs, IntRegs, s4_0Imm, ModRegs, IntRegs, IntRegs,
18893 /* PS_storerh_pcr */
18894 IntRegs, IntRegs, ModRegs, IntRegs, IntRegs,
18895 /* PS_storeri_pci */
18896 IntRegs, IntRegs, s4_0Imm, ModRegs, IntRegs, IntRegs,
18897 /* PS_storeri_pcr */
18898 IntRegs, IntRegs, ModRegs, IntRegs, IntRegs,
18899 /* PS_tailcall_i */
18900 a30_2Imm,
18901 /* PS_tailcall_r */
18902 IntRegs,
18903 /* PS_true */
18904 PredRegs,
18905 /* PS_vdd0 */
18906 HvxWR,
18907 /* PS_vloadrq_ai */
18908 HvxQR, IntRegs, s32_0Imm,
18909 /* PS_vloadrv_ai */
18910 HvxVR, IntRegs, s32_0Imm,
18911 /* PS_vloadrv_nt_ai */
18912 HvxVR, IntRegs, s32_0Imm,
18913 /* PS_vloadrw_ai */
18914 HvxWR, IntRegs, s32_0Imm,
18915 /* PS_vloadrw_nt_ai */
18916 HvxWR, IntRegs, s32_0Imm,
18917 /* PS_vmulw */
18918 DoubleRegs, DoubleRegs, DoubleRegs,
18919 /* PS_vmulw_acc */
18920 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
18921 /* PS_vselect */
18922 HvxVR, PredRegs, HvxVR, HvxVR,
18923 /* PS_vsplatib */
18924 HvxVR, s32_0Imm,
18925 /* PS_vsplatih */
18926 HvxVR, s32_0Imm,
18927 /* PS_vsplatiw */
18928 HvxVR, s32_0Imm,
18929 /* PS_vsplatrb */
18930 HvxVR, IntRegs,
18931 /* PS_vsplatrh */
18932 HvxVR, IntRegs,
18933 /* PS_vsplatrw */
18934 HvxVR, IntRegs,
18935 /* PS_vstorerq_ai */
18936 IntRegs, s32_0Imm, HvxQR,
18937 /* PS_vstorerv_ai */
18938 IntRegs, s32_0Imm, HvxVR,
18939 /* PS_vstorerv_nt_ai */
18940 IntRegs, s32_0Imm, HvxVR,
18941 /* PS_vstorerw_ai */
18942 IntRegs, s32_0Imm, HvxWR,
18943 /* PS_vstorerw_nt_ai */
18944 IntRegs, s32_0Imm, HvxWR,
18945 /* PS_wselect */
18946 HvxWR, PredRegs, HvxWR, HvxWR,
18947 /* S2_asr_i_p_rnd_goodsyntax */
18948 DoubleRegs, DoubleRegs, u6_0Imm,
18949 /* S2_asr_i_r_rnd_goodsyntax */
18950 IntRegs, IntRegs, u5_0Imm,
18951 /* S2_pstorerbf_zomap */
18952 PredRegs, IntRegs, IntRegs,
18953 /* S2_pstorerbnewf_zomap */
18954 PredRegs, IntRegs, IntRegs,
18955 /* S2_pstorerbnewt_zomap */
18956 PredRegs, IntRegs, IntRegs,
18957 /* S2_pstorerbt_zomap */
18958 PredRegs, IntRegs, IntRegs,
18959 /* S2_pstorerdf_zomap */
18960 PredRegs, IntRegs, DoubleRegs,
18961 /* S2_pstorerdt_zomap */
18962 PredRegs, IntRegs, DoubleRegs,
18963 /* S2_pstorerff_zomap */
18964 PredRegs, IntRegs, IntRegs,
18965 /* S2_pstorerft_zomap */
18966 PredRegs, IntRegs, IntRegs,
18967 /* S2_pstorerhf_zomap */
18968 PredRegs, IntRegs, IntRegs,
18969 /* S2_pstorerhnewf_zomap */
18970 PredRegs, IntRegs, IntRegs,
18971 /* S2_pstorerhnewt_zomap */
18972 PredRegs, IntRegs, IntRegs,
18973 /* S2_pstorerht_zomap */
18974 PredRegs, IntRegs, IntRegs,
18975 /* S2_pstorerif_zomap */
18976 PredRegs, IntRegs, IntRegs,
18977 /* S2_pstorerinewf_zomap */
18978 PredRegs, IntRegs, IntRegs,
18979 /* S2_pstorerinewt_zomap */
18980 PredRegs, IntRegs, IntRegs,
18981 /* S2_pstorerit_zomap */
18982 PredRegs, IntRegs, IntRegs,
18983 /* S2_storerb_zomap */
18984 IntRegs, IntRegs,
18985 /* S2_storerbnew_zomap */
18986 IntRegs, IntRegs,
18987 /* S2_storerd_zomap */
18988 IntRegs, DoubleRegs,
18989 /* S2_storerf_zomap */
18990 IntRegs, IntRegs,
18991 /* S2_storerh_zomap */
18992 IntRegs, IntRegs,
18993 /* S2_storerhnew_zomap */
18994 IntRegs, IntRegs,
18995 /* S2_storeri_zomap */
18996 IntRegs, IntRegs,
18997 /* S2_storerinew_zomap */
18998 IntRegs, IntRegs,
18999 /* S2_tableidxb_goodsyntax */
19000 IntRegs, IntRegs, IntRegs, u4_0Imm, u5_0Imm,
19001 /* S2_tableidxd_goodsyntax */
19002 IntRegs, IntRegs, IntRegs, u4_0Imm, u5_0Imm,
19003 /* S2_tableidxh_goodsyntax */
19004 IntRegs, IntRegs, IntRegs, u4_0Imm, u5_0Imm,
19005 /* S2_tableidxw_goodsyntax */
19006 IntRegs, IntRegs, IntRegs, u4_0Imm, u5_0Imm,
19007 /* S4_pstorerbfnew_zomap */
19008 PredRegs, IntRegs, IntRegs,
19009 /* S4_pstorerbnewfnew_zomap */
19010 PredRegs, IntRegs, IntRegs,
19011 /* S4_pstorerbnewtnew_zomap */
19012 PredRegs, IntRegs, IntRegs,
19013 /* S4_pstorerbtnew_zomap */
19014 PredRegs, IntRegs, IntRegs,
19015 /* S4_pstorerdfnew_zomap */
19016 PredRegs, IntRegs, DoubleRegs,
19017 /* S4_pstorerdtnew_zomap */
19018 PredRegs, IntRegs, DoubleRegs,
19019 /* S4_pstorerffnew_zomap */
19020 PredRegs, IntRegs, IntRegs,
19021 /* S4_pstorerftnew_zomap */
19022 PredRegs, IntRegs, IntRegs,
19023 /* S4_pstorerhfnew_zomap */
19024 PredRegs, IntRegs, IntRegs,
19025 /* S4_pstorerhnewfnew_zomap */
19026 PredRegs, IntRegs, IntRegs,
19027 /* S4_pstorerhnewtnew_zomap */
19028 PredRegs, IntRegs, IntRegs,
19029 /* S4_pstorerhtnew_zomap */
19030 PredRegs, IntRegs, IntRegs,
19031 /* S4_pstorerifnew_zomap */
19032 PredRegs, IntRegs, IntRegs,
19033 /* S4_pstorerinewfnew_zomap */
19034 PredRegs, IntRegs, IntRegs,
19035 /* S4_pstorerinewtnew_zomap */
19036 PredRegs, IntRegs, IntRegs,
19037 /* S4_pstoreritnew_zomap */
19038 PredRegs, IntRegs, IntRegs,
19039 /* S4_storeirb_zomap */
19040 IntRegs, s8_0Imm,
19041 /* S4_storeirbf_zomap */
19042 PredRegs, IntRegs, s6_0Imm,
19043 /* S4_storeirbfnew_zomap */
19044 PredRegs, IntRegs, s6_0Imm,
19045 /* S4_storeirbt_zomap */
19046 PredRegs, IntRegs, s6_0Imm,
19047 /* S4_storeirbtnew_zomap */
19048 PredRegs, IntRegs, s6_0Imm,
19049 /* S4_storeirh_zomap */
19050 IntRegs, s8_0Imm,
19051 /* S4_storeirhf_zomap */
19052 PredRegs, IntRegs, s6_0Imm,
19053 /* S4_storeirhfnew_zomap */
19054 PredRegs, IntRegs, s6_0Imm,
19055 /* S4_storeirht_zomap */
19056 PredRegs, IntRegs, s6_0Imm,
19057 /* S4_storeirhtnew_zomap */
19058 PredRegs, IntRegs, s6_0Imm,
19059 /* S4_storeiri_zomap */
19060 IntRegs, s8_0Imm,
19061 /* S4_storeirif_zomap */
19062 PredRegs, IntRegs, s6_0Imm,
19063 /* S4_storeirifnew_zomap */
19064 PredRegs, IntRegs, s6_0Imm,
19065 /* S4_storeirit_zomap */
19066 PredRegs, IntRegs, s6_0Imm,
19067 /* S4_storeiritnew_zomap */
19068 PredRegs, IntRegs, s6_0Imm,
19069 /* S5_asrhub_rnd_sat_goodsyntax */
19070 IntRegs, DoubleRegs, u4_0Imm,
19071 /* S5_vasrhrnd_goodsyntax */
19072 DoubleRegs, DoubleRegs, u4_0Imm,
19073 /* S6_allocframe_to_raw */
19074 u11_3Imm,
19075 /* STriw_ctr */
19076 IntRegs, s32_0Imm, CtrRegs,
19077 /* STriw_pred */
19078 IntRegs, s32_0Imm, PredRegs,
19079 /* V6_MAP_equb */
19080 HvxQR, HvxVR, HvxVR,
19081 /* V6_MAP_equb_and */
19082 HvxQR, HvxQR, HvxVR, HvxVR,
19083 /* V6_MAP_equb_ior */
19084 HvxQR, HvxQR, HvxVR, HvxVR,
19085 /* V6_MAP_equb_xor */
19086 HvxQR, HvxQR, HvxVR, HvxVR,
19087 /* V6_MAP_equh */
19088 HvxQR, HvxVR, HvxVR,
19089 /* V6_MAP_equh_and */
19090 HvxQR, HvxQR, HvxVR, HvxVR,
19091 /* V6_MAP_equh_ior */
19092 HvxQR, HvxQR, HvxVR, HvxVR,
19093 /* V6_MAP_equh_xor */
19094 HvxQR, HvxQR, HvxVR, HvxVR,
19095 /* V6_MAP_equw */
19096 HvxQR, HvxVR, HvxVR,
19097 /* V6_MAP_equw_and */
19098 HvxQR, HvxQR, HvxVR, HvxVR,
19099 /* V6_MAP_equw_ior */
19100 HvxQR, HvxQR, HvxVR, HvxVR,
19101 /* V6_MAP_equw_xor */
19102 HvxQR, HvxQR, HvxVR, HvxVR,
19103 /* V6_dbl_ld0 */
19104 HvxWR, IntRegs,
19105 /* V6_dbl_st0 */
19106 IntRegs, HvxWR,
19107 /* V6_extractw_alt */
19108 IntRegs, HvxVR, IntRegs,
19109 /* V6_hi */
19110 HvxVR, HvxWR,
19111 /* V6_ld0 */
19112 HvxVR, IntRegs,
19113 /* V6_ldcnp0 */
19114 HvxVR, PredRegs, IntRegs,
19115 /* V6_ldcnpnt0 */
19116 HvxVR, PredRegs, IntRegs,
19117 /* V6_ldcp0 */
19118 HvxVR, PredRegs, IntRegs,
19119 /* V6_ldcpnt0 */
19120 HvxVR, PredRegs, IntRegs,
19121 /* V6_ldnp0 */
19122 HvxVR, PredRegs, IntRegs,
19123 /* V6_ldnpnt0 */
19124 HvxVR, PredRegs, IntRegs,
19125 /* V6_ldnt0 */
19126 HvxVR, IntRegs,
19127 /* V6_ldp0 */
19128 HvxVR, PredRegs, IntRegs,
19129 /* V6_ldpnt0 */
19130 HvxVR, PredRegs, IntRegs,
19131 /* V6_ldtnp0 */
19132 HvxVR, PredRegs, IntRegs,
19133 /* V6_ldtnpnt0 */
19134 HvxVR, PredRegs, IntRegs,
19135 /* V6_ldtp0 */
19136 HvxVR, PredRegs, IntRegs,
19137 /* V6_ldtpnt0 */
19138 HvxVR, PredRegs, IntRegs,
19139 /* V6_ldu0 */
19140 HvxVR, IntRegs,
19141 /* V6_lo */
19142 HvxVR, HvxWR,
19143 /* V6_st0 */
19144 IntRegs, HvxVR,
19145 /* V6_stn0 */
19146 IntRegs, HvxVR,
19147 /* V6_stnnt0 */
19148 IntRegs, HvxVR,
19149 /* V6_stnp0 */
19150 PredRegs, IntRegs, HvxVR,
19151 /* V6_stnpnt0 */
19152 PredRegs, IntRegs, HvxVR,
19153 /* V6_stnq0 */
19154 HvxQR, IntRegs, HvxVR,
19155 /* V6_stnqnt0 */
19156 HvxQR, IntRegs, HvxVR,
19157 /* V6_stnt0 */
19158 IntRegs, HvxVR,
19159 /* V6_stp0 */
19160 PredRegs, IntRegs, HvxVR,
19161 /* V6_stpnt0 */
19162 PredRegs, IntRegs, HvxVR,
19163 /* V6_stq0 */
19164 HvxQR, IntRegs, HvxVR,
19165 /* V6_stqnt0 */
19166 HvxQR, IntRegs, HvxVR,
19167 /* V6_stu0 */
19168 IntRegs, HvxVR,
19169 /* V6_stunp0 */
19170 PredRegs, IntRegs, HvxVR,
19171 /* V6_stup0 */
19172 PredRegs, IntRegs, HvxVR,
19173 /* V6_v10mpyubs10 */
19174 HvxWR, HvxWR, HvxWR, u1_0Imm,
19175 /* V6_v10mpyubs10_vxx */
19176 HvxWR, HvxWR, HvxWR, HvxWR, u1_0Imm,
19177 /* V6_v6mpyhubs10_alt */
19178 HvxWR, HvxWR, HvxWR, u2_0Imm,
19179 /* V6_v6mpyvubs10_alt */
19180 HvxWR, HvxWR, HvxWR, u2_0Imm,
19181 /* V6_vabsb_alt */
19182 HvxVR, HvxVR,
19183 /* V6_vabsb_sat_alt */
19184 HvxVR, HvxVR,
19185 /* V6_vabsdiffh_alt */
19186 HvxVR, HvxVR, HvxVR,
19187 /* V6_vabsdiffub_alt */
19188 HvxVR, HvxVR, HvxVR,
19189 /* V6_vabsdiffuh_alt */
19190 HvxVR, HvxVR, HvxVR,
19191 /* V6_vabsdiffw_alt */
19192 HvxVR, HvxVR, HvxVR,
19193 /* V6_vabsh_alt */
19194 HvxVR, HvxVR,
19195 /* V6_vabsh_sat_alt */
19196 HvxVR, HvxVR,
19197 /* V6_vabsub_alt */
19198 HvxVR, HvxVR,
19199 /* V6_vabsuh_alt */
19200 HvxVR, HvxVR,
19201 /* V6_vabsuw_alt */
19202 HvxVR, HvxVR,
19203 /* V6_vabsw_alt */
19204 HvxVR, HvxVR,
19205 /* V6_vabsw_sat_alt */
19206 HvxVR, HvxVR,
19207 /* V6_vaddb_alt */
19208 HvxVR, HvxVR, HvxVR,
19209 /* V6_vaddb_dv_alt */
19210 HvxWR, HvxWR, HvxWR,
19211 /* V6_vaddbnq_alt */
19212 HvxVR, HvxQR, HvxVR, HvxVR,
19213 /* V6_vaddbq_alt */
19214 HvxVR, HvxQR, HvxVR, HvxVR,
19215 /* V6_vaddbsat_alt */
19216 HvxVR, HvxVR, HvxVR,
19217 /* V6_vaddbsat_dv_alt */
19218 HvxWR, HvxWR, HvxWR,
19219 /* V6_vaddh_alt */
19220 HvxVR, HvxVR, HvxVR,
19221 /* V6_vaddh_dv_alt */
19222 HvxWR, HvxWR, HvxWR,
19223 /* V6_vaddhnq_alt */
19224 HvxVR, HvxQR, HvxVR, HvxVR,
19225 /* V6_vaddhq_alt */
19226 HvxVR, HvxQR, HvxVR, HvxVR,
19227 /* V6_vaddhsat_alt */
19228 HvxVR, HvxVR, HvxVR,
19229 /* V6_vaddhsat_dv_alt */
19230 HvxWR, HvxWR, HvxWR,
19231 /* V6_vaddhw_acc_alt */
19232 HvxWR, HvxWR, HvxVR, HvxVR,
19233 /* V6_vaddhw_alt */
19234 HvxWR, HvxVR, HvxVR,
19235 /* V6_vaddubh_acc_alt */
19236 HvxWR, HvxWR, HvxVR, HvxVR,
19237 /* V6_vaddubh_alt */
19238 HvxWR, HvxVR, HvxVR,
19239 /* V6_vaddubsat_alt */
19240 HvxVR, HvxVR, HvxVR,
19241 /* V6_vaddubsat_dv_alt */
19242 HvxWR, HvxWR, HvxWR,
19243 /* V6_vadduhsat_alt */
19244 HvxVR, HvxVR, HvxVR,
19245 /* V6_vadduhsat_dv_alt */
19246 HvxWR, HvxWR, HvxWR,
19247 /* V6_vadduhw_acc_alt */
19248 HvxWR, HvxWR, HvxVR, HvxVR,
19249 /* V6_vadduhw_alt */
19250 HvxWR, HvxVR, HvxVR,
19251 /* V6_vadduwsat_alt */
19252 HvxVR, HvxVR, HvxVR,
19253 /* V6_vadduwsat_dv_alt */
19254 HvxWR, HvxWR, HvxWR,
19255 /* V6_vaddw_alt */
19256 HvxVR, HvxVR, HvxVR,
19257 /* V6_vaddw_dv_alt */
19258 HvxWR, HvxWR, HvxWR,
19259 /* V6_vaddwnq_alt */
19260 HvxVR, HvxQR, HvxVR, HvxVR,
19261 /* V6_vaddwq_alt */
19262 HvxVR, HvxQR, HvxVR, HvxVR,
19263 /* V6_vaddwsat_alt */
19264 HvxVR, HvxVR, HvxVR,
19265 /* V6_vaddwsat_dv_alt */
19266 HvxWR, HvxWR, HvxWR,
19267 /* V6_vandnqrt_acc_alt */
19268 HvxVR, HvxVR, HvxQR, IntRegs,
19269 /* V6_vandnqrt_alt */
19270 HvxVR, HvxQR, IntRegs,
19271 /* V6_vandqrt_acc_alt */
19272 HvxVR, HvxVR, HvxQR, IntRegs,
19273 /* V6_vandqrt_alt */
19274 HvxVR, HvxQR, IntRegs,
19275 /* V6_vandvrt_acc_alt */
19276 HvxQR, HvxQR, HvxVR, IntRegs,
19277 /* V6_vandvrt_alt */
19278 HvxQR, HvxVR, IntRegs,
19279 /* V6_vaslh_acc_alt */
19280 HvxVR, HvxVR, HvxVR, IntRegs,
19281 /* V6_vaslh_alt */
19282 HvxVR, HvxVR, IntRegs,
19283 /* V6_vaslhv_alt */
19284 HvxVR, HvxVR, HvxVR,
19285 /* V6_vaslw_acc_alt */
19286 HvxVR, HvxVR, HvxVR, IntRegs,
19287 /* V6_vaslw_alt */
19288 HvxVR, HvxVR, IntRegs,
19289 /* V6_vaslwv_alt */
19290 HvxVR, HvxVR, HvxVR,
19291 /* V6_vasr_into_alt */
19292 HvxWR, HvxWR, HvxVR, HvxVR,
19293 /* V6_vasrh_acc_alt */
19294 HvxVR, HvxVR, HvxVR, IntRegs,
19295 /* V6_vasrh_alt */
19296 HvxVR, HvxVR, IntRegs,
19297 /* V6_vasrhv_alt */
19298 HvxVR, HvxVR, HvxVR,
19299 /* V6_vasrw_acc_alt */
19300 HvxVR, HvxVR, HvxVR, IntRegs,
19301 /* V6_vasrw_alt */
19302 HvxVR, HvxVR, IntRegs,
19303 /* V6_vasrwv_alt */
19304 HvxVR, HvxVR, HvxVR,
19305 /* V6_vassignp */
19306 HvxWR, HvxWR,
19307 /* V6_vavgb_alt */
19308 HvxVR, HvxVR, HvxVR,
19309 /* V6_vavgbrnd_alt */
19310 HvxVR, HvxVR, HvxVR,
19311 /* V6_vavgh_alt */
19312 HvxVR, HvxVR, HvxVR,
19313 /* V6_vavghrnd_alt */
19314 HvxVR, HvxVR, HvxVR,
19315 /* V6_vavgub_alt */
19316 HvxVR, HvxVR, HvxVR,
19317 /* V6_vavgubrnd_alt */
19318 HvxVR, HvxVR, HvxVR,
19319 /* V6_vavguh_alt */
19320 HvxVR, HvxVR, HvxVR,
19321 /* V6_vavguhrnd_alt */
19322 HvxVR, HvxVR, HvxVR,
19323 /* V6_vavguw_alt */
19324 HvxVR, HvxVR, HvxVR,
19325 /* V6_vavguwrnd_alt */
19326 HvxVR, HvxVR, HvxVR,
19327 /* V6_vavgw_alt */
19328 HvxVR, HvxVR, HvxVR,
19329 /* V6_vavgwrnd_alt */
19330 HvxVR, HvxVR, HvxVR,
19331 /* V6_vcl0h_alt */
19332 HvxVR, HvxVR,
19333 /* V6_vcl0w_alt */
19334 HvxVR, HvxVR,
19335 /* V6_vd0 */
19336 HvxVR,
19337 /* V6_vdd0 */
19338 HvxWR,
19339 /* V6_vdealb4w_alt */
19340 HvxVR, HvxVR, HvxVR,
19341 /* V6_vdealb_alt */
19342 HvxVR, HvxVR,
19343 /* V6_vdealh_alt */
19344 HvxVR, HvxVR,
19345 /* V6_vdmpybus_acc_alt */
19346 HvxVR, HvxVR, HvxVR, IntRegs,
19347 /* V6_vdmpybus_alt */
19348 HvxVR, HvxVR, IntRegs,
19349 /* V6_vdmpybus_dv_acc_alt */
19350 HvxWR, HvxWR, HvxWR, IntRegs,
19351 /* V6_vdmpybus_dv_alt */
19352 HvxWR, HvxWR, IntRegs,
19353 /* V6_vdmpyhb_acc_alt */
19354 HvxVR, HvxVR, HvxVR, IntRegs,
19355 /* V6_vdmpyhb_alt */
19356 HvxVR, HvxVR, IntRegs,
19357 /* V6_vdmpyhb_dv_acc_alt */
19358 HvxWR, HvxWR, HvxWR, IntRegs,
19359 /* V6_vdmpyhb_dv_alt */
19360 HvxWR, HvxWR, IntRegs,
19361 /* V6_vdmpyhisat_acc_alt */
19362 HvxVR, HvxVR, HvxWR, IntRegs,
19363 /* V6_vdmpyhisat_alt */
19364 HvxVR, HvxWR, IntRegs,
19365 /* V6_vdmpyhsat_acc_alt */
19366 HvxVR, HvxVR, HvxVR, IntRegs,
19367 /* V6_vdmpyhsat_alt */
19368 HvxVR, HvxVR, IntRegs,
19369 /* V6_vdmpyhsuisat_acc_alt */
19370 HvxVR, HvxVR, HvxWR, IntRegs,
19371 /* V6_vdmpyhsuisat_alt */
19372 HvxVR, HvxWR, IntRegs,
19373 /* V6_vdmpyhsusat_acc_alt */
19374 HvxVR, HvxVR, HvxVR, IntRegs,
19375 /* V6_vdmpyhsusat_alt */
19376 HvxVR, HvxVR, IntRegs,
19377 /* V6_vdmpyhvsat_acc_alt */
19378 HvxVR, HvxVR, HvxVR, HvxVR,
19379 /* V6_vdmpyhvsat_alt */
19380 HvxVR, HvxVR, HvxVR,
19381 /* V6_vdsaduh_acc_alt */
19382 HvxWR, HvxWR, HvxWR, IntRegs,
19383 /* V6_vdsaduh_alt */
19384 HvxWR, HvxWR, IntRegs,
19385 /* V6_vgathermh_pseudo */
19386 IntRegs, s4_0Imm, IntRegs, ModRegs, HvxVR,
19387 /* V6_vgathermhq_pseudo */
19388 IntRegs, s4_0Imm, HvxQR, IntRegs, ModRegs, HvxVR,
19389 /* V6_vgathermhw_pseudo */
19390 IntRegs, s4_0Imm, IntRegs, ModRegs, HvxWR,
19391 /* V6_vgathermhwq_pseudo */
19392 IntRegs, s4_0Imm, HvxQR, IntRegs, ModRegs, HvxWR,
19393 /* V6_vgathermw_pseudo */
19394 IntRegs, s4_0Imm, IntRegs, ModRegs, HvxVR,
19395 /* V6_vgathermwq_pseudo */
19396 IntRegs, s4_0Imm, HvxQR, IntRegs, ModRegs, HvxVR,
19397 /* V6_vlsrh_alt */
19398 HvxVR, HvxVR, IntRegs,
19399 /* V6_vlsrhv_alt */
19400 HvxVR, HvxVR, HvxVR,
19401 /* V6_vlsrw_alt */
19402 HvxVR, HvxVR, IntRegs,
19403 /* V6_vlsrwv_alt */
19404 HvxVR, HvxVR, HvxVR,
19405 /* V6_vmaxb_alt */
19406 HvxVR, HvxVR, HvxVR,
19407 /* V6_vmaxh_alt */
19408 HvxVR, HvxVR, HvxVR,
19409 /* V6_vmaxub_alt */
19410 HvxVR, HvxVR, HvxVR,
19411 /* V6_vmaxuh_alt */
19412 HvxVR, HvxVR, HvxVR,
19413 /* V6_vmaxw_alt */
19414 HvxVR, HvxVR, HvxVR,
19415 /* V6_vminb_alt */
19416 HvxVR, HvxVR, HvxVR,
19417 /* V6_vminh_alt */
19418 HvxVR, HvxVR, HvxVR,
19419 /* V6_vminub_alt */
19420 HvxVR, HvxVR, HvxVR,
19421 /* V6_vminuh_alt */
19422 HvxVR, HvxVR, HvxVR,
19423 /* V6_vminw_alt */
19424 HvxVR, HvxVR, HvxVR,
19425 /* V6_vmpabus_acc_alt */
19426 HvxWR, HvxWR, HvxWR, IntRegs,
19427 /* V6_vmpabus_alt */
19428 HvxWR, HvxWR, IntRegs,
19429 /* V6_vmpabusv_alt */
19430 HvxWR, HvxWR, HvxWR,
19431 /* V6_vmpabuu_acc_alt */
19432 HvxWR, HvxWR, HvxWR, IntRegs,
19433 /* V6_vmpabuu_alt */
19434 HvxWR, HvxWR, IntRegs,
19435 /* V6_vmpabuuv_alt */
19436 HvxWR, HvxWR, HvxWR,
19437 /* V6_vmpahb_acc_alt */
19438 HvxWR, HvxWR, HvxWR, IntRegs,
19439 /* V6_vmpahb_alt */
19440 HvxWR, HvxWR, IntRegs,
19441 /* V6_vmpauhb_acc_alt */
19442 HvxWR, HvxWR, HvxWR, IntRegs,
19443 /* V6_vmpauhb_alt */
19444 HvxWR, HvxWR, IntRegs,
19445 /* V6_vmpybus_acc_alt */
19446 HvxWR, HvxWR, HvxVR, IntRegs,
19447 /* V6_vmpybus_alt */
19448 HvxWR, HvxVR, IntRegs,
19449 /* V6_vmpybusv_acc_alt */
19450 HvxWR, HvxWR, HvxVR, HvxVR,
19451 /* V6_vmpybusv_alt */
19452 HvxWR, HvxVR, HvxVR,
19453 /* V6_vmpybv_acc_alt */
19454 HvxWR, HvxWR, HvxVR, HvxVR,
19455 /* V6_vmpybv_alt */
19456 HvxWR, HvxVR, HvxVR,
19457 /* V6_vmpyewuh_alt */
19458 HvxVR, HvxVR, HvxVR,
19459 /* V6_vmpyh_acc_alt */
19460 HvxWR, HvxWR, HvxVR, IntRegs,
19461 /* V6_vmpyh_alt */
19462 HvxWR, HvxVR, IntRegs,
19463 /* V6_vmpyhsat_acc_alt */
19464 HvxWR, HvxWR, HvxVR, IntRegs,
19465 /* V6_vmpyhsrs_alt */
19466 HvxVR, HvxVR, IntRegs,
19467 /* V6_vmpyhss_alt */
19468 HvxVR, HvxVR, IntRegs,
19469 /* V6_vmpyhus_acc_alt */
19470 HvxWR, HvxWR, HvxVR, HvxVR,
19471 /* V6_vmpyhus_alt */
19472 HvxWR, HvxVR, HvxVR,
19473 /* V6_vmpyhv_acc_alt */
19474 HvxWR, HvxWR, HvxVR, HvxVR,
19475 /* V6_vmpyhv_alt */
19476 HvxWR, HvxVR, HvxVR,
19477 /* V6_vmpyhvsrs_alt */
19478 HvxVR, HvxVR, HvxVR,
19479 /* V6_vmpyiewh_acc_alt */
19480 HvxVR, HvxVR, HvxVR, HvxVR,
19481 /* V6_vmpyiewuh_acc_alt */
19482 HvxVR, HvxVR, HvxVR, HvxVR,
19483 /* V6_vmpyiewuh_alt */
19484 HvxVR, HvxVR, HvxVR,
19485 /* V6_vmpyih_acc_alt */
19486 HvxVR, HvxVR, HvxVR, HvxVR,
19487 /* V6_vmpyih_alt */
19488 HvxVR, HvxVR, HvxVR,
19489 /* V6_vmpyihb_acc_alt */
19490 HvxVR, HvxVR, HvxVR, IntRegs,
19491 /* V6_vmpyihb_alt */
19492 HvxVR, HvxVR, IntRegs,
19493 /* V6_vmpyiowh_alt */
19494 HvxVR, HvxVR, HvxVR,
19495 /* V6_vmpyiwb_acc_alt */
19496 HvxVR, HvxVR, HvxVR, IntRegs,
19497 /* V6_vmpyiwb_alt */
19498 HvxVR, HvxVR, IntRegs,
19499 /* V6_vmpyiwh_acc_alt */
19500 HvxVR, HvxVR, HvxVR, IntRegs,
19501 /* V6_vmpyiwh_alt */
19502 HvxVR, HvxVR, IntRegs,
19503 /* V6_vmpyiwub_acc_alt */
19504 HvxVR, HvxVR, HvxVR, IntRegs,
19505 /* V6_vmpyiwub_alt */
19506 HvxVR, HvxVR, IntRegs,
19507 /* V6_vmpyowh_alt */
19508 HvxVR, HvxVR, HvxVR,
19509 /* V6_vmpyowh_rnd_alt */
19510 HvxVR, HvxVR, HvxVR,
19511 /* V6_vmpyowh_rnd_sacc_alt */
19512 HvxVR, HvxVR, HvxVR, HvxVR,
19513 /* V6_vmpyowh_sacc_alt */
19514 HvxVR, HvxVR, HvxVR, HvxVR,
19515 /* V6_vmpyub_acc_alt */
19516 HvxWR, HvxWR, HvxVR, IntRegs,
19517 /* V6_vmpyub_alt */
19518 HvxWR, HvxVR, IntRegs,
19519 /* V6_vmpyubv_acc_alt */
19520 HvxWR, HvxWR, HvxVR, HvxVR,
19521 /* V6_vmpyubv_alt */
19522 HvxWR, HvxVR, HvxVR,
19523 /* V6_vmpyuh_acc_alt */
19524 HvxWR, HvxWR, HvxVR, IntRegs,
19525 /* V6_vmpyuh_alt */
19526 HvxWR, HvxVR, IntRegs,
19527 /* V6_vmpyuhv_acc_alt */
19528 HvxWR, HvxWR, HvxVR, HvxVR,
19529 /* V6_vmpyuhv_alt */
19530 HvxWR, HvxVR, HvxVR,
19531 /* V6_vnavgb_alt */
19532 HvxVR, HvxVR, HvxVR,
19533 /* V6_vnavgh_alt */
19534 HvxVR, HvxVR, HvxVR,
19535 /* V6_vnavgub_alt */
19536 HvxVR, HvxVR, HvxVR,
19537 /* V6_vnavgw_alt */
19538 HvxVR, HvxVR, HvxVR,
19539 /* V6_vnormamth_alt */
19540 HvxVR, HvxVR,
19541 /* V6_vnormamtw_alt */
19542 HvxVR, HvxVR,
19543 /* V6_vpackeb_alt */
19544 HvxVR, HvxVR, HvxVR,
19545 /* V6_vpackeh_alt */
19546 HvxVR, HvxVR, HvxVR,
19547 /* V6_vpackhb_sat_alt */
19548 HvxVR, HvxVR, HvxVR,
19549 /* V6_vpackhub_sat_alt */
19550 HvxVR, HvxVR, HvxVR,
19551 /* V6_vpackob_alt */
19552 HvxVR, HvxVR, HvxVR,
19553 /* V6_vpackoh_alt */
19554 HvxVR, HvxVR, HvxVR,
19555 /* V6_vpackwh_sat_alt */
19556 HvxVR, HvxVR, HvxVR,
19557 /* V6_vpackwuh_sat_alt */
19558 HvxVR, HvxVR, HvxVR,
19559 /* V6_vpopcounth_alt */
19560 HvxVR, HvxVR,
19561 /* V6_vrmpybub_rtt_acc_alt */
19562 HvxWR, HvxWR, HvxVR, DoubleRegs,
19563 /* V6_vrmpybub_rtt_alt */
19564 HvxWR, HvxVR, DoubleRegs,
19565 /* V6_vrmpybus_acc_alt */
19566 HvxVR, HvxVR, HvxVR, IntRegs,
19567 /* V6_vrmpybus_alt */
19568 HvxVR, HvxVR, IntRegs,
19569 /* V6_vrmpybusi_acc_alt */
19570 HvxWR, HvxWR, HvxWR, IntRegs, u1_0Imm,
19571 /* V6_vrmpybusi_alt */
19572 HvxWR, HvxWR, IntRegs, u1_0Imm,
19573 /* V6_vrmpybusv_acc_alt */
19574 HvxVR, HvxVR, HvxVR, HvxVR,
19575 /* V6_vrmpybusv_alt */
19576 HvxVR, HvxVR, HvxVR,
19577 /* V6_vrmpybv_acc_alt */
19578 HvxVR, HvxVR, HvxVR, HvxVR,
19579 /* V6_vrmpybv_alt */
19580 HvxVR, HvxVR, HvxVR,
19581 /* V6_vrmpyub_acc_alt */
19582 HvxVR, HvxVR, HvxVR, IntRegs,
19583 /* V6_vrmpyub_alt */
19584 HvxVR, HvxVR, IntRegs,
19585 /* V6_vrmpyub_rtt_acc_alt */
19586 HvxWR, HvxWR, HvxVR, DoubleRegs,
19587 /* V6_vrmpyub_rtt_alt */
19588 HvxWR, HvxVR, DoubleRegs,
19589 /* V6_vrmpyubi_acc_alt */
19590 HvxWR, HvxWR, HvxWR, IntRegs, u1_0Imm,
19591 /* V6_vrmpyubi_alt */
19592 HvxWR, HvxWR, IntRegs, u1_0Imm,
19593 /* V6_vrmpyubv_acc_alt */
19594 HvxVR, HvxVR, HvxVR, HvxVR,
19595 /* V6_vrmpyubv_alt */
19596 HvxVR, HvxVR, HvxVR,
19597 /* V6_vrotr_alt */
19598 HvxVR, HvxVR, HvxVR,
19599 /* V6_vroundhb_alt */
19600 HvxVR, HvxVR, HvxVR,
19601 /* V6_vroundhub_alt */
19602 HvxVR, HvxVR, HvxVR,
19603 /* V6_vrounduhub_alt */
19604 HvxVR, HvxVR, HvxVR,
19605 /* V6_vrounduwuh_alt */
19606 HvxVR, HvxVR, HvxVR,
19607 /* V6_vroundwh_alt */
19608 HvxVR, HvxVR, HvxVR,
19609 /* V6_vroundwuh_alt */
19610 HvxVR, HvxVR, HvxVR,
19611 /* V6_vrsadubi_acc_alt */
19612 HvxWR, HvxWR, HvxWR, IntRegs, u1_0Imm,
19613 /* V6_vrsadubi_alt */
19614 HvxWR, HvxWR, IntRegs, u1_0Imm,
19615 /* V6_vsathub_alt */
19616 HvxVR, HvxVR, HvxVR,
19617 /* V6_vsatuwuh_alt */
19618 HvxVR, HvxVR, HvxVR,
19619 /* V6_vsatwh_alt */
19620 HvxVR, HvxVR, HvxVR,
19621 /* V6_vsb_alt */
19622 HvxWR, HvxVR,
19623 /* V6_vscattermh_add_alt */
19624 IntRegs, ModRegs, HvxVR, HvxVR,
19625 /* V6_vscattermh_alt */
19626 IntRegs, ModRegs, HvxVR, HvxVR,
19627 /* V6_vscattermhq_alt */
19628 HvxQR, IntRegs, ModRegs, HvxVR, HvxVR,
19629 /* V6_vscattermw_add_alt */
19630 IntRegs, ModRegs, HvxVR, HvxVR,
19631 /* V6_vscattermw_alt */
19632 IntRegs, ModRegs, HvxVR, HvxVR,
19633 /* V6_vscattermwh_add_alt */
19634 IntRegs, ModRegs, HvxWR, HvxVR,
19635 /* V6_vscattermwh_alt */
19636 IntRegs, ModRegs, HvxWR, HvxVR,
19637 /* V6_vscattermwhq_alt */
19638 HvxQR, IntRegs, ModRegs, HvxWR, HvxVR,
19639 /* V6_vscattermwq_alt */
19640 HvxQR, IntRegs, ModRegs, HvxVR, HvxVR,
19641 /* V6_vsh_alt */
19642 HvxWR, HvxVR,
19643 /* V6_vshufeh_alt */
19644 HvxVR, HvxVR, HvxVR,
19645 /* V6_vshuffb_alt */
19646 HvxVR, HvxVR,
19647 /* V6_vshuffeb_alt */
19648 HvxVR, HvxVR, HvxVR,
19649 /* V6_vshuffh_alt */
19650 HvxVR, HvxVR,
19651 /* V6_vshuffob_alt */
19652 HvxVR, HvxVR, HvxVR,
19653 /* V6_vshufoeb_alt */
19654 HvxWR, HvxVR, HvxVR,
19655 /* V6_vshufoeh_alt */
19656 HvxWR, HvxVR, HvxVR,
19657 /* V6_vshufoh_alt */
19658 HvxVR, HvxVR, HvxVR,
19659 /* V6_vsubb_alt */
19660 HvxVR, HvxVR, HvxVR,
19661 /* V6_vsubb_dv_alt */
19662 HvxWR, HvxWR, HvxWR,
19663 /* V6_vsubbnq_alt */
19664 HvxVR, HvxQR, HvxVR, HvxVR,
19665 /* V6_vsubbq_alt */
19666 HvxVR, HvxQR, HvxVR, HvxVR,
19667 /* V6_vsubbsat_alt */
19668 HvxVR, HvxVR, HvxVR,
19669 /* V6_vsubbsat_dv_alt */
19670 HvxWR, HvxWR, HvxWR,
19671 /* V6_vsubh_alt */
19672 HvxVR, HvxVR, HvxVR,
19673 /* V6_vsubh_dv_alt */
19674 HvxWR, HvxWR, HvxWR,
19675 /* V6_vsubhnq_alt */
19676 HvxVR, HvxQR, HvxVR, HvxVR,
19677 /* V6_vsubhq_alt */
19678 HvxVR, HvxQR, HvxVR, HvxVR,
19679 /* V6_vsubhsat_alt */
19680 HvxVR, HvxVR, HvxVR,
19681 /* V6_vsubhsat_dv_alt */
19682 HvxWR, HvxWR, HvxWR,
19683 /* V6_vsubhw_alt */
19684 HvxWR, HvxVR, HvxVR,
19685 /* V6_vsububh_alt */
19686 HvxWR, HvxVR, HvxVR,
19687 /* V6_vsububsat_alt */
19688 HvxVR, HvxVR, HvxVR,
19689 /* V6_vsububsat_dv_alt */
19690 HvxWR, HvxWR, HvxWR,
19691 /* V6_vsubuhsat_alt */
19692 HvxVR, HvxVR, HvxVR,
19693 /* V6_vsubuhsat_dv_alt */
19694 HvxWR, HvxWR, HvxWR,
19695 /* V6_vsubuhw_alt */
19696 HvxWR, HvxVR, HvxVR,
19697 /* V6_vsubuwsat_alt */
19698 HvxVR, HvxVR, HvxVR,
19699 /* V6_vsubuwsat_dv_alt */
19700 HvxWR, HvxWR, HvxWR,
19701 /* V6_vsubw_alt */
19702 HvxVR, HvxVR, HvxVR,
19703 /* V6_vsubw_dv_alt */
19704 HvxWR, HvxWR, HvxWR,
19705 /* V6_vsubwnq_alt */
19706 HvxVR, HvxQR, HvxVR, HvxVR,
19707 /* V6_vsubwq_alt */
19708 HvxVR, HvxQR, HvxVR, HvxVR,
19709 /* V6_vsubwsat_alt */
19710 HvxVR, HvxVR, HvxVR,
19711 /* V6_vsubwsat_dv_alt */
19712 HvxWR, HvxWR, HvxWR,
19713 /* V6_vtmpyb_acc_alt */
19714 HvxWR, HvxWR, HvxWR, IntRegs,
19715 /* V6_vtmpyb_alt */
19716 HvxWR, HvxWR, IntRegs,
19717 /* V6_vtmpybus_acc_alt */
19718 HvxWR, HvxWR, HvxWR, IntRegs,
19719 /* V6_vtmpybus_alt */
19720 HvxWR, HvxWR, IntRegs,
19721 /* V6_vtmpyhb_acc_alt */
19722 HvxWR, HvxWR, HvxWR, IntRegs,
19723 /* V6_vtmpyhb_alt */
19724 HvxWR, HvxWR, IntRegs,
19725 /* V6_vtran2x2_map */
19726 HvxVR, HvxVR, HvxVR, HvxVR, IntRegs,
19727 /* V6_vunpackb_alt */
19728 HvxWR, HvxVR,
19729 /* V6_vunpackh_alt */
19730 HvxWR, HvxVR,
19731 /* V6_vunpackob_alt */
19732 HvxWR, HvxWR, HvxVR,
19733 /* V6_vunpackoh_alt */
19734 HvxWR, HvxWR, HvxVR,
19735 /* V6_vunpackub_alt */
19736 HvxWR, HvxVR,
19737 /* V6_vunpackuh_alt */
19738 HvxWR, HvxVR,
19739 /* V6_vzb_alt */
19740 HvxWR, HvxVR,
19741 /* V6_vzh_alt */
19742 HvxWR, HvxVR,
19743 /* V6_zld0 */
19744 IntRegs,
19745 /* V6_zldp0 */
19746 PredRegs, IntRegs,
19747 /* Y2_crswap_old */
19748 IntRegs, IntRegs,
19749 /* Y2_dcfetch */
19750 IntRegs,
19751 /* Y2_k1lock_map */
19752 /* Y2_k1unlock_map */
19753 /* dup_A2_add */
19754 IntRegs, IntRegs, IntRegs,
19755 /* dup_A2_addi */
19756 IntRegs, IntRegs, s32_0Imm,
19757 /* dup_A2_andir */
19758 IntRegs, IntRegs, s32_0Imm,
19759 /* dup_A2_combineii */
19760 DoubleRegs, s32_0Imm, s8_0Imm,
19761 /* dup_A2_sxtb */
19762 IntRegs, IntRegs,
19763 /* dup_A2_sxth */
19764 IntRegs, IntRegs,
19765 /* dup_A2_tfr */
19766 IntRegs, IntRegs,
19767 /* dup_A2_tfrsi */
19768 IntRegs, s32_0Imm,
19769 /* dup_A2_zxtb */
19770 IntRegs, IntRegs,
19771 /* dup_A2_zxth */
19772 IntRegs, IntRegs,
19773 /* dup_A4_combineii */
19774 DoubleRegs, s8_0Imm, u32_0Imm,
19775 /* dup_A4_combineir */
19776 DoubleRegs, s32_0Imm, IntRegs,
19777 /* dup_A4_combineri */
19778 DoubleRegs, IntRegs, s32_0Imm,
19779 /* dup_C2_cmoveif */
19780 IntRegs, PredRegs, s32_0Imm,
19781 /* dup_C2_cmoveit */
19782 IntRegs, PredRegs, s32_0Imm,
19783 /* dup_C2_cmovenewif */
19784 IntRegs, PredRegs, s32_0Imm,
19785 /* dup_C2_cmovenewit */
19786 IntRegs, PredRegs, s32_0Imm,
19787 /* dup_C2_cmpeqi */
19788 PredRegs, IntRegs, s32_0Imm,
19789 /* dup_L2_deallocframe */
19790 DoubleRegs, IntRegs,
19791 /* dup_L2_loadrb_io */
19792 IntRegs, IntRegs, s32_0Imm,
19793 /* dup_L2_loadrd_io */
19794 DoubleRegs, IntRegs, s29_3Imm,
19795 /* dup_L2_loadrh_io */
19796 IntRegs, IntRegs, s31_1Imm,
19797 /* dup_L2_loadri_io */
19798 IntRegs, IntRegs, s30_2Imm,
19799 /* dup_L2_loadrub_io */
19800 IntRegs, IntRegs, s32_0Imm,
19801 /* dup_L2_loadruh_io */
19802 IntRegs, IntRegs, s31_1Imm,
19803 /* dup_S2_allocframe */
19804 IntRegs, IntRegs, u11_3Imm,
19805 /* dup_S2_storerb_io */
19806 IntRegs, s32_0Imm, IntRegs,
19807 /* dup_S2_storerd_io */
19808 IntRegs, s29_3Imm, DoubleRegs,
19809 /* dup_S2_storerh_io */
19810 IntRegs, s31_1Imm, IntRegs,
19811 /* dup_S2_storeri_io */
19812 IntRegs, s30_2Imm, IntRegs,
19813 /* dup_S4_storeirb_io */
19814 IntRegs, u6_0Imm, s32_0Imm,
19815 /* dup_S4_storeiri_io */
19816 IntRegs, u6_2Imm, s32_0Imm,
19817 /* A2_abs */
19818 IntRegs, IntRegs,
19819 /* A2_absp */
19820 DoubleRegs, DoubleRegs,
19821 /* A2_abssat */
19822 IntRegs, IntRegs,
19823 /* A2_add */
19824 IntRegs, IntRegs, IntRegs,
19825 /* A2_addh_h16_hh */
19826 IntRegs, IntRegs, IntRegs,
19827 /* A2_addh_h16_hl */
19828 IntRegs, IntRegs, IntRegs,
19829 /* A2_addh_h16_lh */
19830 IntRegs, IntRegs, IntRegs,
19831 /* A2_addh_h16_ll */
19832 IntRegs, IntRegs, IntRegs,
19833 /* A2_addh_h16_sat_hh */
19834 IntRegs, IntRegs, IntRegs,
19835 /* A2_addh_h16_sat_hl */
19836 IntRegs, IntRegs, IntRegs,
19837 /* A2_addh_h16_sat_lh */
19838 IntRegs, IntRegs, IntRegs,
19839 /* A2_addh_h16_sat_ll */
19840 IntRegs, IntRegs, IntRegs,
19841 /* A2_addh_l16_hl */
19842 IntRegs, IntRegs, IntRegs,
19843 /* A2_addh_l16_ll */
19844 IntRegs, IntRegs, IntRegs,
19845 /* A2_addh_l16_sat_hl */
19846 IntRegs, IntRegs, IntRegs,
19847 /* A2_addh_l16_sat_ll */
19848 IntRegs, IntRegs, IntRegs,
19849 /* A2_addi */
19850 IntRegs, IntRegs, s32_0Imm,
19851 /* A2_addp */
19852 DoubleRegs, DoubleRegs, DoubleRegs,
19853 /* A2_addpsat */
19854 DoubleRegs, DoubleRegs, DoubleRegs,
19855 /* A2_addsat */
19856 IntRegs, IntRegs, IntRegs,
19857 /* A2_addsph */
19858 DoubleRegs, DoubleRegs, DoubleRegs,
19859 /* A2_addspl */
19860 DoubleRegs, DoubleRegs, DoubleRegs,
19861 /* A2_and */
19862 IntRegs, IntRegs, IntRegs,
19863 /* A2_andir */
19864 IntRegs, IntRegs, s32_0Imm,
19865 /* A2_andp */
19866 DoubleRegs, DoubleRegs, DoubleRegs,
19867 /* A2_aslh */
19868 IntRegs, IntRegs,
19869 /* A2_asrh */
19870 IntRegs, IntRegs,
19871 /* A2_combine_hh */
19872 IntRegs, IntRegs, IntRegs,
19873 /* A2_combine_hl */
19874 IntRegs, IntRegs, IntRegs,
19875 /* A2_combine_lh */
19876 IntRegs, IntRegs, IntRegs,
19877 /* A2_combine_ll */
19878 IntRegs, IntRegs, IntRegs,
19879 /* A2_combineii */
19880 DoubleRegs, s32_0Imm, s8_0Imm,
19881 /* A2_combinew */
19882 DoubleRegs, IntRegs, IntRegs,
19883 /* A2_max */
19884 IntRegs, IntRegs, IntRegs,
19885 /* A2_maxp */
19886 DoubleRegs, DoubleRegs, DoubleRegs,
19887 /* A2_maxu */
19888 IntRegs, IntRegs, IntRegs,
19889 /* A2_maxup */
19890 DoubleRegs, DoubleRegs, DoubleRegs,
19891 /* A2_min */
19892 IntRegs, IntRegs, IntRegs,
19893 /* A2_minp */
19894 DoubleRegs, DoubleRegs, DoubleRegs,
19895 /* A2_minu */
19896 IntRegs, IntRegs, IntRegs,
19897 /* A2_minup */
19898 DoubleRegs, DoubleRegs, DoubleRegs,
19899 /* A2_negp */
19900 DoubleRegs, DoubleRegs,
19901 /* A2_negsat */
19902 IntRegs, IntRegs,
19903 /* A2_nop */
19904 /* A2_notp */
19905 DoubleRegs, DoubleRegs,
19906 /* A2_or */
19907 IntRegs, IntRegs, IntRegs,
19908 /* A2_orir */
19909 IntRegs, IntRegs, s32_0Imm,
19910 /* A2_orp */
19911 DoubleRegs, DoubleRegs, DoubleRegs,
19912 /* A2_paddf */
19913 IntRegs, PredRegs, IntRegs, IntRegs,
19914 /* A2_paddfnew */
19915 IntRegs, PredRegs, IntRegs, IntRegs,
19916 /* A2_paddif */
19917 IntRegs, PredRegs, IntRegs, s32_0Imm,
19918 /* A2_paddifnew */
19919 IntRegs, PredRegs, IntRegs, s32_0Imm,
19920 /* A2_paddit */
19921 IntRegs, PredRegs, IntRegs, s32_0Imm,
19922 /* A2_padditnew */
19923 IntRegs, PredRegs, IntRegs, s32_0Imm,
19924 /* A2_paddt */
19925 IntRegs, PredRegs, IntRegs, IntRegs,
19926 /* A2_paddtnew */
19927 IntRegs, PredRegs, IntRegs, IntRegs,
19928 /* A2_pandf */
19929 IntRegs, PredRegs, IntRegs, IntRegs,
19930 /* A2_pandfnew */
19931 IntRegs, PredRegs, IntRegs, IntRegs,
19932 /* A2_pandt */
19933 IntRegs, PredRegs, IntRegs, IntRegs,
19934 /* A2_pandtnew */
19935 IntRegs, PredRegs, IntRegs, IntRegs,
19936 /* A2_porf */
19937 IntRegs, PredRegs, IntRegs, IntRegs,
19938 /* A2_porfnew */
19939 IntRegs, PredRegs, IntRegs, IntRegs,
19940 /* A2_port */
19941 IntRegs, PredRegs, IntRegs, IntRegs,
19942 /* A2_portnew */
19943 IntRegs, PredRegs, IntRegs, IntRegs,
19944 /* A2_psubf */
19945 IntRegs, PredRegs, IntRegs, IntRegs,
19946 /* A2_psubfnew */
19947 IntRegs, PredRegs, IntRegs, IntRegs,
19948 /* A2_psubt */
19949 IntRegs, PredRegs, IntRegs, IntRegs,
19950 /* A2_psubtnew */
19951 IntRegs, PredRegs, IntRegs, IntRegs,
19952 /* A2_pxorf */
19953 IntRegs, PredRegs, IntRegs, IntRegs,
19954 /* A2_pxorfnew */
19955 IntRegs, PredRegs, IntRegs, IntRegs,
19956 /* A2_pxort */
19957 IntRegs, PredRegs, IntRegs, IntRegs,
19958 /* A2_pxortnew */
19959 IntRegs, PredRegs, IntRegs, IntRegs,
19960 /* A2_roundsat */
19961 IntRegs, DoubleRegs,
19962 /* A2_sat */
19963 IntRegs, DoubleRegs,
19964 /* A2_satb */
19965 IntRegs, IntRegs,
19966 /* A2_sath */
19967 IntRegs, IntRegs,
19968 /* A2_satub */
19969 IntRegs, IntRegs,
19970 /* A2_satuh */
19971 IntRegs, IntRegs,
19972 /* A2_sub */
19973 IntRegs, IntRegs, IntRegs,
19974 /* A2_subh_h16_hh */
19975 IntRegs, IntRegs, IntRegs,
19976 /* A2_subh_h16_hl */
19977 IntRegs, IntRegs, IntRegs,
19978 /* A2_subh_h16_lh */
19979 IntRegs, IntRegs, IntRegs,
19980 /* A2_subh_h16_ll */
19981 IntRegs, IntRegs, IntRegs,
19982 /* A2_subh_h16_sat_hh */
19983 IntRegs, IntRegs, IntRegs,
19984 /* A2_subh_h16_sat_hl */
19985 IntRegs, IntRegs, IntRegs,
19986 /* A2_subh_h16_sat_lh */
19987 IntRegs, IntRegs, IntRegs,
19988 /* A2_subh_h16_sat_ll */
19989 IntRegs, IntRegs, IntRegs,
19990 /* A2_subh_l16_hl */
19991 IntRegs, IntRegs, IntRegs,
19992 /* A2_subh_l16_ll */
19993 IntRegs, IntRegs, IntRegs,
19994 /* A2_subh_l16_sat_hl */
19995 IntRegs, IntRegs, IntRegs,
19996 /* A2_subh_l16_sat_ll */
19997 IntRegs, IntRegs, IntRegs,
19998 /* A2_subp */
19999 DoubleRegs, DoubleRegs, DoubleRegs,
20000 /* A2_subri */
20001 IntRegs, s32_0Imm, IntRegs,
20002 /* A2_subsat */
20003 IntRegs, IntRegs, IntRegs,
20004 /* A2_svaddh */
20005 IntRegs, IntRegs, IntRegs,
20006 /* A2_svaddhs */
20007 IntRegs, IntRegs, IntRegs,
20008 /* A2_svadduhs */
20009 IntRegs, IntRegs, IntRegs,
20010 /* A2_svavgh */
20011 IntRegs, IntRegs, IntRegs,
20012 /* A2_svavghs */
20013 IntRegs, IntRegs, IntRegs,
20014 /* A2_svnavgh */
20015 IntRegs, IntRegs, IntRegs,
20016 /* A2_svsubh */
20017 IntRegs, IntRegs, IntRegs,
20018 /* A2_svsubhs */
20019 IntRegs, IntRegs, IntRegs,
20020 /* A2_svsubuhs */
20021 IntRegs, IntRegs, IntRegs,
20022 /* A2_swiz */
20023 IntRegs, IntRegs,
20024 /* A2_sxtb */
20025 IntRegs, IntRegs,
20026 /* A2_sxth */
20027 IntRegs, IntRegs,
20028 /* A2_sxtw */
20029 DoubleRegs, IntRegs,
20030 /* A2_tfr */
20031 IntRegs, IntRegs,
20032 /* A2_tfrcrr */
20033 IntRegs, CtrRegs,
20034 /* A2_tfrih */
20035 IntRegs, IntRegs, u16_0Imm,
20036 /* A2_tfril */
20037 IntRegs, IntRegs, u16_0Imm,
20038 /* A2_tfrrcr */
20039 CtrRegs, IntRegs,
20040 /* A2_tfrsi */
20041 IntRegs, s32_0Imm,
20042 /* A2_vabsh */
20043 DoubleRegs, DoubleRegs,
20044 /* A2_vabshsat */
20045 DoubleRegs, DoubleRegs,
20046 /* A2_vabsw */
20047 DoubleRegs, DoubleRegs,
20048 /* A2_vabswsat */
20049 DoubleRegs, DoubleRegs,
20050 /* A2_vaddh */
20051 DoubleRegs, DoubleRegs, DoubleRegs,
20052 /* A2_vaddhs */
20053 DoubleRegs, DoubleRegs, DoubleRegs,
20054 /* A2_vaddub */
20055 DoubleRegs, DoubleRegs, DoubleRegs,
20056 /* A2_vaddubs */
20057 DoubleRegs, DoubleRegs, DoubleRegs,
20058 /* A2_vadduhs */
20059 DoubleRegs, DoubleRegs, DoubleRegs,
20060 /* A2_vaddw */
20061 DoubleRegs, DoubleRegs, DoubleRegs,
20062 /* A2_vaddws */
20063 DoubleRegs, DoubleRegs, DoubleRegs,
20064 /* A2_vavgh */
20065 DoubleRegs, DoubleRegs, DoubleRegs,
20066 /* A2_vavghcr */
20067 DoubleRegs, DoubleRegs, DoubleRegs,
20068 /* A2_vavghr */
20069 DoubleRegs, DoubleRegs, DoubleRegs,
20070 /* A2_vavgub */
20071 DoubleRegs, DoubleRegs, DoubleRegs,
20072 /* A2_vavgubr */
20073 DoubleRegs, DoubleRegs, DoubleRegs,
20074 /* A2_vavguh */
20075 DoubleRegs, DoubleRegs, DoubleRegs,
20076 /* A2_vavguhr */
20077 DoubleRegs, DoubleRegs, DoubleRegs,
20078 /* A2_vavguw */
20079 DoubleRegs, DoubleRegs, DoubleRegs,
20080 /* A2_vavguwr */
20081 DoubleRegs, DoubleRegs, DoubleRegs,
20082 /* A2_vavgw */
20083 DoubleRegs, DoubleRegs, DoubleRegs,
20084 /* A2_vavgwcr */
20085 DoubleRegs, DoubleRegs, DoubleRegs,
20086 /* A2_vavgwr */
20087 DoubleRegs, DoubleRegs, DoubleRegs,
20088 /* A2_vcmpbeq */
20089 PredRegs, DoubleRegs, DoubleRegs,
20090 /* A2_vcmpbgtu */
20091 PredRegs, DoubleRegs, DoubleRegs,
20092 /* A2_vcmpheq */
20093 PredRegs, DoubleRegs, DoubleRegs,
20094 /* A2_vcmphgt */
20095 PredRegs, DoubleRegs, DoubleRegs,
20096 /* A2_vcmphgtu */
20097 PredRegs, DoubleRegs, DoubleRegs,
20098 /* A2_vcmpweq */
20099 PredRegs, DoubleRegs, DoubleRegs,
20100 /* A2_vcmpwgt */
20101 PredRegs, DoubleRegs, DoubleRegs,
20102 /* A2_vcmpwgtu */
20103 PredRegs, DoubleRegs, DoubleRegs,
20104 /* A2_vconj */
20105 DoubleRegs, DoubleRegs,
20106 /* A2_vmaxb */
20107 DoubleRegs, DoubleRegs, DoubleRegs,
20108 /* A2_vmaxh */
20109 DoubleRegs, DoubleRegs, DoubleRegs,
20110 /* A2_vmaxub */
20111 DoubleRegs, DoubleRegs, DoubleRegs,
20112 /* A2_vmaxuh */
20113 DoubleRegs, DoubleRegs, DoubleRegs,
20114 /* A2_vmaxuw */
20115 DoubleRegs, DoubleRegs, DoubleRegs,
20116 /* A2_vmaxw */
20117 DoubleRegs, DoubleRegs, DoubleRegs,
20118 /* A2_vminb */
20119 DoubleRegs, DoubleRegs, DoubleRegs,
20120 /* A2_vminh */
20121 DoubleRegs, DoubleRegs, DoubleRegs,
20122 /* A2_vminub */
20123 DoubleRegs, DoubleRegs, DoubleRegs,
20124 /* A2_vminuh */
20125 DoubleRegs, DoubleRegs, DoubleRegs,
20126 /* A2_vminuw */
20127 DoubleRegs, DoubleRegs, DoubleRegs,
20128 /* A2_vminw */
20129 DoubleRegs, DoubleRegs, DoubleRegs,
20130 /* A2_vnavgh */
20131 DoubleRegs, DoubleRegs, DoubleRegs,
20132 /* A2_vnavghcr */
20133 DoubleRegs, DoubleRegs, DoubleRegs,
20134 /* A2_vnavghr */
20135 DoubleRegs, DoubleRegs, DoubleRegs,
20136 /* A2_vnavgw */
20137 DoubleRegs, DoubleRegs, DoubleRegs,
20138 /* A2_vnavgwcr */
20139 DoubleRegs, DoubleRegs, DoubleRegs,
20140 /* A2_vnavgwr */
20141 DoubleRegs, DoubleRegs, DoubleRegs,
20142 /* A2_vraddub */
20143 DoubleRegs, DoubleRegs, DoubleRegs,
20144 /* A2_vraddub_acc */
20145 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
20146 /* A2_vrsadub */
20147 DoubleRegs, DoubleRegs, DoubleRegs,
20148 /* A2_vrsadub_acc */
20149 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
20150 /* A2_vsubh */
20151 DoubleRegs, DoubleRegs, DoubleRegs,
20152 /* A2_vsubhs */
20153 DoubleRegs, DoubleRegs, DoubleRegs,
20154 /* A2_vsubub */
20155 DoubleRegs, DoubleRegs, DoubleRegs,
20156 /* A2_vsububs */
20157 DoubleRegs, DoubleRegs, DoubleRegs,
20158 /* A2_vsubuhs */
20159 DoubleRegs, DoubleRegs, DoubleRegs,
20160 /* A2_vsubw */
20161 DoubleRegs, DoubleRegs, DoubleRegs,
20162 /* A2_vsubws */
20163 DoubleRegs, DoubleRegs, DoubleRegs,
20164 /* A2_xor */
20165 IntRegs, IntRegs, IntRegs,
20166 /* A2_xorp */
20167 DoubleRegs, DoubleRegs, DoubleRegs,
20168 /* A2_zxth */
20169 IntRegs, IntRegs,
20170 /* A4_addp_c */
20171 DoubleRegs, PredRegs, DoubleRegs, DoubleRegs, PredRegs,
20172 /* A4_andn */
20173 IntRegs, IntRegs, IntRegs,
20174 /* A4_andnp */
20175 DoubleRegs, DoubleRegs, DoubleRegs,
20176 /* A4_bitsplit */
20177 DoubleRegs, IntRegs, IntRegs,
20178 /* A4_bitspliti */
20179 DoubleRegs, IntRegs, u5_0Imm,
20180 /* A4_boundscheck_hi */
20181 PredRegs, DoubleRegs, DoubleRegs,
20182 /* A4_boundscheck_lo */
20183 PredRegs, DoubleRegs, DoubleRegs,
20184 /* A4_cmpbeq */
20185 PredRegs, IntRegs, IntRegs,
20186 /* A4_cmpbeqi */
20187 PredRegs, IntRegs, u8_0Imm,
20188 /* A4_cmpbgt */
20189 PredRegs, IntRegs, IntRegs,
20190 /* A4_cmpbgti */
20191 PredRegs, IntRegs, s8_0Imm,
20192 /* A4_cmpbgtu */
20193 PredRegs, IntRegs, IntRegs,
20194 /* A4_cmpbgtui */
20195 PredRegs, IntRegs, u32_0Imm,
20196 /* A4_cmpheq */
20197 PredRegs, IntRegs, IntRegs,
20198 /* A4_cmpheqi */
20199 PredRegs, IntRegs, s32_0Imm,
20200 /* A4_cmphgt */
20201 PredRegs, IntRegs, IntRegs,
20202 /* A4_cmphgti */
20203 PredRegs, IntRegs, s32_0Imm,
20204 /* A4_cmphgtu */
20205 PredRegs, IntRegs, IntRegs,
20206 /* A4_cmphgtui */
20207 PredRegs, IntRegs, u32_0Imm,
20208 /* A4_combineii */
20209 DoubleRegs, s8_0Imm, u32_0Imm,
20210 /* A4_combineir */
20211 DoubleRegs, s32_0Imm, IntRegs,
20212 /* A4_combineri */
20213 DoubleRegs, IntRegs, s32_0Imm,
20214 /* A4_cround_ri */
20215 IntRegs, IntRegs, u5_0Imm,
20216 /* A4_cround_rr */
20217 IntRegs, IntRegs, IntRegs,
20218 /* A4_ext */
20219 u26_6Imm,
20220 /* A4_modwrapu */
20221 IntRegs, IntRegs, IntRegs,
20222 /* A4_orn */
20223 IntRegs, IntRegs, IntRegs,
20224 /* A4_ornp */
20225 DoubleRegs, DoubleRegs, DoubleRegs,
20226 /* A4_paslhf */
20227 IntRegs, PredRegs, IntRegs,
20228 /* A4_paslhfnew */
20229 IntRegs, PredRegs, IntRegs,
20230 /* A4_paslht */
20231 IntRegs, PredRegs, IntRegs,
20232 /* A4_paslhtnew */
20233 IntRegs, PredRegs, IntRegs,
20234 /* A4_pasrhf */
20235 IntRegs, PredRegs, IntRegs,
20236 /* A4_pasrhfnew */
20237 IntRegs, PredRegs, IntRegs,
20238 /* A4_pasrht */
20239 IntRegs, PredRegs, IntRegs,
20240 /* A4_pasrhtnew */
20241 IntRegs, PredRegs, IntRegs,
20242 /* A4_psxtbf */
20243 IntRegs, PredRegs, IntRegs,
20244 /* A4_psxtbfnew */
20245 IntRegs, PredRegs, IntRegs,
20246 /* A4_psxtbt */
20247 IntRegs, PredRegs, IntRegs,
20248 /* A4_psxtbtnew */
20249 IntRegs, PredRegs, IntRegs,
20250 /* A4_psxthf */
20251 IntRegs, PredRegs, IntRegs,
20252 /* A4_psxthfnew */
20253 IntRegs, PredRegs, IntRegs,
20254 /* A4_psxtht */
20255 IntRegs, PredRegs, IntRegs,
20256 /* A4_psxthtnew */
20257 IntRegs, PredRegs, IntRegs,
20258 /* A4_pzxtbf */
20259 IntRegs, PredRegs, IntRegs,
20260 /* A4_pzxtbfnew */
20261 IntRegs, PredRegs, IntRegs,
20262 /* A4_pzxtbt */
20263 IntRegs, PredRegs, IntRegs,
20264 /* A4_pzxtbtnew */
20265 IntRegs, PredRegs, IntRegs,
20266 /* A4_pzxthf */
20267 IntRegs, PredRegs, IntRegs,
20268 /* A4_pzxthfnew */
20269 IntRegs, PredRegs, IntRegs,
20270 /* A4_pzxtht */
20271 IntRegs, PredRegs, IntRegs,
20272 /* A4_pzxthtnew */
20273 IntRegs, PredRegs, IntRegs,
20274 /* A4_rcmpeq */
20275 IntRegs, IntRegs, IntRegs,
20276 /* A4_rcmpeqi */
20277 IntRegs, IntRegs, s32_0Imm,
20278 /* A4_rcmpneq */
20279 IntRegs, IntRegs, IntRegs,
20280 /* A4_rcmpneqi */
20281 IntRegs, IntRegs, s32_0Imm,
20282 /* A4_round_ri */
20283 IntRegs, IntRegs, u5_0Imm,
20284 /* A4_round_ri_sat */
20285 IntRegs, IntRegs, u5_0Imm,
20286 /* A4_round_rr */
20287 IntRegs, IntRegs, IntRegs,
20288 /* A4_round_rr_sat */
20289 IntRegs, IntRegs, IntRegs,
20290 /* A4_subp_c */
20291 DoubleRegs, PredRegs, DoubleRegs, DoubleRegs, PredRegs,
20292 /* A4_tfrcpp */
20293 DoubleRegs, CtrRegs64,
20294 /* A4_tfrpcp */
20295 CtrRegs64, DoubleRegs,
20296 /* A4_tlbmatch */
20297 PredRegs, DoubleRegs, IntRegs,
20298 /* A4_vcmpbeq_any */
20299 PredRegs, DoubleRegs, DoubleRegs,
20300 /* A4_vcmpbeqi */
20301 PredRegs, DoubleRegs, u8_0Imm,
20302 /* A4_vcmpbgt */
20303 PredRegs, DoubleRegs, DoubleRegs,
20304 /* A4_vcmpbgti */
20305 PredRegs, DoubleRegs, s8_0Imm,
20306 /* A4_vcmpbgtui */
20307 PredRegs, DoubleRegs, u7_0Imm,
20308 /* A4_vcmpheqi */
20309 PredRegs, DoubleRegs, s8_0Imm,
20310 /* A4_vcmphgti */
20311 PredRegs, DoubleRegs, s8_0Imm,
20312 /* A4_vcmphgtui */
20313 PredRegs, DoubleRegs, u7_0Imm,
20314 /* A4_vcmpweqi */
20315 PredRegs, DoubleRegs, s8_0Imm,
20316 /* A4_vcmpwgti */
20317 PredRegs, DoubleRegs, s8_0Imm,
20318 /* A4_vcmpwgtui */
20319 PredRegs, DoubleRegs, u7_0Imm,
20320 /* A4_vrmaxh */
20321 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
20322 /* A4_vrmaxuh */
20323 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
20324 /* A4_vrmaxuw */
20325 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
20326 /* A4_vrmaxw */
20327 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
20328 /* A4_vrminh */
20329 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
20330 /* A4_vrminuh */
20331 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
20332 /* A4_vrminuw */
20333 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
20334 /* A4_vrminw */
20335 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
20336 /* A5_ACS */
20337 DoubleRegs, PredRegs, DoubleRegs, DoubleRegs, DoubleRegs,
20338 /* A5_vaddhubs */
20339 IntRegs, DoubleRegs, DoubleRegs,
20340 /* A6_vcmpbeq_notany */
20341 PredRegs, DoubleRegs, DoubleRegs,
20342 /* A6_vminub_RdP */
20343 DoubleRegs, PredRegs, DoubleRegs, DoubleRegs,
20344 /* A7_clip */
20345 IntRegs, IntRegs, u5_0Imm,
20346 /* A7_croundd_ri */
20347 DoubleRegs, DoubleRegs, u6_0Imm,
20348 /* A7_croundd_rr */
20349 DoubleRegs, DoubleRegs, IntRegs,
20350 /* A7_vclip */
20351 DoubleRegs, DoubleRegs, u5_0Imm,
20352 /* C2_all8 */
20353 PredRegs, PredRegs,
20354 /* C2_and */
20355 PredRegs, PredRegs, PredRegs,
20356 /* C2_andn */
20357 PredRegs, PredRegs, PredRegs,
20358 /* C2_any8 */
20359 PredRegs, PredRegs,
20360 /* C2_bitsclr */
20361 PredRegs, IntRegs, IntRegs,
20362 /* C2_bitsclri */
20363 PredRegs, IntRegs, u6_0Imm,
20364 /* C2_bitsset */
20365 PredRegs, IntRegs, IntRegs,
20366 /* C2_ccombinewf */
20367 DoubleRegs, PredRegs, IntRegs, IntRegs,
20368 /* C2_ccombinewnewf */
20369 DoubleRegs, PredRegs, IntRegs, IntRegs,
20370 /* C2_ccombinewnewt */
20371 DoubleRegs, PredRegs, IntRegs, IntRegs,
20372 /* C2_ccombinewt */
20373 DoubleRegs, PredRegs, IntRegs, IntRegs,
20374 /* C2_cmoveif */
20375 IntRegs, PredRegs, s32_0Imm,
20376 /* C2_cmoveit */
20377 IntRegs, PredRegs, s32_0Imm,
20378 /* C2_cmovenewif */
20379 IntRegs, PredRegs, s32_0Imm,
20380 /* C2_cmovenewit */
20381 IntRegs, PredRegs, s32_0Imm,
20382 /* C2_cmpeq */
20383 PredRegs, IntRegs, IntRegs,
20384 /* C2_cmpeqi */
20385 PredRegs, IntRegs, s32_0Imm,
20386 /* C2_cmpeqp */
20387 PredRegs, DoubleRegs, DoubleRegs,
20388 /* C2_cmpgt */
20389 PredRegs, IntRegs, IntRegs,
20390 /* C2_cmpgti */
20391 PredRegs, IntRegs, s32_0Imm,
20392 /* C2_cmpgtp */
20393 PredRegs, DoubleRegs, DoubleRegs,
20394 /* C2_cmpgtu */
20395 PredRegs, IntRegs, IntRegs,
20396 /* C2_cmpgtui */
20397 PredRegs, IntRegs, u32_0Imm,
20398 /* C2_cmpgtup */
20399 PredRegs, DoubleRegs, DoubleRegs,
20400 /* C2_mask */
20401 DoubleRegs, PredRegs,
20402 /* C2_mux */
20403 IntRegs, PredRegs, IntRegs, IntRegs,
20404 /* C2_muxii */
20405 IntRegs, PredRegs, s32_0Imm, s8_0Imm,
20406 /* C2_muxir */
20407 IntRegs, PredRegs, IntRegs, s32_0Imm,
20408 /* C2_muxri */
20409 IntRegs, PredRegs, s32_0Imm, IntRegs,
20410 /* C2_not */
20411 PredRegs, PredRegs,
20412 /* C2_or */
20413 PredRegs, PredRegs, PredRegs,
20414 /* C2_orn */
20415 PredRegs, PredRegs, PredRegs,
20416 /* C2_tfrpr */
20417 IntRegs, PredRegs,
20418 /* C2_tfrrp */
20419 PredRegs, IntRegs,
20420 /* C2_vitpack */
20421 IntRegs, PredRegs, PredRegs,
20422 /* C2_vmux */
20423 DoubleRegs, PredRegs, DoubleRegs, DoubleRegs,
20424 /* C2_xor */
20425 PredRegs, PredRegs, PredRegs,
20426 /* C4_addipc */
20427 IntRegs, u32_0Imm,
20428 /* C4_and_and */
20429 PredRegs, PredRegs, PredRegs, PredRegs,
20430 /* C4_and_andn */
20431 PredRegs, PredRegs, PredRegs, PredRegs,
20432 /* C4_and_or */
20433 PredRegs, PredRegs, PredRegs, PredRegs,
20434 /* C4_and_orn */
20435 PredRegs, PredRegs, PredRegs, PredRegs,
20436 /* C4_cmplte */
20437 PredRegs, IntRegs, IntRegs,
20438 /* C4_cmpltei */
20439 PredRegs, IntRegs, s32_0Imm,
20440 /* C4_cmplteu */
20441 PredRegs, IntRegs, IntRegs,
20442 /* C4_cmplteui */
20443 PredRegs, IntRegs, u32_0Imm,
20444 /* C4_cmpneq */
20445 PredRegs, IntRegs, IntRegs,
20446 /* C4_cmpneqi */
20447 PredRegs, IntRegs, s32_0Imm,
20448 /* C4_fastcorner9 */
20449 PredRegs, PredRegs, PredRegs,
20450 /* C4_fastcorner9_not */
20451 PredRegs, PredRegs, PredRegs,
20452 /* C4_nbitsclr */
20453 PredRegs, IntRegs, IntRegs,
20454 /* C4_nbitsclri */
20455 PredRegs, IntRegs, u6_0Imm,
20456 /* C4_nbitsset */
20457 PredRegs, IntRegs, IntRegs,
20458 /* C4_or_and */
20459 PredRegs, PredRegs, PredRegs, PredRegs,
20460 /* C4_or_andn */
20461 PredRegs, PredRegs, PredRegs, PredRegs,
20462 /* C4_or_or */
20463 PredRegs, PredRegs, PredRegs, PredRegs,
20464 /* C4_or_orn */
20465 PredRegs, PredRegs, PredRegs, PredRegs,
20466 /* CALLProfile */
20467 a30_2Imm,
20468 /* CONST32 */
20469 IntRegs, i32imm,
20470 /* CONST64 */
20471 DoubleRegs, i64imm,
20472 /* DuplexIClass0 */
20473 /* DuplexIClass1 */
20474 /* DuplexIClass2 */
20475 /* DuplexIClass3 */
20476 /* DuplexIClass4 */
20477 /* DuplexIClass5 */
20478 /* DuplexIClass6 */
20479 /* DuplexIClass7 */
20480 /* DuplexIClass8 */
20481 /* DuplexIClass9 */
20482 /* DuplexIClassA */
20483 /* DuplexIClassB */
20484 /* DuplexIClassC */
20485 /* DuplexIClassD */
20486 /* DuplexIClassE */
20487 /* DuplexIClassF */
20488 /* EH_RETURN_JMPR */
20489 IntRegs,
20490 /* F2_conv_d2df */
20491 DoubleRegs, DoubleRegs,
20492 /* F2_conv_d2sf */
20493 IntRegs, DoubleRegs,
20494 /* F2_conv_df2d */
20495 DoubleRegs, DoubleRegs,
20496 /* F2_conv_df2d_chop */
20497 DoubleRegs, DoubleRegs,
20498 /* F2_conv_df2sf */
20499 IntRegs, DoubleRegs,
20500 /* F2_conv_df2ud */
20501 DoubleRegs, DoubleRegs,
20502 /* F2_conv_df2ud_chop */
20503 DoubleRegs, DoubleRegs,
20504 /* F2_conv_df2uw */
20505 IntRegs, DoubleRegs,
20506 /* F2_conv_df2uw_chop */
20507 IntRegs, DoubleRegs,
20508 /* F2_conv_df2w */
20509 IntRegs, DoubleRegs,
20510 /* F2_conv_df2w_chop */
20511 IntRegs, DoubleRegs,
20512 /* F2_conv_sf2d */
20513 DoubleRegs, IntRegs,
20514 /* F2_conv_sf2d_chop */
20515 DoubleRegs, IntRegs,
20516 /* F2_conv_sf2df */
20517 DoubleRegs, IntRegs,
20518 /* F2_conv_sf2ud */
20519 DoubleRegs, IntRegs,
20520 /* F2_conv_sf2ud_chop */
20521 DoubleRegs, IntRegs,
20522 /* F2_conv_sf2uw */
20523 IntRegs, IntRegs,
20524 /* F2_conv_sf2uw_chop */
20525 IntRegs, IntRegs,
20526 /* F2_conv_sf2w */
20527 IntRegs, IntRegs,
20528 /* F2_conv_sf2w_chop */
20529 IntRegs, IntRegs,
20530 /* F2_conv_ud2df */
20531 DoubleRegs, DoubleRegs,
20532 /* F2_conv_ud2sf */
20533 IntRegs, DoubleRegs,
20534 /* F2_conv_uw2df */
20535 DoubleRegs, IntRegs,
20536 /* F2_conv_uw2sf */
20537 IntRegs, IntRegs,
20538 /* F2_conv_w2df */
20539 DoubleRegs, IntRegs,
20540 /* F2_conv_w2sf */
20541 IntRegs, IntRegs,
20542 /* F2_dfadd */
20543 DoubleRegs, DoubleRegs, DoubleRegs,
20544 /* F2_dfclass */
20545 PredRegs, DoubleRegs, u5_0Imm,
20546 /* F2_dfcmpeq */
20547 PredRegs, DoubleRegs, DoubleRegs,
20548 /* F2_dfcmpge */
20549 PredRegs, DoubleRegs, DoubleRegs,
20550 /* F2_dfcmpgt */
20551 PredRegs, DoubleRegs, DoubleRegs,
20552 /* F2_dfcmpuo */
20553 PredRegs, DoubleRegs, DoubleRegs,
20554 /* F2_dfimm_n */
20555 DoubleRegs, u10_0Imm,
20556 /* F2_dfimm_p */
20557 DoubleRegs, u10_0Imm,
20558 /* F2_dfmax */
20559 DoubleRegs, DoubleRegs, DoubleRegs,
20560 /* F2_dfmin */
20561 DoubleRegs, DoubleRegs, DoubleRegs,
20562 /* F2_dfmpyfix */
20563 DoubleRegs, DoubleRegs, DoubleRegs,
20564 /* F2_dfmpyhh */
20565 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
20566 /* F2_dfmpylh */
20567 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
20568 /* F2_dfmpyll */
20569 DoubleRegs, DoubleRegs, DoubleRegs,
20570 /* F2_dfsub */
20571 DoubleRegs, DoubleRegs, DoubleRegs,
20572 /* F2_sfadd */
20573 IntRegs, IntRegs, IntRegs,
20574 /* F2_sfclass */
20575 PredRegs, IntRegs, u5_0Imm,
20576 /* F2_sfcmpeq */
20577 PredRegs, IntRegs, IntRegs,
20578 /* F2_sfcmpge */
20579 PredRegs, IntRegs, IntRegs,
20580 /* F2_sfcmpgt */
20581 PredRegs, IntRegs, IntRegs,
20582 /* F2_sfcmpuo */
20583 PredRegs, IntRegs, IntRegs,
20584 /* F2_sffixupd */
20585 IntRegs, IntRegs, IntRegs,
20586 /* F2_sffixupn */
20587 IntRegs, IntRegs, IntRegs,
20588 /* F2_sffixupr */
20589 IntRegs, IntRegs,
20590 /* F2_sffma */
20591 IntRegs, IntRegs, IntRegs, IntRegs,
20592 /* F2_sffma_lib */
20593 IntRegs, IntRegs, IntRegs, IntRegs,
20594 /* F2_sffma_sc */
20595 IntRegs, IntRegs, IntRegs, IntRegs, PredRegs,
20596 /* F2_sffms */
20597 IntRegs, IntRegs, IntRegs, IntRegs,
20598 /* F2_sffms_lib */
20599 IntRegs, IntRegs, IntRegs, IntRegs,
20600 /* F2_sfimm_n */
20601 IntRegs, u10_0Imm,
20602 /* F2_sfimm_p */
20603 IntRegs, u10_0Imm,
20604 /* F2_sfinvsqrta */
20605 IntRegs, PredRegs, IntRegs,
20606 /* F2_sfmax */
20607 IntRegs, IntRegs, IntRegs,
20608 /* F2_sfmin */
20609 IntRegs, IntRegs, IntRegs,
20610 /* F2_sfmpy */
20611 IntRegs, IntRegs, IntRegs,
20612 /* F2_sfrecipa */
20613 IntRegs, PredRegs, IntRegs, IntRegs,
20614 /* F2_sfsub */
20615 IntRegs, IntRegs, IntRegs,
20616 /* G4_tfrgcpp */
20617 DoubleRegs, GuestRegs64,
20618 /* G4_tfrgcrr */
20619 IntRegs, GuestRegs,
20620 /* G4_tfrgpcp */
20621 GuestRegs64, DoubleRegs,
20622 /* G4_tfrgrcr */
20623 GuestRegs, IntRegs,
20624 /* HI */
20625 IntRegs, u16_0Imm,
20626 /* J2_call */
20627 a30_2Imm,
20628 /* J2_callf */
20629 PredRegs, a30_2Imm,
20630 /* J2_callr */
20631 IntRegs,
20632 /* J2_callrf */
20633 PredRegs, IntRegs,
20634 /* J2_callrh */
20635 IntRegs,
20636 /* J2_callrt */
20637 PredRegs, IntRegs,
20638 /* J2_callt */
20639 PredRegs, a30_2Imm,
20640 /* J2_jump */
20641 b30_2Imm,
20642 /* J2_jumpf */
20643 PredRegs, b30_2Imm,
20644 /* J2_jumpfnew */
20645 PredRegs, b30_2Imm,
20646 /* J2_jumpfnewpt */
20647 PredRegs, b30_2Imm,
20648 /* J2_jumpfpt */
20649 PredRegs, b30_2Imm,
20650 /* J2_jumpr */
20651 IntRegs,
20652 /* J2_jumprf */
20653 PredRegs, IntRegs,
20654 /* J2_jumprfnew */
20655 PredRegs, IntRegs,
20656 /* J2_jumprfnewpt */
20657 PredRegs, IntRegs,
20658 /* J2_jumprfpt */
20659 PredRegs, IntRegs,
20660 /* J2_jumprgtez */
20661 IntRegs, b13_2Imm,
20662 /* J2_jumprgtezpt */
20663 IntRegs, b13_2Imm,
20664 /* J2_jumprh */
20665 IntRegs,
20666 /* J2_jumprltez */
20667 IntRegs, b13_2Imm,
20668 /* J2_jumprltezpt */
20669 IntRegs, b13_2Imm,
20670 /* J2_jumprnz */
20671 IntRegs, b13_2Imm,
20672 /* J2_jumprnzpt */
20673 IntRegs, b13_2Imm,
20674 /* J2_jumprt */
20675 PredRegs, IntRegs,
20676 /* J2_jumprtnew */
20677 PredRegs, IntRegs,
20678 /* J2_jumprtnewpt */
20679 PredRegs, IntRegs,
20680 /* J2_jumprtpt */
20681 PredRegs, IntRegs,
20682 /* J2_jumprz */
20683 IntRegs, b13_2Imm,
20684 /* J2_jumprzpt */
20685 IntRegs, b13_2Imm,
20686 /* J2_jumpt */
20687 PredRegs, b30_2Imm,
20688 /* J2_jumptnew */
20689 PredRegs, b30_2Imm,
20690 /* J2_jumptnewpt */
20691 PredRegs, b30_2Imm,
20692 /* J2_jumptpt */
20693 PredRegs, b30_2Imm,
20694 /* J2_loop0i */
20695 b30_2Imm, u10_0Imm,
20696 /* J2_loop0iext */
20697 b30_2Imm, u10_0Imm,
20698 /* J2_loop0r */
20699 b30_2Imm, IntRegs,
20700 /* J2_loop0rext */
20701 b30_2Imm, IntRegs,
20702 /* J2_loop1i */
20703 b30_2Imm, u10_0Imm,
20704 /* J2_loop1iext */
20705 b30_2Imm, u10_0Imm,
20706 /* J2_loop1r */
20707 b30_2Imm, IntRegs,
20708 /* J2_loop1rext */
20709 b30_2Imm, IntRegs,
20710 /* J2_pause */
20711 u10_0Imm,
20712 /* J2_ploop1si */
20713 b30_2Imm, u10_0Imm,
20714 /* J2_ploop1sr */
20715 b30_2Imm, IntRegs,
20716 /* J2_ploop2si */
20717 b30_2Imm, u10_0Imm,
20718 /* J2_ploop2sr */
20719 b30_2Imm, IntRegs,
20720 /* J2_ploop3si */
20721 b30_2Imm, u10_0Imm,
20722 /* J2_ploop3sr */
20723 b30_2Imm, IntRegs,
20724 /* J2_rte */
20725 /* J2_trap0 */
20726 u8_0Imm,
20727 /* J2_trap1 */
20728 IntRegs, IntRegs, u8_0Imm,
20729 /* J2_unpause */
20730 /* J4_cmpeq_f_jumpnv_nt */
20731 IntRegs, IntRegs, b30_2Imm,
20732 /* J4_cmpeq_f_jumpnv_t */
20733 IntRegs, IntRegs, b30_2Imm,
20734 /* J4_cmpeq_fp0_jump_nt */
20735 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20736 /* J4_cmpeq_fp0_jump_t */
20737 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20738 /* J4_cmpeq_fp1_jump_nt */
20739 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20740 /* J4_cmpeq_fp1_jump_t */
20741 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20742 /* J4_cmpeq_t_jumpnv_nt */
20743 IntRegs, IntRegs, b30_2Imm,
20744 /* J4_cmpeq_t_jumpnv_t */
20745 IntRegs, IntRegs, b30_2Imm,
20746 /* J4_cmpeq_tp0_jump_nt */
20747 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20748 /* J4_cmpeq_tp0_jump_t */
20749 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20750 /* J4_cmpeq_tp1_jump_nt */
20751 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20752 /* J4_cmpeq_tp1_jump_t */
20753 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20754 /* J4_cmpeqi_f_jumpnv_nt */
20755 IntRegs, u5_0Imm, b30_2Imm,
20756 /* J4_cmpeqi_f_jumpnv_t */
20757 IntRegs, u5_0Imm, b30_2Imm,
20758 /* J4_cmpeqi_fp0_jump_nt */
20759 GeneralSubRegs, u5_0Imm, b30_2Imm,
20760 /* J4_cmpeqi_fp0_jump_t */
20761 GeneralSubRegs, u5_0Imm, b30_2Imm,
20762 /* J4_cmpeqi_fp1_jump_nt */
20763 GeneralSubRegs, u5_0Imm, b30_2Imm,
20764 /* J4_cmpeqi_fp1_jump_t */
20765 GeneralSubRegs, u5_0Imm, b30_2Imm,
20766 /* J4_cmpeqi_t_jumpnv_nt */
20767 IntRegs, u5_0Imm, b30_2Imm,
20768 /* J4_cmpeqi_t_jumpnv_t */
20769 IntRegs, u5_0Imm, b30_2Imm,
20770 /* J4_cmpeqi_tp0_jump_nt */
20771 GeneralSubRegs, u5_0Imm, b30_2Imm,
20772 /* J4_cmpeqi_tp0_jump_t */
20773 GeneralSubRegs, u5_0Imm, b30_2Imm,
20774 /* J4_cmpeqi_tp1_jump_nt */
20775 GeneralSubRegs, u5_0Imm, b30_2Imm,
20776 /* J4_cmpeqi_tp1_jump_t */
20777 GeneralSubRegs, u5_0Imm, b30_2Imm,
20778 /* J4_cmpeqn1_f_jumpnv_nt */
20779 IntRegs, n1Const, b30_2Imm,
20780 /* J4_cmpeqn1_f_jumpnv_t */
20781 IntRegs, n1Const, b30_2Imm,
20782 /* J4_cmpeqn1_fp0_jump_nt */
20783 GeneralSubRegs, n1Const, b30_2Imm,
20784 /* J4_cmpeqn1_fp0_jump_t */
20785 GeneralSubRegs, n1Const, b30_2Imm,
20786 /* J4_cmpeqn1_fp1_jump_nt */
20787 GeneralSubRegs, n1Const, b30_2Imm,
20788 /* J4_cmpeqn1_fp1_jump_t */
20789 GeneralSubRegs, n1Const, b30_2Imm,
20790 /* J4_cmpeqn1_t_jumpnv_nt */
20791 IntRegs, n1Const, b30_2Imm,
20792 /* J4_cmpeqn1_t_jumpnv_t */
20793 IntRegs, n1Const, b30_2Imm,
20794 /* J4_cmpeqn1_tp0_jump_nt */
20795 GeneralSubRegs, n1Const, b30_2Imm,
20796 /* J4_cmpeqn1_tp0_jump_t */
20797 GeneralSubRegs, n1Const, b30_2Imm,
20798 /* J4_cmpeqn1_tp1_jump_nt */
20799 GeneralSubRegs, n1Const, b30_2Imm,
20800 /* J4_cmpeqn1_tp1_jump_t */
20801 GeneralSubRegs, n1Const, b30_2Imm,
20802 /* J4_cmpgt_f_jumpnv_nt */
20803 IntRegs, IntRegs, b30_2Imm,
20804 /* J4_cmpgt_f_jumpnv_t */
20805 IntRegs, IntRegs, b30_2Imm,
20806 /* J4_cmpgt_fp0_jump_nt */
20807 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20808 /* J4_cmpgt_fp0_jump_t */
20809 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20810 /* J4_cmpgt_fp1_jump_nt */
20811 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20812 /* J4_cmpgt_fp1_jump_t */
20813 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20814 /* J4_cmpgt_t_jumpnv_nt */
20815 IntRegs, IntRegs, b30_2Imm,
20816 /* J4_cmpgt_t_jumpnv_t */
20817 IntRegs, IntRegs, b30_2Imm,
20818 /* J4_cmpgt_tp0_jump_nt */
20819 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20820 /* J4_cmpgt_tp0_jump_t */
20821 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20822 /* J4_cmpgt_tp1_jump_nt */
20823 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20824 /* J4_cmpgt_tp1_jump_t */
20825 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20826 /* J4_cmpgti_f_jumpnv_nt */
20827 IntRegs, u5_0Imm, b30_2Imm,
20828 /* J4_cmpgti_f_jumpnv_t */
20829 IntRegs, u5_0Imm, b30_2Imm,
20830 /* J4_cmpgti_fp0_jump_nt */
20831 GeneralSubRegs, u5_0Imm, b30_2Imm,
20832 /* J4_cmpgti_fp0_jump_t */
20833 GeneralSubRegs, u5_0Imm, b30_2Imm,
20834 /* J4_cmpgti_fp1_jump_nt */
20835 GeneralSubRegs, u5_0Imm, b30_2Imm,
20836 /* J4_cmpgti_fp1_jump_t */
20837 GeneralSubRegs, u5_0Imm, b30_2Imm,
20838 /* J4_cmpgti_t_jumpnv_nt */
20839 IntRegs, u5_0Imm, b30_2Imm,
20840 /* J4_cmpgti_t_jumpnv_t */
20841 IntRegs, u5_0Imm, b30_2Imm,
20842 /* J4_cmpgti_tp0_jump_nt */
20843 GeneralSubRegs, u5_0Imm, b30_2Imm,
20844 /* J4_cmpgti_tp0_jump_t */
20845 GeneralSubRegs, u5_0Imm, b30_2Imm,
20846 /* J4_cmpgti_tp1_jump_nt */
20847 GeneralSubRegs, u5_0Imm, b30_2Imm,
20848 /* J4_cmpgti_tp1_jump_t */
20849 GeneralSubRegs, u5_0Imm, b30_2Imm,
20850 /* J4_cmpgtn1_f_jumpnv_nt */
20851 IntRegs, n1Const, b30_2Imm,
20852 /* J4_cmpgtn1_f_jumpnv_t */
20853 IntRegs, n1Const, b30_2Imm,
20854 /* J4_cmpgtn1_fp0_jump_nt */
20855 GeneralSubRegs, n1Const, b30_2Imm,
20856 /* J4_cmpgtn1_fp0_jump_t */
20857 GeneralSubRegs, n1Const, b30_2Imm,
20858 /* J4_cmpgtn1_fp1_jump_nt */
20859 GeneralSubRegs, n1Const, b30_2Imm,
20860 /* J4_cmpgtn1_fp1_jump_t */
20861 GeneralSubRegs, n1Const, b30_2Imm,
20862 /* J4_cmpgtn1_t_jumpnv_nt */
20863 IntRegs, n1Const, b30_2Imm,
20864 /* J4_cmpgtn1_t_jumpnv_t */
20865 IntRegs, n1Const, b30_2Imm,
20866 /* J4_cmpgtn1_tp0_jump_nt */
20867 GeneralSubRegs, n1Const, b30_2Imm,
20868 /* J4_cmpgtn1_tp0_jump_t */
20869 GeneralSubRegs, n1Const, b30_2Imm,
20870 /* J4_cmpgtn1_tp1_jump_nt */
20871 GeneralSubRegs, n1Const, b30_2Imm,
20872 /* J4_cmpgtn1_tp1_jump_t */
20873 GeneralSubRegs, n1Const, b30_2Imm,
20874 /* J4_cmpgtu_f_jumpnv_nt */
20875 IntRegs, IntRegs, b30_2Imm,
20876 /* J4_cmpgtu_f_jumpnv_t */
20877 IntRegs, IntRegs, b30_2Imm,
20878 /* J4_cmpgtu_fp0_jump_nt */
20879 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20880 /* J4_cmpgtu_fp0_jump_t */
20881 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20882 /* J4_cmpgtu_fp1_jump_nt */
20883 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20884 /* J4_cmpgtu_fp1_jump_t */
20885 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20886 /* J4_cmpgtu_t_jumpnv_nt */
20887 IntRegs, IntRegs, b30_2Imm,
20888 /* J4_cmpgtu_t_jumpnv_t */
20889 IntRegs, IntRegs, b30_2Imm,
20890 /* J4_cmpgtu_tp0_jump_nt */
20891 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20892 /* J4_cmpgtu_tp0_jump_t */
20893 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20894 /* J4_cmpgtu_tp1_jump_nt */
20895 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20896 /* J4_cmpgtu_tp1_jump_t */
20897 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20898 /* J4_cmpgtui_f_jumpnv_nt */
20899 IntRegs, u5_0Imm, b30_2Imm,
20900 /* J4_cmpgtui_f_jumpnv_t */
20901 IntRegs, u5_0Imm, b30_2Imm,
20902 /* J4_cmpgtui_fp0_jump_nt */
20903 GeneralSubRegs, u5_0Imm, b30_2Imm,
20904 /* J4_cmpgtui_fp0_jump_t */
20905 GeneralSubRegs, u5_0Imm, b30_2Imm,
20906 /* J4_cmpgtui_fp1_jump_nt */
20907 GeneralSubRegs, u5_0Imm, b30_2Imm,
20908 /* J4_cmpgtui_fp1_jump_t */
20909 GeneralSubRegs, u5_0Imm, b30_2Imm,
20910 /* J4_cmpgtui_t_jumpnv_nt */
20911 IntRegs, u5_0Imm, b30_2Imm,
20912 /* J4_cmpgtui_t_jumpnv_t */
20913 IntRegs, u5_0Imm, b30_2Imm,
20914 /* J4_cmpgtui_tp0_jump_nt */
20915 GeneralSubRegs, u5_0Imm, b30_2Imm,
20916 /* J4_cmpgtui_tp0_jump_t */
20917 GeneralSubRegs, u5_0Imm, b30_2Imm,
20918 /* J4_cmpgtui_tp1_jump_nt */
20919 GeneralSubRegs, u5_0Imm, b30_2Imm,
20920 /* J4_cmpgtui_tp1_jump_t */
20921 GeneralSubRegs, u5_0Imm, b30_2Imm,
20922 /* J4_cmplt_f_jumpnv_nt */
20923 IntRegs, IntRegs, b30_2Imm,
20924 /* J4_cmplt_f_jumpnv_t */
20925 IntRegs, IntRegs, b30_2Imm,
20926 /* J4_cmplt_t_jumpnv_nt */
20927 IntRegs, IntRegs, b30_2Imm,
20928 /* J4_cmplt_t_jumpnv_t */
20929 IntRegs, IntRegs, b30_2Imm,
20930 /* J4_cmpltu_f_jumpnv_nt */
20931 IntRegs, IntRegs, b30_2Imm,
20932 /* J4_cmpltu_f_jumpnv_t */
20933 IntRegs, IntRegs, b30_2Imm,
20934 /* J4_cmpltu_t_jumpnv_nt */
20935 IntRegs, IntRegs, b30_2Imm,
20936 /* J4_cmpltu_t_jumpnv_t */
20937 IntRegs, IntRegs, b30_2Imm,
20938 /* J4_hintjumpr */
20939 IntRegs,
20940 /* J4_jumpseti */
20941 GeneralSubRegs, u6_0Imm, b30_2Imm,
20942 /* J4_jumpsetr */
20943 GeneralSubRegs, GeneralSubRegs, b30_2Imm,
20944 /* J4_tstbit0_f_jumpnv_nt */
20945 IntRegs, b30_2Imm,
20946 /* J4_tstbit0_f_jumpnv_t */
20947 IntRegs, b30_2Imm,
20948 /* J4_tstbit0_fp0_jump_nt */
20949 GeneralSubRegs, b30_2Imm,
20950 /* J4_tstbit0_fp0_jump_t */
20951 GeneralSubRegs, b30_2Imm,
20952 /* J4_tstbit0_fp1_jump_nt */
20953 GeneralSubRegs, b30_2Imm,
20954 /* J4_tstbit0_fp1_jump_t */
20955 GeneralSubRegs, b30_2Imm,
20956 /* J4_tstbit0_t_jumpnv_nt */
20957 IntRegs, b30_2Imm,
20958 /* J4_tstbit0_t_jumpnv_t */
20959 IntRegs, b30_2Imm,
20960 /* J4_tstbit0_tp0_jump_nt */
20961 GeneralSubRegs, b30_2Imm,
20962 /* J4_tstbit0_tp0_jump_t */
20963 GeneralSubRegs, b30_2Imm,
20964 /* J4_tstbit0_tp1_jump_nt */
20965 GeneralSubRegs, b30_2Imm,
20966 /* J4_tstbit0_tp1_jump_t */
20967 GeneralSubRegs, b30_2Imm,
20968 /* L2_deallocframe */
20969 DoubleRegs, IntRegs,
20970 /* L2_loadalignb_io */
20971 DoubleRegs, DoubleRegs, IntRegs, s32_0Imm,
20972 /* L2_loadalignb_pbr */
20973 DoubleRegs, IntRegs, DoubleRegs, IntRegs, ModRegs,
20974 /* L2_loadalignb_pci */
20975 DoubleRegs, IntRegs, DoubleRegs, IntRegs, s4_0Imm, ModRegs,
20976 /* L2_loadalignb_pcr */
20977 DoubleRegs, IntRegs, DoubleRegs, IntRegs, ModRegs,
20978 /* L2_loadalignb_pi */
20979 DoubleRegs, IntRegs, DoubleRegs, IntRegs, s4_0Imm,
20980 /* L2_loadalignb_pr */
20981 DoubleRegs, IntRegs, DoubleRegs, IntRegs, ModRegs,
20982 /* L2_loadalignh_io */
20983 DoubleRegs, DoubleRegs, IntRegs, s31_1Imm,
20984 /* L2_loadalignh_pbr */
20985 DoubleRegs, IntRegs, DoubleRegs, IntRegs, ModRegs,
20986 /* L2_loadalignh_pci */
20987 DoubleRegs, IntRegs, DoubleRegs, IntRegs, s4_1Imm, ModRegs,
20988 /* L2_loadalignh_pcr */
20989 DoubleRegs, IntRegs, DoubleRegs, IntRegs, ModRegs,
20990 /* L2_loadalignh_pi */
20991 DoubleRegs, IntRegs, DoubleRegs, IntRegs, s4_1Imm,
20992 /* L2_loadalignh_pr */
20993 DoubleRegs, IntRegs, DoubleRegs, IntRegs, ModRegs,
20994 /* L2_loadbsw2_io */
20995 IntRegs, IntRegs, s31_1Imm,
20996 /* L2_loadbsw2_pbr */
20997 IntRegs, IntRegs, IntRegs, ModRegs,
20998 /* L2_loadbsw2_pci */
20999 IntRegs, IntRegs, IntRegs, s4_1Imm, ModRegs,
21000 /* L2_loadbsw2_pcr */
21001 IntRegs, IntRegs, IntRegs, ModRegs,
21002 /* L2_loadbsw2_pi */
21003 IntRegs, IntRegs, IntRegs, s4_1Imm,
21004 /* L2_loadbsw2_pr */
21005 IntRegs, IntRegs, IntRegs, ModRegs,
21006 /* L2_loadbsw4_io */
21007 DoubleRegs, IntRegs, s30_2Imm,
21008 /* L2_loadbsw4_pbr */
21009 DoubleRegs, IntRegs, IntRegs, ModRegs,
21010 /* L2_loadbsw4_pci */
21011 DoubleRegs, IntRegs, IntRegs, s4_2Imm, ModRegs,
21012 /* L2_loadbsw4_pcr */
21013 DoubleRegs, IntRegs, IntRegs, ModRegs,
21014 /* L2_loadbsw4_pi */
21015 DoubleRegs, IntRegs, IntRegs, s4_2Imm,
21016 /* L2_loadbsw4_pr */
21017 DoubleRegs, IntRegs, IntRegs, ModRegs,
21018 /* L2_loadbzw2_io */
21019 IntRegs, IntRegs, s31_1Imm,
21020 /* L2_loadbzw2_pbr */
21021 IntRegs, IntRegs, IntRegs, ModRegs,
21022 /* L2_loadbzw2_pci */
21023 IntRegs, IntRegs, IntRegs, s4_1Imm, ModRegs,
21024 /* L2_loadbzw2_pcr */
21025 IntRegs, IntRegs, IntRegs, ModRegs,
21026 /* L2_loadbzw2_pi */
21027 IntRegs, IntRegs, IntRegs, s4_1Imm,
21028 /* L2_loadbzw2_pr */
21029 IntRegs, IntRegs, IntRegs, ModRegs,
21030 /* L2_loadbzw4_io */
21031 DoubleRegs, IntRegs, s30_2Imm,
21032 /* L2_loadbzw4_pbr */
21033 DoubleRegs, IntRegs, IntRegs, ModRegs,
21034 /* L2_loadbzw4_pci */
21035 DoubleRegs, IntRegs, IntRegs, s4_2Imm, ModRegs,
21036 /* L2_loadbzw4_pcr */
21037 DoubleRegs, IntRegs, IntRegs, ModRegs,
21038 /* L2_loadbzw4_pi */
21039 DoubleRegs, IntRegs, IntRegs, s4_2Imm,
21040 /* L2_loadbzw4_pr */
21041 DoubleRegs, IntRegs, IntRegs, ModRegs,
21042 /* L2_loadrb_io */
21043 IntRegs, IntRegs, s32_0Imm,
21044 /* L2_loadrb_pbr */
21045 IntRegs, IntRegs, IntRegs, ModRegs,
21046 /* L2_loadrb_pci */
21047 IntRegs, IntRegs, IntRegs, s4_0Imm, ModRegs,
21048 /* L2_loadrb_pcr */
21049 IntRegs, IntRegs, IntRegs, ModRegs,
21050 /* L2_loadrb_pi */
21051 IntRegs, IntRegs, IntRegs, s4_0Imm,
21052 /* L2_loadrb_pr */
21053 IntRegs, IntRegs, IntRegs, ModRegs,
21054 /* L2_loadrbgp */
21055 IntRegs, u32_0Imm,
21056 /* L2_loadrd_io */
21057 DoubleRegs, IntRegs, s29_3Imm,
21058 /* L2_loadrd_pbr */
21059 DoubleRegs, IntRegs, IntRegs, ModRegs,
21060 /* L2_loadrd_pci */
21061 DoubleRegs, IntRegs, IntRegs, s4_3Imm, ModRegs,
21062 /* L2_loadrd_pcr */
21063 DoubleRegs, IntRegs, IntRegs, ModRegs,
21064 /* L2_loadrd_pi */
21065 DoubleRegs, IntRegs, IntRegs, s4_3Imm,
21066 /* L2_loadrd_pr */
21067 DoubleRegs, IntRegs, IntRegs, ModRegs,
21068 /* L2_loadrdgp */
21069 DoubleRegs, u29_3Imm,
21070 /* L2_loadrh_io */
21071 IntRegs, IntRegs, s31_1Imm,
21072 /* L2_loadrh_pbr */
21073 IntRegs, IntRegs, IntRegs, ModRegs,
21074 /* L2_loadrh_pci */
21075 IntRegs, IntRegs, IntRegs, s4_1Imm, ModRegs,
21076 /* L2_loadrh_pcr */
21077 IntRegs, IntRegs, IntRegs, ModRegs,
21078 /* L2_loadrh_pi */
21079 IntRegs, IntRegs, IntRegs, s4_1Imm,
21080 /* L2_loadrh_pr */
21081 IntRegs, IntRegs, IntRegs, ModRegs,
21082 /* L2_loadrhgp */
21083 IntRegs, u31_1Imm,
21084 /* L2_loadri_io */
21085 IntRegs, IntRegs, s30_2Imm,
21086 /* L2_loadri_pbr */
21087 IntRegs, IntRegs, IntRegs, ModRegs,
21088 /* L2_loadri_pci */
21089 IntRegs, IntRegs, IntRegs, s4_2Imm, ModRegs,
21090 /* L2_loadri_pcr */
21091 IntRegs, IntRegs, IntRegs, ModRegs,
21092 /* L2_loadri_pi */
21093 IntRegs, IntRegs, IntRegs, s4_2Imm,
21094 /* L2_loadri_pr */
21095 IntRegs, IntRegs, IntRegs, ModRegs,
21096 /* L2_loadrigp */
21097 IntRegs, u30_2Imm,
21098 /* L2_loadrub_io */
21099 IntRegs, IntRegs, s32_0Imm,
21100 /* L2_loadrub_pbr */
21101 IntRegs, IntRegs, IntRegs, ModRegs,
21102 /* L2_loadrub_pci */
21103 IntRegs, IntRegs, IntRegs, s4_0Imm, ModRegs,
21104 /* L2_loadrub_pcr */
21105 IntRegs, IntRegs, IntRegs, ModRegs,
21106 /* L2_loadrub_pi */
21107 IntRegs, IntRegs, IntRegs, s4_0Imm,
21108 /* L2_loadrub_pr */
21109 IntRegs, IntRegs, IntRegs, ModRegs,
21110 /* L2_loadrubgp */
21111 IntRegs, u32_0Imm,
21112 /* L2_loadruh_io */
21113 IntRegs, IntRegs, s31_1Imm,
21114 /* L2_loadruh_pbr */
21115 IntRegs, IntRegs, IntRegs, ModRegs,
21116 /* L2_loadruh_pci */
21117 IntRegs, IntRegs, IntRegs, s4_1Imm, ModRegs,
21118 /* L2_loadruh_pcr */
21119 IntRegs, IntRegs, IntRegs, ModRegs,
21120 /* L2_loadruh_pi */
21121 IntRegs, IntRegs, IntRegs, s4_1Imm,
21122 /* L2_loadruh_pr */
21123 IntRegs, IntRegs, IntRegs, ModRegs,
21124 /* L2_loadruhgp */
21125 IntRegs, u31_1Imm,
21126 /* L2_loadw_aq */
21127 IntRegs, IntRegs,
21128 /* L2_loadw_locked */
21129 IntRegs, IntRegs,
21130 /* L2_ploadrbf_io */
21131 IntRegs, PredRegs, IntRegs, u32_0Imm,
21132 /* L2_ploadrbf_pi */
21133 IntRegs, IntRegs, PredRegs, IntRegs, s4_0Imm,
21134 /* L2_ploadrbfnew_io */
21135 IntRegs, PredRegs, IntRegs, u32_0Imm,
21136 /* L2_ploadrbfnew_pi */
21137 IntRegs, IntRegs, PredRegs, IntRegs, s4_0Imm,
21138 /* L2_ploadrbt_io */
21139 IntRegs, PredRegs, IntRegs, u32_0Imm,
21140 /* L2_ploadrbt_pi */
21141 IntRegs, IntRegs, PredRegs, IntRegs, s4_0Imm,
21142 /* L2_ploadrbtnew_io */
21143 IntRegs, PredRegs, IntRegs, u32_0Imm,
21144 /* L2_ploadrbtnew_pi */
21145 IntRegs, IntRegs, PredRegs, IntRegs, s4_0Imm,
21146 /* L2_ploadrdf_io */
21147 DoubleRegs, PredRegs, IntRegs, u29_3Imm,
21148 /* L2_ploadrdf_pi */
21149 DoubleRegs, IntRegs, PredRegs, IntRegs, s4_3Imm,
21150 /* L2_ploadrdfnew_io */
21151 DoubleRegs, PredRegs, IntRegs, u29_3Imm,
21152 /* L2_ploadrdfnew_pi */
21153 DoubleRegs, IntRegs, PredRegs, IntRegs, s4_3Imm,
21154 /* L2_ploadrdt_io */
21155 DoubleRegs, PredRegs, IntRegs, u29_3Imm,
21156 /* L2_ploadrdt_pi */
21157 DoubleRegs, IntRegs, PredRegs, IntRegs, s4_3Imm,
21158 /* L2_ploadrdtnew_io */
21159 DoubleRegs, PredRegs, IntRegs, u29_3Imm,
21160 /* L2_ploadrdtnew_pi */
21161 DoubleRegs, IntRegs, PredRegs, IntRegs, s4_3Imm,
21162 /* L2_ploadrhf_io */
21163 IntRegs, PredRegs, IntRegs, u31_1Imm,
21164 /* L2_ploadrhf_pi */
21165 IntRegs, IntRegs, PredRegs, IntRegs, s4_1Imm,
21166 /* L2_ploadrhfnew_io */
21167 IntRegs, PredRegs, IntRegs, u31_1Imm,
21168 /* L2_ploadrhfnew_pi */
21169 IntRegs, IntRegs, PredRegs, IntRegs, s4_1Imm,
21170 /* L2_ploadrht_io */
21171 IntRegs, PredRegs, IntRegs, u31_1Imm,
21172 /* L2_ploadrht_pi */
21173 IntRegs, IntRegs, PredRegs, IntRegs, s4_1Imm,
21174 /* L2_ploadrhtnew_io */
21175 IntRegs, PredRegs, IntRegs, u31_1Imm,
21176 /* L2_ploadrhtnew_pi */
21177 IntRegs, IntRegs, PredRegs, IntRegs, s4_1Imm,
21178 /* L2_ploadrif_io */
21179 IntRegs, PredRegs, IntRegs, u30_2Imm,
21180 /* L2_ploadrif_pi */
21181 IntRegs, IntRegs, PredRegs, IntRegs, s4_2Imm,
21182 /* L2_ploadrifnew_io */
21183 IntRegs, PredRegs, IntRegs, u30_2Imm,
21184 /* L2_ploadrifnew_pi */
21185 IntRegs, IntRegs, PredRegs, IntRegs, s4_2Imm,
21186 /* L2_ploadrit_io */
21187 IntRegs, PredRegs, IntRegs, u30_2Imm,
21188 /* L2_ploadrit_pi */
21189 IntRegs, IntRegs, PredRegs, IntRegs, s4_2Imm,
21190 /* L2_ploadritnew_io */
21191 IntRegs, PredRegs, IntRegs, u30_2Imm,
21192 /* L2_ploadritnew_pi */
21193 IntRegs, IntRegs, PredRegs, IntRegs, s4_2Imm,
21194 /* L2_ploadrubf_io */
21195 IntRegs, PredRegs, IntRegs, u32_0Imm,
21196 /* L2_ploadrubf_pi */
21197 IntRegs, IntRegs, PredRegs, IntRegs, s4_0Imm,
21198 /* L2_ploadrubfnew_io */
21199 IntRegs, PredRegs, IntRegs, u32_0Imm,
21200 /* L2_ploadrubfnew_pi */
21201 IntRegs, IntRegs, PredRegs, IntRegs, s4_0Imm,
21202 /* L2_ploadrubt_io */
21203 IntRegs, PredRegs, IntRegs, u32_0Imm,
21204 /* L2_ploadrubt_pi */
21205 IntRegs, IntRegs, PredRegs, IntRegs, s4_0Imm,
21206 /* L2_ploadrubtnew_io */
21207 IntRegs, PredRegs, IntRegs, u32_0Imm,
21208 /* L2_ploadrubtnew_pi */
21209 IntRegs, IntRegs, PredRegs, IntRegs, s4_0Imm,
21210 /* L2_ploadruhf_io */
21211 IntRegs, PredRegs, IntRegs, u31_1Imm,
21212 /* L2_ploadruhf_pi */
21213 IntRegs, IntRegs, PredRegs, IntRegs, s4_1Imm,
21214 /* L2_ploadruhfnew_io */
21215 IntRegs, PredRegs, IntRegs, u31_1Imm,
21216 /* L2_ploadruhfnew_pi */
21217 IntRegs, IntRegs, PredRegs, IntRegs, s4_1Imm,
21218 /* L2_ploadruht_io */
21219 IntRegs, PredRegs, IntRegs, u31_1Imm,
21220 /* L2_ploadruht_pi */
21221 IntRegs, IntRegs, PredRegs, IntRegs, s4_1Imm,
21222 /* L2_ploadruhtnew_io */
21223 IntRegs, PredRegs, IntRegs, u31_1Imm,
21224 /* L2_ploadruhtnew_pi */
21225 IntRegs, IntRegs, PredRegs, IntRegs, s4_1Imm,
21226 /* L4_add_memopb_io */
21227 IntRegs, u32_0Imm, IntRegs,
21228 /* L4_add_memoph_io */
21229 IntRegs, u31_1Imm, IntRegs,
21230 /* L4_add_memopw_io */
21231 IntRegs, u30_2Imm, IntRegs,
21232 /* L4_and_memopb_io */
21233 IntRegs, u32_0Imm, IntRegs,
21234 /* L4_and_memoph_io */
21235 IntRegs, u31_1Imm, IntRegs,
21236 /* L4_and_memopw_io */
21237 IntRegs, u30_2Imm, IntRegs,
21238 /* L4_iadd_memopb_io */
21239 IntRegs, u32_0Imm, u5_0Imm,
21240 /* L4_iadd_memoph_io */
21241 IntRegs, u31_1Imm, u5_0Imm,
21242 /* L4_iadd_memopw_io */
21243 IntRegs, u30_2Imm, u5_0Imm,
21244 /* L4_iand_memopb_io */
21245 IntRegs, u32_0Imm, u5_0Imm,
21246 /* L4_iand_memoph_io */
21247 IntRegs, u31_1Imm, u5_0Imm,
21248 /* L4_iand_memopw_io */
21249 IntRegs, u30_2Imm, u5_0Imm,
21250 /* L4_ior_memopb_io */
21251 IntRegs, u32_0Imm, u5_0Imm,
21252 /* L4_ior_memoph_io */
21253 IntRegs, u31_1Imm, u5_0Imm,
21254 /* L4_ior_memopw_io */
21255 IntRegs, u30_2Imm, u5_0Imm,
21256 /* L4_isub_memopb_io */
21257 IntRegs, u32_0Imm, u5_0Imm,
21258 /* L4_isub_memoph_io */
21259 IntRegs, u31_1Imm, u5_0Imm,
21260 /* L4_isub_memopw_io */
21261 IntRegs, u30_2Imm, u5_0Imm,
21262 /* L4_loadalignb_ap */
21263 DoubleRegs, IntRegs, DoubleRegs, u32_0Imm,
21264 /* L4_loadalignb_ur */
21265 DoubleRegs, DoubleRegs, IntRegs, u2_0Imm, u32_0Imm,
21266 /* L4_loadalignh_ap */
21267 DoubleRegs, IntRegs, DoubleRegs, u32_0Imm,
21268 /* L4_loadalignh_ur */
21269 DoubleRegs, DoubleRegs, IntRegs, u2_0Imm, u32_0Imm,
21270 /* L4_loadbsw2_ap */
21271 IntRegs, IntRegs, u32_0Imm,
21272 /* L4_loadbsw2_ur */
21273 IntRegs, IntRegs, u2_0Imm, u32_0Imm,
21274 /* L4_loadbsw4_ap */
21275 DoubleRegs, IntRegs, u32_0Imm,
21276 /* L4_loadbsw4_ur */
21277 DoubleRegs, IntRegs, u2_0Imm, u32_0Imm,
21278 /* L4_loadbzw2_ap */
21279 IntRegs, IntRegs, u32_0Imm,
21280 /* L4_loadbzw2_ur */
21281 IntRegs, IntRegs, u2_0Imm, u32_0Imm,
21282 /* L4_loadbzw4_ap */
21283 DoubleRegs, IntRegs, u32_0Imm,
21284 /* L4_loadbzw4_ur */
21285 DoubleRegs, IntRegs, u2_0Imm, u32_0Imm,
21286 /* L4_loadd_aq */
21287 DoubleRegs, IntRegs,
21288 /* L4_loadd_locked */
21289 DoubleRegs, IntRegs,
21290 /* L4_loadrb_ap */
21291 IntRegs, IntRegs, u32_0Imm,
21292 /* L4_loadrb_rr */
21293 IntRegs, IntRegs, IntRegs, u2_0Imm,
21294 /* L4_loadrb_ur */
21295 IntRegs, IntRegs, u2_0Imm, u32_0Imm,
21296 /* L4_loadrd_ap */
21297 DoubleRegs, IntRegs, u32_0Imm,
21298 /* L4_loadrd_rr */
21299 DoubleRegs, IntRegs, IntRegs, u2_0Imm,
21300 /* L4_loadrd_ur */
21301 DoubleRegs, IntRegs, u2_0Imm, u32_0Imm,
21302 /* L4_loadrh_ap */
21303 IntRegs, IntRegs, u32_0Imm,
21304 /* L4_loadrh_rr */
21305 IntRegs, IntRegs, IntRegs, u2_0Imm,
21306 /* L4_loadrh_ur */
21307 IntRegs, IntRegs, u2_0Imm, u32_0Imm,
21308 /* L4_loadri_ap */
21309 IntRegs, IntRegs, u32_0Imm,
21310 /* L4_loadri_rr */
21311 IntRegs, IntRegs, IntRegs, u2_0Imm,
21312 /* L4_loadri_ur */
21313 IntRegs, IntRegs, u2_0Imm, u32_0Imm,
21314 /* L4_loadrub_ap */
21315 IntRegs, IntRegs, u32_0Imm,
21316 /* L4_loadrub_rr */
21317 IntRegs, IntRegs, IntRegs, u2_0Imm,
21318 /* L4_loadrub_ur */
21319 IntRegs, IntRegs, u2_0Imm, u32_0Imm,
21320 /* L4_loadruh_ap */
21321 IntRegs, IntRegs, u32_0Imm,
21322 /* L4_loadruh_rr */
21323 IntRegs, IntRegs, IntRegs, u2_0Imm,
21324 /* L4_loadruh_ur */
21325 IntRegs, IntRegs, u2_0Imm, u32_0Imm,
21326 /* L4_loadw_phys */
21327 IntRegs, IntRegs, IntRegs,
21328 /* L4_or_memopb_io */
21329 IntRegs, u32_0Imm, IntRegs,
21330 /* L4_or_memoph_io */
21331 IntRegs, u31_1Imm, IntRegs,
21332 /* L4_or_memopw_io */
21333 IntRegs, u30_2Imm, IntRegs,
21334 /* L4_ploadrbf_abs */
21335 IntRegs, PredRegs, u32_0Imm,
21336 /* L4_ploadrbf_rr */
21337 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21338 /* L4_ploadrbfnew_abs */
21339 IntRegs, PredRegs, u32_0Imm,
21340 /* L4_ploadrbfnew_rr */
21341 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21342 /* L4_ploadrbt_abs */
21343 IntRegs, PredRegs, u32_0Imm,
21344 /* L4_ploadrbt_rr */
21345 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21346 /* L4_ploadrbtnew_abs */
21347 IntRegs, PredRegs, u32_0Imm,
21348 /* L4_ploadrbtnew_rr */
21349 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21350 /* L4_ploadrdf_abs */
21351 DoubleRegs, PredRegs, u32_0Imm,
21352 /* L4_ploadrdf_rr */
21353 DoubleRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21354 /* L4_ploadrdfnew_abs */
21355 DoubleRegs, PredRegs, u32_0Imm,
21356 /* L4_ploadrdfnew_rr */
21357 DoubleRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21358 /* L4_ploadrdt_abs */
21359 DoubleRegs, PredRegs, u32_0Imm,
21360 /* L4_ploadrdt_rr */
21361 DoubleRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21362 /* L4_ploadrdtnew_abs */
21363 DoubleRegs, PredRegs, u32_0Imm,
21364 /* L4_ploadrdtnew_rr */
21365 DoubleRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21366 /* L4_ploadrhf_abs */
21367 IntRegs, PredRegs, u32_0Imm,
21368 /* L4_ploadrhf_rr */
21369 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21370 /* L4_ploadrhfnew_abs */
21371 IntRegs, PredRegs, u32_0Imm,
21372 /* L4_ploadrhfnew_rr */
21373 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21374 /* L4_ploadrht_abs */
21375 IntRegs, PredRegs, u32_0Imm,
21376 /* L4_ploadrht_rr */
21377 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21378 /* L4_ploadrhtnew_abs */
21379 IntRegs, PredRegs, u32_0Imm,
21380 /* L4_ploadrhtnew_rr */
21381 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21382 /* L4_ploadrif_abs */
21383 IntRegs, PredRegs, u32_0Imm,
21384 /* L4_ploadrif_rr */
21385 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21386 /* L4_ploadrifnew_abs */
21387 IntRegs, PredRegs, u32_0Imm,
21388 /* L4_ploadrifnew_rr */
21389 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21390 /* L4_ploadrit_abs */
21391 IntRegs, PredRegs, u32_0Imm,
21392 /* L4_ploadrit_rr */
21393 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21394 /* L4_ploadritnew_abs */
21395 IntRegs, PredRegs, u32_0Imm,
21396 /* L4_ploadritnew_rr */
21397 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21398 /* L4_ploadrubf_abs */
21399 IntRegs, PredRegs, u32_0Imm,
21400 /* L4_ploadrubf_rr */
21401 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21402 /* L4_ploadrubfnew_abs */
21403 IntRegs, PredRegs, u32_0Imm,
21404 /* L4_ploadrubfnew_rr */
21405 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21406 /* L4_ploadrubt_abs */
21407 IntRegs, PredRegs, u32_0Imm,
21408 /* L4_ploadrubt_rr */
21409 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21410 /* L4_ploadrubtnew_abs */
21411 IntRegs, PredRegs, u32_0Imm,
21412 /* L4_ploadrubtnew_rr */
21413 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21414 /* L4_ploadruhf_abs */
21415 IntRegs, PredRegs, u32_0Imm,
21416 /* L4_ploadruhf_rr */
21417 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21418 /* L4_ploadruhfnew_abs */
21419 IntRegs, PredRegs, u32_0Imm,
21420 /* L4_ploadruhfnew_rr */
21421 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21422 /* L4_ploadruht_abs */
21423 IntRegs, PredRegs, u32_0Imm,
21424 /* L4_ploadruht_rr */
21425 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21426 /* L4_ploadruhtnew_abs */
21427 IntRegs, PredRegs, u32_0Imm,
21428 /* L4_ploadruhtnew_rr */
21429 IntRegs, PredRegs, IntRegs, IntRegs, u2_0Imm,
21430 /* L4_return */
21431 DoubleRegs, IntRegs,
21432 /* L4_return_f */
21433 DoubleRegs, PredRegs, IntRegs,
21434 /* L4_return_fnew_pnt */
21435 DoubleRegs, PredRegs, IntRegs,
21436 /* L4_return_fnew_pt */
21437 DoubleRegs, PredRegs, IntRegs,
21438 /* L4_return_t */
21439 DoubleRegs, PredRegs, IntRegs,
21440 /* L4_return_tnew_pnt */
21441 DoubleRegs, PredRegs, IntRegs,
21442 /* L4_return_tnew_pt */
21443 DoubleRegs, PredRegs, IntRegs,
21444 /* L4_sub_memopb_io */
21445 IntRegs, u32_0Imm, IntRegs,
21446 /* L4_sub_memoph_io */
21447 IntRegs, u31_1Imm, IntRegs,
21448 /* L4_sub_memopw_io */
21449 IntRegs, u30_2Imm, IntRegs,
21450 /* L6_memcpy */
21451 IntRegs, IntRegs, ModRegs,
21452 /* LO */
21453 IntRegs, u16_0Imm,
21454 /* M2_acci */
21455 IntRegs, IntRegs, IntRegs, IntRegs,
21456 /* M2_accii */
21457 IntRegs, IntRegs, IntRegs, s32_0Imm,
21458 /* M2_cmaci_s0 */
21459 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21460 /* M2_cmacr_s0 */
21461 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21462 /* M2_cmacs_s0 */
21463 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21464 /* M2_cmacs_s1 */
21465 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21466 /* M2_cmacsc_s0 */
21467 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21468 /* M2_cmacsc_s1 */
21469 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21470 /* M2_cmpyi_s0 */
21471 DoubleRegs, IntRegs, IntRegs,
21472 /* M2_cmpyr_s0 */
21473 DoubleRegs, IntRegs, IntRegs,
21474 /* M2_cmpyrs_s0 */
21475 IntRegs, IntRegs, IntRegs,
21476 /* M2_cmpyrs_s1 */
21477 IntRegs, IntRegs, IntRegs,
21478 /* M2_cmpyrsc_s0 */
21479 IntRegs, IntRegs, IntRegs,
21480 /* M2_cmpyrsc_s1 */
21481 IntRegs, IntRegs, IntRegs,
21482 /* M2_cmpys_s0 */
21483 DoubleRegs, IntRegs, IntRegs,
21484 /* M2_cmpys_s1 */
21485 DoubleRegs, IntRegs, IntRegs,
21486 /* M2_cmpysc_s0 */
21487 DoubleRegs, IntRegs, IntRegs,
21488 /* M2_cmpysc_s1 */
21489 DoubleRegs, IntRegs, IntRegs,
21490 /* M2_cnacs_s0 */
21491 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21492 /* M2_cnacs_s1 */
21493 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21494 /* M2_cnacsc_s0 */
21495 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21496 /* M2_cnacsc_s1 */
21497 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21498 /* M2_dpmpyss_acc_s0 */
21499 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21500 /* M2_dpmpyss_nac_s0 */
21501 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21502 /* M2_dpmpyss_rnd_s0 */
21503 IntRegs, IntRegs, IntRegs,
21504 /* M2_dpmpyss_s0 */
21505 DoubleRegs, IntRegs, IntRegs,
21506 /* M2_dpmpyuu_acc_s0 */
21507 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21508 /* M2_dpmpyuu_nac_s0 */
21509 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21510 /* M2_dpmpyuu_s0 */
21511 DoubleRegs, IntRegs, IntRegs,
21512 /* M2_hmmpyh_rs1 */
21513 IntRegs, IntRegs, IntRegs,
21514 /* M2_hmmpyh_s1 */
21515 IntRegs, IntRegs, IntRegs,
21516 /* M2_hmmpyl_rs1 */
21517 IntRegs, IntRegs, IntRegs,
21518 /* M2_hmmpyl_s1 */
21519 IntRegs, IntRegs, IntRegs,
21520 /* M2_maci */
21521 IntRegs, IntRegs, IntRegs, IntRegs,
21522 /* M2_macsin */
21523 IntRegs, IntRegs, IntRegs, u32_0Imm,
21524 /* M2_macsip */
21525 IntRegs, IntRegs, IntRegs, u32_0Imm,
21526 /* M2_mmachs_rs0 */
21527 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21528 /* M2_mmachs_rs1 */
21529 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21530 /* M2_mmachs_s0 */
21531 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21532 /* M2_mmachs_s1 */
21533 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21534 /* M2_mmacls_rs0 */
21535 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21536 /* M2_mmacls_rs1 */
21537 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21538 /* M2_mmacls_s0 */
21539 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21540 /* M2_mmacls_s1 */
21541 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21542 /* M2_mmacuhs_rs0 */
21543 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21544 /* M2_mmacuhs_rs1 */
21545 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21546 /* M2_mmacuhs_s0 */
21547 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21548 /* M2_mmacuhs_s1 */
21549 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21550 /* M2_mmaculs_rs0 */
21551 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21552 /* M2_mmaculs_rs1 */
21553 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21554 /* M2_mmaculs_s0 */
21555 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21556 /* M2_mmaculs_s1 */
21557 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21558 /* M2_mmpyh_rs0 */
21559 DoubleRegs, DoubleRegs, DoubleRegs,
21560 /* M2_mmpyh_rs1 */
21561 DoubleRegs, DoubleRegs, DoubleRegs,
21562 /* M2_mmpyh_s0 */
21563 DoubleRegs, DoubleRegs, DoubleRegs,
21564 /* M2_mmpyh_s1 */
21565 DoubleRegs, DoubleRegs, DoubleRegs,
21566 /* M2_mmpyl_rs0 */
21567 DoubleRegs, DoubleRegs, DoubleRegs,
21568 /* M2_mmpyl_rs1 */
21569 DoubleRegs, DoubleRegs, DoubleRegs,
21570 /* M2_mmpyl_s0 */
21571 DoubleRegs, DoubleRegs, DoubleRegs,
21572 /* M2_mmpyl_s1 */
21573 DoubleRegs, DoubleRegs, DoubleRegs,
21574 /* M2_mmpyuh_rs0 */
21575 DoubleRegs, DoubleRegs, DoubleRegs,
21576 /* M2_mmpyuh_rs1 */
21577 DoubleRegs, DoubleRegs, DoubleRegs,
21578 /* M2_mmpyuh_s0 */
21579 DoubleRegs, DoubleRegs, DoubleRegs,
21580 /* M2_mmpyuh_s1 */
21581 DoubleRegs, DoubleRegs, DoubleRegs,
21582 /* M2_mmpyul_rs0 */
21583 DoubleRegs, DoubleRegs, DoubleRegs,
21584 /* M2_mmpyul_rs1 */
21585 DoubleRegs, DoubleRegs, DoubleRegs,
21586 /* M2_mmpyul_s0 */
21587 DoubleRegs, DoubleRegs, DoubleRegs,
21588 /* M2_mmpyul_s1 */
21589 DoubleRegs, DoubleRegs, DoubleRegs,
21590 /* M2_mnaci */
21591 IntRegs, IntRegs, IntRegs, IntRegs,
21592 /* M2_mpy_acc_hh_s0 */
21593 IntRegs, IntRegs, IntRegs, IntRegs,
21594 /* M2_mpy_acc_hh_s1 */
21595 IntRegs, IntRegs, IntRegs, IntRegs,
21596 /* M2_mpy_acc_hl_s0 */
21597 IntRegs, IntRegs, IntRegs, IntRegs,
21598 /* M2_mpy_acc_hl_s1 */
21599 IntRegs, IntRegs, IntRegs, IntRegs,
21600 /* M2_mpy_acc_lh_s0 */
21601 IntRegs, IntRegs, IntRegs, IntRegs,
21602 /* M2_mpy_acc_lh_s1 */
21603 IntRegs, IntRegs, IntRegs, IntRegs,
21604 /* M2_mpy_acc_ll_s0 */
21605 IntRegs, IntRegs, IntRegs, IntRegs,
21606 /* M2_mpy_acc_ll_s1 */
21607 IntRegs, IntRegs, IntRegs, IntRegs,
21608 /* M2_mpy_acc_sat_hh_s0 */
21609 IntRegs, IntRegs, IntRegs, IntRegs,
21610 /* M2_mpy_acc_sat_hh_s1 */
21611 IntRegs, IntRegs, IntRegs, IntRegs,
21612 /* M2_mpy_acc_sat_hl_s0 */
21613 IntRegs, IntRegs, IntRegs, IntRegs,
21614 /* M2_mpy_acc_sat_hl_s1 */
21615 IntRegs, IntRegs, IntRegs, IntRegs,
21616 /* M2_mpy_acc_sat_lh_s0 */
21617 IntRegs, IntRegs, IntRegs, IntRegs,
21618 /* M2_mpy_acc_sat_lh_s1 */
21619 IntRegs, IntRegs, IntRegs, IntRegs,
21620 /* M2_mpy_acc_sat_ll_s0 */
21621 IntRegs, IntRegs, IntRegs, IntRegs,
21622 /* M2_mpy_acc_sat_ll_s1 */
21623 IntRegs, IntRegs, IntRegs, IntRegs,
21624 /* M2_mpy_hh_s0 */
21625 IntRegs, IntRegs, IntRegs,
21626 /* M2_mpy_hh_s1 */
21627 IntRegs, IntRegs, IntRegs,
21628 /* M2_mpy_hl_s0 */
21629 IntRegs, IntRegs, IntRegs,
21630 /* M2_mpy_hl_s1 */
21631 IntRegs, IntRegs, IntRegs,
21632 /* M2_mpy_lh_s0 */
21633 IntRegs, IntRegs, IntRegs,
21634 /* M2_mpy_lh_s1 */
21635 IntRegs, IntRegs, IntRegs,
21636 /* M2_mpy_ll_s0 */
21637 IntRegs, IntRegs, IntRegs,
21638 /* M2_mpy_ll_s1 */
21639 IntRegs, IntRegs, IntRegs,
21640 /* M2_mpy_nac_hh_s0 */
21641 IntRegs, IntRegs, IntRegs, IntRegs,
21642 /* M2_mpy_nac_hh_s1 */
21643 IntRegs, IntRegs, IntRegs, IntRegs,
21644 /* M2_mpy_nac_hl_s0 */
21645 IntRegs, IntRegs, IntRegs, IntRegs,
21646 /* M2_mpy_nac_hl_s1 */
21647 IntRegs, IntRegs, IntRegs, IntRegs,
21648 /* M2_mpy_nac_lh_s0 */
21649 IntRegs, IntRegs, IntRegs, IntRegs,
21650 /* M2_mpy_nac_lh_s1 */
21651 IntRegs, IntRegs, IntRegs, IntRegs,
21652 /* M2_mpy_nac_ll_s0 */
21653 IntRegs, IntRegs, IntRegs, IntRegs,
21654 /* M2_mpy_nac_ll_s1 */
21655 IntRegs, IntRegs, IntRegs, IntRegs,
21656 /* M2_mpy_nac_sat_hh_s0 */
21657 IntRegs, IntRegs, IntRegs, IntRegs,
21658 /* M2_mpy_nac_sat_hh_s1 */
21659 IntRegs, IntRegs, IntRegs, IntRegs,
21660 /* M2_mpy_nac_sat_hl_s0 */
21661 IntRegs, IntRegs, IntRegs, IntRegs,
21662 /* M2_mpy_nac_sat_hl_s1 */
21663 IntRegs, IntRegs, IntRegs, IntRegs,
21664 /* M2_mpy_nac_sat_lh_s0 */
21665 IntRegs, IntRegs, IntRegs, IntRegs,
21666 /* M2_mpy_nac_sat_lh_s1 */
21667 IntRegs, IntRegs, IntRegs, IntRegs,
21668 /* M2_mpy_nac_sat_ll_s0 */
21669 IntRegs, IntRegs, IntRegs, IntRegs,
21670 /* M2_mpy_nac_sat_ll_s1 */
21671 IntRegs, IntRegs, IntRegs, IntRegs,
21672 /* M2_mpy_rnd_hh_s0 */
21673 IntRegs, IntRegs, IntRegs,
21674 /* M2_mpy_rnd_hh_s1 */
21675 IntRegs, IntRegs, IntRegs,
21676 /* M2_mpy_rnd_hl_s0 */
21677 IntRegs, IntRegs, IntRegs,
21678 /* M2_mpy_rnd_hl_s1 */
21679 IntRegs, IntRegs, IntRegs,
21680 /* M2_mpy_rnd_lh_s0 */
21681 IntRegs, IntRegs, IntRegs,
21682 /* M2_mpy_rnd_lh_s1 */
21683 IntRegs, IntRegs, IntRegs,
21684 /* M2_mpy_rnd_ll_s0 */
21685 IntRegs, IntRegs, IntRegs,
21686 /* M2_mpy_rnd_ll_s1 */
21687 IntRegs, IntRegs, IntRegs,
21688 /* M2_mpy_sat_hh_s0 */
21689 IntRegs, IntRegs, IntRegs,
21690 /* M2_mpy_sat_hh_s1 */
21691 IntRegs, IntRegs, IntRegs,
21692 /* M2_mpy_sat_hl_s0 */
21693 IntRegs, IntRegs, IntRegs,
21694 /* M2_mpy_sat_hl_s1 */
21695 IntRegs, IntRegs, IntRegs,
21696 /* M2_mpy_sat_lh_s0 */
21697 IntRegs, IntRegs, IntRegs,
21698 /* M2_mpy_sat_lh_s1 */
21699 IntRegs, IntRegs, IntRegs,
21700 /* M2_mpy_sat_ll_s0 */
21701 IntRegs, IntRegs, IntRegs,
21702 /* M2_mpy_sat_ll_s1 */
21703 IntRegs, IntRegs, IntRegs,
21704 /* M2_mpy_sat_rnd_hh_s0 */
21705 IntRegs, IntRegs, IntRegs,
21706 /* M2_mpy_sat_rnd_hh_s1 */
21707 IntRegs, IntRegs, IntRegs,
21708 /* M2_mpy_sat_rnd_hl_s0 */
21709 IntRegs, IntRegs, IntRegs,
21710 /* M2_mpy_sat_rnd_hl_s1 */
21711 IntRegs, IntRegs, IntRegs,
21712 /* M2_mpy_sat_rnd_lh_s0 */
21713 IntRegs, IntRegs, IntRegs,
21714 /* M2_mpy_sat_rnd_lh_s1 */
21715 IntRegs, IntRegs, IntRegs,
21716 /* M2_mpy_sat_rnd_ll_s0 */
21717 IntRegs, IntRegs, IntRegs,
21718 /* M2_mpy_sat_rnd_ll_s1 */
21719 IntRegs, IntRegs, IntRegs,
21720 /* M2_mpy_up */
21721 IntRegs, IntRegs, IntRegs,
21722 /* M2_mpy_up_s1 */
21723 IntRegs, IntRegs, IntRegs,
21724 /* M2_mpy_up_s1_sat */
21725 IntRegs, IntRegs, IntRegs,
21726 /* M2_mpyd_acc_hh_s0 */
21727 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21728 /* M2_mpyd_acc_hh_s1 */
21729 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21730 /* M2_mpyd_acc_hl_s0 */
21731 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21732 /* M2_mpyd_acc_hl_s1 */
21733 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21734 /* M2_mpyd_acc_lh_s0 */
21735 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21736 /* M2_mpyd_acc_lh_s1 */
21737 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21738 /* M2_mpyd_acc_ll_s0 */
21739 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21740 /* M2_mpyd_acc_ll_s1 */
21741 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21742 /* M2_mpyd_hh_s0 */
21743 DoubleRegs, IntRegs, IntRegs,
21744 /* M2_mpyd_hh_s1 */
21745 DoubleRegs, IntRegs, IntRegs,
21746 /* M2_mpyd_hl_s0 */
21747 DoubleRegs, IntRegs, IntRegs,
21748 /* M2_mpyd_hl_s1 */
21749 DoubleRegs, IntRegs, IntRegs,
21750 /* M2_mpyd_lh_s0 */
21751 DoubleRegs, IntRegs, IntRegs,
21752 /* M2_mpyd_lh_s1 */
21753 DoubleRegs, IntRegs, IntRegs,
21754 /* M2_mpyd_ll_s0 */
21755 DoubleRegs, IntRegs, IntRegs,
21756 /* M2_mpyd_ll_s1 */
21757 DoubleRegs, IntRegs, IntRegs,
21758 /* M2_mpyd_nac_hh_s0 */
21759 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21760 /* M2_mpyd_nac_hh_s1 */
21761 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21762 /* M2_mpyd_nac_hl_s0 */
21763 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21764 /* M2_mpyd_nac_hl_s1 */
21765 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21766 /* M2_mpyd_nac_lh_s0 */
21767 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21768 /* M2_mpyd_nac_lh_s1 */
21769 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21770 /* M2_mpyd_nac_ll_s0 */
21771 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21772 /* M2_mpyd_nac_ll_s1 */
21773 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21774 /* M2_mpyd_rnd_hh_s0 */
21775 DoubleRegs, IntRegs, IntRegs,
21776 /* M2_mpyd_rnd_hh_s1 */
21777 DoubleRegs, IntRegs, IntRegs,
21778 /* M2_mpyd_rnd_hl_s0 */
21779 DoubleRegs, IntRegs, IntRegs,
21780 /* M2_mpyd_rnd_hl_s1 */
21781 DoubleRegs, IntRegs, IntRegs,
21782 /* M2_mpyd_rnd_lh_s0 */
21783 DoubleRegs, IntRegs, IntRegs,
21784 /* M2_mpyd_rnd_lh_s1 */
21785 DoubleRegs, IntRegs, IntRegs,
21786 /* M2_mpyd_rnd_ll_s0 */
21787 DoubleRegs, IntRegs, IntRegs,
21788 /* M2_mpyd_rnd_ll_s1 */
21789 DoubleRegs, IntRegs, IntRegs,
21790 /* M2_mpyi */
21791 IntRegs, IntRegs, IntRegs,
21792 /* M2_mpysin */
21793 IntRegs, IntRegs, u8_0Imm,
21794 /* M2_mpysip */
21795 IntRegs, IntRegs, u32_0Imm,
21796 /* M2_mpysu_up */
21797 IntRegs, IntRegs, IntRegs,
21798 /* M2_mpyu_acc_hh_s0 */
21799 IntRegs, IntRegs, IntRegs, IntRegs,
21800 /* M2_mpyu_acc_hh_s1 */
21801 IntRegs, IntRegs, IntRegs, IntRegs,
21802 /* M2_mpyu_acc_hl_s0 */
21803 IntRegs, IntRegs, IntRegs, IntRegs,
21804 /* M2_mpyu_acc_hl_s1 */
21805 IntRegs, IntRegs, IntRegs, IntRegs,
21806 /* M2_mpyu_acc_lh_s0 */
21807 IntRegs, IntRegs, IntRegs, IntRegs,
21808 /* M2_mpyu_acc_lh_s1 */
21809 IntRegs, IntRegs, IntRegs, IntRegs,
21810 /* M2_mpyu_acc_ll_s0 */
21811 IntRegs, IntRegs, IntRegs, IntRegs,
21812 /* M2_mpyu_acc_ll_s1 */
21813 IntRegs, IntRegs, IntRegs, IntRegs,
21814 /* M2_mpyu_hh_s0 */
21815 IntRegs, IntRegs, IntRegs,
21816 /* M2_mpyu_hh_s1 */
21817 IntRegs, IntRegs, IntRegs,
21818 /* M2_mpyu_hl_s0 */
21819 IntRegs, IntRegs, IntRegs,
21820 /* M2_mpyu_hl_s1 */
21821 IntRegs, IntRegs, IntRegs,
21822 /* M2_mpyu_lh_s0 */
21823 IntRegs, IntRegs, IntRegs,
21824 /* M2_mpyu_lh_s1 */
21825 IntRegs, IntRegs, IntRegs,
21826 /* M2_mpyu_ll_s0 */
21827 IntRegs, IntRegs, IntRegs,
21828 /* M2_mpyu_ll_s1 */
21829 IntRegs, IntRegs, IntRegs,
21830 /* M2_mpyu_nac_hh_s0 */
21831 IntRegs, IntRegs, IntRegs, IntRegs,
21832 /* M2_mpyu_nac_hh_s1 */
21833 IntRegs, IntRegs, IntRegs, IntRegs,
21834 /* M2_mpyu_nac_hl_s0 */
21835 IntRegs, IntRegs, IntRegs, IntRegs,
21836 /* M2_mpyu_nac_hl_s1 */
21837 IntRegs, IntRegs, IntRegs, IntRegs,
21838 /* M2_mpyu_nac_lh_s0 */
21839 IntRegs, IntRegs, IntRegs, IntRegs,
21840 /* M2_mpyu_nac_lh_s1 */
21841 IntRegs, IntRegs, IntRegs, IntRegs,
21842 /* M2_mpyu_nac_ll_s0 */
21843 IntRegs, IntRegs, IntRegs, IntRegs,
21844 /* M2_mpyu_nac_ll_s1 */
21845 IntRegs, IntRegs, IntRegs, IntRegs,
21846 /* M2_mpyu_up */
21847 IntRegs, IntRegs, IntRegs,
21848 /* M2_mpyud_acc_hh_s0 */
21849 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21850 /* M2_mpyud_acc_hh_s1 */
21851 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21852 /* M2_mpyud_acc_hl_s0 */
21853 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21854 /* M2_mpyud_acc_hl_s1 */
21855 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21856 /* M2_mpyud_acc_lh_s0 */
21857 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21858 /* M2_mpyud_acc_lh_s1 */
21859 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21860 /* M2_mpyud_acc_ll_s0 */
21861 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21862 /* M2_mpyud_acc_ll_s1 */
21863 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21864 /* M2_mpyud_hh_s0 */
21865 DoubleRegs, IntRegs, IntRegs,
21866 /* M2_mpyud_hh_s1 */
21867 DoubleRegs, IntRegs, IntRegs,
21868 /* M2_mpyud_hl_s0 */
21869 DoubleRegs, IntRegs, IntRegs,
21870 /* M2_mpyud_hl_s1 */
21871 DoubleRegs, IntRegs, IntRegs,
21872 /* M2_mpyud_lh_s0 */
21873 DoubleRegs, IntRegs, IntRegs,
21874 /* M2_mpyud_lh_s1 */
21875 DoubleRegs, IntRegs, IntRegs,
21876 /* M2_mpyud_ll_s0 */
21877 DoubleRegs, IntRegs, IntRegs,
21878 /* M2_mpyud_ll_s1 */
21879 DoubleRegs, IntRegs, IntRegs,
21880 /* M2_mpyud_nac_hh_s0 */
21881 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21882 /* M2_mpyud_nac_hh_s1 */
21883 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21884 /* M2_mpyud_nac_hl_s0 */
21885 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21886 /* M2_mpyud_nac_hl_s1 */
21887 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21888 /* M2_mpyud_nac_lh_s0 */
21889 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21890 /* M2_mpyud_nac_lh_s1 */
21891 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21892 /* M2_mpyud_nac_ll_s0 */
21893 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21894 /* M2_mpyud_nac_ll_s1 */
21895 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21896 /* M2_nacci */
21897 IntRegs, IntRegs, IntRegs, IntRegs,
21898 /* M2_naccii */
21899 IntRegs, IntRegs, IntRegs, s32_0Imm,
21900 /* M2_subacc */
21901 IntRegs, IntRegs, IntRegs, IntRegs,
21902 /* M2_vabsdiffh */
21903 DoubleRegs, DoubleRegs, DoubleRegs,
21904 /* M2_vabsdiffw */
21905 DoubleRegs, DoubleRegs, DoubleRegs,
21906 /* M2_vcmac_s0_sat_i */
21907 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21908 /* M2_vcmac_s0_sat_r */
21909 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21910 /* M2_vcmpy_s0_sat_i */
21911 DoubleRegs, DoubleRegs, DoubleRegs,
21912 /* M2_vcmpy_s0_sat_r */
21913 DoubleRegs, DoubleRegs, DoubleRegs,
21914 /* M2_vcmpy_s1_sat_i */
21915 DoubleRegs, DoubleRegs, DoubleRegs,
21916 /* M2_vcmpy_s1_sat_r */
21917 DoubleRegs, DoubleRegs, DoubleRegs,
21918 /* M2_vdmacs_s0 */
21919 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21920 /* M2_vdmacs_s1 */
21921 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21922 /* M2_vdmpyrs_s0 */
21923 IntRegs, DoubleRegs, DoubleRegs,
21924 /* M2_vdmpyrs_s1 */
21925 IntRegs, DoubleRegs, DoubleRegs,
21926 /* M2_vdmpys_s0 */
21927 DoubleRegs, DoubleRegs, DoubleRegs,
21928 /* M2_vdmpys_s1 */
21929 DoubleRegs, DoubleRegs, DoubleRegs,
21930 /* M2_vmac2 */
21931 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21932 /* M2_vmac2es */
21933 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21934 /* M2_vmac2es_s0 */
21935 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21936 /* M2_vmac2es_s1 */
21937 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21938 /* M2_vmac2s_s0 */
21939 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21940 /* M2_vmac2s_s1 */
21941 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21942 /* M2_vmac2su_s0 */
21943 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21944 /* M2_vmac2su_s1 */
21945 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
21946 /* M2_vmpy2es_s0 */
21947 DoubleRegs, DoubleRegs, DoubleRegs,
21948 /* M2_vmpy2es_s1 */
21949 DoubleRegs, DoubleRegs, DoubleRegs,
21950 /* M2_vmpy2s_s0 */
21951 DoubleRegs, IntRegs, IntRegs,
21952 /* M2_vmpy2s_s0pack */
21953 IntRegs, IntRegs, IntRegs,
21954 /* M2_vmpy2s_s1 */
21955 DoubleRegs, IntRegs, IntRegs,
21956 /* M2_vmpy2s_s1pack */
21957 IntRegs, IntRegs, IntRegs,
21958 /* M2_vmpy2su_s0 */
21959 DoubleRegs, IntRegs, IntRegs,
21960 /* M2_vmpy2su_s1 */
21961 DoubleRegs, IntRegs, IntRegs,
21962 /* M2_vraddh */
21963 IntRegs, DoubleRegs, DoubleRegs,
21964 /* M2_vradduh */
21965 IntRegs, DoubleRegs, DoubleRegs,
21966 /* M2_vrcmaci_s0 */
21967 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21968 /* M2_vrcmaci_s0c */
21969 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21970 /* M2_vrcmacr_s0 */
21971 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21972 /* M2_vrcmacr_s0c */
21973 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21974 /* M2_vrcmpyi_s0 */
21975 DoubleRegs, DoubleRegs, DoubleRegs,
21976 /* M2_vrcmpyi_s0c */
21977 DoubleRegs, DoubleRegs, DoubleRegs,
21978 /* M2_vrcmpyr_s0 */
21979 DoubleRegs, DoubleRegs, DoubleRegs,
21980 /* M2_vrcmpyr_s0c */
21981 DoubleRegs, DoubleRegs, DoubleRegs,
21982 /* M2_vrcmpys_acc_s1_h */
21983 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21984 /* M2_vrcmpys_acc_s1_l */
21985 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21986 /* M2_vrcmpys_s1_h */
21987 DoubleRegs, DoubleRegs, DoubleRegs,
21988 /* M2_vrcmpys_s1_l */
21989 DoubleRegs, DoubleRegs, DoubleRegs,
21990 /* M2_vrcmpys_s1rp_h */
21991 IntRegs, DoubleRegs, DoubleRegs,
21992 /* M2_vrcmpys_s1rp_l */
21993 IntRegs, DoubleRegs, DoubleRegs,
21994 /* M2_vrmac_s0 */
21995 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
21996 /* M2_vrmpy_s0 */
21997 DoubleRegs, DoubleRegs, DoubleRegs,
21998 /* M2_xor_xacc */
21999 IntRegs, IntRegs, IntRegs, IntRegs,
22000 /* M4_and_and */
22001 IntRegs, IntRegs, IntRegs, IntRegs,
22002 /* M4_and_andn */
22003 IntRegs, IntRegs, IntRegs, IntRegs,
22004 /* M4_and_or */
22005 IntRegs, IntRegs, IntRegs, IntRegs,
22006 /* M4_and_xor */
22007 IntRegs, IntRegs, IntRegs, IntRegs,
22008 /* M4_cmpyi_wh */
22009 IntRegs, DoubleRegs, IntRegs,
22010 /* M4_cmpyi_whc */
22011 IntRegs, DoubleRegs, IntRegs,
22012 /* M4_cmpyr_wh */
22013 IntRegs, DoubleRegs, IntRegs,
22014 /* M4_cmpyr_whc */
22015 IntRegs, DoubleRegs, IntRegs,
22016 /* M4_mac_up_s1_sat */
22017 IntRegs, IntRegs, IntRegs, IntRegs,
22018 /* M4_mpyri_addi */
22019 IntRegs, u32_0Imm, IntRegs, u6_0Imm,
22020 /* M4_mpyri_addr */
22021 IntRegs, IntRegs, IntRegs, u32_0Imm,
22022 /* M4_mpyri_addr_u2 */
22023 IntRegs, IntRegs, u6_2Imm, IntRegs,
22024 /* M4_mpyrr_addi */
22025 IntRegs, u32_0Imm, IntRegs, IntRegs,
22026 /* M4_mpyrr_addr */
22027 IntRegs, IntRegs, IntRegs, IntRegs,
22028 /* M4_nac_up_s1_sat */
22029 IntRegs, IntRegs, IntRegs, IntRegs,
22030 /* M4_or_and */
22031 IntRegs, IntRegs, IntRegs, IntRegs,
22032 /* M4_or_andn */
22033 IntRegs, IntRegs, IntRegs, IntRegs,
22034 /* M4_or_or */
22035 IntRegs, IntRegs, IntRegs, IntRegs,
22036 /* M4_or_xor */
22037 IntRegs, IntRegs, IntRegs, IntRegs,
22038 /* M4_pmpyw */
22039 DoubleRegs, IntRegs, IntRegs,
22040 /* M4_pmpyw_acc */
22041 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
22042 /* M4_vpmpyh */
22043 DoubleRegs, IntRegs, IntRegs,
22044 /* M4_vpmpyh_acc */
22045 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
22046 /* M4_vrmpyeh_acc_s0 */
22047 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
22048 /* M4_vrmpyeh_acc_s1 */
22049 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
22050 /* M4_vrmpyeh_s0 */
22051 DoubleRegs, DoubleRegs, DoubleRegs,
22052 /* M4_vrmpyeh_s1 */
22053 DoubleRegs, DoubleRegs, DoubleRegs,
22054 /* M4_vrmpyoh_acc_s0 */
22055 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
22056 /* M4_vrmpyoh_acc_s1 */
22057 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
22058 /* M4_vrmpyoh_s0 */
22059 DoubleRegs, DoubleRegs, DoubleRegs,
22060 /* M4_vrmpyoh_s1 */
22061 DoubleRegs, DoubleRegs, DoubleRegs,
22062 /* M4_xor_and */
22063 IntRegs, IntRegs, IntRegs, IntRegs,
22064 /* M4_xor_andn */
22065 IntRegs, IntRegs, IntRegs, IntRegs,
22066 /* M4_xor_or */
22067 IntRegs, IntRegs, IntRegs, IntRegs,
22068 /* M4_xor_xacc */
22069 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
22070 /* M5_vdmacbsu */
22071 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
22072 /* M5_vdmpybsu */
22073 DoubleRegs, DoubleRegs, DoubleRegs,
22074 /* M5_vmacbsu */
22075 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
22076 /* M5_vmacbuu */
22077 DoubleRegs, DoubleRegs, IntRegs, IntRegs,
22078 /* M5_vmpybsu */
22079 DoubleRegs, IntRegs, IntRegs,
22080 /* M5_vmpybuu */
22081 DoubleRegs, IntRegs, IntRegs,
22082 /* M5_vrmacbsu */
22083 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
22084 /* M5_vrmacbuu */
22085 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
22086 /* M5_vrmpybsu */
22087 DoubleRegs, DoubleRegs, DoubleRegs,
22088 /* M5_vrmpybuu */
22089 DoubleRegs, DoubleRegs, DoubleRegs,
22090 /* M6_vabsdiffb */
22091 DoubleRegs, DoubleRegs, DoubleRegs,
22092 /* M6_vabsdiffub */
22093 DoubleRegs, DoubleRegs, DoubleRegs,
22094 /* M7_dcmpyiw */
22095 DoubleRegs, DoubleRegs, DoubleRegs,
22096 /* M7_dcmpyiw_acc */
22097 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
22098 /* M7_dcmpyiwc */
22099 DoubleRegs, DoubleRegs, DoubleRegs,
22100 /* M7_dcmpyiwc_acc */
22101 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
22102 /* M7_dcmpyrw */
22103 DoubleRegs, DoubleRegs, DoubleRegs,
22104 /* M7_dcmpyrw_acc */
22105 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
22106 /* M7_dcmpyrwc */
22107 DoubleRegs, DoubleRegs, DoubleRegs,
22108 /* M7_dcmpyrwc_acc */
22109 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
22110 /* M7_wcmpyiw */
22111 IntRegs, DoubleRegs, DoubleRegs,
22112 /* M7_wcmpyiw_rnd */
22113 IntRegs, DoubleRegs, DoubleRegs,
22114 /* M7_wcmpyiwc */
22115 IntRegs, DoubleRegs, DoubleRegs,
22116 /* M7_wcmpyiwc_rnd */
22117 IntRegs, DoubleRegs, DoubleRegs,
22118 /* M7_wcmpyrw */
22119 IntRegs, DoubleRegs, DoubleRegs,
22120 /* M7_wcmpyrw_rnd */
22121 IntRegs, DoubleRegs, DoubleRegs,
22122 /* M7_wcmpyrwc */
22123 IntRegs, DoubleRegs, DoubleRegs,
22124 /* M7_wcmpyrwc_rnd */
22125 IntRegs, DoubleRegs, DoubleRegs,
22126 /* PS_call_stk */
22127 a30_2Imm,
22128 /* PS_callr_nr */
22129 IntRegs,
22130 /* PS_jmpret */
22131 IntRegs,
22132 /* PS_jmpretf */
22133 PredRegs, IntRegs,
22134 /* PS_jmpretfnew */
22135 PredRegs, IntRegs,
22136 /* PS_jmpretfnewpt */
22137 PredRegs, IntRegs,
22138 /* PS_jmprett */
22139 PredRegs, IntRegs,
22140 /* PS_jmprettnew */
22141 PredRegs, IntRegs,
22142 /* PS_jmprettnewpt */
22143 PredRegs, IntRegs,
22144 /* PS_loadrbabs */
22145 IntRegs, u32_0Imm,
22146 /* PS_loadrdabs */
22147 DoubleRegs, u29_3Imm,
22148 /* PS_loadrhabs */
22149 IntRegs, u31_1Imm,
22150 /* PS_loadriabs */
22151 IntRegs, u30_2Imm,
22152 /* PS_loadrubabs */
22153 IntRegs, u32_0Imm,
22154 /* PS_loadruhabs */
22155 IntRegs, u31_1Imm,
22156 /* PS_storerbabs */
22157 u32_0Imm, IntRegs,
22158 /* PS_storerbnewabs */
22159 u32_0Imm, IntRegs,
22160 /* PS_storerdabs */
22161 u29_3Imm, DoubleRegs,
22162 /* PS_storerfabs */
22163 u31_1Imm, IntRegs,
22164 /* PS_storerhabs */
22165 u31_1Imm, IntRegs,
22166 /* PS_storerhnewabs */
22167 u31_1Imm, IntRegs,
22168 /* PS_storeriabs */
22169 u30_2Imm, IntRegs,
22170 /* PS_storerinewabs */
22171 u30_2Imm, IntRegs,
22172 /* PS_trap1 */
22173 u8_0Imm,
22174 /* R6_release_at_vi */
22175 IntRegs,
22176 /* R6_release_st_vi */
22177 IntRegs,
22178 /* RESTORE_DEALLOC_BEFORE_TAILCALL_V4 */
22179 a30_2Imm,
22180 /* RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT */
22181 a30_2Imm,
22182 /* RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC */
22183 a30_2Imm,
22184 /* RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC */
22185 a30_2Imm,
22186 /* RESTORE_DEALLOC_RET_JMP_V4 */
22187 b30_2Imm,
22188 /* RESTORE_DEALLOC_RET_JMP_V4_EXT */
22189 b30_2Imm,
22190 /* RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC */
22191 b30_2Imm,
22192 /* RESTORE_DEALLOC_RET_JMP_V4_PIC */
22193 b30_2Imm,
22194 /* S2_addasl_rrri */
22195 IntRegs, IntRegs, IntRegs, u3_0Imm,
22196 /* S2_allocframe */
22197 IntRegs, IntRegs, u11_3Imm,
22198 /* S2_asl_i_p */
22199 DoubleRegs, DoubleRegs, u6_0Imm,
22200 /* S2_asl_i_p_acc */
22201 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22202 /* S2_asl_i_p_and */
22203 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22204 /* S2_asl_i_p_nac */
22205 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22206 /* S2_asl_i_p_or */
22207 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22208 /* S2_asl_i_p_xacc */
22209 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22210 /* S2_asl_i_r */
22211 IntRegs, IntRegs, u5_0Imm,
22212 /* S2_asl_i_r_acc */
22213 IntRegs, IntRegs, IntRegs, u5_0Imm,
22214 /* S2_asl_i_r_and */
22215 IntRegs, IntRegs, IntRegs, u5_0Imm,
22216 /* S2_asl_i_r_nac */
22217 IntRegs, IntRegs, IntRegs, u5_0Imm,
22218 /* S2_asl_i_r_or */
22219 IntRegs, IntRegs, IntRegs, u5_0Imm,
22220 /* S2_asl_i_r_sat */
22221 IntRegs, IntRegs, u5_0Imm,
22222 /* S2_asl_i_r_xacc */
22223 IntRegs, IntRegs, IntRegs, u5_0Imm,
22224 /* S2_asl_i_vh */
22225 DoubleRegs, DoubleRegs, u4_0Imm,
22226 /* S2_asl_i_vw */
22227 DoubleRegs, DoubleRegs, u5_0Imm,
22228 /* S2_asl_r_p */
22229 DoubleRegs, DoubleRegs, IntRegs,
22230 /* S2_asl_r_p_acc */
22231 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22232 /* S2_asl_r_p_and */
22233 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22234 /* S2_asl_r_p_nac */
22235 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22236 /* S2_asl_r_p_or */
22237 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22238 /* S2_asl_r_p_xor */
22239 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22240 /* S2_asl_r_r */
22241 IntRegs, IntRegs, IntRegs,
22242 /* S2_asl_r_r_acc */
22243 IntRegs, IntRegs, IntRegs, IntRegs,
22244 /* S2_asl_r_r_and */
22245 IntRegs, IntRegs, IntRegs, IntRegs,
22246 /* S2_asl_r_r_nac */
22247 IntRegs, IntRegs, IntRegs, IntRegs,
22248 /* S2_asl_r_r_or */
22249 IntRegs, IntRegs, IntRegs, IntRegs,
22250 /* S2_asl_r_r_sat */
22251 IntRegs, IntRegs, IntRegs,
22252 /* S2_asl_r_vh */
22253 DoubleRegs, DoubleRegs, IntRegs,
22254 /* S2_asl_r_vw */
22255 DoubleRegs, DoubleRegs, IntRegs,
22256 /* S2_asr_i_p */
22257 DoubleRegs, DoubleRegs, u6_0Imm,
22258 /* S2_asr_i_p_acc */
22259 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22260 /* S2_asr_i_p_and */
22261 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22262 /* S2_asr_i_p_nac */
22263 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22264 /* S2_asr_i_p_or */
22265 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22266 /* S2_asr_i_p_rnd */
22267 DoubleRegs, DoubleRegs, u6_0Imm,
22268 /* S2_asr_i_r */
22269 IntRegs, IntRegs, u5_0Imm,
22270 /* S2_asr_i_r_acc */
22271 IntRegs, IntRegs, IntRegs, u5_0Imm,
22272 /* S2_asr_i_r_and */
22273 IntRegs, IntRegs, IntRegs, u5_0Imm,
22274 /* S2_asr_i_r_nac */
22275 IntRegs, IntRegs, IntRegs, u5_0Imm,
22276 /* S2_asr_i_r_or */
22277 IntRegs, IntRegs, IntRegs, u5_0Imm,
22278 /* S2_asr_i_r_rnd */
22279 IntRegs, IntRegs, u5_0Imm,
22280 /* S2_asr_i_svw_trun */
22281 IntRegs, DoubleRegs, u5_0Imm,
22282 /* S2_asr_i_vh */
22283 DoubleRegs, DoubleRegs, u4_0Imm,
22284 /* S2_asr_i_vw */
22285 DoubleRegs, DoubleRegs, u5_0Imm,
22286 /* S2_asr_r_p */
22287 DoubleRegs, DoubleRegs, IntRegs,
22288 /* S2_asr_r_p_acc */
22289 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22290 /* S2_asr_r_p_and */
22291 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22292 /* S2_asr_r_p_nac */
22293 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22294 /* S2_asr_r_p_or */
22295 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22296 /* S2_asr_r_p_xor */
22297 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22298 /* S2_asr_r_r */
22299 IntRegs, IntRegs, IntRegs,
22300 /* S2_asr_r_r_acc */
22301 IntRegs, IntRegs, IntRegs, IntRegs,
22302 /* S2_asr_r_r_and */
22303 IntRegs, IntRegs, IntRegs, IntRegs,
22304 /* S2_asr_r_r_nac */
22305 IntRegs, IntRegs, IntRegs, IntRegs,
22306 /* S2_asr_r_r_or */
22307 IntRegs, IntRegs, IntRegs, IntRegs,
22308 /* S2_asr_r_r_sat */
22309 IntRegs, IntRegs, IntRegs,
22310 /* S2_asr_r_svw_trun */
22311 IntRegs, DoubleRegs, IntRegs,
22312 /* S2_asr_r_vh */
22313 DoubleRegs, DoubleRegs, IntRegs,
22314 /* S2_asr_r_vw */
22315 DoubleRegs, DoubleRegs, IntRegs,
22316 /* S2_brev */
22317 IntRegs, IntRegs,
22318 /* S2_brevp */
22319 DoubleRegs, DoubleRegs,
22320 /* S2_cabacdecbin */
22321 DoubleRegs, DoubleRegs, DoubleRegs,
22322 /* S2_cl0 */
22323 IntRegs, IntRegs,
22324 /* S2_cl0p */
22325 IntRegs, DoubleRegs,
22326 /* S2_cl1 */
22327 IntRegs, IntRegs,
22328 /* S2_cl1p */
22329 IntRegs, DoubleRegs,
22330 /* S2_clb */
22331 IntRegs, IntRegs,
22332 /* S2_clbnorm */
22333 IntRegs, IntRegs,
22334 /* S2_clbp */
22335 IntRegs, DoubleRegs,
22336 /* S2_clrbit_i */
22337 IntRegs, IntRegs, u5_0Imm,
22338 /* S2_clrbit_r */
22339 IntRegs, IntRegs, IntRegs,
22340 /* S2_ct0 */
22341 IntRegs, IntRegs,
22342 /* S2_ct0p */
22343 IntRegs, DoubleRegs,
22344 /* S2_ct1 */
22345 IntRegs, IntRegs,
22346 /* S2_ct1p */
22347 IntRegs, DoubleRegs,
22348 /* S2_deinterleave */
22349 DoubleRegs, DoubleRegs,
22350 /* S2_extractu */
22351 IntRegs, IntRegs, u5_0Imm, u5_0Imm,
22352 /* S2_extractu_rp */
22353 IntRegs, IntRegs, DoubleRegs,
22354 /* S2_extractup */
22355 DoubleRegs, DoubleRegs, u6_0Imm, u6_0Imm,
22356 /* S2_extractup_rp */
22357 DoubleRegs, DoubleRegs, DoubleRegs,
22358 /* S2_insert */
22359 IntRegs, IntRegs, IntRegs, u5_0Imm, u5_0Imm,
22360 /* S2_insert_rp */
22361 IntRegs, IntRegs, IntRegs, DoubleRegs,
22362 /* S2_insertp */
22363 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm, u6_0Imm,
22364 /* S2_insertp_rp */
22365 DoubleRegs, DoubleRegs, DoubleRegs, DoubleRegs,
22366 /* S2_interleave */
22367 DoubleRegs, DoubleRegs,
22368 /* S2_lfsp */
22369 DoubleRegs, DoubleRegs, DoubleRegs,
22370 /* S2_lsl_r_p */
22371 DoubleRegs, DoubleRegs, IntRegs,
22372 /* S2_lsl_r_p_acc */
22373 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22374 /* S2_lsl_r_p_and */
22375 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22376 /* S2_lsl_r_p_nac */
22377 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22378 /* S2_lsl_r_p_or */
22379 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22380 /* S2_lsl_r_p_xor */
22381 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22382 /* S2_lsl_r_r */
22383 IntRegs, IntRegs, IntRegs,
22384 /* S2_lsl_r_r_acc */
22385 IntRegs, IntRegs, IntRegs, IntRegs,
22386 /* S2_lsl_r_r_and */
22387 IntRegs, IntRegs, IntRegs, IntRegs,
22388 /* S2_lsl_r_r_nac */
22389 IntRegs, IntRegs, IntRegs, IntRegs,
22390 /* S2_lsl_r_r_or */
22391 IntRegs, IntRegs, IntRegs, IntRegs,
22392 /* S2_lsl_r_vh */
22393 DoubleRegs, DoubleRegs, IntRegs,
22394 /* S2_lsl_r_vw */
22395 DoubleRegs, DoubleRegs, IntRegs,
22396 /* S2_lsr_i_p */
22397 DoubleRegs, DoubleRegs, u6_0Imm,
22398 /* S2_lsr_i_p_acc */
22399 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22400 /* S2_lsr_i_p_and */
22401 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22402 /* S2_lsr_i_p_nac */
22403 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22404 /* S2_lsr_i_p_or */
22405 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22406 /* S2_lsr_i_p_xacc */
22407 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
22408 /* S2_lsr_i_r */
22409 IntRegs, IntRegs, u5_0Imm,
22410 /* S2_lsr_i_r_acc */
22411 IntRegs, IntRegs, IntRegs, u5_0Imm,
22412 /* S2_lsr_i_r_and */
22413 IntRegs, IntRegs, IntRegs, u5_0Imm,
22414 /* S2_lsr_i_r_nac */
22415 IntRegs, IntRegs, IntRegs, u5_0Imm,
22416 /* S2_lsr_i_r_or */
22417 IntRegs, IntRegs, IntRegs, u5_0Imm,
22418 /* S2_lsr_i_r_xacc */
22419 IntRegs, IntRegs, IntRegs, u5_0Imm,
22420 /* S2_lsr_i_vh */
22421 DoubleRegs, DoubleRegs, u4_0Imm,
22422 /* S2_lsr_i_vw */
22423 DoubleRegs, DoubleRegs, u5_0Imm,
22424 /* S2_lsr_r_p */
22425 DoubleRegs, DoubleRegs, IntRegs,
22426 /* S2_lsr_r_p_acc */
22427 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22428 /* S2_lsr_r_p_and */
22429 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22430 /* S2_lsr_r_p_nac */
22431 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22432 /* S2_lsr_r_p_or */
22433 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22434 /* S2_lsr_r_p_xor */
22435 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22436 /* S2_lsr_r_r */
22437 IntRegs, IntRegs, IntRegs,
22438 /* S2_lsr_r_r_acc */
22439 IntRegs, IntRegs, IntRegs, IntRegs,
22440 /* S2_lsr_r_r_and */
22441 IntRegs, IntRegs, IntRegs, IntRegs,
22442 /* S2_lsr_r_r_nac */
22443 IntRegs, IntRegs, IntRegs, IntRegs,
22444 /* S2_lsr_r_r_or */
22445 IntRegs, IntRegs, IntRegs, IntRegs,
22446 /* S2_lsr_r_vh */
22447 DoubleRegs, DoubleRegs, IntRegs,
22448 /* S2_lsr_r_vw */
22449 DoubleRegs, DoubleRegs, IntRegs,
22450 /* S2_mask */
22451 IntRegs, u5_0Imm, u5_0Imm,
22452 /* S2_packhl */
22453 DoubleRegs, IntRegs, IntRegs,
22454 /* S2_parityp */
22455 IntRegs, DoubleRegs, DoubleRegs,
22456 /* S2_pstorerbf_io */
22457 PredRegs, IntRegs, u32_0Imm, IntRegs,
22458 /* S2_pstorerbf_pi */
22459 IntRegs, PredRegs, IntRegs, s4_0Imm, IntRegs,
22460 /* S2_pstorerbfnew_pi */
22461 IntRegs, PredRegs, IntRegs, s4_0Imm, IntRegs,
22462 /* S2_pstorerbnewf_io */
22463 PredRegs, IntRegs, u32_0Imm, IntRegs,
22464 /* S2_pstorerbnewf_pi */
22465 IntRegs, PredRegs, IntRegs, s4_0Imm, IntRegs,
22466 /* S2_pstorerbnewfnew_pi */
22467 IntRegs, PredRegs, IntRegs, s4_0Imm, IntRegs,
22468 /* S2_pstorerbnewt_io */
22469 PredRegs, IntRegs, u32_0Imm, IntRegs,
22470 /* S2_pstorerbnewt_pi */
22471 IntRegs, PredRegs, IntRegs, s4_0Imm, IntRegs,
22472 /* S2_pstorerbnewtnew_pi */
22473 IntRegs, PredRegs, IntRegs, s4_0Imm, IntRegs,
22474 /* S2_pstorerbt_io */
22475 PredRegs, IntRegs, u32_0Imm, IntRegs,
22476 /* S2_pstorerbt_pi */
22477 IntRegs, PredRegs, IntRegs, s4_0Imm, IntRegs,
22478 /* S2_pstorerbtnew_pi */
22479 IntRegs, PredRegs, IntRegs, s4_0Imm, IntRegs,
22480 /* S2_pstorerdf_io */
22481 PredRegs, IntRegs, u29_3Imm, DoubleRegs,
22482 /* S2_pstorerdf_pi */
22483 IntRegs, PredRegs, IntRegs, s4_3Imm, DoubleRegs,
22484 /* S2_pstorerdfnew_pi */
22485 IntRegs, PredRegs, IntRegs, s4_3Imm, DoubleRegs,
22486 /* S2_pstorerdt_io */
22487 PredRegs, IntRegs, u29_3Imm, DoubleRegs,
22488 /* S2_pstorerdt_pi */
22489 IntRegs, PredRegs, IntRegs, s4_3Imm, DoubleRegs,
22490 /* S2_pstorerdtnew_pi */
22491 IntRegs, PredRegs, IntRegs, s4_3Imm, DoubleRegs,
22492 /* S2_pstorerff_io */
22493 PredRegs, IntRegs, u31_1Imm, IntRegs,
22494 /* S2_pstorerff_pi */
22495 IntRegs, PredRegs, IntRegs, s4_1Imm, IntRegs,
22496 /* S2_pstorerffnew_pi */
22497 IntRegs, PredRegs, IntRegs, s4_1Imm, IntRegs,
22498 /* S2_pstorerft_io */
22499 PredRegs, IntRegs, u31_1Imm, IntRegs,
22500 /* S2_pstorerft_pi */
22501 IntRegs, PredRegs, IntRegs, s4_1Imm, IntRegs,
22502 /* S2_pstorerftnew_pi */
22503 IntRegs, PredRegs, IntRegs, s4_1Imm, IntRegs,
22504 /* S2_pstorerhf_io */
22505 PredRegs, IntRegs, u31_1Imm, IntRegs,
22506 /* S2_pstorerhf_pi */
22507 IntRegs, PredRegs, IntRegs, s4_1Imm, IntRegs,
22508 /* S2_pstorerhfnew_pi */
22509 IntRegs, PredRegs, IntRegs, s4_1Imm, IntRegs,
22510 /* S2_pstorerhnewf_io */
22511 PredRegs, IntRegs, u31_1Imm, IntRegs,
22512 /* S2_pstorerhnewf_pi */
22513 IntRegs, PredRegs, IntRegs, s4_1Imm, IntRegs,
22514 /* S2_pstorerhnewfnew_pi */
22515 IntRegs, PredRegs, IntRegs, s4_1Imm, IntRegs,
22516 /* S2_pstorerhnewt_io */
22517 PredRegs, IntRegs, u31_1Imm, IntRegs,
22518 /* S2_pstorerhnewt_pi */
22519 IntRegs, PredRegs, IntRegs, s4_1Imm, IntRegs,
22520 /* S2_pstorerhnewtnew_pi */
22521 IntRegs, PredRegs, IntRegs, s4_1Imm, IntRegs,
22522 /* S2_pstorerht_io */
22523 PredRegs, IntRegs, u31_1Imm, IntRegs,
22524 /* S2_pstorerht_pi */
22525 IntRegs, PredRegs, IntRegs, s4_1Imm, IntRegs,
22526 /* S2_pstorerhtnew_pi */
22527 IntRegs, PredRegs, IntRegs, s4_1Imm, IntRegs,
22528 /* S2_pstorerif_io */
22529 PredRegs, IntRegs, u30_2Imm, IntRegs,
22530 /* S2_pstorerif_pi */
22531 IntRegs, PredRegs, IntRegs, s4_2Imm, IntRegs,
22532 /* S2_pstorerifnew_pi */
22533 IntRegs, PredRegs, IntRegs, s4_2Imm, IntRegs,
22534 /* S2_pstorerinewf_io */
22535 PredRegs, IntRegs, u30_2Imm, IntRegs,
22536 /* S2_pstorerinewf_pi */
22537 IntRegs, PredRegs, IntRegs, s4_2Imm, IntRegs,
22538 /* S2_pstorerinewfnew_pi */
22539 IntRegs, PredRegs, IntRegs, s4_2Imm, IntRegs,
22540 /* S2_pstorerinewt_io */
22541 PredRegs, IntRegs, u30_2Imm, IntRegs,
22542 /* S2_pstorerinewt_pi */
22543 IntRegs, PredRegs, IntRegs, s4_2Imm, IntRegs,
22544 /* S2_pstorerinewtnew_pi */
22545 IntRegs, PredRegs, IntRegs, s4_2Imm, IntRegs,
22546 /* S2_pstorerit_io */
22547 PredRegs, IntRegs, u30_2Imm, IntRegs,
22548 /* S2_pstorerit_pi */
22549 IntRegs, PredRegs, IntRegs, s4_2Imm, IntRegs,
22550 /* S2_pstoreritnew_pi */
22551 IntRegs, PredRegs, IntRegs, s4_2Imm, IntRegs,
22552 /* S2_setbit_i */
22553 IntRegs, IntRegs, u5_0Imm,
22554 /* S2_setbit_r */
22555 IntRegs, IntRegs, IntRegs,
22556 /* S2_shuffeb */
22557 DoubleRegs, DoubleRegs, DoubleRegs,
22558 /* S2_shuffeh */
22559 DoubleRegs, DoubleRegs, DoubleRegs,
22560 /* S2_shuffob */
22561 DoubleRegs, DoubleRegs, DoubleRegs,
22562 /* S2_shuffoh */
22563 DoubleRegs, DoubleRegs, DoubleRegs,
22564 /* S2_storerb_io */
22565 IntRegs, s32_0Imm, IntRegs,
22566 /* S2_storerb_pbr */
22567 IntRegs, IntRegs, ModRegs, IntRegs,
22568 /* S2_storerb_pci */
22569 IntRegs, IntRegs, s4_0Imm, ModRegs, IntRegs,
22570 /* S2_storerb_pcr */
22571 IntRegs, IntRegs, ModRegs, IntRegs,
22572 /* S2_storerb_pi */
22573 IntRegs, IntRegs, s4_0Imm, IntRegs,
22574 /* S2_storerb_pr */
22575 IntRegs, IntRegs, ModRegs, IntRegs,
22576 /* S2_storerbgp */
22577 u32_0Imm, IntRegs,
22578 /* S2_storerbnew_io */
22579 IntRegs, s32_0Imm, IntRegs,
22580 /* S2_storerbnew_pbr */
22581 IntRegs, IntRegs, ModRegs, IntRegs,
22582 /* S2_storerbnew_pci */
22583 IntRegs, IntRegs, s4_0Imm, ModRegs, IntRegs,
22584 /* S2_storerbnew_pcr */
22585 IntRegs, IntRegs, ModRegs, IntRegs,
22586 /* S2_storerbnew_pi */
22587 IntRegs, IntRegs, s4_0Imm, IntRegs,
22588 /* S2_storerbnew_pr */
22589 IntRegs, IntRegs, ModRegs, IntRegs,
22590 /* S2_storerbnewgp */
22591 u32_0Imm, IntRegs,
22592 /* S2_storerd_io */
22593 IntRegs, s29_3Imm, DoubleRegs,
22594 /* S2_storerd_pbr */
22595 IntRegs, IntRegs, ModRegs, DoubleRegs,
22596 /* S2_storerd_pci */
22597 IntRegs, IntRegs, s4_3Imm, ModRegs, DoubleRegs,
22598 /* S2_storerd_pcr */
22599 IntRegs, IntRegs, ModRegs, DoubleRegs,
22600 /* S2_storerd_pi */
22601 IntRegs, IntRegs, s4_3Imm, DoubleRegs,
22602 /* S2_storerd_pr */
22603 IntRegs, IntRegs, ModRegs, DoubleRegs,
22604 /* S2_storerdgp */
22605 u29_3Imm, DoubleRegs,
22606 /* S2_storerf_io */
22607 IntRegs, s31_1Imm, IntRegs,
22608 /* S2_storerf_pbr */
22609 IntRegs, IntRegs, ModRegs, IntRegs,
22610 /* S2_storerf_pci */
22611 IntRegs, IntRegs, s4_1Imm, ModRegs, IntRegs,
22612 /* S2_storerf_pcr */
22613 IntRegs, IntRegs, ModRegs, IntRegs,
22614 /* S2_storerf_pi */
22615 IntRegs, IntRegs, s4_1Imm, IntRegs,
22616 /* S2_storerf_pr */
22617 IntRegs, IntRegs, ModRegs, IntRegs,
22618 /* S2_storerfgp */
22619 u31_1Imm, IntRegs,
22620 /* S2_storerh_io */
22621 IntRegs, s31_1Imm, IntRegs,
22622 /* S2_storerh_pbr */
22623 IntRegs, IntRegs, ModRegs, IntRegs,
22624 /* S2_storerh_pci */
22625 IntRegs, IntRegs, s4_1Imm, ModRegs, IntRegs,
22626 /* S2_storerh_pcr */
22627 IntRegs, IntRegs, ModRegs, IntRegs,
22628 /* S2_storerh_pi */
22629 IntRegs, IntRegs, s4_1Imm, IntRegs,
22630 /* S2_storerh_pr */
22631 IntRegs, IntRegs, ModRegs, IntRegs,
22632 /* S2_storerhgp */
22633 u31_1Imm, IntRegs,
22634 /* S2_storerhnew_io */
22635 IntRegs, s31_1Imm, IntRegs,
22636 /* S2_storerhnew_pbr */
22637 IntRegs, IntRegs, ModRegs, IntRegs,
22638 /* S2_storerhnew_pci */
22639 IntRegs, IntRegs, s4_1Imm, ModRegs, IntRegs,
22640 /* S2_storerhnew_pcr */
22641 IntRegs, IntRegs, ModRegs, IntRegs,
22642 /* S2_storerhnew_pi */
22643 IntRegs, IntRegs, s4_1Imm, IntRegs,
22644 /* S2_storerhnew_pr */
22645 IntRegs, IntRegs, ModRegs, IntRegs,
22646 /* S2_storerhnewgp */
22647 u31_1Imm, IntRegs,
22648 /* S2_storeri_io */
22649 IntRegs, s30_2Imm, IntRegs,
22650 /* S2_storeri_pbr */
22651 IntRegs, IntRegs, ModRegs, IntRegs,
22652 /* S2_storeri_pci */
22653 IntRegs, IntRegs, s4_2Imm, ModRegs, IntRegs,
22654 /* S2_storeri_pcr */
22655 IntRegs, IntRegs, ModRegs, IntRegs,
22656 /* S2_storeri_pi */
22657 IntRegs, IntRegs, s4_2Imm, IntRegs,
22658 /* S2_storeri_pr */
22659 IntRegs, IntRegs, ModRegs, IntRegs,
22660 /* S2_storerigp */
22661 u30_2Imm, IntRegs,
22662 /* S2_storerinew_io */
22663 IntRegs, s30_2Imm, IntRegs,
22664 /* S2_storerinew_pbr */
22665 IntRegs, IntRegs, ModRegs, IntRegs,
22666 /* S2_storerinew_pci */
22667 IntRegs, IntRegs, s4_2Imm, ModRegs, IntRegs,
22668 /* S2_storerinew_pcr */
22669 IntRegs, IntRegs, ModRegs, IntRegs,
22670 /* S2_storerinew_pi */
22671 IntRegs, IntRegs, s4_2Imm, IntRegs,
22672 /* S2_storerinew_pr */
22673 IntRegs, IntRegs, ModRegs, IntRegs,
22674 /* S2_storerinewgp */
22675 u30_2Imm, IntRegs,
22676 /* S2_storew_locked */
22677 PredRegs, IntRegs, IntRegs,
22678 /* S2_storew_rl_at_vi */
22679 IntRegs, IntRegs,
22680 /* S2_storew_rl_st_vi */
22681 IntRegs, IntRegs,
22682 /* S2_svsathb */
22683 IntRegs, IntRegs,
22684 /* S2_svsathub */
22685 IntRegs, IntRegs,
22686 /* S2_tableidxb */
22687 IntRegs, IntRegs, IntRegs, u4_0Imm, s6_0Imm,
22688 /* S2_tableidxd */
22689 IntRegs, IntRegs, IntRegs, u4_0Imm, s6_0Imm,
22690 /* S2_tableidxh */
22691 IntRegs, IntRegs, IntRegs, u4_0Imm, s6_0Imm,
22692 /* S2_tableidxw */
22693 IntRegs, IntRegs, IntRegs, u4_0Imm, s6_0Imm,
22694 /* S2_togglebit_i */
22695 IntRegs, IntRegs, u5_0Imm,
22696 /* S2_togglebit_r */
22697 IntRegs, IntRegs, IntRegs,
22698 /* S2_tstbit_i */
22699 PredRegs, IntRegs, u5_0Imm,
22700 /* S2_tstbit_r */
22701 PredRegs, IntRegs, IntRegs,
22702 /* S2_valignib */
22703 DoubleRegs, DoubleRegs, DoubleRegs, u3_0Imm,
22704 /* S2_valignrb */
22705 DoubleRegs, DoubleRegs, DoubleRegs, PredRegs,
22706 /* S2_vcnegh */
22707 DoubleRegs, DoubleRegs, IntRegs,
22708 /* S2_vcrotate */
22709 DoubleRegs, DoubleRegs, IntRegs,
22710 /* S2_vrcnegh */
22711 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs,
22712 /* S2_vrndpackwh */
22713 IntRegs, DoubleRegs,
22714 /* S2_vrndpackwhs */
22715 IntRegs, DoubleRegs,
22716 /* S2_vsathb */
22717 IntRegs, DoubleRegs,
22718 /* S2_vsathb_nopack */
22719 DoubleRegs, DoubleRegs,
22720 /* S2_vsathub */
22721 IntRegs, DoubleRegs,
22722 /* S2_vsathub_nopack */
22723 DoubleRegs, DoubleRegs,
22724 /* S2_vsatwh */
22725 IntRegs, DoubleRegs,
22726 /* S2_vsatwh_nopack */
22727 DoubleRegs, DoubleRegs,
22728 /* S2_vsatwuh */
22729 IntRegs, DoubleRegs,
22730 /* S2_vsatwuh_nopack */
22731 DoubleRegs, DoubleRegs,
22732 /* S2_vsplatrb */
22733 IntRegs, IntRegs,
22734 /* S2_vsplatrh */
22735 DoubleRegs, IntRegs,
22736 /* S2_vspliceib */
22737 DoubleRegs, DoubleRegs, DoubleRegs, u3_0Imm,
22738 /* S2_vsplicerb */
22739 DoubleRegs, DoubleRegs, DoubleRegs, PredRegs,
22740 /* S2_vsxtbh */
22741 DoubleRegs, IntRegs,
22742 /* S2_vsxthw */
22743 DoubleRegs, IntRegs,
22744 /* S2_vtrunehb */
22745 IntRegs, DoubleRegs,
22746 /* S2_vtrunewh */
22747 DoubleRegs, DoubleRegs, DoubleRegs,
22748 /* S2_vtrunohb */
22749 IntRegs, DoubleRegs,
22750 /* S2_vtrunowh */
22751 DoubleRegs, DoubleRegs, DoubleRegs,
22752 /* S2_vzxtbh */
22753 DoubleRegs, IntRegs,
22754 /* S2_vzxthw */
22755 DoubleRegs, IntRegs,
22756 /* S4_addaddi */
22757 IntRegs, IntRegs, IntRegs, s32_0Imm,
22758 /* S4_addi_asl_ri */
22759 IntRegs, u32_0Imm, IntRegs, u5_0Imm,
22760 /* S4_addi_lsr_ri */
22761 IntRegs, u32_0Imm, IntRegs, u5_0Imm,
22762 /* S4_andi_asl_ri */
22763 IntRegs, u32_0Imm, IntRegs, u5_0Imm,
22764 /* S4_andi_lsr_ri */
22765 IntRegs, u32_0Imm, IntRegs, u5_0Imm,
22766 /* S4_clbaddi */
22767 IntRegs, IntRegs, s6_0Imm,
22768 /* S4_clbpaddi */
22769 IntRegs, DoubleRegs, s6_0Imm,
22770 /* S4_clbpnorm */
22771 IntRegs, DoubleRegs,
22772 /* S4_extract */
22773 IntRegs, IntRegs, u5_0Imm, u5_0Imm,
22774 /* S4_extract_rp */
22775 IntRegs, IntRegs, DoubleRegs,
22776 /* S4_extractp */
22777 DoubleRegs, DoubleRegs, u6_0Imm, u6_0Imm,
22778 /* S4_extractp_rp */
22779 DoubleRegs, DoubleRegs, DoubleRegs,
22780 /* S4_lsli */
22781 IntRegs, s6_0Imm, IntRegs,
22782 /* S4_ntstbit_i */
22783 PredRegs, IntRegs, u5_0Imm,
22784 /* S4_ntstbit_r */
22785 PredRegs, IntRegs, IntRegs,
22786 /* S4_or_andi */
22787 IntRegs, IntRegs, IntRegs, s32_0Imm,
22788 /* S4_or_andix */
22789 IntRegs, IntRegs, IntRegs, s32_0Imm,
22790 /* S4_or_ori */
22791 IntRegs, IntRegs, IntRegs, s32_0Imm,
22792 /* S4_ori_asl_ri */
22793 IntRegs, u32_0Imm, IntRegs, u5_0Imm,
22794 /* S4_ori_lsr_ri */
22795 IntRegs, u32_0Imm, IntRegs, u5_0Imm,
22796 /* S4_parity */
22797 IntRegs, IntRegs, IntRegs,
22798 /* S4_pstorerbf_abs */
22799 PredRegs, u32_0Imm, IntRegs,
22800 /* S4_pstorerbf_rr */
22801 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22802 /* S4_pstorerbfnew_abs */
22803 PredRegs, u32_0Imm, IntRegs,
22804 /* S4_pstorerbfnew_io */
22805 PredRegs, IntRegs, u32_0Imm, IntRegs,
22806 /* S4_pstorerbfnew_rr */
22807 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22808 /* S4_pstorerbnewf_abs */
22809 PredRegs, u32_0Imm, IntRegs,
22810 /* S4_pstorerbnewf_rr */
22811 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22812 /* S4_pstorerbnewfnew_abs */
22813 PredRegs, u32_0Imm, IntRegs,
22814 /* S4_pstorerbnewfnew_io */
22815 PredRegs, IntRegs, u32_0Imm, IntRegs,
22816 /* S4_pstorerbnewfnew_rr */
22817 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22818 /* S4_pstorerbnewt_abs */
22819 PredRegs, u32_0Imm, IntRegs,
22820 /* S4_pstorerbnewt_rr */
22821 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22822 /* S4_pstorerbnewtnew_abs */
22823 PredRegs, u32_0Imm, IntRegs,
22824 /* S4_pstorerbnewtnew_io */
22825 PredRegs, IntRegs, u32_0Imm, IntRegs,
22826 /* S4_pstorerbnewtnew_rr */
22827 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22828 /* S4_pstorerbt_abs */
22829 PredRegs, u32_0Imm, IntRegs,
22830 /* S4_pstorerbt_rr */
22831 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22832 /* S4_pstorerbtnew_abs */
22833 PredRegs, u32_0Imm, IntRegs,
22834 /* S4_pstorerbtnew_io */
22835 PredRegs, IntRegs, u32_0Imm, IntRegs,
22836 /* S4_pstorerbtnew_rr */
22837 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22838 /* S4_pstorerdf_abs */
22839 PredRegs, u32_0Imm, DoubleRegs,
22840 /* S4_pstorerdf_rr */
22841 PredRegs, IntRegs, IntRegs, u2_0Imm, DoubleRegs,
22842 /* S4_pstorerdfnew_abs */
22843 PredRegs, u32_0Imm, DoubleRegs,
22844 /* S4_pstorerdfnew_io */
22845 PredRegs, IntRegs, u29_3Imm, DoubleRegs,
22846 /* S4_pstorerdfnew_rr */
22847 PredRegs, IntRegs, IntRegs, u2_0Imm, DoubleRegs,
22848 /* S4_pstorerdt_abs */
22849 PredRegs, u32_0Imm, DoubleRegs,
22850 /* S4_pstorerdt_rr */
22851 PredRegs, IntRegs, IntRegs, u2_0Imm, DoubleRegs,
22852 /* S4_pstorerdtnew_abs */
22853 PredRegs, u32_0Imm, DoubleRegs,
22854 /* S4_pstorerdtnew_io */
22855 PredRegs, IntRegs, u29_3Imm, DoubleRegs,
22856 /* S4_pstorerdtnew_rr */
22857 PredRegs, IntRegs, IntRegs, u2_0Imm, DoubleRegs,
22858 /* S4_pstorerff_abs */
22859 PredRegs, u32_0Imm, IntRegs,
22860 /* S4_pstorerff_rr */
22861 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22862 /* S4_pstorerffnew_abs */
22863 PredRegs, u32_0Imm, IntRegs,
22864 /* S4_pstorerffnew_io */
22865 PredRegs, IntRegs, u31_1Imm, IntRegs,
22866 /* S4_pstorerffnew_rr */
22867 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22868 /* S4_pstorerft_abs */
22869 PredRegs, u32_0Imm, IntRegs,
22870 /* S4_pstorerft_rr */
22871 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22872 /* S4_pstorerftnew_abs */
22873 PredRegs, u32_0Imm, IntRegs,
22874 /* S4_pstorerftnew_io */
22875 PredRegs, IntRegs, u31_1Imm, IntRegs,
22876 /* S4_pstorerftnew_rr */
22877 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22878 /* S4_pstorerhf_abs */
22879 PredRegs, u32_0Imm, IntRegs,
22880 /* S4_pstorerhf_rr */
22881 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22882 /* S4_pstorerhfnew_abs */
22883 PredRegs, u32_0Imm, IntRegs,
22884 /* S4_pstorerhfnew_io */
22885 PredRegs, IntRegs, u31_1Imm, IntRegs,
22886 /* S4_pstorerhfnew_rr */
22887 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22888 /* S4_pstorerhnewf_abs */
22889 PredRegs, u32_0Imm, IntRegs,
22890 /* S4_pstorerhnewf_rr */
22891 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22892 /* S4_pstorerhnewfnew_abs */
22893 PredRegs, u32_0Imm, IntRegs,
22894 /* S4_pstorerhnewfnew_io */
22895 PredRegs, IntRegs, u31_1Imm, IntRegs,
22896 /* S4_pstorerhnewfnew_rr */
22897 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22898 /* S4_pstorerhnewt_abs */
22899 PredRegs, u32_0Imm, IntRegs,
22900 /* S4_pstorerhnewt_rr */
22901 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22902 /* S4_pstorerhnewtnew_abs */
22903 PredRegs, u32_0Imm, IntRegs,
22904 /* S4_pstorerhnewtnew_io */
22905 PredRegs, IntRegs, u31_1Imm, IntRegs,
22906 /* S4_pstorerhnewtnew_rr */
22907 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22908 /* S4_pstorerht_abs */
22909 PredRegs, u32_0Imm, IntRegs,
22910 /* S4_pstorerht_rr */
22911 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22912 /* S4_pstorerhtnew_abs */
22913 PredRegs, u32_0Imm, IntRegs,
22914 /* S4_pstorerhtnew_io */
22915 PredRegs, IntRegs, u31_1Imm, IntRegs,
22916 /* S4_pstorerhtnew_rr */
22917 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22918 /* S4_pstorerif_abs */
22919 PredRegs, u32_0Imm, IntRegs,
22920 /* S4_pstorerif_rr */
22921 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22922 /* S4_pstorerifnew_abs */
22923 PredRegs, u32_0Imm, IntRegs,
22924 /* S4_pstorerifnew_io */
22925 PredRegs, IntRegs, u30_2Imm, IntRegs,
22926 /* S4_pstorerifnew_rr */
22927 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22928 /* S4_pstorerinewf_abs */
22929 PredRegs, u32_0Imm, IntRegs,
22930 /* S4_pstorerinewf_rr */
22931 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22932 /* S4_pstorerinewfnew_abs */
22933 PredRegs, u32_0Imm, IntRegs,
22934 /* S4_pstorerinewfnew_io */
22935 PredRegs, IntRegs, u30_2Imm, IntRegs,
22936 /* S4_pstorerinewfnew_rr */
22937 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22938 /* S4_pstorerinewt_abs */
22939 PredRegs, u32_0Imm, IntRegs,
22940 /* S4_pstorerinewt_rr */
22941 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22942 /* S4_pstorerinewtnew_abs */
22943 PredRegs, u32_0Imm, IntRegs,
22944 /* S4_pstorerinewtnew_io */
22945 PredRegs, IntRegs, u30_2Imm, IntRegs,
22946 /* S4_pstorerinewtnew_rr */
22947 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22948 /* S4_pstorerit_abs */
22949 PredRegs, u32_0Imm, IntRegs,
22950 /* S4_pstorerit_rr */
22951 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22952 /* S4_pstoreritnew_abs */
22953 PredRegs, u32_0Imm, IntRegs,
22954 /* S4_pstoreritnew_io */
22955 PredRegs, IntRegs, u30_2Imm, IntRegs,
22956 /* S4_pstoreritnew_rr */
22957 PredRegs, IntRegs, IntRegs, u2_0Imm, IntRegs,
22958 /* S4_stored_locked */
22959 PredRegs, IntRegs, DoubleRegs,
22960 /* S4_stored_rl_at_vi */
22961 IntRegs, DoubleRegs,
22962 /* S4_stored_rl_st_vi */
22963 IntRegs, DoubleRegs,
22964 /* S4_storeirb_io */
22965 IntRegs, u6_0Imm, s32_0Imm,
22966 /* S4_storeirbf_io */
22967 PredRegs, IntRegs, u6_0Imm, s32_0Imm,
22968 /* S4_storeirbfnew_io */
22969 PredRegs, IntRegs, u6_0Imm, s32_0Imm,
22970 /* S4_storeirbt_io */
22971 PredRegs, IntRegs, u6_0Imm, s32_0Imm,
22972 /* S4_storeirbtnew_io */
22973 PredRegs, IntRegs, u6_0Imm, s32_0Imm,
22974 /* S4_storeirh_io */
22975 IntRegs, u6_1Imm, s32_0Imm,
22976 /* S4_storeirhf_io */
22977 PredRegs, IntRegs, u6_1Imm, s32_0Imm,
22978 /* S4_storeirhfnew_io */
22979 PredRegs, IntRegs, u6_1Imm, s32_0Imm,
22980 /* S4_storeirht_io */
22981 PredRegs, IntRegs, u6_1Imm, s32_0Imm,
22982 /* S4_storeirhtnew_io */
22983 PredRegs, IntRegs, u6_1Imm, s32_0Imm,
22984 /* S4_storeiri_io */
22985 IntRegs, u6_2Imm, s32_0Imm,
22986 /* S4_storeirif_io */
22987 PredRegs, IntRegs, u6_2Imm, s32_0Imm,
22988 /* S4_storeirifnew_io */
22989 PredRegs, IntRegs, u6_2Imm, s32_0Imm,
22990 /* S4_storeirit_io */
22991 PredRegs, IntRegs, u6_2Imm, s32_0Imm,
22992 /* S4_storeiritnew_io */
22993 PredRegs, IntRegs, u6_2Imm, s32_0Imm,
22994 /* S4_storerb_ap */
22995 IntRegs, u32_0Imm, IntRegs,
22996 /* S4_storerb_rr */
22997 IntRegs, IntRegs, u2_0Imm, IntRegs,
22998 /* S4_storerb_ur */
22999 IntRegs, u2_0Imm, u32_0Imm, IntRegs,
23000 /* S4_storerbnew_ap */
23001 IntRegs, u32_0Imm, IntRegs,
23002 /* S4_storerbnew_rr */
23003 IntRegs, IntRegs, u2_0Imm, IntRegs,
23004 /* S4_storerbnew_ur */
23005 IntRegs, u2_0Imm, u32_0Imm, IntRegs,
23006 /* S4_storerd_ap */
23007 IntRegs, u32_0Imm, DoubleRegs,
23008 /* S4_storerd_rr */
23009 IntRegs, IntRegs, u2_0Imm, DoubleRegs,
23010 /* S4_storerd_ur */
23011 IntRegs, u2_0Imm, u32_0Imm, DoubleRegs,
23012 /* S4_storerf_ap */
23013 IntRegs, u32_0Imm, IntRegs,
23014 /* S4_storerf_rr */
23015 IntRegs, IntRegs, u2_0Imm, IntRegs,
23016 /* S4_storerf_ur */
23017 IntRegs, u2_0Imm, u32_0Imm, IntRegs,
23018 /* S4_storerh_ap */
23019 IntRegs, u32_0Imm, IntRegs,
23020 /* S4_storerh_rr */
23021 IntRegs, IntRegs, u2_0Imm, IntRegs,
23022 /* S4_storerh_ur */
23023 IntRegs, u2_0Imm, u32_0Imm, IntRegs,
23024 /* S4_storerhnew_ap */
23025 IntRegs, u32_0Imm, IntRegs,
23026 /* S4_storerhnew_rr */
23027 IntRegs, IntRegs, u2_0Imm, IntRegs,
23028 /* S4_storerhnew_ur */
23029 IntRegs, u2_0Imm, u32_0Imm, IntRegs,
23030 /* S4_storeri_ap */
23031 IntRegs, u32_0Imm, IntRegs,
23032 /* S4_storeri_rr */
23033 IntRegs, IntRegs, u2_0Imm, IntRegs,
23034 /* S4_storeri_ur */
23035 IntRegs, u2_0Imm, u32_0Imm, IntRegs,
23036 /* S4_storerinew_ap */
23037 IntRegs, u32_0Imm, IntRegs,
23038 /* S4_storerinew_rr */
23039 IntRegs, IntRegs, u2_0Imm, IntRegs,
23040 /* S4_storerinew_ur */
23041 IntRegs, u2_0Imm, u32_0Imm, IntRegs,
23042 /* S4_subaddi */
23043 IntRegs, IntRegs, s32_0Imm, IntRegs,
23044 /* S4_subi_asl_ri */
23045 IntRegs, u32_0Imm, IntRegs, u5_0Imm,
23046 /* S4_subi_lsr_ri */
23047 IntRegs, u32_0Imm, IntRegs, u5_0Imm,
23048 /* S4_vrcrotate */
23049 DoubleRegs, DoubleRegs, IntRegs, u2_0Imm,
23050 /* S4_vrcrotate_acc */
23051 DoubleRegs, DoubleRegs, DoubleRegs, IntRegs, u2_0Imm,
23052 /* S4_vxaddsubh */
23053 DoubleRegs, DoubleRegs, DoubleRegs,
23054 /* S4_vxaddsubhr */
23055 DoubleRegs, DoubleRegs, DoubleRegs,
23056 /* S4_vxaddsubw */
23057 DoubleRegs, DoubleRegs, DoubleRegs,
23058 /* S4_vxsubaddh */
23059 DoubleRegs, DoubleRegs, DoubleRegs,
23060 /* S4_vxsubaddhr */
23061 DoubleRegs, DoubleRegs, DoubleRegs,
23062 /* S4_vxsubaddw */
23063 DoubleRegs, DoubleRegs, DoubleRegs,
23064 /* S5_asrhub_rnd_sat */
23065 IntRegs, DoubleRegs, u4_0Imm,
23066 /* S5_asrhub_sat */
23067 IntRegs, DoubleRegs, u4_0Imm,
23068 /* S5_popcountp */
23069 IntRegs, DoubleRegs,
23070 /* S5_vasrhrnd */
23071 DoubleRegs, DoubleRegs, u4_0Imm,
23072 /* S6_rol_i_p */
23073 DoubleRegs, DoubleRegs, u6_0Imm,
23074 /* S6_rol_i_p_acc */
23075 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
23076 /* S6_rol_i_p_and */
23077 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
23078 /* S6_rol_i_p_nac */
23079 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
23080 /* S6_rol_i_p_or */
23081 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
23082 /* S6_rol_i_p_xacc */
23083 DoubleRegs, DoubleRegs, DoubleRegs, u6_0Imm,
23084 /* S6_rol_i_r */
23085 IntRegs, IntRegs, u5_0Imm,
23086 /* S6_rol_i_r_acc */
23087 IntRegs, IntRegs, IntRegs, u5_0Imm,
23088 /* S6_rol_i_r_and */
23089 IntRegs, IntRegs, IntRegs, u5_0Imm,
23090 /* S6_rol_i_r_nac */
23091 IntRegs, IntRegs, IntRegs, u5_0Imm,
23092 /* S6_rol_i_r_or */
23093 IntRegs, IntRegs, IntRegs, u5_0Imm,
23094 /* S6_rol_i_r_xacc */
23095 IntRegs, IntRegs, IntRegs, u5_0Imm,
23096 /* S6_vsplatrbp */
23097 DoubleRegs, IntRegs,
23098 /* S6_vtrunehb_ppp */
23099 DoubleRegs, DoubleRegs, DoubleRegs,
23100 /* S6_vtrunohb_ppp */
23101 DoubleRegs, DoubleRegs, DoubleRegs,
23102 /* SA1_addi */
23103 GeneralSubRegs, GeneralSubRegs, s32_0Imm,
23104 /* SA1_addrx */
23105 GeneralSubRegs, GeneralSubRegs, GeneralSubRegs,
23106 /* SA1_addsp */
23107 GeneralSubRegs, u6_2Imm,
23108 /* SA1_and1 */
23109 GeneralSubRegs, GeneralSubRegs,
23110 /* SA1_clrf */
23111 GeneralSubRegs,
23112 /* SA1_clrfnew */
23113 GeneralSubRegs,
23114 /* SA1_clrt */
23115 GeneralSubRegs,
23116 /* SA1_clrtnew */
23117 GeneralSubRegs,
23118 /* SA1_cmpeqi */
23119 GeneralSubRegs, u2_0Imm,
23120 /* SA1_combine0i */
23121 GeneralDoubleLow8Regs, u2_0Imm,
23122 /* SA1_combine1i */
23123 GeneralDoubleLow8Regs, u2_0Imm,
23124 /* SA1_combine2i */
23125 GeneralDoubleLow8Regs, u2_0Imm,
23126 /* SA1_combine3i */
23127 GeneralDoubleLow8Regs, u2_0Imm,
23128 /* SA1_combinerz */
23129 GeneralDoubleLow8Regs, GeneralSubRegs,
23130 /* SA1_combinezr */
23131 GeneralDoubleLow8Regs, GeneralSubRegs,
23132 /* SA1_dec */
23133 GeneralSubRegs, GeneralSubRegs, n1Const,
23134 /* SA1_inc */
23135 GeneralSubRegs, GeneralSubRegs,
23136 /* SA1_seti */
23137 GeneralSubRegs, u32_0Imm,
23138 /* SA1_setin1 */
23139 GeneralSubRegs, n1Const,
23140 /* SA1_sxtb */
23141 GeneralSubRegs, GeneralSubRegs,
23142 /* SA1_sxth */
23143 GeneralSubRegs, GeneralSubRegs,
23144 /* SA1_tfr */
23145 GeneralSubRegs, GeneralSubRegs,
23146 /* SA1_zxtb */
23147 GeneralSubRegs, GeneralSubRegs,
23148 /* SA1_zxth */
23149 GeneralSubRegs, GeneralSubRegs,
23150 /* SAVE_REGISTERS_CALL_V4 */
23151 a30_2Imm,
23152 /* SAVE_REGISTERS_CALL_V4STK */
23153 a30_2Imm,
23154 /* SAVE_REGISTERS_CALL_V4STK_EXT */
23155 a30_2Imm,
23156 /* SAVE_REGISTERS_CALL_V4STK_EXT_PIC */
23157 a30_2Imm,
23158 /* SAVE_REGISTERS_CALL_V4STK_PIC */
23159 a30_2Imm,
23160 /* SAVE_REGISTERS_CALL_V4_EXT */
23161 a30_2Imm,
23162 /* SAVE_REGISTERS_CALL_V4_EXT_PIC */
23163 a30_2Imm,
23164 /* SAVE_REGISTERS_CALL_V4_PIC */
23165 a30_2Imm,
23166 /* SL1_loadri_io */
23167 GeneralSubRegs, GeneralSubRegs, u4_2Imm,
23168 /* SL1_loadrub_io */
23169 GeneralSubRegs, GeneralSubRegs, u4_0Imm,
23170 /* SL2_deallocframe */
23171 /* SL2_jumpr31 */
23172 /* SL2_jumpr31_f */
23173 /* SL2_jumpr31_fnew */
23174 /* SL2_jumpr31_t */
23175 /* SL2_jumpr31_tnew */
23176 /* SL2_loadrb_io */
23177 GeneralSubRegs, GeneralSubRegs, u3_0Imm,
23178 /* SL2_loadrd_sp */
23179 GeneralDoubleLow8Regs, u5_3Imm,
23180 /* SL2_loadrh_io */
23181 GeneralSubRegs, GeneralSubRegs, u3_1Imm,
23182 /* SL2_loadri_sp */
23183 GeneralSubRegs, u5_2Imm,
23184 /* SL2_loadruh_io */
23185 GeneralSubRegs, GeneralSubRegs, u3_1Imm,
23186 /* SL2_return */
23187 /* SL2_return_f */
23188 /* SL2_return_fnew */
23189 /* SL2_return_t */
23190 /* SL2_return_tnew */
23191 /* SS1_storeb_io */
23192 GeneralSubRegs, u4_0Imm, GeneralSubRegs,
23193 /* SS1_storew_io */
23194 GeneralSubRegs, u4_2Imm, GeneralSubRegs,
23195 /* SS2_allocframe */
23196 u5_3Imm,
23197 /* SS2_storebi0 */
23198 GeneralSubRegs, u4_0Imm,
23199 /* SS2_storebi1 */
23200 GeneralSubRegs, u4_0Imm,
23201 /* SS2_stored_sp */
23202 s6_3Imm, GeneralDoubleLow8Regs,
23203 /* SS2_storeh_io */
23204 GeneralSubRegs, u3_1Imm, GeneralSubRegs,
23205 /* SS2_storew_sp */
23206 u5_2Imm, GeneralSubRegs,
23207 /* SS2_storewi0 */
23208 GeneralSubRegs, u4_2Imm,
23209 /* SS2_storewi1 */
23210 GeneralSubRegs, u4_2Imm,
23211 /* TFRI64_V2_ext */
23212 DoubleRegs, s32_0Imm, s8_0Imm,
23213 /* TFRI64_V4 */
23214 DoubleRegs, u64_0Imm,
23215 /* V6_extractw */
23216 IntRegs, HvxVR, IntRegs,
23217 /* V6_lvsplatb */
23218 HvxVR, IntRegs,
23219 /* V6_lvsplath */
23220 HvxVR, IntRegs,
23221 /* V6_lvsplatw */
23222 HvxVR, IntRegs,
23223 /* V6_pred_and */
23224 HvxQR, HvxQR, HvxQR,
23225 /* V6_pred_and_n */
23226 HvxQR, HvxQR, HvxQR,
23227 /* V6_pred_not */
23228 HvxQR, HvxQR,
23229 /* V6_pred_or */
23230 HvxQR, HvxQR, HvxQR,
23231 /* V6_pred_or_n */
23232 HvxQR, HvxQR, HvxQR,
23233 /* V6_pred_scalar2 */
23234 HvxQR, IntRegs,
23235 /* V6_pred_scalar2v2 */
23236 HvxQR, IntRegs,
23237 /* V6_pred_xor */
23238 HvxQR, HvxQR, HvxQR,
23239 /* V6_shuffeqh */
23240 HvxQR, HvxQR, HvxQR,
23241 /* V6_shuffeqw */
23242 HvxQR, HvxQR, HvxQR,
23243 /* V6_v6mpyhubs10 */
23244 HvxWR, HvxWR, HvxWR, u2_0Imm,
23245 /* V6_v6mpyhubs10_vxx */
23246 HvxWR, HvxWR, HvxWR, HvxWR, u2_0Imm,
23247 /* V6_v6mpyvubs10 */
23248 HvxWR, HvxWR, HvxWR, u2_0Imm,
23249 /* V6_v6mpyvubs10_vxx */
23250 HvxWR, HvxWR, HvxWR, HvxWR, u2_0Imm,
23251 /* V6_vL32Ub_ai */
23252 HvxVR, IntRegs, s4_0Imm,
23253 /* V6_vL32Ub_pi */
23254 HvxVR, IntRegs, IntRegs, s3_0Imm,
23255 /* V6_vL32Ub_ppu */
23256 HvxVR, IntRegs, IntRegs, ModRegs,
23257 /* V6_vL32b_ai */
23258 HvxVR, IntRegs, s4_0Imm,
23259 /* V6_vL32b_cur_ai */
23260 HvxVR, IntRegs, s4_0Imm,
23261 /* V6_vL32b_cur_npred_ai */
23262 HvxVR, PredRegs, IntRegs, s4_0Imm,
23263 /* V6_vL32b_cur_npred_pi */
23264 HvxVR, IntRegs, PredRegs, IntRegs, s3_0Imm,
23265 /* V6_vL32b_cur_npred_ppu */
23266 HvxVR, IntRegs, PredRegs, IntRegs, ModRegs,
23267 /* V6_vL32b_cur_pi */
23268 HvxVR, IntRegs, IntRegs, s3_0Imm,
23269 /* V6_vL32b_cur_ppu */
23270 HvxVR, IntRegs, IntRegs, ModRegs,
23271 /* V6_vL32b_cur_pred_ai */
23272 HvxVR, PredRegs, IntRegs, s4_0Imm,
23273 /* V6_vL32b_cur_pred_pi */
23274 HvxVR, IntRegs, PredRegs, IntRegs, s3_0Imm,
23275 /* V6_vL32b_cur_pred_ppu */
23276 HvxVR, IntRegs, PredRegs, IntRegs, ModRegs,
23277 /* V6_vL32b_npred_ai */
23278 HvxVR, PredRegs, IntRegs, s4_0Imm,
23279 /* V6_vL32b_npred_pi */
23280 HvxVR, IntRegs, PredRegs, IntRegs, s3_0Imm,
23281 /* V6_vL32b_npred_ppu */
23282 HvxVR, IntRegs, PredRegs, IntRegs, ModRegs,
23283 /* V6_vL32b_nt_ai */
23284 HvxVR, IntRegs, s4_0Imm,
23285 /* V6_vL32b_nt_cur_ai */
23286 HvxVR, IntRegs, s4_0Imm,
23287 /* V6_vL32b_nt_cur_npred_ai */
23288 HvxVR, PredRegs, IntRegs, s4_0Imm,
23289 /* V6_vL32b_nt_cur_npred_pi */
23290 HvxVR, IntRegs, PredRegs, IntRegs, s3_0Imm,
23291 /* V6_vL32b_nt_cur_npred_ppu */
23292 HvxVR, IntRegs, PredRegs, IntRegs, ModRegs,
23293 /* V6_vL32b_nt_cur_pi */
23294 HvxVR, IntRegs, IntRegs, s3_0Imm,
23295 /* V6_vL32b_nt_cur_ppu */
23296 HvxVR, IntRegs, IntRegs, ModRegs,
23297 /* V6_vL32b_nt_cur_pred_ai */
23298 HvxVR, PredRegs, IntRegs, s4_0Imm,
23299 /* V6_vL32b_nt_cur_pred_pi */
23300 HvxVR, IntRegs, PredRegs, IntRegs, s3_0Imm,
23301 /* V6_vL32b_nt_cur_pred_ppu */
23302 HvxVR, IntRegs, PredRegs, IntRegs, ModRegs,
23303 /* V6_vL32b_nt_npred_ai */
23304 HvxVR, PredRegs, IntRegs, s4_0Imm,
23305 /* V6_vL32b_nt_npred_pi */
23306 HvxVR, IntRegs, PredRegs, IntRegs, s3_0Imm,
23307 /* V6_vL32b_nt_npred_ppu */
23308 HvxVR, IntRegs, PredRegs, IntRegs, ModRegs,
23309 /* V6_vL32b_nt_pi */
23310 HvxVR, IntRegs, IntRegs, s3_0Imm,
23311 /* V6_vL32b_nt_ppu */
23312 HvxVR, IntRegs, IntRegs, ModRegs,
23313 /* V6_vL32b_nt_pred_ai */
23314 HvxVR, PredRegs, IntRegs, s4_0Imm,
23315 /* V6_vL32b_nt_pred_pi */
23316 HvxVR, IntRegs, PredRegs, IntRegs, s3_0Imm,
23317 /* V6_vL32b_nt_pred_ppu */
23318 HvxVR, IntRegs, PredRegs, IntRegs, ModRegs,
23319 /* V6_vL32b_nt_tmp_ai */
23320 HvxVR, IntRegs, s4_0Imm,
23321 /* V6_vL32b_nt_tmp_npred_ai */
23322 HvxVR, PredRegs, IntRegs, s4_0Imm,
23323 /* V6_vL32b_nt_tmp_npred_pi */
23324 HvxVR, IntRegs, PredRegs, IntRegs, s3_0Imm,
23325 /* V6_vL32b_nt_tmp_npred_ppu */
23326 HvxVR, IntRegs, PredRegs, IntRegs, ModRegs,
23327 /* V6_vL32b_nt_tmp_pi */
23328 HvxVR, IntRegs, IntRegs, s3_0Imm,
23329 /* V6_vL32b_nt_tmp_ppu */
23330 HvxVR, IntRegs, IntRegs, ModRegs,
23331 /* V6_vL32b_nt_tmp_pred_ai */
23332 HvxVR, PredRegs, IntRegs, s4_0Imm,
23333 /* V6_vL32b_nt_tmp_pred_pi */
23334 HvxVR, IntRegs, PredRegs, IntRegs, s3_0Imm,
23335 /* V6_vL32b_nt_tmp_pred_ppu */
23336 HvxVR, IntRegs, PredRegs, IntRegs, ModRegs,
23337 /* V6_vL32b_pi */
23338 HvxVR, IntRegs, IntRegs, s3_0Imm,
23339 /* V6_vL32b_ppu */
23340 HvxVR, IntRegs, IntRegs, ModRegs,
23341 /* V6_vL32b_pred_ai */
23342 HvxVR, PredRegs, IntRegs, s4_0Imm,
23343 /* V6_vL32b_pred_pi */
23344 HvxVR, IntRegs, PredRegs, IntRegs, s3_0Imm,
23345 /* V6_vL32b_pred_ppu */
23346 HvxVR, IntRegs, PredRegs, IntRegs, ModRegs,
23347 /* V6_vL32b_tmp_ai */
23348 HvxVR, IntRegs, s4_0Imm,
23349 /* V6_vL32b_tmp_npred_ai */
23350 HvxVR, PredRegs, IntRegs, s4_0Imm,
23351 /* V6_vL32b_tmp_npred_pi */
23352 HvxVR, IntRegs, PredRegs, IntRegs, s3_0Imm,
23353 /* V6_vL32b_tmp_npred_ppu */
23354 HvxVR, IntRegs, PredRegs, IntRegs, ModRegs,
23355 /* V6_vL32b_tmp_pi */
23356 HvxVR, IntRegs, IntRegs, s3_0Imm,
23357 /* V6_vL32b_tmp_ppu */
23358 HvxVR, IntRegs, IntRegs, ModRegs,
23359 /* V6_vL32b_tmp_pred_ai */
23360 HvxVR, PredRegs, IntRegs, s4_0Imm,
23361 /* V6_vL32b_tmp_pred_pi */
23362 HvxVR, IntRegs, PredRegs, IntRegs, s3_0Imm,
23363 /* V6_vL32b_tmp_pred_ppu */
23364 HvxVR, IntRegs, PredRegs, IntRegs, ModRegs,
23365 /* V6_vS32Ub_ai */
23366 IntRegs, s4_0Imm, HvxVR,
23367 /* V6_vS32Ub_npred_ai */
23368 PredRegs, IntRegs, s4_0Imm, HvxVR,
23369 /* V6_vS32Ub_npred_pi */
23370 IntRegs, PredRegs, IntRegs, s3_0Imm, HvxVR,
23371 /* V6_vS32Ub_npred_ppu */
23372 IntRegs, PredRegs, IntRegs, ModRegs, HvxVR,
23373 /* V6_vS32Ub_pi */
23374 IntRegs, IntRegs, s3_0Imm, HvxVR,
23375 /* V6_vS32Ub_ppu */
23376 IntRegs, IntRegs, ModRegs, HvxVR,
23377 /* V6_vS32Ub_pred_ai */
23378 PredRegs, IntRegs, s4_0Imm, HvxVR,
23379 /* V6_vS32Ub_pred_pi */
23380 IntRegs, PredRegs, IntRegs, s3_0Imm, HvxVR,
23381 /* V6_vS32Ub_pred_ppu */
23382 IntRegs, PredRegs, IntRegs, ModRegs, HvxVR,
23383 /* V6_vS32b_ai */
23384 IntRegs, s4_0Imm, HvxVR,
23385 /* V6_vS32b_new_ai */
23386 IntRegs, s4_0Imm, HvxVR,
23387 /* V6_vS32b_new_npred_ai */
23388 PredRegs, IntRegs, s4_0Imm, HvxVR,
23389 /* V6_vS32b_new_npred_pi */
23390 IntRegs, PredRegs, IntRegs, s3_0Imm, HvxVR,
23391 /* V6_vS32b_new_npred_ppu */
23392 IntRegs, PredRegs, IntRegs, ModRegs, HvxVR,
23393 /* V6_vS32b_new_pi */
23394 IntRegs, IntRegs, s3_0Imm, HvxVR,
23395 /* V6_vS32b_new_ppu */
23396 IntRegs, IntRegs, ModRegs, HvxVR,
23397 /* V6_vS32b_new_pred_ai */
23398 PredRegs, IntRegs, s4_0Imm, HvxVR,
23399 /* V6_vS32b_new_pred_pi */
23400 IntRegs, PredRegs, IntRegs, s3_0Imm, HvxVR,
23401 /* V6_vS32b_new_pred_ppu */
23402 IntRegs, PredRegs, IntRegs, ModRegs, HvxVR,
23403 /* V6_vS32b_npred_ai */
23404 PredRegs, IntRegs, s4_0Imm, HvxVR,
23405 /* V6_vS32b_npred_pi */
23406 IntRegs, PredRegs, IntRegs, s3_0Imm, HvxVR,
23407 /* V6_vS32b_npred_ppu */
23408 IntRegs, PredRegs, IntRegs, ModRegs, HvxVR,
23409 /* V6_vS32b_nqpred_ai */
23410 HvxQR, IntRegs, s4_0Imm, HvxVR,
23411 /* V6_vS32b_nqpred_pi */
23412 IntRegs, HvxQR, IntRegs, s3_0Imm, HvxVR,
23413 /* V6_vS32b_nqpred_ppu */
23414 IntRegs, HvxQR, IntRegs, ModRegs, HvxVR,
23415 /* V6_vS32b_nt_ai */
23416 IntRegs, s4_0Imm, HvxVR,
23417 /* V6_vS32b_nt_new_ai */
23418 IntRegs, s4_0Imm, HvxVR,
23419 /* V6_vS32b_nt_new_npred_ai */
23420 PredRegs, IntRegs, s4_0Imm, HvxVR,
23421 /* V6_vS32b_nt_new_npred_pi */
23422 IntRegs, PredRegs, IntRegs, s3_0Imm, HvxVR,
23423 /* V6_vS32b_nt_new_npred_ppu */
23424 IntRegs, PredRegs, IntRegs, ModRegs, HvxVR,
23425 /* V6_vS32b_nt_new_pi */
23426 IntRegs, IntRegs, s3_0Imm, HvxVR,
23427 /* V6_vS32b_nt_new_ppu */
23428 IntRegs, IntRegs, ModRegs, HvxVR,
23429 /* V6_vS32b_nt_new_pred_ai */
23430 PredRegs, IntRegs, s4_0Imm, HvxVR,
23431 /* V6_vS32b_nt_new_pred_pi */
23432 IntRegs, PredRegs, IntRegs, s3_0Imm, HvxVR,
23433 /* V6_vS32b_nt_new_pred_ppu */
23434 IntRegs, PredRegs, IntRegs, ModRegs, HvxVR,
23435 /* V6_vS32b_nt_npred_ai */
23436 PredRegs, IntRegs, s4_0Imm, HvxVR,
23437 /* V6_vS32b_nt_npred_pi */
23438 IntRegs, PredRegs, IntRegs, s3_0Imm, HvxVR,
23439 /* V6_vS32b_nt_npred_ppu */
23440 IntRegs, PredRegs, IntRegs, ModRegs, HvxVR,
23441 /* V6_vS32b_nt_nqpred_ai */
23442 HvxQR, IntRegs, s4_0Imm, HvxVR,
23443 /* V6_vS32b_nt_nqpred_pi */
23444 IntRegs, HvxQR, IntRegs, s3_0Imm, HvxVR,
23445 /* V6_vS32b_nt_nqpred_ppu */
23446 IntRegs, HvxQR, IntRegs, ModRegs, HvxVR,
23447 /* V6_vS32b_nt_pi */
23448 IntRegs, IntRegs, s3_0Imm, HvxVR,
23449 /* V6_vS32b_nt_ppu */
23450 IntRegs, IntRegs, ModRegs, HvxVR,
23451 /* V6_vS32b_nt_pred_ai */
23452 PredRegs, IntRegs, s4_0Imm, HvxVR,
23453 /* V6_vS32b_nt_pred_pi */
23454 IntRegs, PredRegs, IntRegs, s3_0Imm, HvxVR,
23455 /* V6_vS32b_nt_pred_ppu */
23456 IntRegs, PredRegs, IntRegs, ModRegs, HvxVR,
23457 /* V6_vS32b_nt_qpred_ai */
23458 HvxQR, IntRegs, s4_0Imm, HvxVR,
23459 /* V6_vS32b_nt_qpred_pi */
23460 IntRegs, HvxQR, IntRegs, s3_0Imm, HvxVR,
23461 /* V6_vS32b_nt_qpred_ppu */
23462 IntRegs, HvxQR, IntRegs, ModRegs, HvxVR,
23463 /* V6_vS32b_pi */
23464 IntRegs, IntRegs, s3_0Imm, HvxVR,
23465 /* V6_vS32b_ppu */
23466 IntRegs, IntRegs, ModRegs, HvxVR,
23467 /* V6_vS32b_pred_ai */
23468 PredRegs, IntRegs, s4_0Imm, HvxVR,
23469 /* V6_vS32b_pred_pi */
23470 IntRegs, PredRegs, IntRegs, s3_0Imm, HvxVR,
23471 /* V6_vS32b_pred_ppu */
23472 IntRegs, PredRegs, IntRegs, ModRegs, HvxVR,
23473 /* V6_vS32b_qpred_ai */
23474 HvxQR, IntRegs, s4_0Imm, HvxVR,
23475 /* V6_vS32b_qpred_pi */
23476 IntRegs, HvxQR, IntRegs, s3_0Imm, HvxVR,
23477 /* V6_vS32b_qpred_ppu */
23478 IntRegs, HvxQR, IntRegs, ModRegs, HvxVR,
23479 /* V6_vS32b_srls_ai */
23480 IntRegs, s4_0Imm,
23481 /* V6_vS32b_srls_pi */
23482 IntRegs, IntRegs, s3_0Imm,
23483 /* V6_vS32b_srls_ppu */
23484 IntRegs, IntRegs, ModRegs,
23485 /* V6_vabs_hf */
23486 HvxVR, HvxVR,
23487 /* V6_vabs_sf */
23488 HvxVR, HvxVR,
23489 /* V6_vabsb */
23490 HvxVR, HvxVR,
23491 /* V6_vabsb_sat */
23492 HvxVR, HvxVR,
23493 /* V6_vabsdiffh */
23494 HvxVR, HvxVR, HvxVR,
23495 /* V6_vabsdiffub */
23496 HvxVR, HvxVR, HvxVR,
23497 /* V6_vabsdiffuh */
23498 HvxVR, HvxVR, HvxVR,
23499 /* V6_vabsdiffw */
23500 HvxVR, HvxVR, HvxVR,
23501 /* V6_vabsh */
23502 HvxVR, HvxVR,
23503 /* V6_vabsh_sat */
23504 HvxVR, HvxVR,
23505 /* V6_vabsw */
23506 HvxVR, HvxVR,
23507 /* V6_vabsw_sat */
23508 HvxVR, HvxVR,
23509 /* V6_vadd_hf */
23510 HvxVR, HvxVR, HvxVR,
23511 /* V6_vadd_hf_hf */
23512 HvxVR, HvxVR, HvxVR,
23513 /* V6_vadd_qf16 */
23514 HvxVR, HvxVR, HvxVR,
23515 /* V6_vadd_qf16_mix */
23516 HvxVR, HvxVR, HvxVR,
23517 /* V6_vadd_qf32 */
23518 HvxVR, HvxVR, HvxVR,
23519 /* V6_vadd_qf32_mix */
23520 HvxVR, HvxVR, HvxVR,
23521 /* V6_vadd_sf */
23522 HvxVR, HvxVR, HvxVR,
23523 /* V6_vadd_sf_bf */
23524 HvxWR, HvxVR, HvxVR,
23525 /* V6_vadd_sf_hf */
23526 HvxWR, HvxVR, HvxVR,
23527 /* V6_vadd_sf_sf */
23528 HvxVR, HvxVR, HvxVR,
23529 /* V6_vaddb */
23530 HvxVR, HvxVR, HvxVR,
23531 /* V6_vaddb_dv */
23532 HvxWR, HvxWR, HvxWR,
23533 /* V6_vaddbnq */
23534 HvxVR, HvxQR, HvxVR, HvxVR,
23535 /* V6_vaddbq */
23536 HvxVR, HvxQR, HvxVR, HvxVR,
23537 /* V6_vaddbsat */
23538 HvxVR, HvxVR, HvxVR,
23539 /* V6_vaddbsat_dv */
23540 HvxWR, HvxWR, HvxWR,
23541 /* V6_vaddcarry */
23542 HvxVR, HvxQR, HvxVR, HvxVR, HvxQR,
23543 /* V6_vaddcarryo */
23544 HvxVR, HvxQR, HvxVR, HvxVR,
23545 /* V6_vaddcarrysat */
23546 HvxVR, HvxVR, HvxVR, HvxQR,
23547 /* V6_vaddclbh */
23548 HvxVR, HvxVR, HvxVR,
23549 /* V6_vaddclbw */
23550 HvxVR, HvxVR, HvxVR,
23551 /* V6_vaddh */
23552 HvxVR, HvxVR, HvxVR,
23553 /* V6_vaddh_dv */
23554 HvxWR, HvxWR, HvxWR,
23555 /* V6_vaddhnq */
23556 HvxVR, HvxQR, HvxVR, HvxVR,
23557 /* V6_vaddhq */
23558 HvxVR, HvxQR, HvxVR, HvxVR,
23559 /* V6_vaddhsat */
23560 HvxVR, HvxVR, HvxVR,
23561 /* V6_vaddhsat_dv */
23562 HvxWR, HvxWR, HvxWR,
23563 /* V6_vaddhw */
23564 HvxWR, HvxVR, HvxVR,
23565 /* V6_vaddhw_acc */
23566 HvxWR, HvxWR, HvxVR, HvxVR,
23567 /* V6_vaddubh */
23568 HvxWR, HvxVR, HvxVR,
23569 /* V6_vaddubh_acc */
23570 HvxWR, HvxWR, HvxVR, HvxVR,
23571 /* V6_vaddubsat */
23572 HvxVR, HvxVR, HvxVR,
23573 /* V6_vaddubsat_dv */
23574 HvxWR, HvxWR, HvxWR,
23575 /* V6_vaddububb_sat */
23576 HvxVR, HvxVR, HvxVR,
23577 /* V6_vadduhsat */
23578 HvxVR, HvxVR, HvxVR,
23579 /* V6_vadduhsat_dv */
23580 HvxWR, HvxWR, HvxWR,
23581 /* V6_vadduhw */
23582 HvxWR, HvxVR, HvxVR,
23583 /* V6_vadduhw_acc */
23584 HvxWR, HvxWR, HvxVR, HvxVR,
23585 /* V6_vadduwsat */
23586 HvxVR, HvxVR, HvxVR,
23587 /* V6_vadduwsat_dv */
23588 HvxWR, HvxWR, HvxWR,
23589 /* V6_vaddw */
23590 HvxVR, HvxVR, HvxVR,
23591 /* V6_vaddw_dv */
23592 HvxWR, HvxWR, HvxWR,
23593 /* V6_vaddwnq */
23594 HvxVR, HvxQR, HvxVR, HvxVR,
23595 /* V6_vaddwq */
23596 HvxVR, HvxQR, HvxVR, HvxVR,
23597 /* V6_vaddwsat */
23598 HvxVR, HvxVR, HvxVR,
23599 /* V6_vaddwsat_dv */
23600 HvxWR, HvxWR, HvxWR,
23601 /* V6_valignb */
23602 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23603 /* V6_valignbi */
23604 HvxVR, HvxVR, HvxVR, u3_0Imm,
23605 /* V6_vand */
23606 HvxVR, HvxVR, HvxVR,
23607 /* V6_vandnqrt */
23608 HvxVR, HvxQR, IntRegs,
23609 /* V6_vandnqrt_acc */
23610 HvxVR, HvxVR, HvxQR, IntRegs,
23611 /* V6_vandqrt */
23612 HvxVR, HvxQR, IntRegs,
23613 /* V6_vandqrt_acc */
23614 HvxVR, HvxVR, HvxQR, IntRegs,
23615 /* V6_vandvnqv */
23616 HvxVR, HvxQR, HvxVR,
23617 /* V6_vandvqv */
23618 HvxVR, HvxQR, HvxVR,
23619 /* V6_vandvrt */
23620 HvxQR, HvxVR, IntRegs,
23621 /* V6_vandvrt_acc */
23622 HvxQR, HvxQR, HvxVR, IntRegs,
23623 /* V6_vaslh */
23624 HvxVR, HvxVR, IntRegs,
23625 /* V6_vaslh_acc */
23626 HvxVR, HvxVR, HvxVR, IntRegs,
23627 /* V6_vaslhv */
23628 HvxVR, HvxVR, HvxVR,
23629 /* V6_vaslw */
23630 HvxVR, HvxVR, IntRegs,
23631 /* V6_vaslw_acc */
23632 HvxVR, HvxVR, HvxVR, IntRegs,
23633 /* V6_vaslwv */
23634 HvxVR, HvxVR, HvxVR,
23635 /* V6_vasr_into */
23636 HvxWR, HvxWR, HvxVR, HvxVR,
23637 /* V6_vasrh */
23638 HvxVR, HvxVR, IntRegs,
23639 /* V6_vasrh_acc */
23640 HvxVR, HvxVR, HvxVR, IntRegs,
23641 /* V6_vasrhbrndsat */
23642 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23643 /* V6_vasrhbsat */
23644 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23645 /* V6_vasrhubrndsat */
23646 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23647 /* V6_vasrhubsat */
23648 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23649 /* V6_vasrhv */
23650 HvxVR, HvxVR, HvxVR,
23651 /* V6_vasruhubrndsat */
23652 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23653 /* V6_vasruhubsat */
23654 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23655 /* V6_vasruwuhrndsat */
23656 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23657 /* V6_vasruwuhsat */
23658 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23659 /* V6_vasrvuhubrndsat */
23660 HvxVR, HvxWR, HvxVR,
23661 /* V6_vasrvuhubsat */
23662 HvxVR, HvxWR, HvxVR,
23663 /* V6_vasrvwuhrndsat */
23664 HvxVR, HvxWR, HvxVR,
23665 /* V6_vasrvwuhsat */
23666 HvxVR, HvxWR, HvxVR,
23667 /* V6_vasrw */
23668 HvxVR, HvxVR, IntRegs,
23669 /* V6_vasrw_acc */
23670 HvxVR, HvxVR, HvxVR, IntRegs,
23671 /* V6_vasrwh */
23672 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23673 /* V6_vasrwhrndsat */
23674 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23675 /* V6_vasrwhsat */
23676 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23677 /* V6_vasrwuhrndsat */
23678 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23679 /* V6_vasrwuhsat */
23680 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23681 /* V6_vasrwv */
23682 HvxVR, HvxVR, HvxVR,
23683 /* V6_vassign */
23684 HvxVR, HvxVR,
23685 /* V6_vassign_fp */
23686 HvxVR, HvxVR,
23687 /* V6_vassign_tmp */
23688 HvxVR, HvxVR,
23689 /* V6_vavgb */
23690 HvxVR, HvxVR, HvxVR,
23691 /* V6_vavgbrnd */
23692 HvxVR, HvxVR, HvxVR,
23693 /* V6_vavgh */
23694 HvxVR, HvxVR, HvxVR,
23695 /* V6_vavghrnd */
23696 HvxVR, HvxVR, HvxVR,
23697 /* V6_vavgub */
23698 HvxVR, HvxVR, HvxVR,
23699 /* V6_vavgubrnd */
23700 HvxVR, HvxVR, HvxVR,
23701 /* V6_vavguh */
23702 HvxVR, HvxVR, HvxVR,
23703 /* V6_vavguhrnd */
23704 HvxVR, HvxVR, HvxVR,
23705 /* V6_vavguw */
23706 HvxVR, HvxVR, HvxVR,
23707 /* V6_vavguwrnd */
23708 HvxVR, HvxVR, HvxVR,
23709 /* V6_vavgw */
23710 HvxVR, HvxVR, HvxVR,
23711 /* V6_vavgwrnd */
23712 HvxVR, HvxVR, HvxVR,
23713 /* V6_vccombine */
23714 HvxWR, PredRegs, HvxVR, HvxVR,
23715 /* V6_vcl0h */
23716 HvxVR, HvxVR,
23717 /* V6_vcl0w */
23718 HvxVR, HvxVR,
23719 /* V6_vcmov */
23720 HvxVR, PredRegs, HvxVR,
23721 /* V6_vcombine */
23722 HvxWR, HvxVR, HvxVR,
23723 /* V6_vcombine_tmp */
23724 HvxWR, HvxVR, HvxVR,
23725 /* V6_vconv_h_hf */
23726 HvxVR, HvxVR,
23727 /* V6_vconv_hf_h */
23728 HvxVR, HvxVR,
23729 /* V6_vconv_hf_qf16 */
23730 HvxVR, HvxVR,
23731 /* V6_vconv_hf_qf32 */
23732 HvxVR, HvxWR,
23733 /* V6_vconv_sf_qf32 */
23734 HvxVR, HvxVR,
23735 /* V6_vconv_sf_w */
23736 HvxVR, HvxVR,
23737 /* V6_vconv_w_sf */
23738 HvxVR, HvxVR,
23739 /* V6_vcvt_b_hf */
23740 HvxVR, HvxVR, HvxVR,
23741 /* V6_vcvt_bf_sf */
23742 HvxVR, HvxVR, HvxVR,
23743 /* V6_vcvt_h_hf */
23744 HvxVR, HvxVR,
23745 /* V6_vcvt_hf_b */
23746 HvxWR, HvxVR,
23747 /* V6_vcvt_hf_h */
23748 HvxVR, HvxVR,
23749 /* V6_vcvt_hf_sf */
23750 HvxVR, HvxVR, HvxVR,
23751 /* V6_vcvt_hf_ub */
23752 HvxWR, HvxVR,
23753 /* V6_vcvt_hf_uh */
23754 HvxVR, HvxVR,
23755 /* V6_vcvt_sf_hf */
23756 HvxWR, HvxVR,
23757 /* V6_vcvt_ub_hf */
23758 HvxVR, HvxVR, HvxVR,
23759 /* V6_vcvt_uh_hf */
23760 HvxVR, HvxVR,
23761 /* V6_vdeal */
23762 HvxVR, HvxVR, HvxVR, HvxVR, IntRegs,
23763 /* V6_vdealb */
23764 HvxVR, HvxVR,
23765 /* V6_vdealb4w */
23766 HvxVR, HvxVR, HvxVR,
23767 /* V6_vdealh */
23768 HvxVR, HvxVR,
23769 /* V6_vdealvdd */
23770 HvxWR, HvxVR, HvxVR, IntRegsLow8,
23771 /* V6_vdelta */
23772 HvxVR, HvxVR, HvxVR,
23773 /* V6_vdmpy_sf_hf */
23774 HvxVR, HvxVR, HvxVR,
23775 /* V6_vdmpy_sf_hf_acc */
23776 HvxVR, HvxVR, HvxVR, HvxVR,
23777 /* V6_vdmpybus */
23778 HvxVR, HvxVR, IntRegs,
23779 /* V6_vdmpybus_acc */
23780 HvxVR, HvxVR, HvxVR, IntRegs,
23781 /* V6_vdmpybus_dv */
23782 HvxWR, HvxWR, IntRegs,
23783 /* V6_vdmpybus_dv_acc */
23784 HvxWR, HvxWR, HvxWR, IntRegs,
23785 /* V6_vdmpyhb */
23786 HvxVR, HvxVR, IntRegs,
23787 /* V6_vdmpyhb_acc */
23788 HvxVR, HvxVR, HvxVR, IntRegs,
23789 /* V6_vdmpyhb_dv */
23790 HvxWR, HvxWR, IntRegs,
23791 /* V6_vdmpyhb_dv_acc */
23792 HvxWR, HvxWR, HvxWR, IntRegs,
23793 /* V6_vdmpyhisat */
23794 HvxVR, HvxWR, IntRegs,
23795 /* V6_vdmpyhisat_acc */
23796 HvxVR, HvxVR, HvxWR, IntRegs,
23797 /* V6_vdmpyhsat */
23798 HvxVR, HvxVR, IntRegs,
23799 /* V6_vdmpyhsat_acc */
23800 HvxVR, HvxVR, HvxVR, IntRegs,
23801 /* V6_vdmpyhsuisat */
23802 HvxVR, HvxWR, IntRegs,
23803 /* V6_vdmpyhsuisat_acc */
23804 HvxVR, HvxVR, HvxWR, IntRegs,
23805 /* V6_vdmpyhsusat */
23806 HvxVR, HvxVR, IntRegs,
23807 /* V6_vdmpyhsusat_acc */
23808 HvxVR, HvxVR, HvxVR, IntRegs,
23809 /* V6_vdmpyhvsat */
23810 HvxVR, HvxVR, HvxVR,
23811 /* V6_vdmpyhvsat_acc */
23812 HvxVR, HvxVR, HvxVR, HvxVR,
23813 /* V6_vdsaduh */
23814 HvxWR, HvxWR, IntRegs,
23815 /* V6_vdsaduh_acc */
23816 HvxWR, HvxWR, HvxWR, IntRegs,
23817 /* V6_veqb */
23818 HvxQR, HvxVR, HvxVR,
23819 /* V6_veqb_and */
23820 HvxQR, HvxQR, HvxVR, HvxVR,
23821 /* V6_veqb_or */
23822 HvxQR, HvxQR, HvxVR, HvxVR,
23823 /* V6_veqb_xor */
23824 HvxQR, HvxQR, HvxVR, HvxVR,
23825 /* V6_veqh */
23826 HvxQR, HvxVR, HvxVR,
23827 /* V6_veqh_and */
23828 HvxQR, HvxQR, HvxVR, HvxVR,
23829 /* V6_veqh_or */
23830 HvxQR, HvxQR, HvxVR, HvxVR,
23831 /* V6_veqh_xor */
23832 HvxQR, HvxQR, HvxVR, HvxVR,
23833 /* V6_veqw */
23834 HvxQR, HvxVR, HvxVR,
23835 /* V6_veqw_and */
23836 HvxQR, HvxQR, HvxVR, HvxVR,
23837 /* V6_veqw_or */
23838 HvxQR, HvxQR, HvxVR, HvxVR,
23839 /* V6_veqw_xor */
23840 HvxQR, HvxQR, HvxVR, HvxVR,
23841 /* V6_vfmax_hf */
23842 HvxVR, HvxVR, HvxVR,
23843 /* V6_vfmax_sf */
23844 HvxVR, HvxVR, HvxVR,
23845 /* V6_vfmin_hf */
23846 HvxVR, HvxVR, HvxVR,
23847 /* V6_vfmin_sf */
23848 HvxVR, HvxVR, HvxVR,
23849 /* V6_vfneg_hf */
23850 HvxVR, HvxVR,
23851 /* V6_vfneg_sf */
23852 HvxVR, HvxVR,
23853 /* V6_vgathermh */
23854 IntRegs, ModRegs, HvxVR,
23855 /* V6_vgathermhq */
23856 HvxQR, IntRegs, ModRegs, HvxVR,
23857 /* V6_vgathermhw */
23858 IntRegs, ModRegs, HvxWR,
23859 /* V6_vgathermhwq */
23860 HvxQR, IntRegs, ModRegs, HvxWR,
23861 /* V6_vgathermw */
23862 IntRegs, ModRegs, HvxVR,
23863 /* V6_vgathermwq */
23864 HvxQR, IntRegs, ModRegs, HvxVR,
23865 /* V6_vgtb */
23866 HvxQR, HvxVR, HvxVR,
23867 /* V6_vgtb_and */
23868 HvxQR, HvxQR, HvxVR, HvxVR,
23869 /* V6_vgtb_or */
23870 HvxQR, HvxQR, HvxVR, HvxVR,
23871 /* V6_vgtb_xor */
23872 HvxQR, HvxQR, HvxVR, HvxVR,
23873 /* V6_vgtbf */
23874 HvxQR, HvxVR, HvxVR,
23875 /* V6_vgtbf_and */
23876 HvxQR, HvxQR, HvxVR, HvxVR,
23877 /* V6_vgtbf_or */
23878 HvxQR, HvxQR, HvxVR, HvxVR,
23879 /* V6_vgtbf_xor */
23880 HvxQR, HvxQR, HvxVR, HvxVR,
23881 /* V6_vgth */
23882 HvxQR, HvxVR, HvxVR,
23883 /* V6_vgth_and */
23884 HvxQR, HvxQR, HvxVR, HvxVR,
23885 /* V6_vgth_or */
23886 HvxQR, HvxQR, HvxVR, HvxVR,
23887 /* V6_vgth_xor */
23888 HvxQR, HvxQR, HvxVR, HvxVR,
23889 /* V6_vgthf */
23890 HvxQR, HvxVR, HvxVR,
23891 /* V6_vgthf_and */
23892 HvxQR, HvxQR, HvxVR, HvxVR,
23893 /* V6_vgthf_or */
23894 HvxQR, HvxQR, HvxVR, HvxVR,
23895 /* V6_vgthf_xor */
23896 HvxQR, HvxQR, HvxVR, HvxVR,
23897 /* V6_vgtsf */
23898 HvxQR, HvxVR, HvxVR,
23899 /* V6_vgtsf_and */
23900 HvxQR, HvxQR, HvxVR, HvxVR,
23901 /* V6_vgtsf_or */
23902 HvxQR, HvxQR, HvxVR, HvxVR,
23903 /* V6_vgtsf_xor */
23904 HvxQR, HvxQR, HvxVR, HvxVR,
23905 /* V6_vgtub */
23906 HvxQR, HvxVR, HvxVR,
23907 /* V6_vgtub_and */
23908 HvxQR, HvxQR, HvxVR, HvxVR,
23909 /* V6_vgtub_or */
23910 HvxQR, HvxQR, HvxVR, HvxVR,
23911 /* V6_vgtub_xor */
23912 HvxQR, HvxQR, HvxVR, HvxVR,
23913 /* V6_vgtuh */
23914 HvxQR, HvxVR, HvxVR,
23915 /* V6_vgtuh_and */
23916 HvxQR, HvxQR, HvxVR, HvxVR,
23917 /* V6_vgtuh_or */
23918 HvxQR, HvxQR, HvxVR, HvxVR,
23919 /* V6_vgtuh_xor */
23920 HvxQR, HvxQR, HvxVR, HvxVR,
23921 /* V6_vgtuw */
23922 HvxQR, HvxVR, HvxVR,
23923 /* V6_vgtuw_and */
23924 HvxQR, HvxQR, HvxVR, HvxVR,
23925 /* V6_vgtuw_or */
23926 HvxQR, HvxQR, HvxVR, HvxVR,
23927 /* V6_vgtuw_xor */
23928 HvxQR, HvxQR, HvxVR, HvxVR,
23929 /* V6_vgtw */
23930 HvxQR, HvxVR, HvxVR,
23931 /* V6_vgtw_and */
23932 HvxQR, HvxQR, HvxVR, HvxVR,
23933 /* V6_vgtw_or */
23934 HvxQR, HvxQR, HvxVR, HvxVR,
23935 /* V6_vgtw_xor */
23936 HvxQR, HvxQR, HvxVR, HvxVR,
23937 /* V6_vhist */
23938 /* V6_vhistq */
23939 HvxQR,
23940 /* V6_vinsertwr */
23941 HvxVR, HvxVR, IntRegs,
23942 /* V6_vlalignb */
23943 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23944 /* V6_vlalignbi */
23945 HvxVR, HvxVR, HvxVR, u3_0Imm,
23946 /* V6_vlsrb */
23947 HvxVR, HvxVR, IntRegs,
23948 /* V6_vlsrh */
23949 HvxVR, HvxVR, IntRegs,
23950 /* V6_vlsrhv */
23951 HvxVR, HvxVR, HvxVR,
23952 /* V6_vlsrw */
23953 HvxVR, HvxVR, IntRegs,
23954 /* V6_vlsrwv */
23955 HvxVR, HvxVR, HvxVR,
23956 /* V6_vlut4 */
23957 HvxVR, HvxVR, DoubleRegs,
23958 /* V6_vlutvvb */
23959 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23960 /* V6_vlutvvb_nm */
23961 HvxVR, HvxVR, HvxVR, IntRegsLow8,
23962 /* V6_vlutvvb_oracc */
23963 HvxVR, HvxVR, HvxVR, HvxVR, IntRegsLow8,
23964 /* V6_vlutvvb_oracci */
23965 HvxVR, HvxVR, HvxVR, HvxVR, u3_0Imm,
23966 /* V6_vlutvvbi */
23967 HvxVR, HvxVR, HvxVR, u3_0Imm,
23968 /* V6_vlutvwh */
23969 HvxWR, HvxVR, HvxVR, IntRegsLow8,
23970 /* V6_vlutvwh_nm */
23971 HvxWR, HvxVR, HvxVR, IntRegsLow8,
23972 /* V6_vlutvwh_oracc */
23973 HvxWR, HvxWR, HvxVR, HvxVR, IntRegsLow8,
23974 /* V6_vlutvwh_oracci */
23975 HvxWR, HvxWR, HvxVR, HvxVR, u3_0Imm,
23976 /* V6_vlutvwhi */
23977 HvxWR, HvxVR, HvxVR, u3_0Imm,
23978 /* V6_vmax_bf */
23979 HvxVR, HvxVR, HvxVR,
23980 /* V6_vmax_hf */
23981 HvxVR, HvxVR, HvxVR,
23982 /* V6_vmax_sf */
23983 HvxVR, HvxVR, HvxVR,
23984 /* V6_vmaxb */
23985 HvxVR, HvxVR, HvxVR,
23986 /* V6_vmaxh */
23987 HvxVR, HvxVR, HvxVR,
23988 /* V6_vmaxub */
23989 HvxVR, HvxVR, HvxVR,
23990 /* V6_vmaxuh */
23991 HvxVR, HvxVR, HvxVR,
23992 /* V6_vmaxw */
23993 HvxVR, HvxVR, HvxVR,
23994 /* V6_vmin_bf */
23995 HvxVR, HvxVR, HvxVR,
23996 /* V6_vmin_hf */
23997 HvxVR, HvxVR, HvxVR,
23998 /* V6_vmin_sf */
23999 HvxVR, HvxVR, HvxVR,
24000 /* V6_vminb */
24001 HvxVR, HvxVR, HvxVR,
24002 /* V6_vminh */
24003 HvxVR, HvxVR, HvxVR,
24004 /* V6_vminub */
24005 HvxVR, HvxVR, HvxVR,
24006 /* V6_vminuh */
24007 HvxVR, HvxVR, HvxVR,
24008 /* V6_vminw */
24009 HvxVR, HvxVR, HvxVR,
24010 /* V6_vmpabus */
24011 HvxWR, HvxWR, IntRegs,
24012 /* V6_vmpabus_acc */
24013 HvxWR, HvxWR, HvxWR, IntRegs,
24014 /* V6_vmpabusv */
24015 HvxWR, HvxWR, HvxWR,
24016 /* V6_vmpabuu */
24017 HvxWR, HvxWR, IntRegs,
24018 /* V6_vmpabuu_acc */
24019 HvxWR, HvxWR, HvxWR, IntRegs,
24020 /* V6_vmpabuuv */
24021 HvxWR, HvxWR, HvxWR,
24022 /* V6_vmpahb */
24023 HvxWR, HvxWR, IntRegs,
24024 /* V6_vmpahb_acc */
24025 HvxWR, HvxWR, HvxWR, IntRegs,
24026 /* V6_vmpahhsat */
24027 HvxVR, HvxVR, HvxVR, DoubleRegs,
24028 /* V6_vmpauhb */
24029 HvxWR, HvxWR, IntRegs,
24030 /* V6_vmpauhb_acc */
24031 HvxWR, HvxWR, HvxWR, IntRegs,
24032 /* V6_vmpauhuhsat */
24033 HvxVR, HvxVR, HvxVR, DoubleRegs,
24034 /* V6_vmpsuhuhsat */
24035 HvxVR, HvxVR, HvxVR, DoubleRegs,
24036 /* V6_vmpy_hf_hf */
24037 HvxVR, HvxVR, HvxVR,
24038 /* V6_vmpy_hf_hf_acc */
24039 HvxVR, HvxVR, HvxVR, HvxVR,
24040 /* V6_vmpy_qf16 */
24041 HvxVR, HvxVR, HvxVR,
24042 /* V6_vmpy_qf16_hf */
24043 HvxVR, HvxVR, HvxVR,
24044 /* V6_vmpy_qf16_mix_hf */
24045 HvxVR, HvxVR, HvxVR,
24046 /* V6_vmpy_qf32 */
24047 HvxVR, HvxVR, HvxVR,
24048 /* V6_vmpy_qf32_hf */
24049 HvxWR, HvxVR, HvxVR,
24050 /* V6_vmpy_qf32_mix_hf */
24051 HvxWR, HvxVR, HvxVR,
24052 /* V6_vmpy_qf32_qf16 */
24053 HvxWR, HvxVR, HvxVR,
24054 /* V6_vmpy_qf32_sf */
24055 HvxVR, HvxVR, HvxVR,
24056 /* V6_vmpy_sf_bf */
24057 HvxWR, HvxVR, HvxVR,
24058 /* V6_vmpy_sf_bf_acc */
24059 HvxWR, HvxWR, HvxVR, HvxVR,
24060 /* V6_vmpy_sf_hf */
24061 HvxWR, HvxVR, HvxVR,
24062 /* V6_vmpy_sf_hf_acc */
24063 HvxWR, HvxWR, HvxVR, HvxVR,
24064 /* V6_vmpy_sf_sf */
24065 HvxVR, HvxVR, HvxVR,
24066 /* V6_vmpybus */
24067 HvxWR, HvxVR, IntRegs,
24068 /* V6_vmpybus_acc */
24069 HvxWR, HvxWR, HvxVR, IntRegs,
24070 /* V6_vmpybusv */
24071 HvxWR, HvxVR, HvxVR,
24072 /* V6_vmpybusv_acc */
24073 HvxWR, HvxWR, HvxVR, HvxVR,
24074 /* V6_vmpybv */
24075 HvxWR, HvxVR, HvxVR,
24076 /* V6_vmpybv_acc */
24077 HvxWR, HvxWR, HvxVR, HvxVR,
24078 /* V6_vmpyewuh */
24079 HvxVR, HvxVR, HvxVR,
24080 /* V6_vmpyewuh_64 */
24081 HvxWR, HvxVR, HvxVR,
24082 /* V6_vmpyh */
24083 HvxWR, HvxVR, IntRegs,
24084 /* V6_vmpyh_acc */
24085 HvxWR, HvxWR, HvxVR, IntRegs,
24086 /* V6_vmpyhsat_acc */
24087 HvxWR, HvxWR, HvxVR, IntRegs,
24088 /* V6_vmpyhsrs */
24089 HvxVR, HvxVR, IntRegs,
24090 /* V6_vmpyhss */
24091 HvxVR, HvxVR, IntRegs,
24092 /* V6_vmpyhus */
24093 HvxWR, HvxVR, HvxVR,
24094 /* V6_vmpyhus_acc */
24095 HvxWR, HvxWR, HvxVR, HvxVR,
24096 /* V6_vmpyhv */
24097 HvxWR, HvxVR, HvxVR,
24098 /* V6_vmpyhv_acc */
24099 HvxWR, HvxWR, HvxVR, HvxVR,
24100 /* V6_vmpyhvsrs */
24101 HvxVR, HvxVR, HvxVR,
24102 /* V6_vmpyieoh */
24103 HvxVR, HvxVR, HvxVR,
24104 /* V6_vmpyiewh_acc */
24105 HvxVR, HvxVR, HvxVR, HvxVR,
24106 /* V6_vmpyiewuh */
24107 HvxVR, HvxVR, HvxVR,
24108 /* V6_vmpyiewuh_acc */
24109 HvxVR, HvxVR, HvxVR, HvxVR,
24110 /* V6_vmpyih */
24111 HvxVR, HvxVR, HvxVR,
24112 /* V6_vmpyih_acc */
24113 HvxVR, HvxVR, HvxVR, HvxVR,
24114 /* V6_vmpyihb */
24115 HvxVR, HvxVR, IntRegs,
24116 /* V6_vmpyihb_acc */
24117 HvxVR, HvxVR, HvxVR, IntRegs,
24118 /* V6_vmpyiowh */
24119 HvxVR, HvxVR, HvxVR,
24120 /* V6_vmpyiwb */
24121 HvxVR, HvxVR, IntRegs,
24122 /* V6_vmpyiwb_acc */
24123 HvxVR, HvxVR, HvxVR, IntRegs,
24124 /* V6_vmpyiwh */
24125 HvxVR, HvxVR, IntRegs,
24126 /* V6_vmpyiwh_acc */
24127 HvxVR, HvxVR, HvxVR, IntRegs,
24128 /* V6_vmpyiwub */
24129 HvxVR, HvxVR, IntRegs,
24130 /* V6_vmpyiwub_acc */
24131 HvxVR, HvxVR, HvxVR, IntRegs,
24132 /* V6_vmpyowh */
24133 HvxVR, HvxVR, HvxVR,
24134 /* V6_vmpyowh_64_acc */
24135 HvxWR, HvxWR, HvxVR, HvxVR,
24136 /* V6_vmpyowh_rnd */
24137 HvxVR, HvxVR, HvxVR,
24138 /* V6_vmpyowh_rnd_sacc */
24139 HvxVR, HvxVR, HvxVR, HvxVR,
24140 /* V6_vmpyowh_sacc */
24141 HvxVR, HvxVR, HvxVR, HvxVR,
24142 /* V6_vmpyub */
24143 HvxWR, HvxVR, IntRegs,
24144 /* V6_vmpyub_acc */
24145 HvxWR, HvxWR, HvxVR, IntRegs,
24146 /* V6_vmpyubv */
24147 HvxWR, HvxVR, HvxVR,
24148 /* V6_vmpyubv_acc */
24149 HvxWR, HvxWR, HvxVR, HvxVR,
24150 /* V6_vmpyuh */
24151 HvxWR, HvxVR, IntRegs,
24152 /* V6_vmpyuh_acc */
24153 HvxWR, HvxWR, HvxVR, IntRegs,
24154 /* V6_vmpyuhe */
24155 HvxVR, HvxVR, IntRegs,
24156 /* V6_vmpyuhe_acc */
24157 HvxVR, HvxVR, HvxVR, IntRegs,
24158 /* V6_vmpyuhv */
24159 HvxWR, HvxVR, HvxVR,
24160 /* V6_vmpyuhv_acc */
24161 HvxWR, HvxWR, HvxVR, HvxVR,
24162 /* V6_vmpyuhvs */
24163 HvxVR, HvxVR, HvxVR,
24164 /* V6_vmux */
24165 HvxVR, HvxQR, HvxVR, HvxVR,
24166 /* V6_vnavgb */
24167 HvxVR, HvxVR, HvxVR,
24168 /* V6_vnavgh */
24169 HvxVR, HvxVR, HvxVR,
24170 /* V6_vnavgub */
24171 HvxVR, HvxVR, HvxVR,
24172 /* V6_vnavgw */
24173 HvxVR, HvxVR, HvxVR,
24174 /* V6_vnccombine */
24175 HvxWR, PredRegs, HvxVR, HvxVR,
24176 /* V6_vncmov */
24177 HvxVR, PredRegs, HvxVR,
24178 /* V6_vnormamth */
24179 HvxVR, HvxVR,
24180 /* V6_vnormamtw */
24181 HvxVR, HvxVR,
24182 /* V6_vnot */
24183 HvxVR, HvxVR,
24184 /* V6_vor */
24185 HvxVR, HvxVR, HvxVR,
24186 /* V6_vpackeb */
24187 HvxVR, HvxVR, HvxVR,
24188 /* V6_vpackeh */
24189 HvxVR, HvxVR, HvxVR,
24190 /* V6_vpackhb_sat */
24191 HvxVR, HvxVR, HvxVR,
24192 /* V6_vpackhub_sat */
24193 HvxVR, HvxVR, HvxVR,
24194 /* V6_vpackob */
24195 HvxVR, HvxVR, HvxVR,
24196 /* V6_vpackoh */
24197 HvxVR, HvxVR, HvxVR,
24198 /* V6_vpackwh_sat */
24199 HvxVR, HvxVR, HvxVR,
24200 /* V6_vpackwuh_sat */
24201 HvxVR, HvxVR, HvxVR,
24202 /* V6_vpopcounth */
24203 HvxVR, HvxVR,
24204 /* V6_vprefixqb */
24205 HvxVR, HvxQR,
24206 /* V6_vprefixqh */
24207 HvxVR, HvxQR,
24208 /* V6_vprefixqw */
24209 HvxVR, HvxQR,
24210 /* V6_vrdelta */
24211 HvxVR, HvxVR, HvxVR,
24212 /* V6_vrmpybub_rtt */
24213 HvxWR, HvxVR, DoubleRegs,
24214 /* V6_vrmpybub_rtt_acc */
24215 HvxWR, HvxWR, HvxVR, DoubleRegs,
24216 /* V6_vrmpybus */
24217 HvxVR, HvxVR, IntRegs,
24218 /* V6_vrmpybus_acc */
24219 HvxVR, HvxVR, HvxVR, IntRegs,
24220 /* V6_vrmpybusi */
24221 HvxWR, HvxWR, IntRegs, u1_0Imm,
24222 /* V6_vrmpybusi_acc */
24223 HvxWR, HvxWR, HvxWR, IntRegs, u1_0Imm,
24224 /* V6_vrmpybusv */
24225 HvxVR, HvxVR, HvxVR,
24226 /* V6_vrmpybusv_acc */
24227 HvxVR, HvxVR, HvxVR, HvxVR,
24228 /* V6_vrmpybv */
24229 HvxVR, HvxVR, HvxVR,
24230 /* V6_vrmpybv_acc */
24231 HvxVR, HvxVR, HvxVR, HvxVR,
24232 /* V6_vrmpyub */
24233 HvxVR, HvxVR, IntRegs,
24234 /* V6_vrmpyub_acc */
24235 HvxVR, HvxVR, HvxVR, IntRegs,
24236 /* V6_vrmpyub_rtt */
24237 HvxWR, HvxVR, DoubleRegs,
24238 /* V6_vrmpyub_rtt_acc */
24239 HvxWR, HvxWR, HvxVR, DoubleRegs,
24240 /* V6_vrmpyubi */
24241 HvxWR, HvxWR, IntRegs, u1_0Imm,
24242 /* V6_vrmpyubi_acc */
24243 HvxWR, HvxWR, HvxWR, IntRegs, u1_0Imm,
24244 /* V6_vrmpyubv */
24245 HvxVR, HvxVR, HvxVR,
24246 /* V6_vrmpyubv_acc */
24247 HvxVR, HvxVR, HvxVR, HvxVR,
24248 /* V6_vrmpyzbb_rt */
24249 HvxVQR, HvxVR, IntRegsLow8,
24250 /* V6_vrmpyzbb_rt_acc */
24251 HvxVQR, HvxVQR, HvxVR, IntRegsLow8,
24252 /* V6_vrmpyzbb_rx */
24253 HvxVQR, IntRegsLow8, HvxVR, IntRegsLow8,
24254 /* V6_vrmpyzbb_rx_acc */
24255 HvxVQR, IntRegsLow8, HvxVQR, HvxVR, IntRegsLow8,
24256 /* V6_vrmpyzbub_rt */
24257 HvxVQR, HvxVR, IntRegsLow8,
24258 /* V6_vrmpyzbub_rt_acc */
24259 HvxVQR, HvxVQR, HvxVR, IntRegsLow8,
24260 /* V6_vrmpyzbub_rx */
24261 HvxVQR, IntRegsLow8, HvxVR, IntRegsLow8,
24262 /* V6_vrmpyzbub_rx_acc */
24263 HvxVQR, IntRegsLow8, HvxVQR, HvxVR, IntRegsLow8,
24264 /* V6_vrmpyzcb_rt */
24265 HvxVQR, HvxVR, IntRegsLow8,
24266 /* V6_vrmpyzcb_rt_acc */
24267 HvxVQR, HvxVQR, HvxVR, IntRegsLow8,
24268 /* V6_vrmpyzcb_rx */
24269 HvxVQR, IntRegsLow8, HvxVR, IntRegsLow8,
24270 /* V6_vrmpyzcb_rx_acc */
24271 HvxVQR, IntRegsLow8, HvxVQR, HvxVR, IntRegsLow8,
24272 /* V6_vrmpyzcbs_rt */
24273 HvxVQR, HvxVR, IntRegsLow8,
24274 /* V6_vrmpyzcbs_rt_acc */
24275 HvxVQR, HvxVQR, HvxVR, IntRegsLow8,
24276 /* V6_vrmpyzcbs_rx */
24277 HvxVQR, IntRegsLow8, HvxVR, IntRegsLow8,
24278 /* V6_vrmpyzcbs_rx_acc */
24279 HvxVQR, IntRegsLow8, HvxVQR, HvxVR, IntRegsLow8,
24280 /* V6_vrmpyznb_rt */
24281 HvxVQR, HvxVR, IntRegsLow8,
24282 /* V6_vrmpyznb_rt_acc */
24283 HvxVQR, HvxVQR, HvxVR, IntRegsLow8,
24284 /* V6_vrmpyznb_rx */
24285 HvxVQR, IntRegsLow8, HvxVR, IntRegsLow8,
24286 /* V6_vrmpyznb_rx_acc */
24287 HvxVQR, IntRegsLow8, HvxVQR, HvxVR, IntRegsLow8,
24288 /* V6_vror */
24289 HvxVR, HvxVR, IntRegs,
24290 /* V6_vrotr */
24291 HvxVR, HvxVR, HvxVR,
24292 /* V6_vroundhb */
24293 HvxVR, HvxVR, HvxVR,
24294 /* V6_vroundhub */
24295 HvxVR, HvxVR, HvxVR,
24296 /* V6_vrounduhub */
24297 HvxVR, HvxVR, HvxVR,
24298 /* V6_vrounduwuh */
24299 HvxVR, HvxVR, HvxVR,
24300 /* V6_vroundwh */
24301 HvxVR, HvxVR, HvxVR,
24302 /* V6_vroundwuh */
24303 HvxVR, HvxVR, HvxVR,
24304 /* V6_vrsadubi */
24305 HvxWR, HvxWR, IntRegs, u1_0Imm,
24306 /* V6_vrsadubi_acc */
24307 HvxWR, HvxWR, HvxWR, IntRegs, u1_0Imm,
24308 /* V6_vsatdw */
24309 HvxVR, HvxVR, HvxVR,
24310 /* V6_vsathub */
24311 HvxVR, HvxVR, HvxVR,
24312 /* V6_vsatuwuh */
24313 HvxVR, HvxVR, HvxVR,
24314 /* V6_vsatwh */
24315 HvxVR, HvxVR, HvxVR,
24316 /* V6_vsb */
24317 HvxWR, HvxVR,
24318 /* V6_vscattermh */
24319 IntRegs, ModRegs, HvxVR, HvxVR,
24320 /* V6_vscattermh_add */
24321 IntRegs, ModRegs, HvxVR, HvxVR,
24322 /* V6_vscattermhq */
24323 HvxQR, IntRegs, ModRegs, HvxVR, HvxVR,
24324 /* V6_vscattermhw */
24325 IntRegs, ModRegs, HvxWR, HvxVR,
24326 /* V6_vscattermhw_add */
24327 IntRegs, ModRegs, HvxWR, HvxVR,
24328 /* V6_vscattermhwq */
24329 HvxQR, IntRegs, ModRegs, HvxWR, HvxVR,
24330 /* V6_vscattermw */
24331 IntRegs, ModRegs, HvxVR, HvxVR,
24332 /* V6_vscattermw_add */
24333 IntRegs, ModRegs, HvxVR, HvxVR,
24334 /* V6_vscattermwq */
24335 HvxQR, IntRegs, ModRegs, HvxVR, HvxVR,
24336 /* V6_vsh */
24337 HvxWR, HvxVR,
24338 /* V6_vshufeh */
24339 HvxVR, HvxVR, HvxVR,
24340 /* V6_vshuff */
24341 HvxVR, HvxVR, HvxVR, HvxVR, IntRegs,
24342 /* V6_vshuffb */
24343 HvxVR, HvxVR,
24344 /* V6_vshuffeb */
24345 HvxVR, HvxVR, HvxVR,
24346 /* V6_vshuffh */
24347 HvxVR, HvxVR,
24348 /* V6_vshuffob */
24349 HvxVR, HvxVR, HvxVR,
24350 /* V6_vshuffvdd */
24351 HvxWR, HvxVR, HvxVR, IntRegsLow8,
24352 /* V6_vshufoeb */
24353 HvxWR, HvxVR, HvxVR,
24354 /* V6_vshufoeh */
24355 HvxWR, HvxVR, HvxVR,
24356 /* V6_vshufoh */
24357 HvxVR, HvxVR, HvxVR,
24358 /* V6_vsub_hf */
24359 HvxVR, HvxVR, HvxVR,
24360 /* V6_vsub_hf_hf */
24361 HvxVR, HvxVR, HvxVR,
24362 /* V6_vsub_qf16 */
24363 HvxVR, HvxVR, HvxVR,
24364 /* V6_vsub_qf16_mix */
24365 HvxVR, HvxVR, HvxVR,
24366 /* V6_vsub_qf32 */
24367 HvxVR, HvxVR, HvxVR,
24368 /* V6_vsub_qf32_mix */
24369 HvxVR, HvxVR, HvxVR,
24370 /* V6_vsub_sf */
24371 HvxVR, HvxVR, HvxVR,
24372 /* V6_vsub_sf_bf */
24373 HvxWR, HvxVR, HvxVR,
24374 /* V6_vsub_sf_hf */
24375 HvxWR, HvxVR, HvxVR,
24376 /* V6_vsub_sf_sf */
24377 HvxVR, HvxVR, HvxVR,
24378 /* V6_vsubb */
24379 HvxVR, HvxVR, HvxVR,
24380 /* V6_vsubb_dv */
24381 HvxWR, HvxWR, HvxWR,
24382 /* V6_vsubbnq */
24383 HvxVR, HvxQR, HvxVR, HvxVR,
24384 /* V6_vsubbq */
24385 HvxVR, HvxQR, HvxVR, HvxVR,
24386 /* V6_vsubbsat */
24387 HvxVR, HvxVR, HvxVR,
24388 /* V6_vsubbsat_dv */
24389 HvxWR, HvxWR, HvxWR,
24390 /* V6_vsubcarry */
24391 HvxVR, HvxQR, HvxVR, HvxVR, HvxQR,
24392 /* V6_vsubcarryo */
24393 HvxVR, HvxQR, HvxVR, HvxVR,
24394 /* V6_vsubh */
24395 HvxVR, HvxVR, HvxVR,
24396 /* V6_vsubh_dv */
24397 HvxWR, HvxWR, HvxWR,
24398 /* V6_vsubhnq */
24399 HvxVR, HvxQR, HvxVR, HvxVR,
24400 /* V6_vsubhq */
24401 HvxVR, HvxQR, HvxVR, HvxVR,
24402 /* V6_vsubhsat */
24403 HvxVR, HvxVR, HvxVR,
24404 /* V6_vsubhsat_dv */
24405 HvxWR, HvxWR, HvxWR,
24406 /* V6_vsubhw */
24407 HvxWR, HvxVR, HvxVR,
24408 /* V6_vsububh */
24409 HvxWR, HvxVR, HvxVR,
24410 /* V6_vsububsat */
24411 HvxVR, HvxVR, HvxVR,
24412 /* V6_vsububsat_dv */
24413 HvxWR, HvxWR, HvxWR,
24414 /* V6_vsubububb_sat */
24415 HvxVR, HvxVR, HvxVR,
24416 /* V6_vsubuhsat */
24417 HvxVR, HvxVR, HvxVR,
24418 /* V6_vsubuhsat_dv */
24419 HvxWR, HvxWR, HvxWR,
24420 /* V6_vsubuhw */
24421 HvxWR, HvxVR, HvxVR,
24422 /* V6_vsubuwsat */
24423 HvxVR, HvxVR, HvxVR,
24424 /* V6_vsubuwsat_dv */
24425 HvxWR, HvxWR, HvxWR,
24426 /* V6_vsubw */
24427 HvxVR, HvxVR, HvxVR,
24428 /* V6_vsubw_dv */
24429 HvxWR, HvxWR, HvxWR,
24430 /* V6_vsubwnq */
24431 HvxVR, HvxQR, HvxVR, HvxVR,
24432 /* V6_vsubwq */
24433 HvxVR, HvxQR, HvxVR, HvxVR,
24434 /* V6_vsubwsat */
24435 HvxVR, HvxVR, HvxVR,
24436 /* V6_vsubwsat_dv */
24437 HvxWR, HvxWR, HvxWR,
24438 /* V6_vswap */
24439 HvxWR, HvxQR, HvxVR, HvxVR,
24440 /* V6_vtmpyb */
24441 HvxWR, HvxWR, IntRegs,
24442 /* V6_vtmpyb_acc */
24443 HvxWR, HvxWR, HvxWR, IntRegs,
24444 /* V6_vtmpybus */
24445 HvxWR, HvxWR, IntRegs,
24446 /* V6_vtmpybus_acc */
24447 HvxWR, HvxWR, HvxWR, IntRegs,
24448 /* V6_vtmpyhb */
24449 HvxWR, HvxWR, IntRegs,
24450 /* V6_vtmpyhb_acc */
24451 HvxWR, HvxWR, HvxWR, IntRegs,
24452 /* V6_vunpackb */
24453 HvxWR, HvxVR,
24454 /* V6_vunpackh */
24455 HvxWR, HvxVR,
24456 /* V6_vunpackob */
24457 HvxWR, HvxWR, HvxVR,
24458 /* V6_vunpackoh */
24459 HvxWR, HvxWR, HvxVR,
24460 /* V6_vunpackub */
24461 HvxWR, HvxVR,
24462 /* V6_vunpackuh */
24463 HvxWR, HvxVR,
24464 /* V6_vwhist128 */
24465 /* V6_vwhist128m */
24466 u1_0Imm,
24467 /* V6_vwhist128q */
24468 HvxQR,
24469 /* V6_vwhist128qm */
24470 HvxQR, u1_0Imm,
24471 /* V6_vwhist256 */
24472 /* V6_vwhist256_sat */
24473 /* V6_vwhist256q */
24474 HvxQR,
24475 /* V6_vwhist256q_sat */
24476 HvxQR,
24477 /* V6_vxor */
24478 HvxVR, HvxVR, HvxVR,
24479 /* V6_vzb */
24480 HvxWR, HvxVR,
24481 /* V6_vzh */
24482 HvxWR, HvxVR,
24483 /* V6_zLd_ai */
24484 IntRegs, s4_0Imm,
24485 /* V6_zLd_pi */
24486 IntRegs, IntRegs, s3_0Imm,
24487 /* V6_zLd_ppu */
24488 IntRegs, IntRegs, ModRegs,
24489 /* V6_zLd_pred_ai */
24490 PredRegs, IntRegs, s4_0Imm,
24491 /* V6_zLd_pred_pi */
24492 IntRegs, PredRegs, IntRegs, s3_0Imm,
24493 /* V6_zLd_pred_ppu */
24494 IntRegs, PredRegs, IntRegs, ModRegs,
24495 /* V6_zextract */
24496 HvxVR, IntRegs,
24497 /* Y2_barrier */
24498 /* Y2_break */
24499 /* Y2_ciad */
24500 IntRegs,
24501 /* Y2_crswap0 */
24502 IntRegs, IntRegs,
24503 /* Y2_cswi */
24504 IntRegs,
24505 /* Y2_dccleana */
24506 IntRegs,
24507 /* Y2_dccleanidx */
24508 IntRegs,
24509 /* Y2_dccleaninva */
24510 IntRegs,
24511 /* Y2_dccleaninvidx */
24512 IntRegs,
24513 /* Y2_dcfetchbo */
24514 IntRegs, u11_3Imm,
24515 /* Y2_dcinva */
24516 IntRegs,
24517 /* Y2_dcinvidx */
24518 IntRegs,
24519 /* Y2_dckill */
24520 /* Y2_dctagr */
24521 IntRegs, IntRegs,
24522 /* Y2_dctagw */
24523 IntRegs, IntRegs,
24524 /* Y2_dczeroa */
24525 IntRegs,
24526 /* Y2_getimask */
24527 IntRegs, IntRegs,
24528 /* Y2_iassignr */
24529 IntRegs, IntRegs,
24530 /* Y2_iassignw */
24531 IntRegs,
24532 /* Y2_icdatar */
24533 IntRegs, IntRegs,
24534 /* Y2_icdataw */
24535 IntRegs, IntRegs,
24536 /* Y2_icinva */
24537 IntRegs,
24538 /* Y2_icinvidx */
24539 IntRegs,
24540 /* Y2_ickill */
24541 /* Y2_ictagr */
24542 IntRegs, IntRegs,
24543 /* Y2_ictagw */
24544 IntRegs, IntRegs,
24545 /* Y2_isync */
24546 /* Y2_k0lock */
24547 /* Y2_k0unlock */
24548 /* Y2_l2cleaninvidx */
24549 IntRegs,
24550 /* Y2_l2kill */
24551 /* Y2_resume */
24552 IntRegs,
24553 /* Y2_setimask */
24554 PredRegs, IntRegs,
24555 /* Y2_setprio */
24556 PredRegs, IntRegs,
24557 /* Y2_start */
24558 IntRegs,
24559 /* Y2_stop */
24560 IntRegs,
24561 /* Y2_swi */
24562 IntRegs,
24563 /* Y2_syncht */
24564 /* Y2_tfrscrr */
24565 IntRegs, SysRegs,
24566 /* Y2_tfrsrcr */
24567 SysRegs, IntRegs,
24568 /* Y2_tlblock */
24569 /* Y2_tlbp */
24570 IntRegs, IntRegs,
24571 /* Y2_tlbr */
24572 DoubleRegs, IntRegs,
24573 /* Y2_tlbunlock */
24574 /* Y2_tlbw */
24575 DoubleRegs, IntRegs,
24576 /* Y2_wait */
24577 IntRegs,
24578 /* Y4_crswap1 */
24579 IntRegs, IntRegs,
24580 /* Y4_crswap10 */
24581 DoubleRegs, DoubleRegs, sgp10Const,
24582 /* Y4_l2fetch */
24583 IntRegs, IntRegs,
24584 /* Y4_l2tagr */
24585 IntRegs, IntRegs,
24586 /* Y4_l2tagw */
24587 IntRegs, IntRegs,
24588 /* Y4_nmi */
24589 IntRegs,
24590 /* Y4_siad */
24591 IntRegs,
24592 /* Y4_tfrscpp */
24593 DoubleRegs, SysRegs64,
24594 /* Y4_tfrspcp */
24595 SysRegs64, DoubleRegs,
24596 /* Y4_trace */
24597 IntRegs,
24598 /* Y5_ctlbw */
24599 IntRegs, DoubleRegs, IntRegs,
24600 /* Y5_l2cleanidx */
24601 IntRegs,
24602 /* Y5_l2fetch */
24603 IntRegs, DoubleRegs,
24604 /* Y5_l2gclean */
24605 /* Y5_l2gcleaninv */
24606 /* Y5_l2gunlock */
24607 /* Y5_l2invidx */
24608 IntRegs,
24609 /* Y5_l2locka */
24610 PredRegs, IntRegs,
24611 /* Y5_l2unlocka */
24612 IntRegs,
24613 /* Y5_tlbasidi */
24614 IntRegs,
24615 /* Y5_tlboc */
24616 IntRegs, DoubleRegs,
24617 /* Y6_diag */
24618 IntRegs,
24619 /* Y6_diag0 */
24620 DoubleRegs, DoubleRegs,
24621 /* Y6_diag1 */
24622 DoubleRegs, DoubleRegs,
24623 /* Y6_dmlink */
24624 IntRegs, IntRegs,
24625 /* Y6_dmpause */
24626 IntRegs,
24627 /* Y6_dmpoll */
24628 IntRegs,
24629 /* Y6_dmresume */
24630 IntRegs,
24631 /* Y6_dmstart */
24632 IntRegs,
24633 /* Y6_dmwait */
24634 IntRegs,
24635 /* Y6_l2gcleaninvpa */
24636 DoubleRegs,
24637 /* Y6_l2gcleanpa */
24638 DoubleRegs,
24639 /* dep_A2_addsat */
24640 IntRegs, IntRegs, IntRegs,
24641 /* dep_A2_subsat */
24642 IntRegs, IntRegs, IntRegs,
24643 /* dep_S2_packhl */
24644 DoubleRegs, IntRegs, IntRegs,
24645 };
24646 return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
24647}
24648} // end namespace Hexagon
24649} // end namespace llvm
24650#endif // GET_INSTRINFO_OPERAND_TYPE
24651
24652#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
24653#undef GET_INSTRINFO_MEM_OPERAND_SIZE
24654namespace llvm {
24655namespace Hexagon {
24656LLVM_READONLY
24657static int getMemOperandSize(int OpType) {
24658 switch (OpType) {
24659 default: return 0;
24660 }
24661}
24662} // end namespace Hexagon
24663} // end namespace llvm
24664#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
24665
24666#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
24667#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
24668namespace llvm {
24669namespace Hexagon {
24670LLVM_READONLY static unsigned
24671getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
24672 return LogicalOpIdx;
24673}
24674LLVM_READONLY static inline unsigned
24675getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
24676 auto S = 0U;
24677 for (auto i = 0U; i < LogicalOpIdx; ++i)
24678 S += getLogicalOperandSize(Opcode, i);
24679 return S;
24680}
24681} // end namespace Hexagon
24682} // end namespace llvm
24683#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
24684
24685#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
24686#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
24687namespace llvm {
24688namespace Hexagon {
24689LLVM_READONLY static int
24690getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
24691 return -1;
24692}
24693} // end namespace Hexagon
24694} // end namespace llvm
24695#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
24696
24697#ifdef GET_INSTRINFO_MC_HELPER_DECLS
24698#undef GET_INSTRINFO_MC_HELPER_DECLS
24699
24700namespace llvm {
24701class MCInst;
24702class FeatureBitset;
24703
24704namespace Hexagon_MC {
24705
24706void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
24707
24708} // end namespace Hexagon_MC
24709} // end namespace llvm
24710
24711#endif // GET_INSTRINFO_MC_HELPER_DECLS
24712
24713#ifdef GET_INSTRINFO_MC_HELPERS
24714#undef GET_INSTRINFO_MC_HELPERS
24715
24716namespace llvm {
24717namespace Hexagon_MC {
24718
24719} // end namespace Hexagon_MC
24720} // end namespace llvm
24721
24722#endif // GET_GENISTRINFO_MC_HELPERS
24723
24724#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
24725 defined(GET_AVAILABLE_OPCODE_CHECKER)
24726#define GET_COMPUTE_FEATURES
24727#endif
24728#ifdef GET_COMPUTE_FEATURES
24729#undef GET_COMPUTE_FEATURES
24730namespace llvm {
24731namespace Hexagon_MC {
24732
24733// Bits for subtarget features that participate in instruction matching.
24734enum SubtargetFeatureBits : uint8_t {
24735 Feature_HasV5Bit = 2,
24736 Feature_HasV55Bit = 3,
24737 Feature_HasV60Bit = 4,
24738 Feature_HasV62Bit = 5,
24739 Feature_HasV65Bit = 6,
24740 Feature_HasV66Bit = 7,
24741 Feature_HasV67Bit = 8,
24742 Feature_HasV68Bit = 9,
24743 Feature_HasV69Bit = 10,
24744 Feature_HasV71Bit = 11,
24745 Feature_HasV73Bit = 12,
24746 Feature_UseHVX64BBit = 16,
24747 Feature_UseHVX128BBit = 17,
24748 Feature_UseHVXBit = 15,
24749 Feature_UseHVXV60Bit = 20,
24750 Feature_UseHVXV62Bit = 21,
24751 Feature_UseHVXV65Bit = 22,
24752 Feature_UseHVXV66Bit = 23,
24753 Feature_UseHVXV67Bit = 24,
24754 Feature_UseHVXV68Bit = 25,
24755 Feature_UseHVXV69Bit = 26,
24756 Feature_UseHVXV71Bit = 27,
24757 Feature_UseHVXV73Bit = 28,
24758 Feature_UseAudioBit = 13,
24759 Feature_UseZRegBit = 29,
24760 Feature_HasPreV65Bit = 1,
24761 Feature_UseHVXIEEEFPBit = 18,
24762 Feature_UseHVXQFloatBit = 19,
24763 Feature_HasMemNoShufBit = 0,
24764 Feature_UseCabacBit = 14,
24765};
24766
24767inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
24768 FeatureBitset Features;
24769 if (FB[Hexagon::ArchV5])
24770 Features.set(Feature_HasV5Bit);
24771 if (FB[Hexagon::ArchV55])
24772 Features.set(Feature_HasV55Bit);
24773 if (FB[Hexagon::ArchV60])
24774 Features.set(Feature_HasV60Bit);
24775 if (FB[Hexagon::ArchV62])
24776 Features.set(Feature_HasV62Bit);
24777 if (FB[Hexagon::ArchV65])
24778 Features.set(Feature_HasV65Bit);
24779 if (FB[Hexagon::ArchV66])
24780 Features.set(Feature_HasV66Bit);
24781 if (FB[Hexagon::ArchV67])
24782 Features.set(Feature_HasV67Bit);
24783 if (FB[Hexagon::ArchV68])
24784 Features.set(Feature_HasV68Bit);
24785 if (FB[Hexagon::ArchV69])
24786 Features.set(Feature_HasV69Bit);
24787 if (FB[Hexagon::ArchV71])
24788 Features.set(Feature_HasV71Bit);
24789 if (FB[Hexagon::ArchV73])
24790 Features.set(Feature_HasV73Bit);
24791 if (FB[Hexagon::ExtensionHVX64B])
24792 Features.set(Feature_UseHVX64BBit);
24793 if (FB[Hexagon::ExtensionHVX128B])
24794 Features.set(Feature_UseHVX128BBit);
24795 if (FB[Hexagon::ExtensionHVXV60])
24796 Features.set(Feature_UseHVXBit);
24797 if (FB[Hexagon::ExtensionHVXV60])
24798 Features.set(Feature_UseHVXV60Bit);
24799 if (FB[Hexagon::ExtensionHVXV62])
24800 Features.set(Feature_UseHVXV62Bit);
24801 if (FB[Hexagon::ExtensionHVXV65])
24802 Features.set(Feature_UseHVXV65Bit);
24803 if (FB[Hexagon::ExtensionHVXV66])
24804 Features.set(Feature_UseHVXV66Bit);
24805 if (FB[Hexagon::ExtensionHVXV67])
24806 Features.set(Feature_UseHVXV67Bit);
24807 if (FB[Hexagon::ExtensionHVXV68])
24808 Features.set(Feature_UseHVXV68Bit);
24809 if (FB[Hexagon::ExtensionHVXV69])
24810 Features.set(Feature_UseHVXV69Bit);
24811 if (FB[Hexagon::ExtensionHVXV71])
24812 Features.set(Feature_UseHVXV71Bit);
24813 if (FB[Hexagon::ExtensionHVXV73])
24814 Features.set(Feature_UseHVXV73Bit);
24815 if (FB[Hexagon::ExtensionAudio])
24816 Features.set(Feature_UseAudioBit);
24817 if (FB[Hexagon::ExtensionZReg])
24818 Features.set(Feature_UseZRegBit);
24819 if (FB[Hexagon::FeaturePreV65])
24820 Features.set(Feature_HasPreV65Bit);
24821 if (FB[Hexagon::ExtensionHVXIEEEFP])
24822 Features.set(Feature_UseHVXIEEEFPBit);
24823 if (FB[Hexagon::ExtensionHVXQFloat])
24824 Features.set(Feature_UseHVXQFloatBit);
24825 if (FB[Hexagon::FeatureMemNoShuf])
24826 Features.set(Feature_HasMemNoShufBit);
24827 if (FB[Hexagon::FeatureCabac])
24828 Features.set(Feature_UseCabacBit);
24829 return Features;
24830}
24831
24832inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
24833 enum : uint8_t {
24834 CEFBS_None,
24835 CEFBS_HasPreV65,
24836 CEFBS_HasV55,
24837 CEFBS_HasV60,
24838 CEFBS_HasV62,
24839 CEFBS_HasV65,
24840 CEFBS_HasV66,
24841 CEFBS_HasV67,
24842 CEFBS_HasV68,
24843 CEFBS_HasV73,
24844 CEFBS_UseCabac,
24845 CEFBS_UseHVX,
24846 CEFBS_UseHVXV60,
24847 CEFBS_UseHVXV62,
24848 CEFBS_UseHVXV65,
24849 CEFBS_UseHVXV66,
24850 CEFBS_UseHVXV68,
24851 CEFBS_UseHVXV69,
24852 CEFBS_UseHVXV73,
24853 CEFBS_HasV60_UseHVX,
24854 CEFBS_HasV67_UseAudio,
24855 CEFBS_UseHVXV66_UseZReg,
24856 CEFBS_UseHVXV68_UseHVXIEEEFP,
24857 CEFBS_UseHVXV68_UseHVXQFloat,
24858 CEFBS_UseHVXV73_UseHVXIEEEFP,
24859 CEFBS_UseHVXV73_UseHVXQFloat,
24860 };
24861
24862 static constexpr FeatureBitset FeatureBitsets[] = {
24863 {}, // CEFBS_None
24864 {Feature_HasPreV65Bit, },
24865 {Feature_HasV55Bit, },
24866 {Feature_HasV60Bit, },
24867 {Feature_HasV62Bit, },
24868 {Feature_HasV65Bit, },
24869 {Feature_HasV66Bit, },
24870 {Feature_HasV67Bit, },
24871 {Feature_HasV68Bit, },
24872 {Feature_HasV73Bit, },
24873 {Feature_UseCabacBit, },
24874 {Feature_UseHVXBit, },
24875 {Feature_UseHVXV60Bit, },
24876 {Feature_UseHVXV62Bit, },
24877 {Feature_UseHVXV65Bit, },
24878 {Feature_UseHVXV66Bit, },
24879 {Feature_UseHVXV68Bit, },
24880 {Feature_UseHVXV69Bit, },
24881 {Feature_UseHVXV73Bit, },
24882 {Feature_HasV60Bit, Feature_UseHVXBit, },
24883 {Feature_HasV67Bit, Feature_UseAudioBit, },
24884 {Feature_UseHVXV66Bit, Feature_UseZRegBit, },
24885 {Feature_UseHVXV68Bit, Feature_UseHVXIEEEFPBit, },
24886 {Feature_UseHVXV68Bit, Feature_UseHVXQFloatBit, },
24887 {Feature_UseHVXV73Bit, Feature_UseHVXIEEEFPBit, },
24888 {Feature_UseHVXV73Bit, Feature_UseHVXQFloatBit, },
24889 };
24890 static constexpr uint8_t RequiredFeaturesRefs[] = {
24891 CEFBS_None, // PHI = 0
24892 CEFBS_None, // INLINEASM = 1
24893 CEFBS_None, // INLINEASM_BR = 2
24894 CEFBS_None, // CFI_INSTRUCTION = 3
24895 CEFBS_None, // EH_LABEL = 4
24896 CEFBS_None, // GC_LABEL = 5
24897 CEFBS_None, // ANNOTATION_LABEL = 6
24898 CEFBS_None, // KILL = 7
24899 CEFBS_None, // EXTRACT_SUBREG = 8
24900 CEFBS_None, // INSERT_SUBREG = 9
24901 CEFBS_None, // IMPLICIT_DEF = 10
24902 CEFBS_None, // SUBREG_TO_REG = 11
24903 CEFBS_None, // COPY_TO_REGCLASS = 12
24904 CEFBS_None, // DBG_VALUE = 13
24905 CEFBS_None, // DBG_VALUE_LIST = 14
24906 CEFBS_None, // DBG_INSTR_REF = 15
24907 CEFBS_None, // DBG_PHI = 16
24908 CEFBS_None, // DBG_LABEL = 17
24909 CEFBS_None, // REG_SEQUENCE = 18
24910 CEFBS_None, // COPY = 19
24911 CEFBS_None, // BUNDLE = 20
24912 CEFBS_None, // LIFETIME_START = 21
24913 CEFBS_None, // LIFETIME_END = 22
24914 CEFBS_None, // PSEUDO_PROBE = 23
24915 CEFBS_None, // ARITH_FENCE = 24
24916 CEFBS_None, // STACKMAP = 25
24917 CEFBS_None, // FENTRY_CALL = 26
24918 CEFBS_None, // PATCHPOINT = 27
24919 CEFBS_None, // LOAD_STACK_GUARD = 28
24920 CEFBS_None, // PREALLOCATED_SETUP = 29
24921 CEFBS_None, // PREALLOCATED_ARG = 30
24922 CEFBS_None, // STATEPOINT = 31
24923 CEFBS_None, // LOCAL_ESCAPE = 32
24924 CEFBS_None, // FAULTING_OP = 33
24925 CEFBS_None, // PATCHABLE_OP = 34
24926 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
24927 CEFBS_None, // PATCHABLE_RET = 36
24928 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
24929 CEFBS_None, // PATCHABLE_TAIL_CALL = 38
24930 CEFBS_None, // PATCHABLE_EVENT_CALL = 39
24931 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
24932 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
24933 CEFBS_None, // MEMBARRIER = 42
24934 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
24935 CEFBS_None, // CONVERGENCECTRL_ENTRY = 44
24936 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 45
24937 CEFBS_None, // CONVERGENCECTRL_LOOP = 46
24938 CEFBS_None, // CONVERGENCECTRL_GLUE = 47
24939 CEFBS_None, // G_ASSERT_SEXT = 48
24940 CEFBS_None, // G_ASSERT_ZEXT = 49
24941 CEFBS_None, // G_ASSERT_ALIGN = 50
24942 CEFBS_None, // G_ADD = 51
24943 CEFBS_None, // G_SUB = 52
24944 CEFBS_None, // G_MUL = 53
24945 CEFBS_None, // G_SDIV = 54
24946 CEFBS_None, // G_UDIV = 55
24947 CEFBS_None, // G_SREM = 56
24948 CEFBS_None, // G_UREM = 57
24949 CEFBS_None, // G_SDIVREM = 58
24950 CEFBS_None, // G_UDIVREM = 59
24951 CEFBS_None, // G_AND = 60
24952 CEFBS_None, // G_OR = 61
24953 CEFBS_None, // G_XOR = 62
24954 CEFBS_None, // G_IMPLICIT_DEF = 63
24955 CEFBS_None, // G_PHI = 64
24956 CEFBS_None, // G_FRAME_INDEX = 65
24957 CEFBS_None, // G_GLOBAL_VALUE = 66
24958 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 67
24959 CEFBS_None, // G_CONSTANT_POOL = 68
24960 CEFBS_None, // G_EXTRACT = 69
24961 CEFBS_None, // G_UNMERGE_VALUES = 70
24962 CEFBS_None, // G_INSERT = 71
24963 CEFBS_None, // G_MERGE_VALUES = 72
24964 CEFBS_None, // G_BUILD_VECTOR = 73
24965 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 74
24966 CEFBS_None, // G_CONCAT_VECTORS = 75
24967 CEFBS_None, // G_PTRTOINT = 76
24968 CEFBS_None, // G_INTTOPTR = 77
24969 CEFBS_None, // G_BITCAST = 78
24970 CEFBS_None, // G_FREEZE = 79
24971 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 80
24972 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 81
24973 CEFBS_None, // G_INTRINSIC_TRUNC = 82
24974 CEFBS_None, // G_INTRINSIC_ROUND = 83
24975 CEFBS_None, // G_INTRINSIC_LRINT = 84
24976 CEFBS_None, // G_INTRINSIC_LLRINT = 85
24977 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 86
24978 CEFBS_None, // G_READCYCLECOUNTER = 87
24979 CEFBS_None, // G_READSTEADYCOUNTER = 88
24980 CEFBS_None, // G_LOAD = 89
24981 CEFBS_None, // G_SEXTLOAD = 90
24982 CEFBS_None, // G_ZEXTLOAD = 91
24983 CEFBS_None, // G_INDEXED_LOAD = 92
24984 CEFBS_None, // G_INDEXED_SEXTLOAD = 93
24985 CEFBS_None, // G_INDEXED_ZEXTLOAD = 94
24986 CEFBS_None, // G_STORE = 95
24987 CEFBS_None, // G_INDEXED_STORE = 96
24988 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97
24989 CEFBS_None, // G_ATOMIC_CMPXCHG = 98
24990 CEFBS_None, // G_ATOMICRMW_XCHG = 99
24991 CEFBS_None, // G_ATOMICRMW_ADD = 100
24992 CEFBS_None, // G_ATOMICRMW_SUB = 101
24993 CEFBS_None, // G_ATOMICRMW_AND = 102
24994 CEFBS_None, // G_ATOMICRMW_NAND = 103
24995 CEFBS_None, // G_ATOMICRMW_OR = 104
24996 CEFBS_None, // G_ATOMICRMW_XOR = 105
24997 CEFBS_None, // G_ATOMICRMW_MAX = 106
24998 CEFBS_None, // G_ATOMICRMW_MIN = 107
24999 CEFBS_None, // G_ATOMICRMW_UMAX = 108
25000 CEFBS_None, // G_ATOMICRMW_UMIN = 109
25001 CEFBS_None, // G_ATOMICRMW_FADD = 110
25002 CEFBS_None, // G_ATOMICRMW_FSUB = 111
25003 CEFBS_None, // G_ATOMICRMW_FMAX = 112
25004 CEFBS_None, // G_ATOMICRMW_FMIN = 113
25005 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 114
25006 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 115
25007 CEFBS_None, // G_FENCE = 116
25008 CEFBS_None, // G_PREFETCH = 117
25009 CEFBS_None, // G_BRCOND = 118
25010 CEFBS_None, // G_BRINDIRECT = 119
25011 CEFBS_None, // G_INVOKE_REGION_START = 120
25012 CEFBS_None, // G_INTRINSIC = 121
25013 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 122
25014 CEFBS_None, // G_INTRINSIC_CONVERGENT = 123
25015 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124
25016 CEFBS_None, // G_ANYEXT = 125
25017 CEFBS_None, // G_TRUNC = 126
25018 CEFBS_None, // G_CONSTANT = 127
25019 CEFBS_None, // G_FCONSTANT = 128
25020 CEFBS_None, // G_VASTART = 129
25021 CEFBS_None, // G_VAARG = 130
25022 CEFBS_None, // G_SEXT = 131
25023 CEFBS_None, // G_SEXT_INREG = 132
25024 CEFBS_None, // G_ZEXT = 133
25025 CEFBS_None, // G_SHL = 134
25026 CEFBS_None, // G_LSHR = 135
25027 CEFBS_None, // G_ASHR = 136
25028 CEFBS_None, // G_FSHL = 137
25029 CEFBS_None, // G_FSHR = 138
25030 CEFBS_None, // G_ROTR = 139
25031 CEFBS_None, // G_ROTL = 140
25032 CEFBS_None, // G_ICMP = 141
25033 CEFBS_None, // G_FCMP = 142
25034 CEFBS_None, // G_SCMP = 143
25035 CEFBS_None, // G_UCMP = 144
25036 CEFBS_None, // G_SELECT = 145
25037 CEFBS_None, // G_UADDO = 146
25038 CEFBS_None, // G_UADDE = 147
25039 CEFBS_None, // G_USUBO = 148
25040 CEFBS_None, // G_USUBE = 149
25041 CEFBS_None, // G_SADDO = 150
25042 CEFBS_None, // G_SADDE = 151
25043 CEFBS_None, // G_SSUBO = 152
25044 CEFBS_None, // G_SSUBE = 153
25045 CEFBS_None, // G_UMULO = 154
25046 CEFBS_None, // G_SMULO = 155
25047 CEFBS_None, // G_UMULH = 156
25048 CEFBS_None, // G_SMULH = 157
25049 CEFBS_None, // G_UADDSAT = 158
25050 CEFBS_None, // G_SADDSAT = 159
25051 CEFBS_None, // G_USUBSAT = 160
25052 CEFBS_None, // G_SSUBSAT = 161
25053 CEFBS_None, // G_USHLSAT = 162
25054 CEFBS_None, // G_SSHLSAT = 163
25055 CEFBS_None, // G_SMULFIX = 164
25056 CEFBS_None, // G_UMULFIX = 165
25057 CEFBS_None, // G_SMULFIXSAT = 166
25058 CEFBS_None, // G_UMULFIXSAT = 167
25059 CEFBS_None, // G_SDIVFIX = 168
25060 CEFBS_None, // G_UDIVFIX = 169
25061 CEFBS_None, // G_SDIVFIXSAT = 170
25062 CEFBS_None, // G_UDIVFIXSAT = 171
25063 CEFBS_None, // G_FADD = 172
25064 CEFBS_None, // G_FSUB = 173
25065 CEFBS_None, // G_FMUL = 174
25066 CEFBS_None, // G_FMA = 175
25067 CEFBS_None, // G_FMAD = 176
25068 CEFBS_None, // G_FDIV = 177
25069 CEFBS_None, // G_FREM = 178
25070 CEFBS_None, // G_FPOW = 179
25071 CEFBS_None, // G_FPOWI = 180
25072 CEFBS_None, // G_FEXP = 181
25073 CEFBS_None, // G_FEXP2 = 182
25074 CEFBS_None, // G_FEXP10 = 183
25075 CEFBS_None, // G_FLOG = 184
25076 CEFBS_None, // G_FLOG2 = 185
25077 CEFBS_None, // G_FLOG10 = 186
25078 CEFBS_None, // G_FLDEXP = 187
25079 CEFBS_None, // G_FFREXP = 188
25080 CEFBS_None, // G_FNEG = 189
25081 CEFBS_None, // G_FPEXT = 190
25082 CEFBS_None, // G_FPTRUNC = 191
25083 CEFBS_None, // G_FPTOSI = 192
25084 CEFBS_None, // G_FPTOUI = 193
25085 CEFBS_None, // G_SITOFP = 194
25086 CEFBS_None, // G_UITOFP = 195
25087 CEFBS_None, // G_FABS = 196
25088 CEFBS_None, // G_FCOPYSIGN = 197
25089 CEFBS_None, // G_IS_FPCLASS = 198
25090 CEFBS_None, // G_FCANONICALIZE = 199
25091 CEFBS_None, // G_FMINNUM = 200
25092 CEFBS_None, // G_FMAXNUM = 201
25093 CEFBS_None, // G_FMINNUM_IEEE = 202
25094 CEFBS_None, // G_FMAXNUM_IEEE = 203
25095 CEFBS_None, // G_FMINIMUM = 204
25096 CEFBS_None, // G_FMAXIMUM = 205
25097 CEFBS_None, // G_GET_FPENV = 206
25098 CEFBS_None, // G_SET_FPENV = 207
25099 CEFBS_None, // G_RESET_FPENV = 208
25100 CEFBS_None, // G_GET_FPMODE = 209
25101 CEFBS_None, // G_SET_FPMODE = 210
25102 CEFBS_None, // G_RESET_FPMODE = 211
25103 CEFBS_None, // G_PTR_ADD = 212
25104 CEFBS_None, // G_PTRMASK = 213
25105 CEFBS_None, // G_SMIN = 214
25106 CEFBS_None, // G_SMAX = 215
25107 CEFBS_None, // G_UMIN = 216
25108 CEFBS_None, // G_UMAX = 217
25109 CEFBS_None, // G_ABS = 218
25110 CEFBS_None, // G_LROUND = 219
25111 CEFBS_None, // G_LLROUND = 220
25112 CEFBS_None, // G_BR = 221
25113 CEFBS_None, // G_BRJT = 222
25114 CEFBS_None, // G_VSCALE = 223
25115 CEFBS_None, // G_INSERT_SUBVECTOR = 224
25116 CEFBS_None, // G_EXTRACT_SUBVECTOR = 225
25117 CEFBS_None, // G_INSERT_VECTOR_ELT = 226
25118 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 227
25119 CEFBS_None, // G_SHUFFLE_VECTOR = 228
25120 CEFBS_None, // G_SPLAT_VECTOR = 229
25121 CEFBS_None, // G_VECTOR_COMPRESS = 230
25122 CEFBS_None, // G_CTTZ = 231
25123 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 232
25124 CEFBS_None, // G_CTLZ = 233
25125 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 234
25126 CEFBS_None, // G_CTPOP = 235
25127 CEFBS_None, // G_BSWAP = 236
25128 CEFBS_None, // G_BITREVERSE = 237
25129 CEFBS_None, // G_FCEIL = 238
25130 CEFBS_None, // G_FCOS = 239
25131 CEFBS_None, // G_FSIN = 240
25132 CEFBS_None, // G_FTAN = 241
25133 CEFBS_None, // G_FACOS = 242
25134 CEFBS_None, // G_FASIN = 243
25135 CEFBS_None, // G_FATAN = 244
25136 CEFBS_None, // G_FCOSH = 245
25137 CEFBS_None, // G_FSINH = 246
25138 CEFBS_None, // G_FTANH = 247
25139 CEFBS_None, // G_FSQRT = 248
25140 CEFBS_None, // G_FFLOOR = 249
25141 CEFBS_None, // G_FRINT = 250
25142 CEFBS_None, // G_FNEARBYINT = 251
25143 CEFBS_None, // G_ADDRSPACE_CAST = 252
25144 CEFBS_None, // G_BLOCK_ADDR = 253
25145 CEFBS_None, // G_JUMP_TABLE = 254
25146 CEFBS_None, // G_DYN_STACKALLOC = 255
25147 CEFBS_None, // G_STACKSAVE = 256
25148 CEFBS_None, // G_STACKRESTORE = 257
25149 CEFBS_None, // G_STRICT_FADD = 258
25150 CEFBS_None, // G_STRICT_FSUB = 259
25151 CEFBS_None, // G_STRICT_FMUL = 260
25152 CEFBS_None, // G_STRICT_FDIV = 261
25153 CEFBS_None, // G_STRICT_FREM = 262
25154 CEFBS_None, // G_STRICT_FMA = 263
25155 CEFBS_None, // G_STRICT_FSQRT = 264
25156 CEFBS_None, // G_STRICT_FLDEXP = 265
25157 CEFBS_None, // G_READ_REGISTER = 266
25158 CEFBS_None, // G_WRITE_REGISTER = 267
25159 CEFBS_None, // G_MEMCPY = 268
25160 CEFBS_None, // G_MEMCPY_INLINE = 269
25161 CEFBS_None, // G_MEMMOVE = 270
25162 CEFBS_None, // G_MEMSET = 271
25163 CEFBS_None, // G_BZERO = 272
25164 CEFBS_None, // G_TRAP = 273
25165 CEFBS_None, // G_DEBUGTRAP = 274
25166 CEFBS_None, // G_UBSANTRAP = 275
25167 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 276
25168 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 277
25169 CEFBS_None, // G_VECREDUCE_FADD = 278
25170 CEFBS_None, // G_VECREDUCE_FMUL = 279
25171 CEFBS_None, // G_VECREDUCE_FMAX = 280
25172 CEFBS_None, // G_VECREDUCE_FMIN = 281
25173 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 282
25174 CEFBS_None, // G_VECREDUCE_FMINIMUM = 283
25175 CEFBS_None, // G_VECREDUCE_ADD = 284
25176 CEFBS_None, // G_VECREDUCE_MUL = 285
25177 CEFBS_None, // G_VECREDUCE_AND = 286
25178 CEFBS_None, // G_VECREDUCE_OR = 287
25179 CEFBS_None, // G_VECREDUCE_XOR = 288
25180 CEFBS_None, // G_VECREDUCE_SMAX = 289
25181 CEFBS_None, // G_VECREDUCE_SMIN = 290
25182 CEFBS_None, // G_VECREDUCE_UMAX = 291
25183 CEFBS_None, // G_VECREDUCE_UMIN = 292
25184 CEFBS_None, // G_SBFX = 293
25185 CEFBS_None, // G_UBFX = 294
25186 CEFBS_None, // A2_addsp = 295
25187 CEFBS_None, // A2_iconst = 296
25188 CEFBS_None, // A2_neg = 297
25189 CEFBS_None, // A2_not = 298
25190 CEFBS_None, // A2_tfrf = 299
25191 CEFBS_None, // A2_tfrfnew = 300
25192 CEFBS_None, // A2_tfrp = 301
25193 CEFBS_None, // A2_tfrpf = 302
25194 CEFBS_None, // A2_tfrpfnew = 303
25195 CEFBS_None, // A2_tfrpi = 304
25196 CEFBS_None, // A2_tfrpt = 305
25197 CEFBS_None, // A2_tfrptnew = 306
25198 CEFBS_None, // A2_tfrt = 307
25199 CEFBS_None, // A2_tfrtnew = 308
25200 CEFBS_None, // A2_vaddb_map = 309
25201 CEFBS_None, // A2_vsubb_map = 310
25202 CEFBS_None, // A2_zxtb = 311
25203 CEFBS_None, // A4_boundscheck = 312
25204 CEFBS_None, // ADJCALLSTACKDOWN = 313
25205 CEFBS_None, // ADJCALLSTACKUP = 314
25206 CEFBS_None, // C2_cmpgei = 315
25207 CEFBS_None, // C2_cmpgeui = 316
25208 CEFBS_None, // C2_cmplt = 317
25209 CEFBS_None, // C2_cmpltu = 318
25210 CEFBS_None, // C2_pxfer_map = 319
25211 CEFBS_None, // DUPLEX_Pseudo = 320
25212 CEFBS_None, // ENDLOOP0 = 321
25213 CEFBS_None, // ENDLOOP01 = 322
25214 CEFBS_None, // ENDLOOP1 = 323
25215 CEFBS_None, // J2_endloop0 = 324
25216 CEFBS_None, // J2_endloop01 = 325
25217 CEFBS_None, // J2_endloop1 = 326
25218 CEFBS_HasV60, // J2_jumpf_nopred_map = 327
25219 CEFBS_HasV60, // J2_jumprf_nopred_map = 328
25220 CEFBS_HasV60, // J2_jumprt_nopred_map = 329
25221 CEFBS_HasV60, // J2_jumpt_nopred_map = 330
25222 CEFBS_HasV65, // J2_trap1_noregmap = 331
25223 CEFBS_None, // L2_loadalignb_zomap = 332
25224 CEFBS_None, // L2_loadalignh_zomap = 333
25225 CEFBS_None, // L2_loadbsw2_zomap = 334
25226 CEFBS_None, // L2_loadbsw4_zomap = 335
25227 CEFBS_None, // L2_loadbzw2_zomap = 336
25228 CEFBS_None, // L2_loadbzw4_zomap = 337
25229 CEFBS_None, // L2_loadrb_zomap = 338
25230 CEFBS_None, // L2_loadrd_zomap = 339
25231 CEFBS_None, // L2_loadrh_zomap = 340
25232 CEFBS_None, // L2_loadri_zomap = 341
25233 CEFBS_None, // L2_loadrub_zomap = 342
25234 CEFBS_None, // L2_loadruh_zomap = 343
25235 CEFBS_None, // L2_ploadrbf_zomap = 344
25236 CEFBS_None, // L2_ploadrbfnew_zomap = 345
25237 CEFBS_None, // L2_ploadrbt_zomap = 346
25238 CEFBS_None, // L2_ploadrbtnew_zomap = 347
25239 CEFBS_None, // L2_ploadrdf_zomap = 348
25240 CEFBS_None, // L2_ploadrdfnew_zomap = 349
25241 CEFBS_None, // L2_ploadrdt_zomap = 350
25242 CEFBS_None, // L2_ploadrdtnew_zomap = 351
25243 CEFBS_None, // L2_ploadrhf_zomap = 352
25244 CEFBS_None, // L2_ploadrhfnew_zomap = 353
25245 CEFBS_None, // L2_ploadrht_zomap = 354
25246 CEFBS_None, // L2_ploadrhtnew_zomap = 355
25247 CEFBS_None, // L2_ploadrif_zomap = 356
25248 CEFBS_None, // L2_ploadrifnew_zomap = 357
25249 CEFBS_None, // L2_ploadrit_zomap = 358
25250 CEFBS_None, // L2_ploadritnew_zomap = 359
25251 CEFBS_None, // L2_ploadrubf_zomap = 360
25252 CEFBS_None, // L2_ploadrubfnew_zomap = 361
25253 CEFBS_None, // L2_ploadrubt_zomap = 362
25254 CEFBS_None, // L2_ploadrubtnew_zomap = 363
25255 CEFBS_None, // L2_ploadruhf_zomap = 364
25256 CEFBS_None, // L2_ploadruhfnew_zomap = 365
25257 CEFBS_None, // L2_ploadruht_zomap = 366
25258 CEFBS_None, // L2_ploadruhtnew_zomap = 367
25259 CEFBS_None, // L4_add_memopb_zomap = 368
25260 CEFBS_None, // L4_add_memoph_zomap = 369
25261 CEFBS_None, // L4_add_memopw_zomap = 370
25262 CEFBS_None, // L4_and_memopb_zomap = 371
25263 CEFBS_None, // L4_and_memoph_zomap = 372
25264 CEFBS_None, // L4_and_memopw_zomap = 373
25265 CEFBS_None, // L4_iadd_memopb_zomap = 374
25266 CEFBS_None, // L4_iadd_memoph_zomap = 375
25267 CEFBS_None, // L4_iadd_memopw_zomap = 376
25268 CEFBS_None, // L4_iand_memopb_zomap = 377
25269 CEFBS_None, // L4_iand_memoph_zomap = 378
25270 CEFBS_None, // L4_iand_memopw_zomap = 379
25271 CEFBS_None, // L4_ior_memopb_zomap = 380
25272 CEFBS_None, // L4_ior_memoph_zomap = 381
25273 CEFBS_None, // L4_ior_memopw_zomap = 382
25274 CEFBS_None, // L4_isub_memopb_zomap = 383
25275 CEFBS_None, // L4_isub_memoph_zomap = 384
25276 CEFBS_None, // L4_isub_memopw_zomap = 385
25277 CEFBS_None, // L4_or_memopb_zomap = 386
25278 CEFBS_None, // L4_or_memoph_zomap = 387
25279 CEFBS_None, // L4_or_memopw_zomap = 388
25280 CEFBS_HasV65, // L4_return_map_to_raw_f = 389
25281 CEFBS_HasV65, // L4_return_map_to_raw_fnew_pnt = 390
25282 CEFBS_HasV65, // L4_return_map_to_raw_fnew_pt = 391
25283 CEFBS_HasV65, // L4_return_map_to_raw_t = 392
25284 CEFBS_HasV65, // L4_return_map_to_raw_tnew_pnt = 393
25285 CEFBS_HasV65, // L4_return_map_to_raw_tnew_pt = 394
25286 CEFBS_None, // L4_sub_memopb_zomap = 395
25287 CEFBS_None, // L4_sub_memoph_zomap = 396
25288 CEFBS_None, // L4_sub_memopw_zomap = 397
25289 CEFBS_HasV65, // L6_deallocframe_map_to_raw = 398
25290 CEFBS_HasV65, // L6_return_map_to_raw = 399
25291 CEFBS_None, // LDriw_ctr = 400
25292 CEFBS_None, // LDriw_pred = 401
25293 CEFBS_None, // M2_mpysmi = 402
25294 CEFBS_None, // M2_mpyui = 403
25295 CEFBS_None, // M2_vrcmpys_acc_s1 = 404
25296 CEFBS_None, // M2_vrcmpys_s1 = 405
25297 CEFBS_None, // M2_vrcmpys_s1rp = 406
25298 CEFBS_HasV67, // M7_vdmpy = 407
25299 CEFBS_HasV67, // M7_vdmpy_acc = 408
25300 CEFBS_None, // PS_aligna = 409
25301 CEFBS_None, // PS_alloca = 410
25302 CEFBS_None, // PS_call_instrprof_custom = 411
25303 CEFBS_None, // PS_call_nr = 412
25304 CEFBS_None, // PS_crash = 413
25305 CEFBS_None, // PS_false = 414
25306 CEFBS_None, // PS_fi = 415
25307 CEFBS_None, // PS_fia = 416
25308 CEFBS_None, // PS_loadrb_pci = 417
25309 CEFBS_None, // PS_loadrb_pcr = 418
25310 CEFBS_None, // PS_loadrd_pci = 419
25311 CEFBS_None, // PS_loadrd_pcr = 420
25312 CEFBS_None, // PS_loadrh_pci = 421
25313 CEFBS_None, // PS_loadrh_pcr = 422
25314 CEFBS_None, // PS_loadri_pci = 423
25315 CEFBS_None, // PS_loadri_pcr = 424
25316 CEFBS_None, // PS_loadrub_pci = 425
25317 CEFBS_None, // PS_loadrub_pcr = 426
25318 CEFBS_None, // PS_loadruh_pci = 427
25319 CEFBS_None, // PS_loadruh_pcr = 428
25320 CEFBS_None, // PS_pselect = 429
25321 CEFBS_None, // PS_qfalse = 430
25322 CEFBS_None, // PS_qtrue = 431
25323 CEFBS_None, // PS_storerb_pci = 432
25324 CEFBS_None, // PS_storerb_pcr = 433
25325 CEFBS_None, // PS_storerd_pci = 434
25326 CEFBS_None, // PS_storerd_pcr = 435
25327 CEFBS_None, // PS_storerf_pci = 436
25328 CEFBS_None, // PS_storerf_pcr = 437
25329 CEFBS_None, // PS_storerh_pci = 438
25330 CEFBS_None, // PS_storerh_pcr = 439
25331 CEFBS_None, // PS_storeri_pci = 440
25332 CEFBS_None, // PS_storeri_pcr = 441
25333 CEFBS_None, // PS_tailcall_i = 442
25334 CEFBS_None, // PS_tailcall_r = 443
25335 CEFBS_None, // PS_true = 444
25336 CEFBS_None, // PS_vdd0 = 445
25337 CEFBS_HasV60_UseHVX, // PS_vloadrq_ai = 446
25338 CEFBS_HasV60_UseHVX, // PS_vloadrv_ai = 447
25339 CEFBS_HasV60_UseHVX, // PS_vloadrv_nt_ai = 448
25340 CEFBS_HasV60_UseHVX, // PS_vloadrw_ai = 449
25341 CEFBS_HasV60_UseHVX, // PS_vloadrw_nt_ai = 450
25342 CEFBS_None, // PS_vmulw = 451
25343 CEFBS_None, // PS_vmulw_acc = 452
25344 CEFBS_HasV60_UseHVX, // PS_vselect = 453
25345 CEFBS_UseHVX, // PS_vsplatib = 454
25346 CEFBS_UseHVX, // PS_vsplatih = 455
25347 CEFBS_UseHVX, // PS_vsplatiw = 456
25348 CEFBS_UseHVX, // PS_vsplatrb = 457
25349 CEFBS_UseHVX, // PS_vsplatrh = 458
25350 CEFBS_UseHVX, // PS_vsplatrw = 459
25351 CEFBS_HasV60_UseHVX, // PS_vstorerq_ai = 460
25352 CEFBS_HasV60_UseHVX, // PS_vstorerv_ai = 461
25353 CEFBS_HasV60_UseHVX, // PS_vstorerv_nt_ai = 462
25354 CEFBS_HasV60_UseHVX, // PS_vstorerw_ai = 463
25355 CEFBS_HasV60_UseHVX, // PS_vstorerw_nt_ai = 464
25356 CEFBS_HasV60_UseHVX, // PS_wselect = 465
25357 CEFBS_None, // S2_asr_i_p_rnd_goodsyntax = 466
25358 CEFBS_None, // S2_asr_i_r_rnd_goodsyntax = 467
25359 CEFBS_None, // S2_pstorerbf_zomap = 468
25360 CEFBS_None, // S2_pstorerbnewf_zomap = 469
25361 CEFBS_None, // S2_pstorerbnewt_zomap = 470
25362 CEFBS_None, // S2_pstorerbt_zomap = 471
25363 CEFBS_None, // S2_pstorerdf_zomap = 472
25364 CEFBS_None, // S2_pstorerdt_zomap = 473
25365 CEFBS_None, // S2_pstorerff_zomap = 474
25366 CEFBS_None, // S2_pstorerft_zomap = 475
25367 CEFBS_None, // S2_pstorerhf_zomap = 476
25368 CEFBS_None, // S2_pstorerhnewf_zomap = 477
25369 CEFBS_None, // S2_pstorerhnewt_zomap = 478
25370 CEFBS_None, // S2_pstorerht_zomap = 479
25371 CEFBS_None, // S2_pstorerif_zomap = 480
25372 CEFBS_None, // S2_pstorerinewf_zomap = 481
25373 CEFBS_None, // S2_pstorerinewt_zomap = 482
25374 CEFBS_None, // S2_pstorerit_zomap = 483
25375 CEFBS_None, // S2_storerb_zomap = 484
25376 CEFBS_None, // S2_storerbnew_zomap = 485
25377 CEFBS_None, // S2_storerd_zomap = 486
25378 CEFBS_None, // S2_storerf_zomap = 487
25379 CEFBS_None, // S2_storerh_zomap = 488
25380 CEFBS_None, // S2_storerhnew_zomap = 489
25381 CEFBS_None, // S2_storeri_zomap = 490
25382 CEFBS_None, // S2_storerinew_zomap = 491
25383 CEFBS_None, // S2_tableidxb_goodsyntax = 492
25384 CEFBS_None, // S2_tableidxd_goodsyntax = 493
25385 CEFBS_None, // S2_tableidxh_goodsyntax = 494
25386 CEFBS_None, // S2_tableidxw_goodsyntax = 495
25387 CEFBS_None, // S4_pstorerbfnew_zomap = 496
25388 CEFBS_None, // S4_pstorerbnewfnew_zomap = 497
25389 CEFBS_None, // S4_pstorerbnewtnew_zomap = 498
25390 CEFBS_None, // S4_pstorerbtnew_zomap = 499
25391 CEFBS_None, // S4_pstorerdfnew_zomap = 500
25392 CEFBS_None, // S4_pstorerdtnew_zomap = 501
25393 CEFBS_None, // S4_pstorerffnew_zomap = 502
25394 CEFBS_None, // S4_pstorerftnew_zomap = 503
25395 CEFBS_None, // S4_pstorerhfnew_zomap = 504
25396 CEFBS_None, // S4_pstorerhnewfnew_zomap = 505
25397 CEFBS_None, // S4_pstorerhnewtnew_zomap = 506
25398 CEFBS_None, // S4_pstorerhtnew_zomap = 507
25399 CEFBS_None, // S4_pstorerifnew_zomap = 508
25400 CEFBS_None, // S4_pstorerinewfnew_zomap = 509
25401 CEFBS_None, // S4_pstorerinewtnew_zomap = 510
25402 CEFBS_None, // S4_pstoreritnew_zomap = 511
25403 CEFBS_None, // S4_storeirb_zomap = 512
25404 CEFBS_None, // S4_storeirbf_zomap = 513
25405 CEFBS_None, // S4_storeirbfnew_zomap = 514
25406 CEFBS_None, // S4_storeirbt_zomap = 515
25407 CEFBS_None, // S4_storeirbtnew_zomap = 516
25408 CEFBS_None, // S4_storeirh_zomap = 517
25409 CEFBS_None, // S4_storeirhf_zomap = 518
25410 CEFBS_None, // S4_storeirhfnew_zomap = 519
25411 CEFBS_None, // S4_storeirht_zomap = 520
25412 CEFBS_None, // S4_storeirhtnew_zomap = 521
25413 CEFBS_None, // S4_storeiri_zomap = 522
25414 CEFBS_None, // S4_storeirif_zomap = 523
25415 CEFBS_None, // S4_storeirifnew_zomap = 524
25416 CEFBS_None, // S4_storeirit_zomap = 525
25417 CEFBS_None, // S4_storeiritnew_zomap = 526
25418 CEFBS_None, // S5_asrhub_rnd_sat_goodsyntax = 527
25419 CEFBS_None, // S5_vasrhrnd_goodsyntax = 528
25420 CEFBS_HasV65, // S6_allocframe_to_raw = 529
25421 CEFBS_None, // STriw_ctr = 530
25422 CEFBS_None, // STriw_pred = 531
25423 CEFBS_UseHVXV60, // V6_MAP_equb = 532
25424 CEFBS_UseHVXV60, // V6_MAP_equb_and = 533
25425 CEFBS_UseHVXV60, // V6_MAP_equb_ior = 534
25426 CEFBS_UseHVXV60, // V6_MAP_equb_xor = 535
25427 CEFBS_UseHVXV60, // V6_MAP_equh = 536
25428 CEFBS_UseHVXV60, // V6_MAP_equh_and = 537
25429 CEFBS_UseHVXV60, // V6_MAP_equh_ior = 538
25430 CEFBS_UseHVXV60, // V6_MAP_equh_xor = 539
25431 CEFBS_UseHVXV60, // V6_MAP_equw = 540
25432 CEFBS_UseHVXV60, // V6_MAP_equw_and = 541
25433 CEFBS_UseHVXV60, // V6_MAP_equw_ior = 542
25434 CEFBS_UseHVXV60, // V6_MAP_equw_xor = 543
25435 CEFBS_UseHVXV73, // V6_dbl_ld0 = 544
25436 CEFBS_UseHVXV73, // V6_dbl_st0 = 545
25437 CEFBS_UseHVXV60, // V6_extractw_alt = 546
25438 CEFBS_UseHVXV60, // V6_hi = 547
25439 CEFBS_UseHVXV60, // V6_ld0 = 548
25440 CEFBS_UseHVXV62, // V6_ldcnp0 = 549
25441 CEFBS_UseHVXV62, // V6_ldcnpnt0 = 550
25442 CEFBS_UseHVXV62, // V6_ldcp0 = 551
25443 CEFBS_UseHVXV62, // V6_ldcpnt0 = 552
25444 CEFBS_UseHVXV62, // V6_ldnp0 = 553
25445 CEFBS_UseHVXV62, // V6_ldnpnt0 = 554
25446 CEFBS_UseHVXV60, // V6_ldnt0 = 555
25447 CEFBS_UseHVXV62, // V6_ldp0 = 556
25448 CEFBS_UseHVXV62, // V6_ldpnt0 = 557
25449 CEFBS_UseHVXV62, // V6_ldtnp0 = 558
25450 CEFBS_UseHVXV62, // V6_ldtnpnt0 = 559
25451 CEFBS_UseHVXV62, // V6_ldtp0 = 560
25452 CEFBS_UseHVXV62, // V6_ldtpnt0 = 561
25453 CEFBS_UseHVXV60, // V6_ldu0 = 562
25454 CEFBS_UseHVXV60, // V6_lo = 563
25455 CEFBS_UseHVXV60, // V6_st0 = 564
25456 CEFBS_UseHVXV60, // V6_stn0 = 565
25457 CEFBS_UseHVXV60, // V6_stnnt0 = 566
25458 CEFBS_UseHVXV60, // V6_stnp0 = 567
25459 CEFBS_UseHVXV60, // V6_stnpnt0 = 568
25460 CEFBS_UseHVXV60, // V6_stnq0 = 569
25461 CEFBS_UseHVXV60, // V6_stnqnt0 = 570
25462 CEFBS_UseHVXV60, // V6_stnt0 = 571
25463 CEFBS_UseHVXV60, // V6_stp0 = 572
25464 CEFBS_UseHVXV60, // V6_stpnt0 = 573
25465 CEFBS_UseHVXV60, // V6_stq0 = 574
25466 CEFBS_UseHVXV60, // V6_stqnt0 = 575
25467 CEFBS_UseHVXV60, // V6_stu0 = 576
25468 CEFBS_UseHVXV60, // V6_stunp0 = 577
25469 CEFBS_UseHVXV60, // V6_stup0 = 578
25470 CEFBS_UseHVXV69, // V6_v10mpyubs10 = 579
25471 CEFBS_UseHVXV69, // V6_v10mpyubs10_vxx = 580
25472 CEFBS_UseHVXV68, // V6_v6mpyhubs10_alt = 581
25473 CEFBS_UseHVXV68, // V6_v6mpyvubs10_alt = 582
25474 CEFBS_UseHVXV65, // V6_vabsb_alt = 583
25475 CEFBS_UseHVXV65, // V6_vabsb_sat_alt = 584
25476 CEFBS_UseHVXV60, // V6_vabsdiffh_alt = 585
25477 CEFBS_UseHVXV60, // V6_vabsdiffub_alt = 586
25478 CEFBS_UseHVXV60, // V6_vabsdiffuh_alt = 587
25479 CEFBS_UseHVXV60, // V6_vabsdiffw_alt = 588
25480 CEFBS_UseHVXV60, // V6_vabsh_alt = 589
25481 CEFBS_UseHVXV60, // V6_vabsh_sat_alt = 590
25482 CEFBS_UseHVXV65, // V6_vabsub_alt = 591
25483 CEFBS_UseHVXV65, // V6_vabsuh_alt = 592
25484 CEFBS_UseHVXV65, // V6_vabsuw_alt = 593
25485 CEFBS_UseHVXV60, // V6_vabsw_alt = 594
25486 CEFBS_UseHVXV60, // V6_vabsw_sat_alt = 595
25487 CEFBS_UseHVXV60, // V6_vaddb_alt = 596
25488 CEFBS_UseHVXV60, // V6_vaddb_dv_alt = 597
25489 CEFBS_UseHVXV60, // V6_vaddbnq_alt = 598
25490 CEFBS_UseHVXV60, // V6_vaddbq_alt = 599
25491 CEFBS_UseHVXV62, // V6_vaddbsat_alt = 600
25492 CEFBS_UseHVXV62, // V6_vaddbsat_dv_alt = 601
25493 CEFBS_UseHVXV60, // V6_vaddh_alt = 602
25494 CEFBS_UseHVXV60, // V6_vaddh_dv_alt = 603
25495 CEFBS_UseHVXV60, // V6_vaddhnq_alt = 604
25496 CEFBS_UseHVXV60, // V6_vaddhq_alt = 605
25497 CEFBS_UseHVXV60, // V6_vaddhsat_alt = 606
25498 CEFBS_UseHVXV60, // V6_vaddhsat_dv_alt = 607
25499 CEFBS_UseHVXV62, // V6_vaddhw_acc_alt = 608
25500 CEFBS_UseHVXV60, // V6_vaddhw_alt = 609
25501 CEFBS_UseHVXV62, // V6_vaddubh_acc_alt = 610
25502 CEFBS_UseHVXV60, // V6_vaddubh_alt = 611
25503 CEFBS_UseHVXV60, // V6_vaddubsat_alt = 612
25504 CEFBS_UseHVXV60, // V6_vaddubsat_dv_alt = 613
25505 CEFBS_UseHVXV60, // V6_vadduhsat_alt = 614
25506 CEFBS_UseHVXV60, // V6_vadduhsat_dv_alt = 615
25507 CEFBS_UseHVXV62, // V6_vadduhw_acc_alt = 616
25508 CEFBS_UseHVXV60, // V6_vadduhw_alt = 617
25509 CEFBS_UseHVXV62, // V6_vadduwsat_alt = 618
25510 CEFBS_UseHVXV62, // V6_vadduwsat_dv_alt = 619
25511 CEFBS_UseHVXV60, // V6_vaddw_alt = 620
25512 CEFBS_UseHVXV60, // V6_vaddw_dv_alt = 621
25513 CEFBS_UseHVXV60, // V6_vaddwnq_alt = 622
25514 CEFBS_UseHVXV60, // V6_vaddwq_alt = 623
25515 CEFBS_UseHVXV60, // V6_vaddwsat_alt = 624
25516 CEFBS_UseHVXV60, // V6_vaddwsat_dv_alt = 625
25517 CEFBS_UseHVXV62, // V6_vandnqrt_acc_alt = 626
25518 CEFBS_UseHVXV62, // V6_vandnqrt_alt = 627
25519 CEFBS_UseHVXV60, // V6_vandqrt_acc_alt = 628
25520 CEFBS_UseHVXV60, // V6_vandqrt_alt = 629
25521 CEFBS_UseHVXV60, // V6_vandvrt_acc_alt = 630
25522 CEFBS_UseHVXV60, // V6_vandvrt_alt = 631
25523 CEFBS_UseHVXV65, // V6_vaslh_acc_alt = 632
25524 CEFBS_UseHVXV60, // V6_vaslh_alt = 633
25525 CEFBS_UseHVXV60, // V6_vaslhv_alt = 634
25526 CEFBS_UseHVXV60, // V6_vaslw_acc_alt = 635
25527 CEFBS_UseHVXV60, // V6_vaslw_alt = 636
25528 CEFBS_UseHVXV60, // V6_vaslwv_alt = 637
25529 CEFBS_UseHVXV66, // V6_vasr_into_alt = 638
25530 CEFBS_UseHVXV65, // V6_vasrh_acc_alt = 639
25531 CEFBS_UseHVXV60, // V6_vasrh_alt = 640
25532 CEFBS_UseHVXV60, // V6_vasrhv_alt = 641
25533 CEFBS_UseHVXV60, // V6_vasrw_acc_alt = 642
25534 CEFBS_UseHVXV60, // V6_vasrw_alt = 643
25535 CEFBS_UseHVXV60, // V6_vasrwv_alt = 644
25536 CEFBS_UseHVXV60, // V6_vassignp = 645
25537 CEFBS_UseHVXV65, // V6_vavgb_alt = 646
25538 CEFBS_UseHVXV65, // V6_vavgbrnd_alt = 647
25539 CEFBS_UseHVXV60, // V6_vavgh_alt = 648
25540 CEFBS_UseHVXV60, // V6_vavghrnd_alt = 649
25541 CEFBS_UseHVXV60, // V6_vavgub_alt = 650
25542 CEFBS_UseHVXV60, // V6_vavgubrnd_alt = 651
25543 CEFBS_UseHVXV60, // V6_vavguh_alt = 652
25544 CEFBS_UseHVXV60, // V6_vavguhrnd_alt = 653
25545 CEFBS_UseHVXV65, // V6_vavguw_alt = 654
25546 CEFBS_UseHVXV65, // V6_vavguwrnd_alt = 655
25547 CEFBS_UseHVXV60, // V6_vavgw_alt = 656
25548 CEFBS_UseHVXV60, // V6_vavgwrnd_alt = 657
25549 CEFBS_UseHVXV60, // V6_vcl0h_alt = 658
25550 CEFBS_UseHVXV60, // V6_vcl0w_alt = 659
25551 CEFBS_UseHVXV60, // V6_vd0 = 660
25552 CEFBS_UseHVXV65, // V6_vdd0 = 661
25553 CEFBS_UseHVXV60, // V6_vdealb4w_alt = 662
25554 CEFBS_UseHVXV60, // V6_vdealb_alt = 663
25555 CEFBS_UseHVXV60, // V6_vdealh_alt = 664
25556 CEFBS_UseHVXV60, // V6_vdmpybus_acc_alt = 665
25557 CEFBS_UseHVXV60, // V6_vdmpybus_alt = 666
25558 CEFBS_UseHVXV60, // V6_vdmpybus_dv_acc_alt = 667
25559 CEFBS_UseHVXV60, // V6_vdmpybus_dv_alt = 668
25560 CEFBS_UseHVXV60, // V6_vdmpyhb_acc_alt = 669
25561 CEFBS_UseHVXV60, // V6_vdmpyhb_alt = 670
25562 CEFBS_UseHVXV60, // V6_vdmpyhb_dv_acc_alt = 671
25563 CEFBS_UseHVXV60, // V6_vdmpyhb_dv_alt = 672
25564 CEFBS_UseHVXV60, // V6_vdmpyhisat_acc_alt = 673
25565 CEFBS_UseHVXV60, // V6_vdmpyhisat_alt = 674
25566 CEFBS_UseHVXV60, // V6_vdmpyhsat_acc_alt = 675
25567 CEFBS_UseHVXV60, // V6_vdmpyhsat_alt = 676
25568 CEFBS_UseHVXV60, // V6_vdmpyhsuisat_acc_alt = 677
25569 CEFBS_UseHVXV60, // V6_vdmpyhsuisat_alt = 678
25570 CEFBS_UseHVXV60, // V6_vdmpyhsusat_acc_alt = 679
25571 CEFBS_UseHVXV60, // V6_vdmpyhsusat_alt = 680
25572 CEFBS_UseHVXV60, // V6_vdmpyhvsat_acc_alt = 681
25573 CEFBS_UseHVXV60, // V6_vdmpyhvsat_alt = 682
25574 CEFBS_UseHVXV60, // V6_vdsaduh_acc_alt = 683
25575 CEFBS_UseHVXV60, // V6_vdsaduh_alt = 684
25576 CEFBS_None, // V6_vgathermh_pseudo = 685
25577 CEFBS_None, // V6_vgathermhq_pseudo = 686
25578 CEFBS_None, // V6_vgathermhw_pseudo = 687
25579 CEFBS_None, // V6_vgathermhwq_pseudo = 688
25580 CEFBS_None, // V6_vgathermw_pseudo = 689
25581 CEFBS_None, // V6_vgathermwq_pseudo = 690
25582 CEFBS_UseHVXV60, // V6_vlsrh_alt = 691
25583 CEFBS_UseHVXV60, // V6_vlsrhv_alt = 692
25584 CEFBS_UseHVXV60, // V6_vlsrw_alt = 693
25585 CEFBS_UseHVXV60, // V6_vlsrwv_alt = 694
25586 CEFBS_UseHVXV62, // V6_vmaxb_alt = 695
25587 CEFBS_UseHVXV60, // V6_vmaxh_alt = 696
25588 CEFBS_UseHVXV60, // V6_vmaxub_alt = 697
25589 CEFBS_UseHVXV60, // V6_vmaxuh_alt = 698
25590 CEFBS_UseHVXV60, // V6_vmaxw_alt = 699
25591 CEFBS_UseHVXV62, // V6_vminb_alt = 700
25592 CEFBS_UseHVXV60, // V6_vminh_alt = 701
25593 CEFBS_UseHVXV60, // V6_vminub_alt = 702
25594 CEFBS_UseHVXV60, // V6_vminuh_alt = 703
25595 CEFBS_UseHVXV60, // V6_vminw_alt = 704
25596 CEFBS_UseHVXV60, // V6_vmpabus_acc_alt = 705
25597 CEFBS_UseHVXV60, // V6_vmpabus_alt = 706
25598 CEFBS_UseHVXV60, // V6_vmpabusv_alt = 707
25599 CEFBS_UseHVXV65, // V6_vmpabuu_acc_alt = 708
25600 CEFBS_UseHVXV65, // V6_vmpabuu_alt = 709
25601 CEFBS_UseHVXV60, // V6_vmpabuuv_alt = 710
25602 CEFBS_UseHVXV60, // V6_vmpahb_acc_alt = 711
25603 CEFBS_UseHVXV60, // V6_vmpahb_alt = 712
25604 CEFBS_UseHVXV62, // V6_vmpauhb_acc_alt = 713
25605 CEFBS_UseHVXV62, // V6_vmpauhb_alt = 714
25606 CEFBS_UseHVXV60, // V6_vmpybus_acc_alt = 715
25607 CEFBS_UseHVXV60, // V6_vmpybus_alt = 716
25608 CEFBS_UseHVXV60, // V6_vmpybusv_acc_alt = 717
25609 CEFBS_UseHVXV60, // V6_vmpybusv_alt = 718
25610 CEFBS_UseHVXV60, // V6_vmpybv_acc_alt = 719
25611 CEFBS_UseHVXV60, // V6_vmpybv_alt = 720
25612 CEFBS_UseHVXV60, // V6_vmpyewuh_alt = 721
25613 CEFBS_UseHVXV65, // V6_vmpyh_acc_alt = 722
25614 CEFBS_UseHVXV60, // V6_vmpyh_alt = 723
25615 CEFBS_UseHVXV60, // V6_vmpyhsat_acc_alt = 724
25616 CEFBS_UseHVXV60, // V6_vmpyhsrs_alt = 725
25617 CEFBS_UseHVXV60, // V6_vmpyhss_alt = 726
25618 CEFBS_UseHVXV60, // V6_vmpyhus_acc_alt = 727
25619 CEFBS_UseHVXV60, // V6_vmpyhus_alt = 728
25620 CEFBS_UseHVXV60, // V6_vmpyhv_acc_alt = 729
25621 CEFBS_UseHVXV60, // V6_vmpyhv_alt = 730
25622 CEFBS_UseHVXV60, // V6_vmpyhvsrs_alt = 731
25623 CEFBS_UseHVXV60, // V6_vmpyiewh_acc_alt = 732
25624 CEFBS_UseHVXV60, // V6_vmpyiewuh_acc_alt = 733
25625 CEFBS_UseHVXV60, // V6_vmpyiewuh_alt = 734
25626 CEFBS_UseHVXV60, // V6_vmpyih_acc_alt = 735
25627 CEFBS_UseHVXV60, // V6_vmpyih_alt = 736
25628 CEFBS_UseHVXV60, // V6_vmpyihb_acc_alt = 737
25629 CEFBS_UseHVXV60, // V6_vmpyihb_alt = 738
25630 CEFBS_UseHVXV60, // V6_vmpyiowh_alt = 739
25631 CEFBS_UseHVXV60, // V6_vmpyiwb_acc_alt = 740
25632 CEFBS_UseHVXV60, // V6_vmpyiwb_alt = 741
25633 CEFBS_UseHVXV60, // V6_vmpyiwh_acc_alt = 742
25634 CEFBS_UseHVXV60, // V6_vmpyiwh_alt = 743
25635 CEFBS_UseHVXV62, // V6_vmpyiwub_acc_alt = 744
25636 CEFBS_UseHVXV62, // V6_vmpyiwub_alt = 745
25637 CEFBS_UseHVXV60, // V6_vmpyowh_alt = 746
25638 CEFBS_UseHVXV60, // V6_vmpyowh_rnd_alt = 747
25639 CEFBS_UseHVXV60, // V6_vmpyowh_rnd_sacc_alt = 748
25640 CEFBS_UseHVXV60, // V6_vmpyowh_sacc_alt = 749
25641 CEFBS_UseHVXV60, // V6_vmpyub_acc_alt = 750
25642 CEFBS_UseHVXV60, // V6_vmpyub_alt = 751
25643 CEFBS_UseHVXV60, // V6_vmpyubv_acc_alt = 752
25644 CEFBS_UseHVXV60, // V6_vmpyubv_alt = 753
25645 CEFBS_UseHVXV60, // V6_vmpyuh_acc_alt = 754
25646 CEFBS_UseHVXV60, // V6_vmpyuh_alt = 755
25647 CEFBS_UseHVXV60, // V6_vmpyuhv_acc_alt = 756
25648 CEFBS_UseHVXV60, // V6_vmpyuhv_alt = 757
25649 CEFBS_UseHVXV65, // V6_vnavgb_alt = 758
25650 CEFBS_UseHVXV60, // V6_vnavgh_alt = 759
25651 CEFBS_UseHVXV60, // V6_vnavgub_alt = 760
25652 CEFBS_UseHVXV60, // V6_vnavgw_alt = 761
25653 CEFBS_UseHVXV60, // V6_vnormamth_alt = 762
25654 CEFBS_UseHVXV60, // V6_vnormamtw_alt = 763
25655 CEFBS_UseHVXV60, // V6_vpackeb_alt = 764
25656 CEFBS_UseHVXV60, // V6_vpackeh_alt = 765
25657 CEFBS_UseHVXV60, // V6_vpackhb_sat_alt = 766
25658 CEFBS_UseHVXV60, // V6_vpackhub_sat_alt = 767
25659 CEFBS_UseHVXV60, // V6_vpackob_alt = 768
25660 CEFBS_UseHVXV60, // V6_vpackoh_alt = 769
25661 CEFBS_UseHVXV60, // V6_vpackwh_sat_alt = 770
25662 CEFBS_UseHVXV60, // V6_vpackwuh_sat_alt = 771
25663 CEFBS_UseHVXV60, // V6_vpopcounth_alt = 772
25664 CEFBS_UseHVXV65, // V6_vrmpybub_rtt_acc_alt = 773
25665 CEFBS_UseHVXV65, // V6_vrmpybub_rtt_alt = 774
25666 CEFBS_UseHVXV60, // V6_vrmpybus_acc_alt = 775
25667 CEFBS_UseHVXV60, // V6_vrmpybus_alt = 776
25668 CEFBS_UseHVXV60, // V6_vrmpybusi_acc_alt = 777
25669 CEFBS_UseHVXV60, // V6_vrmpybusi_alt = 778
25670 CEFBS_UseHVXV60, // V6_vrmpybusv_acc_alt = 779
25671 CEFBS_UseHVXV60, // V6_vrmpybusv_alt = 780
25672 CEFBS_UseHVXV60, // V6_vrmpybv_acc_alt = 781
25673 CEFBS_UseHVXV60, // V6_vrmpybv_alt = 782
25674 CEFBS_UseHVXV60, // V6_vrmpyub_acc_alt = 783
25675 CEFBS_UseHVXV60, // V6_vrmpyub_alt = 784
25676 CEFBS_UseHVXV65, // V6_vrmpyub_rtt_acc_alt = 785
25677 CEFBS_UseHVXV65, // V6_vrmpyub_rtt_alt = 786
25678 CEFBS_UseHVXV60, // V6_vrmpyubi_acc_alt = 787
25679 CEFBS_UseHVXV60, // V6_vrmpyubi_alt = 788
25680 CEFBS_UseHVXV60, // V6_vrmpyubv_acc_alt = 789
25681 CEFBS_UseHVXV60, // V6_vrmpyubv_alt = 790
25682 CEFBS_UseHVXV66, // V6_vrotr_alt = 791
25683 CEFBS_UseHVXV60, // V6_vroundhb_alt = 792
25684 CEFBS_UseHVXV60, // V6_vroundhub_alt = 793
25685 CEFBS_UseHVXV62, // V6_vrounduhub_alt = 794
25686 CEFBS_UseHVXV62, // V6_vrounduwuh_alt = 795
25687 CEFBS_UseHVXV60, // V6_vroundwh_alt = 796
25688 CEFBS_UseHVXV60, // V6_vroundwuh_alt = 797
25689 CEFBS_UseHVXV60, // V6_vrsadubi_acc_alt = 798
25690 CEFBS_UseHVXV60, // V6_vrsadubi_alt = 799
25691 CEFBS_UseHVXV60, // V6_vsathub_alt = 800
25692 CEFBS_UseHVXV62, // V6_vsatuwuh_alt = 801
25693 CEFBS_UseHVXV60, // V6_vsatwh_alt = 802
25694 CEFBS_UseHVXV60, // V6_vsb_alt = 803
25695 CEFBS_UseHVXV65, // V6_vscattermh_add_alt = 804
25696 CEFBS_UseHVXV65, // V6_vscattermh_alt = 805
25697 CEFBS_UseHVXV65, // V6_vscattermhq_alt = 806
25698 CEFBS_UseHVXV65, // V6_vscattermw_add_alt = 807
25699 CEFBS_UseHVXV65, // V6_vscattermw_alt = 808
25700 CEFBS_UseHVXV65, // V6_vscattermwh_add_alt = 809
25701 CEFBS_UseHVXV65, // V6_vscattermwh_alt = 810
25702 CEFBS_UseHVXV65, // V6_vscattermwhq_alt = 811
25703 CEFBS_UseHVXV65, // V6_vscattermwq_alt = 812
25704 CEFBS_UseHVXV60, // V6_vsh_alt = 813
25705 CEFBS_UseHVXV60, // V6_vshufeh_alt = 814
25706 CEFBS_UseHVXV60, // V6_vshuffb_alt = 815
25707 CEFBS_UseHVXV60, // V6_vshuffeb_alt = 816
25708 CEFBS_UseHVXV60, // V6_vshuffh_alt = 817
25709 CEFBS_UseHVXV60, // V6_vshuffob_alt = 818
25710 CEFBS_UseHVXV60, // V6_vshufoeb_alt = 819
25711 CEFBS_UseHVXV60, // V6_vshufoeh_alt = 820
25712 CEFBS_UseHVXV60, // V6_vshufoh_alt = 821
25713 CEFBS_UseHVXV60, // V6_vsubb_alt = 822
25714 CEFBS_UseHVXV60, // V6_vsubb_dv_alt = 823
25715 CEFBS_UseHVXV60, // V6_vsubbnq_alt = 824
25716 CEFBS_UseHVXV60, // V6_vsubbq_alt = 825
25717 CEFBS_UseHVXV62, // V6_vsubbsat_alt = 826
25718 CEFBS_UseHVXV62, // V6_vsubbsat_dv_alt = 827
25719 CEFBS_UseHVXV60, // V6_vsubh_alt = 828
25720 CEFBS_UseHVXV60, // V6_vsubh_dv_alt = 829
25721 CEFBS_UseHVXV60, // V6_vsubhnq_alt = 830
25722 CEFBS_UseHVXV60, // V6_vsubhq_alt = 831
25723 CEFBS_UseHVXV60, // V6_vsubhsat_alt = 832
25724 CEFBS_UseHVXV60, // V6_vsubhsat_dv_alt = 833
25725 CEFBS_UseHVXV60, // V6_vsubhw_alt = 834
25726 CEFBS_UseHVXV60, // V6_vsububh_alt = 835
25727 CEFBS_UseHVXV60, // V6_vsububsat_alt = 836
25728 CEFBS_UseHVXV60, // V6_vsububsat_dv_alt = 837
25729 CEFBS_UseHVXV60, // V6_vsubuhsat_alt = 838
25730 CEFBS_UseHVXV60, // V6_vsubuhsat_dv_alt = 839
25731 CEFBS_UseHVXV60, // V6_vsubuhw_alt = 840
25732 CEFBS_UseHVXV62, // V6_vsubuwsat_alt = 841
25733 CEFBS_UseHVXV62, // V6_vsubuwsat_dv_alt = 842
25734 CEFBS_UseHVXV60, // V6_vsubw_alt = 843
25735 CEFBS_UseHVXV60, // V6_vsubw_dv_alt = 844
25736 CEFBS_UseHVXV60, // V6_vsubwnq_alt = 845
25737 CEFBS_UseHVXV60, // V6_vsubwq_alt = 846
25738 CEFBS_UseHVXV60, // V6_vsubwsat_alt = 847
25739 CEFBS_UseHVXV60, // V6_vsubwsat_dv_alt = 848
25740 CEFBS_UseHVXV60, // V6_vtmpyb_acc_alt = 849
25741 CEFBS_UseHVXV60, // V6_vtmpyb_alt = 850
25742 CEFBS_UseHVXV60, // V6_vtmpybus_acc_alt = 851
25743 CEFBS_UseHVXV60, // V6_vtmpybus_alt = 852
25744 CEFBS_UseHVXV60, // V6_vtmpyhb_acc_alt = 853
25745 CEFBS_UseHVXV60, // V6_vtmpyhb_alt = 854
25746 CEFBS_UseHVXV60, // V6_vtran2x2_map = 855
25747 CEFBS_UseHVXV60, // V6_vunpackb_alt = 856
25748 CEFBS_UseHVXV60, // V6_vunpackh_alt = 857
25749 CEFBS_UseHVXV60, // V6_vunpackob_alt = 858
25750 CEFBS_UseHVXV60, // V6_vunpackoh_alt = 859
25751 CEFBS_UseHVXV60, // V6_vunpackub_alt = 860
25752 CEFBS_UseHVXV60, // V6_vunpackuh_alt = 861
25753 CEFBS_UseHVXV60, // V6_vzb_alt = 862
25754 CEFBS_UseHVXV60, // V6_vzh_alt = 863
25755 CEFBS_UseHVXV66, // V6_zld0 = 864
25756 CEFBS_UseHVXV66, // V6_zldp0 = 865
25757 CEFBS_None, // Y2_crswap_old = 866
25758 CEFBS_None, // Y2_dcfetch = 867
25759 CEFBS_HasV65, // Y2_k1lock_map = 868
25760 CEFBS_HasV65, // Y2_k1unlock_map = 869
25761 CEFBS_HasV73, // dup_A2_add = 870
25762 CEFBS_HasV73, // dup_A2_addi = 871
25763 CEFBS_HasV73, // dup_A2_andir = 872
25764 CEFBS_HasV73, // dup_A2_combineii = 873
25765 CEFBS_HasV73, // dup_A2_sxtb = 874
25766 CEFBS_HasV73, // dup_A2_sxth = 875
25767 CEFBS_HasV73, // dup_A2_tfr = 876
25768 CEFBS_HasV73, // dup_A2_tfrsi = 877
25769 CEFBS_HasV73, // dup_A2_zxtb = 878
25770 CEFBS_HasV73, // dup_A2_zxth = 879
25771 CEFBS_HasV73, // dup_A4_combineii = 880
25772 CEFBS_HasV73, // dup_A4_combineir = 881
25773 CEFBS_HasV73, // dup_A4_combineri = 882
25774 CEFBS_HasV73, // dup_C2_cmoveif = 883
25775 CEFBS_HasV73, // dup_C2_cmoveit = 884
25776 CEFBS_HasV73, // dup_C2_cmovenewif = 885
25777 CEFBS_HasV73, // dup_C2_cmovenewit = 886
25778 CEFBS_HasV73, // dup_C2_cmpeqi = 887
25779 CEFBS_HasV73, // dup_L2_deallocframe = 888
25780 CEFBS_HasV73, // dup_L2_loadrb_io = 889
25781 CEFBS_HasV73, // dup_L2_loadrd_io = 890
25782 CEFBS_HasV73, // dup_L2_loadrh_io = 891
25783 CEFBS_HasV73, // dup_L2_loadri_io = 892
25784 CEFBS_HasV73, // dup_L2_loadrub_io = 893
25785 CEFBS_HasV73, // dup_L2_loadruh_io = 894
25786 CEFBS_HasV73, // dup_S2_allocframe = 895
25787 CEFBS_HasV73, // dup_S2_storerb_io = 896
25788 CEFBS_HasV73, // dup_S2_storerd_io = 897
25789 CEFBS_HasV73, // dup_S2_storerh_io = 898
25790 CEFBS_HasV73, // dup_S2_storeri_io = 899
25791 CEFBS_HasV73, // dup_S4_storeirb_io = 900
25792 CEFBS_HasV73, // dup_S4_storeiri_io = 901
25793 CEFBS_None, // A2_abs = 902
25794 CEFBS_None, // A2_absp = 903
25795 CEFBS_None, // A2_abssat = 904
25796 CEFBS_None, // A2_add = 905
25797 CEFBS_None, // A2_addh_h16_hh = 906
25798 CEFBS_None, // A2_addh_h16_hl = 907
25799 CEFBS_None, // A2_addh_h16_lh = 908
25800 CEFBS_None, // A2_addh_h16_ll = 909
25801 CEFBS_None, // A2_addh_h16_sat_hh = 910
25802 CEFBS_None, // A2_addh_h16_sat_hl = 911
25803 CEFBS_None, // A2_addh_h16_sat_lh = 912
25804 CEFBS_None, // A2_addh_h16_sat_ll = 913
25805 CEFBS_None, // A2_addh_l16_hl = 914
25806 CEFBS_None, // A2_addh_l16_ll = 915
25807 CEFBS_None, // A2_addh_l16_sat_hl = 916
25808 CEFBS_None, // A2_addh_l16_sat_ll = 917
25809 CEFBS_None, // A2_addi = 918
25810 CEFBS_None, // A2_addp = 919
25811 CEFBS_None, // A2_addpsat = 920
25812 CEFBS_None, // A2_addsat = 921
25813 CEFBS_None, // A2_addsph = 922
25814 CEFBS_None, // A2_addspl = 923
25815 CEFBS_None, // A2_and = 924
25816 CEFBS_None, // A2_andir = 925
25817 CEFBS_None, // A2_andp = 926
25818 CEFBS_None, // A2_aslh = 927
25819 CEFBS_None, // A2_asrh = 928
25820 CEFBS_None, // A2_combine_hh = 929
25821 CEFBS_None, // A2_combine_hl = 930
25822 CEFBS_None, // A2_combine_lh = 931
25823 CEFBS_None, // A2_combine_ll = 932
25824 CEFBS_None, // A2_combineii = 933
25825 CEFBS_None, // A2_combinew = 934
25826 CEFBS_None, // A2_max = 935
25827 CEFBS_None, // A2_maxp = 936
25828 CEFBS_None, // A2_maxu = 937
25829 CEFBS_None, // A2_maxup = 938
25830 CEFBS_None, // A2_min = 939
25831 CEFBS_None, // A2_minp = 940
25832 CEFBS_None, // A2_minu = 941
25833 CEFBS_None, // A2_minup = 942
25834 CEFBS_None, // A2_negp = 943
25835 CEFBS_None, // A2_negsat = 944
25836 CEFBS_None, // A2_nop = 945
25837 CEFBS_None, // A2_notp = 946
25838 CEFBS_None, // A2_or = 947
25839 CEFBS_None, // A2_orir = 948
25840 CEFBS_None, // A2_orp = 949
25841 CEFBS_None, // A2_paddf = 950
25842 CEFBS_None, // A2_paddfnew = 951
25843 CEFBS_None, // A2_paddif = 952
25844 CEFBS_None, // A2_paddifnew = 953
25845 CEFBS_None, // A2_paddit = 954
25846 CEFBS_None, // A2_padditnew = 955
25847 CEFBS_None, // A2_paddt = 956
25848 CEFBS_None, // A2_paddtnew = 957
25849 CEFBS_None, // A2_pandf = 958
25850 CEFBS_None, // A2_pandfnew = 959
25851 CEFBS_None, // A2_pandt = 960
25852 CEFBS_None, // A2_pandtnew = 961
25853 CEFBS_None, // A2_porf = 962
25854 CEFBS_None, // A2_porfnew = 963
25855 CEFBS_None, // A2_port = 964
25856 CEFBS_None, // A2_portnew = 965
25857 CEFBS_None, // A2_psubf = 966
25858 CEFBS_None, // A2_psubfnew = 967
25859 CEFBS_None, // A2_psubt = 968
25860 CEFBS_None, // A2_psubtnew = 969
25861 CEFBS_None, // A2_pxorf = 970
25862 CEFBS_None, // A2_pxorfnew = 971
25863 CEFBS_None, // A2_pxort = 972
25864 CEFBS_None, // A2_pxortnew = 973
25865 CEFBS_None, // A2_roundsat = 974
25866 CEFBS_None, // A2_sat = 975
25867 CEFBS_None, // A2_satb = 976
25868 CEFBS_None, // A2_sath = 977
25869 CEFBS_None, // A2_satub = 978
25870 CEFBS_None, // A2_satuh = 979
25871 CEFBS_None, // A2_sub = 980
25872 CEFBS_None, // A2_subh_h16_hh = 981
25873 CEFBS_None, // A2_subh_h16_hl = 982
25874 CEFBS_None, // A2_subh_h16_lh = 983
25875 CEFBS_None, // A2_subh_h16_ll = 984
25876 CEFBS_None, // A2_subh_h16_sat_hh = 985
25877 CEFBS_None, // A2_subh_h16_sat_hl = 986
25878 CEFBS_None, // A2_subh_h16_sat_lh = 987
25879 CEFBS_None, // A2_subh_h16_sat_ll = 988
25880 CEFBS_None, // A2_subh_l16_hl = 989
25881 CEFBS_None, // A2_subh_l16_ll = 990
25882 CEFBS_None, // A2_subh_l16_sat_hl = 991
25883 CEFBS_None, // A2_subh_l16_sat_ll = 992
25884 CEFBS_None, // A2_subp = 993
25885 CEFBS_None, // A2_subri = 994
25886 CEFBS_None, // A2_subsat = 995
25887 CEFBS_None, // A2_svaddh = 996
25888 CEFBS_None, // A2_svaddhs = 997
25889 CEFBS_None, // A2_svadduhs = 998
25890 CEFBS_None, // A2_svavgh = 999
25891 CEFBS_None, // A2_svavghs = 1000
25892 CEFBS_None, // A2_svnavgh = 1001
25893 CEFBS_None, // A2_svsubh = 1002
25894 CEFBS_None, // A2_svsubhs = 1003
25895 CEFBS_None, // A2_svsubuhs = 1004
25896 CEFBS_None, // A2_swiz = 1005
25897 CEFBS_None, // A2_sxtb = 1006
25898 CEFBS_None, // A2_sxth = 1007
25899 CEFBS_None, // A2_sxtw = 1008
25900 CEFBS_None, // A2_tfr = 1009
25901 CEFBS_None, // A2_tfrcrr = 1010
25902 CEFBS_None, // A2_tfrih = 1011
25903 CEFBS_None, // A2_tfril = 1012
25904 CEFBS_None, // A2_tfrrcr = 1013
25905 CEFBS_None, // A2_tfrsi = 1014
25906 CEFBS_None, // A2_vabsh = 1015
25907 CEFBS_None, // A2_vabshsat = 1016
25908 CEFBS_None, // A2_vabsw = 1017
25909 CEFBS_None, // A2_vabswsat = 1018
25910 CEFBS_None, // A2_vaddh = 1019
25911 CEFBS_None, // A2_vaddhs = 1020
25912 CEFBS_None, // A2_vaddub = 1021
25913 CEFBS_None, // A2_vaddubs = 1022
25914 CEFBS_None, // A2_vadduhs = 1023
25915 CEFBS_None, // A2_vaddw = 1024
25916 CEFBS_None, // A2_vaddws = 1025
25917 CEFBS_None, // A2_vavgh = 1026
25918 CEFBS_None, // A2_vavghcr = 1027
25919 CEFBS_None, // A2_vavghr = 1028
25920 CEFBS_None, // A2_vavgub = 1029
25921 CEFBS_None, // A2_vavgubr = 1030
25922 CEFBS_None, // A2_vavguh = 1031
25923 CEFBS_None, // A2_vavguhr = 1032
25924 CEFBS_None, // A2_vavguw = 1033
25925 CEFBS_None, // A2_vavguwr = 1034
25926 CEFBS_None, // A2_vavgw = 1035
25927 CEFBS_None, // A2_vavgwcr = 1036
25928 CEFBS_None, // A2_vavgwr = 1037
25929 CEFBS_None, // A2_vcmpbeq = 1038
25930 CEFBS_None, // A2_vcmpbgtu = 1039
25931 CEFBS_None, // A2_vcmpheq = 1040
25932 CEFBS_None, // A2_vcmphgt = 1041
25933 CEFBS_None, // A2_vcmphgtu = 1042
25934 CEFBS_None, // A2_vcmpweq = 1043
25935 CEFBS_None, // A2_vcmpwgt = 1044
25936 CEFBS_None, // A2_vcmpwgtu = 1045
25937 CEFBS_None, // A2_vconj = 1046
25938 CEFBS_None, // A2_vmaxb = 1047
25939 CEFBS_None, // A2_vmaxh = 1048
25940 CEFBS_None, // A2_vmaxub = 1049
25941 CEFBS_None, // A2_vmaxuh = 1050
25942 CEFBS_None, // A2_vmaxuw = 1051
25943 CEFBS_None, // A2_vmaxw = 1052
25944 CEFBS_None, // A2_vminb = 1053
25945 CEFBS_None, // A2_vminh = 1054
25946 CEFBS_None, // A2_vminub = 1055
25947 CEFBS_None, // A2_vminuh = 1056
25948 CEFBS_None, // A2_vminuw = 1057
25949 CEFBS_None, // A2_vminw = 1058
25950 CEFBS_None, // A2_vnavgh = 1059
25951 CEFBS_None, // A2_vnavghcr = 1060
25952 CEFBS_None, // A2_vnavghr = 1061
25953 CEFBS_None, // A2_vnavgw = 1062
25954 CEFBS_None, // A2_vnavgwcr = 1063
25955 CEFBS_None, // A2_vnavgwr = 1064
25956 CEFBS_None, // A2_vraddub = 1065
25957 CEFBS_None, // A2_vraddub_acc = 1066
25958 CEFBS_None, // A2_vrsadub = 1067
25959 CEFBS_None, // A2_vrsadub_acc = 1068
25960 CEFBS_None, // A2_vsubh = 1069
25961 CEFBS_None, // A2_vsubhs = 1070
25962 CEFBS_None, // A2_vsubub = 1071
25963 CEFBS_None, // A2_vsububs = 1072
25964 CEFBS_None, // A2_vsubuhs = 1073
25965 CEFBS_None, // A2_vsubw = 1074
25966 CEFBS_None, // A2_vsubws = 1075
25967 CEFBS_None, // A2_xor = 1076
25968 CEFBS_None, // A2_xorp = 1077
25969 CEFBS_None, // A2_zxth = 1078
25970 CEFBS_None, // A4_addp_c = 1079
25971 CEFBS_None, // A4_andn = 1080
25972 CEFBS_None, // A4_andnp = 1081
25973 CEFBS_None, // A4_bitsplit = 1082
25974 CEFBS_None, // A4_bitspliti = 1083
25975 CEFBS_None, // A4_boundscheck_hi = 1084
25976 CEFBS_None, // A4_boundscheck_lo = 1085
25977 CEFBS_None, // A4_cmpbeq = 1086
25978 CEFBS_None, // A4_cmpbeqi = 1087
25979 CEFBS_None, // A4_cmpbgt = 1088
25980 CEFBS_None, // A4_cmpbgti = 1089
25981 CEFBS_None, // A4_cmpbgtu = 1090
25982 CEFBS_None, // A4_cmpbgtui = 1091
25983 CEFBS_None, // A4_cmpheq = 1092
25984 CEFBS_None, // A4_cmpheqi = 1093
25985 CEFBS_None, // A4_cmphgt = 1094
25986 CEFBS_None, // A4_cmphgti = 1095
25987 CEFBS_None, // A4_cmphgtu = 1096
25988 CEFBS_None, // A4_cmphgtui = 1097
25989 CEFBS_None, // A4_combineii = 1098
25990 CEFBS_None, // A4_combineir = 1099
25991 CEFBS_None, // A4_combineri = 1100
25992 CEFBS_None, // A4_cround_ri = 1101
25993 CEFBS_None, // A4_cround_rr = 1102
25994 CEFBS_None, // A4_ext = 1103
25995 CEFBS_None, // A4_modwrapu = 1104
25996 CEFBS_None, // A4_orn = 1105
25997 CEFBS_None, // A4_ornp = 1106
25998 CEFBS_None, // A4_paslhf = 1107
25999 CEFBS_None, // A4_paslhfnew = 1108
26000 CEFBS_None, // A4_paslht = 1109
26001 CEFBS_None, // A4_paslhtnew = 1110
26002 CEFBS_None, // A4_pasrhf = 1111
26003 CEFBS_None, // A4_pasrhfnew = 1112
26004 CEFBS_None, // A4_pasrht = 1113
26005 CEFBS_None, // A4_pasrhtnew = 1114
26006 CEFBS_None, // A4_psxtbf = 1115
26007 CEFBS_None, // A4_psxtbfnew = 1116
26008 CEFBS_None, // A4_psxtbt = 1117
26009 CEFBS_None, // A4_psxtbtnew = 1118
26010 CEFBS_None, // A4_psxthf = 1119
26011 CEFBS_None, // A4_psxthfnew = 1120
26012 CEFBS_None, // A4_psxtht = 1121
26013 CEFBS_None, // A4_psxthtnew = 1122
26014 CEFBS_None, // A4_pzxtbf = 1123
26015 CEFBS_None, // A4_pzxtbfnew = 1124
26016 CEFBS_None, // A4_pzxtbt = 1125
26017 CEFBS_None, // A4_pzxtbtnew = 1126
26018 CEFBS_None, // A4_pzxthf = 1127
26019 CEFBS_None, // A4_pzxthfnew = 1128
26020 CEFBS_None, // A4_pzxtht = 1129
26021 CEFBS_None, // A4_pzxthtnew = 1130
26022 CEFBS_None, // A4_rcmpeq = 1131
26023 CEFBS_None, // A4_rcmpeqi = 1132
26024 CEFBS_None, // A4_rcmpneq = 1133
26025 CEFBS_None, // A4_rcmpneqi = 1134
26026 CEFBS_None, // A4_round_ri = 1135
26027 CEFBS_None, // A4_round_ri_sat = 1136
26028 CEFBS_None, // A4_round_rr = 1137
26029 CEFBS_None, // A4_round_rr_sat = 1138
26030 CEFBS_None, // A4_subp_c = 1139
26031 CEFBS_None, // A4_tfrcpp = 1140
26032 CEFBS_None, // A4_tfrpcp = 1141
26033 CEFBS_None, // A4_tlbmatch = 1142
26034 CEFBS_None, // A4_vcmpbeq_any = 1143
26035 CEFBS_None, // A4_vcmpbeqi = 1144
26036 CEFBS_None, // A4_vcmpbgt = 1145
26037 CEFBS_None, // A4_vcmpbgti = 1146
26038 CEFBS_None, // A4_vcmpbgtui = 1147
26039 CEFBS_None, // A4_vcmpheqi = 1148
26040 CEFBS_None, // A4_vcmphgti = 1149
26041 CEFBS_None, // A4_vcmphgtui = 1150
26042 CEFBS_None, // A4_vcmpweqi = 1151
26043 CEFBS_None, // A4_vcmpwgti = 1152
26044 CEFBS_None, // A4_vcmpwgtui = 1153
26045 CEFBS_None, // A4_vrmaxh = 1154
26046 CEFBS_None, // A4_vrmaxuh = 1155
26047 CEFBS_None, // A4_vrmaxuw = 1156
26048 CEFBS_None, // A4_vrmaxw = 1157
26049 CEFBS_None, // A4_vrminh = 1158
26050 CEFBS_None, // A4_vrminuh = 1159
26051 CEFBS_None, // A4_vrminuw = 1160
26052 CEFBS_None, // A4_vrminw = 1161
26053 CEFBS_HasV55, // A5_ACS = 1162
26054 CEFBS_None, // A5_vaddhubs = 1163
26055 CEFBS_HasV65, // A6_vcmpbeq_notany = 1164
26056 CEFBS_HasV62, // A6_vminub_RdP = 1165
26057 CEFBS_HasV67_UseAudio, // A7_clip = 1166
26058 CEFBS_HasV67_UseAudio, // A7_croundd_ri = 1167
26059 CEFBS_HasV67_UseAudio, // A7_croundd_rr = 1168
26060 CEFBS_HasV67_UseAudio, // A7_vclip = 1169
26061 CEFBS_None, // C2_all8 = 1170
26062 CEFBS_None, // C2_and = 1171
26063 CEFBS_None, // C2_andn = 1172
26064 CEFBS_None, // C2_any8 = 1173
26065 CEFBS_None, // C2_bitsclr = 1174
26066 CEFBS_None, // C2_bitsclri = 1175
26067 CEFBS_None, // C2_bitsset = 1176
26068 CEFBS_None, // C2_ccombinewf = 1177
26069 CEFBS_None, // C2_ccombinewnewf = 1178
26070 CEFBS_None, // C2_ccombinewnewt = 1179
26071 CEFBS_None, // C2_ccombinewt = 1180
26072 CEFBS_None, // C2_cmoveif = 1181
26073 CEFBS_None, // C2_cmoveit = 1182
26074 CEFBS_None, // C2_cmovenewif = 1183
26075 CEFBS_None, // C2_cmovenewit = 1184
26076 CEFBS_None, // C2_cmpeq = 1185
26077 CEFBS_None, // C2_cmpeqi = 1186
26078 CEFBS_None, // C2_cmpeqp = 1187
26079 CEFBS_None, // C2_cmpgt = 1188
26080 CEFBS_None, // C2_cmpgti = 1189
26081 CEFBS_None, // C2_cmpgtp = 1190
26082 CEFBS_None, // C2_cmpgtu = 1191
26083 CEFBS_None, // C2_cmpgtui = 1192
26084 CEFBS_None, // C2_cmpgtup = 1193
26085 CEFBS_None, // C2_mask = 1194
26086 CEFBS_None, // C2_mux = 1195
26087 CEFBS_None, // C2_muxii = 1196
26088 CEFBS_None, // C2_muxir = 1197
26089 CEFBS_None, // C2_muxri = 1198
26090 CEFBS_None, // C2_not = 1199
26091 CEFBS_None, // C2_or = 1200
26092 CEFBS_None, // C2_orn = 1201
26093 CEFBS_None, // C2_tfrpr = 1202
26094 CEFBS_None, // C2_tfrrp = 1203
26095 CEFBS_None, // C2_vitpack = 1204
26096 CEFBS_None, // C2_vmux = 1205
26097 CEFBS_None, // C2_xor = 1206
26098 CEFBS_None, // C4_addipc = 1207
26099 CEFBS_None, // C4_and_and = 1208
26100 CEFBS_None, // C4_and_andn = 1209
26101 CEFBS_None, // C4_and_or = 1210
26102 CEFBS_None, // C4_and_orn = 1211
26103 CEFBS_None, // C4_cmplte = 1212
26104 CEFBS_None, // C4_cmpltei = 1213
26105 CEFBS_None, // C4_cmplteu = 1214
26106 CEFBS_None, // C4_cmplteui = 1215
26107 CEFBS_None, // C4_cmpneq = 1216
26108 CEFBS_None, // C4_cmpneqi = 1217
26109 CEFBS_None, // C4_fastcorner9 = 1218
26110 CEFBS_None, // C4_fastcorner9_not = 1219
26111 CEFBS_None, // C4_nbitsclr = 1220
26112 CEFBS_None, // C4_nbitsclri = 1221
26113 CEFBS_None, // C4_nbitsset = 1222
26114 CEFBS_None, // C4_or_and = 1223
26115 CEFBS_None, // C4_or_andn = 1224
26116 CEFBS_None, // C4_or_or = 1225
26117 CEFBS_None, // C4_or_orn = 1226
26118 CEFBS_None, // CALLProfile = 1227
26119 CEFBS_None, // CONST32 = 1228
26120 CEFBS_None, // CONST64 = 1229
26121 CEFBS_None, // DuplexIClass0 = 1230
26122 CEFBS_None, // DuplexIClass1 = 1231
26123 CEFBS_None, // DuplexIClass2 = 1232
26124 CEFBS_None, // DuplexIClass3 = 1233
26125 CEFBS_None, // DuplexIClass4 = 1234
26126 CEFBS_None, // DuplexIClass5 = 1235
26127 CEFBS_None, // DuplexIClass6 = 1236
26128 CEFBS_None, // DuplexIClass7 = 1237
26129 CEFBS_None, // DuplexIClass8 = 1238
26130 CEFBS_None, // DuplexIClass9 = 1239
26131 CEFBS_None, // DuplexIClassA = 1240
26132 CEFBS_None, // DuplexIClassB = 1241
26133 CEFBS_None, // DuplexIClassC = 1242
26134 CEFBS_None, // DuplexIClassD = 1243
26135 CEFBS_None, // DuplexIClassE = 1244
26136 CEFBS_None, // DuplexIClassF = 1245
26137 CEFBS_None, // EH_RETURN_JMPR = 1246
26138 CEFBS_None, // F2_conv_d2df = 1247
26139 CEFBS_None, // F2_conv_d2sf = 1248
26140 CEFBS_None, // F2_conv_df2d = 1249
26141 CEFBS_None, // F2_conv_df2d_chop = 1250
26142 CEFBS_None, // F2_conv_df2sf = 1251
26143 CEFBS_None, // F2_conv_df2ud = 1252
26144 CEFBS_None, // F2_conv_df2ud_chop = 1253
26145 CEFBS_None, // F2_conv_df2uw = 1254
26146 CEFBS_None, // F2_conv_df2uw_chop = 1255
26147 CEFBS_None, // F2_conv_df2w = 1256
26148 CEFBS_None, // F2_conv_df2w_chop = 1257
26149 CEFBS_None, // F2_conv_sf2d = 1258
26150 CEFBS_None, // F2_conv_sf2d_chop = 1259
26151 CEFBS_None, // F2_conv_sf2df = 1260
26152 CEFBS_None, // F2_conv_sf2ud = 1261
26153 CEFBS_None, // F2_conv_sf2ud_chop = 1262
26154 CEFBS_None, // F2_conv_sf2uw = 1263
26155 CEFBS_None, // F2_conv_sf2uw_chop = 1264
26156 CEFBS_None, // F2_conv_sf2w = 1265
26157 CEFBS_None, // F2_conv_sf2w_chop = 1266
26158 CEFBS_None, // F2_conv_ud2df = 1267
26159 CEFBS_None, // F2_conv_ud2sf = 1268
26160 CEFBS_None, // F2_conv_uw2df = 1269
26161 CEFBS_None, // F2_conv_uw2sf = 1270
26162 CEFBS_None, // F2_conv_w2df = 1271
26163 CEFBS_None, // F2_conv_w2sf = 1272
26164 CEFBS_HasV66, // F2_dfadd = 1273
26165 CEFBS_None, // F2_dfclass = 1274
26166 CEFBS_None, // F2_dfcmpeq = 1275
26167 CEFBS_None, // F2_dfcmpge = 1276
26168 CEFBS_None, // F2_dfcmpgt = 1277
26169 CEFBS_None, // F2_dfcmpuo = 1278
26170 CEFBS_None, // F2_dfimm_n = 1279
26171 CEFBS_None, // F2_dfimm_p = 1280
26172 CEFBS_HasV67, // F2_dfmax = 1281
26173 CEFBS_HasV67, // F2_dfmin = 1282
26174 CEFBS_HasV67, // F2_dfmpyfix = 1283
26175 CEFBS_HasV67, // F2_dfmpyhh = 1284
26176 CEFBS_HasV67, // F2_dfmpylh = 1285
26177 CEFBS_HasV67, // F2_dfmpyll = 1286
26178 CEFBS_HasV66, // F2_dfsub = 1287
26179 CEFBS_None, // F2_sfadd = 1288
26180 CEFBS_None, // F2_sfclass = 1289
26181 CEFBS_None, // F2_sfcmpeq = 1290
26182 CEFBS_None, // F2_sfcmpge = 1291
26183 CEFBS_None, // F2_sfcmpgt = 1292
26184 CEFBS_None, // F2_sfcmpuo = 1293
26185 CEFBS_None, // F2_sffixupd = 1294
26186 CEFBS_None, // F2_sffixupn = 1295
26187 CEFBS_None, // F2_sffixupr = 1296
26188 CEFBS_None, // F2_sffma = 1297
26189 CEFBS_None, // F2_sffma_lib = 1298
26190 CEFBS_None, // F2_sffma_sc = 1299
26191 CEFBS_None, // F2_sffms = 1300
26192 CEFBS_None, // F2_sffms_lib = 1301
26193 CEFBS_None, // F2_sfimm_n = 1302
26194 CEFBS_None, // F2_sfimm_p = 1303
26195 CEFBS_None, // F2_sfinvsqrta = 1304
26196 CEFBS_None, // F2_sfmax = 1305
26197 CEFBS_None, // F2_sfmin = 1306
26198 CEFBS_None, // F2_sfmpy = 1307
26199 CEFBS_None, // F2_sfrecipa = 1308
26200 CEFBS_None, // F2_sfsub = 1309
26201 CEFBS_None, // G4_tfrgcpp = 1310
26202 CEFBS_None, // G4_tfrgcrr = 1311
26203 CEFBS_None, // G4_tfrgpcp = 1312
26204 CEFBS_None, // G4_tfrgrcr = 1313
26205 CEFBS_None, // HI = 1314
26206 CEFBS_None, // J2_call = 1315
26207 CEFBS_None, // J2_callf = 1316
26208 CEFBS_None, // J2_callr = 1317
26209 CEFBS_None, // J2_callrf = 1318
26210 CEFBS_HasV73, // J2_callrh = 1319
26211 CEFBS_None, // J2_callrt = 1320
26212 CEFBS_None, // J2_callt = 1321
26213 CEFBS_None, // J2_jump = 1322
26214 CEFBS_None, // J2_jumpf = 1323
26215 CEFBS_None, // J2_jumpfnew = 1324
26216 CEFBS_None, // J2_jumpfnewpt = 1325
26217 CEFBS_HasV60, // J2_jumpfpt = 1326
26218 CEFBS_None, // J2_jumpr = 1327
26219 CEFBS_None, // J2_jumprf = 1328
26220 CEFBS_None, // J2_jumprfnew = 1329
26221 CEFBS_None, // J2_jumprfnewpt = 1330
26222 CEFBS_HasV60, // J2_jumprfpt = 1331
26223 CEFBS_None, // J2_jumprgtez = 1332
26224 CEFBS_None, // J2_jumprgtezpt = 1333
26225 CEFBS_HasV73, // J2_jumprh = 1334
26226 CEFBS_None, // J2_jumprltez = 1335
26227 CEFBS_None, // J2_jumprltezpt = 1336
26228 CEFBS_None, // J2_jumprnz = 1337
26229 CEFBS_None, // J2_jumprnzpt = 1338
26230 CEFBS_None, // J2_jumprt = 1339
26231 CEFBS_None, // J2_jumprtnew = 1340
26232 CEFBS_None, // J2_jumprtnewpt = 1341
26233 CEFBS_HasV60, // J2_jumprtpt = 1342
26234 CEFBS_None, // J2_jumprz = 1343
26235 CEFBS_None, // J2_jumprzpt = 1344
26236 CEFBS_None, // J2_jumpt = 1345
26237 CEFBS_None, // J2_jumptnew = 1346
26238 CEFBS_None, // J2_jumptnewpt = 1347
26239 CEFBS_HasV60, // J2_jumptpt = 1348
26240 CEFBS_None, // J2_loop0i = 1349
26241 CEFBS_None, // J2_loop0iext = 1350
26242 CEFBS_None, // J2_loop0r = 1351
26243 CEFBS_None, // J2_loop0rext = 1352
26244 CEFBS_None, // J2_loop1i = 1353
26245 CEFBS_None, // J2_loop1iext = 1354
26246 CEFBS_None, // J2_loop1r = 1355
26247 CEFBS_None, // J2_loop1rext = 1356
26248 CEFBS_None, // J2_pause = 1357
26249 CEFBS_None, // J2_ploop1si = 1358
26250 CEFBS_None, // J2_ploop1sr = 1359
26251 CEFBS_None, // J2_ploop2si = 1360
26252 CEFBS_None, // J2_ploop2sr = 1361
26253 CEFBS_None, // J2_ploop3si = 1362
26254 CEFBS_None, // J2_ploop3sr = 1363
26255 CEFBS_None, // J2_rte = 1364
26256 CEFBS_None, // J2_trap0 = 1365
26257 CEFBS_HasV65, // J2_trap1 = 1366
26258 CEFBS_HasV73, // J2_unpause = 1367
26259 CEFBS_None, // J4_cmpeq_f_jumpnv_nt = 1368
26260 CEFBS_None, // J4_cmpeq_f_jumpnv_t = 1369
26261 CEFBS_None, // J4_cmpeq_fp0_jump_nt = 1370
26262 CEFBS_None, // J4_cmpeq_fp0_jump_t = 1371
26263 CEFBS_None, // J4_cmpeq_fp1_jump_nt = 1372
26264 CEFBS_None, // J4_cmpeq_fp1_jump_t = 1373
26265 CEFBS_None, // J4_cmpeq_t_jumpnv_nt = 1374
26266 CEFBS_None, // J4_cmpeq_t_jumpnv_t = 1375
26267 CEFBS_None, // J4_cmpeq_tp0_jump_nt = 1376
26268 CEFBS_None, // J4_cmpeq_tp0_jump_t = 1377
26269 CEFBS_None, // J4_cmpeq_tp1_jump_nt = 1378
26270 CEFBS_None, // J4_cmpeq_tp1_jump_t = 1379
26271 CEFBS_None, // J4_cmpeqi_f_jumpnv_nt = 1380
26272 CEFBS_None, // J4_cmpeqi_f_jumpnv_t = 1381
26273 CEFBS_None, // J4_cmpeqi_fp0_jump_nt = 1382
26274 CEFBS_None, // J4_cmpeqi_fp0_jump_t = 1383
26275 CEFBS_None, // J4_cmpeqi_fp1_jump_nt = 1384
26276 CEFBS_None, // J4_cmpeqi_fp1_jump_t = 1385
26277 CEFBS_None, // J4_cmpeqi_t_jumpnv_nt = 1386
26278 CEFBS_None, // J4_cmpeqi_t_jumpnv_t = 1387
26279 CEFBS_None, // J4_cmpeqi_tp0_jump_nt = 1388
26280 CEFBS_None, // J4_cmpeqi_tp0_jump_t = 1389
26281 CEFBS_None, // J4_cmpeqi_tp1_jump_nt = 1390
26282 CEFBS_None, // J4_cmpeqi_tp1_jump_t = 1391
26283 CEFBS_None, // J4_cmpeqn1_f_jumpnv_nt = 1392
26284 CEFBS_None, // J4_cmpeqn1_f_jumpnv_t = 1393
26285 CEFBS_None, // J4_cmpeqn1_fp0_jump_nt = 1394
26286 CEFBS_None, // J4_cmpeqn1_fp0_jump_t = 1395
26287 CEFBS_None, // J4_cmpeqn1_fp1_jump_nt = 1396
26288 CEFBS_None, // J4_cmpeqn1_fp1_jump_t = 1397
26289 CEFBS_None, // J4_cmpeqn1_t_jumpnv_nt = 1398
26290 CEFBS_None, // J4_cmpeqn1_t_jumpnv_t = 1399
26291 CEFBS_None, // J4_cmpeqn1_tp0_jump_nt = 1400
26292 CEFBS_None, // J4_cmpeqn1_tp0_jump_t = 1401
26293 CEFBS_None, // J4_cmpeqn1_tp1_jump_nt = 1402
26294 CEFBS_None, // J4_cmpeqn1_tp1_jump_t = 1403
26295 CEFBS_None, // J4_cmpgt_f_jumpnv_nt = 1404
26296 CEFBS_None, // J4_cmpgt_f_jumpnv_t = 1405
26297 CEFBS_None, // J4_cmpgt_fp0_jump_nt = 1406
26298 CEFBS_None, // J4_cmpgt_fp0_jump_t = 1407
26299 CEFBS_None, // J4_cmpgt_fp1_jump_nt = 1408
26300 CEFBS_None, // J4_cmpgt_fp1_jump_t = 1409
26301 CEFBS_None, // J4_cmpgt_t_jumpnv_nt = 1410
26302 CEFBS_None, // J4_cmpgt_t_jumpnv_t = 1411
26303 CEFBS_None, // J4_cmpgt_tp0_jump_nt = 1412
26304 CEFBS_None, // J4_cmpgt_tp0_jump_t = 1413
26305 CEFBS_None, // J4_cmpgt_tp1_jump_nt = 1414
26306 CEFBS_None, // J4_cmpgt_tp1_jump_t = 1415
26307 CEFBS_None, // J4_cmpgti_f_jumpnv_nt = 1416
26308 CEFBS_None, // J4_cmpgti_f_jumpnv_t = 1417
26309 CEFBS_None, // J4_cmpgti_fp0_jump_nt = 1418
26310 CEFBS_None, // J4_cmpgti_fp0_jump_t = 1419
26311 CEFBS_None, // J4_cmpgti_fp1_jump_nt = 1420
26312 CEFBS_None, // J4_cmpgti_fp1_jump_t = 1421
26313 CEFBS_None, // J4_cmpgti_t_jumpnv_nt = 1422
26314 CEFBS_None, // J4_cmpgti_t_jumpnv_t = 1423
26315 CEFBS_None, // J4_cmpgti_tp0_jump_nt = 1424
26316 CEFBS_None, // J4_cmpgti_tp0_jump_t = 1425
26317 CEFBS_None, // J4_cmpgti_tp1_jump_nt = 1426
26318 CEFBS_None, // J4_cmpgti_tp1_jump_t = 1427
26319 CEFBS_None, // J4_cmpgtn1_f_jumpnv_nt = 1428
26320 CEFBS_None, // J4_cmpgtn1_f_jumpnv_t = 1429
26321 CEFBS_None, // J4_cmpgtn1_fp0_jump_nt = 1430
26322 CEFBS_None, // J4_cmpgtn1_fp0_jump_t = 1431
26323 CEFBS_None, // J4_cmpgtn1_fp1_jump_nt = 1432
26324 CEFBS_None, // J4_cmpgtn1_fp1_jump_t = 1433
26325 CEFBS_None, // J4_cmpgtn1_t_jumpnv_nt = 1434
26326 CEFBS_None, // J4_cmpgtn1_t_jumpnv_t = 1435
26327 CEFBS_None, // J4_cmpgtn1_tp0_jump_nt = 1436
26328 CEFBS_None, // J4_cmpgtn1_tp0_jump_t = 1437
26329 CEFBS_None, // J4_cmpgtn1_tp1_jump_nt = 1438
26330 CEFBS_None, // J4_cmpgtn1_tp1_jump_t = 1439
26331 CEFBS_None, // J4_cmpgtu_f_jumpnv_nt = 1440
26332 CEFBS_None, // J4_cmpgtu_f_jumpnv_t = 1441
26333 CEFBS_None, // J4_cmpgtu_fp0_jump_nt = 1442
26334 CEFBS_None, // J4_cmpgtu_fp0_jump_t = 1443
26335 CEFBS_None, // J4_cmpgtu_fp1_jump_nt = 1444
26336 CEFBS_None, // J4_cmpgtu_fp1_jump_t = 1445
26337 CEFBS_None, // J4_cmpgtu_t_jumpnv_nt = 1446
26338 CEFBS_None, // J4_cmpgtu_t_jumpnv_t = 1447
26339 CEFBS_None, // J4_cmpgtu_tp0_jump_nt = 1448
26340 CEFBS_None, // J4_cmpgtu_tp0_jump_t = 1449
26341 CEFBS_None, // J4_cmpgtu_tp1_jump_nt = 1450
26342 CEFBS_None, // J4_cmpgtu_tp1_jump_t = 1451
26343 CEFBS_None, // J4_cmpgtui_f_jumpnv_nt = 1452
26344 CEFBS_None, // J4_cmpgtui_f_jumpnv_t = 1453
26345 CEFBS_None, // J4_cmpgtui_fp0_jump_nt = 1454
26346 CEFBS_None, // J4_cmpgtui_fp0_jump_t = 1455
26347 CEFBS_None, // J4_cmpgtui_fp1_jump_nt = 1456
26348 CEFBS_None, // J4_cmpgtui_fp1_jump_t = 1457
26349 CEFBS_None, // J4_cmpgtui_t_jumpnv_nt = 1458
26350 CEFBS_None, // J4_cmpgtui_t_jumpnv_t = 1459
26351 CEFBS_None, // J4_cmpgtui_tp0_jump_nt = 1460
26352 CEFBS_None, // J4_cmpgtui_tp0_jump_t = 1461
26353 CEFBS_None, // J4_cmpgtui_tp1_jump_nt = 1462
26354 CEFBS_None, // J4_cmpgtui_tp1_jump_t = 1463
26355 CEFBS_None, // J4_cmplt_f_jumpnv_nt = 1464
26356 CEFBS_None, // J4_cmplt_f_jumpnv_t = 1465
26357 CEFBS_None, // J4_cmplt_t_jumpnv_nt = 1466
26358 CEFBS_None, // J4_cmplt_t_jumpnv_t = 1467
26359 CEFBS_None, // J4_cmpltu_f_jumpnv_nt = 1468
26360 CEFBS_None, // J4_cmpltu_f_jumpnv_t = 1469
26361 CEFBS_None, // J4_cmpltu_t_jumpnv_nt = 1470
26362 CEFBS_None, // J4_cmpltu_t_jumpnv_t = 1471
26363 CEFBS_None, // J4_hintjumpr = 1472
26364 CEFBS_None, // J4_jumpseti = 1473
26365 CEFBS_None, // J4_jumpsetr = 1474
26366 CEFBS_None, // J4_tstbit0_f_jumpnv_nt = 1475
26367 CEFBS_None, // J4_tstbit0_f_jumpnv_t = 1476
26368 CEFBS_None, // J4_tstbit0_fp0_jump_nt = 1477
26369 CEFBS_None, // J4_tstbit0_fp0_jump_t = 1478
26370 CEFBS_None, // J4_tstbit0_fp1_jump_nt = 1479
26371 CEFBS_None, // J4_tstbit0_fp1_jump_t = 1480
26372 CEFBS_None, // J4_tstbit0_t_jumpnv_nt = 1481
26373 CEFBS_None, // J4_tstbit0_t_jumpnv_t = 1482
26374 CEFBS_None, // J4_tstbit0_tp0_jump_nt = 1483
26375 CEFBS_None, // J4_tstbit0_tp0_jump_t = 1484
26376 CEFBS_None, // J4_tstbit0_tp1_jump_nt = 1485
26377 CEFBS_None, // J4_tstbit0_tp1_jump_t = 1486
26378 CEFBS_None, // L2_deallocframe = 1487
26379 CEFBS_None, // L2_loadalignb_io = 1488
26380 CEFBS_None, // L2_loadalignb_pbr = 1489
26381 CEFBS_None, // L2_loadalignb_pci = 1490
26382 CEFBS_None, // L2_loadalignb_pcr = 1491
26383 CEFBS_None, // L2_loadalignb_pi = 1492
26384 CEFBS_None, // L2_loadalignb_pr = 1493
26385 CEFBS_None, // L2_loadalignh_io = 1494
26386 CEFBS_None, // L2_loadalignh_pbr = 1495
26387 CEFBS_None, // L2_loadalignh_pci = 1496
26388 CEFBS_None, // L2_loadalignh_pcr = 1497
26389 CEFBS_None, // L2_loadalignh_pi = 1498
26390 CEFBS_None, // L2_loadalignh_pr = 1499
26391 CEFBS_None, // L2_loadbsw2_io = 1500
26392 CEFBS_None, // L2_loadbsw2_pbr = 1501
26393 CEFBS_None, // L2_loadbsw2_pci = 1502
26394 CEFBS_None, // L2_loadbsw2_pcr = 1503
26395 CEFBS_None, // L2_loadbsw2_pi = 1504
26396 CEFBS_None, // L2_loadbsw2_pr = 1505
26397 CEFBS_None, // L2_loadbsw4_io = 1506
26398 CEFBS_None, // L2_loadbsw4_pbr = 1507
26399 CEFBS_None, // L2_loadbsw4_pci = 1508
26400 CEFBS_None, // L2_loadbsw4_pcr = 1509
26401 CEFBS_None, // L2_loadbsw4_pi = 1510
26402 CEFBS_None, // L2_loadbsw4_pr = 1511
26403 CEFBS_None, // L2_loadbzw2_io = 1512
26404 CEFBS_None, // L2_loadbzw2_pbr = 1513
26405 CEFBS_None, // L2_loadbzw2_pci = 1514
26406 CEFBS_None, // L2_loadbzw2_pcr = 1515
26407 CEFBS_None, // L2_loadbzw2_pi = 1516
26408 CEFBS_None, // L2_loadbzw2_pr = 1517
26409 CEFBS_None, // L2_loadbzw4_io = 1518
26410 CEFBS_None, // L2_loadbzw4_pbr = 1519
26411 CEFBS_None, // L2_loadbzw4_pci = 1520
26412 CEFBS_None, // L2_loadbzw4_pcr = 1521
26413 CEFBS_None, // L2_loadbzw4_pi = 1522
26414 CEFBS_None, // L2_loadbzw4_pr = 1523
26415 CEFBS_None, // L2_loadrb_io = 1524
26416 CEFBS_None, // L2_loadrb_pbr = 1525
26417 CEFBS_None, // L2_loadrb_pci = 1526
26418 CEFBS_None, // L2_loadrb_pcr = 1527
26419 CEFBS_None, // L2_loadrb_pi = 1528
26420 CEFBS_None, // L2_loadrb_pr = 1529
26421 CEFBS_None, // L2_loadrbgp = 1530
26422 CEFBS_None, // L2_loadrd_io = 1531
26423 CEFBS_None, // L2_loadrd_pbr = 1532
26424 CEFBS_None, // L2_loadrd_pci = 1533
26425 CEFBS_None, // L2_loadrd_pcr = 1534
26426 CEFBS_None, // L2_loadrd_pi = 1535
26427 CEFBS_None, // L2_loadrd_pr = 1536
26428 CEFBS_None, // L2_loadrdgp = 1537
26429 CEFBS_None, // L2_loadrh_io = 1538
26430 CEFBS_None, // L2_loadrh_pbr = 1539
26431 CEFBS_None, // L2_loadrh_pci = 1540
26432 CEFBS_None, // L2_loadrh_pcr = 1541
26433 CEFBS_None, // L2_loadrh_pi = 1542
26434 CEFBS_None, // L2_loadrh_pr = 1543
26435 CEFBS_None, // L2_loadrhgp = 1544
26436 CEFBS_None, // L2_loadri_io = 1545
26437 CEFBS_None, // L2_loadri_pbr = 1546
26438 CEFBS_None, // L2_loadri_pci = 1547
26439 CEFBS_None, // L2_loadri_pcr = 1548
26440 CEFBS_None, // L2_loadri_pi = 1549
26441 CEFBS_None, // L2_loadri_pr = 1550
26442 CEFBS_None, // L2_loadrigp = 1551
26443 CEFBS_None, // L2_loadrub_io = 1552
26444 CEFBS_None, // L2_loadrub_pbr = 1553
26445 CEFBS_None, // L2_loadrub_pci = 1554
26446 CEFBS_None, // L2_loadrub_pcr = 1555
26447 CEFBS_None, // L2_loadrub_pi = 1556
26448 CEFBS_None, // L2_loadrub_pr = 1557
26449 CEFBS_None, // L2_loadrubgp = 1558
26450 CEFBS_None, // L2_loadruh_io = 1559
26451 CEFBS_None, // L2_loadruh_pbr = 1560
26452 CEFBS_None, // L2_loadruh_pci = 1561
26453 CEFBS_None, // L2_loadruh_pcr = 1562
26454 CEFBS_None, // L2_loadruh_pi = 1563
26455 CEFBS_None, // L2_loadruh_pr = 1564
26456 CEFBS_None, // L2_loadruhgp = 1565
26457 CEFBS_HasV68, // L2_loadw_aq = 1566
26458 CEFBS_None, // L2_loadw_locked = 1567
26459 CEFBS_None, // L2_ploadrbf_io = 1568
26460 CEFBS_None, // L2_ploadrbf_pi = 1569
26461 CEFBS_None, // L2_ploadrbfnew_io = 1570
26462 CEFBS_None, // L2_ploadrbfnew_pi = 1571
26463 CEFBS_None, // L2_ploadrbt_io = 1572
26464 CEFBS_None, // L2_ploadrbt_pi = 1573
26465 CEFBS_None, // L2_ploadrbtnew_io = 1574
26466 CEFBS_None, // L2_ploadrbtnew_pi = 1575
26467 CEFBS_None, // L2_ploadrdf_io = 1576
26468 CEFBS_None, // L2_ploadrdf_pi = 1577
26469 CEFBS_None, // L2_ploadrdfnew_io = 1578
26470 CEFBS_None, // L2_ploadrdfnew_pi = 1579
26471 CEFBS_None, // L2_ploadrdt_io = 1580
26472 CEFBS_None, // L2_ploadrdt_pi = 1581
26473 CEFBS_None, // L2_ploadrdtnew_io = 1582
26474 CEFBS_None, // L2_ploadrdtnew_pi = 1583
26475 CEFBS_None, // L2_ploadrhf_io = 1584
26476 CEFBS_None, // L2_ploadrhf_pi = 1585
26477 CEFBS_None, // L2_ploadrhfnew_io = 1586
26478 CEFBS_None, // L2_ploadrhfnew_pi = 1587
26479 CEFBS_None, // L2_ploadrht_io = 1588
26480 CEFBS_None, // L2_ploadrht_pi = 1589
26481 CEFBS_None, // L2_ploadrhtnew_io = 1590
26482 CEFBS_None, // L2_ploadrhtnew_pi = 1591
26483 CEFBS_None, // L2_ploadrif_io = 1592
26484 CEFBS_None, // L2_ploadrif_pi = 1593
26485 CEFBS_None, // L2_ploadrifnew_io = 1594
26486 CEFBS_None, // L2_ploadrifnew_pi = 1595
26487 CEFBS_None, // L2_ploadrit_io = 1596
26488 CEFBS_None, // L2_ploadrit_pi = 1597
26489 CEFBS_None, // L2_ploadritnew_io = 1598
26490 CEFBS_None, // L2_ploadritnew_pi = 1599
26491 CEFBS_None, // L2_ploadrubf_io = 1600
26492 CEFBS_None, // L2_ploadrubf_pi = 1601
26493 CEFBS_None, // L2_ploadrubfnew_io = 1602
26494 CEFBS_None, // L2_ploadrubfnew_pi = 1603
26495 CEFBS_None, // L2_ploadrubt_io = 1604
26496 CEFBS_None, // L2_ploadrubt_pi = 1605
26497 CEFBS_None, // L2_ploadrubtnew_io = 1606
26498 CEFBS_None, // L2_ploadrubtnew_pi = 1607
26499 CEFBS_None, // L2_ploadruhf_io = 1608
26500 CEFBS_None, // L2_ploadruhf_pi = 1609
26501 CEFBS_None, // L2_ploadruhfnew_io = 1610
26502 CEFBS_None, // L2_ploadruhfnew_pi = 1611
26503 CEFBS_None, // L2_ploadruht_io = 1612
26504 CEFBS_None, // L2_ploadruht_pi = 1613
26505 CEFBS_None, // L2_ploadruhtnew_io = 1614
26506 CEFBS_None, // L2_ploadruhtnew_pi = 1615
26507 CEFBS_None, // L4_add_memopb_io = 1616
26508 CEFBS_None, // L4_add_memoph_io = 1617
26509 CEFBS_None, // L4_add_memopw_io = 1618
26510 CEFBS_None, // L4_and_memopb_io = 1619
26511 CEFBS_None, // L4_and_memoph_io = 1620
26512 CEFBS_None, // L4_and_memopw_io = 1621
26513 CEFBS_None, // L4_iadd_memopb_io = 1622
26514 CEFBS_None, // L4_iadd_memoph_io = 1623
26515 CEFBS_None, // L4_iadd_memopw_io = 1624
26516 CEFBS_None, // L4_iand_memopb_io = 1625
26517 CEFBS_None, // L4_iand_memoph_io = 1626
26518 CEFBS_None, // L4_iand_memopw_io = 1627
26519 CEFBS_None, // L4_ior_memopb_io = 1628
26520 CEFBS_None, // L4_ior_memoph_io = 1629
26521 CEFBS_None, // L4_ior_memopw_io = 1630
26522 CEFBS_None, // L4_isub_memopb_io = 1631
26523 CEFBS_None, // L4_isub_memoph_io = 1632
26524 CEFBS_None, // L4_isub_memopw_io = 1633
26525 CEFBS_None, // L4_loadalignb_ap = 1634
26526 CEFBS_None, // L4_loadalignb_ur = 1635
26527 CEFBS_None, // L4_loadalignh_ap = 1636
26528 CEFBS_None, // L4_loadalignh_ur = 1637
26529 CEFBS_None, // L4_loadbsw2_ap = 1638
26530 CEFBS_None, // L4_loadbsw2_ur = 1639
26531 CEFBS_None, // L4_loadbsw4_ap = 1640
26532 CEFBS_None, // L4_loadbsw4_ur = 1641
26533 CEFBS_None, // L4_loadbzw2_ap = 1642
26534 CEFBS_None, // L4_loadbzw2_ur = 1643
26535 CEFBS_None, // L4_loadbzw4_ap = 1644
26536 CEFBS_None, // L4_loadbzw4_ur = 1645
26537 CEFBS_HasV68, // L4_loadd_aq = 1646
26538 CEFBS_None, // L4_loadd_locked = 1647
26539 CEFBS_None, // L4_loadrb_ap = 1648
26540 CEFBS_None, // L4_loadrb_rr = 1649
26541 CEFBS_None, // L4_loadrb_ur = 1650
26542 CEFBS_None, // L4_loadrd_ap = 1651
26543 CEFBS_None, // L4_loadrd_rr = 1652
26544 CEFBS_None, // L4_loadrd_ur = 1653
26545 CEFBS_None, // L4_loadrh_ap = 1654
26546 CEFBS_None, // L4_loadrh_rr = 1655
26547 CEFBS_None, // L4_loadrh_ur = 1656
26548 CEFBS_None, // L4_loadri_ap = 1657
26549 CEFBS_None, // L4_loadri_rr = 1658
26550 CEFBS_None, // L4_loadri_ur = 1659
26551 CEFBS_None, // L4_loadrub_ap = 1660
26552 CEFBS_None, // L4_loadrub_rr = 1661
26553 CEFBS_None, // L4_loadrub_ur = 1662
26554 CEFBS_None, // L4_loadruh_ap = 1663
26555 CEFBS_None, // L4_loadruh_rr = 1664
26556 CEFBS_None, // L4_loadruh_ur = 1665
26557 CEFBS_None, // L4_loadw_phys = 1666
26558 CEFBS_None, // L4_or_memopb_io = 1667
26559 CEFBS_None, // L4_or_memoph_io = 1668
26560 CEFBS_None, // L4_or_memopw_io = 1669
26561 CEFBS_None, // L4_ploadrbf_abs = 1670
26562 CEFBS_None, // L4_ploadrbf_rr = 1671
26563 CEFBS_None, // L4_ploadrbfnew_abs = 1672
26564 CEFBS_None, // L4_ploadrbfnew_rr = 1673
26565 CEFBS_None, // L4_ploadrbt_abs = 1674
26566 CEFBS_None, // L4_ploadrbt_rr = 1675
26567 CEFBS_None, // L4_ploadrbtnew_abs = 1676
26568 CEFBS_None, // L4_ploadrbtnew_rr = 1677
26569 CEFBS_None, // L4_ploadrdf_abs = 1678
26570 CEFBS_None, // L4_ploadrdf_rr = 1679
26571 CEFBS_None, // L4_ploadrdfnew_abs = 1680
26572 CEFBS_None, // L4_ploadrdfnew_rr = 1681
26573 CEFBS_None, // L4_ploadrdt_abs = 1682
26574 CEFBS_None, // L4_ploadrdt_rr = 1683
26575 CEFBS_None, // L4_ploadrdtnew_abs = 1684
26576 CEFBS_None, // L4_ploadrdtnew_rr = 1685
26577 CEFBS_None, // L4_ploadrhf_abs = 1686
26578 CEFBS_None, // L4_ploadrhf_rr = 1687
26579 CEFBS_None, // L4_ploadrhfnew_abs = 1688
26580 CEFBS_None, // L4_ploadrhfnew_rr = 1689
26581 CEFBS_None, // L4_ploadrht_abs = 1690
26582 CEFBS_None, // L4_ploadrht_rr = 1691
26583 CEFBS_None, // L4_ploadrhtnew_abs = 1692
26584 CEFBS_None, // L4_ploadrhtnew_rr = 1693
26585 CEFBS_None, // L4_ploadrif_abs = 1694
26586 CEFBS_None, // L4_ploadrif_rr = 1695
26587 CEFBS_None, // L4_ploadrifnew_abs = 1696
26588 CEFBS_None, // L4_ploadrifnew_rr = 1697
26589 CEFBS_None, // L4_ploadrit_abs = 1698
26590 CEFBS_None, // L4_ploadrit_rr = 1699
26591 CEFBS_None, // L4_ploadritnew_abs = 1700
26592 CEFBS_None, // L4_ploadritnew_rr = 1701
26593 CEFBS_None, // L4_ploadrubf_abs = 1702
26594 CEFBS_None, // L4_ploadrubf_rr = 1703
26595 CEFBS_None, // L4_ploadrubfnew_abs = 1704
26596 CEFBS_None, // L4_ploadrubfnew_rr = 1705
26597 CEFBS_None, // L4_ploadrubt_abs = 1706
26598 CEFBS_None, // L4_ploadrubt_rr = 1707
26599 CEFBS_None, // L4_ploadrubtnew_abs = 1708
26600 CEFBS_None, // L4_ploadrubtnew_rr = 1709
26601 CEFBS_None, // L4_ploadruhf_abs = 1710
26602 CEFBS_None, // L4_ploadruhf_rr = 1711
26603 CEFBS_None, // L4_ploadruhfnew_abs = 1712
26604 CEFBS_None, // L4_ploadruhfnew_rr = 1713
26605 CEFBS_None, // L4_ploadruht_abs = 1714
26606 CEFBS_None, // L4_ploadruht_rr = 1715
26607 CEFBS_None, // L4_ploadruhtnew_abs = 1716
26608 CEFBS_None, // L4_ploadruhtnew_rr = 1717
26609 CEFBS_None, // L4_return = 1718
26610 CEFBS_None, // L4_return_f = 1719
26611 CEFBS_None, // L4_return_fnew_pnt = 1720
26612 CEFBS_None, // L4_return_fnew_pt = 1721
26613 CEFBS_None, // L4_return_t = 1722
26614 CEFBS_None, // L4_return_tnew_pnt = 1723
26615 CEFBS_None, // L4_return_tnew_pt = 1724
26616 CEFBS_None, // L4_sub_memopb_io = 1725
26617 CEFBS_None, // L4_sub_memoph_io = 1726
26618 CEFBS_None, // L4_sub_memopw_io = 1727
26619 CEFBS_HasV66, // L6_memcpy = 1728
26620 CEFBS_None, // LO = 1729
26621 CEFBS_None, // M2_acci = 1730
26622 CEFBS_None, // M2_accii = 1731
26623 CEFBS_None, // M2_cmaci_s0 = 1732
26624 CEFBS_None, // M2_cmacr_s0 = 1733
26625 CEFBS_None, // M2_cmacs_s0 = 1734
26626 CEFBS_None, // M2_cmacs_s1 = 1735
26627 CEFBS_None, // M2_cmacsc_s0 = 1736
26628 CEFBS_None, // M2_cmacsc_s1 = 1737
26629 CEFBS_None, // M2_cmpyi_s0 = 1738
26630 CEFBS_None, // M2_cmpyr_s0 = 1739
26631 CEFBS_None, // M2_cmpyrs_s0 = 1740
26632 CEFBS_None, // M2_cmpyrs_s1 = 1741
26633 CEFBS_None, // M2_cmpyrsc_s0 = 1742
26634 CEFBS_None, // M2_cmpyrsc_s1 = 1743
26635 CEFBS_None, // M2_cmpys_s0 = 1744
26636 CEFBS_None, // M2_cmpys_s1 = 1745
26637 CEFBS_None, // M2_cmpysc_s0 = 1746
26638 CEFBS_None, // M2_cmpysc_s1 = 1747
26639 CEFBS_None, // M2_cnacs_s0 = 1748
26640 CEFBS_None, // M2_cnacs_s1 = 1749
26641 CEFBS_None, // M2_cnacsc_s0 = 1750
26642 CEFBS_None, // M2_cnacsc_s1 = 1751
26643 CEFBS_None, // M2_dpmpyss_acc_s0 = 1752
26644 CEFBS_None, // M2_dpmpyss_nac_s0 = 1753
26645 CEFBS_None, // M2_dpmpyss_rnd_s0 = 1754
26646 CEFBS_None, // M2_dpmpyss_s0 = 1755
26647 CEFBS_None, // M2_dpmpyuu_acc_s0 = 1756
26648 CEFBS_None, // M2_dpmpyuu_nac_s0 = 1757
26649 CEFBS_None, // M2_dpmpyuu_s0 = 1758
26650 CEFBS_None, // M2_hmmpyh_rs1 = 1759
26651 CEFBS_None, // M2_hmmpyh_s1 = 1760
26652 CEFBS_None, // M2_hmmpyl_rs1 = 1761
26653 CEFBS_None, // M2_hmmpyl_s1 = 1762
26654 CEFBS_None, // M2_maci = 1763
26655 CEFBS_None, // M2_macsin = 1764
26656 CEFBS_None, // M2_macsip = 1765
26657 CEFBS_None, // M2_mmachs_rs0 = 1766
26658 CEFBS_None, // M2_mmachs_rs1 = 1767
26659 CEFBS_None, // M2_mmachs_s0 = 1768
26660 CEFBS_None, // M2_mmachs_s1 = 1769
26661 CEFBS_None, // M2_mmacls_rs0 = 1770
26662 CEFBS_None, // M2_mmacls_rs1 = 1771
26663 CEFBS_None, // M2_mmacls_s0 = 1772
26664 CEFBS_None, // M2_mmacls_s1 = 1773
26665 CEFBS_None, // M2_mmacuhs_rs0 = 1774
26666 CEFBS_None, // M2_mmacuhs_rs1 = 1775
26667 CEFBS_None, // M2_mmacuhs_s0 = 1776
26668 CEFBS_None, // M2_mmacuhs_s1 = 1777
26669 CEFBS_None, // M2_mmaculs_rs0 = 1778
26670 CEFBS_None, // M2_mmaculs_rs1 = 1779
26671 CEFBS_None, // M2_mmaculs_s0 = 1780
26672 CEFBS_None, // M2_mmaculs_s1 = 1781
26673 CEFBS_None, // M2_mmpyh_rs0 = 1782
26674 CEFBS_None, // M2_mmpyh_rs1 = 1783
26675 CEFBS_None, // M2_mmpyh_s0 = 1784
26676 CEFBS_None, // M2_mmpyh_s1 = 1785
26677 CEFBS_None, // M2_mmpyl_rs0 = 1786
26678 CEFBS_None, // M2_mmpyl_rs1 = 1787
26679 CEFBS_None, // M2_mmpyl_s0 = 1788
26680 CEFBS_None, // M2_mmpyl_s1 = 1789
26681 CEFBS_None, // M2_mmpyuh_rs0 = 1790
26682 CEFBS_None, // M2_mmpyuh_rs1 = 1791
26683 CEFBS_None, // M2_mmpyuh_s0 = 1792
26684 CEFBS_None, // M2_mmpyuh_s1 = 1793
26685 CEFBS_None, // M2_mmpyul_rs0 = 1794
26686 CEFBS_None, // M2_mmpyul_rs1 = 1795
26687 CEFBS_None, // M2_mmpyul_s0 = 1796
26688 CEFBS_None, // M2_mmpyul_s1 = 1797
26689 CEFBS_HasV66, // M2_mnaci = 1798
26690 CEFBS_None, // M2_mpy_acc_hh_s0 = 1799
26691 CEFBS_None, // M2_mpy_acc_hh_s1 = 1800
26692 CEFBS_None, // M2_mpy_acc_hl_s0 = 1801
26693 CEFBS_None, // M2_mpy_acc_hl_s1 = 1802
26694 CEFBS_None, // M2_mpy_acc_lh_s0 = 1803
26695 CEFBS_None, // M2_mpy_acc_lh_s1 = 1804
26696 CEFBS_None, // M2_mpy_acc_ll_s0 = 1805
26697 CEFBS_None, // M2_mpy_acc_ll_s1 = 1806
26698 CEFBS_None, // M2_mpy_acc_sat_hh_s0 = 1807
26699 CEFBS_None, // M2_mpy_acc_sat_hh_s1 = 1808
26700 CEFBS_None, // M2_mpy_acc_sat_hl_s0 = 1809
26701 CEFBS_None, // M2_mpy_acc_sat_hl_s1 = 1810
26702 CEFBS_None, // M2_mpy_acc_sat_lh_s0 = 1811
26703 CEFBS_None, // M2_mpy_acc_sat_lh_s1 = 1812
26704 CEFBS_None, // M2_mpy_acc_sat_ll_s0 = 1813
26705 CEFBS_None, // M2_mpy_acc_sat_ll_s1 = 1814
26706 CEFBS_None, // M2_mpy_hh_s0 = 1815
26707 CEFBS_None, // M2_mpy_hh_s1 = 1816
26708 CEFBS_None, // M2_mpy_hl_s0 = 1817
26709 CEFBS_None, // M2_mpy_hl_s1 = 1818
26710 CEFBS_None, // M2_mpy_lh_s0 = 1819
26711 CEFBS_None, // M2_mpy_lh_s1 = 1820
26712 CEFBS_None, // M2_mpy_ll_s0 = 1821
26713 CEFBS_None, // M2_mpy_ll_s1 = 1822
26714 CEFBS_None, // M2_mpy_nac_hh_s0 = 1823
26715 CEFBS_None, // M2_mpy_nac_hh_s1 = 1824
26716 CEFBS_None, // M2_mpy_nac_hl_s0 = 1825
26717 CEFBS_None, // M2_mpy_nac_hl_s1 = 1826
26718 CEFBS_None, // M2_mpy_nac_lh_s0 = 1827
26719 CEFBS_None, // M2_mpy_nac_lh_s1 = 1828
26720 CEFBS_None, // M2_mpy_nac_ll_s0 = 1829
26721 CEFBS_None, // M2_mpy_nac_ll_s1 = 1830
26722 CEFBS_None, // M2_mpy_nac_sat_hh_s0 = 1831
26723 CEFBS_None, // M2_mpy_nac_sat_hh_s1 = 1832
26724 CEFBS_None, // M2_mpy_nac_sat_hl_s0 = 1833
26725 CEFBS_None, // M2_mpy_nac_sat_hl_s1 = 1834
26726 CEFBS_None, // M2_mpy_nac_sat_lh_s0 = 1835
26727 CEFBS_None, // M2_mpy_nac_sat_lh_s1 = 1836
26728 CEFBS_None, // M2_mpy_nac_sat_ll_s0 = 1837
26729 CEFBS_None, // M2_mpy_nac_sat_ll_s1 = 1838
26730 CEFBS_None, // M2_mpy_rnd_hh_s0 = 1839
26731 CEFBS_None, // M2_mpy_rnd_hh_s1 = 1840
26732 CEFBS_None, // M2_mpy_rnd_hl_s0 = 1841
26733 CEFBS_None, // M2_mpy_rnd_hl_s1 = 1842
26734 CEFBS_None, // M2_mpy_rnd_lh_s0 = 1843
26735 CEFBS_None, // M2_mpy_rnd_lh_s1 = 1844
26736 CEFBS_None, // M2_mpy_rnd_ll_s0 = 1845
26737 CEFBS_None, // M2_mpy_rnd_ll_s1 = 1846
26738 CEFBS_None, // M2_mpy_sat_hh_s0 = 1847
26739 CEFBS_None, // M2_mpy_sat_hh_s1 = 1848
26740 CEFBS_None, // M2_mpy_sat_hl_s0 = 1849
26741 CEFBS_None, // M2_mpy_sat_hl_s1 = 1850
26742 CEFBS_None, // M2_mpy_sat_lh_s0 = 1851
26743 CEFBS_None, // M2_mpy_sat_lh_s1 = 1852
26744 CEFBS_None, // M2_mpy_sat_ll_s0 = 1853
26745 CEFBS_None, // M2_mpy_sat_ll_s1 = 1854
26746 CEFBS_None, // M2_mpy_sat_rnd_hh_s0 = 1855
26747 CEFBS_None, // M2_mpy_sat_rnd_hh_s1 = 1856
26748 CEFBS_None, // M2_mpy_sat_rnd_hl_s0 = 1857
26749 CEFBS_None, // M2_mpy_sat_rnd_hl_s1 = 1858
26750 CEFBS_None, // M2_mpy_sat_rnd_lh_s0 = 1859
26751 CEFBS_None, // M2_mpy_sat_rnd_lh_s1 = 1860
26752 CEFBS_None, // M2_mpy_sat_rnd_ll_s0 = 1861
26753 CEFBS_None, // M2_mpy_sat_rnd_ll_s1 = 1862
26754 CEFBS_None, // M2_mpy_up = 1863
26755 CEFBS_None, // M2_mpy_up_s1 = 1864
26756 CEFBS_None, // M2_mpy_up_s1_sat = 1865
26757 CEFBS_None, // M2_mpyd_acc_hh_s0 = 1866
26758 CEFBS_None, // M2_mpyd_acc_hh_s1 = 1867
26759 CEFBS_None, // M2_mpyd_acc_hl_s0 = 1868
26760 CEFBS_None, // M2_mpyd_acc_hl_s1 = 1869
26761 CEFBS_None, // M2_mpyd_acc_lh_s0 = 1870
26762 CEFBS_None, // M2_mpyd_acc_lh_s1 = 1871
26763 CEFBS_None, // M2_mpyd_acc_ll_s0 = 1872
26764 CEFBS_None, // M2_mpyd_acc_ll_s1 = 1873
26765 CEFBS_None, // M2_mpyd_hh_s0 = 1874
26766 CEFBS_None, // M2_mpyd_hh_s1 = 1875
26767 CEFBS_None, // M2_mpyd_hl_s0 = 1876
26768 CEFBS_None, // M2_mpyd_hl_s1 = 1877
26769 CEFBS_None, // M2_mpyd_lh_s0 = 1878
26770 CEFBS_None, // M2_mpyd_lh_s1 = 1879
26771 CEFBS_None, // M2_mpyd_ll_s0 = 1880
26772 CEFBS_None, // M2_mpyd_ll_s1 = 1881
26773 CEFBS_None, // M2_mpyd_nac_hh_s0 = 1882
26774 CEFBS_None, // M2_mpyd_nac_hh_s1 = 1883
26775 CEFBS_None, // M2_mpyd_nac_hl_s0 = 1884
26776 CEFBS_None, // M2_mpyd_nac_hl_s1 = 1885
26777 CEFBS_None, // M2_mpyd_nac_lh_s0 = 1886
26778 CEFBS_None, // M2_mpyd_nac_lh_s1 = 1887
26779 CEFBS_None, // M2_mpyd_nac_ll_s0 = 1888
26780 CEFBS_None, // M2_mpyd_nac_ll_s1 = 1889
26781 CEFBS_None, // M2_mpyd_rnd_hh_s0 = 1890
26782 CEFBS_None, // M2_mpyd_rnd_hh_s1 = 1891
26783 CEFBS_None, // M2_mpyd_rnd_hl_s0 = 1892
26784 CEFBS_None, // M2_mpyd_rnd_hl_s1 = 1893
26785 CEFBS_None, // M2_mpyd_rnd_lh_s0 = 1894
26786 CEFBS_None, // M2_mpyd_rnd_lh_s1 = 1895
26787 CEFBS_None, // M2_mpyd_rnd_ll_s0 = 1896
26788 CEFBS_None, // M2_mpyd_rnd_ll_s1 = 1897
26789 CEFBS_None, // M2_mpyi = 1898
26790 CEFBS_None, // M2_mpysin = 1899
26791 CEFBS_None, // M2_mpysip = 1900
26792 CEFBS_None, // M2_mpysu_up = 1901
26793 CEFBS_None, // M2_mpyu_acc_hh_s0 = 1902
26794 CEFBS_None, // M2_mpyu_acc_hh_s1 = 1903
26795 CEFBS_None, // M2_mpyu_acc_hl_s0 = 1904
26796 CEFBS_None, // M2_mpyu_acc_hl_s1 = 1905
26797 CEFBS_None, // M2_mpyu_acc_lh_s0 = 1906
26798 CEFBS_None, // M2_mpyu_acc_lh_s1 = 1907
26799 CEFBS_None, // M2_mpyu_acc_ll_s0 = 1908
26800 CEFBS_None, // M2_mpyu_acc_ll_s1 = 1909
26801 CEFBS_None, // M2_mpyu_hh_s0 = 1910
26802 CEFBS_None, // M2_mpyu_hh_s1 = 1911
26803 CEFBS_None, // M2_mpyu_hl_s0 = 1912
26804 CEFBS_None, // M2_mpyu_hl_s1 = 1913
26805 CEFBS_None, // M2_mpyu_lh_s0 = 1914
26806 CEFBS_None, // M2_mpyu_lh_s1 = 1915
26807 CEFBS_None, // M2_mpyu_ll_s0 = 1916
26808 CEFBS_None, // M2_mpyu_ll_s1 = 1917
26809 CEFBS_None, // M2_mpyu_nac_hh_s0 = 1918
26810 CEFBS_None, // M2_mpyu_nac_hh_s1 = 1919
26811 CEFBS_None, // M2_mpyu_nac_hl_s0 = 1920
26812 CEFBS_None, // M2_mpyu_nac_hl_s1 = 1921
26813 CEFBS_None, // M2_mpyu_nac_lh_s0 = 1922
26814 CEFBS_None, // M2_mpyu_nac_lh_s1 = 1923
26815 CEFBS_None, // M2_mpyu_nac_ll_s0 = 1924
26816 CEFBS_None, // M2_mpyu_nac_ll_s1 = 1925
26817 CEFBS_None, // M2_mpyu_up = 1926
26818 CEFBS_None, // M2_mpyud_acc_hh_s0 = 1927
26819 CEFBS_None, // M2_mpyud_acc_hh_s1 = 1928
26820 CEFBS_None, // M2_mpyud_acc_hl_s0 = 1929
26821 CEFBS_None, // M2_mpyud_acc_hl_s1 = 1930
26822 CEFBS_None, // M2_mpyud_acc_lh_s0 = 1931
26823 CEFBS_None, // M2_mpyud_acc_lh_s1 = 1932
26824 CEFBS_None, // M2_mpyud_acc_ll_s0 = 1933
26825 CEFBS_None, // M2_mpyud_acc_ll_s1 = 1934
26826 CEFBS_None, // M2_mpyud_hh_s0 = 1935
26827 CEFBS_None, // M2_mpyud_hh_s1 = 1936
26828 CEFBS_None, // M2_mpyud_hl_s0 = 1937
26829 CEFBS_None, // M2_mpyud_hl_s1 = 1938
26830 CEFBS_None, // M2_mpyud_lh_s0 = 1939
26831 CEFBS_None, // M2_mpyud_lh_s1 = 1940
26832 CEFBS_None, // M2_mpyud_ll_s0 = 1941
26833 CEFBS_None, // M2_mpyud_ll_s1 = 1942
26834 CEFBS_None, // M2_mpyud_nac_hh_s0 = 1943
26835 CEFBS_None, // M2_mpyud_nac_hh_s1 = 1944
26836 CEFBS_None, // M2_mpyud_nac_hl_s0 = 1945
26837 CEFBS_None, // M2_mpyud_nac_hl_s1 = 1946
26838 CEFBS_None, // M2_mpyud_nac_lh_s0 = 1947
26839 CEFBS_None, // M2_mpyud_nac_lh_s1 = 1948
26840 CEFBS_None, // M2_mpyud_nac_ll_s0 = 1949
26841 CEFBS_None, // M2_mpyud_nac_ll_s1 = 1950
26842 CEFBS_None, // M2_nacci = 1951
26843 CEFBS_None, // M2_naccii = 1952
26844 CEFBS_None, // M2_subacc = 1953
26845 CEFBS_None, // M2_vabsdiffh = 1954
26846 CEFBS_None, // M2_vabsdiffw = 1955
26847 CEFBS_None, // M2_vcmac_s0_sat_i = 1956
26848 CEFBS_None, // M2_vcmac_s0_sat_r = 1957
26849 CEFBS_None, // M2_vcmpy_s0_sat_i = 1958
26850 CEFBS_None, // M2_vcmpy_s0_sat_r = 1959
26851 CEFBS_None, // M2_vcmpy_s1_sat_i = 1960
26852 CEFBS_None, // M2_vcmpy_s1_sat_r = 1961
26853 CEFBS_None, // M2_vdmacs_s0 = 1962
26854 CEFBS_None, // M2_vdmacs_s1 = 1963
26855 CEFBS_None, // M2_vdmpyrs_s0 = 1964
26856 CEFBS_None, // M2_vdmpyrs_s1 = 1965
26857 CEFBS_None, // M2_vdmpys_s0 = 1966
26858 CEFBS_None, // M2_vdmpys_s1 = 1967
26859 CEFBS_None, // M2_vmac2 = 1968
26860 CEFBS_None, // M2_vmac2es = 1969
26861 CEFBS_None, // M2_vmac2es_s0 = 1970
26862 CEFBS_None, // M2_vmac2es_s1 = 1971
26863 CEFBS_None, // M2_vmac2s_s0 = 1972
26864 CEFBS_None, // M2_vmac2s_s1 = 1973
26865 CEFBS_None, // M2_vmac2su_s0 = 1974
26866 CEFBS_None, // M2_vmac2su_s1 = 1975
26867 CEFBS_None, // M2_vmpy2es_s0 = 1976
26868 CEFBS_None, // M2_vmpy2es_s1 = 1977
26869 CEFBS_None, // M2_vmpy2s_s0 = 1978
26870 CEFBS_None, // M2_vmpy2s_s0pack = 1979
26871 CEFBS_None, // M2_vmpy2s_s1 = 1980
26872 CEFBS_None, // M2_vmpy2s_s1pack = 1981
26873 CEFBS_None, // M2_vmpy2su_s0 = 1982
26874 CEFBS_None, // M2_vmpy2su_s1 = 1983
26875 CEFBS_None, // M2_vraddh = 1984
26876 CEFBS_None, // M2_vradduh = 1985
26877 CEFBS_None, // M2_vrcmaci_s0 = 1986
26878 CEFBS_None, // M2_vrcmaci_s0c = 1987
26879 CEFBS_None, // M2_vrcmacr_s0 = 1988
26880 CEFBS_None, // M2_vrcmacr_s0c = 1989
26881 CEFBS_None, // M2_vrcmpyi_s0 = 1990
26882 CEFBS_None, // M2_vrcmpyi_s0c = 1991
26883 CEFBS_None, // M2_vrcmpyr_s0 = 1992
26884 CEFBS_None, // M2_vrcmpyr_s0c = 1993
26885 CEFBS_None, // M2_vrcmpys_acc_s1_h = 1994
26886 CEFBS_None, // M2_vrcmpys_acc_s1_l = 1995
26887 CEFBS_None, // M2_vrcmpys_s1_h = 1996
26888 CEFBS_None, // M2_vrcmpys_s1_l = 1997
26889 CEFBS_None, // M2_vrcmpys_s1rp_h = 1998
26890 CEFBS_None, // M2_vrcmpys_s1rp_l = 1999
26891 CEFBS_None, // M2_vrmac_s0 = 2000
26892 CEFBS_None, // M2_vrmpy_s0 = 2001
26893 CEFBS_None, // M2_xor_xacc = 2002
26894 CEFBS_None, // M4_and_and = 2003
26895 CEFBS_None, // M4_and_andn = 2004
26896 CEFBS_None, // M4_and_or = 2005
26897 CEFBS_None, // M4_and_xor = 2006
26898 CEFBS_None, // M4_cmpyi_wh = 2007
26899 CEFBS_None, // M4_cmpyi_whc = 2008
26900 CEFBS_None, // M4_cmpyr_wh = 2009
26901 CEFBS_None, // M4_cmpyr_whc = 2010
26902 CEFBS_None, // M4_mac_up_s1_sat = 2011
26903 CEFBS_None, // M4_mpyri_addi = 2012
26904 CEFBS_None, // M4_mpyri_addr = 2013
26905 CEFBS_None, // M4_mpyri_addr_u2 = 2014
26906 CEFBS_None, // M4_mpyrr_addi = 2015
26907 CEFBS_None, // M4_mpyrr_addr = 2016
26908 CEFBS_None, // M4_nac_up_s1_sat = 2017
26909 CEFBS_None, // M4_or_and = 2018
26910 CEFBS_None, // M4_or_andn = 2019
26911 CEFBS_None, // M4_or_or = 2020
26912 CEFBS_None, // M4_or_xor = 2021
26913 CEFBS_None, // M4_pmpyw = 2022
26914 CEFBS_None, // M4_pmpyw_acc = 2023
26915 CEFBS_None, // M4_vpmpyh = 2024
26916 CEFBS_None, // M4_vpmpyh_acc = 2025
26917 CEFBS_None, // M4_vrmpyeh_acc_s0 = 2026
26918 CEFBS_None, // M4_vrmpyeh_acc_s1 = 2027
26919 CEFBS_None, // M4_vrmpyeh_s0 = 2028
26920 CEFBS_None, // M4_vrmpyeh_s1 = 2029
26921 CEFBS_None, // M4_vrmpyoh_acc_s0 = 2030
26922 CEFBS_None, // M4_vrmpyoh_acc_s1 = 2031
26923 CEFBS_None, // M4_vrmpyoh_s0 = 2032
26924 CEFBS_None, // M4_vrmpyoh_s1 = 2033
26925 CEFBS_None, // M4_xor_and = 2034
26926 CEFBS_None, // M4_xor_andn = 2035
26927 CEFBS_None, // M4_xor_or = 2036
26928 CEFBS_None, // M4_xor_xacc = 2037
26929 CEFBS_None, // M5_vdmacbsu = 2038
26930 CEFBS_None, // M5_vdmpybsu = 2039
26931 CEFBS_None, // M5_vmacbsu = 2040
26932 CEFBS_None, // M5_vmacbuu = 2041
26933 CEFBS_None, // M5_vmpybsu = 2042
26934 CEFBS_None, // M5_vmpybuu = 2043
26935 CEFBS_None, // M5_vrmacbsu = 2044
26936 CEFBS_None, // M5_vrmacbuu = 2045
26937 CEFBS_None, // M5_vrmpybsu = 2046
26938 CEFBS_None, // M5_vrmpybuu = 2047
26939 CEFBS_HasV62, // M6_vabsdiffb = 2048
26940 CEFBS_HasV62, // M6_vabsdiffub = 2049
26941 CEFBS_HasV67_UseAudio, // M7_dcmpyiw = 2050
26942 CEFBS_HasV67_UseAudio, // M7_dcmpyiw_acc = 2051
26943 CEFBS_HasV67_UseAudio, // M7_dcmpyiwc = 2052
26944 CEFBS_HasV67_UseAudio, // M7_dcmpyiwc_acc = 2053
26945 CEFBS_HasV67_UseAudio, // M7_dcmpyrw = 2054
26946 CEFBS_HasV67_UseAudio, // M7_dcmpyrw_acc = 2055
26947 CEFBS_HasV67_UseAudio, // M7_dcmpyrwc = 2056
26948 CEFBS_HasV67_UseAudio, // M7_dcmpyrwc_acc = 2057
26949 CEFBS_HasV67_UseAudio, // M7_wcmpyiw = 2058
26950 CEFBS_HasV67_UseAudio, // M7_wcmpyiw_rnd = 2059
26951 CEFBS_HasV67_UseAudio, // M7_wcmpyiwc = 2060
26952 CEFBS_HasV67_UseAudio, // M7_wcmpyiwc_rnd = 2061
26953 CEFBS_HasV67_UseAudio, // M7_wcmpyrw = 2062
26954 CEFBS_HasV67_UseAudio, // M7_wcmpyrw_rnd = 2063
26955 CEFBS_HasV67_UseAudio, // M7_wcmpyrwc = 2064
26956 CEFBS_HasV67_UseAudio, // M7_wcmpyrwc_rnd = 2065
26957 CEFBS_None, // PS_call_stk = 2066
26958 CEFBS_None, // PS_callr_nr = 2067
26959 CEFBS_None, // PS_jmpret = 2068
26960 CEFBS_None, // PS_jmpretf = 2069
26961 CEFBS_None, // PS_jmpretfnew = 2070
26962 CEFBS_None, // PS_jmpretfnewpt = 2071
26963 CEFBS_None, // PS_jmprett = 2072
26964 CEFBS_None, // PS_jmprettnew = 2073
26965 CEFBS_None, // PS_jmprettnewpt = 2074
26966 CEFBS_None, // PS_loadrbabs = 2075
26967 CEFBS_None, // PS_loadrdabs = 2076
26968 CEFBS_None, // PS_loadrhabs = 2077
26969 CEFBS_None, // PS_loadriabs = 2078
26970 CEFBS_None, // PS_loadrubabs = 2079
26971 CEFBS_None, // PS_loadruhabs = 2080
26972 CEFBS_None, // PS_storerbabs = 2081
26973 CEFBS_None, // PS_storerbnewabs = 2082
26974 CEFBS_None, // PS_storerdabs = 2083
26975 CEFBS_None, // PS_storerfabs = 2084
26976 CEFBS_None, // PS_storerhabs = 2085
26977 CEFBS_None, // PS_storerhnewabs = 2086
26978 CEFBS_None, // PS_storeriabs = 2087
26979 CEFBS_None, // PS_storerinewabs = 2088
26980 CEFBS_HasPreV65, // PS_trap1 = 2089
26981 CEFBS_HasV68, // R6_release_at_vi = 2090
26982 CEFBS_HasV68, // R6_release_st_vi = 2091
26983 CEFBS_None, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4 = 2092
26984 CEFBS_None, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT = 2093
26985 CEFBS_None, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC = 2094
26986 CEFBS_None, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC = 2095
26987 CEFBS_None, // RESTORE_DEALLOC_RET_JMP_V4 = 2096
26988 CEFBS_None, // RESTORE_DEALLOC_RET_JMP_V4_EXT = 2097
26989 CEFBS_None, // RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC = 2098
26990 CEFBS_None, // RESTORE_DEALLOC_RET_JMP_V4_PIC = 2099
26991 CEFBS_None, // S2_addasl_rrri = 2100
26992 CEFBS_None, // S2_allocframe = 2101
26993 CEFBS_None, // S2_asl_i_p = 2102
26994 CEFBS_None, // S2_asl_i_p_acc = 2103
26995 CEFBS_None, // S2_asl_i_p_and = 2104
26996 CEFBS_None, // S2_asl_i_p_nac = 2105
26997 CEFBS_None, // S2_asl_i_p_or = 2106
26998 CEFBS_None, // S2_asl_i_p_xacc = 2107
26999 CEFBS_None, // S2_asl_i_r = 2108
27000 CEFBS_None, // S2_asl_i_r_acc = 2109
27001 CEFBS_None, // S2_asl_i_r_and = 2110
27002 CEFBS_None, // S2_asl_i_r_nac = 2111
27003 CEFBS_None, // S2_asl_i_r_or = 2112
27004 CEFBS_None, // S2_asl_i_r_sat = 2113
27005 CEFBS_None, // S2_asl_i_r_xacc = 2114
27006 CEFBS_None, // S2_asl_i_vh = 2115
27007 CEFBS_None, // S2_asl_i_vw = 2116
27008 CEFBS_None, // S2_asl_r_p = 2117
27009 CEFBS_None, // S2_asl_r_p_acc = 2118
27010 CEFBS_None, // S2_asl_r_p_and = 2119
27011 CEFBS_None, // S2_asl_r_p_nac = 2120
27012 CEFBS_None, // S2_asl_r_p_or = 2121
27013 CEFBS_None, // S2_asl_r_p_xor = 2122
27014 CEFBS_None, // S2_asl_r_r = 2123
27015 CEFBS_None, // S2_asl_r_r_acc = 2124
27016 CEFBS_None, // S2_asl_r_r_and = 2125
27017 CEFBS_None, // S2_asl_r_r_nac = 2126
27018 CEFBS_None, // S2_asl_r_r_or = 2127
27019 CEFBS_None, // S2_asl_r_r_sat = 2128
27020 CEFBS_None, // S2_asl_r_vh = 2129
27021 CEFBS_None, // S2_asl_r_vw = 2130
27022 CEFBS_None, // S2_asr_i_p = 2131
27023 CEFBS_None, // S2_asr_i_p_acc = 2132
27024 CEFBS_None, // S2_asr_i_p_and = 2133
27025 CEFBS_None, // S2_asr_i_p_nac = 2134
27026 CEFBS_None, // S2_asr_i_p_or = 2135
27027 CEFBS_None, // S2_asr_i_p_rnd = 2136
27028 CEFBS_None, // S2_asr_i_r = 2137
27029 CEFBS_None, // S2_asr_i_r_acc = 2138
27030 CEFBS_None, // S2_asr_i_r_and = 2139
27031 CEFBS_None, // S2_asr_i_r_nac = 2140
27032 CEFBS_None, // S2_asr_i_r_or = 2141
27033 CEFBS_None, // S2_asr_i_r_rnd = 2142
27034 CEFBS_None, // S2_asr_i_svw_trun = 2143
27035 CEFBS_None, // S2_asr_i_vh = 2144
27036 CEFBS_None, // S2_asr_i_vw = 2145
27037 CEFBS_None, // S2_asr_r_p = 2146
27038 CEFBS_None, // S2_asr_r_p_acc = 2147
27039 CEFBS_None, // S2_asr_r_p_and = 2148
27040 CEFBS_None, // S2_asr_r_p_nac = 2149
27041 CEFBS_None, // S2_asr_r_p_or = 2150
27042 CEFBS_None, // S2_asr_r_p_xor = 2151
27043 CEFBS_None, // S2_asr_r_r = 2152
27044 CEFBS_None, // S2_asr_r_r_acc = 2153
27045 CEFBS_None, // S2_asr_r_r_and = 2154
27046 CEFBS_None, // S2_asr_r_r_nac = 2155
27047 CEFBS_None, // S2_asr_r_r_or = 2156
27048 CEFBS_None, // S2_asr_r_r_sat = 2157
27049 CEFBS_None, // S2_asr_r_svw_trun = 2158
27050 CEFBS_None, // S2_asr_r_vh = 2159
27051 CEFBS_None, // S2_asr_r_vw = 2160
27052 CEFBS_None, // S2_brev = 2161
27053 CEFBS_None, // S2_brevp = 2162
27054 CEFBS_UseCabac, // S2_cabacdecbin = 2163
27055 CEFBS_None, // S2_cl0 = 2164
27056 CEFBS_None, // S2_cl0p = 2165
27057 CEFBS_None, // S2_cl1 = 2166
27058 CEFBS_None, // S2_cl1p = 2167
27059 CEFBS_None, // S2_clb = 2168
27060 CEFBS_None, // S2_clbnorm = 2169
27061 CEFBS_None, // S2_clbp = 2170
27062 CEFBS_None, // S2_clrbit_i = 2171
27063 CEFBS_None, // S2_clrbit_r = 2172
27064 CEFBS_None, // S2_ct0 = 2173
27065 CEFBS_None, // S2_ct0p = 2174
27066 CEFBS_None, // S2_ct1 = 2175
27067 CEFBS_None, // S2_ct1p = 2176
27068 CEFBS_None, // S2_deinterleave = 2177
27069 CEFBS_None, // S2_extractu = 2178
27070 CEFBS_None, // S2_extractu_rp = 2179
27071 CEFBS_None, // S2_extractup = 2180
27072 CEFBS_None, // S2_extractup_rp = 2181
27073 CEFBS_None, // S2_insert = 2182
27074 CEFBS_None, // S2_insert_rp = 2183
27075 CEFBS_None, // S2_insertp = 2184
27076 CEFBS_None, // S2_insertp_rp = 2185
27077 CEFBS_None, // S2_interleave = 2186
27078 CEFBS_None, // S2_lfsp = 2187
27079 CEFBS_None, // S2_lsl_r_p = 2188
27080 CEFBS_None, // S2_lsl_r_p_acc = 2189
27081 CEFBS_None, // S2_lsl_r_p_and = 2190
27082 CEFBS_None, // S2_lsl_r_p_nac = 2191
27083 CEFBS_None, // S2_lsl_r_p_or = 2192
27084 CEFBS_None, // S2_lsl_r_p_xor = 2193
27085 CEFBS_None, // S2_lsl_r_r = 2194
27086 CEFBS_None, // S2_lsl_r_r_acc = 2195
27087 CEFBS_None, // S2_lsl_r_r_and = 2196
27088 CEFBS_None, // S2_lsl_r_r_nac = 2197
27089 CEFBS_None, // S2_lsl_r_r_or = 2198
27090 CEFBS_None, // S2_lsl_r_vh = 2199
27091 CEFBS_None, // S2_lsl_r_vw = 2200
27092 CEFBS_None, // S2_lsr_i_p = 2201
27093 CEFBS_None, // S2_lsr_i_p_acc = 2202
27094 CEFBS_None, // S2_lsr_i_p_and = 2203
27095 CEFBS_None, // S2_lsr_i_p_nac = 2204
27096 CEFBS_None, // S2_lsr_i_p_or = 2205
27097 CEFBS_None, // S2_lsr_i_p_xacc = 2206
27098 CEFBS_None, // S2_lsr_i_r = 2207
27099 CEFBS_None, // S2_lsr_i_r_acc = 2208
27100 CEFBS_None, // S2_lsr_i_r_and = 2209
27101 CEFBS_None, // S2_lsr_i_r_nac = 2210
27102 CEFBS_None, // S2_lsr_i_r_or = 2211
27103 CEFBS_None, // S2_lsr_i_r_xacc = 2212
27104 CEFBS_None, // S2_lsr_i_vh = 2213
27105 CEFBS_None, // S2_lsr_i_vw = 2214
27106 CEFBS_None, // S2_lsr_r_p = 2215
27107 CEFBS_None, // S2_lsr_r_p_acc = 2216
27108 CEFBS_None, // S2_lsr_r_p_and = 2217
27109 CEFBS_None, // S2_lsr_r_p_nac = 2218
27110 CEFBS_None, // S2_lsr_r_p_or = 2219
27111 CEFBS_None, // S2_lsr_r_p_xor = 2220
27112 CEFBS_None, // S2_lsr_r_r = 2221
27113 CEFBS_None, // S2_lsr_r_r_acc = 2222
27114 CEFBS_None, // S2_lsr_r_r_and = 2223
27115 CEFBS_None, // S2_lsr_r_r_nac = 2224
27116 CEFBS_None, // S2_lsr_r_r_or = 2225
27117 CEFBS_None, // S2_lsr_r_vh = 2226
27118 CEFBS_None, // S2_lsr_r_vw = 2227
27119 CEFBS_HasV66, // S2_mask = 2228
27120 CEFBS_None, // S2_packhl = 2229
27121 CEFBS_None, // S2_parityp = 2230
27122 CEFBS_None, // S2_pstorerbf_io = 2231
27123 CEFBS_None, // S2_pstorerbf_pi = 2232
27124 CEFBS_None, // S2_pstorerbfnew_pi = 2233
27125 CEFBS_None, // S2_pstorerbnewf_io = 2234
27126 CEFBS_None, // S2_pstorerbnewf_pi = 2235
27127 CEFBS_None, // S2_pstorerbnewfnew_pi = 2236
27128 CEFBS_None, // S2_pstorerbnewt_io = 2237
27129 CEFBS_None, // S2_pstorerbnewt_pi = 2238
27130 CEFBS_None, // S2_pstorerbnewtnew_pi = 2239
27131 CEFBS_None, // S2_pstorerbt_io = 2240
27132 CEFBS_None, // S2_pstorerbt_pi = 2241
27133 CEFBS_None, // S2_pstorerbtnew_pi = 2242
27134 CEFBS_None, // S2_pstorerdf_io = 2243
27135 CEFBS_None, // S2_pstorerdf_pi = 2244
27136 CEFBS_None, // S2_pstorerdfnew_pi = 2245
27137 CEFBS_None, // S2_pstorerdt_io = 2246
27138 CEFBS_None, // S2_pstorerdt_pi = 2247
27139 CEFBS_None, // S2_pstorerdtnew_pi = 2248
27140 CEFBS_None, // S2_pstorerff_io = 2249
27141 CEFBS_None, // S2_pstorerff_pi = 2250
27142 CEFBS_None, // S2_pstorerffnew_pi = 2251
27143 CEFBS_None, // S2_pstorerft_io = 2252
27144 CEFBS_None, // S2_pstorerft_pi = 2253
27145 CEFBS_None, // S2_pstorerftnew_pi = 2254
27146 CEFBS_None, // S2_pstorerhf_io = 2255
27147 CEFBS_None, // S2_pstorerhf_pi = 2256
27148 CEFBS_None, // S2_pstorerhfnew_pi = 2257
27149 CEFBS_None, // S2_pstorerhnewf_io = 2258
27150 CEFBS_None, // S2_pstorerhnewf_pi = 2259
27151 CEFBS_None, // S2_pstorerhnewfnew_pi = 2260
27152 CEFBS_None, // S2_pstorerhnewt_io = 2261
27153 CEFBS_None, // S2_pstorerhnewt_pi = 2262
27154 CEFBS_None, // S2_pstorerhnewtnew_pi = 2263
27155 CEFBS_None, // S2_pstorerht_io = 2264
27156 CEFBS_None, // S2_pstorerht_pi = 2265
27157 CEFBS_None, // S2_pstorerhtnew_pi = 2266
27158 CEFBS_None, // S2_pstorerif_io = 2267
27159 CEFBS_None, // S2_pstorerif_pi = 2268
27160 CEFBS_None, // S2_pstorerifnew_pi = 2269
27161 CEFBS_None, // S2_pstorerinewf_io = 2270
27162 CEFBS_None, // S2_pstorerinewf_pi = 2271
27163 CEFBS_None, // S2_pstorerinewfnew_pi = 2272
27164 CEFBS_None, // S2_pstorerinewt_io = 2273
27165 CEFBS_None, // S2_pstorerinewt_pi = 2274
27166 CEFBS_None, // S2_pstorerinewtnew_pi = 2275
27167 CEFBS_None, // S2_pstorerit_io = 2276
27168 CEFBS_None, // S2_pstorerit_pi = 2277
27169 CEFBS_None, // S2_pstoreritnew_pi = 2278
27170 CEFBS_None, // S2_setbit_i = 2279
27171 CEFBS_None, // S2_setbit_r = 2280
27172 CEFBS_None, // S2_shuffeb = 2281
27173 CEFBS_None, // S2_shuffeh = 2282
27174 CEFBS_None, // S2_shuffob = 2283
27175 CEFBS_None, // S2_shuffoh = 2284
27176 CEFBS_None, // S2_storerb_io = 2285
27177 CEFBS_None, // S2_storerb_pbr = 2286
27178 CEFBS_None, // S2_storerb_pci = 2287
27179 CEFBS_None, // S2_storerb_pcr = 2288
27180 CEFBS_None, // S2_storerb_pi = 2289
27181 CEFBS_None, // S2_storerb_pr = 2290
27182 CEFBS_None, // S2_storerbgp = 2291
27183 CEFBS_None, // S2_storerbnew_io = 2292
27184 CEFBS_None, // S2_storerbnew_pbr = 2293
27185 CEFBS_None, // S2_storerbnew_pci = 2294
27186 CEFBS_None, // S2_storerbnew_pcr = 2295
27187 CEFBS_None, // S2_storerbnew_pi = 2296
27188 CEFBS_None, // S2_storerbnew_pr = 2297
27189 CEFBS_None, // S2_storerbnewgp = 2298
27190 CEFBS_None, // S2_storerd_io = 2299
27191 CEFBS_None, // S2_storerd_pbr = 2300
27192 CEFBS_None, // S2_storerd_pci = 2301
27193 CEFBS_None, // S2_storerd_pcr = 2302
27194 CEFBS_None, // S2_storerd_pi = 2303
27195 CEFBS_None, // S2_storerd_pr = 2304
27196 CEFBS_None, // S2_storerdgp = 2305
27197 CEFBS_None, // S2_storerf_io = 2306
27198 CEFBS_None, // S2_storerf_pbr = 2307
27199 CEFBS_None, // S2_storerf_pci = 2308
27200 CEFBS_None, // S2_storerf_pcr = 2309
27201 CEFBS_None, // S2_storerf_pi = 2310
27202 CEFBS_None, // S2_storerf_pr = 2311
27203 CEFBS_None, // S2_storerfgp = 2312
27204 CEFBS_None, // S2_storerh_io = 2313
27205 CEFBS_None, // S2_storerh_pbr = 2314
27206 CEFBS_None, // S2_storerh_pci = 2315
27207 CEFBS_None, // S2_storerh_pcr = 2316
27208 CEFBS_None, // S2_storerh_pi = 2317
27209 CEFBS_None, // S2_storerh_pr = 2318
27210 CEFBS_None, // S2_storerhgp = 2319
27211 CEFBS_None, // S2_storerhnew_io = 2320
27212 CEFBS_None, // S2_storerhnew_pbr = 2321
27213 CEFBS_None, // S2_storerhnew_pci = 2322
27214 CEFBS_None, // S2_storerhnew_pcr = 2323
27215 CEFBS_None, // S2_storerhnew_pi = 2324
27216 CEFBS_None, // S2_storerhnew_pr = 2325
27217 CEFBS_None, // S2_storerhnewgp = 2326
27218 CEFBS_None, // S2_storeri_io = 2327
27219 CEFBS_None, // S2_storeri_pbr = 2328
27220 CEFBS_None, // S2_storeri_pci = 2329
27221 CEFBS_None, // S2_storeri_pcr = 2330
27222 CEFBS_None, // S2_storeri_pi = 2331
27223 CEFBS_None, // S2_storeri_pr = 2332
27224 CEFBS_None, // S2_storerigp = 2333
27225 CEFBS_None, // S2_storerinew_io = 2334
27226 CEFBS_None, // S2_storerinew_pbr = 2335
27227 CEFBS_None, // S2_storerinew_pci = 2336
27228 CEFBS_None, // S2_storerinew_pcr = 2337
27229 CEFBS_None, // S2_storerinew_pi = 2338
27230 CEFBS_None, // S2_storerinew_pr = 2339
27231 CEFBS_None, // S2_storerinewgp = 2340
27232 CEFBS_None, // S2_storew_locked = 2341
27233 CEFBS_HasV68, // S2_storew_rl_at_vi = 2342
27234 CEFBS_HasV68, // S2_storew_rl_st_vi = 2343
27235 CEFBS_None, // S2_svsathb = 2344
27236 CEFBS_None, // S2_svsathub = 2345
27237 CEFBS_None, // S2_tableidxb = 2346
27238 CEFBS_None, // S2_tableidxd = 2347
27239 CEFBS_None, // S2_tableidxh = 2348
27240 CEFBS_None, // S2_tableidxw = 2349
27241 CEFBS_None, // S2_togglebit_i = 2350
27242 CEFBS_None, // S2_togglebit_r = 2351
27243 CEFBS_None, // S2_tstbit_i = 2352
27244 CEFBS_None, // S2_tstbit_r = 2353
27245 CEFBS_None, // S2_valignib = 2354
27246 CEFBS_None, // S2_valignrb = 2355
27247 CEFBS_None, // S2_vcnegh = 2356
27248 CEFBS_None, // S2_vcrotate = 2357
27249 CEFBS_None, // S2_vrcnegh = 2358
27250 CEFBS_None, // S2_vrndpackwh = 2359
27251 CEFBS_None, // S2_vrndpackwhs = 2360
27252 CEFBS_None, // S2_vsathb = 2361
27253 CEFBS_None, // S2_vsathb_nopack = 2362
27254 CEFBS_None, // S2_vsathub = 2363
27255 CEFBS_None, // S2_vsathub_nopack = 2364
27256 CEFBS_None, // S2_vsatwh = 2365
27257 CEFBS_None, // S2_vsatwh_nopack = 2366
27258 CEFBS_None, // S2_vsatwuh = 2367
27259 CEFBS_None, // S2_vsatwuh_nopack = 2368
27260 CEFBS_None, // S2_vsplatrb = 2369
27261 CEFBS_None, // S2_vsplatrh = 2370
27262 CEFBS_None, // S2_vspliceib = 2371
27263 CEFBS_None, // S2_vsplicerb = 2372
27264 CEFBS_None, // S2_vsxtbh = 2373
27265 CEFBS_None, // S2_vsxthw = 2374
27266 CEFBS_None, // S2_vtrunehb = 2375
27267 CEFBS_None, // S2_vtrunewh = 2376
27268 CEFBS_None, // S2_vtrunohb = 2377
27269 CEFBS_None, // S2_vtrunowh = 2378
27270 CEFBS_None, // S2_vzxtbh = 2379
27271 CEFBS_None, // S2_vzxthw = 2380
27272 CEFBS_None, // S4_addaddi = 2381
27273 CEFBS_None, // S4_addi_asl_ri = 2382
27274 CEFBS_None, // S4_addi_lsr_ri = 2383
27275 CEFBS_None, // S4_andi_asl_ri = 2384
27276 CEFBS_None, // S4_andi_lsr_ri = 2385
27277 CEFBS_None, // S4_clbaddi = 2386
27278 CEFBS_None, // S4_clbpaddi = 2387
27279 CEFBS_None, // S4_clbpnorm = 2388
27280 CEFBS_None, // S4_extract = 2389
27281 CEFBS_None, // S4_extract_rp = 2390
27282 CEFBS_None, // S4_extractp = 2391
27283 CEFBS_None, // S4_extractp_rp = 2392
27284 CEFBS_None, // S4_lsli = 2393
27285 CEFBS_None, // S4_ntstbit_i = 2394
27286 CEFBS_None, // S4_ntstbit_r = 2395
27287 CEFBS_None, // S4_or_andi = 2396
27288 CEFBS_None, // S4_or_andix = 2397
27289 CEFBS_None, // S4_or_ori = 2398
27290 CEFBS_None, // S4_ori_asl_ri = 2399
27291 CEFBS_None, // S4_ori_lsr_ri = 2400
27292 CEFBS_None, // S4_parity = 2401
27293 CEFBS_None, // S4_pstorerbf_abs = 2402
27294 CEFBS_None, // S4_pstorerbf_rr = 2403
27295 CEFBS_None, // S4_pstorerbfnew_abs = 2404
27296 CEFBS_None, // S4_pstorerbfnew_io = 2405
27297 CEFBS_None, // S4_pstorerbfnew_rr = 2406
27298 CEFBS_None, // S4_pstorerbnewf_abs = 2407
27299 CEFBS_None, // S4_pstorerbnewf_rr = 2408
27300 CEFBS_None, // S4_pstorerbnewfnew_abs = 2409
27301 CEFBS_None, // S4_pstorerbnewfnew_io = 2410
27302 CEFBS_None, // S4_pstorerbnewfnew_rr = 2411
27303 CEFBS_None, // S4_pstorerbnewt_abs = 2412
27304 CEFBS_None, // S4_pstorerbnewt_rr = 2413
27305 CEFBS_None, // S4_pstorerbnewtnew_abs = 2414
27306 CEFBS_None, // S4_pstorerbnewtnew_io = 2415
27307 CEFBS_None, // S4_pstorerbnewtnew_rr = 2416
27308 CEFBS_None, // S4_pstorerbt_abs = 2417
27309 CEFBS_None, // S4_pstorerbt_rr = 2418
27310 CEFBS_None, // S4_pstorerbtnew_abs = 2419
27311 CEFBS_None, // S4_pstorerbtnew_io = 2420
27312 CEFBS_None, // S4_pstorerbtnew_rr = 2421
27313 CEFBS_None, // S4_pstorerdf_abs = 2422
27314 CEFBS_None, // S4_pstorerdf_rr = 2423
27315 CEFBS_None, // S4_pstorerdfnew_abs = 2424
27316 CEFBS_None, // S4_pstorerdfnew_io = 2425
27317 CEFBS_None, // S4_pstorerdfnew_rr = 2426
27318 CEFBS_None, // S4_pstorerdt_abs = 2427
27319 CEFBS_None, // S4_pstorerdt_rr = 2428
27320 CEFBS_None, // S4_pstorerdtnew_abs = 2429
27321 CEFBS_None, // S4_pstorerdtnew_io = 2430
27322 CEFBS_None, // S4_pstorerdtnew_rr = 2431
27323 CEFBS_None, // S4_pstorerff_abs = 2432
27324 CEFBS_None, // S4_pstorerff_rr = 2433
27325 CEFBS_None, // S4_pstorerffnew_abs = 2434
27326 CEFBS_None, // S4_pstorerffnew_io = 2435
27327 CEFBS_None, // S4_pstorerffnew_rr = 2436
27328 CEFBS_None, // S4_pstorerft_abs = 2437
27329 CEFBS_None, // S4_pstorerft_rr = 2438
27330 CEFBS_None, // S4_pstorerftnew_abs = 2439
27331 CEFBS_None, // S4_pstorerftnew_io = 2440
27332 CEFBS_None, // S4_pstorerftnew_rr = 2441
27333 CEFBS_None, // S4_pstorerhf_abs = 2442
27334 CEFBS_None, // S4_pstorerhf_rr = 2443
27335 CEFBS_None, // S4_pstorerhfnew_abs = 2444
27336 CEFBS_None, // S4_pstorerhfnew_io = 2445
27337 CEFBS_None, // S4_pstorerhfnew_rr = 2446
27338 CEFBS_None, // S4_pstorerhnewf_abs = 2447
27339 CEFBS_None, // S4_pstorerhnewf_rr = 2448
27340 CEFBS_None, // S4_pstorerhnewfnew_abs = 2449
27341 CEFBS_None, // S4_pstorerhnewfnew_io = 2450
27342 CEFBS_None, // S4_pstorerhnewfnew_rr = 2451
27343 CEFBS_None, // S4_pstorerhnewt_abs = 2452
27344 CEFBS_None, // S4_pstorerhnewt_rr = 2453
27345 CEFBS_None, // S4_pstorerhnewtnew_abs = 2454
27346 CEFBS_None, // S4_pstorerhnewtnew_io = 2455
27347 CEFBS_None, // S4_pstorerhnewtnew_rr = 2456
27348 CEFBS_None, // S4_pstorerht_abs = 2457
27349 CEFBS_None, // S4_pstorerht_rr = 2458
27350 CEFBS_None, // S4_pstorerhtnew_abs = 2459
27351 CEFBS_None, // S4_pstorerhtnew_io = 2460
27352 CEFBS_None, // S4_pstorerhtnew_rr = 2461
27353 CEFBS_None, // S4_pstorerif_abs = 2462
27354 CEFBS_None, // S4_pstorerif_rr = 2463
27355 CEFBS_None, // S4_pstorerifnew_abs = 2464
27356 CEFBS_None, // S4_pstorerifnew_io = 2465
27357 CEFBS_None, // S4_pstorerifnew_rr = 2466
27358 CEFBS_None, // S4_pstorerinewf_abs = 2467
27359 CEFBS_None, // S4_pstorerinewf_rr = 2468
27360 CEFBS_None, // S4_pstorerinewfnew_abs = 2469
27361 CEFBS_None, // S4_pstorerinewfnew_io = 2470
27362 CEFBS_None, // S4_pstorerinewfnew_rr = 2471
27363 CEFBS_None, // S4_pstorerinewt_abs = 2472
27364 CEFBS_None, // S4_pstorerinewt_rr = 2473
27365 CEFBS_None, // S4_pstorerinewtnew_abs = 2474
27366 CEFBS_None, // S4_pstorerinewtnew_io = 2475
27367 CEFBS_None, // S4_pstorerinewtnew_rr = 2476
27368 CEFBS_None, // S4_pstorerit_abs = 2477
27369 CEFBS_None, // S4_pstorerit_rr = 2478
27370 CEFBS_None, // S4_pstoreritnew_abs = 2479
27371 CEFBS_None, // S4_pstoreritnew_io = 2480
27372 CEFBS_None, // S4_pstoreritnew_rr = 2481
27373 CEFBS_None, // S4_stored_locked = 2482
27374 CEFBS_HasV68, // S4_stored_rl_at_vi = 2483
27375 CEFBS_HasV68, // S4_stored_rl_st_vi = 2484
27376 CEFBS_None, // S4_storeirb_io = 2485
27377 CEFBS_None, // S4_storeirbf_io = 2486
27378 CEFBS_None, // S4_storeirbfnew_io = 2487
27379 CEFBS_None, // S4_storeirbt_io = 2488
27380 CEFBS_None, // S4_storeirbtnew_io = 2489
27381 CEFBS_None, // S4_storeirh_io = 2490
27382 CEFBS_None, // S4_storeirhf_io = 2491
27383 CEFBS_None, // S4_storeirhfnew_io = 2492
27384 CEFBS_None, // S4_storeirht_io = 2493
27385 CEFBS_None, // S4_storeirhtnew_io = 2494
27386 CEFBS_None, // S4_storeiri_io = 2495
27387 CEFBS_None, // S4_storeirif_io = 2496
27388 CEFBS_None, // S4_storeirifnew_io = 2497
27389 CEFBS_None, // S4_storeirit_io = 2498
27390 CEFBS_None, // S4_storeiritnew_io = 2499
27391 CEFBS_None, // S4_storerb_ap = 2500
27392 CEFBS_None, // S4_storerb_rr = 2501
27393 CEFBS_None, // S4_storerb_ur = 2502
27394 CEFBS_None, // S4_storerbnew_ap = 2503
27395 CEFBS_None, // S4_storerbnew_rr = 2504
27396 CEFBS_None, // S4_storerbnew_ur = 2505
27397 CEFBS_None, // S4_storerd_ap = 2506
27398 CEFBS_None, // S4_storerd_rr = 2507
27399 CEFBS_None, // S4_storerd_ur = 2508
27400 CEFBS_None, // S4_storerf_ap = 2509
27401 CEFBS_None, // S4_storerf_rr = 2510
27402 CEFBS_None, // S4_storerf_ur = 2511
27403 CEFBS_None, // S4_storerh_ap = 2512
27404 CEFBS_None, // S4_storerh_rr = 2513
27405 CEFBS_None, // S4_storerh_ur = 2514
27406 CEFBS_None, // S4_storerhnew_ap = 2515
27407 CEFBS_None, // S4_storerhnew_rr = 2516
27408 CEFBS_None, // S4_storerhnew_ur = 2517
27409 CEFBS_None, // S4_storeri_ap = 2518
27410 CEFBS_None, // S4_storeri_rr = 2519
27411 CEFBS_None, // S4_storeri_ur = 2520
27412 CEFBS_None, // S4_storerinew_ap = 2521
27413 CEFBS_None, // S4_storerinew_rr = 2522
27414 CEFBS_None, // S4_storerinew_ur = 2523
27415 CEFBS_None, // S4_subaddi = 2524
27416 CEFBS_None, // S4_subi_asl_ri = 2525
27417 CEFBS_None, // S4_subi_lsr_ri = 2526
27418 CEFBS_None, // S4_vrcrotate = 2527
27419 CEFBS_None, // S4_vrcrotate_acc = 2528
27420 CEFBS_None, // S4_vxaddsubh = 2529
27421 CEFBS_None, // S4_vxaddsubhr = 2530
27422 CEFBS_None, // S4_vxaddsubw = 2531
27423 CEFBS_None, // S4_vxsubaddh = 2532
27424 CEFBS_None, // S4_vxsubaddhr = 2533
27425 CEFBS_None, // S4_vxsubaddw = 2534
27426 CEFBS_None, // S5_asrhub_rnd_sat = 2535
27427 CEFBS_None, // S5_asrhub_sat = 2536
27428 CEFBS_None, // S5_popcountp = 2537
27429 CEFBS_None, // S5_vasrhrnd = 2538
27430 CEFBS_HasV60, // S6_rol_i_p = 2539
27431 CEFBS_HasV60, // S6_rol_i_p_acc = 2540
27432 CEFBS_HasV60, // S6_rol_i_p_and = 2541
27433 CEFBS_HasV60, // S6_rol_i_p_nac = 2542
27434 CEFBS_HasV60, // S6_rol_i_p_or = 2543
27435 CEFBS_HasV60, // S6_rol_i_p_xacc = 2544
27436 CEFBS_HasV60, // S6_rol_i_r = 2545
27437 CEFBS_HasV60, // S6_rol_i_r_acc = 2546
27438 CEFBS_HasV60, // S6_rol_i_r_and = 2547
27439 CEFBS_HasV60, // S6_rol_i_r_nac = 2548
27440 CEFBS_HasV60, // S6_rol_i_r_or = 2549
27441 CEFBS_HasV60, // S6_rol_i_r_xacc = 2550
27442 CEFBS_HasV62, // S6_vsplatrbp = 2551
27443 CEFBS_HasV62, // S6_vtrunehb_ppp = 2552
27444 CEFBS_HasV62, // S6_vtrunohb_ppp = 2553
27445 CEFBS_None, // SA1_addi = 2554
27446 CEFBS_None, // SA1_addrx = 2555
27447 CEFBS_None, // SA1_addsp = 2556
27448 CEFBS_None, // SA1_and1 = 2557
27449 CEFBS_None, // SA1_clrf = 2558
27450 CEFBS_None, // SA1_clrfnew = 2559
27451 CEFBS_None, // SA1_clrt = 2560
27452 CEFBS_None, // SA1_clrtnew = 2561
27453 CEFBS_None, // SA1_cmpeqi = 2562
27454 CEFBS_None, // SA1_combine0i = 2563
27455 CEFBS_None, // SA1_combine1i = 2564
27456 CEFBS_None, // SA1_combine2i = 2565
27457 CEFBS_None, // SA1_combine3i = 2566
27458 CEFBS_None, // SA1_combinerz = 2567
27459 CEFBS_None, // SA1_combinezr = 2568
27460 CEFBS_None, // SA1_dec = 2569
27461 CEFBS_None, // SA1_inc = 2570
27462 CEFBS_None, // SA1_seti = 2571
27463 CEFBS_None, // SA1_setin1 = 2572
27464 CEFBS_None, // SA1_sxtb = 2573
27465 CEFBS_None, // SA1_sxth = 2574
27466 CEFBS_None, // SA1_tfr = 2575
27467 CEFBS_None, // SA1_zxtb = 2576
27468 CEFBS_None, // SA1_zxth = 2577
27469 CEFBS_None, // SAVE_REGISTERS_CALL_V4 = 2578
27470 CEFBS_None, // SAVE_REGISTERS_CALL_V4STK = 2579
27471 CEFBS_None, // SAVE_REGISTERS_CALL_V4STK_EXT = 2580
27472 CEFBS_None, // SAVE_REGISTERS_CALL_V4STK_EXT_PIC = 2581
27473 CEFBS_None, // SAVE_REGISTERS_CALL_V4STK_PIC = 2582
27474 CEFBS_None, // SAVE_REGISTERS_CALL_V4_EXT = 2583
27475 CEFBS_None, // SAVE_REGISTERS_CALL_V4_EXT_PIC = 2584
27476 CEFBS_None, // SAVE_REGISTERS_CALL_V4_PIC = 2585
27477 CEFBS_None, // SL1_loadri_io = 2586
27478 CEFBS_None, // SL1_loadrub_io = 2587
27479 CEFBS_None, // SL2_deallocframe = 2588
27480 CEFBS_None, // SL2_jumpr31 = 2589
27481 CEFBS_None, // SL2_jumpr31_f = 2590
27482 CEFBS_None, // SL2_jumpr31_fnew = 2591
27483 CEFBS_None, // SL2_jumpr31_t = 2592
27484 CEFBS_None, // SL2_jumpr31_tnew = 2593
27485 CEFBS_None, // SL2_loadrb_io = 2594
27486 CEFBS_None, // SL2_loadrd_sp = 2595
27487 CEFBS_None, // SL2_loadrh_io = 2596
27488 CEFBS_None, // SL2_loadri_sp = 2597
27489 CEFBS_None, // SL2_loadruh_io = 2598
27490 CEFBS_None, // SL2_return = 2599
27491 CEFBS_None, // SL2_return_f = 2600
27492 CEFBS_None, // SL2_return_fnew = 2601
27493 CEFBS_None, // SL2_return_t = 2602
27494 CEFBS_None, // SL2_return_tnew = 2603
27495 CEFBS_None, // SS1_storeb_io = 2604
27496 CEFBS_None, // SS1_storew_io = 2605
27497 CEFBS_None, // SS2_allocframe = 2606
27498 CEFBS_None, // SS2_storebi0 = 2607
27499 CEFBS_None, // SS2_storebi1 = 2608
27500 CEFBS_None, // SS2_stored_sp = 2609
27501 CEFBS_None, // SS2_storeh_io = 2610
27502 CEFBS_None, // SS2_storew_sp = 2611
27503 CEFBS_None, // SS2_storewi0 = 2612
27504 CEFBS_None, // SS2_storewi1 = 2613
27505 CEFBS_None, // TFRI64_V2_ext = 2614
27506 CEFBS_None, // TFRI64_V4 = 2615
27507 CEFBS_UseHVXV60, // V6_extractw = 2616
27508 CEFBS_UseHVXV62, // V6_lvsplatb = 2617
27509 CEFBS_UseHVXV62, // V6_lvsplath = 2618
27510 CEFBS_UseHVXV60, // V6_lvsplatw = 2619
27511 CEFBS_UseHVXV60, // V6_pred_and = 2620
27512 CEFBS_UseHVXV60, // V6_pred_and_n = 2621
27513 CEFBS_UseHVXV60, // V6_pred_not = 2622
27514 CEFBS_UseHVXV60, // V6_pred_or = 2623
27515 CEFBS_UseHVXV60, // V6_pred_or_n = 2624
27516 CEFBS_UseHVXV60, // V6_pred_scalar2 = 2625
27517 CEFBS_UseHVXV62, // V6_pred_scalar2v2 = 2626
27518 CEFBS_UseHVXV60, // V6_pred_xor = 2627
27519 CEFBS_UseHVXV62, // V6_shuffeqh = 2628
27520 CEFBS_UseHVXV62, // V6_shuffeqw = 2629
27521 CEFBS_UseHVXV68, // V6_v6mpyhubs10 = 2630
27522 CEFBS_UseHVXV68, // V6_v6mpyhubs10_vxx = 2631
27523 CEFBS_UseHVXV68, // V6_v6mpyvubs10 = 2632
27524 CEFBS_UseHVXV68, // V6_v6mpyvubs10_vxx = 2633
27525 CEFBS_UseHVXV60, // V6_vL32Ub_ai = 2634
27526 CEFBS_UseHVXV60, // V6_vL32Ub_pi = 2635
27527 CEFBS_UseHVXV60, // V6_vL32Ub_ppu = 2636
27528 CEFBS_UseHVXV60, // V6_vL32b_ai = 2637
27529 CEFBS_UseHVXV60, // V6_vL32b_cur_ai = 2638
27530 CEFBS_UseHVXV62, // V6_vL32b_cur_npred_ai = 2639
27531 CEFBS_UseHVXV62, // V6_vL32b_cur_npred_pi = 2640
27532 CEFBS_UseHVXV62, // V6_vL32b_cur_npred_ppu = 2641
27533 CEFBS_UseHVXV60, // V6_vL32b_cur_pi = 2642
27534 CEFBS_UseHVXV60, // V6_vL32b_cur_ppu = 2643
27535 CEFBS_UseHVXV62, // V6_vL32b_cur_pred_ai = 2644
27536 CEFBS_UseHVXV62, // V6_vL32b_cur_pred_pi = 2645
27537 CEFBS_UseHVXV62, // V6_vL32b_cur_pred_ppu = 2646
27538 CEFBS_UseHVXV62, // V6_vL32b_npred_ai = 2647
27539 CEFBS_UseHVXV62, // V6_vL32b_npred_pi = 2648
27540 CEFBS_UseHVXV62, // V6_vL32b_npred_ppu = 2649
27541 CEFBS_UseHVXV60, // V6_vL32b_nt_ai = 2650
27542 CEFBS_UseHVXV60, // V6_vL32b_nt_cur_ai = 2651
27543 CEFBS_UseHVXV62, // V6_vL32b_nt_cur_npred_ai = 2652
27544 CEFBS_UseHVXV62, // V6_vL32b_nt_cur_npred_pi = 2653
27545 CEFBS_UseHVXV62, // V6_vL32b_nt_cur_npred_ppu = 2654
27546 CEFBS_UseHVXV60, // V6_vL32b_nt_cur_pi = 2655
27547 CEFBS_UseHVXV60, // V6_vL32b_nt_cur_ppu = 2656
27548 CEFBS_UseHVXV62, // V6_vL32b_nt_cur_pred_ai = 2657
27549 CEFBS_UseHVXV62, // V6_vL32b_nt_cur_pred_pi = 2658
27550 CEFBS_UseHVXV62, // V6_vL32b_nt_cur_pred_ppu = 2659
27551 CEFBS_UseHVXV62, // V6_vL32b_nt_npred_ai = 2660
27552 CEFBS_UseHVXV62, // V6_vL32b_nt_npred_pi = 2661
27553 CEFBS_UseHVXV62, // V6_vL32b_nt_npred_ppu = 2662
27554 CEFBS_UseHVXV60, // V6_vL32b_nt_pi = 2663
27555 CEFBS_UseHVXV60, // V6_vL32b_nt_ppu = 2664
27556 CEFBS_UseHVXV62, // V6_vL32b_nt_pred_ai = 2665
27557 CEFBS_UseHVXV62, // V6_vL32b_nt_pred_pi = 2666
27558 CEFBS_UseHVXV62, // V6_vL32b_nt_pred_ppu = 2667
27559 CEFBS_UseHVXV60, // V6_vL32b_nt_tmp_ai = 2668
27560 CEFBS_UseHVXV62, // V6_vL32b_nt_tmp_npred_ai = 2669
27561 CEFBS_UseHVXV62, // V6_vL32b_nt_tmp_npred_pi = 2670
27562 CEFBS_UseHVXV62, // V6_vL32b_nt_tmp_npred_ppu = 2671
27563 CEFBS_UseHVXV60, // V6_vL32b_nt_tmp_pi = 2672
27564 CEFBS_UseHVXV60, // V6_vL32b_nt_tmp_ppu = 2673
27565 CEFBS_UseHVXV62, // V6_vL32b_nt_tmp_pred_ai = 2674
27566 CEFBS_UseHVXV62, // V6_vL32b_nt_tmp_pred_pi = 2675
27567 CEFBS_UseHVXV62, // V6_vL32b_nt_tmp_pred_ppu = 2676
27568 CEFBS_UseHVXV60, // V6_vL32b_pi = 2677
27569 CEFBS_UseHVXV60, // V6_vL32b_ppu = 2678
27570 CEFBS_UseHVXV62, // V6_vL32b_pred_ai = 2679
27571 CEFBS_UseHVXV62, // V6_vL32b_pred_pi = 2680
27572 CEFBS_UseHVXV62, // V6_vL32b_pred_ppu = 2681
27573 CEFBS_UseHVXV60, // V6_vL32b_tmp_ai = 2682
27574 CEFBS_UseHVXV62, // V6_vL32b_tmp_npred_ai = 2683
27575 CEFBS_UseHVXV62, // V6_vL32b_tmp_npred_pi = 2684
27576 CEFBS_UseHVXV62, // V6_vL32b_tmp_npred_ppu = 2685
27577 CEFBS_UseHVXV60, // V6_vL32b_tmp_pi = 2686
27578 CEFBS_UseHVXV60, // V6_vL32b_tmp_ppu = 2687
27579 CEFBS_UseHVXV62, // V6_vL32b_tmp_pred_ai = 2688
27580 CEFBS_UseHVXV62, // V6_vL32b_tmp_pred_pi = 2689
27581 CEFBS_UseHVXV62, // V6_vL32b_tmp_pred_ppu = 2690
27582 CEFBS_UseHVXV60, // V6_vS32Ub_ai = 2691
27583 CEFBS_UseHVXV60, // V6_vS32Ub_npred_ai = 2692
27584 CEFBS_UseHVXV60, // V6_vS32Ub_npred_pi = 2693
27585 CEFBS_UseHVXV60, // V6_vS32Ub_npred_ppu = 2694
27586 CEFBS_UseHVXV60, // V6_vS32Ub_pi = 2695
27587 CEFBS_UseHVXV60, // V6_vS32Ub_ppu = 2696
27588 CEFBS_UseHVXV60, // V6_vS32Ub_pred_ai = 2697
27589 CEFBS_UseHVXV60, // V6_vS32Ub_pred_pi = 2698
27590 CEFBS_UseHVXV60, // V6_vS32Ub_pred_ppu = 2699
27591 CEFBS_UseHVXV60, // V6_vS32b_ai = 2700
27592 CEFBS_UseHVXV60, // V6_vS32b_new_ai = 2701
27593 CEFBS_UseHVXV60, // V6_vS32b_new_npred_ai = 2702
27594 CEFBS_UseHVXV60, // V6_vS32b_new_npred_pi = 2703
27595 CEFBS_UseHVXV60, // V6_vS32b_new_npred_ppu = 2704
27596 CEFBS_UseHVXV60, // V6_vS32b_new_pi = 2705
27597 CEFBS_UseHVXV60, // V6_vS32b_new_ppu = 2706
27598 CEFBS_UseHVXV60, // V6_vS32b_new_pred_ai = 2707
27599 CEFBS_UseHVXV60, // V6_vS32b_new_pred_pi = 2708
27600 CEFBS_UseHVXV60, // V6_vS32b_new_pred_ppu = 2709
27601 CEFBS_UseHVXV60, // V6_vS32b_npred_ai = 2710
27602 CEFBS_UseHVXV60, // V6_vS32b_npred_pi = 2711
27603 CEFBS_UseHVXV60, // V6_vS32b_npred_ppu = 2712
27604 CEFBS_UseHVXV60, // V6_vS32b_nqpred_ai = 2713
27605 CEFBS_UseHVXV60, // V6_vS32b_nqpred_pi = 2714
27606 CEFBS_UseHVXV60, // V6_vS32b_nqpred_ppu = 2715
27607 CEFBS_UseHVXV60, // V6_vS32b_nt_ai = 2716
27608 CEFBS_UseHVXV60, // V6_vS32b_nt_new_ai = 2717
27609 CEFBS_UseHVXV60, // V6_vS32b_nt_new_npred_ai = 2718
27610 CEFBS_UseHVXV60, // V6_vS32b_nt_new_npred_pi = 2719
27611 CEFBS_UseHVXV60, // V6_vS32b_nt_new_npred_ppu = 2720
27612 CEFBS_UseHVXV60, // V6_vS32b_nt_new_pi = 2721
27613 CEFBS_UseHVXV60, // V6_vS32b_nt_new_ppu = 2722
27614 CEFBS_UseHVXV60, // V6_vS32b_nt_new_pred_ai = 2723
27615 CEFBS_UseHVXV60, // V6_vS32b_nt_new_pred_pi = 2724
27616 CEFBS_UseHVXV60, // V6_vS32b_nt_new_pred_ppu = 2725
27617 CEFBS_UseHVXV60, // V6_vS32b_nt_npred_ai = 2726
27618 CEFBS_UseHVXV60, // V6_vS32b_nt_npred_pi = 2727
27619 CEFBS_UseHVXV60, // V6_vS32b_nt_npred_ppu = 2728
27620 CEFBS_UseHVXV60, // V6_vS32b_nt_nqpred_ai = 2729
27621 CEFBS_UseHVXV60, // V6_vS32b_nt_nqpred_pi = 2730
27622 CEFBS_UseHVXV60, // V6_vS32b_nt_nqpred_ppu = 2731
27623 CEFBS_UseHVXV60, // V6_vS32b_nt_pi = 2732
27624 CEFBS_UseHVXV60, // V6_vS32b_nt_ppu = 2733
27625 CEFBS_UseHVXV60, // V6_vS32b_nt_pred_ai = 2734
27626 CEFBS_UseHVXV60, // V6_vS32b_nt_pred_pi = 2735
27627 CEFBS_UseHVXV60, // V6_vS32b_nt_pred_ppu = 2736
27628 CEFBS_UseHVXV60, // V6_vS32b_nt_qpred_ai = 2737
27629 CEFBS_UseHVXV60, // V6_vS32b_nt_qpred_pi = 2738
27630 CEFBS_UseHVXV60, // V6_vS32b_nt_qpred_ppu = 2739
27631 CEFBS_UseHVXV60, // V6_vS32b_pi = 2740
27632 CEFBS_UseHVXV60, // V6_vS32b_ppu = 2741
27633 CEFBS_UseHVXV60, // V6_vS32b_pred_ai = 2742
27634 CEFBS_UseHVXV60, // V6_vS32b_pred_pi = 2743
27635 CEFBS_UseHVXV60, // V6_vS32b_pred_ppu = 2744
27636 CEFBS_UseHVXV60, // V6_vS32b_qpred_ai = 2745
27637 CEFBS_UseHVXV60, // V6_vS32b_qpred_pi = 2746
27638 CEFBS_UseHVXV60, // V6_vS32b_qpred_ppu = 2747
27639 CEFBS_UseHVXV65, // V6_vS32b_srls_ai = 2748
27640 CEFBS_UseHVXV65, // V6_vS32b_srls_pi = 2749
27641 CEFBS_UseHVXV65, // V6_vS32b_srls_ppu = 2750
27642 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vabs_hf = 2751
27643 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vabs_sf = 2752
27644 CEFBS_UseHVXV65, // V6_vabsb = 2753
27645 CEFBS_UseHVXV65, // V6_vabsb_sat = 2754
27646 CEFBS_UseHVXV60, // V6_vabsdiffh = 2755
27647 CEFBS_UseHVXV60, // V6_vabsdiffub = 2756
27648 CEFBS_UseHVXV60, // V6_vabsdiffuh = 2757
27649 CEFBS_UseHVXV60, // V6_vabsdiffw = 2758
27650 CEFBS_UseHVXV60, // V6_vabsh = 2759
27651 CEFBS_UseHVXV60, // V6_vabsh_sat = 2760
27652 CEFBS_UseHVXV60, // V6_vabsw = 2761
27653 CEFBS_UseHVXV60, // V6_vabsw_sat = 2762
27654 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vadd_hf = 2763
27655 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vadd_hf_hf = 2764
27656 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vadd_qf16 = 2765
27657 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vadd_qf16_mix = 2766
27658 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vadd_qf32 = 2767
27659 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vadd_qf32_mix = 2768
27660 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vadd_sf = 2769
27661 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vadd_sf_bf = 2770
27662 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vadd_sf_hf = 2771
27663 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vadd_sf_sf = 2772
27664 CEFBS_UseHVXV60, // V6_vaddb = 2773
27665 CEFBS_UseHVXV60, // V6_vaddb_dv = 2774
27666 CEFBS_UseHVXV60, // V6_vaddbnq = 2775
27667 CEFBS_UseHVXV60, // V6_vaddbq = 2776
27668 CEFBS_UseHVXV62, // V6_vaddbsat = 2777
27669 CEFBS_UseHVXV62, // V6_vaddbsat_dv = 2778
27670 CEFBS_UseHVXV62, // V6_vaddcarry = 2779
27671 CEFBS_UseHVXV66, // V6_vaddcarryo = 2780
27672 CEFBS_UseHVXV66, // V6_vaddcarrysat = 2781
27673 CEFBS_UseHVXV62, // V6_vaddclbh = 2782
27674 CEFBS_UseHVXV62, // V6_vaddclbw = 2783
27675 CEFBS_UseHVXV60, // V6_vaddh = 2784
27676 CEFBS_UseHVXV60, // V6_vaddh_dv = 2785
27677 CEFBS_UseHVXV60, // V6_vaddhnq = 2786
27678 CEFBS_UseHVXV60, // V6_vaddhq = 2787
27679 CEFBS_UseHVXV60, // V6_vaddhsat = 2788
27680 CEFBS_UseHVXV60, // V6_vaddhsat_dv = 2789
27681 CEFBS_UseHVXV60, // V6_vaddhw = 2790
27682 CEFBS_UseHVXV62, // V6_vaddhw_acc = 2791
27683 CEFBS_UseHVXV60, // V6_vaddubh = 2792
27684 CEFBS_UseHVXV62, // V6_vaddubh_acc = 2793
27685 CEFBS_UseHVXV60, // V6_vaddubsat = 2794
27686 CEFBS_UseHVXV60, // V6_vaddubsat_dv = 2795
27687 CEFBS_UseHVXV62, // V6_vaddububb_sat = 2796
27688 CEFBS_UseHVXV60, // V6_vadduhsat = 2797
27689 CEFBS_UseHVXV60, // V6_vadduhsat_dv = 2798
27690 CEFBS_UseHVXV60, // V6_vadduhw = 2799
27691 CEFBS_UseHVXV62, // V6_vadduhw_acc = 2800
27692 CEFBS_UseHVXV62, // V6_vadduwsat = 2801
27693 CEFBS_UseHVXV62, // V6_vadduwsat_dv = 2802
27694 CEFBS_UseHVXV60, // V6_vaddw = 2803
27695 CEFBS_UseHVXV60, // V6_vaddw_dv = 2804
27696 CEFBS_UseHVXV60, // V6_vaddwnq = 2805
27697 CEFBS_UseHVXV60, // V6_vaddwq = 2806
27698 CEFBS_UseHVXV60, // V6_vaddwsat = 2807
27699 CEFBS_UseHVXV60, // V6_vaddwsat_dv = 2808
27700 CEFBS_UseHVXV60, // V6_valignb = 2809
27701 CEFBS_UseHVXV60, // V6_valignbi = 2810
27702 CEFBS_UseHVXV60, // V6_vand = 2811
27703 CEFBS_UseHVXV62, // V6_vandnqrt = 2812
27704 CEFBS_UseHVXV62, // V6_vandnqrt_acc = 2813
27705 CEFBS_UseHVXV60, // V6_vandqrt = 2814
27706 CEFBS_UseHVXV60, // V6_vandqrt_acc = 2815
27707 CEFBS_UseHVXV62, // V6_vandvnqv = 2816
27708 CEFBS_UseHVXV62, // V6_vandvqv = 2817
27709 CEFBS_UseHVXV60, // V6_vandvrt = 2818
27710 CEFBS_UseHVXV60, // V6_vandvrt_acc = 2819
27711 CEFBS_UseHVXV60, // V6_vaslh = 2820
27712 CEFBS_UseHVXV65, // V6_vaslh_acc = 2821
27713 CEFBS_UseHVXV60, // V6_vaslhv = 2822
27714 CEFBS_UseHVXV60, // V6_vaslw = 2823
27715 CEFBS_UseHVXV60, // V6_vaslw_acc = 2824
27716 CEFBS_UseHVXV60, // V6_vaslwv = 2825
27717 CEFBS_UseHVXV66, // V6_vasr_into = 2826
27718 CEFBS_UseHVXV60, // V6_vasrh = 2827
27719 CEFBS_UseHVXV65, // V6_vasrh_acc = 2828
27720 CEFBS_UseHVXV60, // V6_vasrhbrndsat = 2829
27721 CEFBS_UseHVXV62, // V6_vasrhbsat = 2830
27722 CEFBS_UseHVXV60, // V6_vasrhubrndsat = 2831
27723 CEFBS_UseHVXV60, // V6_vasrhubsat = 2832
27724 CEFBS_UseHVXV60, // V6_vasrhv = 2833
27725 CEFBS_UseHVXV65, // V6_vasruhubrndsat = 2834
27726 CEFBS_UseHVXV65, // V6_vasruhubsat = 2835
27727 CEFBS_UseHVXV62, // V6_vasruwuhrndsat = 2836
27728 CEFBS_UseHVXV65, // V6_vasruwuhsat = 2837
27729 CEFBS_UseHVXV69, // V6_vasrvuhubrndsat = 2838
27730 CEFBS_UseHVXV69, // V6_vasrvuhubsat = 2839
27731 CEFBS_UseHVXV69, // V6_vasrvwuhrndsat = 2840
27732 CEFBS_UseHVXV69, // V6_vasrvwuhsat = 2841
27733 CEFBS_UseHVXV60, // V6_vasrw = 2842
27734 CEFBS_UseHVXV60, // V6_vasrw_acc = 2843
27735 CEFBS_UseHVXV60, // V6_vasrwh = 2844
27736 CEFBS_UseHVXV60, // V6_vasrwhrndsat = 2845
27737 CEFBS_UseHVXV60, // V6_vasrwhsat = 2846
27738 CEFBS_UseHVXV62, // V6_vasrwuhrndsat = 2847
27739 CEFBS_UseHVXV60, // V6_vasrwuhsat = 2848
27740 CEFBS_UseHVXV60, // V6_vasrwv = 2849
27741 CEFBS_UseHVXV60, // V6_vassign = 2850
27742 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vassign_fp = 2851
27743 CEFBS_UseHVXV69, // V6_vassign_tmp = 2852
27744 CEFBS_UseHVXV65, // V6_vavgb = 2853
27745 CEFBS_UseHVXV65, // V6_vavgbrnd = 2854
27746 CEFBS_UseHVXV60, // V6_vavgh = 2855
27747 CEFBS_UseHVXV60, // V6_vavghrnd = 2856
27748 CEFBS_UseHVXV60, // V6_vavgub = 2857
27749 CEFBS_UseHVXV60, // V6_vavgubrnd = 2858
27750 CEFBS_UseHVXV60, // V6_vavguh = 2859
27751 CEFBS_UseHVXV60, // V6_vavguhrnd = 2860
27752 CEFBS_UseHVXV65, // V6_vavguw = 2861
27753 CEFBS_UseHVXV65, // V6_vavguwrnd = 2862
27754 CEFBS_UseHVXV60, // V6_vavgw = 2863
27755 CEFBS_UseHVXV60, // V6_vavgwrnd = 2864
27756 CEFBS_UseHVXV60, // V6_vccombine = 2865
27757 CEFBS_UseHVXV60, // V6_vcl0h = 2866
27758 CEFBS_UseHVXV60, // V6_vcl0w = 2867
27759 CEFBS_UseHVXV60, // V6_vcmov = 2868
27760 CEFBS_UseHVXV60, // V6_vcombine = 2869
27761 CEFBS_UseHVXV69, // V6_vcombine_tmp = 2870
27762 CEFBS_UseHVXV73, // V6_vconv_h_hf = 2871
27763 CEFBS_UseHVXV73, // V6_vconv_hf_h = 2872
27764 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vconv_hf_qf16 = 2873
27765 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vconv_hf_qf32 = 2874
27766 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vconv_sf_qf32 = 2875
27767 CEFBS_UseHVXV73, // V6_vconv_sf_w = 2876
27768 CEFBS_UseHVXV73, // V6_vconv_w_sf = 2877
27769 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_b_hf = 2878
27770 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vcvt_bf_sf = 2879
27771 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_h_hf = 2880
27772 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_hf_b = 2881
27773 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_hf_h = 2882
27774 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_hf_sf = 2883
27775 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_hf_ub = 2884
27776 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_hf_uh = 2885
27777 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_sf_hf = 2886
27778 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_ub_hf = 2887
27779 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_uh_hf = 2888
27780 CEFBS_UseHVXV60, // V6_vdeal = 2889
27781 CEFBS_UseHVXV60, // V6_vdealb = 2890
27782 CEFBS_UseHVXV60, // V6_vdealb4w = 2891
27783 CEFBS_UseHVXV60, // V6_vdealh = 2892
27784 CEFBS_UseHVXV60, // V6_vdealvdd = 2893
27785 CEFBS_UseHVXV60, // V6_vdelta = 2894
27786 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vdmpy_sf_hf = 2895
27787 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vdmpy_sf_hf_acc = 2896
27788 CEFBS_UseHVXV60, // V6_vdmpybus = 2897
27789 CEFBS_UseHVXV60, // V6_vdmpybus_acc = 2898
27790 CEFBS_UseHVXV60, // V6_vdmpybus_dv = 2899
27791 CEFBS_UseHVXV60, // V6_vdmpybus_dv_acc = 2900
27792 CEFBS_UseHVXV60, // V6_vdmpyhb = 2901
27793 CEFBS_UseHVXV60, // V6_vdmpyhb_acc = 2902
27794 CEFBS_UseHVXV60, // V6_vdmpyhb_dv = 2903
27795 CEFBS_UseHVXV60, // V6_vdmpyhb_dv_acc = 2904
27796 CEFBS_UseHVXV60, // V6_vdmpyhisat = 2905
27797 CEFBS_UseHVXV60, // V6_vdmpyhisat_acc = 2906
27798 CEFBS_UseHVXV60, // V6_vdmpyhsat = 2907
27799 CEFBS_UseHVXV60, // V6_vdmpyhsat_acc = 2908
27800 CEFBS_UseHVXV60, // V6_vdmpyhsuisat = 2909
27801 CEFBS_UseHVXV60, // V6_vdmpyhsuisat_acc = 2910
27802 CEFBS_UseHVXV60, // V6_vdmpyhsusat = 2911
27803 CEFBS_UseHVXV60, // V6_vdmpyhsusat_acc = 2912
27804 CEFBS_UseHVXV60, // V6_vdmpyhvsat = 2913
27805 CEFBS_UseHVXV60, // V6_vdmpyhvsat_acc = 2914
27806 CEFBS_UseHVXV60, // V6_vdsaduh = 2915
27807 CEFBS_UseHVXV60, // V6_vdsaduh_acc = 2916
27808 CEFBS_UseHVXV60, // V6_veqb = 2917
27809 CEFBS_UseHVXV60, // V6_veqb_and = 2918
27810 CEFBS_UseHVXV60, // V6_veqb_or = 2919
27811 CEFBS_UseHVXV60, // V6_veqb_xor = 2920
27812 CEFBS_UseHVXV60, // V6_veqh = 2921
27813 CEFBS_UseHVXV60, // V6_veqh_and = 2922
27814 CEFBS_UseHVXV60, // V6_veqh_or = 2923
27815 CEFBS_UseHVXV60, // V6_veqh_xor = 2924
27816 CEFBS_UseHVXV60, // V6_veqw = 2925
27817 CEFBS_UseHVXV60, // V6_veqw_and = 2926
27818 CEFBS_UseHVXV60, // V6_veqw_or = 2927
27819 CEFBS_UseHVXV60, // V6_veqw_xor = 2928
27820 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vfmax_hf = 2929
27821 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vfmax_sf = 2930
27822 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vfmin_hf = 2931
27823 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vfmin_sf = 2932
27824 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vfneg_hf = 2933
27825 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vfneg_sf = 2934
27826 CEFBS_UseHVXV65, // V6_vgathermh = 2935
27827 CEFBS_UseHVXV65, // V6_vgathermhq = 2936
27828 CEFBS_UseHVXV65, // V6_vgathermhw = 2937
27829 CEFBS_UseHVXV65, // V6_vgathermhwq = 2938
27830 CEFBS_UseHVXV65, // V6_vgathermw = 2939
27831 CEFBS_UseHVXV65, // V6_vgathermwq = 2940
27832 CEFBS_UseHVXV60, // V6_vgtb = 2941
27833 CEFBS_UseHVXV60, // V6_vgtb_and = 2942
27834 CEFBS_UseHVXV60, // V6_vgtb_or = 2943
27835 CEFBS_UseHVXV60, // V6_vgtb_xor = 2944
27836 CEFBS_UseHVXV73_UseHVXQFloat, // V6_vgtbf = 2945
27837 CEFBS_UseHVXV73_UseHVXQFloat, // V6_vgtbf_and = 2946
27838 CEFBS_UseHVXV73_UseHVXQFloat, // V6_vgtbf_or = 2947
27839 CEFBS_UseHVXV73_UseHVXQFloat, // V6_vgtbf_xor = 2948
27840 CEFBS_UseHVXV60, // V6_vgth = 2949
27841 CEFBS_UseHVXV60, // V6_vgth_and = 2950
27842 CEFBS_UseHVXV60, // V6_vgth_or = 2951
27843 CEFBS_UseHVXV60, // V6_vgth_xor = 2952
27844 CEFBS_UseHVXV68, // V6_vgthf = 2953
27845 CEFBS_UseHVXV68, // V6_vgthf_and = 2954
27846 CEFBS_UseHVXV68, // V6_vgthf_or = 2955
27847 CEFBS_UseHVXV68, // V6_vgthf_xor = 2956
27848 CEFBS_UseHVXV68, // V6_vgtsf = 2957
27849 CEFBS_UseHVXV68, // V6_vgtsf_and = 2958
27850 CEFBS_UseHVXV68, // V6_vgtsf_or = 2959
27851 CEFBS_UseHVXV68, // V6_vgtsf_xor = 2960
27852 CEFBS_UseHVXV60, // V6_vgtub = 2961
27853 CEFBS_UseHVXV60, // V6_vgtub_and = 2962
27854 CEFBS_UseHVXV60, // V6_vgtub_or = 2963
27855 CEFBS_UseHVXV60, // V6_vgtub_xor = 2964
27856 CEFBS_UseHVXV60, // V6_vgtuh = 2965
27857 CEFBS_UseHVXV60, // V6_vgtuh_and = 2966
27858 CEFBS_UseHVXV60, // V6_vgtuh_or = 2967
27859 CEFBS_UseHVXV60, // V6_vgtuh_xor = 2968
27860 CEFBS_UseHVXV60, // V6_vgtuw = 2969
27861 CEFBS_UseHVXV60, // V6_vgtuw_and = 2970
27862 CEFBS_UseHVXV60, // V6_vgtuw_or = 2971
27863 CEFBS_UseHVXV60, // V6_vgtuw_xor = 2972
27864 CEFBS_UseHVXV60, // V6_vgtw = 2973
27865 CEFBS_UseHVXV60, // V6_vgtw_and = 2974
27866 CEFBS_UseHVXV60, // V6_vgtw_or = 2975
27867 CEFBS_UseHVXV60, // V6_vgtw_xor = 2976
27868 CEFBS_UseHVXV60, // V6_vhist = 2977
27869 CEFBS_UseHVXV60, // V6_vhistq = 2978
27870 CEFBS_UseHVXV60, // V6_vinsertwr = 2979
27871 CEFBS_UseHVXV60, // V6_vlalignb = 2980
27872 CEFBS_UseHVXV60, // V6_vlalignbi = 2981
27873 CEFBS_UseHVXV62, // V6_vlsrb = 2982
27874 CEFBS_UseHVXV60, // V6_vlsrh = 2983
27875 CEFBS_UseHVXV60, // V6_vlsrhv = 2984
27876 CEFBS_UseHVXV60, // V6_vlsrw = 2985
27877 CEFBS_UseHVXV60, // V6_vlsrwv = 2986
27878 CEFBS_UseHVXV65, // V6_vlut4 = 2987
27879 CEFBS_UseHVXV60, // V6_vlutvvb = 2988
27880 CEFBS_UseHVXV62, // V6_vlutvvb_nm = 2989
27881 CEFBS_UseHVXV60, // V6_vlutvvb_oracc = 2990
27882 CEFBS_UseHVXV62, // V6_vlutvvb_oracci = 2991
27883 CEFBS_UseHVXV62, // V6_vlutvvbi = 2992
27884 CEFBS_UseHVXV60, // V6_vlutvwh = 2993
27885 CEFBS_UseHVXV62, // V6_vlutvwh_nm = 2994
27886 CEFBS_UseHVXV60, // V6_vlutvwh_oracc = 2995
27887 CEFBS_UseHVXV62, // V6_vlutvwh_oracci = 2996
27888 CEFBS_UseHVXV62, // V6_vlutvwhi = 2997
27889 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vmax_bf = 2998
27890 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmax_hf = 2999
27891 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmax_sf = 3000
27892 CEFBS_UseHVXV62, // V6_vmaxb = 3001
27893 CEFBS_UseHVXV60, // V6_vmaxh = 3002
27894 CEFBS_UseHVXV60, // V6_vmaxub = 3003
27895 CEFBS_UseHVXV60, // V6_vmaxuh = 3004
27896 CEFBS_UseHVXV60, // V6_vmaxw = 3005
27897 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vmin_bf = 3006
27898 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmin_hf = 3007
27899 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmin_sf = 3008
27900 CEFBS_UseHVXV62, // V6_vminb = 3009
27901 CEFBS_UseHVXV60, // V6_vminh = 3010
27902 CEFBS_UseHVXV60, // V6_vminub = 3011
27903 CEFBS_UseHVXV60, // V6_vminuh = 3012
27904 CEFBS_UseHVXV60, // V6_vminw = 3013
27905 CEFBS_UseHVXV60, // V6_vmpabus = 3014
27906 CEFBS_UseHVXV60, // V6_vmpabus_acc = 3015
27907 CEFBS_UseHVXV60, // V6_vmpabusv = 3016
27908 CEFBS_UseHVXV65, // V6_vmpabuu = 3017
27909 CEFBS_UseHVXV65, // V6_vmpabuu_acc = 3018
27910 CEFBS_UseHVXV60, // V6_vmpabuuv = 3019
27911 CEFBS_UseHVXV60, // V6_vmpahb = 3020
27912 CEFBS_UseHVXV60, // V6_vmpahb_acc = 3021
27913 CEFBS_UseHVXV65, // V6_vmpahhsat = 3022
27914 CEFBS_UseHVXV62, // V6_vmpauhb = 3023
27915 CEFBS_UseHVXV62, // V6_vmpauhb_acc = 3024
27916 CEFBS_UseHVXV65, // V6_vmpauhuhsat = 3025
27917 CEFBS_UseHVXV65, // V6_vmpsuhuhsat = 3026
27918 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vmpy_hf_hf = 3027
27919 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vmpy_hf_hf_acc = 3028
27920 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf16 = 3029
27921 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf16_hf = 3030
27922 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf16_mix_hf = 3031
27923 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf32 = 3032
27924 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf32_hf = 3033
27925 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf32_mix_hf = 3034
27926 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf32_qf16 = 3035
27927 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf32_sf = 3036
27928 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vmpy_sf_bf = 3037
27929 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vmpy_sf_bf_acc = 3038
27930 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vmpy_sf_hf = 3039
27931 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vmpy_sf_hf_acc = 3040
27932 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vmpy_sf_sf = 3041
27933 CEFBS_UseHVXV60, // V6_vmpybus = 3042
27934 CEFBS_UseHVXV60, // V6_vmpybus_acc = 3043
27935 CEFBS_UseHVXV60, // V6_vmpybusv = 3044
27936 CEFBS_UseHVXV60, // V6_vmpybusv_acc = 3045
27937 CEFBS_UseHVXV60, // V6_vmpybv = 3046
27938 CEFBS_UseHVXV60, // V6_vmpybv_acc = 3047
27939 CEFBS_UseHVXV60, // V6_vmpyewuh = 3048
27940 CEFBS_UseHVXV62, // V6_vmpyewuh_64 = 3049
27941 CEFBS_UseHVXV60, // V6_vmpyh = 3050
27942 CEFBS_UseHVXV65, // V6_vmpyh_acc = 3051
27943 CEFBS_UseHVXV60, // V6_vmpyhsat_acc = 3052
27944 CEFBS_UseHVXV60, // V6_vmpyhsrs = 3053
27945 CEFBS_UseHVXV60, // V6_vmpyhss = 3054
27946 CEFBS_UseHVXV60, // V6_vmpyhus = 3055
27947 CEFBS_UseHVXV60, // V6_vmpyhus_acc = 3056
27948 CEFBS_UseHVXV60, // V6_vmpyhv = 3057
27949 CEFBS_UseHVXV60, // V6_vmpyhv_acc = 3058
27950 CEFBS_UseHVXV60, // V6_vmpyhvsrs = 3059
27951 CEFBS_UseHVXV60, // V6_vmpyieoh = 3060
27952 CEFBS_UseHVXV60, // V6_vmpyiewh_acc = 3061
27953 CEFBS_UseHVXV60, // V6_vmpyiewuh = 3062
27954 CEFBS_UseHVXV60, // V6_vmpyiewuh_acc = 3063
27955 CEFBS_UseHVXV60, // V6_vmpyih = 3064
27956 CEFBS_UseHVXV60, // V6_vmpyih_acc = 3065
27957 CEFBS_UseHVXV60, // V6_vmpyihb = 3066
27958 CEFBS_UseHVXV60, // V6_vmpyihb_acc = 3067
27959 CEFBS_UseHVXV60, // V6_vmpyiowh = 3068
27960 CEFBS_UseHVXV60, // V6_vmpyiwb = 3069
27961 CEFBS_UseHVXV60, // V6_vmpyiwb_acc = 3070
27962 CEFBS_UseHVXV60, // V6_vmpyiwh = 3071
27963 CEFBS_UseHVXV60, // V6_vmpyiwh_acc = 3072
27964 CEFBS_UseHVXV62, // V6_vmpyiwub = 3073
27965 CEFBS_UseHVXV62, // V6_vmpyiwub_acc = 3074
27966 CEFBS_UseHVXV60, // V6_vmpyowh = 3075
27967 CEFBS_UseHVXV62, // V6_vmpyowh_64_acc = 3076
27968 CEFBS_UseHVXV60, // V6_vmpyowh_rnd = 3077
27969 CEFBS_UseHVXV60, // V6_vmpyowh_rnd_sacc = 3078
27970 CEFBS_UseHVXV60, // V6_vmpyowh_sacc = 3079
27971 CEFBS_UseHVXV60, // V6_vmpyub = 3080
27972 CEFBS_UseHVXV60, // V6_vmpyub_acc = 3081
27973 CEFBS_UseHVXV60, // V6_vmpyubv = 3082
27974 CEFBS_UseHVXV60, // V6_vmpyubv_acc = 3083
27975 CEFBS_UseHVXV60, // V6_vmpyuh = 3084
27976 CEFBS_UseHVXV60, // V6_vmpyuh_acc = 3085
27977 CEFBS_UseHVXV65, // V6_vmpyuhe = 3086
27978 CEFBS_UseHVXV65, // V6_vmpyuhe_acc = 3087
27979 CEFBS_UseHVXV60, // V6_vmpyuhv = 3088
27980 CEFBS_UseHVXV60, // V6_vmpyuhv_acc = 3089
27981 CEFBS_UseHVXV69, // V6_vmpyuhvs = 3090
27982 CEFBS_UseHVXV60, // V6_vmux = 3091
27983 CEFBS_UseHVXV65, // V6_vnavgb = 3092
27984 CEFBS_UseHVXV60, // V6_vnavgh = 3093
27985 CEFBS_UseHVXV60, // V6_vnavgub = 3094
27986 CEFBS_UseHVXV60, // V6_vnavgw = 3095
27987 CEFBS_UseHVXV60, // V6_vnccombine = 3096
27988 CEFBS_UseHVXV60, // V6_vncmov = 3097
27989 CEFBS_UseHVXV60, // V6_vnormamth = 3098
27990 CEFBS_UseHVXV60, // V6_vnormamtw = 3099
27991 CEFBS_UseHVXV60, // V6_vnot = 3100
27992 CEFBS_UseHVXV60, // V6_vor = 3101
27993 CEFBS_UseHVXV60, // V6_vpackeb = 3102
27994 CEFBS_UseHVXV60, // V6_vpackeh = 3103
27995 CEFBS_UseHVXV60, // V6_vpackhb_sat = 3104
27996 CEFBS_UseHVXV60, // V6_vpackhub_sat = 3105
27997 CEFBS_UseHVXV60, // V6_vpackob = 3106
27998 CEFBS_UseHVXV60, // V6_vpackoh = 3107
27999 CEFBS_UseHVXV60, // V6_vpackwh_sat = 3108
28000 CEFBS_UseHVXV60, // V6_vpackwuh_sat = 3109
28001 CEFBS_UseHVXV60, // V6_vpopcounth = 3110
28002 CEFBS_UseHVXV65, // V6_vprefixqb = 3111
28003 CEFBS_UseHVXV65, // V6_vprefixqh = 3112
28004 CEFBS_UseHVXV65, // V6_vprefixqw = 3113
28005 CEFBS_UseHVXV60, // V6_vrdelta = 3114
28006 CEFBS_UseHVXV65, // V6_vrmpybub_rtt = 3115
28007 CEFBS_UseHVXV65, // V6_vrmpybub_rtt_acc = 3116
28008 CEFBS_UseHVXV60, // V6_vrmpybus = 3117
28009 CEFBS_UseHVXV60, // V6_vrmpybus_acc = 3118
28010 CEFBS_UseHVXV60, // V6_vrmpybusi = 3119
28011 CEFBS_UseHVXV60, // V6_vrmpybusi_acc = 3120
28012 CEFBS_UseHVXV60, // V6_vrmpybusv = 3121
28013 CEFBS_UseHVXV60, // V6_vrmpybusv_acc = 3122
28014 CEFBS_UseHVXV60, // V6_vrmpybv = 3123
28015 CEFBS_UseHVXV60, // V6_vrmpybv_acc = 3124
28016 CEFBS_UseHVXV60, // V6_vrmpyub = 3125
28017 CEFBS_UseHVXV60, // V6_vrmpyub_acc = 3126
28018 CEFBS_UseHVXV65, // V6_vrmpyub_rtt = 3127
28019 CEFBS_UseHVXV65, // V6_vrmpyub_rtt_acc = 3128
28020 CEFBS_UseHVXV60, // V6_vrmpyubi = 3129
28021 CEFBS_UseHVXV60, // V6_vrmpyubi_acc = 3130
28022 CEFBS_UseHVXV60, // V6_vrmpyubv = 3131
28023 CEFBS_UseHVXV60, // V6_vrmpyubv_acc = 3132
28024 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbb_rt = 3133
28025 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbb_rt_acc = 3134
28026 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbb_rx = 3135
28027 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbb_rx_acc = 3136
28028 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbub_rt = 3137
28029 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbub_rt_acc = 3138
28030 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbub_rx = 3139
28031 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbub_rx_acc = 3140
28032 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcb_rt = 3141
28033 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcb_rt_acc = 3142
28034 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcb_rx = 3143
28035 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcb_rx_acc = 3144
28036 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcbs_rt = 3145
28037 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcbs_rt_acc = 3146
28038 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcbs_rx = 3147
28039 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcbs_rx_acc = 3148
28040 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyznb_rt = 3149
28041 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyznb_rt_acc = 3150
28042 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyznb_rx = 3151
28043 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyznb_rx_acc = 3152
28044 CEFBS_UseHVXV60, // V6_vror = 3153
28045 CEFBS_UseHVXV66, // V6_vrotr = 3154
28046 CEFBS_UseHVXV60, // V6_vroundhb = 3155
28047 CEFBS_UseHVXV60, // V6_vroundhub = 3156
28048 CEFBS_UseHVXV62, // V6_vrounduhub = 3157
28049 CEFBS_UseHVXV62, // V6_vrounduwuh = 3158
28050 CEFBS_UseHVXV60, // V6_vroundwh = 3159
28051 CEFBS_UseHVXV60, // V6_vroundwuh = 3160
28052 CEFBS_UseHVXV60, // V6_vrsadubi = 3161
28053 CEFBS_UseHVXV60, // V6_vrsadubi_acc = 3162
28054 CEFBS_UseHVXV66, // V6_vsatdw = 3163
28055 CEFBS_UseHVXV60, // V6_vsathub = 3164
28056 CEFBS_UseHVXV62, // V6_vsatuwuh = 3165
28057 CEFBS_UseHVXV60, // V6_vsatwh = 3166
28058 CEFBS_UseHVXV60, // V6_vsb = 3167
28059 CEFBS_UseHVXV65, // V6_vscattermh = 3168
28060 CEFBS_UseHVXV65, // V6_vscattermh_add = 3169
28061 CEFBS_UseHVXV65, // V6_vscattermhq = 3170
28062 CEFBS_UseHVXV65, // V6_vscattermhw = 3171
28063 CEFBS_UseHVXV65, // V6_vscattermhw_add = 3172
28064 CEFBS_UseHVXV65, // V6_vscattermhwq = 3173
28065 CEFBS_UseHVXV65, // V6_vscattermw = 3174
28066 CEFBS_UseHVXV65, // V6_vscattermw_add = 3175
28067 CEFBS_UseHVXV65, // V6_vscattermwq = 3176
28068 CEFBS_UseHVXV60, // V6_vsh = 3177
28069 CEFBS_UseHVXV60, // V6_vshufeh = 3178
28070 CEFBS_UseHVXV60, // V6_vshuff = 3179
28071 CEFBS_UseHVXV60, // V6_vshuffb = 3180
28072 CEFBS_UseHVXV60, // V6_vshuffeb = 3181
28073 CEFBS_UseHVXV60, // V6_vshuffh = 3182
28074 CEFBS_UseHVXV60, // V6_vshuffob = 3183
28075 CEFBS_UseHVXV60, // V6_vshuffvdd = 3184
28076 CEFBS_UseHVXV60, // V6_vshufoeb = 3185
28077 CEFBS_UseHVXV60, // V6_vshufoeh = 3186
28078 CEFBS_UseHVXV60, // V6_vshufoh = 3187
28079 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vsub_hf = 3188
28080 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vsub_hf_hf = 3189
28081 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vsub_qf16 = 3190
28082 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vsub_qf16_mix = 3191
28083 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vsub_qf32 = 3192
28084 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vsub_qf32_mix = 3193
28085 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vsub_sf = 3194
28086 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vsub_sf_bf = 3195
28087 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vsub_sf_hf = 3196
28088 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vsub_sf_sf = 3197
28089 CEFBS_UseHVXV60, // V6_vsubb = 3198
28090 CEFBS_UseHVXV60, // V6_vsubb_dv = 3199
28091 CEFBS_UseHVXV60, // V6_vsubbnq = 3200
28092 CEFBS_UseHVXV60, // V6_vsubbq = 3201
28093 CEFBS_UseHVXV62, // V6_vsubbsat = 3202
28094 CEFBS_UseHVXV62, // V6_vsubbsat_dv = 3203
28095 CEFBS_UseHVXV62, // V6_vsubcarry = 3204
28096 CEFBS_UseHVXV66, // V6_vsubcarryo = 3205
28097 CEFBS_UseHVXV60, // V6_vsubh = 3206
28098 CEFBS_UseHVXV60, // V6_vsubh_dv = 3207
28099 CEFBS_UseHVXV60, // V6_vsubhnq = 3208
28100 CEFBS_UseHVXV60, // V6_vsubhq = 3209
28101 CEFBS_UseHVXV60, // V6_vsubhsat = 3210
28102 CEFBS_UseHVXV60, // V6_vsubhsat_dv = 3211
28103 CEFBS_UseHVXV60, // V6_vsubhw = 3212
28104 CEFBS_UseHVXV60, // V6_vsububh = 3213
28105 CEFBS_UseHVXV60, // V6_vsububsat = 3214
28106 CEFBS_UseHVXV60, // V6_vsububsat_dv = 3215
28107 CEFBS_UseHVXV62, // V6_vsubububb_sat = 3216
28108 CEFBS_UseHVXV60, // V6_vsubuhsat = 3217
28109 CEFBS_UseHVXV60, // V6_vsubuhsat_dv = 3218
28110 CEFBS_UseHVXV60, // V6_vsubuhw = 3219
28111 CEFBS_UseHVXV62, // V6_vsubuwsat = 3220
28112 CEFBS_UseHVXV62, // V6_vsubuwsat_dv = 3221
28113 CEFBS_UseHVXV60, // V6_vsubw = 3222
28114 CEFBS_UseHVXV60, // V6_vsubw_dv = 3223
28115 CEFBS_UseHVXV60, // V6_vsubwnq = 3224
28116 CEFBS_UseHVXV60, // V6_vsubwq = 3225
28117 CEFBS_UseHVXV60, // V6_vsubwsat = 3226
28118 CEFBS_UseHVXV60, // V6_vsubwsat_dv = 3227
28119 CEFBS_UseHVXV60, // V6_vswap = 3228
28120 CEFBS_UseHVXV60, // V6_vtmpyb = 3229
28121 CEFBS_UseHVXV60, // V6_vtmpyb_acc = 3230
28122 CEFBS_UseHVXV60, // V6_vtmpybus = 3231
28123 CEFBS_UseHVXV60, // V6_vtmpybus_acc = 3232
28124 CEFBS_UseHVXV60, // V6_vtmpyhb = 3233
28125 CEFBS_UseHVXV60, // V6_vtmpyhb_acc = 3234
28126 CEFBS_UseHVXV60, // V6_vunpackb = 3235
28127 CEFBS_UseHVXV60, // V6_vunpackh = 3236
28128 CEFBS_UseHVXV60, // V6_vunpackob = 3237
28129 CEFBS_UseHVXV60, // V6_vunpackoh = 3238
28130 CEFBS_UseHVXV60, // V6_vunpackub = 3239
28131 CEFBS_UseHVXV60, // V6_vunpackuh = 3240
28132 CEFBS_UseHVXV62, // V6_vwhist128 = 3241
28133 CEFBS_UseHVXV62, // V6_vwhist128m = 3242
28134 CEFBS_UseHVXV62, // V6_vwhist128q = 3243
28135 CEFBS_UseHVXV62, // V6_vwhist128qm = 3244
28136 CEFBS_UseHVXV62, // V6_vwhist256 = 3245
28137 CEFBS_UseHVXV62, // V6_vwhist256_sat = 3246
28138 CEFBS_UseHVXV62, // V6_vwhist256q = 3247
28139 CEFBS_UseHVXV62, // V6_vwhist256q_sat = 3248
28140 CEFBS_UseHVXV60, // V6_vxor = 3249
28141 CEFBS_UseHVXV60, // V6_vzb = 3250
28142 CEFBS_UseHVXV60, // V6_vzh = 3251
28143 CEFBS_UseHVXV66_UseZReg, // V6_zLd_ai = 3252
28144 CEFBS_UseHVXV66_UseZReg, // V6_zLd_pi = 3253
28145 CEFBS_UseHVXV66_UseZReg, // V6_zLd_ppu = 3254
28146 CEFBS_UseHVXV66_UseZReg, // V6_zLd_pred_ai = 3255
28147 CEFBS_UseHVXV66_UseZReg, // V6_zLd_pred_pi = 3256
28148 CEFBS_UseHVXV66_UseZReg, // V6_zLd_pred_ppu = 3257
28149 CEFBS_UseHVXV66_UseZReg, // V6_zextract = 3258
28150 CEFBS_None, // Y2_barrier = 3259
28151 CEFBS_None, // Y2_break = 3260
28152 CEFBS_None, // Y2_ciad = 3261
28153 CEFBS_None, // Y2_crswap0 = 3262
28154 CEFBS_None, // Y2_cswi = 3263
28155 CEFBS_None, // Y2_dccleana = 3264
28156 CEFBS_None, // Y2_dccleanidx = 3265
28157 CEFBS_None, // Y2_dccleaninva = 3266
28158 CEFBS_None, // Y2_dccleaninvidx = 3267
28159 CEFBS_None, // Y2_dcfetchbo = 3268
28160 CEFBS_None, // Y2_dcinva = 3269
28161 CEFBS_None, // Y2_dcinvidx = 3270
28162 CEFBS_None, // Y2_dckill = 3271
28163 CEFBS_None, // Y2_dctagr = 3272
28164 CEFBS_None, // Y2_dctagw = 3273
28165 CEFBS_None, // Y2_dczeroa = 3274
28166 CEFBS_None, // Y2_getimask = 3275
28167 CEFBS_None, // Y2_iassignr = 3276
28168 CEFBS_None, // Y2_iassignw = 3277
28169 CEFBS_None, // Y2_icdatar = 3278
28170 CEFBS_HasV66, // Y2_icdataw = 3279
28171 CEFBS_None, // Y2_icinva = 3280
28172 CEFBS_None, // Y2_icinvidx = 3281
28173 CEFBS_None, // Y2_ickill = 3282
28174 CEFBS_None, // Y2_ictagr = 3283
28175 CEFBS_None, // Y2_ictagw = 3284
28176 CEFBS_None, // Y2_isync = 3285
28177 CEFBS_None, // Y2_k0lock = 3286
28178 CEFBS_None, // Y2_k0unlock = 3287
28179 CEFBS_None, // Y2_l2cleaninvidx = 3288
28180 CEFBS_None, // Y2_l2kill = 3289
28181 CEFBS_None, // Y2_resume = 3290
28182 CEFBS_None, // Y2_setimask = 3291
28183 CEFBS_HasV66, // Y2_setprio = 3292
28184 CEFBS_None, // Y2_start = 3293
28185 CEFBS_None, // Y2_stop = 3294
28186 CEFBS_None, // Y2_swi = 3295
28187 CEFBS_None, // Y2_syncht = 3296
28188 CEFBS_None, // Y2_tfrscrr = 3297
28189 CEFBS_None, // Y2_tfrsrcr = 3298
28190 CEFBS_None, // Y2_tlblock = 3299
28191 CEFBS_None, // Y2_tlbp = 3300
28192 CEFBS_None, // Y2_tlbr = 3301
28193 CEFBS_None, // Y2_tlbunlock = 3302
28194 CEFBS_None, // Y2_tlbw = 3303
28195 CEFBS_HasV65, // Y2_wait = 3304
28196 CEFBS_None, // Y4_crswap1 = 3305
28197 CEFBS_None, // Y4_crswap10 = 3306
28198 CEFBS_None, // Y4_l2fetch = 3307
28199 CEFBS_None, // Y4_l2tagr = 3308
28200 CEFBS_None, // Y4_l2tagw = 3309
28201 CEFBS_None, // Y4_nmi = 3310
28202 CEFBS_None, // Y4_siad = 3311
28203 CEFBS_None, // Y4_tfrscpp = 3312
28204 CEFBS_None, // Y4_tfrspcp = 3313
28205 CEFBS_None, // Y4_trace = 3314
28206 CEFBS_None, // Y5_ctlbw = 3315
28207 CEFBS_None, // Y5_l2cleanidx = 3316
28208 CEFBS_None, // Y5_l2fetch = 3317
28209 CEFBS_None, // Y5_l2gclean = 3318
28210 CEFBS_None, // Y5_l2gcleaninv = 3319
28211 CEFBS_None, // Y5_l2gunlock = 3320
28212 CEFBS_None, // Y5_l2invidx = 3321
28213 CEFBS_None, // Y5_l2locka = 3322
28214 CEFBS_None, // Y5_l2unlocka = 3323
28215 CEFBS_None, // Y5_tlbasidi = 3324
28216 CEFBS_None, // Y5_tlboc = 3325
28217 CEFBS_HasV67, // Y6_diag = 3326
28218 CEFBS_HasV67, // Y6_diag0 = 3327
28219 CEFBS_HasV67, // Y6_diag1 = 3328
28220 CEFBS_HasV68, // Y6_dmlink = 3329
28221 CEFBS_HasV68, // Y6_dmpause = 3330
28222 CEFBS_HasV68, // Y6_dmpoll = 3331
28223 CEFBS_HasV68, // Y6_dmresume = 3332
28224 CEFBS_HasV68, // Y6_dmstart = 3333
28225 CEFBS_HasV68, // Y6_dmwait = 3334
28226 CEFBS_None, // Y6_l2gcleaninvpa = 3335
28227 CEFBS_None, // Y6_l2gcleanpa = 3336
28228 CEFBS_None, // dep_A2_addsat = 3337
28229 CEFBS_None, // dep_A2_subsat = 3338
28230 CEFBS_None, // dep_S2_packhl = 3339
28231 CEFBS_None, // invalid_decode = 3340
28232 };
28233
28234 assert(Opcode < 3341);
28235 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
28236}
28237
28238} // end namespace Hexagon_MC
28239} // end namespace llvm
28240#endif // GET_COMPUTE_FEATURES
28241
28242#ifdef GET_AVAILABLE_OPCODE_CHECKER
28243#undef GET_AVAILABLE_OPCODE_CHECKER
28244namespace llvm {
28245namespace Hexagon_MC {
28246bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
28247 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
28248 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
28249 FeatureBitset MissingFeatures =
28250 (AvailableFeatures & RequiredFeatures) ^
28251 RequiredFeatures;
28252 return !MissingFeatures.any();
28253}
28254} // end namespace Hexagon_MC
28255} // end namespace llvm
28256#endif // GET_AVAILABLE_OPCODE_CHECKER
28257
28258#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
28259#undef ENABLE_INSTR_PREDICATE_VERIFIER
28260#include <sstream>
28261
28262namespace llvm {
28263namespace Hexagon_MC {
28264
28265#ifndef NDEBUG
28266static const char *SubtargetFeatureNames[] = {
28267 "Feature_HasMemNoShuf",
28268 "Feature_HasPreV65",
28269 "Feature_HasV5",
28270 "Feature_HasV55",
28271 "Feature_HasV60",
28272 "Feature_HasV62",
28273 "Feature_HasV65",
28274 "Feature_HasV66",
28275 "Feature_HasV67",
28276 "Feature_HasV68",
28277 "Feature_HasV69",
28278 "Feature_HasV71",
28279 "Feature_HasV73",
28280 "Feature_UseAudio",
28281 "Feature_UseCabac",
28282 "Feature_UseHVX",
28283 "Feature_UseHVX64B",
28284 "Feature_UseHVX128B",
28285 "Feature_UseHVXIEEEFP",
28286 "Feature_UseHVXQFloat",
28287 "Feature_UseHVXV60",
28288 "Feature_UseHVXV62",
28289 "Feature_UseHVXV65",
28290 "Feature_UseHVXV66",
28291 "Feature_UseHVXV67",
28292 "Feature_UseHVXV68",
28293 "Feature_UseHVXV69",
28294 "Feature_UseHVXV71",
28295 "Feature_UseHVXV73",
28296 "Feature_UseZReg",
28297 nullptr
28298};
28299
28300#endif // NDEBUG
28301
28302void verifyInstructionPredicates(
28303 unsigned Opcode, const FeatureBitset &Features) {
28304#ifndef NDEBUG
28305 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
28306 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
28307 FeatureBitset MissingFeatures =
28308 (AvailableFeatures & RequiredFeatures) ^
28309 RequiredFeatures;
28310 if (MissingFeatures.any()) {
28311 std::ostringstream Msg;
28312 Msg << "Attempting to emit " << &HexagonInstrNameData[HexagonInstrNameIndices[Opcode]]
28313 << " instruction but the ";
28314 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
28315 if (MissingFeatures.test(i))
28316 Msg << SubtargetFeatureNames[i] << " ";
28317 Msg << "predicate(s) are not met";
28318 report_fatal_error(Msg.str().c_str());
28319 }
28320#endif // NDEBUG
28321}
28322} // end namespace Hexagon_MC
28323} // end namespace llvm
28324#endif // ENABLE_INSTR_PREDICATE_VERIFIER
28325
28326#ifdef GET_INSTRMAP_INFO
28327#undef GET_INSTRMAP_INFO
28328namespace llvm {
28329
28330namespace Hexagon {
28331
28332enum InputType {
28333 InputType_reg
28334};
28335
28336enum InstrType {
28337 InstrType_Pseudo,
28338 InstrType_Real
28339};
28340
28341enum NValueST {
28342 NValueST_true,
28343 NValueST_false
28344};
28345
28346enum PNewValue {
28347 PNewValue_new,
28348 PNewValue_
28349};
28350
28351enum PredSense {
28352 PredSense_false,
28353 PredSense_true
28354};
28355
28356enum addrMode {
28357 addrMode_BaseImmOffset,
28358 addrMode_Absolute,
28359 addrMode_PostInc,
28360 addrMode_BaseRegOffset,
28361 addrMode_BaseLongOffset
28362};
28363
28364enum isBrTaken {
28365 isBrTaken_false,
28366 isBrTaken_true
28367};
28368
28369// changeAddrMode_abs_io
28370LLVM_READONLY
28371int changeAddrMode_abs_io(uint16_t Opcode) {
28372static const uint16_t changeAddrMode_abs_ioTable[][2] = {
28373 { Hexagon::L4_ploadrbf_abs, Hexagon::L2_ploadrbf_io },
28374 { Hexagon::L4_ploadrbfnew_abs, Hexagon::L2_ploadrbfnew_io },
28375 { Hexagon::L4_ploadrbt_abs, Hexagon::L2_ploadrbt_io },
28376 { Hexagon::L4_ploadrbtnew_abs, Hexagon::L2_ploadrbtnew_io },
28377 { Hexagon::L4_ploadrdf_abs, Hexagon::L2_ploadrdf_io },
28378 { Hexagon::L4_ploadrdfnew_abs, Hexagon::L2_ploadrdfnew_io },
28379 { Hexagon::L4_ploadrdt_abs, Hexagon::L2_ploadrdt_io },
28380 { Hexagon::L4_ploadrdtnew_abs, Hexagon::L2_ploadrdtnew_io },
28381 { Hexagon::L4_ploadrhf_abs, Hexagon::L2_ploadrhf_io },
28382 { Hexagon::L4_ploadrhfnew_abs, Hexagon::L2_ploadrhfnew_io },
28383 { Hexagon::L4_ploadrht_abs, Hexagon::L2_ploadrht_io },
28384 { Hexagon::L4_ploadrhtnew_abs, Hexagon::L2_ploadrhtnew_io },
28385 { Hexagon::L4_ploadrif_abs, Hexagon::L2_ploadrif_io },
28386 { Hexagon::L4_ploadrifnew_abs, Hexagon::L2_ploadrifnew_io },
28387 { Hexagon::L4_ploadrit_abs, Hexagon::L2_ploadrit_io },
28388 { Hexagon::L4_ploadritnew_abs, Hexagon::L2_ploadritnew_io },
28389 { Hexagon::L4_ploadrubf_abs, Hexagon::L2_ploadrubf_io },
28390 { Hexagon::L4_ploadrubfnew_abs, Hexagon::L2_ploadrubfnew_io },
28391 { Hexagon::L4_ploadrubt_abs, Hexagon::L2_ploadrubt_io },
28392 { Hexagon::L4_ploadrubtnew_abs, Hexagon::L2_ploadrubtnew_io },
28393 { Hexagon::L4_ploadruhf_abs, Hexagon::L2_ploadruhf_io },
28394 { Hexagon::L4_ploadruhfnew_abs, Hexagon::L2_ploadruhfnew_io },
28395 { Hexagon::L4_ploadruht_abs, Hexagon::L2_ploadruht_io },
28396 { Hexagon::L4_ploadruhtnew_abs, Hexagon::L2_ploadruhtnew_io },
28397 { Hexagon::PS_loadrbabs, Hexagon::L2_loadrb_io },
28398 { Hexagon::PS_loadrdabs, Hexagon::L2_loadrd_io },
28399 { Hexagon::PS_loadrhabs, Hexagon::L2_loadrh_io },
28400 { Hexagon::PS_loadriabs, Hexagon::L2_loadri_io },
28401 { Hexagon::PS_loadrubabs, Hexagon::L2_loadrub_io },
28402 { Hexagon::PS_loadruhabs, Hexagon::L2_loadruh_io },
28403 { Hexagon::PS_storerbabs, Hexagon::S2_storerb_io },
28404 { Hexagon::PS_storerbnewabs, Hexagon::S2_storerbnew_io },
28405 { Hexagon::PS_storerdabs, Hexagon::S2_storerd_io },
28406 { Hexagon::PS_storerfabs, Hexagon::S2_storerf_io },
28407 { Hexagon::PS_storerhabs, Hexagon::S2_storerh_io },
28408 { Hexagon::PS_storerhnewabs, Hexagon::S2_storerhnew_io },
28409 { Hexagon::PS_storeriabs, Hexagon::S2_storeri_io },
28410 { Hexagon::PS_storerinewabs, Hexagon::S2_storerinew_io },
28411 { Hexagon::S4_pstorerbf_abs, Hexagon::S2_pstorerbf_io },
28412 { Hexagon::S4_pstorerbfnew_abs, Hexagon::S4_pstorerbfnew_io },
28413 { Hexagon::S4_pstorerbnewf_abs, Hexagon::S2_pstorerbnewf_io },
28414 { Hexagon::S4_pstorerbnewfnew_abs, Hexagon::S4_pstorerbnewfnew_io },
28415 { Hexagon::S4_pstorerbnewt_abs, Hexagon::S2_pstorerbnewt_io },
28416 { Hexagon::S4_pstorerbnewtnew_abs, Hexagon::S4_pstorerbnewtnew_io },
28417 { Hexagon::S4_pstorerbt_abs, Hexagon::S2_pstorerbt_io },
28418 { Hexagon::S4_pstorerbtnew_abs, Hexagon::S4_pstorerbtnew_io },
28419 { Hexagon::S4_pstorerdf_abs, Hexagon::S2_pstorerdf_io },
28420 { Hexagon::S4_pstorerdfnew_abs, Hexagon::S4_pstorerdfnew_io },
28421 { Hexagon::S4_pstorerdt_abs, Hexagon::S2_pstorerdt_io },
28422 { Hexagon::S4_pstorerdtnew_abs, Hexagon::S4_pstorerdtnew_io },
28423 { Hexagon::S4_pstorerff_abs, Hexagon::S2_pstorerff_io },
28424 { Hexagon::S4_pstorerffnew_abs, Hexagon::S4_pstorerffnew_io },
28425 { Hexagon::S4_pstorerft_abs, Hexagon::S2_pstorerft_io },
28426 { Hexagon::S4_pstorerftnew_abs, Hexagon::S4_pstorerftnew_io },
28427 { Hexagon::S4_pstorerhf_abs, Hexagon::S2_pstorerhf_io },
28428 { Hexagon::S4_pstorerhfnew_abs, Hexagon::S4_pstorerhfnew_io },
28429 { Hexagon::S4_pstorerhnewf_abs, Hexagon::S2_pstorerhnewf_io },
28430 { Hexagon::S4_pstorerhnewfnew_abs, Hexagon::S4_pstorerhnewfnew_io },
28431 { Hexagon::S4_pstorerhnewt_abs, Hexagon::S2_pstorerhnewt_io },
28432 { Hexagon::S4_pstorerhnewtnew_abs, Hexagon::S4_pstorerhnewtnew_io },
28433 { Hexagon::S4_pstorerht_abs, Hexagon::S2_pstorerht_io },
28434 { Hexagon::S4_pstorerhtnew_abs, Hexagon::S4_pstorerhtnew_io },
28435 { Hexagon::S4_pstorerif_abs, Hexagon::S2_pstorerif_io },
28436 { Hexagon::S4_pstorerifnew_abs, Hexagon::S4_pstorerifnew_io },
28437 { Hexagon::S4_pstorerinewf_abs, Hexagon::S2_pstorerinewf_io },
28438 { Hexagon::S4_pstorerinewfnew_abs, Hexagon::S4_pstorerinewfnew_io },
28439 { Hexagon::S4_pstorerinewt_abs, Hexagon::S2_pstorerinewt_io },
28440 { Hexagon::S4_pstorerinewtnew_abs, Hexagon::S4_pstorerinewtnew_io },
28441 { Hexagon::S4_pstorerit_abs, Hexagon::S2_pstorerit_io },
28442 { Hexagon::S4_pstoreritnew_abs, Hexagon::S4_pstoreritnew_io },
28443}; // End of changeAddrMode_abs_ioTable
28444
28445 unsigned mid;
28446 unsigned start = 0;
28447 unsigned end = 70;
28448 while (start < end) {
28449 mid = start + (end - start) / 2;
28450 if (Opcode == changeAddrMode_abs_ioTable[mid][0]) {
28451 break;
28452 }
28453 if (Opcode < changeAddrMode_abs_ioTable[mid][0])
28454 end = mid;
28455 else
28456 start = mid + 1;
28457 }
28458 if (start == end)
28459 return -1; // Instruction doesn't exist in this table.
28460
28461 return changeAddrMode_abs_ioTable[mid][1];
28462}
28463
28464// changeAddrMode_io_abs
28465LLVM_READONLY
28466int changeAddrMode_io_abs(uint16_t Opcode) {
28467static const uint16_t changeAddrMode_io_absTable[][2] = {
28468 { Hexagon::L2_loadrb_io, Hexagon::PS_loadrbabs },
28469 { Hexagon::L2_loadrd_io, Hexagon::PS_loadrdabs },
28470 { Hexagon::L2_loadrh_io, Hexagon::PS_loadrhabs },
28471 { Hexagon::L2_loadri_io, Hexagon::PS_loadriabs },
28472 { Hexagon::L2_loadrub_io, Hexagon::PS_loadrubabs },
28473 { Hexagon::L2_loadruh_io, Hexagon::PS_loadruhabs },
28474 { Hexagon::L2_ploadrbf_io, Hexagon::L4_ploadrbf_abs },
28475 { Hexagon::L2_ploadrbfnew_io, Hexagon::L4_ploadrbfnew_abs },
28476 { Hexagon::L2_ploadrbt_io, Hexagon::L4_ploadrbt_abs },
28477 { Hexagon::L2_ploadrbtnew_io, Hexagon::L4_ploadrbtnew_abs },
28478 { Hexagon::L2_ploadrdf_io, Hexagon::L4_ploadrdf_abs },
28479 { Hexagon::L2_ploadrdfnew_io, Hexagon::L4_ploadrdfnew_abs },
28480 { Hexagon::L2_ploadrdt_io, Hexagon::L4_ploadrdt_abs },
28481 { Hexagon::L2_ploadrdtnew_io, Hexagon::L4_ploadrdtnew_abs },
28482 { Hexagon::L2_ploadrhf_io, Hexagon::L4_ploadrhf_abs },
28483 { Hexagon::L2_ploadrhfnew_io, Hexagon::L4_ploadrhfnew_abs },
28484 { Hexagon::L2_ploadrht_io, Hexagon::L4_ploadrht_abs },
28485 { Hexagon::L2_ploadrhtnew_io, Hexagon::L4_ploadrhtnew_abs },
28486 { Hexagon::L2_ploadrif_io, Hexagon::L4_ploadrif_abs },
28487 { Hexagon::L2_ploadrifnew_io, Hexagon::L4_ploadrifnew_abs },
28488 { Hexagon::L2_ploadrit_io, Hexagon::L4_ploadrit_abs },
28489 { Hexagon::L2_ploadritnew_io, Hexagon::L4_ploadritnew_abs },
28490 { Hexagon::L2_ploadrubf_io, Hexagon::L4_ploadrubf_abs },
28491 { Hexagon::L2_ploadrubfnew_io, Hexagon::L4_ploadrubfnew_abs },
28492 { Hexagon::L2_ploadrubt_io, Hexagon::L4_ploadrubt_abs },
28493 { Hexagon::L2_ploadrubtnew_io, Hexagon::L4_ploadrubtnew_abs },
28494 { Hexagon::L2_ploadruhf_io, Hexagon::L4_ploadruhf_abs },
28495 { Hexagon::L2_ploadruhfnew_io, Hexagon::L4_ploadruhfnew_abs },
28496 { Hexagon::L2_ploadruht_io, Hexagon::L4_ploadruht_abs },
28497 { Hexagon::L2_ploadruhtnew_io, Hexagon::L4_ploadruhtnew_abs },
28498 { Hexagon::S2_pstorerbf_io, Hexagon::S4_pstorerbf_abs },
28499 { Hexagon::S2_pstorerbnewf_io, Hexagon::S4_pstorerbnewf_abs },
28500 { Hexagon::S2_pstorerbnewt_io, Hexagon::S4_pstorerbnewt_abs },
28501 { Hexagon::S2_pstorerbt_io, Hexagon::S4_pstorerbt_abs },
28502 { Hexagon::S2_pstorerdf_io, Hexagon::S4_pstorerdf_abs },
28503 { Hexagon::S2_pstorerdt_io, Hexagon::S4_pstorerdt_abs },
28504 { Hexagon::S2_pstorerff_io, Hexagon::S4_pstorerff_abs },
28505 { Hexagon::S2_pstorerft_io, Hexagon::S4_pstorerft_abs },
28506 { Hexagon::S2_pstorerhf_io, Hexagon::S4_pstorerhf_abs },
28507 { Hexagon::S2_pstorerhnewf_io, Hexagon::S4_pstorerhnewf_abs },
28508 { Hexagon::S2_pstorerhnewt_io, Hexagon::S4_pstorerhnewt_abs },
28509 { Hexagon::S2_pstorerht_io, Hexagon::S4_pstorerht_abs },
28510 { Hexagon::S2_pstorerif_io, Hexagon::S4_pstorerif_abs },
28511 { Hexagon::S2_pstorerinewf_io, Hexagon::S4_pstorerinewf_abs },
28512 { Hexagon::S2_pstorerinewt_io, Hexagon::S4_pstorerinewt_abs },
28513 { Hexagon::S2_pstorerit_io, Hexagon::S4_pstorerit_abs },
28514 { Hexagon::S2_storerb_io, Hexagon::PS_storerbabs },
28515 { Hexagon::S2_storerbnew_io, Hexagon::PS_storerbnewabs },
28516 { Hexagon::S2_storerd_io, Hexagon::PS_storerdabs },
28517 { Hexagon::S2_storerf_io, Hexagon::PS_storerfabs },
28518 { Hexagon::S2_storerh_io, Hexagon::PS_storerhabs },
28519 { Hexagon::S2_storerhnew_io, Hexagon::PS_storerhnewabs },
28520 { Hexagon::S2_storeri_io, Hexagon::PS_storeriabs },
28521 { Hexagon::S2_storerinew_io, Hexagon::PS_storerinewabs },
28522 { Hexagon::S4_pstorerbfnew_io, Hexagon::S4_pstorerbfnew_abs },
28523 { Hexagon::S4_pstorerbnewfnew_io, Hexagon::S4_pstorerbnewfnew_abs },
28524 { Hexagon::S4_pstorerbnewtnew_io, Hexagon::S4_pstorerbnewtnew_abs },
28525 { Hexagon::S4_pstorerbtnew_io, Hexagon::S4_pstorerbtnew_abs },
28526 { Hexagon::S4_pstorerdfnew_io, Hexagon::S4_pstorerdfnew_abs },
28527 { Hexagon::S4_pstorerdtnew_io, Hexagon::S4_pstorerdtnew_abs },
28528 { Hexagon::S4_pstorerffnew_io, Hexagon::S4_pstorerffnew_abs },
28529 { Hexagon::S4_pstorerftnew_io, Hexagon::S4_pstorerftnew_abs },
28530 { Hexagon::S4_pstorerhfnew_io, Hexagon::S4_pstorerhfnew_abs },
28531 { Hexagon::S4_pstorerhnewfnew_io, Hexagon::S4_pstorerhnewfnew_abs },
28532 { Hexagon::S4_pstorerhnewtnew_io, Hexagon::S4_pstorerhnewtnew_abs },
28533 { Hexagon::S4_pstorerhtnew_io, Hexagon::S4_pstorerhtnew_abs },
28534 { Hexagon::S4_pstorerifnew_io, Hexagon::S4_pstorerifnew_abs },
28535 { Hexagon::S4_pstorerinewfnew_io, Hexagon::S4_pstorerinewfnew_abs },
28536 { Hexagon::S4_pstorerinewtnew_io, Hexagon::S4_pstorerinewtnew_abs },
28537 { Hexagon::S4_pstoreritnew_io, Hexagon::S4_pstoreritnew_abs },
28538}; // End of changeAddrMode_io_absTable
28539
28540 unsigned mid;
28541 unsigned start = 0;
28542 unsigned end = 70;
28543 while (start < end) {
28544 mid = start + (end - start) / 2;
28545 if (Opcode == changeAddrMode_io_absTable[mid][0]) {
28546 break;
28547 }
28548 if (Opcode < changeAddrMode_io_absTable[mid][0])
28549 end = mid;
28550 else
28551 start = mid + 1;
28552 }
28553 if (start == end)
28554 return -1; // Instruction doesn't exist in this table.
28555
28556 return changeAddrMode_io_absTable[mid][1];
28557}
28558
28559// changeAddrMode_io_pi
28560LLVM_READONLY
28561int changeAddrMode_io_pi(uint16_t Opcode) {
28562static const uint16_t changeAddrMode_io_piTable[][2] = {
28563 { Hexagon::L2_loadrb_io, Hexagon::L2_loadrb_pi },
28564 { Hexagon::L2_loadrd_io, Hexagon::L2_loadrd_pi },
28565 { Hexagon::L2_loadrh_io, Hexagon::L2_loadrh_pi },
28566 { Hexagon::L2_loadri_io, Hexagon::L2_loadri_pi },
28567 { Hexagon::L2_loadrub_io, Hexagon::L2_loadrub_pi },
28568 { Hexagon::L2_loadruh_io, Hexagon::L2_loadruh_pi },
28569 { Hexagon::S2_storerb_io, Hexagon::S2_storerb_pi },
28570 { Hexagon::S2_storerd_io, Hexagon::S2_storerd_pi },
28571 { Hexagon::S2_storerf_io, Hexagon::S2_storerf_pi },
28572 { Hexagon::S2_storerh_io, Hexagon::S2_storerh_pi },
28573 { Hexagon::S2_storeri_io, Hexagon::S2_storeri_pi },
28574 { Hexagon::V6_vL32Ub_ai, Hexagon::V6_vL32Ub_pi },
28575 { Hexagon::V6_vL32b_ai, Hexagon::V6_vL32b_pi },
28576 { Hexagon::V6_vL32b_cur_ai, Hexagon::V6_vL32b_cur_pi },
28577 { Hexagon::V6_vL32b_nt_ai, Hexagon::V6_vL32b_nt_pi },
28578 { Hexagon::V6_vL32b_nt_cur_ai, Hexagon::V6_vL32b_nt_cur_pi },
28579 { Hexagon::V6_vL32b_nt_tmp_ai, Hexagon::V6_vL32b_nt_tmp_pi },
28580 { Hexagon::V6_vL32b_tmp_ai, Hexagon::V6_vL32b_tmp_pi },
28581 { Hexagon::V6_vS32Ub_ai, Hexagon::V6_vS32Ub_pi },
28582 { Hexagon::V6_vS32b_ai, Hexagon::V6_vS32b_pi },
28583 { Hexagon::V6_vS32b_new_ai, Hexagon::V6_vS32b_new_pi },
28584 { Hexagon::V6_vS32b_nt_ai, Hexagon::V6_vS32b_nt_pi },
28585 { Hexagon::V6_vS32b_nt_new_ai, Hexagon::V6_vS32b_nt_new_pi },
28586 { Hexagon::V6_zLd_ai, Hexagon::V6_zLd_pi },
28587}; // End of changeAddrMode_io_piTable
28588
28589 unsigned mid;
28590 unsigned start = 0;
28591 unsigned end = 24;
28592 while (start < end) {
28593 mid = start + (end - start) / 2;
28594 if (Opcode == changeAddrMode_io_piTable[mid][0]) {
28595 break;
28596 }
28597 if (Opcode < changeAddrMode_io_piTable[mid][0])
28598 end = mid;
28599 else
28600 start = mid + 1;
28601 }
28602 if (start == end)
28603 return -1; // Instruction doesn't exist in this table.
28604
28605 return changeAddrMode_io_piTable[mid][1];
28606}
28607
28608// changeAddrMode_io_rr
28609LLVM_READONLY
28610int changeAddrMode_io_rr(uint16_t Opcode) {
28611static const uint16_t changeAddrMode_io_rrTable[][2] = {
28612 { Hexagon::L2_loadrb_io, Hexagon::L4_loadrb_rr },
28613 { Hexagon::L2_loadrd_io, Hexagon::L4_loadrd_rr },
28614 { Hexagon::L2_loadrh_io, Hexagon::L4_loadrh_rr },
28615 { Hexagon::L2_loadri_io, Hexagon::L4_loadri_rr },
28616 { Hexagon::L2_loadrub_io, Hexagon::L4_loadrub_rr },
28617 { Hexagon::L2_loadruh_io, Hexagon::L4_loadruh_rr },
28618 { Hexagon::L2_ploadrbf_io, Hexagon::L4_ploadrbf_rr },
28619 { Hexagon::L2_ploadrbfnew_io, Hexagon::L4_ploadrbfnew_rr },
28620 { Hexagon::L2_ploadrbt_io, Hexagon::L4_ploadrbt_rr },
28621 { Hexagon::L2_ploadrbtnew_io, Hexagon::L4_ploadrbtnew_rr },
28622 { Hexagon::L2_ploadrdf_io, Hexagon::L4_ploadrdf_rr },
28623 { Hexagon::L2_ploadrdfnew_io, Hexagon::L4_ploadrdfnew_rr },
28624 { Hexagon::L2_ploadrdt_io, Hexagon::L4_ploadrdt_rr },
28625 { Hexagon::L2_ploadrdtnew_io, Hexagon::L4_ploadrdtnew_rr },
28626 { Hexagon::L2_ploadrhf_io, Hexagon::L4_ploadrhf_rr },
28627 { Hexagon::L2_ploadrhfnew_io, Hexagon::L4_ploadrhfnew_rr },
28628 { Hexagon::L2_ploadrht_io, Hexagon::L4_ploadrht_rr },
28629 { Hexagon::L2_ploadrhtnew_io, Hexagon::L4_ploadrhtnew_rr },
28630 { Hexagon::L2_ploadrif_io, Hexagon::L4_ploadrif_rr },
28631 { Hexagon::L2_ploadrifnew_io, Hexagon::L4_ploadrifnew_rr },
28632 { Hexagon::L2_ploadrit_io, Hexagon::L4_ploadrit_rr },
28633 { Hexagon::L2_ploadritnew_io, Hexagon::L4_ploadritnew_rr },
28634 { Hexagon::L2_ploadrubf_io, Hexagon::L4_ploadrubf_rr },
28635 { Hexagon::L2_ploadrubfnew_io, Hexagon::L4_ploadrubfnew_rr },
28636 { Hexagon::L2_ploadrubt_io, Hexagon::L4_ploadrubt_rr },
28637 { Hexagon::L2_ploadrubtnew_io, Hexagon::L4_ploadrubtnew_rr },
28638 { Hexagon::L2_ploadruhf_io, Hexagon::L4_ploadruhf_rr },
28639 { Hexagon::L2_ploadruhfnew_io, Hexagon::L4_ploadruhfnew_rr },
28640 { Hexagon::L2_ploadruht_io, Hexagon::L4_ploadruht_rr },
28641 { Hexagon::L2_ploadruhtnew_io, Hexagon::L4_ploadruhtnew_rr },
28642 { Hexagon::S2_pstorerbf_io, Hexagon::S4_pstorerbf_rr },
28643 { Hexagon::S2_pstorerbnewf_io, Hexagon::S4_pstorerbnewf_rr },
28644 { Hexagon::S2_pstorerbnewt_io, Hexagon::S4_pstorerbnewt_rr },
28645 { Hexagon::S2_pstorerbt_io, Hexagon::S4_pstorerbt_rr },
28646 { Hexagon::S2_pstorerdf_io, Hexagon::S4_pstorerdf_rr },
28647 { Hexagon::S2_pstorerdt_io, Hexagon::S4_pstorerdt_rr },
28648 { Hexagon::S2_pstorerff_io, Hexagon::S4_pstorerff_rr },
28649 { Hexagon::S2_pstorerft_io, Hexagon::S4_pstorerft_rr },
28650 { Hexagon::S2_pstorerhf_io, Hexagon::S4_pstorerhf_rr },
28651 { Hexagon::S2_pstorerhnewf_io, Hexagon::S4_pstorerhnewf_rr },
28652 { Hexagon::S2_pstorerhnewt_io, Hexagon::S4_pstorerhnewt_rr },
28653 { Hexagon::S2_pstorerht_io, Hexagon::S4_pstorerht_rr },
28654 { Hexagon::S2_pstorerif_io, Hexagon::S4_pstorerif_rr },
28655 { Hexagon::S2_pstorerinewf_io, Hexagon::S4_pstorerinewf_rr },
28656 { Hexagon::S2_pstorerinewt_io, Hexagon::S4_pstorerinewt_rr },
28657 { Hexagon::S2_pstorerit_io, Hexagon::S4_pstorerit_rr },
28658 { Hexagon::S2_storerb_io, Hexagon::S4_storerb_rr },
28659 { Hexagon::S2_storerbnew_io, Hexagon::S4_storerbnew_rr },
28660 { Hexagon::S2_storerd_io, Hexagon::S4_storerd_rr },
28661 { Hexagon::S2_storerf_io, Hexagon::S4_storerf_rr },
28662 { Hexagon::S2_storerh_io, Hexagon::S4_storerh_rr },
28663 { Hexagon::S2_storerhnew_io, Hexagon::S4_storerhnew_rr },
28664 { Hexagon::S2_storeri_io, Hexagon::S4_storeri_rr },
28665 { Hexagon::S2_storerinew_io, Hexagon::S4_storerinew_rr },
28666 { Hexagon::S4_pstorerbfnew_io, Hexagon::S4_pstorerbfnew_rr },
28667 { Hexagon::S4_pstorerbnewfnew_io, Hexagon::S4_pstorerbnewfnew_rr },
28668 { Hexagon::S4_pstorerbnewtnew_io, Hexagon::S4_pstorerbnewtnew_rr },
28669 { Hexagon::S4_pstorerbtnew_io, Hexagon::S4_pstorerbtnew_rr },
28670 { Hexagon::S4_pstorerdfnew_io, Hexagon::S4_pstorerdfnew_rr },
28671 { Hexagon::S4_pstorerdtnew_io, Hexagon::S4_pstorerdtnew_rr },
28672 { Hexagon::S4_pstorerffnew_io, Hexagon::S4_pstorerffnew_rr },
28673 { Hexagon::S4_pstorerftnew_io, Hexagon::S4_pstorerftnew_rr },
28674 { Hexagon::S4_pstorerhfnew_io, Hexagon::S4_pstorerhfnew_rr },
28675 { Hexagon::S4_pstorerhnewfnew_io, Hexagon::S4_pstorerhnewfnew_rr },
28676 { Hexagon::S4_pstorerhnewtnew_io, Hexagon::S4_pstorerhnewtnew_rr },
28677 { Hexagon::S4_pstorerhtnew_io, Hexagon::S4_pstorerhtnew_rr },
28678 { Hexagon::S4_pstorerifnew_io, Hexagon::S4_pstorerifnew_rr },
28679 { Hexagon::S4_pstorerinewfnew_io, Hexagon::S4_pstorerinewfnew_rr },
28680 { Hexagon::S4_pstorerinewtnew_io, Hexagon::S4_pstorerinewtnew_rr },
28681 { Hexagon::S4_pstoreritnew_io, Hexagon::S4_pstoreritnew_rr },
28682}; // End of changeAddrMode_io_rrTable
28683
28684 unsigned mid;
28685 unsigned start = 0;
28686 unsigned end = 70;
28687 while (start < end) {
28688 mid = start + (end - start) / 2;
28689 if (Opcode == changeAddrMode_io_rrTable[mid][0]) {
28690 break;
28691 }
28692 if (Opcode < changeAddrMode_io_rrTable[mid][0])
28693 end = mid;
28694 else
28695 start = mid + 1;
28696 }
28697 if (start == end)
28698 return -1; // Instruction doesn't exist in this table.
28699
28700 return changeAddrMode_io_rrTable[mid][1];
28701}
28702
28703// changeAddrMode_pi_io
28704LLVM_READONLY
28705int changeAddrMode_pi_io(uint16_t Opcode) {
28706static const uint16_t changeAddrMode_pi_ioTable[][2] = {
28707 { Hexagon::L2_loadrb_pi, Hexagon::L2_loadrb_io },
28708 { Hexagon::L2_loadrd_pi, Hexagon::L2_loadrd_io },
28709 { Hexagon::L2_loadrh_pi, Hexagon::L2_loadrh_io },
28710 { Hexagon::L2_loadri_pi, Hexagon::L2_loadri_io },
28711 { Hexagon::L2_loadrub_pi, Hexagon::L2_loadrub_io },
28712 { Hexagon::L2_loadruh_pi, Hexagon::L2_loadruh_io },
28713 { Hexagon::S2_storerb_pi, Hexagon::S2_storerb_io },
28714 { Hexagon::S2_storerd_pi, Hexagon::S2_storerd_io },
28715 { Hexagon::S2_storerf_pi, Hexagon::S2_storerf_io },
28716 { Hexagon::S2_storerh_pi, Hexagon::S2_storerh_io },
28717 { Hexagon::S2_storeri_pi, Hexagon::S2_storeri_io },
28718 { Hexagon::V6_vL32Ub_pi, Hexagon::V6_vL32Ub_ai },
28719 { Hexagon::V6_vL32b_cur_pi, Hexagon::V6_vL32b_cur_ai },
28720 { Hexagon::V6_vL32b_nt_cur_pi, Hexagon::V6_vL32b_nt_cur_ai },
28721 { Hexagon::V6_vL32b_nt_pi, Hexagon::V6_vL32b_nt_ai },
28722 { Hexagon::V6_vL32b_nt_tmp_pi, Hexagon::V6_vL32b_nt_tmp_ai },
28723 { Hexagon::V6_vL32b_pi, Hexagon::V6_vL32b_ai },
28724 { Hexagon::V6_vL32b_tmp_pi, Hexagon::V6_vL32b_tmp_ai },
28725 { Hexagon::V6_vS32Ub_pi, Hexagon::V6_vS32Ub_ai },
28726 { Hexagon::V6_vS32b_new_pi, Hexagon::V6_vS32b_new_ai },
28727 { Hexagon::V6_vS32b_nt_new_pi, Hexagon::V6_vS32b_nt_new_ai },
28728 { Hexagon::V6_vS32b_nt_pi, Hexagon::V6_vS32b_nt_ai },
28729 { Hexagon::V6_vS32b_pi, Hexagon::V6_vS32b_ai },
28730 { Hexagon::V6_zLd_pi, Hexagon::V6_zLd_ai },
28731}; // End of changeAddrMode_pi_ioTable
28732
28733 unsigned mid;
28734 unsigned start = 0;
28735 unsigned end = 24;
28736 while (start < end) {
28737 mid = start + (end - start) / 2;
28738 if (Opcode == changeAddrMode_pi_ioTable[mid][0]) {
28739 break;
28740 }
28741 if (Opcode < changeAddrMode_pi_ioTable[mid][0])
28742 end = mid;
28743 else
28744 start = mid + 1;
28745 }
28746 if (start == end)
28747 return -1; // Instruction doesn't exist in this table.
28748
28749 return changeAddrMode_pi_ioTable[mid][1];
28750}
28751
28752// changeAddrMode_rr_io
28753LLVM_READONLY
28754int changeAddrMode_rr_io(uint16_t Opcode) {
28755static const uint16_t changeAddrMode_rr_ioTable[][2] = {
28756 { Hexagon::L4_loadrb_rr, Hexagon::L2_loadrb_io },
28757 { Hexagon::L4_loadrd_rr, Hexagon::L2_loadrd_io },
28758 { Hexagon::L4_loadrh_rr, Hexagon::L2_loadrh_io },
28759 { Hexagon::L4_loadri_rr, Hexagon::L2_loadri_io },
28760 { Hexagon::L4_loadrub_rr, Hexagon::L2_loadrub_io },
28761 { Hexagon::L4_loadruh_rr, Hexagon::L2_loadruh_io },
28762 { Hexagon::L4_ploadrbf_rr, Hexagon::L2_ploadrbf_io },
28763 { Hexagon::L4_ploadrbfnew_rr, Hexagon::L2_ploadrbfnew_io },
28764 { Hexagon::L4_ploadrbt_rr, Hexagon::L2_ploadrbt_io },
28765 { Hexagon::L4_ploadrbtnew_rr, Hexagon::L2_ploadrbtnew_io },
28766 { Hexagon::L4_ploadrdf_rr, Hexagon::L2_ploadrdf_io },
28767 { Hexagon::L4_ploadrdfnew_rr, Hexagon::L2_ploadrdfnew_io },
28768 { Hexagon::L4_ploadrdt_rr, Hexagon::L2_ploadrdt_io },
28769 { Hexagon::L4_ploadrdtnew_rr, Hexagon::L2_ploadrdtnew_io },
28770 { Hexagon::L4_ploadrhf_rr, Hexagon::L2_ploadrhf_io },
28771 { Hexagon::L4_ploadrhfnew_rr, Hexagon::L2_ploadrhfnew_io },
28772 { Hexagon::L4_ploadrht_rr, Hexagon::L2_ploadrht_io },
28773 { Hexagon::L4_ploadrhtnew_rr, Hexagon::L2_ploadrhtnew_io },
28774 { Hexagon::L4_ploadrif_rr, Hexagon::L2_ploadrif_io },
28775 { Hexagon::L4_ploadrifnew_rr, Hexagon::L2_ploadrifnew_io },
28776 { Hexagon::L4_ploadrit_rr, Hexagon::L2_ploadrit_io },
28777 { Hexagon::L4_ploadritnew_rr, Hexagon::L2_ploadritnew_io },
28778 { Hexagon::L4_ploadrubf_rr, Hexagon::L2_ploadrubf_io },
28779 { Hexagon::L4_ploadrubfnew_rr, Hexagon::L2_ploadrubfnew_io },
28780 { Hexagon::L4_ploadrubt_rr, Hexagon::L2_ploadrubt_io },
28781 { Hexagon::L4_ploadrubtnew_rr, Hexagon::L2_ploadrubtnew_io },
28782 { Hexagon::L4_ploadruhf_rr, Hexagon::L2_ploadruhf_io },
28783 { Hexagon::L4_ploadruhfnew_rr, Hexagon::L2_ploadruhfnew_io },
28784 { Hexagon::L4_ploadruht_rr, Hexagon::L2_ploadruht_io },
28785 { Hexagon::L4_ploadruhtnew_rr, Hexagon::L2_ploadruhtnew_io },
28786 { Hexagon::S4_pstorerbf_rr, Hexagon::S2_pstorerbf_io },
28787 { Hexagon::S4_pstorerbfnew_rr, Hexagon::S4_pstorerbfnew_io },
28788 { Hexagon::S4_pstorerbnewf_rr, Hexagon::S2_pstorerbnewf_io },
28789 { Hexagon::S4_pstorerbnewfnew_rr, Hexagon::S4_pstorerbnewfnew_io },
28790 { Hexagon::S4_pstorerbnewt_rr, Hexagon::S2_pstorerbnewt_io },
28791 { Hexagon::S4_pstorerbnewtnew_rr, Hexagon::S4_pstorerbnewtnew_io },
28792 { Hexagon::S4_pstorerbt_rr, Hexagon::S2_pstorerbt_io },
28793 { Hexagon::S4_pstorerbtnew_rr, Hexagon::S4_pstorerbtnew_io },
28794 { Hexagon::S4_pstorerdf_rr, Hexagon::S2_pstorerdf_io },
28795 { Hexagon::S4_pstorerdfnew_rr, Hexagon::S4_pstorerdfnew_io },
28796 { Hexagon::S4_pstorerdt_rr, Hexagon::S2_pstorerdt_io },
28797 { Hexagon::S4_pstorerdtnew_rr, Hexagon::S4_pstorerdtnew_io },
28798 { Hexagon::S4_pstorerff_rr, Hexagon::S2_pstorerff_io },
28799 { Hexagon::S4_pstorerffnew_rr, Hexagon::S4_pstorerffnew_io },
28800 { Hexagon::S4_pstorerft_rr, Hexagon::S2_pstorerft_io },
28801 { Hexagon::S4_pstorerftnew_rr, Hexagon::S4_pstorerftnew_io },
28802 { Hexagon::S4_pstorerhf_rr, Hexagon::S2_pstorerhf_io },
28803 { Hexagon::S4_pstorerhfnew_rr, Hexagon::S4_pstorerhfnew_io },
28804 { Hexagon::S4_pstorerhnewf_rr, Hexagon::S2_pstorerhnewf_io },
28805 { Hexagon::S4_pstorerhnewfnew_rr, Hexagon::S4_pstorerhnewfnew_io },
28806 { Hexagon::S4_pstorerhnewt_rr, Hexagon::S2_pstorerhnewt_io },
28807 { Hexagon::S4_pstorerhnewtnew_rr, Hexagon::S4_pstorerhnewtnew_io },
28808 { Hexagon::S4_pstorerht_rr, Hexagon::S2_pstorerht_io },
28809 { Hexagon::S4_pstorerhtnew_rr, Hexagon::S4_pstorerhtnew_io },
28810 { Hexagon::S4_pstorerif_rr, Hexagon::S2_pstorerif_io },
28811 { Hexagon::S4_pstorerifnew_rr, Hexagon::S4_pstorerifnew_io },
28812 { Hexagon::S4_pstorerinewf_rr, Hexagon::S2_pstorerinewf_io },
28813 { Hexagon::S4_pstorerinewfnew_rr, Hexagon::S4_pstorerinewfnew_io },
28814 { Hexagon::S4_pstorerinewt_rr, Hexagon::S2_pstorerinewt_io },
28815 { Hexagon::S4_pstorerinewtnew_rr, Hexagon::S4_pstorerinewtnew_io },
28816 { Hexagon::S4_pstorerit_rr, Hexagon::S2_pstorerit_io },
28817 { Hexagon::S4_pstoreritnew_rr, Hexagon::S4_pstoreritnew_io },
28818 { Hexagon::S4_storerb_rr, Hexagon::S2_storerb_io },
28819 { Hexagon::S4_storerbnew_rr, Hexagon::S2_storerbnew_io },
28820 { Hexagon::S4_storerd_rr, Hexagon::S2_storerd_io },
28821 { Hexagon::S4_storerf_rr, Hexagon::S2_storerf_io },
28822 { Hexagon::S4_storerh_rr, Hexagon::S2_storerh_io },
28823 { Hexagon::S4_storerhnew_rr, Hexagon::S2_storerhnew_io },
28824 { Hexagon::S4_storeri_rr, Hexagon::S2_storeri_io },
28825 { Hexagon::S4_storerinew_rr, Hexagon::S2_storerinew_io },
28826}; // End of changeAddrMode_rr_ioTable
28827
28828 unsigned mid;
28829 unsigned start = 0;
28830 unsigned end = 70;
28831 while (start < end) {
28832 mid = start + (end - start) / 2;
28833 if (Opcode == changeAddrMode_rr_ioTable[mid][0]) {
28834 break;
28835 }
28836 if (Opcode < changeAddrMode_rr_ioTable[mid][0])
28837 end = mid;
28838 else
28839 start = mid + 1;
28840 }
28841 if (start == end)
28842 return -1; // Instruction doesn't exist in this table.
28843
28844 return changeAddrMode_rr_ioTable[mid][1];
28845}
28846
28847// changeAddrMode_rr_ur
28848LLVM_READONLY
28849int changeAddrMode_rr_ur(uint16_t Opcode) {
28850static const uint16_t changeAddrMode_rr_urTable[][2] = {
28851 { Hexagon::L4_loadrb_rr, Hexagon::L4_loadrb_ur },
28852 { Hexagon::L4_loadrd_rr, Hexagon::L4_loadrd_ur },
28853 { Hexagon::L4_loadrh_rr, Hexagon::L4_loadrh_ur },
28854 { Hexagon::L4_loadri_rr, Hexagon::L4_loadri_ur },
28855 { Hexagon::L4_loadrub_rr, Hexagon::L4_loadrub_ur },
28856 { Hexagon::L4_loadruh_rr, Hexagon::L4_loadruh_ur },
28857 { Hexagon::S4_storerb_rr, Hexagon::S4_storerb_ur },
28858 { Hexagon::S4_storerd_rr, Hexagon::S4_storerd_ur },
28859 { Hexagon::S4_storerf_rr, Hexagon::S4_storerf_ur },
28860 { Hexagon::S4_storerh_rr, Hexagon::S4_storerh_ur },
28861 { Hexagon::S4_storeri_rr, Hexagon::S4_storeri_ur },
28862}; // End of changeAddrMode_rr_urTable
28863
28864 unsigned mid;
28865 unsigned start = 0;
28866 unsigned end = 11;
28867 while (start < end) {
28868 mid = start + (end - start) / 2;
28869 if (Opcode == changeAddrMode_rr_urTable[mid][0]) {
28870 break;
28871 }
28872 if (Opcode < changeAddrMode_rr_urTable[mid][0])
28873 end = mid;
28874 else
28875 start = mid + 1;
28876 }
28877 if (start == end)
28878 return -1; // Instruction doesn't exist in this table.
28879
28880 return changeAddrMode_rr_urTable[mid][1];
28881}
28882
28883// changeAddrMode_ur_rr
28884LLVM_READONLY
28885int changeAddrMode_ur_rr(uint16_t Opcode) {
28886static const uint16_t changeAddrMode_ur_rrTable[][2] = {
28887 { Hexagon::L4_loadrb_ur, Hexagon::L4_loadrb_rr },
28888 { Hexagon::L4_loadrd_ur, Hexagon::L4_loadrd_rr },
28889 { Hexagon::L4_loadrh_ur, Hexagon::L4_loadrh_rr },
28890 { Hexagon::L4_loadri_ur, Hexagon::L4_loadri_rr },
28891 { Hexagon::L4_loadrub_ur, Hexagon::L4_loadrub_rr },
28892 { Hexagon::L4_loadruh_ur, Hexagon::L4_loadruh_rr },
28893 { Hexagon::S4_storerb_ur, Hexagon::S4_storerb_rr },
28894 { Hexagon::S4_storerd_ur, Hexagon::S4_storerd_rr },
28895 { Hexagon::S4_storerf_ur, Hexagon::S4_storerf_rr },
28896 { Hexagon::S4_storerh_ur, Hexagon::S4_storerh_rr },
28897 { Hexagon::S4_storeri_ur, Hexagon::S4_storeri_rr },
28898}; // End of changeAddrMode_ur_rrTable
28899
28900 unsigned mid;
28901 unsigned start = 0;
28902 unsigned end = 11;
28903 while (start < end) {
28904 mid = start + (end - start) / 2;
28905 if (Opcode == changeAddrMode_ur_rrTable[mid][0]) {
28906 break;
28907 }
28908 if (Opcode < changeAddrMode_ur_rrTable[mid][0])
28909 end = mid;
28910 else
28911 start = mid + 1;
28912 }
28913 if (start == end)
28914 return -1; // Instruction doesn't exist in this table.
28915
28916 return changeAddrMode_ur_rrTable[mid][1];
28917}
28918
28919// getFalsePredOpcode
28920LLVM_READONLY
28921int getFalsePredOpcode(uint16_t Opcode) {
28922static const uint16_t getFalsePredOpcodeTable[][2] = {
28923 { Hexagon::A2_tfrpt, Hexagon::A2_tfrpf },
28924 { Hexagon::A2_tfrptnew, Hexagon::A2_tfrpfnew },
28925 { Hexagon::A2_tfrt, Hexagon::A2_tfrf },
28926 { Hexagon::A2_tfrtnew, Hexagon::A2_tfrfnew },
28927 { Hexagon::A2_paddit, Hexagon::A2_paddif },
28928 { Hexagon::A2_padditnew, Hexagon::A2_paddifnew },
28929 { Hexagon::A2_paddt, Hexagon::A2_paddf },
28930 { Hexagon::A2_paddtnew, Hexagon::A2_paddfnew },
28931 { Hexagon::A2_pandt, Hexagon::A2_pandf },
28932 { Hexagon::A2_pandtnew, Hexagon::A2_pandfnew },
28933 { Hexagon::A2_port, Hexagon::A2_porf },
28934 { Hexagon::A2_portnew, Hexagon::A2_porfnew },
28935 { Hexagon::A2_psubt, Hexagon::A2_psubf },
28936 { Hexagon::A2_psubtnew, Hexagon::A2_psubfnew },
28937 { Hexagon::A2_pxort, Hexagon::A2_pxorf },
28938 { Hexagon::A2_pxortnew, Hexagon::A2_pxorfnew },
28939 { Hexagon::A4_paslht, Hexagon::A4_paslhf },
28940 { Hexagon::A4_paslhtnew, Hexagon::A4_paslhfnew },
28941 { Hexagon::A4_pasrht, Hexagon::A4_pasrhf },
28942 { Hexagon::A4_pasrhtnew, Hexagon::A4_pasrhfnew },
28943 { Hexagon::A4_psxtbt, Hexagon::A4_psxtbf },
28944 { Hexagon::A4_psxtbtnew, Hexagon::A4_psxtbfnew },
28945 { Hexagon::A4_psxtht, Hexagon::A4_psxthf },
28946 { Hexagon::A4_psxthtnew, Hexagon::A4_psxthfnew },
28947 { Hexagon::A4_pzxtbt, Hexagon::A4_pzxtbf },
28948 { Hexagon::A4_pzxtbtnew, Hexagon::A4_pzxtbfnew },
28949 { Hexagon::A4_pzxtht, Hexagon::A4_pzxthf },
28950 { Hexagon::A4_pzxthtnew, Hexagon::A4_pzxthfnew },
28951 { Hexagon::C2_ccombinewnewt, Hexagon::C2_ccombinewnewf },
28952 { Hexagon::C2_ccombinewt, Hexagon::C2_ccombinewf },
28953 { Hexagon::C2_cmoveit, Hexagon::C2_cmoveif },
28954 { Hexagon::C2_cmovenewit, Hexagon::C2_cmovenewif },
28955 { Hexagon::J2_callt, Hexagon::J2_callf },
28956 { Hexagon::J2_jumprt, Hexagon::J2_jumprf },
28957 { Hexagon::J2_jumprtnew, Hexagon::J2_jumprfnew },
28958 { Hexagon::J2_jumprtnewpt, Hexagon::J2_jumprfnewpt },
28959 { Hexagon::J2_jumprtpt, Hexagon::J2_jumprfpt },
28960 { Hexagon::J2_jumpt, Hexagon::J2_jumpf },
28961 { Hexagon::J2_jumptnew, Hexagon::J2_jumpfnew },
28962 { Hexagon::J2_jumptnewpt, Hexagon::J2_jumpfnewpt },
28963 { Hexagon::J2_jumptpt, Hexagon::J2_jumpfpt },
28964 { Hexagon::J4_cmpeq_t_jumpnv_nt, Hexagon::J4_cmpeq_f_jumpnv_nt },
28965 { Hexagon::J4_cmpeq_t_jumpnv_t, Hexagon::J4_cmpeq_f_jumpnv_t },
28966 { Hexagon::J4_cmpeq_tp0_jump_nt, Hexagon::J4_cmpeq_fp0_jump_nt },
28967 { Hexagon::J4_cmpeq_tp0_jump_t, Hexagon::J4_cmpeq_fp0_jump_t },
28968 { Hexagon::J4_cmpeq_tp1_jump_nt, Hexagon::J4_cmpeq_fp1_jump_nt },
28969 { Hexagon::J4_cmpeq_tp1_jump_t, Hexagon::J4_cmpeq_fp1_jump_t },
28970 { Hexagon::J4_cmpeqi_t_jumpnv_nt, Hexagon::J4_cmpeqi_f_jumpnv_nt },
28971 { Hexagon::J4_cmpeqi_t_jumpnv_t, Hexagon::J4_cmpeqi_f_jumpnv_t },
28972 { Hexagon::J4_cmpeqi_tp0_jump_nt, Hexagon::J4_cmpeqi_fp0_jump_nt },
28973 { Hexagon::J4_cmpeqi_tp0_jump_t, Hexagon::J4_cmpeqi_fp0_jump_t },
28974 { Hexagon::J4_cmpeqi_tp1_jump_nt, Hexagon::J4_cmpeqi_fp1_jump_nt },
28975 { Hexagon::J4_cmpeqi_tp1_jump_t, Hexagon::J4_cmpeqi_fp1_jump_t },
28976 { Hexagon::J4_cmpeqn1_t_jumpnv_nt, Hexagon::J4_cmpeqn1_f_jumpnv_nt },
28977 { Hexagon::J4_cmpeqn1_t_jumpnv_t, Hexagon::J4_cmpeqn1_f_jumpnv_t },
28978 { Hexagon::J4_cmpeqn1_tp0_jump_nt, Hexagon::J4_cmpeqn1_fp0_jump_nt },
28979 { Hexagon::J4_cmpeqn1_tp0_jump_t, Hexagon::J4_cmpeqn1_fp0_jump_t },
28980 { Hexagon::J4_cmpeqn1_tp1_jump_nt, Hexagon::J4_cmpeqn1_fp1_jump_nt },
28981 { Hexagon::J4_cmpeqn1_tp1_jump_t, Hexagon::J4_cmpeqn1_fp1_jump_t },
28982 { Hexagon::J4_cmpgt_t_jumpnv_nt, Hexagon::J4_cmpgt_f_jumpnv_nt },
28983 { Hexagon::J4_cmpgt_t_jumpnv_t, Hexagon::J4_cmpgt_f_jumpnv_t },
28984 { Hexagon::J4_cmpgt_tp0_jump_nt, Hexagon::J4_cmpgt_fp0_jump_nt },
28985 { Hexagon::J4_cmpgt_tp0_jump_t, Hexagon::J4_cmpgt_fp0_jump_t },
28986 { Hexagon::J4_cmpgt_tp1_jump_nt, Hexagon::J4_cmpgt_fp1_jump_nt },
28987 { Hexagon::J4_cmpgt_tp1_jump_t, Hexagon::J4_cmpgt_fp1_jump_t },
28988 { Hexagon::J4_cmpgti_t_jumpnv_nt, Hexagon::J4_cmpgti_f_jumpnv_nt },
28989 { Hexagon::J4_cmpgti_t_jumpnv_t, Hexagon::J4_cmpgti_f_jumpnv_t },
28990 { Hexagon::J4_cmpgti_tp0_jump_nt, Hexagon::J4_cmpgti_fp0_jump_nt },
28991 { Hexagon::J4_cmpgti_tp0_jump_t, Hexagon::J4_cmpgti_fp0_jump_t },
28992 { Hexagon::J4_cmpgti_tp1_jump_nt, Hexagon::J4_cmpgti_fp1_jump_nt },
28993 { Hexagon::J4_cmpgti_tp1_jump_t, Hexagon::J4_cmpgti_fp1_jump_t },
28994 { Hexagon::J4_cmpgtn1_t_jumpnv_nt, Hexagon::J4_cmpgtn1_f_jumpnv_nt },
28995 { Hexagon::J4_cmpgtn1_t_jumpnv_t, Hexagon::J4_cmpgtn1_f_jumpnv_t },
28996 { Hexagon::J4_cmpgtn1_tp0_jump_nt, Hexagon::J4_cmpgtn1_fp0_jump_nt },
28997 { Hexagon::J4_cmpgtn1_tp0_jump_t, Hexagon::J4_cmpgtn1_fp0_jump_t },
28998 { Hexagon::J4_cmpgtn1_tp1_jump_nt, Hexagon::J4_cmpgtn1_fp1_jump_nt },
28999 { Hexagon::J4_cmpgtn1_tp1_jump_t, Hexagon::J4_cmpgtn1_fp1_jump_t },
29000 { Hexagon::J4_cmpgtu_t_jumpnv_nt, Hexagon::J4_cmpgtu_f_jumpnv_nt },
29001 { Hexagon::J4_cmpgtu_t_jumpnv_t, Hexagon::J4_cmpgtu_f_jumpnv_t },
29002 { Hexagon::J4_cmpgtu_tp0_jump_nt, Hexagon::J4_cmpgtu_fp0_jump_nt },
29003 { Hexagon::J4_cmpgtu_tp0_jump_t, Hexagon::J4_cmpgtu_fp0_jump_t },
29004 { Hexagon::J4_cmpgtu_tp1_jump_nt, Hexagon::J4_cmpgtu_fp1_jump_nt },
29005 { Hexagon::J4_cmpgtu_tp1_jump_t, Hexagon::J4_cmpgtu_fp1_jump_t },
29006 { Hexagon::J4_cmpgtui_t_jumpnv_nt, Hexagon::J4_cmpgtui_f_jumpnv_nt },
29007 { Hexagon::J4_cmpgtui_t_jumpnv_t, Hexagon::J4_cmpgtui_f_jumpnv_t },
29008 { Hexagon::J4_cmpgtui_tp0_jump_nt, Hexagon::J4_cmpgtui_fp0_jump_nt },
29009 { Hexagon::J4_cmpgtui_tp0_jump_t, Hexagon::J4_cmpgtui_fp0_jump_t },
29010 { Hexagon::J4_cmpgtui_tp1_jump_nt, Hexagon::J4_cmpgtui_fp1_jump_nt },
29011 { Hexagon::J4_cmpgtui_tp1_jump_t, Hexagon::J4_cmpgtui_fp1_jump_t },
29012 { Hexagon::J4_cmplt_t_jumpnv_nt, Hexagon::J4_cmplt_f_jumpnv_nt },
29013 { Hexagon::J4_cmplt_t_jumpnv_t, Hexagon::J4_cmplt_f_jumpnv_t },
29014 { Hexagon::J4_cmpltu_t_jumpnv_nt, Hexagon::J4_cmpltu_f_jumpnv_nt },
29015 { Hexagon::J4_cmpltu_t_jumpnv_t, Hexagon::J4_cmpltu_f_jumpnv_t },
29016 { Hexagon::L2_ploadrbt_io, Hexagon::L2_ploadrbf_io },
29017 { Hexagon::L2_ploadrbt_pi, Hexagon::L2_ploadrbf_pi },
29018 { Hexagon::L2_ploadrbtnew_io, Hexagon::L2_ploadrbfnew_io },
29019 { Hexagon::L2_ploadrbtnew_pi, Hexagon::L2_ploadrbfnew_pi },
29020 { Hexagon::L2_ploadrdt_io, Hexagon::L2_ploadrdf_io },
29021 { Hexagon::L2_ploadrdt_pi, Hexagon::L2_ploadrdf_pi },
29022 { Hexagon::L2_ploadrdtnew_io, Hexagon::L2_ploadrdfnew_io },
29023 { Hexagon::L2_ploadrdtnew_pi, Hexagon::L2_ploadrdfnew_pi },
29024 { Hexagon::L2_ploadrht_io, Hexagon::L2_ploadrhf_io },
29025 { Hexagon::L2_ploadrht_pi, Hexagon::L2_ploadrhf_pi },
29026 { Hexagon::L2_ploadrhtnew_io, Hexagon::L2_ploadrhfnew_io },
29027 { Hexagon::L2_ploadrhtnew_pi, Hexagon::L2_ploadrhfnew_pi },
29028 { Hexagon::L2_ploadrit_io, Hexagon::L2_ploadrif_io },
29029 { Hexagon::L2_ploadrit_pi, Hexagon::L2_ploadrif_pi },
29030 { Hexagon::L2_ploadritnew_io, Hexagon::L2_ploadrifnew_io },
29031 { Hexagon::L2_ploadritnew_pi, Hexagon::L2_ploadrifnew_pi },
29032 { Hexagon::L2_ploadrubt_io, Hexagon::L2_ploadrubf_io },
29033 { Hexagon::L2_ploadrubt_pi, Hexagon::L2_ploadrubf_pi },
29034 { Hexagon::L2_ploadrubtnew_io, Hexagon::L2_ploadrubfnew_io },
29035 { Hexagon::L2_ploadrubtnew_pi, Hexagon::L2_ploadrubfnew_pi },
29036 { Hexagon::L2_ploadruht_io, Hexagon::L2_ploadruhf_io },
29037 { Hexagon::L2_ploadruht_pi, Hexagon::L2_ploadruhf_pi },
29038 { Hexagon::L2_ploadruhtnew_io, Hexagon::L2_ploadruhfnew_io },
29039 { Hexagon::L2_ploadruhtnew_pi, Hexagon::L2_ploadruhfnew_pi },
29040 { Hexagon::L4_ploadrbt_abs, Hexagon::L4_ploadrbf_abs },
29041 { Hexagon::L4_ploadrbt_rr, Hexagon::L4_ploadrbf_rr },
29042 { Hexagon::L4_ploadrbtnew_abs, Hexagon::L4_ploadrbfnew_abs },
29043 { Hexagon::L4_ploadrbtnew_rr, Hexagon::L4_ploadrbfnew_rr },
29044 { Hexagon::L4_ploadrdt_abs, Hexagon::L4_ploadrdf_abs },
29045 { Hexagon::L4_ploadrdt_rr, Hexagon::L4_ploadrdf_rr },
29046 { Hexagon::L4_ploadrdtnew_abs, Hexagon::L4_ploadrdfnew_abs },
29047 { Hexagon::L4_ploadrdtnew_rr, Hexagon::L4_ploadrdfnew_rr },
29048 { Hexagon::L4_ploadrht_abs, Hexagon::L4_ploadrhf_abs },
29049 { Hexagon::L4_ploadrht_rr, Hexagon::L4_ploadrhf_rr },
29050 { Hexagon::L4_ploadrhtnew_abs, Hexagon::L4_ploadrhfnew_abs },
29051 { Hexagon::L4_ploadrhtnew_rr, Hexagon::L4_ploadrhfnew_rr },
29052 { Hexagon::L4_ploadrit_abs, Hexagon::L4_ploadrif_abs },
29053 { Hexagon::L4_ploadrit_rr, Hexagon::L4_ploadrif_rr },
29054 { Hexagon::L4_ploadritnew_abs, Hexagon::L4_ploadrifnew_abs },
29055 { Hexagon::L4_ploadritnew_rr, Hexagon::L4_ploadrifnew_rr },
29056 { Hexagon::L4_ploadrubt_abs, Hexagon::L4_ploadrubf_abs },
29057 { Hexagon::L4_ploadrubt_rr, Hexagon::L4_ploadrubf_rr },
29058 { Hexagon::L4_ploadrubtnew_abs, Hexagon::L4_ploadrubfnew_abs },
29059 { Hexagon::L4_ploadrubtnew_rr, Hexagon::L4_ploadrubfnew_rr },
29060 { Hexagon::L4_ploadruht_abs, Hexagon::L4_ploadruhf_abs },
29061 { Hexagon::L4_ploadruht_rr, Hexagon::L4_ploadruhf_rr },
29062 { Hexagon::L4_ploadruhtnew_abs, Hexagon::L4_ploadruhfnew_abs },
29063 { Hexagon::L4_ploadruhtnew_rr, Hexagon::L4_ploadruhfnew_rr },
29064 { Hexagon::L4_return_t, Hexagon::L4_return_f },
29065 { Hexagon::L4_return_tnew_pnt, Hexagon::L4_return_fnew_pnt },
29066 { Hexagon::L4_return_tnew_pt, Hexagon::L4_return_fnew_pt },
29067 { Hexagon::PS_jmprett, Hexagon::PS_jmpretf },
29068 { Hexagon::PS_jmprettnew, Hexagon::PS_jmpretfnew },
29069 { Hexagon::PS_jmprettnewpt, Hexagon::PS_jmpretfnewpt },
29070 { Hexagon::S2_pstorerbnewt_io, Hexagon::S2_pstorerbnewf_io },
29071 { Hexagon::S2_pstorerbnewt_pi, Hexagon::S2_pstorerbnewf_pi },
29072 { Hexagon::S2_pstorerbnewtnew_pi, Hexagon::S2_pstorerbnewfnew_pi },
29073 { Hexagon::S2_pstorerbt_io, Hexagon::S2_pstorerbf_io },
29074 { Hexagon::S2_pstorerbt_pi, Hexagon::S2_pstorerbf_pi },
29075 { Hexagon::S2_pstorerbtnew_pi, Hexagon::S2_pstorerbfnew_pi },
29076 { Hexagon::S2_pstorerdt_io, Hexagon::S2_pstorerdf_io },
29077 { Hexagon::S2_pstorerdt_pi, Hexagon::S2_pstorerdf_pi },
29078 { Hexagon::S2_pstorerdtnew_pi, Hexagon::S2_pstorerdfnew_pi },
29079 { Hexagon::S2_pstorerft_io, Hexagon::S2_pstorerff_io },
29080 { Hexagon::S2_pstorerft_pi, Hexagon::S2_pstorerff_pi },
29081 { Hexagon::S2_pstorerftnew_pi, Hexagon::S2_pstorerffnew_pi },
29082 { Hexagon::S2_pstorerhnewt_io, Hexagon::S2_pstorerhnewf_io },
29083 { Hexagon::S2_pstorerhnewt_pi, Hexagon::S2_pstorerhnewf_pi },
29084 { Hexagon::S2_pstorerhnewtnew_pi, Hexagon::S2_pstorerhnewfnew_pi },
29085 { Hexagon::S2_pstorerht_io, Hexagon::S2_pstorerhf_io },
29086 { Hexagon::S2_pstorerht_pi, Hexagon::S2_pstorerhf_pi },
29087 { Hexagon::S2_pstorerhtnew_pi, Hexagon::S2_pstorerhfnew_pi },
29088 { Hexagon::S2_pstorerinewt_io, Hexagon::S2_pstorerinewf_io },
29089 { Hexagon::S2_pstorerinewt_pi, Hexagon::S2_pstorerinewf_pi },
29090 { Hexagon::S2_pstorerinewtnew_pi, Hexagon::S2_pstorerinewfnew_pi },
29091 { Hexagon::S2_pstorerit_io, Hexagon::S2_pstorerif_io },
29092 { Hexagon::S2_pstorerit_pi, Hexagon::S2_pstorerif_pi },
29093 { Hexagon::S2_pstoreritnew_pi, Hexagon::S2_pstorerifnew_pi },
29094 { Hexagon::S4_pstorerbnewt_abs, Hexagon::S4_pstorerbnewf_abs },
29095 { Hexagon::S4_pstorerbnewt_rr, Hexagon::S4_pstorerbnewf_rr },
29096 { Hexagon::S4_pstorerbnewtnew_abs, Hexagon::S4_pstorerbnewfnew_abs },
29097 { Hexagon::S4_pstorerbnewtnew_io, Hexagon::S4_pstorerbnewfnew_io },
29098 { Hexagon::S4_pstorerbnewtnew_rr, Hexagon::S4_pstorerbnewfnew_rr },
29099 { Hexagon::S4_pstorerbt_abs, Hexagon::S4_pstorerbf_abs },
29100 { Hexagon::S4_pstorerbt_rr, Hexagon::S4_pstorerbf_rr },
29101 { Hexagon::S4_pstorerbtnew_abs, Hexagon::S4_pstorerbfnew_abs },
29102 { Hexagon::S4_pstorerbtnew_io, Hexagon::S4_pstorerbfnew_io },
29103 { Hexagon::S4_pstorerbtnew_rr, Hexagon::S4_pstorerbfnew_rr },
29104 { Hexagon::S4_pstorerdt_abs, Hexagon::S4_pstorerdf_abs },
29105 { Hexagon::S4_pstorerdt_rr, Hexagon::S4_pstorerdf_rr },
29106 { Hexagon::S4_pstorerdtnew_abs, Hexagon::S4_pstorerdfnew_abs },
29107 { Hexagon::S4_pstorerdtnew_io, Hexagon::S4_pstorerdfnew_io },
29108 { Hexagon::S4_pstorerdtnew_rr, Hexagon::S4_pstorerdfnew_rr },
29109 { Hexagon::S4_pstorerft_abs, Hexagon::S4_pstorerff_abs },
29110 { Hexagon::S4_pstorerft_rr, Hexagon::S4_pstorerff_rr },
29111 { Hexagon::S4_pstorerftnew_abs, Hexagon::S4_pstorerffnew_abs },
29112 { Hexagon::S4_pstorerftnew_io, Hexagon::S4_pstorerffnew_io },
29113 { Hexagon::S4_pstorerftnew_rr, Hexagon::S4_pstorerffnew_rr },
29114 { Hexagon::S4_pstorerhnewt_abs, Hexagon::S4_pstorerhnewf_abs },
29115 { Hexagon::S4_pstorerhnewt_rr, Hexagon::S4_pstorerhnewf_rr },
29116 { Hexagon::S4_pstorerhnewtnew_abs, Hexagon::S4_pstorerhnewfnew_abs },
29117 { Hexagon::S4_pstorerhnewtnew_io, Hexagon::S4_pstorerhnewfnew_io },
29118 { Hexagon::S4_pstorerhnewtnew_rr, Hexagon::S4_pstorerhnewfnew_rr },
29119 { Hexagon::S4_pstorerht_abs, Hexagon::S4_pstorerhf_abs },
29120 { Hexagon::S4_pstorerht_rr, Hexagon::S4_pstorerhf_rr },
29121 { Hexagon::S4_pstorerhtnew_abs, Hexagon::S4_pstorerhfnew_abs },
29122 { Hexagon::S4_pstorerhtnew_io, Hexagon::S4_pstorerhfnew_io },
29123 { Hexagon::S4_pstorerhtnew_rr, Hexagon::S4_pstorerhfnew_rr },
29124 { Hexagon::S4_pstorerinewt_abs, Hexagon::S4_pstorerinewf_abs },
29125 { Hexagon::S4_pstorerinewt_rr, Hexagon::S4_pstorerinewf_rr },
29126 { Hexagon::S4_pstorerinewtnew_abs, Hexagon::S4_pstorerinewfnew_abs },
29127 { Hexagon::S4_pstorerinewtnew_io, Hexagon::S4_pstorerinewfnew_io },
29128 { Hexagon::S4_pstorerinewtnew_rr, Hexagon::S4_pstorerinewfnew_rr },
29129 { Hexagon::S4_pstorerit_abs, Hexagon::S4_pstorerif_abs },
29130 { Hexagon::S4_pstorerit_rr, Hexagon::S4_pstorerif_rr },
29131 { Hexagon::S4_pstoreritnew_abs, Hexagon::S4_pstorerifnew_abs },
29132 { Hexagon::S4_pstoreritnew_io, Hexagon::S4_pstorerifnew_io },
29133 { Hexagon::S4_pstoreritnew_rr, Hexagon::S4_pstorerifnew_rr },
29134 { Hexagon::S4_storeirbt_io, Hexagon::S4_storeirbf_io },
29135 { Hexagon::S4_storeirbtnew_io, Hexagon::S4_storeirbfnew_io },
29136 { Hexagon::S4_storeirht_io, Hexagon::S4_storeirhf_io },
29137 { Hexagon::S4_storeirhtnew_io, Hexagon::S4_storeirhfnew_io },
29138 { Hexagon::S4_storeirit_io, Hexagon::S4_storeirif_io },
29139 { Hexagon::S4_storeiritnew_io, Hexagon::S4_storeirifnew_io },
29140 { Hexagon::V6_vL32b_cur_pred_ai, Hexagon::V6_vL32b_cur_npred_ai },
29141 { Hexagon::V6_vL32b_cur_pred_pi, Hexagon::V6_vL32b_cur_npred_pi },
29142 { Hexagon::V6_vL32b_cur_pred_ppu, Hexagon::V6_vL32b_cur_npred_ppu },
29143 { Hexagon::V6_vL32b_nt_cur_pred_ai, Hexagon::V6_vL32b_nt_cur_npred_ai },
29144 { Hexagon::V6_vL32b_nt_cur_pred_pi, Hexagon::V6_vL32b_nt_cur_npred_pi },
29145 { Hexagon::V6_vL32b_nt_cur_pred_ppu, Hexagon::V6_vL32b_nt_cur_npred_ppu },
29146 { Hexagon::V6_vL32b_nt_pred_ai, Hexagon::V6_vL32b_nt_npred_ai },
29147 { Hexagon::V6_vL32b_nt_pred_pi, Hexagon::V6_vL32b_nt_npred_pi },
29148 { Hexagon::V6_vL32b_nt_pred_ppu, Hexagon::V6_vL32b_nt_npred_ppu },
29149 { Hexagon::V6_vL32b_nt_tmp_pred_ai, Hexagon::V6_vL32b_nt_tmp_npred_ai },
29150 { Hexagon::V6_vL32b_nt_tmp_pred_pi, Hexagon::V6_vL32b_nt_tmp_npred_pi },
29151 { Hexagon::V6_vL32b_nt_tmp_pred_ppu, Hexagon::V6_vL32b_nt_tmp_npred_ppu },
29152 { Hexagon::V6_vL32b_pred_ai, Hexagon::V6_vL32b_npred_ai },
29153 { Hexagon::V6_vL32b_pred_pi, Hexagon::V6_vL32b_npred_pi },
29154 { Hexagon::V6_vL32b_pred_ppu, Hexagon::V6_vL32b_npred_ppu },
29155 { Hexagon::V6_vL32b_tmp_pred_ai, Hexagon::V6_vL32b_tmp_npred_ai },
29156 { Hexagon::V6_vL32b_tmp_pred_pi, Hexagon::V6_vL32b_tmp_npred_pi },
29157 { Hexagon::V6_vL32b_tmp_pred_ppu, Hexagon::V6_vL32b_tmp_npred_ppu },
29158 { Hexagon::V6_vS32Ub_pred_ai, Hexagon::V6_vS32Ub_npred_ai },
29159 { Hexagon::V6_vS32Ub_pred_pi, Hexagon::V6_vS32Ub_npred_pi },
29160 { Hexagon::V6_vS32Ub_pred_ppu, Hexagon::V6_vS32Ub_npred_ppu },
29161 { Hexagon::V6_vS32b_new_pred_ai, Hexagon::V6_vS32b_new_npred_ai },
29162 { Hexagon::V6_vS32b_new_pred_pi, Hexagon::V6_vS32b_new_npred_pi },
29163 { Hexagon::V6_vS32b_new_pred_ppu, Hexagon::V6_vS32b_new_npred_ppu },
29164 { Hexagon::V6_vS32b_nt_new_pred_ai, Hexagon::V6_vS32b_nt_new_npred_ai },
29165 { Hexagon::V6_vS32b_nt_new_pred_pi, Hexagon::V6_vS32b_nt_new_npred_pi },
29166 { Hexagon::V6_vS32b_nt_new_pred_ppu, Hexagon::V6_vS32b_nt_new_npred_ppu },
29167 { Hexagon::V6_vS32b_nt_pred_ai, Hexagon::V6_vS32b_nt_npred_ai },
29168 { Hexagon::V6_vS32b_nt_pred_pi, Hexagon::V6_vS32b_nt_npred_pi },
29169 { Hexagon::V6_vS32b_nt_pred_ppu, Hexagon::V6_vS32b_nt_npred_ppu },
29170 { Hexagon::V6_vS32b_pred_ai, Hexagon::V6_vS32b_npred_ai },
29171 { Hexagon::V6_vS32b_pred_pi, Hexagon::V6_vS32b_npred_pi },
29172 { Hexagon::V6_vS32b_pred_ppu, Hexagon::V6_vS32b_npred_ppu },
29173}; // End of getFalsePredOpcodeTable
29174
29175 unsigned mid;
29176 unsigned start = 0;
29177 unsigned end = 250;
29178 while (start < end) {
29179 mid = start + (end - start) / 2;
29180 if (Opcode == getFalsePredOpcodeTable[mid][0]) {
29181 break;
29182 }
29183 if (Opcode < getFalsePredOpcodeTable[mid][0])
29184 end = mid;
29185 else
29186 start = mid + 1;
29187 }
29188 if (start == end)
29189 return -1; // Instruction doesn't exist in this table.
29190
29191 return getFalsePredOpcodeTable[mid][1];
29192}
29193
29194// getNewValueOpcode
29195LLVM_READONLY
29196int getNewValueOpcode(uint16_t Opcode) {
29197static const uint16_t getNewValueOpcodeTable[][2] = {
29198 { Hexagon::PS_storerbabs, Hexagon::PS_storerbnewabs },
29199 { Hexagon::PS_storerhabs, Hexagon::PS_storerhnewabs },
29200 { Hexagon::PS_storeriabs, Hexagon::PS_storerinewabs },
29201 { Hexagon::S2_pstorerbf_io, Hexagon::S2_pstorerbnewf_io },
29202 { Hexagon::S2_pstorerbf_pi, Hexagon::S2_pstorerbnewf_pi },
29203 { Hexagon::S2_pstorerbfnew_pi, Hexagon::S2_pstorerbnewfnew_pi },
29204 { Hexagon::S2_pstorerbt_io, Hexagon::S2_pstorerbnewt_io },
29205 { Hexagon::S2_pstorerbt_pi, Hexagon::S2_pstorerbnewt_pi },
29206 { Hexagon::S2_pstorerbtnew_pi, Hexagon::S2_pstorerbnewtnew_pi },
29207 { Hexagon::S2_pstorerhf_io, Hexagon::S2_pstorerhnewf_io },
29208 { Hexagon::S2_pstorerhf_pi, Hexagon::S2_pstorerhnewf_pi },
29209 { Hexagon::S2_pstorerhfnew_pi, Hexagon::S2_pstorerhnewfnew_pi },
29210 { Hexagon::S2_pstorerht_io, Hexagon::S2_pstorerhnewt_io },
29211 { Hexagon::S2_pstorerht_pi, Hexagon::S2_pstorerhnewt_pi },
29212 { Hexagon::S2_pstorerhtnew_pi, Hexagon::S2_pstorerhnewtnew_pi },
29213 { Hexagon::S2_pstorerif_io, Hexagon::S2_pstorerinewf_io },
29214 { Hexagon::S2_pstorerif_pi, Hexagon::S2_pstorerinewf_pi },
29215 { Hexagon::S2_pstorerifnew_pi, Hexagon::S2_pstorerinewfnew_pi },
29216 { Hexagon::S2_pstorerit_io, Hexagon::S2_pstorerinewt_io },
29217 { Hexagon::S2_pstorerit_pi, Hexagon::S2_pstorerinewt_pi },
29218 { Hexagon::S2_pstoreritnew_pi, Hexagon::S2_pstorerinewtnew_pi },
29219 { Hexagon::S2_storerb_io, Hexagon::S2_storerbnew_io },
29220 { Hexagon::S2_storerb_pbr, Hexagon::S2_storerbnew_pbr },
29221 { Hexagon::S2_storerb_pci, Hexagon::S2_storerbnew_pci },
29222 { Hexagon::S2_storerb_pcr, Hexagon::S2_storerbnew_pcr },
29223 { Hexagon::S2_storerb_pi, Hexagon::S2_storerbnew_pi },
29224 { Hexagon::S2_storerb_pr, Hexagon::S2_storerbnew_pr },
29225 { Hexagon::S2_storerbgp, Hexagon::S2_storerbnewgp },
29226 { Hexagon::S2_storerh_io, Hexagon::S2_storerhnew_io },
29227 { Hexagon::S2_storerh_pbr, Hexagon::S2_storerhnew_pbr },
29228 { Hexagon::S2_storerh_pci, Hexagon::S2_storerhnew_pci },
29229 { Hexagon::S2_storerh_pcr, Hexagon::S2_storerhnew_pcr },
29230 { Hexagon::S2_storerh_pi, Hexagon::S2_storerhnew_pi },
29231 { Hexagon::S2_storerh_pr, Hexagon::S2_storerhnew_pr },
29232 { Hexagon::S2_storerhgp, Hexagon::S2_storerhnewgp },
29233 { Hexagon::S2_storeri_io, Hexagon::S2_storerinew_io },
29234 { Hexagon::S2_storeri_pbr, Hexagon::S2_storerinew_pbr },
29235 { Hexagon::S2_storeri_pci, Hexagon::S2_storerinew_pci },
29236 { Hexagon::S2_storeri_pcr, Hexagon::S2_storerinew_pcr },
29237 { Hexagon::S2_storeri_pi, Hexagon::S2_storerinew_pi },
29238 { Hexagon::S2_storeri_pr, Hexagon::S2_storerinew_pr },
29239 { Hexagon::S2_storerigp, Hexagon::S2_storerinewgp },
29240 { Hexagon::S4_pstorerbf_abs, Hexagon::S4_pstorerbnewf_abs },
29241 { Hexagon::S4_pstorerbf_rr, Hexagon::S4_pstorerbnewf_rr },
29242 { Hexagon::S4_pstorerbfnew_abs, Hexagon::S4_pstorerbnewfnew_abs },
29243 { Hexagon::S4_pstorerbfnew_io, Hexagon::S4_pstorerbnewfnew_io },
29244 { Hexagon::S4_pstorerbfnew_rr, Hexagon::S4_pstorerbnewfnew_rr },
29245 { Hexagon::S4_pstorerbt_abs, Hexagon::S4_pstorerbnewt_abs },
29246 { Hexagon::S4_pstorerbt_rr, Hexagon::S4_pstorerbnewt_rr },
29247 { Hexagon::S4_pstorerbtnew_abs, Hexagon::S4_pstorerbnewtnew_abs },
29248 { Hexagon::S4_pstorerbtnew_io, Hexagon::S4_pstorerbnewtnew_io },
29249 { Hexagon::S4_pstorerbtnew_rr, Hexagon::S4_pstorerbnewtnew_rr },
29250 { Hexagon::S4_pstorerhf_abs, Hexagon::S4_pstorerhnewf_abs },
29251 { Hexagon::S4_pstorerhf_rr, Hexagon::S4_pstorerhnewf_rr },
29252 { Hexagon::S4_pstorerhfnew_abs, Hexagon::S4_pstorerhnewfnew_abs },
29253 { Hexagon::S4_pstorerhfnew_io, Hexagon::S4_pstorerhnewfnew_io },
29254 { Hexagon::S4_pstorerhfnew_rr, Hexagon::S4_pstorerhnewfnew_rr },
29255 { Hexagon::S4_pstorerht_abs, Hexagon::S4_pstorerhnewt_abs },
29256 { Hexagon::S4_pstorerht_rr, Hexagon::S4_pstorerhnewt_rr },
29257 { Hexagon::S4_pstorerhtnew_abs, Hexagon::S4_pstorerhnewtnew_abs },
29258 { Hexagon::S4_pstorerhtnew_io, Hexagon::S4_pstorerhnewtnew_io },
29259 { Hexagon::S4_pstorerhtnew_rr, Hexagon::S4_pstorerhnewtnew_rr },
29260 { Hexagon::S4_pstorerif_abs, Hexagon::S4_pstorerinewf_abs },
29261 { Hexagon::S4_pstorerif_rr, Hexagon::S4_pstorerinewf_rr },
29262 { Hexagon::S4_pstorerifnew_abs, Hexagon::S4_pstorerinewfnew_abs },
29263 { Hexagon::S4_pstorerifnew_io, Hexagon::S4_pstorerinewfnew_io },
29264 { Hexagon::S4_pstorerifnew_rr, Hexagon::S4_pstorerinewfnew_rr },
29265 { Hexagon::S4_pstorerit_abs, Hexagon::S4_pstorerinewt_abs },
29266 { Hexagon::S4_pstorerit_rr, Hexagon::S4_pstorerinewt_rr },
29267 { Hexagon::S4_pstoreritnew_abs, Hexagon::S4_pstorerinewtnew_abs },
29268 { Hexagon::S4_pstoreritnew_io, Hexagon::S4_pstorerinewtnew_io },
29269 { Hexagon::S4_pstoreritnew_rr, Hexagon::S4_pstorerinewtnew_rr },
29270 { Hexagon::S4_storerb_ap, Hexagon::S4_storerbnew_ap },
29271 { Hexagon::S4_storerb_rr, Hexagon::S4_storerbnew_rr },
29272 { Hexagon::S4_storerb_ur, Hexagon::S4_storerbnew_ur },
29273 { Hexagon::S4_storerh_ap, Hexagon::S4_storerhnew_ap },
29274 { Hexagon::S4_storerh_rr, Hexagon::S4_storerhnew_rr },
29275 { Hexagon::S4_storerh_ur, Hexagon::S4_storerhnew_ur },
29276 { Hexagon::S4_storeri_ap, Hexagon::S4_storerinew_ap },
29277 { Hexagon::S4_storeri_rr, Hexagon::S4_storerinew_rr },
29278 { Hexagon::S4_storeri_ur, Hexagon::S4_storerinew_ur },
29279 { Hexagon::V6_vS32b_ai, Hexagon::V6_vS32b_new_ai },
29280 { Hexagon::V6_vS32b_npred_ai, Hexagon::V6_vS32b_new_npred_ai },
29281 { Hexagon::V6_vS32b_npred_pi, Hexagon::V6_vS32b_new_npred_pi },
29282 { Hexagon::V6_vS32b_npred_ppu, Hexagon::V6_vS32b_new_npred_ppu },
29283 { Hexagon::V6_vS32b_nt_ai, Hexagon::V6_vS32b_nt_new_ai },
29284 { Hexagon::V6_vS32b_nt_npred_ai, Hexagon::V6_vS32b_nt_new_npred_ai },
29285 { Hexagon::V6_vS32b_nt_npred_pi, Hexagon::V6_vS32b_nt_new_npred_pi },
29286 { Hexagon::V6_vS32b_nt_npred_ppu, Hexagon::V6_vS32b_nt_new_npred_ppu },
29287 { Hexagon::V6_vS32b_nt_pi, Hexagon::V6_vS32b_nt_new_pi },
29288 { Hexagon::V6_vS32b_nt_ppu, Hexagon::V6_vS32b_nt_new_ppu },
29289 { Hexagon::V6_vS32b_nt_pred_ai, Hexagon::V6_vS32b_nt_new_pred_ai },
29290 { Hexagon::V6_vS32b_nt_pred_pi, Hexagon::V6_vS32b_nt_new_pred_pi },
29291 { Hexagon::V6_vS32b_nt_pred_ppu, Hexagon::V6_vS32b_nt_new_pred_ppu },
29292 { Hexagon::V6_vS32b_pi, Hexagon::V6_vS32b_new_pi },
29293 { Hexagon::V6_vS32b_ppu, Hexagon::V6_vS32b_new_ppu },
29294 { Hexagon::V6_vS32b_pred_ai, Hexagon::V6_vS32b_new_pred_ai },
29295 { Hexagon::V6_vS32b_pred_pi, Hexagon::V6_vS32b_new_pred_pi },
29296 { Hexagon::V6_vS32b_pred_ppu, Hexagon::V6_vS32b_new_pred_ppu },
29297}; // End of getNewValueOpcodeTable
29298
29299 unsigned mid;
29300 unsigned start = 0;
29301 unsigned end = 99;
29302 while (start < end) {
29303 mid = start + (end - start) / 2;
29304 if (Opcode == getNewValueOpcodeTable[mid][0]) {
29305 break;
29306 }
29307 if (Opcode < getNewValueOpcodeTable[mid][0])
29308 end = mid;
29309 else
29310 start = mid + 1;
29311 }
29312 if (start == end)
29313 return -1; // Instruction doesn't exist in this table.
29314
29315 return getNewValueOpcodeTable[mid][1];
29316}
29317
29318// getNonNVStore
29319LLVM_READONLY
29320int getNonNVStore(uint16_t Opcode) {
29321static const uint16_t getNonNVStoreTable[][2] = {
29322 { Hexagon::PS_storerbnewabs, Hexagon::PS_storerbabs },
29323 { Hexagon::PS_storerhnewabs, Hexagon::PS_storerhabs },
29324 { Hexagon::PS_storerinewabs, Hexagon::PS_storeriabs },
29325 { Hexagon::S2_pstorerbnewf_io, Hexagon::S2_pstorerbf_io },
29326 { Hexagon::S2_pstorerbnewf_pi, Hexagon::S2_pstorerbf_pi },
29327 { Hexagon::S2_pstorerbnewfnew_pi, Hexagon::S2_pstorerbfnew_pi },
29328 { Hexagon::S2_pstorerbnewt_io, Hexagon::S2_pstorerbt_io },
29329 { Hexagon::S2_pstorerbnewt_pi, Hexagon::S2_pstorerbt_pi },
29330 { Hexagon::S2_pstorerbnewtnew_pi, Hexagon::S2_pstorerbtnew_pi },
29331 { Hexagon::S2_pstorerhnewf_io, Hexagon::S2_pstorerhf_io },
29332 { Hexagon::S2_pstorerhnewf_pi, Hexagon::S2_pstorerhf_pi },
29333 { Hexagon::S2_pstorerhnewfnew_pi, Hexagon::S2_pstorerhfnew_pi },
29334 { Hexagon::S2_pstorerhnewt_io, Hexagon::S2_pstorerht_io },
29335 { Hexagon::S2_pstorerhnewt_pi, Hexagon::S2_pstorerht_pi },
29336 { Hexagon::S2_pstorerhnewtnew_pi, Hexagon::S2_pstorerhtnew_pi },
29337 { Hexagon::S2_pstorerinewf_io, Hexagon::S2_pstorerif_io },
29338 { Hexagon::S2_pstorerinewf_pi, Hexagon::S2_pstorerif_pi },
29339 { Hexagon::S2_pstorerinewfnew_pi, Hexagon::S2_pstorerifnew_pi },
29340 { Hexagon::S2_pstorerinewt_io, Hexagon::S2_pstorerit_io },
29341 { Hexagon::S2_pstorerinewt_pi, Hexagon::S2_pstorerit_pi },
29342 { Hexagon::S2_pstorerinewtnew_pi, Hexagon::S2_pstoreritnew_pi },
29343 { Hexagon::S2_storerbnew_io, Hexagon::S2_storerb_io },
29344 { Hexagon::S2_storerbnew_pbr, Hexagon::S2_storerb_pbr },
29345 { Hexagon::S2_storerbnew_pci, Hexagon::S2_storerb_pci },
29346 { Hexagon::S2_storerbnew_pcr, Hexagon::S2_storerb_pcr },
29347 { Hexagon::S2_storerbnew_pi, Hexagon::S2_storerb_pi },
29348 { Hexagon::S2_storerbnew_pr, Hexagon::S2_storerb_pr },
29349 { Hexagon::S2_storerbnewgp, Hexagon::S2_storerbgp },
29350 { Hexagon::S2_storerhnew_io, Hexagon::S2_storerh_io },
29351 { Hexagon::S2_storerhnew_pbr, Hexagon::S2_storerh_pbr },
29352 { Hexagon::S2_storerhnew_pci, Hexagon::S2_storerh_pci },
29353 { Hexagon::S2_storerhnew_pcr, Hexagon::S2_storerh_pcr },
29354 { Hexagon::S2_storerhnew_pi, Hexagon::S2_storerh_pi },
29355 { Hexagon::S2_storerhnew_pr, Hexagon::S2_storerh_pr },
29356 { Hexagon::S2_storerhnewgp, Hexagon::S2_storerhgp },
29357 { Hexagon::S2_storerinew_io, Hexagon::S2_storeri_io },
29358 { Hexagon::S2_storerinew_pbr, Hexagon::S2_storeri_pbr },
29359 { Hexagon::S2_storerinew_pci, Hexagon::S2_storeri_pci },
29360 { Hexagon::S2_storerinew_pcr, Hexagon::S2_storeri_pcr },
29361 { Hexagon::S2_storerinew_pi, Hexagon::S2_storeri_pi },
29362 { Hexagon::S2_storerinew_pr, Hexagon::S2_storeri_pr },
29363 { Hexagon::S2_storerinewgp, Hexagon::S2_storerigp },
29364 { Hexagon::S4_pstorerbnewf_abs, Hexagon::S4_pstorerbf_abs },
29365 { Hexagon::S4_pstorerbnewf_rr, Hexagon::S4_pstorerbf_rr },
29366 { Hexagon::S4_pstorerbnewfnew_abs, Hexagon::S4_pstorerbfnew_abs },
29367 { Hexagon::S4_pstorerbnewfnew_io, Hexagon::S4_pstorerbfnew_io },
29368 { Hexagon::S4_pstorerbnewfnew_rr, Hexagon::S4_pstorerbfnew_rr },
29369 { Hexagon::S4_pstorerbnewt_abs, Hexagon::S4_pstorerbt_abs },
29370 { Hexagon::S4_pstorerbnewt_rr, Hexagon::S4_pstorerbt_rr },
29371 { Hexagon::S4_pstorerbnewtnew_abs, Hexagon::S4_pstorerbtnew_abs },
29372 { Hexagon::S4_pstorerbnewtnew_io, Hexagon::S4_pstorerbtnew_io },
29373 { Hexagon::S4_pstorerbnewtnew_rr, Hexagon::S4_pstorerbtnew_rr },
29374 { Hexagon::S4_pstorerhnewf_abs, Hexagon::S4_pstorerhf_abs },
29375 { Hexagon::S4_pstorerhnewf_rr, Hexagon::S4_pstorerhf_rr },
29376 { Hexagon::S4_pstorerhnewfnew_abs, Hexagon::S4_pstorerhfnew_abs },
29377 { Hexagon::S4_pstorerhnewfnew_io, Hexagon::S4_pstorerhfnew_io },
29378 { Hexagon::S4_pstorerhnewfnew_rr, Hexagon::S4_pstorerhfnew_rr },
29379 { Hexagon::S4_pstorerhnewt_abs, Hexagon::S4_pstorerht_abs },
29380 { Hexagon::S4_pstorerhnewt_rr, Hexagon::S4_pstorerht_rr },
29381 { Hexagon::S4_pstorerhnewtnew_abs, Hexagon::S4_pstorerhtnew_abs },
29382 { Hexagon::S4_pstorerhnewtnew_io, Hexagon::S4_pstorerhtnew_io },
29383 { Hexagon::S4_pstorerhnewtnew_rr, Hexagon::S4_pstorerhtnew_rr },
29384 { Hexagon::S4_pstorerinewf_abs, Hexagon::S4_pstorerif_abs },
29385 { Hexagon::S4_pstorerinewf_rr, Hexagon::S4_pstorerif_rr },
29386 { Hexagon::S4_pstorerinewfnew_abs, Hexagon::S4_pstorerifnew_abs },
29387 { Hexagon::S4_pstorerinewfnew_io, Hexagon::S4_pstorerifnew_io },
29388 { Hexagon::S4_pstorerinewfnew_rr, Hexagon::S4_pstorerifnew_rr },
29389 { Hexagon::S4_pstorerinewt_abs, Hexagon::S4_pstorerit_abs },
29390 { Hexagon::S4_pstorerinewt_rr, Hexagon::S4_pstorerit_rr },
29391 { Hexagon::S4_pstorerinewtnew_abs, Hexagon::S4_pstoreritnew_abs },
29392 { Hexagon::S4_pstorerinewtnew_io, Hexagon::S4_pstoreritnew_io },
29393 { Hexagon::S4_pstorerinewtnew_rr, Hexagon::S4_pstoreritnew_rr },
29394 { Hexagon::S4_storerbnew_ap, Hexagon::S4_storerb_ap },
29395 { Hexagon::S4_storerbnew_rr, Hexagon::S4_storerb_rr },
29396 { Hexagon::S4_storerbnew_ur, Hexagon::S4_storerb_ur },
29397 { Hexagon::S4_storerhnew_ap, Hexagon::S4_storerh_ap },
29398 { Hexagon::S4_storerhnew_rr, Hexagon::S4_storerh_rr },
29399 { Hexagon::S4_storerhnew_ur, Hexagon::S4_storerh_ur },
29400 { Hexagon::S4_storerinew_ap, Hexagon::S4_storeri_ap },
29401 { Hexagon::S4_storerinew_rr, Hexagon::S4_storeri_rr },
29402 { Hexagon::S4_storerinew_ur, Hexagon::S4_storeri_ur },
29403 { Hexagon::V6_vS32b_new_ai, Hexagon::V6_vS32b_ai },
29404 { Hexagon::V6_vS32b_new_npred_ai, Hexagon::V6_vS32b_npred_ai },
29405 { Hexagon::V6_vS32b_new_npred_pi, Hexagon::V6_vS32b_npred_pi },
29406 { Hexagon::V6_vS32b_new_npred_ppu, Hexagon::V6_vS32b_npred_ppu },
29407 { Hexagon::V6_vS32b_new_pi, Hexagon::V6_vS32b_pi },
29408 { Hexagon::V6_vS32b_new_ppu, Hexagon::V6_vS32b_ppu },
29409 { Hexagon::V6_vS32b_new_pred_ai, Hexagon::V6_vS32b_pred_ai },
29410 { Hexagon::V6_vS32b_new_pred_pi, Hexagon::V6_vS32b_pred_pi },
29411 { Hexagon::V6_vS32b_new_pred_ppu, Hexagon::V6_vS32b_pred_ppu },
29412 { Hexagon::V6_vS32b_nt_new_ai, Hexagon::V6_vS32b_nt_ai },
29413 { Hexagon::V6_vS32b_nt_new_npred_ai, Hexagon::V6_vS32b_nt_npred_ai },
29414 { Hexagon::V6_vS32b_nt_new_npred_pi, Hexagon::V6_vS32b_nt_npred_pi },
29415 { Hexagon::V6_vS32b_nt_new_npred_ppu, Hexagon::V6_vS32b_nt_npred_ppu },
29416 { Hexagon::V6_vS32b_nt_new_pi, Hexagon::V6_vS32b_nt_pi },
29417 { Hexagon::V6_vS32b_nt_new_ppu, Hexagon::V6_vS32b_nt_ppu },
29418 { Hexagon::V6_vS32b_nt_new_pred_ai, Hexagon::V6_vS32b_nt_pred_ai },
29419 { Hexagon::V6_vS32b_nt_new_pred_pi, Hexagon::V6_vS32b_nt_pred_pi },
29420 { Hexagon::V6_vS32b_nt_new_pred_ppu, Hexagon::V6_vS32b_nt_pred_ppu },
29421}; // End of getNonNVStoreTable
29422
29423 unsigned mid;
29424 unsigned start = 0;
29425 unsigned end = 99;
29426 while (start < end) {
29427 mid = start + (end - start) / 2;
29428 if (Opcode == getNonNVStoreTable[mid][0]) {
29429 break;
29430 }
29431 if (Opcode < getNonNVStoreTable[mid][0])
29432 end = mid;
29433 else
29434 start = mid + 1;
29435 }
29436 if (start == end)
29437 return -1; // Instruction doesn't exist in this table.
29438
29439 return getNonNVStoreTable[mid][1];
29440}
29441
29442// getPredNewOpcode
29443LLVM_READONLY
29444int getPredNewOpcode(uint16_t Opcode) {
29445static const uint16_t getPredNewOpcodeTable[][2] = {
29446 { Hexagon::A2_tfrf, Hexagon::A2_tfrfnew },
29447 { Hexagon::A2_tfrpf, Hexagon::A2_tfrpfnew },
29448 { Hexagon::A2_tfrpt, Hexagon::A2_tfrptnew },
29449 { Hexagon::A2_tfrt, Hexagon::A2_tfrtnew },
29450 { Hexagon::A2_paddf, Hexagon::A2_paddfnew },
29451 { Hexagon::A2_paddif, Hexagon::A2_paddifnew },
29452 { Hexagon::A2_paddit, Hexagon::A2_padditnew },
29453 { Hexagon::A2_paddt, Hexagon::A2_paddtnew },
29454 { Hexagon::A2_pandf, Hexagon::A2_pandfnew },
29455 { Hexagon::A2_pandt, Hexagon::A2_pandtnew },
29456 { Hexagon::A2_porf, Hexagon::A2_porfnew },
29457 { Hexagon::A2_port, Hexagon::A2_portnew },
29458 { Hexagon::A2_psubf, Hexagon::A2_psubfnew },
29459 { Hexagon::A2_psubt, Hexagon::A2_psubtnew },
29460 { Hexagon::A2_pxorf, Hexagon::A2_pxorfnew },
29461 { Hexagon::A2_pxort, Hexagon::A2_pxortnew },
29462 { Hexagon::A4_paslhf, Hexagon::A4_paslhfnew },
29463 { Hexagon::A4_paslht, Hexagon::A4_paslhtnew },
29464 { Hexagon::A4_pasrhf, Hexagon::A4_pasrhfnew },
29465 { Hexagon::A4_pasrht, Hexagon::A4_pasrhtnew },
29466 { Hexagon::A4_psxtbf, Hexagon::A4_psxtbfnew },
29467 { Hexagon::A4_psxtbt, Hexagon::A4_psxtbtnew },
29468 { Hexagon::A4_psxthf, Hexagon::A4_psxthfnew },
29469 { Hexagon::A4_psxtht, Hexagon::A4_psxthtnew },
29470 { Hexagon::A4_pzxtbf, Hexagon::A4_pzxtbfnew },
29471 { Hexagon::A4_pzxtbt, Hexagon::A4_pzxtbtnew },
29472 { Hexagon::A4_pzxthf, Hexagon::A4_pzxthfnew },
29473 { Hexagon::A4_pzxtht, Hexagon::A4_pzxthtnew },
29474 { Hexagon::C2_ccombinewf, Hexagon::C2_ccombinewnewf },
29475 { Hexagon::C2_ccombinewt, Hexagon::C2_ccombinewnewt },
29476 { Hexagon::C2_cmoveif, Hexagon::C2_cmovenewif },
29477 { Hexagon::C2_cmoveit, Hexagon::C2_cmovenewit },
29478 { Hexagon::J2_jumpf, Hexagon::J2_jumpfnew },
29479 { Hexagon::J2_jumpfpt, Hexagon::J2_jumpfnewpt },
29480 { Hexagon::J2_jumprf, Hexagon::J2_jumprfnew },
29481 { Hexagon::J2_jumprfpt, Hexagon::J2_jumprfnewpt },
29482 { Hexagon::J2_jumprt, Hexagon::J2_jumprtnew },
29483 { Hexagon::J2_jumprtpt, Hexagon::J2_jumprtnewpt },
29484 { Hexagon::J2_jumpt, Hexagon::J2_jumptnew },
29485 { Hexagon::J2_jumptpt, Hexagon::J2_jumptnewpt },
29486 { Hexagon::L2_ploadrbf_io, Hexagon::L2_ploadrbfnew_io },
29487 { Hexagon::L2_ploadrbf_pi, Hexagon::L2_ploadrbfnew_pi },
29488 { Hexagon::L2_ploadrbt_io, Hexagon::L2_ploadrbtnew_io },
29489 { Hexagon::L2_ploadrbt_pi, Hexagon::L2_ploadrbtnew_pi },
29490 { Hexagon::L2_ploadrdf_io, Hexagon::L2_ploadrdfnew_io },
29491 { Hexagon::L2_ploadrdf_pi, Hexagon::L2_ploadrdfnew_pi },
29492 { Hexagon::L2_ploadrdt_io, Hexagon::L2_ploadrdtnew_io },
29493 { Hexagon::L2_ploadrdt_pi, Hexagon::L2_ploadrdtnew_pi },
29494 { Hexagon::L2_ploadrhf_io, Hexagon::L2_ploadrhfnew_io },
29495 { Hexagon::L2_ploadrhf_pi, Hexagon::L2_ploadrhfnew_pi },
29496 { Hexagon::L2_ploadrht_io, Hexagon::L2_ploadrhtnew_io },
29497 { Hexagon::L2_ploadrht_pi, Hexagon::L2_ploadrhtnew_pi },
29498 { Hexagon::L2_ploadrif_io, Hexagon::L2_ploadrifnew_io },
29499 { Hexagon::L2_ploadrif_pi, Hexagon::L2_ploadrifnew_pi },
29500 { Hexagon::L2_ploadrit_io, Hexagon::L2_ploadritnew_io },
29501 { Hexagon::L2_ploadrit_pi, Hexagon::L2_ploadritnew_pi },
29502 { Hexagon::L2_ploadrubf_io, Hexagon::L2_ploadrubfnew_io },
29503 { Hexagon::L2_ploadrubf_pi, Hexagon::L2_ploadrubfnew_pi },
29504 { Hexagon::L2_ploadrubt_io, Hexagon::L2_ploadrubtnew_io },
29505 { Hexagon::L2_ploadrubt_pi, Hexagon::L2_ploadrubtnew_pi },
29506 { Hexagon::L2_ploadruhf_io, Hexagon::L2_ploadruhfnew_io },
29507 { Hexagon::L2_ploadruhf_pi, Hexagon::L2_ploadruhfnew_pi },
29508 { Hexagon::L2_ploadruht_io, Hexagon::L2_ploadruhtnew_io },
29509 { Hexagon::L2_ploadruht_pi, Hexagon::L2_ploadruhtnew_pi },
29510 { Hexagon::L4_ploadrbf_abs, Hexagon::L4_ploadrbfnew_abs },
29511 { Hexagon::L4_ploadrbf_rr, Hexagon::L4_ploadrbfnew_rr },
29512 { Hexagon::L4_ploadrbt_abs, Hexagon::L4_ploadrbtnew_abs },
29513 { Hexagon::L4_ploadrbt_rr, Hexagon::L4_ploadrbtnew_rr },
29514 { Hexagon::L4_ploadrdf_abs, Hexagon::L4_ploadrdfnew_abs },
29515 { Hexagon::L4_ploadrdf_rr, Hexagon::L4_ploadrdfnew_rr },
29516 { Hexagon::L4_ploadrdt_abs, Hexagon::L4_ploadrdtnew_abs },
29517 { Hexagon::L4_ploadrdt_rr, Hexagon::L4_ploadrdtnew_rr },
29518 { Hexagon::L4_ploadrhf_abs, Hexagon::L4_ploadrhfnew_abs },
29519 { Hexagon::L4_ploadrhf_rr, Hexagon::L4_ploadrhfnew_rr },
29520 { Hexagon::L4_ploadrht_abs, Hexagon::L4_ploadrhtnew_abs },
29521 { Hexagon::L4_ploadrht_rr, Hexagon::L4_ploadrhtnew_rr },
29522 { Hexagon::L4_ploadrif_abs, Hexagon::L4_ploadrifnew_abs },
29523 { Hexagon::L4_ploadrif_rr, Hexagon::L4_ploadrifnew_rr },
29524 { Hexagon::L4_ploadrit_abs, Hexagon::L4_ploadritnew_abs },
29525 { Hexagon::L4_ploadrit_rr, Hexagon::L4_ploadritnew_rr },
29526 { Hexagon::L4_ploadrubf_abs, Hexagon::L4_ploadrubfnew_abs },
29527 { Hexagon::L4_ploadrubf_rr, Hexagon::L4_ploadrubfnew_rr },
29528 { Hexagon::L4_ploadrubt_abs, Hexagon::L4_ploadrubtnew_abs },
29529 { Hexagon::L4_ploadrubt_rr, Hexagon::L4_ploadrubtnew_rr },
29530 { Hexagon::L4_ploadruhf_abs, Hexagon::L4_ploadruhfnew_abs },
29531 { Hexagon::L4_ploadruhf_rr, Hexagon::L4_ploadruhfnew_rr },
29532 { Hexagon::L4_ploadruht_abs, Hexagon::L4_ploadruhtnew_abs },
29533 { Hexagon::L4_ploadruht_rr, Hexagon::L4_ploadruhtnew_rr },
29534 { Hexagon::L4_return_f, Hexagon::L4_return_fnew_pt },
29535 { Hexagon::L4_return_t, Hexagon::L4_return_tnew_pt },
29536 { Hexagon::PS_jmpretf, Hexagon::PS_jmpretfnew },
29537 { Hexagon::PS_jmprett, Hexagon::PS_jmprettnew },
29538 { Hexagon::S2_pstorerbf_io, Hexagon::S4_pstorerbfnew_io },
29539 { Hexagon::S2_pstorerbf_pi, Hexagon::S2_pstorerbfnew_pi },
29540 { Hexagon::S2_pstorerbnewf_io, Hexagon::S4_pstorerbnewfnew_io },
29541 { Hexagon::S2_pstorerbnewf_pi, Hexagon::S2_pstorerbnewfnew_pi },
29542 { Hexagon::S2_pstorerbnewt_io, Hexagon::S4_pstorerbnewtnew_io },
29543 { Hexagon::S2_pstorerbnewt_pi, Hexagon::S2_pstorerbnewtnew_pi },
29544 { Hexagon::S2_pstorerbt_io, Hexagon::S4_pstorerbtnew_io },
29545 { Hexagon::S2_pstorerbt_pi, Hexagon::S2_pstorerbtnew_pi },
29546 { Hexagon::S2_pstorerdf_io, Hexagon::S4_pstorerdfnew_io },
29547 { Hexagon::S2_pstorerdf_pi, Hexagon::S2_pstorerdfnew_pi },
29548 { Hexagon::S2_pstorerdt_io, Hexagon::S4_pstorerdtnew_io },
29549 { Hexagon::S2_pstorerdt_pi, Hexagon::S2_pstorerdtnew_pi },
29550 { Hexagon::S2_pstorerff_io, Hexagon::S4_pstorerffnew_io },
29551 { Hexagon::S2_pstorerff_pi, Hexagon::S2_pstorerffnew_pi },
29552 { Hexagon::S2_pstorerft_io, Hexagon::S4_pstorerftnew_io },
29553 { Hexagon::S2_pstorerft_pi, Hexagon::S2_pstorerftnew_pi },
29554 { Hexagon::S2_pstorerhf_io, Hexagon::S4_pstorerhfnew_io },
29555 { Hexagon::S2_pstorerhf_pi, Hexagon::S2_pstorerhfnew_pi },
29556 { Hexagon::S2_pstorerhnewf_io, Hexagon::S4_pstorerhnewfnew_io },
29557 { Hexagon::S2_pstorerhnewf_pi, Hexagon::S2_pstorerhnewfnew_pi },
29558 { Hexagon::S2_pstorerhnewt_io, Hexagon::S4_pstorerhnewtnew_io },
29559 { Hexagon::S2_pstorerhnewt_pi, Hexagon::S2_pstorerhnewtnew_pi },
29560 { Hexagon::S2_pstorerht_io, Hexagon::S4_pstorerhtnew_io },
29561 { Hexagon::S2_pstorerht_pi, Hexagon::S2_pstorerhtnew_pi },
29562 { Hexagon::S2_pstorerif_io, Hexagon::S4_pstorerifnew_io },
29563 { Hexagon::S2_pstorerif_pi, Hexagon::S2_pstorerifnew_pi },
29564 { Hexagon::S2_pstorerinewf_io, Hexagon::S4_pstorerinewfnew_io },
29565 { Hexagon::S2_pstorerinewf_pi, Hexagon::S2_pstorerinewfnew_pi },
29566 { Hexagon::S2_pstorerinewt_io, Hexagon::S4_pstorerinewtnew_io },
29567 { Hexagon::S2_pstorerinewt_pi, Hexagon::S2_pstorerinewtnew_pi },
29568 { Hexagon::S2_pstorerit_io, Hexagon::S4_pstoreritnew_io },
29569 { Hexagon::S2_pstorerit_pi, Hexagon::S2_pstoreritnew_pi },
29570 { Hexagon::S4_pstorerbf_abs, Hexagon::S4_pstorerbfnew_abs },
29571 { Hexagon::S4_pstorerbf_rr, Hexagon::S4_pstorerbfnew_rr },
29572 { Hexagon::S4_pstorerbnewf_abs, Hexagon::S4_pstorerbnewfnew_abs },
29573 { Hexagon::S4_pstorerbnewf_rr, Hexagon::S4_pstorerbnewfnew_rr },
29574 { Hexagon::S4_pstorerbnewt_abs, Hexagon::S4_pstorerbnewtnew_abs },
29575 { Hexagon::S4_pstorerbnewt_rr, Hexagon::S4_pstorerbnewtnew_rr },
29576 { Hexagon::S4_pstorerbt_abs, Hexagon::S4_pstorerbtnew_abs },
29577 { Hexagon::S4_pstorerbt_rr, Hexagon::S4_pstorerbtnew_rr },
29578 { Hexagon::S4_pstorerdf_abs, Hexagon::S4_pstorerdfnew_abs },
29579 { Hexagon::S4_pstorerdf_rr, Hexagon::S4_pstorerdfnew_rr },
29580 { Hexagon::S4_pstorerdt_abs, Hexagon::S4_pstorerdtnew_abs },
29581 { Hexagon::S4_pstorerdt_rr, Hexagon::S4_pstorerdtnew_rr },
29582 { Hexagon::S4_pstorerff_abs, Hexagon::S4_pstorerffnew_abs },
29583 { Hexagon::S4_pstorerff_rr, Hexagon::S4_pstorerffnew_rr },
29584 { Hexagon::S4_pstorerft_abs, Hexagon::S4_pstorerftnew_abs },
29585 { Hexagon::S4_pstorerft_rr, Hexagon::S4_pstorerftnew_rr },
29586 { Hexagon::S4_pstorerhf_abs, Hexagon::S4_pstorerhfnew_abs },
29587 { Hexagon::S4_pstorerhf_rr, Hexagon::S4_pstorerhfnew_rr },
29588 { Hexagon::S4_pstorerhnewf_abs, Hexagon::S4_pstorerhnewfnew_abs },
29589 { Hexagon::S4_pstorerhnewf_rr, Hexagon::S4_pstorerhnewfnew_rr },
29590 { Hexagon::S4_pstorerhnewt_abs, Hexagon::S4_pstorerhnewtnew_abs },
29591 { Hexagon::S4_pstorerhnewt_rr, Hexagon::S4_pstorerhnewtnew_rr },
29592 { Hexagon::S4_pstorerht_abs, Hexagon::S4_pstorerhtnew_abs },
29593 { Hexagon::S4_pstorerht_rr, Hexagon::S4_pstorerhtnew_rr },
29594 { Hexagon::S4_pstorerif_abs, Hexagon::S4_pstorerifnew_abs },
29595 { Hexagon::S4_pstorerif_rr, Hexagon::S4_pstorerifnew_rr },
29596 { Hexagon::S4_pstorerinewf_abs, Hexagon::S4_pstorerinewfnew_abs },
29597 { Hexagon::S4_pstorerinewf_rr, Hexagon::S4_pstorerinewfnew_rr },
29598 { Hexagon::S4_pstorerinewt_abs, Hexagon::S4_pstorerinewtnew_abs },
29599 { Hexagon::S4_pstorerinewt_rr, Hexagon::S4_pstorerinewtnew_rr },
29600 { Hexagon::S4_pstorerit_abs, Hexagon::S4_pstoreritnew_abs },
29601 { Hexagon::S4_pstorerit_rr, Hexagon::S4_pstoreritnew_rr },
29602 { Hexagon::S4_storeirbf_io, Hexagon::S4_storeirbfnew_io },
29603 { Hexagon::S4_storeirbt_io, Hexagon::S4_storeirbtnew_io },
29604 { Hexagon::S4_storeirhf_io, Hexagon::S4_storeirhfnew_io },
29605 { Hexagon::S4_storeirht_io, Hexagon::S4_storeirhtnew_io },
29606 { Hexagon::S4_storeirif_io, Hexagon::S4_storeirifnew_io },
29607 { Hexagon::S4_storeirit_io, Hexagon::S4_storeiritnew_io },
29608}; // End of getPredNewOpcodeTable
29609
29610 unsigned mid;
29611 unsigned start = 0;
29612 unsigned end = 162;
29613 while (start < end) {
29614 mid = start + (end - start) / 2;
29615 if (Opcode == getPredNewOpcodeTable[mid][0]) {
29616 break;
29617 }
29618 if (Opcode < getPredNewOpcodeTable[mid][0])
29619 end = mid;
29620 else
29621 start = mid + 1;
29622 }
29623 if (start == end)
29624 return -1; // Instruction doesn't exist in this table.
29625
29626 return getPredNewOpcodeTable[mid][1];
29627}
29628
29629// getPredOldOpcode
29630LLVM_READONLY
29631int getPredOldOpcode(uint16_t Opcode) {
29632static const uint16_t getPredOldOpcodeTable[][2] = {
29633 { Hexagon::A2_tfrfnew, Hexagon::A2_tfrf },
29634 { Hexagon::A2_tfrpfnew, Hexagon::A2_tfrpf },
29635 { Hexagon::A2_tfrptnew, Hexagon::A2_tfrpt },
29636 { Hexagon::A2_tfrtnew, Hexagon::A2_tfrt },
29637 { Hexagon::A2_paddfnew, Hexagon::A2_paddf },
29638 { Hexagon::A2_paddifnew, Hexagon::A2_paddif },
29639 { Hexagon::A2_padditnew, Hexagon::A2_paddit },
29640 { Hexagon::A2_paddtnew, Hexagon::A2_paddt },
29641 { Hexagon::A2_pandfnew, Hexagon::A2_pandf },
29642 { Hexagon::A2_pandtnew, Hexagon::A2_pandt },
29643 { Hexagon::A2_porfnew, Hexagon::A2_porf },
29644 { Hexagon::A2_portnew, Hexagon::A2_port },
29645 { Hexagon::A2_psubfnew, Hexagon::A2_psubf },
29646 { Hexagon::A2_psubtnew, Hexagon::A2_psubt },
29647 { Hexagon::A2_pxorfnew, Hexagon::A2_pxorf },
29648 { Hexagon::A2_pxortnew, Hexagon::A2_pxort },
29649 { Hexagon::A4_paslhfnew, Hexagon::A4_paslhf },
29650 { Hexagon::A4_paslhtnew, Hexagon::A4_paslht },
29651 { Hexagon::A4_pasrhfnew, Hexagon::A4_pasrhf },
29652 { Hexagon::A4_pasrhtnew, Hexagon::A4_pasrht },
29653 { Hexagon::A4_psxtbfnew, Hexagon::A4_psxtbf },
29654 { Hexagon::A4_psxtbtnew, Hexagon::A4_psxtbt },
29655 { Hexagon::A4_psxthfnew, Hexagon::A4_psxthf },
29656 { Hexagon::A4_psxthtnew, Hexagon::A4_psxtht },
29657 { Hexagon::A4_pzxtbfnew, Hexagon::A4_pzxtbf },
29658 { Hexagon::A4_pzxtbtnew, Hexagon::A4_pzxtbt },
29659 { Hexagon::A4_pzxthfnew, Hexagon::A4_pzxthf },
29660 { Hexagon::A4_pzxthtnew, Hexagon::A4_pzxtht },
29661 { Hexagon::C2_ccombinewnewf, Hexagon::C2_ccombinewf },
29662 { Hexagon::C2_ccombinewnewt, Hexagon::C2_ccombinewt },
29663 { Hexagon::C2_cmovenewif, Hexagon::C2_cmoveif },
29664 { Hexagon::C2_cmovenewit, Hexagon::C2_cmoveit },
29665 { Hexagon::J2_jumpfnew, Hexagon::J2_jumpf },
29666 { Hexagon::J2_jumpfnewpt, Hexagon::J2_jumpfpt },
29667 { Hexagon::J2_jumprfnew, Hexagon::J2_jumprf },
29668 { Hexagon::J2_jumprfnewpt, Hexagon::J2_jumprfpt },
29669 { Hexagon::J2_jumprtnew, Hexagon::J2_jumprt },
29670 { Hexagon::J2_jumprtnewpt, Hexagon::J2_jumprtpt },
29671 { Hexagon::J2_jumptnew, Hexagon::J2_jumpt },
29672 { Hexagon::J2_jumptnewpt, Hexagon::J2_jumptpt },
29673 { Hexagon::L2_ploadrbfnew_io, Hexagon::L2_ploadrbf_io },
29674 { Hexagon::L2_ploadrbfnew_pi, Hexagon::L2_ploadrbf_pi },
29675 { Hexagon::L2_ploadrbtnew_io, Hexagon::L2_ploadrbt_io },
29676 { Hexagon::L2_ploadrbtnew_pi, Hexagon::L2_ploadrbt_pi },
29677 { Hexagon::L2_ploadrdfnew_io, Hexagon::L2_ploadrdf_io },
29678 { Hexagon::L2_ploadrdfnew_pi, Hexagon::L2_ploadrdf_pi },
29679 { Hexagon::L2_ploadrdtnew_io, Hexagon::L2_ploadrdt_io },
29680 { Hexagon::L2_ploadrdtnew_pi, Hexagon::L2_ploadrdt_pi },
29681 { Hexagon::L2_ploadrhfnew_io, Hexagon::L2_ploadrhf_io },
29682 { Hexagon::L2_ploadrhfnew_pi, Hexagon::L2_ploadrhf_pi },
29683 { Hexagon::L2_ploadrhtnew_io, Hexagon::L2_ploadrht_io },
29684 { Hexagon::L2_ploadrhtnew_pi, Hexagon::L2_ploadrht_pi },
29685 { Hexagon::L2_ploadrifnew_io, Hexagon::L2_ploadrif_io },
29686 { Hexagon::L2_ploadrifnew_pi, Hexagon::L2_ploadrif_pi },
29687 { Hexagon::L2_ploadritnew_io, Hexagon::L2_ploadrit_io },
29688 { Hexagon::L2_ploadritnew_pi, Hexagon::L2_ploadrit_pi },
29689 { Hexagon::L2_ploadrubfnew_io, Hexagon::L2_ploadrubf_io },
29690 { Hexagon::L2_ploadrubfnew_pi, Hexagon::L2_ploadrubf_pi },
29691 { Hexagon::L2_ploadrubtnew_io, Hexagon::L2_ploadrubt_io },
29692 { Hexagon::L2_ploadrubtnew_pi, Hexagon::L2_ploadrubt_pi },
29693 { Hexagon::L2_ploadruhfnew_io, Hexagon::L2_ploadruhf_io },
29694 { Hexagon::L2_ploadruhfnew_pi, Hexagon::L2_ploadruhf_pi },
29695 { Hexagon::L2_ploadruhtnew_io, Hexagon::L2_ploadruht_io },
29696 { Hexagon::L2_ploadruhtnew_pi, Hexagon::L2_ploadruht_pi },
29697 { Hexagon::L4_ploadrbfnew_abs, Hexagon::L4_ploadrbf_abs },
29698 { Hexagon::L4_ploadrbfnew_rr, Hexagon::L4_ploadrbf_rr },
29699 { Hexagon::L4_ploadrbtnew_abs, Hexagon::L4_ploadrbt_abs },
29700 { Hexagon::L4_ploadrbtnew_rr, Hexagon::L4_ploadrbt_rr },
29701 { Hexagon::L4_ploadrdfnew_abs, Hexagon::L4_ploadrdf_abs },
29702 { Hexagon::L4_ploadrdfnew_rr, Hexagon::L4_ploadrdf_rr },
29703 { Hexagon::L4_ploadrdtnew_abs, Hexagon::L4_ploadrdt_abs },
29704 { Hexagon::L4_ploadrdtnew_rr, Hexagon::L4_ploadrdt_rr },
29705 { Hexagon::L4_ploadrhfnew_abs, Hexagon::L4_ploadrhf_abs },
29706 { Hexagon::L4_ploadrhfnew_rr, Hexagon::L4_ploadrhf_rr },
29707 { Hexagon::L4_ploadrhtnew_abs, Hexagon::L4_ploadrht_abs },
29708 { Hexagon::L4_ploadrhtnew_rr, Hexagon::L4_ploadrht_rr },
29709 { Hexagon::L4_ploadrifnew_abs, Hexagon::L4_ploadrif_abs },
29710 { Hexagon::L4_ploadrifnew_rr, Hexagon::L4_ploadrif_rr },
29711 { Hexagon::L4_ploadritnew_abs, Hexagon::L4_ploadrit_abs },
29712 { Hexagon::L4_ploadritnew_rr, Hexagon::L4_ploadrit_rr },
29713 { Hexagon::L4_ploadrubfnew_abs, Hexagon::L4_ploadrubf_abs },
29714 { Hexagon::L4_ploadrubfnew_rr, Hexagon::L4_ploadrubf_rr },
29715 { Hexagon::L4_ploadrubtnew_abs, Hexagon::L4_ploadrubt_abs },
29716 { Hexagon::L4_ploadrubtnew_rr, Hexagon::L4_ploadrubt_rr },
29717 { Hexagon::L4_ploadruhfnew_abs, Hexagon::L4_ploadruhf_abs },
29718 { Hexagon::L4_ploadruhfnew_rr, Hexagon::L4_ploadruhf_rr },
29719 { Hexagon::L4_ploadruhtnew_abs, Hexagon::L4_ploadruht_abs },
29720 { Hexagon::L4_ploadruhtnew_rr, Hexagon::L4_ploadruht_rr },
29721 { Hexagon::L4_return_fnew_pt, Hexagon::L4_return_f },
29722 { Hexagon::L4_return_tnew_pt, Hexagon::L4_return_t },
29723 { Hexagon::PS_jmpretfnew, Hexagon::PS_jmpretf },
29724 { Hexagon::PS_jmprettnew, Hexagon::PS_jmprett },
29725 { Hexagon::S2_pstorerbfnew_pi, Hexagon::S2_pstorerbf_pi },
29726 { Hexagon::S2_pstorerbnewfnew_pi, Hexagon::S2_pstorerbnewf_pi },
29727 { Hexagon::S2_pstorerbnewtnew_pi, Hexagon::S2_pstorerbnewt_pi },
29728 { Hexagon::S2_pstorerbtnew_pi, Hexagon::S2_pstorerbt_pi },
29729 { Hexagon::S2_pstorerdfnew_pi, Hexagon::S2_pstorerdf_pi },
29730 { Hexagon::S2_pstorerdtnew_pi, Hexagon::S2_pstorerdt_pi },
29731 { Hexagon::S2_pstorerffnew_pi, Hexagon::S2_pstorerff_pi },
29732 { Hexagon::S2_pstorerftnew_pi, Hexagon::S2_pstorerft_pi },
29733 { Hexagon::S2_pstorerhfnew_pi, Hexagon::S2_pstorerhf_pi },
29734 { Hexagon::S2_pstorerhnewfnew_pi, Hexagon::S2_pstorerhnewf_pi },
29735 { Hexagon::S2_pstorerhnewtnew_pi, Hexagon::S2_pstorerhnewt_pi },
29736 { Hexagon::S2_pstorerhtnew_pi, Hexagon::S2_pstorerht_pi },
29737 { Hexagon::S2_pstorerifnew_pi, Hexagon::S2_pstorerif_pi },
29738 { Hexagon::S2_pstorerinewfnew_pi, Hexagon::S2_pstorerinewf_pi },
29739 { Hexagon::S2_pstorerinewtnew_pi, Hexagon::S2_pstorerinewt_pi },
29740 { Hexagon::S2_pstoreritnew_pi, Hexagon::S2_pstorerit_pi },
29741 { Hexagon::S4_pstorerbfnew_abs, Hexagon::S4_pstorerbf_abs },
29742 { Hexagon::S4_pstorerbfnew_io, Hexagon::S2_pstorerbf_io },
29743 { Hexagon::S4_pstorerbfnew_rr, Hexagon::S4_pstorerbf_rr },
29744 { Hexagon::S4_pstorerbnewfnew_abs, Hexagon::S4_pstorerbnewf_abs },
29745 { Hexagon::S4_pstorerbnewfnew_io, Hexagon::S2_pstorerbnewf_io },
29746 { Hexagon::S4_pstorerbnewfnew_rr, Hexagon::S4_pstorerbnewf_rr },
29747 { Hexagon::S4_pstorerbnewtnew_abs, Hexagon::S4_pstorerbnewt_abs },
29748 { Hexagon::S4_pstorerbnewtnew_io, Hexagon::S2_pstorerbnewt_io },
29749 { Hexagon::S4_pstorerbnewtnew_rr, Hexagon::S4_pstorerbnewt_rr },
29750 { Hexagon::S4_pstorerbtnew_abs, Hexagon::S4_pstorerbt_abs },
29751 { Hexagon::S4_pstorerbtnew_io, Hexagon::S2_pstorerbt_io },
29752 { Hexagon::S4_pstorerbtnew_rr, Hexagon::S4_pstorerbt_rr },
29753 { Hexagon::S4_pstorerdfnew_abs, Hexagon::S4_pstorerdf_abs },
29754 { Hexagon::S4_pstorerdfnew_io, Hexagon::S2_pstorerdf_io },
29755 { Hexagon::S4_pstorerdfnew_rr, Hexagon::S4_pstorerdf_rr },
29756 { Hexagon::S4_pstorerdtnew_abs, Hexagon::S4_pstorerdt_abs },
29757 { Hexagon::S4_pstorerdtnew_io, Hexagon::S2_pstorerdt_io },
29758 { Hexagon::S4_pstorerdtnew_rr, Hexagon::S4_pstorerdt_rr },
29759 { Hexagon::S4_pstorerffnew_abs, Hexagon::S4_pstorerff_abs },
29760 { Hexagon::S4_pstorerffnew_io, Hexagon::S2_pstorerff_io },
29761 { Hexagon::S4_pstorerffnew_rr, Hexagon::S4_pstorerff_rr },
29762 { Hexagon::S4_pstorerftnew_abs, Hexagon::S4_pstorerft_abs },
29763 { Hexagon::S4_pstorerftnew_io, Hexagon::S2_pstorerft_io },
29764 { Hexagon::S4_pstorerftnew_rr, Hexagon::S4_pstorerft_rr },
29765 { Hexagon::S4_pstorerhfnew_abs, Hexagon::S4_pstorerhf_abs },
29766 { Hexagon::S4_pstorerhfnew_io, Hexagon::S2_pstorerhf_io },
29767 { Hexagon::S4_pstorerhfnew_rr, Hexagon::S4_pstorerhf_rr },
29768 { Hexagon::S4_pstorerhnewfnew_abs, Hexagon::S4_pstorerhnewf_abs },
29769 { Hexagon::S4_pstorerhnewfnew_io, Hexagon::S2_pstorerhnewf_io },
29770 { Hexagon::S4_pstorerhnewfnew_rr, Hexagon::S4_pstorerhnewf_rr },
29771 { Hexagon::S4_pstorerhnewtnew_abs, Hexagon::S4_pstorerhnewt_abs },
29772 { Hexagon::S4_pstorerhnewtnew_io, Hexagon::S2_pstorerhnewt_io },
29773 { Hexagon::S4_pstorerhnewtnew_rr, Hexagon::S4_pstorerhnewt_rr },
29774 { Hexagon::S4_pstorerhtnew_abs, Hexagon::S4_pstorerht_abs },
29775 { Hexagon::S4_pstorerhtnew_io, Hexagon::S2_pstorerht_io },
29776 { Hexagon::S4_pstorerhtnew_rr, Hexagon::S4_pstorerht_rr },
29777 { Hexagon::S4_pstorerifnew_abs, Hexagon::S4_pstorerif_abs },
29778 { Hexagon::S4_pstorerifnew_io, Hexagon::S2_pstorerif_io },
29779 { Hexagon::S4_pstorerifnew_rr, Hexagon::S4_pstorerif_rr },
29780 { Hexagon::S4_pstorerinewfnew_abs, Hexagon::S4_pstorerinewf_abs },
29781 { Hexagon::S4_pstorerinewfnew_io, Hexagon::S2_pstorerinewf_io },
29782 { Hexagon::S4_pstorerinewfnew_rr, Hexagon::S4_pstorerinewf_rr },
29783 { Hexagon::S4_pstorerinewtnew_abs, Hexagon::S4_pstorerinewt_abs },
29784 { Hexagon::S4_pstorerinewtnew_io, Hexagon::S2_pstorerinewt_io },
29785 { Hexagon::S4_pstorerinewtnew_rr, Hexagon::S4_pstorerinewt_rr },
29786 { Hexagon::S4_pstoreritnew_abs, Hexagon::S4_pstorerit_abs },
29787 { Hexagon::S4_pstoreritnew_io, Hexagon::S2_pstorerit_io },
29788 { Hexagon::S4_pstoreritnew_rr, Hexagon::S4_pstorerit_rr },
29789 { Hexagon::S4_storeirbfnew_io, Hexagon::S4_storeirbf_io },
29790 { Hexagon::S4_storeirbtnew_io, Hexagon::S4_storeirbt_io },
29791 { Hexagon::S4_storeirhfnew_io, Hexagon::S4_storeirhf_io },
29792 { Hexagon::S4_storeirhtnew_io, Hexagon::S4_storeirht_io },
29793 { Hexagon::S4_storeirifnew_io, Hexagon::S4_storeirif_io },
29794 { Hexagon::S4_storeiritnew_io, Hexagon::S4_storeirit_io },
29795}; // End of getPredOldOpcodeTable
29796
29797 unsigned mid;
29798 unsigned start = 0;
29799 unsigned end = 162;
29800 while (start < end) {
29801 mid = start + (end - start) / 2;
29802 if (Opcode == getPredOldOpcodeTable[mid][0]) {
29803 break;
29804 }
29805 if (Opcode < getPredOldOpcodeTable[mid][0])
29806 end = mid;
29807 else
29808 start = mid + 1;
29809 }
29810 if (start == end)
29811 return -1; // Instruction doesn't exist in this table.
29812
29813 return getPredOldOpcodeTable[mid][1];
29814}
29815
29816// getPredOpcode
29817LLVM_READONLY
29818int getPredOpcode(uint16_t Opcode, enum PredSense inPredSense) {
29819static const uint16_t getPredOpcodeTable[][3] = {
29820 { Hexagon::A2_tfrp, Hexagon::A2_tfrpt, Hexagon::A2_tfrpf },
29821 { Hexagon::A2_zxtb, Hexagon::A4_pzxtbt, Hexagon::A4_pzxtbf },
29822 { Hexagon::A2_add, Hexagon::A2_paddt, Hexagon::A2_paddf },
29823 { Hexagon::A2_addi, Hexagon::A2_paddit, Hexagon::A2_paddif },
29824 { Hexagon::A2_and, Hexagon::A2_pandt, Hexagon::A2_pandf },
29825 { Hexagon::A2_aslh, Hexagon::A4_paslht, Hexagon::A4_paslhf },
29826 { Hexagon::A2_asrh, Hexagon::A4_pasrht, Hexagon::A4_pasrhf },
29827 { Hexagon::A2_combinew, Hexagon::C2_ccombinewt, Hexagon::C2_ccombinewf },
29828 { Hexagon::A2_or, Hexagon::A2_port, Hexagon::A2_porf },
29829 { Hexagon::A2_sub, Hexagon::A2_psubt, Hexagon::A2_psubf },
29830 { Hexagon::A2_sxtb, Hexagon::A4_psxtbt, Hexagon::A4_psxtbf },
29831 { Hexagon::A2_sxth, Hexagon::A4_psxtht, Hexagon::A4_psxthf },
29832 { Hexagon::A2_tfr, Hexagon::A2_tfrt, Hexagon::A2_tfrf },
29833 { Hexagon::A2_tfrsi, Hexagon::C2_cmoveit, Hexagon::C2_cmoveif },
29834 { Hexagon::A2_xor, Hexagon::A2_pxort, Hexagon::A2_pxorf },
29835 { Hexagon::A2_zxth, Hexagon::A4_pzxtht, Hexagon::A4_pzxthf },
29836 { Hexagon::J2_call, Hexagon::J2_callt, Hexagon::J2_callf },
29837 { Hexagon::J2_jump, Hexagon::J2_jumpt, Hexagon::J2_jumpf },
29838 { Hexagon::J2_jumpr, Hexagon::J2_jumprt, Hexagon::J2_jumprf },
29839 { Hexagon::L2_loadrb_io, Hexagon::L2_ploadrbt_io, Hexagon::L2_ploadrbf_io },
29840 { Hexagon::L2_loadrb_pi, Hexagon::L2_ploadrbt_pi, Hexagon::L2_ploadrbf_pi },
29841 { Hexagon::L2_loadrbgp, Hexagon::L4_ploadrbt_abs, Hexagon::L4_ploadrbf_abs },
29842 { Hexagon::L2_loadrd_io, Hexagon::L2_ploadrdt_io, Hexagon::L2_ploadrdf_io },
29843 { Hexagon::L2_loadrd_pi, Hexagon::L2_ploadrdt_pi, Hexagon::L2_ploadrdf_pi },
29844 { Hexagon::L2_loadrdgp, Hexagon::L4_ploadrdt_abs, Hexagon::L4_ploadrdf_abs },
29845 { Hexagon::L2_loadrh_io, Hexagon::L2_ploadrht_io, Hexagon::L2_ploadrhf_io },
29846 { Hexagon::L2_loadrh_pi, Hexagon::L2_ploadrht_pi, Hexagon::L2_ploadrhf_pi },
29847 { Hexagon::L2_loadrhgp, Hexagon::L4_ploadrht_abs, Hexagon::L4_ploadrhf_abs },
29848 { Hexagon::L2_loadri_io, Hexagon::L2_ploadrit_io, Hexagon::L2_ploadrif_io },
29849 { Hexagon::L2_loadri_pi, Hexagon::L2_ploadrit_pi, Hexagon::L2_ploadrif_pi },
29850 { Hexagon::L2_loadrigp, Hexagon::L4_ploadrit_abs, Hexagon::L4_ploadrif_abs },
29851 { Hexagon::L2_loadrub_io, Hexagon::L2_ploadrubt_io, Hexagon::L2_ploadrubf_io },
29852 { Hexagon::L2_loadrub_pi, Hexagon::L2_ploadrubt_pi, Hexagon::L2_ploadrubf_pi },
29853 { Hexagon::L2_loadrubgp, Hexagon::L4_ploadrubt_abs, Hexagon::L4_ploadrubf_abs },
29854 { Hexagon::L2_loadruh_io, Hexagon::L2_ploadruht_io, Hexagon::L2_ploadruhf_io },
29855 { Hexagon::L2_loadruh_pi, Hexagon::L2_ploadruht_pi, Hexagon::L2_ploadruhf_pi },
29856 { Hexagon::L2_loadruhgp, Hexagon::L4_ploadruht_abs, Hexagon::L4_ploadruhf_abs },
29857 { Hexagon::L4_loadrb_rr, Hexagon::L4_ploadrbt_rr, Hexagon::L4_ploadrbf_rr },
29858 { Hexagon::L4_loadrd_rr, Hexagon::L4_ploadrdt_rr, Hexagon::L4_ploadrdf_rr },
29859 { Hexagon::L4_loadrh_rr, Hexagon::L4_ploadrht_rr, Hexagon::L4_ploadrhf_rr },
29860 { Hexagon::L4_loadri_rr, Hexagon::L4_ploadrit_rr, Hexagon::L4_ploadrif_rr },
29861 { Hexagon::L4_loadrub_rr, Hexagon::L4_ploadrubt_rr, Hexagon::L4_ploadrubf_rr },
29862 { Hexagon::L4_loadruh_rr, Hexagon::L4_ploadruht_rr, Hexagon::L4_ploadruhf_rr },
29863 { Hexagon::L4_return, Hexagon::L4_return_t, Hexagon::L4_return_f },
29864 { Hexagon::PS_jmpret, Hexagon::PS_jmprett, Hexagon::PS_jmpretf },
29865 { Hexagon::PS_loadrbabs, Hexagon::L4_ploadrbt_abs, Hexagon::L4_ploadrbf_abs },
29866 { Hexagon::PS_loadrdabs, Hexagon::L4_ploadrdt_abs, Hexagon::L4_ploadrdf_abs },
29867 { Hexagon::PS_loadrhabs, Hexagon::L4_ploadrht_abs, Hexagon::L4_ploadrhf_abs },
29868 { Hexagon::PS_loadriabs, Hexagon::L4_ploadrit_abs, Hexagon::L4_ploadrif_abs },
29869 { Hexagon::PS_loadrubabs, Hexagon::L4_ploadrubt_abs, Hexagon::L4_ploadrubf_abs },
29870 { Hexagon::PS_loadruhabs, Hexagon::L4_ploadruht_abs, Hexagon::L4_ploadruhf_abs },
29871 { Hexagon::PS_storerbabs, Hexagon::S4_pstorerbt_abs, Hexagon::S4_pstorerbf_abs },
29872 { Hexagon::PS_storerbnewabs, Hexagon::S4_pstorerbnewt_abs, Hexagon::S4_pstorerbnewf_abs },
29873 { Hexagon::PS_storerdabs, Hexagon::S4_pstorerdt_abs, Hexagon::S4_pstorerdf_abs },
29874 { Hexagon::PS_storerfabs, Hexagon::S4_pstorerft_abs, Hexagon::S4_pstorerff_abs },
29875 { Hexagon::PS_storerhabs, Hexagon::S4_pstorerht_abs, Hexagon::S4_pstorerhf_abs },
29876 { Hexagon::PS_storerhnewabs, Hexagon::S4_pstorerhnewt_abs, Hexagon::S4_pstorerhnewf_abs },
29877 { Hexagon::PS_storeriabs, Hexagon::S4_pstorerit_abs, Hexagon::S4_pstorerif_abs },
29878 { Hexagon::PS_storerinewabs, Hexagon::S4_pstorerinewt_abs, Hexagon::S4_pstorerinewf_abs },
29879 { Hexagon::S2_storerb_io, Hexagon::S2_pstorerbt_io, Hexagon::S2_pstorerbf_io },
29880 { Hexagon::S2_storerb_pi, Hexagon::S2_pstorerbt_pi, Hexagon::S2_pstorerbf_pi },
29881 { Hexagon::S2_storerbgp, Hexagon::S4_pstorerbt_abs, Hexagon::S4_pstorerbf_abs },
29882 { Hexagon::S2_storerbnew_io, Hexagon::S2_pstorerbnewt_io, Hexagon::S2_pstorerbnewf_io },
29883 { Hexagon::S2_storerbnew_pi, Hexagon::S2_pstorerbnewt_pi, Hexagon::S2_pstorerbnewf_pi },
29884 { Hexagon::S2_storerbnewgp, Hexagon::S4_pstorerbnewt_abs, Hexagon::S4_pstorerbnewf_abs },
29885 { Hexagon::S2_storerd_io, Hexagon::S2_pstorerdt_io, Hexagon::S2_pstorerdf_io },
29886 { Hexagon::S2_storerd_pi, Hexagon::S2_pstorerdt_pi, Hexagon::S2_pstorerdf_pi },
29887 { Hexagon::S2_storerdgp, Hexagon::S4_pstorerdt_abs, Hexagon::S4_pstorerdf_abs },
29888 { Hexagon::S2_storerf_io, Hexagon::S2_pstorerft_io, Hexagon::S2_pstorerff_io },
29889 { Hexagon::S2_storerf_pi, Hexagon::S2_pstorerft_pi, Hexagon::S2_pstorerff_pi },
29890 { Hexagon::S2_storerfgp, Hexagon::S4_pstorerft_abs, Hexagon::S4_pstorerff_abs },
29891 { Hexagon::S2_storerh_io, Hexagon::S2_pstorerht_io, Hexagon::S2_pstorerhf_io },
29892 { Hexagon::S2_storerh_pi, Hexagon::S2_pstorerht_pi, Hexagon::S2_pstorerhf_pi },
29893 { Hexagon::S2_storerhgp, Hexagon::S4_pstorerht_abs, Hexagon::S4_pstorerhf_abs },
29894 { Hexagon::S2_storerhnew_io, Hexagon::S2_pstorerhnewt_io, Hexagon::S2_pstorerhnewf_io },
29895 { Hexagon::S2_storerhnew_pi, Hexagon::S2_pstorerhnewt_pi, Hexagon::S2_pstorerhnewf_pi },
29896 { Hexagon::S2_storerhnewgp, Hexagon::S4_pstorerhnewt_abs, Hexagon::S4_pstorerhnewf_abs },
29897 { Hexagon::S2_storeri_io, Hexagon::S2_pstorerit_io, Hexagon::S2_pstorerif_io },
29898 { Hexagon::S2_storeri_pi, Hexagon::S2_pstorerit_pi, Hexagon::S2_pstorerif_pi },
29899 { Hexagon::S2_storerigp, Hexagon::S4_pstorerit_abs, Hexagon::S4_pstorerif_abs },
29900 { Hexagon::S2_storerinew_io, Hexagon::S2_pstorerinewt_io, Hexagon::S2_pstorerinewf_io },
29901 { Hexagon::S2_storerinew_pi, Hexagon::S2_pstorerinewt_pi, Hexagon::S2_pstorerinewf_pi },
29902 { Hexagon::S2_storerinewgp, Hexagon::S4_pstorerinewt_abs, Hexagon::S4_pstorerinewf_abs },
29903 { Hexagon::S4_storeirb_io, Hexagon::S4_storeirbt_io, Hexagon::S4_storeirbf_io },
29904 { Hexagon::S4_storeirh_io, Hexagon::S4_storeirht_io, Hexagon::S4_storeirhf_io },
29905 { Hexagon::S4_storeiri_io, Hexagon::S4_storeirit_io, Hexagon::S4_storeirif_io },
29906 { Hexagon::S4_storerb_rr, Hexagon::S4_pstorerbt_rr, Hexagon::S4_pstorerbf_rr },
29907 { Hexagon::S4_storerbnew_rr, Hexagon::S4_pstorerbnewt_rr, Hexagon::S4_pstorerbnewf_rr },
29908 { Hexagon::S4_storerd_rr, Hexagon::S4_pstorerdt_rr, Hexagon::S4_pstorerdf_rr },
29909 { Hexagon::S4_storerf_rr, Hexagon::S4_pstorerft_rr, Hexagon::S4_pstorerff_rr },
29910 { Hexagon::S4_storerf_ur, Hexagon::S4_pstorerft_rr, Hexagon::S4_pstorerff_rr },
29911 { Hexagon::S4_storerh_rr, Hexagon::S4_pstorerht_rr, Hexagon::S4_pstorerhf_rr },
29912 { Hexagon::S4_storerhnew_rr, Hexagon::S4_pstorerhnewt_rr, Hexagon::S4_pstorerhnewf_rr },
29913 { Hexagon::S4_storeri_rr, Hexagon::S4_pstorerit_rr, Hexagon::S4_pstorerif_rr },
29914 { Hexagon::S4_storerinew_rr, Hexagon::S4_pstorerinewt_rr, Hexagon::S4_pstorerinewf_rr },
29915 { Hexagon::V6_vL32b_ai, Hexagon::V6_vL32b_pred_ai, Hexagon::V6_vL32b_npred_ai },
29916 { Hexagon::V6_vL32b_cur_ai, Hexagon::V6_vL32b_cur_pred_ai, Hexagon::V6_vL32b_cur_npred_ai },
29917 { Hexagon::V6_vL32b_cur_pi, Hexagon::V6_vL32b_cur_pred_pi, Hexagon::V6_vL32b_cur_npred_pi },
29918 { Hexagon::V6_vL32b_cur_ppu, Hexagon::V6_vL32b_cur_pred_ppu, Hexagon::V6_vL32b_cur_npred_ppu },
29919 { Hexagon::V6_vL32b_nt_ai, Hexagon::V6_vL32b_nt_pred_ai, Hexagon::V6_vL32b_nt_npred_ai },
29920 { Hexagon::V6_vL32b_nt_cur_ai, Hexagon::V6_vL32b_nt_cur_pred_ai, Hexagon::V6_vL32b_nt_cur_npred_ai },
29921 { Hexagon::V6_vL32b_nt_cur_pi, Hexagon::V6_vL32b_nt_cur_pred_pi, Hexagon::V6_vL32b_nt_cur_npred_pi },
29922 { Hexagon::V6_vL32b_nt_cur_ppu, Hexagon::V6_vL32b_nt_cur_pred_ppu, Hexagon::V6_vL32b_nt_cur_npred_ppu },
29923 { Hexagon::V6_vL32b_nt_pi, Hexagon::V6_vL32b_nt_pred_pi, Hexagon::V6_vL32b_nt_npred_pi },
29924 { Hexagon::V6_vL32b_nt_ppu, Hexagon::V6_vL32b_nt_pred_ppu, Hexagon::V6_vL32b_nt_npred_ppu },
29925 { Hexagon::V6_vL32b_nt_tmp_ai, Hexagon::V6_vL32b_nt_tmp_pred_ai, Hexagon::V6_vL32b_nt_tmp_npred_ai },
29926 { Hexagon::V6_vL32b_nt_tmp_pi, Hexagon::V6_vL32b_nt_tmp_pred_pi, Hexagon::V6_vL32b_nt_tmp_npred_pi },
29927 { Hexagon::V6_vL32b_nt_tmp_ppu, Hexagon::V6_vL32b_nt_tmp_pred_ppu, Hexagon::V6_vL32b_nt_tmp_npred_ppu },
29928 { Hexagon::V6_vL32b_pi, Hexagon::V6_vL32b_pred_pi, Hexagon::V6_vL32b_npred_pi },
29929 { Hexagon::V6_vL32b_ppu, Hexagon::V6_vL32b_pred_ppu, Hexagon::V6_vL32b_npred_ppu },
29930 { Hexagon::V6_vL32b_tmp_ai, Hexagon::V6_vL32b_tmp_pred_ai, Hexagon::V6_vL32b_tmp_npred_ai },
29931 { Hexagon::V6_vL32b_tmp_pi, Hexagon::V6_vL32b_tmp_pred_pi, Hexagon::V6_vL32b_tmp_npred_pi },
29932 { Hexagon::V6_vL32b_tmp_ppu, Hexagon::V6_vL32b_tmp_pred_ppu, Hexagon::V6_vL32b_tmp_npred_ppu },
29933 { Hexagon::V6_vS32Ub_ai, Hexagon::V6_vS32Ub_pred_ai, Hexagon::V6_vS32Ub_npred_ai },
29934 { Hexagon::V6_vS32Ub_pi, Hexagon::V6_vS32Ub_pred_pi, Hexagon::V6_vS32Ub_npred_pi },
29935 { Hexagon::V6_vS32Ub_ppu, Hexagon::V6_vS32Ub_pred_ppu, Hexagon::V6_vS32Ub_npred_ppu },
29936 { Hexagon::V6_vS32b_ai, Hexagon::V6_vS32b_pred_ai, Hexagon::V6_vS32b_npred_ai },
29937 { Hexagon::V6_vS32b_new_ai, Hexagon::V6_vS32b_new_pred_ai, Hexagon::V6_vS32b_new_npred_ai },
29938 { Hexagon::V6_vS32b_new_pi, Hexagon::V6_vS32b_new_pred_pi, Hexagon::V6_vS32b_new_npred_pi },
29939 { Hexagon::V6_vS32b_new_ppu, Hexagon::V6_vS32b_new_pred_ppu, Hexagon::V6_vS32b_new_npred_ppu },
29940 { Hexagon::V6_vS32b_nt_ai, Hexagon::V6_vS32b_nt_pred_ai, Hexagon::V6_vS32b_nt_npred_ai },
29941 { Hexagon::V6_vS32b_nt_new_ai, Hexagon::V6_vS32b_nt_new_pred_ai, Hexagon::V6_vS32b_nt_new_npred_ai },
29942 { Hexagon::V6_vS32b_nt_new_pi, Hexagon::V6_vS32b_nt_new_pred_pi, Hexagon::V6_vS32b_nt_new_npred_pi },
29943 { Hexagon::V6_vS32b_nt_new_ppu, Hexagon::V6_vS32b_nt_new_pred_ppu, Hexagon::V6_vS32b_nt_new_npred_ppu },
29944 { Hexagon::V6_vS32b_nt_pi, Hexagon::V6_vS32b_nt_pred_pi, Hexagon::V6_vS32b_nt_npred_pi },
29945 { Hexagon::V6_vS32b_nt_ppu, Hexagon::V6_vS32b_nt_pred_ppu, Hexagon::V6_vS32b_nt_npred_ppu },
29946 { Hexagon::V6_vS32b_pi, Hexagon::V6_vS32b_pred_pi, Hexagon::V6_vS32b_npred_pi },
29947 { Hexagon::V6_vS32b_ppu, Hexagon::V6_vS32b_pred_ppu, Hexagon::V6_vS32b_npred_ppu },
29948}; // End of getPredOpcodeTable
29949
29950 unsigned mid;
29951 unsigned start = 0;
29952 unsigned end = 128;
29953 while (start < end) {
29954 mid = start + (end - start) / 2;
29955 if (Opcode == getPredOpcodeTable[mid][0]) {
29956 break;
29957 }
29958 if (Opcode < getPredOpcodeTable[mid][0])
29959 end = mid;
29960 else
29961 start = mid + 1;
29962 }
29963 if (start == end)
29964 return -1; // Instruction doesn't exist in this table.
29965
29966 if (inPredSense == PredSense_true)
29967 return getPredOpcodeTable[mid][1];
29968 if (inPredSense == PredSense_false)
29969 return getPredOpcodeTable[mid][2];
29970 return -1;}
29971
29972// getRealHWInstr
29973LLVM_READONLY
29974int getRealHWInstr(uint16_t Opcode, enum InstrType inInstrType) {
29975static const uint16_t getRealHWInstrTable[][3] = {
29976 { Hexagon::INSTRUCTION_LIST_END, Hexagon::INSTRUCTION_LIST_END }}; // End of getRealHWInstrTable
29977
29978 unsigned mid;
29979 unsigned start = 0;
29980 unsigned end = 0;
29981 while (start < end) {
29982 mid = start + (end - start) / 2;
29983 if (Opcode == getRealHWInstrTable[mid][0]) {
29984 break;
29985 }
29986 if (Opcode < getRealHWInstrTable[mid][0])
29987 end = mid;
29988 else
29989 start = mid + 1;
29990 }
29991 if (start == end)
29992 return -1; // Instruction doesn't exist in this table.
29993
29994 if (inInstrType == InstrType_Pseudo)
29995 return getRealHWInstrTable[mid][1];
29996 if (inInstrType == InstrType_Real)
29997 return getRealHWInstrTable[mid][2];
29998 return -1;}
29999
30000// getRegForm
30001LLVM_READONLY
30002int getRegForm(uint16_t Opcode) {
30003static const uint16_t getRegFormTable[][2] = {
30004 { Hexagon::M2_mpysmi, Hexagon::M2_mpyi },
30005 { Hexagon::A2_addi, Hexagon::A2_add },
30006 { Hexagon::A2_andir, Hexagon::A2_and },
30007 { Hexagon::A2_orir, Hexagon::A2_or },
30008 { Hexagon::A2_paddif, Hexagon::A2_paddf },
30009 { Hexagon::A2_paddifnew, Hexagon::A2_paddfnew },
30010 { Hexagon::A2_paddit, Hexagon::A2_paddt },
30011 { Hexagon::A2_padditnew, Hexagon::A2_paddtnew },
30012 { Hexagon::A2_subri, Hexagon::A2_sub },
30013 { Hexagon::A4_cmpbeqi, Hexagon::A4_cmpbeq },
30014 { Hexagon::A4_cmpbgti, Hexagon::A4_cmpbgt },
30015 { Hexagon::A4_cmpbgtui, Hexagon::A4_cmpbgtu },
30016 { Hexagon::A4_cmpheqi, Hexagon::A4_cmpheq },
30017 { Hexagon::A4_cmphgti, Hexagon::A4_cmphgt },
30018 { Hexagon::A4_cmphgtui, Hexagon::A4_cmphgtu },
30019 { Hexagon::C2_cmoveif, Hexagon::A2_tfrf },
30020 { Hexagon::C2_cmoveit, Hexagon::A2_tfrt },
30021 { Hexagon::C2_cmovenewif, Hexagon::A2_tfrfnew },
30022 { Hexagon::C2_cmovenewit, Hexagon::A2_tfrtnew },
30023 { Hexagon::C2_cmpeqi, Hexagon::C2_cmpeq },
30024 { Hexagon::C2_cmpgti, Hexagon::C2_cmpgt },
30025 { Hexagon::C2_cmpgtui, Hexagon::C2_cmpgtu },
30026 { Hexagon::C4_cmpltei, Hexagon::C4_cmplte },
30027 { Hexagon::C4_cmplteui, Hexagon::C4_cmplteu },
30028 { Hexagon::C4_cmpneqi, Hexagon::C4_cmpneq },
30029 { Hexagon::M2_accii, Hexagon::M2_acci },
30030 { Hexagon::M2_macsip, Hexagon::M2_maci },
30031 { Hexagon::M4_mpyrr_addi, Hexagon::M4_mpyrr_addr },
30032}; // End of getRegFormTable
30033
30034 unsigned mid;
30035 unsigned start = 0;
30036 unsigned end = 28;
30037 while (start < end) {
30038 mid = start + (end - start) / 2;
30039 if (Opcode == getRegFormTable[mid][0]) {
30040 break;
30041 }
30042 if (Opcode < getRegFormTable[mid][0])
30043 end = mid;
30044 else
30045 start = mid + 1;
30046 }
30047 if (start == end)
30048 return -1; // Instruction doesn't exist in this table.
30049
30050 return getRegFormTable[mid][1];
30051}
30052
30053// getTruePredOpcode
30054LLVM_READONLY
30055int getTruePredOpcode(uint16_t Opcode) {
30056static const uint16_t getTruePredOpcodeTable[][2] = {
30057 { Hexagon::A2_tfrf, Hexagon::A2_tfrt },
30058 { Hexagon::A2_tfrfnew, Hexagon::A2_tfrtnew },
30059 { Hexagon::A2_tfrpf, Hexagon::A2_tfrpt },
30060 { Hexagon::A2_tfrpfnew, Hexagon::A2_tfrptnew },
30061 { Hexagon::A2_paddf, Hexagon::A2_paddt },
30062 { Hexagon::A2_paddfnew, Hexagon::A2_paddtnew },
30063 { Hexagon::A2_paddif, Hexagon::A2_paddit },
30064 { Hexagon::A2_paddifnew, Hexagon::A2_padditnew },
30065 { Hexagon::A2_pandf, Hexagon::A2_pandt },
30066 { Hexagon::A2_pandfnew, Hexagon::A2_pandtnew },
30067 { Hexagon::A2_porf, Hexagon::A2_port },
30068 { Hexagon::A2_porfnew, Hexagon::A2_portnew },
30069 { Hexagon::A2_psubf, Hexagon::A2_psubt },
30070 { Hexagon::A2_psubfnew, Hexagon::A2_psubtnew },
30071 { Hexagon::A2_pxorf, Hexagon::A2_pxort },
30072 { Hexagon::A2_pxorfnew, Hexagon::A2_pxortnew },
30073 { Hexagon::A4_paslhf, Hexagon::A4_paslht },
30074 { Hexagon::A4_paslhfnew, Hexagon::A4_paslhtnew },
30075 { Hexagon::A4_pasrhf, Hexagon::A4_pasrht },
30076 { Hexagon::A4_pasrhfnew, Hexagon::A4_pasrhtnew },
30077 { Hexagon::A4_psxtbf, Hexagon::A4_psxtbt },
30078 { Hexagon::A4_psxtbfnew, Hexagon::A4_psxtbtnew },
30079 { Hexagon::A4_psxthf, Hexagon::A4_psxtht },
30080 { Hexagon::A4_psxthfnew, Hexagon::A4_psxthtnew },
30081 { Hexagon::A4_pzxtbf, Hexagon::A4_pzxtbt },
30082 { Hexagon::A4_pzxtbfnew, Hexagon::A4_pzxtbtnew },
30083 { Hexagon::A4_pzxthf, Hexagon::A4_pzxtht },
30084 { Hexagon::A4_pzxthfnew, Hexagon::A4_pzxthtnew },
30085 { Hexagon::C2_ccombinewf, Hexagon::C2_ccombinewt },
30086 { Hexagon::C2_ccombinewnewf, Hexagon::C2_ccombinewnewt },
30087 { Hexagon::C2_cmoveif, Hexagon::C2_cmoveit },
30088 { Hexagon::C2_cmovenewif, Hexagon::C2_cmovenewit },
30089 { Hexagon::J2_callf, Hexagon::J2_callt },
30090 { Hexagon::J2_jumpf, Hexagon::J2_jumpt },
30091 { Hexagon::J2_jumpfnew, Hexagon::J2_jumptnew },
30092 { Hexagon::J2_jumpfnewpt, Hexagon::J2_jumptnewpt },
30093 { Hexagon::J2_jumpfpt, Hexagon::J2_jumptpt },
30094 { Hexagon::J2_jumprf, Hexagon::J2_jumprt },
30095 { Hexagon::J2_jumprfnew, Hexagon::J2_jumprtnew },
30096 { Hexagon::J2_jumprfnewpt, Hexagon::J2_jumprtnewpt },
30097 { Hexagon::J2_jumprfpt, Hexagon::J2_jumprtpt },
30098 { Hexagon::J4_cmpeq_f_jumpnv_nt, Hexagon::J4_cmpeq_t_jumpnv_nt },
30099 { Hexagon::J4_cmpeq_f_jumpnv_t, Hexagon::J4_cmpeq_t_jumpnv_t },
30100 { Hexagon::J4_cmpeq_fp0_jump_nt, Hexagon::J4_cmpeq_tp0_jump_nt },
30101 { Hexagon::J4_cmpeq_fp0_jump_t, Hexagon::J4_cmpeq_tp0_jump_t },
30102 { Hexagon::J4_cmpeq_fp1_jump_nt, Hexagon::J4_cmpeq_tp1_jump_nt },
30103 { Hexagon::J4_cmpeq_fp1_jump_t, Hexagon::J4_cmpeq_tp1_jump_t },
30104 { Hexagon::J4_cmpeqi_f_jumpnv_nt, Hexagon::J4_cmpeqi_t_jumpnv_nt },
30105 { Hexagon::J4_cmpeqi_f_jumpnv_t, Hexagon::J4_cmpeqi_t_jumpnv_t },
30106 { Hexagon::J4_cmpeqi_fp0_jump_nt, Hexagon::J4_cmpeqi_tp0_jump_nt },
30107 { Hexagon::J4_cmpeqi_fp0_jump_t, Hexagon::J4_cmpeqi_tp0_jump_t },
30108 { Hexagon::J4_cmpeqi_fp1_jump_nt, Hexagon::J4_cmpeqi_tp1_jump_nt },
30109 { Hexagon::J4_cmpeqi_fp1_jump_t, Hexagon::J4_cmpeqi_tp1_jump_t },
30110 { Hexagon::J4_cmpeqn1_f_jumpnv_nt, Hexagon::J4_cmpeqn1_t_jumpnv_nt },
30111 { Hexagon::J4_cmpeqn1_f_jumpnv_t, Hexagon::J4_cmpeqn1_t_jumpnv_t },
30112 { Hexagon::J4_cmpeqn1_fp0_jump_nt, Hexagon::J4_cmpeqn1_tp0_jump_nt },
30113 { Hexagon::J4_cmpeqn1_fp0_jump_t, Hexagon::J4_cmpeqn1_tp0_jump_t },
30114 { Hexagon::J4_cmpeqn1_fp1_jump_nt, Hexagon::J4_cmpeqn1_tp1_jump_nt },
30115 { Hexagon::J4_cmpeqn1_fp1_jump_t, Hexagon::J4_cmpeqn1_tp1_jump_t },
30116 { Hexagon::J4_cmpgt_f_jumpnv_nt, Hexagon::J4_cmpgt_t_jumpnv_nt },
30117 { Hexagon::J4_cmpgt_f_jumpnv_t, Hexagon::J4_cmpgt_t_jumpnv_t },
30118 { Hexagon::J4_cmpgt_fp0_jump_nt, Hexagon::J4_cmpgt_tp0_jump_nt },
30119 { Hexagon::J4_cmpgt_fp0_jump_t, Hexagon::J4_cmpgt_tp0_jump_t },
30120 { Hexagon::J4_cmpgt_fp1_jump_nt, Hexagon::J4_cmpgt_tp1_jump_nt },
30121 { Hexagon::J4_cmpgt_fp1_jump_t, Hexagon::J4_cmpgt_tp1_jump_t },
30122 { Hexagon::J4_cmpgti_f_jumpnv_nt, Hexagon::J4_cmpgti_t_jumpnv_nt },
30123 { Hexagon::J4_cmpgti_f_jumpnv_t, Hexagon::J4_cmpgti_t_jumpnv_t },
30124 { Hexagon::J4_cmpgti_fp0_jump_nt, Hexagon::J4_cmpgti_tp0_jump_nt },
30125 { Hexagon::J4_cmpgti_fp0_jump_t, Hexagon::J4_cmpgti_tp0_jump_t },
30126 { Hexagon::J4_cmpgti_fp1_jump_nt, Hexagon::J4_cmpgti_tp1_jump_nt },
30127 { Hexagon::J4_cmpgti_fp1_jump_t, Hexagon::J4_cmpgti_tp1_jump_t },
30128 { Hexagon::J4_cmpgtn1_f_jumpnv_nt, Hexagon::J4_cmpgtn1_t_jumpnv_nt },
30129 { Hexagon::J4_cmpgtn1_f_jumpnv_t, Hexagon::J4_cmpgtn1_t_jumpnv_t },
30130 { Hexagon::J4_cmpgtn1_fp0_jump_nt, Hexagon::J4_cmpgtn1_tp0_jump_nt },
30131 { Hexagon::J4_cmpgtn1_fp0_jump_t, Hexagon::J4_cmpgtn1_tp0_jump_t },
30132 { Hexagon::J4_cmpgtn1_fp1_jump_nt, Hexagon::J4_cmpgtn1_tp1_jump_nt },
30133 { Hexagon::J4_cmpgtn1_fp1_jump_t, Hexagon::J4_cmpgtn1_tp1_jump_t },
30134 { Hexagon::J4_cmpgtu_f_jumpnv_nt, Hexagon::J4_cmpgtu_t_jumpnv_nt },
30135 { Hexagon::J4_cmpgtu_f_jumpnv_t, Hexagon::J4_cmpgtu_t_jumpnv_t },
30136 { Hexagon::J4_cmpgtu_fp0_jump_nt, Hexagon::J4_cmpgtu_tp0_jump_nt },
30137 { Hexagon::J4_cmpgtu_fp0_jump_t, Hexagon::J4_cmpgtu_tp0_jump_t },
30138 { Hexagon::J4_cmpgtu_fp1_jump_nt, Hexagon::J4_cmpgtu_tp1_jump_nt },
30139 { Hexagon::J4_cmpgtu_fp1_jump_t, Hexagon::J4_cmpgtu_tp1_jump_t },
30140 { Hexagon::J4_cmpgtui_f_jumpnv_nt, Hexagon::J4_cmpgtui_t_jumpnv_nt },
30141 { Hexagon::J4_cmpgtui_f_jumpnv_t, Hexagon::J4_cmpgtui_t_jumpnv_t },
30142 { Hexagon::J4_cmpgtui_fp0_jump_nt, Hexagon::J4_cmpgtui_tp0_jump_nt },
30143 { Hexagon::J4_cmpgtui_fp0_jump_t, Hexagon::J4_cmpgtui_tp0_jump_t },
30144 { Hexagon::J4_cmpgtui_fp1_jump_nt, Hexagon::J4_cmpgtui_tp1_jump_nt },
30145 { Hexagon::J4_cmpgtui_fp1_jump_t, Hexagon::J4_cmpgtui_tp1_jump_t },
30146 { Hexagon::J4_cmplt_f_jumpnv_nt, Hexagon::J4_cmplt_t_jumpnv_nt },
30147 { Hexagon::J4_cmplt_f_jumpnv_t, Hexagon::J4_cmplt_t_jumpnv_t },
30148 { Hexagon::J4_cmpltu_f_jumpnv_nt, Hexagon::J4_cmpltu_t_jumpnv_nt },
30149 { Hexagon::J4_cmpltu_f_jumpnv_t, Hexagon::J4_cmpltu_t_jumpnv_t },
30150 { Hexagon::L2_ploadrbf_io, Hexagon::L2_ploadrbt_io },
30151 { Hexagon::L2_ploadrbf_pi, Hexagon::L2_ploadrbt_pi },
30152 { Hexagon::L2_ploadrbfnew_io, Hexagon::L2_ploadrbtnew_io },
30153 { Hexagon::L2_ploadrbfnew_pi, Hexagon::L2_ploadrbtnew_pi },
30154 { Hexagon::L2_ploadrdf_io, Hexagon::L2_ploadrdt_io },
30155 { Hexagon::L2_ploadrdf_pi, Hexagon::L2_ploadrdt_pi },
30156 { Hexagon::L2_ploadrdfnew_io, Hexagon::L2_ploadrdtnew_io },
30157 { Hexagon::L2_ploadrdfnew_pi, Hexagon::L2_ploadrdtnew_pi },
30158 { Hexagon::L2_ploadrhf_io, Hexagon::L2_ploadrht_io },
30159 { Hexagon::L2_ploadrhf_pi, Hexagon::L2_ploadrht_pi },
30160 { Hexagon::L2_ploadrhfnew_io, Hexagon::L2_ploadrhtnew_io },
30161 { Hexagon::L2_ploadrhfnew_pi, Hexagon::L2_ploadrhtnew_pi },
30162 { Hexagon::L2_ploadrif_io, Hexagon::L2_ploadrit_io },
30163 { Hexagon::L2_ploadrif_pi, Hexagon::L2_ploadrit_pi },
30164 { Hexagon::L2_ploadrifnew_io, Hexagon::L2_ploadritnew_io },
30165 { Hexagon::L2_ploadrifnew_pi, Hexagon::L2_ploadritnew_pi },
30166 { Hexagon::L2_ploadrubf_io, Hexagon::L2_ploadrubt_io },
30167 { Hexagon::L2_ploadrubf_pi, Hexagon::L2_ploadrubt_pi },
30168 { Hexagon::L2_ploadrubfnew_io, Hexagon::L2_ploadrubtnew_io },
30169 { Hexagon::L2_ploadrubfnew_pi, Hexagon::L2_ploadrubtnew_pi },
30170 { Hexagon::L2_ploadruhf_io, Hexagon::L2_ploadruht_io },
30171 { Hexagon::L2_ploadruhf_pi, Hexagon::L2_ploadruht_pi },
30172 { Hexagon::L2_ploadruhfnew_io, Hexagon::L2_ploadruhtnew_io },
30173 { Hexagon::L2_ploadruhfnew_pi, Hexagon::L2_ploadruhtnew_pi },
30174 { Hexagon::L4_ploadrbf_abs, Hexagon::L4_ploadrbt_abs },
30175 { Hexagon::L4_ploadrbf_rr, Hexagon::L4_ploadrbt_rr },
30176 { Hexagon::L4_ploadrbfnew_abs, Hexagon::L4_ploadrbtnew_abs },
30177 { Hexagon::L4_ploadrbfnew_rr, Hexagon::L4_ploadrbtnew_rr },
30178 { Hexagon::L4_ploadrdf_abs, Hexagon::L4_ploadrdt_abs },
30179 { Hexagon::L4_ploadrdf_rr, Hexagon::L4_ploadrdt_rr },
30180 { Hexagon::L4_ploadrdfnew_abs, Hexagon::L4_ploadrdtnew_abs },
30181 { Hexagon::L4_ploadrdfnew_rr, Hexagon::L4_ploadrdtnew_rr },
30182 { Hexagon::L4_ploadrhf_abs, Hexagon::L4_ploadrht_abs },
30183 { Hexagon::L4_ploadrhf_rr, Hexagon::L4_ploadrht_rr },
30184 { Hexagon::L4_ploadrhfnew_abs, Hexagon::L4_ploadrhtnew_abs },
30185 { Hexagon::L4_ploadrhfnew_rr, Hexagon::L4_ploadrhtnew_rr },
30186 { Hexagon::L4_ploadrif_abs, Hexagon::L4_ploadrit_abs },
30187 { Hexagon::L4_ploadrif_rr, Hexagon::L4_ploadrit_rr },
30188 { Hexagon::L4_ploadrifnew_abs, Hexagon::L4_ploadritnew_abs },
30189 { Hexagon::L4_ploadrifnew_rr, Hexagon::L4_ploadritnew_rr },
30190 { Hexagon::L4_ploadrubf_abs, Hexagon::L4_ploadrubt_abs },
30191 { Hexagon::L4_ploadrubf_rr, Hexagon::L4_ploadrubt_rr },
30192 { Hexagon::L4_ploadrubfnew_abs, Hexagon::L4_ploadrubtnew_abs },
30193 { Hexagon::L4_ploadrubfnew_rr, Hexagon::L4_ploadrubtnew_rr },
30194 { Hexagon::L4_ploadruhf_abs, Hexagon::L4_ploadruht_abs },
30195 { Hexagon::L4_ploadruhf_rr, Hexagon::L4_ploadruht_rr },
30196 { Hexagon::L4_ploadruhfnew_abs, Hexagon::L4_ploadruhtnew_abs },
30197 { Hexagon::L4_ploadruhfnew_rr, Hexagon::L4_ploadruhtnew_rr },
30198 { Hexagon::L4_return_f, Hexagon::L4_return_t },
30199 { Hexagon::L4_return_fnew_pnt, Hexagon::L4_return_tnew_pnt },
30200 { Hexagon::L4_return_fnew_pt, Hexagon::L4_return_tnew_pt },
30201 { Hexagon::PS_jmpretf, Hexagon::PS_jmprett },
30202 { Hexagon::PS_jmpretfnew, Hexagon::PS_jmprettnew },
30203 { Hexagon::PS_jmpretfnewpt, Hexagon::PS_jmprettnewpt },
30204 { Hexagon::S2_pstorerbf_io, Hexagon::S2_pstorerbt_io },
30205 { Hexagon::S2_pstorerbf_pi, Hexagon::S2_pstorerbt_pi },
30206 { Hexagon::S2_pstorerbfnew_pi, Hexagon::S2_pstorerbtnew_pi },
30207 { Hexagon::S2_pstorerbnewf_io, Hexagon::S2_pstorerbnewt_io },
30208 { Hexagon::S2_pstorerbnewf_pi, Hexagon::S2_pstorerbnewt_pi },
30209 { Hexagon::S2_pstorerbnewfnew_pi, Hexagon::S2_pstorerbnewtnew_pi },
30210 { Hexagon::S2_pstorerdf_io, Hexagon::S2_pstorerdt_io },
30211 { Hexagon::S2_pstorerdf_pi, Hexagon::S2_pstorerdt_pi },
30212 { Hexagon::S2_pstorerdfnew_pi, Hexagon::S2_pstorerdtnew_pi },
30213 { Hexagon::S2_pstorerff_io, Hexagon::S2_pstorerft_io },
30214 { Hexagon::S2_pstorerff_pi, Hexagon::S2_pstorerft_pi },
30215 { Hexagon::S2_pstorerffnew_pi, Hexagon::S2_pstorerftnew_pi },
30216 { Hexagon::S2_pstorerhf_io, Hexagon::S2_pstorerht_io },
30217 { Hexagon::S2_pstorerhf_pi, Hexagon::S2_pstorerht_pi },
30218 { Hexagon::S2_pstorerhfnew_pi, Hexagon::S2_pstorerhtnew_pi },
30219 { Hexagon::S2_pstorerhnewf_io, Hexagon::S2_pstorerhnewt_io },
30220 { Hexagon::S2_pstorerhnewf_pi, Hexagon::S2_pstorerhnewt_pi },
30221 { Hexagon::S2_pstorerhnewfnew_pi, Hexagon::S2_pstorerhnewtnew_pi },
30222 { Hexagon::S2_pstorerif_io, Hexagon::S2_pstorerit_io },
30223 { Hexagon::S2_pstorerif_pi, Hexagon::S2_pstorerit_pi },
30224 { Hexagon::S2_pstorerifnew_pi, Hexagon::S2_pstoreritnew_pi },
30225 { Hexagon::S2_pstorerinewf_io, Hexagon::S2_pstorerinewt_io },
30226 { Hexagon::S2_pstorerinewf_pi, Hexagon::S2_pstorerinewt_pi },
30227 { Hexagon::S2_pstorerinewfnew_pi, Hexagon::S2_pstorerinewtnew_pi },
30228 { Hexagon::S4_pstorerbf_abs, Hexagon::S4_pstorerbt_abs },
30229 { Hexagon::S4_pstorerbf_rr, Hexagon::S4_pstorerbt_rr },
30230 { Hexagon::S4_pstorerbfnew_abs, Hexagon::S4_pstorerbtnew_abs },
30231 { Hexagon::S4_pstorerbfnew_io, Hexagon::S4_pstorerbtnew_io },
30232 { Hexagon::S4_pstorerbfnew_rr, Hexagon::S4_pstorerbtnew_rr },
30233 { Hexagon::S4_pstorerbnewf_abs, Hexagon::S4_pstorerbnewt_abs },
30234 { Hexagon::S4_pstorerbnewf_rr, Hexagon::S4_pstorerbnewt_rr },
30235 { Hexagon::S4_pstorerbnewfnew_abs, Hexagon::S4_pstorerbnewtnew_abs },
30236 { Hexagon::S4_pstorerbnewfnew_io, Hexagon::S4_pstorerbnewtnew_io },
30237 { Hexagon::S4_pstorerbnewfnew_rr, Hexagon::S4_pstorerbnewtnew_rr },
30238 { Hexagon::S4_pstorerdf_abs, Hexagon::S4_pstorerdt_abs },
30239 { Hexagon::S4_pstorerdf_rr, Hexagon::S4_pstorerdt_rr },
30240 { Hexagon::S4_pstorerdfnew_abs, Hexagon::S4_pstorerdtnew_abs },
30241 { Hexagon::S4_pstorerdfnew_io, Hexagon::S4_pstorerdtnew_io },
30242 { Hexagon::S4_pstorerdfnew_rr, Hexagon::S4_pstorerdtnew_rr },
30243 { Hexagon::S4_pstorerff_abs, Hexagon::S4_pstorerft_abs },
30244 { Hexagon::S4_pstorerff_rr, Hexagon::S4_pstorerft_rr },
30245 { Hexagon::S4_pstorerffnew_abs, Hexagon::S4_pstorerftnew_abs },
30246 { Hexagon::S4_pstorerffnew_io, Hexagon::S4_pstorerftnew_io },
30247 { Hexagon::S4_pstorerffnew_rr, Hexagon::S4_pstorerftnew_rr },
30248 { Hexagon::S4_pstorerhf_abs, Hexagon::S4_pstorerht_abs },
30249 { Hexagon::S4_pstorerhf_rr, Hexagon::S4_pstorerht_rr },
30250 { Hexagon::S4_pstorerhfnew_abs, Hexagon::S4_pstorerhtnew_abs },
30251 { Hexagon::S4_pstorerhfnew_io, Hexagon::S4_pstorerhtnew_io },
30252 { Hexagon::S4_pstorerhfnew_rr, Hexagon::S4_pstorerhtnew_rr },
30253 { Hexagon::S4_pstorerhnewf_abs, Hexagon::S4_pstorerhnewt_abs },
30254 { Hexagon::S4_pstorerhnewf_rr, Hexagon::S4_pstorerhnewt_rr },
30255 { Hexagon::S4_pstorerhnewfnew_abs, Hexagon::S4_pstorerhnewtnew_abs },
30256 { Hexagon::S4_pstorerhnewfnew_io, Hexagon::S4_pstorerhnewtnew_io },
30257 { Hexagon::S4_pstorerhnewfnew_rr, Hexagon::S4_pstorerhnewtnew_rr },
30258 { Hexagon::S4_pstorerif_abs, Hexagon::S4_pstorerit_abs },
30259 { Hexagon::S4_pstorerif_rr, Hexagon::S4_pstorerit_rr },
30260 { Hexagon::S4_pstorerifnew_abs, Hexagon::S4_pstoreritnew_abs },
30261 { Hexagon::S4_pstorerifnew_io, Hexagon::S4_pstoreritnew_io },
30262 { Hexagon::S4_pstorerifnew_rr, Hexagon::S4_pstoreritnew_rr },
30263 { Hexagon::S4_pstorerinewf_abs, Hexagon::S4_pstorerinewt_abs },
30264 { Hexagon::S4_pstorerinewf_rr, Hexagon::S4_pstorerinewt_rr },
30265 { Hexagon::S4_pstorerinewfnew_abs, Hexagon::S4_pstorerinewtnew_abs },
30266 { Hexagon::S4_pstorerinewfnew_io, Hexagon::S4_pstorerinewtnew_io },
30267 { Hexagon::S4_pstorerinewfnew_rr, Hexagon::S4_pstorerinewtnew_rr },
30268 { Hexagon::S4_storeirbf_io, Hexagon::S4_storeirbt_io },
30269 { Hexagon::S4_storeirbfnew_io, Hexagon::S4_storeirbtnew_io },
30270 { Hexagon::S4_storeirhf_io, Hexagon::S4_storeirht_io },
30271 { Hexagon::S4_storeirhfnew_io, Hexagon::S4_storeirhtnew_io },
30272 { Hexagon::S4_storeirif_io, Hexagon::S4_storeirit_io },
30273 { Hexagon::S4_storeirifnew_io, Hexagon::S4_storeiritnew_io },
30274 { Hexagon::V6_vL32b_cur_npred_ai, Hexagon::V6_vL32b_cur_pred_ai },
30275 { Hexagon::V6_vL32b_cur_npred_pi, Hexagon::V6_vL32b_cur_pred_pi },
30276 { Hexagon::V6_vL32b_cur_npred_ppu, Hexagon::V6_vL32b_cur_pred_ppu },
30277 { Hexagon::V6_vL32b_npred_ai, Hexagon::V6_vL32b_pred_ai },
30278 { Hexagon::V6_vL32b_npred_pi, Hexagon::V6_vL32b_pred_pi },
30279 { Hexagon::V6_vL32b_npred_ppu, Hexagon::V6_vL32b_pred_ppu },
30280 { Hexagon::V6_vL32b_nt_cur_npred_ai, Hexagon::V6_vL32b_nt_cur_pred_ai },
30281 { Hexagon::V6_vL32b_nt_cur_npred_pi, Hexagon::V6_vL32b_nt_cur_pred_pi },
30282 { Hexagon::V6_vL32b_nt_cur_npred_ppu, Hexagon::V6_vL32b_nt_cur_pred_ppu },
30283 { Hexagon::V6_vL32b_nt_npred_ai, Hexagon::V6_vL32b_nt_pred_ai },
30284 { Hexagon::V6_vL32b_nt_npred_pi, Hexagon::V6_vL32b_nt_pred_pi },
30285 { Hexagon::V6_vL32b_nt_npred_ppu, Hexagon::V6_vL32b_nt_pred_ppu },
30286 { Hexagon::V6_vL32b_nt_tmp_npred_ai, Hexagon::V6_vL32b_nt_tmp_pred_ai },
30287 { Hexagon::V6_vL32b_nt_tmp_npred_pi, Hexagon::V6_vL32b_nt_tmp_pred_pi },
30288 { Hexagon::V6_vL32b_nt_tmp_npred_ppu, Hexagon::V6_vL32b_nt_tmp_pred_ppu },
30289 { Hexagon::V6_vL32b_tmp_npred_ai, Hexagon::V6_vL32b_tmp_pred_ai },
30290 { Hexagon::V6_vL32b_tmp_npred_pi, Hexagon::V6_vL32b_tmp_pred_pi },
30291 { Hexagon::V6_vL32b_tmp_npred_ppu, Hexagon::V6_vL32b_tmp_pred_ppu },
30292 { Hexagon::V6_vS32Ub_npred_ai, Hexagon::V6_vS32Ub_pred_ai },
30293 { Hexagon::V6_vS32Ub_npred_pi, Hexagon::V6_vS32Ub_pred_pi },
30294 { Hexagon::V6_vS32Ub_npred_ppu, Hexagon::V6_vS32Ub_pred_ppu },
30295 { Hexagon::V6_vS32b_new_npred_ai, Hexagon::V6_vS32b_new_pred_ai },
30296 { Hexagon::V6_vS32b_new_npred_pi, Hexagon::V6_vS32b_new_pred_pi },
30297 { Hexagon::V6_vS32b_new_npred_ppu, Hexagon::V6_vS32b_new_pred_ppu },
30298 { Hexagon::V6_vS32b_npred_ai, Hexagon::V6_vS32b_pred_ai },
30299 { Hexagon::V6_vS32b_npred_pi, Hexagon::V6_vS32b_pred_pi },
30300 { Hexagon::V6_vS32b_npred_ppu, Hexagon::V6_vS32b_pred_ppu },
30301 { Hexagon::V6_vS32b_nt_new_npred_ai, Hexagon::V6_vS32b_nt_new_pred_ai },
30302 { Hexagon::V6_vS32b_nt_new_npred_pi, Hexagon::V6_vS32b_nt_new_pred_pi },
30303 { Hexagon::V6_vS32b_nt_new_npred_ppu, Hexagon::V6_vS32b_nt_new_pred_ppu },
30304 { Hexagon::V6_vS32b_nt_npred_ai, Hexagon::V6_vS32b_nt_pred_ai },
30305 { Hexagon::V6_vS32b_nt_npred_pi, Hexagon::V6_vS32b_nt_pred_pi },
30306 { Hexagon::V6_vS32b_nt_npred_ppu, Hexagon::V6_vS32b_nt_pred_ppu },
30307}; // End of getTruePredOpcodeTable
30308
30309 unsigned mid;
30310 unsigned start = 0;
30311 unsigned end = 250;
30312 while (start < end) {
30313 mid = start + (end - start) / 2;
30314 if (Opcode == getTruePredOpcodeTable[mid][0]) {
30315 break;
30316 }
30317 if (Opcode < getTruePredOpcodeTable[mid][0])
30318 end = mid;
30319 else
30320 start = mid + 1;
30321 }
30322 if (start == end)
30323 return -1; // Instruction doesn't exist in this table.
30324
30325 return getTruePredOpcodeTable[mid][1];
30326}
30327
30328// notTakenBranchPrediction
30329LLVM_READONLY
30330int notTakenBranchPrediction(uint16_t Opcode) {
30331static const uint16_t notTakenBranchPredictionTable[][2] = {
30332 { Hexagon::J2_jumpfnewpt, Hexagon::J2_jumpfnew },
30333 { Hexagon::J2_jumpfpt, Hexagon::J2_jumpf },
30334 { Hexagon::J2_jumprfnewpt, Hexagon::J2_jumprfnew },
30335 { Hexagon::J2_jumprfpt, Hexagon::J2_jumprf },
30336 { Hexagon::J2_jumprtnewpt, Hexagon::J2_jumprtnew },
30337 { Hexagon::J2_jumprtpt, Hexagon::J2_jumprt },
30338 { Hexagon::J2_jumptnewpt, Hexagon::J2_jumptnew },
30339 { Hexagon::J2_jumptpt, Hexagon::J2_jumpt },
30340 { Hexagon::J4_cmpeq_f_jumpnv_t, Hexagon::J4_cmpeq_f_jumpnv_nt },
30341 { Hexagon::J4_cmpeq_fp0_jump_t, Hexagon::J4_cmpeq_fp0_jump_nt },
30342 { Hexagon::J4_cmpeq_fp1_jump_t, Hexagon::J4_cmpeq_fp1_jump_nt },
30343 { Hexagon::J4_cmpeq_t_jumpnv_t, Hexagon::J4_cmpeq_t_jumpnv_nt },
30344 { Hexagon::J4_cmpeq_tp0_jump_t, Hexagon::J4_cmpeq_tp0_jump_nt },
30345 { Hexagon::J4_cmpeq_tp1_jump_t, Hexagon::J4_cmpeq_tp1_jump_nt },
30346 { Hexagon::J4_cmpeqi_f_jumpnv_t, Hexagon::J4_cmpeqi_f_jumpnv_nt },
30347 { Hexagon::J4_cmpeqi_fp0_jump_t, Hexagon::J4_cmpeqi_fp0_jump_nt },
30348 { Hexagon::J4_cmpeqi_fp1_jump_t, Hexagon::J4_cmpeqi_fp1_jump_nt },
30349 { Hexagon::J4_cmpeqi_t_jumpnv_t, Hexagon::J4_cmpeqi_t_jumpnv_nt },
30350 { Hexagon::J4_cmpeqi_tp0_jump_t, Hexagon::J4_cmpeqi_tp0_jump_nt },
30351 { Hexagon::J4_cmpeqi_tp1_jump_t, Hexagon::J4_cmpeqi_tp1_jump_nt },
30352 { Hexagon::J4_cmpeqn1_f_jumpnv_t, Hexagon::J4_cmpeqn1_f_jumpnv_nt },
30353 { Hexagon::J4_cmpeqn1_fp0_jump_t, Hexagon::J4_cmpeqn1_fp0_jump_nt },
30354 { Hexagon::J4_cmpeqn1_fp1_jump_t, Hexagon::J4_cmpeqn1_fp1_jump_nt },
30355 { Hexagon::J4_cmpeqn1_t_jumpnv_t, Hexagon::J4_cmpeqn1_t_jumpnv_nt },
30356 { Hexagon::J4_cmpeqn1_tp0_jump_t, Hexagon::J4_cmpeqn1_tp0_jump_nt },
30357 { Hexagon::J4_cmpeqn1_tp1_jump_t, Hexagon::J4_cmpeqn1_tp1_jump_nt },
30358 { Hexagon::J4_cmpgt_f_jumpnv_t, Hexagon::J4_cmpgt_f_jumpnv_nt },
30359 { Hexagon::J4_cmpgt_fp0_jump_t, Hexagon::J4_cmpgt_fp0_jump_nt },
30360 { Hexagon::J4_cmpgt_fp1_jump_t, Hexagon::J4_cmpgt_fp1_jump_nt },
30361 { Hexagon::J4_cmpgt_t_jumpnv_t, Hexagon::J4_cmpgt_t_jumpnv_nt },
30362 { Hexagon::J4_cmpgt_tp0_jump_t, Hexagon::J4_cmpgt_tp0_jump_nt },
30363 { Hexagon::J4_cmpgt_tp1_jump_t, Hexagon::J4_cmpgt_tp1_jump_nt },
30364 { Hexagon::J4_cmpgti_f_jumpnv_t, Hexagon::J4_cmpgti_f_jumpnv_nt },
30365 { Hexagon::J4_cmpgti_fp0_jump_t, Hexagon::J4_cmpgti_fp0_jump_nt },
30366 { Hexagon::J4_cmpgti_fp1_jump_t, Hexagon::J4_cmpgti_fp1_jump_nt },
30367 { Hexagon::J4_cmpgti_t_jumpnv_t, Hexagon::J4_cmpgti_t_jumpnv_nt },
30368 { Hexagon::J4_cmpgti_tp0_jump_t, Hexagon::J4_cmpgti_tp0_jump_nt },
30369 { Hexagon::J4_cmpgti_tp1_jump_t, Hexagon::J4_cmpgti_tp1_jump_nt },
30370 { Hexagon::J4_cmpgtn1_f_jumpnv_t, Hexagon::J4_cmpgtn1_f_jumpnv_nt },
30371 { Hexagon::J4_cmpgtn1_fp0_jump_t, Hexagon::J4_cmpgtn1_fp0_jump_nt },
30372 { Hexagon::J4_cmpgtn1_fp1_jump_t, Hexagon::J4_cmpgtn1_fp1_jump_nt },
30373 { Hexagon::J4_cmpgtn1_t_jumpnv_t, Hexagon::J4_cmpgtn1_t_jumpnv_nt },
30374 { Hexagon::J4_cmpgtn1_tp0_jump_t, Hexagon::J4_cmpgtn1_tp0_jump_nt },
30375 { Hexagon::J4_cmpgtn1_tp1_jump_t, Hexagon::J4_cmpgtn1_tp1_jump_nt },
30376 { Hexagon::J4_cmpgtu_f_jumpnv_t, Hexagon::J4_cmpgtu_f_jumpnv_nt },
30377 { Hexagon::J4_cmpgtu_fp0_jump_t, Hexagon::J4_cmpgtu_fp0_jump_nt },
30378 { Hexagon::J4_cmpgtu_fp1_jump_t, Hexagon::J4_cmpgtu_fp1_jump_nt },
30379 { Hexagon::J4_cmpgtu_t_jumpnv_t, Hexagon::J4_cmpgtu_t_jumpnv_nt },
30380 { Hexagon::J4_cmpgtu_tp0_jump_t, Hexagon::J4_cmpgtu_tp0_jump_nt },
30381 { Hexagon::J4_cmpgtu_tp1_jump_t, Hexagon::J4_cmpgtu_tp1_jump_nt },
30382 { Hexagon::J4_cmpgtui_f_jumpnv_t, Hexagon::J4_cmpgtui_f_jumpnv_nt },
30383 { Hexagon::J4_cmpgtui_fp0_jump_t, Hexagon::J4_cmpgtui_fp0_jump_nt },
30384 { Hexagon::J4_cmpgtui_fp1_jump_t, Hexagon::J4_cmpgtui_fp1_jump_nt },
30385 { Hexagon::J4_cmpgtui_t_jumpnv_t, Hexagon::J4_cmpgtui_t_jumpnv_nt },
30386 { Hexagon::J4_cmpgtui_tp0_jump_t, Hexagon::J4_cmpgtui_tp0_jump_nt },
30387 { Hexagon::J4_cmpgtui_tp1_jump_t, Hexagon::J4_cmpgtui_tp1_jump_nt },
30388 { Hexagon::J4_cmplt_f_jumpnv_t, Hexagon::J4_cmplt_f_jumpnv_nt },
30389 { Hexagon::J4_cmplt_t_jumpnv_t, Hexagon::J4_cmplt_t_jumpnv_nt },
30390 { Hexagon::J4_cmpltu_f_jumpnv_t, Hexagon::J4_cmpltu_f_jumpnv_nt },
30391 { Hexagon::J4_cmpltu_t_jumpnv_t, Hexagon::J4_cmpltu_t_jumpnv_nt },
30392 { Hexagon::L4_return_fnew_pt, Hexagon::L4_return_fnew_pnt },
30393 { Hexagon::L4_return_tnew_pt, Hexagon::L4_return_tnew_pnt },
30394 { Hexagon::PS_jmpretfnewpt, Hexagon::PS_jmpretfnew },
30395 { Hexagon::PS_jmprettnewpt, Hexagon::PS_jmprettnew },
30396}; // End of notTakenBranchPredictionTable
30397
30398 unsigned mid;
30399 unsigned start = 0;
30400 unsigned end = 64;
30401 while (start < end) {
30402 mid = start + (end - start) / 2;
30403 if (Opcode == notTakenBranchPredictionTable[mid][0]) {
30404 break;
30405 }
30406 if (Opcode < notTakenBranchPredictionTable[mid][0])
30407 end = mid;
30408 else
30409 start = mid + 1;
30410 }
30411 if (start == end)
30412 return -1; // Instruction doesn't exist in this table.
30413
30414 return notTakenBranchPredictionTable[mid][1];
30415}
30416
30417// takenBranchPrediction
30418LLVM_READONLY
30419int takenBranchPrediction(uint16_t Opcode) {
30420static const uint16_t takenBranchPredictionTable[][2] = {
30421 { Hexagon::J2_jumpf, Hexagon::J2_jumpfpt },
30422 { Hexagon::J2_jumpfnew, Hexagon::J2_jumpfnewpt },
30423 { Hexagon::J2_jumprf, Hexagon::J2_jumprfpt },
30424 { Hexagon::J2_jumprfnew, Hexagon::J2_jumprfnewpt },
30425 { Hexagon::J2_jumprt, Hexagon::J2_jumprtpt },
30426 { Hexagon::J2_jumprtnew, Hexagon::J2_jumprtnewpt },
30427 { Hexagon::J2_jumpt, Hexagon::J2_jumptpt },
30428 { Hexagon::J2_jumptnew, Hexagon::J2_jumptnewpt },
30429 { Hexagon::J4_cmpeq_f_jumpnv_nt, Hexagon::J4_cmpeq_f_jumpnv_t },
30430 { Hexagon::J4_cmpeq_fp0_jump_nt, Hexagon::J4_cmpeq_fp0_jump_t },
30431 { Hexagon::J4_cmpeq_fp1_jump_nt, Hexagon::J4_cmpeq_fp1_jump_t },
30432 { Hexagon::J4_cmpeq_t_jumpnv_nt, Hexagon::J4_cmpeq_t_jumpnv_t },
30433 { Hexagon::J4_cmpeq_tp0_jump_nt, Hexagon::J4_cmpeq_tp0_jump_t },
30434 { Hexagon::J4_cmpeq_tp1_jump_nt, Hexagon::J4_cmpeq_tp1_jump_t },
30435 { Hexagon::J4_cmpeqi_f_jumpnv_nt, Hexagon::J4_cmpeqi_f_jumpnv_t },
30436 { Hexagon::J4_cmpeqi_fp0_jump_nt, Hexagon::J4_cmpeqi_fp0_jump_t },
30437 { Hexagon::J4_cmpeqi_fp1_jump_nt, Hexagon::J4_cmpeqi_fp1_jump_t },
30438 { Hexagon::J4_cmpeqi_t_jumpnv_nt, Hexagon::J4_cmpeqi_t_jumpnv_t },
30439 { Hexagon::J4_cmpeqi_tp0_jump_nt, Hexagon::J4_cmpeqi_tp0_jump_t },
30440 { Hexagon::J4_cmpeqi_tp1_jump_nt, Hexagon::J4_cmpeqi_tp1_jump_t },
30441 { Hexagon::J4_cmpeqn1_f_jumpnv_nt, Hexagon::J4_cmpeqn1_f_jumpnv_t },
30442 { Hexagon::J4_cmpeqn1_fp0_jump_nt, Hexagon::J4_cmpeqn1_fp0_jump_t },
30443 { Hexagon::J4_cmpeqn1_fp1_jump_nt, Hexagon::J4_cmpeqn1_fp1_jump_t },
30444 { Hexagon::J4_cmpeqn1_t_jumpnv_nt, Hexagon::J4_cmpeqn1_t_jumpnv_t },
30445 { Hexagon::J4_cmpeqn1_tp0_jump_nt, Hexagon::J4_cmpeqn1_tp0_jump_t },
30446 { Hexagon::J4_cmpeqn1_tp1_jump_nt, Hexagon::J4_cmpeqn1_tp1_jump_t },
30447 { Hexagon::J4_cmpgt_f_jumpnv_nt, Hexagon::J4_cmpgt_f_jumpnv_t },
30448 { Hexagon::J4_cmpgt_fp0_jump_nt, Hexagon::J4_cmpgt_fp0_jump_t },
30449 { Hexagon::J4_cmpgt_fp1_jump_nt, Hexagon::J4_cmpgt_fp1_jump_t },
30450 { Hexagon::J4_cmpgt_t_jumpnv_nt, Hexagon::J4_cmpgt_t_jumpnv_t },
30451 { Hexagon::J4_cmpgt_tp0_jump_nt, Hexagon::J4_cmpgt_tp0_jump_t },
30452 { Hexagon::J4_cmpgt_tp1_jump_nt, Hexagon::J4_cmpgt_tp1_jump_t },
30453 { Hexagon::J4_cmpgti_f_jumpnv_nt, Hexagon::J4_cmpgti_f_jumpnv_t },
30454 { Hexagon::J4_cmpgti_fp0_jump_nt, Hexagon::J4_cmpgti_fp0_jump_t },
30455 { Hexagon::J4_cmpgti_fp1_jump_nt, Hexagon::J4_cmpgti_fp1_jump_t },
30456 { Hexagon::J4_cmpgti_t_jumpnv_nt, Hexagon::J4_cmpgti_t_jumpnv_t },
30457 { Hexagon::J4_cmpgti_tp0_jump_nt, Hexagon::J4_cmpgti_tp0_jump_t },
30458 { Hexagon::J4_cmpgti_tp1_jump_nt, Hexagon::J4_cmpgti_tp1_jump_t },
30459 { Hexagon::J4_cmpgtn1_f_jumpnv_nt, Hexagon::J4_cmpgtn1_f_jumpnv_t },
30460 { Hexagon::J4_cmpgtn1_fp0_jump_nt, Hexagon::J4_cmpgtn1_fp0_jump_t },
30461 { Hexagon::J4_cmpgtn1_fp1_jump_nt, Hexagon::J4_cmpgtn1_fp1_jump_t },
30462 { Hexagon::J4_cmpgtn1_t_jumpnv_nt, Hexagon::J4_cmpgtn1_t_jumpnv_t },
30463 { Hexagon::J4_cmpgtn1_tp0_jump_nt, Hexagon::J4_cmpgtn1_tp0_jump_t },
30464 { Hexagon::J4_cmpgtn1_tp1_jump_nt, Hexagon::J4_cmpgtn1_tp1_jump_t },
30465 { Hexagon::J4_cmpgtu_f_jumpnv_nt, Hexagon::J4_cmpgtu_f_jumpnv_t },
30466 { Hexagon::J4_cmpgtu_fp0_jump_nt, Hexagon::J4_cmpgtu_fp0_jump_t },
30467 { Hexagon::J4_cmpgtu_fp1_jump_nt, Hexagon::J4_cmpgtu_fp1_jump_t },
30468 { Hexagon::J4_cmpgtu_t_jumpnv_nt, Hexagon::J4_cmpgtu_t_jumpnv_t },
30469 { Hexagon::J4_cmpgtu_tp0_jump_nt, Hexagon::J4_cmpgtu_tp0_jump_t },
30470 { Hexagon::J4_cmpgtu_tp1_jump_nt, Hexagon::J4_cmpgtu_tp1_jump_t },
30471 { Hexagon::J4_cmpgtui_f_jumpnv_nt, Hexagon::J4_cmpgtui_f_jumpnv_t },
30472 { Hexagon::J4_cmpgtui_fp0_jump_nt, Hexagon::J4_cmpgtui_fp0_jump_t },
30473 { Hexagon::J4_cmpgtui_fp1_jump_nt, Hexagon::J4_cmpgtui_fp1_jump_t },
30474 { Hexagon::J4_cmpgtui_t_jumpnv_nt, Hexagon::J4_cmpgtui_t_jumpnv_t },
30475 { Hexagon::J4_cmpgtui_tp0_jump_nt, Hexagon::J4_cmpgtui_tp0_jump_t },
30476 { Hexagon::J4_cmpgtui_tp1_jump_nt, Hexagon::J4_cmpgtui_tp1_jump_t },
30477 { Hexagon::J4_cmplt_f_jumpnv_nt, Hexagon::J4_cmplt_f_jumpnv_t },
30478 { Hexagon::J4_cmplt_t_jumpnv_nt, Hexagon::J4_cmplt_t_jumpnv_t },
30479 { Hexagon::J4_cmpltu_f_jumpnv_nt, Hexagon::J4_cmpltu_f_jumpnv_t },
30480 { Hexagon::J4_cmpltu_t_jumpnv_nt, Hexagon::J4_cmpltu_t_jumpnv_t },
30481 { Hexagon::L4_return_fnew_pnt, Hexagon::L4_return_fnew_pt },
30482 { Hexagon::L4_return_tnew_pnt, Hexagon::L4_return_tnew_pt },
30483 { Hexagon::PS_jmpretfnew, Hexagon::PS_jmpretfnewpt },
30484 { Hexagon::PS_jmprettnew, Hexagon::PS_jmprettnewpt },
30485}; // End of takenBranchPredictionTable
30486
30487 unsigned mid;
30488 unsigned start = 0;
30489 unsigned end = 64;
30490 while (start < end) {
30491 mid = start + (end - start) / 2;
30492 if (Opcode == takenBranchPredictionTable[mid][0]) {
30493 break;
30494 }
30495 if (Opcode < takenBranchPredictionTable[mid][0])
30496 end = mid;
30497 else
30498 start = mid + 1;
30499 }
30500 if (start == end)
30501 return -1; // Instruction doesn't exist in this table.
30502
30503 return takenBranchPredictionTable[mid][1];
30504}
30505
30506} // end namespace Hexagon
30507} // end namespace llvm
30508#endif // GET_INSTRMAP_INFO
30509
30510