1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass HexagonMCRegisterClasses[];
17
18namespace Hexagon {
19enum {
20 NoRegister,
21 BADVA = 1,
22 CCR = 2,
23 CFGBASE = 3,
24 CS = 4,
25 DIAG = 5,
26 ELR = 6,
27 EVB = 7,
28 FRAMEKEY = 8,
29 FRAMELIMIT = 9,
30 GELR = 10,
31 GOSP = 11,
32 GP = 12,
33 GPCYCLEHI = 13,
34 GPCYCLELO = 14,
35 GSR = 15,
36 HTID = 16,
37 IMASK = 17,
38 ISDBEN = 18,
39 ISDBGPR = 19,
40 ISDBMBXIN = 20,
41 ISDBMBXOUT = 21,
42 ISDBST = 22,
43 MODECTL = 23,
44 PC = 24,
45 PCYCLEHI = 25,
46 PCYCLELO = 26,
47 PKTCOUNT = 27,
48 PKTCOUNTHI = 28,
49 PKTCOUNTLO = 29,
50 PMUCFG = 30,
51 PMUEVTCFG = 31,
52 REV = 32,
53 SSR = 33,
54 STID = 34,
55 SYSCFG = 35,
56 UGP = 36,
57 UPCYCLE = 37,
58 UPCYCLEHI = 38,
59 UPCYCLELO = 39,
60 USR = 40,
61 USR_OVF = 41,
62 UTIMER = 42,
63 UTIMERHI = 43,
64 UTIMERLO = 44,
65 VID = 45,
66 VTMP = 46,
67 BADVA0 = 47,
68 BADVA1 = 48,
69 BRKPTCFG0 = 49,
70 BRKPTCFG1 = 50,
71 BRKPTPC0 = 51,
72 BRKPTPC1 = 52,
73 C5 = 53,
74 C8 = 54,
75 CS0 = 55,
76 CS1 = 56,
77 D0 = 57,
78 D1 = 58,
79 D2 = 59,
80 D3 = 60,
81 D4 = 61,
82 D5 = 62,
83 D6 = 63,
84 D7 = 64,
85 D8 = 65,
86 D9 = 66,
87 D10 = 67,
88 D11 = 68,
89 D12 = 69,
90 D13 = 70,
91 D14 = 71,
92 D15 = 72,
93 G3 = 73,
94 G4 = 74,
95 G5 = 75,
96 G6 = 76,
97 G7 = 77,
98 G8 = 78,
99 G9 = 79,
100 G10 = 80,
101 G11 = 81,
102 G12 = 82,
103 G13 = 83,
104 G14 = 84,
105 G15 = 85,
106 G20 = 86,
107 G21 = 87,
108 G22 = 88,
109 G23 = 89,
110 G30 = 90,
111 G31 = 91,
112 GPMUCNT0 = 92,
113 GPMUCNT1 = 93,
114 GPMUCNT2 = 94,
115 GPMUCNT3 = 95,
116 GPMUCNT4 = 96,
117 GPMUCNT5 = 97,
118 GPMUCNT6 = 98,
119 GPMUCNT7 = 99,
120 ISDBCFG0 = 100,
121 ISDBCFG1 = 101,
122 LC0 = 102,
123 LC1 = 103,
124 M0 = 104,
125 M1 = 105,
126 P0 = 106,
127 P1 = 107,
128 P2 = 108,
129 P3 = 109,
130 PMUCNT0 = 110,
131 PMUCNT1 = 111,
132 PMUCNT2 = 112,
133 PMUCNT3 = 113,
134 Q0 = 114,
135 Q1 = 115,
136 Q2 = 116,
137 Q3 = 117,
138 R0 = 118,
139 R1 = 119,
140 R2 = 120,
141 R3 = 121,
142 R4 = 122,
143 R5 = 123,
144 R6 = 124,
145 R7 = 125,
146 R8 = 126,
147 R9 = 127,
148 R10 = 128,
149 R11 = 129,
150 R12 = 130,
151 R13 = 131,
152 R14 = 132,
153 R15 = 133,
154 R16 = 134,
155 R17 = 135,
156 R18 = 136,
157 R19 = 137,
158 R20 = 138,
159 R21 = 139,
160 R22 = 140,
161 R23 = 141,
162 R24 = 142,
163 R25 = 143,
164 R26 = 144,
165 R27 = 145,
166 R28 = 146,
167 R29 = 147,
168 R30 = 148,
169 R31 = 149,
170 S11 = 150,
171 S12 = 151,
172 S13 = 152,
173 S14 = 153,
174 S15 = 154,
175 S19 = 155,
176 S20 = 156,
177 S22 = 157,
178 S23 = 158,
179 S24 = 159,
180 S25 = 160,
181 S26 = 161,
182 S35 = 162,
183 S44 = 163,
184 S45 = 164,
185 S46 = 165,
186 S47 = 166,
187 S54 = 167,
188 S55 = 168,
189 S56 = 169,
190 S57 = 170,
191 S58 = 171,
192 S59 = 172,
193 S60 = 173,
194 S61 = 174,
195 S62 = 175,
196 S63 = 176,
197 S64 = 177,
198 S65 = 178,
199 S66 = 179,
200 S67 = 180,
201 S68 = 181,
202 S69 = 182,
203 S70 = 183,
204 S71 = 184,
205 S72 = 185,
206 S73 = 186,
207 S74 = 187,
208 S75 = 188,
209 S76 = 189,
210 S77 = 190,
211 S78 = 191,
212 S79 = 192,
213 S80 = 193,
214 SA0 = 194,
215 SA1 = 195,
216 SGP0 = 196,
217 SGP1 = 197,
218 V0 = 198,
219 V1 = 199,
220 V2 = 200,
221 V3 = 201,
222 V4 = 202,
223 V5 = 203,
224 V6 = 204,
225 V7 = 205,
226 V8 = 206,
227 V9 = 207,
228 V10 = 208,
229 V11 = 209,
230 V12 = 210,
231 V13 = 211,
232 V14 = 212,
233 V15 = 213,
234 V16 = 214,
235 V17 = 215,
236 V18 = 216,
237 V19 = 217,
238 V20 = 218,
239 V21 = 219,
240 V22 = 220,
241 V23 = 221,
242 V24 = 222,
243 V25 = 223,
244 V26 = 224,
245 V27 = 225,
246 V28 = 226,
247 V29 = 227,
248 V30 = 228,
249 V31 = 229,
250 VF0 = 230,
251 VF1 = 231,
252 VF2 = 232,
253 VF3 = 233,
254 VF4 = 234,
255 VF5 = 235,
256 VF6 = 236,
257 VF7 = 237,
258 VF8 = 238,
259 VF9 = 239,
260 VF10 = 240,
261 VF11 = 241,
262 VF12 = 242,
263 VF13 = 243,
264 VF14 = 244,
265 VF15 = 245,
266 VF16 = 246,
267 VF17 = 247,
268 VF18 = 248,
269 VF19 = 249,
270 VF20 = 250,
271 VF21 = 251,
272 VF22 = 252,
273 VF23 = 253,
274 VF24 = 254,
275 VF25 = 255,
276 VF26 = 256,
277 VF27 = 257,
278 VF28 = 258,
279 VF29 = 259,
280 VF30 = 260,
281 VF31 = 261,
282 VFR0 = 262,
283 VFR1 = 263,
284 VFR2 = 264,
285 VFR3 = 265,
286 VFR4 = 266,
287 VFR5 = 267,
288 VFR6 = 268,
289 VFR7 = 269,
290 VFR8 = 270,
291 VFR9 = 271,
292 VFR10 = 272,
293 VFR11 = 273,
294 VFR12 = 274,
295 VFR13 = 275,
296 VFR14 = 276,
297 VFR15 = 277,
298 VFR16 = 278,
299 VFR17 = 279,
300 VFR18 = 280,
301 VFR19 = 281,
302 VFR20 = 282,
303 VFR21 = 283,
304 VFR22 = 284,
305 VFR23 = 285,
306 VFR24 = 286,
307 VFR25 = 287,
308 VFR26 = 288,
309 VFR27 = 289,
310 VFR28 = 290,
311 VFR29 = 291,
312 VFR30 = 292,
313 VFR31 = 293,
314 VQ0 = 294,
315 VQ1 = 295,
316 VQ2 = 296,
317 VQ3 = 297,
318 VQ4 = 298,
319 VQ5 = 299,
320 VQ6 = 300,
321 VQ7 = 301,
322 W0 = 302,
323 W1 = 303,
324 W2 = 304,
325 W3 = 305,
326 W4 = 306,
327 W5 = 307,
328 W6 = 308,
329 W7 = 309,
330 W8 = 310,
331 W9 = 311,
332 W10 = 312,
333 W11 = 313,
334 W12 = 314,
335 W13 = 315,
336 W14 = 316,
337 W15 = 317,
338 WR0 = 318,
339 WR1 = 319,
340 WR2 = 320,
341 WR3 = 321,
342 WR4 = 322,
343 WR5 = 323,
344 WR6 = 324,
345 WR7 = 325,
346 WR8 = 326,
347 WR9 = 327,
348 WR10 = 328,
349 WR11 = 329,
350 WR12 = 330,
351 WR13 = 331,
352 WR14 = 332,
353 WR15 = 333,
354 C1_0 = 334,
355 C3_2 = 335,
356 C5_4 = 336,
357 C7_6 = 337,
358 C9_8 = 338,
359 C11_10 = 339,
360 C17_16 = 340,
361 G1_0 = 341,
362 G3_2 = 342,
363 G5_4 = 343,
364 G7_6 = 344,
365 G9_8 = 345,
366 G11_10 = 346,
367 G13_12 = 347,
368 G15_14 = 348,
369 G17_16 = 349,
370 G19_18 = 350,
371 G21_20 = 351,
372 G23_22 = 352,
373 G25_24 = 353,
374 G27_26 = 354,
375 G29_28 = 355,
376 G31_30 = 356,
377 P3_0 = 357,
378 S3_2 = 358,
379 S5_4 = 359,
380 S7_6 = 360,
381 S9_8 = 361,
382 S11_10 = 362,
383 S13_12 = 363,
384 S15_14 = 364,
385 S17_16 = 365,
386 S19_18 = 366,
387 S21_20 = 367,
388 S23_22 = 368,
389 S25_24 = 369,
390 S27_26 = 370,
391 S29_28 = 371,
392 S31_30 = 372,
393 S33_32 = 373,
394 S35_34 = 374,
395 S37_36 = 375,
396 S39_38 = 376,
397 S41_40 = 377,
398 S43_42 = 378,
399 S45_44 = 379,
400 S47_46 = 380,
401 S49_48 = 381,
402 S51_50 = 382,
403 S53_52 = 383,
404 S55_54 = 384,
405 S57_56 = 385,
406 S59_58 = 386,
407 S61_60 = 387,
408 S63_62 = 388,
409 S65_64 = 389,
410 S67_66 = 390,
411 S69_68 = 391,
412 S71_70 = 392,
413 S73_72 = 393,
414 S75_74 = 394,
415 S77_76 = 395,
416 S79_78 = 396,
417 SGP1_0 = 397,
418 NUM_TARGET_REGS // 398
419};
420} // end namespace Hexagon
421
422// Register classes
423
424namespace Hexagon {
425enum {
426 UsrBitsRegClassID = 0,
427 SysRegsRegClassID = 1,
428 GuestRegsRegClassID = 2,
429 IntRegsRegClassID = 3,
430 CtrRegsRegClassID = 4,
431 GeneralSubRegsRegClassID = 5,
432 V62RegsRegClassID = 6,
433 IntRegsLow8RegClassID = 7,
434 CtrRegs_and_V62RegsRegClassID = 8,
435 PredRegsRegClassID = 9,
436 V62Regs_with_isub_hiRegClassID = 10,
437 ModRegsRegClassID = 11,
438 CtrRegs_with_subreg_overflowRegClassID = 12,
439 V65RegsRegClassID = 13,
440 SysRegs64RegClassID = 14,
441 DoubleRegsRegClassID = 15,
442 GuestRegs64RegClassID = 16,
443 VectRegRevRegClassID = 17,
444 CtrRegs64RegClassID = 18,
445 GeneralDoubleLow8RegsRegClassID = 19,
446 DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID = 20,
447 CtrRegs64_and_V62RegsRegClassID = 21,
448 CtrRegs64_with_isub_hi_in_ModRegsRegClassID = 22,
449 HvxQRRegClassID = 23,
450 HvxVRRegClassID = 24,
451 HvxVR_and_V65RegsRegClassID = 25,
452 HvxWRRegClassID = 26,
453 HvxWR_and_VectRegRevRegClassID = 27,
454 HvxVQRRegClassID = 28,
455
456};
457} // end namespace Hexagon
458
459
460// Subregister indices
461
462namespace Hexagon {
463enum : uint16_t {
464 NoSubRegister,
465 isub_hi, // 1
466 isub_lo, // 2
467 subreg_overflow, // 3
468 vsub_fake, // 4
469 vsub_hi, // 5
470 vsub_lo, // 6
471 wsub_hi, // 7
472 wsub_lo, // 8
473 wsub_hi_then_vsub_fake, // 9
474 wsub_hi_then_vsub_hi, // 10
475 wsub_hi_then_vsub_lo, // 11
476 NUM_TARGET_SUBREGS
477};
478} // end namespace Hexagon
479
480// Register pressure sets enum.
481namespace Hexagon {
482enum RegisterPressureSets {
483 HvxVR_and_V65Regs = 0,
484 ModRegs = 1,
485 PredRegs = 2,
486 HvxQR = 3,
487 IntRegsLow8 = 4,
488 GeneralSubRegs = 5,
489 IntRegs = 6,
490 HvxVR = 7,
491};
492} // end namespace Hexagon
493
494} // end namespace llvm
495
496#endif // GET_REGINFO_ENUM
497
498/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
499|* *|
500|* MC Register Information *|
501|* *|
502|* Automatically generated file, do not edit! *|
503|* *|
504\*===----------------------------------------------------------------------===*/
505
506
507#ifdef GET_REGINFO_MC_DESC
508#undef GET_REGINFO_MC_DESC
509
510namespace llvm {
511
512extern const int16_t HexagonRegDiffLists[] = {
513 /* 0 */ 21, -304, 0,
514 /* 3 */ -209, -158, 0,
515 /* 6 */ -211, -111, 0,
516 /* 9 */ -140, -92, 0,
517 /* 12 */ -77, 0,
518 /* 14 */ -76, 0,
519 /* 16 */ -75, 0,
520 /* 18 */ -74, 0,
521 /* 20 */ -73, 0,
522 /* 22 */ -72, 0,
523 /* 24 */ -71, 0,
524 /* 26 */ -70, 0,
525 /* 28 */ -69, 0,
526 /* 30 */ -68, 0,
527 /* 32 */ -67, 0,
528 /* 34 */ -66, 0,
529 /* 36 */ -65, 0,
530 /* 38 */ -64, 0,
531 /* 40 */ -63, 0,
532 /* 42 */ -62, 0,
533 /* 44 */ -61, 0,
534 /* 46 */ -52, 0,
535 /* 48 */ -51, 0,
536 /* 50 */ -327, -31, 0,
537 /* 53 */ -284, -30, 0,
538 /* 56 */ -324, -28, 0,
539 /* 59 */ -303, -24, 0,
540 /* 62 */ -21, 0,
541 /* 64 */ 72, -16, 0,
542 /* 67 */ -345, -15, 0,
543 /* 70 */ 72, -15, 0,
544 /* 73 */ 72, -14, 0,
545 /* 76 */ 72, -13, 0,
546 /* 79 */ 72, -12, 0,
547 /* 82 */ 72, -11, 0,
548 /* 85 */ 72, -10, 0,
549 /* 88 */ 72, -9, 0,
550 /* 91 */ 72, -8, 0,
551 /* 94 */ -324, -2, 0,
552 /* 97 */ -352, -1, 0,
553 /* 100 */ -346, -1, 0,
554 /* 103 */ -339, -1, 0,
555 /* 106 */ -331, -1, 0,
556 /* 109 */ -205, -1, 0,
557 /* 112 */ -204, -1, 0,
558 /* 115 */ 2, -1, 0,
559 /* 118 */ -360, 1, 0,
560 /* 121 */ -357, 1, 0,
561 /* 124 */ -312, 1, 0,
562 /* 127 */ -271, 1, 0,
563 /* 130 */ -270, 1, 0,
564 /* 133 */ -269, 1, 0,
565 /* 136 */ -268, 1, 0,
566 /* 139 */ -267, 1, 0,
567 /* 142 */ -266, 1, 0,
568 /* 145 */ -265, 1, 0,
569 /* 148 */ -264, 1, 0,
570 /* 151 */ -262, 1, 0,
571 /* 154 */ -261, 1, 0,
572 /* 157 */ -253, 1, 0,
573 /* 160 */ -252, 1, 0,
574 /* 163 */ -233, 1, 0,
575 /* 166 */ -217, 1, 0,
576 /* 169 */ -216, 1, 0,
577 /* 172 */ -215, 1, 0,
578 /* 175 */ -214, 1, 0,
579 /* 178 */ -213, 1, 0,
580 /* 181 */ -212, 1, 0,
581 /* 184 */ -211, 1, 0,
582 /* 187 */ -210, 1, 0,
583 /* 190 */ -209, 1, 0,
584 /* 193 */ -208, 1, 0,
585 /* 196 */ -207, 1, 0,
586 /* 199 */ -201, 1, 0,
587 /* 202 */ 66, 1, 1, 1, 0,
588 /* 207 */ 1, 1, 1, 15, 1, 0,
589 /* 213 */ 1, 1, 1, 17, 1, 0,
590 /* 219 */ 1, 1, 1, 19, 1, 0,
591 /* 225 */ 1, 1, 1, 21, 1, 0,
592 /* 231 */ 1, 1, 1, 23, 1, 0,
593 /* 237 */ 1, 1, 1, 25, 1, 0,
594 /* 243 */ 1, 1, 1, 27, 1, 0,
595 /* 249 */ 1, 1, 1, 29, 1, 0,
596 /* 255 */ 51, 1, 0,
597 /* 258 */ 61, 1, 0,
598 /* 261 */ 62, 1, 0,
599 /* 264 */ 63, 1, 0,
600 /* 267 */ 64, 1, 0,
601 /* 270 */ 65, 1, 0,
602 /* 273 */ 66, 1, 0,
603 /* 276 */ 67, 1, 0,
604 /* 279 */ 68, 1, 0,
605 /* 282 */ 69, 1, 0,
606 /* 285 */ 70, 1, 0,
607 /* 288 */ 71, 1, 0,
608 /* 291 */ 72, 1, 0,
609 /* 294 */ 73, 1, 0,
610 /* 297 */ 74, 1, 0,
611 /* 300 */ 75, 1, 0,
612 /* 303 */ 76, 1, 0,
613 /* 306 */ 2, 0,
614 /* 308 */ -331, 5, 0,
615 /* 311 */ 15, 0,
616 /* 313 */ -358, 16, 0,
617 /* 316 */ 15, -90, 1, 17, 73, -89, 1, 16, 0,
618 /* 325 */ -90, 1, 17, 0,
619 /* 329 */ 14, -92, 1, 19, 73, -91, 1, 18, 0,
620 /* 338 */ -92, 1, 19, 0,
621 /* 342 */ 13, -94, 1, 21, 73, -93, 1, 20, 0,
622 /* 351 */ -94, 1, 21, 0,
623 /* 355 */ 12, -96, 1, 23, 73, -95, 1, 22, 0,
624 /* 364 */ -96, 1, 23, 0,
625 /* 368 */ 103, -8, 24, 0,
626 /* 372 */ 104, -8, 24, 0,
627 /* 376 */ 11, -98, 1, 25, 73, -97, 1, 24, 0,
628 /* 385 */ 101, -9, 25, 0,
629 /* 389 */ 102, -9, 25, 0,
630 /* 393 */ 103, -9, 25, 0,
631 /* 397 */ -98, 1, 25, 0,
632 /* 401 */ 99, -10, 26, 0,
633 /* 405 */ 100, -10, 26, 0,
634 /* 409 */ 101, -10, 26, 0,
635 /* 413 */ 10, -100, 1, 27, 73, -99, 1, 26, 0,
636 /* 422 */ -366, 27, 0,
637 /* 425 */ 97, -11, 27, 0,
638 /* 429 */ 98, -11, 27, 0,
639 /* 433 */ 99, -11, 27, 0,
640 /* 437 */ -100, 1, 27, 0,
641 /* 441 */ 95, -12, 28, 0,
642 /* 445 */ 96, -12, 28, 0,
643 /* 449 */ 97, -12, 28, 0,
644 /* 453 */ 9, -102, 1, 29, 73, -101, 1, 28, 0,
645 /* 462 */ 93, -13, 29, 0,
646 /* 466 */ 94, -13, 29, 0,
647 /* 470 */ 95, -13, 29, 0,
648 /* 474 */ -102, 1, 29, 0,
649 /* 478 */ 91, -14, 30, 0,
650 /* 482 */ 92, -14, 30, 0,
651 /* 486 */ 93, -14, 30, 0,
652 /* 490 */ 8, -104, 1, 31, 73, -103, 1, 30, 0,
653 /* 499 */ 89, -15, 31, 0,
654 /* 503 */ 90, -15, 31, 0,
655 /* 507 */ 91, -15, 31, 0,
656 /* 511 */ -104, 1, 31, 0,
657 /* 515 */ 88, -16, 32, 0,
658 /* 519 */ 89, -16, 32, 0,
659 /* 523 */ -105, 1, 48, 0,
660 /* 527 */ -106, 1, 49, 0,
661 /* 531 */ -107, 1, 50, 0,
662 /* 535 */ -108, 1, 51, 0,
663 /* 539 */ -109, 1, 52, 0,
664 /* 543 */ -110, 1, 53, 0,
665 /* 547 */ -111, 1, 54, 0,
666 /* 551 */ -112, 1, 55, 0,
667 /* 555 */ -113, 1, 56, 0,
668 /* 559 */ -114, 1, 57, 0,
669 /* 563 */ -115, 1, 58, 0,
670 /* 567 */ -116, 1, 59, 0,
671 /* 571 */ -117, 1, 60, 0,
672 /* 575 */ -273, 61, 0,
673 /* 578 */ -118, 1, 61, 0,
674 /* 582 */ -331, 62, 0,
675 /* 585 */ -119, 1, 62, 0,
676 /* 589 */ -120, 1, 63, 0,
677 /* 593 */ 72, 0,
678 /* 595 */ -351, 78, 0,
679 /* 598 */ 88, 0,
680 /* 600 */ 92, 0,
681 /* 602 */ 99, 0,
682 /* 604 */ 111, 0,
683 /* 606 */ -331, 120, 0,
684 /* 609 */ -345, 133, 0,
685 /* 612 */ 137, 0,
686 /* 614 */ 140, 0,
687 /* 616 */ 200, 0,
688 /* 618 */ 201, 0,
689 /* 620 */ 204, 0,
690 /* 622 */ 205, 0,
691 /* 624 */ 206, 0,
692 /* 626 */ 207, 0,
693 /* 628 */ 208, 0,
694 /* 630 */ 209, 0,
695 /* 632 */ 210, 0,
696 /* 634 */ 211, 0,
697 /* 636 */ 212, 0,
698 /* 638 */ 213, 0,
699 /* 640 */ 214, 0,
700 /* 642 */ 215, 0,
701 /* 644 */ 216, 0,
702 /* 646 */ 217, 0,
703 /* 648 */ 232, 0,
704 /* 650 */ 233, 0,
705 /* 652 */ 251, 0,
706 /* 654 */ 252, 0,
707 /* 656 */ 253, 0,
708 /* 658 */ 260, 0,
709 /* 660 */ 261, 0,
710 /* 662 */ 262, 0,
711 /* 664 */ 263, 0,
712 /* 666 */ 264, 0,
713 /* 668 */ 265, 0,
714 /* 670 */ 266, 0,
715 /* 672 */ 267, 0,
716 /* 674 */ 268, 0,
717 /* 676 */ 269, 0,
718 /* 678 */ 270, 0,
719 /* 680 */ 271, 0,
720 /* 682 */ 273, 0,
721 /* 684 */ 283, 0,
722 /* 686 */ 284, 0,
723 /* 688 */ 303, 0,
724 /* 690 */ 311, 0,
725 /* 692 */ 312, 0,
726 /* 694 */ 314, 0,
727 /* 696 */ 322, 0,
728 /* 698 */ 324, 0,
729 /* 700 */ 326, 0,
730 /* 702 */ 327, 0,
731 /* 704 */ 331, 0,
732 /* 706 */ 332, 0,
733 /* 708 */ 339, 0,
734 /* 710 */ 340, 0,
735 /* 712 */ 342, 0,
736 /* 714 */ 345, 0,
737 /* 716 */ 346, 0,
738 /* 718 */ 347, 0,
739 /* 720 */ 351, 0,
740 /* 722 */ 352, 0,
741 /* 724 */ 353, 0,
742 /* 726 */ 356, 0,
743 /* 728 */ 357, 0,
744 /* 730 */ 358, 0,
745 /* 732 */ 359, 0,
746 /* 734 */ 360, 0,
747 /* 736 */ 366, 0,
748 /* 738 */ 367, 0,
749};
750
751extern const LaneBitmask HexagonLaneMaskLists[] = {
752 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
753 /* 3 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask::getAll(),
754 /* 6 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), LaneBitmask::getAll(),
755 /* 12 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
756 /* 16 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),
757 /* 23 */ LaneBitmask(0x0000000000000004), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
758 /* 26 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
759};
760
761extern const uint16_t HexagonSubRegIdxLists[] = {
762 /* 0 */ 2, 1, 0,
763 /* 3 */ 3, 0,
764 /* 5 */ 6, 5, 4, 0,
765 /* 9 */ 8, 6, 5, 4, 7, 11, 10, 9, 0,
766};
767
768
769#ifdef __GNUC__
770#pragma GCC diagnostic push
771#pragma GCC diagnostic ignored "-Woverlength-strings"
772#endif
773extern const char HexagonRegStrings[] = {
774 /* 0 */ "D10\0"
775 /* 4 */ "VF10\0"
776 /* 9 */ "G10\0"
777 /* 13 */ "VFR10\0"
778 /* 19 */ "WR10\0"
779 /* 24 */ "V10\0"
780 /* 28 */ "W10\0"
781 /* 32 */ "C11_10\0"
782 /* 39 */ "G11_10\0"
783 /* 46 */ "S11_10\0"
784 /* 53 */ "VF20\0"
785 /* 58 */ "G20\0"
786 /* 62 */ "VFR20\0"
787 /* 68 */ "S20\0"
788 /* 72 */ "V20\0"
789 /* 76 */ "G21_20\0"
790 /* 83 */ "S21_20\0"
791 /* 90 */ "VF30\0"
792 /* 95 */ "G30\0"
793 /* 99 */ "VFR30\0"
794 /* 105 */ "V30\0"
795 /* 109 */ "G31_30\0"
796 /* 116 */ "S31_30\0"
797 /* 123 */ "S41_40\0"
798 /* 130 */ "S51_50\0"
799 /* 137 */ "S60\0"
800 /* 141 */ "S61_60\0"
801 /* 148 */ "S70\0"
802 /* 152 */ "S71_70\0"
803 /* 159 */ "S80\0"
804 /* 163 */ "SA0\0"
805 /* 167 */ "BADVA0\0"
806 /* 174 */ "LC0\0"
807 /* 178 */ "BRKPTPC0\0"
808 /* 187 */ "D0\0"
809 /* 190 */ "VF0\0"
810 /* 194 */ "ISDBCFG0\0"
811 /* 203 */ "BRKPTCFG0\0"
812 /* 213 */ "M0\0"
813 /* 216 */ "SGP0\0"
814 /* 221 */ "VQ0\0"
815 /* 225 */ "VFR0\0"
816 /* 230 */ "WR0\0"
817 /* 234 */ "CS0\0"
818 /* 238 */ "GPMUCNT0\0"
819 /* 247 */ "V0\0"
820 /* 250 */ "W0\0"
821 /* 253 */ "C1_0\0"
822 /* 258 */ "G1_0\0"
823 /* 263 */ "SGP1_0\0"
824 /* 270 */ "P3_0\0"
825 /* 275 */ "D11\0"
826 /* 279 */ "VF11\0"
827 /* 284 */ "G11\0"
828 /* 288 */ "VFR11\0"
829 /* 294 */ "WR11\0"
830 /* 299 */ "S11\0"
831 /* 303 */ "V11\0"
832 /* 307 */ "W11\0"
833 /* 311 */ "VF21\0"
834 /* 316 */ "G21\0"
835 /* 320 */ "VFR21\0"
836 /* 326 */ "V21\0"
837 /* 330 */ "VF31\0"
838 /* 335 */ "G31\0"
839 /* 339 */ "VFR31\0"
840 /* 345 */ "V31\0"
841 /* 349 */ "S61\0"
842 /* 353 */ "S71\0"
843 /* 357 */ "SA1\0"
844 /* 361 */ "BADVA1\0"
845 /* 368 */ "LC1\0"
846 /* 372 */ "BRKPTPC1\0"
847 /* 381 */ "D1\0"
848 /* 384 */ "VF1\0"
849 /* 388 */ "ISDBCFG1\0"
850 /* 397 */ "BRKPTCFG1\0"
851 /* 407 */ "M1\0"
852 /* 410 */ "SGP1\0"
853 /* 415 */ "VQ1\0"
854 /* 419 */ "VFR1\0"
855 /* 424 */ "WR1\0"
856 /* 428 */ "CS1\0"
857 /* 432 */ "GPMUCNT1\0"
858 /* 441 */ "V1\0"
859 /* 444 */ "W1\0"
860 /* 447 */ "D12\0"
861 /* 451 */ "VF12\0"
862 /* 456 */ "G12\0"
863 /* 460 */ "VFR12\0"
864 /* 466 */ "WR12\0"
865 /* 471 */ "S12\0"
866 /* 475 */ "V12\0"
867 /* 479 */ "W12\0"
868 /* 483 */ "G13_12\0"
869 /* 490 */ "S13_12\0"
870 /* 497 */ "VF22\0"
871 /* 502 */ "G22\0"
872 /* 506 */ "VFR22\0"
873 /* 512 */ "S22\0"
874 /* 516 */ "V22\0"
875 /* 520 */ "G23_22\0"
876 /* 527 */ "S23_22\0"
877 /* 534 */ "S33_32\0"
878 /* 541 */ "S43_42\0"
879 /* 548 */ "S53_52\0"
880 /* 555 */ "S62\0"
881 /* 559 */ "S63_62\0"
882 /* 566 */ "S72\0"
883 /* 570 */ "S73_72\0"
884 /* 577 */ "D2\0"
885 /* 580 */ "VF2\0"
886 /* 584 */ "P2\0"
887 /* 587 */ "VQ2\0"
888 /* 591 */ "VFR2\0"
889 /* 596 */ "WR2\0"
890 /* 600 */ "GPMUCNT2\0"
891 /* 609 */ "V2\0"
892 /* 612 */ "W2\0"
893 /* 615 */ "C3_2\0"
894 /* 620 */ "G3_2\0"
895 /* 625 */ "S3_2\0"
896 /* 630 */ "D13\0"
897 /* 634 */ "VF13\0"
898 /* 639 */ "G13\0"
899 /* 643 */ "VFR13\0"
900 /* 649 */ "WR13\0"
901 /* 654 */ "S13\0"
902 /* 658 */ "V13\0"
903 /* 662 */ "W13\0"
904 /* 666 */ "VF23\0"
905 /* 671 */ "G23\0"
906 /* 675 */ "VFR23\0"
907 /* 681 */ "S23\0"
908 /* 685 */ "V23\0"
909 /* 689 */ "S63\0"
910 /* 693 */ "S73\0"
911 /* 697 */ "D3\0"
912 /* 700 */ "VF3\0"
913 /* 704 */ "G3\0"
914 /* 707 */ "P3\0"
915 /* 710 */ "VQ3\0"
916 /* 714 */ "VFR3\0"
917 /* 719 */ "WR3\0"
918 /* 723 */ "GPMUCNT3\0"
919 /* 732 */ "V3\0"
920 /* 735 */ "W3\0"
921 /* 738 */ "D14\0"
922 /* 742 */ "VF14\0"
923 /* 747 */ "G14\0"
924 /* 751 */ "VFR14\0"
925 /* 757 */ "WR14\0"
926 /* 762 */ "S14\0"
927 /* 766 */ "V14\0"
928 /* 770 */ "W14\0"
929 /* 774 */ "G15_14\0"
930 /* 781 */ "S15_14\0"
931 /* 788 */ "VF24\0"
932 /* 793 */ "VFR24\0"
933 /* 799 */ "S24\0"
934 /* 803 */ "V24\0"
935 /* 807 */ "G25_24\0"
936 /* 814 */ "S25_24\0"
937 /* 821 */ "S35_34\0"
938 /* 828 */ "S44\0"
939 /* 832 */ "S45_44\0"
940 /* 839 */ "S54\0"
941 /* 843 */ "S55_54\0"
942 /* 850 */ "S64\0"
943 /* 854 */ "S65_64\0"
944 /* 861 */ "S74\0"
945 /* 865 */ "S75_74\0"
946 /* 872 */ "D4\0"
947 /* 875 */ "VF4\0"
948 /* 879 */ "G4\0"
949 /* 882 */ "VQ4\0"
950 /* 886 */ "VFR4\0"
951 /* 891 */ "WR4\0"
952 /* 895 */ "GPMUCNT4\0"
953 /* 904 */ "V4\0"
954 /* 907 */ "W4\0"
955 /* 910 */ "C5_4\0"
956 /* 915 */ "G5_4\0"
957 /* 920 */ "S5_4\0"
958 /* 925 */ "D15\0"
959 /* 929 */ "VF15\0"
960 /* 934 */ "G15\0"
961 /* 938 */ "VFR15\0"
962 /* 944 */ "WR15\0"
963 /* 949 */ "S15\0"
964 /* 953 */ "V15\0"
965 /* 957 */ "W15\0"
966 /* 961 */ "VF25\0"
967 /* 966 */ "VFR25\0"
968 /* 972 */ "S25\0"
969 /* 976 */ "V25\0"
970 /* 980 */ "S35\0"
971 /* 984 */ "S45\0"
972 /* 988 */ "S55\0"
973 /* 992 */ "S65\0"
974 /* 996 */ "S75\0"
975 /* 1000 */ "C5\0"
976 /* 1003 */ "D5\0"
977 /* 1006 */ "VF5\0"
978 /* 1010 */ "G5\0"
979 /* 1013 */ "VQ5\0"
980 /* 1017 */ "VFR5\0"
981 /* 1022 */ "WR5\0"
982 /* 1026 */ "GPMUCNT5\0"
983 /* 1035 */ "V5\0"
984 /* 1038 */ "W5\0"
985 /* 1041 */ "VF16\0"
986 /* 1046 */ "VFR16\0"
987 /* 1052 */ "V16\0"
988 /* 1056 */ "C17_16\0"
989 /* 1063 */ "G17_16\0"
990 /* 1070 */ "S17_16\0"
991 /* 1077 */ "VF26\0"
992 /* 1082 */ "VFR26\0"
993 /* 1088 */ "S26\0"
994 /* 1092 */ "V26\0"
995 /* 1096 */ "G27_26\0"
996 /* 1103 */ "S27_26\0"
997 /* 1110 */ "S37_36\0"
998 /* 1117 */ "S46\0"
999 /* 1121 */ "S47_46\0"
1000 /* 1128 */ "S56\0"
1001 /* 1132 */ "S57_56\0"
1002 /* 1139 */ "S66\0"
1003 /* 1143 */ "S67_66\0"
1004 /* 1150 */ "S76\0"
1005 /* 1154 */ "S77_76\0"
1006 /* 1161 */ "D6\0"
1007 /* 1164 */ "VF6\0"
1008 /* 1168 */ "G6\0"
1009 /* 1171 */ "VQ6\0"
1010 /* 1175 */ "VFR6\0"
1011 /* 1180 */ "WR6\0"
1012 /* 1184 */ "GPMUCNT6\0"
1013 /* 1193 */ "V6\0"
1014 /* 1196 */ "W6\0"
1015 /* 1199 */ "C7_6\0"
1016 /* 1204 */ "G7_6\0"
1017 /* 1209 */ "S7_6\0"
1018 /* 1214 */ "VF17\0"
1019 /* 1219 */ "VFR17\0"
1020 /* 1225 */ "V17\0"
1021 /* 1229 */ "VF27\0"
1022 /* 1234 */ "VFR27\0"
1023 /* 1240 */ "V27\0"
1024 /* 1244 */ "S47\0"
1025 /* 1248 */ "S57\0"
1026 /* 1252 */ "S67\0"
1027 /* 1256 */ "S77\0"
1028 /* 1260 */ "D7\0"
1029 /* 1263 */ "VF7\0"
1030 /* 1267 */ "G7\0"
1031 /* 1270 */ "VQ7\0"
1032 /* 1274 */ "VFR7\0"
1033 /* 1279 */ "WR7\0"
1034 /* 1283 */ "GPMUCNT7\0"
1035 /* 1292 */ "V7\0"
1036 /* 1295 */ "W7\0"
1037 /* 1298 */ "VF18\0"
1038 /* 1303 */ "VFR18\0"
1039 /* 1309 */ "V18\0"
1040 /* 1313 */ "G19_18\0"
1041 /* 1320 */ "S19_18\0"
1042 /* 1327 */ "VF28\0"
1043 /* 1332 */ "VFR28\0"
1044 /* 1338 */ "V28\0"
1045 /* 1342 */ "G29_28\0"
1046 /* 1349 */ "S29_28\0"
1047 /* 1356 */ "S39_38\0"
1048 /* 1363 */ "S49_48\0"
1049 /* 1370 */ "S58\0"
1050 /* 1374 */ "S59_58\0"
1051 /* 1381 */ "S68\0"
1052 /* 1385 */ "S69_68\0"
1053 /* 1392 */ "S78\0"
1054 /* 1396 */ "S79_78\0"
1055 /* 1403 */ "C8\0"
1056 /* 1406 */ "D8\0"
1057 /* 1409 */ "VF8\0"
1058 /* 1413 */ "G8\0"
1059 /* 1416 */ "VFR8\0"
1060 /* 1421 */ "WR8\0"
1061 /* 1425 */ "V8\0"
1062 /* 1428 */ "W8\0"
1063 /* 1431 */ "C9_8\0"
1064 /* 1436 */ "G9_8\0"
1065 /* 1441 */ "S9_8\0"
1066 /* 1446 */ "VF19\0"
1067 /* 1451 */ "VFR19\0"
1068 /* 1457 */ "S19\0"
1069 /* 1461 */ "V19\0"
1070 /* 1465 */ "VF29\0"
1071 /* 1470 */ "VFR29\0"
1072 /* 1476 */ "V29\0"
1073 /* 1480 */ "S59\0"
1074 /* 1484 */ "S69\0"
1075 /* 1488 */ "S79\0"
1076 /* 1492 */ "D9\0"
1077 /* 1495 */ "VF9\0"
1078 /* 1499 */ "G9\0"
1079 /* 1502 */ "VFR9\0"
1080 /* 1507 */ "WR9\0"
1081 /* 1511 */ "V9\0"
1082 /* 1514 */ "W9\0"
1083 /* 1517 */ "BADVA\0"
1084 /* 1523 */ "EVB\0"
1085 /* 1527 */ "PC\0"
1086 /* 1530 */ "HTID\0"
1087 /* 1535 */ "STID\0"
1088 /* 1540 */ "VID\0"
1089 /* 1544 */ "UPCYCLE\0"
1090 /* 1552 */ "CFGBASE\0"
1091 /* 1560 */ "USR_OVF\0"
1092 /* 1568 */ "DIAG\0"
1093 /* 1573 */ "SYSCFG\0"
1094 /* 1580 */ "PMUEVTCFG\0"
1095 /* 1590 */ "PMUCFG\0"
1096 /* 1597 */ "GPCYCLEHI\0"
1097 /* 1607 */ "UPCYCLEHI\0"
1098 /* 1617 */ "UTIMERHI\0"
1099 /* 1626 */ "PKTCOUNTHI\0"
1100 /* 1637 */ "IMASK\0"
1101 /* 1643 */ "MODECTL\0"
1102 /* 1651 */ "ISDBEN\0"
1103 /* 1658 */ "ISDBMBXIN\0"
1104 /* 1668 */ "GPCYCLELO\0"
1105 /* 1678 */ "UPCYCLELO\0"
1106 /* 1688 */ "UTIMERLO\0"
1107 /* 1697 */ "PKTCOUNTLO\0"
1108 /* 1708 */ "UGP\0"
1109 /* 1712 */ "VTMP\0"
1110 /* 1717 */ "GOSP\0"
1111 /* 1722 */ "CCR\0"
1112 /* 1726 */ "UTIMER\0"
1113 /* 1733 */ "GELR\0"
1114 /* 1738 */ "ISDBGPR\0"
1115 /* 1746 */ "GSR\0"
1116 /* 1750 */ "SSR\0"
1117 /* 1754 */ "USR\0"
1118 /* 1758 */ "CS\0"
1119 /* 1761 */ "FRAMELIMIT\0"
1120 /* 1772 */ "PKTCOUNT\0"
1121 /* 1781 */ "ISDBST\0"
1122 /* 1788 */ "ISDBMBXOUT\0"
1123 /* 1799 */ "REV\0"
1124 /* 1803 */ "FRAMEKEY\0"
1125};
1126#ifdef __GNUC__
1127#pragma GCC diagnostic pop
1128#endif
1129
1130extern const MCRegisterDesc HexagonRegDesc[] = { // Descriptors
1131 { 3, 0, 0, 0, 0, 0, 0 },
1132 { 1517, 2, 734, 2, 8192, 24, 0 },
1133 { 1722, 2, 730, 2, 8193, 24, 0 },
1134 { 1552, 2, 738, 2, 8194, 24, 0 },
1135 { 1758, 255, 2, 0, 487427, 0, 0 },
1136 { 1568, 2, 736, 2, 8197, 24, 0 },
1137 { 1734, 2, 722, 2, 8198, 24, 0 },
1138 { 1523, 2, 730, 2, 8199, 24, 0 },
1139 { 1803, 2, 706, 2, 8200, 24, 0 },
1140 { 1761, 2, 704, 2, 8201, 24, 0 },
1141 { 1733, 2, 704, 2, 8202, 24, 0 },
1142 { 1717, 2, 704, 2, 8203, 24, 0 },
1143 { 1709, 2, 702, 2, 8204, 24, 0 },
1144 { 1597, 2, 710, 2, 8205, 24, 0 },
1145 { 1668, 2, 708, 2, 8206, 24, 0 },
1146 { 1746, 2, 700, 2, 8207, 24, 0 },
1147 { 1530, 2, 714, 2, 8208, 24, 0 },
1148 { 1637, 2, 714, 2, 8209, 24, 0 },
1149 { 1651, 2, 734, 2, 8210, 24, 0 },
1150 { 1738, 2, 732, 2, 8211, 24, 0 },
1151 { 1658, 2, 728, 2, 8212, 24, 0 },
1152 { 1788, 2, 726, 2, 8213, 24, 0 },
1153 { 1781, 2, 720, 2, 8214, 24, 0 },
1154 { 1643, 2, 712, 2, 8215, 24, 0 },
1155 { 1527, 2, 694, 2, 8216, 24, 0 },
1156 { 1598, 2, 718, 2, 8217, 24, 0 },
1157 { 1669, 2, 716, 2, 8218, 24, 0 },
1158 { 1772, 115, 2, 0, 487451, 0, 0 },
1159 { 1626, 2, 98, 2, 8220, 24, 0 },
1160 { 1697, 2, 95, 2, 8219, 24, 0 },
1161 { 1590, 2, 724, 2, 8221, 24, 0 },
1162 { 1580, 2, 722, 2, 8222, 24, 0 },
1163 { 1799, 2, 708, 2, 8223, 24, 0 },
1164 { 1750, 2, 702, 2, 8224, 24, 0 },
1165 { 1535, 2, 698, 2, 8225, 24, 0 },
1166 { 1573, 2, 704, 2, 8226, 24, 0 },
1167 { 1708, 2, 688, 2, 8227, 24, 0 },
1168 { 1544, 115, 2, 0, 487460, 0, 0 },
1169 { 1607, 2, 98, 2, 8229, 24, 0 },
1170 { 1678, 2, 95, 2, 8228, 24, 0 },
1171 { 1754, 119, 2, 3, 487462, 23, 0 },
1172 { 1560, 2, 98, 2, 8230, 24, 0 },
1173 { 1726, 115, 2, 0, 487464, 0, 0 },
1174 { 1617, 2, 98, 2, 8233, 24, 0 },
1175 { 1688, 2, 95, 2, 8232, 24, 0 },
1176 { 1540, 2, 696, 2, 8234, 24, 0 },
1177 { 1712, 2, 2, 2, 8235, 24, 0 },
1178 { 167, 2, 692, 2, 8236, 24, 0 },
1179 { 361, 2, 690, 2, 8237, 24, 0 },
1180 { 203, 2, 700, 2, 8238, 24, 0 },
1181 { 397, 2, 700, 2, 8239, 24, 0 },
1182 { 178, 2, 698, 2, 8240, 24, 0 },
1183 { 372, 2, 698, 2, 8241, 24, 0 },
1184 { 1000, 2, 684, 2, 8242, 24, 0 },
1185 { 1403, 2, 686, 2, 8231, 24, 0 },
1186 { 234, 2, 48, 2, 8195, 24, 0 },
1187 { 428, 2, 46, 2, 8196, 24, 0 },
1188 { 187, 258, 2, 0, 487475, 0, 0 },
1189 { 381, 261, 2, 0, 487477, 0, 0 },
1190 { 577, 264, 2, 0, 487479, 0, 0 },
1191 { 697, 267, 2, 0, 487481, 0, 0 },
1192 { 872, 270, 2, 0, 487483, 0, 0 },
1193 { 1003, 273, 2, 0, 487485, 0, 0 },
1194 { 1161, 276, 2, 0, 487487, 0, 0 },
1195 { 1260, 279, 2, 0, 487489, 0, 0 },
1196 { 1406, 282, 2, 0, 487491, 0, 0 },
1197 { 1492, 285, 2, 0, 487493, 0, 0 },
1198 { 0, 288, 2, 0, 487495, 0, 0 },
1199 { 275, 291, 2, 0, 487497, 0, 0 },
1200 { 447, 294, 2, 0, 487499, 0, 0 },
1201 { 630, 297, 2, 0, 487501, 0, 0 },
1202 { 738, 300, 2, 0, 487503, 0, 0 },
1203 { 925, 303, 2, 0, 487505, 0, 0 },
1204 { 704, 2, 676, 2, 8275, 24, 0 },
1205 { 879, 2, 676, 2, 8276, 24, 0 },
1206 { 1010, 2, 674, 2, 8277, 24, 0 },
1207 { 1168, 2, 674, 2, 8278, 24, 0 },
1208 { 1267, 2, 672, 2, 8279, 24, 0 },
1209 { 1413, 2, 672, 2, 8280, 24, 0 },
1210 { 1499, 2, 670, 2, 8281, 24, 0 },
1211 { 9, 2, 670, 2, 8282, 24, 0 },
1212 { 284, 2, 668, 2, 8283, 24, 0 },
1213 { 456, 2, 668, 2, 8284, 24, 0 },
1214 { 639, 2, 666, 2, 8285, 24, 0 },
1215 { 747, 2, 666, 2, 8286, 24, 0 },
1216 { 934, 2, 664, 2, 8287, 24, 0 },
1217 { 58, 2, 668, 2, 8288, 24, 0 },
1218 { 316, 2, 666, 2, 8289, 24, 0 },
1219 { 502, 2, 666, 2, 8290, 24, 0 },
1220 { 671, 2, 664, 2, 8291, 24, 0 },
1221 { 95, 2, 670, 2, 8292, 24, 0 },
1222 { 335, 2, 668, 2, 8293, 24, 0 },
1223 { 238, 2, 662, 2, 8294, 24, 0 },
1224 { 432, 2, 660, 2, 8295, 24, 0 },
1225 { 600, 2, 660, 2, 8296, 24, 0 },
1226 { 723, 2, 658, 2, 8297, 24, 0 },
1227 { 895, 2, 656, 2, 8298, 24, 0 },
1228 { 1026, 2, 654, 2, 8299, 24, 0 },
1229 { 1184, 2, 654, 2, 8300, 24, 0 },
1230 { 1283, 2, 652, 2, 8301, 24, 0 },
1231 { 194, 2, 682, 2, 8302, 24, 0 },
1232 { 388, 2, 682, 2, 8303, 24, 0 },
1233 { 174, 2, 648, 2, 8304, 24, 0 },
1234 { 368, 2, 648, 2, 8305, 24, 0 },
1235 { 213, 2, 650, 2, 8306, 24, 0 },
1236 { 407, 2, 648, 2, 8307, 24, 0 },
1237 { 218, 2, 2, 2, 8308, 24, 0 },
1238 { 412, 2, 2, 2, 8309, 24, 0 },
1239 { 584, 2, 2, 2, 8310, 24, 0 },
1240 { 707, 2, 2, 2, 8311, 24, 0 },
1241 { 239, 2, 680, 2, 8312, 24, 0 },
1242 { 433, 2, 678, 2, 8313, 24, 0 },
1243 { 601, 2, 678, 2, 8314, 24, 0 },
1244 { 724, 2, 676, 2, 8315, 24, 0 },
1245 { 222, 2, 2, 2, 8316, 24, 0 },
1246 { 416, 2, 2, 2, 8317, 24, 0 },
1247 { 588, 2, 2, 2, 8318, 24, 0 },
1248 { 711, 2, 2, 2, 8319, 24, 0 },
1249 { 227, 2, 44, 2, 8243, 24, 0 },
1250 { 421, 2, 42, 2, 8244, 24, 0 },
1251 { 593, 2, 42, 2, 8245, 24, 0 },
1252 { 716, 2, 40, 2, 8246, 24, 0 },
1253 { 888, 2, 40, 2, 8247, 24, 0 },
1254 { 1019, 2, 38, 2, 8248, 24, 0 },
1255 { 1177, 2, 38, 2, 8249, 24, 0 },
1256 { 1276, 2, 36, 2, 8250, 24, 0 },
1257 { 1418, 2, 36, 2, 8251, 24, 0 },
1258 { 1504, 2, 34, 2, 8252, 24, 0 },
1259 { 15, 2, 34, 2, 8253, 24, 0 },
1260 { 290, 2, 32, 2, 8254, 24, 0 },
1261 { 462, 2, 32, 2, 8255, 24, 0 },
1262 { 645, 2, 30, 2, 8256, 24, 0 },
1263 { 753, 2, 30, 2, 8257, 24, 0 },
1264 { 940, 2, 28, 2, 8258, 24, 0 },
1265 { 1048, 2, 28, 2, 8259, 24, 0 },
1266 { 1221, 2, 26, 2, 8260, 24, 0 },
1267 { 1305, 2, 26, 2, 8261, 24, 0 },
1268 { 1453, 2, 24, 2, 8262, 24, 0 },
1269 { 64, 2, 24, 2, 8263, 24, 0 },
1270 { 322, 2, 22, 2, 8264, 24, 0 },
1271 { 508, 2, 22, 2, 8265, 24, 0 },
1272 { 677, 2, 20, 2, 8266, 24, 0 },
1273 { 795, 2, 20, 2, 8267, 24, 0 },
1274 { 968, 2, 18, 2, 8268, 24, 0 },
1275 { 1084, 2, 18, 2, 8269, 24, 0 },
1276 { 1236, 2, 16, 2, 8270, 24, 0 },
1277 { 1334, 2, 16, 2, 8271, 24, 0 },
1278 { 1472, 2, 14, 2, 8272, 24, 0 },
1279 { 101, 2, 14, 2, 8273, 24, 0 },
1280 { 341, 2, 12, 2, 8274, 24, 0 },
1281 { 299, 2, 636, 2, 8320, 24, 0 },
1282 { 471, 2, 636, 2, 8321, 24, 0 },
1283 { 654, 2, 634, 2, 8322, 24, 0 },
1284 { 762, 2, 634, 2, 8323, 24, 0 },
1285 { 949, 2, 632, 2, 8324, 24, 0 },
1286 { 1457, 2, 634, 2, 8325, 24, 0 },
1287 { 68, 2, 634, 2, 8326, 24, 0 },
1288 { 512, 2, 634, 2, 8327, 24, 0 },
1289 { 681, 2, 632, 2, 8328, 24, 0 },
1290 { 799, 2, 632, 2, 8329, 24, 0 },
1291 { 972, 2, 630, 2, 8330, 24, 0 },
1292 { 1088, 2, 630, 2, 8331, 24, 0 },
1293 { 980, 2, 636, 2, 8332, 24, 0 },
1294 { 828, 2, 644, 2, 8333, 24, 0 },
1295 { 984, 2, 642, 2, 8334, 24, 0 },
1296 { 1117, 2, 642, 2, 8335, 24, 0 },
1297 { 1244, 2, 640, 2, 8336, 24, 0 },
1298 { 839, 2, 646, 2, 8337, 24, 0 },
1299 { 988, 2, 644, 2, 8338, 24, 0 },
1300 { 1128, 2, 644, 2, 8339, 24, 0 },
1301 { 1248, 2, 642, 2, 8340, 24, 0 },
1302 { 1370, 2, 642, 2, 8341, 24, 0 },
1303 { 1480, 2, 640, 2, 8342, 24, 0 },
1304 { 137, 2, 640, 2, 8343, 24, 0 },
1305 { 349, 2, 638, 2, 8344, 24, 0 },
1306 { 555, 2, 638, 2, 8345, 24, 0 },
1307 { 689, 2, 636, 2, 8346, 24, 0 },
1308 { 850, 2, 636, 2, 8347, 24, 0 },
1309 { 992, 2, 634, 2, 8348, 24, 0 },
1310 { 1139, 2, 634, 2, 8349, 24, 0 },
1311 { 1252, 2, 632, 2, 8350, 24, 0 },
1312 { 1381, 2, 632, 2, 8351, 24, 0 },
1313 { 1484, 2, 630, 2, 8352, 24, 0 },
1314 { 148, 2, 630, 2, 8353, 24, 0 },
1315 { 353, 2, 628, 2, 8354, 24, 0 },
1316 { 566, 2, 628, 2, 8355, 24, 0 },
1317 { 693, 2, 626, 2, 8356, 24, 0 },
1318 { 861, 2, 626, 2, 8357, 24, 0 },
1319 { 996, 2, 624, 2, 8358, 24, 0 },
1320 { 1150, 2, 624, 2, 8359, 24, 0 },
1321 { 1256, 2, 622, 2, 8360, 24, 0 },
1322 { 1392, 2, 622, 2, 8361, 24, 0 },
1323 { 1488, 2, 620, 2, 8362, 24, 0 },
1324 { 159, 2, 2, 2, 8363, 24, 0 },
1325 { 163, 2, 614, 2, 8364, 24, 0 },
1326 { 357, 2, 614, 2, 8365, 24, 0 },
1327 { 216, 2, 618, 2, 8366, 24, 0 },
1328 { 410, 2, 616, 2, 8367, 24, 0 },
1329 { 247, 2, 372, 2, 8368, 24, 0 },
1330 { 441, 2, 368, 2, 8369, 24, 0 },
1331 { 609, 2, 393, 2, 8370, 24, 0 },
1332 { 732, 2, 389, 2, 8371, 24, 0 },
1333 { 904, 2, 389, 2, 8372, 24, 0 },
1334 { 1035, 2, 385, 2, 8373, 24, 0 },
1335 { 1193, 2, 409, 2, 8374, 24, 0 },
1336 { 1292, 2, 405, 2, 8375, 24, 0 },
1337 { 1425, 2, 405, 2, 8376, 24, 0 },
1338 { 1511, 2, 401, 2, 8377, 24, 0 },
1339 { 24, 2, 433, 2, 8378, 24, 0 },
1340 { 303, 2, 429, 2, 8379, 24, 0 },
1341 { 475, 2, 429, 2, 8380, 24, 0 },
1342 { 658, 2, 425, 2, 8381, 24, 0 },
1343 { 766, 2, 449, 2, 8382, 24, 0 },
1344 { 953, 2, 445, 2, 8383, 24, 0 },
1345 { 1052, 2, 445, 2, 8384, 24, 0 },
1346 { 1225, 2, 441, 2, 8385, 24, 0 },
1347 { 1309, 2, 470, 2, 8386, 24, 0 },
1348 { 1461, 2, 466, 2, 8387, 24, 0 },
1349 { 72, 2, 466, 2, 8388, 24, 0 },
1350 { 326, 2, 462, 2, 8389, 24, 0 },
1351 { 516, 2, 486, 2, 8390, 24, 0 },
1352 { 685, 2, 482, 2, 8391, 24, 0 },
1353 { 803, 2, 482, 2, 8392, 24, 0 },
1354 { 976, 2, 478, 2, 8393, 24, 0 },
1355 { 1092, 2, 507, 2, 8394, 24, 0 },
1356 { 1240, 2, 503, 2, 8395, 24, 0 },
1357 { 1338, 2, 503, 2, 8396, 24, 0 },
1358 { 1476, 2, 499, 2, 8397, 24, 0 },
1359 { 105, 2, 519, 2, 8398, 24, 0 },
1360 { 345, 2, 515, 2, 8399, 24, 0 },
1361 { 190, 2, 91, 2, 8400, 24, 0 },
1362 { 384, 2, 88, 2, 8401, 24, 0 },
1363 { 580, 2, 88, 2, 8402, 24, 0 },
1364 { 700, 2, 85, 2, 8403, 24, 0 },
1365 { 875, 2, 85, 2, 8404, 24, 0 },
1366 { 1006, 2, 82, 2, 8405, 24, 0 },
1367 { 1164, 2, 82, 2, 8406, 24, 0 },
1368 { 1263, 2, 79, 2, 8407, 24, 0 },
1369 { 1409, 2, 79, 2, 8408, 24, 0 },
1370 { 1495, 2, 76, 2, 8409, 24, 0 },
1371 { 4, 2, 76, 2, 8410, 24, 0 },
1372 { 279, 2, 73, 2, 8411, 24, 0 },
1373 { 451, 2, 73, 2, 8412, 24, 0 },
1374 { 634, 2, 70, 2, 8413, 24, 0 },
1375 { 742, 2, 70, 2, 8414, 24, 0 },
1376 { 929, 2, 64, 2, 8415, 24, 0 },
1377 { 1041, 2, 2, 2, 8416, 24, 0 },
1378 { 1214, 2, 2, 2, 8417, 24, 0 },
1379 { 1298, 2, 2, 2, 8418, 24, 0 },
1380 { 1446, 2, 2, 2, 8419, 24, 0 },
1381 { 53, 2, 2, 2, 8420, 24, 0 },
1382 { 311, 2, 2, 2, 8421, 24, 0 },
1383 { 497, 2, 2, 2, 8422, 24, 0 },
1384 { 666, 2, 2, 2, 8423, 24, 0 },
1385 { 788, 2, 2, 2, 8424, 24, 0 },
1386 { 961, 2, 2, 2, 8425, 24, 0 },
1387 { 1077, 2, 2, 2, 8426, 24, 0 },
1388 { 1229, 2, 2, 2, 8427, 24, 0 },
1389 { 1327, 2, 2, 2, 8428, 24, 0 },
1390 { 1465, 2, 2, 2, 8429, 24, 0 },
1391 { 90, 2, 2, 2, 8430, 24, 0 },
1392 { 330, 2, 2, 2, 8431, 24, 0 },
1393 { 225, 2, 557, 2, 8432, 24, 0 },
1394 { 419, 2, 557, 2, 8433, 24, 0 },
1395 { 591, 2, 557, 2, 8434, 24, 0 },
1396 { 714, 2, 557, 2, 8435, 24, 0 },
1397 { 886, 2, 557, 2, 8436, 24, 0 },
1398 { 1017, 2, 557, 2, 8437, 24, 0 },
1399 { 1175, 2, 557, 2, 8438, 24, 0 },
1400 { 1274, 2, 557, 2, 8439, 24, 0 },
1401 { 1416, 2, 557, 2, 8440, 24, 0 },
1402 { 1502, 2, 557, 2, 8441, 24, 0 },
1403 { 13, 2, 557, 2, 8442, 24, 0 },
1404 { 288, 2, 557, 2, 8443, 24, 0 },
1405 { 460, 2, 557, 2, 8444, 24, 0 },
1406 { 643, 2, 557, 2, 8445, 24, 0 },
1407 { 751, 2, 557, 2, 8446, 24, 0 },
1408 { 938, 2, 557, 2, 8447, 24, 0 },
1409 { 1046, 2, 2, 2, 8448, 24, 0 },
1410 { 1219, 2, 2, 2, 8449, 24, 0 },
1411 { 1303, 2, 2, 2, 8450, 24, 0 },
1412 { 1451, 2, 2, 2, 8451, 24, 0 },
1413 { 62, 2, 2, 2, 8452, 24, 0 },
1414 { 320, 2, 2, 2, 8453, 24, 0 },
1415 { 506, 2, 2, 2, 8454, 24, 0 },
1416 { 675, 2, 2, 2, 8455, 24, 0 },
1417 { 793, 2, 2, 2, 8456, 24, 0 },
1418 { 966, 2, 2, 2, 8457, 24, 0 },
1419 { 1082, 2, 2, 2, 8458, 24, 0 },
1420 { 1234, 2, 2, 2, 8459, 24, 0 },
1421 { 1332, 2, 2, 2, 8460, 24, 0 },
1422 { 1470, 2, 2, 2, 8461, 24, 0 },
1423 { 99, 2, 2, 2, 8462, 24, 0 },
1424 { 339, 2, 2, 2, 8463, 24, 0 },
1425 { 221, 490, 2, 9, 1020080, 16, 0 },
1426 { 415, 453, 2, 9, 995508, 16, 0 },
1427 { 587, 413, 2, 9, 970936, 16, 0 },
1428 { 710, 376, 2, 9, 946364, 16, 0 },
1429 { 882, 355, 2, 9, 921792, 16, 0 },
1430 { 1013, 342, 2, 9, 897220, 16, 0 },
1431 { 1171, 329, 2, 9, 872648, 16, 0 },
1432 { 1270, 316, 2, 9, 848076, 16, 0 },
1433 { 250, 511, 92, 5, 2097328, 12, 0 },
1434 { 444, 495, 89, 5, 2031794, 12, 0 },
1435 { 612, 474, 89, 5, 1945780, 12, 0 },
1436 { 735, 458, 86, 5, 1880246, 12, 0 },
1437 { 907, 437, 86, 5, 1794232, 12, 0 },
1438 { 1038, 418, 83, 5, 1716410, 12, 0 },
1439 { 1196, 397, 83, 5, 1630396, 12, 0 },
1440 { 1295, 381, 80, 5, 1564862, 12, 0 },
1441 { 1428, 364, 80, 5, 1495232, 12, 0 },
1442 { 1514, 360, 77, 5, 1478850, 12, 0 },
1443 { 28, 351, 77, 5, 1441988, 12, 0 },
1444 { 307, 347, 74, 5, 1425606, 12, 0 },
1445 { 479, 338, 74, 5, 1388744, 12, 0 },
1446 { 662, 334, 68, 5, 1372362, 12, 0 },
1447 { 770, 325, 68, 5, 1335500, 12, 0 },
1448 { 957, 321, 65, 5, 1319118, 12, 0 },
1449 { 230, 589, 2, 5, 2416816, 12, 0 },
1450 { 424, 585, 2, 5, 2400434, 12, 0 },
1451 { 596, 578, 2, 5, 2371764, 12, 0 },
1452 { 719, 571, 2, 5, 2343094, 12, 0 },
1453 { 891, 567, 2, 5, 2326712, 12, 0 },
1454 { 1022, 563, 2, 5, 2310330, 12, 0 },
1455 { 1180, 559, 2, 5, 2293948, 12, 0 },
1456 { 1279, 555, 2, 5, 2277566, 12, 0 },
1457 { 1421, 551, 2, 5, 2261184, 12, 0 },
1458 { 1507, 547, 2, 5, 2244802, 12, 0 },
1459 { 19, 543, 2, 5, 2228420, 12, 0 },
1460 { 294, 539, 2, 5, 2212038, 12, 0 },
1461 { 466, 535, 2, 5, 2195656, 12, 0 },
1462 { 649, 531, 2, 5, 2179274, 12, 0 },
1463 { 757, 527, 2, 5, 2162892, 12, 0 },
1464 { 944, 523, 2, 5, 2146510, 12, 0 },
1465 { 253, 9, 2, 0, 2347120, 3, 0 },
1466 { 615, 9, 2, 0, 2347121, 3, 0 },
1467 { 910, 0, 2, 0, 827442, 6, 0 },
1468 { 1199, 163, 2, 0, 487538, 0, 0 },
1469 { 1431, 53, 2, 0, 1273880, 3, 0 },
1470 { 32, 59, 2, 0, 1499148, 3, 0 },
1471 { 1056, 106, 2, 0, 487432, 3, 0 },
1472 { 258, 308, 2, 0, 1265674, 0, 0 },
1473 { 620, 582, 2, 0, 2428939, 0, 0 },
1474 { 915, 133, 2, 0, 487508, 0, 0 },
1475 { 1204, 136, 2, 0, 487510, 0, 0 },
1476 { 1436, 139, 2, 0, 487512, 0, 0 },
1477 { 39, 142, 2, 0, 487514, 0, 0 },
1478 { 483, 145, 2, 0, 487516, 0, 0 },
1479 { 774, 148, 2, 0, 487518, 0, 0 },
1480 { 1063, 157, 2, 0, 487530, 0, 0 },
1481 { 1313, 160, 2, 0, 487532, 0, 0 },
1482 { 76, 145, 2, 0, 487520, 0, 0 },
1483 { 520, 148, 2, 0, 487522, 0, 0 },
1484 { 807, 103, 2, 0, 487437, 3, 0 },
1485 { 1096, 151, 2, 0, 487526, 0, 0 },
1486 { 1342, 154, 2, 0, 487528, 0, 0 },
1487 { 109, 142, 2, 0, 487524, 0, 0 },
1488 { 270, 2, 62, 2, 831604, 26, 0 },
1489 { 625, 56, 2, 0, 1732614, 3, 0 },
1490 { 920, 124, 2, 0, 487468, 0, 0 },
1491 { 1209, 50, 2, 0, 2052097, 3, 0 },
1492 { 1441, 67, 2, 0, 1286144, 3, 0 },
1493 { 46, 609, 2, 0, 2474001, 0, 0 },
1494 { 490, 181, 2, 0, 487553, 0, 0 },
1495 { 781, 184, 2, 0, 487555, 0, 0 },
1496 { 1070, 313, 2, 0, 1286151, 0, 0 },
1497 { 1320, 606, 2, 0, 2465826, 0, 0 },
1498 { 83, 6, 2, 0, 2457642, 3, 0 },
1499 { 527, 184, 2, 0, 487559, 0, 0 },
1500 { 814, 187, 2, 0, 487561, 0, 0 },
1501 { 1103, 3, 2, 0, 2506754, 3, 0 },
1502 { 1349, 422, 2, 0, 1650693, 0, 0 },
1503 { 116, 100, 2, 0, 487449, 3, 0 },
1504 { 534, 595, 2, 0, 2449430, 0, 0 },
1505 { 821, 575, 2, 0, 1900655, 0, 0 },
1506 { 1110, 94, 2, 0, 1253422, 3, 0 },
1507 { 1356, 94, 2, 0, 1253423, 3, 0 },
1508 { 123, 121, 2, 0, 487444, 0, 0 },
1509 { 541, 118, 2, 0, 487442, 0, 0 },
1510 { 832, 169, 2, 0, 487565, 0, 0 },
1511 { 1121, 172, 2, 0, 487567, 0, 0 },
1512 { 1363, 127, 2, 0, 487544, 0, 0 },
1513 { 130, 130, 2, 0, 487546, 0, 0 },
1514 { 548, 97, 2, 0, 487453, 3, 0 },
1515 { 843, 166, 2, 0, 487569, 0, 0 },
1516 { 1132, 169, 2, 0, 487571, 0, 0 },
1517 { 1374, 172, 2, 0, 487573, 0, 0 },
1518 { 141, 175, 2, 0, 487575, 0, 0 },
1519 { 559, 178, 2, 0, 487577, 0, 0 },
1520 { 854, 181, 2, 0, 487579, 0, 0 },
1521 { 1143, 184, 2, 0, 487581, 0, 0 },
1522 { 1385, 187, 2, 0, 487583, 0, 0 },
1523 { 152, 190, 2, 0, 487585, 0, 0 },
1524 { 570, 193, 2, 0, 487587, 0, 0 },
1525 { 865, 196, 2, 0, 487589, 0, 0 },
1526 { 1154, 109, 2, 0, 487591, 3, 0 },
1527 { 1396, 112, 2, 0, 487593, 3, 0 },
1528 { 263, 199, 2, 0, 487598, 0, 0 },
1529};
1530
1531extern const MCPhysReg HexagonRegUnitRoots[][2] = {
1532 { Hexagon::BADVA },
1533 { Hexagon::CCR },
1534 { Hexagon::CFGBASE },
1535 { Hexagon::CS0 },
1536 { Hexagon::CS1 },
1537 { Hexagon::DIAG },
1538 { Hexagon::ELR },
1539 { Hexagon::EVB },
1540 { Hexagon::FRAMEKEY },
1541 { Hexagon::FRAMELIMIT },
1542 { Hexagon::GELR },
1543 { Hexagon::GOSP },
1544 { Hexagon::GP },
1545 { Hexagon::GPCYCLEHI },
1546 { Hexagon::GPCYCLELO },
1547 { Hexagon::GSR },
1548 { Hexagon::HTID },
1549 { Hexagon::IMASK },
1550 { Hexagon::ISDBEN },
1551 { Hexagon::ISDBGPR },
1552 { Hexagon::ISDBMBXIN },
1553 { Hexagon::ISDBMBXOUT },
1554 { Hexagon::ISDBST },
1555 { Hexagon::MODECTL },
1556 { Hexagon::PC },
1557 { Hexagon::PCYCLEHI },
1558 { Hexagon::PCYCLELO },
1559 { Hexagon::PKTCOUNTLO },
1560 { Hexagon::PKTCOUNTHI },
1561 { Hexagon::PMUCFG },
1562 { Hexagon::PMUEVTCFG },
1563 { Hexagon::REV },
1564 { Hexagon::SSR },
1565 { Hexagon::STID },
1566 { Hexagon::SYSCFG },
1567 { Hexagon::UGP },
1568 { Hexagon::UPCYCLELO },
1569 { Hexagon::UPCYCLEHI },
1570 { Hexagon::USR_OVF },
1571 { Hexagon::USR, Hexagon::C8 },
1572 { Hexagon::UTIMERLO },
1573 { Hexagon::UTIMERHI },
1574 { Hexagon::VID },
1575 { Hexagon::VTMP },
1576 { Hexagon::BADVA0 },
1577 { Hexagon::BADVA1 },
1578 { Hexagon::BRKPTCFG0 },
1579 { Hexagon::BRKPTCFG1 },
1580 { Hexagon::BRKPTPC0 },
1581 { Hexagon::BRKPTPC1 },
1582 { Hexagon::C5 },
1583 { Hexagon::R0 },
1584 { Hexagon::R1 },
1585 { Hexagon::R2 },
1586 { Hexagon::R3 },
1587 { Hexagon::R4 },
1588 { Hexagon::R5 },
1589 { Hexagon::R6 },
1590 { Hexagon::R7 },
1591 { Hexagon::R8 },
1592 { Hexagon::R9 },
1593 { Hexagon::R10 },
1594 { Hexagon::R11 },
1595 { Hexagon::R12 },
1596 { Hexagon::R13 },
1597 { Hexagon::R14 },
1598 { Hexagon::R15 },
1599 { Hexagon::R16 },
1600 { Hexagon::R17 },
1601 { Hexagon::R18 },
1602 { Hexagon::R19 },
1603 { Hexagon::R20 },
1604 { Hexagon::R21 },
1605 { Hexagon::R22 },
1606 { Hexagon::R23 },
1607 { Hexagon::R24 },
1608 { Hexagon::R25 },
1609 { Hexagon::R26 },
1610 { Hexagon::R27 },
1611 { Hexagon::R28 },
1612 { Hexagon::R29 },
1613 { Hexagon::R30 },
1614 { Hexagon::R31 },
1615 { Hexagon::G3 },
1616 { Hexagon::G4 },
1617 { Hexagon::G5 },
1618 { Hexagon::G6 },
1619 { Hexagon::G7 },
1620 { Hexagon::G8 },
1621 { Hexagon::G9 },
1622 { Hexagon::G10 },
1623 { Hexagon::G11 },
1624 { Hexagon::G12 },
1625 { Hexagon::G13 },
1626 { Hexagon::G14 },
1627 { Hexagon::G15 },
1628 { Hexagon::G20 },
1629 { Hexagon::G21 },
1630 { Hexagon::G22 },
1631 { Hexagon::G23 },
1632 { Hexagon::G30 },
1633 { Hexagon::G31 },
1634 { Hexagon::GPMUCNT0 },
1635 { Hexagon::GPMUCNT1 },
1636 { Hexagon::GPMUCNT2 },
1637 { Hexagon::GPMUCNT3 },
1638 { Hexagon::GPMUCNT4 },
1639 { Hexagon::GPMUCNT5 },
1640 { Hexagon::GPMUCNT6 },
1641 { Hexagon::GPMUCNT7 },
1642 { Hexagon::ISDBCFG0 },
1643 { Hexagon::ISDBCFG1 },
1644 { Hexagon::LC0 },
1645 { Hexagon::LC1 },
1646 { Hexagon::M0 },
1647 { Hexagon::M1 },
1648 { Hexagon::P0, Hexagon::P3_0 },
1649 { Hexagon::P1, Hexagon::P3_0 },
1650 { Hexagon::P2, Hexagon::P3_0 },
1651 { Hexagon::P3, Hexagon::P3_0 },
1652 { Hexagon::PMUCNT0 },
1653 { Hexagon::PMUCNT1 },
1654 { Hexagon::PMUCNT2 },
1655 { Hexagon::PMUCNT3 },
1656 { Hexagon::Q0 },
1657 { Hexagon::Q1 },
1658 { Hexagon::Q2 },
1659 { Hexagon::Q3 },
1660 { Hexagon::S11 },
1661 { Hexagon::S12 },
1662 { Hexagon::S13 },
1663 { Hexagon::S14 },
1664 { Hexagon::S15 },
1665 { Hexagon::S19 },
1666 { Hexagon::S20 },
1667 { Hexagon::S22 },
1668 { Hexagon::S23 },
1669 { Hexagon::S24 },
1670 { Hexagon::S25 },
1671 { Hexagon::S26 },
1672 { Hexagon::S35 },
1673 { Hexagon::S44 },
1674 { Hexagon::S45 },
1675 { Hexagon::S46 },
1676 { Hexagon::S47 },
1677 { Hexagon::S54 },
1678 { Hexagon::S55 },
1679 { Hexagon::S56 },
1680 { Hexagon::S57 },
1681 { Hexagon::S58 },
1682 { Hexagon::S59 },
1683 { Hexagon::S60 },
1684 { Hexagon::S61 },
1685 { Hexagon::S62 },
1686 { Hexagon::S63 },
1687 { Hexagon::S64 },
1688 { Hexagon::S65 },
1689 { Hexagon::S66 },
1690 { Hexagon::S67 },
1691 { Hexagon::S68 },
1692 { Hexagon::S69 },
1693 { Hexagon::S70 },
1694 { Hexagon::S71 },
1695 { Hexagon::S72 },
1696 { Hexagon::S73 },
1697 { Hexagon::S74 },
1698 { Hexagon::S75 },
1699 { Hexagon::S76 },
1700 { Hexagon::S77 },
1701 { Hexagon::S78 },
1702 { Hexagon::S79 },
1703 { Hexagon::S80 },
1704 { Hexagon::SA0 },
1705 { Hexagon::SA1 },
1706 { Hexagon::SGP0 },
1707 { Hexagon::SGP1 },
1708 { Hexagon::V0 },
1709 { Hexagon::V1 },
1710 { Hexagon::V2 },
1711 { Hexagon::V3 },
1712 { Hexagon::V4 },
1713 { Hexagon::V5 },
1714 { Hexagon::V6 },
1715 { Hexagon::V7 },
1716 { Hexagon::V8 },
1717 { Hexagon::V9 },
1718 { Hexagon::V10 },
1719 { Hexagon::V11 },
1720 { Hexagon::V12 },
1721 { Hexagon::V13 },
1722 { Hexagon::V14 },
1723 { Hexagon::V15 },
1724 { Hexagon::V16 },
1725 { Hexagon::V17 },
1726 { Hexagon::V18 },
1727 { Hexagon::V19 },
1728 { Hexagon::V20 },
1729 { Hexagon::V21 },
1730 { Hexagon::V22 },
1731 { Hexagon::V23 },
1732 { Hexagon::V24 },
1733 { Hexagon::V25 },
1734 { Hexagon::V26 },
1735 { Hexagon::V27 },
1736 { Hexagon::V28 },
1737 { Hexagon::V29 },
1738 { Hexagon::V30 },
1739 { Hexagon::V31 },
1740 { Hexagon::VF0 },
1741 { Hexagon::VF1 },
1742 { Hexagon::VF2 },
1743 { Hexagon::VF3 },
1744 { Hexagon::VF4 },
1745 { Hexagon::VF5 },
1746 { Hexagon::VF6 },
1747 { Hexagon::VF7 },
1748 { Hexagon::VF8 },
1749 { Hexagon::VF9 },
1750 { Hexagon::VF10 },
1751 { Hexagon::VF11 },
1752 { Hexagon::VF12 },
1753 { Hexagon::VF13 },
1754 { Hexagon::VF14 },
1755 { Hexagon::VF15 },
1756 { Hexagon::VF16 },
1757 { Hexagon::VF17 },
1758 { Hexagon::VF18 },
1759 { Hexagon::VF19 },
1760 { Hexagon::VF20 },
1761 { Hexagon::VF21 },
1762 { Hexagon::VF22 },
1763 { Hexagon::VF23 },
1764 { Hexagon::VF24 },
1765 { Hexagon::VF25 },
1766 { Hexagon::VF26 },
1767 { Hexagon::VF27 },
1768 { Hexagon::VF28 },
1769 { Hexagon::VF29 },
1770 { Hexagon::VF30 },
1771 { Hexagon::VF31 },
1772 { Hexagon::VFR0 },
1773 { Hexagon::VFR1 },
1774 { Hexagon::VFR2 },
1775 { Hexagon::VFR3 },
1776 { Hexagon::VFR4 },
1777 { Hexagon::VFR5 },
1778 { Hexagon::VFR6 },
1779 { Hexagon::VFR7 },
1780 { Hexagon::VFR8 },
1781 { Hexagon::VFR9 },
1782 { Hexagon::VFR10 },
1783 { Hexagon::VFR11 },
1784 { Hexagon::VFR12 },
1785 { Hexagon::VFR13 },
1786 { Hexagon::VFR14 },
1787 { Hexagon::VFR15 },
1788 { Hexagon::VFR16 },
1789 { Hexagon::VFR17 },
1790 { Hexagon::VFR18 },
1791 { Hexagon::VFR19 },
1792 { Hexagon::VFR20 },
1793 { Hexagon::VFR21 },
1794 { Hexagon::VFR22 },
1795 { Hexagon::VFR23 },
1796 { Hexagon::VFR24 },
1797 { Hexagon::VFR25 },
1798 { Hexagon::VFR26 },
1799 { Hexagon::VFR27 },
1800 { Hexagon::VFR28 },
1801 { Hexagon::VFR29 },
1802 { Hexagon::VFR30 },
1803 { Hexagon::VFR31 },
1804};
1805
1806namespace { // Register classes...
1807 // UsrBits Register Class...
1808 const MCPhysReg UsrBits[] = {
1809 Hexagon::USR_OVF,
1810 };
1811
1812 // UsrBits Bit set.
1813 const uint8_t UsrBitsBits[] = {
1814 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
1815 };
1816
1817 // SysRegs Register Class...
1818 const MCPhysReg SysRegs[] = {
1819 Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID, Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1, Hexagon::SSR, Hexagon::CCR, Hexagon::HTID, Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11, Hexagon::S12, Hexagon::S13, Hexagon::S14, Hexagon::S15, Hexagon::S19, Hexagon::S23, Hexagon::S25, Hexagon::EVB, Hexagon::MODECTL, Hexagon::SYSCFG, Hexagon::S20, Hexagon::VID, Hexagon::S22, Hexagon::S24, Hexagon::S26, Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV, Hexagon::PCYCLEHI, Hexagon::PCYCLELO, Hexagon::ISDBST, Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35, Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1, Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT, Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44, Hexagon::S45, Hexagon::S46, Hexagon::S47, Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2, Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG, Hexagon::S54, Hexagon::S55, Hexagon::S56, Hexagon::S57, Hexagon::S58, Hexagon::S59, Hexagon::S60, Hexagon::S61, Hexagon::S62, Hexagon::S63, Hexagon::S64, Hexagon::S65, Hexagon::S66, Hexagon::S67, Hexagon::S68, Hexagon::S69, Hexagon::S70, Hexagon::S71, Hexagon::S72, Hexagon::S73, Hexagon::S74, Hexagon::S75, Hexagon::S76, Hexagon::S77, Hexagon::S78, Hexagon::S79, Hexagon::S80,
1820 };
1821
1822 // SysRegs Bit set.
1823 const uint8_t SysRegsBits[] = {
1824 0xee, 0x00, 0xff, 0xc6, 0x0f, 0xa0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xc0, 0x03, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x33,
1825 };
1826
1827 // GuestRegs Register Class...
1828 const MCPhysReg GuestRegs[] = {
1829 Hexagon::GELR, Hexagon::GSR, Hexagon::GOSP, Hexagon::G3, Hexagon::G4, Hexagon::G5, Hexagon::G6, Hexagon::G7, Hexagon::G8, Hexagon::G9, Hexagon::G10, Hexagon::G11, Hexagon::G12, Hexagon::G13, Hexagon::G14, Hexagon::G15, Hexagon::GPMUCNT4, Hexagon::GPMUCNT5, Hexagon::GPMUCNT6, Hexagon::GPMUCNT7, Hexagon::G20, Hexagon::G21, Hexagon::G22, Hexagon::G23, Hexagon::GPCYCLELO, Hexagon::GPCYCLEHI, Hexagon::GPMUCNT0, Hexagon::GPMUCNT1, Hexagon::GPMUCNT2, Hexagon::GPMUCNT3, Hexagon::G30, Hexagon::G31,
1830 };
1831
1832 // GuestRegs Bit set.
1833 const uint8_t GuestRegsBits[] = {
1834 0x00, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x0f,
1835 };
1836
1837 // IntRegs Register Class...
1838 const MCPhysReg IntRegs[] = {
1839 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, Hexagon::R12, Hexagon::R13, Hexagon::R14, Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R10, Hexagon::R11, Hexagon::R29, Hexagon::R30, Hexagon::R31,
1840 };
1841
1842 // IntRegs Bit set.
1843 const uint8_t IntRegsBits[] = {
1844 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
1845 };
1846
1847 // CtrRegs Register Class...
1848 const MCPhysReg CtrRegs[] = {
1849 Hexagon::LC0, Hexagon::SA0, Hexagon::LC1, Hexagon::SA1, Hexagon::P3_0, Hexagon::C5, Hexagon::C8, Hexagon::PC, Hexagon::UGP, Hexagon::GP, Hexagon::CS0, Hexagon::CS1, Hexagon::UPCYCLELO, Hexagon::UPCYCLEHI, Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::UTIMERLO, Hexagon::UTIMERHI, Hexagon::M0, Hexagon::M1, Hexagon::USR,
1850 };
1851
1852 // CtrRegs Bit set.
1853 const uint8_t CtrRegsBits[] = {
1854 0x00, 0x13, 0x00, 0x31, 0xd0, 0x19, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
1855 };
1856
1857 // GeneralSubRegs Register Class...
1858 const MCPhysReg GeneralSubRegs[] = {
1859 Hexagon::R23, Hexagon::R22, Hexagon::R21, Hexagon::R20, Hexagon::R19, Hexagon::R18, Hexagon::R17, Hexagon::R16, Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon::R0,
1860 };
1861
1862 // GeneralSubRegs Bit set.
1863 const uint8_t GeneralSubRegsBits[] = {
1864 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 0xc0, 0x3f,
1865 };
1866
1867 // V62Regs Register Class...
1868 const MCPhysReg V62Regs[] = {
1869 Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::C17_16, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::PKTCOUNT, Hexagon::UTIMERLO, Hexagon::UTIMERHI, Hexagon::UTIMER,
1870 };
1871
1872 // V62Regs Bit set.
1873 const uint8_t V62RegsBits[] = {
1874 0x00, 0x03, 0x00, 0x38, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
1875 };
1876
1877 // IntRegsLow8 Register Class...
1878 const MCPhysReg IntRegsLow8[] = {
1879 Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon::R0,
1880 };
1881
1882 // IntRegsLow8 Bit set.
1883 const uint8_t IntRegsLow8Bits[] = {
1884 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
1885 };
1886
1887 // CtrRegs_and_V62Regs Register Class...
1888 const MCPhysReg CtrRegs_and_V62Regs[] = {
1889 Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::UTIMERLO, Hexagon::UTIMERHI,
1890 };
1891
1892 // CtrRegs_and_V62Regs Bit set.
1893 const uint8_t CtrRegs_and_V62RegsBits[] = {
1894 0x00, 0x03, 0x00, 0x30, 0x00, 0x18,
1895 };
1896
1897 // PredRegs Register Class...
1898 const MCPhysReg PredRegs[] = {
1899 Hexagon::P0, Hexagon::P1, Hexagon::P2, Hexagon::P3,
1900 };
1901
1902 // PredRegs Bit set.
1903 const uint8_t PredRegsBits[] = {
1904 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1905 };
1906
1907 // V62Regs_with_isub_hi Register Class...
1908 const MCPhysReg V62Regs_with_isub_hi[] = {
1909 Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER,
1910 };
1911
1912 // V62Regs_with_isub_hi Bit set.
1913 const uint8_t V62Regs_with_isub_hiBits[] = {
1914 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
1915 };
1916
1917 // ModRegs Register Class...
1918 const MCPhysReg ModRegs[] = {
1919 Hexagon::M0, Hexagon::M1,
1920 };
1921
1922 // ModRegs Bit set.
1923 const uint8_t ModRegsBits[] = {
1924 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
1925 };
1926
1927 // CtrRegs_with_subreg_overflow Register Class...
1928 const MCPhysReg CtrRegs_with_subreg_overflow[] = {
1929 Hexagon::USR,
1930 };
1931
1932 // CtrRegs_with_subreg_overflow Bit set.
1933 const uint8_t CtrRegs_with_subreg_overflowBits[] = {
1934 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1935 };
1936
1937 // V65Regs Register Class...
1938 const MCPhysReg V65Regs[] = {
1939 Hexagon::VTMP,
1940 };
1941
1942 // V65Regs Bit set.
1943 const uint8_t V65RegsBits[] = {
1944 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
1945 };
1946
1947 // SysRegs64 Register Class...
1948 const MCPhysReg SysRegs64[] = {
1949 Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6, Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14, Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22, Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30, Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38, Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46, Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54, Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62, Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70, Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
1950 };
1951
1952 // SysRegs64 Bit set.
1953 const uint8_t SysRegs64Bits[] = {
1954 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0x3f,
1955 };
1956
1957 // DoubleRegs Register Class...
1958 const MCPhysReg DoubleRegs[] = {
1959 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D4, Hexagon::D6, Hexagon::D7, Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13, Hexagon::D5, Hexagon::D14, Hexagon::D15,
1960 };
1961
1962 // DoubleRegs Bit set.
1963 const uint8_t DoubleRegsBits[] = {
1964 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
1965 };
1966
1967 // GuestRegs64 Register Class...
1968 const MCPhysReg GuestRegs64[] = {
1969 Hexagon::G1_0, Hexagon::G3_2, Hexagon::G5_4, Hexagon::G7_6, Hexagon::G9_8, Hexagon::G11_10, Hexagon::G13_12, Hexagon::G15_14, Hexagon::G17_16, Hexagon::G19_18, Hexagon::G21_20, Hexagon::G23_22, Hexagon::G25_24, Hexagon::G27_26, Hexagon::G29_28, Hexagon::G31_30,
1970 };
1971
1972 // GuestRegs64 Bit set.
1973 const uint8_t GuestRegs64Bits[] = {
1974 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
1975 };
1976
1977 // VectRegRev Register Class...
1978 const MCPhysReg VectRegRev[] = {
1979 Hexagon::WR0, Hexagon::WR1, Hexagon::WR2, Hexagon::WR3, Hexagon::WR4, Hexagon::WR5, Hexagon::WR6, Hexagon::WR7, Hexagon::WR8, Hexagon::WR9, Hexagon::WR10, Hexagon::WR11, Hexagon::WR12, Hexagon::WR13, Hexagon::WR14, Hexagon::WR15,
1980 };
1981
1982 // VectRegRev Bit set.
1983 const uint8_t VectRegRevBits[] = {
1984 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1985 };
1986
1987 // CtrRegs64 Register Class...
1988 const MCPhysReg CtrRegs64[] = {
1989 Hexagon::C1_0, Hexagon::C3_2, Hexagon::C5_4, Hexagon::C7_6, Hexagon::C9_8, Hexagon::C11_10, Hexagon::CS, Hexagon::UPCYCLE, Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER,
1990 };
1991
1992 // CtrRegs64 Bit set.
1993 const uint8_t CtrRegs64Bits[] = {
1994 0x10, 0x00, 0x00, 0x08, 0x20, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f,
1995 };
1996
1997 // GeneralDoubleLow8Regs Register Class...
1998 const MCPhysReg GeneralDoubleLow8Regs[] = {
1999 Hexagon::D11, Hexagon::D10, Hexagon::D9, Hexagon::D8, Hexagon::D3, Hexagon::D2, Hexagon::D1, Hexagon::D0,
2000 };
2001
2002 // GeneralDoubleLow8Regs Bit set.
2003 const uint8_t GeneralDoubleLow8RegsBits[] = {
2004 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1e,
2005 };
2006
2007 // DoubleRegs_with_isub_hi_in_IntRegsLow8 Register Class...
2008 const MCPhysReg DoubleRegs_with_isub_hi_in_IntRegsLow8[] = {
2009 Hexagon::D3, Hexagon::D2, Hexagon::D1, Hexagon::D0,
2010 };
2011
2012 // DoubleRegs_with_isub_hi_in_IntRegsLow8 Bit set.
2013 const uint8_t DoubleRegs_with_isub_hi_in_IntRegsLow8Bits[] = {
2014 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
2015 };
2016
2017 // CtrRegs64_and_V62Regs Register Class...
2018 const MCPhysReg CtrRegs64_and_V62Regs[] = {
2019 Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER,
2020 };
2021
2022 // CtrRegs64_and_V62Regs Bit set.
2023 const uint8_t CtrRegs64_and_V62RegsBits[] = {
2024 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2025 };
2026
2027 // CtrRegs64_with_isub_hi_in_ModRegs Register Class...
2028 const MCPhysReg CtrRegs64_with_isub_hi_in_ModRegs[] = {
2029 Hexagon::C7_6,
2030 };
2031
2032 // CtrRegs64_with_isub_hi_in_ModRegs Bit set.
2033 const uint8_t CtrRegs64_with_isub_hi_in_ModRegsBits[] = {
2034 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
2035 };
2036
2037 // HvxQR Register Class...
2038 const MCPhysReg HvxQR[] = {
2039 Hexagon::Q0, Hexagon::Q1, Hexagon::Q2, Hexagon::Q3,
2040 };
2041
2042 // HvxQR Bit set.
2043 const uint8_t HvxQRBits[] = {
2044 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
2045 };
2046
2047 // HvxVR Register Class...
2048 const MCPhysReg HvxVR[] = {
2049 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, Hexagon::V30, Hexagon::V31, Hexagon::VTMP,
2050 };
2051
2052 // HvxVR Bit set.
2053 const uint8_t HvxVRBits[] = {
2054 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
2055 };
2056
2057 // HvxVR_and_V65Regs Register Class...
2058 const MCPhysReg HvxVR_and_V65Regs[] = {
2059 Hexagon::VTMP,
2060 };
2061
2062 // HvxVR_and_V65Regs Bit set.
2063 const uint8_t HvxVR_and_V65RegsBits[] = {
2064 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2065 };
2066
2067 // HvxWR Register Class...
2068 const MCPhysReg HvxWR[] = {
2069 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15, Hexagon::WR0, Hexagon::WR1, Hexagon::WR2, Hexagon::WR3, Hexagon::WR4, Hexagon::WR5, Hexagon::WR6, Hexagon::WR7, Hexagon::WR8, Hexagon::WR9, Hexagon::WR10, Hexagon::WR11, Hexagon::WR12, Hexagon::WR13, Hexagon::WR14, Hexagon::WR15,
2070 };
2071
2072 // HvxWR Bit set.
2073 const uint8_t HvxWRBits[] = {
2074 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
2075 };
2076
2077 // HvxWR_and_VectRegRev Register Class...
2078 const MCPhysReg HvxWR_and_VectRegRev[] = {
2079 Hexagon::WR0, Hexagon::WR1, Hexagon::WR2, Hexagon::WR3, Hexagon::WR4, Hexagon::WR5, Hexagon::WR6, Hexagon::WR7, Hexagon::WR8, Hexagon::WR9, Hexagon::WR10, Hexagon::WR11, Hexagon::WR12, Hexagon::WR13, Hexagon::WR14, Hexagon::WR15,
2080 };
2081
2082 // HvxWR_and_VectRegRev Bit set.
2083 const uint8_t HvxWR_and_VectRegRevBits[] = {
2084 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
2085 };
2086
2087 // HvxVQR Register Class...
2088 const MCPhysReg HvxVQR[] = {
2089 Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3, Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7,
2090 };
2091
2092 // HvxVQR Bit set.
2093 const uint8_t HvxVQRBits[] = {
2094 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
2095 };
2096
2097} // end anonymous namespace
2098
2099
2100#ifdef __GNUC__
2101#pragma GCC diagnostic push
2102#pragma GCC diagnostic ignored "-Woverlength-strings"
2103#endif
2104extern const char HexagonRegClassStrings[] = {
2105 /* 0 */ "CtrRegs64\0"
2106 /* 10 */ "SysRegs64\0"
2107 /* 20 */ "GuestRegs64\0"
2108 /* 32 */ "DoubleRegs_with_isub_hi_in_IntRegsLow8\0"
2109 /* 71 */ "HvxVQR\0"
2110 /* 78 */ "HvxQR\0"
2111 /* 84 */ "HvxVR\0"
2112 /* 90 */ "HvxWR\0"
2113 /* 96 */ "V62Regs_with_isub_hi\0"
2114 /* 117 */ "CtrRegs64_and_V62Regs\0"
2115 /* 139 */ "CtrRegs_and_V62Regs\0"
2116 /* 159 */ "HvxVR_and_V65Regs\0"
2117 /* 177 */ "GeneralDoubleLow8Regs\0"
2118 /* 199 */ "GeneralSubRegs\0"
2119 /* 214 */ "PredRegs\0"
2120 /* 223 */ "CtrRegs64_with_isub_hi_in_ModRegs\0"
2121 /* 257 */ "DoubleRegs\0"
2122 /* 268 */ "CtrRegs\0"
2123 /* 276 */ "SysRegs\0"
2124 /* 284 */ "IntRegs\0"
2125 /* 292 */ "GuestRegs\0"
2126 /* 302 */ "UsrBits\0"
2127 /* 310 */ "HvxWR_and_VectRegRev\0"
2128 /* 331 */ "CtrRegs_with_subreg_overflow\0"
2129};
2130#ifdef __GNUC__
2131#pragma GCC diagnostic pop
2132#endif
2133
2134extern const MCRegisterClass HexagonMCRegisterClasses[] = {
2135 { UsrBits, UsrBitsBits, 302, 1, sizeof(UsrBitsBits), Hexagon::UsrBitsRegClassID, 1, 1, false, false },
2136 { SysRegs, SysRegsBits, 276, 81, sizeof(SysRegsBits), Hexagon::SysRegsRegClassID, 32, 1, false, false },
2137 { GuestRegs, GuestRegsBits, 292, 32, sizeof(GuestRegsBits), Hexagon::GuestRegsRegClassID, 32, 1, false, false },
2138 { IntRegs, IntRegsBits, 284, 32, sizeof(IntRegsBits), Hexagon::IntRegsRegClassID, 32, 1, true, false },
2139 { CtrRegs, CtrRegsBits, 268, 23, sizeof(CtrRegsBits), Hexagon::CtrRegsRegClassID, 32, 1, false, false },
2140 { GeneralSubRegs, GeneralSubRegsBits, 199, 16, sizeof(GeneralSubRegsBits), Hexagon::GeneralSubRegsRegClassID, 32, 1, true, false },
2141 { V62Regs, V62RegsBits, 131, 9, sizeof(V62RegsBits), Hexagon::V62RegsRegClassID, 32, 1, false, false },
2142 { IntRegsLow8, IntRegsLow8Bits, 59, 8, sizeof(IntRegsLow8Bits), Hexagon::IntRegsLow8RegClassID, 32, 1, true, false },
2143 { CtrRegs_and_V62Regs, CtrRegs_and_V62RegsBits, 139, 6, sizeof(CtrRegs_and_V62RegsBits), Hexagon::CtrRegs_and_V62RegsRegClassID, 32, 1, false, false },
2144 { PredRegs, PredRegsBits, 214, 4, sizeof(PredRegsBits), Hexagon::PredRegsRegClassID, 32, 1, true, false },
2145 { V62Regs_with_isub_hi, V62Regs_with_isub_hiBits, 96, 3, sizeof(V62Regs_with_isub_hiBits), Hexagon::V62Regs_with_isub_hiRegClassID, 32, 1, false, false },
2146 { ModRegs, ModRegsBits, 249, 2, sizeof(ModRegsBits), Hexagon::ModRegsRegClassID, 32, 1, true, false },
2147 { CtrRegs_with_subreg_overflow, CtrRegs_with_subreg_overflowBits, 331, 1, sizeof(CtrRegs_with_subreg_overflowBits), Hexagon::CtrRegs_with_subreg_overflowRegClassID, 32, 1, false, false },
2148 { V65Regs, V65RegsBits, 169, 1, sizeof(V65RegsBits), Hexagon::V65RegsRegClassID, 32, 1, false, false },
2149 { SysRegs64, SysRegs64Bits, 10, 40, sizeof(SysRegs64Bits), Hexagon::SysRegs64RegClassID, 64, 1, false, false },
2150 { DoubleRegs, DoubleRegsBits, 257, 16, sizeof(DoubleRegsBits), Hexagon::DoubleRegsRegClassID, 64, 1, true, false },
2151 { GuestRegs64, GuestRegs64Bits, 20, 16, sizeof(GuestRegs64Bits), Hexagon::GuestRegs64RegClassID, 64, 1, false, false },
2152 { VectRegRev, VectRegRevBits, 320, 16, sizeof(VectRegRevBits), Hexagon::VectRegRevRegClassID, 64, 1, true, false },
2153 { CtrRegs64, CtrRegs64Bits, 0, 11, sizeof(CtrRegs64Bits), Hexagon::CtrRegs64RegClassID, 64, 1, false, false },
2154 { GeneralDoubleLow8Regs, GeneralDoubleLow8RegsBits, 177, 8, sizeof(GeneralDoubleLow8RegsBits), Hexagon::GeneralDoubleLow8RegsRegClassID, 64, 1, true, false },
2155 { DoubleRegs_with_isub_hi_in_IntRegsLow8, DoubleRegs_with_isub_hi_in_IntRegsLow8Bits, 32, 4, sizeof(DoubleRegs_with_isub_hi_in_IntRegsLow8Bits), Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, 64, 1, true, false },
2156 { CtrRegs64_and_V62Regs, CtrRegs64_and_V62RegsBits, 117, 3, sizeof(CtrRegs64_and_V62RegsBits), Hexagon::CtrRegs64_and_V62RegsRegClassID, 64, 1, false, false },
2157 { CtrRegs64_with_isub_hi_in_ModRegs, CtrRegs64_with_isub_hi_in_ModRegsBits, 223, 1, sizeof(CtrRegs64_with_isub_hi_in_ModRegsBits), Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClassID, 64, 1, false, false },
2158 { HvxQR, HvxQRBits, 78, 4, sizeof(HvxQRBits), Hexagon::HvxQRRegClassID, 0, 1, true, false },
2159 { HvxVR, HvxVRBits, 84, 33, sizeof(HvxVRBits), Hexagon::HvxVRRegClassID, 0, 1, true, false },
2160 { HvxVR_and_V65Regs, HvxVR_and_V65RegsBits, 159, 1, sizeof(HvxVR_and_V65RegsBits), Hexagon::HvxVR_and_V65RegsRegClassID, 0, 1, true, false },
2161 { HvxWR, HvxWRBits, 90, 32, sizeof(HvxWRBits), Hexagon::HvxWRRegClassID, 0, 1, true, false },
2162 { HvxWR_and_VectRegRev, HvxWR_and_VectRegRevBits, 310, 16, sizeof(HvxWR_and_VectRegRevBits), Hexagon::HvxWR_and_VectRegRevRegClassID, 0, 1, true, false },
2163 { HvxVQR, HvxVQRBits, 71, 8, sizeof(HvxVQRBits), Hexagon::HvxVQRRegClassID, 0, 1, true, false },
2164};
2165
2166// Hexagon Dwarf<->LLVM register mappings.
2167extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[] = {
2168 { 0U, Hexagon::R0 },
2169 { 1U, Hexagon::R1 },
2170 { 2U, Hexagon::R2 },
2171 { 3U, Hexagon::R3 },
2172 { 4U, Hexagon::R4 },
2173 { 5U, Hexagon::R5 },
2174 { 6U, Hexagon::R6 },
2175 { 7U, Hexagon::R7 },
2176 { 8U, Hexagon::R8 },
2177 { 9U, Hexagon::R9 },
2178 { 10U, Hexagon::R10 },
2179 { 11U, Hexagon::R11 },
2180 { 12U, Hexagon::R12 },
2181 { 13U, Hexagon::R13 },
2182 { 14U, Hexagon::R14 },
2183 { 15U, Hexagon::R15 },
2184 { 16U, Hexagon::R16 },
2185 { 17U, Hexagon::R17 },
2186 { 18U, Hexagon::R18 },
2187 { 19U, Hexagon::R19 },
2188 { 20U, Hexagon::R20 },
2189 { 21U, Hexagon::R21 },
2190 { 22U, Hexagon::R22 },
2191 { 23U, Hexagon::R23 },
2192 { 24U, Hexagon::R24 },
2193 { 25U, Hexagon::R25 },
2194 { 26U, Hexagon::R26 },
2195 { 27U, Hexagon::R27 },
2196 { 28U, Hexagon::R28 },
2197 { 29U, Hexagon::R29 },
2198 { 30U, Hexagon::R30 },
2199 { 31U, Hexagon::R31 },
2200 { 32U, Hexagon::D0 },
2201 { 34U, Hexagon::D1 },
2202 { 36U, Hexagon::D2 },
2203 { 38U, Hexagon::D3 },
2204 { 40U, Hexagon::D4 },
2205 { 42U, Hexagon::D5 },
2206 { 44U, Hexagon::D6 },
2207 { 46U, Hexagon::D7 },
2208 { 48U, Hexagon::D8 },
2209 { 50U, Hexagon::D9 },
2210 { 52U, Hexagon::D10 },
2211 { 54U, Hexagon::D11 },
2212 { 56U, Hexagon::D12 },
2213 { 58U, Hexagon::D13 },
2214 { 60U, Hexagon::D14 },
2215 { 62U, Hexagon::D15 },
2216 { 63U, Hexagon::P0 },
2217 { 64U, Hexagon::P1 },
2218 { 65U, Hexagon::P2 },
2219 { 66U, Hexagon::P3 },
2220 { 67U, Hexagon::C1_0 },
2221 { 68U, Hexagon::LC0 },
2222 { 69U, Hexagon::C3_2 },
2223 { 70U, Hexagon::LC1 },
2224 { 71U, Hexagon::P3_0 },
2225 { 72U, Hexagon::C7_6 },
2226 { 73U, Hexagon::M0 },
2227 { 74U, Hexagon::C9_8 },
2228 { 75U, Hexagon::C8 },
2229 { 76U, Hexagon::C11_10 },
2230 { 77U, Hexagon::UGP },
2231 { 78U, Hexagon::GP },
2232 { 79U, Hexagon::CS0 },
2233 { 80U, Hexagon::CS1 },
2234 { 81U, Hexagon::UPCYCLELO },
2235 { 82U, Hexagon::UPCYCLEHI },
2236 { 83U, Hexagon::C17_16 },
2237 { 84U, Hexagon::FRAMEKEY },
2238 { 85U, Hexagon::PKTCOUNTLO },
2239 { 86U, Hexagon::PKTCOUNTHI },
2240 { 97U, Hexagon::UTIMERLO },
2241 { 98U, Hexagon::UTIMERHI },
2242 { 99U, Hexagon::W0 },
2243 { 100U, Hexagon::V1 },
2244 { 101U, Hexagon::W1 },
2245 { 102U, Hexagon::V3 },
2246 { 103U, Hexagon::W2 },
2247 { 104U, Hexagon::V5 },
2248 { 105U, Hexagon::W3 },
2249 { 106U, Hexagon::V7 },
2250 { 107U, Hexagon::W4 },
2251 { 108U, Hexagon::V9 },
2252 { 109U, Hexagon::W5 },
2253 { 110U, Hexagon::V11 },
2254 { 111U, Hexagon::W6 },
2255 { 112U, Hexagon::V13 },
2256 { 113U, Hexagon::W7 },
2257 { 114U, Hexagon::V15 },
2258 { 115U, Hexagon::W8 },
2259 { 116U, Hexagon::V17 },
2260 { 117U, Hexagon::W9 },
2261 { 118U, Hexagon::V19 },
2262 { 119U, Hexagon::W10 },
2263 { 120U, Hexagon::V21 },
2264 { 121U, Hexagon::W11 },
2265 { 122U, Hexagon::V23 },
2266 { 123U, Hexagon::W12 },
2267 { 124U, Hexagon::V25 },
2268 { 125U, Hexagon::W13 },
2269 { 126U, Hexagon::V27 },
2270 { 127U, Hexagon::W14 },
2271 { 128U, Hexagon::V29 },
2272 { 129U, Hexagon::W15 },
2273 { 130U, Hexagon::V31 },
2274 { 131U, Hexagon::Q0 },
2275 { 132U, Hexagon::Q1 },
2276 { 133U, Hexagon::Q2 },
2277 { 134U, Hexagon::Q3 },
2278 { 144U, Hexagon::SGP1_0 },
2279 { 145U, Hexagon::SGP1 },
2280 { 146U, Hexagon::S3_2 },
2281 { 147U, Hexagon::ELR },
2282 { 148U, Hexagon::S5_4 },
2283 { 149U, Hexagon::BADVA1 },
2284 { 150U, Hexagon::S7_6 },
2285 { 151U, Hexagon::CCR },
2286 { 152U, Hexagon::S9_8 },
2287 { 153U, Hexagon::BADVA },
2288 { 154U, Hexagon::S11_10 },
2289 { 155U, Hexagon::S11 },
2290 { 156U, Hexagon::S13_12 },
2291 { 157U, Hexagon::S13 },
2292 { 158U, Hexagon::S15_14 },
2293 { 159U, Hexagon::S15 },
2294 { 160U, Hexagon::S17_16 },
2295 { 161U, Hexagon::WR0 },
2296 { 162U, Hexagon::S19_18 },
2297 { 163U, Hexagon::WR2 },
2298 { 164U, Hexagon::S21_20 },
2299 { 165U, Hexagon::WR4 },
2300 { 166U, Hexagon::S23_22 },
2301 { 167U, Hexagon::WR6 },
2302 { 168U, Hexagon::S25_24 },
2303 { 169U, Hexagon::WR8 },
2304 { 170U, Hexagon::S27_26 },
2305 { 171U, Hexagon::WR10 },
2306 { 172U, Hexagon::S29_28 },
2307 { 173U, Hexagon::WR12 },
2308 { 174U, Hexagon::S31_30 },
2309 { 175U, Hexagon::WR14 },
2310 { 176U, Hexagon::S33_32 },
2311 { 177U, Hexagon::ISDBCFG0 },
2312 { 178U, Hexagon::S35_34 },
2313 { 179U, Hexagon::S35 },
2314 { 180U, Hexagon::S37_36 },
2315 { 181U, Hexagon::BRKPTCFG0 },
2316 { 182U, Hexagon::S39_38 },
2317 { 183U, Hexagon::BRKPTCFG1 },
2318 { 184U, Hexagon::S41_40 },
2319 { 185U, Hexagon::ISDBMBXOUT },
2320 { 186U, Hexagon::S43_42 },
2321 { 187U, Hexagon::ISDBGPR },
2322 { 188U, Hexagon::S45_44 },
2323 { 189U, Hexagon::S45 },
2324 { 190U, Hexagon::S47_46 },
2325 { 191U, Hexagon::S47 },
2326 { 192U, Hexagon::S49_48 },
2327 { 193U, Hexagon::PMUCNT1 },
2328 { 194U, Hexagon::S51_50 },
2329 { 195U, Hexagon::PMUCNT3 },
2330 { 196U, Hexagon::S53_52 },
2331 { 197U, Hexagon::PMUCFG },
2332 { 198U, Hexagon::S55_54 },
2333 { 199U, Hexagon::S55 },
2334 { 200U, Hexagon::S57_56 },
2335 { 201U, Hexagon::S57 },
2336 { 202U, Hexagon::S59_58 },
2337 { 203U, Hexagon::S59 },
2338 { 204U, Hexagon::S61_60 },
2339 { 205U, Hexagon::S61 },
2340 { 206U, Hexagon::S63_62 },
2341 { 207U, Hexagon::S63 },
2342 { 208U, Hexagon::S65_64 },
2343 { 209U, Hexagon::S65 },
2344 { 210U, Hexagon::S67_66 },
2345 { 211U, Hexagon::S67 },
2346 { 212U, Hexagon::S69_68 },
2347 { 213U, Hexagon::S69 },
2348 { 214U, Hexagon::S71_70 },
2349 { 215U, Hexagon::S71 },
2350 { 216U, Hexagon::S73_72 },
2351 { 217U, Hexagon::S73 },
2352 { 218U, Hexagon::S75_74 },
2353 { 219U, Hexagon::S77_76 },
2354 { 220U, Hexagon::S79_78 },
2355 { 221U, Hexagon::S77 },
2356 { 222U, Hexagon::G3_2 },
2357 { 223U, Hexagon::S79 },
2358 { 224U, Hexagon::G5_4 },
2359 { 225U, Hexagon::G5 },
2360 { 226U, Hexagon::G7_6 },
2361 { 227U, Hexagon::G7 },
2362 { 228U, Hexagon::G9_8 },
2363 { 229U, Hexagon::G9 },
2364 { 230U, Hexagon::G11_10 },
2365 { 231U, Hexagon::G11 },
2366 { 232U, Hexagon::G13_12 },
2367 { 233U, Hexagon::G13 },
2368 { 234U, Hexagon::G15_14 },
2369 { 235U, Hexagon::G15 },
2370 { 236U, Hexagon::G17_16 },
2371 { 237U, Hexagon::GPMUCNT5 },
2372 { 238U, Hexagon::G19_18 },
2373 { 239U, Hexagon::GPMUCNT7 },
2374 { 240U, Hexagon::G21_20 },
2375 { 241U, Hexagon::G21 },
2376 { 242U, Hexagon::G23_22 },
2377 { 243U, Hexagon::G23 },
2378 { 244U, Hexagon::G25_24 },
2379 { 245U, Hexagon::GPCYCLEHI },
2380 { 246U, Hexagon::G27_26 },
2381 { 247U, Hexagon::GPMUCNT1 },
2382 { 248U, Hexagon::G29_28 },
2383 { 249U, Hexagon::GPMUCNT3 },
2384 { 250U, Hexagon::G31_30 },
2385 { 251U, Hexagon::G31 },
2386 { 252U, Hexagon::VQ0 },
2387 { 253U, Hexagon::VQ1 },
2388 { 254U, Hexagon::VQ2 },
2389 { 255U, Hexagon::VQ3 },
2390 { 256U, Hexagon::VQ4 },
2391 { 257U, Hexagon::VQ5 },
2392 { 258U, Hexagon::VQ6 },
2393 { 259U, Hexagon::VQ7 },
2394 { 999999U, Hexagon::VF0 },
2395 { 1000000U, Hexagon::VF1 },
2396 { 1000001U, Hexagon::VF2 },
2397 { 1000002U, Hexagon::VF3 },
2398 { 1000003U, Hexagon::VF4 },
2399 { 1000004U, Hexagon::VF5 },
2400 { 1000005U, Hexagon::VF6 },
2401 { 1000006U, Hexagon::VF7 },
2402 { 1000007U, Hexagon::VF8 },
2403 { 1000008U, Hexagon::VF9 },
2404 { 1000009U, Hexagon::VF10 },
2405 { 1000010U, Hexagon::VF11 },
2406 { 1000011U, Hexagon::VF12 },
2407 { 1000012U, Hexagon::VF13 },
2408 { 1000013U, Hexagon::VF14 },
2409 { 1000014U, Hexagon::VF15 },
2410 { 1000015U, Hexagon::VF16 },
2411 { 1000016U, Hexagon::VF17 },
2412 { 1000017U, Hexagon::VF18 },
2413 { 1000018U, Hexagon::VF19 },
2414 { 1000019U, Hexagon::VF20 },
2415 { 1000020U, Hexagon::VF21 },
2416 { 1000021U, Hexagon::VF22 },
2417 { 1000022U, Hexagon::VF23 },
2418 { 1000023U, Hexagon::VF24 },
2419 { 1000024U, Hexagon::VF25 },
2420 { 1000025U, Hexagon::VF26 },
2421 { 1000026U, Hexagon::VF27 },
2422 { 1000027U, Hexagon::VF28 },
2423 { 1000028U, Hexagon::VF29 },
2424 { 1000029U, Hexagon::VF30 },
2425 { 1000030U, Hexagon::VF31 },
2426 { 9999999U, Hexagon::VFR0 },
2427 { 10000000U, Hexagon::VFR1 },
2428 { 10000001U, Hexagon::VFR2 },
2429 { 10000002U, Hexagon::VFR3 },
2430 { 10000003U, Hexagon::VFR4 },
2431 { 10000004U, Hexagon::VFR5 },
2432 { 10000005U, Hexagon::VFR6 },
2433 { 10000006U, Hexagon::VFR7 },
2434 { 10000007U, Hexagon::VFR8 },
2435 { 10000008U, Hexagon::VFR9 },
2436 { 10000009U, Hexagon::VFR10 },
2437 { 10000010U, Hexagon::VFR11 },
2438 { 10000011U, Hexagon::VFR12 },
2439 { 10000012U, Hexagon::VFR13 },
2440 { 10000013U, Hexagon::VFR14 },
2441 { 10000014U, Hexagon::VFR15 },
2442 { 10000015U, Hexagon::VFR16 },
2443 { 10000016U, Hexagon::VFR17 },
2444 { 10000017U, Hexagon::VFR18 },
2445 { 10000018U, Hexagon::VFR19 },
2446 { 10000019U, Hexagon::VFR20 },
2447 { 10000020U, Hexagon::VFR21 },
2448 { 10000021U, Hexagon::VFR22 },
2449 { 10000022U, Hexagon::VFR23 },
2450 { 10000023U, Hexagon::VFR24 },
2451 { 10000024U, Hexagon::VFR25 },
2452 { 10000025U, Hexagon::VFR26 },
2453 { 10000026U, Hexagon::VFR27 },
2454 { 10000027U, Hexagon::VFR28 },
2455 { 10000028U, Hexagon::VFR29 },
2456 { 10000029U, Hexagon::VFR30 },
2457 { 10000030U, Hexagon::VFR31 },
2458};
2459extern const unsigned HexagonDwarfFlavour0Dwarf2LSize = std::size(HexagonDwarfFlavour0Dwarf2L);
2460
2461extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[] = {
2462 { 0U, Hexagon::R0 },
2463 { 1U, Hexagon::R1 },
2464 { 2U, Hexagon::R2 },
2465 { 3U, Hexagon::R3 },
2466 { 4U, Hexagon::R4 },
2467 { 5U, Hexagon::R5 },
2468 { 6U, Hexagon::R6 },
2469 { 7U, Hexagon::R7 },
2470 { 8U, Hexagon::R8 },
2471 { 9U, Hexagon::R9 },
2472 { 10U, Hexagon::R10 },
2473 { 11U, Hexagon::R11 },
2474 { 12U, Hexagon::R12 },
2475 { 13U, Hexagon::R13 },
2476 { 14U, Hexagon::R14 },
2477 { 15U, Hexagon::R15 },
2478 { 16U, Hexagon::R16 },
2479 { 17U, Hexagon::R17 },
2480 { 18U, Hexagon::R18 },
2481 { 19U, Hexagon::R19 },
2482 { 20U, Hexagon::R20 },
2483 { 21U, Hexagon::R21 },
2484 { 22U, Hexagon::R22 },
2485 { 23U, Hexagon::R23 },
2486 { 24U, Hexagon::R24 },
2487 { 25U, Hexagon::R25 },
2488 { 26U, Hexagon::R26 },
2489 { 27U, Hexagon::R27 },
2490 { 28U, Hexagon::R28 },
2491 { 29U, Hexagon::R29 },
2492 { 30U, Hexagon::R30 },
2493 { 31U, Hexagon::R31 },
2494 { 32U, Hexagon::D0 },
2495 { 34U, Hexagon::D1 },
2496 { 36U, Hexagon::D2 },
2497 { 38U, Hexagon::D3 },
2498 { 40U, Hexagon::D4 },
2499 { 42U, Hexagon::D5 },
2500 { 44U, Hexagon::D6 },
2501 { 46U, Hexagon::D7 },
2502 { 48U, Hexagon::D8 },
2503 { 50U, Hexagon::D9 },
2504 { 52U, Hexagon::D10 },
2505 { 54U, Hexagon::D11 },
2506 { 56U, Hexagon::D12 },
2507 { 58U, Hexagon::D13 },
2508 { 60U, Hexagon::D14 },
2509 { 62U, Hexagon::D15 },
2510 { 63U, Hexagon::P0 },
2511 { 64U, Hexagon::P1 },
2512 { 65U, Hexagon::P2 },
2513 { 66U, Hexagon::P3 },
2514 { 67U, Hexagon::C1_0 },
2515 { 68U, Hexagon::LC0 },
2516 { 69U, Hexagon::C3_2 },
2517 { 70U, Hexagon::LC1 },
2518 { 71U, Hexagon::P3_0 },
2519 { 72U, Hexagon::C7_6 },
2520 { 73U, Hexagon::M0 },
2521 { 74U, Hexagon::C9_8 },
2522 { 75U, Hexagon::C8 },
2523 { 76U, Hexagon::C11_10 },
2524 { 77U, Hexagon::UGP },
2525 { 78U, Hexagon::GP },
2526 { 79U, Hexagon::CS0 },
2527 { 80U, Hexagon::CS1 },
2528 { 81U, Hexagon::UPCYCLELO },
2529 { 82U, Hexagon::UPCYCLEHI },
2530 { 83U, Hexagon::C17_16 },
2531 { 84U, Hexagon::FRAMEKEY },
2532 { 85U, Hexagon::PKTCOUNTLO },
2533 { 86U, Hexagon::PKTCOUNTHI },
2534 { 97U, Hexagon::UTIMERLO },
2535 { 98U, Hexagon::UTIMERHI },
2536 { 99U, Hexagon::W0 },
2537 { 100U, Hexagon::V1 },
2538 { 101U, Hexagon::W1 },
2539 { 102U, Hexagon::V3 },
2540 { 103U, Hexagon::W2 },
2541 { 104U, Hexagon::V5 },
2542 { 105U, Hexagon::W3 },
2543 { 106U, Hexagon::V7 },
2544 { 107U, Hexagon::W4 },
2545 { 108U, Hexagon::V9 },
2546 { 109U, Hexagon::W5 },
2547 { 110U, Hexagon::V11 },
2548 { 111U, Hexagon::W6 },
2549 { 112U, Hexagon::V13 },
2550 { 113U, Hexagon::W7 },
2551 { 114U, Hexagon::V15 },
2552 { 115U, Hexagon::W8 },
2553 { 116U, Hexagon::V17 },
2554 { 117U, Hexagon::W9 },
2555 { 118U, Hexagon::V19 },
2556 { 119U, Hexagon::W10 },
2557 { 120U, Hexagon::V21 },
2558 { 121U, Hexagon::W11 },
2559 { 122U, Hexagon::V23 },
2560 { 123U, Hexagon::W12 },
2561 { 124U, Hexagon::V25 },
2562 { 125U, Hexagon::W13 },
2563 { 126U, Hexagon::V27 },
2564 { 127U, Hexagon::W14 },
2565 { 128U, Hexagon::V29 },
2566 { 129U, Hexagon::W15 },
2567 { 130U, Hexagon::V31 },
2568 { 131U, Hexagon::Q0 },
2569 { 132U, Hexagon::Q1 },
2570 { 133U, Hexagon::Q2 },
2571 { 134U, Hexagon::Q3 },
2572 { 144U, Hexagon::SGP1_0 },
2573 { 145U, Hexagon::SGP1 },
2574 { 146U, Hexagon::S3_2 },
2575 { 147U, Hexagon::ELR },
2576 { 148U, Hexagon::S5_4 },
2577 { 149U, Hexagon::BADVA1 },
2578 { 150U, Hexagon::S7_6 },
2579 { 151U, Hexagon::CCR },
2580 { 152U, Hexagon::S9_8 },
2581 { 153U, Hexagon::BADVA },
2582 { 154U, Hexagon::S11_10 },
2583 { 155U, Hexagon::S11 },
2584 { 156U, Hexagon::S13_12 },
2585 { 157U, Hexagon::S13 },
2586 { 158U, Hexagon::S15_14 },
2587 { 159U, Hexagon::S15 },
2588 { 160U, Hexagon::S17_16 },
2589 { 161U, Hexagon::WR0 },
2590 { 162U, Hexagon::S19_18 },
2591 { 163U, Hexagon::WR2 },
2592 { 164U, Hexagon::S21_20 },
2593 { 165U, Hexagon::WR4 },
2594 { 166U, Hexagon::S23_22 },
2595 { 167U, Hexagon::WR6 },
2596 { 168U, Hexagon::S25_24 },
2597 { 169U, Hexagon::WR8 },
2598 { 170U, Hexagon::S27_26 },
2599 { 171U, Hexagon::WR10 },
2600 { 172U, Hexagon::S29_28 },
2601 { 173U, Hexagon::WR12 },
2602 { 174U, Hexagon::S31_30 },
2603 { 175U, Hexagon::WR14 },
2604 { 176U, Hexagon::S33_32 },
2605 { 177U, Hexagon::ISDBCFG0 },
2606 { 178U, Hexagon::S35_34 },
2607 { 179U, Hexagon::S35 },
2608 { 180U, Hexagon::S37_36 },
2609 { 181U, Hexagon::BRKPTCFG0 },
2610 { 182U, Hexagon::S39_38 },
2611 { 183U, Hexagon::BRKPTCFG1 },
2612 { 184U, Hexagon::S41_40 },
2613 { 185U, Hexagon::ISDBMBXOUT },
2614 { 186U, Hexagon::S43_42 },
2615 { 187U, Hexagon::ISDBGPR },
2616 { 188U, Hexagon::S45_44 },
2617 { 189U, Hexagon::S45 },
2618 { 190U, Hexagon::S47_46 },
2619 { 191U, Hexagon::S47 },
2620 { 192U, Hexagon::S49_48 },
2621 { 193U, Hexagon::PMUCNT1 },
2622 { 194U, Hexagon::S51_50 },
2623 { 195U, Hexagon::PMUCNT3 },
2624 { 196U, Hexagon::S53_52 },
2625 { 197U, Hexagon::PMUCFG },
2626 { 198U, Hexagon::S55_54 },
2627 { 199U, Hexagon::S55 },
2628 { 200U, Hexagon::S57_56 },
2629 { 201U, Hexagon::S57 },
2630 { 202U, Hexagon::S59_58 },
2631 { 203U, Hexagon::S59 },
2632 { 204U, Hexagon::S61_60 },
2633 { 205U, Hexagon::S61 },
2634 { 206U, Hexagon::S63_62 },
2635 { 207U, Hexagon::S63 },
2636 { 208U, Hexagon::S65_64 },
2637 { 209U, Hexagon::S65 },
2638 { 210U, Hexagon::S67_66 },
2639 { 211U, Hexagon::S67 },
2640 { 212U, Hexagon::S69_68 },
2641 { 213U, Hexagon::S69 },
2642 { 214U, Hexagon::S71_70 },
2643 { 215U, Hexagon::S71 },
2644 { 216U, Hexagon::S73_72 },
2645 { 217U, Hexagon::S73 },
2646 { 218U, Hexagon::S75_74 },
2647 { 219U, Hexagon::S77_76 },
2648 { 220U, Hexagon::S79_78 },
2649 { 221U, Hexagon::S77 },
2650 { 222U, Hexagon::G3_2 },
2651 { 223U, Hexagon::S79 },
2652 { 224U, Hexagon::G5_4 },
2653 { 225U, Hexagon::G5 },
2654 { 226U, Hexagon::G7_6 },
2655 { 227U, Hexagon::G7 },
2656 { 228U, Hexagon::G9_8 },
2657 { 229U, Hexagon::G9 },
2658 { 230U, Hexagon::G11_10 },
2659 { 231U, Hexagon::G11 },
2660 { 232U, Hexagon::G13_12 },
2661 { 233U, Hexagon::G13 },
2662 { 234U, Hexagon::G15_14 },
2663 { 235U, Hexagon::G15 },
2664 { 236U, Hexagon::G17_16 },
2665 { 237U, Hexagon::GPMUCNT5 },
2666 { 238U, Hexagon::G19_18 },
2667 { 239U, Hexagon::GPMUCNT7 },
2668 { 240U, Hexagon::G21_20 },
2669 { 241U, Hexagon::G21 },
2670 { 242U, Hexagon::G23_22 },
2671 { 243U, Hexagon::G23 },
2672 { 244U, Hexagon::G25_24 },
2673 { 245U, Hexagon::GPCYCLEHI },
2674 { 246U, Hexagon::G27_26 },
2675 { 247U, Hexagon::GPMUCNT1 },
2676 { 248U, Hexagon::G29_28 },
2677 { 249U, Hexagon::GPMUCNT3 },
2678 { 250U, Hexagon::G31_30 },
2679 { 251U, Hexagon::G31 },
2680 { 252U, Hexagon::VQ0 },
2681 { 253U, Hexagon::VQ1 },
2682 { 254U, Hexagon::VQ2 },
2683 { 255U, Hexagon::VQ3 },
2684 { 256U, Hexagon::VQ4 },
2685 { 257U, Hexagon::VQ5 },
2686 { 258U, Hexagon::VQ6 },
2687 { 259U, Hexagon::VQ7 },
2688 { 999999U, Hexagon::VF0 },
2689 { 1000000U, Hexagon::VF1 },
2690 { 1000001U, Hexagon::VF2 },
2691 { 1000002U, Hexagon::VF3 },
2692 { 1000003U, Hexagon::VF4 },
2693 { 1000004U, Hexagon::VF5 },
2694 { 1000005U, Hexagon::VF6 },
2695 { 1000006U, Hexagon::VF7 },
2696 { 1000007U, Hexagon::VF8 },
2697 { 1000008U, Hexagon::VF9 },
2698 { 1000009U, Hexagon::VF10 },
2699 { 1000010U, Hexagon::VF11 },
2700 { 1000011U, Hexagon::VF12 },
2701 { 1000012U, Hexagon::VF13 },
2702 { 1000013U, Hexagon::VF14 },
2703 { 1000014U, Hexagon::VF15 },
2704 { 1000015U, Hexagon::VF16 },
2705 { 1000016U, Hexagon::VF17 },
2706 { 1000017U, Hexagon::VF18 },
2707 { 1000018U, Hexagon::VF19 },
2708 { 1000019U, Hexagon::VF20 },
2709 { 1000020U, Hexagon::VF21 },
2710 { 1000021U, Hexagon::VF22 },
2711 { 1000022U, Hexagon::VF23 },
2712 { 1000023U, Hexagon::VF24 },
2713 { 1000024U, Hexagon::VF25 },
2714 { 1000025U, Hexagon::VF26 },
2715 { 1000026U, Hexagon::VF27 },
2716 { 1000027U, Hexagon::VF28 },
2717 { 1000028U, Hexagon::VF29 },
2718 { 1000029U, Hexagon::VF30 },
2719 { 1000030U, Hexagon::VF31 },
2720 { 9999999U, Hexagon::VFR0 },
2721 { 10000000U, Hexagon::VFR1 },
2722 { 10000001U, Hexagon::VFR2 },
2723 { 10000002U, Hexagon::VFR3 },
2724 { 10000003U, Hexagon::VFR4 },
2725 { 10000004U, Hexagon::VFR5 },
2726 { 10000005U, Hexagon::VFR6 },
2727 { 10000006U, Hexagon::VFR7 },
2728 { 10000007U, Hexagon::VFR8 },
2729 { 10000008U, Hexagon::VFR9 },
2730 { 10000009U, Hexagon::VFR10 },
2731 { 10000010U, Hexagon::VFR11 },
2732 { 10000011U, Hexagon::VFR12 },
2733 { 10000012U, Hexagon::VFR13 },
2734 { 10000013U, Hexagon::VFR14 },
2735 { 10000014U, Hexagon::VFR15 },
2736 { 10000015U, Hexagon::VFR16 },
2737 { 10000016U, Hexagon::VFR17 },
2738 { 10000017U, Hexagon::VFR18 },
2739 { 10000018U, Hexagon::VFR19 },
2740 { 10000019U, Hexagon::VFR20 },
2741 { 10000020U, Hexagon::VFR21 },
2742 { 10000021U, Hexagon::VFR22 },
2743 { 10000022U, Hexagon::VFR23 },
2744 { 10000023U, Hexagon::VFR24 },
2745 { 10000024U, Hexagon::VFR25 },
2746 { 10000025U, Hexagon::VFR26 },
2747 { 10000026U, Hexagon::VFR27 },
2748 { 10000027U, Hexagon::VFR28 },
2749 { 10000028U, Hexagon::VFR29 },
2750 { 10000029U, Hexagon::VFR30 },
2751 { 10000030U, Hexagon::VFR31 },
2752};
2753extern const unsigned HexagonEHFlavour0Dwarf2LSize = std::size(HexagonEHFlavour0Dwarf2L);
2754
2755extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[] = {
2756 { Hexagon::BADVA, 153U },
2757 { Hexagon::CCR, 151U },
2758 { Hexagon::CFGBASE, 171U },
2759 { Hexagon::CS, 78U },
2760 { Hexagon::DIAG, 172U },
2761 { Hexagon::ELR, 147U },
2762 { Hexagon::EVB, 160U },
2763 { Hexagon::FRAMEKEY, 84U },
2764 { Hexagon::FRAMELIMIT, 83U },
2765 { Hexagon::GELR, 220U },
2766 { Hexagon::GOSP, 222U },
2767 { Hexagon::GP, 78U },
2768 { Hexagon::GPCYCLEHI, 245U },
2769 { Hexagon::GPCYCLELO, 244U },
2770 { Hexagon::GSR, 221U },
2771 { Hexagon::HTID, 152U },
2772 { Hexagon::IMASK, 154U },
2773 { Hexagon::ISDBEN, 186U },
2774 { Hexagon::ISDBGPR, 187U },
2775 { Hexagon::ISDBMBXIN, 184U },
2776 { Hexagon::ISDBMBXOUT, 185U },
2777 { Hexagon::ISDBST, 176U },
2778 { Hexagon::MODECTL, 161U },
2779 { Hexagon::PC, 76U },
2780 { Hexagon::PCYCLEHI, 175U },
2781 { Hexagon::PCYCLELO, 174U },
2782 { Hexagon::PKTCOUNT, 85U },
2783 { Hexagon::PKTCOUNTHI, 86U },
2784 { Hexagon::PKTCOUNTLO, 85U },
2785 { Hexagon::PMUCFG, 197U },
2786 { Hexagon::PMUEVTCFG, 196U },
2787 { Hexagon::REV, 173U },
2788 { Hexagon::SSR, 150U },
2789 { Hexagon::STID, 146U },
2790 { Hexagon::SYSCFG, 162U },
2791 { Hexagon::UGP, 77U },
2792 { Hexagon::UPCYCLE, 80U },
2793 { Hexagon::UPCYCLEHI, 82U },
2794 { Hexagon::UPCYCLELO, 81U },
2795 { Hexagon::USR, 75U },
2796 { Hexagon::UTIMER, 97U },
2797 { Hexagon::UTIMERHI, 98U },
2798 { Hexagon::UTIMERLO, 97U },
2799 { Hexagon::VID, 165U },
2800 { Hexagon::VTMP, 131U },
2801 { Hexagon::BADVA0, 148U },
2802 { Hexagon::BADVA1, 149U },
2803 { Hexagon::BRKPTCFG0, 181U },
2804 { Hexagon::BRKPTCFG1, 183U },
2805 { Hexagon::BRKPTPC0, 180U },
2806 { Hexagon::BRKPTPC1, 182U },
2807 { Hexagon::C5, 72U },
2808 { Hexagon::C8, 75U },
2809 { Hexagon::CS0, 79U },
2810 { Hexagon::CS1, 80U },
2811 { Hexagon::D0, 32U },
2812 { Hexagon::D1, 34U },
2813 { Hexagon::D2, 36U },
2814 { Hexagon::D3, 38U },
2815 { Hexagon::D4, 40U },
2816 { Hexagon::D5, 42U },
2817 { Hexagon::D6, 44U },
2818 { Hexagon::D7, 46U },
2819 { Hexagon::D8, 48U },
2820 { Hexagon::D9, 50U },
2821 { Hexagon::D10, 52U },
2822 { Hexagon::D11, 54U },
2823 { Hexagon::D12, 56U },
2824 { Hexagon::D13, 58U },
2825 { Hexagon::D14, 60U },
2826 { Hexagon::D15, 62U },
2827 { Hexagon::G3, 223U },
2828 { Hexagon::G4, 224U },
2829 { Hexagon::G5, 225U },
2830 { Hexagon::G6, 226U },
2831 { Hexagon::G7, 227U },
2832 { Hexagon::G8, 228U },
2833 { Hexagon::G9, 229U },
2834 { Hexagon::G10, 230U },
2835 { Hexagon::G11, 231U },
2836 { Hexagon::G12, 232U },
2837 { Hexagon::G13, 233U },
2838 { Hexagon::G14, 234U },
2839 { Hexagon::G15, 235U },
2840 { Hexagon::G20, 240U },
2841 { Hexagon::G21, 241U },
2842 { Hexagon::G22, 242U },
2843 { Hexagon::G23, 243U },
2844 { Hexagon::G30, 250U },
2845 { Hexagon::G31, 251U },
2846 { Hexagon::GPMUCNT0, 246U },
2847 { Hexagon::GPMUCNT1, 247U },
2848 { Hexagon::GPMUCNT2, 248U },
2849 { Hexagon::GPMUCNT3, 249U },
2850 { Hexagon::GPMUCNT4, 236U },
2851 { Hexagon::GPMUCNT5, 237U },
2852 { Hexagon::GPMUCNT6, 238U },
2853 { Hexagon::GPMUCNT7, 239U },
2854 { Hexagon::ISDBCFG0, 177U },
2855 { Hexagon::ISDBCFG1, 178U },
2856 { Hexagon::LC0, 68U },
2857 { Hexagon::LC1, 70U },
2858 { Hexagon::M0, 73U },
2859 { Hexagon::M1, 74U },
2860 { Hexagon::P0, 63U },
2861 { Hexagon::P1, 64U },
2862 { Hexagon::P2, 65U },
2863 { Hexagon::P3, 66U },
2864 { Hexagon::PMUCNT0, 192U },
2865 { Hexagon::PMUCNT1, 193U },
2866 { Hexagon::PMUCNT2, 194U },
2867 { Hexagon::PMUCNT3, 195U },
2868 { Hexagon::Q0, 131U },
2869 { Hexagon::Q1, 132U },
2870 { Hexagon::Q2, 133U },
2871 { Hexagon::Q3, 134U },
2872 { Hexagon::R0, 0U },
2873 { Hexagon::R1, 1U },
2874 { Hexagon::R2, 2U },
2875 { Hexagon::R3, 3U },
2876 { Hexagon::R4, 4U },
2877 { Hexagon::R5, 5U },
2878 { Hexagon::R6, 6U },
2879 { Hexagon::R7, 7U },
2880 { Hexagon::R8, 8U },
2881 { Hexagon::R9, 9U },
2882 { Hexagon::R10, 10U },
2883 { Hexagon::R11, 11U },
2884 { Hexagon::R12, 12U },
2885 { Hexagon::R13, 13U },
2886 { Hexagon::R14, 14U },
2887 { Hexagon::R15, 15U },
2888 { Hexagon::R16, 16U },
2889 { Hexagon::R17, 17U },
2890 { Hexagon::R18, 18U },
2891 { Hexagon::R19, 19U },
2892 { Hexagon::R20, 20U },
2893 { Hexagon::R21, 21U },
2894 { Hexagon::R22, 22U },
2895 { Hexagon::R23, 23U },
2896 { Hexagon::R24, 24U },
2897 { Hexagon::R25, 25U },
2898 { Hexagon::R26, 26U },
2899 { Hexagon::R27, 27U },
2900 { Hexagon::R28, 28U },
2901 { Hexagon::R29, 29U },
2902 { Hexagon::R30, 30U },
2903 { Hexagon::R31, 31U },
2904 { Hexagon::S11, 155U },
2905 { Hexagon::S12, 156U },
2906 { Hexagon::S13, 157U },
2907 { Hexagon::S14, 158U },
2908 { Hexagon::S15, 159U },
2909 { Hexagon::S19, 163U },
2910 { Hexagon::S20, 164U },
2911 { Hexagon::S22, 166U },
2912 { Hexagon::S23, 167U },
2913 { Hexagon::S24, 168U },
2914 { Hexagon::S25, 169U },
2915 { Hexagon::S26, 170U },
2916 { Hexagon::S35, 179U },
2917 { Hexagon::S44, 188U },
2918 { Hexagon::S45, 189U },
2919 { Hexagon::S46, 190U },
2920 { Hexagon::S47, 191U },
2921 { Hexagon::S54, 198U },
2922 { Hexagon::S55, 199U },
2923 { Hexagon::S56, 200U },
2924 { Hexagon::S57, 201U },
2925 { Hexagon::S58, 202U },
2926 { Hexagon::S59, 203U },
2927 { Hexagon::S60, 204U },
2928 { Hexagon::S61, 205U },
2929 { Hexagon::S62, 206U },
2930 { Hexagon::S63, 207U },
2931 { Hexagon::S64, 208U },
2932 { Hexagon::S65, 209U },
2933 { Hexagon::S66, 210U },
2934 { Hexagon::S67, 211U },
2935 { Hexagon::S68, 212U },
2936 { Hexagon::S69, 213U },
2937 { Hexagon::S70, 214U },
2938 { Hexagon::S71, 215U },
2939 { Hexagon::S72, 216U },
2940 { Hexagon::S73, 217U },
2941 { Hexagon::S74, 218U },
2942 { Hexagon::S75, 219U },
2943 { Hexagon::S76, 220U },
2944 { Hexagon::S77, 221U },
2945 { Hexagon::S78, 222U },
2946 { Hexagon::S79, 223U },
2947 { Hexagon::S80, 224U },
2948 { Hexagon::SA0, 67U },
2949 { Hexagon::SA1, 69U },
2950 { Hexagon::SGP0, 144U },
2951 { Hexagon::SGP1, 145U },
2952 { Hexagon::V0, 99U },
2953 { Hexagon::V1, 100U },
2954 { Hexagon::V2, 101U },
2955 { Hexagon::V3, 102U },
2956 { Hexagon::V4, 103U },
2957 { Hexagon::V5, 104U },
2958 { Hexagon::V6, 105U },
2959 { Hexagon::V7, 106U },
2960 { Hexagon::V8, 107U },
2961 { Hexagon::V9, 108U },
2962 { Hexagon::V10, 109U },
2963 { Hexagon::V11, 110U },
2964 { Hexagon::V12, 111U },
2965 { Hexagon::V13, 112U },
2966 { Hexagon::V14, 113U },
2967 { Hexagon::V15, 114U },
2968 { Hexagon::V16, 115U },
2969 { Hexagon::V17, 116U },
2970 { Hexagon::V18, 117U },
2971 { Hexagon::V19, 118U },
2972 { Hexagon::V20, 119U },
2973 { Hexagon::V21, 120U },
2974 { Hexagon::V22, 121U },
2975 { Hexagon::V23, 122U },
2976 { Hexagon::V24, 123U },
2977 { Hexagon::V25, 124U },
2978 { Hexagon::V26, 125U },
2979 { Hexagon::V27, 126U },
2980 { Hexagon::V28, 127U },
2981 { Hexagon::V29, 128U },
2982 { Hexagon::V30, 129U },
2983 { Hexagon::V31, 130U },
2984 { Hexagon::VF0, 999999U },
2985 { Hexagon::VF1, 1000000U },
2986 { Hexagon::VF2, 1000001U },
2987 { Hexagon::VF3, 1000002U },
2988 { Hexagon::VF4, 1000003U },
2989 { Hexagon::VF5, 1000004U },
2990 { Hexagon::VF6, 1000005U },
2991 { Hexagon::VF7, 1000006U },
2992 { Hexagon::VF8, 1000007U },
2993 { Hexagon::VF9, 1000008U },
2994 { Hexagon::VF10, 1000009U },
2995 { Hexagon::VF11, 1000010U },
2996 { Hexagon::VF12, 1000011U },
2997 { Hexagon::VF13, 1000012U },
2998 { Hexagon::VF14, 1000013U },
2999 { Hexagon::VF15, 1000014U },
3000 { Hexagon::VF16, 1000015U },
3001 { Hexagon::VF17, 1000016U },
3002 { Hexagon::VF18, 1000017U },
3003 { Hexagon::VF19, 1000018U },
3004 { Hexagon::VF20, 1000019U },
3005 { Hexagon::VF21, 1000020U },
3006 { Hexagon::VF22, 1000021U },
3007 { Hexagon::VF23, 1000022U },
3008 { Hexagon::VF24, 1000023U },
3009 { Hexagon::VF25, 1000024U },
3010 { Hexagon::VF26, 1000025U },
3011 { Hexagon::VF27, 1000026U },
3012 { Hexagon::VF28, 1000027U },
3013 { Hexagon::VF29, 1000028U },
3014 { Hexagon::VF30, 1000029U },
3015 { Hexagon::VF31, 1000030U },
3016 { Hexagon::VFR0, 9999999U },
3017 { Hexagon::VFR1, 10000000U },
3018 { Hexagon::VFR2, 10000001U },
3019 { Hexagon::VFR3, 10000002U },
3020 { Hexagon::VFR4, 10000003U },
3021 { Hexagon::VFR5, 10000004U },
3022 { Hexagon::VFR6, 10000005U },
3023 { Hexagon::VFR7, 10000006U },
3024 { Hexagon::VFR8, 10000007U },
3025 { Hexagon::VFR9, 10000008U },
3026 { Hexagon::VFR10, 10000009U },
3027 { Hexagon::VFR11, 10000010U },
3028 { Hexagon::VFR12, 10000011U },
3029 { Hexagon::VFR13, 10000012U },
3030 { Hexagon::VFR14, 10000013U },
3031 { Hexagon::VFR15, 10000014U },
3032 { Hexagon::VFR16, 10000015U },
3033 { Hexagon::VFR17, 10000016U },
3034 { Hexagon::VFR18, 10000017U },
3035 { Hexagon::VFR19, 10000018U },
3036 { Hexagon::VFR20, 10000019U },
3037 { Hexagon::VFR21, 10000020U },
3038 { Hexagon::VFR22, 10000021U },
3039 { Hexagon::VFR23, 10000022U },
3040 { Hexagon::VFR24, 10000023U },
3041 { Hexagon::VFR25, 10000024U },
3042 { Hexagon::VFR26, 10000025U },
3043 { Hexagon::VFR27, 10000026U },
3044 { Hexagon::VFR28, 10000027U },
3045 { Hexagon::VFR29, 10000028U },
3046 { Hexagon::VFR30, 10000029U },
3047 { Hexagon::VFR31, 10000030U },
3048 { Hexagon::VQ0, 252U },
3049 { Hexagon::VQ1, 253U },
3050 { Hexagon::VQ2, 254U },
3051 { Hexagon::VQ3, 255U },
3052 { Hexagon::VQ4, 256U },
3053 { Hexagon::VQ5, 257U },
3054 { Hexagon::VQ6, 258U },
3055 { Hexagon::VQ7, 259U },
3056 { Hexagon::W0, 99U },
3057 { Hexagon::W1, 101U },
3058 { Hexagon::W2, 103U },
3059 { Hexagon::W3, 105U },
3060 { Hexagon::W4, 107U },
3061 { Hexagon::W5, 109U },
3062 { Hexagon::W6, 111U },
3063 { Hexagon::W7, 113U },
3064 { Hexagon::W8, 115U },
3065 { Hexagon::W9, 117U },
3066 { Hexagon::W10, 119U },
3067 { Hexagon::W11, 121U },
3068 { Hexagon::W12, 123U },
3069 { Hexagon::W13, 125U },
3070 { Hexagon::W14, 127U },
3071 { Hexagon::W15, 129U },
3072 { Hexagon::WR0, 161U },
3073 { Hexagon::WR1, 162U },
3074 { Hexagon::WR2, 163U },
3075 { Hexagon::WR3, 164U },
3076 { Hexagon::WR4, 165U },
3077 { Hexagon::WR5, 166U },
3078 { Hexagon::WR6, 167U },
3079 { Hexagon::WR7, 168U },
3080 { Hexagon::WR8, 169U },
3081 { Hexagon::WR9, 170U },
3082 { Hexagon::WR10, 171U },
3083 { Hexagon::WR11, 172U },
3084 { Hexagon::WR12, 173U },
3085 { Hexagon::WR13, 174U },
3086 { Hexagon::WR14, 175U },
3087 { Hexagon::WR15, 176U },
3088 { Hexagon::C1_0, 67U },
3089 { Hexagon::C3_2, 69U },
3090 { Hexagon::C5_4, 71U },
3091 { Hexagon::C7_6, 72U },
3092 { Hexagon::C9_8, 74U },
3093 { Hexagon::C11_10, 76U },
3094 { Hexagon::C17_16, 83U },
3095 { Hexagon::G1_0, 220U },
3096 { Hexagon::G3_2, 222U },
3097 { Hexagon::G5_4, 224U },
3098 { Hexagon::G7_6, 226U },
3099 { Hexagon::G9_8, 228U },
3100 { Hexagon::G11_10, 230U },
3101 { Hexagon::G13_12, 232U },
3102 { Hexagon::G15_14, 234U },
3103 { Hexagon::G17_16, 236U },
3104 { Hexagon::G19_18, 238U },
3105 { Hexagon::G21_20, 240U },
3106 { Hexagon::G23_22, 242U },
3107 { Hexagon::G25_24, 244U },
3108 { Hexagon::G27_26, 246U },
3109 { Hexagon::G29_28, 248U },
3110 { Hexagon::G31_30, 250U },
3111 { Hexagon::P3_0, 71U },
3112 { Hexagon::S3_2, 146U },
3113 { Hexagon::S5_4, 148U },
3114 { Hexagon::S7_6, 150U },
3115 { Hexagon::S9_8, 152U },
3116 { Hexagon::S11_10, 154U },
3117 { Hexagon::S13_12, 156U },
3118 { Hexagon::S15_14, 158U },
3119 { Hexagon::S17_16, 160U },
3120 { Hexagon::S19_18, 162U },
3121 { Hexagon::S21_20, 164U },
3122 { Hexagon::S23_22, 166U },
3123 { Hexagon::S25_24, 168U },
3124 { Hexagon::S27_26, 170U },
3125 { Hexagon::S29_28, 172U },
3126 { Hexagon::S31_30, 174U },
3127 { Hexagon::S33_32, 176U },
3128 { Hexagon::S35_34, 178U },
3129 { Hexagon::S37_36, 180U },
3130 { Hexagon::S39_38, 182U },
3131 { Hexagon::S41_40, 184U },
3132 { Hexagon::S43_42, 186U },
3133 { Hexagon::S45_44, 188U },
3134 { Hexagon::S47_46, 190U },
3135 { Hexagon::S49_48, 192U },
3136 { Hexagon::S51_50, 194U },
3137 { Hexagon::S53_52, 196U },
3138 { Hexagon::S55_54, 198U },
3139 { Hexagon::S57_56, 200U },
3140 { Hexagon::S59_58, 202U },
3141 { Hexagon::S61_60, 204U },
3142 { Hexagon::S63_62, 206U },
3143 { Hexagon::S65_64, 208U },
3144 { Hexagon::S67_66, 210U },
3145 { Hexagon::S69_68, 212U },
3146 { Hexagon::S71_70, 214U },
3147 { Hexagon::S73_72, 216U },
3148 { Hexagon::S75_74, 218U },
3149 { Hexagon::S77_76, 219U },
3150 { Hexagon::S79_78, 220U },
3151 { Hexagon::SGP1_0, 144U },
3152};
3153extern const unsigned HexagonDwarfFlavour0L2DwarfSize = std::size(HexagonDwarfFlavour0L2Dwarf);
3154
3155extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[] = {
3156 { Hexagon::BADVA, 153U },
3157 { Hexagon::CCR, 151U },
3158 { Hexagon::CFGBASE, 171U },
3159 { Hexagon::CS, 78U },
3160 { Hexagon::DIAG, 172U },
3161 { Hexagon::ELR, 147U },
3162 { Hexagon::EVB, 160U },
3163 { Hexagon::FRAMEKEY, 84U },
3164 { Hexagon::FRAMELIMIT, 83U },
3165 { Hexagon::GELR, 220U },
3166 { Hexagon::GOSP, 222U },
3167 { Hexagon::GP, 78U },
3168 { Hexagon::GPCYCLEHI, 245U },
3169 { Hexagon::GPCYCLELO, 244U },
3170 { Hexagon::GSR, 221U },
3171 { Hexagon::HTID, 152U },
3172 { Hexagon::IMASK, 154U },
3173 { Hexagon::ISDBEN, 186U },
3174 { Hexagon::ISDBGPR, 187U },
3175 { Hexagon::ISDBMBXIN, 184U },
3176 { Hexagon::ISDBMBXOUT, 185U },
3177 { Hexagon::ISDBST, 176U },
3178 { Hexagon::MODECTL, 161U },
3179 { Hexagon::PC, 76U },
3180 { Hexagon::PCYCLEHI, 175U },
3181 { Hexagon::PCYCLELO, 174U },
3182 { Hexagon::PKTCOUNT, 85U },
3183 { Hexagon::PKTCOUNTHI, 86U },
3184 { Hexagon::PKTCOUNTLO, 85U },
3185 { Hexagon::PMUCFG, 197U },
3186 { Hexagon::PMUEVTCFG, 196U },
3187 { Hexagon::REV, 173U },
3188 { Hexagon::SSR, 150U },
3189 { Hexagon::STID, 146U },
3190 { Hexagon::SYSCFG, 162U },
3191 { Hexagon::UGP, 77U },
3192 { Hexagon::UPCYCLE, 80U },
3193 { Hexagon::UPCYCLEHI, 82U },
3194 { Hexagon::UPCYCLELO, 81U },
3195 { Hexagon::USR, 75U },
3196 { Hexagon::UTIMER, 97U },
3197 { Hexagon::UTIMERHI, 98U },
3198 { Hexagon::UTIMERLO, 97U },
3199 { Hexagon::VID, 165U },
3200 { Hexagon::VTMP, 131U },
3201 { Hexagon::BADVA0, 148U },
3202 { Hexagon::BADVA1, 149U },
3203 { Hexagon::BRKPTCFG0, 181U },
3204 { Hexagon::BRKPTCFG1, 183U },
3205 { Hexagon::BRKPTPC0, 180U },
3206 { Hexagon::BRKPTPC1, 182U },
3207 { Hexagon::C5, 72U },
3208 { Hexagon::C8, 75U },
3209 { Hexagon::CS0, 79U },
3210 { Hexagon::CS1, 80U },
3211 { Hexagon::D0, 32U },
3212 { Hexagon::D1, 34U },
3213 { Hexagon::D2, 36U },
3214 { Hexagon::D3, 38U },
3215 { Hexagon::D4, 40U },
3216 { Hexagon::D5, 42U },
3217 { Hexagon::D6, 44U },
3218 { Hexagon::D7, 46U },
3219 { Hexagon::D8, 48U },
3220 { Hexagon::D9, 50U },
3221 { Hexagon::D10, 52U },
3222 { Hexagon::D11, 54U },
3223 { Hexagon::D12, 56U },
3224 { Hexagon::D13, 58U },
3225 { Hexagon::D14, 60U },
3226 { Hexagon::D15, 62U },
3227 { Hexagon::G3, 223U },
3228 { Hexagon::G4, 224U },
3229 { Hexagon::G5, 225U },
3230 { Hexagon::G6, 226U },
3231 { Hexagon::G7, 227U },
3232 { Hexagon::G8, 228U },
3233 { Hexagon::G9, 229U },
3234 { Hexagon::G10, 230U },
3235 { Hexagon::G11, 231U },
3236 { Hexagon::G12, 232U },
3237 { Hexagon::G13, 233U },
3238 { Hexagon::G14, 234U },
3239 { Hexagon::G15, 235U },
3240 { Hexagon::G20, 240U },
3241 { Hexagon::G21, 241U },
3242 { Hexagon::G22, 242U },
3243 { Hexagon::G23, 243U },
3244 { Hexagon::G30, 250U },
3245 { Hexagon::G31, 251U },
3246 { Hexagon::GPMUCNT0, 246U },
3247 { Hexagon::GPMUCNT1, 247U },
3248 { Hexagon::GPMUCNT2, 248U },
3249 { Hexagon::GPMUCNT3, 249U },
3250 { Hexagon::GPMUCNT4, 236U },
3251 { Hexagon::GPMUCNT5, 237U },
3252 { Hexagon::GPMUCNT6, 238U },
3253 { Hexagon::GPMUCNT7, 239U },
3254 { Hexagon::ISDBCFG0, 177U },
3255 { Hexagon::ISDBCFG1, 178U },
3256 { Hexagon::LC0, 68U },
3257 { Hexagon::LC1, 70U },
3258 { Hexagon::M0, 73U },
3259 { Hexagon::M1, 74U },
3260 { Hexagon::P0, 63U },
3261 { Hexagon::P1, 64U },
3262 { Hexagon::P2, 65U },
3263 { Hexagon::P3, 66U },
3264 { Hexagon::PMUCNT0, 192U },
3265 { Hexagon::PMUCNT1, 193U },
3266 { Hexagon::PMUCNT2, 194U },
3267 { Hexagon::PMUCNT3, 195U },
3268 { Hexagon::Q0, 131U },
3269 { Hexagon::Q1, 132U },
3270 { Hexagon::Q2, 133U },
3271 { Hexagon::Q3, 134U },
3272 { Hexagon::R0, 0U },
3273 { Hexagon::R1, 1U },
3274 { Hexagon::R2, 2U },
3275 { Hexagon::R3, 3U },
3276 { Hexagon::R4, 4U },
3277 { Hexagon::R5, 5U },
3278 { Hexagon::R6, 6U },
3279 { Hexagon::R7, 7U },
3280 { Hexagon::R8, 8U },
3281 { Hexagon::R9, 9U },
3282 { Hexagon::R10, 10U },
3283 { Hexagon::R11, 11U },
3284 { Hexagon::R12, 12U },
3285 { Hexagon::R13, 13U },
3286 { Hexagon::R14, 14U },
3287 { Hexagon::R15, 15U },
3288 { Hexagon::R16, 16U },
3289 { Hexagon::R17, 17U },
3290 { Hexagon::R18, 18U },
3291 { Hexagon::R19, 19U },
3292 { Hexagon::R20, 20U },
3293 { Hexagon::R21, 21U },
3294 { Hexagon::R22, 22U },
3295 { Hexagon::R23, 23U },
3296 { Hexagon::R24, 24U },
3297 { Hexagon::R25, 25U },
3298 { Hexagon::R26, 26U },
3299 { Hexagon::R27, 27U },
3300 { Hexagon::R28, 28U },
3301 { Hexagon::R29, 29U },
3302 { Hexagon::R30, 30U },
3303 { Hexagon::R31, 31U },
3304 { Hexagon::S11, 155U },
3305 { Hexagon::S12, 156U },
3306 { Hexagon::S13, 157U },
3307 { Hexagon::S14, 158U },
3308 { Hexagon::S15, 159U },
3309 { Hexagon::S19, 163U },
3310 { Hexagon::S20, 164U },
3311 { Hexagon::S22, 166U },
3312 { Hexagon::S23, 167U },
3313 { Hexagon::S24, 168U },
3314 { Hexagon::S25, 169U },
3315 { Hexagon::S26, 170U },
3316 { Hexagon::S35, 179U },
3317 { Hexagon::S44, 188U },
3318 { Hexagon::S45, 189U },
3319 { Hexagon::S46, 190U },
3320 { Hexagon::S47, 191U },
3321 { Hexagon::S54, 198U },
3322 { Hexagon::S55, 199U },
3323 { Hexagon::S56, 200U },
3324 { Hexagon::S57, 201U },
3325 { Hexagon::S58, 202U },
3326 { Hexagon::S59, 203U },
3327 { Hexagon::S60, 204U },
3328 { Hexagon::S61, 205U },
3329 { Hexagon::S62, 206U },
3330 { Hexagon::S63, 207U },
3331 { Hexagon::S64, 208U },
3332 { Hexagon::S65, 209U },
3333 { Hexagon::S66, 210U },
3334 { Hexagon::S67, 211U },
3335 { Hexagon::S68, 212U },
3336 { Hexagon::S69, 213U },
3337 { Hexagon::S70, 214U },
3338 { Hexagon::S71, 215U },
3339 { Hexagon::S72, 216U },
3340 { Hexagon::S73, 217U },
3341 { Hexagon::S74, 218U },
3342 { Hexagon::S75, 219U },
3343 { Hexagon::S76, 220U },
3344 { Hexagon::S77, 221U },
3345 { Hexagon::S78, 222U },
3346 { Hexagon::S79, 223U },
3347 { Hexagon::S80, 224U },
3348 { Hexagon::SA0, 67U },
3349 { Hexagon::SA1, 69U },
3350 { Hexagon::SGP0, 144U },
3351 { Hexagon::SGP1, 145U },
3352 { Hexagon::V0, 99U },
3353 { Hexagon::V1, 100U },
3354 { Hexagon::V2, 101U },
3355 { Hexagon::V3, 102U },
3356 { Hexagon::V4, 103U },
3357 { Hexagon::V5, 104U },
3358 { Hexagon::V6, 105U },
3359 { Hexagon::V7, 106U },
3360 { Hexagon::V8, 107U },
3361 { Hexagon::V9, 108U },
3362 { Hexagon::V10, 109U },
3363 { Hexagon::V11, 110U },
3364 { Hexagon::V12, 111U },
3365 { Hexagon::V13, 112U },
3366 { Hexagon::V14, 113U },
3367 { Hexagon::V15, 114U },
3368 { Hexagon::V16, 115U },
3369 { Hexagon::V17, 116U },
3370 { Hexagon::V18, 117U },
3371 { Hexagon::V19, 118U },
3372 { Hexagon::V20, 119U },
3373 { Hexagon::V21, 120U },
3374 { Hexagon::V22, 121U },
3375 { Hexagon::V23, 122U },
3376 { Hexagon::V24, 123U },
3377 { Hexagon::V25, 124U },
3378 { Hexagon::V26, 125U },
3379 { Hexagon::V27, 126U },
3380 { Hexagon::V28, 127U },
3381 { Hexagon::V29, 128U },
3382 { Hexagon::V30, 129U },
3383 { Hexagon::V31, 130U },
3384 { Hexagon::VF0, 999999U },
3385 { Hexagon::VF1, 1000000U },
3386 { Hexagon::VF2, 1000001U },
3387 { Hexagon::VF3, 1000002U },
3388 { Hexagon::VF4, 1000003U },
3389 { Hexagon::VF5, 1000004U },
3390 { Hexagon::VF6, 1000005U },
3391 { Hexagon::VF7, 1000006U },
3392 { Hexagon::VF8, 1000007U },
3393 { Hexagon::VF9, 1000008U },
3394 { Hexagon::VF10, 1000009U },
3395 { Hexagon::VF11, 1000010U },
3396 { Hexagon::VF12, 1000011U },
3397 { Hexagon::VF13, 1000012U },
3398 { Hexagon::VF14, 1000013U },
3399 { Hexagon::VF15, 1000014U },
3400 { Hexagon::VF16, 1000015U },
3401 { Hexagon::VF17, 1000016U },
3402 { Hexagon::VF18, 1000017U },
3403 { Hexagon::VF19, 1000018U },
3404 { Hexagon::VF20, 1000019U },
3405 { Hexagon::VF21, 1000020U },
3406 { Hexagon::VF22, 1000021U },
3407 { Hexagon::VF23, 1000022U },
3408 { Hexagon::VF24, 1000023U },
3409 { Hexagon::VF25, 1000024U },
3410 { Hexagon::VF26, 1000025U },
3411 { Hexagon::VF27, 1000026U },
3412 { Hexagon::VF28, 1000027U },
3413 { Hexagon::VF29, 1000028U },
3414 { Hexagon::VF30, 1000029U },
3415 { Hexagon::VF31, 1000030U },
3416 { Hexagon::VFR0, 9999999U },
3417 { Hexagon::VFR1, 10000000U },
3418 { Hexagon::VFR2, 10000001U },
3419 { Hexagon::VFR3, 10000002U },
3420 { Hexagon::VFR4, 10000003U },
3421 { Hexagon::VFR5, 10000004U },
3422 { Hexagon::VFR6, 10000005U },
3423 { Hexagon::VFR7, 10000006U },
3424 { Hexagon::VFR8, 10000007U },
3425 { Hexagon::VFR9, 10000008U },
3426 { Hexagon::VFR10, 10000009U },
3427 { Hexagon::VFR11, 10000010U },
3428 { Hexagon::VFR12, 10000011U },
3429 { Hexagon::VFR13, 10000012U },
3430 { Hexagon::VFR14, 10000013U },
3431 { Hexagon::VFR15, 10000014U },
3432 { Hexagon::VFR16, 10000015U },
3433 { Hexagon::VFR17, 10000016U },
3434 { Hexagon::VFR18, 10000017U },
3435 { Hexagon::VFR19, 10000018U },
3436 { Hexagon::VFR20, 10000019U },
3437 { Hexagon::VFR21, 10000020U },
3438 { Hexagon::VFR22, 10000021U },
3439 { Hexagon::VFR23, 10000022U },
3440 { Hexagon::VFR24, 10000023U },
3441 { Hexagon::VFR25, 10000024U },
3442 { Hexagon::VFR26, 10000025U },
3443 { Hexagon::VFR27, 10000026U },
3444 { Hexagon::VFR28, 10000027U },
3445 { Hexagon::VFR29, 10000028U },
3446 { Hexagon::VFR30, 10000029U },
3447 { Hexagon::VFR31, 10000030U },
3448 { Hexagon::VQ0, 252U },
3449 { Hexagon::VQ1, 253U },
3450 { Hexagon::VQ2, 254U },
3451 { Hexagon::VQ3, 255U },
3452 { Hexagon::VQ4, 256U },
3453 { Hexagon::VQ5, 257U },
3454 { Hexagon::VQ6, 258U },
3455 { Hexagon::VQ7, 259U },
3456 { Hexagon::W0, 99U },
3457 { Hexagon::W1, 101U },
3458 { Hexagon::W2, 103U },
3459 { Hexagon::W3, 105U },
3460 { Hexagon::W4, 107U },
3461 { Hexagon::W5, 109U },
3462 { Hexagon::W6, 111U },
3463 { Hexagon::W7, 113U },
3464 { Hexagon::W8, 115U },
3465 { Hexagon::W9, 117U },
3466 { Hexagon::W10, 119U },
3467 { Hexagon::W11, 121U },
3468 { Hexagon::W12, 123U },
3469 { Hexagon::W13, 125U },
3470 { Hexagon::W14, 127U },
3471 { Hexagon::W15, 129U },
3472 { Hexagon::WR0, 161U },
3473 { Hexagon::WR1, 162U },
3474 { Hexagon::WR2, 163U },
3475 { Hexagon::WR3, 164U },
3476 { Hexagon::WR4, 165U },
3477 { Hexagon::WR5, 166U },
3478 { Hexagon::WR6, 167U },
3479 { Hexagon::WR7, 168U },
3480 { Hexagon::WR8, 169U },
3481 { Hexagon::WR9, 170U },
3482 { Hexagon::WR10, 171U },
3483 { Hexagon::WR11, 172U },
3484 { Hexagon::WR12, 173U },
3485 { Hexagon::WR13, 174U },
3486 { Hexagon::WR14, 175U },
3487 { Hexagon::WR15, 176U },
3488 { Hexagon::C1_0, 67U },
3489 { Hexagon::C3_2, 69U },
3490 { Hexagon::C5_4, 71U },
3491 { Hexagon::C7_6, 72U },
3492 { Hexagon::C9_8, 74U },
3493 { Hexagon::C11_10, 76U },
3494 { Hexagon::C17_16, 83U },
3495 { Hexagon::G1_0, 220U },
3496 { Hexagon::G3_2, 222U },
3497 { Hexagon::G5_4, 224U },
3498 { Hexagon::G7_6, 226U },
3499 { Hexagon::G9_8, 228U },
3500 { Hexagon::G11_10, 230U },
3501 { Hexagon::G13_12, 232U },
3502 { Hexagon::G15_14, 234U },
3503 { Hexagon::G17_16, 236U },
3504 { Hexagon::G19_18, 238U },
3505 { Hexagon::G21_20, 240U },
3506 { Hexagon::G23_22, 242U },
3507 { Hexagon::G25_24, 244U },
3508 { Hexagon::G27_26, 246U },
3509 { Hexagon::G29_28, 248U },
3510 { Hexagon::G31_30, 250U },
3511 { Hexagon::P3_0, 71U },
3512 { Hexagon::S3_2, 146U },
3513 { Hexagon::S5_4, 148U },
3514 { Hexagon::S7_6, 150U },
3515 { Hexagon::S9_8, 152U },
3516 { Hexagon::S11_10, 154U },
3517 { Hexagon::S13_12, 156U },
3518 { Hexagon::S15_14, 158U },
3519 { Hexagon::S17_16, 160U },
3520 { Hexagon::S19_18, 162U },
3521 { Hexagon::S21_20, 164U },
3522 { Hexagon::S23_22, 166U },
3523 { Hexagon::S25_24, 168U },
3524 { Hexagon::S27_26, 170U },
3525 { Hexagon::S29_28, 172U },
3526 { Hexagon::S31_30, 174U },
3527 { Hexagon::S33_32, 176U },
3528 { Hexagon::S35_34, 178U },
3529 { Hexagon::S37_36, 180U },
3530 { Hexagon::S39_38, 182U },
3531 { Hexagon::S41_40, 184U },
3532 { Hexagon::S43_42, 186U },
3533 { Hexagon::S45_44, 188U },
3534 { Hexagon::S47_46, 190U },
3535 { Hexagon::S49_48, 192U },
3536 { Hexagon::S51_50, 194U },
3537 { Hexagon::S53_52, 196U },
3538 { Hexagon::S55_54, 198U },
3539 { Hexagon::S57_56, 200U },
3540 { Hexagon::S59_58, 202U },
3541 { Hexagon::S61_60, 204U },
3542 { Hexagon::S63_62, 206U },
3543 { Hexagon::S65_64, 208U },
3544 { Hexagon::S67_66, 210U },
3545 { Hexagon::S69_68, 212U },
3546 { Hexagon::S71_70, 214U },
3547 { Hexagon::S73_72, 216U },
3548 { Hexagon::S75_74, 218U },
3549 { Hexagon::S77_76, 219U },
3550 { Hexagon::S79_78, 220U },
3551 { Hexagon::SGP1_0, 144U },
3552};
3553extern const unsigned HexagonEHFlavour0L2DwarfSize = std::size(HexagonEHFlavour0L2Dwarf);
3554
3555extern const uint16_t HexagonRegEncodingTable[] = {
3556 0,
3557 9,
3558 7,
3559 27,
3560 12,
3561 28,
3562 3,
3563 16,
3564 17,
3565 16,
3566 0,
3567 2,
3568 11,
3569 25,
3570 24,
3571 1,
3572 8,
3573 10,
3574 42,
3575 43,
3576 40,
3577 41,
3578 32,
3579 17,
3580 9,
3581 31,
3582 30,
3583 18,
3584 19,
3585 18,
3586 53,
3587 52,
3588 29,
3589 6,
3590 2,
3591 18,
3592 10,
3593 14,
3594 15,
3595 14,
3596 8,
3597 0,
3598 30,
3599 31,
3600 30,
3601 21,
3602 0,
3603 4,
3604 5,
3605 37,
3606 39,
3607 36,
3608 38,
3609 5,
3610 8,
3611 12,
3612 13,
3613 0,
3614 2,
3615 4,
3616 6,
3617 8,
3618 10,
3619 12,
3620 14,
3621 16,
3622 18,
3623 20,
3624 22,
3625 24,
3626 26,
3627 28,
3628 30,
3629 3,
3630 4,
3631 5,
3632 6,
3633 7,
3634 8,
3635 9,
3636 10,
3637 11,
3638 12,
3639 13,
3640 14,
3641 15,
3642 20,
3643 21,
3644 22,
3645 23,
3646 30,
3647 31,
3648 26,
3649 27,
3650 28,
3651 29,
3652 16,
3653 17,
3654 18,
3655 19,
3656 33,
3657 34,
3658 1,
3659 3,
3660 6,
3661 7,
3662 0,
3663 1,
3664 2,
3665 3,
3666 48,
3667 49,
3668 50,
3669 51,
3670 0,
3671 1,
3672 2,
3673 3,
3674 0,
3675 1,
3676 2,
3677 3,
3678 4,
3679 5,
3680 6,
3681 7,
3682 8,
3683 9,
3684 10,
3685 11,
3686 12,
3687 13,
3688 14,
3689 15,
3690 16,
3691 17,
3692 18,
3693 19,
3694 20,
3695 21,
3696 22,
3697 23,
3698 24,
3699 25,
3700 26,
3701 27,
3702 28,
3703 29,
3704 30,
3705 31,
3706 11,
3707 12,
3708 13,
3709 14,
3710 15,
3711 19,
3712 20,
3713 22,
3714 23,
3715 24,
3716 25,
3717 26,
3718 35,
3719 44,
3720 45,
3721 46,
3722 47,
3723 54,
3724 55,
3725 56,
3726 57,
3727 58,
3728 59,
3729 60,
3730 61,
3731 62,
3732 63,
3733 64,
3734 65,
3735 66,
3736 67,
3737 68,
3738 69,
3739 70,
3740 71,
3741 72,
3742 73,
3743 74,
3744 75,
3745 76,
3746 77,
3747 78,
3748 79,
3749 80,
3750 0,
3751 2,
3752 0,
3753 1,
3754 0,
3755 1,
3756 2,
3757 3,
3758 4,
3759 5,
3760 6,
3761 7,
3762 8,
3763 9,
3764 10,
3765 11,
3766 12,
3767 13,
3768 14,
3769 15,
3770 16,
3771 17,
3772 18,
3773 19,
3774 20,
3775 21,
3776 22,
3777 23,
3778 24,
3779 25,
3780 26,
3781 27,
3782 28,
3783 29,
3784 30,
3785 31,
3786 0,
3787 0,
3788 0,
3789 0,
3790 0,
3791 0,
3792 0,
3793 0,
3794 0,
3795 0,
3796 0,
3797 0,
3798 0,
3799 0,
3800 0,
3801 0,
3802 0,
3803 0,
3804 0,
3805 0,
3806 0,
3807 0,
3808 0,
3809 0,
3810 0,
3811 0,
3812 0,
3813 0,
3814 0,
3815 0,
3816 0,
3817 0,
3818 0,
3819 0,
3820 0,
3821 0,
3822 0,
3823 0,
3824 0,
3825 0,
3826 0,
3827 0,
3828 0,
3829 0,
3830 0,
3831 0,
3832 0,
3833 0,
3834 0,
3835 0,
3836 0,
3837 0,
3838 0,
3839 0,
3840 0,
3841 0,
3842 0,
3843 0,
3844 0,
3845 0,
3846 0,
3847 0,
3848 0,
3849 0,
3850 0,
3851 4,
3852 8,
3853 12,
3854 16,
3855 20,
3856 24,
3857 28,
3858 0,
3859 2,
3860 4,
3861 6,
3862 8,
3863 10,
3864 12,
3865 14,
3866 16,
3867 18,
3868 20,
3869 22,
3870 24,
3871 26,
3872 28,
3873 30,
3874 1,
3875 3,
3876 5,
3877 7,
3878 9,
3879 11,
3880 13,
3881 15,
3882 17,
3883 19,
3884 21,
3885 23,
3886 25,
3887 27,
3888 29,
3889 31,
3890 0,
3891 2,
3892 4,
3893 6,
3894 8,
3895 10,
3896 16,
3897 0,
3898 2,
3899 4,
3900 6,
3901 8,
3902 10,
3903 12,
3904 14,
3905 16,
3906 18,
3907 20,
3908 22,
3909 24,
3910 26,
3911 28,
3912 30,
3913 4,
3914 2,
3915 4,
3916 6,
3917 8,
3918 10,
3919 12,
3920 14,
3921 16,
3922 18,
3923 20,
3924 22,
3925 24,
3926 26,
3927 28,
3928 30,
3929 32,
3930 34,
3931 36,
3932 38,
3933 40,
3934 42,
3935 44,
3936 46,
3937 48,
3938 50,
3939 52,
3940 54,
3941 56,
3942 58,
3943 60,
3944 62,
3945 64,
3946 66,
3947 68,
3948 70,
3949 72,
3950 74,
3951 76,
3952 78,
3953 0,
3954};
3955static inline void InitHexagonMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3956 RI->InitMCRegisterInfo(HexagonRegDesc, 398, RA, PC, HexagonMCRegisterClasses, 29, HexagonRegUnitRoots, 272, HexagonRegDiffLists, HexagonLaneMaskLists, HexagonRegStrings, HexagonRegClassStrings, HexagonSubRegIdxLists, 12,
3957HexagonRegEncodingTable);
3958
3959 switch (DwarfFlavour) {
3960 default:
3961 llvm_unreachable("Unknown DWARF flavour");
3962 case 0:
3963 RI->mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
3964 break;
3965 }
3966 switch (EHFlavour) {
3967 default:
3968 llvm_unreachable("Unknown DWARF flavour");
3969 case 0:
3970 RI->mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
3971 break;
3972 }
3973 switch (DwarfFlavour) {
3974 default:
3975 llvm_unreachable("Unknown DWARF flavour");
3976 case 0:
3977 RI->mapLLVMRegsToDwarfRegs(HexagonDwarfFlavour0L2Dwarf, HexagonDwarfFlavour0L2DwarfSize, false);
3978 break;
3979 }
3980 switch (EHFlavour) {
3981 default:
3982 llvm_unreachable("Unknown DWARF flavour");
3983 case 0:
3984 RI->mapLLVMRegsToDwarfRegs(HexagonEHFlavour0L2Dwarf, HexagonEHFlavour0L2DwarfSize, true);
3985 break;
3986 }
3987}
3988
3989} // end namespace llvm
3990
3991#endif // GET_REGINFO_MC_DESC
3992
3993/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3994|* *|
3995|* Register Information Header Fragment *|
3996|* *|
3997|* Automatically generated file, do not edit! *|
3998|* *|
3999\*===----------------------------------------------------------------------===*/
4000
4001
4002#ifdef GET_REGINFO_HEADER
4003#undef GET_REGINFO_HEADER
4004
4005#include "llvm/CodeGen/TargetRegisterInfo.h"
4006
4007namespace llvm {
4008
4009class HexagonFrameLowering;
4010
4011struct HexagonGenRegisterInfo : public TargetRegisterInfo {
4012 explicit HexagonGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
4013 unsigned PC = 0, unsigned HwMode = 0);
4014 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
4015 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4016 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4017 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
4018 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
4019 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
4020 unsigned getRegUnitWeight(unsigned RegUnit) const override;
4021 unsigned getNumRegPressureSets() const override;
4022 const char *getRegPressureSetName(unsigned Idx) const override;
4023 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
4024 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
4025 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
4026 ArrayRef<const char *> getRegMaskNames() const override;
4027 ArrayRef<const uint32_t *> getRegMasks() const override;
4028 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
4029 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
4030 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
4031 bool isConstantPhysReg(MCRegister PhysReg) const override final;
4032 /// Devirtualized TargetFrameLowering.
4033 static const HexagonFrameLowering *getFrameLowering(
4034 const MachineFunction &MF);
4035};
4036
4037namespace Hexagon { // Register classes
4038 extern const TargetRegisterClass UsrBitsRegClass;
4039 extern const TargetRegisterClass SysRegsRegClass;
4040 extern const TargetRegisterClass GuestRegsRegClass;
4041 extern const TargetRegisterClass IntRegsRegClass;
4042 extern const TargetRegisterClass CtrRegsRegClass;
4043 extern const TargetRegisterClass GeneralSubRegsRegClass;
4044 extern const TargetRegisterClass V62RegsRegClass;
4045 extern const TargetRegisterClass IntRegsLow8RegClass;
4046 extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass;
4047 extern const TargetRegisterClass PredRegsRegClass;
4048 extern const TargetRegisterClass V62Regs_with_isub_hiRegClass;
4049 extern const TargetRegisterClass ModRegsRegClass;
4050 extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass;
4051 extern const TargetRegisterClass V65RegsRegClass;
4052 extern const TargetRegisterClass SysRegs64RegClass;
4053 extern const TargetRegisterClass DoubleRegsRegClass;
4054 extern const TargetRegisterClass GuestRegs64RegClass;
4055 extern const TargetRegisterClass VectRegRevRegClass;
4056 extern const TargetRegisterClass CtrRegs64RegClass;
4057 extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass;
4058 extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass;
4059 extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass;
4060 extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass;
4061 extern const TargetRegisterClass HvxQRRegClass;
4062 extern const TargetRegisterClass HvxVRRegClass;
4063 extern const TargetRegisterClass HvxVR_and_V65RegsRegClass;
4064 extern const TargetRegisterClass HvxWRRegClass;
4065 extern const TargetRegisterClass HvxWR_and_VectRegRevRegClass;
4066 extern const TargetRegisterClass HvxVQRRegClass;
4067} // end namespace Hexagon
4068
4069} // end namespace llvm
4070
4071#endif // GET_REGINFO_HEADER
4072
4073/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
4074|* *|
4075|* Target Register and Register Classes Information *|
4076|* *|
4077|* Automatically generated file, do not edit! *|
4078|* *|
4079\*===----------------------------------------------------------------------===*/
4080
4081
4082#ifdef GET_REGINFO_TARGET_DESC
4083#undef GET_REGINFO_TARGET_DESC
4084
4085namespace llvm {
4086
4087extern const MCRegisterClass HexagonMCRegisterClasses[];
4088
4089static const MVT::SimpleValueType VTLists[] = {
4090 /* 0 */ MVT::i1, MVT::Other,
4091 /* 2 */ MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
4092 /* 10 */ MVT::i64, MVT::Other,
4093 /* 12 */ MVT::v64i1, MVT::v64i1, MVT::v32i1, MVT::v16i1, MVT::Other,
4094 /* 17 */ MVT::v128i1, MVT::v128i1, MVT::v64i1, MVT::v32i1, MVT::Other,
4095 /* 22 */ MVT::i32, MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
4096 /* 27 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::Other,
4097 /* 33 */ MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v32f16, MVT::v16f32, MVT::Other,
4098 /* 39 */ MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v64f16, MVT::v32f32, MVT::Other,
4099 /* 45 */ MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v128f16, MVT::v64f32, MVT::Other,
4100 /* 51 */ MVT::Untyped, MVT::Other,
4101};
4102
4103static const char *SubRegIndexNameTable[] = { "isub_hi", "isub_lo", "subreg_overflow", "vsub_fake", "vsub_hi", "vsub_lo", "wsub_hi", "wsub_lo", "wsub_hi_then_vsub_fake", "wsub_hi_then_vsub_hi", "wsub_hi_then_vsub_lo", "" };
4104
4105static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
4106 { 65535, 65535 },
4107 { 32, 32 }, // isub_hi
4108 { 0, 32 }, // isub_lo
4109 { 0, 1 }, // subreg_overflow
4110 { 65535, 65535 }, // vsub_fake
4111 { 65535, 65535 }, // vsub_hi
4112 { 65535, 65535 }, // vsub_lo
4113 { 65535, 65535 }, // wsub_hi
4114 { 65535, 65535 }, // wsub_lo
4115 { 65535, 65535 }, // wsub_hi_then_vsub_fake
4116 { 65535, 65535 }, // wsub_hi_then_vsub_hi
4117 { 65535, 65535 }, // wsub_hi_then_vsub_lo
4118 { 65535, 65535 },
4119 { 32, 32 }, // isub_hi
4120 { 0, 32 }, // isub_lo
4121 { 0, 1 }, // subreg_overflow
4122 { 65535, 65535 }, // vsub_fake
4123 { 65535, 65535 }, // vsub_hi
4124 { 65535, 65535 }, // vsub_lo
4125 { 65535, 65535 }, // wsub_hi
4126 { 65535, 65535 }, // wsub_lo
4127 { 65535, 65535 }, // wsub_hi_then_vsub_fake
4128 { 65535, 65535 }, // wsub_hi_then_vsub_hi
4129 { 65535, 65535 }, // wsub_hi_then_vsub_lo
4130 { 65535, 65535 },
4131 { 32, 32 }, // isub_hi
4132 { 0, 32 }, // isub_lo
4133 { 0, 1 }, // subreg_overflow
4134 { 65535, 65535 }, // vsub_fake
4135 { 65535, 65535 }, // vsub_hi
4136 { 65535, 65535 }, // vsub_lo
4137 { 65535, 65535 }, // wsub_hi
4138 { 65535, 65535 }, // wsub_lo
4139 { 65535, 65535 }, // wsub_hi_then_vsub_fake
4140 { 65535, 65535 }, // wsub_hi_then_vsub_hi
4141 { 65535, 65535 }, // wsub_hi_then_vsub_lo
4142};
4143
4144
4145static const LaneBitmask SubRegIndexLaneMaskTable[] = {
4146 LaneBitmask::getAll(),
4147 LaneBitmask(0x0000000000000001), // isub_hi
4148 LaneBitmask(0x0000000000000002), // isub_lo
4149 LaneBitmask(0x0000000000000004), // subreg_overflow
4150 LaneBitmask(0x0000000000000008), // vsub_fake
4151 LaneBitmask(0x0000000000000010), // vsub_hi
4152 LaneBitmask(0x0000000000000020), // vsub_lo
4153 LaneBitmask(0x00000000000001C0), // wsub_hi
4154 LaneBitmask(0x0000000000000038), // wsub_lo
4155 LaneBitmask(0x0000000000000040), // wsub_hi_then_vsub_fake
4156 LaneBitmask(0x0000000000000080), // wsub_hi_then_vsub_hi
4157 LaneBitmask(0x0000000000000100), // wsub_hi_then_vsub_lo
4158 };
4159
4160
4161
4162static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
4163 // Mode = 0 (Default)
4164 { 1, 1, 0, /*VTLists+*/0 }, // UsrBits
4165 { 32, 32, 32, /*VTLists+*/8 }, // SysRegs
4166 { 32, 32, 32, /*VTLists+*/8 }, // GuestRegs
4167 { 32, 32, 32, /*VTLists+*/22 }, // IntRegs
4168 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs
4169 { 32, 32, 32, /*VTLists+*/8 }, // GeneralSubRegs
4170 { 32, 32, 32, /*VTLists+*/8 }, // V62Regs
4171 { 32, 32, 32, /*VTLists+*/8 }, // IntRegsLow8
4172 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs_and_V62Regs
4173 { 32, 32, 32, /*VTLists+*/2 }, // PredRegs
4174 { 32, 32, 32, /*VTLists+*/8 }, // V62Regs_with_isub_hi
4175 { 32, 32, 32, /*VTLists+*/8 }, // ModRegs
4176 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs_with_subreg_overflow
4177 { 32, 32, 32, /*VTLists+*/8 }, // V65Regs
4178 { 64, 64, 64, /*VTLists+*/10 }, // SysRegs64
4179 { 64, 64, 64, /*VTLists+*/27 }, // DoubleRegs
4180 { 64, 64, 64, /*VTLists+*/10 }, // GuestRegs64
4181 { 64, 64, 64, /*VTLists+*/10 }, // VectRegRev
4182 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64
4183 { 64, 64, 64, /*VTLists+*/10 }, // GeneralDoubleLow8Regs
4184 { 64, 64, 64, /*VTLists+*/10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
4185 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64_and_V62Regs
4186 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64_with_isub_hi_in_ModRegs
4187 { 64, 512, 512, /*VTLists+*/12 }, // HvxQR
4188 { 512, 512, 512, /*VTLists+*/33 }, // HvxVR
4189 { 512, 512, 512, /*VTLists+*/33 }, // HvxVR_and_V65Regs
4190 { 1024, 1024, 512, /*VTLists+*/39 }, // HvxWR
4191 { 1024, 1024, 512, /*VTLists+*/39 }, // HvxWR_and_VectRegRev
4192 { 2048, 2048, 512, /*VTLists+*/51 }, // HvxVQR
4193 // Mode = 1 (Hvx64)
4194 { 1, 1, 0, /*VTLists+*/0 }, // UsrBits
4195 { 32, 32, 32, /*VTLists+*/8 }, // SysRegs
4196 { 32, 32, 32, /*VTLists+*/8 }, // GuestRegs
4197 { 32, 32, 32, /*VTLists+*/22 }, // IntRegs
4198 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs
4199 { 32, 32, 32, /*VTLists+*/8 }, // GeneralSubRegs
4200 { 32, 32, 32, /*VTLists+*/8 }, // V62Regs
4201 { 32, 32, 32, /*VTLists+*/8 }, // IntRegsLow8
4202 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs_and_V62Regs
4203 { 32, 32, 32, /*VTLists+*/2 }, // PredRegs
4204 { 32, 32, 32, /*VTLists+*/8 }, // V62Regs_with_isub_hi
4205 { 32, 32, 32, /*VTLists+*/8 }, // ModRegs
4206 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs_with_subreg_overflow
4207 { 32, 32, 32, /*VTLists+*/8 }, // V65Regs
4208 { 64, 64, 64, /*VTLists+*/10 }, // SysRegs64
4209 { 64, 64, 64, /*VTLists+*/27 }, // DoubleRegs
4210 { 64, 64, 64, /*VTLists+*/10 }, // GuestRegs64
4211 { 64, 64, 64, /*VTLists+*/10 }, // VectRegRev
4212 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64
4213 { 64, 64, 64, /*VTLists+*/10 }, // GeneralDoubleLow8Regs
4214 { 64, 64, 64, /*VTLists+*/10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
4215 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64_and_V62Regs
4216 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64_with_isub_hi_in_ModRegs
4217 { 64, 512, 512, /*VTLists+*/12 }, // HvxQR
4218 { 512, 512, 512, /*VTLists+*/33 }, // HvxVR
4219 { 512, 512, 512, /*VTLists+*/33 }, // HvxVR_and_V65Regs
4220 { 1024, 1024, 512, /*VTLists+*/39 }, // HvxWR
4221 { 1024, 1024, 512, /*VTLists+*/39 }, // HvxWR_and_VectRegRev
4222 { 2048, 2048, 512, /*VTLists+*/51 }, // HvxVQR
4223 // Mode = 2 (Hvx128)
4224 { 1, 1, 0, /*VTLists+*/0 }, // UsrBits
4225 { 32, 32, 32, /*VTLists+*/8 }, // SysRegs
4226 { 32, 32, 32, /*VTLists+*/8 }, // GuestRegs
4227 { 32, 32, 32, /*VTLists+*/22 }, // IntRegs
4228 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs
4229 { 32, 32, 32, /*VTLists+*/8 }, // GeneralSubRegs
4230 { 32, 32, 32, /*VTLists+*/8 }, // V62Regs
4231 { 32, 32, 32, /*VTLists+*/8 }, // IntRegsLow8
4232 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs_and_V62Regs
4233 { 32, 32, 32, /*VTLists+*/2 }, // PredRegs
4234 { 32, 32, 32, /*VTLists+*/8 }, // V62Regs_with_isub_hi
4235 { 32, 32, 32, /*VTLists+*/8 }, // ModRegs
4236 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs_with_subreg_overflow
4237 { 32, 32, 32, /*VTLists+*/8 }, // V65Regs
4238 { 64, 64, 64, /*VTLists+*/10 }, // SysRegs64
4239 { 64, 64, 64, /*VTLists+*/27 }, // DoubleRegs
4240 { 64, 64, 64, /*VTLists+*/10 }, // GuestRegs64
4241 { 64, 64, 64, /*VTLists+*/10 }, // VectRegRev
4242 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64
4243 { 64, 64, 64, /*VTLists+*/10 }, // GeneralDoubleLow8Regs
4244 { 64, 64, 64, /*VTLists+*/10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
4245 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64_and_V62Regs
4246 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64_with_isub_hi_in_ModRegs
4247 { 128, 1024, 1024, /*VTLists+*/17 }, // HvxQR
4248 { 1024, 1024, 1024, /*VTLists+*/39 }, // HvxVR
4249 { 1024, 1024, 1024, /*VTLists+*/39 }, // HvxVR_and_V65Regs
4250 { 2048, 2048, 1024, /*VTLists+*/45 }, // HvxWR
4251 { 2048, 2048, 1024, /*VTLists+*/45 }, // HvxWR_and_VectRegRev
4252 { 4096, 4096, 1024, /*VTLists+*/51 }, // HvxVQR
4253};
4254
4255static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4256
4257static const uint32_t UsrBitsSubClassMask[] = {
4258 0x00000001,
4259 0x00001000, // subreg_overflow
4260};
4261
4262static const uint32_t SysRegsSubClassMask[] = {
4263 0x00000002,
4264 0x00004000, // isub_hi
4265 0x00004000, // isub_lo
4266};
4267
4268static const uint32_t GuestRegsSubClassMask[] = {
4269 0x00000004,
4270 0x00010000, // isub_hi
4271 0x00010000, // isub_lo
4272};
4273
4274static const uint32_t IntRegsSubClassMask[] = {
4275 0x000000a8,
4276 0x00188000, // isub_hi
4277 0x00188000, // isub_lo
4278};
4279
4280static const uint32_t CtrRegsSubClassMask[] = {
4281 0x00001910,
4282 0x00640400, // isub_hi
4283 0x00640400, // isub_lo
4284};
4285
4286static const uint32_t GeneralSubRegsSubClassMask[] = {
4287 0x000000a0,
4288 0x00180000, // isub_hi
4289 0x00180000, // isub_lo
4290};
4291
4292static const uint32_t V62RegsSubClassMask[] = {
4293 0x00200540,
4294 0x00200400, // isub_hi
4295 0x00200400, // isub_lo
4296};
4297
4298static const uint32_t IntRegsLow8SubClassMask[] = {
4299 0x00000080,
4300 0x00100000, // isub_hi
4301 0x00100000, // isub_lo
4302};
4303
4304static const uint32_t CtrRegs_and_V62RegsSubClassMask[] = {
4305 0x00000100,
4306 0x00200400, // isub_hi
4307 0x00200400, // isub_lo
4308};
4309
4310static const uint32_t PredRegsSubClassMask[] = {
4311 0x00000200,
4312};
4313
4314static const uint32_t V62Regs_with_isub_hiSubClassMask[] = {
4315 0x00200400,
4316};
4317
4318static const uint32_t ModRegsSubClassMask[] = {
4319 0x00000800,
4320 0x00400000, // isub_hi
4321 0x00400000, // isub_lo
4322};
4323
4324static const uint32_t CtrRegs_with_subreg_overflowSubClassMask[] = {
4325 0x00001000,
4326};
4327
4328static const uint32_t V65RegsSubClassMask[] = {
4329 0x02002000,
4330};
4331
4332static const uint32_t SysRegs64SubClassMask[] = {
4333 0x00004000,
4334};
4335
4336static const uint32_t DoubleRegsSubClassMask[] = {
4337 0x00188000,
4338};
4339
4340static const uint32_t GuestRegs64SubClassMask[] = {
4341 0x00010000,
4342};
4343
4344static const uint32_t VectRegRevSubClassMask[] = {
4345 0x08020000,
4346};
4347
4348static const uint32_t CtrRegs64SubClassMask[] = {
4349 0x00640000,
4350};
4351
4352static const uint32_t GeneralDoubleLow8RegsSubClassMask[] = {
4353 0x00180000,
4354};
4355
4356static const uint32_t DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask[] = {
4357 0x00100000,
4358};
4359
4360static const uint32_t CtrRegs64_and_V62RegsSubClassMask[] = {
4361 0x00200000,
4362};
4363
4364static const uint32_t CtrRegs64_with_isub_hi_in_ModRegsSubClassMask[] = {
4365 0x00400000,
4366};
4367
4368static const uint32_t HvxQRSubClassMask[] = {
4369 0x00800000,
4370};
4371
4372static const uint32_t HvxVRSubClassMask[] = {
4373 0x03000000,
4374 0x1c020000, // vsub_hi
4375 0x1c020000, // vsub_lo
4376 0x10000000, // wsub_hi_then_vsub_hi
4377 0x10000000, // wsub_hi_then_vsub_lo
4378};
4379
4380static const uint32_t HvxVR_and_V65RegsSubClassMask[] = {
4381 0x02000000,
4382};
4383
4384static const uint32_t HvxWRSubClassMask[] = {
4385 0x0c000000,
4386 0x10000000, // wsub_hi
4387 0x10000000, // wsub_lo
4388};
4389
4390static const uint32_t HvxWR_and_VectRegRevSubClassMask[] = {
4391 0x08000000,
4392};
4393
4394static const uint32_t HvxVQRSubClassMask[] = {
4395 0x10000000,
4396};
4397
4398static const uint16_t SuperRegIdxSeqs[] = {
4399 /* 0 */ 1, 2, 0,
4400 /* 3 */ 3, 0,
4401 /* 5 */ 7, 8, 0,
4402 /* 8 */ 5, 6, 10, 11, 0,
4403};
4404
4405static const TargetRegisterClass *const GeneralSubRegsSuperclasses[] = {
4406 &Hexagon::IntRegsRegClass,
4407 nullptr
4408};
4409
4410static const TargetRegisterClass *const IntRegsLow8Superclasses[] = {
4411 &Hexagon::IntRegsRegClass,
4412 &Hexagon::GeneralSubRegsRegClass,
4413 nullptr
4414};
4415
4416static const TargetRegisterClass *const CtrRegs_and_V62RegsSuperclasses[] = {
4417 &Hexagon::CtrRegsRegClass,
4418 &Hexagon::V62RegsRegClass,
4419 nullptr
4420};
4421
4422static const TargetRegisterClass *const V62Regs_with_isub_hiSuperclasses[] = {
4423 &Hexagon::V62RegsRegClass,
4424 nullptr
4425};
4426
4427static const TargetRegisterClass *const ModRegsSuperclasses[] = {
4428 &Hexagon::CtrRegsRegClass,
4429 nullptr
4430};
4431
4432static const TargetRegisterClass *const CtrRegs_with_subreg_overflowSuperclasses[] = {
4433 &Hexagon::CtrRegsRegClass,
4434 nullptr
4435};
4436
4437static const TargetRegisterClass *const GeneralDoubleLow8RegsSuperclasses[] = {
4438 &Hexagon::DoubleRegsRegClass,
4439 nullptr
4440};
4441
4442static const TargetRegisterClass *const DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses[] = {
4443 &Hexagon::DoubleRegsRegClass,
4444 &Hexagon::GeneralDoubleLow8RegsRegClass,
4445 nullptr
4446};
4447
4448static const TargetRegisterClass *const CtrRegs64_and_V62RegsSuperclasses[] = {
4449 &Hexagon::V62RegsRegClass,
4450 &Hexagon::V62Regs_with_isub_hiRegClass,
4451 &Hexagon::CtrRegs64RegClass,
4452 nullptr
4453};
4454
4455static const TargetRegisterClass *const CtrRegs64_with_isub_hi_in_ModRegsSuperclasses[] = {
4456 &Hexagon::CtrRegs64RegClass,
4457 nullptr
4458};
4459
4460static const TargetRegisterClass *const HvxVR_and_V65RegsSuperclasses[] = {
4461 &Hexagon::V65RegsRegClass,
4462 &Hexagon::HvxVRRegClass,
4463 nullptr
4464};
4465
4466static const TargetRegisterClass *const HvxWR_and_VectRegRevSuperclasses[] = {
4467 &Hexagon::VectRegRevRegClass,
4468 &Hexagon::HvxWRRegClass,
4469 nullptr
4470};
4471
4472
4473namespace Hexagon { // Register class instances
4474 extern const TargetRegisterClass UsrBitsRegClass = {
4475 &HexagonMCRegisterClasses[UsrBitsRegClassID],
4476 UsrBitsSubClassMask,
4477 SuperRegIdxSeqs + 3,
4478 LaneBitmask(0x0000000000000001),
4479 0,
4480 false,
4481 0x00, /* TSFlags */
4482 false, /* HasDisjunctSubRegs */
4483 false, /* CoveredBySubRegs */
4484 NullRegClasses,
4485 nullptr
4486 };
4487
4488 extern const TargetRegisterClass SysRegsRegClass = {
4489 &HexagonMCRegisterClasses[SysRegsRegClassID],
4490 SysRegsSubClassMask,
4491 SuperRegIdxSeqs + 0,
4492 LaneBitmask(0x0000000000000001),
4493 0,
4494 false,
4495 0x00, /* TSFlags */
4496 false, /* HasDisjunctSubRegs */
4497 false, /* CoveredBySubRegs */
4498 NullRegClasses,
4499 nullptr
4500 };
4501
4502 extern const TargetRegisterClass GuestRegsRegClass = {
4503 &HexagonMCRegisterClasses[GuestRegsRegClassID],
4504 GuestRegsSubClassMask,
4505 SuperRegIdxSeqs + 0,
4506 LaneBitmask(0x0000000000000001),
4507 0,
4508 false,
4509 0x00, /* TSFlags */
4510 false, /* HasDisjunctSubRegs */
4511 false, /* CoveredBySubRegs */
4512 NullRegClasses,
4513 nullptr
4514 };
4515
4516 extern const TargetRegisterClass IntRegsRegClass = {
4517 &HexagonMCRegisterClasses[IntRegsRegClassID],
4518 IntRegsSubClassMask,
4519 SuperRegIdxSeqs + 0,
4520 LaneBitmask(0x0000000000000001),
4521 0,
4522 false,
4523 0x00, /* TSFlags */
4524 false, /* HasDisjunctSubRegs */
4525 false, /* CoveredBySubRegs */
4526 NullRegClasses,
4527 nullptr
4528 };
4529
4530 extern const TargetRegisterClass CtrRegsRegClass = {
4531 &HexagonMCRegisterClasses[CtrRegsRegClassID],
4532 CtrRegsSubClassMask,
4533 SuperRegIdxSeqs + 0,
4534 LaneBitmask(0x0000000000000004),
4535 0,
4536 false,
4537 0x00, /* TSFlags */
4538 false, /* HasDisjunctSubRegs */
4539 false, /* CoveredBySubRegs */
4540 NullRegClasses,
4541 nullptr
4542 };
4543
4544 extern const TargetRegisterClass GeneralSubRegsRegClass = {
4545 &HexagonMCRegisterClasses[GeneralSubRegsRegClassID],
4546 GeneralSubRegsSubClassMask,
4547 SuperRegIdxSeqs + 0,
4548 LaneBitmask(0x0000000000000001),
4549 0,
4550 false,
4551 0x00, /* TSFlags */
4552 false, /* HasDisjunctSubRegs */
4553 false, /* CoveredBySubRegs */
4554 GeneralSubRegsSuperclasses,
4555 nullptr
4556 };
4557
4558 extern const TargetRegisterClass V62RegsRegClass = {
4559 &HexagonMCRegisterClasses[V62RegsRegClassID],
4560 V62RegsSubClassMask,
4561 SuperRegIdxSeqs + 0,
4562 LaneBitmask(0x0000000000000003),
4563 0,
4564 false,
4565 0x00, /* TSFlags */
4566 true, /* HasDisjunctSubRegs */
4567 false, /* CoveredBySubRegs */
4568 NullRegClasses,
4569 nullptr
4570 };
4571
4572 extern const TargetRegisterClass IntRegsLow8RegClass = {
4573 &HexagonMCRegisterClasses[IntRegsLow8RegClassID],
4574 IntRegsLow8SubClassMask,
4575 SuperRegIdxSeqs + 0,
4576 LaneBitmask(0x0000000000000001),
4577 0,
4578 false,
4579 0x00, /* TSFlags */
4580 false, /* HasDisjunctSubRegs */
4581 false, /* CoveredBySubRegs */
4582 IntRegsLow8Superclasses,
4583 nullptr
4584 };
4585
4586 extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass = {
4587 &HexagonMCRegisterClasses[CtrRegs_and_V62RegsRegClassID],
4588 CtrRegs_and_V62RegsSubClassMask,
4589 SuperRegIdxSeqs + 0,
4590 LaneBitmask(0x0000000000000001),
4591 0,
4592 false,
4593 0x00, /* TSFlags */
4594 false, /* HasDisjunctSubRegs */
4595 false, /* CoveredBySubRegs */
4596 CtrRegs_and_V62RegsSuperclasses,
4597 nullptr
4598 };
4599
4600 extern const TargetRegisterClass PredRegsRegClass = {
4601 &HexagonMCRegisterClasses[PredRegsRegClassID],
4602 PredRegsSubClassMask,
4603 SuperRegIdxSeqs + 2,
4604 LaneBitmask(0x0000000000000001),
4605 0,
4606 false,
4607 0x00, /* TSFlags */
4608 false, /* HasDisjunctSubRegs */
4609 false, /* CoveredBySubRegs */
4610 NullRegClasses,
4611 nullptr
4612 };
4613
4614 extern const TargetRegisterClass V62Regs_with_isub_hiRegClass = {
4615 &HexagonMCRegisterClasses[V62Regs_with_isub_hiRegClassID],
4616 V62Regs_with_isub_hiSubClassMask,
4617 SuperRegIdxSeqs + 2,
4618 LaneBitmask(0x0000000000000003),
4619 0,
4620 false,
4621 0x00, /* TSFlags */
4622 true, /* HasDisjunctSubRegs */
4623 true, /* CoveredBySubRegs */
4624 V62Regs_with_isub_hiSuperclasses,
4625 nullptr
4626 };
4627
4628 extern const TargetRegisterClass ModRegsRegClass = {
4629 &HexagonMCRegisterClasses[ModRegsRegClassID],
4630 ModRegsSubClassMask,
4631 SuperRegIdxSeqs + 0,
4632 LaneBitmask(0x0000000000000001),
4633 0,
4634 false,
4635 0x00, /* TSFlags */
4636 false, /* HasDisjunctSubRegs */
4637 false, /* CoveredBySubRegs */
4638 ModRegsSuperclasses,
4639 nullptr
4640 };
4641
4642 extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass = {
4643 &HexagonMCRegisterClasses[CtrRegs_with_subreg_overflowRegClassID],
4644 CtrRegs_with_subreg_overflowSubClassMask,
4645 SuperRegIdxSeqs + 2,
4646 LaneBitmask(0x0000000000000004),
4647 0,
4648 false,
4649 0x00, /* TSFlags */
4650 false, /* HasDisjunctSubRegs */
4651 false, /* CoveredBySubRegs */
4652 CtrRegs_with_subreg_overflowSuperclasses,
4653 nullptr
4654 };
4655
4656 extern const TargetRegisterClass V65RegsRegClass = {
4657 &HexagonMCRegisterClasses[V65RegsRegClassID],
4658 V65RegsSubClassMask,
4659 SuperRegIdxSeqs + 2,
4660 LaneBitmask(0x0000000000000001),
4661 0,
4662 false,
4663 0x00, /* TSFlags */
4664 false, /* HasDisjunctSubRegs */
4665 false, /* CoveredBySubRegs */
4666 NullRegClasses,
4667 nullptr
4668 };
4669
4670 extern const TargetRegisterClass SysRegs64RegClass = {
4671 &HexagonMCRegisterClasses[SysRegs64RegClassID],
4672 SysRegs64SubClassMask,
4673 SuperRegIdxSeqs + 2,
4674 LaneBitmask(0x0000000000000003),
4675 0,
4676 false,
4677 0x00, /* TSFlags */
4678 true, /* HasDisjunctSubRegs */
4679 true, /* CoveredBySubRegs */
4680 NullRegClasses,
4681 nullptr
4682 };
4683
4684 extern const TargetRegisterClass DoubleRegsRegClass = {
4685 &HexagonMCRegisterClasses[DoubleRegsRegClassID],
4686 DoubleRegsSubClassMask,
4687 SuperRegIdxSeqs + 2,
4688 LaneBitmask(0x0000000000000003),
4689 0,
4690 false,
4691 0x00, /* TSFlags */
4692 true, /* HasDisjunctSubRegs */
4693 true, /* CoveredBySubRegs */
4694 NullRegClasses,
4695 nullptr
4696 };
4697
4698 extern const TargetRegisterClass GuestRegs64RegClass = {
4699 &HexagonMCRegisterClasses[GuestRegs64RegClassID],
4700 GuestRegs64SubClassMask,
4701 SuperRegIdxSeqs + 2,
4702 LaneBitmask(0x0000000000000003),
4703 0,
4704 false,
4705 0x00, /* TSFlags */
4706 true, /* HasDisjunctSubRegs */
4707 true, /* CoveredBySubRegs */
4708 NullRegClasses,
4709 nullptr
4710 };
4711
4712 extern const TargetRegisterClass VectRegRevRegClass = {
4713 &HexagonMCRegisterClasses[VectRegRevRegClassID],
4714 VectRegRevSubClassMask,
4715 SuperRegIdxSeqs + 2,
4716 LaneBitmask(0x0000000000000030),
4717 0,
4718 false,
4719 0x00, /* TSFlags */
4720 true, /* HasDisjunctSubRegs */
4721 true, /* CoveredBySubRegs */
4722 NullRegClasses,
4723 nullptr
4724 };
4725
4726 extern const TargetRegisterClass CtrRegs64RegClass = {
4727 &HexagonMCRegisterClasses[CtrRegs64RegClassID],
4728 CtrRegs64SubClassMask,
4729 SuperRegIdxSeqs + 2,
4730 LaneBitmask(0x0000000000000003),
4731 0,
4732 false,
4733 0x00, /* TSFlags */
4734 true, /* HasDisjunctSubRegs */
4735 true, /* CoveredBySubRegs */
4736 NullRegClasses,
4737 nullptr
4738 };
4739
4740 extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass = {
4741 &HexagonMCRegisterClasses[GeneralDoubleLow8RegsRegClassID],
4742 GeneralDoubleLow8RegsSubClassMask,
4743 SuperRegIdxSeqs + 2,
4744 LaneBitmask(0x0000000000000003),
4745 0,
4746 false,
4747 0x00, /* TSFlags */
4748 true, /* HasDisjunctSubRegs */
4749 true, /* CoveredBySubRegs */
4750 GeneralDoubleLow8RegsSuperclasses,
4751 nullptr
4752 };
4753
4754 extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass = {
4755 &HexagonMCRegisterClasses[DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID],
4756 DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask,
4757 SuperRegIdxSeqs + 2,
4758 LaneBitmask(0x0000000000000003),
4759 0,
4760 false,
4761 0x00, /* TSFlags */
4762 true, /* HasDisjunctSubRegs */
4763 true, /* CoveredBySubRegs */
4764 DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses,
4765 nullptr
4766 };
4767
4768 extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass = {
4769 &HexagonMCRegisterClasses[CtrRegs64_and_V62RegsRegClassID],
4770 CtrRegs64_and_V62RegsSubClassMask,
4771 SuperRegIdxSeqs + 2,
4772 LaneBitmask(0x0000000000000003),
4773 0,
4774 false,
4775 0x00, /* TSFlags */
4776 true, /* HasDisjunctSubRegs */
4777 true, /* CoveredBySubRegs */
4778 CtrRegs64_and_V62RegsSuperclasses,
4779 nullptr
4780 };
4781
4782 extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass = {
4783 &HexagonMCRegisterClasses[CtrRegs64_with_isub_hi_in_ModRegsRegClassID],
4784 CtrRegs64_with_isub_hi_in_ModRegsSubClassMask,
4785 SuperRegIdxSeqs + 2,
4786 LaneBitmask(0x0000000000000003),
4787 0,
4788 false,
4789 0x00, /* TSFlags */
4790 true, /* HasDisjunctSubRegs */
4791 true, /* CoveredBySubRegs */
4792 CtrRegs64_with_isub_hi_in_ModRegsSuperclasses,
4793 nullptr
4794 };
4795
4796 extern const TargetRegisterClass HvxQRRegClass = {
4797 &HexagonMCRegisterClasses[HvxQRRegClassID],
4798 HvxQRSubClassMask,
4799 SuperRegIdxSeqs + 2,
4800 LaneBitmask(0x0000000000000001),
4801 0,
4802 false,
4803 0x00, /* TSFlags */
4804 false, /* HasDisjunctSubRegs */
4805 false, /* CoveredBySubRegs */
4806 NullRegClasses,
4807 nullptr
4808 };
4809
4810 extern const TargetRegisterClass HvxVRRegClass = {
4811 &HexagonMCRegisterClasses[HvxVRRegClassID],
4812 HvxVRSubClassMask,
4813 SuperRegIdxSeqs + 8,
4814 LaneBitmask(0x0000000000000001),
4815 0,
4816 false,
4817 0x00, /* TSFlags */
4818 false, /* HasDisjunctSubRegs */
4819 false, /* CoveredBySubRegs */
4820 NullRegClasses,
4821 nullptr
4822 };
4823
4824 extern const TargetRegisterClass HvxVR_and_V65RegsRegClass = {
4825 &HexagonMCRegisterClasses[HvxVR_and_V65RegsRegClassID],
4826 HvxVR_and_V65RegsSubClassMask,
4827 SuperRegIdxSeqs + 2,
4828 LaneBitmask(0x0000000000000001),
4829 0,
4830 false,
4831 0x00, /* TSFlags */
4832 false, /* HasDisjunctSubRegs */
4833 false, /* CoveredBySubRegs */
4834 HvxVR_and_V65RegsSuperclasses,
4835 nullptr
4836 };
4837
4838 extern const TargetRegisterClass HvxWRRegClass = {
4839 &HexagonMCRegisterClasses[HvxWRRegClassID],
4840 HvxWRSubClassMask,
4841 SuperRegIdxSeqs + 5,
4842 LaneBitmask(0x0000000000000030),
4843 0,
4844 false,
4845 0x00, /* TSFlags */
4846 true, /* HasDisjunctSubRegs */
4847 true, /* CoveredBySubRegs */
4848 NullRegClasses,
4849 nullptr
4850 };
4851
4852 extern const TargetRegisterClass HvxWR_and_VectRegRevRegClass = {
4853 &HexagonMCRegisterClasses[HvxWR_and_VectRegRevRegClassID],
4854 HvxWR_and_VectRegRevSubClassMask,
4855 SuperRegIdxSeqs + 2,
4856 LaneBitmask(0x0000000000000030),
4857 0,
4858 false,
4859 0x00, /* TSFlags */
4860 true, /* HasDisjunctSubRegs */
4861 true, /* CoveredBySubRegs */
4862 HvxWR_and_VectRegRevSuperclasses,
4863 nullptr
4864 };
4865
4866 extern const TargetRegisterClass HvxVQRRegClass = {
4867 &HexagonMCRegisterClasses[HvxVQRRegClassID],
4868 HvxVQRSubClassMask,
4869 SuperRegIdxSeqs + 2,
4870 LaneBitmask(0x00000000000001F8),
4871 0,
4872 false,
4873 0x00, /* TSFlags */
4874 true, /* HasDisjunctSubRegs */
4875 true, /* CoveredBySubRegs */
4876 NullRegClasses,
4877 nullptr
4878 };
4879
4880} // end namespace Hexagon
4881
4882namespace {
4883 const TargetRegisterClass *const RegisterClasses[] = {
4884 &Hexagon::UsrBitsRegClass,
4885 &Hexagon::SysRegsRegClass,
4886 &Hexagon::GuestRegsRegClass,
4887 &Hexagon::IntRegsRegClass,
4888 &Hexagon::CtrRegsRegClass,
4889 &Hexagon::GeneralSubRegsRegClass,
4890 &Hexagon::V62RegsRegClass,
4891 &Hexagon::IntRegsLow8RegClass,
4892 &Hexagon::CtrRegs_and_V62RegsRegClass,
4893 &Hexagon::PredRegsRegClass,
4894 &Hexagon::V62Regs_with_isub_hiRegClass,
4895 &Hexagon::ModRegsRegClass,
4896 &Hexagon::CtrRegs_with_subreg_overflowRegClass,
4897 &Hexagon::V65RegsRegClass,
4898 &Hexagon::SysRegs64RegClass,
4899 &Hexagon::DoubleRegsRegClass,
4900 &Hexagon::GuestRegs64RegClass,
4901 &Hexagon::VectRegRevRegClass,
4902 &Hexagon::CtrRegs64RegClass,
4903 &Hexagon::GeneralDoubleLow8RegsRegClass,
4904 &Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass,
4905 &Hexagon::CtrRegs64_and_V62RegsRegClass,
4906 &Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClass,
4907 &Hexagon::HvxQRRegClass,
4908 &Hexagon::HvxVRRegClass,
4909 &Hexagon::HvxVR_and_V65RegsRegClass,
4910 &Hexagon::HvxWRRegClass,
4911 &Hexagon::HvxWR_and_VectRegRevRegClass,
4912 &Hexagon::HvxVQRRegClass,
4913 };
4914} // end anonymous namespace
4915
4916static const uint8_t CostPerUseTable[] = {
49170, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
4918
4919
4920static const bool InAllocatableClassTable[] = {
4921false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
4922
4923
4924static const TargetRegisterInfoDesc HexagonRegInfoDesc = { // Extra Descriptors
4925CostPerUseTable, 1, InAllocatableClassTable};
4926
4927unsigned HexagonGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
4928 static const uint8_t RowMap[11] = {
4929 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
4930 };
4931 static const uint8_t Rows[2][11] = {
4932 { 0, 0, 0, Hexagon::wsub_hi_then_vsub_fake, Hexagon::wsub_hi_then_vsub_hi, Hexagon::wsub_hi_then_vsub_lo, 0, 0, 0, 0, 0, },
4933 { 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, 0, },
4934 };
4935
4936 --IdxA; assert(IdxA < 11); (void) IdxA;
4937 --IdxB; assert(IdxB < 11);
4938 return Rows[RowMap[IdxA]][IdxB];
4939}
4940
4941 struct MaskRolOp {
4942 LaneBitmask Mask;
4943 uint8_t RotateLeft;
4944 };
4945 static const MaskRolOp LaneMaskComposeSequences[] = {
4946 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
4947 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
4948 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
4949 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
4950 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
4951 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10
4952 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 12
4953 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 14
4954 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 } // Sequence 16
4955 };
4956 static const uint8_t CompositeSequences[] = {
4957 0, // to isub_hi
4958 2, // to isub_lo
4959 4, // to subreg_overflow
4960 6, // to vsub_fake
4961 8, // to vsub_hi
4962 10, // to vsub_lo
4963 6, // to wsub_hi
4964 0, // to wsub_lo
4965 12, // to wsub_hi_then_vsub_fake
4966 14, // to wsub_hi_then_vsub_hi
4967 16 // to wsub_hi_then_vsub_lo
4968 };
4969
4970LaneBitmask HexagonGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
4971 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
4972 LaneBitmask Result;
4973 for (const MaskRolOp *Ops =
4974 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
4975 Ops->Mask.any(); ++Ops) {
4976 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
4977 if (unsigned S = Ops->RotateLeft)
4978 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
4979 else
4980 Result |= LaneBitmask(M);
4981 }
4982 return Result;
4983}
4984
4985LaneBitmask HexagonGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
4986 LaneMask &= getSubRegIndexLaneMask(IdxA);
4987 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
4988 LaneBitmask Result;
4989 for (const MaskRolOp *Ops =
4990 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
4991 Ops->Mask.any(); ++Ops) {
4992 LaneBitmask::Type M = LaneMask.getAsInteger();
4993 if (unsigned S = Ops->RotateLeft)
4994 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
4995 else
4996 Result |= LaneBitmask(M);
4997 }
4998 return Result;
4999}
5000
5001const TargetRegisterClass *HexagonGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
5002 static const uint8_t Table[29][11] = {
5003 { // UsrBits
5004 0, // isub_hi
5005 0, // isub_lo
5006 0, // subreg_overflow
5007 0, // vsub_fake
5008 0, // vsub_hi
5009 0, // vsub_lo
5010 0, // wsub_hi
5011 0, // wsub_lo
5012 0, // wsub_hi_then_vsub_fake
5013 0, // wsub_hi_then_vsub_hi
5014 0, // wsub_hi_then_vsub_lo
5015 },
5016 { // SysRegs
5017 0, // isub_hi
5018 0, // isub_lo
5019 0, // subreg_overflow
5020 0, // vsub_fake
5021 0, // vsub_hi
5022 0, // vsub_lo
5023 0, // wsub_hi
5024 0, // wsub_lo
5025 0, // wsub_hi_then_vsub_fake
5026 0, // wsub_hi_then_vsub_hi
5027 0, // wsub_hi_then_vsub_lo
5028 },
5029 { // GuestRegs
5030 0, // isub_hi
5031 0, // isub_lo
5032 0, // subreg_overflow
5033 0, // vsub_fake
5034 0, // vsub_hi
5035 0, // vsub_lo
5036 0, // wsub_hi
5037 0, // wsub_lo
5038 0, // wsub_hi_then_vsub_fake
5039 0, // wsub_hi_then_vsub_hi
5040 0, // wsub_hi_then_vsub_lo
5041 },
5042 { // IntRegs
5043 0, // isub_hi
5044 0, // isub_lo
5045 0, // subreg_overflow
5046 0, // vsub_fake
5047 0, // vsub_hi
5048 0, // vsub_lo
5049 0, // wsub_hi
5050 0, // wsub_lo
5051 0, // wsub_hi_then_vsub_fake
5052 0, // wsub_hi_then_vsub_hi
5053 0, // wsub_hi_then_vsub_lo
5054 },
5055 { // CtrRegs
5056 0, // isub_hi
5057 0, // isub_lo
5058 13, // subreg_overflow -> CtrRegs_with_subreg_overflow
5059 0, // vsub_fake
5060 0, // vsub_hi
5061 0, // vsub_lo
5062 0, // wsub_hi
5063 0, // wsub_lo
5064 0, // wsub_hi_then_vsub_fake
5065 0, // wsub_hi_then_vsub_hi
5066 0, // wsub_hi_then_vsub_lo
5067 },
5068 { // GeneralSubRegs
5069 0, // isub_hi
5070 0, // isub_lo
5071 0, // subreg_overflow
5072 0, // vsub_fake
5073 0, // vsub_hi
5074 0, // vsub_lo
5075 0, // wsub_hi
5076 0, // wsub_lo
5077 0, // wsub_hi_then_vsub_fake
5078 0, // wsub_hi_then_vsub_hi
5079 0, // wsub_hi_then_vsub_lo
5080 },
5081 { // V62Regs
5082 11, // isub_hi -> V62Regs_with_isub_hi
5083 11, // isub_lo -> V62Regs_with_isub_hi
5084 0, // subreg_overflow
5085 0, // vsub_fake
5086 0, // vsub_hi
5087 0, // vsub_lo
5088 0, // wsub_hi
5089 0, // wsub_lo
5090 0, // wsub_hi_then_vsub_fake
5091 0, // wsub_hi_then_vsub_hi
5092 0, // wsub_hi_then_vsub_lo
5093 },
5094 { // IntRegsLow8
5095 0, // isub_hi
5096 0, // isub_lo
5097 0, // subreg_overflow
5098 0, // vsub_fake
5099 0, // vsub_hi
5100 0, // vsub_lo
5101 0, // wsub_hi
5102 0, // wsub_lo
5103 0, // wsub_hi_then_vsub_fake
5104 0, // wsub_hi_then_vsub_hi
5105 0, // wsub_hi_then_vsub_lo
5106 },
5107 { // CtrRegs_and_V62Regs
5108 0, // isub_hi
5109 0, // isub_lo
5110 0, // subreg_overflow
5111 0, // vsub_fake
5112 0, // vsub_hi
5113 0, // vsub_lo
5114 0, // wsub_hi
5115 0, // wsub_lo
5116 0, // wsub_hi_then_vsub_fake
5117 0, // wsub_hi_then_vsub_hi
5118 0, // wsub_hi_then_vsub_lo
5119 },
5120 { // PredRegs
5121 0, // isub_hi
5122 0, // isub_lo
5123 0, // subreg_overflow
5124 0, // vsub_fake
5125 0, // vsub_hi
5126 0, // vsub_lo
5127 0, // wsub_hi
5128 0, // wsub_lo
5129 0, // wsub_hi_then_vsub_fake
5130 0, // wsub_hi_then_vsub_hi
5131 0, // wsub_hi_then_vsub_lo
5132 },
5133 { // V62Regs_with_isub_hi
5134 11, // isub_hi -> V62Regs_with_isub_hi
5135 11, // isub_lo -> V62Regs_with_isub_hi
5136 0, // subreg_overflow
5137 0, // vsub_fake
5138 0, // vsub_hi
5139 0, // vsub_lo
5140 0, // wsub_hi
5141 0, // wsub_lo
5142 0, // wsub_hi_then_vsub_fake
5143 0, // wsub_hi_then_vsub_hi
5144 0, // wsub_hi_then_vsub_lo
5145 },
5146 { // ModRegs
5147 0, // isub_hi
5148 0, // isub_lo
5149 0, // subreg_overflow
5150 0, // vsub_fake
5151 0, // vsub_hi
5152 0, // vsub_lo
5153 0, // wsub_hi
5154 0, // wsub_lo
5155 0, // wsub_hi_then_vsub_fake
5156 0, // wsub_hi_then_vsub_hi
5157 0, // wsub_hi_then_vsub_lo
5158 },
5159 { // CtrRegs_with_subreg_overflow
5160 0, // isub_hi
5161 0, // isub_lo
5162 13, // subreg_overflow -> CtrRegs_with_subreg_overflow
5163 0, // vsub_fake
5164 0, // vsub_hi
5165 0, // vsub_lo
5166 0, // wsub_hi
5167 0, // wsub_lo
5168 0, // wsub_hi_then_vsub_fake
5169 0, // wsub_hi_then_vsub_hi
5170 0, // wsub_hi_then_vsub_lo
5171 },
5172 { // V65Regs
5173 0, // isub_hi
5174 0, // isub_lo
5175 0, // subreg_overflow
5176 0, // vsub_fake
5177 0, // vsub_hi
5178 0, // vsub_lo
5179 0, // wsub_hi
5180 0, // wsub_lo
5181 0, // wsub_hi_then_vsub_fake
5182 0, // wsub_hi_then_vsub_hi
5183 0, // wsub_hi_then_vsub_lo
5184 },
5185 { // SysRegs64
5186 15, // isub_hi -> SysRegs64
5187 15, // isub_lo -> SysRegs64
5188 0, // subreg_overflow
5189 0, // vsub_fake
5190 0, // vsub_hi
5191 0, // vsub_lo
5192 0, // wsub_hi
5193 0, // wsub_lo
5194 0, // wsub_hi_then_vsub_fake
5195 0, // wsub_hi_then_vsub_hi
5196 0, // wsub_hi_then_vsub_lo
5197 },
5198 { // DoubleRegs
5199 16, // isub_hi -> DoubleRegs
5200 16, // isub_lo -> DoubleRegs
5201 0, // subreg_overflow
5202 0, // vsub_fake
5203 0, // vsub_hi
5204 0, // vsub_lo
5205 0, // wsub_hi
5206 0, // wsub_lo
5207 0, // wsub_hi_then_vsub_fake
5208 0, // wsub_hi_then_vsub_hi
5209 0, // wsub_hi_then_vsub_lo
5210 },
5211 { // GuestRegs64
5212 17, // isub_hi -> GuestRegs64
5213 17, // isub_lo -> GuestRegs64
5214 0, // subreg_overflow
5215 0, // vsub_fake
5216 0, // vsub_hi
5217 0, // vsub_lo
5218 0, // wsub_hi
5219 0, // wsub_lo
5220 0, // wsub_hi_then_vsub_fake
5221 0, // wsub_hi_then_vsub_hi
5222 0, // wsub_hi_then_vsub_lo
5223 },
5224 { // VectRegRev
5225 0, // isub_hi
5226 0, // isub_lo
5227 0, // subreg_overflow
5228 0, // vsub_fake
5229 18, // vsub_hi -> VectRegRev
5230 18, // vsub_lo -> VectRegRev
5231 0, // wsub_hi
5232 0, // wsub_lo
5233 0, // wsub_hi_then_vsub_fake
5234 0, // wsub_hi_then_vsub_hi
5235 0, // wsub_hi_then_vsub_lo
5236 },
5237 { // CtrRegs64
5238 19, // isub_hi -> CtrRegs64
5239 19, // isub_lo -> CtrRegs64
5240 0, // subreg_overflow
5241 0, // vsub_fake
5242 0, // vsub_hi
5243 0, // vsub_lo
5244 0, // wsub_hi
5245 0, // wsub_lo
5246 0, // wsub_hi_then_vsub_fake
5247 0, // wsub_hi_then_vsub_hi
5248 0, // wsub_hi_then_vsub_lo
5249 },
5250 { // GeneralDoubleLow8Regs
5251 20, // isub_hi -> GeneralDoubleLow8Regs
5252 20, // isub_lo -> GeneralDoubleLow8Regs
5253 0, // subreg_overflow
5254 0, // vsub_fake
5255 0, // vsub_hi
5256 0, // vsub_lo
5257 0, // wsub_hi
5258 0, // wsub_lo
5259 0, // wsub_hi_then_vsub_fake
5260 0, // wsub_hi_then_vsub_hi
5261 0, // wsub_hi_then_vsub_lo
5262 },
5263 { // DoubleRegs_with_isub_hi_in_IntRegsLow8
5264 21, // isub_hi -> DoubleRegs_with_isub_hi_in_IntRegsLow8
5265 21, // isub_lo -> DoubleRegs_with_isub_hi_in_IntRegsLow8
5266 0, // subreg_overflow
5267 0, // vsub_fake
5268 0, // vsub_hi
5269 0, // vsub_lo
5270 0, // wsub_hi
5271 0, // wsub_lo
5272 0, // wsub_hi_then_vsub_fake
5273 0, // wsub_hi_then_vsub_hi
5274 0, // wsub_hi_then_vsub_lo
5275 },
5276 { // CtrRegs64_and_V62Regs
5277 22, // isub_hi -> CtrRegs64_and_V62Regs
5278 22, // isub_lo -> CtrRegs64_and_V62Regs
5279 0, // subreg_overflow
5280 0, // vsub_fake
5281 0, // vsub_hi
5282 0, // vsub_lo
5283 0, // wsub_hi
5284 0, // wsub_lo
5285 0, // wsub_hi_then_vsub_fake
5286 0, // wsub_hi_then_vsub_hi
5287 0, // wsub_hi_then_vsub_lo
5288 },
5289 { // CtrRegs64_with_isub_hi_in_ModRegs
5290 23, // isub_hi -> CtrRegs64_with_isub_hi_in_ModRegs
5291 23, // isub_lo -> CtrRegs64_with_isub_hi_in_ModRegs
5292 0, // subreg_overflow
5293 0, // vsub_fake
5294 0, // vsub_hi
5295 0, // vsub_lo
5296 0, // wsub_hi
5297 0, // wsub_lo
5298 0, // wsub_hi_then_vsub_fake
5299 0, // wsub_hi_then_vsub_hi
5300 0, // wsub_hi_then_vsub_lo
5301 },
5302 { // HvxQR
5303 0, // isub_hi
5304 0, // isub_lo
5305 0, // subreg_overflow
5306 0, // vsub_fake
5307 0, // vsub_hi
5308 0, // vsub_lo
5309 0, // wsub_hi
5310 0, // wsub_lo
5311 0, // wsub_hi_then_vsub_fake
5312 0, // wsub_hi_then_vsub_hi
5313 0, // wsub_hi_then_vsub_lo
5314 },
5315 { // HvxVR
5316 0, // isub_hi
5317 0, // isub_lo
5318 0, // subreg_overflow
5319 0, // vsub_fake
5320 0, // vsub_hi
5321 0, // vsub_lo
5322 0, // wsub_hi
5323 0, // wsub_lo
5324 0, // wsub_hi_then_vsub_fake
5325 0, // wsub_hi_then_vsub_hi
5326 0, // wsub_hi_then_vsub_lo
5327 },
5328 { // HvxVR_and_V65Regs
5329 0, // isub_hi
5330 0, // isub_lo
5331 0, // subreg_overflow
5332 0, // vsub_fake
5333 0, // vsub_hi
5334 0, // vsub_lo
5335 0, // wsub_hi
5336 0, // wsub_lo
5337 0, // wsub_hi_then_vsub_fake
5338 0, // wsub_hi_then_vsub_hi
5339 0, // wsub_hi_then_vsub_lo
5340 },
5341 { // HvxWR
5342 0, // isub_hi
5343 0, // isub_lo
5344 0, // subreg_overflow
5345 0, // vsub_fake
5346 27, // vsub_hi -> HvxWR
5347 27, // vsub_lo -> HvxWR
5348 0, // wsub_hi
5349 0, // wsub_lo
5350 0, // wsub_hi_then_vsub_fake
5351 0, // wsub_hi_then_vsub_hi
5352 0, // wsub_hi_then_vsub_lo
5353 },
5354 { // HvxWR_and_VectRegRev
5355 0, // isub_hi
5356 0, // isub_lo
5357 0, // subreg_overflow
5358 0, // vsub_fake
5359 28, // vsub_hi -> HvxWR_and_VectRegRev
5360 28, // vsub_lo -> HvxWR_and_VectRegRev
5361 0, // wsub_hi
5362 0, // wsub_lo
5363 0, // wsub_hi_then_vsub_fake
5364 0, // wsub_hi_then_vsub_hi
5365 0, // wsub_hi_then_vsub_lo
5366 },
5367 { // HvxVQR
5368 0, // isub_hi
5369 0, // isub_lo
5370 0, // subreg_overflow
5371 0, // vsub_fake
5372 29, // vsub_hi -> HvxVQR
5373 29, // vsub_lo -> HvxVQR
5374 29, // wsub_hi -> HvxVQR
5375 29, // wsub_lo -> HvxVQR
5376 0, // wsub_hi_then_vsub_fake
5377 29, // wsub_hi_then_vsub_hi -> HvxVQR
5378 29, // wsub_hi_then_vsub_lo -> HvxVQR
5379 },
5380 };
5381 assert(RC && "Missing regclass");
5382 if (!Idx) return RC;
5383 --Idx;
5384 assert(Idx < 11 && "Bad subreg");
5385 unsigned TV = Table[RC->getID()][Idx];
5386 return TV ? getRegClass(TV - 1) : nullptr;
5387}
5388
5389const TargetRegisterClass *HexagonGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
5390 static const uint8_t Table[29][11] = {
5391 { // UsrBits
5392 0, // UsrBits:isub_hi
5393 0, // UsrBits:isub_lo
5394 0, // UsrBits:subreg_overflow
5395 0, // UsrBits:vsub_fake
5396 0, // UsrBits:vsub_hi
5397 0, // UsrBits:vsub_lo
5398 0, // UsrBits:wsub_hi
5399 0, // UsrBits:wsub_lo
5400 0, // UsrBits:wsub_hi_then_vsub_fake
5401 0, // UsrBits:wsub_hi_then_vsub_hi
5402 0, // UsrBits:wsub_hi_then_vsub_lo
5403 },
5404 { // SysRegs
5405 0, // SysRegs:isub_hi
5406 0, // SysRegs:isub_lo
5407 0, // SysRegs:subreg_overflow
5408 0, // SysRegs:vsub_fake
5409 0, // SysRegs:vsub_hi
5410 0, // SysRegs:vsub_lo
5411 0, // SysRegs:wsub_hi
5412 0, // SysRegs:wsub_lo
5413 0, // SysRegs:wsub_hi_then_vsub_fake
5414 0, // SysRegs:wsub_hi_then_vsub_hi
5415 0, // SysRegs:wsub_hi_then_vsub_lo
5416 },
5417 { // GuestRegs
5418 0, // GuestRegs:isub_hi
5419 0, // GuestRegs:isub_lo
5420 0, // GuestRegs:subreg_overflow
5421 0, // GuestRegs:vsub_fake
5422 0, // GuestRegs:vsub_hi
5423 0, // GuestRegs:vsub_lo
5424 0, // GuestRegs:wsub_hi
5425 0, // GuestRegs:wsub_lo
5426 0, // GuestRegs:wsub_hi_then_vsub_fake
5427 0, // GuestRegs:wsub_hi_then_vsub_hi
5428 0, // GuestRegs:wsub_hi_then_vsub_lo
5429 },
5430 { // IntRegs
5431 0, // IntRegs:isub_hi
5432 0, // IntRegs:isub_lo
5433 0, // IntRegs:subreg_overflow
5434 0, // IntRegs:vsub_fake
5435 0, // IntRegs:vsub_hi
5436 0, // IntRegs:vsub_lo
5437 0, // IntRegs:wsub_hi
5438 0, // IntRegs:wsub_lo
5439 0, // IntRegs:wsub_hi_then_vsub_fake
5440 0, // IntRegs:wsub_hi_then_vsub_hi
5441 0, // IntRegs:wsub_hi_then_vsub_lo
5442 },
5443 { // CtrRegs
5444 0, // CtrRegs:isub_hi
5445 0, // CtrRegs:isub_lo
5446 1, // CtrRegs:subreg_overflow -> UsrBits
5447 0, // CtrRegs:vsub_fake
5448 0, // CtrRegs:vsub_hi
5449 0, // CtrRegs:vsub_lo
5450 0, // CtrRegs:wsub_hi
5451 0, // CtrRegs:wsub_lo
5452 0, // CtrRegs:wsub_hi_then_vsub_fake
5453 0, // CtrRegs:wsub_hi_then_vsub_hi
5454 0, // CtrRegs:wsub_hi_then_vsub_lo
5455 },
5456 { // GeneralSubRegs
5457 0, // GeneralSubRegs:isub_hi
5458 0, // GeneralSubRegs:isub_lo
5459 0, // GeneralSubRegs:subreg_overflow
5460 0, // GeneralSubRegs:vsub_fake
5461 0, // GeneralSubRegs:vsub_hi
5462 0, // GeneralSubRegs:vsub_lo
5463 0, // GeneralSubRegs:wsub_hi
5464 0, // GeneralSubRegs:wsub_lo
5465 0, // GeneralSubRegs:wsub_hi_then_vsub_fake
5466 0, // GeneralSubRegs:wsub_hi_then_vsub_hi
5467 0, // GeneralSubRegs:wsub_hi_then_vsub_lo
5468 },
5469 { // V62Regs
5470 9, // V62Regs:isub_hi -> CtrRegs_and_V62Regs
5471 9, // V62Regs:isub_lo -> CtrRegs_and_V62Regs
5472 0, // V62Regs:subreg_overflow
5473 0, // V62Regs:vsub_fake
5474 0, // V62Regs:vsub_hi
5475 0, // V62Regs:vsub_lo
5476 0, // V62Regs:wsub_hi
5477 0, // V62Regs:wsub_lo
5478 0, // V62Regs:wsub_hi_then_vsub_fake
5479 0, // V62Regs:wsub_hi_then_vsub_hi
5480 0, // V62Regs:wsub_hi_then_vsub_lo
5481 },
5482 { // IntRegsLow8
5483 0, // IntRegsLow8:isub_hi
5484 0, // IntRegsLow8:isub_lo
5485 0, // IntRegsLow8:subreg_overflow
5486 0, // IntRegsLow8:vsub_fake
5487 0, // IntRegsLow8:vsub_hi
5488 0, // IntRegsLow8:vsub_lo
5489 0, // IntRegsLow8:wsub_hi
5490 0, // IntRegsLow8:wsub_lo
5491 0, // IntRegsLow8:wsub_hi_then_vsub_fake
5492 0, // IntRegsLow8:wsub_hi_then_vsub_hi
5493 0, // IntRegsLow8:wsub_hi_then_vsub_lo
5494 },
5495 { // CtrRegs_and_V62Regs
5496 0, // CtrRegs_and_V62Regs:isub_hi
5497 0, // CtrRegs_and_V62Regs:isub_lo
5498 0, // CtrRegs_and_V62Regs:subreg_overflow
5499 0, // CtrRegs_and_V62Regs:vsub_fake
5500 0, // CtrRegs_and_V62Regs:vsub_hi
5501 0, // CtrRegs_and_V62Regs:vsub_lo
5502 0, // CtrRegs_and_V62Regs:wsub_hi
5503 0, // CtrRegs_and_V62Regs:wsub_lo
5504 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_fake
5505 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_hi
5506 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_lo
5507 },
5508 { // PredRegs
5509 0, // PredRegs:isub_hi
5510 0, // PredRegs:isub_lo
5511 0, // PredRegs:subreg_overflow
5512 0, // PredRegs:vsub_fake
5513 0, // PredRegs:vsub_hi
5514 0, // PredRegs:vsub_lo
5515 0, // PredRegs:wsub_hi
5516 0, // PredRegs:wsub_lo
5517 0, // PredRegs:wsub_hi_then_vsub_fake
5518 0, // PredRegs:wsub_hi_then_vsub_hi
5519 0, // PredRegs:wsub_hi_then_vsub_lo
5520 },
5521 { // V62Regs_with_isub_hi
5522 9, // V62Regs_with_isub_hi:isub_hi -> CtrRegs_and_V62Regs
5523 9, // V62Regs_with_isub_hi:isub_lo -> CtrRegs_and_V62Regs
5524 0, // V62Regs_with_isub_hi:subreg_overflow
5525 0, // V62Regs_with_isub_hi:vsub_fake
5526 0, // V62Regs_with_isub_hi:vsub_hi
5527 0, // V62Regs_with_isub_hi:vsub_lo
5528 0, // V62Regs_with_isub_hi:wsub_hi
5529 0, // V62Regs_with_isub_hi:wsub_lo
5530 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_fake
5531 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_hi
5532 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_lo
5533 },
5534 { // ModRegs
5535 0, // ModRegs:isub_hi
5536 0, // ModRegs:isub_lo
5537 0, // ModRegs:subreg_overflow
5538 0, // ModRegs:vsub_fake
5539 0, // ModRegs:vsub_hi
5540 0, // ModRegs:vsub_lo
5541 0, // ModRegs:wsub_hi
5542 0, // ModRegs:wsub_lo
5543 0, // ModRegs:wsub_hi_then_vsub_fake
5544 0, // ModRegs:wsub_hi_then_vsub_hi
5545 0, // ModRegs:wsub_hi_then_vsub_lo
5546 },
5547 { // CtrRegs_with_subreg_overflow
5548 0, // CtrRegs_with_subreg_overflow:isub_hi
5549 0, // CtrRegs_with_subreg_overflow:isub_lo
5550 1, // CtrRegs_with_subreg_overflow:subreg_overflow -> UsrBits
5551 0, // CtrRegs_with_subreg_overflow:vsub_fake
5552 0, // CtrRegs_with_subreg_overflow:vsub_hi
5553 0, // CtrRegs_with_subreg_overflow:vsub_lo
5554 0, // CtrRegs_with_subreg_overflow:wsub_hi
5555 0, // CtrRegs_with_subreg_overflow:wsub_lo
5556 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_fake
5557 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_hi
5558 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_lo
5559 },
5560 { // V65Regs
5561 0, // V65Regs:isub_hi
5562 0, // V65Regs:isub_lo
5563 0, // V65Regs:subreg_overflow
5564 0, // V65Regs:vsub_fake
5565 0, // V65Regs:vsub_hi
5566 0, // V65Regs:vsub_lo
5567 0, // V65Regs:wsub_hi
5568 0, // V65Regs:wsub_lo
5569 0, // V65Regs:wsub_hi_then_vsub_fake
5570 0, // V65Regs:wsub_hi_then_vsub_hi
5571 0, // V65Regs:wsub_hi_then_vsub_lo
5572 },
5573 { // SysRegs64
5574 2, // SysRegs64:isub_hi -> SysRegs
5575 2, // SysRegs64:isub_lo -> SysRegs
5576 0, // SysRegs64:subreg_overflow
5577 0, // SysRegs64:vsub_fake
5578 0, // SysRegs64:vsub_hi
5579 0, // SysRegs64:vsub_lo
5580 0, // SysRegs64:wsub_hi
5581 0, // SysRegs64:wsub_lo
5582 0, // SysRegs64:wsub_hi_then_vsub_fake
5583 0, // SysRegs64:wsub_hi_then_vsub_hi
5584 0, // SysRegs64:wsub_hi_then_vsub_lo
5585 },
5586 { // DoubleRegs
5587 4, // DoubleRegs:isub_hi -> IntRegs
5588 4, // DoubleRegs:isub_lo -> IntRegs
5589 0, // DoubleRegs:subreg_overflow
5590 0, // DoubleRegs:vsub_fake
5591 0, // DoubleRegs:vsub_hi
5592 0, // DoubleRegs:vsub_lo
5593 0, // DoubleRegs:wsub_hi
5594 0, // DoubleRegs:wsub_lo
5595 0, // DoubleRegs:wsub_hi_then_vsub_fake
5596 0, // DoubleRegs:wsub_hi_then_vsub_hi
5597 0, // DoubleRegs:wsub_hi_then_vsub_lo
5598 },
5599 { // GuestRegs64
5600 3, // GuestRegs64:isub_hi -> GuestRegs
5601 3, // GuestRegs64:isub_lo -> GuestRegs
5602 0, // GuestRegs64:subreg_overflow
5603 0, // GuestRegs64:vsub_fake
5604 0, // GuestRegs64:vsub_hi
5605 0, // GuestRegs64:vsub_lo
5606 0, // GuestRegs64:wsub_hi
5607 0, // GuestRegs64:wsub_lo
5608 0, // GuestRegs64:wsub_hi_then_vsub_fake
5609 0, // GuestRegs64:wsub_hi_then_vsub_hi
5610 0, // GuestRegs64:wsub_hi_then_vsub_lo
5611 },
5612 { // VectRegRev
5613 0, // VectRegRev:isub_hi
5614 0, // VectRegRev:isub_lo
5615 0, // VectRegRev:subreg_overflow
5616 0, // VectRegRev:vsub_fake
5617 25, // VectRegRev:vsub_hi -> HvxVR
5618 25, // VectRegRev:vsub_lo -> HvxVR
5619 0, // VectRegRev:wsub_hi
5620 0, // VectRegRev:wsub_lo
5621 0, // VectRegRev:wsub_hi_then_vsub_fake
5622 0, // VectRegRev:wsub_hi_then_vsub_hi
5623 0, // VectRegRev:wsub_hi_then_vsub_lo
5624 },
5625 { // CtrRegs64
5626 5, // CtrRegs64:isub_hi -> CtrRegs
5627 5, // CtrRegs64:isub_lo -> CtrRegs
5628 0, // CtrRegs64:subreg_overflow
5629 0, // CtrRegs64:vsub_fake
5630 0, // CtrRegs64:vsub_hi
5631 0, // CtrRegs64:vsub_lo
5632 0, // CtrRegs64:wsub_hi
5633 0, // CtrRegs64:wsub_lo
5634 0, // CtrRegs64:wsub_hi_then_vsub_fake
5635 0, // CtrRegs64:wsub_hi_then_vsub_hi
5636 0, // CtrRegs64:wsub_hi_then_vsub_lo
5637 },
5638 { // GeneralDoubleLow8Regs
5639 6, // GeneralDoubleLow8Regs:isub_hi -> GeneralSubRegs
5640 6, // GeneralDoubleLow8Regs:isub_lo -> GeneralSubRegs
5641 0, // GeneralDoubleLow8Regs:subreg_overflow
5642 0, // GeneralDoubleLow8Regs:vsub_fake
5643 0, // GeneralDoubleLow8Regs:vsub_hi
5644 0, // GeneralDoubleLow8Regs:vsub_lo
5645 0, // GeneralDoubleLow8Regs:wsub_hi
5646 0, // GeneralDoubleLow8Regs:wsub_lo
5647 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_fake
5648 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_hi
5649 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_lo
5650 },
5651 { // DoubleRegs_with_isub_hi_in_IntRegsLow8
5652 8, // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_hi -> IntRegsLow8
5653 8, // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_lo -> IntRegsLow8
5654 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:subreg_overflow
5655 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_fake
5656 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_hi
5657 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_lo
5658 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi
5659 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_lo
5660 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_fake
5661 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_hi
5662 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_lo
5663 },
5664 { // CtrRegs64_and_V62Regs
5665 9, // CtrRegs64_and_V62Regs:isub_hi -> CtrRegs_and_V62Regs
5666 9, // CtrRegs64_and_V62Regs:isub_lo -> CtrRegs_and_V62Regs
5667 0, // CtrRegs64_and_V62Regs:subreg_overflow
5668 0, // CtrRegs64_and_V62Regs:vsub_fake
5669 0, // CtrRegs64_and_V62Regs:vsub_hi
5670 0, // CtrRegs64_and_V62Regs:vsub_lo
5671 0, // CtrRegs64_and_V62Regs:wsub_hi
5672 0, // CtrRegs64_and_V62Regs:wsub_lo
5673 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_fake
5674 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_hi
5675 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_lo
5676 },
5677 { // CtrRegs64_with_isub_hi_in_ModRegs
5678 12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_hi -> ModRegs
5679 12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_lo -> ModRegs
5680 0, // CtrRegs64_with_isub_hi_in_ModRegs:subreg_overflow
5681 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_fake
5682 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_hi
5683 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_lo
5684 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi
5685 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_lo
5686 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_fake
5687 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_hi
5688 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_lo
5689 },
5690 { // HvxQR
5691 0, // HvxQR:isub_hi
5692 0, // HvxQR:isub_lo
5693 0, // HvxQR:subreg_overflow
5694 0, // HvxQR:vsub_fake
5695 0, // HvxQR:vsub_hi
5696 0, // HvxQR:vsub_lo
5697 0, // HvxQR:wsub_hi
5698 0, // HvxQR:wsub_lo
5699 0, // HvxQR:wsub_hi_then_vsub_fake
5700 0, // HvxQR:wsub_hi_then_vsub_hi
5701 0, // HvxQR:wsub_hi_then_vsub_lo
5702 },
5703 { // HvxVR
5704 0, // HvxVR:isub_hi
5705 0, // HvxVR:isub_lo
5706 0, // HvxVR:subreg_overflow
5707 0, // HvxVR:vsub_fake
5708 0, // HvxVR:vsub_hi
5709 0, // HvxVR:vsub_lo
5710 0, // HvxVR:wsub_hi
5711 0, // HvxVR:wsub_lo
5712 0, // HvxVR:wsub_hi_then_vsub_fake
5713 0, // HvxVR:wsub_hi_then_vsub_hi
5714 0, // HvxVR:wsub_hi_then_vsub_lo
5715 },
5716 { // HvxVR_and_V65Regs
5717 0, // HvxVR_and_V65Regs:isub_hi
5718 0, // HvxVR_and_V65Regs:isub_lo
5719 0, // HvxVR_and_V65Regs:subreg_overflow
5720 0, // HvxVR_and_V65Regs:vsub_fake
5721 0, // HvxVR_and_V65Regs:vsub_hi
5722 0, // HvxVR_and_V65Regs:vsub_lo
5723 0, // HvxVR_and_V65Regs:wsub_hi
5724 0, // HvxVR_and_V65Regs:wsub_lo
5725 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_fake
5726 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_hi
5727 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_lo
5728 },
5729 { // HvxWR
5730 0, // HvxWR:isub_hi
5731 0, // HvxWR:isub_lo
5732 0, // HvxWR:subreg_overflow
5733 0, // HvxWR:vsub_fake
5734 25, // HvxWR:vsub_hi -> HvxVR
5735 25, // HvxWR:vsub_lo -> HvxVR
5736 0, // HvxWR:wsub_hi
5737 0, // HvxWR:wsub_lo
5738 0, // HvxWR:wsub_hi_then_vsub_fake
5739 0, // HvxWR:wsub_hi_then_vsub_hi
5740 0, // HvxWR:wsub_hi_then_vsub_lo
5741 },
5742 { // HvxWR_and_VectRegRev
5743 0, // HvxWR_and_VectRegRev:isub_hi
5744 0, // HvxWR_and_VectRegRev:isub_lo
5745 0, // HvxWR_and_VectRegRev:subreg_overflow
5746 0, // HvxWR_and_VectRegRev:vsub_fake
5747 25, // HvxWR_and_VectRegRev:vsub_hi -> HvxVR
5748 25, // HvxWR_and_VectRegRev:vsub_lo -> HvxVR
5749 0, // HvxWR_and_VectRegRev:wsub_hi
5750 0, // HvxWR_and_VectRegRev:wsub_lo
5751 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_fake
5752 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_hi
5753 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_lo
5754 },
5755 { // HvxVQR
5756 0, // HvxVQR:isub_hi
5757 0, // HvxVQR:isub_lo
5758 0, // HvxVQR:subreg_overflow
5759 0, // HvxVQR:vsub_fake
5760 25, // HvxVQR:vsub_hi -> HvxVR
5761 25, // HvxVQR:vsub_lo -> HvxVR
5762 27, // HvxVQR:wsub_hi -> HvxWR
5763 27, // HvxVQR:wsub_lo -> HvxWR
5764 0, // HvxVQR:wsub_hi_then_vsub_fake
5765 25, // HvxVQR:wsub_hi_then_vsub_hi -> HvxVR
5766 25, // HvxVQR:wsub_hi_then_vsub_lo -> HvxVR
5767 },
5768 };
5769 assert(RC && "Missing regclass");
5770 if (!Idx) return RC;
5771 --Idx;
5772 assert(Idx < 11 && "Bad subreg");
5773 unsigned TV = Table[RC->getID()][Idx];
5774 return TV ? getRegClass(TV - 1) : nullptr;
5775}
5776
5777/// Get the weight in units of pressure for this register class.
5778const RegClassWeight &HexagonGenRegisterInfo::
5779getRegClassWeight(const TargetRegisterClass *RC) const {
5780 static const RegClassWeight RCWeightTable[] = {
5781 {0, 0}, // UsrBits
5782 {0, 0}, // SysRegs
5783 {0, 0}, // GuestRegs
5784 {1, 32}, // IntRegs
5785 {0, 6}, // CtrRegs
5786 {1, 16}, // GeneralSubRegs
5787 {0, 0}, // V62Regs
5788 {1, 8}, // IntRegsLow8
5789 {0, 0}, // CtrRegs_and_V62Regs
5790 {1, 4}, // PredRegs
5791 {0, 0}, // V62Regs_with_isub_hi
5792 {1, 2}, // ModRegs
5793 {0, 0}, // CtrRegs_with_subreg_overflow
5794 {1, 1}, // V65Regs
5795 {0, 0}, // SysRegs64
5796 {2, 32}, // DoubleRegs
5797 {0, 0}, // GuestRegs64
5798 {2, 32}, // VectRegRev
5799 {0, 6}, // CtrRegs64
5800 {2, 16}, // GeneralDoubleLow8Regs
5801 {2, 8}, // DoubleRegs_with_isub_hi_in_IntRegsLow8
5802 {0, 0}, // CtrRegs64_and_V62Regs
5803 {2, 2}, // CtrRegs64_with_isub_hi_in_ModRegs
5804 {1, 4}, // HvxQR
5805 {1, 33}, // HvxVR
5806 {1, 1}, // HvxVR_and_V65Regs
5807 {2, 32}, // HvxWR
5808 {2, 32}, // HvxWR_and_VectRegRev
5809 {4, 32}, // HvxVQR
5810 };
5811 return RCWeightTable[RC->getID()];
5812}
5813
5814/// Get the weight in units of pressure for this register unit.
5815unsigned HexagonGenRegisterInfo::
5816getRegUnitWeight(unsigned RegUnit) const {
5817 assert(RegUnit < 272 && "invalid register unit");
5818 // All register units have unit weight.
5819 return 1;
5820}
5821
5822
5823// Get the number of dimensions of register pressure.
5824unsigned HexagonGenRegisterInfo::getNumRegPressureSets() const {
5825 return 8;
5826}
5827
5828// Get the name of this register unit pressure set.
5829const char *HexagonGenRegisterInfo::
5830getRegPressureSetName(unsigned Idx) const {
5831 static const char *PressureNameTable[] = {
5832 "HvxVR_and_V65Regs",
5833 "ModRegs",
5834 "PredRegs",
5835 "HvxQR",
5836 "IntRegsLow8",
5837 "GeneralSubRegs",
5838 "IntRegs",
5839 "HvxVR",
5840 };
5841 return PressureNameTable[Idx];
5842}
5843
5844// Get the register unit pressure limit for this dimension.
5845// This limit must be adjusted dynamically for reserved registers.
5846unsigned HexagonGenRegisterInfo::
5847getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
5848 static const uint8_t PressureLimitTable[] = {
5849 1, // 0: HvxVR_and_V65Regs
5850 2, // 1: ModRegs
5851 4, // 2: PredRegs
5852 4, // 3: HvxQR
5853 8, // 4: IntRegsLow8
5854 16, // 5: GeneralSubRegs
5855 32, // 6: IntRegs
5856 33, // 7: HvxVR
5857 };
5858 return PressureLimitTable[Idx];
5859}
5860
5861/// Table of pressure sets per register class or unit.
5862static const int RCSetsTable[] = {
5863 /* 0 */ 1, -1,
5864 /* 2 */ 2, -1,
5865 /* 4 */ 3, -1,
5866 /* 6 */ 4, 5, 6, -1,
5867 /* 10 */ 0, 7, -1,
5868};
5869
5870/// Get the dimensions of register pressure impacted by this register class.
5871/// Returns a -1 terminated array of pressure set IDs
5872const int *HexagonGenRegisterInfo::
5873getRegClassPressureSets(const TargetRegisterClass *RC) const {
5874 static const uint8_t RCSetStartTable[] = {
5875 1,1,1,8,1,7,1,6,1,2,1,0,1,1,1,8,1,11,1,7,6,1,1,4,11,10,11,11,11,};
5876 return &RCSetsTable[RCSetStartTable[RC->getID()]];
5877}
5878
5879/// Get the dimensions of register pressure impacted by this register unit.
5880/// Returns a -1 terminated array of pressure set IDs
5881const int *HexagonGenRegisterInfo::
5882getRegUnitPressureSets(unsigned RegUnit) const {
5883 assert(RegUnit < 272 && "invalid register unit");
5884 static const uint8_t RUSetStartTable[] = {
5885 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,10,1,1,1,1,1,1,1,6,6,6,6,6,6,6,6,8,8,8,8,8,8,8,8,7,7,7,7,7,7,7,7,8,8,8,8,8,8,8,8,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,2,2,2,2,1,1,1,1,4,4,4,4,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
5886 return &RCSetsTable[RUSetStartTable[RegUnit]];
5887}
5888
5889extern const MCRegisterDesc HexagonRegDesc[];
5890extern const int16_t HexagonRegDiffLists[];
5891extern const LaneBitmask HexagonLaneMaskLists[];
5892extern const char HexagonRegStrings[];
5893extern const char HexagonRegClassStrings[];
5894extern const MCPhysReg HexagonRegUnitRoots[][2];
5895extern const uint16_t HexagonSubRegIdxLists[];
5896extern const uint16_t HexagonRegEncodingTable[];
5897// Hexagon Dwarf<->LLVM register mappings.
5898extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[];
5899extern const unsigned HexagonDwarfFlavour0Dwarf2LSize;
5900
5901extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[];
5902extern const unsigned HexagonEHFlavour0Dwarf2LSize;
5903
5904extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[];
5905extern const unsigned HexagonDwarfFlavour0L2DwarfSize;
5906
5907extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[];
5908extern const unsigned HexagonEHFlavour0L2DwarfSize;
5909
5910HexagonGenRegisterInfo::
5911HexagonGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
5912 unsigned PC, unsigned HwMode)
5913 : TargetRegisterInfo(&HexagonRegInfoDesc, RegisterClasses, RegisterClasses+29,
5914 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
5915 LaneBitmask(0xFFFFFFFFFFFFFFFB), RegClassInfos, VTLists, HwMode) {
5916 InitMCRegisterInfo(HexagonRegDesc, 398, RA, PC,
5917 HexagonMCRegisterClasses, 29,
5918 HexagonRegUnitRoots,
5919 272,
5920 HexagonRegDiffLists,
5921 HexagonLaneMaskLists,
5922 HexagonRegStrings,
5923 HexagonRegClassStrings,
5924 HexagonSubRegIdxLists,
5925 12,
5926 HexagonRegEncodingTable);
5927
5928 switch (DwarfFlavour) {
5929 default:
5930 llvm_unreachable("Unknown DWARF flavour");
5931 case 0:
5932 mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
5933 break;
5934 }
5935 switch (EHFlavour) {
5936 default:
5937 llvm_unreachable("Unknown DWARF flavour");
5938 case 0:
5939 mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
5940 break;
5941 }
5942 switch (DwarfFlavour) {
5943 default:
5944 llvm_unreachable("Unknown DWARF flavour");
5945 case 0:
5946 mapLLVMRegsToDwarfRegs(HexagonDwarfFlavour0L2Dwarf, HexagonDwarfFlavour0L2DwarfSize, false);
5947 break;
5948 }
5949 switch (EHFlavour) {
5950 default:
5951 llvm_unreachable("Unknown DWARF flavour");
5952 case 0:
5953 mapLLVMRegsToDwarfRegs(HexagonEHFlavour0L2Dwarf, HexagonEHFlavour0L2DwarfSize, true);
5954 break;
5955 }
5956}
5957
5958static const MCPhysReg HexagonCSR_SaveList[] = { Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 };
5959static const uint32_t HexagonCSR_RegMask[] = { 0x00000000, 0x00000000, 0x0000007e, 0x00000000, 0x0003ffc0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
5960
5961
5962ArrayRef<const uint32_t *> HexagonGenRegisterInfo::getRegMasks() const {
5963 static const uint32_t *const Masks[] = {
5964 HexagonCSR_RegMask,
5965 };
5966 return ArrayRef(Masks);
5967}
5968
5969bool HexagonGenRegisterInfo::
5970isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
5971 return
5972 false;
5973}
5974
5975bool HexagonGenRegisterInfo::
5976isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
5977 return
5978 false;
5979}
5980
5981bool HexagonGenRegisterInfo::
5982isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
5983 return
5984 false;
5985}
5986
5987bool HexagonGenRegisterInfo::
5988isConstantPhysReg(MCRegister PhysReg) const {
5989 return
5990 false;
5991}
5992
5993ArrayRef<const char *> HexagonGenRegisterInfo::getRegMaskNames() const {
5994 static const char *Names[] = {
5995 "HexagonCSR",
5996 };
5997 return ArrayRef(Names);
5998}
5999
6000const HexagonFrameLowering *
6001HexagonGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
6002 return static_cast<const HexagonFrameLowering *>(
6003 MF.getSubtarget().getFrameLowering());
6004}
6005
6006} // end namespace llvm
6007
6008#endif // GET_REGINFO_TARGET_DESC
6009
6010