1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm {
12
13namespace Lanai {
14 enum {
15 PHI = 0,
16 INLINEASM = 1,
17 INLINEASM_BR = 2,
18 CFI_INSTRUCTION = 3,
19 EH_LABEL = 4,
20 GC_LABEL = 5,
21 ANNOTATION_LABEL = 6,
22 KILL = 7,
23 EXTRACT_SUBREG = 8,
24 INSERT_SUBREG = 9,
25 IMPLICIT_DEF = 10,
26 SUBREG_TO_REG = 11,
27 COPY_TO_REGCLASS = 12,
28 DBG_VALUE = 13,
29 DBG_VALUE_LIST = 14,
30 DBG_INSTR_REF = 15,
31 DBG_PHI = 16,
32 DBG_LABEL = 17,
33 REG_SEQUENCE = 18,
34 COPY = 19,
35 BUNDLE = 20,
36 LIFETIME_START = 21,
37 LIFETIME_END = 22,
38 PSEUDO_PROBE = 23,
39 ARITH_FENCE = 24,
40 STACKMAP = 25,
41 FENTRY_CALL = 26,
42 PATCHPOINT = 27,
43 LOAD_STACK_GUARD = 28,
44 PREALLOCATED_SETUP = 29,
45 PREALLOCATED_ARG = 30,
46 STATEPOINT = 31,
47 LOCAL_ESCAPE = 32,
48 FAULTING_OP = 33,
49 PATCHABLE_OP = 34,
50 PATCHABLE_FUNCTION_ENTER = 35,
51 PATCHABLE_RET = 36,
52 PATCHABLE_FUNCTION_EXIT = 37,
53 PATCHABLE_TAIL_CALL = 38,
54 PATCHABLE_EVENT_CALL = 39,
55 PATCHABLE_TYPED_EVENT_CALL = 40,
56 ICALL_BRANCH_FUNNEL = 41,
57 MEMBARRIER = 42,
58 JUMP_TABLE_DEBUG_INFO = 43,
59 CONVERGENCECTRL_ENTRY = 44,
60 CONVERGENCECTRL_ANCHOR = 45,
61 CONVERGENCECTRL_LOOP = 46,
62 CONVERGENCECTRL_GLUE = 47,
63 G_ASSERT_SEXT = 48,
64 G_ASSERT_ZEXT = 49,
65 G_ASSERT_ALIGN = 50,
66 G_ADD = 51,
67 G_SUB = 52,
68 G_MUL = 53,
69 G_SDIV = 54,
70 G_UDIV = 55,
71 G_SREM = 56,
72 G_UREM = 57,
73 G_SDIVREM = 58,
74 G_UDIVREM = 59,
75 G_AND = 60,
76 G_OR = 61,
77 G_XOR = 62,
78 G_IMPLICIT_DEF = 63,
79 G_PHI = 64,
80 G_FRAME_INDEX = 65,
81 G_GLOBAL_VALUE = 66,
82 G_PTRAUTH_GLOBAL_VALUE = 67,
83 G_CONSTANT_POOL = 68,
84 G_EXTRACT = 69,
85 G_UNMERGE_VALUES = 70,
86 G_INSERT = 71,
87 G_MERGE_VALUES = 72,
88 G_BUILD_VECTOR = 73,
89 G_BUILD_VECTOR_TRUNC = 74,
90 G_CONCAT_VECTORS = 75,
91 G_PTRTOINT = 76,
92 G_INTTOPTR = 77,
93 G_BITCAST = 78,
94 G_FREEZE = 79,
95 G_CONSTANT_FOLD_BARRIER = 80,
96 G_INTRINSIC_FPTRUNC_ROUND = 81,
97 G_INTRINSIC_TRUNC = 82,
98 G_INTRINSIC_ROUND = 83,
99 G_INTRINSIC_LRINT = 84,
100 G_INTRINSIC_LLRINT = 85,
101 G_INTRINSIC_ROUNDEVEN = 86,
102 G_READCYCLECOUNTER = 87,
103 G_READSTEADYCOUNTER = 88,
104 G_LOAD = 89,
105 G_SEXTLOAD = 90,
106 G_ZEXTLOAD = 91,
107 G_INDEXED_LOAD = 92,
108 G_INDEXED_SEXTLOAD = 93,
109 G_INDEXED_ZEXTLOAD = 94,
110 G_STORE = 95,
111 G_INDEXED_STORE = 96,
112 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97,
113 G_ATOMIC_CMPXCHG = 98,
114 G_ATOMICRMW_XCHG = 99,
115 G_ATOMICRMW_ADD = 100,
116 G_ATOMICRMW_SUB = 101,
117 G_ATOMICRMW_AND = 102,
118 G_ATOMICRMW_NAND = 103,
119 G_ATOMICRMW_OR = 104,
120 G_ATOMICRMW_XOR = 105,
121 G_ATOMICRMW_MAX = 106,
122 G_ATOMICRMW_MIN = 107,
123 G_ATOMICRMW_UMAX = 108,
124 G_ATOMICRMW_UMIN = 109,
125 G_ATOMICRMW_FADD = 110,
126 G_ATOMICRMW_FSUB = 111,
127 G_ATOMICRMW_FMAX = 112,
128 G_ATOMICRMW_FMIN = 113,
129 G_ATOMICRMW_UINC_WRAP = 114,
130 G_ATOMICRMW_UDEC_WRAP = 115,
131 G_FENCE = 116,
132 G_PREFETCH = 117,
133 G_BRCOND = 118,
134 G_BRINDIRECT = 119,
135 G_INVOKE_REGION_START = 120,
136 G_INTRINSIC = 121,
137 G_INTRINSIC_W_SIDE_EFFECTS = 122,
138 G_INTRINSIC_CONVERGENT = 123,
139 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124,
140 G_ANYEXT = 125,
141 G_TRUNC = 126,
142 G_CONSTANT = 127,
143 G_FCONSTANT = 128,
144 G_VASTART = 129,
145 G_VAARG = 130,
146 G_SEXT = 131,
147 G_SEXT_INREG = 132,
148 G_ZEXT = 133,
149 G_SHL = 134,
150 G_LSHR = 135,
151 G_ASHR = 136,
152 G_FSHL = 137,
153 G_FSHR = 138,
154 G_ROTR = 139,
155 G_ROTL = 140,
156 G_ICMP = 141,
157 G_FCMP = 142,
158 G_SCMP = 143,
159 G_UCMP = 144,
160 G_SELECT = 145,
161 G_UADDO = 146,
162 G_UADDE = 147,
163 G_USUBO = 148,
164 G_USUBE = 149,
165 G_SADDO = 150,
166 G_SADDE = 151,
167 G_SSUBO = 152,
168 G_SSUBE = 153,
169 G_UMULO = 154,
170 G_SMULO = 155,
171 G_UMULH = 156,
172 G_SMULH = 157,
173 G_UADDSAT = 158,
174 G_SADDSAT = 159,
175 G_USUBSAT = 160,
176 G_SSUBSAT = 161,
177 G_USHLSAT = 162,
178 G_SSHLSAT = 163,
179 G_SMULFIX = 164,
180 G_UMULFIX = 165,
181 G_SMULFIXSAT = 166,
182 G_UMULFIXSAT = 167,
183 G_SDIVFIX = 168,
184 G_UDIVFIX = 169,
185 G_SDIVFIXSAT = 170,
186 G_UDIVFIXSAT = 171,
187 G_FADD = 172,
188 G_FSUB = 173,
189 G_FMUL = 174,
190 G_FMA = 175,
191 G_FMAD = 176,
192 G_FDIV = 177,
193 G_FREM = 178,
194 G_FPOW = 179,
195 G_FPOWI = 180,
196 G_FEXP = 181,
197 G_FEXP2 = 182,
198 G_FEXP10 = 183,
199 G_FLOG = 184,
200 G_FLOG2 = 185,
201 G_FLOG10 = 186,
202 G_FLDEXP = 187,
203 G_FFREXP = 188,
204 G_FNEG = 189,
205 G_FPEXT = 190,
206 G_FPTRUNC = 191,
207 G_FPTOSI = 192,
208 G_FPTOUI = 193,
209 G_SITOFP = 194,
210 G_UITOFP = 195,
211 G_FABS = 196,
212 G_FCOPYSIGN = 197,
213 G_IS_FPCLASS = 198,
214 G_FCANONICALIZE = 199,
215 G_FMINNUM = 200,
216 G_FMAXNUM = 201,
217 G_FMINNUM_IEEE = 202,
218 G_FMAXNUM_IEEE = 203,
219 G_FMINIMUM = 204,
220 G_FMAXIMUM = 205,
221 G_GET_FPENV = 206,
222 G_SET_FPENV = 207,
223 G_RESET_FPENV = 208,
224 G_GET_FPMODE = 209,
225 G_SET_FPMODE = 210,
226 G_RESET_FPMODE = 211,
227 G_PTR_ADD = 212,
228 G_PTRMASK = 213,
229 G_SMIN = 214,
230 G_SMAX = 215,
231 G_UMIN = 216,
232 G_UMAX = 217,
233 G_ABS = 218,
234 G_LROUND = 219,
235 G_LLROUND = 220,
236 G_BR = 221,
237 G_BRJT = 222,
238 G_VSCALE = 223,
239 G_INSERT_SUBVECTOR = 224,
240 G_EXTRACT_SUBVECTOR = 225,
241 G_INSERT_VECTOR_ELT = 226,
242 G_EXTRACT_VECTOR_ELT = 227,
243 G_SHUFFLE_VECTOR = 228,
244 G_SPLAT_VECTOR = 229,
245 G_VECTOR_COMPRESS = 230,
246 G_CTTZ = 231,
247 G_CTTZ_ZERO_UNDEF = 232,
248 G_CTLZ = 233,
249 G_CTLZ_ZERO_UNDEF = 234,
250 G_CTPOP = 235,
251 G_BSWAP = 236,
252 G_BITREVERSE = 237,
253 G_FCEIL = 238,
254 G_FCOS = 239,
255 G_FSIN = 240,
256 G_FTAN = 241,
257 G_FACOS = 242,
258 G_FASIN = 243,
259 G_FATAN = 244,
260 G_FCOSH = 245,
261 G_FSINH = 246,
262 G_FTANH = 247,
263 G_FSQRT = 248,
264 G_FFLOOR = 249,
265 G_FRINT = 250,
266 G_FNEARBYINT = 251,
267 G_ADDRSPACE_CAST = 252,
268 G_BLOCK_ADDR = 253,
269 G_JUMP_TABLE = 254,
270 G_DYN_STACKALLOC = 255,
271 G_STACKSAVE = 256,
272 G_STACKRESTORE = 257,
273 G_STRICT_FADD = 258,
274 G_STRICT_FSUB = 259,
275 G_STRICT_FMUL = 260,
276 G_STRICT_FDIV = 261,
277 G_STRICT_FREM = 262,
278 G_STRICT_FMA = 263,
279 G_STRICT_FSQRT = 264,
280 G_STRICT_FLDEXP = 265,
281 G_READ_REGISTER = 266,
282 G_WRITE_REGISTER = 267,
283 G_MEMCPY = 268,
284 G_MEMCPY_INLINE = 269,
285 G_MEMMOVE = 270,
286 G_MEMSET = 271,
287 G_BZERO = 272,
288 G_TRAP = 273,
289 G_DEBUGTRAP = 274,
290 G_UBSANTRAP = 275,
291 G_VECREDUCE_SEQ_FADD = 276,
292 G_VECREDUCE_SEQ_FMUL = 277,
293 G_VECREDUCE_FADD = 278,
294 G_VECREDUCE_FMUL = 279,
295 G_VECREDUCE_FMAX = 280,
296 G_VECREDUCE_FMIN = 281,
297 G_VECREDUCE_FMAXIMUM = 282,
298 G_VECREDUCE_FMINIMUM = 283,
299 G_VECREDUCE_ADD = 284,
300 G_VECREDUCE_MUL = 285,
301 G_VECREDUCE_AND = 286,
302 G_VECREDUCE_OR = 287,
303 G_VECREDUCE_XOR = 288,
304 G_VECREDUCE_SMAX = 289,
305 G_VECREDUCE_SMIN = 290,
306 G_VECREDUCE_UMAX = 291,
307 G_VECREDUCE_UMIN = 292,
308 G_SBFX = 293,
309 G_UBFX = 294,
310 ADJCALLSTACKDOWN = 295,
311 ADJCALLSTACKUP = 296,
312 ADJDYNALLOC = 297,
313 CALL = 298,
314 CALLR = 299,
315 ADDC_F_I_HI = 300,
316 ADDC_F_I_LO = 301,
317 ADDC_F_R = 302,
318 ADDC_I_HI = 303,
319 ADDC_I_LO = 304,
320 ADDC_R = 305,
321 ADD_F_I_HI = 306,
322 ADD_F_I_LO = 307,
323 ADD_F_R = 308,
324 ADD_I_HI = 309,
325 ADD_I_LO = 310,
326 ADD_R = 311,
327 AND_F_I_HI = 312,
328 AND_F_I_LO = 313,
329 AND_F_R = 314,
330 AND_I_HI = 315,
331 AND_I_LO = 316,
332 AND_R = 317,
333 BRCC = 318,
334 BRIND_CC = 319,
335 BRIND_CCA = 320,
336 BRR = 321,
337 BT = 322,
338 JR = 323,
339 LDADDR = 324,
340 LDBs_RI = 325,
341 LDBs_RR = 326,
342 LDBz_RI = 327,
343 LDBz_RR = 328,
344 LDHs_RI = 329,
345 LDHs_RR = 330,
346 LDHz_RI = 331,
347 LDHz_RR = 332,
348 LDW_RI = 333,
349 LDW_RR = 334,
350 LDWz_RR = 335,
351 LEADZ = 336,
352 LOG0 = 337,
353 LOG1 = 338,
354 LOG2 = 339,
355 LOG3 = 340,
356 LOG4 = 341,
357 MOVHI = 342,
358 NOP = 343,
359 OR_F_I_HI = 344,
360 OR_F_I_LO = 345,
361 OR_F_R = 346,
362 OR_I_HI = 347,
363 OR_I_LO = 348,
364 OR_R = 349,
365 POPC = 350,
366 RET = 351,
367 SA_F_I = 352,
368 SA_I = 353,
369 SCC = 354,
370 SELECT = 355,
371 SFSUB_F_RI_HI = 356,
372 SFSUB_F_RI_LO = 357,
373 SFSUB_F_RR = 358,
374 SHL_F_R = 359,
375 SHL_R = 360,
376 SLI = 361,
377 SL_F_I = 362,
378 SL_I = 363,
379 SRA_F_R = 364,
380 SRA_R = 365,
381 SRL_F_R = 366,
382 SRL_R = 367,
383 STADDR = 368,
384 STB_RI = 369,
385 STB_RR = 370,
386 STH_RI = 371,
387 STH_RR = 372,
388 SUBB_F_I_HI = 373,
389 SUBB_F_I_LO = 374,
390 SUBB_F_R = 375,
391 SUBB_I_HI = 376,
392 SUBB_I_LO = 377,
393 SUBB_R = 378,
394 SUB_F_I_HI = 379,
395 SUB_F_I_LO = 380,
396 SUB_F_R = 381,
397 SUB_I_HI = 382,
398 SUB_I_LO = 383,
399 SUB_R = 384,
400 SW_RI = 385,
401 SW_RR = 386,
402 TRAILZ = 387,
403 XOR_F_I_HI = 388,
404 XOR_F_I_LO = 389,
405 XOR_F_R = 390,
406 XOR_I_HI = 391,
407 XOR_I_LO = 392,
408 XOR_R = 393,
409 INSTRUCTION_LIST_END = 394
410 };
411
412} // end namespace Lanai
413} // end namespace llvm
414#endif // GET_INSTRINFO_ENUM
415
416#ifdef GET_INSTRINFO_SCHED_ENUM
417#undef GET_INSTRINFO_SCHED_ENUM
418namespace llvm {
419
420namespace Lanai {
421namespace Sched {
422 enum {
423 NoInstrModel = 0,
424 IIC_ALU_WriteALU = 1,
425 IIC_ALU = 2,
426 IIC_LD_WriteLD = 3,
427 IIC_LDSW_WriteLDSW = 4,
428 WriteLD = 5,
429 IIC_ST_WriteST = 6,
430 IIC_STSW_WriteSTSW = 7,
431 SCHED_LIST_END = 8
432 };
433} // end namespace Sched
434} // end namespace Lanai
435} // end namespace llvm
436#endif // GET_INSTRINFO_SCHED_ENUM
437
438#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
439namespace llvm {
440
441struct LanaiInstrTable {
442 MCInstrDesc Insts[394];
443 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
444 MCOperandInfo OperandInfo[178];
445 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
446 MCPhysReg ImplicitOps[8];
447};
448
449} // end namespace llvm
450#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
451
452#ifdef GET_INSTRINFO_MC_DESC
453#undef GET_INSTRINFO_MC_DESC
454namespace llvm {
455
456static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
457static constexpr unsigned LanaiImpOpBase = sizeof LanaiInstrTable::OperandInfo / (sizeof(MCPhysReg));
458
459extern const LanaiInstrTable LanaiDescs = {
460 {
461 { 393, 4, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = XOR_R
462 { 392, 3, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = XOR_I_LO
463 { 391, 3, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = XOR_I_HI
464 { 390, 4, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = XOR_F_R
465 { 389, 3, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = XOR_F_I_LO
466 { 388, 3, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = XOR_F_I_HI
467 { 387, 2, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 152, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = TRAILZ
468 { 386, 4, 0, 4, 6, 0, 0, LanaiImpOpBase + 0, 170, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = SW_RR
469 { 385, 4, 0, 4, 6, 0, 0, LanaiImpOpBase + 0, 166, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = SW_RI
470 { 384, 4, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = SUB_R
471 { 383, 3, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 155, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = SUB_I_LO
472 { 382, 3, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 155, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = SUB_I_HI
473 { 381, 4, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = SUB_F_R
474 { 380, 3, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = SUB_F_I_LO
475 { 379, 3, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = SUB_F_I_HI
476 { 378, 4, 1, 4, 1, 1, 0, LanaiImpOpBase + 6, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = SUBB_R
477 { 377, 3, 1, 4, 1, 1, 0, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = SUBB_I_LO
478 { 376, 3, 1, 4, 1, 1, 0, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = SUBB_I_HI
479 { 375, 4, 1, 4, 1, 1, 1, LanaiImpOpBase + 4, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = SUBB_F_R
480 { 374, 3, 1, 4, 1, 1, 1, LanaiImpOpBase + 4, 155, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = SUBB_F_I_LO
481 { 373, 3, 1, 4, 1, 1, 1, LanaiImpOpBase + 4, 155, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = SUBB_F_I_HI
482 { 372, 4, 0, 4, 6, 0, 0, LanaiImpOpBase + 0, 170, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = STH_RR
483 { 371, 4, 0, 4, 7, 0, 0, LanaiImpOpBase + 0, 166, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = STH_RI
484 { 370, 4, 0, 4, 6, 0, 0, LanaiImpOpBase + 0, 170, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = STB_RR
485 { 369, 4, 0, 4, 7, 0, 0, LanaiImpOpBase + 0, 166, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = STB_RI
486 { 368, 2, 0, 4, 6, 0, 0, LanaiImpOpBase + 0, 162, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = STADDR
487 { 367, 4, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = SRL_R
488 { 366, 4, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = SRL_F_R
489 { 365, 4, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = SRA_R
490 { 364, 4, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = SRA_F_R
491 { 363, 3, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 155, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = SL_I
492 { 362, 3, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = SL_F_I
493 { 361, 2, 1, 4, 0, 0, 0, LanaiImpOpBase + 0, 162, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = SLI
494 { 360, 4, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = SHL_R
495 { 359, 4, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = SHL_F_R
496 { 358, 2, 0, 4, 1, 0, 1, LanaiImpOpBase + 6, 152, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = SFSUB_F_RR
497 { 357, 2, 0, 4, 1, 0, 1, LanaiImpOpBase + 6, 162, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = SFSUB_F_RI_LO
498 { 356, 2, 0, 4, 1, 0, 1, LanaiImpOpBase + 6, 162, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = SFSUB_F_RI_HI
499 { 355, 4, 1, 4, 1, 1, 0, LanaiImpOpBase + 6, 174, 0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = SELECT
500 { 354, 2, 1, 4, 2, 1, 0, LanaiImpOpBase + 6, 162, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = SCC
501 { 353, 3, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 155, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = SA_I
502 { 352, 3, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = SA_F_I
503 { 351, 0, 0, 4, 0, 1, 0, LanaiImpOpBase + 7, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = RET
504 { 350, 2, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 152, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = POPC
505 { 349, 4, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = OR_R
506 { 348, 3, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = OR_I_LO
507 { 347, 3, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = OR_I_HI
508 { 346, 4, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = OR_F_R
509 { 345, 3, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = OR_F_I_LO
510 { 344, 3, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = OR_F_I_HI
511 { 343, 0, 0, 4, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = NOP
512 { 342, 2, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 162, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = MOVHI
513 { 341, 0, 0, 4, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = LOG4
514 { 340, 0, 0, 4, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = LOG3
515 { 339, 0, 0, 4, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = LOG2
516 { 338, 0, 0, 4, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = LOG1
517 { 337, 0, 0, 4, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = LOG0
518 { 336, 2, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 152, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = LEADZ
519 { 335, 4, 1, 4, 5, 0, 0, LanaiImpOpBase + 0, 170, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = LDWz_RR
520 { 334, 4, 1, 4, 5, 0, 0, LanaiImpOpBase + 0, 170, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = LDW_RR
521 { 333, 4, 1, 4, 3, 0, 0, LanaiImpOpBase + 0, 166, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = LDW_RI
522 { 332, 4, 1, 4, 5, 0, 0, LanaiImpOpBase + 0, 170, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = LDHz_RR
523 { 331, 4, 1, 4, 4, 0, 0, LanaiImpOpBase + 0, 166, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = LDHz_RI
524 { 330, 4, 1, 4, 5, 0, 0, LanaiImpOpBase + 0, 170, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = LDHs_RR
525 { 329, 4, 1, 4, 4, 0, 0, LanaiImpOpBase + 0, 166, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = LDHs_RI
526 { 328, 4, 1, 4, 5, 0, 0, LanaiImpOpBase + 0, 170, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = LDBz_RR
527 { 327, 4, 1, 4, 4, 0, 0, LanaiImpOpBase + 0, 166, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = LDBz_RI
528 { 326, 4, 1, 4, 5, 0, 0, LanaiImpOpBase + 0, 170, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = LDBs_RR
529 { 325, 4, 1, 4, 4, 0, 0, LanaiImpOpBase + 0, 166, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = LDBs_RI
530 { 324, 2, 1, 4, 3, 0, 0, LanaiImpOpBase + 0, 162, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = LDADDR
531 { 323, 1, 0, 4, 1, 0, 0, LanaiImpOpBase + 0, 154, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = JR
532 { 322, 1, 0, 4, 2, 0, 0, LanaiImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = BT
533 { 321, 2, 0, 4, 0, 1, 0, LanaiImpOpBase + 6, 164, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #321 = BRR
534 { 320, 3, 0, 4, 1, 1, 0, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #320 = BRIND_CCA
535 { 319, 2, 0, 4, 1, 1, 0, LanaiImpOpBase + 6, 162, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = BRIND_CC
536 { 318, 2, 0, 4, 2, 1, 0, LanaiImpOpBase + 6, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = BRCC
537 { 317, 4, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = AND_R
538 { 316, 3, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = AND_I_LO
539 { 315, 3, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = AND_I_HI
540 { 314, 4, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = AND_F_R
541 { 313, 3, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #313 = AND_F_I_LO
542 { 312, 3, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #312 = AND_F_I_HI
543 { 311, 4, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #311 = ADD_R
544 { 310, 3, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = ADD_I_LO
545 { 309, 3, 1, 4, 1, 0, 0, LanaiImpOpBase + 0, 155, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = ADD_I_HI
546 { 308, 4, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = ADD_F_R
547 { 307, 3, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #307 = ADD_F_I_LO
548 { 306, 3, 1, 4, 1, 0, 1, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #306 = ADD_F_I_HI
549 { 305, 4, 1, 4, 1, 1, 0, LanaiImpOpBase + 6, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #305 = ADDC_R
550 { 304, 3, 1, 4, 1, 1, 0, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #304 = ADDC_I_LO
551 { 303, 3, 1, 4, 1, 1, 0, LanaiImpOpBase + 6, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #303 = ADDC_I_HI
552 { 302, 4, 1, 4, 1, 1, 1, LanaiImpOpBase + 4, 158, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = ADDC_F_R
553 { 301, 3, 1, 4, 1, 1, 1, LanaiImpOpBase + 4, 155, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = ADDC_F_I_LO
554 { 300, 3, 1, 4, 1, 1, 1, LanaiImpOpBase + 4, 155, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = ADDC_F_I_HI
555 { 299, 1, 0, 4, 0, 1, 1, LanaiImpOpBase + 2, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #299 = CALLR
556 { 298, 1, 0, 4, 0, 1, 1, LanaiImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #298 = CALL
557 { 297, 2, 1, 4, 0, 1, 1, LanaiImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #297 = ADJDYNALLOC
558 { 296, 2, 0, 4, 0, 1, 1, LanaiImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = ADJCALLSTACKUP
559 { 295, 2, 0, 4, 0, 1, 1, LanaiImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = ADJCALLSTACKDOWN
560 { 294, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_UBFX
561 { 293, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_SBFX
562 { 292, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMIN
563 { 291, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_UMAX
564 { 290, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMIN
565 { 289, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_VECREDUCE_SMAX
566 { 288, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_VECREDUCE_XOR
567 { 287, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_VECREDUCE_OR
568 { 286, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_VECREDUCE_AND
569 { 285, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_VECREDUCE_MUL
570 { 284, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_VECREDUCE_ADD
571 { 283, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMINIMUM
572 { 282, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMAXIMUM
573 { 281, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMIN
574 { 280, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMAX
575 { 279, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_VECREDUCE_FMUL
576 { 278, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_VECREDUCE_FADD
577 { 277, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FMUL
578 { 276, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_VECREDUCE_SEQ_FADD
579 { 275, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_UBSANTRAP
580 { 274, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #274 = G_DEBUGTRAP
581 { 273, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #273 = G_TRAP
582 { 272, 3, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #272 = G_BZERO
583 { 271, 4, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_MEMSET
584 { 270, 4, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_MEMMOVE
585 { 269, 3, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_MEMCPY_INLINE
586 { 268, 4, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #268 = G_MEMCPY
587 { 267, 2, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_WRITE_REGISTER
588 { 266, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #266 = G_READ_REGISTER
589 { 265, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_STRICT_FLDEXP
590 { 264, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_STRICT_FSQRT
591 { 263, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_STRICT_FMA
592 { 262, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_STRICT_FREM
593 { 261, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_STRICT_FDIV
594 { 260, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_STRICT_FMUL
595 { 259, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_STRICT_FSUB
596 { 258, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_STRICT_FADD
597 { 257, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_STACKRESTORE
598 { 256, 1, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_STACKSAVE
599 { 255, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_DYN_STACKALLOC
600 { 254, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_JUMP_TABLE
601 { 253, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_BLOCK_ADDR
602 { 252, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_ADDRSPACE_CAST
603 { 251, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FNEARBYINT
604 { 250, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_FRINT
605 { 249, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_FFLOOR
606 { 248, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_FSQRT
607 { 247, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_FTANH
608 { 246, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_FSINH
609 { 245, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_FCOSH
610 { 244, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_FATAN
611 { 243, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_FASIN
612 { 242, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_FACOS
613 { 241, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_FTAN
614 { 240, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_FSIN
615 { 239, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_FCOS
616 { 238, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_FCEIL
617 { 237, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_BITREVERSE
618 { 236, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_BSWAP
619 { 235, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_CTPOP
620 { 234, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_CTLZ_ZERO_UNDEF
621 { 233, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_CTLZ
622 { 232, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_CTTZ_ZERO_UNDEF
623 { 231, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_CTTZ
624 { 230, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_VECTOR_COMPRESS
625 { 229, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_SPLAT_VECTOR
626 { 228, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_SHUFFLE_VECTOR
627 { 227, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_EXTRACT_VECTOR_ELT
628 { 226, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_INSERT_VECTOR_ELT
629 { 225, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_EXTRACT_SUBVECTOR
630 { 224, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_INSERT_SUBVECTOR
631 { 223, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_VSCALE
632 { 222, 3, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_BRJT
633 { 221, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_BR
634 { 220, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_LLROUND
635 { 219, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_LROUND
636 { 218, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_ABS
637 { 217, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_UMAX
638 { 216, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_UMIN
639 { 215, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_SMAX
640 { 214, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_SMIN
641 { 213, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_PTRMASK
642 { 212, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_PTR_ADD
643 { 211, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_RESET_FPMODE
644 { 210, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_SET_FPMODE
645 { 209, 1, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_GET_FPMODE
646 { 208, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_RESET_FPENV
647 { 207, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_SET_FPENV
648 { 206, 1, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_GET_FPENV
649 { 205, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FMAXIMUM
650 { 204, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_FMINIMUM
651 { 203, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_FMAXNUM_IEEE
652 { 202, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_FMINNUM_IEEE
653 { 201, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FMAXNUM
654 { 200, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FMINNUM
655 { 199, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_FCANONICALIZE
656 { 198, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_IS_FPCLASS
657 { 197, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FCOPYSIGN
658 { 196, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_FABS
659 { 195, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_UITOFP
660 { 194, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_SITOFP
661 { 193, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FPTOUI
662 { 192, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FPTOSI
663 { 191, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FPTRUNC
664 { 190, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FPEXT
665 { 189, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FNEG
666 { 188, 3, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FFREXP
667 { 187, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FLDEXP
668 { 186, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FLOG10
669 { 185, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FLOG2
670 { 184, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FLOG
671 { 183, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FEXP10
672 { 182, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FEXP2
673 { 181, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FEXP
674 { 180, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FPOWI
675 { 179, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #179 = G_FPOW
676 { 178, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #178 = G_FREM
677 { 177, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #177 = G_FDIV
678 { 176, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #176 = G_FMAD
679 { 175, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #175 = G_FMA
680 { 174, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #174 = G_FMUL
681 { 173, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #173 = G_FSUB
682 { 172, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #172 = G_FADD
683 { 171, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #171 = G_UDIVFIXSAT
684 { 170, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #170 = G_SDIVFIXSAT
685 { 169, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #169 = G_UDIVFIX
686 { 168, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #168 = G_SDIVFIX
687 { 167, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #167 = G_UMULFIXSAT
688 { 166, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #166 = G_SMULFIXSAT
689 { 165, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #165 = G_UMULFIX
690 { 164, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #164 = G_SMULFIX
691 { 163, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #163 = G_SSHLSAT
692 { 162, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #162 = G_USHLSAT
693 { 161, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #161 = G_SSUBSAT
694 { 160, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #160 = G_USUBSAT
695 { 159, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #159 = G_SADDSAT
696 { 158, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #158 = G_UADDSAT
697 { 157, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #157 = G_SMULH
698 { 156, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #156 = G_UMULH
699 { 155, 4, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #155 = G_SMULO
700 { 154, 4, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #154 = G_UMULO
701 { 153, 5, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #153 = G_SSUBE
702 { 152, 4, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #152 = G_SSUBO
703 { 151, 5, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #151 = G_SADDE
704 { 150, 4, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #150 = G_SADDO
705 { 149, 5, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #149 = G_USUBE
706 { 148, 4, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #148 = G_USUBO
707 { 147, 5, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #147 = G_UADDE
708 { 146, 4, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #146 = G_UADDO
709 { 145, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #145 = G_SELECT
710 { 144, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #144 = G_UCMP
711 { 143, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #143 = G_SCMP
712 { 142, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #142 = G_FCMP
713 { 141, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #141 = G_ICMP
714 { 140, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #140 = G_ROTL
715 { 139, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #139 = G_ROTR
716 { 138, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #138 = G_FSHR
717 { 137, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #137 = G_FSHL
718 { 136, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #136 = G_ASHR
719 { 135, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #135 = G_LSHR
720 { 134, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #134 = G_SHL
721 { 133, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #133 = G_ZEXT
722 { 132, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #132 = G_SEXT_INREG
723 { 131, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #131 = G_SEXT
724 { 130, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #130 = G_VAARG
725 { 129, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #129 = G_VASTART
726 { 128, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #128 = G_FCONSTANT
727 { 127, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #127 = G_CONSTANT
728 { 126, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #126 = G_TRUNC
729 { 125, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #125 = G_ANYEXT
730 { 124, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
731 { 123, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #123 = G_INTRINSIC_CONVERGENT
732 { 122, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #122 = G_INTRINSIC_W_SIDE_EFFECTS
733 { 121, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #121 = G_INTRINSIC
734 { 120, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #120 = G_INVOKE_REGION_START
735 { 119, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #119 = G_BRINDIRECT
736 { 118, 2, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #118 = G_BRCOND
737 { 117, 4, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #117 = G_PREFETCH
738 { 116, 2, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #116 = G_FENCE
739 { 115, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UDEC_WRAP
740 { 114, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #114 = G_ATOMICRMW_UINC_WRAP
741 { 113, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMIN
742 { 112, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FMAX
743 { 111, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FSUB
744 { 110, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #110 = G_ATOMICRMW_FADD
745 { 109, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMIN
746 { 108, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #108 = G_ATOMICRMW_UMAX
747 { 107, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MIN
748 { 106, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #106 = G_ATOMICRMW_MAX
749 { 105, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #105 = G_ATOMICRMW_XOR
750 { 104, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #104 = G_ATOMICRMW_OR
751 { 103, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #103 = G_ATOMICRMW_NAND
752 { 102, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #102 = G_ATOMICRMW_AND
753 { 101, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #101 = G_ATOMICRMW_SUB
754 { 100, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #100 = G_ATOMICRMW_ADD
755 { 99, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #99 = G_ATOMICRMW_XCHG
756 { 98, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG
757 { 97, 5, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #97 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
758 { 96, 5, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #96 = G_INDEXED_STORE
759 { 95, 2, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #95 = G_STORE
760 { 94, 5, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #94 = G_INDEXED_ZEXTLOAD
761 { 93, 5, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #93 = G_INDEXED_SEXTLOAD
762 { 92, 5, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #92 = G_INDEXED_LOAD
763 { 91, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #91 = G_ZEXTLOAD
764 { 90, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #90 = G_SEXTLOAD
765 { 89, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #89 = G_LOAD
766 { 88, 1, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #88 = G_READSTEADYCOUNTER
767 { 87, 1, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #87 = G_READCYCLECOUNTER
768 { 86, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #86 = G_INTRINSIC_ROUNDEVEN
769 { 85, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #85 = G_INTRINSIC_LLRINT
770 { 84, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #84 = G_INTRINSIC_LRINT
771 { 83, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #83 = G_INTRINSIC_ROUND
772 { 82, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #82 = G_INTRINSIC_TRUNC
773 { 81, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #81 = G_INTRINSIC_FPTRUNC_ROUND
774 { 80, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #80 = G_CONSTANT_FOLD_BARRIER
775 { 79, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #79 = G_FREEZE
776 { 78, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #78 = G_BITCAST
777 { 77, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #77 = G_INTTOPTR
778 { 76, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #76 = G_PTRTOINT
779 { 75, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #75 = G_CONCAT_VECTORS
780 { 74, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR_TRUNC
781 { 73, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #73 = G_BUILD_VECTOR
782 { 72, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #72 = G_MERGE_VALUES
783 { 71, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #71 = G_INSERT
784 { 70, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #70 = G_UNMERGE_VALUES
785 { 69, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #69 = G_EXTRACT
786 { 68, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #68 = G_CONSTANT_POOL
787 { 67, 5, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #67 = G_PTRAUTH_GLOBAL_VALUE
788 { 66, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #66 = G_GLOBAL_VALUE
789 { 65, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #65 = G_FRAME_INDEX
790 { 64, 1, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #64 = G_PHI
791 { 63, 1, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #63 = G_IMPLICIT_DEF
792 { 62, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #62 = G_XOR
793 { 61, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #61 = G_OR
794 { 60, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #60 = G_AND
795 { 59, 4, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #59 = G_UDIVREM
796 { 58, 4, 2, 0, 0, 0, 0, LanaiImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #58 = G_SDIVREM
797 { 57, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #57 = G_UREM
798 { 56, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #56 = G_SREM
799 { 55, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #55 = G_UDIV
800 { 54, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #54 = G_SDIV
801 { 53, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #53 = G_MUL
802 { 52, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #52 = G_SUB
803 { 51, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #51 = G_ADD
804 { 50, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #50 = G_ASSERT_ALIGN
805 { 49, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #49 = G_ASSERT_ZEXT
806 { 48, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #48 = G_ASSERT_SEXT
807 { 47, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_GLUE
808 { 46, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_LOOP
809 { 45, 1, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ANCHOR
810 { 44, 1, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #44 = CONVERGENCECTRL_ENTRY
811 { 43, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #43 = JUMP_TABLE_DEBUG_INFO
812 { 42, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #42 = MEMBARRIER
813 { 41, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL
814 { 40, 3, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
815 { 39, 2, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL
816 { 38, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL
817 { 37, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT
818 { 36, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #36 = PATCHABLE_RET
819 { 35, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER
820 { 34, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #34 = PATCHABLE_OP
821 { 33, 1, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #33 = FAULTING_OP
822 { 32, 2, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE
823 { 31, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #31 = STATEPOINT
824 { 30, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG
825 { 29, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP
826 { 28, 1, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD
827 { 27, 6, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #27 = PATCHPOINT
828 { 26, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #26 = FENTRY_CALL
829 { 25, 2, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #25 = STACKMAP
830 { 24, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #24 = ARITH_FENCE
831 { 23, 4, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #23 = PSEUDO_PROBE
832 { 22, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #22 = LIFETIME_END
833 { 21, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #21 = LIFETIME_START
834 { 20, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #20 = BUNDLE
835 { 19, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #19 = COPY
836 { 18, 2, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #18 = REG_SEQUENCE
837 { 17, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #17 = DBG_LABEL
838 { 16, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #16 = DBG_PHI
839 { 15, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #15 = DBG_INSTR_REF
840 { 14, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST
841 { 13, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #13 = DBG_VALUE
842 { 12, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS
843 { 11, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #11 = SUBREG_TO_REG
844 { 10, 1, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
845 { 9, 4, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #9 = INSERT_SUBREG
846 { 8, 3, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
847 { 7, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #7 = KILL
848 { 6, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
849 { 5, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #5 = GC_LABEL
850 { 4, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #4 = EH_LABEL
851 { 3, 1, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
852 { 2, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #2 = INLINEASM_BR
853 { 1, 0, 0, 0, 0, 0, 0, LanaiImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1 = INLINEASM
854 { 0, 1, 1, 0, 0, 0, 0, LanaiImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #0 = PHI
855 }, {
856 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
857 /* 1 */
858 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
859 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
860 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
861 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
862 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
863 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
864 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
865 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
866 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
867 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
868 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
869 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
870 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
871 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
872 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
873 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
874 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
875 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
876 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
877 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
878 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
879 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
880 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
881 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
882 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
883 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
884 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
885 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
886 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
887 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
888 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
889 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
890 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
891 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
892 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
893 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
894 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
895 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
896 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
897 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
898 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
899 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
900 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
901 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
902 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
903 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
904 /* 152 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
905 /* 154 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
906 /* 155 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
907 /* 158 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 },
908 /* 162 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
909 /* 164 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
910 /* 166 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
911 /* 170 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
912 /* 174 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
913 }, {
914 /* 0 */
915 /* 0 */ Lanai::SP, Lanai::SP,
916 /* 2 */ Lanai::SP, Lanai::RCA,
917 /* 4 */ Lanai::SR, Lanai::SR,
918 /* 6 */ Lanai::SR,
919 /* 7 */ Lanai::RCA,
920 }
921};
922
923
924#ifdef __GNUC__
925#pragma GCC diagnostic push
926#pragma GCC diagnostic ignored "-Woverlength-strings"
927#endif
928extern const char LanaiInstrNameData[] = {
929 /* 0 */ "G_FLOG10\0"
930 /* 9 */ "G_FEXP10\0"
931 /* 18 */ "LOG0\0"
932 /* 23 */ "LOG1\0"
933 /* 28 */ "G_FLOG2\0"
934 /* 36 */ "G_FEXP2\0"
935 /* 44 */ "LOG3\0"
936 /* 49 */ "LOG4\0"
937 /* 54 */ "BRIND_CCA\0"
938 /* 64 */ "G_FMA\0"
939 /* 70 */ "G_STRICT_FMA\0"
940 /* 83 */ "G_FSUB\0"
941 /* 90 */ "G_STRICT_FSUB\0"
942 /* 104 */ "G_ATOMICRMW_FSUB\0"
943 /* 121 */ "G_SUB\0"
944 /* 127 */ "G_ATOMICRMW_SUB\0"
945 /* 143 */ "BRCC\0"
946 /* 148 */ "SCC\0"
947 /* 152 */ "BRIND_CC\0"
948 /* 161 */ "G_INTRINSIC\0"
949 /* 173 */ "G_FPTRUNC\0"
950 /* 183 */ "G_INTRINSIC_TRUNC\0"
951 /* 201 */ "G_TRUNC\0"
952 /* 209 */ "G_BUILD_VECTOR_TRUNC\0"
953 /* 230 */ "G_DYN_STACKALLOC\0"
954 /* 247 */ "ADJDYNALLOC\0"
955 /* 259 */ "POPC\0"
956 /* 264 */ "G_FMAD\0"
957 /* 271 */ "G_INDEXED_SEXTLOAD\0"
958 /* 290 */ "G_SEXTLOAD\0"
959 /* 301 */ "G_INDEXED_ZEXTLOAD\0"
960 /* 320 */ "G_ZEXTLOAD\0"
961 /* 331 */ "G_INDEXED_LOAD\0"
962 /* 346 */ "G_LOAD\0"
963 /* 353 */ "G_VECREDUCE_FADD\0"
964 /* 370 */ "G_FADD\0"
965 /* 377 */ "G_VECREDUCE_SEQ_FADD\0"
966 /* 398 */ "G_STRICT_FADD\0"
967 /* 412 */ "G_ATOMICRMW_FADD\0"
968 /* 429 */ "G_VECREDUCE_ADD\0"
969 /* 445 */ "G_ADD\0"
970 /* 451 */ "G_PTR_ADD\0"
971 /* 461 */ "G_ATOMICRMW_ADD\0"
972 /* 477 */ "G_ATOMICRMW_NAND\0"
973 /* 494 */ "G_VECREDUCE_AND\0"
974 /* 510 */ "G_AND\0"
975 /* 516 */ "G_ATOMICRMW_AND\0"
976 /* 532 */ "LIFETIME_END\0"
977 /* 545 */ "G_BRCOND\0"
978 /* 554 */ "G_LLROUND\0"
979 /* 564 */ "G_LROUND\0"
980 /* 573 */ "G_INTRINSIC_ROUND\0"
981 /* 591 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
982 /* 617 */ "LOAD_STACK_GUARD\0"
983 /* 634 */ "PSEUDO_PROBE\0"
984 /* 647 */ "G_SSUBE\0"
985 /* 655 */ "G_USUBE\0"
986 /* 663 */ "G_FENCE\0"
987 /* 671 */ "ARITH_FENCE\0"
988 /* 683 */ "REG_SEQUENCE\0"
989 /* 696 */ "G_SADDE\0"
990 /* 704 */ "G_UADDE\0"
991 /* 712 */ "G_GET_FPMODE\0"
992 /* 725 */ "G_RESET_FPMODE\0"
993 /* 740 */ "G_SET_FPMODE\0"
994 /* 753 */ "G_FMINNUM_IEEE\0"
995 /* 768 */ "G_FMAXNUM_IEEE\0"
996 /* 783 */ "G_VSCALE\0"
997 /* 792 */ "G_JUMP_TABLE\0"
998 /* 805 */ "BUNDLE\0"
999 /* 812 */ "G_MEMCPY_INLINE\0"
1000 /* 828 */ "LOCAL_ESCAPE\0"
1001 /* 841 */ "G_STACKRESTORE\0"
1002 /* 856 */ "G_INDEXED_STORE\0"
1003 /* 872 */ "G_STORE\0"
1004 /* 880 */ "G_BITREVERSE\0"
1005 /* 893 */ "DBG_VALUE\0"
1006 /* 903 */ "G_GLOBAL_VALUE\0"
1007 /* 918 */ "G_PTRAUTH_GLOBAL_VALUE\0"
1008 /* 941 */ "CONVERGENCECTRL_GLUE\0"
1009 /* 962 */ "G_STACKSAVE\0"
1010 /* 974 */ "G_MEMMOVE\0"
1011 /* 984 */ "G_FREEZE\0"
1012 /* 993 */ "G_FCANONICALIZE\0"
1013 /* 1009 */ "G_CTLZ_ZERO_UNDEF\0"
1014 /* 1027 */ "G_CTTZ_ZERO_UNDEF\0"
1015 /* 1045 */ "G_IMPLICIT_DEF\0"
1016 /* 1060 */ "DBG_INSTR_REF\0"
1017 /* 1074 */ "G_FNEG\0"
1018 /* 1081 */ "EXTRACT_SUBREG\0"
1019 /* 1096 */ "INSERT_SUBREG\0"
1020 /* 1110 */ "G_SEXT_INREG\0"
1021 /* 1123 */ "SUBREG_TO_REG\0"
1022 /* 1137 */ "G_ATOMIC_CMPXCHG\0"
1023 /* 1154 */ "G_ATOMICRMW_XCHG\0"
1024 /* 1171 */ "G_FLOG\0"
1025 /* 1178 */ "G_VAARG\0"
1026 /* 1186 */ "PREALLOCATED_ARG\0"
1027 /* 1203 */ "G_PREFETCH\0"
1028 /* 1214 */ "G_SMULH\0"
1029 /* 1222 */ "G_UMULH\0"
1030 /* 1230 */ "G_FTANH\0"
1031 /* 1238 */ "G_FSINH\0"
1032 /* 1246 */ "G_FCOSH\0"
1033 /* 1254 */ "DBG_PHI\0"
1034 /* 1262 */ "MOVHI\0"
1035 /* 1268 */ "SFSUB_F_RI_HI\0"
1036 /* 1282 */ "SUBB_I_HI\0"
1037 /* 1292 */ "SUB_I_HI\0"
1038 /* 1301 */ "ADDC_I_HI\0"
1039 /* 1311 */ "ADD_I_HI\0"
1040 /* 1320 */ "AND_I_HI\0"
1041 /* 1329 */ "SUBB_F_I_HI\0"
1042 /* 1341 */ "SUB_F_I_HI\0"
1043 /* 1352 */ "ADDC_F_I_HI\0"
1044 /* 1364 */ "ADD_F_I_HI\0"
1045 /* 1375 */ "AND_F_I_HI\0"
1046 /* 1386 */ "XOR_F_I_HI\0"
1047 /* 1397 */ "XOR_I_HI\0"
1048 /* 1406 */ "SLI\0"
1049 /* 1410 */ "STB_RI\0"
1050 /* 1417 */ "STH_RI\0"
1051 /* 1424 */ "LDW_RI\0"
1052 /* 1431 */ "SW_RI\0"
1053 /* 1437 */ "LDBs_RI\0"
1054 /* 1445 */ "LDHs_RI\0"
1055 /* 1453 */ "LDBz_RI\0"
1056 /* 1461 */ "LDHz_RI\0"
1057 /* 1469 */ "G_FPTOSI\0"
1058 /* 1478 */ "G_FPTOUI\0"
1059 /* 1487 */ "G_FPOWI\0"
1060 /* 1495 */ "SA_I\0"
1061 /* 1500 */ "SA_F_I\0"
1062 /* 1507 */ "SL_F_I\0"
1063 /* 1514 */ "SL_I\0"
1064 /* 1519 */ "G_PTRMASK\0"
1065 /* 1529 */ "GC_LABEL\0"
1066 /* 1538 */ "DBG_LABEL\0"
1067 /* 1548 */ "EH_LABEL\0"
1068 /* 1557 */ "ANNOTATION_LABEL\0"
1069 /* 1574 */ "ICALL_BRANCH_FUNNEL\0"
1070 /* 1594 */ "G_FSHL\0"
1071 /* 1601 */ "G_SHL\0"
1072 /* 1607 */ "G_FCEIL\0"
1073 /* 1615 */ "PATCHABLE_TAIL_CALL\0"
1074 /* 1635 */ "PATCHABLE_TYPED_EVENT_CALL\0"
1075 /* 1662 */ "PATCHABLE_EVENT_CALL\0"
1076 /* 1683 */ "FENTRY_CALL\0"
1077 /* 1695 */ "KILL\0"
1078 /* 1700 */ "G_CONSTANT_POOL\0"
1079 /* 1716 */ "G_ROTL\0"
1080 /* 1723 */ "G_VECREDUCE_FMUL\0"
1081 /* 1740 */ "G_FMUL\0"
1082 /* 1747 */ "G_VECREDUCE_SEQ_FMUL\0"
1083 /* 1768 */ "G_STRICT_FMUL\0"
1084 /* 1782 */ "G_VECREDUCE_MUL\0"
1085 /* 1798 */ "G_MUL\0"
1086 /* 1804 */ "G_FREM\0"
1087 /* 1811 */ "G_STRICT_FREM\0"
1088 /* 1825 */ "G_SREM\0"
1089 /* 1832 */ "G_UREM\0"
1090 /* 1839 */ "G_SDIVREM\0"
1091 /* 1849 */ "G_UDIVREM\0"
1092 /* 1859 */ "INLINEASM\0"
1093 /* 1869 */ "G_VECREDUCE_FMINIMUM\0"
1094 /* 1890 */ "G_FMINIMUM\0"
1095 /* 1901 */ "G_VECREDUCE_FMAXIMUM\0"
1096 /* 1922 */ "G_FMAXIMUM\0"
1097 /* 1933 */ "G_FMINNUM\0"
1098 /* 1943 */ "G_FMAXNUM\0"
1099 /* 1953 */ "G_FATAN\0"
1100 /* 1961 */ "G_FTAN\0"
1101 /* 1968 */ "G_INTRINSIC_ROUNDEVEN\0"
1102 /* 1990 */ "G_ASSERT_ALIGN\0"
1103 /* 2005 */ "G_FCOPYSIGN\0"
1104 /* 2017 */ "G_VECREDUCE_FMIN\0"
1105 /* 2034 */ "G_ATOMICRMW_FMIN\0"
1106 /* 2051 */ "G_VECREDUCE_SMIN\0"
1107 /* 2068 */ "G_SMIN\0"
1108 /* 2075 */ "G_VECREDUCE_UMIN\0"
1109 /* 2092 */ "G_UMIN\0"
1110 /* 2099 */ "G_ATOMICRMW_UMIN\0"
1111 /* 2116 */ "G_ATOMICRMW_MIN\0"
1112 /* 2132 */ "G_FASIN\0"
1113 /* 2140 */ "G_FSIN\0"
1114 /* 2147 */ "CFI_INSTRUCTION\0"
1115 /* 2163 */ "ADJCALLSTACKDOWN\0"
1116 /* 2180 */ "G_SSUBO\0"
1117 /* 2188 */ "G_USUBO\0"
1118 /* 2196 */ "G_SADDO\0"
1119 /* 2204 */ "G_UADDO\0"
1120 /* 2212 */ "JUMP_TABLE_DEBUG_INFO\0"
1121 /* 2234 */ "G_SMULO\0"
1122 /* 2242 */ "G_UMULO\0"
1123 /* 2250 */ "SFSUB_F_RI_LO\0"
1124 /* 2264 */ "SUBB_I_LO\0"
1125 /* 2274 */ "SUB_I_LO\0"
1126 /* 2283 */ "ADDC_I_LO\0"
1127 /* 2293 */ "ADD_I_LO\0"
1128 /* 2302 */ "AND_I_LO\0"
1129 /* 2311 */ "SUBB_F_I_LO\0"
1130 /* 2323 */ "SUB_F_I_LO\0"
1131 /* 2334 */ "ADDC_F_I_LO\0"
1132 /* 2346 */ "ADD_F_I_LO\0"
1133 /* 2357 */ "AND_F_I_LO\0"
1134 /* 2368 */ "XOR_F_I_LO\0"
1135 /* 2379 */ "XOR_I_LO\0"
1136 /* 2388 */ "G_BZERO\0"
1137 /* 2396 */ "STACKMAP\0"
1138 /* 2405 */ "G_DEBUGTRAP\0"
1139 /* 2417 */ "G_UBSANTRAP\0"
1140 /* 2429 */ "G_TRAP\0"
1141 /* 2436 */ "G_ATOMICRMW_UDEC_WRAP\0"
1142 /* 2458 */ "G_ATOMICRMW_UINC_WRAP\0"
1143 /* 2480 */ "G_BSWAP\0"
1144 /* 2488 */ "G_SITOFP\0"
1145 /* 2497 */ "G_UITOFP\0"
1146 /* 2506 */ "G_FCMP\0"
1147 /* 2513 */ "G_ICMP\0"
1148 /* 2520 */ "G_SCMP\0"
1149 /* 2527 */ "G_UCMP\0"
1150 /* 2534 */ "NOP\0"
1151 /* 2538 */ "CONVERGENCECTRL_LOOP\0"
1152 /* 2559 */ "G_CTPOP\0"
1153 /* 2567 */ "PATCHABLE_OP\0"
1154 /* 2580 */ "FAULTING_OP\0"
1155 /* 2592 */ "ADJCALLSTACKUP\0"
1156 /* 2607 */ "PREALLOCATED_SETUP\0"
1157 /* 2626 */ "G_FLDEXP\0"
1158 /* 2635 */ "G_STRICT_FLDEXP\0"
1159 /* 2651 */ "G_FEXP\0"
1160 /* 2658 */ "G_FFREXP\0"
1161 /* 2667 */ "G_BR\0"
1162 /* 2672 */ "INLINEASM_BR\0"
1163 /* 2685 */ "LDADDR\0"
1164 /* 2692 */ "STADDR\0"
1165 /* 2699 */ "G_BLOCK_ADDR\0"
1166 /* 2712 */ "MEMBARRIER\0"
1167 /* 2723 */ "G_CONSTANT_FOLD_BARRIER\0"
1168 /* 2747 */ "PATCHABLE_FUNCTION_ENTER\0"
1169 /* 2772 */ "G_READCYCLECOUNTER\0"
1170 /* 2791 */ "G_READSTEADYCOUNTER\0"
1171 /* 2811 */ "G_READ_REGISTER\0"
1172 /* 2827 */ "G_WRITE_REGISTER\0"
1173 /* 2844 */ "G_ASHR\0"
1174 /* 2851 */ "G_FSHR\0"
1175 /* 2858 */ "G_LSHR\0"
1176 /* 2865 */ "JR\0"
1177 /* 2868 */ "CALLR\0"
1178 /* 2874 */ "CONVERGENCECTRL_ANCHOR\0"
1179 /* 2897 */ "G_FFLOOR\0"
1180 /* 2906 */ "G_EXTRACT_SUBVECTOR\0"
1181 /* 2926 */ "G_INSERT_SUBVECTOR\0"
1182 /* 2945 */ "G_BUILD_VECTOR\0"
1183 /* 2960 */ "G_SHUFFLE_VECTOR\0"
1184 /* 2977 */ "G_SPLAT_VECTOR\0"
1185 /* 2992 */ "G_VECREDUCE_XOR\0"
1186 /* 3008 */ "G_XOR\0"
1187 /* 3014 */ "G_ATOMICRMW_XOR\0"
1188 /* 3030 */ "G_VECREDUCE_OR\0"
1189 /* 3045 */ "G_OR\0"
1190 /* 3050 */ "G_ATOMICRMW_OR\0"
1191 /* 3065 */ "BRR\0"
1192 /* 3069 */ "STB_RR\0"
1193 /* 3076 */ "SFSUB_F_RR\0"
1194 /* 3087 */ "STH_RR\0"
1195 /* 3094 */ "LDW_RR\0"
1196 /* 3101 */ "SW_RR\0"
1197 /* 3107 */ "LDBs_RR\0"
1198 /* 3115 */ "LDHs_RR\0"
1199 /* 3123 */ "LDBz_RR\0"
1200 /* 3131 */ "LDHz_RR\0"
1201 /* 3139 */ "LDWz_RR\0"
1202 /* 3147 */ "G_ROTR\0"
1203 /* 3154 */ "G_INTTOPTR\0"
1204 /* 3165 */ "SRA_R\0"
1205 /* 3171 */ "SUBB_R\0"
1206 /* 3178 */ "SUB_R\0"
1207 /* 3184 */ "ADDC_R\0"
1208 /* 3191 */ "ADD_R\0"
1209 /* 3197 */ "AND_R\0"
1210 /* 3203 */ "SRA_F_R\0"
1211 /* 3211 */ "SUBB_F_R\0"
1212 /* 3220 */ "SUB_F_R\0"
1213 /* 3228 */ "ADDC_F_R\0"
1214 /* 3237 */ "ADD_F_R\0"
1215 /* 3245 */ "AND_F_R\0"
1216 /* 3253 */ "SHL_F_R\0"
1217 /* 3261 */ "SRL_F_R\0"
1218 /* 3269 */ "XOR_F_R\0"
1219 /* 3277 */ "SHL_R\0"
1220 /* 3283 */ "SRL_R\0"
1221 /* 3289 */ "XOR_R\0"
1222 /* 3295 */ "G_FABS\0"
1223 /* 3302 */ "G_ABS\0"
1224 /* 3308 */ "G_UNMERGE_VALUES\0"
1225 /* 3325 */ "G_MERGE_VALUES\0"
1226 /* 3340 */ "G_FACOS\0"
1227 /* 3348 */ "G_FCOS\0"
1228 /* 3355 */ "G_CONCAT_VECTORS\0"
1229 /* 3372 */ "COPY_TO_REGCLASS\0"
1230 /* 3389 */ "G_IS_FPCLASS\0"
1231 /* 3402 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
1232 /* 3432 */ "G_VECTOR_COMPRESS\0"
1233 /* 3450 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
1234 /* 3477 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
1235 /* 3515 */ "G_SSUBSAT\0"
1236 /* 3525 */ "G_USUBSAT\0"
1237 /* 3535 */ "G_SADDSAT\0"
1238 /* 3545 */ "G_UADDSAT\0"
1239 /* 3555 */ "G_SSHLSAT\0"
1240 /* 3565 */ "G_USHLSAT\0"
1241 /* 3575 */ "G_SMULFIXSAT\0"
1242 /* 3588 */ "G_UMULFIXSAT\0"
1243 /* 3601 */ "G_SDIVFIXSAT\0"
1244 /* 3614 */ "G_UDIVFIXSAT\0"
1245 /* 3627 */ "BT\0"
1246 /* 3630 */ "G_EXTRACT\0"
1247 /* 3640 */ "G_SELECT\0"
1248 /* 3649 */ "G_BRINDIRECT\0"
1249 /* 3662 */ "PATCHABLE_RET\0"
1250 /* 3676 */ "G_MEMSET\0"
1251 /* 3685 */ "PATCHABLE_FUNCTION_EXIT\0"
1252 /* 3709 */ "G_BRJT\0"
1253 /* 3716 */ "G_EXTRACT_VECTOR_ELT\0"
1254 /* 3737 */ "G_INSERT_VECTOR_ELT\0"
1255 /* 3757 */ "G_FCONSTANT\0"
1256 /* 3769 */ "G_CONSTANT\0"
1257 /* 3780 */ "G_INTRINSIC_CONVERGENT\0"
1258 /* 3803 */ "STATEPOINT\0"
1259 /* 3814 */ "PATCHPOINT\0"
1260 /* 3825 */ "G_PTRTOINT\0"
1261 /* 3836 */ "G_FRINT\0"
1262 /* 3844 */ "G_INTRINSIC_LLRINT\0"
1263 /* 3863 */ "G_INTRINSIC_LRINT\0"
1264 /* 3881 */ "G_FNEARBYINT\0"
1265 /* 3894 */ "G_VASTART\0"
1266 /* 3904 */ "LIFETIME_START\0"
1267 /* 3919 */ "G_INVOKE_REGION_START\0"
1268 /* 3941 */ "G_INSERT\0"
1269 /* 3950 */ "G_FSQRT\0"
1270 /* 3958 */ "G_STRICT_FSQRT\0"
1271 /* 3973 */ "G_BITCAST\0"
1272 /* 3983 */ "G_ADDRSPACE_CAST\0"
1273 /* 4000 */ "DBG_VALUE_LIST\0"
1274 /* 4015 */ "G_FPEXT\0"
1275 /* 4023 */ "G_SEXT\0"
1276 /* 4030 */ "G_ASSERT_SEXT\0"
1277 /* 4044 */ "G_ANYEXT\0"
1278 /* 4053 */ "G_ZEXT\0"
1279 /* 4060 */ "G_ASSERT_ZEXT\0"
1280 /* 4074 */ "G_FDIV\0"
1281 /* 4081 */ "G_STRICT_FDIV\0"
1282 /* 4095 */ "G_SDIV\0"
1283 /* 4102 */ "G_UDIV\0"
1284 /* 4109 */ "G_GET_FPENV\0"
1285 /* 4121 */ "G_RESET_FPENV\0"
1286 /* 4135 */ "G_SET_FPENV\0"
1287 /* 4147 */ "G_FPOW\0"
1288 /* 4154 */ "G_VECREDUCE_FMAX\0"
1289 /* 4171 */ "G_ATOMICRMW_FMAX\0"
1290 /* 4188 */ "G_VECREDUCE_SMAX\0"
1291 /* 4205 */ "G_SMAX\0"
1292 /* 4212 */ "G_VECREDUCE_UMAX\0"
1293 /* 4229 */ "G_UMAX\0"
1294 /* 4236 */ "G_ATOMICRMW_UMAX\0"
1295 /* 4253 */ "G_ATOMICRMW_MAX\0"
1296 /* 4269 */ "G_FRAME_INDEX\0"
1297 /* 4283 */ "G_SBFX\0"
1298 /* 4290 */ "G_UBFX\0"
1299 /* 4297 */ "G_SMULFIX\0"
1300 /* 4307 */ "G_UMULFIX\0"
1301 /* 4317 */ "G_SDIVFIX\0"
1302 /* 4327 */ "G_UDIVFIX\0"
1303 /* 4337 */ "G_MEMCPY\0"
1304 /* 4346 */ "COPY\0"
1305 /* 4351 */ "CONVERGENCECTRL_ENTRY\0"
1306 /* 4373 */ "LEADZ\0"
1307 /* 4379 */ "TRAILZ\0"
1308 /* 4386 */ "G_CTLZ\0"
1309 /* 4393 */ "G_CTTZ\0"
1310};
1311#ifdef __GNUC__
1312#pragma GCC diagnostic pop
1313#endif
1314
1315extern const unsigned LanaiInstrNameIndices[] = {
1316 1258U, 1859U, 2672U, 2147U, 1548U, 1529U, 1557U, 1695U,
1317 1081U, 1096U, 1047U, 1123U, 3372U, 893U, 4000U, 1060U,
1318 1254U, 1538U, 683U, 4346U, 805U, 3904U, 532U, 634U,
1319 671U, 2396U, 1683U, 3814U, 617U, 2607U, 1186U, 3803U,
1320 828U, 2580U, 2567U, 2747U, 3662U, 3685U, 1615U, 1662U,
1321 1635U, 1574U, 2712U, 2212U, 4351U, 2874U, 2538U, 941U,
1322 4030U, 4060U, 1990U, 445U, 121U, 1798U, 4095U, 4102U,
1323 1825U, 1832U, 1839U, 1849U, 510U, 3045U, 3008U, 1045U,
1324 1256U, 4269U, 903U, 918U, 1700U, 3630U, 3308U, 3941U,
1325 3325U, 2945U, 209U, 3355U, 3825U, 3154U, 3973U, 984U,
1326 2723U, 591U, 183U, 573U, 3863U, 3844U, 1968U, 2772U,
1327 2791U, 346U, 290U, 320U, 331U, 271U, 301U, 872U,
1328 856U, 3402U, 1137U, 1154U, 461U, 127U, 516U, 477U,
1329 3050U, 3014U, 4253U, 2116U, 4236U, 2099U, 412U, 104U,
1330 4171U, 2034U, 2458U, 2436U, 663U, 1203U, 545U, 3649U,
1331 3919U, 161U, 3450U, 3780U, 3477U, 4044U, 201U, 3769U,
1332 3757U, 3894U, 1178U, 4023U, 1110U, 4053U, 1601U, 2858U,
1333 2844U, 1594U, 2851U, 3147U, 1716U, 2513U, 2506U, 2520U,
1334 2527U, 3640U, 2204U, 704U, 2188U, 655U, 2196U, 696U,
1335 2180U, 647U, 2242U, 2234U, 1222U, 1214U, 3545U, 3535U,
1336 3525U, 3515U, 3565U, 3555U, 4297U, 4307U, 3575U, 3588U,
1337 4317U, 4327U, 3601U, 3614U, 370U, 83U, 1740U, 64U,
1338 264U, 4074U, 1804U, 4147U, 1487U, 2651U, 36U, 9U,
1339 1171U, 28U, 0U, 2626U, 2658U, 1074U, 4015U, 173U,
1340 1469U, 1478U, 2488U, 2497U, 3295U, 2005U, 3389U, 993U,
1341 1933U, 1943U, 753U, 768U, 1890U, 1922U, 4109U, 4135U,
1342 4121U, 712U, 740U, 725U, 451U, 1519U, 2068U, 4205U,
1343 2092U, 4229U, 3302U, 564U, 554U, 2667U, 3709U, 783U,
1344 2926U, 2906U, 3737U, 3716U, 2960U, 2977U, 3432U, 4393U,
1345 1027U, 4386U, 1009U, 2559U, 2480U, 880U, 1607U, 3348U,
1346 2140U, 1961U, 3340U, 2132U, 1953U, 1246U, 1238U, 1230U,
1347 3950U, 2897U, 3836U, 3881U, 3983U, 2699U, 792U, 230U,
1348 962U, 841U, 398U, 90U, 1768U, 4081U, 1811U, 70U,
1349 3958U, 2635U, 2811U, 2827U, 4337U, 812U, 974U, 3676U,
1350 2388U, 2429U, 2405U, 2417U, 377U, 1747U, 353U, 1723U,
1351 4154U, 2017U, 1901U, 1869U, 429U, 1782U, 494U, 3030U,
1352 2992U, 4188U, 2051U, 4212U, 2075U, 4283U, 4290U, 2163U,
1353 2592U, 247U, 1630U, 2868U, 1352U, 2334U, 3228U, 1301U,
1354 2283U, 3184U, 1364U, 2346U, 3237U, 1311U, 2293U, 3191U,
1355 1375U, 2357U, 3245U, 1320U, 2302U, 3197U, 143U, 152U,
1356 54U, 3065U, 3627U, 2865U, 2685U, 1437U, 3107U, 1453U,
1357 3123U, 1445U, 3115U, 1461U, 3131U, 1424U, 3094U, 3139U,
1358 4373U, 18U, 23U, 31U, 44U, 49U, 1262U, 2534U,
1359 1387U, 2369U, 3270U, 1398U, 2380U, 3290U, 259U, 3672U,
1360 1500U, 1495U, 148U, 3642U, 1268U, 2250U, 3076U, 3253U,
1361 3277U, 1406U, 1507U, 1514U, 3203U, 3165U, 3261U, 3283U,
1362 2692U, 1410U, 3069U, 1417U, 3087U, 1329U, 2311U, 3211U,
1363 1282U, 2264U, 3171U, 1341U, 2323U, 3220U, 1292U, 2274U,
1364 3178U, 1431U, 3101U, 4379U, 1386U, 2368U, 3269U, 1397U,
1365 2379U, 3289U,
1366};
1367
1368static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
1369 II->InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 394);
1370}
1371
1372} // end namespace llvm
1373#endif // GET_INSTRINFO_MC_DESC
1374
1375#ifdef GET_INSTRINFO_HEADER
1376#undef GET_INSTRINFO_HEADER
1377namespace llvm {
1378struct LanaiGenInstrInfo : public TargetInstrInfo {
1379 explicit LanaiGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1380 ~LanaiGenInstrInfo() override = default;
1381
1382};
1383} // end namespace llvm
1384#endif // GET_INSTRINFO_HEADER
1385
1386#ifdef GET_INSTRINFO_HELPER_DECLS
1387#undef GET_INSTRINFO_HELPER_DECLS
1388
1389
1390#endif // GET_INSTRINFO_HELPER_DECLS
1391
1392#ifdef GET_INSTRINFO_HELPERS
1393#undef GET_INSTRINFO_HELPERS
1394
1395#endif // GET_INSTRINFO_HELPERS
1396
1397#ifdef GET_INSTRINFO_CTOR_DTOR
1398#undef GET_INSTRINFO_CTOR_DTOR
1399namespace llvm {
1400extern const LanaiInstrTable LanaiDescs;
1401extern const unsigned LanaiInstrNameIndices[];
1402extern const char LanaiInstrNameData[];
1403LanaiGenInstrInfo::LanaiGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1404 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1405 InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 394);
1406}
1407} // end namespace llvm
1408#endif // GET_INSTRINFO_CTOR_DTOR
1409
1410#ifdef GET_INSTRINFO_OPERAND_ENUM
1411#undef GET_INSTRINFO_OPERAND_ENUM
1412namespace llvm {
1413namespace Lanai {
1414namespace OpName {
1415enum {
1416 OPERAND_LAST
1417};
1418} // end namespace OpName
1419} // end namespace Lanai
1420} // end namespace llvm
1421#endif //GET_INSTRINFO_OPERAND_ENUM
1422
1423#ifdef GET_INSTRINFO_NAMED_OPS
1424#undef GET_INSTRINFO_NAMED_OPS
1425namespace llvm {
1426namespace Lanai {
1427LLVM_READONLY
1428int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1429 return -1;
1430}
1431} // end namespace Lanai
1432} // end namespace llvm
1433#endif //GET_INSTRINFO_NAMED_OPS
1434
1435#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1436#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1437namespace llvm {
1438namespace Lanai {
1439namespace OpTypes {
1440enum OperandType {
1441 AluOp = 0,
1442 BrTarget = 1,
1443 CCOp = 2,
1444 CallTarget = 3,
1445 MEMi = 4,
1446 MEMri = 5,
1447 MEMrr = 6,
1448 MEMspls = 7,
1449 f32imm = 8,
1450 f64imm = 9,
1451 i1imm = 10,
1452 i8imm = 11,
1453 i16imm = 12,
1454 i32hi16 = 13,
1455 i32hi16and = 14,
1456 i32imm = 15,
1457 i32lo16and = 16,
1458 i32lo16s = 17,
1459 i32lo16z = 18,
1460 i32lo21 = 19,
1461 i32neg16 = 20,
1462 i64imm = 21,
1463 imm10 = 22,
1464 immShift = 23,
1465 pred = 24,
1466 ptype0 = 25,
1467 ptype1 = 26,
1468 ptype2 = 27,
1469 ptype3 = 28,
1470 ptype4 = 29,
1471 ptype5 = 30,
1472 type0 = 31,
1473 type1 = 32,
1474 type2 = 33,
1475 type3 = 34,
1476 type4 = 35,
1477 type5 = 36,
1478 untyped_imm_0 = 37,
1479 CCR = 38,
1480 GPR = 39,
1481 OPERAND_TYPE_LIST_END
1482};
1483} // end namespace OpTypes
1484} // end namespace Lanai
1485} // end namespace llvm
1486#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1487
1488#ifdef GET_INSTRINFO_OPERAND_TYPE
1489#undef GET_INSTRINFO_OPERAND_TYPE
1490namespace llvm {
1491namespace Lanai {
1492LLVM_READONLY
1493static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
1494 static const uint16_t Offsets[] = {
1495 /* PHI */
1496 0,
1497 /* INLINEASM */
1498 1,
1499 /* INLINEASM_BR */
1500 1,
1501 /* CFI_INSTRUCTION */
1502 1,
1503 /* EH_LABEL */
1504 2,
1505 /* GC_LABEL */
1506 3,
1507 /* ANNOTATION_LABEL */
1508 4,
1509 /* KILL */
1510 5,
1511 /* EXTRACT_SUBREG */
1512 5,
1513 /* INSERT_SUBREG */
1514 8,
1515 /* IMPLICIT_DEF */
1516 12,
1517 /* SUBREG_TO_REG */
1518 13,
1519 /* COPY_TO_REGCLASS */
1520 17,
1521 /* DBG_VALUE */
1522 20,
1523 /* DBG_VALUE_LIST */
1524 20,
1525 /* DBG_INSTR_REF */
1526 20,
1527 /* DBG_PHI */
1528 20,
1529 /* DBG_LABEL */
1530 20,
1531 /* REG_SEQUENCE */
1532 21,
1533 /* COPY */
1534 23,
1535 /* BUNDLE */
1536 25,
1537 /* LIFETIME_START */
1538 25,
1539 /* LIFETIME_END */
1540 26,
1541 /* PSEUDO_PROBE */
1542 27,
1543 /* ARITH_FENCE */
1544 31,
1545 /* STACKMAP */
1546 33,
1547 /* FENTRY_CALL */
1548 35,
1549 /* PATCHPOINT */
1550 35,
1551 /* LOAD_STACK_GUARD */
1552 41,
1553 /* PREALLOCATED_SETUP */
1554 42,
1555 /* PREALLOCATED_ARG */
1556 43,
1557 /* STATEPOINT */
1558 46,
1559 /* LOCAL_ESCAPE */
1560 46,
1561 /* FAULTING_OP */
1562 48,
1563 /* PATCHABLE_OP */
1564 49,
1565 /* PATCHABLE_FUNCTION_ENTER */
1566 49,
1567 /* PATCHABLE_RET */
1568 49,
1569 /* PATCHABLE_FUNCTION_EXIT */
1570 49,
1571 /* PATCHABLE_TAIL_CALL */
1572 49,
1573 /* PATCHABLE_EVENT_CALL */
1574 49,
1575 /* PATCHABLE_TYPED_EVENT_CALL */
1576 51,
1577 /* ICALL_BRANCH_FUNNEL */
1578 54,
1579 /* MEMBARRIER */
1580 54,
1581 /* JUMP_TABLE_DEBUG_INFO */
1582 54,
1583 /* CONVERGENCECTRL_ENTRY */
1584 55,
1585 /* CONVERGENCECTRL_ANCHOR */
1586 56,
1587 /* CONVERGENCECTRL_LOOP */
1588 57,
1589 /* CONVERGENCECTRL_GLUE */
1590 59,
1591 /* G_ASSERT_SEXT */
1592 60,
1593 /* G_ASSERT_ZEXT */
1594 63,
1595 /* G_ASSERT_ALIGN */
1596 66,
1597 /* G_ADD */
1598 69,
1599 /* G_SUB */
1600 72,
1601 /* G_MUL */
1602 75,
1603 /* G_SDIV */
1604 78,
1605 /* G_UDIV */
1606 81,
1607 /* G_SREM */
1608 84,
1609 /* G_UREM */
1610 87,
1611 /* G_SDIVREM */
1612 90,
1613 /* G_UDIVREM */
1614 94,
1615 /* G_AND */
1616 98,
1617 /* G_OR */
1618 101,
1619 /* G_XOR */
1620 104,
1621 /* G_IMPLICIT_DEF */
1622 107,
1623 /* G_PHI */
1624 108,
1625 /* G_FRAME_INDEX */
1626 109,
1627 /* G_GLOBAL_VALUE */
1628 111,
1629 /* G_PTRAUTH_GLOBAL_VALUE */
1630 113,
1631 /* G_CONSTANT_POOL */
1632 118,
1633 /* G_EXTRACT */
1634 120,
1635 /* G_UNMERGE_VALUES */
1636 123,
1637 /* G_INSERT */
1638 125,
1639 /* G_MERGE_VALUES */
1640 129,
1641 /* G_BUILD_VECTOR */
1642 131,
1643 /* G_BUILD_VECTOR_TRUNC */
1644 133,
1645 /* G_CONCAT_VECTORS */
1646 135,
1647 /* G_PTRTOINT */
1648 137,
1649 /* G_INTTOPTR */
1650 139,
1651 /* G_BITCAST */
1652 141,
1653 /* G_FREEZE */
1654 143,
1655 /* G_CONSTANT_FOLD_BARRIER */
1656 145,
1657 /* G_INTRINSIC_FPTRUNC_ROUND */
1658 147,
1659 /* G_INTRINSIC_TRUNC */
1660 150,
1661 /* G_INTRINSIC_ROUND */
1662 152,
1663 /* G_INTRINSIC_LRINT */
1664 154,
1665 /* G_INTRINSIC_LLRINT */
1666 156,
1667 /* G_INTRINSIC_ROUNDEVEN */
1668 158,
1669 /* G_READCYCLECOUNTER */
1670 160,
1671 /* G_READSTEADYCOUNTER */
1672 161,
1673 /* G_LOAD */
1674 162,
1675 /* G_SEXTLOAD */
1676 164,
1677 /* G_ZEXTLOAD */
1678 166,
1679 /* G_INDEXED_LOAD */
1680 168,
1681 /* G_INDEXED_SEXTLOAD */
1682 173,
1683 /* G_INDEXED_ZEXTLOAD */
1684 178,
1685 /* G_STORE */
1686 183,
1687 /* G_INDEXED_STORE */
1688 185,
1689 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
1690 190,
1691 /* G_ATOMIC_CMPXCHG */
1692 195,
1693 /* G_ATOMICRMW_XCHG */
1694 199,
1695 /* G_ATOMICRMW_ADD */
1696 202,
1697 /* G_ATOMICRMW_SUB */
1698 205,
1699 /* G_ATOMICRMW_AND */
1700 208,
1701 /* G_ATOMICRMW_NAND */
1702 211,
1703 /* G_ATOMICRMW_OR */
1704 214,
1705 /* G_ATOMICRMW_XOR */
1706 217,
1707 /* G_ATOMICRMW_MAX */
1708 220,
1709 /* G_ATOMICRMW_MIN */
1710 223,
1711 /* G_ATOMICRMW_UMAX */
1712 226,
1713 /* G_ATOMICRMW_UMIN */
1714 229,
1715 /* G_ATOMICRMW_FADD */
1716 232,
1717 /* G_ATOMICRMW_FSUB */
1718 235,
1719 /* G_ATOMICRMW_FMAX */
1720 238,
1721 /* G_ATOMICRMW_FMIN */
1722 241,
1723 /* G_ATOMICRMW_UINC_WRAP */
1724 244,
1725 /* G_ATOMICRMW_UDEC_WRAP */
1726 247,
1727 /* G_FENCE */
1728 250,
1729 /* G_PREFETCH */
1730 252,
1731 /* G_BRCOND */
1732 256,
1733 /* G_BRINDIRECT */
1734 258,
1735 /* G_INVOKE_REGION_START */
1736 259,
1737 /* G_INTRINSIC */
1738 259,
1739 /* G_INTRINSIC_W_SIDE_EFFECTS */
1740 260,
1741 /* G_INTRINSIC_CONVERGENT */
1742 261,
1743 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
1744 262,
1745 /* G_ANYEXT */
1746 263,
1747 /* G_TRUNC */
1748 265,
1749 /* G_CONSTANT */
1750 267,
1751 /* G_FCONSTANT */
1752 269,
1753 /* G_VASTART */
1754 271,
1755 /* G_VAARG */
1756 272,
1757 /* G_SEXT */
1758 275,
1759 /* G_SEXT_INREG */
1760 277,
1761 /* G_ZEXT */
1762 280,
1763 /* G_SHL */
1764 282,
1765 /* G_LSHR */
1766 285,
1767 /* G_ASHR */
1768 288,
1769 /* G_FSHL */
1770 291,
1771 /* G_FSHR */
1772 295,
1773 /* G_ROTR */
1774 299,
1775 /* G_ROTL */
1776 302,
1777 /* G_ICMP */
1778 305,
1779 /* G_FCMP */
1780 309,
1781 /* G_SCMP */
1782 313,
1783 /* G_UCMP */
1784 316,
1785 /* G_SELECT */
1786 319,
1787 /* G_UADDO */
1788 323,
1789 /* G_UADDE */
1790 327,
1791 /* G_USUBO */
1792 332,
1793 /* G_USUBE */
1794 336,
1795 /* G_SADDO */
1796 341,
1797 /* G_SADDE */
1798 345,
1799 /* G_SSUBO */
1800 350,
1801 /* G_SSUBE */
1802 354,
1803 /* G_UMULO */
1804 359,
1805 /* G_SMULO */
1806 363,
1807 /* G_UMULH */
1808 367,
1809 /* G_SMULH */
1810 370,
1811 /* G_UADDSAT */
1812 373,
1813 /* G_SADDSAT */
1814 376,
1815 /* G_USUBSAT */
1816 379,
1817 /* G_SSUBSAT */
1818 382,
1819 /* G_USHLSAT */
1820 385,
1821 /* G_SSHLSAT */
1822 388,
1823 /* G_SMULFIX */
1824 391,
1825 /* G_UMULFIX */
1826 395,
1827 /* G_SMULFIXSAT */
1828 399,
1829 /* G_UMULFIXSAT */
1830 403,
1831 /* G_SDIVFIX */
1832 407,
1833 /* G_UDIVFIX */
1834 411,
1835 /* G_SDIVFIXSAT */
1836 415,
1837 /* G_UDIVFIXSAT */
1838 419,
1839 /* G_FADD */
1840 423,
1841 /* G_FSUB */
1842 426,
1843 /* G_FMUL */
1844 429,
1845 /* G_FMA */
1846 432,
1847 /* G_FMAD */
1848 436,
1849 /* G_FDIV */
1850 440,
1851 /* G_FREM */
1852 443,
1853 /* G_FPOW */
1854 446,
1855 /* G_FPOWI */
1856 449,
1857 /* G_FEXP */
1858 452,
1859 /* G_FEXP2 */
1860 454,
1861 /* G_FEXP10 */
1862 456,
1863 /* G_FLOG */
1864 458,
1865 /* G_FLOG2 */
1866 460,
1867 /* G_FLOG10 */
1868 462,
1869 /* G_FLDEXP */
1870 464,
1871 /* G_FFREXP */
1872 467,
1873 /* G_FNEG */
1874 470,
1875 /* G_FPEXT */
1876 472,
1877 /* G_FPTRUNC */
1878 474,
1879 /* G_FPTOSI */
1880 476,
1881 /* G_FPTOUI */
1882 478,
1883 /* G_SITOFP */
1884 480,
1885 /* G_UITOFP */
1886 482,
1887 /* G_FABS */
1888 484,
1889 /* G_FCOPYSIGN */
1890 486,
1891 /* G_IS_FPCLASS */
1892 489,
1893 /* G_FCANONICALIZE */
1894 492,
1895 /* G_FMINNUM */
1896 494,
1897 /* G_FMAXNUM */
1898 497,
1899 /* G_FMINNUM_IEEE */
1900 500,
1901 /* G_FMAXNUM_IEEE */
1902 503,
1903 /* G_FMINIMUM */
1904 506,
1905 /* G_FMAXIMUM */
1906 509,
1907 /* G_GET_FPENV */
1908 512,
1909 /* G_SET_FPENV */
1910 513,
1911 /* G_RESET_FPENV */
1912 514,
1913 /* G_GET_FPMODE */
1914 514,
1915 /* G_SET_FPMODE */
1916 515,
1917 /* G_RESET_FPMODE */
1918 516,
1919 /* G_PTR_ADD */
1920 516,
1921 /* G_PTRMASK */
1922 519,
1923 /* G_SMIN */
1924 522,
1925 /* G_SMAX */
1926 525,
1927 /* G_UMIN */
1928 528,
1929 /* G_UMAX */
1930 531,
1931 /* G_ABS */
1932 534,
1933 /* G_LROUND */
1934 536,
1935 /* G_LLROUND */
1936 538,
1937 /* G_BR */
1938 540,
1939 /* G_BRJT */
1940 541,
1941 /* G_VSCALE */
1942 544,
1943 /* G_INSERT_SUBVECTOR */
1944 546,
1945 /* G_EXTRACT_SUBVECTOR */
1946 550,
1947 /* G_INSERT_VECTOR_ELT */
1948 553,
1949 /* G_EXTRACT_VECTOR_ELT */
1950 557,
1951 /* G_SHUFFLE_VECTOR */
1952 560,
1953 /* G_SPLAT_VECTOR */
1954 564,
1955 /* G_VECTOR_COMPRESS */
1956 566,
1957 /* G_CTTZ */
1958 570,
1959 /* G_CTTZ_ZERO_UNDEF */
1960 572,
1961 /* G_CTLZ */
1962 574,
1963 /* G_CTLZ_ZERO_UNDEF */
1964 576,
1965 /* G_CTPOP */
1966 578,
1967 /* G_BSWAP */
1968 580,
1969 /* G_BITREVERSE */
1970 582,
1971 /* G_FCEIL */
1972 584,
1973 /* G_FCOS */
1974 586,
1975 /* G_FSIN */
1976 588,
1977 /* G_FTAN */
1978 590,
1979 /* G_FACOS */
1980 592,
1981 /* G_FASIN */
1982 594,
1983 /* G_FATAN */
1984 596,
1985 /* G_FCOSH */
1986 598,
1987 /* G_FSINH */
1988 600,
1989 /* G_FTANH */
1990 602,
1991 /* G_FSQRT */
1992 604,
1993 /* G_FFLOOR */
1994 606,
1995 /* G_FRINT */
1996 608,
1997 /* G_FNEARBYINT */
1998 610,
1999 /* G_ADDRSPACE_CAST */
2000 612,
2001 /* G_BLOCK_ADDR */
2002 614,
2003 /* G_JUMP_TABLE */
2004 616,
2005 /* G_DYN_STACKALLOC */
2006 618,
2007 /* G_STACKSAVE */
2008 621,
2009 /* G_STACKRESTORE */
2010 622,
2011 /* G_STRICT_FADD */
2012 623,
2013 /* G_STRICT_FSUB */
2014 626,
2015 /* G_STRICT_FMUL */
2016 629,
2017 /* G_STRICT_FDIV */
2018 632,
2019 /* G_STRICT_FREM */
2020 635,
2021 /* G_STRICT_FMA */
2022 638,
2023 /* G_STRICT_FSQRT */
2024 642,
2025 /* G_STRICT_FLDEXP */
2026 644,
2027 /* G_READ_REGISTER */
2028 647,
2029 /* G_WRITE_REGISTER */
2030 649,
2031 /* G_MEMCPY */
2032 651,
2033 /* G_MEMCPY_INLINE */
2034 655,
2035 /* G_MEMMOVE */
2036 658,
2037 /* G_MEMSET */
2038 662,
2039 /* G_BZERO */
2040 666,
2041 /* G_TRAP */
2042 669,
2043 /* G_DEBUGTRAP */
2044 669,
2045 /* G_UBSANTRAP */
2046 669,
2047 /* G_VECREDUCE_SEQ_FADD */
2048 670,
2049 /* G_VECREDUCE_SEQ_FMUL */
2050 673,
2051 /* G_VECREDUCE_FADD */
2052 676,
2053 /* G_VECREDUCE_FMUL */
2054 678,
2055 /* G_VECREDUCE_FMAX */
2056 680,
2057 /* G_VECREDUCE_FMIN */
2058 682,
2059 /* G_VECREDUCE_FMAXIMUM */
2060 684,
2061 /* G_VECREDUCE_FMINIMUM */
2062 686,
2063 /* G_VECREDUCE_ADD */
2064 688,
2065 /* G_VECREDUCE_MUL */
2066 690,
2067 /* G_VECREDUCE_AND */
2068 692,
2069 /* G_VECREDUCE_OR */
2070 694,
2071 /* G_VECREDUCE_XOR */
2072 696,
2073 /* G_VECREDUCE_SMAX */
2074 698,
2075 /* G_VECREDUCE_SMIN */
2076 700,
2077 /* G_VECREDUCE_UMAX */
2078 702,
2079 /* G_VECREDUCE_UMIN */
2080 704,
2081 /* G_SBFX */
2082 706,
2083 /* G_UBFX */
2084 710,
2085 /* ADJCALLSTACKDOWN */
2086 714,
2087 /* ADJCALLSTACKUP */
2088 716,
2089 /* ADJDYNALLOC */
2090 718,
2091 /* CALL */
2092 720,
2093 /* CALLR */
2094 721,
2095 /* ADDC_F_I_HI */
2096 722,
2097 /* ADDC_F_I_LO */
2098 725,
2099 /* ADDC_F_R */
2100 728,
2101 /* ADDC_I_HI */
2102 732,
2103 /* ADDC_I_LO */
2104 735,
2105 /* ADDC_R */
2106 738,
2107 /* ADD_F_I_HI */
2108 742,
2109 /* ADD_F_I_LO */
2110 745,
2111 /* ADD_F_R */
2112 748,
2113 /* ADD_I_HI */
2114 752,
2115 /* ADD_I_LO */
2116 755,
2117 /* ADD_R */
2118 758,
2119 /* AND_F_I_HI */
2120 762,
2121 /* AND_F_I_LO */
2122 765,
2123 /* AND_F_R */
2124 768,
2125 /* AND_I_HI */
2126 772,
2127 /* AND_I_LO */
2128 775,
2129 /* AND_R */
2130 778,
2131 /* BRCC */
2132 782,
2133 /* BRIND_CC */
2134 784,
2135 /* BRIND_CCA */
2136 786,
2137 /* BRR */
2138 789,
2139 /* BT */
2140 791,
2141 /* JR */
2142 792,
2143 /* LDADDR */
2144 793,
2145 /* LDBs_RI */
2146 795,
2147 /* LDBs_RR */
2148 799,
2149 /* LDBz_RI */
2150 803,
2151 /* LDBz_RR */
2152 807,
2153 /* LDHs_RI */
2154 811,
2155 /* LDHs_RR */
2156 815,
2157 /* LDHz_RI */
2158 819,
2159 /* LDHz_RR */
2160 823,
2161 /* LDW_RI */
2162 827,
2163 /* LDW_RR */
2164 831,
2165 /* LDWz_RR */
2166 835,
2167 /* LEADZ */
2168 839,
2169 /* LOG0 */
2170 841,
2171 /* LOG1 */
2172 841,
2173 /* LOG2 */
2174 841,
2175 /* LOG3 */
2176 841,
2177 /* LOG4 */
2178 841,
2179 /* MOVHI */
2180 841,
2181 /* NOP */
2182 843,
2183 /* OR_F_I_HI */
2184 843,
2185 /* OR_F_I_LO */
2186 846,
2187 /* OR_F_R */
2188 849,
2189 /* OR_I_HI */
2190 853,
2191 /* OR_I_LO */
2192 856,
2193 /* OR_R */
2194 859,
2195 /* POPC */
2196 863,
2197 /* RET */
2198 865,
2199 /* SA_F_I */
2200 865,
2201 /* SA_I */
2202 868,
2203 /* SCC */
2204 871,
2205 /* SELECT */
2206 873,
2207 /* SFSUB_F_RI_HI */
2208 877,
2209 /* SFSUB_F_RI_LO */
2210 879,
2211 /* SFSUB_F_RR */
2212 881,
2213 /* SHL_F_R */
2214 883,
2215 /* SHL_R */
2216 887,
2217 /* SLI */
2218 891,
2219 /* SL_F_I */
2220 893,
2221 /* SL_I */
2222 896,
2223 /* SRA_F_R */
2224 899,
2225 /* SRA_R */
2226 903,
2227 /* SRL_F_R */
2228 907,
2229 /* SRL_R */
2230 911,
2231 /* STADDR */
2232 915,
2233 /* STB_RI */
2234 917,
2235 /* STB_RR */
2236 921,
2237 /* STH_RI */
2238 925,
2239 /* STH_RR */
2240 929,
2241 /* SUBB_F_I_HI */
2242 933,
2243 /* SUBB_F_I_LO */
2244 936,
2245 /* SUBB_F_R */
2246 939,
2247 /* SUBB_I_HI */
2248 943,
2249 /* SUBB_I_LO */
2250 946,
2251 /* SUBB_R */
2252 949,
2253 /* SUB_F_I_HI */
2254 953,
2255 /* SUB_F_I_LO */
2256 956,
2257 /* SUB_F_R */
2258 959,
2259 /* SUB_I_HI */
2260 963,
2261 /* SUB_I_LO */
2262 966,
2263 /* SUB_R */
2264 969,
2265 /* SW_RI */
2266 973,
2267 /* SW_RR */
2268 977,
2269 /* TRAILZ */
2270 981,
2271 /* XOR_F_I_HI */
2272 983,
2273 /* XOR_F_I_LO */
2274 986,
2275 /* XOR_F_R */
2276 989,
2277 /* XOR_I_HI */
2278 993,
2279 /* XOR_I_LO */
2280 996,
2281 /* XOR_R */
2282 999,
2283 };
2284
2285 using namespace OpTypes;
2286 static const int8_t OpcodeOperandTypes[] = {
2287
2288 /* PHI */
2289 -1,
2290 /* INLINEASM */
2291 /* INLINEASM_BR */
2292 /* CFI_INSTRUCTION */
2293 i32imm,
2294 /* EH_LABEL */
2295 i32imm,
2296 /* GC_LABEL */
2297 i32imm,
2298 /* ANNOTATION_LABEL */
2299 i32imm,
2300 /* KILL */
2301 /* EXTRACT_SUBREG */
2302 -1, -1, i32imm,
2303 /* INSERT_SUBREG */
2304 -1, -1, -1, i32imm,
2305 /* IMPLICIT_DEF */
2306 -1,
2307 /* SUBREG_TO_REG */
2308 -1, -1, -1, i32imm,
2309 /* COPY_TO_REGCLASS */
2310 -1, -1, i32imm,
2311 /* DBG_VALUE */
2312 /* DBG_VALUE_LIST */
2313 /* DBG_INSTR_REF */
2314 /* DBG_PHI */
2315 /* DBG_LABEL */
2316 -1,
2317 /* REG_SEQUENCE */
2318 -1, -1,
2319 /* COPY */
2320 -1, -1,
2321 /* BUNDLE */
2322 /* LIFETIME_START */
2323 i32imm,
2324 /* LIFETIME_END */
2325 i32imm,
2326 /* PSEUDO_PROBE */
2327 i64imm, i64imm, i8imm, i32imm,
2328 /* ARITH_FENCE */
2329 -1, -1,
2330 /* STACKMAP */
2331 i64imm, i32imm,
2332 /* FENTRY_CALL */
2333 /* PATCHPOINT */
2334 -1, i64imm, i32imm, -1, i32imm, i32imm,
2335 /* LOAD_STACK_GUARD */
2336 -1,
2337 /* PREALLOCATED_SETUP */
2338 i32imm,
2339 /* PREALLOCATED_ARG */
2340 -1, i32imm, i32imm,
2341 /* STATEPOINT */
2342 /* LOCAL_ESCAPE */
2343 -1, i32imm,
2344 /* FAULTING_OP */
2345 -1,
2346 /* PATCHABLE_OP */
2347 /* PATCHABLE_FUNCTION_ENTER */
2348 /* PATCHABLE_RET */
2349 /* PATCHABLE_FUNCTION_EXIT */
2350 /* PATCHABLE_TAIL_CALL */
2351 /* PATCHABLE_EVENT_CALL */
2352 -1, -1,
2353 /* PATCHABLE_TYPED_EVENT_CALL */
2354 -1, -1, -1,
2355 /* ICALL_BRANCH_FUNNEL */
2356 /* MEMBARRIER */
2357 /* JUMP_TABLE_DEBUG_INFO */
2358 i64imm,
2359 /* CONVERGENCECTRL_ENTRY */
2360 -1,
2361 /* CONVERGENCECTRL_ANCHOR */
2362 -1,
2363 /* CONVERGENCECTRL_LOOP */
2364 -1, -1,
2365 /* CONVERGENCECTRL_GLUE */
2366 -1,
2367 /* G_ASSERT_SEXT */
2368 type0, type0, untyped_imm_0,
2369 /* G_ASSERT_ZEXT */
2370 type0, type0, untyped_imm_0,
2371 /* G_ASSERT_ALIGN */
2372 type0, type0, untyped_imm_0,
2373 /* G_ADD */
2374 type0, type0, type0,
2375 /* G_SUB */
2376 type0, type0, type0,
2377 /* G_MUL */
2378 type0, type0, type0,
2379 /* G_SDIV */
2380 type0, type0, type0,
2381 /* G_UDIV */
2382 type0, type0, type0,
2383 /* G_SREM */
2384 type0, type0, type0,
2385 /* G_UREM */
2386 type0, type0, type0,
2387 /* G_SDIVREM */
2388 type0, type0, type0, type0,
2389 /* G_UDIVREM */
2390 type0, type0, type0, type0,
2391 /* G_AND */
2392 type0, type0, type0,
2393 /* G_OR */
2394 type0, type0, type0,
2395 /* G_XOR */
2396 type0, type0, type0,
2397 /* G_IMPLICIT_DEF */
2398 type0,
2399 /* G_PHI */
2400 type0,
2401 /* G_FRAME_INDEX */
2402 type0, -1,
2403 /* G_GLOBAL_VALUE */
2404 type0, -1,
2405 /* G_PTRAUTH_GLOBAL_VALUE */
2406 type0, -1, i32imm, type1, i64imm,
2407 /* G_CONSTANT_POOL */
2408 type0, -1,
2409 /* G_EXTRACT */
2410 type0, type1, untyped_imm_0,
2411 /* G_UNMERGE_VALUES */
2412 type0, type1,
2413 /* G_INSERT */
2414 type0, type0, type1, untyped_imm_0,
2415 /* G_MERGE_VALUES */
2416 type0, type1,
2417 /* G_BUILD_VECTOR */
2418 type0, type1,
2419 /* G_BUILD_VECTOR_TRUNC */
2420 type0, type1,
2421 /* G_CONCAT_VECTORS */
2422 type0, type1,
2423 /* G_PTRTOINT */
2424 type0, type1,
2425 /* G_INTTOPTR */
2426 type0, type1,
2427 /* G_BITCAST */
2428 type0, type1,
2429 /* G_FREEZE */
2430 type0, type0,
2431 /* G_CONSTANT_FOLD_BARRIER */
2432 type0, type0,
2433 /* G_INTRINSIC_FPTRUNC_ROUND */
2434 type0, type1, i32imm,
2435 /* G_INTRINSIC_TRUNC */
2436 type0, type0,
2437 /* G_INTRINSIC_ROUND */
2438 type0, type0,
2439 /* G_INTRINSIC_LRINT */
2440 type0, type1,
2441 /* G_INTRINSIC_LLRINT */
2442 type0, type1,
2443 /* G_INTRINSIC_ROUNDEVEN */
2444 type0, type0,
2445 /* G_READCYCLECOUNTER */
2446 type0,
2447 /* G_READSTEADYCOUNTER */
2448 type0,
2449 /* G_LOAD */
2450 type0, ptype1,
2451 /* G_SEXTLOAD */
2452 type0, ptype1,
2453 /* G_ZEXTLOAD */
2454 type0, ptype1,
2455 /* G_INDEXED_LOAD */
2456 type0, ptype1, ptype1, type2, -1,
2457 /* G_INDEXED_SEXTLOAD */
2458 type0, ptype1, ptype1, type2, -1,
2459 /* G_INDEXED_ZEXTLOAD */
2460 type0, ptype1, ptype1, type2, -1,
2461 /* G_STORE */
2462 type0, ptype1,
2463 /* G_INDEXED_STORE */
2464 ptype0, type1, ptype0, ptype2, -1,
2465 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
2466 type0, type1, type2, type0, type0,
2467 /* G_ATOMIC_CMPXCHG */
2468 type0, ptype1, type0, type0,
2469 /* G_ATOMICRMW_XCHG */
2470 type0, ptype1, type0,
2471 /* G_ATOMICRMW_ADD */
2472 type0, ptype1, type0,
2473 /* G_ATOMICRMW_SUB */
2474 type0, ptype1, type0,
2475 /* G_ATOMICRMW_AND */
2476 type0, ptype1, type0,
2477 /* G_ATOMICRMW_NAND */
2478 type0, ptype1, type0,
2479 /* G_ATOMICRMW_OR */
2480 type0, ptype1, type0,
2481 /* G_ATOMICRMW_XOR */
2482 type0, ptype1, type0,
2483 /* G_ATOMICRMW_MAX */
2484 type0, ptype1, type0,
2485 /* G_ATOMICRMW_MIN */
2486 type0, ptype1, type0,
2487 /* G_ATOMICRMW_UMAX */
2488 type0, ptype1, type0,
2489 /* G_ATOMICRMW_UMIN */
2490 type0, ptype1, type0,
2491 /* G_ATOMICRMW_FADD */
2492 type0, ptype1, type0,
2493 /* G_ATOMICRMW_FSUB */
2494 type0, ptype1, type0,
2495 /* G_ATOMICRMW_FMAX */
2496 type0, ptype1, type0,
2497 /* G_ATOMICRMW_FMIN */
2498 type0, ptype1, type0,
2499 /* G_ATOMICRMW_UINC_WRAP */
2500 type0, ptype1, type0,
2501 /* G_ATOMICRMW_UDEC_WRAP */
2502 type0, ptype1, type0,
2503 /* G_FENCE */
2504 i32imm, i32imm,
2505 /* G_PREFETCH */
2506 ptype0, i32imm, i32imm, i32imm,
2507 /* G_BRCOND */
2508 type0, -1,
2509 /* G_BRINDIRECT */
2510 type0,
2511 /* G_INVOKE_REGION_START */
2512 /* G_INTRINSIC */
2513 -1,
2514 /* G_INTRINSIC_W_SIDE_EFFECTS */
2515 -1,
2516 /* G_INTRINSIC_CONVERGENT */
2517 -1,
2518 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
2519 -1,
2520 /* G_ANYEXT */
2521 type0, type1,
2522 /* G_TRUNC */
2523 type0, type1,
2524 /* G_CONSTANT */
2525 type0, -1,
2526 /* G_FCONSTANT */
2527 type0, -1,
2528 /* G_VASTART */
2529 type0,
2530 /* G_VAARG */
2531 type0, type1, -1,
2532 /* G_SEXT */
2533 type0, type1,
2534 /* G_SEXT_INREG */
2535 type0, type0, untyped_imm_0,
2536 /* G_ZEXT */
2537 type0, type1,
2538 /* G_SHL */
2539 type0, type0, type1,
2540 /* G_LSHR */
2541 type0, type0, type1,
2542 /* G_ASHR */
2543 type0, type0, type1,
2544 /* G_FSHL */
2545 type0, type0, type0, type1,
2546 /* G_FSHR */
2547 type0, type0, type0, type1,
2548 /* G_ROTR */
2549 type0, type0, type1,
2550 /* G_ROTL */
2551 type0, type0, type1,
2552 /* G_ICMP */
2553 type0, -1, type1, type1,
2554 /* G_FCMP */
2555 type0, -1, type1, type1,
2556 /* G_SCMP */
2557 type0, type1, type1,
2558 /* G_UCMP */
2559 type0, type1, type1,
2560 /* G_SELECT */
2561 type0, type1, type0, type0,
2562 /* G_UADDO */
2563 type0, type1, type0, type0,
2564 /* G_UADDE */
2565 type0, type1, type0, type0, type1,
2566 /* G_USUBO */
2567 type0, type1, type0, type0,
2568 /* G_USUBE */
2569 type0, type1, type0, type0, type1,
2570 /* G_SADDO */
2571 type0, type1, type0, type0,
2572 /* G_SADDE */
2573 type0, type1, type0, type0, type1,
2574 /* G_SSUBO */
2575 type0, type1, type0, type0,
2576 /* G_SSUBE */
2577 type0, type1, type0, type0, type1,
2578 /* G_UMULO */
2579 type0, type1, type0, type0,
2580 /* G_SMULO */
2581 type0, type1, type0, type0,
2582 /* G_UMULH */
2583 type0, type0, type0,
2584 /* G_SMULH */
2585 type0, type0, type0,
2586 /* G_UADDSAT */
2587 type0, type0, type0,
2588 /* G_SADDSAT */
2589 type0, type0, type0,
2590 /* G_USUBSAT */
2591 type0, type0, type0,
2592 /* G_SSUBSAT */
2593 type0, type0, type0,
2594 /* G_USHLSAT */
2595 type0, type0, type1,
2596 /* G_SSHLSAT */
2597 type0, type0, type1,
2598 /* G_SMULFIX */
2599 type0, type0, type0, untyped_imm_0,
2600 /* G_UMULFIX */
2601 type0, type0, type0, untyped_imm_0,
2602 /* G_SMULFIXSAT */
2603 type0, type0, type0, untyped_imm_0,
2604 /* G_UMULFIXSAT */
2605 type0, type0, type0, untyped_imm_0,
2606 /* G_SDIVFIX */
2607 type0, type0, type0, untyped_imm_0,
2608 /* G_UDIVFIX */
2609 type0, type0, type0, untyped_imm_0,
2610 /* G_SDIVFIXSAT */
2611 type0, type0, type0, untyped_imm_0,
2612 /* G_UDIVFIXSAT */
2613 type0, type0, type0, untyped_imm_0,
2614 /* G_FADD */
2615 type0, type0, type0,
2616 /* G_FSUB */
2617 type0, type0, type0,
2618 /* G_FMUL */
2619 type0, type0, type0,
2620 /* G_FMA */
2621 type0, type0, type0, type0,
2622 /* G_FMAD */
2623 type0, type0, type0, type0,
2624 /* G_FDIV */
2625 type0, type0, type0,
2626 /* G_FREM */
2627 type0, type0, type0,
2628 /* G_FPOW */
2629 type0, type0, type0,
2630 /* G_FPOWI */
2631 type0, type0, type1,
2632 /* G_FEXP */
2633 type0, type0,
2634 /* G_FEXP2 */
2635 type0, type0,
2636 /* G_FEXP10 */
2637 type0, type0,
2638 /* G_FLOG */
2639 type0, type0,
2640 /* G_FLOG2 */
2641 type0, type0,
2642 /* G_FLOG10 */
2643 type0, type0,
2644 /* G_FLDEXP */
2645 type0, type0, type1,
2646 /* G_FFREXP */
2647 type0, type1, type0,
2648 /* G_FNEG */
2649 type0, type0,
2650 /* G_FPEXT */
2651 type0, type1,
2652 /* G_FPTRUNC */
2653 type0, type1,
2654 /* G_FPTOSI */
2655 type0, type1,
2656 /* G_FPTOUI */
2657 type0, type1,
2658 /* G_SITOFP */
2659 type0, type1,
2660 /* G_UITOFP */
2661 type0, type1,
2662 /* G_FABS */
2663 type0, type0,
2664 /* G_FCOPYSIGN */
2665 type0, type0, type1,
2666 /* G_IS_FPCLASS */
2667 type0, type1, -1,
2668 /* G_FCANONICALIZE */
2669 type0, type0,
2670 /* G_FMINNUM */
2671 type0, type0, type0,
2672 /* G_FMAXNUM */
2673 type0, type0, type0,
2674 /* G_FMINNUM_IEEE */
2675 type0, type0, type0,
2676 /* G_FMAXNUM_IEEE */
2677 type0, type0, type0,
2678 /* G_FMINIMUM */
2679 type0, type0, type0,
2680 /* G_FMAXIMUM */
2681 type0, type0, type0,
2682 /* G_GET_FPENV */
2683 type0,
2684 /* G_SET_FPENV */
2685 type0,
2686 /* G_RESET_FPENV */
2687 /* G_GET_FPMODE */
2688 type0,
2689 /* G_SET_FPMODE */
2690 type0,
2691 /* G_RESET_FPMODE */
2692 /* G_PTR_ADD */
2693 ptype0, ptype0, type1,
2694 /* G_PTRMASK */
2695 ptype0, ptype0, type1,
2696 /* G_SMIN */
2697 type0, type0, type0,
2698 /* G_SMAX */
2699 type0, type0, type0,
2700 /* G_UMIN */
2701 type0, type0, type0,
2702 /* G_UMAX */
2703 type0, type0, type0,
2704 /* G_ABS */
2705 type0, type0,
2706 /* G_LROUND */
2707 type0, type1,
2708 /* G_LLROUND */
2709 type0, type1,
2710 /* G_BR */
2711 -1,
2712 /* G_BRJT */
2713 ptype0, -1, type1,
2714 /* G_VSCALE */
2715 type0, -1,
2716 /* G_INSERT_SUBVECTOR */
2717 type0, type0, type1, untyped_imm_0,
2718 /* G_EXTRACT_SUBVECTOR */
2719 type0, type0, untyped_imm_0,
2720 /* G_INSERT_VECTOR_ELT */
2721 type0, type0, type1, type2,
2722 /* G_EXTRACT_VECTOR_ELT */
2723 type0, type1, type2,
2724 /* G_SHUFFLE_VECTOR */
2725 type0, type1, type1, -1,
2726 /* G_SPLAT_VECTOR */
2727 type0, type1,
2728 /* G_VECTOR_COMPRESS */
2729 type0, type0, type1, type0,
2730 /* G_CTTZ */
2731 type0, type1,
2732 /* G_CTTZ_ZERO_UNDEF */
2733 type0, type1,
2734 /* G_CTLZ */
2735 type0, type1,
2736 /* G_CTLZ_ZERO_UNDEF */
2737 type0, type1,
2738 /* G_CTPOP */
2739 type0, type1,
2740 /* G_BSWAP */
2741 type0, type0,
2742 /* G_BITREVERSE */
2743 type0, type0,
2744 /* G_FCEIL */
2745 type0, type0,
2746 /* G_FCOS */
2747 type0, type0,
2748 /* G_FSIN */
2749 type0, type0,
2750 /* G_FTAN */
2751 type0, type0,
2752 /* G_FACOS */
2753 type0, type0,
2754 /* G_FASIN */
2755 type0, type0,
2756 /* G_FATAN */
2757 type0, type0,
2758 /* G_FCOSH */
2759 type0, type0,
2760 /* G_FSINH */
2761 type0, type0,
2762 /* G_FTANH */
2763 type0, type0,
2764 /* G_FSQRT */
2765 type0, type0,
2766 /* G_FFLOOR */
2767 type0, type0,
2768 /* G_FRINT */
2769 type0, type0,
2770 /* G_FNEARBYINT */
2771 type0, type0,
2772 /* G_ADDRSPACE_CAST */
2773 type0, type1,
2774 /* G_BLOCK_ADDR */
2775 type0, -1,
2776 /* G_JUMP_TABLE */
2777 type0, -1,
2778 /* G_DYN_STACKALLOC */
2779 ptype0, type1, i32imm,
2780 /* G_STACKSAVE */
2781 ptype0,
2782 /* G_STACKRESTORE */
2783 ptype0,
2784 /* G_STRICT_FADD */
2785 type0, type0, type0,
2786 /* G_STRICT_FSUB */
2787 type0, type0, type0,
2788 /* G_STRICT_FMUL */
2789 type0, type0, type0,
2790 /* G_STRICT_FDIV */
2791 type0, type0, type0,
2792 /* G_STRICT_FREM */
2793 type0, type0, type0,
2794 /* G_STRICT_FMA */
2795 type0, type0, type0, type0,
2796 /* G_STRICT_FSQRT */
2797 type0, type0,
2798 /* G_STRICT_FLDEXP */
2799 type0, type0, type1,
2800 /* G_READ_REGISTER */
2801 type0, -1,
2802 /* G_WRITE_REGISTER */
2803 -1, type0,
2804 /* G_MEMCPY */
2805 ptype0, ptype1, type2, untyped_imm_0,
2806 /* G_MEMCPY_INLINE */
2807 ptype0, ptype1, type2,
2808 /* G_MEMMOVE */
2809 ptype0, ptype1, type2, untyped_imm_0,
2810 /* G_MEMSET */
2811 ptype0, type1, type2, untyped_imm_0,
2812 /* G_BZERO */
2813 ptype0, type1, untyped_imm_0,
2814 /* G_TRAP */
2815 /* G_DEBUGTRAP */
2816 /* G_UBSANTRAP */
2817 i8imm,
2818 /* G_VECREDUCE_SEQ_FADD */
2819 type0, type1, type2,
2820 /* G_VECREDUCE_SEQ_FMUL */
2821 type0, type1, type2,
2822 /* G_VECREDUCE_FADD */
2823 type0, type1,
2824 /* G_VECREDUCE_FMUL */
2825 type0, type1,
2826 /* G_VECREDUCE_FMAX */
2827 type0, type1,
2828 /* G_VECREDUCE_FMIN */
2829 type0, type1,
2830 /* G_VECREDUCE_FMAXIMUM */
2831 type0, type1,
2832 /* G_VECREDUCE_FMINIMUM */
2833 type0, type1,
2834 /* G_VECREDUCE_ADD */
2835 type0, type1,
2836 /* G_VECREDUCE_MUL */
2837 type0, type1,
2838 /* G_VECREDUCE_AND */
2839 type0, type1,
2840 /* G_VECREDUCE_OR */
2841 type0, type1,
2842 /* G_VECREDUCE_XOR */
2843 type0, type1,
2844 /* G_VECREDUCE_SMAX */
2845 type0, type1,
2846 /* G_VECREDUCE_SMIN */
2847 type0, type1,
2848 /* G_VECREDUCE_UMAX */
2849 type0, type1,
2850 /* G_VECREDUCE_UMIN */
2851 type0, type1,
2852 /* G_SBFX */
2853 type0, type0, type1, type1,
2854 /* G_UBFX */
2855 type0, type0, type1, type1,
2856 /* ADJCALLSTACKDOWN */
2857 i32imm, i32imm,
2858 /* ADJCALLSTACKUP */
2859 i32imm, i32imm,
2860 /* ADJDYNALLOC */
2861 GPR, GPR,
2862 /* CALL */
2863 CallTarget,
2864 /* CALLR */
2865 GPR,
2866 /* ADDC_F_I_HI */
2867 GPR, GPR, i32hi16,
2868 /* ADDC_F_I_LO */
2869 GPR, GPR, i32lo16z,
2870 /* ADDC_F_R */
2871 GPR, GPR, GPR, i32imm,
2872 /* ADDC_I_HI */
2873 GPR, GPR, i32hi16,
2874 /* ADDC_I_LO */
2875 GPR, GPR, i32lo16z,
2876 /* ADDC_R */
2877 GPR, GPR, GPR, i32imm,
2878 /* ADD_F_I_HI */
2879 GPR, GPR, i32hi16,
2880 /* ADD_F_I_LO */
2881 GPR, GPR, i32lo16z,
2882 /* ADD_F_R */
2883 GPR, GPR, GPR, i32imm,
2884 /* ADD_I_HI */
2885 GPR, GPR, i32hi16,
2886 /* ADD_I_LO */
2887 GPR, GPR, i32lo16z,
2888 /* ADD_R */
2889 GPR, GPR, GPR, i32imm,
2890 /* AND_F_I_HI */
2891 GPR, GPR, i32hi16and,
2892 /* AND_F_I_LO */
2893 GPR, GPR, i32lo16and,
2894 /* AND_F_R */
2895 GPR, GPR, GPR, i32imm,
2896 /* AND_I_HI */
2897 GPR, GPR, i32hi16and,
2898 /* AND_I_LO */
2899 GPR, GPR, i32lo16and,
2900 /* AND_R */
2901 GPR, GPR, GPR, i32imm,
2902 /* BRCC */
2903 BrTarget, CCOp,
2904 /* BRIND_CC */
2905 GPR, CCOp,
2906 /* BRIND_CCA */
2907 GPR, GPR, CCOp,
2908 /* BRR */
2909 i16imm, CCOp,
2910 /* BT */
2911 BrTarget,
2912 /* JR */
2913 GPR,
2914 /* LDADDR */
2915 GPR, i32lo21,
2916 /* LDBs_RI */
2917 GPR, GPR, imm10, AluOp,
2918 /* LDBs_RR */
2919 GPR, GPR, GPR, AluOp,
2920 /* LDBz_RI */
2921 GPR, GPR, imm10, AluOp,
2922 /* LDBz_RR */
2923 GPR, GPR, GPR, AluOp,
2924 /* LDHs_RI */
2925 GPR, GPR, imm10, AluOp,
2926 /* LDHs_RR */
2927 GPR, GPR, GPR, AluOp,
2928 /* LDHz_RI */
2929 GPR, GPR, imm10, AluOp,
2930 /* LDHz_RR */
2931 GPR, GPR, GPR, AluOp,
2932 /* LDW_RI */
2933 GPR, GPR, i32lo16s, AluOp,
2934 /* LDW_RR */
2935 GPR, GPR, GPR, AluOp,
2936 /* LDWz_RR */
2937 GPR, GPR, GPR, AluOp,
2938 /* LEADZ */
2939 GPR, GPR,
2940 /* LOG0 */
2941 /* LOG1 */
2942 /* LOG2 */
2943 /* LOG3 */
2944 /* LOG4 */
2945 /* MOVHI */
2946 GPR, i32hi16,
2947 /* NOP */
2948 /* OR_F_I_HI */
2949 GPR, GPR, i32hi16,
2950 /* OR_F_I_LO */
2951 GPR, GPR, i32lo16z,
2952 /* OR_F_R */
2953 GPR, GPR, GPR, i32imm,
2954 /* OR_I_HI */
2955 GPR, GPR, i32hi16,
2956 /* OR_I_LO */
2957 GPR, GPR, i32lo16z,
2958 /* OR_R */
2959 GPR, GPR, GPR, i32imm,
2960 /* POPC */
2961 GPR, GPR,
2962 /* RET */
2963 /* SA_F_I */
2964 GPR, GPR, immShift,
2965 /* SA_I */
2966 GPR, GPR, immShift,
2967 /* SCC */
2968 GPR, CCOp,
2969 /* SELECT */
2970 GPR, GPR, GPR, CCOp,
2971 /* SFSUB_F_RI_HI */
2972 GPR, i32hi16,
2973 /* SFSUB_F_RI_LO */
2974 GPR, i32lo16z,
2975 /* SFSUB_F_RR */
2976 GPR, GPR,
2977 /* SHL_F_R */
2978 GPR, GPR, GPR, i32imm,
2979 /* SHL_R */
2980 GPR, GPR, GPR, i32imm,
2981 /* SLI */
2982 GPR, i32lo21,
2983 /* SL_F_I */
2984 GPR, GPR, immShift,
2985 /* SL_I */
2986 GPR, GPR, immShift,
2987 /* SRA_F_R */
2988 GPR, GPR, GPR, i32imm,
2989 /* SRA_R */
2990 GPR, GPR, GPR, i32imm,
2991 /* SRL_F_R */
2992 GPR, GPR, GPR, i32imm,
2993 /* SRL_R */
2994 GPR, GPR, GPR, i32imm,
2995 /* STADDR */
2996 GPR, i32lo21,
2997 /* STB_RI */
2998 GPR, GPR, imm10, AluOp,
2999 /* STB_RR */
3000 GPR, GPR, GPR, AluOp,
3001 /* STH_RI */
3002 GPR, GPR, imm10, AluOp,
3003 /* STH_RR */
3004 GPR, GPR, GPR, AluOp,
3005 /* SUBB_F_I_HI */
3006 GPR, GPR, i32hi16,
3007 /* SUBB_F_I_LO */
3008 GPR, GPR, i32lo16z,
3009 /* SUBB_F_R */
3010 GPR, GPR, GPR, i32imm,
3011 /* SUBB_I_HI */
3012 GPR, GPR, i32hi16,
3013 /* SUBB_I_LO */
3014 GPR, GPR, i32lo16z,
3015 /* SUBB_R */
3016 GPR, GPR, GPR, i32imm,
3017 /* SUB_F_I_HI */
3018 GPR, GPR, i32hi16,
3019 /* SUB_F_I_LO */
3020 GPR, GPR, i32lo16z,
3021 /* SUB_F_R */
3022 GPR, GPR, GPR, i32imm,
3023 /* SUB_I_HI */
3024 GPR, GPR, i32hi16,
3025 /* SUB_I_LO */
3026 GPR, GPR, i32lo16z,
3027 /* SUB_R */
3028 GPR, GPR, GPR, i32imm,
3029 /* SW_RI */
3030 GPR, GPR, i32lo16s, AluOp,
3031 /* SW_RR */
3032 GPR, GPR, GPR, AluOp,
3033 /* TRAILZ */
3034 GPR, GPR,
3035 /* XOR_F_I_HI */
3036 GPR, GPR, i32hi16,
3037 /* XOR_F_I_LO */
3038 GPR, GPR, i32lo16z,
3039 /* XOR_F_R */
3040 GPR, GPR, GPR, i32imm,
3041 /* XOR_I_HI */
3042 GPR, GPR, i32hi16,
3043 /* XOR_I_LO */
3044 GPR, GPR, i32lo16z,
3045 /* XOR_R */
3046 GPR, GPR, GPR, i32imm,
3047 };
3048 return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
3049}
3050} // end namespace Lanai
3051} // end namespace llvm
3052#endif // GET_INSTRINFO_OPERAND_TYPE
3053
3054#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
3055#undef GET_INSTRINFO_MEM_OPERAND_SIZE
3056namespace llvm {
3057namespace Lanai {
3058LLVM_READONLY
3059static int getMemOperandSize(int OpType) {
3060 switch (OpType) {
3061 default: return 0;
3062 }
3063}
3064} // end namespace Lanai
3065} // end namespace llvm
3066#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
3067
3068#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3069#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3070namespace llvm {
3071namespace Lanai {
3072LLVM_READONLY static unsigned
3073getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
3074 return LogicalOpIdx;
3075}
3076LLVM_READONLY static inline unsigned
3077getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
3078 auto S = 0U;
3079 for (auto i = 0U; i < LogicalOpIdx; ++i)
3080 S += getLogicalOperandSize(Opcode, i);
3081 return S;
3082}
3083} // end namespace Lanai
3084} // end namespace llvm
3085#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3086
3087#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3088#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3089namespace llvm {
3090namespace Lanai {
3091LLVM_READONLY static int
3092getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
3093 return -1;
3094}
3095} // end namespace Lanai
3096} // end namespace llvm
3097#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3098
3099#ifdef GET_INSTRINFO_MC_HELPER_DECLS
3100#undef GET_INSTRINFO_MC_HELPER_DECLS
3101
3102namespace llvm {
3103class MCInst;
3104class FeatureBitset;
3105
3106namespace Lanai_MC {
3107
3108void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
3109
3110} // end namespace Lanai_MC
3111} // end namespace llvm
3112
3113#endif // GET_INSTRINFO_MC_HELPER_DECLS
3114
3115#ifdef GET_INSTRINFO_MC_HELPERS
3116#undef GET_INSTRINFO_MC_HELPERS
3117
3118namespace llvm {
3119namespace Lanai_MC {
3120
3121} // end namespace Lanai_MC
3122} // end namespace llvm
3123
3124#endif // GET_GENISTRINFO_MC_HELPERS
3125
3126#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
3127 defined(GET_AVAILABLE_OPCODE_CHECKER)
3128#define GET_COMPUTE_FEATURES
3129#endif
3130#ifdef GET_COMPUTE_FEATURES
3131#undef GET_COMPUTE_FEATURES
3132namespace llvm {
3133namespace Lanai_MC {
3134
3135// Bits for subtarget features that participate in instruction matching.
3136enum SubtargetFeatureBits : uint8_t {
3137};
3138
3139inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
3140 FeatureBitset Features;
3141 return Features;
3142}
3143
3144inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
3145 enum : uint8_t {
3146 CEFBS_None,
3147 };
3148
3149 static constexpr FeatureBitset FeatureBitsets[] = {
3150 {}, // CEFBS_None
3151 };
3152 static constexpr uint8_t RequiredFeaturesRefs[] = {
3153 CEFBS_None, // PHI = 0
3154 CEFBS_None, // INLINEASM = 1
3155 CEFBS_None, // INLINEASM_BR = 2
3156 CEFBS_None, // CFI_INSTRUCTION = 3
3157 CEFBS_None, // EH_LABEL = 4
3158 CEFBS_None, // GC_LABEL = 5
3159 CEFBS_None, // ANNOTATION_LABEL = 6
3160 CEFBS_None, // KILL = 7
3161 CEFBS_None, // EXTRACT_SUBREG = 8
3162 CEFBS_None, // INSERT_SUBREG = 9
3163 CEFBS_None, // IMPLICIT_DEF = 10
3164 CEFBS_None, // SUBREG_TO_REG = 11
3165 CEFBS_None, // COPY_TO_REGCLASS = 12
3166 CEFBS_None, // DBG_VALUE = 13
3167 CEFBS_None, // DBG_VALUE_LIST = 14
3168 CEFBS_None, // DBG_INSTR_REF = 15
3169 CEFBS_None, // DBG_PHI = 16
3170 CEFBS_None, // DBG_LABEL = 17
3171 CEFBS_None, // REG_SEQUENCE = 18
3172 CEFBS_None, // COPY = 19
3173 CEFBS_None, // BUNDLE = 20
3174 CEFBS_None, // LIFETIME_START = 21
3175 CEFBS_None, // LIFETIME_END = 22
3176 CEFBS_None, // PSEUDO_PROBE = 23
3177 CEFBS_None, // ARITH_FENCE = 24
3178 CEFBS_None, // STACKMAP = 25
3179 CEFBS_None, // FENTRY_CALL = 26
3180 CEFBS_None, // PATCHPOINT = 27
3181 CEFBS_None, // LOAD_STACK_GUARD = 28
3182 CEFBS_None, // PREALLOCATED_SETUP = 29
3183 CEFBS_None, // PREALLOCATED_ARG = 30
3184 CEFBS_None, // STATEPOINT = 31
3185 CEFBS_None, // LOCAL_ESCAPE = 32
3186 CEFBS_None, // FAULTING_OP = 33
3187 CEFBS_None, // PATCHABLE_OP = 34
3188 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
3189 CEFBS_None, // PATCHABLE_RET = 36
3190 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
3191 CEFBS_None, // PATCHABLE_TAIL_CALL = 38
3192 CEFBS_None, // PATCHABLE_EVENT_CALL = 39
3193 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
3194 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
3195 CEFBS_None, // MEMBARRIER = 42
3196 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
3197 CEFBS_None, // CONVERGENCECTRL_ENTRY = 44
3198 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 45
3199 CEFBS_None, // CONVERGENCECTRL_LOOP = 46
3200 CEFBS_None, // CONVERGENCECTRL_GLUE = 47
3201 CEFBS_None, // G_ASSERT_SEXT = 48
3202 CEFBS_None, // G_ASSERT_ZEXT = 49
3203 CEFBS_None, // G_ASSERT_ALIGN = 50
3204 CEFBS_None, // G_ADD = 51
3205 CEFBS_None, // G_SUB = 52
3206 CEFBS_None, // G_MUL = 53
3207 CEFBS_None, // G_SDIV = 54
3208 CEFBS_None, // G_UDIV = 55
3209 CEFBS_None, // G_SREM = 56
3210 CEFBS_None, // G_UREM = 57
3211 CEFBS_None, // G_SDIVREM = 58
3212 CEFBS_None, // G_UDIVREM = 59
3213 CEFBS_None, // G_AND = 60
3214 CEFBS_None, // G_OR = 61
3215 CEFBS_None, // G_XOR = 62
3216 CEFBS_None, // G_IMPLICIT_DEF = 63
3217 CEFBS_None, // G_PHI = 64
3218 CEFBS_None, // G_FRAME_INDEX = 65
3219 CEFBS_None, // G_GLOBAL_VALUE = 66
3220 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 67
3221 CEFBS_None, // G_CONSTANT_POOL = 68
3222 CEFBS_None, // G_EXTRACT = 69
3223 CEFBS_None, // G_UNMERGE_VALUES = 70
3224 CEFBS_None, // G_INSERT = 71
3225 CEFBS_None, // G_MERGE_VALUES = 72
3226 CEFBS_None, // G_BUILD_VECTOR = 73
3227 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 74
3228 CEFBS_None, // G_CONCAT_VECTORS = 75
3229 CEFBS_None, // G_PTRTOINT = 76
3230 CEFBS_None, // G_INTTOPTR = 77
3231 CEFBS_None, // G_BITCAST = 78
3232 CEFBS_None, // G_FREEZE = 79
3233 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 80
3234 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 81
3235 CEFBS_None, // G_INTRINSIC_TRUNC = 82
3236 CEFBS_None, // G_INTRINSIC_ROUND = 83
3237 CEFBS_None, // G_INTRINSIC_LRINT = 84
3238 CEFBS_None, // G_INTRINSIC_LLRINT = 85
3239 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 86
3240 CEFBS_None, // G_READCYCLECOUNTER = 87
3241 CEFBS_None, // G_READSTEADYCOUNTER = 88
3242 CEFBS_None, // G_LOAD = 89
3243 CEFBS_None, // G_SEXTLOAD = 90
3244 CEFBS_None, // G_ZEXTLOAD = 91
3245 CEFBS_None, // G_INDEXED_LOAD = 92
3246 CEFBS_None, // G_INDEXED_SEXTLOAD = 93
3247 CEFBS_None, // G_INDEXED_ZEXTLOAD = 94
3248 CEFBS_None, // G_STORE = 95
3249 CEFBS_None, // G_INDEXED_STORE = 96
3250 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97
3251 CEFBS_None, // G_ATOMIC_CMPXCHG = 98
3252 CEFBS_None, // G_ATOMICRMW_XCHG = 99
3253 CEFBS_None, // G_ATOMICRMW_ADD = 100
3254 CEFBS_None, // G_ATOMICRMW_SUB = 101
3255 CEFBS_None, // G_ATOMICRMW_AND = 102
3256 CEFBS_None, // G_ATOMICRMW_NAND = 103
3257 CEFBS_None, // G_ATOMICRMW_OR = 104
3258 CEFBS_None, // G_ATOMICRMW_XOR = 105
3259 CEFBS_None, // G_ATOMICRMW_MAX = 106
3260 CEFBS_None, // G_ATOMICRMW_MIN = 107
3261 CEFBS_None, // G_ATOMICRMW_UMAX = 108
3262 CEFBS_None, // G_ATOMICRMW_UMIN = 109
3263 CEFBS_None, // G_ATOMICRMW_FADD = 110
3264 CEFBS_None, // G_ATOMICRMW_FSUB = 111
3265 CEFBS_None, // G_ATOMICRMW_FMAX = 112
3266 CEFBS_None, // G_ATOMICRMW_FMIN = 113
3267 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 114
3268 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 115
3269 CEFBS_None, // G_FENCE = 116
3270 CEFBS_None, // G_PREFETCH = 117
3271 CEFBS_None, // G_BRCOND = 118
3272 CEFBS_None, // G_BRINDIRECT = 119
3273 CEFBS_None, // G_INVOKE_REGION_START = 120
3274 CEFBS_None, // G_INTRINSIC = 121
3275 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 122
3276 CEFBS_None, // G_INTRINSIC_CONVERGENT = 123
3277 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124
3278 CEFBS_None, // G_ANYEXT = 125
3279 CEFBS_None, // G_TRUNC = 126
3280 CEFBS_None, // G_CONSTANT = 127
3281 CEFBS_None, // G_FCONSTANT = 128
3282 CEFBS_None, // G_VASTART = 129
3283 CEFBS_None, // G_VAARG = 130
3284 CEFBS_None, // G_SEXT = 131
3285 CEFBS_None, // G_SEXT_INREG = 132
3286 CEFBS_None, // G_ZEXT = 133
3287 CEFBS_None, // G_SHL = 134
3288 CEFBS_None, // G_LSHR = 135
3289 CEFBS_None, // G_ASHR = 136
3290 CEFBS_None, // G_FSHL = 137
3291 CEFBS_None, // G_FSHR = 138
3292 CEFBS_None, // G_ROTR = 139
3293 CEFBS_None, // G_ROTL = 140
3294 CEFBS_None, // G_ICMP = 141
3295 CEFBS_None, // G_FCMP = 142
3296 CEFBS_None, // G_SCMP = 143
3297 CEFBS_None, // G_UCMP = 144
3298 CEFBS_None, // G_SELECT = 145
3299 CEFBS_None, // G_UADDO = 146
3300 CEFBS_None, // G_UADDE = 147
3301 CEFBS_None, // G_USUBO = 148
3302 CEFBS_None, // G_USUBE = 149
3303 CEFBS_None, // G_SADDO = 150
3304 CEFBS_None, // G_SADDE = 151
3305 CEFBS_None, // G_SSUBO = 152
3306 CEFBS_None, // G_SSUBE = 153
3307 CEFBS_None, // G_UMULO = 154
3308 CEFBS_None, // G_SMULO = 155
3309 CEFBS_None, // G_UMULH = 156
3310 CEFBS_None, // G_SMULH = 157
3311 CEFBS_None, // G_UADDSAT = 158
3312 CEFBS_None, // G_SADDSAT = 159
3313 CEFBS_None, // G_USUBSAT = 160
3314 CEFBS_None, // G_SSUBSAT = 161
3315 CEFBS_None, // G_USHLSAT = 162
3316 CEFBS_None, // G_SSHLSAT = 163
3317 CEFBS_None, // G_SMULFIX = 164
3318 CEFBS_None, // G_UMULFIX = 165
3319 CEFBS_None, // G_SMULFIXSAT = 166
3320 CEFBS_None, // G_UMULFIXSAT = 167
3321 CEFBS_None, // G_SDIVFIX = 168
3322 CEFBS_None, // G_UDIVFIX = 169
3323 CEFBS_None, // G_SDIVFIXSAT = 170
3324 CEFBS_None, // G_UDIVFIXSAT = 171
3325 CEFBS_None, // G_FADD = 172
3326 CEFBS_None, // G_FSUB = 173
3327 CEFBS_None, // G_FMUL = 174
3328 CEFBS_None, // G_FMA = 175
3329 CEFBS_None, // G_FMAD = 176
3330 CEFBS_None, // G_FDIV = 177
3331 CEFBS_None, // G_FREM = 178
3332 CEFBS_None, // G_FPOW = 179
3333 CEFBS_None, // G_FPOWI = 180
3334 CEFBS_None, // G_FEXP = 181
3335 CEFBS_None, // G_FEXP2 = 182
3336 CEFBS_None, // G_FEXP10 = 183
3337 CEFBS_None, // G_FLOG = 184
3338 CEFBS_None, // G_FLOG2 = 185
3339 CEFBS_None, // G_FLOG10 = 186
3340 CEFBS_None, // G_FLDEXP = 187
3341 CEFBS_None, // G_FFREXP = 188
3342 CEFBS_None, // G_FNEG = 189
3343 CEFBS_None, // G_FPEXT = 190
3344 CEFBS_None, // G_FPTRUNC = 191
3345 CEFBS_None, // G_FPTOSI = 192
3346 CEFBS_None, // G_FPTOUI = 193
3347 CEFBS_None, // G_SITOFP = 194
3348 CEFBS_None, // G_UITOFP = 195
3349 CEFBS_None, // G_FABS = 196
3350 CEFBS_None, // G_FCOPYSIGN = 197
3351 CEFBS_None, // G_IS_FPCLASS = 198
3352 CEFBS_None, // G_FCANONICALIZE = 199
3353 CEFBS_None, // G_FMINNUM = 200
3354 CEFBS_None, // G_FMAXNUM = 201
3355 CEFBS_None, // G_FMINNUM_IEEE = 202
3356 CEFBS_None, // G_FMAXNUM_IEEE = 203
3357 CEFBS_None, // G_FMINIMUM = 204
3358 CEFBS_None, // G_FMAXIMUM = 205
3359 CEFBS_None, // G_GET_FPENV = 206
3360 CEFBS_None, // G_SET_FPENV = 207
3361 CEFBS_None, // G_RESET_FPENV = 208
3362 CEFBS_None, // G_GET_FPMODE = 209
3363 CEFBS_None, // G_SET_FPMODE = 210
3364 CEFBS_None, // G_RESET_FPMODE = 211
3365 CEFBS_None, // G_PTR_ADD = 212
3366 CEFBS_None, // G_PTRMASK = 213
3367 CEFBS_None, // G_SMIN = 214
3368 CEFBS_None, // G_SMAX = 215
3369 CEFBS_None, // G_UMIN = 216
3370 CEFBS_None, // G_UMAX = 217
3371 CEFBS_None, // G_ABS = 218
3372 CEFBS_None, // G_LROUND = 219
3373 CEFBS_None, // G_LLROUND = 220
3374 CEFBS_None, // G_BR = 221
3375 CEFBS_None, // G_BRJT = 222
3376 CEFBS_None, // G_VSCALE = 223
3377 CEFBS_None, // G_INSERT_SUBVECTOR = 224
3378 CEFBS_None, // G_EXTRACT_SUBVECTOR = 225
3379 CEFBS_None, // G_INSERT_VECTOR_ELT = 226
3380 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 227
3381 CEFBS_None, // G_SHUFFLE_VECTOR = 228
3382 CEFBS_None, // G_SPLAT_VECTOR = 229
3383 CEFBS_None, // G_VECTOR_COMPRESS = 230
3384 CEFBS_None, // G_CTTZ = 231
3385 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 232
3386 CEFBS_None, // G_CTLZ = 233
3387 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 234
3388 CEFBS_None, // G_CTPOP = 235
3389 CEFBS_None, // G_BSWAP = 236
3390 CEFBS_None, // G_BITREVERSE = 237
3391 CEFBS_None, // G_FCEIL = 238
3392 CEFBS_None, // G_FCOS = 239
3393 CEFBS_None, // G_FSIN = 240
3394 CEFBS_None, // G_FTAN = 241
3395 CEFBS_None, // G_FACOS = 242
3396 CEFBS_None, // G_FASIN = 243
3397 CEFBS_None, // G_FATAN = 244
3398 CEFBS_None, // G_FCOSH = 245
3399 CEFBS_None, // G_FSINH = 246
3400 CEFBS_None, // G_FTANH = 247
3401 CEFBS_None, // G_FSQRT = 248
3402 CEFBS_None, // G_FFLOOR = 249
3403 CEFBS_None, // G_FRINT = 250
3404 CEFBS_None, // G_FNEARBYINT = 251
3405 CEFBS_None, // G_ADDRSPACE_CAST = 252
3406 CEFBS_None, // G_BLOCK_ADDR = 253
3407 CEFBS_None, // G_JUMP_TABLE = 254
3408 CEFBS_None, // G_DYN_STACKALLOC = 255
3409 CEFBS_None, // G_STACKSAVE = 256
3410 CEFBS_None, // G_STACKRESTORE = 257
3411 CEFBS_None, // G_STRICT_FADD = 258
3412 CEFBS_None, // G_STRICT_FSUB = 259
3413 CEFBS_None, // G_STRICT_FMUL = 260
3414 CEFBS_None, // G_STRICT_FDIV = 261
3415 CEFBS_None, // G_STRICT_FREM = 262
3416 CEFBS_None, // G_STRICT_FMA = 263
3417 CEFBS_None, // G_STRICT_FSQRT = 264
3418 CEFBS_None, // G_STRICT_FLDEXP = 265
3419 CEFBS_None, // G_READ_REGISTER = 266
3420 CEFBS_None, // G_WRITE_REGISTER = 267
3421 CEFBS_None, // G_MEMCPY = 268
3422 CEFBS_None, // G_MEMCPY_INLINE = 269
3423 CEFBS_None, // G_MEMMOVE = 270
3424 CEFBS_None, // G_MEMSET = 271
3425 CEFBS_None, // G_BZERO = 272
3426 CEFBS_None, // G_TRAP = 273
3427 CEFBS_None, // G_DEBUGTRAP = 274
3428 CEFBS_None, // G_UBSANTRAP = 275
3429 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 276
3430 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 277
3431 CEFBS_None, // G_VECREDUCE_FADD = 278
3432 CEFBS_None, // G_VECREDUCE_FMUL = 279
3433 CEFBS_None, // G_VECREDUCE_FMAX = 280
3434 CEFBS_None, // G_VECREDUCE_FMIN = 281
3435 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 282
3436 CEFBS_None, // G_VECREDUCE_FMINIMUM = 283
3437 CEFBS_None, // G_VECREDUCE_ADD = 284
3438 CEFBS_None, // G_VECREDUCE_MUL = 285
3439 CEFBS_None, // G_VECREDUCE_AND = 286
3440 CEFBS_None, // G_VECREDUCE_OR = 287
3441 CEFBS_None, // G_VECREDUCE_XOR = 288
3442 CEFBS_None, // G_VECREDUCE_SMAX = 289
3443 CEFBS_None, // G_VECREDUCE_SMIN = 290
3444 CEFBS_None, // G_VECREDUCE_UMAX = 291
3445 CEFBS_None, // G_VECREDUCE_UMIN = 292
3446 CEFBS_None, // G_SBFX = 293
3447 CEFBS_None, // G_UBFX = 294
3448 CEFBS_None, // ADJCALLSTACKDOWN = 295
3449 CEFBS_None, // ADJCALLSTACKUP = 296
3450 CEFBS_None, // ADJDYNALLOC = 297
3451 CEFBS_None, // CALL = 298
3452 CEFBS_None, // CALLR = 299
3453 CEFBS_None, // ADDC_F_I_HI = 300
3454 CEFBS_None, // ADDC_F_I_LO = 301
3455 CEFBS_None, // ADDC_F_R = 302
3456 CEFBS_None, // ADDC_I_HI = 303
3457 CEFBS_None, // ADDC_I_LO = 304
3458 CEFBS_None, // ADDC_R = 305
3459 CEFBS_None, // ADD_F_I_HI = 306
3460 CEFBS_None, // ADD_F_I_LO = 307
3461 CEFBS_None, // ADD_F_R = 308
3462 CEFBS_None, // ADD_I_HI = 309
3463 CEFBS_None, // ADD_I_LO = 310
3464 CEFBS_None, // ADD_R = 311
3465 CEFBS_None, // AND_F_I_HI = 312
3466 CEFBS_None, // AND_F_I_LO = 313
3467 CEFBS_None, // AND_F_R = 314
3468 CEFBS_None, // AND_I_HI = 315
3469 CEFBS_None, // AND_I_LO = 316
3470 CEFBS_None, // AND_R = 317
3471 CEFBS_None, // BRCC = 318
3472 CEFBS_None, // BRIND_CC = 319
3473 CEFBS_None, // BRIND_CCA = 320
3474 CEFBS_None, // BRR = 321
3475 CEFBS_None, // BT = 322
3476 CEFBS_None, // JR = 323
3477 CEFBS_None, // LDADDR = 324
3478 CEFBS_None, // LDBs_RI = 325
3479 CEFBS_None, // LDBs_RR = 326
3480 CEFBS_None, // LDBz_RI = 327
3481 CEFBS_None, // LDBz_RR = 328
3482 CEFBS_None, // LDHs_RI = 329
3483 CEFBS_None, // LDHs_RR = 330
3484 CEFBS_None, // LDHz_RI = 331
3485 CEFBS_None, // LDHz_RR = 332
3486 CEFBS_None, // LDW_RI = 333
3487 CEFBS_None, // LDW_RR = 334
3488 CEFBS_None, // LDWz_RR = 335
3489 CEFBS_None, // LEADZ = 336
3490 CEFBS_None, // LOG0 = 337
3491 CEFBS_None, // LOG1 = 338
3492 CEFBS_None, // LOG2 = 339
3493 CEFBS_None, // LOG3 = 340
3494 CEFBS_None, // LOG4 = 341
3495 CEFBS_None, // MOVHI = 342
3496 CEFBS_None, // NOP = 343
3497 CEFBS_None, // OR_F_I_HI = 344
3498 CEFBS_None, // OR_F_I_LO = 345
3499 CEFBS_None, // OR_F_R = 346
3500 CEFBS_None, // OR_I_HI = 347
3501 CEFBS_None, // OR_I_LO = 348
3502 CEFBS_None, // OR_R = 349
3503 CEFBS_None, // POPC = 350
3504 CEFBS_None, // RET = 351
3505 CEFBS_None, // SA_F_I = 352
3506 CEFBS_None, // SA_I = 353
3507 CEFBS_None, // SCC = 354
3508 CEFBS_None, // SELECT = 355
3509 CEFBS_None, // SFSUB_F_RI_HI = 356
3510 CEFBS_None, // SFSUB_F_RI_LO = 357
3511 CEFBS_None, // SFSUB_F_RR = 358
3512 CEFBS_None, // SHL_F_R = 359
3513 CEFBS_None, // SHL_R = 360
3514 CEFBS_None, // SLI = 361
3515 CEFBS_None, // SL_F_I = 362
3516 CEFBS_None, // SL_I = 363
3517 CEFBS_None, // SRA_F_R = 364
3518 CEFBS_None, // SRA_R = 365
3519 CEFBS_None, // SRL_F_R = 366
3520 CEFBS_None, // SRL_R = 367
3521 CEFBS_None, // STADDR = 368
3522 CEFBS_None, // STB_RI = 369
3523 CEFBS_None, // STB_RR = 370
3524 CEFBS_None, // STH_RI = 371
3525 CEFBS_None, // STH_RR = 372
3526 CEFBS_None, // SUBB_F_I_HI = 373
3527 CEFBS_None, // SUBB_F_I_LO = 374
3528 CEFBS_None, // SUBB_F_R = 375
3529 CEFBS_None, // SUBB_I_HI = 376
3530 CEFBS_None, // SUBB_I_LO = 377
3531 CEFBS_None, // SUBB_R = 378
3532 CEFBS_None, // SUB_F_I_HI = 379
3533 CEFBS_None, // SUB_F_I_LO = 380
3534 CEFBS_None, // SUB_F_R = 381
3535 CEFBS_None, // SUB_I_HI = 382
3536 CEFBS_None, // SUB_I_LO = 383
3537 CEFBS_None, // SUB_R = 384
3538 CEFBS_None, // SW_RI = 385
3539 CEFBS_None, // SW_RR = 386
3540 CEFBS_None, // TRAILZ = 387
3541 CEFBS_None, // XOR_F_I_HI = 388
3542 CEFBS_None, // XOR_F_I_LO = 389
3543 CEFBS_None, // XOR_F_R = 390
3544 CEFBS_None, // XOR_I_HI = 391
3545 CEFBS_None, // XOR_I_LO = 392
3546 CEFBS_None, // XOR_R = 393
3547 };
3548
3549 assert(Opcode < 394);
3550 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3551}
3552
3553} // end namespace Lanai_MC
3554} // end namespace llvm
3555#endif // GET_COMPUTE_FEATURES
3556
3557#ifdef GET_AVAILABLE_OPCODE_CHECKER
3558#undef GET_AVAILABLE_OPCODE_CHECKER
3559namespace llvm {
3560namespace Lanai_MC {
3561bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3562 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3563 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3564 FeatureBitset MissingFeatures =
3565 (AvailableFeatures & RequiredFeatures) ^
3566 RequiredFeatures;
3567 return !MissingFeatures.any();
3568}
3569} // end namespace Lanai_MC
3570} // end namespace llvm
3571#endif // GET_AVAILABLE_OPCODE_CHECKER
3572
3573#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3574#undef ENABLE_INSTR_PREDICATE_VERIFIER
3575#include <sstream>
3576
3577namespace llvm {
3578namespace Lanai_MC {
3579
3580#ifndef NDEBUG
3581static const char *SubtargetFeatureNames[] = {
3582 nullptr
3583};
3584
3585#endif // NDEBUG
3586
3587void verifyInstructionPredicates(
3588 unsigned Opcode, const FeatureBitset &Features) {
3589#ifndef NDEBUG
3590 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3591 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3592 FeatureBitset MissingFeatures =
3593 (AvailableFeatures & RequiredFeatures) ^
3594 RequiredFeatures;
3595 if (MissingFeatures.any()) {
3596 std::ostringstream Msg;
3597 Msg << "Attempting to emit " << &LanaiInstrNameData[LanaiInstrNameIndices[Opcode]]
3598 << " instruction but the ";
3599 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3600 if (MissingFeatures.test(i))
3601 Msg << SubtargetFeatureNames[i] << " ";
3602 Msg << "predicate(s) are not met";
3603 report_fatal_error(Msg.str().c_str());
3604 }
3605#endif // NDEBUG
3606}
3607} // end namespace Lanai_MC
3608} // end namespace llvm
3609#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3610
3611#ifdef GET_INSTRMAP_INFO
3612#undef GET_INSTRMAP_INFO
3613namespace llvm {
3614
3615namespace Lanai {
3616
3617enum PostEncoderMethod {
3618 PostEncoderMethod_adjustPqBitsSpls
3619};
3620
3621// splsIdempotent
3622LLVM_READONLY
3623int splsIdempotent(uint16_t Opcode) {
3624static const uint16_t splsIdempotentTable[][2] = {
3625 { Lanai::LDBs_RI, Lanai::LDBs_RI },
3626 { Lanai::LDBz_RI, Lanai::LDBz_RI },
3627 { Lanai::LDHs_RI, Lanai::LDHs_RI },
3628 { Lanai::LDHz_RI, Lanai::LDHz_RI },
3629 { Lanai::STB_RI, Lanai::STB_RI },
3630 { Lanai::STH_RI, Lanai::STH_RI },
3631}; // End of splsIdempotentTable
3632
3633 unsigned mid;
3634 unsigned start = 0;
3635 unsigned end = 6;
3636 while (start < end) {
3637 mid = start + (end - start) / 2;
3638 if (Opcode == splsIdempotentTable[mid][0]) {
3639 break;
3640 }
3641 if (Opcode < splsIdempotentTable[mid][0])
3642 end = mid;
3643 else
3644 start = mid + 1;
3645 }
3646 if (start == end)
3647 return -1; // Instruction doesn't exist in this table.
3648
3649 return splsIdempotentTable[mid][1];
3650}
3651
3652} // end namespace Lanai
3653} // end namespace llvm
3654#endif // GET_INSTRMAP_INFO
3655
3656