1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass LanaiMCRegisterClasses[];
17
18namespace Lanai {
19enum {
20 NoRegister,
21 FP = 1,
22 PC = 2,
23 RCA = 3,
24 RV = 4,
25 SP = 5,
26 SR = 6,
27 R0 = 7,
28 R1 = 8,
29 R2 = 9,
30 R3 = 10,
31 R4 = 11,
32 R5 = 12,
33 R6 = 13,
34 R7 = 14,
35 R8 = 15,
36 R9 = 16,
37 R10 = 17,
38 R11 = 18,
39 R12 = 19,
40 R13 = 20,
41 R14 = 21,
42 R15 = 22,
43 R16 = 23,
44 R17 = 24,
45 R18 = 25,
46 R19 = 26,
47 R20 = 27,
48 R21 = 28,
49 R22 = 29,
50 R23 = 30,
51 R24 = 31,
52 R25 = 32,
53 R26 = 33,
54 R27 = 34,
55 R28 = 35,
56 R29 = 36,
57 R30 = 37,
58 R31 = 38,
59 RR1 = 39,
60 RR2 = 40,
61 NUM_TARGET_REGS // 41
62};
63} // end namespace Lanai
64
65// Register classes
66
67namespace Lanai {
68enum {
69 GPRRegClassID = 0,
70 GPR_with_sub_32RegClassID = 1,
71 CCRRegClassID = 2,
72
73};
74} // end namespace Lanai
75
76
77// Subregister indices
78
79namespace Lanai {
80enum : uint16_t {
81 NoSubRegister,
82 sub_32, // 1
83 NUM_TARGET_SUBREGS
84};
85} // end namespace Lanai
86
87// Register pressure sets enum.
88namespace Lanai {
89enum RegisterPressureSets {
90 GPR_with_sub_32 = 0,
91 GPR = 1,
92};
93} // end namespace Lanai
94
95} // end namespace llvm
96
97#endif // GET_REGINFO_ENUM
98
99/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
100|* *|
101|* MC Register Information *|
102|* *|
103|* Automatically generated file, do not edit! *|
104|* *|
105\*===----------------------------------------------------------------------===*/
106
107
108#ifdef GET_REGINFO_MC_DESC
109#undef GET_REGINFO_MC_DESC
110
111namespace llvm {
112
113extern const int16_t LanaiRegDiffLists[] = {
114 /* 0 */ -22, 0,
115 /* 2 */ -19, 0,
116 /* 4 */ -11, 0,
117 /* 6 */ -7, 0,
118 /* 8 */ -6, 0,
119 /* 10 */ 6, 0,
120 /* 12 */ 7, 0,
121 /* 14 */ 11, 0,
122 /* 16 */ 19, 0,
123 /* 18 */ 22, 0,
124};
125
126extern const LaneBitmask LanaiLaneMaskLists[] = {
127 /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
128 /* 2 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
129};
130
131extern const uint16_t LanaiSubRegIdxLists[] = {
132 /* 0 */ 1, 0,
133};
134
135
136#ifdef __GNUC__
137#pragma GCC diagnostic push
138#pragma GCC diagnostic ignored "-Woverlength-strings"
139#endif
140extern const char LanaiRegStrings[] = {
141 /* 0 */ "R10\0"
142 /* 4 */ "R20\0"
143 /* 8 */ "R30\0"
144 /* 12 */ "R0\0"
145 /* 15 */ "R11\0"
146 /* 19 */ "R21\0"
147 /* 23 */ "R31\0"
148 /* 27 */ "RR1\0"
149 /* 31 */ "R12\0"
150 /* 35 */ "R22\0"
151 /* 39 */ "RR2\0"
152 /* 43 */ "R13\0"
153 /* 47 */ "R23\0"
154 /* 51 */ "R3\0"
155 /* 54 */ "R14\0"
156 /* 58 */ "R24\0"
157 /* 62 */ "R4\0"
158 /* 65 */ "R15\0"
159 /* 69 */ "R25\0"
160 /* 73 */ "R5\0"
161 /* 76 */ "R16\0"
162 /* 80 */ "R26\0"
163 /* 84 */ "R6\0"
164 /* 87 */ "R17\0"
165 /* 91 */ "R27\0"
166 /* 95 */ "R7\0"
167 /* 98 */ "R18\0"
168 /* 102 */ "R28\0"
169 /* 106 */ "R8\0"
170 /* 109 */ "R19\0"
171 /* 113 */ "R29\0"
172 /* 117 */ "R9\0"
173 /* 120 */ "RCA\0"
174 /* 124 */ "PC\0"
175 /* 127 */ "FP\0"
176 /* 130 */ "SP\0"
177 /* 133 */ "SR\0"
178 /* 136 */ "RV\0"
179};
180#ifdef __GNUC__
181#pragma GCC diagnostic pop
182#endif
183
184extern const MCRegisterDesc LanaiRegDesc[] = { // Descriptors
185 { 3, 0, 0, 0, 0, 0, 0 },
186 { 127, 14, 1, 0, 4096, 0, 0 },
187 { 124, 12, 1, 0, 4097, 0, 0 },
188 { 120, 16, 1, 0, 4098, 0, 0 },
189 { 136, 14, 1, 0, 4099, 0, 0 },
190 { 130, 10, 1, 0, 4100, 0, 0 },
191 { 133, 1, 1, 1, 4101, 2, 0 },
192 { 12, 1, 1, 1, 4102, 2, 0 },
193 { 28, 1, 1, 1, 4103, 2, 0 },
194 { 40, 1, 6, 1, 4097, 2, 0 },
195 { 51, 1, 1, 1, 4104, 2, 0 },
196 { 62, 1, 8, 1, 4100, 2, 0 },
197 { 73, 1, 4, 1, 4096, 2, 0 },
198 { 84, 1, 1, 1, 4105, 2, 0 },
199 { 95, 1, 1, 1, 4106, 2, 0 },
200 { 106, 1, 4, 1, 4099, 2, 0 },
201 { 117, 1, 1, 1, 4107, 2, 0 },
202 { 0, 1, 18, 1, 4108, 2, 0 },
203 { 15, 1, 18, 1, 4109, 2, 0 },
204 { 31, 1, 1, 1, 4110, 2, 0 },
205 { 43, 1, 1, 1, 4111, 2, 0 },
206 { 54, 1, 1, 1, 4112, 2, 0 },
207 { 65, 1, 2, 1, 4098, 2, 0 },
208 { 76, 1, 1, 1, 4113, 2, 0 },
209 { 87, 1, 1, 1, 4114, 2, 0 },
210 { 98, 1, 1, 1, 4115, 2, 0 },
211 { 109, 1, 1, 1, 4116, 2, 0 },
212 { 4, 1, 1, 1, 4117, 2, 0 },
213 { 19, 1, 1, 1, 4118, 2, 0 },
214 { 35, 1, 1, 1, 4119, 2, 0 },
215 { 47, 1, 1, 1, 4120, 2, 0 },
216 { 58, 1, 1, 1, 4121, 2, 0 },
217 { 69, 1, 1, 1, 4122, 2, 0 },
218 { 80, 1, 1, 1, 4123, 2, 0 },
219 { 91, 1, 1, 1, 4124, 2, 0 },
220 { 102, 1, 1, 1, 4125, 2, 0 },
221 { 113, 1, 1, 1, 4126, 2, 0 },
222 { 8, 1, 1, 1, 4127, 2, 0 },
223 { 23, 1, 1, 1, 4128, 2, 0 },
224 { 27, 0, 1, 0, 4108, 0, 0 },
225 { 39, 0, 1, 0, 4109, 0, 0 },
226};
227
228extern const MCPhysReg LanaiRegUnitRoots[][2] = {
229 { Lanai::R5 },
230 { Lanai::R2 },
231 { Lanai::R15 },
232 { Lanai::R8 },
233 { Lanai::R4 },
234 { Lanai::SR },
235 { Lanai::R0 },
236 { Lanai::R1 },
237 { Lanai::R3 },
238 { Lanai::R6 },
239 { Lanai::R7 },
240 { Lanai::R9 },
241 { Lanai::R10 },
242 { Lanai::R11 },
243 { Lanai::R12 },
244 { Lanai::R13 },
245 { Lanai::R14 },
246 { Lanai::R16 },
247 { Lanai::R17 },
248 { Lanai::R18 },
249 { Lanai::R19 },
250 { Lanai::R20 },
251 { Lanai::R21 },
252 { Lanai::R22 },
253 { Lanai::R23 },
254 { Lanai::R24 },
255 { Lanai::R25 },
256 { Lanai::R26 },
257 { Lanai::R27 },
258 { Lanai::R28 },
259 { Lanai::R29 },
260 { Lanai::R30 },
261 { Lanai::R31 },
262};
263
264namespace { // Register classes...
265 // GPR Register Class...
266 const MCPhysReg GPR[] = {
267 Lanai::R3, Lanai::R9, Lanai::R12, Lanai::R13, Lanai::R14, Lanai::R16, Lanai::R17, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23, Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29, Lanai::R30, Lanai::R31, Lanai::R6, Lanai::R7, Lanai::R18, Lanai::R19, Lanai::R15, Lanai::RCA, Lanai::R10, Lanai::RR1, Lanai::R11, Lanai::RR2, Lanai::R8, Lanai::RV, Lanai::R5, Lanai::FP, Lanai::R4, Lanai::SP, Lanai::R2, Lanai::PC, Lanai::R1, Lanai::R0,
268 };
269
270 // GPR Bit set.
271 const uint8_t GPRBits[] = {
272 0xbe, 0xff, 0xff, 0xff, 0xff, 0x01,
273 };
274
275 // GPR_with_sub_32 Register Class...
276 const MCPhysReg GPR_with_sub_32[] = {
277 Lanai::RCA, Lanai::RR1, Lanai::RR2, Lanai::RV, Lanai::FP, Lanai::SP, Lanai::PC,
278 };
279
280 // GPR_with_sub_32 Bit set.
281 const uint8_t GPR_with_sub_32Bits[] = {
282 0x3e, 0x00, 0x00, 0x00, 0x80, 0x01,
283 };
284
285 // CCR Register Class...
286 const MCPhysReg CCR[] = {
287 Lanai::SR,
288 };
289
290 // CCR Bit set.
291 const uint8_t CCRBits[] = {
292 0x40,
293 };
294
295} // end anonymous namespace
296
297
298#ifdef __GNUC__
299#pragma GCC diagnostic push
300#pragma GCC diagnostic ignored "-Woverlength-strings"
301#endif
302extern const char LanaiRegClassStrings[] = {
303 /* 0 */ "GPR_with_sub_32\0"
304 /* 16 */ "CCR\0"
305 /* 20 */ "GPR\0"
306};
307#ifdef __GNUC__
308#pragma GCC diagnostic pop
309#endif
310
311extern const MCRegisterClass LanaiMCRegisterClasses[] = {
312 { GPR, GPRBits, 20, 39, sizeof(GPRBits), Lanai::GPRRegClassID, 32, 1, true, false },
313 { GPR_with_sub_32, GPR_with_sub_32Bits, 0, 7, sizeof(GPR_with_sub_32Bits), Lanai::GPR_with_sub_32RegClassID, 32, 1, true, false },
314 { CCR, CCRBits, 16, 1, sizeof(CCRBits), Lanai::CCRRegClassID, 32, -1, false, false },
315};
316
317// Lanai Dwarf<->LLVM register mappings.
318extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0Dwarf2L[] = {
319 { 0U, Lanai::R0 },
320 { 1U, Lanai::R1 },
321 { 2U, Lanai::R2 },
322 { 3U, Lanai::R3 },
323 { 4U, Lanai::R4 },
324 { 5U, Lanai::R5 },
325 { 6U, Lanai::R6 },
326 { 7U, Lanai::R7 },
327 { 8U, Lanai::R8 },
328 { 9U, Lanai::R9 },
329 { 10U, Lanai::R10 },
330 { 11U, Lanai::R11 },
331 { 12U, Lanai::R12 },
332 { 13U, Lanai::R13 },
333 { 14U, Lanai::R14 },
334 { 15U, Lanai::R15 },
335 { 16U, Lanai::R16 },
336 { 17U, Lanai::R17 },
337 { 18U, Lanai::R18 },
338 { 19U, Lanai::R19 },
339 { 20U, Lanai::R20 },
340 { 21U, Lanai::R21 },
341 { 22U, Lanai::R22 },
342 { 23U, Lanai::R23 },
343 { 24U, Lanai::R24 },
344 { 25U, Lanai::R25 },
345 { 26U, Lanai::R26 },
346 { 27U, Lanai::R27 },
347 { 28U, Lanai::R28 },
348 { 29U, Lanai::R29 },
349 { 30U, Lanai::R30 },
350 { 31U, Lanai::R31 },
351};
352extern const unsigned LanaiDwarfFlavour0Dwarf2LSize = std::size(LanaiDwarfFlavour0Dwarf2L);
353
354extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0Dwarf2L[] = {
355 { 0U, Lanai::R0 },
356 { 1U, Lanai::R1 },
357 { 2U, Lanai::R2 },
358 { 3U, Lanai::R3 },
359 { 4U, Lanai::R4 },
360 { 5U, Lanai::R5 },
361 { 6U, Lanai::R6 },
362 { 7U, Lanai::R7 },
363 { 8U, Lanai::R8 },
364 { 9U, Lanai::R9 },
365 { 10U, Lanai::R10 },
366 { 11U, Lanai::R11 },
367 { 12U, Lanai::R12 },
368 { 13U, Lanai::R13 },
369 { 14U, Lanai::R14 },
370 { 15U, Lanai::R15 },
371 { 16U, Lanai::R16 },
372 { 17U, Lanai::R17 },
373 { 18U, Lanai::R18 },
374 { 19U, Lanai::R19 },
375 { 20U, Lanai::R20 },
376 { 21U, Lanai::R21 },
377 { 22U, Lanai::R22 },
378 { 23U, Lanai::R23 },
379 { 24U, Lanai::R24 },
380 { 25U, Lanai::R25 },
381 { 26U, Lanai::R26 },
382 { 27U, Lanai::R27 },
383 { 28U, Lanai::R28 },
384 { 29U, Lanai::R29 },
385 { 30U, Lanai::R30 },
386 { 31U, Lanai::R31 },
387};
388extern const unsigned LanaiEHFlavour0Dwarf2LSize = std::size(LanaiEHFlavour0Dwarf2L);
389
390extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0L2Dwarf[] = {
391 { Lanai::FP, 5U },
392 { Lanai::PC, 2U },
393 { Lanai::RCA, 15U },
394 { Lanai::RV, 8U },
395 { Lanai::SP, 4U },
396 { Lanai::R0, 0U },
397 { Lanai::R1, 1U },
398 { Lanai::R2, 2U },
399 { Lanai::R3, 3U },
400 { Lanai::R4, 4U },
401 { Lanai::R5, 5U },
402 { Lanai::R6, 6U },
403 { Lanai::R7, 7U },
404 { Lanai::R8, 8U },
405 { Lanai::R9, 9U },
406 { Lanai::R10, 10U },
407 { Lanai::R11, 11U },
408 { Lanai::R12, 12U },
409 { Lanai::R13, 13U },
410 { Lanai::R14, 14U },
411 { Lanai::R15, 15U },
412 { Lanai::R16, 16U },
413 { Lanai::R17, 17U },
414 { Lanai::R18, 18U },
415 { Lanai::R19, 19U },
416 { Lanai::R20, 20U },
417 { Lanai::R21, 21U },
418 { Lanai::R22, 22U },
419 { Lanai::R23, 23U },
420 { Lanai::R24, 24U },
421 { Lanai::R25, 25U },
422 { Lanai::R26, 26U },
423 { Lanai::R27, 27U },
424 { Lanai::R28, 28U },
425 { Lanai::R29, 29U },
426 { Lanai::R30, 30U },
427 { Lanai::R31, 31U },
428 { Lanai::RR1, 10U },
429 { Lanai::RR2, 11U },
430};
431extern const unsigned LanaiDwarfFlavour0L2DwarfSize = std::size(LanaiDwarfFlavour0L2Dwarf);
432
433extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0L2Dwarf[] = {
434 { Lanai::FP, 5U },
435 { Lanai::PC, 2U },
436 { Lanai::RCA, 15U },
437 { Lanai::RV, 8U },
438 { Lanai::SP, 4U },
439 { Lanai::R0, 0U },
440 { Lanai::R1, 1U },
441 { Lanai::R2, 2U },
442 { Lanai::R3, 3U },
443 { Lanai::R4, 4U },
444 { Lanai::R5, 5U },
445 { Lanai::R6, 6U },
446 { Lanai::R7, 7U },
447 { Lanai::R8, 8U },
448 { Lanai::R9, 9U },
449 { Lanai::R10, 10U },
450 { Lanai::R11, 11U },
451 { Lanai::R12, 12U },
452 { Lanai::R13, 13U },
453 { Lanai::R14, 14U },
454 { Lanai::R15, 15U },
455 { Lanai::R16, 16U },
456 { Lanai::R17, 17U },
457 { Lanai::R18, 18U },
458 { Lanai::R19, 19U },
459 { Lanai::R20, 20U },
460 { Lanai::R21, 21U },
461 { Lanai::R22, 22U },
462 { Lanai::R23, 23U },
463 { Lanai::R24, 24U },
464 { Lanai::R25, 25U },
465 { Lanai::R26, 26U },
466 { Lanai::R27, 27U },
467 { Lanai::R28, 28U },
468 { Lanai::R29, 29U },
469 { Lanai::R30, 30U },
470 { Lanai::R31, 31U },
471 { Lanai::RR1, 10U },
472 { Lanai::RR2, 11U },
473};
474extern const unsigned LanaiEHFlavour0L2DwarfSize = std::size(LanaiEHFlavour0L2Dwarf);
475
476extern const uint16_t LanaiRegEncodingTable[] = {
477 0,
478 0,
479 0,
480 0,
481 0,
482 0,
483 0,
484 0,
485 0,
486 0,
487 0,
488 0,
489 0,
490 0,
491 0,
492 0,
493 0,
494 0,
495 0,
496 0,
497 0,
498 0,
499 0,
500 0,
501 0,
502 0,
503 0,
504 0,
505 0,
506 0,
507 0,
508 0,
509 0,
510 0,
511 0,
512 0,
513 0,
514 0,
515 0,
516 0,
517 0,
518};
519static inline void InitLanaiMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
520 RI->InitMCRegisterInfo(LanaiRegDesc, 41, RA, PC, LanaiMCRegisterClasses, 3, LanaiRegUnitRoots, 33, LanaiRegDiffLists, LanaiLaneMaskLists, LanaiRegStrings, LanaiRegClassStrings, LanaiSubRegIdxLists, 2,
521LanaiRegEncodingTable);
522
523 switch (DwarfFlavour) {
524 default:
525 llvm_unreachable("Unknown DWARF flavour");
526 case 0:
527 RI->mapDwarfRegsToLLVMRegs(LanaiDwarfFlavour0Dwarf2L, LanaiDwarfFlavour0Dwarf2LSize, false);
528 break;
529 }
530 switch (EHFlavour) {
531 default:
532 llvm_unreachable("Unknown DWARF flavour");
533 case 0:
534 RI->mapDwarfRegsToLLVMRegs(LanaiEHFlavour0Dwarf2L, LanaiEHFlavour0Dwarf2LSize, true);
535 break;
536 }
537 switch (DwarfFlavour) {
538 default:
539 llvm_unreachable("Unknown DWARF flavour");
540 case 0:
541 RI->mapLLVMRegsToDwarfRegs(LanaiDwarfFlavour0L2Dwarf, LanaiDwarfFlavour0L2DwarfSize, false);
542 break;
543 }
544 switch (EHFlavour) {
545 default:
546 llvm_unreachable("Unknown DWARF flavour");
547 case 0:
548 RI->mapLLVMRegsToDwarfRegs(LanaiEHFlavour0L2Dwarf, LanaiEHFlavour0L2DwarfSize, true);
549 break;
550 }
551}
552
553} // end namespace llvm
554
555#endif // GET_REGINFO_MC_DESC
556
557/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
558|* *|
559|* Register Information Header Fragment *|
560|* *|
561|* Automatically generated file, do not edit! *|
562|* *|
563\*===----------------------------------------------------------------------===*/
564
565
566#ifdef GET_REGINFO_HEADER
567#undef GET_REGINFO_HEADER
568
569#include "llvm/CodeGen/TargetRegisterInfo.h"
570
571namespace llvm {
572
573class LanaiFrameLowering;
574
575struct LanaiGenRegisterInfo : public TargetRegisterInfo {
576 explicit LanaiGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
577 unsigned PC = 0, unsigned HwMode = 0);
578 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
579 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
580 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
581 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
582 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
583 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
584 unsigned getRegUnitWeight(unsigned RegUnit) const override;
585 unsigned getNumRegPressureSets() const override;
586 const char *getRegPressureSetName(unsigned Idx) const override;
587 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
588 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
589 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
590 ArrayRef<const char *> getRegMaskNames() const override;
591 ArrayRef<const uint32_t *> getRegMasks() const override;
592 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
593 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
594 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
595 bool isConstantPhysReg(MCRegister PhysReg) const override final;
596 /// Devirtualized TargetFrameLowering.
597 static const LanaiFrameLowering *getFrameLowering(
598 const MachineFunction &MF);
599};
600
601namespace Lanai { // Register classes
602 extern const TargetRegisterClass GPRRegClass;
603 extern const TargetRegisterClass GPR_with_sub_32RegClass;
604 extern const TargetRegisterClass CCRRegClass;
605} // end namespace Lanai
606
607} // end namespace llvm
608
609#endif // GET_REGINFO_HEADER
610
611/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
612|* *|
613|* Target Register and Register Classes Information *|
614|* *|
615|* Automatically generated file, do not edit! *|
616|* *|
617\*===----------------------------------------------------------------------===*/
618
619
620#ifdef GET_REGINFO_TARGET_DESC
621#undef GET_REGINFO_TARGET_DESC
622
623namespace llvm {
624
625extern const MCRegisterClass LanaiMCRegisterClasses[];
626
627static const MVT::SimpleValueType VTLists[] = {
628 /* 0 */ MVT::i32, MVT::Other,
629};
630
631static const char *SubRegIndexNameTable[] = { "sub_32", "" };
632
633static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
634 { 65535, 65535 },
635 { 0, 32 }, // sub_32
636};
637
638
639static const LaneBitmask SubRegIndexLaneMaskTable[] = {
640 LaneBitmask::getAll(),
641 LaneBitmask(0x0000000000000001), // sub_32
642 };
643
644
645
646static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
647 // Mode = 0 (Default)
648 { 32, 32, 32, /*VTLists+*/0 }, // GPR
649 { 32, 32, 32, /*VTLists+*/0 }, // GPR_with_sub_32
650 { 32, 32, 32, /*VTLists+*/0 }, // CCR
651};
652
653static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
654
655static const uint32_t GPRSubClassMask[] = {
656 0x00000003,
657 0x00000002, // sub_32
658};
659
660static const uint32_t GPR_with_sub_32SubClassMask[] = {
661 0x00000002,
662};
663
664static const uint32_t CCRSubClassMask[] = {
665 0x00000004,
666};
667
668static const uint16_t SuperRegIdxSeqs[] = {
669 /* 0 */ 1, 0,
670};
671
672static const TargetRegisterClass *const GPR_with_sub_32Superclasses[] = {
673 &Lanai::GPRRegClass,
674 nullptr
675};
676
677
678namespace Lanai { // Register class instances
679 extern const TargetRegisterClass GPRRegClass = {
680 &LanaiMCRegisterClasses[GPRRegClassID],
681 GPRSubClassMask,
682 SuperRegIdxSeqs + 0,
683 LaneBitmask(0x0000000000000001),
684 0,
685 false,
686 0x00, /* TSFlags */
687 false, /* HasDisjunctSubRegs */
688 false, /* CoveredBySubRegs */
689 NullRegClasses,
690 nullptr
691 };
692
693 extern const TargetRegisterClass GPR_with_sub_32RegClass = {
694 &LanaiMCRegisterClasses[GPR_with_sub_32RegClassID],
695 GPR_with_sub_32SubClassMask,
696 SuperRegIdxSeqs + 1,
697 LaneBitmask(0x0000000000000001),
698 0,
699 false,
700 0x00, /* TSFlags */
701 false, /* HasDisjunctSubRegs */
702 false, /* CoveredBySubRegs */
703 GPR_with_sub_32Superclasses,
704 nullptr
705 };
706
707 extern const TargetRegisterClass CCRRegClass = {
708 &LanaiMCRegisterClasses[CCRRegClassID],
709 CCRSubClassMask,
710 SuperRegIdxSeqs + 1,
711 LaneBitmask(0x0000000000000001),
712 0,
713 false,
714 0x00, /* TSFlags */
715 false, /* HasDisjunctSubRegs */
716 false, /* CoveredBySubRegs */
717 NullRegClasses,
718 nullptr
719 };
720
721} // end namespace Lanai
722
723namespace {
724 const TargetRegisterClass *const RegisterClasses[] = {
725 &Lanai::GPRRegClass,
726 &Lanai::GPR_with_sub_32RegClass,
727 &Lanai::CCRRegClass,
728 };
729} // end anonymous namespace
730
731static const uint8_t CostPerUseTable[] = {
7320, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
733
734
735static const bool InAllocatableClassTable[] = {
736false, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
737
738
739static const TargetRegisterInfoDesc LanaiRegInfoDesc = { // Extra Descriptors
740CostPerUseTable, 1, InAllocatableClassTable};
741
742unsigned LanaiGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
743 static const uint8_t Rows[1][1] = {
744 { 0, },
745 };
746
747 --IdxA; assert(IdxA < 1); (void) IdxA;
748 --IdxB; assert(IdxB < 1);
749 return Rows[0][IdxB];
750}
751
752 struct MaskRolOp {
753 LaneBitmask Mask;
754 uint8_t RotateLeft;
755 };
756 static const MaskRolOp LaneMaskComposeSequences[] = {
757 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 } // Sequence 0
758 };
759 static const uint8_t CompositeSequences[] = {
760 0 // to sub_32
761 };
762
763LaneBitmask LanaiGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
764 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
765 LaneBitmask Result;
766 for (const MaskRolOp *Ops =
767 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
768 Ops->Mask.any(); ++Ops) {
769 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
770 if (unsigned S = Ops->RotateLeft)
771 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
772 else
773 Result |= LaneBitmask(M);
774 }
775 return Result;
776}
777
778LaneBitmask LanaiGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
779 LaneMask &= getSubRegIndexLaneMask(IdxA);
780 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
781 LaneBitmask Result;
782 for (const MaskRolOp *Ops =
783 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
784 Ops->Mask.any(); ++Ops) {
785 LaneBitmask::Type M = LaneMask.getAsInteger();
786 if (unsigned S = Ops->RotateLeft)
787 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
788 else
789 Result |= LaneBitmask(M);
790 }
791 return Result;
792}
793
794const TargetRegisterClass *LanaiGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
795 static const uint8_t Table[3][1] = {
796 { // GPR
797 2, // sub_32 -> GPR_with_sub_32
798 },
799 { // GPR_with_sub_32
800 2, // sub_32 -> GPR_with_sub_32
801 },
802 { // CCR
803 0, // sub_32
804 },
805 };
806 assert(RC && "Missing regclass");
807 if (!Idx) return RC;
808 --Idx;
809 assert(Idx < 1 && "Bad subreg");
810 unsigned TV = Table[RC->getID()][Idx];
811 return TV ? getRegClass(TV - 1) : nullptr;
812}
813
814const TargetRegisterClass *LanaiGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
815 static const uint8_t Table[3][1] = {
816 { // GPR
817 1, // GPR:sub_32 -> GPR
818 },
819 { // GPR_with_sub_32
820 1, // GPR_with_sub_32:sub_32 -> GPR
821 },
822 { // CCR
823 0, // CCR:sub_32
824 },
825 };
826 assert(RC && "Missing regclass");
827 if (!Idx) return RC;
828 --Idx;
829 assert(Idx < 1 && "Bad subreg");
830 unsigned TV = Table[RC->getID()][Idx];
831 return TV ? getRegClass(TV - 1) : nullptr;
832}
833
834/// Get the weight in units of pressure for this register class.
835const RegClassWeight &LanaiGenRegisterInfo::
836getRegClassWeight(const TargetRegisterClass *RC) const {
837 static const RegClassWeight RCWeightTable[] = {
838 {1, 32}, // GPR
839 {1, 7}, // GPR_with_sub_32
840 {0, 0}, // CCR
841 };
842 return RCWeightTable[RC->getID()];
843}
844
845/// Get the weight in units of pressure for this register unit.
846unsigned LanaiGenRegisterInfo::
847getRegUnitWeight(unsigned RegUnit) const {
848 assert(RegUnit < 33 && "invalid register unit");
849 // All register units have unit weight.
850 return 1;
851}
852
853
854// Get the number of dimensions of register pressure.
855unsigned LanaiGenRegisterInfo::getNumRegPressureSets() const {
856 return 2;
857}
858
859// Get the name of this register unit pressure set.
860const char *LanaiGenRegisterInfo::
861getRegPressureSetName(unsigned Idx) const {
862 static const char *PressureNameTable[] = {
863 "GPR_with_sub_32",
864 "GPR",
865 };
866 return PressureNameTable[Idx];
867}
868
869// Get the register unit pressure limit for this dimension.
870// This limit must be adjusted dynamically for reserved registers.
871unsigned LanaiGenRegisterInfo::
872getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
873 static const uint8_t PressureLimitTable[] = {
874 7, // 0: GPR_with_sub_32
875 32, // 1: GPR
876 };
877 return PressureLimitTable[Idx];
878}
879
880/// Table of pressure sets per register class or unit.
881static const int RCSetsTable[] = {
882 /* 0 */ 0, 1, -1,
883};
884
885/// Get the dimensions of register pressure impacted by this register class.
886/// Returns a -1 terminated array of pressure set IDs
887const int *LanaiGenRegisterInfo::
888getRegClassPressureSets(const TargetRegisterClass *RC) const {
889 static const uint8_t RCSetStartTable[] = {
890 1,0,2,};
891 return &RCSetsTable[RCSetStartTable[RC->getID()]];
892}
893
894/// Get the dimensions of register pressure impacted by this register unit.
895/// Returns a -1 terminated array of pressure set IDs
896const int *LanaiGenRegisterInfo::
897getRegUnitPressureSets(unsigned RegUnit) const {
898 assert(RegUnit < 33 && "invalid register unit");
899 static const uint8_t RUSetStartTable[] = {
900 0,0,0,0,0,2,1,1,1,1,1,1,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
901 return &RCSetsTable[RUSetStartTable[RegUnit]];
902}
903
904extern const MCRegisterDesc LanaiRegDesc[];
905extern const int16_t LanaiRegDiffLists[];
906extern const LaneBitmask LanaiLaneMaskLists[];
907extern const char LanaiRegStrings[];
908extern const char LanaiRegClassStrings[];
909extern const MCPhysReg LanaiRegUnitRoots[][2];
910extern const uint16_t LanaiSubRegIdxLists[];
911extern const uint16_t LanaiRegEncodingTable[];
912// Lanai Dwarf<->LLVM register mappings.
913extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0Dwarf2L[];
914extern const unsigned LanaiDwarfFlavour0Dwarf2LSize;
915
916extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0Dwarf2L[];
917extern const unsigned LanaiEHFlavour0Dwarf2LSize;
918
919extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0L2Dwarf[];
920extern const unsigned LanaiDwarfFlavour0L2DwarfSize;
921
922extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0L2Dwarf[];
923extern const unsigned LanaiEHFlavour0L2DwarfSize;
924
925LanaiGenRegisterInfo::
926LanaiGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
927 unsigned PC, unsigned HwMode)
928 : TargetRegisterInfo(&LanaiRegInfoDesc, RegisterClasses, RegisterClasses+3,
929 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
930 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
931 InitMCRegisterInfo(LanaiRegDesc, 41, RA, PC,
932 LanaiMCRegisterClasses, 3,
933 LanaiRegUnitRoots,
934 33,
935 LanaiRegDiffLists,
936 LanaiLaneMaskLists,
937 LanaiRegStrings,
938 LanaiRegClassStrings,
939 LanaiSubRegIdxLists,
940 2,
941 LanaiRegEncodingTable);
942
943 switch (DwarfFlavour) {
944 default:
945 llvm_unreachable("Unknown DWARF flavour");
946 case 0:
947 mapDwarfRegsToLLVMRegs(LanaiDwarfFlavour0Dwarf2L, LanaiDwarfFlavour0Dwarf2LSize, false);
948 break;
949 }
950 switch (EHFlavour) {
951 default:
952 llvm_unreachable("Unknown DWARF flavour");
953 case 0:
954 mapDwarfRegsToLLVMRegs(LanaiEHFlavour0Dwarf2L, LanaiEHFlavour0Dwarf2LSize, true);
955 break;
956 }
957 switch (DwarfFlavour) {
958 default:
959 llvm_unreachable("Unknown DWARF flavour");
960 case 0:
961 mapLLVMRegsToDwarfRegs(LanaiDwarfFlavour0L2Dwarf, LanaiDwarfFlavour0L2DwarfSize, false);
962 break;
963 }
964 switch (EHFlavour) {
965 default:
966 llvm_unreachable("Unknown DWARF flavour");
967 case 0:
968 mapLLVMRegsToDwarfRegs(LanaiEHFlavour0L2Dwarf, LanaiEHFlavour0L2DwarfSize, true);
969 break;
970 }
971}
972
973static const MCPhysReg CSR_SaveList[] = { 0 };
974static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, };
975
976
977ArrayRef<const uint32_t *> LanaiGenRegisterInfo::getRegMasks() const {
978 static const uint32_t *const Masks[] = {
979 CSR_RegMask,
980 };
981 return ArrayRef(Masks);
982}
983
984bool LanaiGenRegisterInfo::
985isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
986 return
987 false;
988}
989
990bool LanaiGenRegisterInfo::
991isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
992 return
993 false;
994}
995
996bool LanaiGenRegisterInfo::
997isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
998 return
999 false;
1000}
1001
1002bool LanaiGenRegisterInfo::
1003isConstantPhysReg(MCRegister PhysReg) const {
1004 return
1005 false;
1006}
1007
1008ArrayRef<const char *> LanaiGenRegisterInfo::getRegMaskNames() const {
1009 static const char *Names[] = {
1010 "CSR",
1011 };
1012 return ArrayRef(Names);
1013}
1014
1015const LanaiFrameLowering *
1016LanaiGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
1017 return static_cast<const LanaiFrameLowering *>(
1018 MF.getSubtarget().getFrameLowering());
1019}
1020
1021} // end namespace llvm
1022
1023#endif // GET_REGINFO_TARGET_DESC
1024
1025