1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14} // end namespace llvm
15
16#endif // GET_SUBTARGETINFO_ENUM
17
18
19#ifdef GET_SUBTARGETINFO_MACRO
20#undef GET_SUBTARGETINFO_MACRO
21#endif // GET_SUBTARGETINFO_MACRO
22
23
24#ifdef GET_SUBTARGETINFO_MC_DESC
25#undef GET_SUBTARGETINFO_MC_DESC
26
27namespace llvm {
28
29#ifdef DBGFIELD
30#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
31#endif
32#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
33#define DBGFIELD(x) x,
34#else
35#define DBGFIELD(x)
36#endif
37
38// Functional units for "LanaiItinerary"
39namespace LanaiItineraryFU {
40 const InstrStage::FuncUnits ALU_FU = 1ULL << 0;
41 const InstrStage::FuncUnits LDST_FU = 1ULL << 1;
42} // end namespace LanaiItineraryFU
43
44extern const llvm::InstrStage LanaiStages[] = {
45 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
46 { 1, LanaiItineraryFU::ALU_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
47 { 1, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
48 { 2, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
49 { 0, 0, 0, llvm::InstrStage::Required } // End stages
50};
51extern const unsigned LanaiOperandCycles[] = {
52 0, // No itinerary
53 0 // End operand cycles
54};
55extern const unsigned LanaiForwardingPaths[] = {
56 0, // No itinerary
57 0 // End bypass tables
58};
59
60static const llvm::InstrItinerary LanaiItinerary[] = {
61 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
62 { 1, 1, 2, 0, 0 }, // 1 IIC_ALU_WriteALU
63 { 1, 1, 2, 0, 0 }, // 2 IIC_ALU
64 { 1, 2, 3, 0, 0 }, // 3 IIC_LD_WriteLD
65 { 1, 3, 4, 0, 0 }, // 4 IIC_LDSW_WriteLDSW
66 { 0, 0, 0, 0, 0 }, // 5 WriteLD
67 { 1, 2, 3, 0, 0 }, // 6 IIC_ST_WriteST
68 { 1, 3, 4, 0, 0 }, // 7 IIC_STSW_WriteSTSW
69 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
70};
71
72// ===============================================================
73// Data tables for the new per-operand machine model.
74
75// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
76extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[] = {
77 { 0, 0, 0 }, // Invalid
78 { 1, 1, 0}, // #1
79 { 2, 1, 0} // #2
80}; // LanaiWriteProcResTable
81
82// {Cycles, WriteResourceID}
83extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[] = {
84 { 0, 0}, // Invalid
85 { 1, 0}, // #1 WriteALU
86 { 2, 0}, // #2 WriteLD_WriteLDSW_WriteST
87 { 4, 0} // #3 WriteSTSW
88}; // LanaiWriteLatencyTable
89
90// {UseIdx, WriteResourceID, Cycles}
91extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[] = {
92 {0, 0, 0}, // Invalid
93}; // LanaiReadAdvanceTable
94
95// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
96static const llvm::MCSchedClassDesc LanaiSchedModelSchedClasses[] = {
97 {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0},
98 {DBGFIELD("IIC_ALU_WriteALU") 1, false, false, false, 1, 1, 1, 1, 0, 0}, // #1
99 {DBGFIELD("IIC_ALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #2
100 {DBGFIELD("IIC_LD_WriteLD") 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #3
101 {DBGFIELD("IIC_LDSW_WriteLDSW") 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #4
102 {DBGFIELD("WriteLD") 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #5
103 {DBGFIELD("IIC_ST_WriteST") 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #6
104 {DBGFIELD("IIC_STSW_WriteSTSW") 1, false, false, false, 2, 1, 3, 1, 0, 0}, // #7
105}; // LanaiSchedModelSchedClasses
106
107#undef DBGFIELD
108
109static const llvm::MCSchedModel NoSchedModel = {
110 MCSchedModel::DefaultIssueWidth,
111 MCSchedModel::DefaultMicroOpBufferSize,
112 MCSchedModel::DefaultLoopMicroOpBufferSize,
113 MCSchedModel::DefaultLoadLatency,
114 MCSchedModel::DefaultHighLatency,
115 MCSchedModel::DefaultMispredictPenalty,
116 false, // PostRAScheduler
117 false, // CompleteModel
118 false, // EnableIntervals
119 0, // Processor ID
120 nullptr, nullptr, 0, 0, // No instruction-level machine model.
121 nullptr, // No Itinerary
122 nullptr // No extra processor descriptor
123};
124
125static const unsigned LanaiSchedModelProcResourceSubUnits[] = {
126 0, // Invalid
127};
128
129// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
130static const llvm::MCProcResourceDesc LanaiSchedModelProcResources[] = {
131 {"InvalidUnit", 0, 0, 0, 0},
132 {"ALU", 1, 0, 0, nullptr}, // #1
133 {"LdSt", 1, 0, 0, nullptr}, // #2
134};
135
136static const llvm::MCSchedModel LanaiSchedModel = {
137 1, // IssueWidth
138 0, // MicroOpBufferSize
139 0, // LoopMicroOpBufferSize
140 2, // LoadLatency
141 MCSchedModel::DefaultHighLatency,
142 10, // MispredictPenalty
143 false, // PostRAScheduler
144 false, // CompleteModel
145 false, // EnableIntervals
146 1, // Processor ID
147 LanaiSchedModelProcResources,
148 LanaiSchedModelSchedClasses,
149 3,
150 8,
151 LanaiItinerary,
152 nullptr // No extra processor descriptor
153};
154
155// Sorted (by key) array of values for CPU subtype.
156extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[] = {
157 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
158 { "v11", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
159};
160
161namespace Lanai_MC {
162unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
163 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
164 // Don't know how to resolve this scheduling class.
165 return 0;
166}
167} // end namespace Lanai_MC
168
169struct LanaiGenMCSubtargetInfo : public MCSubtargetInfo {
170 LanaiGenMCSubtargetInfo(const Triple &TT,
171 StringRef CPU, StringRef TuneCPU, StringRef FS,
172 ArrayRef<SubtargetFeatureKV> PF,
173 ArrayRef<SubtargetSubTypeKV> PD,
174 const MCWriteProcResEntry *WPR,
175 const MCWriteLatencyEntry *WL,
176 const MCReadAdvanceEntry *RA, const InstrStage *IS,
177 const unsigned *OC, const unsigned *FP) :
178 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
179 WPR, WL, RA, IS, OC, FP) { }
180
181 unsigned resolveVariantSchedClass(unsigned SchedClass,
182 const MCInst *MI, const MCInstrInfo *MCII,
183 unsigned CPUID) const override {
184 return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
185 }
186};
187
188static inline MCSubtargetInfo *createLanaiMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
189 return new LanaiGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, std::nullopt, LanaiSubTypeKV,
190 LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
191 LanaiStages, LanaiOperandCycles, LanaiForwardingPaths);
192}
193
194} // end namespace llvm
195
196#endif // GET_SUBTARGETINFO_MC_DESC
197
198
199#ifdef GET_SUBTARGETINFO_TARGET_DESC
200#undef GET_SUBTARGETINFO_TARGET_DESC
201
202#include "llvm/Support/Debug.h"
203#include "llvm/Support/raw_ostream.h"
204
205// ParseSubtargetFeatures - Parses features string setting specified
206// subtarget options.
207void llvm::LanaiSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
208 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
209 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
210 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
211}
212#endif // GET_SUBTARGETINFO_TARGET_DESC
213
214
215#ifdef GET_SUBTARGETINFO_HEADER
216#undef GET_SUBTARGETINFO_HEADER
217
218namespace llvm {
219class DFAPacketizer;
220namespace Lanai_MC {
221unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
222} // end namespace Lanai_MC
223
224struct LanaiGenSubtargetInfo : public TargetSubtargetInfo {
225 explicit LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
226public:
227 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
228 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
229 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
230};
231} // end namespace llvm
232
233#endif // GET_SUBTARGETINFO_HEADER
234
235
236#ifdef GET_SUBTARGETINFO_CTOR
237#undef GET_SUBTARGETINFO_CTOR
238
239#include "llvm/CodeGen/TargetSchedule.h"
240
241namespace llvm {
242extern const llvm::SubtargetFeatureKV LanaiFeatureKV[];
243extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[];
244extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[];
245extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[];
246extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[];
247extern const llvm::InstrStage LanaiStages[];
248extern const unsigned LanaiOperandCycles[];
249extern const unsigned LanaiForwardingPaths[];
250LanaiGenSubtargetInfo::LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
251 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, std::nullopt, ArrayRef(LanaiSubTypeKV, 2),
252 LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
253 LanaiStages, LanaiOperandCycles, LanaiForwardingPaths) {}
254
255unsigned LanaiGenSubtargetInfo
256::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
257 report_fatal_error("Expected a variant SchedClass");
258} // LanaiGenSubtargetInfo::resolveSchedClass
259
260unsigned LanaiGenSubtargetInfo
261::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
262 return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
263} // LanaiGenSubtargetInfo::resolveVariantSchedClass
264
265} // end namespace llvm
266
267#endif // GET_SUBTARGETINFO_CTOR
268
269
270#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
271#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
272
273#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
274
275
276#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
277#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
278
279#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
280
281